diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index ca274f9b597..95211bb5116 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -1,22 +1,23 @@ Notes: -* Pull requests will not be accepted until the submitter has agreed to the [contributer agreement](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md). -* This is just a template, so feel free to use/remove the unnecessary things +- Pull requests will not be accepted until the submitter has agreed to the [contributer agreement](https://github.com/ARMmbed/mbed-os/blob/master/CONTRIBUTING.md). +- This is just a template, so feel free to use/remove the unnecessary things ## Description -A few sentences describing the overall goals of the pull request's commits. +A few sentences describing the overall goals of the pull request's commits. ## Status -**READY/IN DEVELOPMENT/HOLD** +**READY/IN DEVELOPMENT/HOLD** ## Migrations + If this PR changes any APIs or behaviors, give a short description of what *API users* should do when this PR is merged. YES | NO - ## Related PRs + List related PRs against other branches: branch | PR @@ -24,16 +25,15 @@ branch | PR other_pr_production | [link]() other_pr_master | [link]() - ## Todos + - [ ] Tests - [ ] Documentation - ## Deploy notes -Notes regarding the deployment of this PR. These should note any -required changes in the build environment, tools, compilers, etc. +Notes regarding the deployment of this PR. These should note any required changes in the build environment, tools, compilers and so on. ## Steps to test or reproduce + Outline the steps to test or reproduce the PR here. diff --git a/TESTS/events/queue/main.cpp b/TESTS/events/queue/main.cpp index f779ee0c24d..738fdd0d8dc 100644 --- a/TESTS/events/queue/main.cpp +++ b/TESTS/events/queue/main.cpp @@ -22,7 +22,10 @@ using namespace utest::v1; -#define TEST_EQUEUE_SIZE 1024 +// TEST_EQUEUE_SIZE was reduced below 1024B to fit this test to devices with small RAM (RAM <= 16kB) +// additionally TEST_EQUEUE_SIZE was expressed in EVENTS_EVENT_SIZE to increase readability +// (for more details about EVENTS_EVENT_SIZE see EventQueue constructor) +#define TEST_EQUEUE_SIZE (18*EVENTS_EVENT_SIZE) // flag for called volatile bool touched = false; diff --git a/TESTS/mbed_drivers/echo/main.cpp b/TESTS/mbed_drivers/echo/main.cpp index 8e849c9dd04..6388299c401 100644 --- a/TESTS/mbed_drivers/echo/main.cpp +++ b/TESTS/mbed_drivers/echo/main.cpp @@ -26,13 +26,18 @@ using namespace utest::v1; // Echo server (echo payload to host) template void test_case_echo_server_x() { - char _key[10] = {}; + char _key[11] = {}; char _value[128] = {}; const int echo_count = N; + const char _key_const[] = "echo_count"; + int expected_key = 1; + greentea_send_kv(_key_const, echo_count); // Handshake with host - greentea_send_kv("echo_count", echo_count); - greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + do { + greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + expected_key = strcmp(_key_const, _key); + } while (expected_key); TEST_ASSERT_EQUAL_INT(echo_count, atoi(_value)); for (int i=0; i < echo_count; ++i) { @@ -48,12 +53,10 @@ utest::v1::status_t greentea_failure_handler(const Case *const source, const fai Case cases[] = { Case("Echo server: x16", test_case_echo_server_x<16>, greentea_failure_handler), - Case("Echo server: x32", test_case_echo_server_x<32>, greentea_failure_handler), - Case("Echo server: x64", test_case_echo_server_x<64>, greentea_failure_handler), }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(180, "echo"); + GREENTEA_SETUP(30, "echo"); return greentea_test_setup_handler(number_of_cases); } diff --git a/TESTS/mbed_drivers/lp_ticker/main.cpp b/TESTS/mbed_drivers/lp_ticker/main.cpp new file mode 100644 index 00000000000..aeb36765f1a --- /dev/null +++ b/TESTS/mbed_drivers/lp_ticker/main.cpp @@ -0,0 +1,221 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "utest/utest.h" +#include "unity/unity.h" + + +#if !DEVICE_LOWPOWERTIMER + #error [NOT_SUPPORTED] Low power ticker not supported for this target +#endif + +using utest::v1::Case; + +static const int test_timeout = 10; + +#define TICKER_COUNT 16 +#define MULTI_TICKER_TIME_MS 100 + +/* Due to poor accuracy of LowPowerTicker on many platforms + there is no sense to tune tolerance value as it was in Ticker tests. + + Tolerance value is set to 2000us to cover this diversity */ +#define TOLERANCE_US 2000 + + +volatile uint32_t ticker_callback_flag; +volatile uint32_t multi_counter; +Timer gtimer; + + + +void sem_release(Semaphore *sem) +{ + sem->release(); +} + + +void stop_gtimer_set_flag(void) +{ + gtimer.stop(); + core_util_atomic_incr_u32((uint32_t*)&ticker_callback_flag, 1); +} + +void increment_multi_counter(void) +{ + core_util_atomic_incr_u32((uint32_t*)&multi_counter, 1);; +} + +/** Test many tickers run one after the other + + Given many Tickers + When schedule them one after the other with the same time intervals + Then tickers properly execute callbacks + When schedule them one after the other with the different time intervals + Then tickers properly execute callbacks + */ +void test_multi_ticker(void) +{ + LowPowerTicker ticker[TICKER_COUNT]; + const uint32_t extra_wait = 10; // extra 10ms wait time + + multi_counter = 0; + for (int i = 0; i < TICKER_COUNT; i++) { + ticker[i].attach_us(callback(increment_multi_counter), MULTI_TICKER_TIME_MS * 1000); + } + + Thread::wait(MULTI_TICKER_TIME_MS + extra_wait); + for (int i = 0; i < TICKER_COUNT; i++) { + ticker[i].detach(); + } + TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter); + + multi_counter = 0; + for (int i = 0; i < TICKER_COUNT; i++) { + ticker[i].attach_us(callback(increment_multi_counter), (MULTI_TICKER_TIME_MS + i) * 1000); + } + + Thread::wait(MULTI_TICKER_TIME_MS + TICKER_COUNT + extra_wait); + for (int i = 0; i < TICKER_COUNT; i++) { + ticker[i].detach(); + } + TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter); +} + +/** Test multi callback time + + Given a Ticker + When the callback is attached multiple times + Then ticker properly execute callback multiple times + */ +void test_multi_call_time(void) +{ + LowPowerTicker ticker; + int time_diff; + const int attach_count = 10; + + for (int i = 0; i < attach_count; i++) { + ticker_callback_flag = 0; + gtimer.reset(); + + gtimer.start(); + ticker.attach_us(callback(stop_gtimer_set_flag), MULTI_TICKER_TIME_MS * 1000); + while(!ticker_callback_flag); + time_diff = gtimer.read_us(); + + TEST_ASSERT_UINT32_WITHIN(TOLERANCE_US, MULTI_TICKER_TIME_MS * 1000, time_diff); + } +} + +/** Test if detach cancel scheduled callback event + + Given a Ticker with callback attached + When the callback is detached + Then the callback is not being called + */ +void test_detach(void) +{ + LowPowerTicker ticker; + int32_t ret; + const float ticker_time_s = 0.1f; + const uint32_t wait_time_ms = 500; + Semaphore sem(0, 1); + + ticker.attach(callback(sem_release, &sem), ticker_time_s); + + ret = sem.wait(); + TEST_ASSERT_TRUE(ret > 0); + + ret = sem.wait(); + ticker.detach(); /* cancel */ + TEST_ASSERT_TRUE(ret > 0); + + ret = sem.wait(wait_time_ms); + TEST_ASSERT_EQUAL(0, ret); +} + +/** Test single callback time via attach + + Given a Ticker + When callback attached with time interval specified + Then ticker properly executes callback within a specified time interval + */ +template +void test_attach_time(void) +{ + LowPowerTicker ticker; + ticker_callback_flag = 0; + + gtimer.reset(); + gtimer.start(); + ticker.attach(callback(stop_gtimer_set_flag), ((float)DELAY_US) / 1000000.0f); + while(!ticker_callback_flag); + ticker.detach(); + const int time_diff = gtimer.read_us(); + + TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff); +} + +/** Test single callback time via attach_us + + Given a Ticker + When callback attached with time interval specified + Then ticker properly executes callback within a specified time interval + */ +template +void test_attach_us_time(void) +{ + LowPowerTicker ticker; + ticker_callback_flag = 0; + + gtimer.reset(); + gtimer.start(); + ticker.attach_us(callback(stop_gtimer_set_flag), DELAY_US); + while(!ticker_callback_flag); + ticker.detach(); + const int time_diff = gtimer.read_us(); + + TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff); +} + +// Test cases +Case cases[] = { + Case("Test attach for 0.001s and time measure", test_attach_time<1000>), + Case("Test attach_us for 1ms and time measure", test_attach_us_time<1000>), + Case("Test attach for 0.01s and time measure", test_attach_time<10000>), + Case("Test attach_us for 10ms and time measure", test_attach_us_time<10000>), + Case("Test attach for 0.1s and time measure", test_attach_time<100000>), + Case("Test attach_us for 100ms and time measure", test_attach_us_time<100000>), + Case("Test attach for 0.5s and time measure", test_attach_time<500000>), + Case("Test attach_us for 500ms and time measure", test_attach_us_time<500000>), + Case("Test detach", test_detach), + Case("Test multi call and time measure", test_multi_call_time), + Case("Test multi ticker", test_multi_ticker), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(test_timeout, "timing_drift_auto"); + return utest::v1::greentea_test_setup_handler(number_of_cases); +} + +utest::v1::Specification specification(greentea_test_setup, cases, utest::v1::greentea_test_teardown_handler); + +int main() +{ + utest::v1::Harness::run(specification); +} diff --git a/TESTS/mbed_drivers/lp_timeout/main.cpp b/TESTS/mbed_drivers/lp_timeout/main.cpp index df56388dc5b..9a16d6bdfbd 100644 --- a/TESTS/mbed_drivers/lp_timeout/main.cpp +++ b/TESTS/mbed_drivers/lp_timeout/main.cpp @@ -59,7 +59,10 @@ void lp_timeout_1s_deepsleep(void) */ timer.start(); lpt.attach(&cb_done, 1); - deepsleep(); + /* Make sure deepsleep is allowed, to go to deepsleep */ + bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); + TEST_ASSERT_TRUE_MESSAGE(deep_sleep_allowed, "Deep sleep should be allowed"); + sleep(); while (!complete); /* It takes longer to wake up from deep sleep */ @@ -75,6 +78,8 @@ void lp_timeout_1s_sleep(void) sleep_manager_lock_deep_sleep(); lpt.attach(&cb_done, 1); + bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); + TEST_ASSERT_FALSE_MESSAGE(deep_sleep_allowed, "Deep sleep should be disallowed"); sleep(); while (!complete); sleep_manager_unlock_deep_sleep(); diff --git a/TESTS/mbed_drivers/lp_timer/main.cpp b/TESTS/mbed_drivers/lp_timer/main.cpp new file mode 100644 index 00000000000..bf3f09639e8 --- /dev/null +++ b/TESTS/mbed_drivers/lp_timer/main.cpp @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "rtos.h" +#include "hal/us_ticker_api.h" + +#if !DEVICE_LOWPOWERTIMER +#error [NOT_SUPPORTED] test not supported +#endif + +using namespace utest::v1; + +extern uint32_t SystemCoreClock; + +/* This test is created based on the test for Timer class. + * Since low power timer is less accurate than regular + * timer we need to adjust delta. + */ + +/* Macro to define delta based on CPU clock frequency. + * + * Note that some extra time is counted by the timer. + * Additional time is caused by the function calls and + * additional operations performed by wait and + * stop functions before in fact timer is stopped. This may + * add additional time to the counted result. + * + * To take in to account this extra time we introduce DELTA + * value based on CPU clock (speed): + * DELTA = TOLERANCE_FACTOR / SystemCoreClock * US_FACTOR + * + * e.g. + * For K64F DELTA = (80000 / 120000000) * 1000000 = 666[us] + * For NUCLEO_F070RB DELTA = (80000 / 48000000) * 1000000 = 1666[us] + * For NRF51_DK DELTA = (80000 / 16000000) * 1000000 = 5000[us] + */ +#define US_PER_SEC 1000000 +#define US_PER_MSEC 1000 +#define TOLERANCE_FACTOR 80000.0f +#define US_FACTOR 1000000.0f + +static const int delta_sys_clk_us = ((int) (TOLERANCE_FACTOR / (float) SystemCoreClock * US_FACTOR)); + +/* When test performs time measurement using Timer in sequence, then measurement error accumulates + * in the successive attempts. */ + #define DELTA_US(i) (delta_sys_clk_us * i) + #define DELTA_S(i) ((float)delta_sys_clk_us * i / US_PER_SEC) + #define DELTA_MS(i) (1 + ( (i * delta_sys_clk_us) / US_PER_MSEC)) + +/* This test verifies if low power timer is stopped after + * creation. + * + * Given Timer has been successfully created. + * When read of timer elapsed time is requested. + * Then result is always 0. + */ +void test_lptimer_creation() +{ + LowPowerTimer lp_timer; + + /* Check results. */ + TEST_ASSERT_EQUAL_FLOAT(0, lp_timer.read()); + TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_ms()); + TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_us()); + TEST_ASSERT_EQUAL_UINT64(0, lp_timer.read_high_resolution_us()); + + /* Wait 10 ms. + * After that operation timer read routines should still return 0. */ + wait_ms(10); + + /* Check results. */ + TEST_ASSERT_EQUAL_FLOAT(0, lp_timer.read()); + TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_ms()); + TEST_ASSERT_EQUAL_INT32(0, lp_timer.read_us()); + TEST_ASSERT_EQUAL_UINT64(0, lp_timer.read_high_resolution_us()); +} + +/* This test verifies if read(), read_us(), read_ms(), + * read_high_resolution_us() + * functions return time accumulated between + * low power timer starts and stops. + * + * Given Timer has been successfully created and + * few times started and stopped after a specified period of time. + * When timer read request is performed. + * Then read functions return accumulated time elapsed between starts + * and stops. + */ +void test_lptimer_time_accumulation() +{ + LowPowerTimer lp_timer; + + /* Start the timer. */ + lp_timer.start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - totally 10 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, lp_timer.read_high_resolution_us()); + + /* Wait 50 ms - this is done to show that time elapsed when + * the timer is stopped does not have influence on the + * timer counted time. */ + wait_ms(50); + + /* ------ */ + + /* Start the timer. */ + lp_timer.start(); + + /* Wait 20 ms. */ + wait_ms(20); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - totally 30 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, lp_timer.read_high_resolution_us()); + + /* Wait 50 ms - this is done to show that time elapsed when + * the timer is stopped does not have influence on the + * timer counted time. */ + + /* ------ */ + + /* Start the timer. */ + lp_timer.start(); + + /* Wait 30 ms. */ + wait_ms(30); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - totally 60 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(3), 0.060f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(3), 60, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(3), 60000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(3), 60000, lp_timer.read_high_resolution_us()); + + /* Wait 50 ms - this is done to show that time elapsed when + * the timer is stopped does not have influence on the + * timer time. */ + wait_ms(50); + + /* ------ */ + + /* Start the timer. */ + lp_timer.start(); + + /* Wait 1 sec. */ + wait_ms(1000); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - totally 1060 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(4), 1.060f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(4), 1060, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(4), 1060000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(4), 1060000, lp_timer.read_high_resolution_us()); +} + +/* This test verifies if reset() function resets the + * low power timer counted time. + * + * Given timer has been started and stopped once, then reset + * operation was performed. + * When timer is started and stopped next time. + * Then timer read functions returns only the the second + * measured time. + */ +void test_lptimer_reset() +{ + LowPowerTimer lp_timer; + + /* First measure 10 ms delay. */ + lp_timer.start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - totally 10 ms elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, lp_timer.read_high_resolution_us()); + + /* Reset the timer - previous measured time should be lost now. */ + lp_timer.reset(); + + /* Now measure 20 ms delay. */ + lp_timer.start(); + + /* Wait 20 ms. */ + wait_ms(20); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - 20 ms elapsed since the reset. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.020f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 20, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 20000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 20000, lp_timer.read_high_resolution_us()); +} + +/* This test verifies if calling start() for already + * started low power timer does nothing. + * + * Given timer is already started. + * When timer is started again. + * Then second start operation is ignored. + */ +void test_lptimer_start_started_timer() +{ + LowPowerTimer lp_timer; + + /* Start the timer. */ + lp_timer.start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Now start timer again. */ + lp_timer.start(); + + /* Wait 20 ms. */ + wait_ms(20); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - 30 ms have elapsed since the first start. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, lp_timer.read_high_resolution_us()); +} + +/* This test verifies low power timer float operator. + * + * Given timer is created and a time period time is counted. + * When timer object is casted on float type. + * Then counted type in seconds is returned by means of + * read() function. + */ +void test_lptimer_float_operator() +{ + LowPowerTimer lp_timer; + + /* Start the timer. */ + lp_timer.start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check result - 10 ms elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, (float )(lp_timer)); +} + +/* This test verifies if time counted by the low power timer is + * valid. + * + * Given timer is created. + * When timer is used to measure 1ms/10ms/100ms/1s + * delays. + * Then the results are valid (within acceptable range). + */ +template +void test_lptimer_time_measurement() +{ + LowPowerTimer lp_timer; + + /* Start the timer. */ + lp_timer.start(); + + /* Wait us. */ + wait_us(wait_val_us); + + /* Stop the timer. */ + lp_timer.stop(); + + /* Check results - wait_val_us us have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), (float )wait_val_us / 1000000, lp_timer.read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), wait_val_us / 1000, lp_timer.read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), wait_val_us, lp_timer.read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), wait_val_us, lp_timer.read_high_resolution_us()); +} + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(15, "default_auto"); + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Test: LowPowerTimer - stopped after creation.", test_lptimer_creation), + Case("Test: LowPowerTimer - measure time accumulation.", test_lptimer_time_accumulation), + Case("Test: LowPowerTimer - reset.", test_lptimer_reset), + Case("Test: LowPowerTimer - start started timer.", test_lptimer_start_started_timer), + Case("Test: LowPowerTimer - float operator.", test_lptimer_float_operator), + Case("Test: LowPowerTimer - time measurement 1 ms.", test_lptimer_time_measurement<1000>), + Case("Test: LowPowerTimer - time measurement 10 ms.", test_lptimer_time_measurement<10000>), + Case("Test: LowPowerTimer - time measurement 100 ms.", test_lptimer_time_measurement<100000>), + Case("Test: LowPowerTimer - time measurement 1 s.", test_lptimer_time_measurement<1000000>) +}; + +Specification specification(test_setup, cases); + +int main() +{ + return !Harness::run(specification); +} diff --git a/TESTS/mbed_drivers/race_test/main.cpp b/TESTS/mbed_drivers/race_test/main.cpp index c0a89ff8c5a..f4753f9bf40 100644 --- a/TESTS/mbed_drivers/race_test/main.cpp +++ b/TESTS/mbed_drivers/race_test/main.cpp @@ -68,21 +68,18 @@ static void main_class_race() void test_case_func_race() { Callback cb(main_func_race); - Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE); - Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE); + Thread t1(osPriorityNormal, TEST_STACK_SIZE); + Thread t2(osPriorityNormal, TEST_STACK_SIZE); // Start start first thread - t1->start(cb); + t1.start(cb); // Start second thread while the first is inside the constructor Thread::wait(250); - t2->start(cb); + t2.start(cb); // Wait for the threads to finish - t1->join(); - t2->join(); - - delete t1; - delete t2; + t1.join(); + t2.join(); TEST_ASSERT_EQUAL_UINT32(1, instance_count); @@ -93,21 +90,18 @@ void test_case_func_race() void test_case_class_race() { Callback cb(main_class_race); - Thread *t1 = new Thread(osPriorityNormal, TEST_STACK_SIZE); - Thread *t2 = new Thread(osPriorityNormal, TEST_STACK_SIZE); + Thread t1(osPriorityNormal, TEST_STACK_SIZE); + Thread t2(osPriorityNormal, TEST_STACK_SIZE); // Start start first thread - t1->start(cb); + t1.start(cb); // Start second thread while the first is inside the constructor Thread::wait(250); - t2->start(cb); + t2.start(cb); // Wait for the threads to finish - t1->join(); - t2->join(); - - delete t1; - delete t2; + t1.join(); + t2.join(); TEST_ASSERT_EQUAL_UINT32(1, instance_count); diff --git a/TESTS/mbed_drivers/sleep_lock/main.cpp b/TESTS/mbed_drivers/sleep_lock/main.cpp new file mode 100644 index 00000000000..2e1bcbd80a2 --- /dev/null +++ b/TESTS/mbed_drivers/sleep_lock/main.cpp @@ -0,0 +1,132 @@ + +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if !DEVICE_SLEEP + #error [NOT_SUPPORTED] Sleep not supported for this target +#endif + +#include "utest/utest.h" +#include "unity/unity.h" +#include "greentea-client/test_env.h" + +#include "mbed.h" + +using namespace utest::v1; + +void deep_sleep_lock_lock_test() +{ + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Check basic usage works + DeepSleepLock lock; + TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep()); + } + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Check that unlock and lock change can deep sleep as expected + DeepSleepLock lock; + TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep()); + lock.unlock(); + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + lock.lock(); + TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep()); + } + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Check that unlock releases sleep based on count + DeepSleepLock lock; + lock.lock(); + lock.lock(); + lock.unlock(); + TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep()); + } + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Check that unbalanced locks do not leave deep sleep locked + DeepSleepLock lock; + lock.lock(); + TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep()); + } + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + +} + +void timer_lock_test() +{ + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Just creating a timer object does not lock sleep + Timer timer; + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + } + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Starting a timer does lock sleep + Timer timer; + timer.start(); + TEST_ASSERT_EQUAL(false, sleep_manager_can_deep_sleep()); + } + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Stopping a timer after starting it allows sleep + Timer timer; + timer.start(); + timer.stop(); + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + } + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Starting a timer multiple times still lets you sleep + Timer timer; + timer.start(); + timer.start(); + } + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + { + // Stopping a timer multiple times still lets you sleep + Timer timer; + timer.start(); + timer.stop(); + timer.stop(); + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); + } + TEST_ASSERT_EQUAL(true, sleep_manager_can_deep_sleep()); +} + +Case cases[] = { + Case("DeepSleepLock lock test", deep_sleep_lock_lock_test), + Case("timer lock test", timer_lock_test), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { + GREENTEA_SETUP(20, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() { + Harness::run(specification); +} diff --git a/TESTS/mbed_drivers/ticker/main.cpp b/TESTS/mbed_drivers/ticker/main.cpp index f273cd13ede..abbcdb32eac 100644 --- a/TESTS/mbed_drivers/ticker/main.cpp +++ b/TESTS/mbed_drivers/ticker/main.cpp @@ -13,66 +13,34 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - #include "mbed.h" #include "greentea-client/test_env.h" #include "utest/utest.h" #include "unity/unity.h" -using namespace utest::v1; +using utest::v1::Case; #define ONE_MILLI_SEC 1000 +#define TICKER_COUNT 16 +#define MULTI_TICKER_TIME_MS 100 volatile uint32_t callback_trigger_count = 0; static const int test_timeout = 240; static const int total_ticks = 10; -/* CPU clock */ -extern uint32_t SystemCoreClock; - -#define TOLERANCE_FACTOR 10000.0f -#define US_FACTOR 1000000.0f - -/* Tolerance in microseconds - - Assume below code - - ... - Ticker ticker; - Timer timer; - int32_t ret; - - timer.start(); - ticker.attach_us(callback(wait_callback_sem), 100000); - ret = ticker_callback_sem.wait(); - timer.stop(); - int time_diff = timer.read_us(); - TEST_ASSERT_UINT32_WITHIN((uint32_t)TOLERANCE, 100000, time_diff); - ... - - For 100000[us] callback for NUCLEO_F070RB we get time_diff: 100070[us] - So the extra 70[us] is from time measure functions calls - To take in to account this extra time we introduces TOLERANCE value based on CPU clock (speed) +/* Tolerance is quite arbitrary due to large number of boards with varying level of accuracy */ +#define TOLERANCE_US 1000 - e.g. - For K64F TOLERANCE = (10000 / 120000000) * 1000000 = 83[us] - For NUCLEO_F070RB TOLERANCE = (10000 / 48000000) * 1000000 = 208[us] - For NRF51_DK TOLERANCE = (10000 / 16000000) * 1000000 = 625[us] - */ -#define TOLERANCE ((TOLERANCE_FACTOR / (float)SystemCoreClock) * US_FACTOR) - -#define TICKER_COUNT 16 - -Semaphore ticker_callback_sem(0, 1); -volatile bool ticker_callback_flag; +volatile uint32_t ticker_callback_flag; volatile uint32_t multi_counter; DigitalOut led1(LED1); DigitalOut led2(LED2); -Ticker *ticker1; -Ticker *ticker2; +Ticker *volatile ticker1; +Ticker *volatile ticker2; +Timer gtimer; volatile int ticker_count = 0; volatile bool print_tick = false; @@ -80,18 +48,17 @@ volatile bool print_tick = false; void ticker_callback_1_switch_to_2(void); void ticker_callback_2_switch_to_1(void); - -void ticker_callback_0(void) +void increment_ticker_counter(void) { ++callback_trigger_count; } -void ticker_callback_1_led(void) +void switch_led1_state(void) { led1 = !led1; } -void ticker_callback_2_led(void) +void switch_led2_state(void) { led2 = !led2; } @@ -99,40 +66,44 @@ void ticker_callback_2_led(void) void ticker_callback_1_switch_to_2(void) { ++callback_trigger_count; - ticker1->detach(); - ticker1->attach_us(ticker_callback_2_switch_to_1, ONE_MILLI_SEC); - ticker_callback_1_led(); + // If ticker is NULL then it is being or has been deleted + if (ticker1) { + ticker1->detach(); + ticker1->attach_us(ticker_callback_2_switch_to_1, ONE_MILLI_SEC); + } + switch_led1_state(); } void ticker_callback_2_switch_to_1(void) { ++callback_trigger_count; - ticker2->detach(); - ticker2->attach_us(ticker_callback_1_switch_to_2, ONE_MILLI_SEC); - ticker_callback_2_led(); + // If ticker is NULL then it is being or has been deleted + if (ticker2) { + ticker2->detach(); + ticker2->attach_us(ticker_callback_1_switch_to_2, ONE_MILLI_SEC); + } + switch_led2_state(); } -void wait_and_print() + +void sem_release(Semaphore *sem) { - while (ticker_count <= total_ticks) { - if (print_tick) { - print_tick = false; - greentea_send_kv("tick", ticker_count++); - } - } + sem->release(); } -void wait_callback_sem(void) + +void stop_gtimer_set_flag(void) { - ticker_callback_flag = true; - ticker_callback_sem.release(); + gtimer.stop(); + core_util_atomic_incr_u32((uint32_t*)&ticker_callback_flag, 1); } -void wait_callback_multi(void) +void increment_multi_counter(void) { - multi_counter++; + core_util_atomic_incr_u32((uint32_t*)&multi_counter, 1); } + /* Tests is to measure the accuracy of Ticker over a period of time * * 1) DUT would start to update callback_trigger_count every milli sec, in 2x callback we use 2 tickers @@ -150,7 +121,7 @@ void test_case_1x_ticker() int expected_key = 1; greentea_send_kv("timing_drift_check_start", 0); - ticker1->attach_us(&ticker_callback_0, ONE_MILLI_SEC); + ticker1->attach_us(&increment_ticker_counter, ONE_MILLI_SEC); // wait for 1st signal from host do { @@ -167,7 +138,6 @@ void test_case_1x_ticker() greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail..."); - } void test_case_2x_callbacks() @@ -198,12 +168,11 @@ void test_case_2x_callbacks() greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail..."); - } /** Test many tickers run one after the other - Given a 16 Tickers + Given many Tickers When schedule them one after the other with the same time intervals Then tickers properly execute callbacks When schedule them one after the other with the different time intervals @@ -212,25 +181,25 @@ void test_case_2x_callbacks() void test_multi_ticker(void) { Ticker ticker[TICKER_COUNT]; + const uint32_t extra_wait = 5; // extra 5ms wait time multi_counter = 0; for (int i = 0; i < TICKER_COUNT; i++) { - ticker[i].attach_us(callback(wait_callback_multi), 100 * 1000); + ticker[i].attach_us(callback(increment_multi_counter), MULTI_TICKER_TIME_MS * 1000); } - Thread::wait(105); + Thread::wait(MULTI_TICKER_TIME_MS + extra_wait); for (int i = 0; i < TICKER_COUNT; i++) { ticker[i].detach(); } - TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter); multi_counter = 0; for (int i = 0; i < TICKER_COUNT; i++) { - ticker[i].attach_us(callback(wait_callback_multi), (100 + i) * 1000); + ticker[i].attach_us(callback(increment_multi_counter), (MULTI_TICKER_TIME_MS + i) * 1000); } - Thread::wait(120); + Thread::wait(MULTI_TICKER_TIME_MS + TICKER_COUNT + extra_wait); for (int i = 0; i < TICKER_COUNT; i++) { ticker[i].detach(); } @@ -246,23 +215,19 @@ void test_multi_ticker(void) void test_multi_call_time(void) { Ticker ticker; - int32_t ret; - Timer timer; int time_diff; + const int attach_count = 10; - for (int i = 0; i < 10; i++) { - ticker_callback_flag = false; - timer.reset(); + for (int i = 0; i < attach_count; i++) { + ticker_callback_flag = 0; + gtimer.reset(); - timer.start(); - ticker.attach_us(callback(wait_callback_sem), 100000); - ret = ticker_callback_sem.wait(); - timer.stop(); - time_diff = timer.read_us(); + gtimer.start(); + ticker.attach_us(callback(stop_gtimer_set_flag), MULTI_TICKER_TIME_MS * 1000); + while(!ticker_callback_flag); + time_diff = gtimer.read_us(); - TEST_ASSERT_TRUE(ret > 0); - TEST_ASSERT_EQUAL(true, ticker_callback_flag); - TEST_ASSERT_UINT32_WITHIN(TOLERANCE, 100000, time_diff); + TEST_ASSERT_UINT32_WITHIN(TOLERANCE_US, MULTI_TICKER_TIME_MS * 1000, time_diff); } } @@ -276,24 +241,21 @@ void test_detach(void) { Ticker ticker; int32_t ret; - ticker_callback_flag = false; + const float ticker_time_s = 0.1f; + const uint32_t wait_time_ms = 500; + Semaphore sem(0, 1); - ticker.attach(callback(wait_callback_sem), 0.1f); + ticker.attach(callback(sem_release, &sem), ticker_time_s); - ret = ticker_callback_sem.wait(); + ret = sem.wait(); TEST_ASSERT_TRUE(ret > 0); - TEST_ASSERT_EQUAL(true, ticker_callback_flag); - ticker_callback_flag = false; - ret = ticker_callback_sem.wait(); + ret = sem.wait(); ticker.detach(); /* cancel */ TEST_ASSERT_TRUE(ret > 0); - TEST_ASSERT_EQUAL(true, ticker_callback_flag); - ticker_callback_flag = false; - ret = ticker_callback_sem.wait(500); + ret = sem.wait(wait_time_ms); TEST_ASSERT_EQUAL(0, ret); - TEST_ASSERT_EQUAL(false, ticker_callback_flag); } /** Test single callback time via attach @@ -306,20 +268,16 @@ template void test_attach_time(void) { Ticker ticker; - int32_t ret; - Timer timer; - ticker_callback_flag = false; + ticker_callback_flag = 0; - timer.start(); - ticker.attach(callback(wait_callback_sem), ((float)DELAY_US) / 1000000.0f); - ret = ticker_callback_sem.wait(1000 + (DELAY_US / 1000)); /* prevents infinite wait */ - timer.stop(); + gtimer.reset(); + gtimer.start(); + ticker.attach(callback(stop_gtimer_set_flag), ((float)DELAY_US) / 1000000.0f); + while(!ticker_callback_flag); ticker.detach(); - int time_diff = timer.read_us(); + const int time_diff = gtimer.read_us(); - TEST_ASSERT_TRUE(ret > 0); - TEST_ASSERT_EQUAL(true, ticker_callback_flag); - TEST_ASSERT_UINT64_WITHIN((us_timestamp_t)TOLERANCE, DELAY_US, time_diff); + TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff); } /** Test single callback time via attach_us @@ -332,24 +290,21 @@ template void test_attach_us_time(void) { Ticker ticker; - int32_t ret; - Timer timer; - ticker_callback_flag = false; + ticker_callback_flag = 0; - timer.start(); - ticker.attach_us(callback(wait_callback_sem), DELAY_US); - ret = ticker_callback_sem.wait(1000 + (DELAY_US / 1000)); /* prevents infinite wait */ - timer.stop(); + gtimer.reset(); + gtimer.start(); + ticker.attach_us(callback(stop_gtimer_set_flag), DELAY_US); + while(!ticker_callback_flag); ticker.detach(); - int time_diff = timer.read_us(); + const int time_diff = gtimer.read_us(); - TEST_ASSERT_TRUE(ret > 0); - TEST_ASSERT_EQUAL(true, ticker_callback_flag); - TEST_ASSERT_UINT64_WITHIN((us_timestamp_t)TOLERANCE, DELAY_US, time_diff); + TEST_ASSERT_UINT64_WITHIN(TOLERANCE_US, DELAY_US, time_diff); } -utest::v1::status_t one_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) { +utest::v1::status_t one_ticker_case_setup_handler_t(const Case *const source, const size_t index_of_case) +{ ticker1 = new Ticker(); return greentea_case_setup_handler(source, index_of_case); } @@ -358,26 +313,31 @@ utest::v1::status_t two_ticker_case_setup_handler_t(const Case *const source, co { ticker1 = new Ticker(); ticker2 = new Ticker(); - return greentea_case_setup_handler(source, index_of_case); + return utest::v1::greentea_case_setup_handler(source, index_of_case); } -utest::v1::status_t one_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) +utest::v1::status_t one_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const utest::v1::failure_t reason) { - delete ticker1; - return greentea_case_teardown_handler(source, passed, failed, reason); + Ticker *temp1 = ticker1; + ticker1 = NULL; + delete temp1; + return utest::v1::greentea_case_teardown_handler(source, passed, failed, reason); } -utest::v1::status_t two_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) +utest::v1::status_t two_ticker_case_teardown_handler_t(const Case *const source, const size_t passed, const size_t failed, const utest::v1::failure_t reason) { - delete ticker1; - delete ticker2; - return greentea_case_teardown_handler(source, passed, failed, reason); + Ticker *temp1 = ticker1; + Ticker *temp2 = ticker2; + ticker1 = NULL; + ticker2 = NULL; + delete temp1; + delete temp2; + return utest::v1::greentea_case_teardown_handler(source, passed, failed, reason); } + // Test cases Case cases[] = { - Case("Test attach for 0.001s and time measure", test_attach_time<1000>), - Case("Test attach_us for 1ms and time measure", test_attach_us_time<1000>), Case("Test attach for 0.01s and time measure", test_attach_time<10000>), Case("Test attach_us for 10ms and time measure", test_attach_us_time<10000>), Case("Test attach for 0.1s and time measure", test_attach_time<100000>), @@ -388,18 +348,18 @@ Case cases[] = { Case("Test multi call and time measure", test_multi_call_time), Case("Test multi ticker", test_multi_ticker), Case("Test timers: 1x ticker", one_ticker_case_setup_handler_t,test_case_1x_ticker, one_ticker_case_teardown_handler_t), - Case("Test timers: 2x callbacks", two_ticker_case_setup_handler_t,test_case_2x_callbacks, two_ticker_case_teardown_handler_t), + Case("Test timers: 2x callbacks", two_ticker_case_setup_handler_t,test_case_2x_callbacks, two_ticker_case_teardown_handler_t) }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { GREENTEA_SETUP(test_timeout, "timing_drift_auto"); - return greentea_test_setup_handler(number_of_cases); + return utest::v1::greentea_test_setup_handler(number_of_cases); } -Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); +utest::v1::Specification specification(greentea_test_setup, cases, utest::v1::greentea_test_teardown_handler); int main() { - Harness::run(specification); + utest::v1::Harness::run(specification); } diff --git a/TESTS/mbed_drivers/timer/main.cpp b/TESTS/mbed_drivers/timer/main.cpp new file mode 100644 index 00000000000..dfc16fdf3f2 --- /dev/null +++ b/TESTS/mbed_drivers/timer/main.cpp @@ -0,0 +1,769 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "rtos.h" +#include "hal/us_ticker_api.h" + +using namespace utest::v1; + +extern uint32_t SystemCoreClock; + +/* Macro to define delta based on CPU clock frequency. + * + * Note that some extra time is counted by the timer. + * Additional time is caused by the function calls and + * additional operations performed by wait and + * stop functions before in fact timer is stopped. This may + * add additional time to the counted result. + * + * To take in to account this extra time we introduce DELTA + * value based on CPU clock (speed): + * DELTA = TOLERANCE_FACTOR / SystemCoreClock * US_FACTOR + * + * e.g. + * For K64F DELTA = (30000 / 120000000) * 1000000 = 250[us] + * For NUCLEO_F070RB DELTA = (30000 / 48000000) * 1000000 = 625[us] + * For NRF51_DK DELTA = (30000 / 16000000) * 1000000 = 1875[us] + */ +#define US_PER_SEC 1000000 +#define US_PER_MSEC 1000 +#define TOLERANCE_FACTOR 30000.0f +#define US_FACTOR 1000000.0f + +static const int delta_sys_clk_us = ((int) (TOLERANCE_FACTOR / (float)SystemCoreClock * US_FACTOR)); + +/* When test performs time measurement using Timer in sequence, then measurement error accumulates + * in the successive attempts. */ + #define DELTA_US(i) (delta_sys_clk_us * i) + #define DELTA_S(i) ((float)delta_sys_clk_us * i / US_PER_SEC) + #define DELTA_MS(i) (1 + ( (i * delta_sys_clk_us) / US_PER_MSEC)) + +#define TICKER_FREQ_1MHZ 1000000 +#define TICKER_BITS 32 + +static Timer *p_timer = NULL; + +/* Global variable used to simulate passage of time + * in case when timer which uses user ticker is tested. + */ +static uint32_t curr_ticker_ticks_val; + +/* User ticker interface function. */ +static void stub_interface_init() +{ + /* do nothing. */ +} + +/* User ticker interface function - only this + * ticker interface function is used by Timer API. */ +static uint32_t stub_ticker_read(void) +{ + /* Simulate elapsed time. */ + return curr_ticker_ticks_val; +} + +/* User ticker interface function. */ +static void stub_disable_interrupt(void) +{ + /* do nothing. */ +} + +/* User ticker interface function. */ +static void stub_clear_interrupt(void) +{ + /* do nothing. */ +} + +/* User ticker interface function. */ +static void stub_set_interrupt(timestamp_t timestamp) +{ + /* do nothing. */ +} + +/* User ticker interface function. */ +static void stub_fire_interrupt(void) +{ + /* do nothing. */ +} + +ticker_info_t info = +{ TICKER_FREQ_1MHZ, TICKER_BITS }; + +const ticker_info_t * stub_get_info(void) +{ + return &info; +} + +/* User ticker event queue. */ +static ticker_event_queue_t my_events = { 0 }; + +/* User ticker interface data. */ +static const ticker_interface_t us_interface = { + .init = stub_interface_init, + .read = stub_ticker_read, /* Only this function is used by the Timer. */ + .disable_interrupt = stub_disable_interrupt, + .clear_interrupt = stub_clear_interrupt, + .set_interrupt = stub_set_interrupt, + .fire_interrupt = stub_fire_interrupt, + .get_info = stub_get_info, +}; + +/* User ticker data structure. */ +static const ticker_data_t us_data = { + .interface = &us_interface, + .queue = &my_events +}; + +/* Function which returns user ticker data. */ +const ticker_data_t* get_user_ticker_data(void) +{ + return &us_data; +} + +/* Initialisation of the Timer object which uses + * ticker data provided by the user. + * + * */ +utest::v1::status_t timer_user_ticker_setup_handler(const Case *const source, const size_t index_of_case) +{ + p_timer = new Timer(get_user_ticker_data()); + + /* Check if Timer object has been created. */ + TEST_ASSERT_NOT_NULL(p_timer); + + return greentea_case_setup_handler(source, index_of_case); +} + +/* Initialisation of the Timer object which uses + * default os ticker data. + * + * */ +utest::v1::status_t timer_os_ticker_setup_handler(const Case *const source, const size_t index_of_case) +{ + p_timer = new Timer(); + + /* Check if Timer object has been created. */ + TEST_ASSERT_NOT_NULL(p_timer); + + return greentea_case_setup_handler(source, index_of_case); +} + +/* Test finalisation. + * + * */ +utest::v1::status_t cleanup_handler(const Case *const source, const size_t passed, const size_t failed, const failure_t reason) +{ + delete p_timer; + + p_timer = NULL; + + return greentea_case_teardown_handler(source, passed, failed, reason); +} + +/* This test verifies if timer is stopped after + * creation. + * + * Note: this function assumes that Timer uses os ticker. + * + * Given Timer has been successfully created. + * When read of timer elapsed time is requested. + * Then result is always 0. + */ +void test_timer_creation_os_ticker() +{ + /* Check results. */ + TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us()); + + /* Wait 10 ms. + * After that operation timer read routines should still return 0. */ + wait_ms(10); + + /* Check results. */ + TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us()); +} + +/* This test verifies if timer is stopped after + * creation. + * + * Note: this function assumes that Timer uses user/fake ticker + * which returns time value provided in curr_ticker_ticks_val + * global variable. + * + * Given Timer has been successfully created. + * When read of timer elapsed time is requested. + * Then result is always 0. + */ +void test_timer_creation_user_ticker() +{ + /* For timer which is using user ticker simulate timer + * creation time (irrelevant in case of os ticker). */ + curr_ticker_ticks_val = 10000; + + /* Check results. */ + TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us()); + + /* Simulate that 10 ms has elapsed. + * After that operation timer read routines should still return 0. */ + curr_ticker_ticks_val += 10000; + + /* Check results. */ + TEST_ASSERT_EQUAL_FLOAT(0, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(0, p_timer->read_high_resolution_us()); +} + +/* This test verifies verifies if read(), read_us(), read_ms(), + * read_high_resolution_us() functions returns valid values. + * + * Note: this function assumes that Timer uses user/fake ticker + * which returns time value provided in curr_ticker_ticks_val + * global variable. + * + * Given Timer has been successfully created and + * few times started and stopped after a specified period of time. + * When timer read request is performed. + * Then read functions return accumulated time elapsed between starts + * and stops. + */ +void test_timer_time_accumulation_user_ticker() +{ + /* Simulate that current time is equal to 0 us. */ + curr_ticker_ticks_val = 0; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to 1 us -- */ + curr_ticker_ticks_val = 1; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 1 us has elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(0.000001f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(1, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(1, p_timer->read_high_resolution_us()); + + /* Simulate that 100 us has elapsed between stop and start. */ + curr_ticker_ticks_val = 101; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to 225 us -- */ + curr_ticker_ticks_val = 225; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 125 us have elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(0.000125f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(0, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(125, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(125, p_timer->read_high_resolution_us()); + + /* Simulate that 100 us has elapsed between stop and start. */ + curr_ticker_ticks_val = 325; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to 1200 us -- */ + curr_ticker_ticks_val = 1200; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 1 ms has elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(0.001000f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(1, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(1000, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(1000, p_timer->read_high_resolution_us()); + + /* Simulate that 100 us has elapsed between stop and start. */ + curr_ticker_ticks_val = 1300; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to 125300 us -- */ + curr_ticker_ticks_val = 125300; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 125 ms have elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(0.125000f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(125, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(125000, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(125000, p_timer->read_high_resolution_us()); + + /* Simulate that 100 us has elapsed between stop and start. */ + curr_ticker_ticks_val = 125400; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to 1000400 us -- */ + curr_ticker_ticks_val = 1000400; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 1 s has elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(1.000000f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(1000, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(1000000, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(1000000, p_timer->read_high_resolution_us()); + + /* Simulate that 100 us has elapsed between stop and start. */ + curr_ticker_ticks_val = 1000500; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to 125000500 us -- */ + curr_ticker_ticks_val = 125000500; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 125 s have elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(125.000000f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(125000, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(125000000, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(125000000, p_timer->read_high_resolution_us()); + + /* Simulate that 100 us has elapsed between stop and start. */ + curr_ticker_ticks_val = 125000600; + + /* Start the timer. */ + p_timer->start(); + + /* -- Simulate that current time is equal to MAX_INT_32 us + 600 us (delays + * between stops and starts) -- */ + + /* Note that ticker is based on unsigned 32-bit int microsecond counters + * while timers are based on 32-bit signed int microsecond counters, + * so timers can only count up to a maximum of 2^31-1 microseconds i.e. + * 2147483647 us (about 35 minutes). */ + curr_ticker_ticks_val = 2147484247; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 2147483647 (MAX_INT_32) us have elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(2147.483647f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(2147483, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(2147483647, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(2147483647, p_timer->read_high_resolution_us()); +} + +/* This test verifies if read(), read_us(), read_ms(), + * read_high_resolution_us() + * functions return time accumulated between + * timer starts and stops. + * + * Note this function assumes that Timer uses os ticker. + * + * Given Timer has been successfully created and + * few times started and stopped after a specified period of time. + * When timer read request is performed. + * Then read functions return accumulated time elapsed between starts + * and stops. + */ +void test_timer_time_accumulation_os_ticker() +{ + /* Start the timer. */ + p_timer->start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - totally 10 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, p_timer->read_high_resolution_us()); + + /* Wait 50 ms - this is done to show that time elapsed when + * the timer is stopped does not have influence on the + * timer counted time. */ + wait_ms(50); + + /* ------ */ + + /* Start the timer. */ + p_timer->start(); + + /* Wait 20 ms. */ + wait_ms(20); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - totally 30 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, p_timer->read_high_resolution_us()); + + /* Wait 50 ms - this is done to show that time elapsed when + * the timer is stopped does not have influence on the + * timer counted time. */ + + /* ------ */ + + /* Start the timer. */ + p_timer->start(); + + /* Wait 30 ms. */ + wait_ms(30); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - totally 60 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(3), 0.060f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(3), 60, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(3), 60000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(3), 60000, p_timer->read_high_resolution_us()); + + /* Wait 50 ms - this is done to show that time elapsed when + * the timer is stopped does not have influence on the + * timer time. */ + wait_ms(50); + + /* ------ */ + + /* Start the timer. */ + p_timer->start(); + + /* Wait 1 sec. */ + wait_ms(1000); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - totally 1060 ms have elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(4), 1.060f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(4), 1060, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(4), 1060000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(4), 1060000, p_timer->read_high_resolution_us()); +} + +/* This test verifies if reset() function resets the timer + * counted time. + * + * Note this function assumes that Timer uses os ticker. + * + * Given timer has been started and stopped once, then reset + * operation was performed. + * When timer is started and stopped next time. + * Then timer read functions returns only the the second + * measured time. + */ +void test_timer_reset_os_ticker() +{ + /* First measure 10 ms delay. */ + p_timer->start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - totally 10 ms elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 10, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 10000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 10000, p_timer->read_high_resolution_us()); + + /* Reset the timer - previous measured time should be lost now. */ + p_timer->reset(); + + /* Now measure 20 ms delay. */ + p_timer->start(); + + /* Wait 20 ms. */ + wait_ms(20); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 20 ms elapsed since the reset. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.020f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), 20, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), 20000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), 20000, p_timer->read_high_resolution_us()); +} + +/* This test verifies if reset() function resets the timer + * counted time. + * + * Note this function assumes that Timer uses user ticker. + * + * Given timer has been started and stopped once, then reset + * operation was performed. + * When timer is started and stopped next time. + * Then timer read functions returns only the the second + * measured time. + */ +void test_timer_reset_user_ticker() +{ + /* For timer which is using user ticker simulate set current + * time (irrelevant in case of os ticker). */ + curr_ticker_ticks_val = 0; + + /* First measure 10 ms delay. */ + p_timer->start(); + + /* Simulate that 10 ms have elapsed. */ + curr_ticker_ticks_val = 10000; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - totally 10 ms elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(0.010f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(10, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(10000, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(10000, p_timer->read_high_resolution_us()); + + /* Reset the timer - previous measured time should be lost now. */ + p_timer->reset(); + + /* Now measure 20 ms delay. */ + p_timer->start(); + + /* Simulate that 20 ms have elapsed. */ + curr_ticker_ticks_val = 30000; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 20 ms elapsed since the reset. */ + TEST_ASSERT_EQUAL_FLOAT(0.020f, p_timer->read()); + TEST_ASSERT_EQUAL_INT32(20, p_timer->read_ms()); + TEST_ASSERT_EQUAL_INT32(20000, p_timer->read_us()); + TEST_ASSERT_EQUAL_UINT64(20000, p_timer->read_high_resolution_us()); +} + +/* This test verifies if calling start() for already + * started timer does nothing. + * + * Note this function assumes that Timer uses os ticker. + * + * Given timer is already started. + * When timer is started again. + * Then second start operation is ignored. + */ +void test_timer_start_started_timer_os_ticker() +{ + /* Start the timer. */ + p_timer->start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Now start timer again. */ + p_timer->start(); + + /* Wait 20 ms. */ + wait_ms(20); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 30 ms have elapsed since the first start. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, p_timer->read_high_resolution_us()); +} + +/* This test verifies if calling start() for already + * started timer does nothing. + * + * Note this function assumes that Timer uses user ticker. + * + * Given timer is already started. + * When timer is started again. + * Then second start operation is ignored. + */ +void test_timer_start_started_timer_user_ticker() +{ + /* For timer which is using user ticker set current + * time (irrelevant in case of os ticker). */ + curr_ticker_ticks_val = 0; + + /* Start the timer. */ + p_timer->start(); + + /* Simulate that 10 ms have elapsed. */ + curr_ticker_ticks_val = 10000; + + /* Now start timer again. */ + p_timer->start(); + + /* Simulate that 20 ms have elapsed. */ + curr_ticker_ticks_val = 30000; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results - 30 ms have elapsed since the first start. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(2), 0.030f, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(2), 30, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(2), 30000, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(2), 30000, p_timer->read_high_resolution_us()); +} + +/* This test verifies Timer float operator. + * + * Note this function assumes that Timer uses os ticker. + * + * Given timer is created and a time period time is counted. + * When timer object is casted on float type. + * Then counted type in seconds is returned by means of + * read() function. + */ +void test_timer_float_operator_os_ticker() +{ + /* Start the timer. */ + p_timer->start(); + + /* Wait 10 ms. */ + wait_ms(10); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check result - 10 ms elapsed. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), 0.010f, (float)(*p_timer)); +} + +/* This test verifies Timer float operator. + * + * Note this function assumes that Timer uses user ticker. + * + * Given timer is created and a time period time is counted. + * When timer object is casted on float type. + * Then counted type in seconds is returned by means of + * read() function. + */ +void test_timer_float_operator_user_ticker() +{ + /* For timer which is using user ticker set current + * time (irrelevant in case of os ticker). */ + curr_ticker_ticks_val = 0; + + /* Start the timer. */ + p_timer->start(); + + /* Simulate that 10 ms have elapsed. */ + curr_ticker_ticks_val = 10000; + + /* Stop the timer. */ + p_timer->stop(); + + /* Check result - 10 ms elapsed. */ + TEST_ASSERT_EQUAL_FLOAT(0.010f, (float)(*p_timer)); +} + +/* This test verifies if time counted by the timer is + * valid. + * + * For this test Timer which uses os ticker + * must be used. + * + * Given timer is created. + * When timer is used to measure 1ms/10ms/100ms/1s + * delays. + * Then the results are valid (within acceptable range). + */ +template +void test_timer_time_measurement() +{ + /* Start the timer. */ + p_timer->start(); + + /* Wait us. */ + wait_us(wait_val_us); + + /* Stop the timer. */ + p_timer->stop(); + + /* Check results. */ + TEST_ASSERT_FLOAT_WITHIN(DELTA_S(1), (float)wait_val_us / 1000000, p_timer->read()); + TEST_ASSERT_INT32_WITHIN(DELTA_MS(1), wait_val_us / 1000, p_timer->read_ms()); + TEST_ASSERT_INT32_WITHIN(DELTA_US(1), wait_val_us, p_timer->read_us()); + TEST_ASSERT_UINT64_WITHIN(DELTA_US(1), wait_val_us, p_timer->read_high_resolution_us()); +} + +utest::v1::status_t test_setup(const size_t number_of_cases) { + GREENTEA_SETUP(15, "default_auto"); + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Test: Timer (based on os ticker) is stopped after creation.", timer_os_ticker_setup_handler, test_timer_creation_os_ticker, cleanup_handler), + Case("Test: Timer (based on user ticker) is stopped after creation.", timer_user_ticker_setup_handler, test_timer_creation_user_ticker, cleanup_handler), + + Case("Test: Timer (based on os ticker) - measured time accumulation.", timer_os_ticker_setup_handler, test_timer_time_accumulation_os_ticker, cleanup_handler), + Case("Test: Timer (based on user ticker) measured time accumulation.", timer_user_ticker_setup_handler, test_timer_time_accumulation_user_ticker, cleanup_handler), + + Case("Test: Timer (based on os ticker) - reset.", timer_os_ticker_setup_handler, test_timer_reset_os_ticker, cleanup_handler), + Case("Test: Timer (based on user ticker) - reset.", timer_user_ticker_setup_handler, test_timer_reset_user_ticker, cleanup_handler), + + Case("Test: Timer (based on os ticker) - start started timer.", timer_os_ticker_setup_handler, test_timer_start_started_timer_os_ticker, cleanup_handler), + Case("Test: Timer (based on user ticker) - start started timer.", timer_user_ticker_setup_handler, test_timer_start_started_timer_user_ticker, cleanup_handler), + + Case("Test: Timer (based on os ticker) - float operator.", timer_os_ticker_setup_handler, test_timer_float_operator_os_ticker, cleanup_handler), + Case("Test: Timer (based on user ticker) - float operator.", timer_user_ticker_setup_handler, test_timer_float_operator_user_ticker, cleanup_handler), + + Case("Test: Timer - time measurement 1 ms.", timer_os_ticker_setup_handler, test_timer_time_measurement<1000>, cleanup_handler), + Case("Test: Timer - time measurement 10 ms.", timer_os_ticker_setup_handler, test_timer_time_measurement<10000>, cleanup_handler), + Case("Test: Timer - time measurement 100 ms.", timer_os_ticker_setup_handler, test_timer_time_measurement<100000>, cleanup_handler), + Case("Test: Timer - time measurement 1 s.", timer_os_ticker_setup_handler, test_timer_time_measurement<1000000>, cleanup_handler), +}; + +Specification specification(test_setup, cases); + +int main() { + return !Harness::run(specification); +} + diff --git a/TESTS/mbed_hal/lp_ticker/main.cpp b/TESTS/mbed_hal/lp_ticker/main.cpp index c609c57b8a6..5802644c580 100644 --- a/TESTS/mbed_hal/lp_ticker/main.cpp +++ b/TESTS/mbed_hal/lp_ticker/main.cpp @@ -104,7 +104,10 @@ void lp_ticker_1s_deepsleep() lp_timer.reset(); lp_timer.start(); ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event); - deepsleep(); + /* Make sure deepsleep is allowed, to go to deepsleep */ + bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); + TEST_ASSERT_TRUE_MESSAGE(deep_sleep_allowed, "Deep sleep should be allowed"); + sleep(); while (!complete); lp_timer.stop(); @@ -124,6 +127,8 @@ void lp_ticker_1s_sleep() sleep_manager_lock_deep_sleep(); timer.reset(); timer.start(); + bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); + TEST_ASSERT_FALSE_MESSAGE(deep_sleep_allowed, "Deep sleep should be disallowed"); ticker_insert_event(lp_ticker_data, &delay_event, delay_ts, (uint32_t)&delay_event); sleep(); while (!complete); diff --git a/TESTS/mbed_hal/ticker/main.cpp b/TESTS/mbed_hal/ticker/main.cpp index 334a1ae404e..93ab4f4a94c 100644 --- a/TESTS/mbed_hal/ticker/main.cpp +++ b/TESTS/mbed_hal/ticker/main.cpp @@ -29,7 +29,8 @@ using namespace utest::v1; #define MBED_ARRAY_SIZE(array) (sizeof(array)/sizeof(array[0])) -#define TIMESTAMP_MAX_DELTA MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA +#define TIMESTAMP_MAX_DELTA_BITS(bits) ((uint64_t)(0x7 << ((bits) - 4))) +#define TIMESTAMP_MAX_DELTA TIMESTAMP_MAX_DELTA_BITS(32) struct ticker_interface_stub_t { ticker_interface_t interface; @@ -43,9 +44,11 @@ struct ticker_interface_stub_t { unsigned int clear_interrupt_call; unsigned int set_interrupt_call; unsigned int fire_interrupt_call; + unsigned int get_info_call; }; static ticker_interface_stub_t interface_stub = { 0 }; +static ticker_info_t interface_info_stub = { 0 }; static void ticker_interface_stub_init() { @@ -81,6 +84,12 @@ static void ticker_interface_stub_fire_interrupt() ++interface_stub.fire_interrupt_call; } +static const ticker_info_t *ticker_interface_stub_get_info() +{ + ++interface_stub.get_info_call; + return &interface_info_stub; +} + static void reset_ticker_interface_stub() { interface_stub.interface.init = ticker_interface_stub_init; @@ -91,6 +100,7 @@ static void reset_ticker_interface_stub() ticker_interface_stub_clear_interrupt; interface_stub.interface.set_interrupt =ticker_interface_stub_set_interrupt; interface_stub.interface.fire_interrupt = ticker_interface_stub_fire_interrupt; + interface_stub.interface.get_info = ticker_interface_stub_get_info; interface_stub.initialized = false; interface_stub.interrupt_flag = false; interface_stub.timestamp = 0; @@ -101,6 +111,9 @@ static void reset_ticker_interface_stub() interface_stub.clear_interrupt_call = 0; interface_stub.set_interrupt_call = 0; interface_stub.fire_interrupt_call = 0; + + interface_info_stub.frequency = 1000000; + interface_info_stub.bits = 32; } // stub of the event queue @@ -115,6 +128,12 @@ static void reset_queue_stub() { queue_stub.event_handler = NULL; queue_stub.head = NULL, + queue_stub.tick_last_read = 0; + queue_stub.tick_remainder = 0; + queue_stub.frequency = 0; + queue_stub.bitmask = 0; + queue_stub.max_delta = 0; + queue_stub.max_delta_us = 0; queue_stub.present_time = 0; queue_stub.initialized = false; } @@ -131,6 +150,34 @@ static void reset_ticker_stub() reset_ticker_interface_stub(); } +const uint32_t test_frequencies[] = { + 1, + 32768, // 2^15 + 1000000, + 0xFFFFFFFF // 2^32 - 1 +}; + +const uint32_t test_bitwidths[] = { + 32, + 31, + 16, + 8 +}; + +template < void (F)(uint32_t a, uint32_t b)> +static void test_over_frequency_and_width(void) +{ + for (unsigned int i = 0; i < MBED_ARRAY_SIZE(test_frequencies); i++) { + for (unsigned int j = 0; j < MBED_ARRAY_SIZE(test_bitwidths); j++) { + reset_ticker_stub(); + interface_info_stub.frequency = test_frequencies[i]; + interface_info_stub.bits = test_bitwidths[j]; + + F(test_frequencies[i], test_bitwidths[j]); + } + } +} + static utest::v1::status_t case_setup_handler( const Case *const source, const size_t index_of_case ) { @@ -175,8 +222,7 @@ static utest::v1::status_t greentea_failure_handler( * Then: * - The ticker interface should be initialized * - The queue handler should be set to the handler provided in parameter - * - The internal ticker timestamp should be synced with the counter in the - * interface counter. + * - The internal ticker timestamp should be zero * - interrupt should be scheduled in current timestamp + * TIMESTAMP_MAX_DELTA * - The queue should not contains any event @@ -192,7 +238,7 @@ static void test_ticker_initialization() TEST_ASSERT_TRUE(interface_stub.initialized); TEST_ASSERT_EQUAL_PTR(dummy_handler, queue_stub.event_handler); - TEST_ASSERT_EQUAL_UINT64(interface_stub.timestamp, queue_stub.present_time); + TEST_ASSERT_EQUAL_UINT64(0, queue_stub.present_time); TEST_ASSERT_EQUAL(1, interface_stub.set_interrupt_call); TEST_ASSERT_EQUAL_UINT32( interface_stub.timestamp + TIMESTAMP_MAX_DELTA, @@ -347,7 +393,7 @@ static void test_legacy_insert_event_outside_overflow_range() // test the beginning of the range ticker_event_t first_event = { 0 }; - const timestamp_t timestamp_first_event = interface_stub.timestamp + 1; + const timestamp_t timestamp_first_event = interface_stub.timestamp + 1; const uint32_t id_first_event = 0xAAAAAAAA; ticker_insert_event( @@ -820,6 +866,7 @@ static void test_insert_event_us_outside_overflow_range() ticker_set_handler(&ticker_stub, NULL); interface_stub.set_interrupt_call = 0; interface_stub.timestamp = 0xAAAAAAAA; + queue_stub.tick_last_read = interface_stub.timestamp; queue_stub.present_time = 10ULL << 32 | interface_stub.timestamp; // test the end of the range @@ -881,6 +928,7 @@ static void test_insert_event_us_in_overflow_range() ticker_set_handler(&ticker_stub, NULL); interface_stub.set_interrupt_call = 0; interface_stub.timestamp = 0xAAAAAAAA; + queue_stub.tick_last_read = interface_stub.timestamp; queue_stub.present_time = 10ULL << 32 | interface_stub.timestamp; // test the end of the range @@ -944,6 +992,7 @@ static void test_insert_event_us_underflow() interface_stub.set_interrupt_call = 0; interface_stub.timestamp = 0xAAAAAAAA; + queue_stub.tick_last_read = interface_stub.timestamp; queue_stub.present_time = 10ULL << 32 | interface_stub.timestamp; // test the end of the range @@ -979,6 +1028,7 @@ static void test_insert_event_us_head() ticker_set_handler(&ticker_stub, NULL); interface_stub.set_interrupt_call = 0; interface_stub.timestamp = 0xAAAAAAAA; + queue_stub.tick_last_read = interface_stub.timestamp; queue_stub.present_time = 10ULL << 32 | interface_stub.timestamp; const us_timestamp_t timestamps[] = { @@ -2003,6 +2053,8 @@ static uint32_t ticker_interface_stub_read_interrupt_time() */ static void test_set_interrupt_past_time() { + ticker_set_handler(&ticker_stub, NULL); + interface_stub.set_interrupt_call = 0; interface_stub.fire_interrupt_call = 0; interface_stub.timestamp = 0xFF; @@ -2023,6 +2075,8 @@ static void test_set_interrupt_past_time() */ static void test_set_interrupt_past_time_with_delay() { + ticker_set_handler(&ticker_stub, NULL); + interface_stub.set_interrupt_call = 0; interface_stub.fire_interrupt_call = 0; interface_stub.timestamp = 0xFF; @@ -2038,6 +2092,168 @@ static void test_set_interrupt_past_time_with_delay() TEST_ASSERT_EQUAL(1, interface_stub.fire_interrupt_call); } +/** + * Convert ticks at a given frequency to time in microseconds + * + * Assert if there is a 64-bit overflow + */ +static uint64_t convert_to_us(uint64_t ticks, uint32_t frequency) +{ + uint64_t scaled_ticks = ticks * 1000000; + // Assert that there was not an overflow + TEST_ASSERT_EQUAL(ticks, scaled_ticks / 1000000); + return scaled_ticks / frequency; +} + +/** + * Given an uninitialized ticker instance and an interface of a + * certain frequency and bit width. + * Then the time returned the ticker should match the cumulative time. + */ +void test_frequencies_and_masks(uint32_t frequency, uint32_t bits) +{ + const uint32_t bitmask = ((uint64_t)1 << bits) - 1; + + ticker_set_handler(&ticker_stub, NULL); + uint64_t ticks = 0; + + // Single tick + ticks += 1; + interface_stub.timestamp = ticks & bitmask; + TEST_ASSERT_EQUAL_UINT32(convert_to_us(ticks, frequency), ticker_read(&ticker_stub)); + TEST_ASSERT_EQUAL_UINT64(convert_to_us(ticks, frequency), ticker_read_us(&ticker_stub)); + + // Run until the loop before 64-bit overflow (worst case with frequency=1hz, bits=32) + for (unsigned int k = 0; k < 4294; k++) { + + // Largest value possible tick + ticks += ((uint64_t)1 << bits) - 1; + interface_stub.timestamp = ticks & bitmask; + TEST_ASSERT_EQUAL_UINT32(convert_to_us(ticks, frequency), ticker_read(&ticker_stub)); + TEST_ASSERT_EQUAL_UINT64(convert_to_us(ticks, frequency), ticker_read_us(&ticker_stub)); + } +} + +/** + * Given an uninitialized ticker_data instance. + * When the ticker is initialized + * Then: + * - The internal ticker timestamp should be zero + * - interrupt should be scheduled in current (timestamp + + * TIMESTAMP_MAX_DELTA_BITS(bitwidth)) % modval + * - The queue should not contains any event + */ +static void test_ticker_max_value() +{ + for (int bitwidth = 8; bitwidth <= 32; bitwidth++) { + const uint64_t modval = 1ULL << bitwidth; + + // setup of the stub + reset_ticker_stub(); + interface_info_stub.bits = bitwidth; + interface_stub.timestamp = 0xBA; + + ticker_set_handler(&ticker_stub, NULL); + + TEST_ASSERT_EQUAL_UINT64(0, queue_stub.present_time); + TEST_ASSERT_EQUAL(1, interface_stub.set_interrupt_call); + TEST_ASSERT_EQUAL_UINT32( + (interface_stub.timestamp + TIMESTAMP_MAX_DELTA_BITS(bitwidth)) % modval, + interface_stub.interrupt_timestamp + ); + TEST_ASSERT_EQUAL_PTR(NULL, queue_stub.head); + TEST_ASSERT_EQUAL(0, interface_stub.disable_interrupt_call); + } +} + +/** + * Check that _ticker_match_interval_passed correctly detects matches + * + * Brute force test that _ticker_match_interval_passed returns the correct match value + * for all cominations of values within a small range. + */ +static void test_match_interval_passed() +{ + + for (int modval = 1; modval <= 5; modval++) { + for (int prev = 0; prev < modval; prev++) { + for (int cur = 0; cur < modval; cur++) { + for (int match = 0; match < modval; match++) { + uint32_t delta = (cur - prev) % modval; + uint32_t delta_to_match = (match - prev) % modval; + bool match_expected = false; + if (delta_to_match) { + match_expected = delta >= delta_to_match; + } + + // Sanity checks + if (prev == cur) { + // No time has passed + TEST_ASSERT_EQUAL(false, match_expected); + } else if (match == prev) { + // Match can't occur without an overflow occurring + TEST_ASSERT_EQUAL(false, match_expected); + } else if (cur == match) { + // All other cases where cur == match a match should be expected + TEST_ASSERT_EQUAL(true, match_expected); + } + + // Actual test + TEST_ASSERT_EQUAL(match_expected, _ticker_match_interval_passed(prev, cur, match)); + } + } + } + } +} + +typedef struct { + timestamp_t prev; + timestamp_t cur; + timestamp_t match; + bool result; +} match_interval_entry_t; + +/** + * Check that _ticker_match_interval_passed correctly detects matches + * + * Use a table of pre-computed values to check that _ticker_match_interval_passed + * returns the correct match value. + */ +static void test_match_interval_passed_table() +{ + static const match_interval_entry_t test_values[] = { + /* prev, cur, match, result */ + {0x00000000, 0x00000000, 0x00000000, false}, + {0x00000000, 0x00000000, 0xffffffff, false}, + {0x00000000, 0x00000000, 0x00000001, false}, + {0x00000000, 0xffffffff, 0x00000000, false}, + {0x00000000, 0x00000001, 0x00000000, false}, + {0xffffffff, 0x00000000, 0x00000000, true}, + {0x00000001, 0x00000000, 0x00000000, true}, + {0x00005555, 0x00005555, 0x00005555, false}, + {0x00005555, 0x00005555, 0x00005554, false}, + {0x00005555, 0x00005555, 0x00005556, false}, + {0x00005555, 0x00005554, 0x00005555, false}, + {0x00005555, 0x00005556, 0x00005555, false}, + {0x00005554, 0x00005555, 0x00005555, true}, + {0x00005556, 0x00005555, 0x00005555, true}, + {0xffffffff, 0xffffffff, 0xffffffff, false}, + {0xffffffff, 0xffffffff, 0xfffffffe, false}, + {0xffffffff, 0xffffffff, 0x00000000, false}, + {0xffffffff, 0xfffffffe, 0xffffffff, false}, + {0xffffffff, 0x00000000, 0xffffffff, false}, + {0xfffffffe, 0xffffffff, 0xffffffff, true}, + {0x00000000, 0xffffffff, 0xffffffff, true}, + }; + for (int i = 0; i < MBED_ARRAY_SIZE(test_values); i++) { + const uint32_t prev = test_values[i].prev; + const uint32_t cur = test_values[i].cur; + const uint32_t match = test_values[i].match; + const uint32_t result = test_values[i].result; + TEST_ASSERT_EQUAL(result, _ticker_match_interval_passed(prev, cur, match)); + } +} + static const case_t cases[] = { MAKE_TEST_CASE("ticker initialization", test_ticker_initialization), MAKE_TEST_CASE( @@ -2130,12 +2346,28 @@ static const case_t cases[] = { MAKE_TEST_CASE( "test_set_interrupt_past_time_with_delay", test_set_interrupt_past_time_with_delay + ), + MAKE_TEST_CASE( + "test_frequencies_and_masks", + test_over_frequency_and_width + ), + MAKE_TEST_CASE( + "test_ticker_max_value", + test_ticker_max_value + ), + MAKE_TEST_CASE( + "test_match_interval_passed", + test_match_interval_passed + ), + MAKE_TEST_CASE( + "test_match_interval_passed_table", + test_match_interval_passed_table ) }; static utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(30, "default_auto"); + GREENTEA_SETUP(60, "default_auto"); return verbose_test_setup_handler(number_of_cases); } diff --git a/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp b/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp new file mode 100644 index 00000000000..1428d48e948 --- /dev/null +++ b/TESTS/mbedmicro-rtos-mbed/MemoryPool/main.cpp @@ -0,0 +1,623 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" + +using namespace utest::v1; + +/* Enum used to select block allocation method. */ +typedef enum +{ + ALLOC, CALLOC +} AllocType; + +/* Structure for complex block type. */ +typedef struct +{ + int a; + char b; + int c; +} COMPLEX_TYPE; + +/* Function to check if complex type object is cleared.*/ +bool comp_is_cleared(COMPLEX_TYPE *object) +{ + if (object->a == 0 && object->b == 0 && object->c == 0) { + return true; + } + + return false; +} + +/* Function to check if complex type object holds specified values.*/ +bool comp_is_equal(COMPLEX_TYPE *object, int a, char b, int c) +{ + if (object->a == a && object->b == b && object->c == c) { + return true; + } + + return false; +} + +/* Function to set complex type object fields.*/ +void comp_set(COMPLEX_TYPE *object, int a, char b, int c) +{ + object->a = a; + object->b = b; + object->c = c; +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Given MemoryPool object of the specified type and queue size has + * been successfully created. + * When max number of blocks is allocated from the pool. + * Then all allocations are successful. + * + * */ +template +void test_mem_pool_alloc_success(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + + /* Test alloc()/calloc() methods - try to allocate max number of + blocks. All allocations should be successful. */ + for (i = 0; i < numOfEntries; i++) { + /* Allocate memory block. */ + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + + /* Check if Calloc clears the block. */ + if (atype == CALLOC) { + TEST_ASSERT_EQUAL(0, *p_blocks[i]); + } + + /* Init fields. */ + *p_blocks[i] = (i + 5); + } + + /* Check if blocks holds valid values. */ + for (i = 0; i < numOfEntries; i++) { + TEST_ASSERT_EQUAL((i + 5), *p_blocks[i]); + } +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Complex memory pool block type is used. + * + * Given MemoryPool object of the specified type and queue size has + * been successfully created. + * When max number of blocks is allocated from the pool. + * Then all allocations are successful. + * + * */ +template +void test_mem_pool_alloc_success_complex(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + + /* Test alloc()/calloc() methods - try to allocate max number of + blocks. All allocations should be successful. */ + for (i = 0; i < numOfEntries; i++) { + /* Allocate memory block. */ + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + + /* Check if Calloc clears the block. */ + if (atype == CALLOC) { + TEST_ASSERT_EQUAL(true, comp_is_cleared(p_blocks[i])); + } + + /* Init fields. */ + comp_set(p_blocks[i], i + 1, i + 2, i + 3); + } + + /* Check if blocks holds valid values. */ + for (i = 0; i < numOfEntries; i++) { + TEST_ASSERT_EQUAL(true, comp_is_equal(p_blocks[i], i + 1, i + 2, i + 3)); + } +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Given MemoryPool has already max number of blocks allocated from the pool. + * When next block is allocated. + * Then allocation fails. + * + * */ +template +void test_mem_pool_alloc_fail(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + T * p_extra_block; + uint32_t i; + + /* Allocate all available blocks. */ + for (i = 0; i < numOfEntries; i++) { + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + } + + /* There are no more blocks available. Try to allocate another block. */ + if (atype == ALLOC) { + p_extra_block = mem_pool.alloc(); + } else { + p_extra_block = mem_pool.calloc(); + } + + /* Show that memory pool block has NOT been allocated. */ + TEST_ASSERT_NULL(p_extra_block); +} + +/* Template for functional tests for free() function + * of MemoryPool object. + * + * Given MemoryPool has all blocks allocated. + * When free operation is executed on the each allocated block. + * Then each deallocation is successfully performed. + * + * */ +template +void test_mem_pool_free_success(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + osStatus status; + + /* Allocate all available blocks. */ + for (i = 0; i < numOfEntries; i++) { + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + } + + /* Free all memory blocks. */ + for (i = 0; i < numOfEntries; i++) { + status = mem_pool.free(p_blocks[i]); + + /* Check operation status. */ + TEST_ASSERT_EQUAL(osOK, status); + } +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Basic memory pool block type is used. + * + * Given MemoryPool had all blocks allocated and one block has + * been freed (last). + * When next block is allocated. + * Then allocation is successful. + * + * */ +template +void test_mem_pool_free_realloc_last(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + osStatus status; + + /* Allocate all available blocks. */ + for (i = 0; i < numOfEntries; i++) { + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Init block. */ + *p_blocks[i] = 0xAB; + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + } + + /* Free the last block. */ + status = mem_pool.free(p_blocks[numOfEntries - 1]); + + /* Check status. */ + TEST_ASSERT_EQUAL(osOK, status); + + /* Try to allocate another block (one block is now available). */ + if (atype == ALLOC) { + p_blocks[numOfEntries - 1] = mem_pool.alloc(); + } else { + p_blocks[numOfEntries - 1] = mem_pool.calloc(); + } + + /* Show that memory pool block has been now allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[numOfEntries - 1]); + + /* Check if Calloc clears the block. */ + if (atype == CALLOC) { + TEST_ASSERT_EQUAL(0, *p_blocks[numOfEntries - 1]); + } +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Complex memory pool block type is used. + * + * Given MemoryPool had all blocks allocated and one block has + * been freed (last). + * When next block is allocated. + * Then allocation is successful. + * + * */ +template +void test_mem_pool_free_realloc_last_complex(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + osStatus status; + + /* Allocate all available blocks. */ + for (i = 0; i < numOfEntries; i++) { + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Init block. */ + comp_set(p_blocks[i], i + 1, i + 2, i + 3); + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + } + + /* Free the last block. */ + status = mem_pool.free(p_blocks[numOfEntries - 1]); + + /* Check status. */ + TEST_ASSERT_EQUAL(osOK, status); + + /* Try to allocate another block (one block is now available). */ + if (atype == ALLOC) { + p_blocks[numOfEntries - 1] = mem_pool.alloc(); + } else { + p_blocks[numOfEntries - 1] = mem_pool.calloc(); + } + + /* Show that memory pool block has been now allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[numOfEntries - 1]); + + /* Check if Calloc clears the block. */ + if (atype == CALLOC) { + TEST_ASSERT_EQUAL(true, comp_is_cleared(p_blocks[numOfEntries - 1])); + } +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Basic memory pool block type is used. + * + * Given MemoryPool had all blocks allocated and one block has + * been freed (first). + * When next block is allocated. + * Then allocation is successful. + * + * */ +template +void test_mem_pool_free_realloc_first(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + osStatus status; + + /* Allocate all available blocks. */ + for (i = 0; i < numOfEntries; i++) { + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Init block. */ + *p_blocks[i] = 0xAB; + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + } + + /* Free the last block. */ + status = mem_pool.free(p_blocks[0]); + + /* Check status. */ + TEST_ASSERT_EQUAL(osOK, status); + + /* Try to allocate another block (one block is now available). */ + if (atype == ALLOC) { + p_blocks[0] = mem_pool.alloc(); + } else { + p_blocks[0] = mem_pool.calloc(); + } + + /* Show that memory pool block has been now allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[0]); + + /* Check if Calloc clears the block. */ + if (atype == CALLOC) { + TEST_ASSERT_EQUAL(0, *p_blocks[0]); + } +} + +/* Template for functional tests for alloc(), calloc() functions + * of MemoryPool object. + * + * Complex memory pool block type is used. + * + * Given MemoryPool had all blocks allocated and one block has + * been freed (first). + * When next block is allocated. + * Then allocation is successful. + * + * */ +template +void test_mem_pool_free_realloc_first_complex(AllocType atype) +{ + MemoryPool mem_pool; + T * p_blocks[numOfEntries]; + uint32_t i; + osStatus status; + + /* Allocate all available blocks. */ + for (i = 0; i < numOfEntries; i++) { + if (atype == ALLOC) { + p_blocks[i] = mem_pool.alloc(); + } else { + p_blocks[i] = mem_pool.calloc(); + } + + /* Init block. */ + comp_set(p_blocks[i], i + 1, i + 2, i + 3); + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[i]); + } + + /* Free the last block. */ + status = mem_pool.free(p_blocks[0]); + + /* Check status. */ + TEST_ASSERT_EQUAL(osOK, status); + + /* Try to allocate another block (one block is now available). */ + if (atype == ALLOC) { + p_blocks[0] = mem_pool.alloc(); + } else { + p_blocks[0] = mem_pool.calloc(); + } + + /* Show that memory pool block has been now allocated. */ + TEST_ASSERT_NOT_NULL(p_blocks[0]); + + /* Check if Calloc clears the block. */ + if (atype == CALLOC) { + TEST_ASSERT_EQUAL(true, comp_is_cleared(p_blocks[0])); + } +} + +/* Robustness checks for free() function. + * + * Given block from the MemoryPool has been successfully deallocated. + * When free operation is executed on this block again. + * Then operation fails with osErrorResource status. + * + * */ +void test_mem_pool_free_on_freed_block() +{ + MemoryPool mem_pool; + int * p_block; + osStatus status; + + /* Allocate memory block. */ + p_block = mem_pool.alloc(); + + /* Show that memory pool block has been allocated. */ + TEST_ASSERT_NOT_NULL(p_block); + + /* Free memory block. */ + status = mem_pool.free(p_block); + + /* Check operation status. */ + TEST_ASSERT_EQUAL(osOK, status); + + /* Free memory block again. */ + status = mem_pool.free(p_block); + + /* Check operation status. */ + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/* Robustness checks for free() function. + * Function under test is called with invalid parameters. + * + * Given MemoryPool object has been successfully created. + * When free operation is performed on NULL address. + * Then deallocation fails with osErrorParameter error. + * + */ +void free_block_invalid_parameter_null() +{ + MemoryPool mem_pool; + osStatus status; + + /* Try to free block passing invalid parameter (NULL). */ + status = mem_pool.free(NULL); + + /* Check operation status. */ + TEST_ASSERT_EQUAL(osErrorParameter, status); +} + +/* Robustness checks for free() function. + * Function under test is called with invalid parameters. + * + * Given MemoryPool object has been successfully created. + * When free operation is performed on invalid address. + * Then deallocation fails with osErrorParameter error. + * + */ +void free_block_invalid_parameter() +{ + MemoryPool mem_pool; + osStatus status; + + /* Try to free block passing invalid parameter (variable address). */ + status = mem_pool.free(reinterpret_cast(&status)); + + /* Check operation status. */ + TEST_ASSERT_EQUAL(osErrorParameter, status); +} + +/* Use wrapper functions to reduce memory usage. */ + +template +void test_mem_pool_alloc_success_wrapper() +{ + test_mem_pool_alloc_success(ALLOC); + test_mem_pool_alloc_success(CALLOC); +} + +template +void test_mem_pool_alloc_success_complex_wrapper() +{ + test_mem_pool_alloc_success_complex(ALLOC); + test_mem_pool_alloc_success_complex(CALLOC); +} + +template +void test_mem_pool_free_success_wrapper() +{ + test_mem_pool_free_success(ALLOC); + test_mem_pool_free_success(CALLOC); +} + +template +void test_mem_pool_free_realloc_last_wrapper() +{ + test_mem_pool_free_realloc_last(ALLOC); + test_mem_pool_free_realloc_last(CALLOC); + +} + +template +void test_mem_pool_free_realloc_first_wrapper() +{ + test_mem_pool_free_realloc_first(ALLOC); + test_mem_pool_free_realloc_first(CALLOC); +} + +template +void test_mem_pool_free_realloc_first_complex_wrapper() +{ + test_mem_pool_free_realloc_first_complex(ALLOC); + test_mem_pool_free_realloc_first_complex(CALLOC); +} + +template +void test_mem_pool_free_realloc_last_complex_wrapper() +{ + test_mem_pool_free_realloc_last_complex(ALLOC); + test_mem_pool_free_realloc_last_complex(CALLOC); +} + +template +void test_mem_pool_alloc_fail_wrapper() +{ + test_mem_pool_alloc_fail(ALLOC); + test_mem_pool_alloc_fail(CALLOC); +} + +Case cases[] = { + Case("Test: alloc()/calloc() - success, 4 bytes b_type, q_size equal to 1.", test_mem_pool_alloc_success_wrapper), + Case("Test: alloc()/calloc() - success, 4 bytes b_type, q_size equal to 3.", test_mem_pool_alloc_success_wrapper), + Case("Test: alloc()/calloc() - success, 1 bytes b_type, q_size equal to 1.", test_mem_pool_alloc_success_wrapper), + Case("Test: alloc()/calloc() - success, 1 bytes b_type, q_size equal to 3.", test_mem_pool_alloc_success_wrapper), + Case("Test: alloc()/calloc() - success, complex b_type, q_size equal to 1.", test_mem_pool_alloc_success_complex_wrapper), + Case("Test: alloc()/calloc() - success, complex b_type, q_size equal to 3.", test_mem_pool_alloc_success_complex_wrapper), + + Case("Test: free() - success, 4 bytes b_type, q_size equal to 1.", test_mem_pool_free_success_wrapper), + Case("Test: free() - success, 4 bytes b_type, q_size equal to 3.", test_mem_pool_free_success_wrapper), + Case("Test: free() - success, complex b_type, q_size equal to 1.", test_mem_pool_free_success_wrapper), + Case("Test: free() - success, complex b_type, q_size equal to 3.", test_mem_pool_free_success_wrapper), + + Case("Test: re-allocation of the last block, basic type.", test_mem_pool_free_realloc_last_wrapper), + Case("Test: re-allocation of the first block, basic type.", test_mem_pool_free_realloc_first_wrapper), + Case("Test: re-allocation of the first block, complex type.", test_mem_pool_free_realloc_first_complex_wrapper), + Case("Test: re-allocation of the last block, complex type.", test_mem_pool_free_realloc_last_complex_wrapper), + + Case("Test: fail (out of free blocks).", test_mem_pool_alloc_fail_wrapper), + + Case("Test: free() - robust (free block twice).", test_mem_pool_free_on_freed_block), + Case("Test: free() - robust (free called with invalid param - NULL).", free_block_invalid_parameter_null), + Case("Test: free() - robust (free called with invalid param).", free_block_invalid_parameter) +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(20, "default_auto"); + return greentea_test_setup_handler(number_of_cases); +} + +Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); + +int main() +{ + Harness::run(specification); +} + diff --git a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp index dc066c9093f..87b1e6712f9 100644 --- a/TESTS/mbedmicro-rtos-mbed/basic/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/basic/main.cpp @@ -14,49 +14,57 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - - -/* - * Tests is to measure the accuracy of Thread::wait() over a period of time - * - * - * 1) DUT would start to update callback_trigger_count every milli sec - * 2) Host would query what is current count base_time, Device responds by the callback_trigger_count - * 3) Host after waiting for measurement stretch. It will query for device time again final_time. - * 4) Host computes the drift considering base_time, final_time, transport delay and measurement stretch - * 5) Finally host send the results back to device pass/fail based on tolerance. - * 6) More details on tests can be found in timing_drift_auto.py - * - */ - #include "mbed.h" #include "greentea-client/test_env.h" -#include "rtos.h" +#include "utest/utest.h" #include "unity/unity.h" #if defined(MBED_RTOS_SINGLE_THREAD) #error [NOT_SUPPORTED] test not supported #endif -#define TEST_STACK_SIZE 1024 +using utest::v1::Case; + +#define TEST_STACK_SIZE 256 #define ONE_MILLI_SEC 1000 -volatile uint32_t callback_trigger_count = 0; +volatile uint32_t elapsed_time_ms = 0; +static const int test_timeout = 40; -static const int test_timeout = 240; -bool test_result = false; -void update_tick_thread() { +void update_tick_thread(Mutex *mutex) +{ while (true) { Thread::wait(1); - ++callback_trigger_count; + mutex->lock(); + ++elapsed_time_ms; + mutex->unlock(); } } -void gt_comm_wait_thread() { + +/** Tests is to measure the accuracy of Thread::wait() over a period of time + + Given + a thread updating elapsed_time_ms every milli sec + and host script for time measurement accuracy check (More details on tests can be found in timing_drift_auto.py) + When host query what is current count base_time + Then Device responds by the elapsed_time_ms + When host query what is current count final_time + Then Device responds by the elapsed_time_ms + When host computes the drift considering base_time, final_time, transport delay and measurement stretch + Then host send the results back to device pass/fail based on tolerance + */ +void test(void) +{ char _key[11] = { }; char _value[128] = { }; int expected_key = 1; + Mutex mutex; + uint32_t elapsed_time; + + Thread tick_thread(osPriorityHigh, TEST_STACK_SIZE); + tick_thread.start(callback(update_tick_thread, &mutex)); greentea_send_kv("timing_drift_check_start", 0); @@ -65,28 +73,41 @@ void gt_comm_wait_thread() { greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); expected_key = strcmp(_key, "base_time"); } while (expected_key); - greentea_send_kv(_key, callback_trigger_count * ONE_MILLI_SEC); + + mutex.lock(); + elapsed_time = elapsed_time_ms; + mutex.unlock(); + // send base_time + greentea_send_kv(_key, elapsed_time * ONE_MILLI_SEC); // wait for 2nd signal from host greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); - greentea_send_kv(_key, callback_trigger_count * ONE_MILLI_SEC); + + mutex.lock(); + elapsed_time = elapsed_time_ms; + mutex.unlock(); + // send final_time + greentea_send_kv(_key, elapsed_time * ONE_MILLI_SEC); //get the results from host greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); - if (strcmp("pass", _key) == 0) { - test_result = true; - } + TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail..."); } -int main() { +Case cases[] = { + Case("Test Thread::wait accuracy", test) +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ GREENTEA_SETUP(test_timeout, "timing_drift_auto"); - Thread tick_thread(osPriorityHigh, TEST_STACK_SIZE); - Thread gt_conn_thread(osPriorityNormal, TEST_STACK_SIZE); + return utest::v1::greentea_test_setup_handler(number_of_cases); +} - tick_thread.start(update_tick_thread); - gt_conn_thread.start(gt_comm_wait_thread); - gt_conn_thread.join(); +utest::v1::Specification specification(greentea_test_setup, cases); - GREENTEA_TESTSUITE_RESULT(test_result); +int main() +{ + utest::v1::Harness::run(specification); } diff --git a/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp b/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp new file mode 100644 index 00000000000..d33c9c7bac0 --- /dev/null +++ b/TESTS/mbedmicro-rtos-mbed/condition_variable/main.cpp @@ -0,0 +1,186 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "rtos.h" + +#if defined(MBED_RTOS_SINGLE_THREAD) + #error [NOT_SUPPORTED] test not supported +#endif + +using namespace utest::v1; + +#define TEST_STACK_SIZE 512 +#define TEST_DELAY 10 + +static int change_counter = 0; +static Mutex mutex; +static ConditionVariable cond(mutex); + +void increment_on_signal() +{ + mutex.lock(); + + cond.wait(); + change_counter++; + + mutex.unlock(); +} + +void test_notify_one() +{ + Thread t1(osPriorityNormal, TEST_STACK_SIZE); + Thread t2(osPriorityNormal, TEST_STACK_SIZE); + + change_counter = 0; + t1.start(increment_on_signal); + t2.start(increment_on_signal); + + wait_ms(TEST_DELAY); + TEST_ASSERT_EQUAL(0, change_counter); + + mutex.lock(); + cond.notify_one(); + mutex.unlock(); + + wait_ms(TEST_DELAY); + TEST_ASSERT_EQUAL(1, change_counter); + + mutex.lock(); + cond.notify_one(); + mutex.unlock(); + + t1.join(); + t2.join(); +} + +void test_notify_all() +{ + Thread t1(osPriorityNormal, TEST_STACK_SIZE); + Thread t2(osPriorityNormal, TEST_STACK_SIZE); + + change_counter = 0; + t1.start(increment_on_signal); + t2.start(increment_on_signal); + + wait_ms(TEST_DELAY); + TEST_ASSERT_EQUAL(0, change_counter); + + mutex.lock(); + cond.notify_all(); + mutex.unlock(); + + wait_ms(TEST_DELAY); + TEST_ASSERT_EQUAL(2, change_counter); + + t1.join(); + t2.join(); +} + + +class TestConditionVariable : public ConditionVariable { + +public: + static void test_linked_list(void) + { + Waiter *list = NULL; + Waiter w1; + Waiter w2; + Waiter w3; + Waiter w4; + + TEST_ASSERT_EQUAL(0, validate_and_get_size(&list)); + + // Add 4 nodes + _add_wait_list(&list, &w1); + TEST_ASSERT_EQUAL(1, validate_and_get_size(&list)); + _add_wait_list(&list, &w2); + TEST_ASSERT_EQUAL(2, validate_and_get_size(&list)); + _add_wait_list(&list, &w3); + TEST_ASSERT_EQUAL(3, validate_and_get_size(&list)); + _add_wait_list(&list, &w4); + TEST_ASSERT_EQUAL(4, validate_and_get_size(&list)); + + // Remove a middle node + _remove_wait_list(&list, &w2); + TEST_ASSERT_EQUAL(3, validate_and_get_size(&list)); + + // Remove front node + _remove_wait_list(&list, &w1); + TEST_ASSERT_EQUAL(2, validate_and_get_size(&list)); + + // remove back node + _remove_wait_list(&list, &w4); + TEST_ASSERT_EQUAL(1, validate_and_get_size(&list)); + + // remove last node + _remove_wait_list(&list, &w3); + TEST_ASSERT_EQUAL(0, validate_and_get_size(&list)); + + TEST_ASSERT_EQUAL_PTR(NULL, list); + } + + /** + * Validate the linked list an return the number of elements + * + * If this list is invalid then this function asserts and does not + * return. + * + * Every node in a valid linked list has the properties: + * 1. node->prev->next == node + * 2. node->next->prev == node + */ + static int validate_and_get_size(Waiter **list) + { + Waiter *first = *list; + if (NULL == first) { + // List is empty + return 0; + } + + int size = 0; + Waiter *current = first; + do { + TEST_ASSERT_EQUAL_PTR(current, current->prev->next); + TEST_ASSERT_EQUAL_PTR(current, current->next->prev); + current = current->next; + size++; + } while (current != first); + return size; + } + +}; + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(10, "default_auto"); + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Test notify one", test_notify_one), + Case("Test notify all", test_notify_all), + Case("Test linked list", TestConditionVariable::test_linked_list), +}; + +Specification specification(test_setup, cases); + +int main() +{ + return !Harness::run(specification); +} diff --git a/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp b/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp index e9d0a269e40..7753a4521d9 100644 --- a/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/event_flags/main.cpp @@ -17,47 +17,361 @@ #include "mbed.h" #include "greentea-client/test_env.h" -#include "rtos.h" +#include "unity/unity.h" +#include "utest/utest.h" + +using utest::v1::Case; #if defined(MBED_RTOS_SINGLE_THREAD) #error [NOT_SUPPORTED] test not supported #endif -#define TEST_STACK_SIZE 512 +#define THREAD_STACK_SIZE 320 /* 512B stack on GCC_ARM compiler cause out of memory on some 16kB RAM boards e.g. NUCLEO_F070RB */ + +#define MAX_FLAG_POS 30 +#define PROHIBITED_FLAG_POS 31 -#define EVENT_SET_VALUE 0x01 -const int EVENT_TO_EMIT = 100; -const int EVENT_HANDLE_DELAY = 25; +/* flags */ +#define FLAG01 0x1FFF /* 00000000000000000001111111111111 */ +#define FLAG02 0x3FFE000 /* 00000011111111111110000000000000 */ +#define FLAG03 0x7C000000 /* 01111100000000000000000000000000 */ +#define PROHIBITED_FLAG 0x80000000 /* 10000000000000000000000000000000 */ +#define NO_FLAGS 0x0 -DigitalOut led(LED1); -EventFlags event_flags; +Semaphore sync_sem(0, 1); -int events_counter = 0; +/* In order to successfully run this test suite when compiled with --profile=debug + * error() has to be redefined as noop. + * + * EventFlags calls RTX API which uses Event Recorder functionality. When compiled + * with MBED_TRAP_ERRORS_ENABLED=1 (set in debug profile) EvrRtxEventFlagsError() calls error() + * which aborts test program. + */ +#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED +void error(const char* format, ...) { + (void) format; +} +#endif -void led_thread() { - while (true) { - event_flags.wait_all(EVENT_SET_VALUE); - led = !led; - events_counter++; +template +void send_thread(EventFlags *ef) +{ + for (uint32_t i = 0; i <= MAX_FLAG_POS; i++) { + const uint32_t flag = flags & (1 << i); + if (flag) { + ef->set(flag); + Thread::wait(wait_ms); + } } } -int main (void) { - GREENTEA_SETUP(10, "default_auto"); +template +void send_thread_sync(EventFlags *ef) +{ + for (uint32_t i = 0; i <= MAX_FLAG_POS; i++) { + const uint32_t flag = flags & (1 << i); + if (flag) { + sync_sem.wait(); + ef->set(flag); + Thread::wait(wait_ms); + } + } +} - Thread thread(osPriorityNormal, TEST_STACK_SIZE); - thread.start(led_thread); +template +void wait_thread_all(EventFlags *ef) +{ + uint32_t ret, flags_after_clear; + ret = ef->wait_all(flags); + flags_after_clear = ef->get(); + TEST_ASSERT(flags | ret); + TEST_ASSERT(flags | ~flags_after_clear); +} - bool result = false; - while (true) { - Thread::wait(2 * EVENT_HANDLE_DELAY); - event_flags.set(EVENT_SET_VALUE); - if (events_counter == EVENT_TO_EMIT) { - result = true; - break; - } +/** Test if get on empty EventFlags object return NO_FLAGS + + Given a empty EventFlags object + When call @a get + Then @a get return status is NO_FLAGS + */ +void test_empty_get(void) +{ + EventFlags ev; + uint32_t flags; + + flags = ev.get(); + TEST_ASSERT_EQUAL(NO_FLAGS, flags); +} + +/** Test if clear on empty EventFlags object return NO_FLAGS + + Given a empty EventFlags object + When call @a clear(NO_FLAGS) + Then @a clear return status is NO_FLAGS + */ +void test_empty_clear(void) +{ + EventFlags ev; + uint32_t flags; + + flags = ev.clear(NO_FLAGS); + TEST_ASSERT_EQUAL(NO_FLAGS, flags); +} + +/** Test if set on empty EventFlags object return NO_FLAGS + + Given a empty EventFlags object + When call @a set(NO_FLAGS) + Then @a set return status is NO_FLAGS + */ +void test_empty_set(void) +{ + EventFlags ev; + uint32_t flags; + + flags = ev.set(NO_FLAGS); + TEST_ASSERT_EQUAL(NO_FLAGS, flags); +} + +/** Test if call of set/clean with PROHIBITED_FLAG doesn't invalidates object flags + + Given a EventFlags object with all flags already set + When call @a clear(PROHIBITED_FLAG) with prohibited flag + Then @a clear return status is osFlagsErrorParameter and object flags stays unchanged + When call @a set(PROHIBITED_FLAG) with prohibited flag + Then @a set return status is osFlagsErrorParameter and object flags stays unchanged + + @note Each signal has up to 31 event flags 0x1, 0x2, 0x4, 0x8, ..., 0x40000000 + Most significant bit is reserved and thereby flag 0x80000000 is prohibited + */ +void test_prohibited(void) +{ + EventFlags ev; + uint32_t flags; + + ev.set(FLAG01 | FLAG02 | FLAG03); + + flags = ev.clear(PROHIBITED_FLAG); + TEST_ASSERT_EQUAL(osFlagsErrorParameter, flags); + + flags = ev.get(); + TEST_ASSERT_EQUAL(FLAG01 | FLAG02 | FLAG03, flags); + + flags = ev.set(PROHIBITED_FLAG); + TEST_ASSERT_EQUAL(osFlagsErrorParameter, flags); + + flags = ev.get(); + TEST_ASSERT_EQUAL(FLAG01 | FLAG02 | FLAG03, flags); +} + +/** Test set/get/clear for full flag range + + Given a EventFlags object + When call @a clear + Then @a clear return status is already set flags + When call @a set with specified flag + Then @a set return status is flags after setting + When call @a get + Then @a get return status is set flags + */ +void test_set_get_clear_full_flag_range(void) +{ + EventFlags ev; + uint32_t flag, flags, ret; + + flags = NO_FLAGS; + for (int i = 0; i <= MAX_FLAG_POS; i++) { + ret = ev.clear(); + TEST_ASSERT_EQUAL(flags, ret); + flags = 1 << i; + ret = ev.set(flags); + TEST_ASSERT_EQUAL(flags, ret); + ret = ev.get(); + TEST_ASSERT_EQUAL(flags, ret); + } + + ev.clear(); + flags = NO_FLAGS; + for (int i = 0; i <= MAX_FLAG_POS; i++) { + ret = ev.clear(NO_FLAGS); + TEST_ASSERT_EQUAL(flags, ret); + flag = 1 << i; + flags |= flag; + ret = ev.set(flag); + TEST_ASSERT_EQUAL(flags, ret); + ret = ev.get(); + TEST_ASSERT_EQUAL(flags, ret); + } +} + +/** Test if multi-threaded flag set cause wait_all to return + + Given a EventFlags object and three threads are started in parallel + When threads set specified flags + Then main thread waits until receive all of them + */ +void test_multi_thread_all(void) +{ + EventFlags ef; + Thread thread1(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread2(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread3(osPriorityNormal, THREAD_STACK_SIZE); + thread1.start(callback(send_thread, &ef)); + thread2.start(callback(send_thread, &ef)); + thread3.start(callback(send_thread, &ef)); + + uint32_t ret = ef.wait_all(FLAG01 | FLAG02 | FLAG03); + TEST_ASSERT_EQUAL(FLAG01 | FLAG02 | FLAG03, ret); +} + +/** Test if multi-threaded flag set cause wait_any to return + + Given a EventFlags object and three threads are started in parallel + When threads set specified flags + Then main thread waits until receive all of them + */ +void test_multi_thread_any(void) +{ + EventFlags ef; + uint32_t ret; + Thread thread1(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread2(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread3(osPriorityNormal, THREAD_STACK_SIZE); + thread1.start(callback(send_thread, &ef)); + thread2.start(callback(send_thread, &ef)); + thread3.start(callback(send_thread, &ef)); + + for (int i = 0; i <= MAX_FLAG_POS; i++) { + uint32_t flag = 1 << i; + ret = ef.wait_any(flag); + TEST_ASSERT(flag | ret); + } + ret = ef.get(); + TEST_ASSERT_EQUAL(NO_FLAGS, ret); +} + +/** Test if multi-threaded flag set cause wait_any(with timeout) to return + + Given a EventFlags object and thread is running + When main thread call @ wait_any with timeout + Then when timeout expires @ wait_any return status is osFlagsErrorTimeout + When main thread call @ wait_any with timeout and thread set specified flags + Then main thread waits until receive all of them and @ wait_any return status is wait flag + */ +void test_multi_thread_any_timeout(void) +{ + EventFlags ef; + uint32_t ret; + Thread thread(osPriorityNormal, THREAD_STACK_SIZE); + thread.start(callback(send_thread_sync, &ef)); + + for (int i = 0; i <= MAX_FLAG_POS; i++) { + uint32_t flag = 1 << i; + + ret = ef.wait_any(flag, 10); + TEST_ASSERT_EQUAL(osFlagsErrorTimeout, ret); + + sync_sem.release(); + ret = ef.wait_any(flag, 10); + TEST_ASSERT_EQUAL(flag, ret); + } + ret = ef.get(); + TEST_ASSERT_EQUAL(NO_FLAGS, ret); +} + +/** Test if multi-threaded flag set cause wait_any(without clear) to return + + Given a EventFlags object and three threads are started in parallel + When threads set specified flags + Then main thread waits until receive all of them + */ +void test_multi_thread_any_no_clear(void) +{ + EventFlags ef; + uint32_t ret; + Thread thread1(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread2(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread3(osPriorityNormal, THREAD_STACK_SIZE); + thread1.start(callback(send_thread, &ef)); + thread2.start(callback(send_thread, &ef)); + thread3.start(callback(send_thread, &ef)); + + for (int i = 0; i <= MAX_FLAG_POS; i++) { + uint32_t flag = 1 << i; + ret = ef.wait_any(flag, osWaitForever, false); + TEST_ASSERT(flag | ret); + ret = ef.clear(flag); + TEST_ASSERT(ret < osFlagsError); + } + ret = ef.get(); + TEST_ASSERT_EQUAL(NO_FLAGS, ret); +} + +/** Test multi-threaded wait_any + + Given a EventFlags object and three threads are started in parallel + When flags are set in main thread + Then other threads waits until receive all of them + */ +void test_multi_thread_all_many_wait(void) +{ + EventFlags ef; + { + Thread thread1(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread2(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread3(osPriorityNormal, THREAD_STACK_SIZE); + thread1.start(callback(wait_thread_all, &ef)); + thread2.start(callback(wait_thread_all, &ef)); + thread3.start(callback(wait_thread_all, &ef)); + + ef.set(FLAG01 | FLAG02 | FLAG03); + thread1.join(); + thread2.join(); + thread3.join(); + TEST_ASSERT_EQUAL(NO_FLAGS, ef.get()); } - GREENTEA_TESTSUITE_RESULT(result); - return 0; + + { + Thread thread1(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread2(osPriorityNormal, THREAD_STACK_SIZE); + Thread thread3(osPriorityNormal, THREAD_STACK_SIZE); + thread1.start(callback(wait_thread_all, &ef)); + thread2.start(callback(wait_thread_all, &ef)); + thread3.start(callback(wait_thread_all, &ef)); + + ef.set(FLAG01); + thread1.join(); + ef.set(FLAG02); + thread2.join(); + ef.set(FLAG03); + thread3.join(); + TEST_ASSERT_EQUAL(NO_FLAGS, ef.get()); + } +} + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(10, "default_auto"); + return utest::v1::verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Test empty clear", test_empty_clear), + Case("Test empty get", test_empty_get), + Case("Test empty set", test_empty_set), + Case("Test clear/set with prohibited flag", test_prohibited), + Case("Test set/get/clear for full flag range", test_set_get_clear_full_flag_range), + Case("Test multi-threaded wait_all", test_multi_thread_all), + Case("Test multi-threaded wait_any", test_multi_thread_any), + Case("Test multi-threaded wait_all many wait", test_multi_thread_all_many_wait), + Case("Test multi-threaded wait_any timeout", test_multi_thread_any_timeout), + Case("Test multi-threaded wait_any no clear", test_multi_thread_any_no_clear) +}; + +utest::v1::Specification specification(test_setup, cases); + +int main() +{ + return !utest::v1::Harness::run(specification); } diff --git a/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp new file mode 100644 index 00000000000..b2e253a13f8 --- /dev/null +++ b/TESTS/mbedmicro-rtos-mbed/heap_and_stack/main.cpp @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2016-2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(TARGET_CORTEX_A) +　 #error [NOT_SUPPORTED] This function not supported for this target +#endif + +#include +#include +#include + +#include "mbed.h" +#include "cmsis.h" +#include "greentea-client/test_env.h" +#include "utest/utest.h" +#include "unity/unity.h" + +using utest::v1::Case; + +static const int test_timeout = 30; + + +// Amount to malloc for each iteration +#define MALLOC_TEST_SIZE 256 +// Malloc fill pattern +#define MALLOC_FILL 0x55 + +extern uint32_t mbed_heap_start; +extern uint32_t mbed_heap_size; +extern uint32_t mbed_stack_isr_start; +extern uint32_t mbed_stack_isr_size; + + +struct linked_list { + linked_list * next; + uint8_t data[MALLOC_TEST_SIZE]; +}; + + + +/* TODO: add memory layout test. + * + * The test was skipped for now since not all devices seems to comply with Mbed OS memory. + * + * @note Mbed OS memory model: https://os.mbed.com/docs/latest/reference/memory.html + * + */ + + +/* + * Return true if addr is in range [start:start+size) + */ +static bool inrange(uint32_t addr, uint32_t start, uint32_t size) +{ + return (addr >= start) && (addr < (start + size)); +} + +/* + * Return true if [addr:addr+size] is inside [start:start+len] + */ +static bool rangeinrange(uint32_t addr, uint32_t size, uint32_t start, uint32_t len) +{ + if ((addr + size) > (start + len)) { + return false; + } + if (addr < start) { + return false; + } + return true; +} + +/* + * Return true if the region is filled only with the specified value + */ +static bool valid_fill(uint8_t * data, uint32_t size, uint8_t fill) +{ + for (uint32_t i = 0; i < size; i++) { + if (data[i] != fill) { + return false; + } + } + return true; +} + +static void allocate_and_fill_heap(linked_list *&head) +{ + linked_list *current; + + current = (linked_list*) malloc(sizeof(linked_list)); + TEST_ASSERT_NOT_NULL(current); + + current->next = NULL; + memset((void*) current->data, MALLOC_FILL, sizeof(current->data)); + + // Allocate until malloc returns NULL + head = current; + while (true) { + + // Allocate + linked_list *temp = (linked_list*) malloc(sizeof(linked_list)); + + if (NULL == temp) { + break; + } + bool result = rangeinrange((uint32_t) temp, sizeof(linked_list), mbed_heap_start, mbed_heap_size); + + TEST_ASSERT_TRUE_MESSAGE(result, "Memory allocation out of range"); + + // Init + temp->next = NULL; + memset((void*) temp->data, MALLOC_FILL, sizeof(current->data)); + + // Add to list + current->next = temp; + current = temp; + } +} + +static void check_and_free_heap(linked_list *head, uint32_t &max_allocation_size) +{ + uint32_t total_size = 0; + linked_list * current = head; + + while (current != NULL) { + total_size += sizeof(linked_list); + bool result = valid_fill(current->data, sizeof(current->data), MALLOC_FILL); + + TEST_ASSERT_TRUE_MESSAGE(result, "Memory fill check failed"); + + linked_list * next = current->next; + free(current); + current = next; + } + + max_allocation_size = total_size; +} + +/** Test heap allocation + + Given a heap + When memory is allocated from heap + Then the memory is within heap boundary + + */ +void test_heap_in_range(void) +{ + char *initial_heap; + + // Sanity check malloc + initial_heap = (char*) malloc(1); + TEST_ASSERT_NOT_NULL(initial_heap); + + bool result = inrange((uint32_t) initial_heap, mbed_heap_start, mbed_heap_size); + + TEST_ASSERT_TRUE_MESSAGE(result, "Heap in wrong location"); + free(initial_heap); +} + +/** Test for Main thread stack + + Given a Main thread and its stack + When check Main thread stack pointer + Then the SP is within Main stack boundary + */ +void test_main_stack_in_range(void) +{ + os_thread_t *thread = (os_thread_t*) osThreadGetId(); + + uint32_t psp = __get_PSP(); + uint8_t *stack_mem = (uint8_t*) thread->stack_mem; + uint32_t stack_size = thread->stack_size; + + // PSP stack should be somewhere in the middle + bool result = inrange(psp, (uint32_t) stack_mem, stack_size); + + TEST_ASSERT_TRUE_MESSAGE(result, "Main stack in wrong location"); +} + +/** Test for Scheduler/ISR thread stack + + Given a Scheduler/ISR thread and its stack + When check Scheduler/ISR thread stack pointer + Then the SP is within Scheduler/ISR stack boundary + */ +void test_isr_stack_in_range(void) +{ + // MSP stack should be very near end (test using within 128 bytes) + uint32_t msp = __get_MSP(); + bool result = inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 128, 128); + + TEST_ASSERT_TRUE_MESSAGE(result, "Interrupt stack in wrong location"); +} + +/** Test full heap allocation + + Given a heap and linked_list data structure + When linked_list is filled till run out of heap memory + Then the memory is properly initialised and freed + */ +void test_heap_allocation_free(void) +{ + linked_list *head = NULL; + uint32_t max_allocation_size = 0; + + // Fully allocate the heap and stack + allocate_and_fill_heap(head); + + check_and_free_heap(head, max_allocation_size); + + // Force a task switch so a stack check is performed + Thread::wait(10); + + printf("Total size dynamically allocated: %luB\n", max_allocation_size); +} + + +// Test cases +Case cases[] = { + Case("Test heap in range", test_heap_in_range), + Case("Test main stack in range", test_main_stack_in_range), + Case("Test isr stack in range", test_isr_stack_in_range), + Case("Test heap allocation and free", test_heap_allocation_free) +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(test_timeout, "default_auto"); + return utest::v1::greentea_test_setup_handler(number_of_cases); +} + +utest::v1::Specification specification(greentea_test_setup, cases); + +int main() +{ + return !utest::v1::Harness::run(specification); +} diff --git a/TESTS/mbedmicro-rtos-mbed/isr/main.cpp b/TESTS/mbedmicro-rtos-mbed/isr/main.cpp deleted file mode 100644 index 1ba963f37d2..00000000000 --- a/TESTS/mbedmicro-rtos-mbed/isr/main.cpp +++ /dev/null @@ -1,77 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed.h" -#include "greentea-client/test_env.h" -#include "rtos.h" - -#if defined(MBED_RTOS_SINGLE_THREAD) - #error [NOT_SUPPORTED] test not supported -#endif - -#define QUEUE_SIZE 5 -#define THREAD_DELAY 250 -#define QUEUE_PUT_ISR_VALUE 128 -#define QUEUE_PUT_THREAD_VALUE 127 - -#define TEST_STACK_SIZE 512 - -Queue queue; - -DigitalOut myled(LED1); - -void queue_isr() { - - queue.put((uint32_t*)QUEUE_PUT_ISR_VALUE); - myled = !myled; -} - -void queue_thread() { - while (true) { - queue.put((uint32_t*)QUEUE_PUT_THREAD_VALUE); - Thread::wait(THREAD_DELAY); - } -} - -int main (void) { - GREENTEA_SETUP(20, "default_auto"); - - Thread thread(osPriorityNormal, TEST_STACK_SIZE); - thread.start(queue_thread); - Ticker ticker; - ticker.attach(queue_isr, 1.0); - int isr_puts_counter = 0; - bool result = true; - - while (true) { - osEvent evt = queue.get(); - if (evt.status != osEventMessage) { - printf("QUEUE_GET: FAIL\r\n"); - result = false; - break; - } else { - printf("QUEUE_GET: Value(%u) ... [OK]\r\n", evt.value.v); - if (evt.value.v == QUEUE_PUT_ISR_VALUE) { - isr_puts_counter++; - } - if (isr_puts_counter >= QUEUE_SIZE) { - break; - } - } - } - - GREENTEA_TESTSUITE_RESULT(result); - return 0; -} diff --git a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp index 3332de41e10..6c9aa96d1fb 100644 --- a/TESTS/mbedmicro-rtos-mbed/mail/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/mail/main.cpp @@ -25,7 +25,7 @@ using namespace utest::v1; -#define THREAD_STACK_SIZE 384 /* larger stack cause out of memory on some 16kB RAM boards in multi thread test*/ +#define THREAD_STACK_SIZE 320 /* larger stack cause out of heap memory on some 16kB RAM boards in multi thread test*/ #define QUEUE_SIZE 16 #define THREAD_1_ID 1 #define THREAD_2_ID 2 @@ -454,6 +454,43 @@ void test_calloc() TEST_ASSERT_EQUAL(0, *mail); } +/** Test mail empty + + Given a mail of uint32_t data + before data is inserted the mail should be empty + after data is inserted the mail shouldn't be empty + */ +void test_mail_empty() +{ + Mail m; + + mail_t *mail = m.alloc(); + + TEST_ASSERT_EQUAL(true, m.empty()); + + m.put(mail); + + TEST_ASSERT_EQUAL(false, m.empty()); +} + +/** Test mail empty + + Given a mail of uint32_t data with size of 1 + before data is inserted the mail shouldn't be full + after data is inserted the mail should be full + */ +void test_mail_full() +{ + Mail m; + + mail_t *mail = m.alloc(); + + TEST_ASSERT_EQUAL(false, m.full()); + + m.put(mail); + + TEST_ASSERT_EQUAL(true, m.full()); +} utest::v1::status_t test_setup(const size_t number_of_cases) { @@ -475,7 +512,9 @@ Case cases[] = { Case("Test invalid message free", test_free_wrong), Case("Test message send/receive single thread and order", test_single_thread_order), Case("Test message send/receive multi-thread and per thread order", test_multi_thread_order), - Case("Test message send/receive multi-thread, multi-Mail and per thread order", test_multi_thread_multi_mail_order) + Case("Test message send/receive multi-thread, multi-Mail and per thread order", test_multi_thread_multi_mail_order), + Case("Test mail empty", test_mail_empty), + Case("Test mail full", test_mail_full) }; Specification specification(test_setup, cases); diff --git a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp index 8c4cae324f3..2b685783117 100644 --- a/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/malloc/main.cpp @@ -14,14 +14,22 @@ * limitations under the License. */ #include "mbed.h" -#include "test_env.h" -#include "rtos.h" +#include "greentea-client/test_env.h" +#include "utest/utest.h" +#include "unity/unity.h" + #if defined(MBED_RTOS_SINGLE_THREAD) #error [NOT_SUPPORTED] test not supported #endif -#define NUM_THREADS 5 +using utest::v1::Case; + +extern uint32_t mbed_heap_size; +static const int test_timeout = 25; +volatile bool thread_should_continue = true; +#define NUM_THREADS 4 +#define THREAD_MALLOC_SIZE 100 #if defined(__CORTEX_A9) #define THREAD_STACK_SIZE DEFAULT_STACK_SIZE @@ -29,60 +37,138 @@ #define THREAD_STACK_SIZE 256 #endif -DigitalOut led1(LED1); -volatile bool should_exit = false; -volatile bool allocation_failure = false; void task_using_malloc(void) { - void* data; - while (1) { + void *data = NULL; + + while (thread_should_continue) { // Repeatedly allocate and free memory - data = malloc(100); - if (data != NULL) { - memset(data, 0, 100); - } else { - allocation_failure = true; - } - free(data); + data = malloc(THREAD_MALLOC_SIZE); + TEST_ASSERT_NOT_NULL(data); - if (should_exit) { - return; - } + // test whole allocated memory + memset(data, 0, THREAD_MALLOC_SIZE); + + free(data); } } -int main() +/** Test for multithreaded heap allocations + + Given multiple threads are started in parallel + When each of the threads allocate memory + Then the memory allocation succeed and @a malloc return valid memory + */ +void test_multithread_allocation(void) { + // static stack for threads to reduce heap usage on devices with small RAM + // and eliminate run out of heap memory problem + uint8_t stack[NUM_THREADS][THREAD_STACK_SIZE]; + + bool thread_alloc_failure = false; Thread *thread_list[NUM_THREADS]; - int test_time = 15; - GREENTEA_SETUP(20, "default_auto"); + int test_time = 20; // Allocate threads for the test for (int i = 0; i < NUM_THREADS; i++) { - thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE); + thread_list[i] = new Thread(osPriorityNormal, THREAD_STACK_SIZE, stack[i]); if (NULL == thread_list[i]) { - allocation_failure = true; + thread_alloc_failure = true; + } else { + thread_list[i]->start(task_using_malloc); } - thread_list[i]->start(task_using_malloc); } // Give the test time to run - while (test_time) { - led1 = !led1; + while (test_time--) { Thread::wait(1000); - test_time--; } // Join and delete all threads - should_exit = 1; + thread_should_continue = false; for (int i = 0; i < NUM_THREADS; i++) { - if (NULL == thread_list[i]) { - continue; + if (NULL != thread_list[i]) { + thread_list[i]->join(); + delete thread_list[i]; + thread_list[i] = NULL; } - thread_list[i]->join(); - delete thread_list[i]; } + TEST_ASSERT_FALSE(thread_alloc_failure); +} + +/** Test for large heap allocation + + Given a heap of size mbed_heap_size + When try to allocate memory of size mbed_heap_size/5 (20% of whole heap) + Then the memory is allocated and @a malloc return valid memory + */ +void test_big_allocation(void) +{ + const uint32_t alloc_size = mbed_heap_size / 5; + void *data = NULL; + + data = malloc(alloc_size); + TEST_ASSERT_NOT_NULL(data); + + // test whole allocated memory + memset(data, 0, alloc_size); + + free(data); +} + +/** Test if allocation of zero size does not cause any undefined behaviour + + Given a heap + When try to allocate memory of size 0 + Then the return value of @a malloc depends on the particular library implementation + (NULL or smallest possible allocation) and no undefined behaviour happens + + @note If allocation size is zero, the return value depends on the particular library implementation + (it may or may not be a null pointer), but the returned pointer shall not be dereferenced + */ +void test_zero_allocation(void) +{ + void *data = NULL; + + data = malloc(0); + if(data != NULL) { + free(data); + } + TEST_ASSERT_MESSAGE(true, "malloc(0) succeed - no undefined behaviour happens"); +} + +/** Test if free on NULL pointer does not cause any undefined behaviour - GREENTEA_TESTSUITE_RESULT(!allocation_failure); + Given a NULL pointer + When try to free it + Then the function @a free does nothing and no undefined behaviour happens + */ +void test_null_free(void) +{ + void *data = NULL; + free(data); + + TEST_ASSERT_MESSAGE(true, "free(NULL) succeed - no undefined behaviour happens"); +} + +// Test cases +Case cases[] = { + Case("Test 0 size allocation", test_zero_allocation), + Case("Test NULL pointer free", test_null_free), + Case("Test multithreaded allocations", test_multithread_allocation), + Case("Test large allocation", test_big_allocation) +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(test_timeout, "timing_drift_auto"); + return utest::v1::greentea_test_setup_handler(number_of_cases); +} + +utest::v1::Specification specification(greentea_test_setup, cases); + +int main() +{ + return !utest::v1::Harness::run(specification); } diff --git a/TESTS/mbedmicro-rtos-mbed/queue/main.cpp b/TESTS/mbedmicro-rtos-mbed/queue/main.cpp index d275784dbda..81fe8177bdf 100644 --- a/TESTS/mbedmicro-rtos-mbed/queue/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/queue/main.cpp @@ -282,6 +282,40 @@ void test_msg_prio() TEST_ASSERT_EQUAL(TEST_UINT_MSG, evt.value.v); } +/** Test queue empty + + Given a queue of uint32_t data + before data is inserted the queue should be empty + after data is inserted the queue shouldn't be empty + */ +void test_queue_empty() +{ + Queue q; + + TEST_ASSERT_EQUAL(true, q.empty()); + + q.put((uint32_t*) TEST_UINT_MSG, TEST_TIMEOUT, 1); + + TEST_ASSERT_EQUAL(false, q.empty()); +} + +/** Test queue empty + + Given a queue of uint32_t data with size of 1 + before data is inserted the queue shouldn't be full + after data is inserted the queue should be full + */ +void test_queue_full() +{ + Queue q; + + TEST_ASSERT_EQUAL(false, q.full()); + + q.put((uint32_t*) TEST_UINT_MSG, TEST_TIMEOUT, 1); + + TEST_ASSERT_EQUAL(true, q.full()); +} + utest::v1::status_t test_setup(const size_t number_of_cases) { GREENTEA_SETUP(5, "default_auto"); @@ -299,7 +333,9 @@ Case cases[] = { Case("Test put full timeout", test_put_full_timeout), Case("Test put full wait forever", test_put_full_waitforever), Case("Test message ordering", test_msg_order), - Case("Test message priority", test_msg_prio) + Case("Test message priority", test_msg_prio), + Case("Test queue empty", test_queue_empty), + Case("Test queue full", test_queue_full) }; Specification specification(test_setup, cases); diff --git a/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp new file mode 100644 index 00000000000..694ea04bf3a --- /dev/null +++ b/TESTS/mbedmicro-rtos-mbed/rtostimer/main.cpp @@ -0,0 +1,349 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "rtos.h" + +using namespace utest::v1; + +#define DELAY_MS 50 +#define DELTA_MS 5 +#define RESTART_DELAY_MS 10 +#define DELAY2_MS 30 + +#if RESTART_DELAY_MS >= DELAY_MS +#error invalid RESTART_DELAY_MS value +#endif + +class Stopwatch: public Timer { +private: + Semaphore _sem; + +public: + Stopwatch() : + Timer(), _sem(1) + { + } + + ~Stopwatch() + { + } + + void start(void) + { + _sem.wait(0); + Timer::start(); + } + + void stop(void) + { + Timer::stop(); + _sem.release(); + } + + int32_t wait_until_stopped(uint32_t millisec = osWaitForever) + { + core_util_critical_section_enter(); + int running = _running; + core_util_critical_section_exit(); + if (!running) { + return 1; + } + return _sem.wait(millisec); + } +}; + +void sem_callback(Semaphore *sem) +{ + sem->release(); +} + +/* In order to successfully run this test suite when compiled with --profile=debug + * error() has to be redefined as noop. + * + * RtosTimer calls RTX API which uses Event Recorder functionality. When compiled + * with MBED_TRAP_ERRORS_ENABLED=1 (set in debug profile) EvrRtxTimerError() calls error() + * which aborts test program. + */ +#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED +void error(const char* format, ...) +{ + (void) format; +} +#endif + +/** Test one-shot not restarted when elapsed + * + * Given a one-shot RtosTimer + * When the timer is started + * and given time elapses + * Then timer stops + * and elapsed time matches given delay + * and timer stays stopped + */ +void test_oneshot_not_restarted() +{ + Stopwatch stopwatch; + RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerOnce); + + stopwatch.start(); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); + + int32_t slots = stopwatch.wait_until_stopped(); + TEST_ASSERT_EQUAL(1, slots); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, stopwatch.read_ms()); + stopwatch.start(); + + slots = stopwatch.wait_until_stopped(DELAY_MS + DELTA_MS); + TEST_ASSERT_EQUAL(0, slots); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/** Test periodic repeats continuously + * + * Given a periodic RtosTimer + * When timer is started + * and given time elapses + * Then timer repeats its operation + * When timer is stopped + * Then timer stops operation + */ +void test_periodic_repeats() +{ + Stopwatch stopwatch; + RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerPeriodic); + + stopwatch.start(); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); + + int32_t slots = stopwatch.wait_until_stopped(); + int t1 = stopwatch.read_ms(); + stopwatch.reset(); + stopwatch.start(); + TEST_ASSERT_EQUAL(1, slots); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, t1); + + slots = stopwatch.wait_until_stopped(); + TEST_ASSERT_EQUAL(1, slots); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY_MS, stopwatch.read_ms()); + stopwatch.start(); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osOK, status); + + slots = stopwatch.wait_until_stopped(DELAY_MS + DELTA_MS); + TEST_ASSERT_EQUAL(0, slots); + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/** Test timer can be started again + * + * Given a one-shot Rtosimer + * When the timer is started + * and given time elapses + * Then timer stops + * When the timer is started again + * and given time elapses + * Then timer stops again + */ +void test_start_again() +{ + Semaphore sem(0, 1); + RtosTimer rtostimer(mbed::callback(sem_callback, &sem), osTimerOnce); + + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); + + int32_t slots = sem.wait(DELAY_MS + DELTA_MS); + TEST_ASSERT_EQUAL(1, slots); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); + + status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); + + slots = sem.wait(DELAY_MS + DELTA_MS); + TEST_ASSERT_EQUAL(1, slots); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/** Test timer restart updates delay + * + * Given a one-shot RtosTimer + * When the timer is started + * and @a start is called again with a different delay before given time elapses + * and updated delay elapses + * Then timer stops + * and time elapsed since the second @a start call matches updated delay + */ +void test_restart_updates_delay() +{ + Stopwatch stopwatch; + RtosTimer rtostimer(mbed::callback(&stopwatch, &Stopwatch::stop), osTimerOnce); + + stopwatch.start(); + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); + + int32_t slots = stopwatch.wait_until_stopped(RESTART_DELAY_MS); + TEST_ASSERT_EQUAL(0, slots); + + stopwatch.reset(); + stopwatch.start(); + status = rtostimer.start(DELAY2_MS); + TEST_ASSERT_EQUAL(osOK, status); + + slots = stopwatch.wait_until_stopped(); + TEST_ASSERT_EQUAL(1, slots); + TEST_ASSERT_INT_WITHIN(DELTA_MS, DELAY2_MS, stopwatch.read_ms()); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/** Test timer is created in stopped state + * + * Given a one-shot RtosTimer + * When the timer has not been started + * Then the timer is stopped + */ +void test_created_stopped() +{ + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); + osStatus status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/** Test one-shot can be stopped + * + * Given a one-shot RtosTimer + * When the timer is started + * and timer is stopped while still running + * Then timer stops operation + */ +void test_stop() +{ + Semaphore sem(0, 1); + RtosTimer rtostimer(mbed::callback(sem_callback, &sem), osTimerOnce); + + osStatus status = rtostimer.start(DELAY_MS); + TEST_ASSERT_EQUAL(osOK, status); + + int32_t slots = sem.wait(RESTART_DELAY_MS); + TEST_ASSERT_EQUAL(0, slots); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osOK, status); + + slots = sem.wait(DELAY_MS + DELTA_MS); + TEST_ASSERT_EQUAL(0, slots); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +/** Test timer started with infinite delay + * + * Given a one-shot RtosTimer + * When the timer is started with @a osWaitForever delay + * Then @a start return status is @a osOK + */ +void test_wait_forever() +{ + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); + + osStatus status = rtostimer.start(osWaitForever); + TEST_ASSERT_EQUAL(osOK, status); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osOK, status); +} + +/** Test timer started with zero delay + * + * Given a one-shot RtosTimer + * When the timer is started with 0 delay + * Then @a start return status is @a osErrorParameter + */ +void test_no_wait() +{ + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); + + osStatus status = rtostimer.start(0); + TEST_ASSERT_EQUAL(osErrorParameter, status); + + status = rtostimer.stop(); + TEST_ASSERT_EQUAL(osErrorResource, status); +} + +void rtostimer_isr_call(RtosTimer *rtostimer) +{ + osStatus status = rtostimer->start(DELAY_MS); + TEST_ASSERT_EQUAL(osErrorISR, status); + + status = rtostimer->stop(); + TEST_ASSERT_EQUAL(osErrorISR, status); +} + +/** Test timer method calls from an ISR fail + * + * Given a one-shot RtosTimer + * When a timer method is called from an ISR + * Then method return status is @a osErrorISR + */ +void test_isr_calls_fail() +{ + RtosTimer rtostimer(mbed::callback(sem_callback, (Semaphore *) NULL), osTimerOnce); + + Ticker ticker; + ticker.attach(mbed::callback(rtostimer_isr_call, &rtostimer), (float) DELAY_MS / 1000.0); + + wait_ms(DELAY_MS + DELTA_MS); +} + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(5, "default_auto"); + return verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("One-shot not restarted when elapsed", test_oneshot_not_restarted), + Case("Periodic repeats continuously", test_periodic_repeats), + Case("Stopped timer can be started again", test_start_again), + Case("Restart changes timeout", test_restart_updates_delay), + Case("Timer can be stopped", test_stop), + Case("Timer is created in stopped state", test_created_stopped), + Case("Timer started with infinite delay", test_wait_forever), + Case("Timer started with zero delay", test_no_wait), + Case("Calls from ISR fail", test_isr_calls_fail) +}; + +Specification specification(test_setup, cases); + +int main() +{ + return !Harness::run(specification); +} diff --git a/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp b/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp index 691589d0e83..ce211752080 100644 --- a/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/semaphore/main.cpp @@ -30,7 +30,7 @@ using namespace utest::v1; #define SEM_CHANGES 100 #define SHORT_WAIT 5 -#define THREAD_STACK_SIZE 512 +#define THREAD_STACK_SIZE 320 /* larger stack cause out of heap memory on some 16kB RAM boards in multi thread test*/ Semaphore two_slots(SEMAPHORE_SLOTS); diff --git a/TESTS/mbedmicro-rtos-mbed/signals/main.cpp b/TESTS/mbedmicro-rtos-mbed/signals/main.cpp index 195bfcf2c21..0809b14f175 100644 --- a/TESTS/mbedmicro-rtos-mbed/signals/main.cpp +++ b/TESTS/mbedmicro-rtos-mbed/signals/main.cpp @@ -15,49 +15,394 @@ */ #include "mbed.h" #include "greentea-client/test_env.h" -#include "rtos.h" +#include "utest/utest.h" +#include "unity/unity.h" + +using utest::v1::Case; + #if defined(MBED_RTOS_SINGLE_THREAD) #error [NOT_SUPPORTED] test not supported #endif -#define TEST_STACK_SIZE 512 +#define TEST_STACK_SIZE 512 +#define MAX_FLAG_POS 30 + +#define ALL_SIGNALS 0x7fffffff +#define NO_SIGNALS 0x0 +#define PROHIBITED_SIGNAL 0x80000000 +#define SIGNAL1 0x1 +#define SIGNAL2 0x2 +#define SIGNAL3 0x4 + +struct Sync { + Sync(Semaphore &parent, Semaphore &child): sem_parent(parent), sem_child(child) + {} + + Semaphore &sem_parent; + Semaphore &sem_child; +}; + + +/* In order to successfully run this test suite when compiled with --profile=debug + * error() has to be redefined as noop. + * + * ThreadFlags calls RTX API which uses Event Recorder functionality. When compiled + * with MBED_TRAP_ERRORS_ENABLED=1 (set in debug profile) EvrRtxEventFlagsError() calls error() + * which aborts test program. + */ +#if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED +void error(const char* format, ...) { + (void) format; +} +#endif + + +template +void run_signal_wait(void) +{ + osEvent ev = Thread::signal_wait(signals, timeout); + TEST_ASSERT_EQUAL(test_val, ev.status); +} + +template +void run_release_signal_wait(Semaphore *sem) +{ + sem->release(); + osEvent ev = Thread::signal_wait(signals, timeout); + TEST_ASSERT_EQUAL(test_val, ev.status); +} + +template +void run_release_wait_signal_wait(Sync *sync) +{ + sync->sem_parent.release(); + sync->sem_child.wait(); + osEvent ev = Thread::signal_wait(signals, timeout); + TEST_ASSERT_EQUAL(test_val, ev.status); +} + +template +void run_clear(void) +{ + int32_t ret = Thread::signal_clr(signals); + TEST_ASSERT_EQUAL(test_val, ret); +} + +template +void run_wait_clear(Sync *sync) +{ + sync->sem_parent.release(); + sync->sem_child.wait(); + int32_t ret = Thread::signal_clr(signals); + TEST_ASSERT_EQUAL(test_val, ret); +} + +template +void run_double_wait_clear(Sync *sync) +{ + int32_t ret; + + sync->sem_parent.release(); + sync->sem_child.wait(); + ret = Thread::signal_clr(signals1); + TEST_ASSERT_EQUAL(test_val1, ret); + + ret = Thread::signal_clr(signals2); + TEST_ASSERT_EQUAL(test_val2, ret); +} + +void run_loop_wait_clear(Sync *sync) +{ + int32_t signals = NO_SIGNALS; + for (int i = 0; i <= MAX_FLAG_POS; i++) { + int32_t signal = 1 << i; + signals |= signal; + sync->sem_child.wait(); + int32_t ret = Thread::signal_clr(NO_SIGNALS); + TEST_ASSERT_EQUAL(signals, ret); + sync->sem_parent.release(); + } +} + + +/** Validate that call signal_clr(NO_SIGNALS) doesn't change thread signals and return actual signals + + Given two threads A & B are started, B with all signals already set + When thread B calls @a signal_clr(NO_SIGNALS) + Then thread B @a signal_clr status should be ALL_SIGNALS indicating that thread B state is unchanged + */ +void test_clear_no_signals(void) +{ + Semaphore sem_parent(0, 1); + Semaphore sem_child(0, 1); + Sync sync(sem_parent, sem_child); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_double_wait_clear, &sync)); + sem_parent.wait(); + t.signal_set(ALL_SIGNALS); + sem_child.release(); + t.join(); +} + +/** Validate if any signals are set on just created thread + + Given the thread is running + When thread execute @a signal_clr(NO_SIGNALS) + Then thread @a signal_clr return status should be NO_SIGNALS(0) indicating no signals set + */ +void test_init_state(void) +{ + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_clear)); + t.join(); +} + +/** Validate all signals set in one shot + + Given two threads A & B are started + When thread A call @a signal_set(ALL_SIGNALS) with all possible signals + Then thread B @a signal_clr(NO_SIGNALS) status should be ALL_SIGNALS indicating all signals set correctly + */ +void test_set_all(void) +{ + int32_t ret; + Semaphore sem_parent(0, 1); + Semaphore sem_child(0, 1); + Sync sync(sem_parent, sem_child); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_wait_clear, &sync)); + + sem_parent.wait(); + ret = t.signal_set(ALL_SIGNALS); + TEST_ASSERT_EQUAL(ALL_SIGNALS, ret); + + sem_child.release(); + t.join(); +} + +/** Validate that call signal_set with prohibited signal doesn't change thread signals + + Given two threads A & B are started, B with all signals set + When thread A executes @a signal_set(PROHIBITED_SIGNAL) with prohibited signal + Then thread B @a signal_clr(NO_SIGNALS) status should be ALL_SIGNALS indicating that thread B signals are unchanged + + @note Each signal has up to 31 event flags 0x1, 0x2, 0x4, 0x8, ..., 0x40000000 + Most significant bit is reserved and thereby flag 0x80000000 is prohibited + */ +void test_set_prohibited(void) +{ + int32_t ret; + Semaphore sem_parent(0, 1); + Semaphore sem_child(0, 1); + Sync sync(sem_parent, sem_child); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_wait_clear, &sync)); + + sem_parent.wait(); + t.signal_set(ALL_SIGNALS); + + ret = t.signal_set(PROHIBITED_SIGNAL); + TEST_ASSERT_EQUAL(osErrorParameter, ret); + + sem_child.release(); + t.join(); +} + +/** Validate all signals clear in one shot -#define SIGNAL_SET_VALUE 0x01 -const int SIGNALS_TO_EMIT = 100; -const int SIGNAL_HANDLE_DELEY = 25; + Given two threads A & B are started, B with all signals set + When thread B execute @a signal_clr(ALL_SIGNALS) with all possible signals + Then thread B @a signal_clr(NO_SIGNALS) status should be NO_SIGNALS(0) indicating all signals cleared correctly + */ +void test_clear_all(void) +{ + Semaphore sem_parent(0, 1); + Semaphore sem_child(0, 1); + Sync sync(sem_parent, sem_child); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_double_wait_clear, &sync)); + sem_parent.wait(); + t.signal_set(ALL_SIGNALS); + sem_child.release(); + t.join(); +} + +/** Validate all signals set one by one in loop + + Given two threads A & B are started + When thread A executes @a signal_set(signal) in loop with all possible signals + */ +void test_set_all_loop(void) +{ + int32_t ret; + Semaphore sem_parent(0, 1); + Semaphore sem_child(0, 1); + Sync sync(sem_parent, sem_child); -DigitalOut led(LED1); -int signal_counter = 0; + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_loop_wait_clear, &sync)); -void led_thread() { - while (true) { - // Signal flags that are reported as event are automatically cleared. - Thread::signal_wait(SIGNAL_SET_VALUE); - led = !led; - signal_counter++; + int32_t signals = 0; + for (int i = 0; i <= MAX_FLAG_POS; i++) { + int32_t signal = 1 << i; + + ret = t.signal_set(signal); + signals |= signal; + TEST_ASSERT_EQUAL(signals, ret); + sem_child.release(); + sem_parent.wait(); } + t.join(); +} + +/** Validate signal_wait return status if timeout specified + + Given the thread is running + When thread executes @a signal_wait(signals, timeout) with specified signals and timeout + Then thread @a signal_wait status should be osEventTimeout indicating a timeout + thread @a signal_wait status should be osOK indicating 0[ms] timeout set + */ +template +void test_wait_timeout(void) +{ + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_signal_wait)); + t.join(); +} + +/** Validate that call of signal_wait return correctly when thread has all signals already set + + Given two threads A & B are started, B with all signals already set + When thread B executes @a signal_wait(ALL_SIGNALS, osWaitForever), + Then thread B @a signal_wait return immediately with status osEventSignal indicating all wait signals was already set + */ +void test_wait_all_already_set(void) +{ + Semaphore sem_parent(0, 1); + Semaphore sem_child(0, 1); + Sync sync(sem_parent, sem_child); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_release_wait_signal_wait, &sync)); + + sem_parent.wait(); + TEST_ASSERT_EQUAL(Thread::WaitingSemaphore, t.get_state()); + t.signal_set(ALL_SIGNALS); + sem_child.release(); + t.join(); } -int main (void) { - GREENTEA_SETUP(20, "default_auto"); +/** Validate if signal_wait return correctly when all signals set - Thread thread(osPriorityNormal, TEST_STACK_SIZE); - thread.start(led_thread); + Given two threads A & B are started and B waiting for a thread flag to be set + When thread A executes @a signal_set(ALL_SIGNALS) with all possible signals + Then thread B @a signal_wait status is osEventSignal indicating all wait signals was set + */ +void test_wait_all(void) +{ + Semaphore sem(0, 1); - bool result = false; + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_release_signal_wait, &sem)); - printf("Handling %d signals...\r\n", SIGNALS_TO_EMIT); + sem.wait(); + TEST_ASSERT_EQUAL(Thread::WaitingThreadFlag, t.get_state()); - while (true) { - Thread::wait(2 * SIGNAL_HANDLE_DELEY); - thread.signal_set(SIGNAL_SET_VALUE); - if (signal_counter == SIGNALS_TO_EMIT) { - printf("Handled %d signals\r\n", signal_counter); - result = true; - break; - } + t.signal_set(ALL_SIGNALS); + t.join(); +} + +/** Validate if signal_wait accumulate signals and return correctly when all signals set + + Given two threads A & B are started and B waiting for a thread signals to be set + When thread A executes @a signal_set setting all signals in loop + Then thread B @a signal_wait status is osEventSignal indicating that all wait signals was set + */ +void test_wait_all_loop(void) +{ + int32_t ret; + Semaphore sem(0, 1); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_release_signal_wait, &sem)); + + sem.wait(); + TEST_ASSERT_EQUAL(Thread::WaitingThreadFlag, t.get_state()); + + for (int i = 0; i < MAX_FLAG_POS; i++) { + int32_t signal = 1 << i; + ret = t.signal_set(signal); } - GREENTEA_TESTSUITE_RESULT(result); - return 0; + ret = t.signal_set(1 << MAX_FLAG_POS); + TEST_ASSERT_EQUAL(NO_SIGNALS, ret); + t.join(); +} + +/** Validate if setting same signal twice cause any unwanted behaviour + + Given two threads A & B are started and B waiting for a thread signals to be set + When thread A executes @a signal_set twice for the same signal + Then thread A @a signal_set status is current signal set + thread B @a signal_wait status is osEventSignal indicating that all wait signals was set + */ +void test_set_double(void) +{ + int32_t ret; + Semaphore sem(0, 1); + + Thread t(osPriorityNormal, TEST_STACK_SIZE); + t.start(callback(run_release_signal_wait, &sem)); + + sem.wait(); + TEST_ASSERT_EQUAL(Thread::WaitingThreadFlag, t.get_state()); + + ret = t.signal_set(SIGNAL1); + TEST_ASSERT_EQUAL(SIGNAL1, ret); + + ret = t.signal_set(SIGNAL2); + TEST_ASSERT_EQUAL(SIGNAL1 | SIGNAL2, ret); + + ret = t.signal_set(SIGNAL2); + TEST_ASSERT_EQUAL(SIGNAL1 | SIGNAL2, ret); + TEST_ASSERT_EQUAL(Thread::WaitingThreadFlag, t.get_state()); + + ret = t.signal_set(SIGNAL3); + TEST_ASSERT_EQUAL(NO_SIGNALS, ret); + t.join(); +} + + +utest::v1::status_t test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(10, "default_auto"); + return utest::v1::verbose_test_setup_handler(number_of_cases); +} + +Case cases[] = { + Case("Validate that call signal_clr(NO_SIGNALS) doesn't change thread signals and return actual signals", test_clear_no_signals), + Case("Validate if any signals are set on just created thread", test_init_state), + Case("Validate all signals set in one shot", test_set_all), + Case("Validate that call signal_set with prohibited signal doesn't change thread signals", test_set_prohibited), + Case("Validate all signals clear in one shot", test_clear_all), + Case("Validate all signals set one by one in loop", test_set_all_loop), + Case("Validate signal_wait return status if timeout specified: 0[ms] no signals", test_wait_timeout<0, 0, osOK>), + Case("Validate signal_wait return status if timeout specified: 0[ms] all signals", test_wait_timeout), + Case("Validate signal_wait return status if timeout specified: 1[ms] no signals", test_wait_timeout<0, 1, osEventTimeout>), + Case("Validate signal_wait return status if timeout specified: 1[ms] all signals", test_wait_timeout), + Case("Validate that call of signal_wait return correctly when thread has all signals already set", test_wait_all_already_set), + Case("Validate if signal_wait return correctly when all signals set", test_wait_all), + Case("Validate if signal_wait accumulate signals and return correctly when all signals set", test_wait_all_loop), + Case("Validate if setting same signal twice cause any unwanted behaviour", test_set_double) +}; + +utest::v1::Specification specification(test_setup, cases); + +int main() +{ + return !utest::v1::Harness::run(specification); } diff --git a/TESTS/netsocket/socket_sigio/main.cpp b/TESTS/netsocket/socket_sigio/main.cpp index dcce008a448..6c357abd4a6 100644 --- a/TESTS/netsocket/socket_sigio/main.cpp +++ b/TESTS/netsocket/socket_sigio/main.cpp @@ -105,7 +105,7 @@ void prep_buffer() { void test_socket_attach() { // Dispatch event queue Thread eventThread; - EventQueue queue; + EventQueue queue(4*EVENTS_EVENT_SIZE); eventThread.start(callback(&queue, &EventQueue::dispatch_forever)); printf("TCP client IP Address is %s\r\n", net->get_ip_address()); @@ -139,7 +139,7 @@ void cb_pass() { void test_socket_detach() { // Dispatch event queue Thread eventThread; - EventQueue queue; + EventQueue queue(4*EVENTS_EVENT_SIZE); eventThread.start(callback(&queue, &EventQueue::dispatch_forever)); printf("TCP client IP Address is %s\r\n", net->get_ip_address()); @@ -166,7 +166,7 @@ void test_socket_detach() { void test_socket_reattach() { // Dispatch event queue Thread eventThread; - EventQueue queue; + EventQueue queue(4*EVENTS_EVENT_SIZE); eventThread.start(callback(&queue, &EventQueue::dispatch_forever)); printf("TCP client IP Address is %s\r\n", net->get_ip_address()); diff --git a/TESTS/network/wifi/get_interface.cpp b/TESTS/network/wifi/get_interface.cpp new file mode 100644 index 00000000000..9bafab9b588 --- /dev/null +++ b/TESTS/network/wifi/get_interface.cpp @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" + +// Pick the correct driver based on mbed_app.json +#define INTERNAL 1 +#define WIFI_ESP8266 2 +#define X_NUCLEO_IDW01M1 3 + +#if MBED_CONF_APP_WIFI_DRIVER == INTERNAL + +#if TARGET_UBLOX_EVK_ODIN_W2 +#include "OdinWiFiInterface.h" +#define DRIVER OdinWiFiInterface + +#elif TARGET_REALTEK_RTL8195AM +#include "RTWInterface.h" +#define DRIVER RTWInterface +#else +#error [NOT_SUPPORTED] Unsupported Wifi driver +#endif + +#elif MBED_CONF_APP_WIFI_DRIVER == WIFI_ESP8266 +#include "ESP8266Interface.h" +#define DRIVER ESP8266Interface + +#elif MBED_CONF_APP_WIFI_DRIVER == X_NUCLEO_IDW01M1 +#include "SpwfSAInterface.h" +#define DRIVER SpwfSAInterface +#else +#error [NOT_SUPPORTED] Unsupported Wifi driver +#endif + +WiFiInterface *get_interface() +{ + static WiFiInterface *interface = NULL; + + if (interface) + delete interface; + +#if MBED_CONF_APP_WIFI_DRIVER == INTERNAL + interface = new DRIVER(); +#else + interface = new DRIVER(MBED_CONF_APP_WIFI_TX, MBED_CONF_APP_WIFI_RX); +#endif + return interface; +} diff --git a/TESTS/network/wifi/main.cpp b/TESTS/network/wifi/main.cpp index c242a8c291f..1245b11e2dd 100644 --- a/TESTS/network/wifi/main.cpp +++ b/TESTS/network/wifi/main.cpp @@ -1,196 +1,71 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 ARM Limited +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ -#include "utest/utest.h" -#include "unity/unity.h" -#include "greentea-client/test_env.h" - #include "mbed.h" - -#if TARGET_UBLOX_EVK_ODIN_W2 -#include "OdinWiFiInterface.h" -#else -#error [NOT_SUPPORTED] Only built in WiFi modules are supported at this time. +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +// Test for parameters +#if !defined(MBED_CONF_APP_AP_MAC_SECURE) || \ + !defined(MBED_CONF_APP_AP_MAC_UNSECURE) || \ + !defined(MBED_CONF_APP_MAX_SCAN_SIZE) || \ + !defined(MBED_CONF_APP_WIFI_CH_SECURE) || \ + !defined(MBED_CONF_APP_WIFI_CH_UNSECURE) || \ + !defined(MBED_CONF_APP_WIFI_DRIVER) || \ + !defined(MBED_CONF_APP_WIFI_PASSWORD) || \ + !defined(MBED_CONF_APP_WIFI_RX) || \ + !defined(MBED_CONF_APP_WIFI_SECURE_SSID) || \ + !defined(MBED_CONF_APP_WIFI_TX) || \ + !defined(MBED_CONF_APP_WIFI_UNSECURE_SSID) +#error [NOT_SUPPORTED] Requires parameters from mbed_app.json #endif using namespace utest::v1; -/** - * WiFi tests require following macros to be defined: - * - MBED_CONF_APP_WIFI_SSID - SSID of a network the test will try connecting to - * - MBED_CONF_APP_WIFI_PASSWORD - Passphrase that will be used to connecting to the network - * - WIFI_TEST_NETWORKS - List of network that presence will be asserted e.g. "net1", "net2", "net3" - */ -#if !defined(MBED_CONF_APP_WIFI_SSID) || !defined(MBED_CONF_APP_WIFI_PASSWORD) || !defined(MBED_CONF_APP_WIFI_NETWORKS) -#error [NOT_SUPPORTED] MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD and MBED_CONF_APP_WIFI_NETWORKS have to be defined for this test. -#endif - -const char *networks[] = {MBED_CONF_APP_WIFI_NETWORKS, NULL}; - -WiFiInterface *wifi; - -/* In normal circumstances the WiFi object could be global, but the delay introduced by WiFi initialization is an issue - for the tests. It causes Greentea to timeout on syncing with the board. To solve it we defer the actual object - creation till we actually need it. - */ -WiFiInterface *get_wifi() -{ - if (wifi == NULL) { - /* We don't really care about freeing this, as its lifetime is through the full test suit run. */ -#if TARGET_UBLOX_EVK_ODIN_W2 - wifi = new OdinWiFiInterface; -#endif - } - - return wifi; -} - -void check_wifi(const char *ssid, bool *net_stat) -{ - int i = 0; - while(networks[i]) { - if (strcmp(networks[i], ssid) == 0) { - net_stat[i] = true; - break; - } - i++; - } -} - -void wifi_scan() -{ - int count; - WiFiAccessPoint *aps; - const int net_len = sizeof(networks)/sizeof(networks[0]); - bool net_stat[net_len - 1]; - - memset(net_stat, 0, sizeof(net_stat)); - - count = get_wifi()->scan(NULL, 0); - TEST_ASSERT_MESSAGE(count >= 0, "WiFi interface returned error"); - TEST_ASSERT_MESSAGE(count > 0, "Scan result empty"); - - aps = new WiFiAccessPoint[count]; - count = get_wifi()->scan(aps, count); - for(int i = 0; i < count; i++) { - check_wifi(aps[i].get_ssid(), net_stat); - } - - delete[] aps; - - for (unsigned i = 0; i < sizeof(net_stat); i++) { - TEST_ASSERT_MESSAGE(net_stat[i] == true, "Not all required WiFi network detected"); - } -} - -void wifi_connect() -{ - int ret; - - ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2); - TEST_ASSERT_MESSAGE(ret == 0, "Connect failed"); - - ret = get_wifi()->disconnect(); - TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed"); -} - -void wifi_connect_scan() -{ - int ret; - int count; - WiFiAccessPoint *aps; - const int net_len = sizeof(networks)/sizeof(networks[0]); - bool net_stat[net_len - 1]; - - memset(net_stat, 0, sizeof(net_stat)); - - ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2); - TEST_ASSERT_MESSAGE(ret == 0, "Connect failed"); - - count = get_wifi()->scan(NULL, 0); - TEST_ASSERT_MESSAGE(count >= 0, "WiFi interface returned error"); - TEST_ASSERT_MESSAGE(count > 0, "Scan result empty"); - - aps = new WiFiAccessPoint[count]; - count = get_wifi()->scan(aps, count); - for(int i = 0; i < count; i++) { - check_wifi(aps[i].get_ssid(), net_stat); - } - - delete[] aps; - - ret = get_wifi()->disconnect(); - TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed"); - - for (unsigned i = 0; i < sizeof(net_stat); i++) { - TEST_ASSERT_MESSAGE(net_stat[i] == true, "Not all required WiFi network detected"); - } -} - -void wifi_http() -{ - TCPSocket socket; - int ret; - - ret = get_wifi()->connect(MBED_CONF_APP_WIFI_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA_WPA2); - TEST_ASSERT_MESSAGE(ret == 0, "Connect failed"); - - // Open a socket on the network interface, and create a TCP connection to www.arm.com - ret = socket.open(get_wifi()); - TEST_ASSERT_MESSAGE(ret == 0, "Socket open failed"); - ret = socket.connect("www.arm.com", 80); - TEST_ASSERT_MESSAGE(ret == 0, "Socket connect failed"); - - // Send a simple http request - char sbuffer[] = "GET / HTTP/1.1\r\nHost: www.arm.com\r\n\r\n"; - int scount = socket.send(sbuffer, sizeof sbuffer); - TEST_ASSERT_MESSAGE(scount >= 0, "Socket send failed"); - - // Recieve a simple http response and check if it's not empty - char rbuffer[64]; - int rcount = socket.recv(rbuffer, sizeof rbuffer); - TEST_ASSERT_MESSAGE(rcount >= 0, "Socket recv error"); - TEST_ASSERT_MESSAGE(rcount > 0, "No data received"); - - ret = socket.close(); - TEST_ASSERT_MESSAGE(ret == 0, "Socket close failed"); - - ret = get_wifi()->disconnect(); - TEST_ASSERT_MESSAGE(ret == 0, "Disconnect failed"); -} - -status_t greentea_failure_handler(const Case *const source, const failure_t reason) { - greentea_case_failure_abort_handler(source, reason); - return STATUS_CONTINUE; +utest::v1::status_t test_setup(const size_t number_of_cases) { + GREENTEA_SETUP(240, "default_auto"); + return verbose_test_setup_handler(number_of_cases); } +// Test cases Case cases[] = { - Case("Scan test", wifi_scan, greentea_failure_handler), - Case("Connect test", wifi_connect, greentea_failure_handler), - Case("Scan while connected test", wifi_connect_scan, greentea_failure_handler), - Case("HTTP test", wifi_http, greentea_failure_handler), + Case("WIFI-CONSTRUCTOR", wifi_constructor), + Case("WIFI-SET-CREDENTIAL", wifi_set_credential), + Case("WIFI-SET-CHANNEL", wifi_set_channel), + Case("WIFI-GET-RSSI", wifi_get_rssi), + Case("WIFI-CONNECT-PARAMS-NULL", wifi_connect_params_null), + Case("WIFI-CONNECT-PARAMS-VALID-UNSECURE", wifi_connect_params_valid_unsecure), + Case("WIFI-CONNECT-PARAMS-VALID-SECURE", wifi_connect_params_valid_secure), + Case("WIFI-CONNECT-PARAMS-CHANNEL", wifi_connect_params_channel), + Case("WIFI-CONNECT-PARAMS-CHANNEL-FAIL", wifi_connect_params_channel_fail), + Case("WIFI-CONNECT-NOCREDENTIALS", wifi_connect_nocredentials), + Case("WIFI-CONNECT", wifi_connect), + Case("WIFI-CONNECT-SECURE", wifi_connect_secure), + Case("WIFI-CONNECT-SECURE-FAIL", wifi_connect_secure_fail), + Case("WIFI-CONNECT-DISCONNECT-REPEAT", wifi_connect_disconnect_repeat), + Case("WIFI-SCAN-NULL", wifi_scan_null), + Case("WIFI-SCAN", wifi_scan), }; -status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(90, "default_auto"); - return greentea_test_setup_handler(number_of_cases); -} - +Specification specification(test_setup, cases); +// Entry point into the tests int main() { - Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); - Harness::run(specification); + return !Harness::run(specification); } diff --git a/TESTS/network/wifi/template_mbed_app.txt b/TESTS/network/wifi/template_mbed_app.txt index 77a7af0cf95..ddab934545a 100644 --- a/TESTS/network/wifi/template_mbed_app.txt +++ b/TESTS/network/wifi/template_mbed_app.txt @@ -1,21 +1,48 @@ { "config": { - "wifi-ssid": { - "help": "WiFi SSID", - "value": "\"SSID\"" + "wifi-secure-ssid": { + "help": "WiFi SSID for WPA2 secured network", + "value": "\"SSID-SECURE\"" + }, + "wifi-unsecure-ssid": { + "help": "WiFi SSID for unsecure netwrok", + "value": "\"SSID-UNSECURE\"" }, "wifi-password": { "help": "WiFi Password", - "value": "\"PASS\"" + "value": "\"PASSWORD\"" }, - "wifi-networks": { - "help": "WiFi SSIDs which presence will be asserted in the test", - "value": "\"SSID1\",\"SSID2\",\"SSID3\"" - } - }, - "target_overrides": { - "UBLOX_EVK_ODIN_W2": { - "target.device_has": ["EMAC"] + "wifi-ch-secure": { + "help": "Channel number of secure SSID", + "value": 1 + }, + "wifi-ch-unsecure": { + "help": "Channel number of unsecure SSID", + "value": 2 + }, + "wifi-driver": { + "help": "Wifi driver to use, valid values are INTERNAL, WIFI_ESP8266 and X_NUCLEO_IDW01M1", + "value": "INTERNAL" + }, + "wifi-tx": { + "help": "TX pin for serial connection to external device", + "value": "D1" + }, + "wifi-rx": { + "help": "RX pin for serial connection to external device", + "value": "D0" + }, + "ap-mac-secure": { + "help": "BSSID of secure AP in form of AA:BB:CC:DD:EE:FF", + "value": "\"AA:AA:AA:AA:AA:AA\"" + }, + "ap-mac-unsecure": { + "help": "BSSID of unsecure AP in form of \"AA:BB:CC:DD:EE:FF\"", + "value": "\"BB:BB:BB:BB:BB:BB\"" + }, + "max-scan-size": { + "help": "How many networks may appear in Wifi scan result", + "value": 10 } } } diff --git a/TESTS/network/wifi/wifi-constructor.cpp b/TESTS/network/wifi/wifi-constructor.cpp new file mode 100644 index 00000000000..3fa80ff5cbb --- /dev/null +++ b/TESTS/network/wifi/wifi-constructor.cpp @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_constructor() { + WiFiInterface *wifi = get_interface(); + TEST_ASSERT(wifi); +} diff --git a/TESTS/network/wifi/wifi_connect.cpp b/TESTS/network/wifi/wifi_connect.cpp new file mode 100644 index 00000000000..c244e0247fc --- /dev/null +++ b/TESTS/network/wifi/wifi_connect.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect(void) +{ + WiFiInterface *wifi = get_interface(); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL)); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect()); +} diff --git a/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp new file mode 100644 index 00000000000..9ee73fc5587 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_disconnect_repeat.cpp @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_disconnect_repeat(void) +{ + WiFiInterface *wifi = get_interface(); + nsapi_error_t error; + + error = wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL); + TEST_ASSERT(error == NSAPI_ERROR_OK); + + for(int i=0; i<10; i++) { + error = wifi->connect(); + TEST_ASSERT(error == NSAPI_ERROR_OK); + error = wifi->disconnect(); + TEST_ASSERT(error == NSAPI_ERROR_OK); + } +} diff --git a/TESTS/network/wifi/wifi_connect_nocredentials.cpp b/TESTS/network/wifi/wifi_connect_nocredentials.cpp new file mode 100644 index 00000000000..c930d7d0a95 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_nocredentials.cpp @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_nocredentials(void) +{ + WiFiInterface *wifi = get_interface(); + nsapi_error_t error; + error = wifi->connect(); + wifi->disconnect(); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); +} diff --git a/TESTS/network/wifi/wifi_connect_params_channel.cpp b/TESTS/network/wifi/wifi_connect_params_channel.cpp new file mode 100644 index 00000000000..08c34a9c541 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_params_channel.cpp @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_params_channel(void) +{ + WiFiInterface *wifi = get_interface(); + + if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) { + TEST_IGNORE_MESSAGE("set_channel() not supported"); + return; + } + + nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2, MBED_CONF_APP_WIFI_CH_SECURE); + TEST_ASSERT_EQUAL(NSAPI_ERROR_OK, error); +} + diff --git a/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp b/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp new file mode 100644 index 00000000000..f1d56d22496 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_params_channel_fail.cpp @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_params_channel_fail(void) +{ + WiFiInterface *wifi = get_interface(); + + if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) { + TEST_IGNORE_MESSAGE("set_channel() not supported"); + return; + } + + nsapi_error_t error = wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2, MBED_CONF_APP_WIFI_CH_UNSECURE); + TEST_ASSERT(error==NSAPI_ERROR_CONNECTION_TIMEOUT || error==NSAPI_ERROR_NO_CONNECTION); +} + diff --git a/TESTS/network/wifi/wifi_connect_params_null.cpp b/TESTS/network/wifi/wifi_connect_params_null.cpp new file mode 100644 index 00000000000..6a471bd6049 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_params_null.cpp @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_params_null(void) +{ + WiFiInterface *wifi = get_interface(); + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_PARAMETER, wifi->connect(NULL, NULL)); +} diff --git a/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp b/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp new file mode 100644 index 00000000000..0da25c67927 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_params_valid_secure.cpp @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_params_valid_secure(void) +{ + WiFiInterface *wifi = get_interface(); + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2)); +} diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug.h b/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp similarity index 60% rename from features/FEATURE_UVISOR/includes/uvisor/api/inc/debug.h rename to TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp index 22e4a24e001..e1540b24a8d 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug.h +++ b/TESTS/network/wifi/wifi_connect_params_valid_unsecure.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited, All Rights Reserved + * Copyright (c) 2017, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); you may @@ -14,19 +14,18 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef __UVISOR_API_DEBUG_H__ -#define __UVISOR_API_DEBUG_H__ -#include "api/inc/debug_exports.h" -#include "api/inc/uvisor_exports.h" +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" -UVISOR_EXTERN_C_BEGIN +using namespace utest::v1; -static UVISOR_FORCEINLINE void uvisor_debug_init(const TUvisorDebugDriver * const driver) +void wifi_connect_params_valid_unsecure(void) { - uvisor_api.debug_init(driver); + WiFiInterface *wifi = get_interface(); + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL)); } -UVISOR_EXTERN_C_END - -#endif /* __UVISOR_API_DEBUG_H__ */ diff --git a/TESTS/network/wifi/wifi_connect_secure.cpp b/TESTS/network/wifi/wifi_connect_secure.cpp new file mode 100644 index 00000000000..dce86f969fd --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_secure.cpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_secure(void) +{ + WiFiInterface *wifi = get_interface(); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, MBED_CONF_APP_WIFI_PASSWORD, NSAPI_SECURITY_WPA2)); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect()); +} + diff --git a/TESTS/network/wifi/wifi_connect_secure_fail.cpp b/TESTS/network/wifi/wifi_connect_secure_fail.cpp new file mode 100644 index 00000000000..7e55a290a87 --- /dev/null +++ b/TESTS/network/wifi/wifi_connect_secure_fail.cpp @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_connect_secure_fail(void) +{ + WiFiInterface *wifi = get_interface(); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_SECURE_SSID, "aaaaaaaa", NSAPI_SECURITY_WPA2)); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_AUTH_FAILURE, wifi->connect()); +} + diff --git a/TESTS/network/wifi/wifi_get_rssi.cpp b/TESTS/network/wifi/wifi_get_rssi.cpp new file mode 100644 index 00000000000..ac4338ff934 --- /dev/null +++ b/TESTS/network/wifi/wifi_get_rssi.cpp @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_get_rssi(void) +{ + WiFiInterface *wifi = get_interface(); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->set_credentials(MBED_CONF_APP_WIFI_UNSECURE_SSID, NULL)); + + TEST_ASSERT_EQUAL_INT8(0, wifi->get_rssi()); + + TEST_ASSERT_EQUAL_INT(NSAPI_ERROR_OK, wifi->connect()); + + TEST_ASSERT_INT8_WITHIN(-35, -65, wifi->get_rssi()); // -30 ... -100 +} + diff --git a/TESTS/network/wifi/wifi_scan.cpp b/TESTS/network/wifi/wifi_scan.cpp new file mode 100644 index 00000000000..d4722dd0d08 --- /dev/null +++ b/TESTS/network/wifi/wifi_scan.cpp @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" +#include + +using namespace utest::v1; + +void wifi_scan(void) +{ + WiFiInterface *wifi = get_interface(); + + WiFiAccessPoint ap[MBED_CONF_APP_MAX_SCAN_SIZE]; + + int size = wifi->scan(ap, MBED_CONF_APP_MAX_SCAN_SIZE); + TEST_ASSERT(size >= 2); + + bool secure_found = false; + bool unsecure_found = false; + + char secure_bssid[6]; + char unsecure_bssid[6]; + const char *coversion_string = "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx"; + TEST_ASSERT_EQUAL_INT_MESSAGE(6, sscanf(MBED_CONF_APP_AP_MAC_SECURE, coversion_string, &secure_bssid[0], &secure_bssid[1], &secure_bssid[2], &secure_bssid[3], &secure_bssid[4], &secure_bssid[5]), "Failed to convert ap-mac-secure from mbed_app.json"); + TEST_ASSERT_EQUAL_INT_MESSAGE(6, sscanf(MBED_CONF_APP_AP_MAC_UNSECURE, coversion_string, &unsecure_bssid[0], &unsecure_bssid[1], &unsecure_bssid[2], &unsecure_bssid[3], &unsecure_bssid[4], &unsecure_bssid[5]), "Failed to convert ap-mac-unsecure from mbed_app.json"); + + for (int i=0; iscan(NULL, 0) >= 2); +} + diff --git a/TESTS/network/wifi/wifi_set_channel.cpp b/TESTS/network/wifi/wifi_set_channel.cpp new file mode 100644 index 00000000000..ecb79150042 --- /dev/null +++ b/TESTS/network/wifi/wifi_set_channel.cpp @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" +#include + +using namespace utest::v1; + +void wifi_set_channel(void) +{ + bool is_2Ghz = false; + bool is_5Ghz = false; + + WiFiInterface *wifi = get_interface(); + + if (wifi->set_channel(1) == NSAPI_ERROR_UNSUPPORTED && wifi->set_channel(36) == NSAPI_ERROR_UNSUPPORTED) { + TEST_IGNORE_MESSAGE("set_channel() not supported"); + return; + } + + nsapi_error_t error; + error = wifi->set_channel(1); + if (error == NSAPI_ERROR_OK) { + is_2Ghz = true; + } + + error = wifi->set_channel(30); + if (error == NSAPI_ERROR_OK) { + is_5Ghz = true; + } + + TEST_ASSERT(is_2Ghz || is_5Ghz); + + if (is_2Ghz) { + error = wifi->set_channel(0); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + error = wifi->set_channel(1); + TEST_ASSERT(error == NSAPI_ERROR_OK); + error = wifi->set_channel(13); + TEST_ASSERT(error == NSAPI_ERROR_OK || error == NSAPI_ERROR_PARAMETER); + error = wifi->set_channel(15); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + } + + if (is_5Ghz) { + error = wifi->set_channel(30); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + error = wifi->set_channel(36); + TEST_ASSERT(error == NSAPI_ERROR_OK); + error = wifi->set_channel(169); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + } + +} + diff --git a/TESTS/network/wifi/wifi_set_credential.cpp b/TESTS/network/wifi/wifi_set_credential.cpp new file mode 100644 index 00000000000..78f5d604270 --- /dev/null +++ b/TESTS/network/wifi/wifi_set_credential.cpp @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017, ARM Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbed.h" +#include "greentea-client/test_env.h" +#include "unity.h" +#include "utest.h" +#include "wifi_tests.h" + +using namespace utest::v1; + +void wifi_set_credential(void) +{ + WiFiInterface *iface = get_interface(); + nsapi_error_t error; + + error = iface->set_credentials(NULL, NULL, NSAPI_SECURITY_NONE); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + + error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_NONE); + TEST_ASSERT(error == NSAPI_ERROR_OK); + + error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_WEP); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + + error = iface->set_credentials("OK", NULL, NSAPI_SECURITY_WPA_WPA2); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); + + error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA); + TEST_ASSERT(error == NSAPI_ERROR_OK); + + error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA2); + TEST_ASSERT(error == NSAPI_ERROR_OK); + + error = iface->set_credentials("OK", "12345678", NSAPI_SECURITY_WPA_WPA2); + TEST_ASSERT(error == NSAPI_ERROR_OK); + + error = iface->set_credentials("OK", "kUjd0PHHeAqaDoyfcDDEOvbyiVbYMpUHDukGoR6EJZnO5iLzWsfwiM9JQqOngni82", NSAPI_SECURITY_WPA2); + TEST_ASSERT(error == NSAPI_ERROR_PARAMETER); +} diff --git a/TESTS/network/wifi/wifi_tests.h b/TESTS/network/wifi/wifi_tests.h new file mode 100644 index 00000000000..1ef40ccc2de --- /dev/null +++ b/TESTS/network/wifi/wifi_tests.h @@ -0,0 +1,63 @@ +#ifndef WIFI_TESTS_H +#define WIFI_TESTS_H + +#include "WiFiInterface.h" + +/** Get WiFiInterface based on provided + * app_json. */ +WiFiInterface *get_interface(void); + +/* + * Test cases + */ + +/** Test that constructor of the driver works. */ +void wifi_constructor(void); + +/** This test case is to test whether the driver accepts valid credentials and reject ones that are not valid. */ +void wifi_set_credential(void); + +/** Test validity of WiFiInterface::set_channel(). */ +void wifi_set_channel(void); + +/** Test WiFiInterface::get_rssi() API. + * When connected, it should return valid RSSI value. When unconnected it should return 0. */ +void wifi_get_rssi(void); + +/** Test WiFiInterface::connect(ssid, pass, security, channel) with NULL parameters */ +void wifi_connect_params_null(void); + +/** Test WiFiInterface::connect(ssid, pass, security) with valid parameters for unsecure network */ +void wifi_connect_params_valid_unsecure(void); + +/** Test WiFiInterface::connect(ssid, pass, security) with valid parameters for secure network */ +void wifi_connect_params_valid_secure(void); + +/** Test WiFiInterface::connect(ssid, pass, security, channel) with valid parameters for secure network using channel specified. */ +void wifi_connect_params_channel(void); + +/** Test WiFiInterface::connect(ssid, pass, security, channel) with valid parameters for secure network using wrong channel number. */ +void wifi_connect_params_channel_fail(void); + +/** Test WiFiInterface::connect() without parameters. Use set_credentials() for setting parameters. */ +void wifi_connect(void); + +/** Test WiFiInterface::connect() without parameters. Don't set parameters with set_credentials() */ +void wifi_connect_nocredentials(void); + +/** Test WiFiInterface::connect() without parameters. Use secure settings for set_credentials. */ +void wifi_connect_secure(void); + +/** Test WiFiInterface::connect() failing with wrong password. */ +void wifi_connect_secure_fail(void); + +/** Test WiFiInterface::connect() - disconnect() repeatition works. */ +void wifi_connect_disconnect_repeat(void); + +/** Call WiFiInterface::scan() with null parameters to get number of networks available. */ +void wifi_scan_null(void); + +/** Call WiFiInterface::scan() with valid accesspoint list allocated */ +void wifi_scan(void); + +#endif //WIFI_TESTS_H diff --git a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h similarity index 59% rename from cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h rename to cmsis/TARGET_CORTEX_A/cmsis_armcc.h index 80f9dd95791..1b4ab2c321c 100644 --- a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armcc.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.00 - * @date 22. Feb 2017 + * @version V1.0.1 + * @date 07. Sep 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -36,68 +36,53 @@ /* CMSIS compiler specific defines */ #ifndef __ASM - #define __ASM __asm + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __forceinline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) #endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline +#ifndef __PACKED + #define __PACKED __attribute__((packed)) #endif -#ifndef __STATIC_ASM - #define __STATIC_ASM static __asm +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct #endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) #endif -#ifndef __USED - #define __USED __attribute__((used)) +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) #endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) #endif -#ifndef __UNALIGNED_UINT32 - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) #endif #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif - - -/* ########################### Core Function Access ########################### */ - -/** - \brief Get FPSCR - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) #endif -} - -/** - \brief Set FPSCR - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} /* ########################## Core Instruction Access ######################### */ /** @@ -209,7 +194,142 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in */ #define __CLZ __clz -/** \brief Get CPSR Register +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/* ########################### Core Function Access ########################### */ + +/** + \brief Get FPSCR (Floating Point Status/Control) + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + +/** + \brief Set FPSCR (Floating Point Status/Control) + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + +/** \brief Get CPSR (Current Program Status Register) \return CPSR Register value */ __STATIC_INLINE uint32_t __get_CPSR(void) @@ -219,7 +339,7 @@ __STATIC_INLINE uint32_t __get_CPSR(void) } -/** \brief Set CPSR Register +/** \brief Set CPSR (Current Program Status Register) \param [in] cpsr CPSR value to set */ __STATIC_INLINE void __set_CPSR(uint32_t cpsr) @@ -244,7 +364,16 @@ __STATIC_INLINE __ASM void __set_mode(uint32_t mode) { BX r1 } -/** \brief Set Stack Pointer +/** \brief Get Stack Pointer + \return Stack Pointer + */ +__STATIC_INLINE __ASM uint32_t __get_SP(void) +{ + MOV r0, sp + BX lr +} + +/** \brief Set Stack Pointer \param [in] stack Stack Pointer value to set */ __STATIC_INLINE __ASM void __set_SP(uint32_t stack) @@ -253,35 +382,41 @@ __STATIC_INLINE __ASM void __set_SP(uint32_t stack) BX lr } -/** \brief Set Process Stack Pointer - \param [in] topOfProcStack USR/SYS Stack Pointer value to set + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYSStack Pointer */ -__STATIC_INLINE __ASM void __set_PSP(uint32_t topOfProcStack) +__STATIC_INLINE __ASM uint32_t __get_SP_usr(void) { ARM PRESERVE8 - BIC R0, R0, #7 ;ensure stack is 8-byte aligned MRS R1, CPSR CPS #0x1F ;no effect in USR mode - MOV SP, R0 + MOV R0, SP MSR CPSR_c, R1 ;no effect in USR mode ISB BX LR } -/** \brief Set User Mode +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ -__STATIC_INLINE __ASM void __set_CPS_USR(void) +__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack) { ARM + PRESERVE8 - CPS #0x10 - BX LR + MRS R1, CPSR + CPS #0x1F ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR } -/** \brief Get FPEXC - \return Floating Point Exception Control register value +/** \brief Get FPEXC (Floating Point Exception Control Register) + \return Floating Point Exception Control Register value */ __STATIC_INLINE uint32_t __get_FPEXC(void) { @@ -293,7 +428,7 @@ __STATIC_INLINE uint32_t __get_FPEXC(void) #endif } -/** \brief Set FPEXC +/** \brief Set FPEXC (Floating Point Exception Control Register) \param [in] fpexc Floating Point Exception Control value to set */ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) @@ -304,243 +439,18 @@ __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) #endif } -/** \brief Get CPACR - \return Coprocessor Access Control register value - */ -__STATIC_INLINE uint32_t __get_CPACR(void) -{ - register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); - return __regCPACR; -} - -/** \brief Set CPACR - \param [in] cpacr Coprocessor Acccess Control value to set - */ -__STATIC_INLINE void __set_CPACR(uint32_t cpacr) -{ - register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); - __regCPACR = cpacr; -} - -/** \brief Get CBAR - \return Configuration Base Address register value - */ -__STATIC_INLINE uint32_t __get_CBAR() { - register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); - return(__regCBAR); -} - -/** \brief Get TTBR0 - - This function returns the value of the Translation Table Base Register 0. - - \return Translation Table Base Register 0 value - */ -__STATIC_INLINE uint32_t __get_TTBR0() { - register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); - return(__regTTBR0); -} - -/** \brief Set TTBR0 - - This function assigns the given value to the Translation Table Base Register 0. - - \param [in] ttbr0 Translation Table Base Register 0 value to set - */ -__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { - register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); - __regTTBR0 = ttbr0; -} - -/** \brief Get DACR - - This function returns the value of the Domain Access Control Register. - - \return Domain Access Control Register value - */ -__STATIC_INLINE uint32_t __get_DACR() { - register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); - return(__regDACR); -} - -/** \brief Set DACR - - This function assigns the given value to the Domain Access Control Register. - - \param [in] dacr Domain Access Control Register value to set - */ -__STATIC_INLINE void __set_DACR(uint32_t dacr) { - register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); - __regDACR = dacr; -} - -/** \brief Set SCTLR - - This function assigns the given value to the System Control Register. - - \param [in] sctlr System Control Register value to set - */ -__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) -{ - register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); - __regSCTLR = sctlr; -} - -/** \brief Get SCTLR - \return System Control Register value - */ -__STATIC_INLINE uint32_t __get_SCTLR() { - register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); - return(__regSCTLR); -} - -/** \brief Set ACTRL - \param [in] actrl Auxiliary Control Register value to set - */ -__STATIC_INLINE void __set_ACTRL(uint32_t actrl) -{ - register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1"); - __regACTRL = actrl; -} - -/** \brief Get ACTRL - \return Auxiliary Control Register value - */ -__STATIC_INLINE uint32_t __get_ACTRL(void) -{ - register uint32_t __regACTRL __ASM("cp15:0:c1:c0:1"); - return(__regACTRL); -} - -/** \brief Get MPIDR - - This function returns the value of the Multiprocessor Affinity Register. - - \return Multiprocessor Affinity Register value - */ -__STATIC_INLINE uint32_t __get_MPIDR(void) -{ - register uint32_t __regMPIDR __ASM("cp15:0:c0:c0:5"); - return(__regMPIDR); -} - - /** \brief Get VBAR - - This function returns the value of the Vector Base Address Register. - - \return Vector Base Address Register - */ -__STATIC_INLINE uint32_t __get_VBAR(void) -{ - register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0"); - return(__regVBAR); -} - -/** \brief Set VBAR - - This function assigns the given value to the Vector Base Address Register. - - \param [in] vbar Vector Base Address Register value to set - */ -__STATIC_INLINE void __set_VBAR(uint32_t vbar) -{ - register uint32_t __regVBAR __ASM("cp15:0:c12:c0:0"); - __regVBAR = vbar; -} - -/** \brief Set CNTP_TVAL - - This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). - - \param [in] value CNTP_TVAL Register value to set -*/ -__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) { - register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0"); - __regCNTP_TVAL = value; -} - -/** \brief Get CNTP_TVAL - - This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). - - \return CNTP_TVAL Register value - */ -__STATIC_INLINE uint32_t __get_CNTP_TVAL() { - register uint32_t __regCNTP_TVAL __ASM("cp15:0:c14:c2:0"); - return(__regCNTP_TVAL); -} - -/** \brief Set CNTP_CTL - - This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). - - \param [in] value CNTP_CTL Register value to set -*/ -__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) { - register uint32_t __regCNTP_CTL __ASM("cp15:0:c14:c2:1"); - __regCNTP_CTL = value; -} - -/** \brief Set TLBIALL - - TLB Invalidate All - */ -__STATIC_INLINE void __set_TLBIALL(uint32_t value) { - register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); - __TLBIALL = value; -} - -/** \brief Set BPIALL. - - Branch Predictor Invalidate All - */ -__STATIC_INLINE void __set_BPIALL(uint32_t value) { - register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); - __BPIALL = value; -} - -/** \brief Set ICIALLU - - Instruction Cache Invalidate All - */ -__STATIC_INLINE void __set_ICIALLU(uint32_t value) { - register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); - __ICIALLU = value; -} - -/** \brief Set DCCMVAC - - Data cache clean - */ -__STATIC_INLINE void __set_DCCMVAC(uint32_t value) { - register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); - __DCCMVAC = value; -} - -/** \brief Set DCIMVAC - - Data cache invalidate +/* + * Include common core functions to access Coprocessor 15 registers */ -__STATIC_INLINE void __set_DCIMVAC(uint32_t value) { - register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); - __DCIMVAC = value; -} - -/** \brief Set DCCIMVAC + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); Rt = tmp; } while(0) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = Rt; } while(0) - Data cache clean and invalidate - */ -__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) { - register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); - __DCCIMVAC = value; -} +#include "cmsis_cp15.h" /** \brief Clean and Invalidate the entire data or unified cache - - Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency + * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean */ -#pragma push -#pragma arm __STATIC_INLINE __ASM void __L1C_CleanInvalidateCache(uint32_t op) { ARM @@ -595,14 +505,11 @@ Finished POP {R4-R11} BX lr } -#pragma pop /** \brief Enable Floating Point Unit Critical section, called from undef handler, so systick is disabled */ -#pragma push -#pragma arm __STATIC_INLINE __ASM void __FPU_Enable(void) { ARM @@ -668,6 +575,5 @@ __STATIC_INLINE __ASM void __FPU_Enable(void) { BX LR } -#pragma pop #endif /* __CMSIS_ARMCC_H */ diff --git a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h similarity index 57% rename from cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h rename to cmsis/TARGET_CORTEX_A/cmsis_armclang.h index 40069837d15..9c93f2fd1d5 100644 --- a/cmsis/TARGET_CORTEX_A/TOOLCHAIN_ARM/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_armclang.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_armclang.h * @brief CMSIS compiler specific macros, functions, instructions - * @version V1.00 - * @date 05. Apr 2017 + * @version V1.0.1 + * @date 07. Sep 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -31,68 +31,72 @@ /* CMSIS compiler specific defines */ #ifndef __ASM - #define __ASM __asm + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) #endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) #endif -#ifndef __STATIC_ASM - #define __STATIC_ASM static __asm +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) #endif -#ifndef __USED - #define __USED __attribute__((used)) +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) #endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) #endif -#ifndef __UNALIGNED_UINT32 - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) #endif #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif - - -/* ########################### Core Function Access ########################### */ - -/** - \brief Get FPSCR - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - __ASM volatile("MRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0U); -#endif -} - -/** - \brief Set FPSCR - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) : "memory"); -#else - (void)fpscr; + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) #endif -} /* ########################## Core Instruction Access ######################### */ /** @@ -210,316 +214,226 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint */ #define __CLZ __builtin_clz -/** \brief Get CPSR Register - \return CPSR Register value - */ -__STATIC_INLINE uint32_t __get_CPSR(void) -{ - uint32_t result; - __ASM volatile("MRS %0, cpsr" : "=r" (result) ); - return(result); -} - -/** \brief Get Mode - \return Processor Mode +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) */ -__STATIC_INLINE uint32_t __get_mode(void) { - return (__get_CPSR() & 0x1FU); -} +#define __LDREXB (uint8_t)__builtin_arm_ldrex -/** \brief Set Mode - \param [in] mode Mode value to set - */ -__STATIC_INLINE void __set_mode(uint32_t mode) { - __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); -} -/** \brief Set Stack Pointer - \param [in] stack Stack Pointer value to set +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) */ -__STATIC_INLINE void __set_SP(uint32_t stack) -{ - __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); -} +#define __LDREXH (uint16_t)__builtin_arm_ldrex -/** \brief Set Process Stack Pointer - \param [in] topOfProcStack USR/SYS Stack Pointer value to set +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile( - ".preserve8 \n" - "BIC r0, r0, #7 \n" // ensure stack is 8-byte aligned - "MRS r1, cpsr \n" - "CPS #0x1F \n" // no effect in USR mode - "MOV sp, r0 \n" - "MSR cpsr_c, r1 \n" // no effect in USR mode - "ISB" - ); -} +#define __LDREXW (uint32_t)__builtin_arm_ldrex -/** \brief Set User Mode +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_INLINE void __set_CPS_USR(void) -{ - __ASM volatile("CPS #0x10"); -} +#define __STREXB (uint32_t)__builtin_arm_strex -/** \brief Get FPEXC - \return Floating Point Exception Control register value +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_INLINE uint32_t __get_FPEXC(void) -{ -#if (__FPU_PRESENT == 1) - uint32_t result; - __ASM volatile("MRS %0, fpexc" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} +#define __STREXH (uint32_t)__builtin_arm_strex -/** \brief Set FPEXC - \param [in] fpexc Floating Point Exception Control value to set +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed */ -__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) -{ -#if (__FPU_PRESENT == 1) - __ASM volatile ("MSR fpexc, %0" : : "r" (fpexc) : "memory"); -#endif -} +#define __STREXW (uint32_t)__builtin_arm_strex -/** \brief Get CPACR - \return Coprocessor Access Control register value +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. */ -__STATIC_INLINE uint32_t __get_CPACR(void) -{ - uint32_t result; - __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result)); - return result; -} +#define __CLREX __builtin_arm_clrex -/** \brief Set CPACR - \param [in] cpacr Coprocessor Acccess Control value to set +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value */ -__STATIC_INLINE void __set_CPACR(uint32_t cpacr) -{ - __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory"); -} +#define __SSAT __builtin_arm_ssat -/** \brief Get CBAR - \return Configuration Base Address register value +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value */ -__STATIC_INLINE uint32_t __get_CBAR() { - uint32_t result; - __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result)); - return result; -} +#define __USAT __builtin_arm_usat -/** \brief Get TTBR0 - This function returns the value of the Translation Table Base Register 0. +/* ########################### Core Function Access ########################### */ - \return Translation Table Base Register 0 value +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value */ -__STATIC_INLINE uint32_t __get_TTBR0() { - uint32_t result; - __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result)); - return result; -} - -/** \brief Set TTBR0 +#define __get_FPSCR __builtin_arm_get_fpscr - This function assigns the given value to the Translation Table Base Register 0. - - \param [in] ttbr0 Translation Table Base Register 0 value to set +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set */ -__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { - __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory"); -} - -/** \brief Get DACR +#define __set_FPSCR __builtin_arm_set_fpscr - This function returns the value of the Domain Access Control Register. - - \return Domain Access Control Register value +/** \brief Get CPSR Register + \return CPSR Register value */ -__STATIC_INLINE uint32_t __get_DACR() { +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPSR(void) +{ uint32_t result; - __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result)); - return result; -} - -/** \brief Set DACR - - This function assigns the given value to the Domain Access Control Register. - - \param [in] dacr Domain Access Control Register value to set - */ -__STATIC_INLINE void __set_DACR(uint32_t dacr) { - __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory"); + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); } -/** \brief Set SCTLR - - This function assigns the given value to the System Control Register. - - \param [in] sctlr System Control Register value to set +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set */ -__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) +__attribute__((always_inline)) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) { - __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory"); +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); } -/** \brief Get SCTLR - \return System Control Register value +/** \brief Get Mode + \return Processor Mode */ -__STATIC_INLINE uint32_t __get_SCTLR() { - uint32_t result; - __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result)); - return result; +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); } -/** \brief Set ACTRL - \param [in] actrl Auxiliary Control Register value to set +/** \brief Set Mode + \param [in] mode Mode value to set */ -__STATIC_INLINE void __set_ACTRL(uint32_t actrl) +__attribute__((always_inline)) __STATIC_INLINE void __set_mode(uint32_t mode) { - __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory"); + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); } -/** \brief Get ACTRL - \return Auxiliary Control Register value +/** \brief Get Stack Pointer + \return Stack Pointer value */ -__STATIC_INLINE uint32_t __get_ACTRL(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP() { uint32_t result; - __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result)); + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); return result; } -/** \brief Get MPIDR - - This function returns the value of the Multiprocessor Affinity Register. - - \return Multiprocessor Affinity Register value +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set */ -__STATIC_INLINE uint32_t __get_MPIDR(void) +__attribute__((always_inline)) __STATIC_INLINE void __set_SP(uint32_t stack) { - uint32_t result; - __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result)); - return result; + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); } - /** \brief Get VBAR - - This function returns the value of the Vector Base Address Register. - - \return Vector Base Address Register +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value */ -__STATIC_INLINE uint32_t __get_VBAR(void) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_SP_usr() { + uint32_t cpsr; uint32_t result; - __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result)); + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); return result; } -/** \brief Set VBAR - - This function assigns the given value to the Vector Base Address Register. - - \param [in] vbar Vector Base Address Register value to set +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set */ -__STATIC_INLINE void __set_VBAR(uint32_t vbar) +__attribute__((always_inline)) __STATIC_INLINE void __set_SP_usr(uint32_t topOfProcStack) { - __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory"); -} - -/** \brief Set CNTP_TVAL - - This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). - - \param [in] value CNTP_TVAL Register value to set -*/ -__STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory"); + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); } -/** \brief Get CNTP_TVAL - - This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). - - \return CNTP_TVAL Register value +/** \brief Get FPEXC + \return Floating Point Exception Control register value */ -__STATIC_INLINE uint32_t __get_CNTP_TVAL() { +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) uint32_t result; - __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result)); - return result; -} - -/** \brief Set CNTP_CTL - - This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). - - \param [in] value CNTP_CTL Register value to set -*/ -__STATIC_INLINE void __set_CNTP_CTL(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory"); -} - -/** \brief Set TLBIALL - - TLB Invalidate All - */ -__STATIC_INLINE void __set_TLBIALL(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory"); -} - -/** \brief Set BPIALL. - - Branch Predictor Invalidate All - */ -__STATIC_INLINE void __set_BPIALL(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory"); + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); +#else + return(0); +#endif } -/** \brief Set ICIALLU - - Instruction Cache Invalidate All +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set */ -__STATIC_INLINE void __set_ICIALLU(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory"); +__attribute__((always_inline)) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif } -/** \brief Set DCCMVAC - - Data cache clean +/* + * Include common core functions to access Coprocessor 15 registers */ -__STATIC_INLINE void __set_DCCMVAC(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory"); -} - -/** \brief Set DCIMVAC - Data cache invalidate - */ -__STATIC_INLINE void __set_DCIMVAC(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory"); -} +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) -/** \brief Set DCCIMVAC +#include "cmsis_cp15.h" - Data cache clean and invalidate - */ -__STATIC_INLINE void __set_DCCIMVAC(uint32_t value) { - __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory"); -} /** \brief Clean and Invalidate the entire data or unified cache Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency */ -__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) { +__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) +{ __ASM volatile( " PUSH {R4-R11} \n" @@ -577,26 +491,27 @@ __STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) { Critical section, called from undef handler, so systick is disabled */ -__STATIC_INLINE void __FPU_Enable(void) { +__STATIC_INLINE void __FPU_Enable(void) +{ __ASM volatile( - //Permit access to VFP/NEON, registers by modifying CPACR + //Permit access to VFP/NEON, registers by modifying CPACR " MRC p15,0,R1,c1,c0,2 \n" " ORR R1,R1,#0x00F00000 \n" " MCR p15,0,R1,c1,c0,2 \n" - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted " ISB \n" - //Enable VFP/NEON + //Enable VFP/NEON " VMRS R1,FPEXC \n" " ORR R1,R1,#0x40000000 \n" " VMSR FPEXC,R1 \n" - //Initialise VFP/NEON registers to 0 + //Initialise VFP/NEON registers to 0 " MOV R2,#0 \n" -#if 0 // TODO: Initialize FPU registers according to available register count - ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} >= 16 \n" - //Initialise D16 registers to 0 + +#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16 + //Initialise D16 registers to 0 " VMOV D0, R2,R2 \n" " VMOV D1, R2,R2 \n" " VMOV D2, R2,R2 \n" @@ -613,10 +528,10 @@ __STATIC_INLINE void __FPU_Enable(void) { " VMOV D13,R2,R2 \n" " VMOV D14,R2,R2 \n" " VMOV D15,R2,R2 \n" - ".endif \n" +#endif - ".if {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 \n" - //Initialise D32 registers to 0 +#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 + //Initialise D32 registers to 0 " VMOV D16,R2,R2 \n" " VMOV D17,R2,R2 \n" " VMOV D18,R2,R2 \n" @@ -635,7 +550,7 @@ __STATIC_INLINE void __FPU_Enable(void) { " VMOV D31,R2,R2 \n" ".endif \n" #endif - //Initialise FPSCR to a known state + //Initialise FPSCR to a known state " VMRS R2,FPSCR \n" " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. " AND R2,R2,R3 \n" @@ -643,4 +558,4 @@ __STATIC_INLINE void __FPU_Enable(void) { ); } -#endif /* __CMSIS_ARMCC_H */ +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h index 9fa0e0ea49d..ec27cfeac8e 100644 --- a/cmsis/TARGET_CORTEX_A/cmsis_compiler.h +++ b/cmsis/TARGET_CORTEX_A/cmsis_compiler.h @@ -52,41 +52,9 @@ * IAR Compiler */ #elif defined ( __ICCARM__ ) + #include "cmsis_iccarm.h" - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - - #include - - #ifndef __NO_RETURN - #define __NO_RETURN __noreturn - #endif - #ifndef __USED - #define __USED __root - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __UNALIGNED_UINT32 - __packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - - + /* * TI ARM Compiler */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_cp15.h b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h new file mode 100644 index 00000000000..68b39f30921 --- /dev/null +++ b/cmsis/TARGET_CORTEX_A/cmsis_cp15.h @@ -0,0 +1,437 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get ACTLR + \return Auxiliary Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTLR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r" (result) : : "memory" ); + __get_CP(15, 0, result, 1, 0, 1); + return(result); +} + +/** \brief Set ACTLR + \param [in] actlr Auxiliary Control value to set + */ +__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr) +{ + // __ASM volatile ("MCR p15, 0, %0, c1, c0, 1" : : "r" (actlr) : "memory"); + __set_CP(15, 0, actlr, 1, 0, 1); +} + +/** \brief Get CPACR + \return Coprocessor Access Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPACR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c1, c0, 2" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 1, 0, 2); + return result; +} + +/** \brief Set CPACR + \param [in] cpacr Coprocessor Access Control value to set + */ +__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr) +{ +// __ASM volatile("MCR p15, 0, %0, c1, c0, 2" : : "r"(cpacr) : "memory"); + __set_CP(15, 0, cpacr, 1, 0, 2); +} + +/** \brief Get DFSR + \return Data Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DFSR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c5, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 5, 0, 0); + return result; +} + +/** \brief Set DFSR + \param [in] dfsr Data Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr) +{ +// __ASM volatile("MCR p15, 0, %0, c5, c0, 0" : : "r"(dfsr) : "memory"); + __set_CP(15, 0, dfsr, 5, 0, 0); +} + +/** \brief Get IFSR + \return Instruction Fault Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IFSR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c5, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 5, 0, 1); + return result; +} + +/** \brief Set IFSR + \param [in] ifsr Instruction Fault Status value to set + */ +__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr) +{ +// __ASM volatile("MCR p15, 0, %0, c5, c0, 1" : : "r"(ifsr) : "memory"); + __set_CP(15, 0, ifsr, 5, 0, 1); +} + +/** \brief Get ISR + \return Interrupt Status Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c12, c1, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CBAR + \return Configuration Base Address register value + */ +__STATIC_FORCEINLINE uint32_t __get_CBAR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 4, result, 15, 0, 0); + return result; +} + +/** \brief Get TTBR0 + + This function returns the value of the Translation Table Base Register 0. + + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_TTBR0(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 2, 0, 0); + return result; +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Translation Table Base Register 0. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0) +{ +// __ASM volatile("MCR p15, 0, %0, c2, c0, 0" : : "r"(ttbr0) : "memory"); + __set_CP(15, 0, ttbr0, 2, 0, 0); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_DACR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 3, 0, 0); + return result; +} + +/** \brief Set DACR + + This function assigns the given value to the Domain Access Control Register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr) +{ +// __ASM volatile("MCR p15, 0, %0, c3, c0, 0" : : "r"(dacr) : "memory"); + __set_CP(15, 0, dacr, 3, 0, 0); +} + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ +// __ASM volatile("MCR p15, 0, %0, c1, c0, 0" : : "r"(sctlr) : "memory"); + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get SCTLR + \return System Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set ACTRL + \param [in] actrl Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl) +{ +// __ASM volatile("MCR p15, 0, %0, c1, c0, 1" : : "r"(actrl) : "memory"); + __set_CP(15, 0, actrl, 1, 0, 1); +} + +/** \brief Get ACTRL + \return Auxiliary Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ACTRL(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c1, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 1, 0, 1); + return result; +} + +/** \brief Get MPIDR + + This function returns the value of the Multiprocessor Affinity Register. + + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c0, c0, 5" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + + /** \brief Get VBAR + + This function returns the value of the Vector Base Address Register. + + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 0, %0, c12, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + + This function assigns the given value to the Vector Base Address Register. + + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ +// __ASM volatile("MCR p15, 0, %0, c12, c0, 1" : : "r"(vbar) : "memory"); + __set_CP(15, 0, vbar, 12, 0, 1); +} + +#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \ + defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \ + defined(DOXYGEN) + +/** \brief Set CNTFRQ + + This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \param [in] value CNTFRQ Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value) +{ + // __ASM volatile("MCR p15, 0, %0, c14, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 14, 0, 0); +} + +/** \brief Get CNTFRQ + + This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). + + \return CNTFRQ Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void) +{ + uint32_t result; + // __ASM volatile("MRC p15, 0, %0, c14, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 14, 0 , 0); + return result; +} + +/** \brief Set CNTP_TVAL + + This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). + + \param [in] value CNTP_TVAL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value) +{ + // __ASM volatile("MCR p15, 0, %0, c14, c2, 0" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 14, 2, 0); +} + +/** \brief Get CNTP_TVAL + + This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). + + \return CNTP_TVAL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void) +{ + uint32_t result; + // __ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 14, 2, 0); + return result; +} + +/** \brief Set CNTP_CTL + + This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). + + \param [in] value CNTP_CTL Register value to set +*/ +__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value) +{ + // __ASM volatile("MCR p15, 0, %0, c14, c2, 1" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 14, 2, 1); +} + +/** \brief Get CNTP_CTL register + \return CNTP_CTL Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void) +{ + uint32_t result; + // __ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result) : : "memory"); + __get_CP(15, 0, result, 14, 2, 1); + return result; +} + +#endif + +/** \brief Set TLBIALL + + TLB Invalidate All + */ +__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c8, c7, 0" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 8, 7, 0); +} + +/** \brief Set BPIALL. + + Branch Predictor Invalidate All + */ +__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c5, 6" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 7, 5, 6); +} + +/** \brief Set ICIALLU + + Instruction Cache Invalidate All + */ +__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c5, 0" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 7, 5, 0); +} + +/** \brief Set DCCMVAC + + Data cache clean + */ +__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c10, 1" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 7, 10, 1); +} + +/** \brief Set DCIMVAC + + Data cache invalidate + */ +__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c6, 1" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 7, 6, 1); +} + +/** \brief Set DCCIMVAC + + Data cache clean and invalidate + */ +__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value) +{ +// __ASM volatile("MCR p15, 0, %0, c7, c14, 1" : : "r"(value) : "memory"); + __set_CP(15, 0, value, 7, 14, 1); +} + + +/** \brief Set CCSIDR + */ +__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value) +{ +// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory"); + __set_CP(15, 2, value, 0, 0, 0); +} + +/** \brief Get CCSIDR + \return CCSIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + \return CLIDR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; +// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory"); + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +#endif diff --git a/cmsis/TARGET_CORTEX_A/cmsis_gcc.h b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h new file mode 100644 index 00000000000..45b6129456f --- /dev/null +++ b/cmsis/TARGET_CORTEX_A/cmsis_gcc.h @@ -0,0 +1,737 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.1 + * @date 07. Sep 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE __attribute__((always_inline)) +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + */ +#define __WFI() __ASM volatile ("wfi") + +/** + \brief Wait For Event + */ +#define __WFE() __ASM volatile ("wfe") + +/** + \brief Send Event + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + +/** + \brief Reverse byte order (16 bit) + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value)); + return result; +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + +/** + \brief Breakpoint + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + +/** + \brief Count leading zeros + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +/* ########################### Core Function Access ########################### */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value +*/ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); + #else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); + #endif + #else + return(0U); + #endif +} + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); + #else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + #endif + #else + (void)fpscr; + #endif +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) { + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + +/** \brief Get FPEXC + \return Floating Point Exception Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** \brief Set FPEXC + \param [in] fpexc Floating Point Exception Control value to set + */ +__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); +#endif +} + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +__STATIC_FORCEINLINE int32_t log2_up(uint32_t n) +{ + int32_t log = -1; + uint32_t t = n; + while(t) + { + log++; t >>=1; + } + /* if n not power of 2 -> round up*/ + if ( n & (n - 1) ) log++; + return log; +} + +__STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint) +{ + register volatile uint32_t Dummy; + register volatile uint32_t ccsidr; + uint32_t num_sets; + uint32_t num_ways; + uint32_t shift_way; + uint32_t log2_linesize; + uint32_t log2_num_ways; + + Dummy = level << 1; + /* set csselr, select ccsidr register */ + __set_CCSIDR(Dummy); + /* get current ccsidr register */ + ccsidr = __get_CCSIDR(); + num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1; + num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1; + log2_linesize = (ccsidr & 0x00000007) + 2 + 2; + log2_num_ways = log2_up(num_ways); + shift_way = 32 - log2_num_ways; + for(int way = num_ways-1; way >= 0; way--) { + for(int set = num_sets-1; set >= 0; set--) { + Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way); + switch (maint) + { + case 0: + __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(Dummy) : "memory"); // DCISW. Invalidate by Set/Way + break; + + case 1: + __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(Dummy) : "memory"); // DCCSW. Clean by Set/Way + break; + + default: + __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(Dummy) : "memory"); // DCCISW. Clean and Invalidate by Set/Way + break; + + } + } + } + __DMB(); +} + +/** \brief Clean and Invalidate the entire data or unified cache + + Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency + */ +__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op) { + register volatile uint32_t clidr; + uint32_t cache_type; + clidr = __get_CLIDR(); + for(uint32_t i = 0; i<7; i++) + { + cache_type = (clidr >> i*3) & 0x7UL; + if ((cache_type >= 2) && (cache_type <= 4)) + { + __L1C_MaintainDCacheSetWay(i, op); + } + } + +} + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) { + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + +#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16 + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" +#endif + +#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 " + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h new file mode 100644 index 00000000000..18e6e6acfb0 --- /dev/null +++ b/cmsis/TARGET_CORTEX_A/cmsis_iccarm.h @@ -0,0 +1,591 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR compiler) header file + * @version V5.0.3 + * @date 29. August 2017 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#pragma language=extended + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_7A__ +/* Macro already defined */ +#else + #if defined(__ARM7A__) + #define __ARM_ARCH_7A__ 1 + #endif +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #define __NO_RETURN _Pragma("object_attribute=__noreturn") +#endif + +#ifndef __PACKED + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + /* Needs IAR language extensions */ + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE _Pragma("inline=forced") static inline +#endif +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __UNALIGNED_UINT16_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint16_t __iar_uint16_read(void const *ptr) { + return *(__packed uint16_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { + *(__packed uint16_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ + #pragma language=save + #pragma language=extended + __IAR_FT uint32_t __iar_uint32_read(void const *ptr) { + return *(__packed uint32_t*)(ptr); + } + #pragma language=restore + #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE + #pragma language=save + #pragma language=extended + __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { + *(__packed uint32_t*)(ptr) = val;; + } + #pragma language=restore + #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#if 0 +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma language=save + #pragma language=extended + __packed struct __iar_u32 { uint32_t v; }; + #pragma language=restore + #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __enable_irq __iar_builtin_enable_interrupt + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + #if __FPU_PRESENT + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #else + #define __get_FPSCR() ( 0 ) + #endif + + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE)) + + #define __get_CPSR() (__arm_rsr("CPSR")) + #define __get_mode() (__get_CPSR() & 0x1FU) + + #define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE))) + #define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE))) + + + #define __get_FPEXC() (__arm_rsr("FPEXC")) + #define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE)) + + #define __get_CP(cp, op1, RT, CRn, CRm, op2) \ + (RT = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2)) + + #define __set_CP(cp, op1, RT, CRn, CRm, op2) \ + (__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, RT)) + + #include "cmsis_cp15.h" + + #define __NOP __iar_builtin_no_operation + + __IAR_FT uint8_t __CLZ(uint32_t val) { + return __iar_builtin_CLZ(val); + } + + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int32_t __REVSH(int32_t val) { + return __iar_builtin_REVSH((int16_t)val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #define __SSAT __iar_builtin_SSAT + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #define __USAT __iar_builtin_USAT + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if !__FPU_PRESENT + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #endif + + #include + + #if !__FPU_PRESENT + #define __get_FPSCR() (0) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + __IAR_FT void __set_mode(uint32_t mode) + { + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); + } + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { + return __STREX(value, (unsigned long *)ptr); + } + + + __IAR_FT uint32_t __RRX(uint32_t value) { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + __IAR_FT uint32_t __get_FPEXC(void) + { + #if (__FPU_PRESENT == 1) + uint32_t result; + __ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory"); + return(result); + #else + return(0); + #endif + } + + __IAR_FT void __set_FPEXC(uint32_t fpexc) + { + #if (__FPU_PRESENT == 1) + __ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory"); + #endif + } + + + #define __get_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) + #define __set_CP(cp, op1, Rt, CRn, CRm, op2) \ + __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) + + #include "cmsis_cp15.h" + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + + +__IAR_FT uint32_t __get_SP_usr(void) +{ + uint32_t cpsr; + uint32_t result; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV %1, sp \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory" + ); + return result; +} + +__IAR_FT void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr; + __ASM volatile( + "MRS %0, cpsr \n" + "CPS #0x1F \n" // no effect in USR mode + "MOV sp, %1 \n" + "MSR cpsr_c, %2 \n" // no effect in USR mode + "ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory" + ); +} + +#define __get_mode() (__get_CPSR() & 0x1FU) + + +__STATIC_INLINE +void __L1C_CleanInvalidateCache(uint32_t op) +{ + __ASM volatile( + " PUSH {R4-R11} \n" + + " MRC p15, 1, R6, c0, c0, 1 \n" // Read CLIDR + " ANDS R3, R6, #0x07000000 \n" // Extract coherency level + " MOV R3, R3, LSR #23 \n" // Total cache levels << 1 + " BEQ Finished \n" // If 0, no need to clean + + " MOV R10, #0 \n" // R10 holds current cache level << 1 + "Loop1: ADD R2, R10, R10, LSR #1 \n" // R2 holds cache "Set" position + " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level + " AND R1, R1, #7 \n" // Isolate those lower 3 bits + " CMP R1, #2 \n" + " BLT Skip \n" // No cache or only instruction cache at this level + + " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register + " ISB \n" // ISB to sync the change to the CacheSizeID reg + " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register + " AND R2, R1, #7 \n" // Extract the line length field + " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes) + " MOVW R4, #0x3FF \n" + " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned) + " CLZ R5, R4 \n" // R5 is the bit position of the way size increment + " MOVW R7, #0x7FFF \n" + " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned) + + "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned) + + "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11 + " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number + " CMP R0, #0 \n" + " BNE Dccsw \n" + " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way + " B cont \n" + "Dccsw: CMP R0, #1 \n" + " BNE Dccisw \n" + " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way + " B cont \n" + "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW. Clean and Invalidate by Set/Way + "cont: SUBS R9, R9, #1 \n" // Decrement the Way number + " BGE Loop3 \n" + " SUBS R7, R7, #1 \n" // Decrement the Set number + " BGE Loop2 \n" + "Skip: ADD R10, R10, #2 \n" // Increment the cache number + " CMP R3, R10 \n" + " BGT Loop1 \n" + + "Finished: \n" + " DSB \n" + " POP {R4-R11} " + ); +} + + +__STATIC_INLINE +void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + +#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT >= 16 + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" +#endif + +#if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" + ".endif \n" +#endif + //Initialise FPSCR to a known state + " VMRS R2,FPSCR \n" + " MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R2,R2,R3 \n" + " VMSR FPSCR,R2 \n"); +} + + + +#undef __IAR_FT +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/cmsis/core_ca.h b/cmsis/TARGET_CORTEX_A/core_ca.h similarity index 58% rename from cmsis/core_ca.h rename to cmsis/TARGET_CORTEX_A/core_ca.h index 6d1e29f60ff..1792dc35db7 100644 --- a/cmsis/core_ca.h +++ b/cmsis/TARGET_CORTEX_A/core_ca.h @@ -39,10 +39,10 @@ ******************************************************************************/ /* CMSIS CA definitions */ -#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS HAL main version */ -#define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS HAL sub version */ +#define __CA_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ #define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ - __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS HAL version number */ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP @@ -56,6 +56,18 @@ #define __FPU_USED 0U #endif +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if (__FPU_PRESENT == 1) @@ -133,12 +145,7 @@ #define __FPU_PRESENT 0U #warning "__FPU_PRESENT not defined in device header file; using default!" #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - + #ifndef __GIC_PRESENT #define __GIC_PRESENT 1U #warning "__GIC_PRESENT not defined in device header file; using default!" @@ -168,7 +175,7 @@ #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */ #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */ #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */ - +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas /******************************************************************************* * Register Abstraction @@ -193,7 +200,7 @@ typedef union uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved0:4; /*!< \brief bit: 20..23 Reserved */ + RESERVED(0:4, uint32_t) uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ @@ -205,6 +212,8 @@ typedef union uint32_t w; /*!< \brief Type used for word access */ } CPSR_Type; + + /* CPSR Register Definitions */ #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ @@ -251,6 +260,16 @@ typedef union #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + /* CP15 Register SCTLR */ typedef union { @@ -259,32 +278,32 @@ typedef union uint32_t M:1; /*!< \brief bit: 0 MMU enable */ uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ uint32_t C:1; /*!< \brief bit: 2 Cache enable */ - uint32_t _reserved0:2; /*!< \brief bit: 3.. 4 Reserved */ + RESERVED(0:2, uint32_t) uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ - uint32_t _reserved1:1; /*!< \brief bit: 6 Reserved */ + RESERVED(1:1, uint32_t) uint32_t B:1; /*!< \brief bit: 7 Endianness model */ - uint32_t _reserved2:2; /*!< \brief bit: 8.. 9 Reserved */ + RESERVED(2:2, uint32_t) uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */ uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */ uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */ - uint32_t _reserved3:2; /*!< \brief bit:15..16 Reserved */ + RESERVED(3:2, uint32_t) uint32_t HA:1; /*!< \brief bit: 17 Hardware Access flag enable */ - uint32_t _reserved4:1; /*!< \brief bit: 18 Reserved */ + RESERVED(4:1, uint32_t) uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */ uint32_t U:1; /*!< \brief bit: 22 Alignment model */ - uint32_t _reserved5:1; /*!< \brief bit: 23 Reserved */ + RESERVED(5:1, uint32_t) uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */ uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ - uint32_t _reserved6:1; /*!< \brief bit: 26 Reserved */ + RESERVED(6:1, uint32_t) uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */ uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ - uint32_t _reserved7:1; /*!< \brief bit: 31 Reserved */ + RESERVED(7:1, uint32_t) } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } SCTLR_Type; @@ -352,15 +371,144 @@ typedef union #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ +/* CP15 Register ACTLR */ +typedef union +{ +#if __CORTEX_A == 5 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A5 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:5, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + RESERVED(1:2, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t DWBST:1; /*!< \brief bit: 11 AXI data write bursts to Normal memory */ + uint32_t RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t BP:2; /*!< \brief bit:16..15 Branch prediction policy */ + uint32_t RSDIS:1; /*!< \brief bit: 17 Disable return stack operation */ + uint32_t BTDIS:1; /*!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) */ + RESERVED(3:9, uint32_t) + uint32_t DBDI:1; /*!< \brief bit: 28 Disable branch dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 7 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A7 */ + struct + { + RESERVED(0:6, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + RESERVED(1:3, uint32_t) + uint32_t DODMBS:1; /*!< \brief bit: 10 Disable optimized data memory barrier behavior */ + uint32_t L2RADIS:1; /*!< \brief bit: 11 L2 Data Cache read-allocate mode disable */ + uint32_t L1RADIS:1; /*!< \brief bit: 12 L1 Data Cache read-allocate mode disable */ + uint32_t L1PCTL:2; /*!< \brief bit:13..14 L1 Data prefetch control */ + uint32_t DDVM:1; /*!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions */ + RESERVED(3:12, uint32_t) + uint32_t DDI:1; /*!< \brief bit: 28 Disable dual issue */ + RESERVED(7:3, uint32_t) + } b; +#endif +#if __CORTEX_A == 9 || defined(DOXYGEN) + /** \brief Structure used for bit access on Cortex-A9 */ + struct + { + uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */ + RESERVED(0:1, uint32_t) + uint32_t L1PE:1; /*!< \brief bit: 2 Dside prefetch */ + uint32_t WFLZM:1; /*!< \brief bit: 3 Cache and TLB maintenance broadcast */ + RESERVED(1:2, uint32_t) + uint32_t SMP:1; /*!< \brief bit: 6 Enables coherent requests to the processor */ + uint32_t EXCL:1; /*!< \brief bit: 7 Exclusive L1/L2 cache control */ + uint32_t AOW:1; /*!< \brief bit: 8 Enable allocation in one cache way only */ + uint32_t PARITY:1; /*!< \brief bit: 9 Support for parity checking, if implemented */ + RESERVED(7:22, uint32_t) + } b; +#endif + uint32_t w; /*!< \brief Type used for word access */ +} ACTLR_Type; + +#define ACTLR_DDI_Pos 28U /*!< \brief ACTLR: DDI Position */ +#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /*!< \brief ACTLR: DDI Mask */ + +#define ACTLR_DBDI_Pos 28U /*!< \brief ACTLR: DBDI Position */ +#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /*!< \brief ACTLR: DBDI Mask */ + +#define ACTLR_BTDIS_Pos 18U /*!< \brief ACTLR: BTDIS Position */ +#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /*!< \brief ACTLR: BTDIS Mask */ + +#define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */ +#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */ + +#define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */ +#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */ + +#define ACTLR_DDVM_Pos 15U /*!< \brief ACTLR: DDVM Position */ +#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /*!< \brief ACTLR: DDVM Mask */ + +#define ACTLR_L1PCTL_Pos 13U /*!< \brief ACTLR: L1PCTL Position */ +#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /*!< \brief ACTLR: L1PCTL Mask */ + +#define ACTLR_RADIS_Pos 12U /*!< \brief ACTLR: RADIS Position */ +#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /*!< \brief ACTLR: RADIS Mask */ + +#define ACTLR_L1RADIS_Pos 12U /*!< \brief ACTLR: L1RADIS Position */ +#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /*!< \brief ACTLR: L1RADIS Mask */ + +#define ACTLR_DWBST_Pos 11U /*!< \brief ACTLR: DWBST Position */ +#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /*!< \brief ACTLR: DWBST Mask */ + +#define ACTLR_L2RADIS_Pos 11U /*!< \brief ACTLR: L2RADIS Position */ +#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /*!< \brief ACTLR: L2RADIS Mask */ + +#define ACTLR_DODMBS_Pos 10U /*!< \brief ACTLR: DODMBS Position */ +#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /*!< \brief ACTLR: DODMBS Mask */ + +#define ACTLR_PARITY_Pos 9U /*!< \brief ACTLR: PARITY Position */ +#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /*!< \brief ACTLR: PARITY Mask */ + +#define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */ +#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */ + +#define ACTLR_EXCL_Pos 7U /*!< \brief ACTLR: EXCL Position */ +#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /*!< \brief ACTLR: EXCL Mask */ + +#define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */ +#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */ + +#define ACTLR_WFLZM_Pos 3U /*!< \brief ACTLR: WFLZM Position */ +#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /*!< \brief ACTLR: WFLZM Mask */ + +#define ACTLR_L1PE_Pos 2U /*!< \brief ACTLR: L1PE Position */ +#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /*!< \brief ACTLR: L1PE Mask */ + +#define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */ +#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */ + /* CP15 Register CPACR */ typedef union { struct { - uint32_t _reserved0:20; /*!< \brief bit: 0..19 Reserved */ - uint32_t cp10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ - uint32_t cp11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ - uint32_t _reserved1:6; /*!< \brief bit:24..29 Reserved */ + uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */ + uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */ + uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */ + uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */ + uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */ + uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */ + uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */ + uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */ + uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */ + uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */ + uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */ + uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */ + uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */ + uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */ + uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */ + RESERVED(0:1, uint32_t) uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */ uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */ } b; /*!< \brief Structure used for bit access */ @@ -373,11 +521,15 @@ typedef union #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */ #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ -#define CPACR_cp11_Pos 22U /*!< \brief CPACR: cp11 Position */ -#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /*!< \brief CPACR: cp11 Mask */ +#define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */ +#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */ -#define CPACR_cp10_Pos 20U /*!< \brief CPACR: cp10 Position */ -#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /*!< \brief CPACR: cp10 Mask */ +#define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */ +#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */ + +#define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */ +#define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */ +#define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */ /* CP15 Register DFSR */ typedef union @@ -386,13 +538,25 @@ typedef union { uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */ - uint32_t _reserved0:2; /*!< \brief bit: 8.. 9 Reserved */ + RESERVED(0:1, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ - uint32_t _reserved1:18; /*!< \brief bit:14..31 Reserved */ - } b; /*!< \brief Structure used for bit access */ + RESERVED(1:18, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:1, uint32_t) + uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */ + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */ + RESERVED(2:18, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ uint32_t w; /*!< \brief Type used for word access */ } DFSR_Type; @@ -408,24 +572,40 @@ typedef union #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */ #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */ +#define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */ +#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */ + #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */ #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */ #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */ #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */ +#define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */ +#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */ + /* CP15 Register IFSR */ typedef union { struct { uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */ - uint32_t _reserved0:6; /*!< \brief bit: 4.. 9 Reserved */ + RESERVED(0:5, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */ - uint32_t _reserved1:1; /*!< \brief bit: 11 Reserved */ + RESERVED(1:1, uint32_t) uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ - uint32_t _reserved2:19; /*!< \brief bit:13..31 Reserved */ - } b; /*!< \brief Structure used for bit access */ + RESERVED(2:19, uint32_t) + } s; /*!< \brief Structure used for bit access in short format */ + struct + { + uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */ + RESERVED(0:3, uint32_t) + uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */ + RESERVED(1:2, uint32_t) + uint32_t ExT:1; /*!< \brief bit: 12 External abort type */ + RESERVED(2:19, uint32_t) + } l; /*!< \brief Structure used for bit access in long format */ uint32_t w; /*!< \brief Type used for word access */ } IFSR_Type; @@ -435,19 +615,25 @@ typedef union #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */ #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */ +#define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */ +#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */ + #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */ #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */ +#define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */ +#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */ + /* CP15 Register ISR */ typedef union { struct { - uint32_t _reserved0:6; /*!< \brief bit: 0.. 5 Reserved */ + RESERVED(0:6, uint32_t) uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */ uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */ uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */ - uint32_t _reserved1:23; /*!< \brief bit:14..31 Reserved */ + RESERVED(1:23, uint32_t) } b; /*!< \brief Structure used for bit access */ uint32_t w; /*!< \brief Type used for word access */ } ISR_Type; @@ -461,136 +647,188 @@ typedef union #define ISR_F_Pos 11U /*!< \brief ISR: F Position */ #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */ +/* DACR Register */ +#define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */ +#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */ +#define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */ +#define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */ +#define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param [in] field Name of the register bit field. + \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param [in] field Name of the register bit field. + \param [in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + /** \brief Union type to access the L2C_310 Cache Controller. */ -#if (__L2C_PRESENT == 1U) +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) typedef struct { - __I uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 Cache ID Register */ - __I uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 Cache Type Register */ - uint32_t RESERVED0[0x3e]; - __IO uint32_t CONTROL; /*!< \brief Offset: 0x0100 Control Register */ - __IO uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 Auxiliary Control */ - uint32_t RESERVED1[0x3e]; - __IO uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 Event Counter Control */ - __IO uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 Event Counter 1 Configuration */ - __IO uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 Event Counter 1 Configuration */ - uint32_t RESERVED2[0x2]; - __IO uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 Interrupt Mask */ - __I uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 Masked Interrupt Status */ - __I uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c Raw Interrupt Status */ - __O uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 Interrupt Clear */ - uint32_t RESERVED3[0x143]; - __IO uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 Cache Sync */ - uint32_t RESERVED4[0xf]; - __IO uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 Invalidate Line By PA */ - uint32_t RESERVED6[2]; - __IO uint32_t INV_WAY; /*!< \brief Offset: 0x077c Invalidate by Way */ - uint32_t RESERVED5[0xc]; - __IO uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 Clean Line by PA */ - uint32_t RESERVED7[1]; - __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 Clean Line by Index/Way */ - __IO uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc Clean by Way */ - uint32_t RESERVED8[0xc]; - __IO uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA */ - uint32_t RESERVED9[1]; - __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ - __IO uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc Clean and Invalidate by Way */ - uint32_t RESERVED10[0x40]; - __IO uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 Data Lockdown 0 by Way */ - __IO uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way */ - __IO uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 Data Lockdown 1 by Way */ - __IO uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c Instruction Lockdown 1 by Way */ - __IO uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 Data Lockdown 2 by Way */ - __IO uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way */ - __IO uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 Data Lockdown 3 by Way */ - __IO uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c Instruction Lockdown 3 by Way */ - __IO uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 Data Lockdown 4 by Way */ - __IO uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way */ - __IO uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 Data Lockdown 6 by Way */ - __IO uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c Instruction Lockdown 6 by Way */ - uint32_t RESERVED11[0x4]; - __IO uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 Lockdown by Line Enable */ - __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 Unlock All Lines by Way */ - uint32_t RESERVED12[0xaa]; - __IO uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 Address Filtering Start */ - __IO uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 Address Filtering End */ - uint32_t RESERVED13[0xce]; - __IO uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 Debug Control Register */ + __IM uint32_t CACHE_ID; /*!< \brief Offset: 0x0000 (R/ ) Cache ID Register */ + __IM uint32_t CACHE_TYPE; /*!< \brief Offset: 0x0004 (R/ ) Cache Type Register */ + RESERVED(0[0x3e], uint32_t) + __IOM uint32_t CONTROL; /*!< \brief Offset: 0x0100 (R/W) Control Register */ + __IOM uint32_t AUX_CNT; /*!< \brief Offset: 0x0104 (R/W) Auxiliary Control */ + RESERVED(1[0x3e], uint32_t) + __IOM uint32_t EVENT_CONTROL; /*!< \brief Offset: 0x0200 (R/W) Event Counter Control */ + __IOM uint32_t EVENT_COUNTER1_CONF; /*!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration */ + __IOM uint32_t EVENT_COUNTER0_CONF; /*!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration */ + RESERVED(2[0x2], uint32_t) + __IOM uint32_t INTERRUPT_MASK; /*!< \brief Offset: 0x0214 (R/W) Interrupt Mask */ + __IM uint32_t MASKED_INT_STATUS; /*!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status */ + __IM uint32_t RAW_INT_STATUS; /*!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status */ + __OM uint32_t INTERRUPT_CLEAR; /*!< \brief Offset: 0x0220 ( /W) Interrupt Clear */ + RESERVED(3[0x143], uint32_t) + __IOM uint32_t CACHE_SYNC; /*!< \brief Offset: 0x0730 (R/W) Cache Sync */ + RESERVED(4[0xf], uint32_t) + __IOM uint32_t INV_LINE_PA; /*!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA */ + RESERVED(6[2], uint32_t) + __IOM uint32_t INV_WAY; /*!< \brief Offset: 0x077c (R/W) Invalidate by Way */ + RESERVED(5[0xc], uint32_t) + __IOM uint32_t CLEAN_LINE_PA; /*!< \brief Offset: 0x07b0 (R/W) Clean Line by PA */ + RESERVED(7[1], uint32_t) + __IOM uint32_t CLEAN_LINE_INDEX_WAY; /*!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way */ + __IOM uint32_t CLEAN_WAY; /*!< \brief Offset: 0x07bc (R/W) Clean by Way */ + RESERVED(8[0xc], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_PA; /*!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA */ + RESERVED(9[1], uint32_t) + __IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way */ + __IOM uint32_t CLEAN_INV_WAY; /*!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way */ + RESERVED(10[0x40], uint32_t) + __IOM uint32_t DATA_LOCK_0_WAY; /*!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way */ + __IOM uint32_t INST_LOCK_0_WAY; /*!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way */ + __IOM uint32_t DATA_LOCK_1_WAY; /*!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way */ + __IOM uint32_t INST_LOCK_1_WAY; /*!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way */ + __IOM uint32_t DATA_LOCK_2_WAY; /*!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way */ + __IOM uint32_t INST_LOCK_2_WAY; /*!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way */ + __IOM uint32_t DATA_LOCK_3_WAY; /*!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way */ + __IOM uint32_t INST_LOCK_3_WAY; /*!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way */ + __IOM uint32_t DATA_LOCK_4_WAY; /*!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way */ + __IOM uint32_t INST_LOCK_4_WAY; /*!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way */ + __IOM uint32_t DATA_LOCK_5_WAY; /*!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_5_WAY; /*!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_6_WAY; /*!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way */ + __IOM uint32_t INST_LOCK_6_WAY; /*!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way */ + __IOM uint32_t DATA_LOCK_7_WAY; /*!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way */ + __IOM uint32_t INST_LOCK_7_WAY; /*!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way */ + RESERVED(11[0x4], uint32_t) + __IOM uint32_t LOCK_LINE_EN; /*!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable */ + __IOM uint32_t UNLOCK_ALL_BY_WAY; /*!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way */ + RESERVED(12[0xaa], uint32_t) + __IOM uint32_t ADDRESS_FILTER_START; /*!< \brief Offset: 0x0c00 (R/W) Address Filtering Start */ + __IOM uint32_t ADDRESS_FILTER_END; /*!< \brief Offset: 0x0c04 (R/W) Address Filtering End */ + RESERVED(13[0xce], uint32_t) + __IOM uint32_t DEBUG_CONTROL; /*!< \brief Offset: 0x0f40 (R/W) Debug Control Register */ } L2C_310_TypeDef; -#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 Declaration */ +#define L2C_310 ((L2C_310_TypeDef *)L2C_310_BASE) /*!< \brief L2C_310 register set access pointer */ #endif -#if (__GIC_PRESENT == 1U) +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) */ typedef struct { - __IO uint32_t ICDDCR; - __I uint32_t ICDICTR; - __I uint32_t ICDIIDR; - uint32_t RESERVED0[29]; - __IO uint32_t ICDISR[32]; - __IO uint32_t ICDISER[32]; - __IO uint32_t ICDICER[32]; - __IO uint32_t ICDISPR[32]; - __IO uint32_t ICDICPR[32]; - __I uint32_t ICDABR[32]; - uint32_t RESERVED1[32]; - __IO uint32_t ICDIPR[256]; - __IO uint32_t ICDIPTR[256]; - __IO uint32_t ICDICFR[64]; - uint32_t RESERVED2[128]; - __IO uint32_t ICDSGIR; + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */ + __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */ + RESERVED(0, uint32_t) + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */ + RESERVED(1[11], uint32_t) + __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */ + RESERVED(2, uint32_t) + __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */ + RESERVED(3, uint32_t) + __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */ + RESERVED(4, uint32_t) + __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */ + RESERVED(5[9], uint32_t) + __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */ + __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */ + __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */ + __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */ + __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */ + __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */ + __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */ + __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */ + RESERVED(6, uint32_t) + __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */ + RESERVED(7, uint32_t) + __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */ + __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */ + RESERVED(8[32], uint32_t) + __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */ + __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */ + RESERVED(9[3], uint32_t) + __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */ + __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */ + RESERVED(10[5236], uint32_t) + __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */ } GICDistributor_Type; -#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ +#define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */ /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC) */ typedef struct { - __IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register - __IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register - __IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register - __I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register - __IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register - __I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register - __I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register - __IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register - uint32_t RESERVED[55]; - __I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register + __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */ + __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */ + __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */ + __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */ + __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */ + __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */ + __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */ + __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */ + __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */ + __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */ + __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */ + __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */ + RESERVED(1[40], uint32_t) + __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */ + __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */ + RESERVED(2[3], uint32_t) + __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */ + RESERVED(3[960], uint32_t) + __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */ } GICInterface_Type; -#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ +#define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */ #endif -#if (__TIM_PRESENT == 1U) -#if ((__CORTEX_A == 5U)||(__CORTEX_A == 9U)) +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) /** \brief Structure type to access the Private Timer */ typedef struct { - __IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register - __IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register - __IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register - __IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register - uint32_t RESERVED[8]; - __IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register - __IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register - __IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register - __IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register - __IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register - __I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register + __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register + __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register + __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register + __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register + RESERVED(0[4], uint32_t) + __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register + __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register + __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register + __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register + __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register + __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register } Timer_Type; -#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer configuration struct */ +#define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */ #endif #endif @@ -606,60 +844,43 @@ typedef struct /* ########################## L1 Cache functions ################################# */ -/** \brief Enable Caches - - Enable Caches - */ +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ __STATIC_INLINE void L1C_EnableCaches(void) { - // Set I bit 12 to enable I Cache - // Set C bit 2 to enable D Cache - __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); + __set_SCTLR( __get_SCTLR() | (1U << SCTLR_I_Pos) | (1U << SCTLR_C_Pos)); + __ISB(); } -/** \brief Disable Caches - - Disable Caches - */ +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ __STATIC_INLINE void L1C_DisableCaches(void) { - // Clear I bit 12 to disable I Cache - // Clear C bit 2 to disable D Cache - __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); + __set_SCTLR( __get_SCTLR() & ~(1U << SCTLR_I_Pos) & ~(1U << SCTLR_C_Pos)); __ISB(); } -/** \brief Enable BTAC - - Enable BTAC - */ +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ __STATIC_INLINE void L1C_EnableBTAC(void) { - // Set Z bit 11 to enable branch prediction - __set_SCTLR( __get_SCTLR() | (1 << 11)); + __set_SCTLR( __get_SCTLR() | (1U << SCTLR_Z_Pos)); __ISB(); } -/** \brief Disable BTAC - - Disable BTAC - */ +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ __STATIC_INLINE void L1C_DisableBTAC(void) { - // Clear Z bit 11 to disable branch prediction - __set_SCTLR( __get_SCTLR() & ~(1 << 11)); + __set_SCTLR( __get_SCTLR() & ~(1U << SCTLR_Z_Pos)); + __ISB(); } /** \brief Invalidate entire branch predictor array - - BPIALL. Branch Predictor Invalidate All. - */ - +*/ __STATIC_INLINE void L1C_InvalidateBTAC(void) { __set_BPIALL(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new state } -/** \brief Invalidate the whole I$ - - ICIALLU. Instruction Cache Invalidate All to PoU +/** \brief Invalidate the whole instruction cache */ __STATIC_INLINE void L1C_InvalidateICacheAll(void) { __set_ICIALLU(0); @@ -667,27 +888,24 @@ __STATIC_INLINE void L1C_InvalidateICacheAll(void) { __ISB(); //ensure instruction fetch path sees new I cache state } -/** \brief Clean D$ by MVA - - DCCMVAC. Data cache clean by MVA to PoC +/** \brief Clean data cache line by address. +* \param [in] va Pointer to data to clear the cache for. */ __STATIC_INLINE void L1C_CleanDCacheMVA(void *va) { __set_DCCMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } -/** \brief Invalidate D$ by MVA - - DCIMVAC. Data cache invalidate by MVA to PoC +/** \brief Invalidate data cache line by address. +* \param [in] va Pointer to data to invalidate the cache for. */ __STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) { __set_DCIMVAC((uint32_t)va); __DMB(); //ensure the ordering of data cache maintenance operations and their effects } -/** \brief Clean and Invalidate D$ by MVA - - DCCIMVAC. Data cache clean and invalidate by MVA to PoC +/** \brief Clean and Invalidate data cache by address. +* \param [in] va Pointer to data to invalidate the cache for. */ __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) { __set_DCCIMVAC((uint32_t)va); @@ -695,95 +913,95 @@ __STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) { } /** \brief Clean and Invalidate the entire data or unified cache - - Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. +* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean +* \see __L1C_CleanInvalidateCache */ __STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) { - __L1C_CleanInvalidateCache(op); // compiler specific call + __L1C_CleanInvalidateCache(op); } - -/** \brief Invalidate the whole D$ - - DCISW. Invalidate by Set/Way +/** \brief Invalidate the whole data cache. */ - __STATIC_INLINE void L1C_InvalidateDCacheAll(void) { L1C_CleanInvalidateCache(0); } -/** \brief Clean the whole D$ - - DCCSW. Clean by Set/Way +/** \brief Clean the whole data cache. */ - __STATIC_INLINE void L1C_CleanDCacheAll(void) { L1C_CleanInvalidateCache(1); } -/** \brief Clean and invalidate the whole D$ - - DCCISW. Clean and Invalidate by Set/Way +/** \brief Clean and invalidate the whole data cache. */ - __STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) { L1C_CleanInvalidateCache(2); } /* ########################## L2 Cache functions ################################# */ -#if (__L2C_PRESENT == 1U) -//Cache Sync operation +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Cache Sync operation by writing CACHE_SYNC register. +*/ __STATIC_INLINE void L2C_Sync(void) { L2C_310->CACHE_SYNC = 0x0; } -//return Cache controller cache ID +/** \brief Read cache controller cache ID from CACHE_ID register. + * \return L2C_310_TypeDef::CACHE_ID + */ __STATIC_INLINE int L2C_GetID (void) { return L2C_310->CACHE_ID; } -//return Cache controller cache Type +/** \brief Read cache controller cache type from CACHE_TYPE register. +* \return L2C_310_TypeDef::CACHE_TYPE +*/ __STATIC_INLINE int L2C_GetType (void) { return L2C_310->CACHE_TYPE; } -//Invalidate all cache by way +/** \brief Invalidate all cache by way +*/ __STATIC_INLINE void L2C_InvAllByWay (void) { unsigned int assoc; - if (L2C_310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - L2C_310->INV_WAY = (1 << assoc) - 1; - while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } + + L2C_310->INV_WAY = (1U << assoc) - 1U; + while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate L2C_Sync(); } -//Clean and Invalidate all cache by way +/** \brief Clean and Invalidate all cache by way +*/ __STATIC_INLINE void L2C_CleanInvAllByWay (void) { unsigned int assoc; - if (L2C_310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; + if (L2C_310->AUX_CNT & (1U << 16U)) { + assoc = 16U; + } else { + assoc = 8U; + } - L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1; - while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate + L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U; + while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate L2C_Sync(); } -//Enable Cache +/** \brief Enable Level 2 Cache +*/ __STATIC_INLINE void L2C_Enable(void) { L2C_310->CONTROL = 0; @@ -794,28 +1012,36 @@ __STATIC_INLINE void L2C_Enable(void) L2C_310->CONTROL = 0x01; L2C_Sync(); } -//Disable Cache + +/** \brief Disable Level 2 Cache +*/ __STATIC_INLINE void L2C_Disable(void) { L2C_310->CONTROL = 0x00; L2C_Sync(); } -//Invalidate cache by physical address +/** \brief Invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ __STATIC_INLINE void L2C_InvPa (void *pa) { L2C_310->INV_LINE_PA = (unsigned int)pa; L2C_Sync(); } -//Clean cache by physical address +/** \brief Clean cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ __STATIC_INLINE void L2C_CleanPa (void *pa) { L2C_310->CLEAN_LINE_PA = (unsigned int)pa; L2C_Sync(); } -//Clean and invalidate cache by physical address +/** \brief Clean and invalidate cache by physical address +* \param [in] pa Pointer to data to invalidate cache for. +*/ __STATIC_INLINE void L2C_CleanInvPa (void *pa) { L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa; @@ -824,159 +1050,315 @@ __STATIC_INLINE void L2C_CleanInvPa (void *pa) #endif /* ########################## GIC functions ###################################### */ -#if (__GIC_PRESENT == 1U) +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) +/** \brief Enable the interrupt distributor using the GIC's CTLR register. +*/ __STATIC_INLINE void GIC_EnableDistributor(void) { - GICDistributor->ICDDCR |= 1; //enable distributor + GICDistributor->CTLR |= 1U; } +/** \brief Disable the interrupt distributor using the GIC's CTLR register. +*/ __STATIC_INLINE void GIC_DisableDistributor(void) { - GICDistributor->ICDDCR &=~1; //disable distributor + GICDistributor->CTLR &=~1U; } +/** \brief Read the GIC's TYPER register. +* \return GICDistributor_Type::TYPER +*/ __STATIC_INLINE uint32_t GIC_DistributorInfo(void) { - return (uint32_t)(GICDistributor->ICDICTR); + return (GICDistributor->TYPER); } +/** \brief Reads the GIC's IIDR register. +* \return GICDistributor_Type::IIDR +*/ __STATIC_INLINE uint32_t GIC_DistributorImplementer(void) { - return (uint32_t)(GICDistributor->ICDIIDR); + return (GICDistributor->IIDR); } +/** \brief Sets the GIC's ITARGETSR register for the given interrupt. +* \param [in] IRQn Interrupt to be configured. +* \param [in] cpu_target CPU interfaces to assign this interrupt to. +*/ __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) { - char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - *field = (char)cpu_target & 0xf; -} - -__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn) -{ - uint32_t i, num_irq; - - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - for (i = 0; i < (num_irq/16); i++) - { - GICDistributor->ICDISPR[i] = *ICDICFRn++; - } + uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); } +/** \brief Read the GIC's ITARGETSR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return GICDistributor_Type::ITARGETSR +*/ __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn) { - char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - return ((uint32_t)*field & 0xf); + return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; } +/** \brief Enable the CPU's interrupt interface. +*/ __STATIC_INLINE void GIC_EnableInterface(void) { - GICInterface->ICCICR |= 1; //enable interface + GICInterface->CTLR |= 1U; //enable interface } +/** \brief Disable the CPU's interrupt interface. +*/ __STATIC_INLINE void GIC_DisableInterface(void) { - GICInterface->ICCICR &=~1; //disable distributor + GICInterface->CTLR &=~1U; //disable distributor } +/** \brief Read the CPU's IAR register. +* \return GICInterface_Type::IAR +*/ __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void) { - return (IRQn_Type)(GICInterface->ICCIAR); + return (IRQn_Type)(GICInterface->IAR); } +/** \brief Writes the given interrupt number to the CPU's EOIR register. +* \param [in] IRQn The interrupt to be signaled as finished. +*/ __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn) { - GICInterface->ICCEOIR = IRQn; + GICInterface->EOIR = IRQn; } +/** \brief Enables the given interrupt using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be enabled. +*/ __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn) { - GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); + GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U); } +/** \brief Get interrupt enable status using GIC's ISENABLER register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not enabled, 1 - interrupt is enabled. +*/ +__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn) +{ + return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL; +} + +/** \brief Disables the given interrupt using GIC's ICENABLER register. +* \param [in] IRQn The interrupt to be disabled. +*/ __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn) { - GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); + GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U); } +/** \brief Get interrupt pending status from GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - interrupt is not pending, 1 - interrupt is pendig. +*/ +__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn) +{ + uint32_t pend; + + if (IRQn >= 16U) { + pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; + } else { + // INTID 0-15 Software Generated Interrupt + pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; + // No CPU identification offered + if (pend != 0U) { + pend = 1U; + } else { + pend = 0U; + } + } + + return (pend); +} + +/** \brief Sets the given interrupt as pending using GIC's ISPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn) { - GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); + if (IRQn >= 16U) { + GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + // Forward the interrupt to the CPU interface that requested it + GICDistributor->SGIR = (IRQn | 0x02000000U); + } } +/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register. +* \param [in] IRQn The interrupt to be enabled. +*/ __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn) { - GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); + if (IRQn >= 16U) { + GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U); + } else { + // INTID 0-15 Software Generated Interrupt + GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U); + } } -__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) -{ - // Word-size read/writes must be used to access this register - volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]); - unsigned bit_shift = (IRQn % 16)<<1; - unsigned int save_word; +/** \brief Sets the interrupt configuration using GIC's ICFGR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config) +{ + uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U]; + uint32_t shift = (IRQn % 16U) << 1U; - save_word = *field; - save_word &= (~(3 << bit_shift)); + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICDistributor->ICFGR[IRQn / 16U] = icfgr; +} - *field = (save_word | (((edge_level<<1) | model) << bit_shift)); +/** \brief Get the interrupt configuration from the GIC's ICFGR register. +* \param [in] IRQn Interrupt to acquire the configuration for. +* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1) +* Bit 1: 0 - level sensitive, 1 - edge triggered +*/ +__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn) +{ + return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U)); } +/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be configured. +* \param [in] priority The priority for the interrupt, lower values denote higher priorities. +*/ __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += IRQn % 4; - *field = (char)priority; + uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); + GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U)); } +/** \brief Read the current interrupt priority from GIC's IPRIORITYR register. +* \param [in] IRQn The interrupt to be queried. +*/ __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn) { - char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += IRQn % 4; - return (uint32_t)*field; + return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; } -__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority) +/** \brief Set the interrupt priority mask using CPU's PMR register. +* \param [in] priority Priority mask to be set. +*/ +__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority) { - GICInterface->ICCPMR = priority & 0xff; //set priority mask + GICInterface->PMR = priority & 0xFFUL; //set priority mask } +/** \brief Read the current interrupt priority mask from CPU's PMR register. +* \result GICInterface_Type::PMR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void) +{ + return GICInterface->PMR; +} + +/** \brief Configures the group priority and subpriority split point using CPU's BPR register. +* \param [in] binary_point Amount of bits used as subpriority. +*/ __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point) { - GICInterface->ICCBPR = binary_point & 0x07; //set binary point + GICInterface->BPR = binary_point & 7U; //set binary point } -__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point) +/** \brief Read the current group priority and subpriority split point from CPU's BPR register. +* \return GICInterface_Type::BPR +*/ +__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void) { - return (uint32_t)GICInterface->ICCBPR; + return GICInterface->BPR; } +/** \brief Get the status for a given interrupt. +* \param [in] IRQn The interrupt to get status for. +* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active +*/ __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) { uint32_t pending, active; - active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; + pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL; - return ((active<<1) | pending); + return ((active<<1U) | pending); } +/** \brief Generate a software interrupt using GIC's SGIR register. +* \param [in] IRQn Software interrupt to be generated. +* \param [in] target_list List of CPUs the software interrupt should be forwarded to. +* \param [in] filter_list Filter to be applied to determine interrupt receivers. +*/ __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) { - GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); + GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL); +} + +/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. +* \return GICInterface_Type::HPPIR +*/ +__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void) +{ + return GICInterface->HPPIR; +} + +/** \brief Provides information about the implementer and revision of the CPU interface. +* \return GICInterface_Type::IIDR +*/ +__STATIC_INLINE uint32_t GIC_GetInterfaceId(void) +{ + return GICInterface->IIDR; +} + +/** \brief Set the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group) +{ + uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U]; + uint32_t shift = (IRQn % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICDistributor->IGROUPR[IRQn / 32U] = igroupr; +} +#define GIC_SetSecurity GIC_SetGroup + +/** \brief Get the interrupt group from the GIC's IGROUPR register. +* \param [in] IRQn The interrupt to be queried. +* \return 0 - Group 0, 1 - Group 1 +*/ +__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn) +{ + return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL; } +#define GIC_GetSecurity GIC_GetGroup +/** \brief Initialize the interrupt distributor. +*/ __STATIC_INLINE void GIC_DistInit(void) { IRQn_Type i; uint32_t num_irq = 0; uint32_t priority_field; - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, //configuring all of the interrupts as Secure. //Disable interrupt forwarding @@ -985,7 +1367,7 @@ __STATIC_INLINE void GIC_DistInit(void) num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR priority field and read back the value stored.*/ GIC_SetPriority((IRQn_Type)0, 0xff); priority_field = GIC_GetPriority((IRQn_Type)0); @@ -994,8 +1376,10 @@ __STATIC_INLINE void GIC_DistInit(void) { //Disable the SPI interrupt GIC_DisableIRQ(i); - //Set level-sensitive and 1-N model - GIC_SetLevelModel(i, 0, 1); + if (i > 15) { + //Set level-sensitive (and N-N model) + GIC_SetConfiguration(i, 0); + } //Set priority GIC_SetPriority(i, priority_field/2); //Set target list to CPU0 @@ -1005,19 +1389,21 @@ __STATIC_INLINE void GIC_DistInit(void) GIC_EnableDistributor(); } +/** \brief Initialize the CPU's interrupt interface +*/ __STATIC_INLINE void GIC_CPUInterfaceInit(void) { IRQn_Type i; uint32_t priority_field; - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0, //configuring all of the interrupts as Secure. //Disable interrupt forwarding GIC_DisableInterface(); /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR + To determine the number of priority bits implemented write 0xFF to an IPRIORITYR priority field and read back the value stored.*/ GIC_SetPriority((IRQn_Type)0, 0xff); priority_field = GIC_GetPriority((IRQn_Type)0); @@ -1025,22 +1411,25 @@ __STATIC_INLINE void GIC_CPUInterfaceInit(void) //SGI and PPI for (i = (IRQn_Type)0; i < 32; i++) { - //Set level-sensitive and 1-N model for PPI - if(i > 15) - GIC_SetLevelModel(i, 0, 1); - //Disable SGI and PPI interrupts - GIC_DisableIRQ(i); - //Set priority - GIC_SetPriority(i, priority_field/2); + if(i > 15) { + //Set level-sensitive (and N-N model) for PPI + GIC_SetConfiguration(i, 0U); + } + //Disable SGI and PPI interrupts + GIC_DisableIRQ(i); + //Set priority + GIC_SetPriority(i, priority_field/2); } //Enable interface GIC_EnableInterface(); //Set binary point to 0 GIC_SetBinaryPoint(0); //Set priority mask - GIC_InterfacePriorityMask(0xff); + GIC_SetInterfacePriorityMask(0xff); } +/** \brief Initialize and enable the GIC +*/ __STATIC_INLINE void GIC_Enable(void) { GIC_DistInit(); @@ -1049,47 +1438,129 @@ __STATIC_INLINE void GIC_Enable(void) #endif /* ########################## Generic Timer functions ############################ */ -#if (__TIM_PRESENT == 1U) +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) /* PL1 Physical Timer */ -#if (__CORTEX_A == 7U) -__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) { +#if (__CORTEX_A == 7U) || defined(DOXYGEN) + +/** \brief Physical Timer Control register */ +typedef union +{ + struct + { + uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */ + uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */ + uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */ + RESERVED(0:29, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CNTP_CTL_Type; + +/** \brief Configures the frequency the timer shall run at. +* \param [in] value The timer frequency in Hz. +*/ +__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value) +{ + __set_CNTFRQ(value); + __ISB(); +} + +/** \brief Sets the reset value of the timer. +* \param [in] value The value the timer is loaded with. +*/ +__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) +{ __set_CNTP_TVAL(value); __ISB(); } -__STATIC_INLINE uint32_t PL1_GetCurrentValue() { +/** \brief Get the current counter value. +* \return Current counter value. +*/ +__STATIC_INLINE uint32_t PL1_GetCurrentValue() +{ return(__get_CNTP_TVAL()); } -__STATIC_INLINE void PL1_SetControl(uint32_t value) { +/** \brief Configure the timer by setting the control value. +* \param [in] value New timer control value. +*/ +__STATIC_INLINE void PL1_SetControl(uint32_t value) +{ __set_CNTP_CTL(value); __ISB(); } +/** \brief Get the control value. +* \return Control value. +*/ +__STATIC_INLINE uint32_t PL1_GetControl() +{ + return(__get_CNTP_CTL()); +} +#endif + /* Private Timer */ -#elif ((__CORTEX_A == 5U)||(__CORTEX_A == 9U)) -__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) { +#if ((__CORTEX_A == 5U) || (__CORTEX_A == 9U)) || defined(DOXYGEN) +/** \brief Set the load value to timers LOAD register. +* \param [in] value The load value to be set. +*/ +__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) +{ PTIM->LOAD = value; } -__STATIC_INLINE uint32_t PTIM_GetLoadValue() { +/** \brief Get the load value from timers LOAD register. +* \return Timer_Type::LOAD +*/ +__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) +{ return(PTIM->LOAD); } -__STATIC_INLINE uint32_t PTIM_GetCurrentValue() { +/** \brief Set current counter value from its COUNTER register. +*/ +__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) +{ + PTIM->COUNTER = value; +} + +/** \brief Get current counter value from timers COUNTER register. +* \result Timer_Type::COUNTER +*/ +__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) +{ return(PTIM->COUNTER); } -__STATIC_INLINE void PTIM_SetControl(uint32_t value) { +/** \brief Configure the timer using its CONTROL register. +* \param [in] value The new configuration value to be set. +*/ +__STATIC_INLINE void PTIM_SetControl(uint32_t value) +{ PTIM->CONTROL = value; } -__STATIC_INLINE uint32_t PTIM_GetControl(void) { +/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register. +* \return Timer_Type::CONTROL +*/ +__STATIC_INLINE uint32_t PTIM_GetControl(void) +{ return(PTIM->CONTROL); } -__STATIC_INLINE void PTIM_ClearEventFlag(void) { +/** ref Timer_Type::CONTROL Get the event flag in timers ISR register. +* \return 0 - flag is not set, 1- flag is set +*/ +__STATIC_INLINE uint32_t PTIM_GetEventFlag(void) +{ + return (PTIM->ISR & 1UL); +} + +/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register. +*/ +__STATIC_INLINE void PTIM_ClearEventFlag(void) +{ PTIM->ISR = 1; } #endif @@ -1974,10 +2445,9 @@ __STATIC_INLINE void MMU_TTPage64k(uint32_t *ttb, uint32_t base_address, uint32_ } /** \brief Enable MMU - - Enable MMU */ -__STATIC_INLINE void MMU_Enable(void) { +__STATIC_INLINE void MMU_Enable(void) +{ // Set M bit 0 to enable the MMU // Set AFE bit to enable simplified access permissions model // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking @@ -1986,21 +2456,19 @@ __STATIC_INLINE void MMU_Enable(void) { } /** \brief Disable MMU - - Disable MMU */ -__STATIC_INLINE void MMU_Disable(void) { +__STATIC_INLINE void MMU_Disable(void) +{ // Clear M bit 0 to disable the MMU __set_SCTLR( __get_SCTLR() & ~1); __ISB(); } /** \brief Invalidate entire unified TLB - - TLBIALL. Invalidate entire unified TLB */ -__STATIC_INLINE void MMU_InvalidateTLB(void) { +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ __set_TLBIALL(0); __DSB(); //ensure completion of the invalidation __ISB(); //ensure instruction fetch path sees new state diff --git a/cmsis/TARGET_CORTEX_A/core_ca9.h b/cmsis/TARGET_CORTEX_A/core_ca9.h deleted file mode 100644 index c7c402d7508..00000000000 --- a/cmsis/TARGET_CORTEX_A/core_ca9.h +++ /dev/null @@ -1,276 +0,0 @@ -/**************************************************************************//** - * @file core_ca9.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 25 March 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CA9_H_GENERIC -#define __CORE_CA9_H_GENERIC - - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_A9 - @{ - */ - -/* CMSIS CA9 definitions */ -#define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \ - __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_A (0x09) /*!< Cortex-A Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - #define __STATIC_ASM static __asm - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - #define __STATIC_ASM static __asm - -#include -inline uint32_t __get_PSR(void) { - __ASM("mrs r0, cpsr"); -} - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - #define __STATIC_ASM static __asm - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - #define __STATIC_ASM static __asm - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - #define __STATIC_ASM static __asm - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /*!< standard types definitions */ -#include "core_caInstr.h" /*!< Core Instruction Access */ -#include "core_caFunc.h" /*!< Core Function Access */ -#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CA9_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CA9_H_DEPENDANT -#define __CORE_CA9_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CA9_REV - #define __CA9_REV 0x0000 - #warning "__CA9_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 1 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 1 - #endif - - #if __Vendor_SysTickConfig == 0 - #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_A9 */ - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-A processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t reserved1:7; /*!< bit: 20..23 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/*@} end of group CMSIS_CORE */ - -/*@} end of CMSIS_Core_FPUFunctions */ - - -#endif /* __CORE_CA9_H_GENERIC */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} - - -#endif diff --git a/cmsis/TARGET_CORTEX_A/core_caFunc.h b/cmsis/TARGET_CORTEX_A/core_caFunc.h deleted file mode 100644 index 6e473214b68..00000000000 --- a/cmsis/TARGET_CORTEX_A/core_caFunc.h +++ /dev/null @@ -1,1444 +0,0 @@ -/**************************************************************************//** - * @file core_caFunc.h - * @brief CMSIS Cortex-A Core Function Access Header File - * @version V3.10 - * @date 30 Oct 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CAFUNC_H__ -#define __CORE_CAFUNC_H__ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -#define MODE_USR 0x10 -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_MON 0x16 -#define MODE_ABT 0x17 -#define MODE_HYP 0x1A -#define MODE_UND 0x1B -#define MODE_SYS 0x1F - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get CPSR Register - - This function returns the content of the CPSR Register. - - \return CPSR Register value - */ -__STATIC_INLINE uint32_t __get_CPSR(void) -{ - register uint32_t __regCPSR __ASM("cpsr"); - return(__regCPSR); -} - -/** \brief Set Stack Pointer - - This function assigns the given value to the current stack pointer. - - \param [in] topOfStack Stack Pointer value to set - */ -register uint32_t __regSP __ASM("sp"); -__STATIC_INLINE void __set_SP(uint32_t topOfStack) -{ - __regSP = topOfStack; -} - - -/** \brief Get link register - - This function returns the value of the link register - - \return Value of link register - */ -register uint32_t __reglr __ASM("lr"); -__STATIC_INLINE uint32_t __get_LR(void) -{ - return(__reglr); -} - -/** \brief Set link register - - This function sets the value of the link register - - \param [in] lr LR value to set - */ -__STATIC_INLINE void __set_LR(uint32_t lr) -{ - __reglr = lr; -} - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the USR/SYS Stack Pointer (PSP). - - \param [in] topOfProcStack USR/SYS Stack Pointer value to set - */ -__STATIC_ASM void __set_PSP(uint32_t topOfProcStack) -{ - ARM - PRESERVE8 - - BIC R0, R0, #7 ;ensure stack is 8-byte aligned - MRS R1, CPSR - CPS #MODE_SYS ;no effect in USR mode - MOV SP, R0 - MSR CPSR_c, R1 ;no effect in USR mode - ISB - BX LR - -} - -/** \brief Set User Mode - - This function changes the processor state to User Mode - */ -__STATIC_ASM void __set_CPS_USR(void) -{ - ARM - - CPS #MODE_USR - BX LR -} - - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -/** \brief Get FPEXC - - This function returns the current value of the Floating Point Exception Control register. - - \return Floating Point Exception Control register value - */ -__STATIC_INLINE uint32_t __get_FPEXC(void) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpexc __ASM("fpexc"); - return(__regfpexc); -#else - return(0); -#endif -} - - -/** \brief Set FPEXC - - This function assigns the given value to the Floating Point Exception Control register. - - \param [in] fpscr Floating Point Exception Control value to set - */ -__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpexc __ASM("fpexc"); - __regfpexc = (fpexc); -#endif -} - -/** \brief Get CPACR - - This function returns the current value of the Coprocessor Access Control register. - - \return Coprocessor Access Control register value - */ -__STATIC_INLINE uint32_t __get_CPACR(void) -{ - register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); - return __regCPACR; -} - -/** \brief Set CPACR - - This function assigns the given value to the Coprocessor Access Control register. - - \param [in] cpacr Coprocessor Acccess Control value to set - */ -__STATIC_INLINE void __set_CPACR(uint32_t cpacr) -{ - register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); - __regCPACR = cpacr; - __ISB(); -} - -/** \brief Get CBAR - - This function returns the value of the Configuration Base Address register. - - \return Configuration Base Address register value - */ -__STATIC_INLINE uint32_t __get_CBAR() { - register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); - return(__regCBAR); -} - -/** \brief Get TTBR0 - - This function returns the value of the Translation Table Base Register 0. - - \return Translation Table Base Register 0 value - */ -__STATIC_INLINE uint32_t __get_TTBR0() { - register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); - return(__regTTBR0); -} - -/** \brief Set TTBR0 - - This function assigns the given value to the Translation Table Base Register 0. - - \param [in] ttbr0 Translation Table Base Register 0 value to set - */ -__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { - register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); - __regTTBR0 = ttbr0; - __ISB(); -} - -/** \brief Get DACR - - This function returns the value of the Domain Access Control Register. - - \return Domain Access Control Register value - */ -__STATIC_INLINE uint32_t __get_DACR() { - register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); - return(__regDACR); -} - -/** \brief Set DACR - - This function assigns the given value to the Domain Access Control Register. - - \param [in] dacr Domain Access Control Register value to set - */ -__STATIC_INLINE void __set_DACR(uint32_t dacr) { - register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); - __regDACR = dacr; - __ISB(); -} - -/******************************** Cache and BTAC enable ****************************************************/ - -/** \brief Set SCTLR - - This function assigns the given value to the System Control Register. - - \param [in] sctlr System Control Register value to set - */ -__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) -{ - register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); - __regSCTLR = sctlr; -} - -/** \brief Get SCTLR - - This function returns the value of the System Control Register. - - \return System Control Register value - */ -__STATIC_INLINE uint32_t __get_SCTLR() { - register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); - return(__regSCTLR); -} - -/** \brief Enable Caches - - Enable Caches - */ -__STATIC_INLINE void __enable_caches(void) { - // Set I bit 12 to enable I Cache - // Set C bit 2 to enable D Cache - __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); -} - -/** \brief Disable Caches - - Disable Caches - */ -__STATIC_INLINE void __disable_caches(void) { - // Clear I bit 12 to disable I Cache - // Clear C bit 2 to disable D Cache - __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); - __ISB(); -} - -/** \brief Enable BTAC - - Enable BTAC - */ -__STATIC_INLINE void __enable_btac(void) { - // Set Z bit 11 to enable branch prediction - __set_SCTLR( __get_SCTLR() | (1 << 11)); - __ISB(); -} - -/** \brief Disable BTAC - - Disable BTAC - */ -__STATIC_INLINE void __disable_btac(void) { - // Clear Z bit 11 to disable branch prediction - __set_SCTLR( __get_SCTLR() & ~(1 << 11)); -} - - -/** \brief Enable MMU - - Enable MMU - */ -__STATIC_INLINE void __enable_mmu(void) { - // Set M bit 0 to enable the MMU - // Set AFE bit to enable simplified access permissions model - // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking - __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); - __ISB(); -} - -/** \brief Disable MMU - - Disable MMU - */ -__STATIC_INLINE void __disable_mmu(void) { - // Clear M bit 0 to disable the MMU - __set_SCTLR( __get_SCTLR() & ~1); - __ISB(); -} - -/******************************** TLB maintenance operations ************************************************/ -/** \brief Invalidate the whole tlb - - TLBIALL. Invalidate the whole tlb - */ - -__STATIC_INLINE void __ca9u_inv_tlb_all(void) { - register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); - __TLBIALL = 0; - __DSB(); - __ISB(); -} - -/******************************** BTB maintenance operations ************************************************/ -/** \brief Invalidate entire branch predictor array - - BPIALL. Branch Predictor Invalidate All. - */ - -__STATIC_INLINE void __v7_inv_btac(void) { - register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); - __BPIALL = 0; - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new state -} - - -/******************************** L1 cache operations ******************************************************/ - -/** \brief Invalidate the whole I$ - - ICIALLU. Instruction Cache Invalidate All to PoU - */ -__STATIC_INLINE void __v7_inv_icache_all(void) { - register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); - __ICIALLU = 0; - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new I cache state -} - -/** \brief Clean D$ by MVA - - DCCMVAC. Data cache clean by MVA to PoC - */ -__STATIC_INLINE void __v7_clean_dcache_mva(void *va) { - register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); - __DCCMVAC = (uint32_t)va; - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Invalidate D$ by MVA - - DCIMVAC. Data cache invalidate by MVA to PoC - */ -__STATIC_INLINE void __v7_inv_dcache_mva(void *va) { - register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); - __DCIMVAC = (uint32_t)va; - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Clean and Invalidate D$ by MVA - - DCCIMVAC. Data cache clean and invalidate by MVA to PoC - */ -__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { - register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); - __DCCIMVAC = (uint32_t)va; - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Clean and Invalidate the entire data or unified cache - - Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. - */ -#pragma push -#pragma arm -__STATIC_ASM void __v7_all_cache(uint32_t op) { - ARM - - PUSH {R4-R11} - - MRC p15, 1, R6, c0, c0, 1 // Read CLIDR - ANDS R3, R6, #0x07000000 // Extract coherency level - MOV R3, R3, LSR #23 // Total cache levels << 1 - BEQ Finished // If 0, no need to clean - - MOV R10, #0 // R10 holds current cache level << 1 -Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position - MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level - AND R1, R1, #7 // Isolate those lower 3 bits - CMP R1, #2 - BLT Skip // No cache or only instruction cache at this level - - MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register - ISB // ISB to sync the change to the CacheSizeID reg - MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register - AND R2, R1, #7 // Extract the line length field - ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) - LDR R4, =0x3FF - ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) - CLZ R5, R4 // R5 is the bit position of the way size increment - LDR R7, =0x7FFF - ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) - -Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) - -Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 - ORR R11, R11, R7, LSL R2 // Factor in the Set number - CMP R0, #0 - BNE Dccsw - MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way - B cont -Dccsw CMP R0, #1 - BNE Dccisw - MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way - B cont -Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way -cont SUBS R9, R9, #1 // Decrement the Way number - BGE Loop3 - SUBS R7, R7, #1 // Decrement the Set number - BGE Loop2 -Skip ADD R10, R10, #2 // Increment the cache number - CMP R3, R10 - BGT Loop1 - -Finished - DSB - POP {R4-R11} - BX lr - -} -#pragma pop - - -/** \brief Invalidate the whole D$ - - DCISW. Invalidate by Set/Way - */ - -__STATIC_INLINE void __v7_inv_dcache_all(void) { - __v7_all_cache(0); -} - -/** \brief Clean the whole D$ - - DCCSW. Clean by Set/Way - */ - -__STATIC_INLINE void __v7_clean_dcache_all(void) { - __v7_all_cache(1); -} - -/** \brief Clean and invalidate the whole D$ - - DCCISW. Clean and Invalidate by Set/Way - */ - -__STATIC_INLINE void __v7_clean_inv_dcache_all(void) { - __v7_all_cache(2); -} - -#include "core_ca_mmu.h" - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ - -#define __inline inline - -inline static uint32_t __disable_irq_iar() { - int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I - __disable_irq(); - return irq_dis; -} - -#define MODE_USR 0x10 -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_MON 0x16 -#define MODE_ABT 0x17 -#define MODE_HYP 0x1A -#define MODE_UND 0x1B -#define MODE_SYS 0x1F - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the USR/SYS Stack Pointer (PSP). - - \param [in] topOfProcStack USR/SYS Stack Pointer value to set - */ -// from rt_CMSIS.c -__arm static inline void __set_PSP(uint32_t topOfProcStack) { -__asm( - " ARM\n" -// " PRESERVE8\n" - - " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n" - " MRS R1, CPSR \n" - " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS - " MOV SP, R0 \n" - " MSR CPSR_c, R1 ;no effect in USR mode \n" - " ISB \n" - " BX LR \n"); -} - -/** \brief Set User Mode - - This function changes the processor state to User Mode - */ -// from rt_CMSIS.c -__arm static inline void __set_CPS_USR(void) { -__asm( - " ARM \n" - - " CPS #0x10 \n" // MODE_USR - " BX LR\n"); -} - -/** \brief Set TTBR0 - - This function assigns the given value to the Translation Table Base Register 0. - - \param [in] ttbr0 Translation Table Base Register 0 value to set - */ -// from mmu_Renesas_RZ_A1.c -__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { - __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15 - __ISB(); -} - -/** \brief Set DACR - - This function assigns the given value to the Domain Access Control Register. - - \param [in] dacr Domain Access Control Register value to set - */ -// from mmu_Renesas_RZ_A1.c -__STATIC_INLINE void __set_DACR(uint32_t dacr) { - __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15 - __ISB(); -} - - -/******************************** Cache and BTAC enable ****************************************************/ -/** \brief Set SCTLR - - This function assigns the given value to the System Control Register. - - \param [in] sctlr System Control Register value to set - */ -// from __enable_mmu() -__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) { - __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15 -} - -/** \brief Get SCTLR - - This function returns the value of the System Control Register. - - \return System Control Register value - */ -// from __enable_mmu() -__STATIC_INLINE uint32_t __get_SCTLR() { - uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0); - return __regSCTLR; -} - -/** \brief Enable Caches - - Enable Caches - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __enable_caches(void) { - __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); -} - -/** \brief Enable BTAC - - Enable BTAC - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __enable_btac(void) { - __set_SCTLR( __get_SCTLR() | (1 << 11)); - __ISB(); -} - -/** \brief Enable MMU - - Enable MMU - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __enable_mmu(void) { - // Set M bit 0 to enable the MMU - // Set AFE bit to enable simplified access permissions model - // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking - __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); - __ISB(); -} - -/******************************** TLB maintenance operations ************************************************/ -/** \brief Invalidate the whole tlb - - TLBIALL. Invalidate the whole tlb - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __ca9u_inv_tlb_all(void) { - uint32_t val = 0; - __MCR(15, 0, val, 8, 7, 0); // reg to cp15 - __MCR(15, 0, val, 8, 6, 0); // reg to cp15 - __MCR(15, 0, val, 8, 5, 0); // reg to cp15 - __DSB(); - __ISB(); -} - -/******************************** BTB maintenance operations ************************************************/ -/** \brief Invalidate entire branch predictor array - - BPIALL. Branch Predictor Invalidate All. - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __v7_inv_btac(void) { - uint32_t val = 0; - __MCR(15, 0, val, 7, 5, 6); // reg to cp15 - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new state -} - - -/******************************** L1 cache operations ******************************************************/ - -/** \brief Invalidate the whole I$ - - ICIALLU. Instruction Cache Invalidate All to PoU - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __v7_inv_icache_all(void) { - uint32_t val = 0; - __MCR(15, 0, val, 7, 5, 0); // reg to cp15 - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new I cache state -} - -// from __v7_inv_dcache_all() -__arm static inline void __v7_all_cache(uint32_t op) { -__asm( - " ARM \n" - - " PUSH {R4-R11} \n" - - " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR - " ANDS R3, R6, #0x07000000\n" // Extract coherency level - " MOV R3, R3, LSR #23\n" // Total cache levels << 1 - " BEQ Finished\n" // If 0, no need to clean - - " MOV R10, #0\n" // R10 holds current cache level << 1 - "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position - " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level - " AND R1, R1, #7 \n" // Isolate those lower 3 bits - " CMP R1, #2 \n" - " BLT Skip \n" // No cache or only instruction cache at this level - - " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register - " ISB \n" // ISB to sync the change to the CacheSizeID reg - " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register - " AND R2, R1, #7 \n" // Extract the line length field - " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes) - " movw R4, #0x3FF \n" - " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned) - " CLZ R5, R4 \n" // R5 is the bit position of the way size increment - " movw R7, #0x7FFF \n" - " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned) - - "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned) - - "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11 - " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number - " CMP R0, #0 \n" - " BNE Dccsw \n" - " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way - " B cont \n" - "Dccsw: CMP R0, #1 \n" - " BNE Dccisw \n" - " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way - " B cont \n" - "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way - "cont: SUBS R9, R9, #1 \n" // Decrement the Way number - " BGE Loop3 \n" - " SUBS R7, R7, #1 \n" // Decrement the Set number - " BGE Loop2 \n" - "Skip: ADD R10, R10, #2 \n" // increment the cache number - " CMP R3, R10 \n" - " BGT Loop1 \n" - - "Finished: \n" - " DSB \n" - " POP {R4-R11} \n" - " BX lr \n" ); -} - -/** \brief Invalidate the whole D$ - - DCISW. Invalidate by Set/Way - */ -// from system_Renesas_RZ_A1.c -__STATIC_INLINE void __v7_inv_dcache_all(void) { - __v7_all_cache(0); -} -/** \brief Clean the whole D$ - - DCCSW. Clean by Set/Way - */ - -__STATIC_INLINE void __v7_clean_dcache_all(void) { - __v7_all_cache(1); -} - -/** \brief Clean and invalidate the whole D$ - - DCCISW. Clean and Invalidate by Set/Way - */ - -__STATIC_INLINE void __v7_clean_inv_dcache_all(void) { - __v7_all_cache(2); -} -/** \brief Clean and Invalidate D$ by MVA - - DCCIMVAC. Data cache clean and invalidate by MVA to PoC - */ -__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { - __MCR(15, 0, (uint32_t)va, 7, 14, 1); - __DMB(); -} - -#include "core_ca_mmu.h" - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -#define MODE_USR 0x10 -#define MODE_FIQ 0x11 -#define MODE_IRQ 0x12 -#define MODE_SVC 0x13 -#define MODE_MON 0x16 -#define MODE_ABT 0x17 -#define MODE_HYP 0x1A -#define MODE_UND 0x1B -#define MODE_SYS 0x1F - - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void) -{ - uint32_t result; - - __ASM volatile ("mrs %0, cpsr" : "=r" (result)); - __ASM volatile ("cpsid i"); - return(result & 0x80); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ -#if 1 - register uint32_t __regAPSR; - __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) ); -#else - register uint32_t __regAPSR __ASM("apsr"); -#endif - return(__regAPSR); -} - - -/** \brief Get CPSR Register - - This function returns the content of the CPSR Register. - - \return CPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) -{ -#if 1 - register uint32_t __regCPSR; - __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR)); -#else - register uint32_t __regCPSR __ASM("cpsr"); -#endif - return(__regCPSR); -} - -#if 0 -/** \brief Set Stack Pointer - - This function assigns the given value to the current stack pointer. - - \param [in] topOfStack Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack) -{ - register uint32_t __regSP __ASM("sp"); - __regSP = topOfStack; -} -#endif - -/** \brief Get link register - - This function returns the value of the link register - - \return Value of link register - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void) -{ - register uint32_t __reglr __ASM("lr"); - return(__reglr); -} - -#if 0 -/** \brief Set link register - - This function sets the value of the link register - - \param [in] lr LR value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr) -{ - register uint32_t __reglr __ASM("lr"); - __reglr = lr; -} -#endif - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the USR/SYS Stack Pointer (PSP). - - \param [in] topOfProcStack USR/SYS Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __asm__ volatile ( - ".ARM;" - ".eabi_attribute Tag_ABI_align8_preserved,1;" - - "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */ - "MRS R1, CPSR;" - "CPS %0;" /* ;no effect in USR mode */ - "MOV SP, R0;" - "MSR CPSR_c, R1;" /* ;no effect in USR mode */ - "ISB;" - //"BX LR;" - : - : "i"(MODE_SYS) - : "r0", "r1"); - return; -} - -/** \brief Set User Mode - - This function changes the processor state to User Mode - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void) -{ - __asm__ volatile ( - ".ARM;" - - "CPS %0;" - //"BX LR;" - : - : "i"(MODE_USR) - : ); - return; -} - - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq() __asm__ volatile ("cpsie f") - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq() __asm__ volatile ("cpsid f") - - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -#if 1 - uint32_t result; - - __ASM volatile ("vmrs %0, fpscr" : "=r" (result) ); - return (result); -#else - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#endif -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) -#if 1 - __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) ); -#else - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -#endif -} - -/** \brief Get FPEXC - - This function returns the current value of the Floating Point Exception Control register. - - \return Floating Point Exception Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) -{ -#if (__FPU_PRESENT == 1) -#if 1 - uint32_t result; - - __ASM volatile ("vmrs %0, fpexc" : "=r" (result)); - return (result); -#else - register uint32_t __regfpexc __ASM("fpexc"); - return(__regfpexc); -#endif -#else - return(0); -#endif -} - - -/** \brief Set FPEXC - - This function assigns the given value to the Floating Point Exception Control register. - - \param [in] fpscr Floating Point Exception Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) -{ -#if (__FPU_PRESENT == 1) -#if 1 - __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc)); -#else - register uint32_t __regfpexc __ASM("fpexc"); - __regfpexc = (fpexc); -#endif -#endif -} - -/** \brief Get CPACR - - This function returns the current value of the Coprocessor Access Control register. - - \return Coprocessor Access Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void) -{ -#if 1 - register uint32_t __regCPACR; - __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR)); -#else - register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); -#endif - return __regCPACR; -} - -/** \brief Set CPACR - - This function assigns the given value to the Coprocessor Access Control register. - - \param [in] cpacr Coprocessor Acccess Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr) -{ -#if 1 - __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr)); -#else - register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); - __regCPACR = cpacr; -#endif - __ISB(); -} - -/** \brief Get CBAR - - This function returns the value of the Configuration Base Address register. - - \return Configuration Base Address register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() { -#if 1 - register uint32_t __regCBAR; - __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR)); -#else - register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); -#endif - return(__regCBAR); -} - -/** \brief Get TTBR0 - - This function returns the value of the Translation Table Base Register 0. - - \return Translation Table Base Register 0 value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() { -#if 1 - register uint32_t __regTTBR0; - __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0)); -#else - register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); -#endif - return(__regTTBR0); -} - -/** \brief Set TTBR0 - - This function assigns the given value to the Translation Table Base Register 0. - - \param [in] ttbr0 Translation Table Base Register 0 value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0)); -#else - register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); - __regTTBR0 = ttbr0; -#endif - __ISB(); -} - -/** \brief Get DACR - - This function returns the value of the Domain Access Control Register. - - \return Domain Access Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() { -#if 1 - register uint32_t __regDACR; - __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR)); -#else - register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); -#endif - return(__regDACR); -} - -/** \brief Set DACR - - This function assigns the given value to the Domain Access Control Register. - - \param [in] dacr Domain Access Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr)); -#else - register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); - __regDACR = dacr; -#endif - __ISB(); -} - -/******************************** Cache and BTAC enable ****************************************************/ - -/** \brief Set SCTLR - - This function assigns the given value to the System Control Register. - - \param [in] sctlr System Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) -{ -#if 1 - __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr)); -#else - register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); - __regSCTLR = sctlr; -#endif -} - -/** \brief Get SCTLR - - This function returns the value of the System Control Register. - - \return System Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() { -#if 1 - register uint32_t __regSCTLR; - __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR)); -#else - register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); -#endif - return(__regSCTLR); -} - -/** \brief Enable Caches - - Enable Caches - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) { - // Set I bit 12 to enable I Cache - // Set C bit 2 to enable D Cache - __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); -} - -/** \brief Disable Caches - - Disable Caches - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) { - // Clear I bit 12 to disable I Cache - // Clear C bit 2 to disable D Cache - __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); - __ISB(); -} - -/** \brief Enable BTAC - - Enable BTAC - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) { - // Set Z bit 11 to enable branch prediction - __set_SCTLR( __get_SCTLR() | (1 << 11)); - __ISB(); -} - -/** \brief Disable BTAC - - Disable BTAC - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) { - // Clear Z bit 11 to disable branch prediction - __set_SCTLR( __get_SCTLR() & ~(1 << 11)); -} - - -/** \brief Enable MMU - - Enable MMU - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) { - // Set M bit 0 to enable the MMU - // Set AFE bit to enable simplified access permissions model - // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking - __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); - __ISB(); -} - -/** \brief Disable MMU - - Disable MMU - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) { - // Clear M bit 0 to disable the MMU - __set_SCTLR( __get_SCTLR() & ~1); - __ISB(); -} - -/******************************** TLB maintenance operations ************************************************/ -/** \brief Invalidate the whole tlb - - TLBIALL. Invalidate the whole tlb - */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); -#else - register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); - __TLBIALL = 0; -#endif - __DSB(); - __ISB(); -} - -/******************************** BTB maintenance operations ************************************************/ -/** \brief Invalidate entire branch predictor array - - BPIALL. Branch Predictor Invalidate All. - */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); -#else - register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); - __BPIALL = 0; -#endif - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new state -} - - -/******************************** L1 cache operations ******************************************************/ - -/** \brief Invalidate the whole I$ - - ICIALLU. Instruction Cache Invalidate All to PoU - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); -#else - register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); - __ICIALLU = 0; -#endif - __DSB(); //ensure completion of the invalidation - __ISB(); //ensure instruction fetch path sees new I cache state -} - -/** \brief Clean D$ by MVA - - DCCMVAC. Data cache clean by MVA to PoC - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va)); -#else - register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); - __DCCMVAC = (uint32_t)va; -#endif - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Invalidate D$ by MVA - - DCIMVAC. Data cache invalidate by MVA to PoC - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va)); -#else - register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); - __DCIMVAC = (uint32_t)va; -#endif - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Clean and Invalidate D$ by MVA - - DCCIMVAC. Data cache clean and invalidate by MVA to PoC - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { -#if 1 - __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va)); -#else - register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); - __DCCIMVAC = (uint32_t)va; -#endif - __DMB(); //ensure the ordering of data cache maintenance operations and their effects -} - -/** \brief Clean and Invalidate the entire data or unified cache - - Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. - */ -extern void __v7_all_cache(uint32_t op); - - -/** \brief Invalidate the whole D$ - - DCISW. Invalidate by Set/Way - */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) { - __v7_all_cache(0); -} - -/** \brief Clean the whole D$ - - DCCSW. Clean by Set/Way - */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) { - __v7_all_cache(1); -} - -/** \brief Clean and invalidate the whole D$ - - DCCISW. Clean and Invalidate by Set/Way - */ - -__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) { - __v7_all_cache(2); -} - -#include "core_ca_mmu.h" - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ - -#error TASKING Compiler support not implemented for Cortex-A - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CAFUNC_H__ */ diff --git a/cmsis/TARGET_CORTEX_A/core_ca_mmu.h b/cmsis/TARGET_CORTEX_A/core_ca_mmu.h deleted file mode 100644 index 189b073dbc9..00000000000 --- a/cmsis/TARGET_CORTEX_A/core_ca_mmu.h +++ /dev/null @@ -1,847 +0,0 @@ -;/**************************************************************************//** -; * @file core_ca_mmu.h -; * @brief MMU Startup File for A9_MP Device Series -; * @version V1.01 -; * @date 10 Sept 2014 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2012-2014 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef _MMU_FUNC_H -#define _MMU_FUNC_H - -#define SECTION_DESCRIPTOR (0x2) -#define SECTION_MASK (0xFFFFFFFC) - -#define SECTION_TEXCB_MASK (0xFFFF8FF3) -#define SECTION_B_SHIFT (2) -#define SECTION_C_SHIFT (3) -#define SECTION_TEX0_SHIFT (12) -#define SECTION_TEX1_SHIFT (13) -#define SECTION_TEX2_SHIFT (14) - -#define SECTION_XN_MASK (0xFFFFFFEF) -#define SECTION_XN_SHIFT (4) - -#define SECTION_DOMAIN_MASK (0xFFFFFE1F) -#define SECTION_DOMAIN_SHIFT (5) - -#define SECTION_P_MASK (0xFFFFFDFF) -#define SECTION_P_SHIFT (9) - -#define SECTION_AP_MASK (0xFFFF73FF) -#define SECTION_AP_SHIFT (10) -#define SECTION_AP2_SHIFT (15) - -#define SECTION_S_MASK (0xFFFEFFFF) -#define SECTION_S_SHIFT (16) - -#define SECTION_NG_MASK (0xFFFDFFFF) -#define SECTION_NG_SHIFT (17) - -#define SECTION_NS_MASK (0xFFF7FFFF) -#define SECTION_NS_SHIFT (19) - - -#define PAGE_L1_DESCRIPTOR (0x1) -#define PAGE_L1_MASK (0xFFFFFFFC) - -#define PAGE_L2_4K_DESC (0x2) -#define PAGE_L2_4K_MASK (0xFFFFFFFD) - -#define PAGE_L2_64K_DESC (0x1) -#define PAGE_L2_64K_MASK (0xFFFFFFFC) - -#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) -#define PAGE_4K_B_SHIFT (2) -#define PAGE_4K_C_SHIFT (3) -#define PAGE_4K_TEX0_SHIFT (6) -#define PAGE_4K_TEX1_SHIFT (7) -#define PAGE_4K_TEX2_SHIFT (8) - -#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) -#define PAGE_64K_B_SHIFT (2) -#define PAGE_64K_C_SHIFT (3) -#define PAGE_64K_TEX0_SHIFT (12) -#define PAGE_64K_TEX1_SHIFT (13) -#define PAGE_64K_TEX2_SHIFT (14) - -#define PAGE_TEXCB_MASK (0xFFFF8FF3) -#define PAGE_B_SHIFT (2) -#define PAGE_C_SHIFT (3) -#define PAGE_TEX_SHIFT (12) - -#define PAGE_XN_4K_MASK (0xFFFFFFFE) -#define PAGE_XN_4K_SHIFT (0) -#define PAGE_XN_64K_MASK (0xFFFF7FFF) -#define PAGE_XN_64K_SHIFT (15) - - -#define PAGE_DOMAIN_MASK (0xFFFFFE1F) -#define PAGE_DOMAIN_SHIFT (5) - -#define PAGE_P_MASK (0xFFFFFDFF) -#define PAGE_P_SHIFT (9) - -#define PAGE_AP_MASK (0xFFFFFDCF) -#define PAGE_AP_SHIFT (4) -#define PAGE_AP2_SHIFT (9) - -#define PAGE_S_MASK (0xFFFFFBFF) -#define PAGE_S_SHIFT (10) - -#define PAGE_NG_MASK (0xFFFFF7FF) -#define PAGE_NG_SHIFT (11) - -#define PAGE_NS_MASK (0xFFFFFFF7) -#define PAGE_NS_SHIFT (3) - -#define OFFSET_1M (0x00100000) -#define OFFSET_64K (0x00010000) -#define OFFSET_4K (0x00001000) - -#define DESCRIPTOR_FAULT (0x00000000) - -/* ########################### MMU Function Access ########################### */ -/** \ingroup MMU_FunctionInterface - \defgroup MMU_Functions MMU Functions Interface - @{ - */ - -/* Attributes enumerations */ - -/* Region size attributes */ -typedef enum -{ - SECTION, - PAGE_4k, - PAGE_64k, -} mmu_region_size_Type; - -/* Region type attributes */ -typedef enum -{ - NORMAL, - DEVICE, - SHARED_DEVICE, - NON_SHARED_DEVICE, - STRONGLY_ORDERED -} mmu_memory_Type; - -/* Region cacheability attributes */ -typedef enum -{ - NON_CACHEABLE, - WB_WA, - WT, - WB_NO_WA, -} mmu_cacheability_Type; - -/* Region parity check attributes */ -typedef enum -{ - ECC_DISABLED, - ECC_ENABLED, -} mmu_ecc_check_Type; - -/* Region execution attributes */ -typedef enum -{ - EXECUTE, - NON_EXECUTE, -} mmu_execute_Type; - -/* Region global attributes */ -typedef enum -{ - GLOBAL, - NON_GLOBAL, -} mmu_global_Type; - -/* Region shareability attributes */ -typedef enum -{ - NON_SHARED, - SHARED, -} mmu_shared_Type; - -/* Region security attributes */ -typedef enum -{ - SECURE, - NON_SECURE, -} mmu_secure_Type; - -/* Region access attributes */ -typedef enum -{ - NO_ACCESS, - RW, - READ, -} mmu_access_Type; - -/* Memory Region definition */ -typedef struct RegionStruct { - mmu_region_size_Type rg_t; - mmu_memory_Type mem_t; - uint8_t domain; - mmu_cacheability_Type inner_norm_t; - mmu_cacheability_Type outer_norm_t; - mmu_ecc_check_Type e_t; - mmu_execute_Type xn_t; - mmu_global_Type g_t; - mmu_secure_Type sec_t; - mmu_access_Type priv_t; - mmu_access_Type user_t; - mmu_shared_Type sh_t; - -} mmu_region_attributes_Type; - -/** \brief Set section execution-never attribute - - The function sets section execution-never attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. - - \return 0 - */ -__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn) -{ - *descriptor_l1 &= SECTION_XN_MASK; - *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); - return 0; -} - -/** \brief Set section domain - - The function sets section domain - - \param [out] descriptor_l1 L1 descriptor. - \param [in] domain Section domain - - \return 0 - */ -__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain) -{ - *descriptor_l1 &= SECTION_DOMAIN_MASK; - *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); - return 0; -} - -/** \brief Set section parity check - - The function sets section parity check - - \param [out] descriptor_l1 L1 descriptor. - \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED - - \return 0 - */ -__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) -{ - *descriptor_l1 &= SECTION_P_MASK; - *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); - return 0; -} - -/** \brief Set section access privileges - - The function sets section access privileges - - \param [out] descriptor_l1 L1 descriptor. - \param [in] user User Level Access: NO_ACCESS, RW, READ - \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ - \param [in] afe Access flag enable - - \return 0 - */ -__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) -{ - uint32_t ap = 0; - - if (afe == 0) { //full access - if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } - else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == READ)) { ap = 0x2; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x7; } - } - - else { //Simplified access - if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x7; } - } - - *descriptor_l1 &= SECTION_AP_MASK; - *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; - *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; - - return 0; -} - -/** \brief Set section shareability - - The function sets section shareability - - \param [out] descriptor_l1 L1 descriptor. - \param [in] s_bit Section shareability: NON_SHARED, SHARED - - \return 0 - */ -__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit) -{ - *descriptor_l1 &= SECTION_S_MASK; - *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); - return 0; -} - -/** \brief Set section Global attribute - - The function sets section Global attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL - - \return 0 - */ -__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit) -{ - *descriptor_l1 &= SECTION_NG_MASK; - *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); - return 0; -} - -/** \brief Set section Security attribute - - The function sets section Global attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] s_bit Section Security attribute: SECURE, NON_SECURE - - \return 0 - */ -__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit) -{ - *descriptor_l1 &= SECTION_NS_MASK; - *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); - return 0; -} - -/* Page 4k or 64k */ -/** \brief Set 4k/64k page execution-never attribute - - The function sets 4k/64k page execution-never attribute - - \param [out] descriptor_l2 L2 descriptor. - \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. - \param [in] page Page size: PAGE_4k, PAGE_64k, - - \return 0 - */ -__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) -{ - if (page == PAGE_4k) - { - *descriptor_l2 &= PAGE_XN_4K_MASK; - *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); - } - else - { - *descriptor_l2 &= PAGE_XN_64K_MASK; - *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); - } - return 0; -} - -/** \brief Set 4k/64k page domain - - The function sets 4k/64k page domain - - \param [out] descriptor_l1 L1 descriptor. - \param [in] domain Page domain - - \return 0 - */ -__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain) -{ - *descriptor_l1 &= PAGE_DOMAIN_MASK; - *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page parity check - - The function sets 4k/64k page parity check - - \param [out] descriptor_l1 L1 descriptor. - \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED - - \return 0 - */ -__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) -{ - *descriptor_l1 &= SECTION_P_MASK; - *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page access privileges - - The function sets 4k/64k page access privileges - - \param [out] descriptor_l2 L2 descriptor. - \param [in] user User Level Access: NO_ACCESS, RW, READ - \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ - \param [in] afe Access flag enable - - \return 0 - */ -__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) -{ - uint32_t ap = 0; - - if (afe == 0) { //full access - if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } - else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == READ)) { ap = 0x2; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x6; } - } - - else { //Simplified access - if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } - else if ((priv == RW) && (user == RW)) { ap = 0x3; } - else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } - else if ((priv == READ) && (user == READ)) { ap = 0x7; } - } - - *descriptor_l2 &= PAGE_AP_MASK; - *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; - *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; - - return 0; -} - -/** \brief Set 4k/64k page shareability - - The function sets 4k/64k page shareability - - \param [out] descriptor_l2 L2 descriptor. - \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED - - \return 0 - */ -__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit) -{ - *descriptor_l2 &= PAGE_S_MASK; - *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page Global attribute - - The function sets 4k/64k page Global attribute - - \param [out] descriptor_l2 L2 descriptor. - \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL - - \return 0 - */ -__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit) -{ - *descriptor_l2 &= PAGE_NG_MASK; - *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); - return 0; -} - -/** \brief Set 4k/64k page Security attribute - - The function sets 4k/64k page Global attribute - - \param [out] descriptor_l1 L1 descriptor. - \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE - - \return 0 - */ -__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit) -{ - *descriptor_l1 &= PAGE_NS_MASK; - *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); - return 0; -} - - -/** \brief Set Section memory attributes - - The function sets section memory attributes - - \param [out] descriptor_l1 L1 descriptor. - \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED - \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - - \return 0 - */ -__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) -{ - *descriptor_l1 &= SECTION_TEXCB_MASK; - - if (STRONGLY_ORDERED == mem) - { - return 0; - } - else if (SHARED_DEVICE == mem) - { - *descriptor_l1 |= (1 << SECTION_B_SHIFT); - } - else if (NON_SHARED_DEVICE == mem) - { - *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); - } - else if (NORMAL == mem) - { - *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; - switch(inner) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l1 |= (1 << SECTION_B_SHIFT); - break; - case WT: - *descriptor_l1 |= 1 << SECTION_C_SHIFT; - break; - case WB_NO_WA: - *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); - break; - } - switch(outer) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); - break; - case WT: - *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; - break; - case WB_NO_WA: - *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); - break; - } - } - - return 0; -} - -/** \brief Set 4k/64k page memory attributes - - The function sets 4k/64k page memory attributes - - \param [out] descriptor_l2 L2 descriptor. - \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED - \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, - - \return 0 - */ -__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) -{ - *descriptor_l2 &= PAGE_4K_TEXCB_MASK; - - if (page == PAGE_64k) - { - //same as section - __memory_section(descriptor_l2, mem, outer, inner); - } - else - { - if (STRONGLY_ORDERED == mem) - { - return 0; - } - else if (SHARED_DEVICE == mem) - { - *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); - } - else if (NON_SHARED_DEVICE == mem) - { - *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); - } - else if (NORMAL == mem) - { - *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; - switch(inner) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); - break; - case WT: - *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; - break; - case WB_NO_WA: - *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); - break; - } - switch(outer) - { - case NON_CACHEABLE: - break; - case WB_WA: - *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); - break; - case WT: - *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; - break; - case WB_NO_WA: - *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); - break; - } - } - } - - return 0; -} - -/** \brief Create a L1 section descriptor - - The function creates a section descriptor. - - Assumptions: - - 16MB super sections not supported - - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor - - Functions always return 0 - - \param [out] descriptor L1 descriptor - \param [out] descriptor2 L2 descriptor - \param [in] reg Section attributes - - \return 0 - */ -__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) -{ - *descriptor = 0; - - __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); - __xn_section(descriptor,reg.xn_t); - __domain_section(descriptor, reg.domain); - __p_section(descriptor, reg.e_t); - __ap_section(descriptor, reg.priv_t, reg.user_t, 1); - __shared_section(descriptor,reg.sh_t); - __global_section(descriptor,reg.g_t); - __secure_section(descriptor,reg.sec_t); - *descriptor &= SECTION_MASK; - *descriptor |= SECTION_DESCRIPTOR; - - return 0; - -} - - -/** \brief Create a L1 and L2 4k/64k page descriptor - - The function creates a 4k/64k page descriptor. - Assumptions: - - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor - - Functions always return 0 - - \param [out] descriptor L1 descriptor - \param [out] descriptor2 L2 descriptor - \param [in] reg 4k/64k page attributes - - \return 0 - */ -__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) -{ - *descriptor = 0; - *descriptor2 = 0; - - switch (reg.rg_t) - { - case PAGE_4k: - __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); - __xn_page(descriptor2, reg.xn_t, PAGE_4k); - __domain_page(descriptor, reg.domain); - __p_page(descriptor, reg.e_t); - __ap_page(descriptor2, reg.priv_t, reg.user_t, 1); - __shared_page(descriptor2,reg.sh_t); - __global_page(descriptor2,reg.g_t); - __secure_page(descriptor,reg.sec_t); - *descriptor &= PAGE_L1_MASK; - *descriptor |= PAGE_L1_DESCRIPTOR; - *descriptor2 &= PAGE_L2_4K_MASK; - *descriptor2 |= PAGE_L2_4K_DESC; - break; - - case PAGE_64k: - __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); - __xn_page(descriptor2, reg.xn_t, PAGE_64k); - __domain_page(descriptor, reg.domain); - __p_page(descriptor, reg.e_t); - __ap_page(descriptor2, reg.priv_t, reg.user_t, 1); - __shared_page(descriptor2,reg.sh_t); - __global_page(descriptor2,reg.g_t); - __secure_page(descriptor,reg.sec_t); - *descriptor &= PAGE_L1_MASK; - *descriptor |= PAGE_L1_DESCRIPTOR; - *descriptor2 &= PAGE_L2_64K_MASK; - *descriptor2 |= PAGE_L2_64K_DESC; - break; - - case SECTION: - //error - break; - - } - - return 0; - -} - -/** \brief Create a 1MB Section - - \param [in] ttb Translation table base address - \param [in] base_address Section base address - \param [in] count Number of sections to create - \param [in] descriptor_l1 L1 descriptor (region attributes) - - */ -__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) -{ - uint32_t offset; - uint32_t entry; - uint32_t i; - - offset = base_address >> 20; - entry = (base_address & 0xFFF00000) | descriptor_l1; - - //4 bytes aligned - ttb = ttb + offset; - - for (i = 0; i < count; i++ ) - { - //4 bytes aligned - *ttb++ = entry; - entry += OFFSET_1M; - } -} - -/** \brief Create a 4k page entry - - \param [in] ttb L1 table base address - \param [in] base_address 4k base address - \param [in] count Number of 4k pages to create - \param [in] descriptor_l1 L1 descriptor (region attributes) - \param [in] ttb_l2 L2 table base address - \param [in] descriptor_l2 L2 descriptor (region attributes) - - */ -__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) -{ - - uint32_t offset, offset2; - uint32_t entry, entry2; - uint32_t i; - - - offset = base_address >> 20; - entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; - - //4 bytes aligned - ttb += offset; - //create l1_entry - *ttb = entry; - - offset2 = (base_address & 0xff000) >> 12; - ttb_l2 += offset2; - entry2 = (base_address & 0xFFFFF000) | descriptor_l2; - for (i = 0; i < count; i++ ) - { - //4 bytes aligned - *ttb_l2++ = entry2; - entry2 += OFFSET_4K; - } -} - -/** \brief Create a 64k page entry - - \param [in] ttb L1 table base address - \param [in] base_address 64k base address - \param [in] count Number of 64k pages to create - \param [in] descriptor_l1 L1 descriptor (region attributes) - \param [in] ttb_l2 L2 table base address - \param [in] descriptor_l2 L2 descriptor (region attributes) - - */ -__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) -{ - uint32_t offset, offset2; - uint32_t entry, entry2; - uint32_t i,j; - - - offset = base_address >> 20; - entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; - - //4 bytes aligned - ttb += offset; - //create l1_entry - *ttb = entry; - - offset2 = (base_address & 0xff000) >> 12; - ttb_l2 += offset2; - entry2 = (base_address & 0xFFFF0000) | descriptor_l2; - for (i = 0; i < count; i++ ) - { - //create 16 entries - for (j = 0; j < 16; j++) - //4 bytes aligned - *ttb_l2++ = entry2; - entry2 += OFFSET_64K; - } -} - -/*@} end of MMU_Functions */ -#endif - -#ifdef __cplusplus -} -#endif diff --git a/cmsis/TARGET_CORTEX_A/core_cm4_simd.h b/cmsis/TARGET_CORTEX_A/core_cm4_simd.h deleted file mode 100644 index 83db95b5f11..00000000000 --- a/cmsis/TARGET_CORTEX_A/core_cm4_simd.h +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/cmsis/TARGET_CORTEX_A/core_cmInstr.h b/cmsis/TARGET_CORTEX_A/core_cmInstr.h deleted file mode 100644 index fca425c51db..00000000000 --- a/cmsis/TARGET_CORTEX_A/core_cmInstr.h +++ /dev/null @@ -1,916 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero - return(result); -} -#endif - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero -#endif - return(result); -} - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/cmsis/TARGET_CORTEX_A/irq_ctrl.h b/cmsis/TARGET_CORTEX_A/irq_ctrl.h new file mode 100644 index 00000000000..4299c2831c3 --- /dev/null +++ b/cmsis/TARGET_CORTEX_A/irq_ctrl.h @@ -0,0 +1,180 @@ +/**************************************************************************//** + * @file irq_ctrl.h + * @brief Interrupt Controller API header file + * @version V1.0.0 + * @date 23. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef IRQ_CTRL_H_ +#define IRQ_CTRL_H_ + +#include + +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +/// Interrupt handler data type +typedef void (*IRQHandler_t) (void); +#endif + +#ifndef IRQN_ID_T +#define IRQN_ID_T +/// Interrupt ID number data type +typedef int32_t IRQn_ID_t; +#endif + +/* Interrupt mode bit-masks */ +#define IRQ_MODE_TRIG_Pos (0U) +#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) +#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt +#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt +#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt +#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt + +#define IRQ_MODE_TYPE_Pos (3U) +#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos) +#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line +#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line + +#define IRQ_MODE_DOMAIN_Pos (4U) +#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos) +#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain +#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain + +#define IRQ_MODE_CPU_Pos (5U) +#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos) +#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs +#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0 +#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1 +#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2 +#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3 +#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4 +#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5 +#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6 +#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7 + +#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error + +/* Interrupt priority bit-masks */ +#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask +#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error + +/// Initialize interrupt controller. +/// \return 0 on success, -1 on error. +int32_t IRQ_Initialize (void); + +/// Register interrupt handler. +/// \param[in] irqn interrupt ID number +/// \param[in] handler interrupt handler function address +/// \return 0 on success, -1 on error. +int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler); + +/// Get the registered interrupt handler. +/// \param[in] irqn interrupt ID number +/// \return registered interrupt handler function address. +IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn); + +/// Enable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Enable (IRQn_ID_t irqn); + +/// Disable interrupt. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_Disable (IRQn_ID_t irqn); + +/// Get interrupt enable state. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is disabled, 1 - interrupt is enabled. +uint32_t IRQ_GetEnableState (IRQn_ID_t irqn); + +/// Configure interrupt request mode. +/// \param[in] irqn interrupt ID number +/// \param[in] mode mode configuration +/// \return 0 on success, -1 on error. +int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode); + +/// Get interrupt mode configuration. +/// \param[in] irqn interrupt ID number +/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set. +uint32_t IRQ_GetMode (IRQn_ID_t irqn); + +/// Get ID number of current interrupt request (IRQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveIRQ (void); + +/// Get ID number of current fast interrupt request (FIQ). +/// \return interrupt ID number. +IRQn_ID_t IRQ_GetActiveFIQ (void); + +/// Signal end of interrupt processing. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn); + +/// Set interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPending (IRQn_ID_t irqn); + +/// Get interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 - interrupt is not pending, 1 - interrupt is pending. +uint32_t IRQ_GetPending (IRQn_ID_t irqn); + +/// Clear interrupt pending flag. +/// \param[in] irqn interrupt ID number +/// \return 0 on success, -1 on error. +int32_t IRQ_ClearPending (IRQn_ID_t irqn); + +/// Set interrupt priority value. +/// \param[in] irqn interrupt ID number +/// \param[in] priority interrupt priority value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority); + +/// Get interrupt priority. +/// \param[in] irqn interrupt ID number +/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriority (IRQn_ID_t irqn); + +/// Set priority masking threshold. +/// \param[in] priority priority masking threshold value +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityMask (uint32_t priority); + +/// Get priority masking threshold +/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityMask (void); + +/// Set priority grouping field split point +/// \param[in] bits number of MSB bits included in the group priority field comparison +/// \return 0 on success, -1 on error. +int32_t IRQ_SetPriorityGroupBits (uint32_t bits); + +/// Get priority grouping field split point +/// \return current number of MSB bits included in the group priority field comparison with +/// optional IRQ_PRIORITY_ERROR bit set. +uint32_t IRQ_GetPriorityGroupBits (void); + +#endif // IRQ_CTRL_H_ diff --git a/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c b/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c new file mode 100644 index 00000000000..39be23e04fa --- /dev/null +++ b/cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c @@ -0,0 +1,403 @@ +/**************************************************************************//** + * @file irq_ctrl_gic.c + * @brief Interrupt controller handling implementation for GIC + * @version V1.0.0 + * @date 30. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include + +#include "irq_ctrl.h" + +#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U) + +/// Number of implemented interrupt lines +#ifndef IRQ_GIC_LINE_COUNT +#define IRQ_GIC_LINE_COUNT (1020U) +#endif + +static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U }; +static uint32_t IRQ_ID0; + +/// Initialize interrupt controller. +__WEAK int32_t IRQ_Initialize (void) { + uint32_t i; + + for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) { + IRQTable[i] = (IRQHandler_t)NULL; + } + GIC_Enable(); + return (0); +} + + +/// Register interrupt handler. +__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + IRQTable[irqn] = handler; + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get the registered interrupt handler. +__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) { + IRQHandler_t h; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + h = IRQTable[irqn]; + } else { + h = (IRQHandler_t)0; + } + + return (h); +} + + +/// Enable interrupt. +__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EnableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Disable interrupt. +__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_DisableIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt enable state. +__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) { + uint32_t enable; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + enable = GIC_GetEnableIRQ((IRQn_Type)irqn); + } else { + enable = 0U; + } + + return (enable); +} + + +/// Configure interrupt request mode. +__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) { + int32_t status; + uint32_t val; + uint8_t cfg; + uint8_t secure; + uint8_t cpu; + + status = 0; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + // Check triggering mode + val = (mode & IRQ_MODE_TRIG_Msk); + + if (val == IRQ_MODE_TRIG_LEVEL) { + cfg = 0x00U; + } else if (val == IRQ_MODE_TRIG_EDGE) { + cfg = 0x02U; + } else { + status = -1; + } + + // Check interrupt type + val = mode & IRQ_MODE_TYPE_Msk; + + if (val != IRQ_MODE_TYPE_IRQ) { + status = -1; + } + + // Check interrupt domain + val = mode & IRQ_MODE_DOMAIN_Msk; + + if (val == IRQ_MODE_DOMAIN_NONSECURE) { + secure = 0; + } else { + // Check security extensions support + val = GIC_DistributorInfo() & (1UL << 10U); + + if (val != 0U) { + // Security extensions are supported + secure = 1; + } else { + status = -1; + } + } + + // Check interrupt CPU targets + val = mode & IRQ_MODE_CPU_Msk; + + if (val == IRQ_MODE_CPU_ALL) { + cpu = 0xFF; + } else { + cpu = val >> IRQ_MODE_CPU_Pos; + } + + // Apply configuration if no mode error + if (status == 0) { + GIC_SetConfiguration((IRQn_Type)irqn, cfg); + GIC_SetTarget ((IRQn_Type)irqn, cpu); + + if (secure != 0U) { + GIC_SetGroup ((IRQn_Type)irqn, secure); + } + } + } + + return (status); +} + + +/// Get interrupt mode configuration. +__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) { + uint32_t mode; + uint32_t val; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + mode = IRQ_MODE_TYPE_IRQ; + + // Get trigger mode + val = GIC_GetConfiguration((IRQn_Type)irqn); + + if ((val & 2U) != 0U) { + // Corresponding interrupt is edge triggered + mode |= IRQ_MODE_TRIG_EDGE; + } else { + // Corresponding interrupt is level triggered + mode |= IRQ_MODE_TRIG_LEVEL; + } + + // Get interrupt CPU targets + mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos; + + } else { + mode = IRQ_MODE_ERROR; + } + + return (mode); +} + + +/// Get ID number of current interrupt request (IRQ). +__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) { + IRQn_ID_t irqn; + uint32_t prio; + + /* Dummy read to avoid GIC 390 errata 801120 */ + GIC_GetHighPendingIRQ(); + + irqn = GIC_AcknowledgePending(); + + __DSB(); + + /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */ + /* The following workaround code is for a single-core system. It would be */ + /* different in a multi-core system. */ + /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */ + /* so unlock it, otherwise service the interrupt as normal. */ + /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */ + /* so will not occur here. */ + + if ((irqn == 0) || (irqn >= 0x3FE)) { + /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */ + prio = GIC_GetPriority((IRQn_Type)0); + GIC_SetPriority ((IRQn_Type)0, prio); + + __DSB(); + + if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) { + /* If the ID is 0, is active and has not been seen before */ + IRQ_ID0 = 1U; + } + /* End of Workaround GIC 390 errata 733075 */ + } + + return (irqn); +} + + +/// Get ID number of current fast interrupt request (FIQ). +__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) { + return ((IRQn_ID_t)-1); +} + + +/// Signal end of interrupt processing. +__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_EndInterrupt ((IRQn_Type)irqn); + + if (irqn == 0) { + IRQ_ID0 = 0U; + } + + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt pending flag. +__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + +/// Get interrupt pending flag. +__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) { + uint32_t pending; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + pending = GIC_GetPendingIRQ ((IRQn_Type)irqn); + } else { + pending = 0U; + } + + return (pending & 1U); +} + + +/// Clear interrupt pending flag. +__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) { + int32_t status; + + if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_ClearPendingIRQ ((IRQn_Type)irqn); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Set interrupt priority value. +__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) { + int32_t status; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + GIC_SetPriority ((IRQn_Type)irqn, priority); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get interrupt priority. +__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) { + uint32_t priority; + + if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) { + priority = GIC_GetPriority ((IRQn_Type)irqn); + } else { + priority = IRQ_PRIORITY_ERROR; + } + + return (priority); +} + + +/// Set priority masking threshold. +__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) { + GIC_SetInterfacePriorityMask (priority); + return (0); +} + + +/// Get priority masking threshold +__WEAK uint32_t IRQ_GetPriorityMask (void) { + return GIC_GetInterfacePriorityMask(); +} + + +/// Set priority grouping field split point +__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) { + int32_t status; + + if (bits == IRQ_PRIORITY_Msk) { + bits = 7U; + } + + if (bits < 8U) { + GIC_SetBinaryPoint (7U - bits); + status = 0; + } else { + status = -1; + } + + return (status); +} + + +/// Get priority grouping field split point +__WEAK uint32_t IRQ_GetPriorityGroupBits (void) { + uint32_t bp; + + bp = GIC_GetBinaryPoint() & 0x07U; + + return (7U - bp); +} + +#endif diff --git a/cmsis/TOOLCHAIN_IAR/cmain.S b/cmsis/TARGET_CORTEX_M/TOOLCHAIN_IAR/cmain.S similarity index 100% rename from cmsis/TOOLCHAIN_IAR/cmain.S rename to cmsis/TARGET_CORTEX_M/TOOLCHAIN_IAR/cmain.S diff --git a/cmsis/arm_math.h b/cmsis/TARGET_CORTEX_M/arm_math.h similarity index 99% rename from cmsis/arm_math.h rename to cmsis/TARGET_CORTEX_M/arm_math.h index 6d754018966..f867d494309 100644 --- a/cmsis/arm_math.h +++ b/cmsis/TARGET_CORTEX_M/arm_math.h @@ -572,32 +572,6 @@ extern "C" (((q63_t) (x >> 32) * y))); } -/* - #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) - #define __CLZ __clz - #endif - */ -/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */ -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data); - - CMSIS_INLINE __STATIC_INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while ((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - } -#endif - /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ @@ -700,47 +674,6 @@ extern "C" return (signBits + 1); } - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - CMSIS_INLINE __STATIC_INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if (x > 0) - { - posMax = (posMax - 1); - - if (x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if (x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - /* * @brief C custom defined intrinsic function for M3 and M0 processors */ diff --git a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h similarity index 94% rename from cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h rename to cmsis/TARGET_CORTEX_M/cmsis_armcc.h index 7b2a2847e0e..c2ef0a5b8ca 100644 --- a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armcc.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_armcc.h @@ -73,6 +73,9 @@ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT __packed struct #endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) #endif @@ -91,7 +94,9 @@ #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif - +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface @@ -456,7 +461,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) \return Reversed value */ #ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint16_t __REV16(uint16_t value) { rev16 r0, r0 bx lr @@ -471,7 +476,7 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u \return Reversed value */ #ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) { revsh r0, r0 bx lr @@ -512,17 +517,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) + for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ - return(result); + return result; } #endif @@ -719,6 +724,50 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 */ #define __STRT(value, ptr) __strt(value, ptr) +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) { + return max; + } else if (val < min) { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) { + return max; + } else if (val < 0) { + return 0U; + } + } + return (uint32_t)val; +} + #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ diff --git a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h similarity index 95% rename from cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h rename to cmsis/TARGET_CORTEX_M/cmsis_armclang.h index 7c22d84096b..f13bb171f56 100644 --- a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_ARM/cmsis_armclang.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_armclang.h @@ -22,7 +22,7 @@ * limitations under the License. */ -//lint -esym(9058, IRQn) disable MISRA 2012 Rule 2.4 for IRQn +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ #ifndef __CMSIS_ARMCLANG_H #define __CMSIS_ARMCLANG_H @@ -56,10 +56,13 @@ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -//lint -esym(9058, T_UINT32) disable MISRA 2012 Rule 2.4 for T_UINT32 +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) @@ -67,7 +70,7 @@ #ifndef __UNALIGNED_UINT16_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -//lint -esym(9058, T_UINT16_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) @@ -75,7 +78,7 @@ #ifndef __UNALIGNED_UINT16_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -//lint -esym(9058, T_UINT16_READ) disable MISRA 2012 Rule 2.4 for T_UINT16_READ +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) @@ -83,7 +86,7 @@ #ifndef __UNALIGNED_UINT32_WRITE #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" -//lint -esym(9058, T_UINT32_WRITE) disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) @@ -91,6 +94,7 @@ #ifndef __UNALIGNED_UINT32_READ #pragma clang diagnostic push #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; #pragma clang diagnostic pop #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) @@ -98,6 +102,9 @@ #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif /* ########################### Core Function Access ########################### */ @@ -677,36 +684,24 @@ __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t \details Returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ -/* #define __get_FPSCR __builtin_arm_get_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr #else - return(0U); +#define __get_FPSCR() ((uint32_t)0U) #endif -} - /** \brief Set FPSCR \details Assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ -/* #define __set_FPSCR __builtin_arm_set_fpscr */ -__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "memory"); +#define __set_FPSCR __builtin_arm_set_fpscr #else - (void)fpscr; +#define __set_FPSCR(x) ((void)(x)) #endif -} #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ @@ -791,7 +786,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) \param [in] value Value to reverse \return Reversed value */ -#define __REV __builtin_bswap32 +#define __REV (uint32_t)__builtin_bswap32 /** @@ -800,16 +795,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) \param [in] value Value to reverse \return Reversed value */ -#define __REV16 __builtin_bswap16 /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -#if 0 -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} -#endif +#define __REV16 (uint16_t)__builtin_bswap16 /** @@ -818,13 +804,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) \param [in] value Value to reverse \return Reversed value */ - /* ToDo ARMCLANG: check if __builtin_bswap16 could be used */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value) { - int32_t result; + int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + + return result; } @@ -848,7 +834,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) +#define __BKPT(value) __ASM volatile ("bkpt "#value) /** @@ -857,30 +843,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint \param [in] value Value to reverse \return Reversed value */ - /* ToDo ARMCLANG: check if __builtin_arm_rbit is supported */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return(result); -} - +#define __RBIT (uint32_t)__builtin_arm_rbit /** \brief Count leading zeros @@ -970,6 +933,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + /** \brief Signed Saturate \details Saturates a signed value. @@ -1086,6 +1050,51 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volat __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) { + return max; + } else if (val < min) { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) { + return max; + } else if (val < 0) { + return 0U; + } + } + return (uint32_t)val; +} + #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ diff --git a/cmsis/TARGET_CORTEX_M/cmsis_compiler.h b/cmsis/TARGET_CORTEX_M/cmsis_compiler.h index 9e87cfd74a4..5a9a222cdba 100644 --- a/cmsis/TARGET_CORTEX_M/cmsis_compiler.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_compiler.h @@ -52,88 +52,9 @@ * IAR Compiler */ #elif defined ( __ICCARM__ ) + #include - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - - #include - - /* CMSIS compiler control architecture macros */ - #if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__) - #ifndef __ARM_ARCH_6M__ - #define __ARM_ARCH_6M__ 1 - #endif - #elif (__CORE__ == __ARM7M__) - #ifndef __ARM_ARCH_7M__ - #define __ARM_ARCH_7M__ 1 - #endif - #elif (__CORE__ == __ARM7EM__) - #ifndef __ARM_ARCH_7EM__ - #define __ARM_ARCH_7EM__ 1 - #endif - #elif (__CORE__ == __ARM8M_BASELINE__) - #ifndef __ARM_ARCH_8M_BASE__ - #define __ARM_ARCH_8M_BASE__ 1 - #endif - #elif (__CORE__ == __ARM8M_MAINLINE__) - #ifndef __ARM_ARCH_8M_MAIN__ - #define __ARM_ARCH_8M_MAIN__ 1 - #endif - #endif - - // IAR version 7.8.1 and earlier do not include __ALIGNED - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - - #ifndef __NO_RETURN - #define __NO_RETURN __noreturn - #endif - #ifndef __USED - #define __USED __root - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED __packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - __packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - - + /* * TI ARM Compiler */ @@ -164,6 +85,9 @@ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed)) #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __attribute__((packed)) T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) @@ -187,6 +111,10 @@ #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif /* @@ -223,6 +151,9 @@ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __packed__ #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ struct __packed__ T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) @@ -246,6 +177,10 @@ #ifndef __ALIGNED #define __ALIGNED(x) __align(x) #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif /* @@ -280,6 +215,9 @@ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT @packed struct #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif #ifndef __UNALIGNED_UINT32 /* deprecated */ @packed struct T_UINT32 { uint32_t v; }; #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) @@ -304,6 +242,10 @@ #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. #define __ALIGNED(x) #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif #else diff --git a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h similarity index 95% rename from cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h rename to cmsis/TARGET_CORTEX_M/cmsis_gcc.h index f023d77b230..4aef7af1e5b 100644 --- a/cmsis/TARGET_CORTEX_M/TOOLCHAIN_GCC/cmsis_gcc.h +++ b/cmsis/TARGET_CORTEX_M/cmsis_gcc.h @@ -31,6 +31,11 @@ #pragma GCC diagnostic ignored "-Wconversion" #pragma GCC diagnostic ignored "-Wunused-parameter" +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm @@ -56,6 +61,9 @@ #ifndef __PACKED_STRUCT #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) #endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif #ifndef __UNALIGNED_UINT32 /* deprecated */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wpacked" @@ -99,6 +107,9 @@ #ifndef __ALIGNED #define __ALIGNED(x) __attribute__((aligned(x))) #endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif /* ########################### Core Function Access ########################### */ @@ -694,12 +705,17 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else uint32_t result; __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); return(result); +#endif #else - return(0U); + return(0U); #endif } @@ -713,7 +729,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif #else (void)fpscr; #endif @@ -826,7 +847,7 @@ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void) /** \brief Reverse byte order (32 bit) - \details Reverses the byte order in integer value. + \details Reverses the byte order in unsigned integer value. \param [in] value Value to reverse \return Reversed value */ @@ -845,13 +866,13 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) /** \brief Reverse byte order (16 bit) - \details Reverses the byte order in two unsigned short values. + \details Reverses the byte order in unsigned short value. \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __REV16(uint16_t value) { - uint32_t result; + uint16_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); @@ -864,15 +885,15 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) \param [in] value Value to reverse \return Reversed value */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); + return (int16_t)__builtin_bswap16(value); #else - int32_t result; + int16_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); + return result; #endif } @@ -915,10 +936,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else - int32_t s = (4 /*sizeof(v)*/ * 8) - 1; /* extra shift needed at end */ + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value; value >>= 1U) + for (value >>= 1U; value != 0U; value >>= 1U) { result <<= 1U; result |= value & 1U; @@ -926,7 +947,7 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) } result <<= s; /* shift when v's highest bits are zero */ #endif - return(result); + return result; } @@ -1074,11 +1095,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) /** \brief Signed Saturate \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ +__extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ @@ -1089,11 +1111,12 @@ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) /** \brief Unsigned Saturate \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ + __extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ @@ -1211,6 +1234,51 @@ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volat __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); } +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) { + return max; + } else if (val < min) { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) { + return max; + } else if (val < 0) { + return 0U; + } + } + return (uint32_t)val; +} + #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ diff --git a/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h new file mode 100644 index 00000000000..01612854bbd --- /dev/null +++ b/cmsis/TARGET_CORTEX_M/cmsis_iccarm.h @@ -0,0 +1,771 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR compiler) header file + * @version V5.0.3 + * @date 29. August 2017 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017 IAR Systems +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((noreturn)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #define __RESTRICT restrict +#endif + + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) { + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) { + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) { + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) { + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + __IAR_FT uint8_t __CLZ(uint32_t val) { + return __iar_builtin_CLZ(val); + } + + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int32_t __REVSH(int32_t val) { + return __iar_builtin_REVSH((int16_t)val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) { + if (data == 0u) { return 32u; } + + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + return (count); + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) { + uint8_t sc = 31; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { + uint32_t res; + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) { + if ((sat >= 1U) && (sat <= 32U)) { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) { + return max; + } else if (val < min) { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) { + if (sat <= 31U) { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) { + return max; + } else if (val < 0) { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { + __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { + __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { + __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/cmsis/TARGET_CORTEX_M/cmsis_version.h b/cmsis/TARGET_CORTEX_M/cmsis_version.h new file mode 100644 index 00000000000..d458a6c8599 --- /dev/null +++ b/cmsis/TARGET_CORTEX_M/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.2 + * @date 19. April 2017 + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/cmsis/core_armv8mbl.h b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h similarity index 99% rename from cmsis/core_armv8mbl.h rename to cmsis/TARGET_CORTEX_M/core_armv8mbl.h index d03935201ce..917b16e1a32 100644 --- a/cmsis/core_armv8mbl.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mbl.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_armv8mbl.h * @brief CMSIS ARMv8MBL Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -59,12 +59,14 @@ \ingroup Cortex_ARMv8MBL @{ */ + +#include "cmsis_version.h" -/* CMSIS cmGrebe definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M ( 2U) /*!< Cortex-M Core */ @@ -881,10 +883,17 @@ typedef struct __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; } MPU_Type; +#define MPU_TYPE_RALIASES 1U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1627,6 +1636,10 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } + else + { + return(0U); + } } @@ -1729,6 +1742,13 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_armv8mml.h b/cmsis/TARGET_CORTEX_M/core_armv8mml.h similarity index 98% rename from cmsis/core_armv8mml.h rename to cmsis/TARGET_CORTEX_M/core_armv8mml.h index 286322f75c4..afea7588c75 100644 --- a/cmsis/core_armv8mml.h +++ b/cmsis/TARGET_CORTEX_M/core_armv8mml.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_armv8mml.h * @brief CMSIS ARMv8MML Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS ARMv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (81U) /*!< Cortex-M Core */ @@ -83,6 +85,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -95,6 +108,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -106,7 +130,18 @@ #else #define __FPU_USED 0U #endif - + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -119,6 +154,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -480,7 +526,7 @@ typedef struct uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; @@ -1505,10 +1551,17 @@ typedef struct __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -2661,6 +2714,13 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cm0.h b/cmsis/TARGET_CORTEX_M/core_cm0.h similarity index 99% rename from cmsis/core_cm0.h rename to cmsis/TARGET_CORTEX_M/core_cm0.h index f1fbbe9c172..2f63b68610b 100644 --- a/cmsis/core_cm0.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0.h @@ -2,7 +2,7 @@ * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V5.0.2 - * @date 13. February 2017 + * @date 19. April 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ diff --git a/cmsis/core_cm0plus.h b/cmsis/TARGET_CORTEX_M/core_cm0plus.h similarity index 98% rename from cmsis/core_cm0plus.h rename to cmsis/TARGET_CORTEX_M/core_cm0plus.h index 2dca31a3cf1..84f32813fd2 100644 --- a/cmsis/core_cm0plus.h +++ b/cmsis/TARGET_CORTEX_M/core_cm0plus.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (0U) /*!< Cortex-M Core */ @@ -528,6 +530,8 @@ typedef struct __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 1U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -932,6 +936,13 @@ __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cm23.h b/cmsis/TARGET_CORTEX_M/core_cm23.h similarity index 99% rename from cmsis/core_cm23.h rename to cmsis/TARGET_CORTEX_M/core_cm23.h index 378c69beeb2..1852efbb54c 100644 --- a/cmsis/core_cm23.h +++ b/cmsis/TARGET_CORTEX_M/core_cm23.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm23.h * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ -/* CMSIS cmGrebe definitions */ -#define __CM23_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (23U) /*!< Cortex-M Core */ @@ -881,10 +883,17 @@ typedef struct __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; } MPU_Type; +#define MPU_TYPE_RALIASES 1U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1627,6 +1636,10 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } + else + { + return(0U); + } } @@ -1729,6 +1742,13 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cm3.h b/cmsis/TARGET_CORTEX_M/core_cm3.h similarity index 99% rename from cmsis/core_cm3.h rename to cmsis/TARGET_CORTEX_M/core_cm3.h index cfeb58bea91..3809f716c52 100644 --- a/cmsis/core_cm3.h +++ b/cmsis/TARGET_CORTEX_M/core_cm3.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (3U) /*!< Cortex-M Core */ @@ -1162,6 +1164,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1761,6 +1765,13 @@ __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cm33.h b/cmsis/TARGET_CORTEX_M/core_cm33.h similarity index 98% rename from cmsis/core_cm33.h rename to cmsis/TARGET_CORTEX_M/core_cm33.h index 9e880ae7dc9..ef0b7c7c530 100644 --- a/cmsis/core_cm33.h +++ b/cmsis/TARGET_CORTEX_M/core_cm33.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (33U) /*!< Cortex-M Core */ @@ -83,6 +85,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) #if defined __ARM_PCS_VFP #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -95,6 +108,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -107,6 +131,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -119,6 +154,17 @@ #define __FPU_USED 0U #endif + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + #elif defined ( __TI_ARM__ ) #if defined __TI_VFP_SUPPORT__ #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) @@ -480,7 +526,7 @@ typedef struct uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; @@ -1505,10 +1551,17 @@ typedef struct __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1534,8 +1587,8 @@ typedef struct #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ @@ -2557,6 +2610,10 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) { return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } + else + { + return(0U); + } } @@ -2657,6 +2714,13 @@ __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cm4.h b/cmsis/TARGET_CORTEX_M/core_cm4.h similarity index 99% rename from cmsis/core_cm4.h rename to cmsis/TARGET_CORTEX_M/core_cm4.h index bdaedcf9f31..1c12d4e51cc 100644 --- a/cmsis/core_cm4.h +++ b/cmsis/TARGET_CORTEX_M/core_cm4.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (4U) /*!< Cortex-M Core */ @@ -1227,6 +1229,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -1935,6 +1939,14 @@ __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cm7.h b/cmsis/TARGET_CORTEX_M/core_cm7.h similarity index 99% rename from cmsis/core_cm7.h rename to cmsis/TARGET_CORTEX_M/core_cm7.h index fee3d0c977a..65fa60fc85b 100644 --- a/cmsis/core_cm7.h +++ b/cmsis/TARGET_CORTEX_M/core_cm7.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.0.2 - * @date 13. February 2017 + * @version V5.0.3 + * @date 09. August 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_M (7U) /*!< Cortex-M Core */ @@ -482,7 +484,7 @@ typedef struct uint32_t RESERVED4[15U]; __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ uint32_t RESERVED5[1U]; __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1U]; @@ -1432,6 +1434,8 @@ typedef struct __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; +#define MPU_TYPE_RALIASES 4U + /* MPU Type Register Definitions */ #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ @@ -2143,6 +2147,13 @@ __STATIC_INLINE void __NVIC_SystemReset(void) /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif /* ########################## FPU functions #################################### */ /** diff --git a/cmsis/core_cmSecureAccess.h b/cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h similarity index 100% rename from cmsis/core_cmSecureAccess.h rename to cmsis/TARGET_CORTEX_M/core_cmSecureAccess.h diff --git a/cmsis/core_sc000.h b/cmsis/TARGET_CORTEX_M/core_sc000.h similarity index 99% rename from cmsis/core_sc000.h rename to cmsis/TARGET_CORTEX_M/core_sc000.h index 53dfaadd8b3..bd26eaa0db9 100644 --- a/cmsis/core_sc000.h +++ b/cmsis/TARGET_CORTEX_M/core_sc000.h @@ -2,7 +2,7 @@ * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V5.0.2 - * @date 13. February 2017 + * @date 19. April 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (000U) /*!< Cortex secure core */ diff --git a/cmsis/core_sc300.h b/cmsis/TARGET_CORTEX_M/core_sc300.h similarity index 99% rename from cmsis/core_sc300.h rename to cmsis/TARGET_CORTEX_M/core_sc300.h index 78450e0f7c5..780372a350c 100644 --- a/cmsis/core_sc300.h +++ b/cmsis/TARGET_CORTEX_M/core_sc300.h @@ -2,7 +2,7 @@ * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V5.0.2 - * @date 13. February 2017 + * @date 19. April 2017 ******************************************************************************/ /* * Copyright (c) 2009-2017 ARM Limited. All rights reserved. @@ -60,11 +60,13 @@ @{ */ +#include "cmsis_version.h" + /* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ #define __CORTEX_SC (300U) /*!< Cortex secure core */ diff --git a/cmsis/TARGET_CORTEX_M/mpu_armv7.h b/cmsis/TARGET_CORTEX_M/mpu_armv7.h new file mode 100644 index 00000000000..44d0930cc3f --- /dev/null +++ b/cmsis/TARGET_CORTEX_M/mpu_armv7.h @@ -0,0 +1,191 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for ARMv7 MPU + * @version V5.0.3 + * @date 09. August 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) + +#define ARM_MPU_AP_NONE 0U +#define ARM_MPU_AP_PRIV 1U +#define ARM_MPU_AP_URO 2U +#define ARM_MPU_AP_FULL 3U +#define ARM_MPU_AP_PRO 5U +#define ARM_MPU_AP_RO 6U + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Region Attribut and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (MPU_RASR_ENABLE_Msk)) + + +/** +* Struct for a single MPU Region +*/ +typedef struct _ARM_MPU_Region_t { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt > MPU_TYPE_RALIASES) { + orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + ARM_MPU_Load(table+MPU_TYPE_RALIASES, cnt-MPU_TYPE_RALIASES); + } else { + orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); + } +} + +#endif diff --git a/cmsis/TARGET_CORTEX_M/mpu_armv8.h b/cmsis/TARGET_CORTEX_M/mpu_armv8.h new file mode 100644 index 00000000000..69452e0d0b3 --- /dev/null +++ b/cmsis/TARGET_CORTEX_M/mpu_armv8.h @@ -0,0 +1,323 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for ARMv8 MPU + * @version V5.0.3 + * @date 09. August 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Pos) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +/** +* Struct for a single MPU Region +*/ +typedef struct _ARM_MPU_Region_t { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DSB(); + __ISB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DSB(); + __ISB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) { + return; // invalid index + } + + MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c); + } else { + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/cmsis/tz_context.h b/cmsis/TARGET_CORTEX_M/tz_context.h similarity index 100% rename from cmsis/tz_context.h rename to cmsis/TARGET_CORTEX_M/tz_context.h diff --git a/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S b/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S deleted file mode 100644 index d37f889191d..00000000000 --- a/cmsis/TOOLCHAIN_GCC/TARGET_CORTEX_A/cache.S +++ /dev/null @@ -1,94 +0,0 @@ -/* Copyright (c) 2009 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - * Functions - *---------------------------------------------------------------------------*/ - .text - .global __v7_all_cache -/* - * __STATIC_ASM void __v7_all_cache(uint32_t op) { - */ -__v7_all_cache: - .arm - - PUSH {R4-R11} - - MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ - ANDS R3, R6, #0x07000000 /* Extract coherency level */ - MOV R3, R3, LSR #23 /* Total cache levels << 1 */ - BEQ Finished /* If 0, no need to clean */ - - MOV R10, #0 /* R10 holds current cache level << 1 */ -Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ - MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ - AND R1, R1, #7 /* Isolate those lower 3 bits */ - CMP R1, #2 - BLT Skip /* No cache or only instruction cache at this level */ - - MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ - ISB /* ISB to sync the change to the CacheSizeID reg */ - MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ - AND R2, R1, #7 /* Extract the line length field */ - ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ - LDR R4, =0x3FF - ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ - CLZ R5, R4 /* R5 is the bit position of the way size increment */ - LDR R7, =0x7FFF - ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ - -Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ - -Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ - ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ - CMP R0, #0 - BNE Dccsw - MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ - B cont -Dccsw: CMP R0, #1 - BNE Dccisw - MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ - B cont -Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ -cont: SUBS R9, R9, #1 /* Decrement the Way number */ - BGE Loop3 - SUBS R7, R7, #1 /* Decrement the Set number */ - BGE Loop2 -Skip: ADD R10, R10, #2 /* increment the cache number */ - CMP R3, R10 - BGT Loop1 - -Finished: - DSB - POP {R4-R11} - BX lr - - - .END -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S b/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S deleted file mode 100644 index 00352787a20..00000000000 --- a/cmsis/TOOLCHAIN_IAR/TARGET_CORTEX_A/cache.S +++ /dev/null @@ -1,97 +0,0 @@ -/* Copyright (c) 2009 - 2012 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - * Functions - *---------------------------------------------------------------------------*/ - SECTION `.text`:CODE:NOROOT(2) - arm - PUBLIC __v7_all_cache -/* - * __STATIC_ASM void __v7_all_cache(uint32_t op) { - */ - -__v7_all_cache: - - - PUSH {R4-R11} - - MRC p15, 1, R6, c0, c0, 1 /* Read CLIDR */ - ANDS R3, R6, #0x07000000 /* Extract coherency level */ - MOV R3, R3, LSR #23 /* Total cache levels << 1 */ - BEQ Finished /* If 0, no need to clean */ - - MOV R10, #0 /* R10 holds current cache level << 1 */ -Loop1: ADD R2, R10, R10, LSR #1 /* R2 holds cache "Set" position */ - MOV R1, R6, LSR R2 /* Bottom 3 bits are the Cache-type for this level */ - AND R1, R1, #7 /* Isolate those lower 3 bits */ - CMP R1, #2 - BLT Skip /* No cache or only instruction cache at this level */ - - MCR p15, 2, R10, c0, c0, 0 /* Write the Cache Size selection register */ - ISB /* ISB to sync the change to the CacheSizeID reg */ - MRC p15, 1, R1, c0, c0, 0 /* Reads current Cache Size ID register */ - AND R2, R1, #7 /* Extract the line length field */ - ADD R2, R2, #4 /* Add 4 for the line length offset (log2 16 bytes) */ - LDR R4, =0x3FF - ANDS R4, R4, R1, LSR #3 /* R4 is the max number on the way size (right aligned) */ - CLZ R5, R4 /* R5 is the bit position of the way size increment */ - LDR R7, =0x7FFF - ANDS R7, R7, R1, LSR #13 /* R7 is the max number of the index size (right aligned) */ - -Loop2: MOV R9, R4 /* R9 working copy of the max way size (right aligned) */ - -Loop3: ORR R11, R10, R9, LSL R5 /* Factor in the Way number and cache number into R11 */ - ORR R11, R11, R7, LSL R2 /* Factor in the Set number */ - CMP R0, #0 - BNE Dccsw - MCR p15, 0, R11, c7, c6, 2 /* DCISW. Invalidate by Set/Way */ - B cont -Dccsw: CMP R0, #1 - BNE Dccisw - MCR p15, 0, R11, c7, c10, 2 /* DCCSW. Clean by Set/Way */ - B cont -Dccisw: MCR p15, 0, R11, c7, c14, 2 /* DCCISW, Clean and Invalidate by Set/Way */ -cont: SUBS R9, R9, #1 /* Decrement the Way number */ - BGE Loop3 - SUBS R7, R7, #1 /* Decrement the Set number */ - BGE Loop2 -Skip: ADD R10, R10, #2 /* increment the cache number */ - CMP R3, R10 - BGT Loop1 - -Finished: - DSB - POP {R4-R11} - BX lr - - - END -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ - diff --git a/doxyfile_options b/doxyfile_options index 33eb3a2478d..3018654640f 100644 --- a/doxyfile_options +++ b/doxyfile_options @@ -32,7 +32,7 @@ DOXYFILE_ENCODING = UTF-8 # title of most generated pages and in a few other places. # The default value is: My Project. -PROJECT_NAME = "My Project" +PROJECT_NAME = "Mbed OS Reference" # The PROJECT_NUMBER tag can be used to enter a project or revision number. This # could be handy for archiving the generated documentation or if some version @@ -837,7 +837,6 @@ EXCLUDE_SYMLINKS = YES # exclude all test directories for example use the pattern */test/* EXCLUDE_PATTERNS = */tools/* \ - */TESTS/* \ */targets/* \ */BUILD/* \ */rtos/TARGET_CORTEX/rtx* \ @@ -846,7 +845,6 @@ EXCLUDE_PATTERNS = */tools/* \ */features/mbedtls/* \ */features/storage/* \ */features/unsupported/* \ - */features/filesystem/* \ # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names # (namespaces, classes, functions, etc.) that should be excluded from the diff --git a/doxygen_options.json b/doxygen_options.json index 37433da2e86..ed187aca800 100644 --- a/doxygen_options.json +++ b/doxygen_options.json @@ -1,4 +1,5 @@ { + "PROJECT_NAME": "Mbed OS Reference", "ENABLE_PREPROCESSING": "YES", "MACRO_EXPANSION": "YES", "EXPAND_ONLY_PREDEF": "NO", @@ -8,5 +9,5 @@ "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\"", "EXPAND_AS_DEFINED": "", "SKIP_FUNCTION_MACROS": "NO", - "EXCLUDE_PATTERNS": "*/tools/* */TESTS/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */features/filesystem/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURES_*" + "EXCLUDE_PATTERNS": "*/tools/* */targets/* */FEATURE_*/* */features/mbedtls/* */features/storage/* */features/unsupported/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURES_*" } diff --git a/drivers/CAN.cpp b/drivers/CAN.cpp index e49b7adfcb7..b84d6082cee 100644 --- a/drivers/CAN.cpp +++ b/drivers/CAN.cpp @@ -46,6 +46,11 @@ CAN::CAN(PinName rd, PinName td, int hz) : _can(), _irq() { CAN::~CAN() { // No lock needed in destructor + + // Detaching interrupts releases the sleep lock if it was locked + for (int irq = 0; irq < IrqCnt; irq++) { + attach(NULL, (IrqType)irq); + } can_irq_free(&_can); can_free(&_can); } diff --git a/drivers/InterruptManager.cpp b/drivers/InterruptManager.cpp index ac8c83d88c7..9c2b4c2acb8 100644 --- a/drivers/InterruptManager.cpp +++ b/drivers/InterruptManager.cpp @@ -16,6 +16,12 @@ #include "cmsis.h" #if defined(NVIC_NUM_VECTORS) +// Suppress deprecation warnings since this whole +// class is deprecated already +#include "mbed_toolchain.h" +#undef MBED_DEPRECATED_SINCE +#define MBED_DEPRECATED_SINCE(...) + #include "drivers/InterruptManager.h" #include "platform/mbed_critical.h" #include diff --git a/drivers/InterruptManager.h b/drivers/InterruptManager.h index 80607381159..ac10ebc8789 100644 --- a/drivers/InterruptManager.h +++ b/drivers/InterruptManager.h @@ -60,10 +60,14 @@ class InterruptManager : private NonCopyable { * * @return the only instance of this class */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") static InterruptManager* get(); /** Destroy the current instance of the interrupt manager */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") static void destroy(); /** Add a handler for an interrupt at the end of the handler list @@ -74,6 +78,8 @@ class InterruptManager : private NonCopyable { * @returns * The function object created for 'function' */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) { // Underlying call is thread safe return add_common(function, irq); @@ -87,6 +93,8 @@ class InterruptManager : private NonCopyable { * @returns * The function object created for 'function' */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) { // Underlying call is thread safe return add_common(function, irq, true); @@ -102,6 +110,8 @@ class InterruptManager : private NonCopyable { * The function object created for 'tptr' and 'mptr' */ template + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) { // Underlying call is thread safe return add_common(tptr, mptr, irq); @@ -117,6 +127,8 @@ class InterruptManager : private NonCopyable { * The function object created for 'tptr' and 'mptr' */ template + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) { // Underlying call is thread safe return add_common(tptr, mptr, irq, true); @@ -130,6 +142,8 @@ class InterruptManager : private NonCopyable { * @returns * true if the handler was found and removed, false otherwise */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq); private: diff --git a/drivers/SerialBase.cpp b/drivers/SerialBase.cpp index e07a44149dd..5ec47ff83a6 100644 --- a/drivers/SerialBase.cpp +++ b/drivers/SerialBase.cpp @@ -133,6 +133,16 @@ void SerialBase:: unlock() { // Stub } +SerialBase::~SerialBase() +{ + // No lock needed in destructor + + // Detaching interrupts releases the sleep lock if it was locked + for (int irq = 0; irq < IrqCnt; irq++) { + attach(NULL, (IrqType)irq); + } +} + #if DEVICE_SERIAL_FC void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) { lock(); diff --git a/drivers/SerialBase.h b/drivers/SerialBase.h index 835e1a33b18..faf29a06998 100644 --- a/drivers/SerialBase.h +++ b/drivers/SerialBase.h @@ -241,8 +241,7 @@ class SerialBase : private NonCopyable { protected: SerialBase(PinName tx, PinName rx, int baud); - virtual ~SerialBase() { - } + virtual ~SerialBase(); int _base_getc(); int _base_putc(int c); diff --git a/drivers/Ticker.h b/drivers/Ticker.h index cc5e5dd9e04..c8f1f9deb33 100644 --- a/drivers/Ticker.h +++ b/drivers/Ticker.h @@ -22,6 +22,7 @@ #include "platform/NonCopyable.h" #include "platform/mbed_sleep.h" #include "hal/lp_ticker_api.h" +#include "platform/mbed_critical.h" namespace mbed { /** \addtogroup drivers */ @@ -113,12 +114,14 @@ class Ticker : public TimerEvent, private NonCopyable { * */ void attach_us(Callback func, us_timestamp_t t) { + core_util_critical_section_enter(); // lock only for the initial callback setup and this is not low power ticker if(!_function && _lock_deepsleep) { sleep_manager_lock_deep_sleep(); } _function = func; setup(t); + core_util_critical_section_exit(); } /** Attach a member function to be called by the Ticker, specifying the interval in micro-seconds diff --git a/drivers/Timer.cpp b/drivers/Timer.cpp index 5da9863d953..f523974e6b4 100644 --- a/drivers/Timer.cpp +++ b/drivers/Timer.cpp @@ -35,7 +35,9 @@ Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker Timer::~Timer() { core_util_critical_section_enter(); if (_running) { - sleep_manager_unlock_deep_sleep(); + if(_lock_deepsleep) { + sleep_manager_unlock_deep_sleep(); + } } _running = 0; core_util_critical_section_exit(); diff --git a/drivers/UARTSerial.cpp b/drivers/UARTSerial.cpp index 96cdc831d84..69aaa2fbade 100644 --- a/drivers/UARTSerial.cpp +++ b/drivers/UARTSerial.cpp @@ -19,7 +19,12 @@ #include #include "UARTSerial.h" #include "platform/mbed_poll.h" + +#if MBED_CONF_RTOS_PRESENT +#include "rtos/Thread.h" +#else #include "platform/mbed_wait_api.h" +#endif namespace mbed { @@ -27,6 +32,7 @@ UARTSerial::UARTSerial(PinName tx, PinName rx, int baud) : SerialBase(tx, rx, baud), _blocking(true), _tx_irq_enabled(false), + _rx_irq_enabled(true), _dcd_irq(NULL) { /* Attatch IRQ routines to the serial device. */ @@ -63,6 +69,22 @@ void UARTSerial::set_data_carrier_detect(PinName dcd_pin, bool active_high) } } +void UARTSerial::set_format(int bits, Parity parity, int stop_bits) +{ + api_lock(); + SerialBase::format(bits, parity, stop_bits); + api_unlock(); +} + +#if DEVICE_SERIAL_FC +void UARTSerial::set_flow_control(Flow type, PinName flow1, PinName flow2) +{ + api_lock(); + SerialBase::set_flow_control(type, flow1, flow2); + api_unlock(); +} +#endif + int UARTSerial::close() { /* Does not let us pass a file descriptor. So how to close ? @@ -171,6 +193,16 @@ ssize_t UARTSerial::read(void* buffer, size_t length) data_read++; } + core_util_critical_section_enter(); + if (!_rx_irq_enabled) { + UARTSerial::rx_irq(); // only read from hardware in one place + if (!_rxbuf.full()) { + SerialBase::attach(callback(this, &UARTSerial::rx_irq), RxIrq); + _rx_irq_enabled = true; + } + } + core_util_critical_section_exit(); + api_unlock(); return data_read; @@ -238,13 +270,14 @@ void UARTSerial::rx_irq(void) /* Fill in the receive buffer if the peripheral is readable * and receive buffer is not full. */ - while (SerialBase::readable()) { + while (!_rxbuf.full() && SerialBase::readable()) { char data = SerialBase::_base_getc(); - if (!_rxbuf.full()) { - _rxbuf.push(data); - } else { - /* Drop - can we report in some way? */ - } + _rxbuf.push(data); + } + + if (_rx_irq_enabled && _rxbuf.full()) { + SerialBase::attach(NULL, RxIrq); + _rx_irq_enabled = false; } /* Report the File handler that data is ready to be read from the buffer. */ @@ -277,6 +310,17 @@ void UARTSerial::tx_irq(void) } } +void UARTSerial::wait_ms(uint32_t millisec) +{ + /* wait_ms implementation for RTOS spins until exact microseconds - we + * want to just sleep until next tick. + */ +#if MBED_CONF_RTOS_PRESENT + rtos::Thread::wait(millisec); +#else + ::wait_ms(millisec); +#endif +} } //namespace mbed #endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN) diff --git a/drivers/UARTSerial.h b/drivers/UARTSerial.h index a269dea2855..afd98c107bc 100644 --- a/drivers/UARTSerial.h +++ b/drivers/UARTSerial.h @@ -39,6 +39,13 @@ namespace mbed { +/** \addtogroup drivers */ + +/** Class providing buffered UART communication functionality using separate circular buffer for send and receive channels + * + * @ingroup drivers + */ + class UARTSerial : private SerialBase, public FileHandle, private NonCopyable { public: @@ -164,8 +171,46 @@ class UARTSerial : private SerialBase, public FileHandle, private NonCopyable #include "mbed.h" +#if MBED_CONF_EVENTS_USE_LOWPOWER_TIMER_TICKER +#define ALIAS_TIMER LowPowerTimer +#define ALIAS_TICKER LowPowerTicker +#define ALIAS_TIMEOUT LowPowerTimeout +#else +#define ALIAS_TIMER Timer +#define ALIAS_TICKER Ticker +#define ALIAS_TIMEOUT Timeout +#endif // Ticker operations static bool equeue_tick_inited = false; static volatile unsigned equeue_minutes = 0; static unsigned equeue_timer[ - (sizeof(Timer)+sizeof(unsigned)-1)/sizeof(unsigned)]; + (sizeof(ALIAS_TIMER)+sizeof(unsigned)-1)/sizeof(unsigned)]; static unsigned equeue_ticker[ - (sizeof(Ticker)+sizeof(unsigned)-1)/sizeof(unsigned)]; + (sizeof(ALIAS_TICKER)+sizeof(unsigned)-1)/sizeof(unsigned)]; static void equeue_tick_update() { - equeue_minutes += reinterpret_cast(equeue_timer)->read_ms(); - reinterpret_cast(equeue_timer)->reset(); + equeue_minutes += reinterpret_cast(equeue_timer)->read_ms(); + reinterpret_cast(equeue_timer)->reset(); } static void equeue_tick_init() { - MBED_STATIC_ASSERT(sizeof(equeue_timer) >= sizeof(Timer), + MBED_STATIC_ASSERT(sizeof(equeue_timer) >= sizeof(ALIAS_TIMER), "The equeue_timer buffer must fit the class Timer"); - MBED_STATIC_ASSERT(sizeof(equeue_ticker) >= sizeof(Ticker), + MBED_STATIC_ASSERT(sizeof(equeue_ticker) >= sizeof(ALIAS_TICKER), "The equeue_ticker buffer must fit the class Ticker"); - Timer *timer = new (equeue_timer) Timer; - Ticker *ticker = new (equeue_ticker) Ticker; + ALIAS_TIMER *timer = new (equeue_timer) ALIAS_TIMER; + ALIAS_TICKER *ticker = new (equeue_ticker) ALIAS_TICKER; equeue_minutes = 0; timer->start(); @@ -62,7 +71,7 @@ unsigned equeue_tick() { do { minutes = equeue_minutes; - ms = reinterpret_cast(equeue_timer)->read_ms(); + ms = reinterpret_cast(equeue_timer)->read_ms(); } while (minutes != equeue_minutes); return minutes + ms; @@ -132,7 +141,7 @@ static void equeue_sema_timeout(equeue_sema_t *s) { bool equeue_sema_wait(equeue_sema_t *s, int ms) { int signal = 0; - Timeout timeout; + ALIAS_TIMEOUT timeout; if (ms == 0) { return false; } else if (ms > 0) { diff --git a/events/mbed_lib.json b/events/mbed_lib.json index 0f786f66376..1dbc1794b40 100644 --- a/events/mbed_lib.json +++ b/events/mbed_lib.json @@ -21,6 +21,10 @@ "shared-highprio-eventsize": { "help": "Event buffer size (bytes) for shared high-priority event queue", "value": 256 + }, + "use-lowpower-timer-ticker": { + "help": "Enable use of low power timer and ticker classes. May reduce the accuracy of the event queue.", + "value": 0 } } } diff --git a/features/FEATURE_BLE/ble/ArrayView.h b/features/FEATURE_BLE/ble/ArrayView.h index 5cf7336c1dd..d2a2b6d1357 100644 --- a/features/FEATURE_BLE/ble/ArrayView.h +++ b/features/FEATURE_BLE/ble/ArrayView.h @@ -20,28 +20,67 @@ #include #include +/** + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ + +/** + * @file + */ + namespace ble { /** * Immutable view to an array. + * + * Array views encapsulate the pointer to an array and its size into a single + * object; however, it does not manage the lifetime of the array viewed. + * You can use instances of ArrayView to replace the traditional pair of pointer + * and size arguments in function calls. + * + * You can use the size member function to query the number of elements present + * in the array, and overloads of the subscript operator allow code using + * this object to access to the content of the array viewed. + * + * @note You can create ArrayView instances with the help of the function + * template make_ArrayView() and make_const_ArrayView(). + * + * @tparam T type of objects held by the array. */ template struct ArrayView { /** - * construct an array view to an empty array + * Construct a view to an empty array. + * + * @post a call to size() will return 0, and data() will return NULL. */ ArrayView() : _array(0), _size(0) { } /** - * construct an array view from a pointer. - * and its size. + * Construct an array view from a pointer to a buffer and its size. + * + * @param array_ptr Pointer to the array data + * @param array_size Number of elements of T present in the array. + * + * @post a call to size() will return array_size and data() will return + * array_tpr. */ ArrayView(T* array_ptr, size_t array_size) : _array(array_ptr), _size(array_size) { } /** * Construct an array view from the reference to an array. + * + * @param elements Reference to the array viewed. + * + * @tparam Size Number of elements of T presents in the array. + * + * @post a call to size() will return Size, and data() will return + * a pointer to elements. */ template ArrayView(T (&elements)[Size]): @@ -49,43 +88,73 @@ struct ArrayView { /** * Return the size of the array viewed. + * + * @return The number of elements present in the array viewed. */ - size_t size() const { + size_t size() const + { return _size; } /** * Access to a mutable element of the array. + * + * @param index Element index to access. + * + * @return A reference to the element at the index specified in input. + * + * @pre index shall be less than size(). */ - T& operator[](size_t index) { + T& operator[](size_t index) + { return _array[index]; } /** * Access to an immutable element of the array. + * + * @param index Element index to access. + * + * @return A const reference to the element at the index specified in input. + * + * @pre index shall be less than size(). */ - const T& operator[](size_t index) const { + const T& operator[](size_t index) const + { return _array[index]; } /** - * Get the pointer to the array + * Get the raw pointer to the array. + * + * @return The raw pointer to the array. */ - T* data() { + T* data() + { return _array; } /** - * Get the pointer to the const array + * Get the raw const pointer to the array. + * + * @return The raw pointer to the array. */ - const T* data() const { + const T* data() const + { return _array; } /** - * Equality operator + * Equality operator. + * + * @param lhs Left hand side of the binary operation. + * @param rhs Right hand side of the binary operation. + * + * @return True if arrays in input have the same size and the same content + * and false otherwise. */ - friend bool operator==(const ArrayView& lhs, const ArrayView& rhs) { + friend bool operator==(const ArrayView& lhs, const ArrayView& rhs) + { if (lhs.size() != rhs.size()) { return false; } @@ -99,8 +168,15 @@ struct ArrayView { /** * Not equal operator + * + * @param lhs Left hand side of the binary operation. + * @param rhs Right hand side of the binary operation. + * + * @return True if arrays in input do not have the same size or the same + * content and false otherwise. */ - friend bool operator!=(const ArrayView& lhs, const ArrayView& rhs) { + friend bool operator!=(const ArrayView& lhs, const ArrayView& rhs) + { return !(lhs == rhs); } @@ -111,55 +187,86 @@ struct ArrayView { /** - * Generate an array view from a C/C++ array. - * This helper avoid the typing of template parameter when ArrayView are + * Generate an array view from a reference to a C/C++ array. + * + * @tparam T Type of elements held in elements. + * @tparam Size Number of items held in elements. + * + * @param elements The reference to the array viewed. + * + * @return The ArrayView to elements. + * + * @note This helper avoids the typing of template parameter when ArrayView is * created 'inline'. - * @param elements The array viewed. - * @return The array_view to elements. */ template -ArrayView make_ArrayView(T (&elements)[Size]) { +ArrayView make_ArrayView(T (&elements)[Size]) +{ return ArrayView(elements); } /** * Generate an array view from a C/C++ pointer and the size of the array. - * This helper avoid the typing of template parameter when ArrayView are + * + * @tparam T Type of elements held in array_ptr. + * + * @param array_ptr The pointer to the array to viewed. + * @param array_size The number of T elements in the array. + * + * @return The ArrayView to array_ptr with a size of array_size. + * + * @note This helper avoids the typing of template parameter when ArrayView is * created 'inline'. - * @param array_ptr The pointer to the array to view. - * @param array_size The size of the array. - * @return The array_view to array_ptr with a size of array_size. */ template -ArrayView make_ArrayView(T* array_ptr, size_t array_size) { +ArrayView make_ArrayView(T* array_ptr, size_t array_size) +{ return ArrayView(array_ptr, array_size); } /** - * Generate a const array view from a C/C++ array. - * This helper avoid the typing of template parameter when ArrayView are - * created 'inline'. + * Generate a const array view from a reference to a C/C++ array. + * + * @tparam T Type of elements held in elements. + * @tparam Size Number of items held in elements. + * * @param elements The array viewed. * @return The ArrayView to elements. + * + * @note This helper avoids the typing of template parameter when ArrayView is + * created 'inline'. */ template -ArrayView make_const_ArrayView(T (&elements)[Size]) { +ArrayView make_const_ArrayView(T (&elements)[Size]) +{ return ArrayView(elements); } /** * Generate a const array view from a C/C++ pointer and the size of the array. - * This helper avoid the typing of template parameter when ArrayView are - * created 'inline'. - * @param array_ptr The pointer to the array to view. - * @param array_size The size of the array. + * + * @tparam T Type of elements held in array_ptr. + * + * @param array_ptr The pointer to the array to viewed. + * @param array_size The number of T elements in the array. + * * @return The ArrayView to array_ptr with a size of array_size. + * + * @note This helper avoids the typing of template parameter when ArrayView is + * created 'inline'. */ template -ArrayView make_const_ArrayView(T* array_ptr, size_t array_size) { +ArrayView make_const_ArrayView(T* array_ptr, size_t array_size) +{ return ArrayView(array_ptr, array_size); } } // namespace ble +/** + * @} + * @} + */ + + #endif /* BLE_ARRAY_VIEW_H_ */ diff --git a/features/FEATURE_BLE/ble/BLE.h b/features/FEATURE_BLE/ble/BLE.h index 9cd27f58ef6..0aea37dc32c 100644 --- a/features/FEATURE_BLE/ble/BLE.h +++ b/features/FEATURE_BLE/ble/BLE.h @@ -14,13 +14,14 @@ * limitations under the License. */ -#ifndef __BLE_H__ -#define __BLE_H__ +#ifndef MBED_BLE_H__ +#define MBED_BLE_H__ #include "blecommon.h" #include "Gap.h" #include "GattServer.h" #include "GattClient.h" +#include "SecurityManager.h" #include "ble/FunctionPointerWithContext.h" @@ -30,21 +31,162 @@ #include "mbed_error.h" #endif +#include "platform/mbed_toolchain.h" + /* Forward declaration for the implementation class */ class BLEInstanceBase; /** - * The base class used to abstract away BLE-capable radio transceivers or SOCs, - * so that the BLE API can work with any radio transparently. + * @addtogroup ble + * @{ + */ + +/** + * Abstract away BLE-capable radio transceivers or SOCs. + * + * Instances of this class have three responsibilities: + * - Initialize the inner BLE subsystem. + * - Signal user code that BLE events are available and an API to process them. + * - Manage access to the instances abstracting each BLE layer: + * + GAP: Handle advertising and scan, as well as connection and + * disconnection. + * + GATTServer: API to construct and manage a GATT server, which connected peers can + * access. + * + GATTClient: API to interact with a peer GATT server. + * + SecurityManager: API to manage security. + * + * The user should not create BLE instances directly but rather access to the + * singleton(s) holding the BLE interfaces present in the system by using the + * static function Instance(). + * + * @code + * #include "ble/BLE.h" + * + * BLE& ble_interface = BLE::Instance(); + * @endcode + * + * Next, the signal handling/process mechanism should be set up. By design, + * Mbed BLE does not impose to the user an event handling/processing mechanism; + * however, it exposes APIs, which allows an application to compose its own: + * - onEventsToProcess(), whichs register a callback that + * the BLE subsystem will call when there is an event ready to be processed. + * - processEvents(), which processes all the events present in the BLE subsystem. + * + * It is common to bind BLE event mechanism with Mbed EventQueue: + * + * @code + * #include + * #include "ble/BLE.h" + * + * // declare the event queue, which the whole application will share. + * static EventQueue event_queue( 4 * EVENTS_EVENT_SIZE); + * + * // Function invoked when there is a BLE event available. + * // It put into the event queue the processing of the event(s) + * void schedule_ble_processing(BLE::OnEventsToProcessCallbackContext* context) { + * event_queue.call(callback(&(context->ble), &BLE::processEvents)); + * } + * + * int main() + * { + * BLE &ble_interface = BLE::Instance(); + * + * // Bind event signaling to schedule_ble_processing + * ble_interface.onEventsToProcess(schedule_ble_processing); + * + * // Launch BLE initialisation + * + * // Dispatch events in the event queue + * event_queue.dispatch_forever(); + * return 0; + * } + * @endcode + * + * Once the event processing mechanism is in place, the Bluetooth subsystem can + * be initialized with the init() function. That function accepts in input a + * callback, which will be invoked once the initialization process has finished. + * + * @code + * void on_ble_init_complete(BLE::InitializationCompleteCallbackContext *context) + * { + * BLE& ble_interface = context->ble; + * ble_error_t initialization_error = context->error; + * + * if (initialization_error) { + * // handle error + * return; + * } + * + * // The BLE interface can be accessed now. + * } + * + * int main() { + * BLE &ble_interface = BLE::Instance(); + * ble_interface.onEventsToProcess(schedule_ble_processing); + * + * // Initialize the BLE interface + * ble_interface.init(on_ble_init_complete); + * + * event_queue.dispatch_forever(); + * return 0; + * } + * @endcode */ class BLE { public: - typedef unsigned InstanceID_t; /**< The type returned by BLE::getInstanceID(). */ + /** + * Opaque type used to store the ID of a BLE instance. + */ + typedef unsigned InstanceID_t; + + /** + * The value of the BLE::InstanceID_t for the default BLE instance. + */ + static const InstanceID_t DEFAULT_INSTANCE = 0; + +#ifndef YOTTA_CFG_BLE_INSTANCES_COUNT + /** + * The number of permitted BLE instances for the application. + */ + static const InstanceID_t NUM_INSTANCES = 1; +#else + /** + * The number of permitted BLE instances for the application. + */ + static const InstanceID_t NUM_INSTANCES = YOTTA_CFG_BLE_INSTANCES_COUNT; +#endif + + /** + * Get a reference to the BLE singleton corresponding to a given interface. + * + * There is a static array of BLE singletons. + * + * @note Calling Instance() is preferred over constructing a BLE object + * directly because it returns references to singletons. + * + * @param[in] id BLE Instance ID to get. + * + * @return A reference to a single object. + * + * @pre id shall be less than NUM_INSTANCES. + */ + static BLE &Instance(InstanceID_t id = DEFAULT_INSTANCE); /** - * Parameters provided to the callback registered by onEventsToProcess - * when there is events to process. + * Fetch the ID of a BLE instance. + * + * @return Instance id of this BLE instance. + */ + InstanceID_t getInstanceID(void) const { + return instanceID; + } + + /** + * Events to process event. + * + * Instances of OnEventsToProcessCallbackContext are passed to the event + * handler registered with onEventsToProcess(). */ struct OnEventsToProcessCallbackContext { /** @@ -54,109 +196,149 @@ class BLE }; /** - * Callback type used by the onEventsToProcess function. + * Events to process event handler + */ + typedef FunctionPointerWithContext + OnEventsToProcessCallback_t; + + /** + * Register a callback called when the BLE stack has pending work. + * + * By registering a callback, application code can know when event processing + * has to be scheduled. + * + * @param on_event_cb Callback invoked when there are new events to process. */ - typedef FunctionPointerWithContext OnEventsToProcessCallback_t; + void onEventsToProcess(const OnEventsToProcessCallback_t& on_event_cb); /** - * The context provided to init-completion-callbacks (see init() below). + * Process ALL pending events living in the BLE stack and return once all + * events have been consumed. * - * @param ble - * A reference to the BLE instance being initialized. - * @param error - * Captures the result of initialization. It is set to - * BLE_ERROR_NONE if initialization completed successfully. Else - * the error value is implementation specific. + * @see onEventsToProcess() + */ + void processEvents(); + + /** + * Initialization complete event. + * + * This event is generated at the end of the init() procedure and is passed + * to the completion callback passed to init(). */ struct InitializationCompleteCallbackContext { - BLE& ble; /**< Reference to the BLE object that has been initialized */ - ble_error_t error; /**< Error status of the initialization. It is set to BLE_ERROR_NONE if initialization completed successfully. */ + /** + * Reference to the BLE object that has been initialized + */ + BLE& ble; + + /** + * Error status of the initialization. + * + * That value is set to BLE_ERROR_NONE if initialization completed + * successfully or the appropriate error code otherwise. + * */ + ble_error_t error; }; /** - * The signature for function-pointer like callbacks for initialization-completion. + * Initialization complete event handler. * - * @note There are two versions of init(). In addition to the simple - * function-pointer, init() can also take a tuple as its - * callback target. In case of the latter, the following declaration doesn't apply. + * @note There are two versions of init(). In addition to the + * function-pointer, init() can also take an tuple as its + * callback target. In case of the latter, the following declaration doesn't + * apply. */ - typedef void (*InitializationCompleteCallback_t)(InitializationCompleteCallbackContext *context); + typedef void (*InitializationCompleteCallback_t)( + InitializationCompleteCallbackContext *context + ); /** - * Initialize the BLE controller. This should be called before using - * anything else in the BLE API. + * Initialize the BLE controller/stack. * * init() hands control to the underlying BLE module to accomplish * initialization. This initialization may tacitly depend on other hardware - * setup (such as clocks or power-modes) that happens early on during - * system startup. It may not be safe to call init() from a global static - * context where ordering is compiler-specific and can't be guaranteed - it - * is safe to call BLE::init() from within main(). + * setup (such as clocks or power-modes) that happens early on during system + * startup. It may not be safe to call init() from a global static context + * where ordering is compiler-specific and can't be guaranteed - it is safe + * to call BLE::init() from within main(). * - * @param initCompleteCallback - * A callback for when initialization completes for a BLE - * instance. This is an optional parameter; if no callback is - * set up the application can still determine the status of - * initialization using BLE::hasInitialized() (see below). + * @param[in] completion_cb A callback for when initialization completes for + * a BLE instance. This is an optional parameter; if no callback is set up, + * the application can still determine the status of initialization using + * BLE::hasInitialized() (see below). * - * @return BLE_ERROR_NONE if the initialization procedure was started - * successfully. + * @return BLE_ERROR_NONE if the initialization procedure started + * successfully. * * @note If init() returns BLE_ERROR_NONE, the underlying stack must invoke - * the initialization completion callback at some point. + * the initialization completion callback at some point. + * + * @note Nearly all BLE APIs would return BLE_ERROR_INITIALIZATION_INCOMPLETE + * if used on an instance before the corresponding transport is initialized. * - * @note Nearly all BLE APIs would return - * BLE_ERROR_INITIALIZATION_INCOMPLETE if used on an instance before the - * corresponding transport is initialized. + * @note There are two versions of init(). In addition to the + * function-pointer, init() can also take an pair as its + * callback target. * - * @note There are two versions of init(). In addition to the simple - * function-pointer, init() can also take an tuple as its - * callback target. + * @important This should be called before using anything else in the BLE + * API. */ - ble_error_t init(InitializationCompleteCallback_t initCompleteCallback = NULL) { - FunctionPointerWithContext callback(initCompleteCallback); + ble_error_t init(InitializationCompleteCallback_t completion_cb = NULL) { + FunctionPointerWithContext callback(completion_cb); return initImplementation(callback); } /** - * An alternate declaration for init(). This one takes an tuple as its - * callback target. + * Initialize the BLE controller/stack. + * + * This is an alternate declaration for init(). This one takes an + * pair as its callback target. + * + * @param[in] object Object, which will be used to invoke the completion callback. + * @param[in] completion_cb Member function pointer, which will be invoked when + * initialization is complete. */ template - ble_error_t init(T *object, void (T::*initCompleteCallback)(InitializationCompleteCallbackContext *context)) { - FunctionPointerWithContext callback(object, initCompleteCallback); + ble_error_t init(T *object, void (T::*completion_cb)(InitializationCompleteCallbackContext *context)) { + FunctionPointerWithContext callback(object, completion_cb); return initImplementation(callback); } /** + * Indicate if the BLE instance has been initialized. + * * @return true if initialization has completed for the underlying BLE - * transport. + * transport. * - * The application can set up a callback to signal completion of - * initialization when using init(). Otherwise, this method can be used to - * poll the state of initialization. + * @note The application should set up a callback to signal completion of + * initialization when using init(). */ bool hasInitialized(void) const; /** - * Purge the BLE stack of GATT and GAP state. init() must be called - * afterwards to re-instate services and GAP state. This API offers a way to - * repopulate the GATT database with new services and characteristics. + * Shut down the underlying stack, and reset state of this BLE instance. + * + * @return BLE_ERROR_NONE if the instance was shut down without error or the + * appropriate error code. + * + * @important init() must be called afterward to reinstate services and + * GAP state. This API offers a way to repopulate the GATT database with new + * services and characteristics. */ ble_error_t shutdown(void); /** * This call allows the application to get the BLE stack version information. * - * @return A pointer to a const string representing the version. + * @return A pointer to a const string representing the version. * - * @note The string returned is owned by BLE API. + * @note The BLE API owns the string returned. */ const char *getVersion(void); /** - * Accessor to Gap. All Gap related functionality requires - * going through this accessor. + * Accessor to Gap. All Gap-related functionality requires going through + * this accessor. * * @return A reference to a Gap object associated to this BLE instance. */ @@ -180,13 +362,14 @@ class BLE /** * A const alternative to gattServer(). * - * @return A const reference to a GattServer object associated to this BLE instance. + * @return A const reference to a GattServer object associated to this BLE + * instance. */ const GattServer& gattServer() const; /** - * Accessors to GattClient. All GattClient related functionality requires going - * through this accessor. + * Accessors to GattClient. All GattClient related functionality requires + * going through this accessor. * * @return A reference to a GattClient object associated to this BLE instance. */ @@ -195,66 +378,34 @@ class BLE /** * A const alternative to gattClient(). * - * @return A const reference to a GattClient object associated to this BLE instance. + * @return A const reference to a GattClient object associated to this BLE + * instance. */ const GattClient& gattClient() const; /** - * Accessors to SecurityManager. All SecurityManager related functionality requires - * going through this accessor. + * Accessors to SecurityManager. All SecurityManager-related functionality + * requires going through this accessor. * - * @return A reference to a SecurityManager object associated to this BLE instance. + * @return A reference to a SecurityManager object associated to this BLE + * instance. */ SecurityManager& securityManager(); /** * A const alternative to securityManager(). * - * @return A const reference to a SecurityManager object associated to this BLE instance. + * @return A const reference to a SecurityManager object associated to this + * BLE instance. */ const SecurityManager& securityManager() const; - /** - * Yield control to the BLE stack or to other tasks waiting for events. This - * is a sleep function that will return when there is an application-specific - * interrupt, but the MCU might wake up several times before - * returning (to service the stack). This is not always interchangeable with - * WFE(). + /* + * Deprecation alert! + * All of the following are deprecated and may be dropped in a future + * release. Documentation should refer to alternative APIs. */ - void waitForEvent(void); - public: - /** - * The value of the BLE::InstanceID_t for the default BLE instance. - */ - static const InstanceID_t DEFAULT_INSTANCE = 0; -#ifndef YOTTA_CFG_BLE_INSTANCES_COUNT - /** - * The number of permitted BLE instances for the application. - */ - static const InstanceID_t NUM_INSTANCES = 1; -#else - /** - * The number of permitted BLE instances for the application. - */ - static const InstanceID_t NUM_INSTANCES = YOTTA_CFG_BLE_INSTANCES_COUNT; -#endif - - /** - * Get a reference to the BLE singleton corresponding to a given interface. - * There is a static array of BLE singletons. - * - * @note Calling Instance() is preferred over constructing a BLE object - * directly, as it returns references to singletons. - * - * @param[in] id - * Instance-ID. This should be less than NUM_INSTANCES - * for the returned BLE singleton to be useful. - * - * @return A reference to a single object. - */ - static BLE &Instance(InstanceID_t id = DEFAULT_INSTANCE); - /** * Constructor for a handle to a BLE instance (the BLE stack). BLE handles * are thin wrappers around a transport object (that is, ptr. to @@ -262,60 +413,70 @@ class BLE * * It is better to create BLE objects as singletons accessed through the * Instance() method. If multiple BLE handles are constructed for the same - * interface (using this constructor), they will share the same underlying + * interface (using this constructor), they share the same underlying * transport object. + * + * @deprecated Use the Instance() function instead of the constructor. */ + MBED_DEPRECATED("Use BLE::Instance() instead of BLE constructor.") BLE(InstanceID_t instanceID = DEFAULT_INSTANCE); /** - * Fetch the ID of a BLE instance. Typically there would only be the DEFAULT_INSTANCE. - */ - InstanceID_t getInstanceID(void) const { - return instanceID; - } - - /* - * Deprecation alert! - * All of the following are deprecated and may be dropped in a future - * release. Documentation should refer to alternative APIs. + * Yield control to the BLE stack or to other tasks waiting for events. + * + * This is a sleep function that returns when there is an application-specific + * interrupt. This is not interchangeable with WFE() considering that the + * MCU might wake up several times to service the stack before returning + * control to the caller. + * + * @deprecated This function block the CPU prefer to use the pair + * onEventsToProcess() and processEvents(). */ + MBED_DEPRECATED("Use BLE::processEvents() and BLE::onEventsToProcess().") + void waitForEvent(void); - /* GAP specific APIs. */ -public: /** * Set the BTLE MAC address and type. + * * @return BLE_ERROR_NONE on success. * * @deprecated You should use the parallel API from Gap directly, refer to - * Gap::setAddress(). A former call to - * ble.setAddress(...) should be replaced with - * ble.gap().setAddress(...). - */ - ble_error_t setAddress(BLEProtocol::AddressType_t type, const BLEProtocol::AddressBytes_t address) { + * Gap::setAddress(). A former call to ble.setAddress(...) should be + * replaced with ble.gap().setAddress(...). + */ + MBED_DEPRECATED("Use ble.gap().setAddress(...)") + ble_error_t setAddress( + BLEProtocol::AddressType_t type, + const BLEProtocol::AddressBytes_t address + ) { return gap().setAddress(type, address); } /** * Fetch the Bluetooth Low Energy MAC address and type. + * * @return BLE_ERROR_NONE on success. * - * @deprecated You should use the parallel API from Gap directly, refer to - * Gap::getAddress(). A former call to - * ble.getAddress(...) should be replaced with - * ble.gap().getAddress(...). + * @deprecated You should use the parallel API from Gap directly and refer to + * Gap::getAddress(). A former call to ble.getAddress(...) should be + * replaced with ble.gap().getAddress(...). */ - ble_error_t getAddress(BLEProtocol::AddressType_t *typeP, BLEProtocol::AddressBytes_t address) { + MBED_DEPRECATED("Use ble.gap().getAddress(...)") + ble_error_t getAddress( + BLEProtocol::AddressType_t *typeP, BLEProtocol::AddressBytes_t address + ) { return gap().getAddress(typeP, address); } /** * Set the GAP advertising mode to use for this device. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setAdvertisingType(). A former call to * ble.setAdvertisingType(...) should be replaced with * ble.gap().setAdvertisingType(...). */ + MBED_DEPRECATED("Use ble.gap().setAdvertisingType(...)") void setAdvertisingType(GapAdvertisingParams::AdvertisingType advType) { gap().setAdvertisingType(advType); } @@ -332,10 +493,10 @@ class BLE * to ADV_CONNECTABLE_DIRECTED. * * @note Decreasing this value allows central devices to detect a - * peripheral faster, at the expense of more power being used by the radio + * peripheral faster at the expense of more power being used by the radio * due to the higher data transmit rate. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setAdvertisingInterval(). A former call to * ble.setAdvertisingInterval(...) should be replaced with * ble.gap().setAdvertisingInterval(...). @@ -346,6 +507,7 @@ class BLE * no longer required as the new units are milliseconds. Any application * code depending on the old semantics needs to be updated accordingly. */ + MBED_DEPRECATED("Use ble.gap().setAdvertisingInterval(...)") void setAdvertisingInterval(uint16_t interval) { gap().setAdvertisingInterval(interval); } @@ -358,18 +520,20 @@ class BLE * ble.getMinAdvertisingInterval(...) should be replaced with * ble.gap().getMinAdvertisingInterval(...). */ + MBED_DEPRECATED("Use ble.gap().getMinAdvertisingInterval(...)") uint16_t getMinAdvertisingInterval(void) const { return gap().getMinAdvertisingInterval(); } /** - * @return Minimum Advertising interval in milliseconds for non-connectible mode. + * @return Minimum Advertising interval in milliseconds for nonconnectible mode. * * @deprecated You should use the parallel API from Gap directly, refer to * Gap::MinNonConnectableAdvertisingInterval(). A former call to * ble.getMinNonConnectableAdvertisingInterval(...) should be replaced with * ble.gap().getMinNonConnectableAdvertisingInterval(...). */ + MBED_DEPRECATED("Use ble.gap().getMinNonConnectableAdvertisingInterval(...)") uint16_t getMinNonConnectableAdvertisingInterval(void) const { return gap().getMinNonConnectableAdvertisingInterval(); } @@ -382,6 +546,7 @@ class BLE * ble.getMaxAdvertisingInterval(...) should be replaced with * ble.gap().getMaxAdvertisingInterval(...). */ + MBED_DEPRECATED("Use ble.gap().getMaxAdvertisingInterval(...)") uint16_t getMaxAdvertisingInterval(void) const { return gap().getMaxAdvertisingInterval(); } @@ -391,11 +556,12 @@ class BLE * Advertising timeout (in seconds) between 0x1 and 0x3FFF (1 * and 16383). Use 0 to disable the advertising timeout. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setAdvertisingTimeout(). A former call to * ble.setAdvertisingTimeout(...) should be replaced with * ble.gap().setAdvertisingTimeout(...). */ + MBED_DEPRECATED("Use ble.gap().setAdvertisingTimeout(...)") void setAdvertisingTimeout(uint16_t timeout) { gap().setAdvertisingTimeout(timeout); } @@ -406,11 +572,12 @@ class BLE * directly; there are other APIs to tweak advertisement parameters * individually (see above). * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setAdvertisingParams(). A former call to * ble.setAdvertisingParams(...) should be replaced with * ble.gap().setAdvertisingParams(...). */ + MBED_DEPRECATED("Use ble.gap().setAdvertisingParams(...)") void setAdvertisingParams(const GapAdvertisingParams &advParams) { gap().setAdvertisingParams(advParams); } @@ -419,11 +586,12 @@ class BLE * @return Read back advertising parameters. Useful for storing and * restoring parameters rapidly. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::getAdvertisingParams(). A former call to * ble.getAdvertisingParams(...) should be replaced with * ble.gap().getAdvertisingParams(...). */ + MBED_DEPRECATED("Use ble.gap().getAdvertisingParams(...)") const GapAdvertisingParams &getAdvertisingParams(void) const { return gap().getAdvertisingParams(); } @@ -444,6 +612,7 @@ class BLE * ble.accumulateAdvertisingPayload(flags) should be replaced with * ble.gap().accumulateAdvertisingPayload(flags). */ + MBED_DEPRECATED("Use ble.gap().accumulateAdvertisingPayload(flags)") ble_error_t accumulateAdvertisingPayload(uint8_t flags) { return gap().accumulateAdvertisingPayload(flags); } @@ -457,12 +626,13 @@ class BLE * @param[in] app * The appearance of the peripheral. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::accumulateAdvertisingPayload(GapAdvertisingData::Appearance). * A former call to ble.accumulateAdvertisingPayload(appearance) * should be replaced with * ble.gap().accumulateAdvertisingPayload(appearance). */ + MBED_DEPRECATED("Use ble.gap().accumulateAdvertisingPayload(appearance)") ble_error_t accumulateAdvertisingPayload(GapAdvertisingData::Appearance app) { return gap().accumulateAdvertisingPayload(app); } @@ -477,11 +647,12 @@ class BLE * The max transmit power to be used by the controller. This * is only a hint. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::accumulateAdvertisingPayloadTxPower(). A former call to * ble.accumulateAdvertisingPayloadTxPower(txPower) should be replaced with * ble.gap().accumulateAdvertisingPayloadTxPower(txPower). */ + MBED_DEPRECATED("Use ble.gap().accumulateAdvertisingPayloadTxPower(...)") ble_error_t accumulateAdvertisingPayloadTxPower(int8_t power) { return gap().accumulateAdvertisingPayloadTxPower(power); } @@ -501,12 +672,13 @@ class BLE * A former call to ble.accumulateAdvertisingPayload(...) should * be replaced with ble.gap().accumulateAdvertisingPayload(...). */ + MBED_DEPRECATED("Use ble.gap().accumulateAdvertisingPayload(...)") ble_error_t accumulateAdvertisingPayload(GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len) { return gap().accumulateAdvertisingPayload(type, data, len); } /** - * Setup a particular, user-constructed advertisement payload for the + * Set up a particular, user-constructed advertisement payload for the * underlying stack. It would be uncommon for this API to be used directly; * there are other APIs to build an advertisement payload (see above). * @@ -515,6 +687,7 @@ class BLE * ble.setAdvertisingData(...) should be replaced with * ble.gap().setAdvertisingPayload(...). */ + MBED_DEPRECATED("Use ble.gap().setAdvertisingData(...)") ble_error_t setAdvertisingData(const GapAdvertisingData &advData) { return gap().setAdvertisingPayload(advData); } @@ -528,6 +701,7 @@ class BLE * ble.getAdvertisingData(...) should be replaced with * ble.gap().getAdvertisingPayload()(...). */ + MBED_DEPRECATED("Use ble.gap().getAdvertisingData(...)") const GapAdvertisingData &getAdvertisingData(void) const { return gap().getAdvertisingPayload(); } @@ -537,11 +711,12 @@ class BLE * accumulateAdvertisingPayload(). This automatically propagates the re- * initialized advertising payload to the underlying stack. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::clearAdvertisingPayload(). A former call to * ble.clearAdvertisingPayload(...) should be replaced with * ble.gap().clearAdvertisingPayload(...). */ + MBED_DEPRECATED("Use ble.gap().clearAdvertisingPayload(...)") void clearAdvertisingPayload(void) { gap().clearAdvertisingPayload(); } @@ -549,7 +724,7 @@ class BLE /** * Dynamically reset the accumulated advertising * payload and scanResponse. The application must clear and re- - * accumulates a new advertising payload (and scanResponse) before using this + * accumulate a new advertising payload (and scanResponse) before using this * API. * * @return BLE_ERROR_NONE when the advertising payload is set successfully. @@ -560,6 +735,7 @@ class BLE * @note The new APIs in Gap update the underlying advertisement payload * implicitly. */ + MBED_DEPRECATED("Use ble.gap().setAdvertisingPayload(...)") ble_error_t setAdvertisingPayload(void) { return BLE_ERROR_NONE; } @@ -572,11 +748,12 @@ class BLE * @param[in] data Data bytes. * @param[in] len Data length. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::accumulateScanResponse(). A former call to * ble.accumulateScanResponse(...) should be replaced with * ble.gap().accumulateScanResponse(...). */ + MBED_DEPRECATED("Use ble.gap().accumulateScanResponse(...)") ble_error_t accumulateScanResponse(GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len) { return gap().accumulateScanResponse(type, data, len); } @@ -585,11 +762,12 @@ class BLE * Reset any scan response prepared from prior calls to * accumulateScanResponse(). * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::clearScanResponse(). A former call to * ble.clearScanResponse(...) should be replaced with * ble.gap().clearScanResponse(...). */ + MBED_DEPRECATED("Use ble.gap().clearScanResponse(...)") void clearScanResponse(void) { gap().clearScanResponse(); } @@ -597,11 +775,12 @@ class BLE /** * Start advertising. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::startAdvertising(). A former call to * ble.startAdvertising(...) should be replaced with * ble.gap().startAdvertising(...). */ + MBED_DEPRECATED("Use ble.gap().startAdvertising(...)") ble_error_t startAdvertising(void) { return gap().startAdvertising(); } @@ -609,11 +788,12 @@ class BLE /** * Stop advertising. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::stopAdvertising(). A former call to * ble.stopAdvertising(...) should be replaced with * ble.gap().stopAdvertising(...). */ + MBED_DEPRECATED("Use ble.gap().stopAdvertising(...)") ble_error_t stopAdvertising(void) { return gap().stopAdvertising(); } @@ -642,11 +822,12 @@ class BLE * * @note The scan interval and window are recommendations to the BLE stack. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setScanParams(). A former call to * ble.setScanParams(...) should be replaced with * ble.gap().setScanParams(...). */ + MBED_DEPRECATED("Use ble.gap().setScanParams(...)") ble_error_t setScanParams(uint16_t interval = GapScanningParams::SCAN_INTERVAL_MAX, uint16_t window = GapScanningParams::SCAN_WINDOW_MAX, uint16_t timeout = 0, @@ -669,11 +850,12 @@ class BLE * Once the scanning parameters have been configured, scanning can be * enabled by using startScan(). * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setScanInterval(). A former call to * ble.setScanInterval(interval) should be replaced with * ble.gap().setScanInterval(interval). */ + MBED_DEPRECATED("Use ble.gap().setScanInterval(...)") ble_error_t setScanInterval(uint16_t interval) { return gap().setScanInterval(interval); } @@ -693,11 +875,12 @@ class BLE * Once the scanning parameters have been configured, scanning can be * enabled by using startScan(). * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setScanWindow(). A former call to * ble.setScanWindow(window) should be replaced with * ble.gap().setScanWindow(window). */ + MBED_DEPRECATED("Use ble.gap().setScanWindow(...)") ble_error_t setScanWindow(uint16_t window) { return gap().setScanWindow(window); } @@ -719,11 +902,12 @@ class BLE * * @note The scan interval and window are recommendations to the BLE stack. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setScanTimeout(). A former call to * ble.setScanTimeout(...) should be replaced with * ble.gap().setScanTimeout(...). */ + MBED_DEPRECATED("Use ble.gap().setScanTimeout(...)") ble_error_t setScanTimeout(uint16_t timeout) { return gap().setScanTimeout(timeout); } @@ -742,6 +926,7 @@ class BLE * ble.setActiveScan(...) should be replaced with * ble.gap().setActiveScanning(...). */ + MBED_DEPRECATED("Use ble.gap().setActiveScan(...)") void setActiveScan(bool activeScanning) { gap().setActiveScanning(activeScanning); } @@ -760,6 +945,7 @@ class BLE * ble.startScan(callback) should be replaced with * ble.gap().startScan(callback). */ + MBED_DEPRECATED("Use ble.gap().startScan(callback)") ble_error_t startScan(void (*callback)(const Gap::AdvertisementCallbackParams_t *params)) { return gap().startScan(callback); } @@ -773,6 +959,7 @@ class BLE * ble.gap().startScan(object, callback). */ template + MBED_DEPRECATED("Use ble.gap().startScan(object, callback)") ble_error_t startScan(T *object, void (T::*memberCallback)(const Gap::AdvertisementCallbackParams_t *params)); /** @@ -780,11 +967,12 @@ class BLE * * @retval BLE_ERROR_NONE if successfully stopped scanning procedure. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::stopScan(). A former call to * ble.stopScan() should be replaced with * ble.gap().stopScan(). */ + MBED_DEPRECATED("Use ble.gap().stopScan()") ble_error_t stopScan(void) { return gap().stopScan(); } @@ -803,11 +991,12 @@ class BLE * successfully. The onConnection callback (if set) is invoked upon * a connection event. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::connect(). A former call to * ble.connect(...) should be replaced with * ble.gap().connect(...). */ + MBED_DEPRECATED("Use ble.gap().connect(...)") ble_error_t connect(const BLEProtocol::AddressBytes_t peerAddr, BLEProtocol::AddressType_t peerAddrType = BLEProtocol::AddressType::RANDOM_STATIC, const Gap::ConnectionParams_t *connectionParams = NULL, @@ -824,6 +1013,7 @@ class BLE * @param[in] reason * The reason for disconnection; sent back to the peer. */ + MBED_DEPRECATED("Use ble.gap().disconnect(...)") ble_error_t disconnect(Gap::Handle_t connectionHandle, Gap::DisconnectionReason_t reason) { return gap().disconnect(connectionHandle, reason); } @@ -836,7 +1026,7 @@ class BLE * @param reason * The reason for disconnection; sent back to the peer. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::disconnect(). A former call to * ble.disconnect(reason) should be replaced with * ble.gap().disconnect(reason). @@ -845,6 +1035,7 @@ class BLE * works reliably only for stacks that are limited to a single * connection. */ + MBED_DEPRECATED("Use ble.gap().disconnect(...)") ble_error_t disconnect(Gap::DisconnectionReason_t reason) { return gap().disconnect(reason); } @@ -853,11 +1044,12 @@ class BLE * Returns the current Gap state of the device using a bitmask that * describes whether the device is advertising or connected. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::getState(). A former call to * ble.getGapState() should be replaced with * ble.gap().getState(). */ + MBED_DEPRECATED("Use ble.gap().getGapState(...)") Gap::GapState_t getGapState(void) const { return gap().getState(); } @@ -868,17 +1060,18 @@ class BLE * choice of the connection parameters is eventually up to the central. * * @param[out] params - * The structure where the parameters will be stored. Memory - * for this is owned by the caller. + * The structure where the parameters will be stored. The caller owns memory + * for this. * * @return BLE_ERROR_NONE if the parameters were successfully filled into * the given structure pointed to by params. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::getPreferredConnectionParams(). A former call to * ble.getPreferredConnectionParams() should be replaced with * ble.gap().getPreferredConnectionParams(). */ + MBED_DEPRECATED("Use ble.gap().getPreferredConnectionParams(...)") ble_error_t getPreferredConnectionParams(Gap::ConnectionParams_t *params) { return gap().getPreferredConnectionParams(params); } @@ -891,11 +1084,12 @@ class BLE * @param[in] params * The structure containing the desired parameters. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setPreferredConnectionParams(). A former call to * ble.setPreferredConnectionParams() should be replaced with * ble.gap().setPreferredConnectionParams(). */ + MBED_DEPRECATED("Use ble.gap().setPreferredConnectionParams(...)") ble_error_t setPreferredConnectionParams(const Gap::ConnectionParams_t *params) { return gap().setPreferredConnectionParams(params); } @@ -910,11 +1104,12 @@ class BLE * Pointer to desired connection parameters. If NULL is provided on a peripheral role, * the parameters in the PPCP characteristic of the GAP service will be used instead. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::updateConnectionParams(). A former call to * ble.updateConnectionParams() should be replaced with * ble.gap().updateConnectionParams(). */ + MBED_DEPRECATED("Use ble.gap().updateConnectionParams(...)") ble_error_t updateConnectionParams(Gap::Handle_t handle, const Gap::ConnectionParams_t *params) { return gap().updateConnectionParams(handle, params); } @@ -924,11 +1119,12 @@ class BLE * @param[in] deviceName * The new value for the device-name. This is a UTF-8 encoded, NULL-terminated string. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setDeviceName(). A former call to * ble.setDeviceName() should be replaced with * ble.gap().setDeviceName(). */ + MBED_DEPRECATED("Use ble.gap().setDeviceName(...)") ble_error_t setDeviceName(const uint8_t *deviceName) { return gap().setDeviceName(deviceName); } @@ -938,7 +1134,7 @@ class BLE * @param[out] deviceName * Pointer to an empty buffer where the UTF-8 *non NULL- * terminated* string will be placed. Set this - * value to NULL in order to obtain the deviceName-length + * value to NULL to obtain the deviceName-length * from the 'length' parameter. * * @param[in,out] lengthP @@ -947,15 +1143,16 @@ class BLE * null terminator). * * @note If the device name is longer than the size of the supplied buffer, - * length will return the complete device name length, and not the + * the length will return the complete device name length and not the * number of bytes actually returned in deviceName. The application may * use this information to retry with a suitable buffer size. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::getDeviceName(). A former call to * ble.getDeviceName() should be replaced with * ble.gap().getDeviceName(). */ + MBED_DEPRECATED("Use ble.gap().getDeviceName(...)") ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP) { return gap().getDeviceName(deviceName, lengthP); } @@ -965,11 +1162,12 @@ class BLE * @param[in] appearance * The new value for the device-appearance. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setAppearance(). A former call to * ble.setAppearance() should be replaced with * ble.gap().setAppearance(). */ + MBED_DEPRECATED("Use ble.gap().setAppearance(...)") ble_error_t setAppearance(GapAdvertisingData::Appearance appearance) { return gap().setAppearance(appearance); } @@ -984,6 +1182,7 @@ class BLE * ble.getAppearance() should be replaced with * ble.gap().getAppearance(). */ + MBED_DEPRECATED("Use ble.gap().getAppearance(...)") ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP) { return gap().getAppearance(appearanceP); } @@ -992,11 +1191,12 @@ class BLE * Set the radio's transmit power. * @param[in] txPower Radio transmit power in dBm. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::setTxPower(). A former call to * ble.setTxPower() should be replaced with * ble.gap().setTxPower(). */ + MBED_DEPRECATED("Use ble.gap().setTxPower(...)") ble_error_t setTxPower(int8_t txPower) { return gap().setTxPower(txPower); } @@ -1014,6 +1214,7 @@ class BLE * ble.getPermittedTxPowerValues() should be replaced with * ble.gap().getPermittedTxPowerValues(). */ + MBED_DEPRECATED("Use ble.gap().getPermittedTxPowerValues(...)") void getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP) { gap().getPermittedTxPowerValues(valueArrayPP, countP); } @@ -1027,6 +1228,7 @@ class BLE * to ble.addService() should be replaced with * ble.gattServer().addService(). */ + MBED_DEPRECATED("Use ble.gattServer().addService(...)") ble_error_t addService(GattService &service) { return gattServer().addService(service); } @@ -1051,6 +1253,7 @@ class BLE * to ble.readCharacteristicValue() should be replaced with * ble.gattServer().read(). */ + MBED_DEPRECATED("Use ble.gattServer().read(...)") ble_error_t readCharacteristicValue(GattAttribute::Handle_t attributeHandle, uint8_t *buffer, uint16_t *lengthP) { return gattServer().read(attributeHandle, buffer, lengthP); } @@ -1081,6 +1284,7 @@ class BLE * A former call to ble.readCharacteristicValue() should be replaced with * ble.gattServer().read(). */ + MBED_DEPRECATED("Use ble.gattServer().read(...)") ble_error_t readCharacteristicValue(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t *buffer, uint16_t *lengthP) { return gattServer().read(connectionHandle, attributeHandle, buffer, lengthP); } @@ -1103,11 +1307,12 @@ class BLE * * @return BLE_ERROR_NONE if we have successfully set the value of the attribute. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::write(GattAttribute::Handle_t,const uint8_t,uint16_t,bool). * A former call to ble.updateCharacteristicValue() should be replaced with * ble.gattServer().write(). */ + MBED_DEPRECATED("Use ble.gattServer().write(...)") ble_error_t updateCharacteristicValue(GattAttribute::Handle_t attributeHandle, const uint8_t *value, uint16_t size, @@ -1137,11 +1342,12 @@ class BLE * * @return BLE_ERROR_NONE if we have successfully set the value of the attribute. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::write(Gap::Handle_t,GattAttribute::Handle_t,const uint8_t,uint16_t,bool). * A former call to ble.updateCharacteristicValue() should be replaced with * ble.gattServer().write(). */ + MBED_DEPRECATED("Use ble.gattServer().write(...)") ble_error_t updateCharacteristicValue(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, const uint8_t *value, @@ -1170,6 +1376,7 @@ class BLE * call to ble.initializeSecurity(...) should be replaced with * ble.securityManager().init(...). */ + MBED_DEPRECATED("Use ble.gattServer().write(...)") ble_error_t initializeSecurity(bool enableBonding = true, bool requireMITM = true, SecurityManager::SecurityIOCapabilities_t iocaps = SecurityManager::IO_CAPS_NONE, @@ -1190,6 +1397,7 @@ class BLE * call to ble.getLinkSecurity(...) should be replaced with * ble.securityManager().getLinkSecurity(...). */ + MBED_DEPRECATED("ble.securityManager().getLinkSecurity(...)") ble_error_t getLinkSecurity(Gap::Handle_t connectionHandle, SecurityManager::LinkSecurityStatus_t *securityStatusP) { return securityManager().getLinkSecurity(connectionHandle, securityStatusP); } @@ -1202,11 +1410,12 @@ class BLE * @retval BLE_ERROR_INVALID_STATE If the API is called without module initialization or * application registration. * - * @deprecated You should use the parallel API from SecurityManager directly, refer to + * @deprecated You should use the parallel API from SecurityManager directly and refer to * SecurityManager::purgeAllBondingState(). A former * call to ble.purgeAllBondingState() should be replaced with * ble.securityManager().purgeAllBondingState(). */ + MBED_DEPRECATED("ble.securityManager().purgeAllBondingState(...)") ble_error_t purgeAllBondingState(void) { return securityManager().purgeAllBondingState(); } @@ -1215,11 +1424,12 @@ class BLE * Set up a callback for timeout events. Refer to Gap::TimeoutSource_t for * possible event types. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::onTimeout(). A former call * to ble.onTimeout(callback) should be replaced with * ble.gap().onTimeout(callback). */ + MBED_DEPRECATED("ble.gap().onTimeout(callback)") void onTimeout(Gap::TimeoutEventCallback_t timeoutCallback) { gap().onTimeout(timeoutCallback); } @@ -1232,6 +1442,7 @@ class BLE * to ble.onConnection(callback) should be replaced with * ble.gap().onConnection(callback). */ + MBED_DEPRECATED("ble.gap().onConnection(callback)") void onConnection(Gap::ConnectionEventCallback_t connectionCallback) { gap().onConnection(connectionCallback); } @@ -1239,25 +1450,27 @@ class BLE /** * Append to a chain of callbacks to be invoked upon GAP disconnection. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::onDisconnection(). A former call * to ble.onDisconnection(callback) should be replaced with * ble.gap().onDisconnection(callback). */ + MBED_DEPRECATED("ble.gap().onDisconnection(callback)") void onDisconnection(Gap::DisconnectionEventCallback_t disconnectionCallback) { gap().onDisconnection(disconnectionCallback); } /** - * The same as onDisconnection(), but allows an object reference and member function + * The same as onDisconnection() but allows an object reference and member function * to be added to the chain of callbacks. * - * @deprecated You should use the parallel API from Gap directly, refer to + * @deprecated You should use the parallel API from Gap directly and refer to * Gap::onDisconnection(). A former call * to ble.onDisconnection(callback) should be replaced with * ble.gap().onDisconnection(callback). */ template + MBED_DEPRECATED("ble.gap().onDisconnection(callback)") void onDisconnection(T *tptr, void (T::*mptr)(const Gap::DisconnectionCallbackParams_t*)) { gap().onDisconnection(tptr, mptr); } @@ -1283,6 +1496,7 @@ class BLE * to ble.onRadioNotification(...) should be replaced with * ble.gap().onRadioNotification(...). */ + MBED_DEPRECATED("ble.gap().onRadioNotification(...)") void onRadioNotification(void (*callback)(bool)) { gap().onRadioNotification(callback); } @@ -1298,25 +1512,28 @@ class BLE * @note It is also possible to set up a callback into a member function of * some object. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onDataSent(). A former call * to ble.onDataSent(...) should be replaced with * ble.gattServer().onDataSent(...). */ + MBED_DEPRECATED("ble.gattServer().onDataSent(...)") void onDataSent(void (*callback)(unsigned count)) { gattServer().onDataSent(callback); } /** - * The same as onDataSent(), but allows an object reference and member function + * The same as onDataSent() but allows an object reference and member function * to be added to the chain of callbacks. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onDataSent(). A former call * to ble.onDataSent(...) should be replaced with * ble.gattServer().onDataSent(...). */ - template void onDataSent(T * objPtr, void (T::*memberPtr)(unsigned count)) { + template + MBED_DEPRECATED("ble.gattServer().onDataSent(...)") + void onDataSent(T * objPtr, void (T::*memberPtr)(unsigned count)) { gattServer().onDataSent(objPtr, memberPtr); } @@ -1335,17 +1552,18 @@ class BLE * @note It is also possible to set up a callback into a member function of * some object. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onDataWritten(). A former call * to ble.onDataWritten(...) should be replaced with * ble.gattServer().onDataWritten(...). */ + MBED_DEPRECATED("ble.gattServer().onDataWritten(...)") void onDataWritten(void (*callback)(const GattWriteCallbackParams *eventDataP)) { gattServer().onDataWritten(callback); } /** - * The same as onDataWritten(), but allows an object reference and member function + * The same as onDataWritten() but allows an object reference and member function * to be added to the chain of callbacks. * * @deprecated You should use the parallel API from GattServer directly, refer to @@ -1353,7 +1571,9 @@ class BLE * to ble.onDataWritten(...) should be replaced with * ble.gattServer().onDataWritten(...). */ - template void onDataWritten(T * objPtr, void (T::*memberPtr)(const GattWriteCallbackParams *context)) { + template + MBED_DEPRECATED("ble.gattServer().onDataWritten(...)") + void onDataWritten(T * objPtr, void (T::*memberPtr)(const GattWriteCallbackParams *context)) { gattServer().onDataWritten(objPtr, memberPtr); } @@ -1376,25 +1596,28 @@ class BLE * @return BLE_ERROR_NOT_IMPLEMENTED if this functionality isn't available; * else BLE_ERROR_NONE. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onDataRead(). A former call * to ble.onDataRead(...) should be replaced with * ble.gattServer().onDataRead(...). */ + MBED_DEPRECATED("ble.gattServer().onDataRead(...)") ble_error_t onDataRead(void (*callback)(const GattReadCallbackParams *eventDataP)) { return gattServer().onDataRead(callback); } /** - * The same as onDataRead(), but allows an object reference and member function + * The same as onDataRead() but allows an object reference and member function * to be added to the chain of callbacks. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onDataRead(). A former call * to ble.onDataRead(...) should be replaced with * ble.gattServer().onDataRead(...). */ - template ble_error_t onDataRead(T * objPtr, void (T::*memberPtr)(const GattReadCallbackParams *context)) { + template + MBED_DEPRECATED("ble.gattServer().onDataRead(...)") + ble_error_t onDataRead(T * objPtr, void (T::*memberPtr)(const GattReadCallbackParams *context)) { return gattServer().onDataRead(objPtr, memberPtr); } @@ -1402,11 +1625,12 @@ class BLE * Set up a callback for when notifications or indications are enabled for a * characteristic on the local GattServer. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onUpdatesEnabled(). A former call * to ble.onUpdatesEnabled(callback) should be replaced with * ble.gattServer().onUpdatesEnabled(callback). */ + MBED_DEPRECATED("ble.gattServer().onUpdatesEnabled(...)") void onUpdatesEnabled(GattServer::EventCallback_t callback) { gattServer().onUpdatesEnabled(callback); } @@ -1415,11 +1639,12 @@ class BLE * Set up a callback for when notifications or indications are disabled for a * characteristic on the local GattServer. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onUpdatesDisabled(). A former call - * to ble.onUpdatesEnabled(callback) should be replaced with - * ble.gattServer().onUpdatesEnabled(callback). + * to ble.onUpdatesDisabled(callback) should be replaced with + * ble.gattServer().onUpdatesDisabled(callback). */ + MBED_DEPRECATED("ble.gattServer().onUpdatesDisabled(...)") void onUpdatesDisabled(GattServer::EventCallback_t callback) { gattServer().onUpdatesDisabled(callback); } @@ -1428,11 +1653,12 @@ class BLE * Set up a callback for when the GATT server receives a response for an * indication event sent previously. * - * @deprecated You should use the parallel API from GattServer directly, refer to + * @deprecated You should use the parallel API from GattServer directly and refer to * GattServer::onConfirmationReceived(). A former call * to ble.onConfirmationReceived(callback) should be replaced with * ble.gattServer().onConfirmationReceived(callback). */ + MBED_DEPRECATED("ble.gattServer().onConfirmationReceived(...)") void onConfirmationReceived(GattServer::EventCallback_t callback) { gattServer().onConfirmationReceived(callback); } @@ -1441,14 +1667,15 @@ class BLE * Set up a callback for when the security setup procedure (key generation * and exchange) for a link has started. This will be skipped for bonded * devices. The callback is passed in parameters received from the peer's - * security request: bool allowBonding, bool requireMITM, and + * security request: bool allowBonding, bool requireMITM and * SecurityIOCapabilities_t. * - * @deprecated You should use the parallel API from SecurityManager directly, refer to + * @deprecated You should use the parallel API from SecurityManager directly and refer to * SecurityManager::onSecuritySetupInitiated(). A former * call to ble.onSecuritySetupInitiated(callback) should be replaced with * ble.securityManager().onSecuritySetupInitiated(callback). */ + MBED_DEPRECATED("ble.securityManager().onSecuritySetupInitiated(callback)") void onSecuritySetupInitiated(SecurityManager::SecuritySetupInitiatedCallback_t callback) { securityManager().onSecuritySetupInitiated(callback); } @@ -1459,11 +1686,12 @@ class BLE * devices. The callback is passed in the success/failure status of the * security setup procedure. * - * @deprecated You should use the parallel API from SecurityManager directly, refer to + * @deprecated You should use the parallel API from SecurityManager directly and refer to * SecurityManager::onSecuritySetupCompleted(). A former * call to ble.onSecuritySetupCompleted(callback) should be replaced with * ble.securityManager().onSecuritySetupCompleted(callback). */ + MBED_DEPRECATED("ble.securityManager().onSecuritySetupCompleted(callback)") void onSecuritySetupCompleted(SecurityManager::SecuritySetupCompletedCallback_t callback) { securityManager().onSecuritySetupCompleted(callback); } @@ -1476,11 +1704,12 @@ class BLE * or both sides. The callback is passed in a SecurityManager::SecurityMode_t according * to the level of security in effect for the secured link. * - * @deprecated You should use the parallel API from SecurityManager directly, refer to + * @deprecated You should use the parallel API from SecurityManager directly and refer to * SecurityManager::onLinkSecured(). A former * call to ble.onLinkSecured(callback) should be replaced with * ble.securityManager().onLinkSecured(callback). */ + MBED_DEPRECATED("ble.securityManager().onLinkSecured(callback)") void onLinkSecured(SecurityManager::LinkSecuredCallback_t callback) { securityManager().onLinkSecured(callback); } @@ -1489,11 +1718,12 @@ class BLE * Set up a callback for successful bonding, meaning that link-specific security * context is stored persistently for a peer device. * - * @deprecated You should use the parallel API from SecurityManager directly, refer to + * @deprecated You should use the parallel API from SecurityManager directly and refer to * SecurityManager::onSecurityContextStored(). A former * call to ble.onSecurityContextStored(callback) should be replaced with * ble.securityManager().onSecurityContextStored(callback). */ + MBED_DEPRECATED("ble.securityManager().onSecurityContextStored(callback)") void onSecurityContextStored(SecurityManager::HandleSpecificEvent_t callback) { securityManager().onSecurityContextStored(callback); } @@ -1501,46 +1731,29 @@ class BLE /** * Set up a callback for when the passkey needs to be displayed on a * peripheral with DISPLAY capability. This happens when security is - * configured to prevent Man-In-The-Middle attacks, and the peers need to exchange + * configured to prevent man-in-the-middle attacks, and the peers need to exchange * a passkey (or PIN) to authenticate the connection * attempt. * - * @deprecated You should use the parallel API from SecurityManager directly, refer to + * @deprecated You should use the parallel API from SecurityManager directly and refer to * SecurityManager::onPasskeyDisplay(). A former * call to ble.onPasskeyDisplay(callback) should be replaced with * ble.securityManager().onPasskeyDisplay(callback). */ + MBED_DEPRECATED("ble.securityManager().onPasskeyDisplay(callback)") void onPasskeyDisplay(SecurityManager::PasskeyDisplayCallback_t callback) { return securityManager().onPasskeyDisplay(callback); } - /** - * Process ALL pending events living in the BLE stack . - * Return once all events have been consumed. - * This function is called by user in their while loop (mbed Classic) - * or automatically by Minar (mbed OS) when BLE event processing is scheduled. - * Internally, this function will call BLEInstanceBase::processEvent. - */ - void processEvents(); - - /** - * Register a hook which will be called every time the BLE stack has pending - * work. - * By registering a callback, user code can know when event processing has to be - * scheduled. - * Callback format is void (*)(BLE& ble); - */ - void onEventsToProcess(const OnEventsToProcessCallback_t& callback); - private: - friend class BLEInstanceBase; /** - * This function allow the BLE stack to signal that their is work to do and + * This function allows the BLE stack to signal that there is work to do and * event processing should be done (BLE::processEvent()). - * This function should be called by the port of BLE_API, it shouldn't be - * accessible to end users. + * + * @note This function should be called by the port of BLE_API. It is not + * meant to be used by end users. */ void signalEventsToProcess(); @@ -1550,20 +1763,34 @@ class BLE * The implementation is separated into a private method because it isn't * suitable to be included in the header. */ - ble_error_t initImplementation(FunctionPointerWithContext callback); + ble_error_t initImplementation( + FunctionPointerWithContext callback + ); private: + // Prevent copy construction and copy assignment of BLE. BLE(const BLE&); BLE &operator=(const BLE &); private: - InstanceID_t instanceID; + InstanceID_t instanceID; BLEInstanceBase *transport; /* The device-specific backend */ OnEventsToProcessCallback_t whenEventsToProcess; + bool event_signaled; }; -typedef BLE BLEDevice; /**< @deprecated This type alias is retained for the - * sake of compatibility with older - * code. Will be dropped at some point soon.*/ +/** + * @deprecated This type alias is retained for the sake of compatibility with + * older code. This will be dropped at some point. + */ +typedef BLE BLEDevice; + +/** + * @namespace ble Entry namespace for all %BLE API definitions. + */ + +/** + * @} + */ -#endif /* ifndef __BLE_H__ */ +#endif /* ifndef MBED_BLE_H__ */ diff --git a/features/FEATURE_BLE/ble/BLEInstanceBase.h b/features/FEATURE_BLE/ble/BLEInstanceBase.h index bb4cc69dd81..18eb0264845 100644 --- a/features/FEATURE_BLE/ble/BLEInstanceBase.h +++ b/features/FEATURE_BLE/ble/BLEInstanceBase.h @@ -14,8 +14,12 @@ * limitations under the License. */ -#ifndef __BLE_DEVICE_INSTANCE_BASE__ -#define __BLE_DEVICE_INSTANCE_BASE__ +/** + * @file + */ + +#ifndef MBED_BLE_DEVICE_INSTANCE_BASE__ +#define MBED_BLE_DEVICE_INSTANCE_BASE__ #include "Gap.h" #include "ble/SecurityManager.h" @@ -26,16 +30,33 @@ class GattServer; class GattClient; /** - * The interface for the transport object to be created by the target library's - * createBLEInstance(). + * @addtogroup ble + * @{ + * @addtogroup porting + * @{ + */ + +/** + * Private interface used to implement the BLE class. + * + * The BLE class delegates all its abstract operations to an instance of this + * abstract class, which every vendor port of Mbed BLE shall implement. * - * @note This class is part of the interface of BLE API with the implementation; - * therefore, it is meant to be used only by porters rather than normal - * BLE API users. + * The vendor port shall also define an implementation of the freestanding function + * createBLEInstance(). The BLE API uses this singleton function to gain + * access to a concrete implementation of this class defined in the vendor port. + * + * @important This class is part of the porting API and is not meant to be used + * by end users of BLE API. + * + * @see BLE */ class BLEInstanceBase { public: + /** + * Base constructor. + */ BLEInstanceBase() {} /** @@ -44,133 +65,206 @@ class BLEInstanceBase virtual ~BLEInstanceBase(); /** - * Initialize the underlying BLE stack. This should be called before - * anything else in the BLE API. + * Process ALL pending events living in the vendor BLE subsystem. * - * @param[in] instanceID - * The ID of the instance to initialize. - * @param[in] initCallback - * A callback for when initialization completes for a BLE - * instance. This is an optional parameter set to NULL when not - * supplied. + * Return once all pending events have been consumed. * - * @return BLE_ERROR_NONE if the initialization procedure was started - * successfully. + * @see BLE::processEvents() */ - virtual ble_error_t init(BLE::InstanceID_t instanceID, - FunctionPointerWithContext initCallback) = 0; + virtual void processEvents() = 0; /** - * Check whether the underlying stack has already been initialized, - * possible with a call to init(). + * Signal to BLE that events needing processing are available. + * + * The vendor port shall call this function whenever there are events + * ready to be processed in the internal stack or BLE subsystem. As a result + * of this call, the callback registered by the end user via + * BLE::onEventsToProcess will be invoked. * - * @return true if the initialization has completed for the underlying BLE - * stack. + * @param[in] id: Identifier of the BLE instance, which does have events to + * ready to be processed. */ - virtual bool hasInitialized(void) const = 0; + void signalEventsToProcess(BLE::InstanceID_t id); /** - * Shutdown the underlying BLE stack. This includes purging the stack of - * GATT and GAP state and clearing all state from other BLE components - * such as the SecurityManager. init() must be called afterwards to - * re-instantiate services and GAP state. + * Start the initialization of the vendor BLE subsystem. * - * @return BLE_ERROR_NONE if the underlying stack and all other services of - * the BLE API were shutdown correctly. + * Calls to this function are initiated by BLE::init, instanceID identify + * the BLE instance which issue that call while the initCallback is used to + * signal asynchronously the completion of the initialization process. + * + * @param[in] instanceID Identifier of the BLE instance requesting + * initialization. + * @param[in] initCallback Callback which the vendor port shall invoke + * when the initialization completes. + * + * This is an optional parameter set to NULL when not supplied. + * + * @return BLE_ERROR_NONE if the initialization procedure started + * successfully. + * + * @post initCallback shall be invoked upon completion of the initialization + * process. + * + * @post hasInitialized() shall return false until the initialization is + * complete, and it shall return true after succesful completion of the + * initialization process. + * + * @see BLE::init() */ - virtual ble_error_t shutdown(void) = 0; + virtual ble_error_t init( + BLE::InstanceID_t instanceID, + FunctionPointerWithContext initCallback + ) = 0; /** - * Fetches a string representation of the underlying BLE stack's version. + * Check whether the vendor BLE subsystem has been initialized or not. + * + * @return true if the initialization has completed for the vendor BLE + * subsystem. + * + * @note this function is invoked by BLE::hasInitialized() * - * @return A pointer to the string representation of the underlying - * BLE stack's version. + * @see BLE::init() BLE::hasInitialized() */ - virtual const char * getVersion(void) = 0; + virtual bool hasInitialized(void) const = 0; /** - * Accessor to Gap. This function is used by BLE::gap(). + * Shutdown the vendor BLE subsystem. * - * @return A reference to a Gap object associated to this BLE instance. + * This operation includes purging the stack of GATT and GAP state and + * clearing all state from other BLE components, such as the SecurityManager. + * Clearing all states may be realized by a call to Gap::reset(), + * GattClient::reset(), GattServer::reset() and SecurityManager::reset(). + * + * BLE::init() must be called afterward to reinstantiate services and GAP + * state. + * + * @return BLE_ERROR_NONE if the underlying stack and all other services of + * the BLE API were shut down correctly. + * + * @post hasInitialized() shall return false. + * + * @note This function is invoked by BLE::shutdown(). + * + * @see BLE::shutdown() BLE::init() BLE::hasInitialized() Gap::reset() + * GattClient::reset() GattServer::reset() SecurityManager::reset() . */ - virtual Gap& getGap() = 0; + virtual ble_error_t shutdown(void) = 0; /** - * A const alternative to getGap(). + * Fetches a NULL terminated string representation of the underlying BLE + * vendor subsystem. + * + * @return A pointer to the NULL terminated string representation of the + * underlying BLE stack's version. * - * @return A const reference to a Gap object associated to this BLE instance. + * @see BLE::getVersion() */ - virtual const Gap& getGap() const = 0; + virtual const char *getVersion(void) = 0; /** - * Accessor to GattServer. This function is used by BLE::gattServer(). + * Accessor to the vendor implementation of the Gap interface. * - * @return A reference to a GattServer object associated to this BLE instance. + * @return A reference to a Gap object associated to this BLEInstanceBase + * instance. + * + * @see BLE::gap() Gap */ - virtual GattServer& getGattServer() = 0; + virtual Gap &getGap(void) = 0; /** - * A const alternative to getGattServer(). + * Const alternative to getGap(). + * + * @return A const reference to a Gap object associated to this + * BLEInstanceBase instance. * - * @return A const reference to a GattServer object associated to this BLE instance. + * @see BLE::gap() Gap */ - virtual const GattServer& getGattServer() const = 0; + virtual const Gap &getGap(void) const = 0; /** - * Accessors to GattClient. This function is used by BLE::gattClient(). + * Accessor to the vendor implementation of the GattServer interface. * - * @return A reference to a GattClient object associated to this BLE instance. + * @return A reference to a GattServer object associated to this + * BLEInstanceBase instance. + * + * @see BLE::gattServer() GattServer */ - virtual GattClient& getGattClient() = 0; + virtual GattServer &getGattServer(void) = 0; /** - * Accessors to SecurityManager. This function is used by BLE::securityManager(). + * A const alternative to getGattServer(). + * + * @return A const reference to a GattServer object associated to this + * BLEInstanceBase instance. * - * @return A reference to a SecurityManager object associated to this BLE instance. + * @see BLE::gattServer() GattServer */ - virtual SecurityManager& getSecurityManager() = 0; + virtual const GattServer &getGattServer(void) const = 0; /** - * A const alternative to getSecurityManager(). + * Accessor to the vendor implementation of the GattClient interface. + * + * @return A reference to a GattClient object associated to this + * BLEInstanceBase instance. * - * @return A const reference to a SecurityManager object associated to this BLE instance. + * @see BLE::gattClient() GattClient */ - virtual const SecurityManager& getSecurityManager() const = 0; + virtual GattClient &getGattClient(void) = 0; /** - * Yield control to the BLE stack or to other tasks waiting for events. - * refer to BLE::waitForEvent(). + * Accessor to the vendor implementation of the SecurityManager interface. + * + * @return A reference to a SecurityManager object associated to this + * BLEInstanceBase instance. + * + * @see BLE::securityManager() SecurityManager */ - virtual void waitForEvent(void) = 0; + virtual SecurityManager &getSecurityManager(void) = 0; /** - * Process ALL pending events living in the BLE stack . - * Return once all events have been consumed. + * A const alternative to getSecurityManager(). + * + * @return A const reference to a SecurityManager object associated to this + * BLEInstancebase instance. + * + * @see BLE::securityManager() SecurityManager */ - virtual void processEvents() = 0; + virtual const SecurityManager &getSecurityManager(void) const = 0; /** - * This function allow the BLE stack to signal that their is work to do and - * event processing should be done (BLE::processEvent()). - * @param id: The ID of the BLE instance which does have events to process. + * Process pending events present in the vendor subsystem; then, put the MCU + * to sleep until an external source wakes it up. + * + * @important This function is deprecated in the BLE class. It will be + * removed from this interface once it is removed from BLE. + * + * @see BLE::waitForEvent() BLE::processEvents() */ - void signalEventsToProcess(BLE::InstanceID_t id); + virtual void waitForEvent(void) = 0; private: // this class is not a value type. // prohibit copy construction and copy assignement BLEInstanceBase(const BLEInstanceBase&); - BLEInstanceBase& operator=(const BLEInstanceBase&); + BLEInstanceBase &operator=(const BLEInstanceBase&); }; /** - * BLE uses composition to hide an interface object encapsulating the - * backend transport. + * Return the instance of the vendor implementation of BLEInstanceBase. + * + * @important Contrary to its name, this function does not return a new instance + * at each call. It rather acts like an accessor to a singleton. * - * The following API is used to create the singleton interface object. An - * implementation for this function must be provided by the device-specific - * library, otherwise there will be a linker error. + * @important The vendor library must provide an implementation for this function + * library. Otherwise, there will be a linker error. */ extern BLEInstanceBase *createBLEInstance(void); -#endif // ifndef __BLE_DEVICE_INSTANCE_BASE__ +/** + * @} + * @} + */ + +#endif // ifndef MBED_BLE_DEVICE_INSTANCE_BASE__ diff --git a/features/FEATURE_BLE/ble/BLEProtocol.h b/features/FEATURE_BLE/ble/BLEProtocol.h index bcfb08765a5..4fdcb59bc5c 100644 --- a/features/FEATURE_BLE/ble/BLEProtocol.h +++ b/features/FEATURE_BLE/ble/BLEProtocol.h @@ -14,67 +14,130 @@ * limitations under the License. */ -#ifndef __BLE_PROTOCOL_H__ -#define __BLE_PROTOCOL_H__ +#ifndef MBED_BLE_PROTOCOL_H__ +#define MBED_BLE_PROTOCOL_H__ #include #include #include /** - * A common namespace for types and constants used everywhere in BLE API. + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ + +/** + * Common namespace for types and constants used everywhere in BLE API. */ namespace BLEProtocol { + /** - * A simple container for the enumeration of address-types for Protocol addresses. + * Container for the enumeration of BLE address types. * - * Adding a struct to encapsulate the contained enumeration prevents + * @note Adding a struct to encapsulate the contained enumeration prevents * polluting the BLEProtocol namespace with the enumerated values. It also * allows type-aliases for the enumeration while retaining the enumerated * values. i.e. doing: + * + * @code * typedef AddressType AliasedType; + * @endcode * * would allow the use of AliasedType::PUBLIC in code. + * + * @note see Bluetooth Standard version 4.2 [Vol 6, Part B] section 1.3 . */ struct AddressType { - /** Address-types for Protocol addresses. */ + /** + * Address-types for Protocol addresses. + */ enum Type { + /** + * Public device address. + */ PUBLIC = 0, + + /** + * Random static device address. + */ RANDOM_STATIC, + + /** + * Private resolvable device address. + */ RANDOM_PRIVATE_RESOLVABLE, + + /** + * Private non-resolvable device address. + */ RANDOM_PRIVATE_NON_RESOLVABLE }; }; - typedef AddressType::Type AddressType_t; /**< Alias for AddressType::Type */ - static const size_t ADDR_LEN = 6; /**< Length (in octets) of the BLE MAC address. */ - typedef uint8_t AddressBytes_t[ADDR_LEN]; /**< 48-bit address, in LSB format. */ + /** + * Alias for AddressType::Type + */ + typedef AddressType::Type AddressType_t; + + /** + * Length (in octets) of the BLE MAC address. + */ + static const size_t ADDR_LEN = 6; /** - * BLE address. It contains an address-type (AddressType_t) and bytes (AddressBytes_t). + * 48-bit address, in LSB format. */ - struct Address_t { - AddressType_t type; /**< The type of the BLE address. */ - AddressBytes_t address; /**< The BLE address. */ + typedef uint8_t AddressBytes_t[ADDR_LEN]; + /** + * BLE address representation. + * + * It contains an address-type (::AddressType_t) and the address value + * (::AddressBytes_t). + */ + struct Address_t { /** * Construct an Address_t object with the supplied type and address. * - * @param[in] typeIn - * The BLE address type. - * @param[in] addressIn - * The BLE address. + * @param[in] typeIn The BLE address type. + * @param[in] addressIn The BLE address. + * + * @post type is equal to typeIn and address is equal to the content + * present in addressIn. */ - Address_t(AddressType_t typeIn, const AddressBytes_t& addressIn) : type(typeIn) { + Address_t(AddressType_t typeIn, const AddressBytes_t &addressIn) : + type(typeIn) { std::copy(addressIn, addressIn + ADDR_LEN, address); } /** * Empty constructor. + * + * @note The address constructed with the empty constructor is not + * valid. + * + * @post type is equal to PUBLIC and the address value is equal to + * 00:00:00:00:00:00 */ - Address_t() : type(), address() { - } + Address_t(void) : type(), address() { } + + /** + * Type of the BLE device address. + */ + AddressType_t type; + + /** + * Value of the device address. + */ + AddressBytes_t address; }; }; -#endif /* __BLE_PROTOCOL_H__ */ +/** + * @} + * @} + */ + +#endif /* MBED_BLE_PROTOCOL_H__ */ diff --git a/features/FEATURE_BLE/ble/BLETypes.h b/features/FEATURE_BLE/ble/BLETypes.h index f20f03c432a..cf71d040df7 100644 --- a/features/FEATURE_BLE/ble/BLETypes.h +++ b/features/FEATURE_BLE/ble/BLETypes.h @@ -20,36 +20,73 @@ #include #include +/** + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ + namespace ble { /** - * A connection handle is an unsigned integer capable of holding a pointer. - * The real type (either a pointer to an object or an integer) is opaque and - * platform dependent. + * Opaque reference to a connection. + * + * Internally a connection handle is an unsigned integer capable of holding a + * pointer. + * + * The real type (either a pointer to an object or an integer) is opaque for + * users and platform dependent. */ typedef uintptr_t connection_handle_t; /** - * Model an attribute handle in a GATT database. + * Reference to an attribute in a GATT database. */ typedef uint16_t attribute_handle_t; /** - * Model an inclusive range of GATT attributes handles. + * Inclusive range of GATT attributes handles. + * + * @note Instances can be constructed with the help of the factory function + * attribute_handle_range(). */ struct attribute_handle_range_t { + /** + * Begining of the range. + */ attribute_handle_t begin; + + /** + * End of the range. + */ attribute_handle_t end; + /** + * Equal operator for attribute_handle_range_t. + * + * @param[in] lhs Left hand side of the expression. + * @param[in] rhs Right hand side of the expression. + * + * @return true if lhs is equal to rhs and false otherwise. + */ friend bool operator==( - const attribute_handle_range_t& lhs, const attribute_handle_range_t& rhs + const attribute_handle_range_t &lhs, const attribute_handle_range_t &rhs ) { return (lhs.begin == rhs.begin) && (lhs.end == rhs.end); } + /** + * Not equal operator for attribute_handle_range_t. + * + * @param[in] lhs Left hand side of the expression. + * @param[in] rhs Right hand side of the expression. + * + * @return true if lhs is not equal to rhs and false otherwise. + */ friend bool operator!=( - const attribute_handle_range_t& lhs, const attribute_handle_range_t& rhs + const attribute_handle_range_t &lhs, const attribute_handle_range_t &rhs ) { return !(lhs == rhs); } @@ -57,7 +94,15 @@ struct attribute_handle_range_t { /** - * Construct an attribute_handle_range_t from its start and end handle. + * Construct an attribute_handle_range_t from its first and last attribute handle. + * + * @param begin Handle at the begining of the range. + * @param end Handle at the end of the range. + * + * @return An instance of attribute_handle_range_t where + * attribute_handle_range_t::begin is equal to begin and + * attribute_handle_range_t::end is equal to end. + * * @note This function is defined instead of a constructor to keep "POD-ness" * of attribute_handle_range_t. */ @@ -74,4 +119,9 @@ static inline attribute_handle_range_t attribute_handle_range( } // namespace ble +/** + * @} + * @} + */ + #endif /* BLE_TYPES_H_ */ diff --git a/features/FEATURE_BLE/ble/CallChainOfFunctionPointersWithContext.h b/features/FEATURE_BLE/ble/CallChainOfFunctionPointersWithContext.h index dd1434c7057..96887ddb1a5 100644 --- a/features/FEATURE_BLE/ble/CallChainOfFunctionPointersWithContext.h +++ b/features/FEATURE_BLE/ble/CallChainOfFunctionPointersWithContext.h @@ -20,10 +20,22 @@ #include "FunctionPointerWithContext.h" #include "SafeBool.h" +/** + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ -/** Group one or more functions in an instance of a CallChainOfFunctionPointersWithContext, then call them in - * sequence using CallChainOfFunctionPointersWithContext::call(). Used mostly by the interrupt chaining code, - * but can be used for other purposes. +/** + * Function like object hosting a list of FunctionPointerWithContext. + * + * Upon call, each FunctionPointerWithContext instance present in the object will + * be called in sequence with the initial parameters. + * + * It can be seen as a variation of the observer pattern this object being the + * observable, instances of the FunctionPointerWithContext being the observable + * and the notify/update operation being the function call. * * Example: * @code @@ -51,81 +63,96 @@ * chain.add(second); * chain.add_front(first); * chain.add(&test, &Test::f); + * + * // will print: + * // 'second' function. + * // 'first' function. + * // A::f (class member). * chain.call(); * } * @endcode + * + * @note memory allocation is used to add new function like objects into the + * call chain. + * + * @tparam ContextType Type of the parameter accepted by the callbacks hosted + * in the object. */ template -class CallChainOfFunctionPointersWithContext : public SafeBool > { +class CallChainOfFunctionPointersWithContext : + public SafeBool > { public: /** - * The type of each callback in the callchain. + * Alias of the FunctionPointerWithContext type this object can store. */ typedef FunctionPointerWithContext *pFunctionPointerWithContext_t; public: /** - * Create an empty chain. + * Create an empty callchain. */ - CallChainOfFunctionPointersWithContext() : chainHead(NULL) { - /* empty */ - } + CallChainOfFunctionPointersWithContext() : chainHead(NULL) { } - virtual ~CallChainOfFunctionPointersWithContext() { + /** + * Destruction of the callchain. + */ + virtual ~CallChainOfFunctionPointersWithContext() + { clear(); } /** - * Add a function at the front of the chain. + * Add a function pointer at the front of the chain. * - * @param[in] function - * A pointer to a void function. + * @param[in] function A pointer to a void function. * - * @return The function object created for @p function. + * @return The FunctionPointerWithContext object created from @p function. */ - pFunctionPointerWithContext_t add(void (*function)(ContextType context)) { + pFunctionPointerWithContext_t add(void (*function)(ContextType context)) + { return common_add(new FunctionPointerWithContext(function)); } /** - * Add a function at the front of the chain. + * Add a member function bound to its instance at the front of the chain. * - * @param[in] tptr - * Pointer to the object to call the member function on. - * @param[in] mptr - * Pointer to the member function to be called. + * @param[in] tptr Pointer to the object to call the member function on. + * @param[in] mptr Pointer to the member function to be called. * - * @return The function object created for @p tptr and @p mptr. + * @return The FunctionPointerWithContext object created from @p tptr and + * @p mptr. */ template - pFunctionPointerWithContext_t add(T *tptr, void (T::*mptr)(ContextType context)) { + pFunctionPointerWithContext_t add(T *tptr, void (T::*mptr)(ContextType context)) + { return common_add(new FunctionPointerWithContext(tptr, mptr)); } /** - * Add a function at the front of the chain. + * Add a FunctionPointerWithContext at the front of the chain. * - * @param[in] func - * The FunctionPointerWithContext to add. + * @param[in] func The FunctionPointerWithContext to add. * * @return The function object created for @p func. */ - pFunctionPointerWithContext_t add(const FunctionPointerWithContext& func) { + pFunctionPointerWithContext_t add(const FunctionPointerWithContext &func) + { return common_add(new FunctionPointerWithContext(func)); } /** * Detach a function pointer from a callchain. * - * @param[in] toDetach - * FunctionPointerWithContext to detach from this callchain. + * @param[in] toDetach FunctionPointerWithContext instance to detach from + * this callchain. * * @return true if a function pointer has been detached and false otherwise. * - * @note It is safe to remove a function pointer while the chain is - * traversed by call(ContextType). + * @note It is safe to remove a function pointer while + * call(ContextType) is traversing the chain. */ - bool detach(const FunctionPointerWithContext& toDetach) { + bool detach(const FunctionPointerWithContext &toDetach) + { pFunctionPointerWithContext_t current = chainHead; pFunctionPointerWithContext_t previous = NULL; @@ -154,9 +181,10 @@ class CallChainOfFunctionPointersWithContext : public SafeBoolcall(context); } /** - * Same as call() above, but const. + * Call sequentially each member of the chain. + * + * @param[in] context Parameter to pass to the functions called. */ - void call(ContextType context) const { + void call(ContextType context) const + { currentCalled = chainHead; while(currentCalled) { @@ -201,7 +236,10 @@ class CallChainOfFunctionPointersWithContext : public SafeBool chain; + * + * if (!chain) { + * // Do something if the chain is empty. + * } + * + * if (chain) { + * // Do something if the chain is not empty. + * } + * @endcode + * */ - bool toBool() const { + bool toBool() const + { return chainHead != NULL; } @@ -236,7 +291,8 @@ class CallChainOfFunctionPointersWithContext : public SafeBool DiscoveryCallback_t; + typedef FunctionPointerWithContext + DiscoveryCallback_t; /** - * @brief Callback type for when characteristic descriptor discovery terminates. + * Handler of Characteristic descriptor discovery ended event. + * + * As a parameter, it expects a pointer to a TerminationCallbackParams_t instance. + * + * @note The object passed in parameter will remain valid for the lifetime + * of the callback. The BLE_API eventing framework owns the memory for this + * object. The application can safely make a persistent shallow-copy of + * this object to work with the service beyond the callback. * - * @param param A pointer to a TerminationCallbackParams_t object which will remain - * valid for the lifetime of the callback. Memory for this object is owned by - * the BLE_API eventing framework. The application can safely make a persistent - * shallow-copy of this object in order to work with the service beyond the - * callback. + * @see TerminationCallbackParams_t + * GattClient::discoverCharacteristicDescriptors + * DiscoveredCharacteristic::discoverDescriptors */ - typedef FunctionPointerWithContext TerminationCallback_t; + typedef FunctionPointerWithContext + TerminationCallback_t; }; -#endif // ifndef __CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__ +/** + * @} + * @} + */ + +#endif // ifndef MBED_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__ diff --git a/features/FEATURE_BLE/ble/DiscoveredCharacteristic.h b/features/FEATURE_BLE/ble/DiscoveredCharacteristic.h index 4fcd719dc95..effc887851f 100644 --- a/features/FEATURE_BLE/ble/DiscoveredCharacteristic.h +++ b/features/FEATURE_BLE/ble/DiscoveredCharacteristic.h @@ -14,8 +14,8 @@ * limitations under the License. */ -#ifndef __DISCOVERED_CHARACTERISTIC_H__ -#define __DISCOVERED_CHARACTERISTIC_H__ +#ifndef MBED_DISCOVERED_CHARACTERISTIC_H__ +#define MBED_DISCOVERED_CHARACTERISTIC_H__ #include "UUID.h" #include "Gap.h" @@ -25,116 +25,230 @@ #include "DiscoveredCharacteristicDescriptor.h" /** - * @brief Representation of a characteristic discovered during a GattClient - * discovery procedure (see GattClient::launchServiceDiscovery ). + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup client + * @{ + */ + +/** + * Representation of a characteristic discovered. + * + * The GattClient discovery procedure initiated with + * GattClient::launchServiceDiscovery() generates instances of this class. + * + * It exposes the main attributes of the discovered characteristic: + * - The UUID of the characteristic, it can be retrieved by a call to the + * function getUUID(). This UUID is the type of the characteristic. + * - Attribute Handles of the characteristic are present as the triplet + * declaration handle, value handle and last handle. The value handle is + * used to read or write the content of the characteristic. + * - The properties contain the set of operations the characteristic can + * handle, for instance being read or written. + * + * It important to note that the value of the characteristic - if it is + * accessible - is not fetched at discovery time. + * + * The main operations the class offers are reading, writing and discovering + * the descriptors of the characteristic discovered. + * + * Reading a discovered characteristic can be accomplished in two different + * fashions: + * + * If the user has a callback registered for the data read operation in the + * GattClient, then a call to the read(uint16_t) function will initiate a read of + * the characteristic. Results of the operation will be pass on the callback + * registered by GattClient::onDataRead(), which processes all the responses to + * read requests. The read request for a given characteristic can be identified + * by the connection handle and the attribute handle, which are present in + * GattReadCallbackParams. + * + * Another overload (read(uint16_t, const GattClient::ReadCallback_t&)) of the + * read function accepts a completion callback as a last parameter. That + * completion callback will be invoked automatically once the response to the + * read request for that given characteristic has been received. However, + * convenience came at the expense of dynamic memory usage for the time of the + * transaction. + * + * Similarly, two versions of the write() API are exposed. One where the user + * has to register a callback handling write response through the function + * GattClient::onDataWritten() and another one that accepts a completion + * callback in input. * - * @details Provide detailed informations about a discovered characteristic like: - * - Its UUID (see getUUID()). - * - The most important handles of the characteristic definition - * (see getDeclHandle(), getValueHandle(), getLastHandle()) - * - Its properties (see getProperties()). - * This class also provide functions to operate on the characteristic: - * - Read the characteristic value (see read()) - * - Writing a characteristic value (see write() or writeWoResponse()) - * - Discover descriptors inside the characteristic definition. These descriptors - * extends the characteristic. More information about descriptor usage is - * available in DiscoveredCharacteristicDescriptor class. + * It is also possible to send a write command, which is not acknowledged by the + * peer server by using the function writeWoResponse(). + * + * Finally, descriptors of the characteristic can be discovered by invoking the + * function discoverDescriptors, which is shorthand for calling + * GattClient::discoverCharacteristicDescriptors. That discovery is necessary to + * enable or disable characteristic notification or indication that is achieved + * by writing on the Client Characteristic Configuration Descriptor (CCCD). */ class DiscoveredCharacteristic { public: /** - * Structure that encapsulates the properties of a discovered - * characteristic. + * Properties of a discovered characteristic. */ struct Properties_t { - uint8_t _broadcast :1; /**< Broadcasting the value permitted. */ - uint8_t _read :1; /**< Reading the value permitted. */ - uint8_t _writeWoResp :1; /**< Writing the value with Write Command permitted. */ - uint8_t _write :1; /**< Writing the value with Write Request permitted. */ - uint8_t _notify :1; /**< Notifications of the value permitted. */ - uint8_t _indicate :1; /**< Indications of the value permitted. */ - uint8_t _authSignedWrite :1; /**< Writing the value with Signed Write Command permitted. */ + /** + * Permits broadcasts of the characteristic value using the character + * the Server Characteristic Configuration Descriptor. + * + * @note If set, descriptors of the characteristic contain a Server + * Characteristic Configuration Descriptor. + */ + uint8_t _broadcast :1; + + /** + * If set, the value of the characteristic can be read. + */ + uint8_t _read :1; + + /** + * If set, a write command can write the characteristic value + * (write without response). + */ + uint8_t _writeWoResp :1; + + /** + * If set, clients can issue requests to write the characteristic. + */ + uint8_t _write :1; + + /** + * If set, the server can emit notifications of the Characteristic Value + * (without client acknowledgment). + * + * @note If set, descriptors of the characteristic contain a Client + * Characteristic Configuration Descriptor. + */ + uint8_t _notify :1; + + /** + * If set, the server can emit indication of the Characteristic Value + * (with client acknowledgement). + * + * @note If set, descriptors of the characteristic contain a Client + * Characteristic Configuration Descriptor. + */ + uint8_t _indicate :1; + + /** + * If set, signed write of the Characteristic Value is supported. + */ + uint8_t _authSignedWrite :1; public: /** - * @brief Check if broadcasting is permitted. + * Return the value of the broadcast propertie. * - * @return true if broadcasting the value is permitted, and false - * otherwise. + * @return true if the Server Characteristic Configuration Descriptor + * of the characteristic can be configured to broadcast the + * characteristic value during broadcast procedure. + * + * @see _broadcast */ - bool broadcast(void) const { + bool broadcast(void) const + { return _broadcast; } /** - * @brief Check reading is permitted. + * Return the value of the read property + * + * @return true if the characteristic value can be read and false + * otherwise. * - * @return true if reading the value is permitted, and false - * otherwise. + * @see _read */ - bool read(void) const { + bool read(void) const + { return _read; } /** - * @brief Check if writing with Write Command is permitted. + * Return the value of the write without response property. * - * @return true if writing the value with Write Command is permitted, - * false otherwise. + * @return true if the characteristic accepts write without response + * commands and false otherwise. + * + * @see _writeWoResp */ - bool writeWoResp(void) const { + bool writeWoResp(void) const + { return _writeWoResp; } /** - * @brief Check if writing with Write Request is permitted. + * Return the value of the write property. + * + * @return true if writing the characteristic accepts write requests and + * false otherwise. * - * @return true if writing the value with Write Request is permitted, - * false otherwise. + * @see _write */ - bool write(void) const { + bool write(void) const + { return _write; } /** - * @brief Check notifications are permitted. + * Return the value of the notification property. + * + * @return true if the Client Characteristic Configuration Descriptor + * can be configured to notify the characteristic value to a given + * client and false otherwise. * - * @return true if notifications of the value are permitted, false - * otherwise. + * @note unlike indication, the notification procedure does not require + * acknowledgement from the client. + * + * @see _notify */ - bool notify(void) const { + bool notify(void) const + { return _notify; } /** - * @brief Check if indications are permitted. + * Return the value of the indicate property. + * + * @return true if the Client Characteristic Configuration Descriptor + * can be configured to indicate the characteristic value to a given + * client and false otherwise. * - * @return true if indications of the value are permitted, false - * otherwise. + * @note unlike notification the indication procedure does require + * acknowledgment from the client. + * + * @see _indicate */ - bool indicate(void) const { + bool indicate(void) const + { return _indicate; } /** - * @brief Check if writing with Signed Write Command is permitted. + * Return the value of the authenticated signed writes property. * - * @return true if writing the value with Signed Write Command is - * permitted, false otherwise. + * @return true if the characteristic accepts authenticated signed write + * and false otherwise. */ - bool authSignedWrite(void) const { + bool authSignedWrite(void) const + { return _authSignedWrite; } /** - * @brief "Equal to" operator for DiscoveredCharacteristic::Properties_t + * Equal to operator for DiscoveredCharacteristic::Properties_t. * - * @param[in] lhs The left hand side of the equality expression - * @param[in] rhs The right hand side of the equality expression + * @param[in] lhs The left hand side of the equality expression. + * @param[in] rhs The right hand side of the equality expression. * - * @return true if operands are equals, false otherwise. + * @return true if operands are equals and false otherwise. */ - friend bool operator==(Properties_t lhs, Properties_t rhs) { + friend bool operator==(Properties_t lhs, Properties_t rhs) + { return lhs._broadcast == rhs._broadcast && lhs._read == rhs._read && lhs._writeWoResp == rhs._writeWoResp && @@ -145,121 +259,178 @@ class DiscoveredCharacteristic { } /** - * @brief "Not equal to" operator for DiscoveredCharacteristic::Properties_t + * Not equal to operator for DiscoveredCharacteristic::Properties_t. * - * @param lhs The right hand side of the expression - * @param rhs The left hand side of the expression + * @param lhs The left hand side of the expression. + * @param rhs The right hand side of the expression. * * @return true if operands are not equals, false otherwise. */ - friend bool operator!=(Properties_t lhs, Properties_t rhs) { + friend bool operator!=(Properties_t lhs, Properties_t rhs) + { return !(lhs == rhs); } private: - operator uint8_t() const; /* Disallow implicit conversion into an integer. */ - operator unsigned() const; /* Disallow implicit conversion into an integer. */ + /* Disallow implicit conversion to integer types. */ + operator uint8_t() const; + operator unsigned() const; }; /** - * Initiate (or continue) a read for the value attribute, optionally at a - * given offset. If the characteristic or descriptor to be read is longer - * than ATT_MTU - 1, this function must be called multiple times with - * appropriate offset to read the complete value. - * - * @param[in] offset - * The position - in the characteristic value bytes stream - where - * the read operation begin. - * - * @return BLE_ERROR_NONE if a read has been initiated, or - * BLE_ERROR_INVALID_STATE if some internal state about the connection is invalid, or - * BLE_STACK_BUSY if some client procedure is already in progress, or - * BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's properties. + * Initiate a read of the characteristic value. + * + * The characteristic value is read in its entirety from the value attribute + * of the characteristic. + * + * Read responses will be passed to the callback registered in + * GattClient::onDataRead(). Read responses to read requests that this function + * call initiates will have their GattReadCallbackParams::connHandle + * field equal to the value returned by getConnectionHandle() and their + * GattReadCallbackParams::handle field equal to the value returned by + * getValueHandle(). + * + * @param[in] offset The position - in the characteristic value bytes stream + * - where the read operation begin. This parameter is optional. + * + * @return BLE_ERROR_NONE if a read has been initiated. + * @return BLE_ERROR_INVALID_STATE if some internal state about the + * connection is invalid. + * @return BLE_STACK_BUSY if some client procedure is already in progress. + * @return BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's + * properties. */ ble_error_t read(uint16_t offset = 0) const; /** - * @brief Same as #read(uint16_t) const but allow the user to register a callback - * which will be fired once the read is done. - * - * @param[in] offset - * The position - in the characteristic value bytes stream - where - * the read operation begin. - * @param[in] onRead - * Continuation of the read operation + * Initiate a read of the characteristic value and pass the response to its + * completion callback. + * + * @param[in] offset The position - in the characteristic value bytes stream + * - where the read operation begin. + * + * @param[in] onRead Completion callback which will accept the response of + * the read request. The callback is copied; it is unnecessary to keep it + * in memory after the call. + * + * @return BLE_ERROR_NONE if a read has been initiated. + * @return BLE_ERROR_INVALID_STATE if some internal state about the + * connection is invalid. + * @return BLE_STACK_BUSY if some client procedure is already in progress. + * @return BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's + * properties. + * + * @note This function is similar to read(uint16_t) const; however, it uses + * dynamic memory to store the use completion callback. */ - ble_error_t read(uint16_t offset, const GattClient::ReadCallback_t& onRead) const; + ble_error_t read( + uint16_t offset, + const GattClient::ReadCallback_t &onRead + ) const; /** * Perform a write without response procedure. * - * @param[in] length - * The amount of data being written. - * @param[in] value - * The bytes being written. - * - * @note It is important to note that a write without response will generate - * an onDataSent() callback when the packet has been transmitted. There - * will be a BLE-stack specific limit to the number of pending - * writeWoResponse operations; the user may want to use the onDataSent() - * callback for flow-control. - * - * @retval BLE_ERROR_NONE Successfully started the Write procedure, or - * BLE_ERROR_INVALID_STATE if some internal state about the connection is invalid, or - * BLE_STACK_BUSY if some client procedure is already in progress, or - * BLE_ERROR_NO_MEM if there are no available buffers left to process the request, or - * BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's properties. + * @note The server does not acknowledge write without responses. + * Therefore, they won't generate any event on the client side. + * + * @param[in] length The amount of data being written. + * @param[in] value The bytes being written. + * + * @return BLE_ERROR_NONE Successfully started the Write procedure. + * @return BLE_ERROR_INVALID_STATE if some internal state about the + * connection is invalid. + * @return BLE_STACK_BUSY if some client procedure is already in progress. + * @return BLE_ERROR_NO_MEM if there are no available buffers left to + * process the request. + * @return BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's + * properties. */ ble_error_t writeWoResponse(uint16_t length, const uint8_t *value) const; /** - * Initiate a GATT Characteristic Descriptor Discovery procedure for descriptors within this characteristic. + * Initiate a discovery of the characteristic descriptors. * - * @param[in] onDescriptorDiscovered This callback will be called every time a descriptor is discovered - * @param[in] onTermination This callback will be called when the discovery process is over. + * When a descriptor is discovered, the callback onDescriptorDiscovered is + * invoked with the descriptor discovered as parameter. When the process + * ends, the callback onTermination is invoked. * - * @return BLE_ERROR_NONE if descriptor discovery is launched successfully; else an appropriate error. + * @param[in] onDescriptorDiscovered Callback is invoked when a descriptor is + * discovered. + * + * @param[in] onTermination Callback is invoked when the discovery process ends. + * + * @return BLE_ERROR_NONE if descriptor discovery is launched successfully; + * else an appropriate error. + * + * @note This function is shorthand for + * GattClient::discoverCharacteristicDescriptors; therefore, + * GattClient::isCharacteristicDescriptorDiscoveryActive can be used to + * determine the descriptor discovery and + * GattClient::terminateCharacteristicDescriptorDiscovery can be used to + * end the discovery process. */ - ble_error_t discoverDescriptors(const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& onDescriptorDiscovered, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& onTermination) const; + ble_error_t discoverDescriptors( + const CharacteristicDescriptorDiscovery::DiscoveryCallback_t &onDescriptorDiscovered, + const CharacteristicDescriptorDiscovery::TerminationCallback_t &onTermination + ) const; /** - * Perform a write procedure. + * Initiate a write procedure of the characteristic value. + * + * Unlike write without responses (see writeWoResponse()), an acknowledgment + * is expected for this procedure. The response of the peer GATT server to + * the write request is passed to callbacks registered in + * GattClient::onDataWritten(). + * + * Similarly to read responses, responses to write request of this + * characteristic can be identified by their connection handle ( + * GattWriteCallbackParams::connHandle), which is equal to the value + * returned by getConnectionHandle() and their attribute handle ( + * GattWriteCallbackParams::handle), which is equal to the value + * returned by getValueHandle(). * - * @param[in] length - * The amount of data being written. - * @param[in] value - * The bytes being written. + * @param[in] length The amount of data being written. + * @param[in] value The bytes being written. * - * @note It is important to note that a write will generate - * an onDataWritten() callback when the peer acknowledges the request. + * @return BLE_ERROR_NONE Successfully started the Write procedure. + * @return BLE_ERROR_INVALID_STATE If some internal state about the + * connection is invalid. + * @return BLE_STACK_BUSY If some client procedure is already in progress. + * @return BLE_ERROR_NO_MEM If there are no available buffers left to + * process the request. + * @return BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's + * properties. * - * @retval BLE_ERROR_NONE Successfully started the Write procedure, or - * BLE_ERROR_INVALID_STATE if some internal state about the connection is invalid, or - * BLE_STACK_BUSY if some client procedure is already in progress, or - * BLE_ERROR_NO_MEM if there are no available buffers left to process the request, or - * BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's properties. + * @note Internally, the API uses the write or long write procedure, depending + * on the number of bytes to write and the MTU size. */ ble_error_t write(uint16_t length, const uint8_t *value) const; /** - * Same as write(uint16_t, const uint8_t *) const but register a callback - * which will be called once the data has been written. - * - * @param[in] length - * The amount of bytes to write. - * @param[in] value - * The bytes to write. - * @param[in] onWrite - * Continuation callback for the write operation - * - * @retval BLE_ERROR_NONE Successfully started the Write procedure, or - * BLE_ERROR_INVALID_STATE if some internal state about the connection is invalid, or - * BLE_STACK_BUSY if some client procedure is already in progress, or - * BLE_ERROR_NO_MEM if there are no available buffers left to process the request, or - * BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's properties. + * Initiate a write procedure of the characteristic value. + * + * Same as write(uint16_t, const uint8_t *) const but accepts a completion + * callback, which is invoked when the server response is received. + * + * @param[in] length The amount of bytes to write. + * @param[in] value The bytes to write. + * @param[in] onWrite Continuation callback of the write procedure. + * + * @return BLE_ERROR_NONE Successfully started the Write procedure. + * @return BLE_ERROR_INVALID_STATE if some internal state about the + * connection is invalid. + * @return BLE_STACK_BUSY if some client procedure is already in progress. + * @return BLE_ERROR_NO_MEM if there are no available buffers left to + * process the request. + * @return BLE_ERROR_OPERATION_NOT_PERMITTED due to the characteristic's + * properties. */ - ble_error_t write(uint16_t length, const uint8_t *value, const GattClient::WriteCallback_t& onWrite) const; + ble_error_t write( + uint16_t length, + const uint8_t *value, + const GattClient::WriteCallback_t &onWrite + ) const; void setupLongUUID(UUID::LongUUIDBytes_t longUUID, UUID::ByteOrder_t order = UUID::MSB) { uuid.setupLong(longUUID, order); @@ -267,24 +438,29 @@ class DiscoveredCharacteristic { public: /** - * @brief Get the UUID of the discovered characteristic - * @return the UUID of this characteristic + * Get the UUID of the discovered characteristic. + * + * @return The UUID of this characteristic. */ - const UUID& getUUID(void) const { + const UUID &getUUID(void) const + { return uuid; } /** - * @brief Get the properties of this characteristic - * @return the set of properties of this characteristic + * Get the properties of this characteristic. + * + * @return The set of properties of this characteristic. */ - const Properties_t& getProperties(void) const { + const Properties_t &getProperties(void) const + { return props; } /** - * @brief Get the declaration handle of this characteristic. - * @details The declaration handle is the first handle of a characteristic + * Get the declaration handle of this characteristic. + * + * The declaration handle is the first handle of a characteristic * definition. The value accessible at this handle contains the following * informations: * - The characteristics properties (see Properties_t). This value can @@ -293,74 +469,90 @@ class DiscoveredCharacteristic { * by using #getValueHandle . * - The characteristic UUID, this value can be accessed by using the * function #getUUID . + * * @return the declaration handle of this characteristic. */ - GattAttribute::Handle_t getDeclHandle(void) const { + GattAttribute::Handle_t getDeclHandle(void) const + { return declHandle; } /** - * @brief Return the handle used to access the value of this characteristic. - * @details This handle is the one provided in the characteristic declaration - * value. Usually, it is equal to #getDeclHandle() + 1. But it is not always - * the case. Anyway, users are allowed to use #getDeclHandle() + 1 to access - * the value of a characteristic. + * Get the attribute handle of the characteristic value. + * + * This handle is used to read or write the value of the characteristic. + * * @return The handle to access the value of this characteristic. */ - GattAttribute::Handle_t getValueHandle(void) const { + GattAttribute::Handle_t getValueHandle(void) const + { return valueHandle; } /** - * @brief Return the last handle of the characteristic definition. - * @details A Characteristic definition can contain a lot of handles: - * - one for the declaration (see #getDeclHandle) - * - one for the value (see #getValueHandle) - * - zero of more for the characteristic descriptors. - * This handle is the last handle of the characteristic definition. + * Return the last attribute handle of the characteristic definition. + * + * The attribute layout of a characteristic definition is: + * - Declaration attribute (see #getDeclHandle). + * - Value attribute (see #getValueHandle). + * - Zero or more characteristic descriptors attribute. + * + * The last attribute handle is used internally to discover characteristic + * descriptors. The discovery operates on the range [ValueHandle + 1 : + * LastHandle]. + * * @return The last handle of this characteristic definition. + * + * @note This function is public for informative purposes. */ - GattAttribute::Handle_t getLastHandle(void) const { + GattAttribute::Handle_t getLastHandle(void) const + { return lastHandle; } /** - * @brief Return the GattClient which can operate on this characteristic. - * @return The GattClient which can operate on this characteristic. + * Get the GattClient, which can operate on this characteristic. + * + * @return The GattClient, which can operate on this characteristic. */ - GattClient* getGattClient() { + GattClient* getGattClient() + { return gattc; } /** - * @brief Return the GattClient which can operate on this characteristic. - * @return The GattClient which can operate on this characteristic. + * Get the GattClient, which can operate on this characteristic. + * + * @return The GattClient, which can operate on this characteristic. */ - const GattClient* getGattClient() const { + const GattClient* getGattClient() const + { return gattc; } /** - * @brief Return the connection handle to the GattServer which contain - * this characteristic. - * @return the connection handle to the GattServer which contain - * this characteristic. + * @brief Get the connection handle to the GattServer containing this + * characteristic. + * + * @return Connection handle to the GattServer, which contains this + * characteristic. */ - Gap::Handle_t getConnectionHandle() const { + Gap::Handle_t getConnectionHandle() const + { return connHandle; } /** - * @brief "Equal to" operator for DiscoveredCharacteristic + * "Equal to" operator for DiscoveredCharacteristic. * - * @param[in] lhs - * The left hand side of the equality expression - * @param[in] rhs - * The right hand side of the equality expression + * @param[in] lhs The left hand side of the equality expression. + * @param[in] rhs The right hand side of the equality expression. * - * @return true if operands are equals, false otherwise. + * @return true if operands are equals and false otherwise. */ - friend bool operator==(const DiscoveredCharacteristic& lhs, const DiscoveredCharacteristic& rhs) { + friend bool operator==( + const DiscoveredCharacteristic& lhs, const DiscoveredCharacteristic& rhs + ) { return lhs.gattc == rhs.gattc && lhs.uuid == rhs.uuid && lhs.props == rhs.props && @@ -371,63 +563,75 @@ class DiscoveredCharacteristic { } /** - * @brief "Not equal to" operator for DiscoveredCharacteristic + * "Not equal to" operator for DiscoveredCharacteristic. * - * @param[in] lhs - * The right hand side of the expression - * @param[in] rhs - * The left hand side of the expression + * @param[in] lhs The right hand side of the expression. + * @param[in] rhs The left hand side of the expression. * - * @return true if operands are not equal, false otherwise. + * @return true if operands are not equal and false otherwise. */ - friend bool operator !=(const DiscoveredCharacteristic& lhs, const DiscoveredCharacteristic& rhs) { + friend bool operator !=( + const DiscoveredCharacteristic& lhs, const DiscoveredCharacteristic& rhs + ) { return !(lhs == rhs); } public: - DiscoveredCharacteristic() : gattc(NULL), - uuid(UUID::ShortUUIDBytes_t(0)), - props(), - declHandle(GattAttribute::INVALID_HANDLE), - valueHandle(GattAttribute::INVALID_HANDLE), - lastHandle(GattAttribute::INVALID_HANDLE), - connHandle() { - /* empty */ + DiscoveredCharacteristic() : + gattc(NULL), + uuid(UUID::ShortUUIDBytes_t(0)), + props(), + declHandle(GattAttribute::INVALID_HANDLE), + valueHandle(GattAttribute::INVALID_HANDLE), + lastHandle(GattAttribute::INVALID_HANDLE), + connHandle() { } protected: /** - * Pointer to the underlying GattClient for this DiscoveredCharacteristic object. + * Pointer to the underlying GattClient for this DiscoveredCharacteristic + * object. */ - GattClient *gattc; + GattClient *gattc; protected: /** * Discovered characteristic's UUID. */ - UUID uuid; + UUID uuid; + /** * Hold the configured properties of the discovered characteristic. - * For more information refer to Properties_t. + * + * @see Properties_t. */ - Properties_t props; + Properties_t props; + /** * Value handle of the discovered characteristic's declaration attribute. */ - GattAttribute::Handle_t declHandle; + GattAttribute::Handle_t declHandle; + /** * Value handle of the discovered characteristic's value attribute. */ - GattAttribute::Handle_t valueHandle; + GattAttribute::Handle_t valueHandle; + /** * Value handle of the discovered characteristic's last attribute. */ - GattAttribute::Handle_t lastHandle; + GattAttribute::Handle_t lastHandle; /** - * Handle for the connection where the characteristic was discovered. + * Handle of the connection where the characteristic was discovered. */ - Gap::Handle_t connHandle; + Gap::Handle_t connHandle; }; -#endif /*__DISCOVERED_CHARACTERISTIC_H__*/ +/** + * @} + * @} + * @} + */ + +#endif /*MBED_DISCOVERED_CHARACTERISTIC_H__*/ diff --git a/features/FEATURE_BLE/ble/DiscoveredCharacteristicDescriptor.h b/features/FEATURE_BLE/ble/DiscoveredCharacteristicDescriptor.h index 07aa1275923..bb64c74486d 100644 --- a/features/FEATURE_BLE/ble/DiscoveredCharacteristicDescriptor.h +++ b/features/FEATURE_BLE/ble/DiscoveredCharacteristicDescriptor.h @@ -14,8 +14,8 @@ * limitations under the License. */ -#ifndef __DISCOVERED_CHARACTERISTIC_DESCRIPTOR_H__ -#define __DISCOVERED_CHARACTERISTIC_DESCRIPTOR_H__ +#ifndef MBED_DISCOVERED_CHARACTERISTIC_DESCRIPTOR_H__ +#define MBED_DISCOVERED_CHARACTERISTIC_DESCRIPTOR_H__ #include "UUID.h" #include "Gap.h" @@ -24,16 +24,32 @@ #include "CharacteristicDescriptorDiscovery.h" /** - * @brief Representation of a descriptor discovered during a GattClient - * discovery procedure (see GattClient::discoverCharacteristicDescriptors or - * DiscoveredCharacteristic::discoverDescriptors ). + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup client + * @{ + */ + +/** + * Representation of a characteristic descriptor discovered. + * + * Characteristic descriptors can be seen as the metadata of the characteristic. + * They can contain things such as the unit of the characteristic value, extra + * permission informations or the Client Configuration state in regard to + * notification or indication. + * + * The descriptors of a characterstic are discovered by a Characteristic + * Descriptor Discovery Procedure, which can be initiated by either + * GattClient::discoverCharacteristicDescriptors() or + * DiscoveredCharacteristic::discoverDescriptors(). * - * @details Provide detailed informations about a discovered characteristic descriptor - * like: - * - Its UUID (see #getUUID). - * - Its handle (see #getAttributeHandle) - * Basic read (see GattClient::read) and write (see GattClient::write) procedure from - * GattClient can be used access the value of the descriptor. + * The discovery procedure returns the UUID of the descriptor (its type) and its + * handle. + * + * Read and write of the descriptor value can be initiated by + * GattClient::read and GattClient::write. * * @todo read member function * @todo write member function @@ -44,60 +60,80 @@ class DiscoveredCharacteristicDescriptor { public: /** - * @brief construct a new instance of a DiscoveredCharacteristicDescriptor + * Construct a new instance of a DiscoveredCharacteristicDescriptor. + * + * @param[in] client The client that has discovered the descriptor. + * @param[in] connectionHandle Handle of the connection to the GATT server + * containing the descriptor. + * @param[in] attributeHandle GATT attribute handle of the descriptor. + * @param[in] uuid UUID of the descriptor. * - * @param client The client from where the descriptor has been discovered - * @param connectionHandle The connection handle on which the descriptor has - * been discovered - * @param attributeHandle The handle of the attribute containing this descriptor - * @param uuid The UUID of the descriptor + * @note This constructor is not meant to be called directly by application + * code. The Gattclient class generates descriptors discovered. */ DiscoveredCharacteristicDescriptor( - GattClient* client, Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, const UUID& uuid) : - _client(client), _connectionHandle(connectionHandle), _uuid(uuid), _gattHandle(attributeHandle) { - + GattClient *client, + Gap::Handle_t connectionHandle, + GattAttribute::Handle_t attributeHandle, + const UUID &uuid + ) : _client(client), + _connectionHandle(connectionHandle), + _uuid(uuid), + _gattHandle(attributeHandle) { } /** - * @brief Return the GattClient which can operate on this descriptor. - * @return The GattClient which can operate on this descriptor. + * Return the GattClient, which can operate on this descriptor. + * + * @return GattClient, which can operate on this descriptor. */ - GattClient* getGattClient() { + GattClient* getGattClient() + { return _client; } /** - * @brief Return the GattClient which can operate on this descriptor. - * @return The GattClient which can operate on this descriptor. + * Return the GattClient, which can operate on this descriptor. + * + * @return GattClient, which can operate on this descriptor. */ - const GattClient* getGattClient() const { + const GattClient* getGattClient() const + { return _client; } /** - * @brief Return the connection handle to the GattServer which contain - * this descriptor. - * @return the connection handle to the GattServer which contain - * this descriptor. + * Return the connection handle to the GattServer containing this + * descriptor. + * + * @return the connection handle to the GattServer containing this + * descriptor. */ - Gap::Handle_t getConnectionHandle() const { + Gap::Handle_t getConnectionHandle() const + { return _connectionHandle; } /** - * @brief Return the UUID of this descriptor - * @return the UUID of this descriptor + * Return the UUID of this descriptor. + * + * @return UUID of this descriptor. */ - const UUID& getUUID(void) const { + const UUID& getUUID(void) const + { return _uuid; } /** - * @brief Return the attribute handle to use to access to this descriptor - * on the gatt server. - * @return The attribute handle of the descriptor + * Return the attribute handle of this descriptor. + * + * This attribute handle can be used to interact with the descriptor on its + * gatt server. + * + * @return Attribute handle of the descriptor */ - GattAttribute::Handle_t getAttributeHandle() const { + GattAttribute::Handle_t getAttributeHandle() const + { return _gattHandle; } @@ -108,4 +144,10 @@ class DiscoveredCharacteristicDescriptor { GattAttribute::Handle_t _gattHandle; }; -#endif /*__DISCOVERED_CHARACTERISTIC_DESCRIPTOR_H__*/ +/** + * @} + * @} + * @} + */ + +#endif /* MBED_DISCOVERED_CHARACTERISTIC_DESCRIPTOR_H__ */ diff --git a/features/FEATURE_BLE/ble/DiscoveredService.h b/features/FEATURE_BLE/ble/DiscoveredService.h index b0e6105dbdc..cfa97e9039f 100644 --- a/features/FEATURE_BLE/ble/DiscoveredService.h +++ b/features/FEATURE_BLE/ble/DiscoveredService.h @@ -14,106 +14,168 @@ * limitations under the License. */ -#ifndef __DISCOVERED_SERVICE_H__ -#define __DISCOVERED_SERVICE_H__ +#ifndef MBED_DISCOVERED_SERVICE_H__ +#define MBED_DISCOVERED_SERVICE_H__ #include "UUID.h" #include "GattAttribute.h" -/**@brief Type for holding information about the service and the characteristics found during - * the discovery process. +/** + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup client + * @{ + */ + +/** + * Representation of a GATT service discovered. + * + * The discovery procedure discovers GATT Services are discovered on distant + * GATT servers, which can be initiated by calling + * GattClient::launchServiceDiscovery() or GattClient::discoverServices(). The + * discovery process passes instances of this class to the callback handling + * service discovered. + * + * Discovered services are characterized by the UUID of the service discovered + * and the range of the GATT attributes belonging to the service. + * + * The UUID can be queried by calling getUUID() while the begining of the + * attribute range can be obtained through getStartHandle() and the end of the + * attribute range with a call to getEndHandle(). + * + * The characteristics composing the service may be discovered by the function + * GattClient::launchServiceDiscovery(). */ class DiscoveredService { public: /** - * Set information about the discovered service. + * Get the UUID of the discovered service. * - * @param[in] uuidIn - * The UUID of the discovered service. - * @param[in] startHandleIn - * The start handle of the discovered service in the peer's - * ATT table. - * @param[in] endHandleIn - * The end handle of the discovered service in the peer's - * ATT table. + * @return A reference to the UUID of the discovered service. */ - void setup(UUID uuidIn, GattAttribute::Handle_t startHandleIn, GattAttribute::Handle_t endHandleIn) { - uuid = uuidIn; - startHandle = startHandleIn; - endHandle = endHandleIn; + const UUID &getUUID(void) const + { + return uuid; } /** - * Set the start and end handle of the discovered service. - * @param[in] startHandleIn - * The start handle of the discovered service in the peer's - * ATT table. - * @param[in] endHandleIn - * The end handle of the discovered service in the peer's - * ATT table. + * Get the start handle of the discovered service in the peer's GATT server. + * + * @return A reference to the start handle. */ - void setup(GattAttribute::Handle_t startHandleIn, GattAttribute::Handle_t endHandleIn) { - startHandle = startHandleIn; - endHandle = endHandleIn; + const GattAttribute::Handle_t& getStartHandle(void) const + { + return startHandle; } /** - * Set the long UUID of the discovered service. + * Get the end handle of the discovered service in the peer's GATT server. * - * @param[in] longUUID - * The long UUID of the discovered service. - * @param[in] order - * The byte ordering of @p longUUID. + * @return A reference to the end handle. */ - void setupLongUUID(UUID::LongUUIDBytes_t longUUID, UUID::ByteOrder_t order = UUID::MSB) { - uuid.setupLong(longUUID, order); + const GattAttribute::Handle_t& getEndHandle(void) const + { + return endHandle; } public: /** - * Get the UUID of the discovered service. + * Construct a DiscoveredService instance. * - * @return A reference to the UUID of the discovered service. + * @important This API is not meant to be used publicly. It is meant to be + * used by internal APIs of Mbed BLE. */ - const UUID &getUUID(void) const { - return uuid; + DiscoveredService() : + uuid(UUID::ShortUUIDBytes_t(0)), + startHandle(GattAttribute::INVALID_HANDLE), + endHandle(GattAttribute::INVALID_HANDLE) { } /** - * Get the start handle of the discovered service in the peer's ATT table. + * Set information about the discovered service. * - * @return A reference to the start handle. + * @important This API is not meant to be used publicly. It is meant to be + * used by internal APIs of Mbed BLE. + * + * @param[in] uuidIn The UUID of the discovered service. + * @param[in] startHandleIn The start handle of the discovered service in + * the peer's GATT server. + * @param[in] endHandleIn The end handle of the discovered service in the + * peer's GATT server. */ - const GattAttribute::Handle_t& getStartHandle(void) const { - return startHandle; + void setup( + UUID uuidIn, + GattAttribute::Handle_t startHandleIn, + GattAttribute::Handle_t endHandleIn + ) { + uuid = uuidIn; + startHandle = startHandleIn; + endHandle = endHandleIn; } /** - * Get the end handle of the discovered service in the peer's ATT table. + * Set the start and end handle of the discovered service. * - * @return A reference to the end handle. + * @important This API is not meant to be used publicly. It is meant to be + * used by internal APIs of Mbed BLE. + * + * @param[in] startHandleIn The start handle of the discovered service in + * the peer's GATT server. + * @param[in] endHandleIn The end handle of the discovered service in the + * peer's GATT server. */ - const GattAttribute::Handle_t& getEndHandle(void) const { - return endHandle; + void setup( + GattAttribute::Handle_t startHandleIn, + GattAttribute::Handle_t endHandleIn + ) { + startHandle = startHandleIn; + endHandle = endHandleIn; } -public: /** - * Construct a DiscoveredService instance. + * Set the long UUID of the discovered service. + * + * @important This API is not meant to be used publicly. It is meant to be + * used by internal APIs of Mbed BLE. + * + * @param[in] longUUID The bytes composing the long UUID of this discovered + * service. + * @param[in] order The byte ordering of @p longUUID. */ - DiscoveredService() : uuid(UUID::ShortUUIDBytes_t(0)), - startHandle(GattAttribute::INVALID_HANDLE), - endHandle(GattAttribute::INVALID_HANDLE) { - /* empty */ + void setupLongUUID( + UUID::LongUUIDBytes_t longUUID, + UUID::ByteOrder_t order = UUID::MSB + ) { + uuid.setupLong(longUUID, order); } + private: DiscoveredService(const DiscoveredService &); private: - UUID uuid; /**< UUID of the service. */ - GattAttribute::Handle_t startHandle; /**< Service Handle Range. */ - GattAttribute::Handle_t endHandle; /**< Service Handle Range. */ + /** + * UUID of the service. + */ + UUID uuid; + + /** + * Begining of the Service Handle Range. + */ + GattAttribute::Handle_t startHandle; + + /** + * Service Handle Range. + */ + GattAttribute::Handle_t endHandle; }; -#endif /*__DISCOVERED_SERVICE_H__*/ +/** + * @} + * @} + * @} + */ + +#endif /* MBED_DISCOVERED_SERVICE_H__ */ diff --git a/features/FEATURE_BLE/ble/FunctionPointerWithContext.h b/features/FEATURE_BLE/ble/FunctionPointerWithContext.h index 02b07a680e2..1a38a987e86 100644 --- a/features/FEATURE_BLE/ble/FunctionPointerWithContext.h +++ b/features/FEATURE_BLE/ble/FunctionPointerWithContext.h @@ -20,8 +20,37 @@ #include #include "SafeBool.h" -/** A class for storing and calling a pointer to a static or member void function - * that takes a context. +/** + * @file + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ + +/** + * Function like object adapter over freestanding and member functions. + * + * Freestanding and member functions are two distinct types in C++. One is + * not convertible into the other, and the call syntax between the two is + * different even if conceptually they are similar: Both primitives can be + * copied, called and produce a result. + * + * To solve incompatibilities, this class adapts freestanding and member functions + * to a common interface. The interface chosen is similar to the freestanding + * function pointers interface: + * - Copyable. + * - Nullable. + * - Callable. + * + * This class also offers a mechanism to chain other instances to it. When an + * instance is called, all the instances being part of the chain are called. + * + * @important freestanding or member function adapted must accept a single + * argument, and this argument is a pointer to ContextType. Adapted + * primitives do not return anything. + * + * @tparam ContextType Type of the argument pointee. */ template class FunctionPointerWithContext : public SafeBool > { @@ -30,111 +59,201 @@ class FunctionPointerWithContext : public SafeBool *cpFunctionPointerWithContext_t; typedef void (*pvoidfcontext_t)(ContextType context); - /** Create a FunctionPointerWithContext, attaching a static function. + /** + * Create a FunctionPointerWithContext from a pointer to a freestanding + * function. * - * @param function The void static function to attach (default is none). + * @param[in] function The freestanding function to attach. */ FunctionPointerWithContext(void (*function)(ContextType context) = NULL) : - _memberFunctionAndPointer(), _caller(NULL), _next(NULL) { + _memberFunctionAndPointer(), _caller(NULL), _next(NULL) + { attach(function); } - /** Create a FunctionPointerWithContext, attaching a member function. + /** + * Create a FunctionPointerWithContext from a pointer to a member function + * and the instance which is used to call it. * - * @param object The object pointer to invoke the member function on (the "this" pointer). - * @param function The address of the void member function to attach. + * @param[in] object Pointer to the instance which is used to invoke @p + * member. + * @param[in] Pointer to the member function to adapt. */ template FunctionPointerWithContext(T *object, void (T::*member)(ContextType context)) : - _memberFunctionAndPointer(), _caller(NULL), _next(NULL) { + _memberFunctionAndPointer(), _caller(NULL), _next(NULL) + { attach(object, member); } - FunctionPointerWithContext(const FunctionPointerWithContext& that) : - _memberFunctionAndPointer(that._memberFunctionAndPointer), _caller(that._caller), _next(NULL) { + /** + * Copy construction. + * + * @param[in] that The FunctionPointerWithContext instance used to create + * this. + */ + FunctionPointerWithContext(const FunctionPointerWithContext &that) : + _memberFunctionAndPointer(that._memberFunctionAndPointer), + _caller(that._caller), _next(NULL) { } - FunctionPointerWithContext& operator=(const FunctionPointerWithContext& that) { + /** + * Copy assignment. + * + * @param[in] that The FunctionPointerWithContext instance copied into this. + */ + FunctionPointerWithContext &operator=(const FunctionPointerWithContext &that) + { _memberFunctionAndPointer = that._memberFunctionAndPointer; - _caller = that._caller; + _caller = that._caller; _next = NULL; return *this; } - /** Attach a static function. + /** + * Adapt a freestanding function. + * + * Previous content adapted is discarded while @p function replaces it. * - * @param function The void static function to attach (default is none). + * @note This function is equivalent to a call to the copy assignment + * operator. + * + * @param[in] function The freestanding function to attach. */ - void attach(void (*function)(ContextType context) = NULL) { + void attach(void (*function)(ContextType context) = NULL) + { _function = function; _caller = functioncaller; } - /** Attach a member function. + /** + * Adapt a pointer to member function and the instance to use to call it. * - * @param object The object pointer to invoke the member function on (the "this" pointer). - * @param function The address of the void member function to attach. + * Previous content adapted is discarded while the adaptation + * of the pair @p object and @p member replaces it. + * + * @note This function is equivalent to a call to the copy assignment + * operator. + * + * @param[in] object Pointer to the instance is used to invoke @p member. + * @param[in] function Pointer to the member function to adapt. */ template - void attach(T *object, void (T::*member)(ContextType context)) { + void attach(T *object, void (T::*member)(ContextType context)) + { _memberFunctionAndPointer._object = static_cast(object); - memcpy(_memberFunctionAndPointer._memberFunction, (char*) &member, sizeof(member)); + memcpy( + _memberFunctionAndPointer._memberFunction, + (char*) &member, + sizeof(member) + ); _caller = &FunctionPointerWithContext::membercaller; } - /** Call the attached static or member function; if there are chained - * FunctionPointers their callbacks are invoked as well. - * @Note: All chained callbacks stack up, so hopefully there won't be too - * many FunctionPointers in a chain. */ - void call(ContextType context) const { + /** + * Call the adapted function and functions chained to the instance. + * + * @param[in] context parameter to pass to chain of adapted functions. + */ + void call(ContextType context) const + { _caller(this, context); } /** - * @brief Same as above + * Call the adapted function and functions chained to the instance. + * + * @param[in] context parameter to pass to chain of adapted functions. */ - void operator()(ContextType context) const { - call(context); + void call(ContextType context) + { + ((const FunctionPointerWithContext*) this)->call(context); } - /** Same as above, workaround for mbed os FunctionPointer implementation. */ - void call(ContextType context) { - ((const FunctionPointerWithContext*) this)->call(context); + /** + * Call the adapted function and functions chained to the instance. + * + * @param[in] context parameter to pass to chain of adapted functions. + */ + void operator()(ContextType context) const + { + call(context); } typedef void (FunctionPointerWithContext::*bool_type)() const; - /** - * implementation of safe bool operator + /** + * Indicate if a callable object is being adapted. + * + * @note implementation of safe bool operator. + * + * @return true if the content of the instance can be invoked and false + * otherwise. */ - bool toBool() const { + bool toBool() const + { return (_function || _memberFunctionAndPointer._object); } /** - * Set up an external FunctionPointer as a next in the chain of related - * callbacks. Invoking call() on the head FunctionPointer will invoke all + * Set a FunctionPointer instance as the next element in the chain of + * callable objects. + * + * @note Invoking call() on the head FunctionPointer invokes all * chained callbacks. * - * Refer to 'CallChain' as an alternative. + * @note Refer to CallChainOfFunctionPointerWithContext as an alternative. + * + * @param next The instance to set as the next element in the chain of + * callable objects. */ - void chainAsNext(pFunctionPointerWithContext_t next) { + void chainAsNext(pFunctionPointerWithContext_t next) + { _next = next; } - pFunctionPointerWithContext_t getNext(void) const { + /** + * Access the next element in the call chain. + * + * If there is no next element in the chain, this function returns NULL. + * + * @return A pointer to the next FunctionPointerWithContext instance in the + * chain. + */ + pFunctionPointerWithContext_t getNext(void) const + { return _next; } - pvoidfcontext_t get_function() const { + /** + * Access the next element in the call chain. + * + * If there is no next element in the chain, this function returns NULL. + * + * @return A pointer to the next FunctionPointerWithContext instance in the + * chain. + */ + pvoidfcontext_t get_function() const + { return (pvoidfcontext_t)_function; } - friend bool operator==(const FunctionPointerWithContext& lhs, const FunctionPointerWithContext& rhs) { + /** + * Equal to operator between two FunctionPointerWithContext instances. + * + * @param[in] lhs Left hand side of the expression. + * @param[in] rhs Right hand side of the expression. + * + * @return true if lhs and rhs adapt the same object and false otherwise. + */ + friend bool operator==( + const FunctionPointerWithContext &lhs, + const FunctionPointerWithContext &rhs + ) { return rhs._caller == lhs._caller && memcmp( - &rhs._memberFunctionAndPointer, - &lhs._memberFunctionAndPointer, + &rhs._memberFunctionAndPointer, + &lhs._memberFunctionAndPointer, sizeof(rhs._memberFunctionAndPointer) ) == 0; } @@ -160,7 +279,7 @@ class FunctionPointerWithContext : public SafeBool( + * &read_handler, + * &ReadHandler::on_data_read + * ) + * ); + * @endcode + * + * + * @param[in] object Instance to bound with @p member. + * @param member The member being adapted. + * + * @return Adaptation of the parameters in a FunctionPointerWithContext instance. */ template -FunctionPointerWithContext makeFunctionPointer(T *object, void (T::*member)(ContextType context)) -{ +FunctionPointerWithContext makeFunctionPointer( + T *object, + void (T::*member)(ContextType context) +) { return FunctionPointerWithContext(object, member); } +/** + * @} + * @} + */ + #endif // ifndef MBED_FUNCTIONPOINTER_WITH_CONTEXT_H diff --git a/features/FEATURE_BLE/ble/Gap.h b/features/FEATURE_BLE/ble/Gap.h index 1f8c62cb69f..fb13050d91d 100644 --- a/features/FEATURE_BLE/ble/Gap.h +++ b/features/FEATURE_BLE/ble/Gap.h @@ -14,24 +14,257 @@ * limitations under the License. */ -#ifndef __GAP_H__ -#define __GAP_H__ +#ifndef MBED_BLE_GAP_H__ +#define MBED_BLE_GAP_H__ #include "BLETypes.h" -#include "ble/BLEProtocol.h" +#include "BLEProtocol.h" #include "GapAdvertisingData.h" #include "GapAdvertisingParams.h" #include "GapScanningParams.h" #include "GapEvents.h" #include "CallChainOfFunctionPointersWithContext.h" #include "FunctionPointerWithContext.h" -#include "deprecate.h" +#include "platform/mbed_toolchain.h" -/* Forward declarations for classes that will only be used for pointers or references in the following. */ +/* Forward declarations for classes that are only used for pointers or + references. */ class GapAdvertisingParams; class GapScanningParams; class GapAdvertisingData; +/** + * @addtogroup ble + * @{ + * @addtogroup gap + * @{ + */ + +/** + * Define device discovery, connection and link management procedures. + * + * - Device discovery: A device can advertise nearby peers of its existence, + * identity and capabilities. Similarly, a device can scan its environment to + * find advertising peers. The information acquired during the scan helps to + * identify peers and understand their use. A scanner may acquire more information + * about an advertising peer by sending a scan request. If the peer accepts scan + * requests, it may reply with additional information about its state. + * + * - Connection: A bluetooth device can establish a connection to a connectable + * advertising peer. Once the connection is established, both devices can + * communicate using the GATT protocol. The GATT protocol allows connected + * devices to expose a set of states that the other peer can discover, read and write. + * + * - Link Management: Connected devices may drop the connection and may adjust + * connection parameters according to the power envelop needed for their + * application. + * + * @par Accessing gap + * + * Instance of a Gap class for a given BLE device should be accessed using + * BLE::gap(). The reference returned remains valid until the BLE instance + * shut down (see BLE::shutdown()). + * + * @code + * // assuming ble_device has been initialized + * BLE& ble_device; + * + * Gap& gap = ble_device.gap(); + * @endcode + * + * @par Advertising + * + * Advertising consists of broadcasting at a regular interval a small amount of + * data containing valuable informations about the device. These packets may be + * scanned by peer devices listening on BLE advertising channels. + * + * Scanners may also request additional information from a device advertising by + * sending a scan request. If the broadcaster accepts scan requests, it can reply + * with a scan response packet containing additional information. + * + * @code + * // assuming gap has been initialized + * Gap& gap; + * + * // construct the packet to advertise + * GapAdvertisingData advertising_data; + * + * // Add advertiser flags + * advertising_data.addFlags( + * GapAdvertisingData::LE_GENERAL_DISCOVERABLE | + * GapAdvertisingData::BREDR_NOT_SUPPORTED + * ); + * + * // Add the name of the device to the advertising data + * static const uint8_t device_name[] = "HRM"; + * advertising_data.addData( + * GapAdvertisingData::COMPLETE_LOCAL_NAME, + * device_name, + * sizeof(device_name) + * ); + * + * // set the advertising data in the gap instance, they will be used when + * // advertising starts. + * gap.setAdvertisingPayload(advertising_data); + * + * // Configure the advertising procedure + * GapAdvertisingParams advertising_params( + * GapAdvertisingParams::ADV_CONNECTABLE_UNDIRECTED, // type of advertising + * GapAdvertisingParams::MSEC_TO_ADVERTISEMENT_DURATION_UNITS(1000), // interval + * 0 // The advertising procedure will not timeout + * ); + * + * gap.setAdvertisingParams(advertising_params); + * + * // start the advertising procedure, the device will advertise its flag and the + * // name "HRM". Other peers will also be allowed to connect to it. + * gap.startAdvertising(); + * @endcode + * + * @par Scanning + * + * Scanning consist of listening for peer advertising packets. From a scan, a + * device can identify devices available in its environment. + * + * If the device scans actively, then it will send scan request to scannable + * advertisers and collect their scan response. + * + * @code + * // assuming gap has been initialized + * Gap& gap; + * + * // Handle advertising packet by dumping their content + * void handle_advertising_packet(const AdvertisementCallbackParams_t* packet) + * { + * printf("Packet received: \r\n"); + * printf(" - peer address: %02X:%02X:%02X:%02X:%02X:%02X\r\n", + * packet->peerAddr[5], packet->peerAddr[4], packet->peerAddr[3], + * packet->peerAddr[2], packet->peerAddr[1], packet->peerAddr[0]); + * printf(" - rssi: %d", packet->rssi); + * printf(" - scan response: %s\r\n", packet->isScanresponse ? "true" : "false"); + * printf(" - advertising type: %d\r\n", packet->type); + * printf(" - advertising type: %d\r\n", packet->type); + * printf(" - Advertising data: \r\n"); + * + * // parse advertising data, it is a succession of AD structures where + * // the first byte is the size of the AD structure, the second byte the + * // type of the data and remaining bytes are the value. + * + * for (size_t i = 0; i < packet->advertisingDataLen; i += packet->advertisingData[i]) { + * printf(" - type: 0X%02X, data: ", packet->advertisingData[i + 1]); + * for (size_t j = 0; j < packet->advertisingData[i] - 2; ++j) { + * printf("0X%02X ", packet->advertisingData[i + 2 + j]); + * } + * printf("\r\n"); + * } + * } + * + * // set the scan parameters + * gap.setScanParams( + * 100, // interval between two scan window in ms + * 50, // scan window: period during which the device listen for advertising packets. + * 0, // the scan process never ends + * true // the device sends scan request to scannable peers. + * ); + * + * // start the scan procedure + * gap.startScan(handle_advertising_packet); + * @endcode + * + * @par Connection event handling + * + * A peer may connect device advertising connectable packets. The + * advertising procedure ends as soon as the device is connected. + * + * A device accepting a connection request from a peer is named a peripheral, + * and the device initiating the connection is named a central. + * + * Peripheral and central receive a connection event when the connection is + * effective. + * + * @code + * Gap& gap; + * + * // handle connection event + * void when_connected(const ConnectionCallbackParams_t *connection_event) { + * // If this callback is entered, then the connection to a peer is effective. + * } + * + * // register connection event handler, which will be invoked whether the device + * // acts as a central or a peripheral + * gap.onConnection(when_connected); + * @endcode + * + * @par Connection initiation + * + * Connection is initiated central devices. + * + * @code + * // assuming gap has been initialized + * Gap& gap; + * + * // Handle the connection event + * void handle_connection(const ConnectionCallbackParams_t* connection_event) + * { + * // event handling + * } + * + * // Handle advertising packet: connect to the first connectable device + * void handle_advertising_packet(const AdvertisementCallbackParams_t* packet) + * { + * if (packet->type != GapAdvertisingParams::ADV_CONNECTABLE_UNDIRECTED) { + * return; + * } + * + * // register connection event handler + * gap.onConnection(handle_connection); + * + * Gap::ConnectionParams_t connection_parameters = { + * 50, // min connection interval + * 100, // max connection interval + * 0, // slave latency + * 600 // connection supervision timeout + * }; + * + * // scan parameter used to find the device to connect to + * GapScanningParams scanning_params( + * 100, // interval + * 100, // window + * 0, // timeout + * false // active + * ); + * + * // Initiate the connection procedure + * gap.connect( + * packet->peerAddr, + * BLEProtocol::RANDOM_STATIC, + * &connection_parameters, + * &scanning_params + * ); + * } + * + * // set the scan parameters + * gap.setScanParams( + * 100, // interval between two scan window in ms + * 50, // scan window: period during which the device listen for advertising packets. + * 0, // the scan process never ends + * true // the device sends scan request to scannable peers. + * ); + * + * // start the scan procedure + * gap.startScan(handle_advertising_packet); + * @endcode + * + * @par disconnection + * + * The application code initiates a disconnection when it calls the + * disconnect(Handle_t, DisconnectionReason_t) function. + * + * Disconnection may also be initiated by the remote peer or the local + * controller/stack. To catch all disconnection events, application code may + * set up an handler taking care of disconnection events by calling + * onDisconnection(). + */ class Gap { /* * DEPRECATION ALERT: all of the APIs in this `public` block are deprecated. @@ -56,14 +289,13 @@ class Gap { * Address-type for BLEProtocol addresses. * * @deprecated Use BLEProtocol::AddressType_t instead. The following - * constants have been left in their deprecated state to - * transparently support existing applications which may have - * used Gap::ADDR_TYPE_*. + * constants have been left in their deprecated state to transparently + * support existing applications that may have used Gap::ADDR_TYPE_*. */ enum DeprecatedAddressType_t { - ADDR_TYPE_PUBLIC = BLEProtocol::AddressType::PUBLIC, - ADDR_TYPE_RANDOM_STATIC = BLEProtocol::AddressType::RANDOM_STATIC, - ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE = BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE, + ADDR_TYPE_PUBLIC = BLEProtocol::AddressType::PUBLIC, + ADDR_TYPE_RANDOM_STATIC = BLEProtocol::AddressType::RANDOM_STATIC, + ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE = BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE, ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE = BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE }; @@ -71,12 +303,14 @@ class Gap { * Length (in octets) of the BLE MAC address. */ static const unsigned ADDR_LEN = BLEProtocol::ADDR_LEN; + /** * 48-bit address, LSB format. * * @deprecated Use BLEProtocol::AddressBytes_t instead. */ typedef BLEProtocol::AddressBytes_t Address_t; + /** * 48-bit address, LSB format. * @@ -86,511 +320,813 @@ class Gap { public: /** - * Enumeration for timeout sources. + * Enumeration of possible timeout sources. */ enum TimeoutSource_t { - TIMEOUT_SRC_ADVERTISING = 0x00, /**< Advertising timeout. */ - TIMEOUT_SRC_SECURITY_REQUEST = 0x01, /**< Security request timeout. */ - TIMEOUT_SRC_SCAN = 0x02, /**< Scanning timeout. */ - TIMEOUT_SRC_CONN = 0x03, /**< Connection timeout. */ + /** + * Advertising timeout. + */ + TIMEOUT_SRC_ADVERTISING = 0x00, + + /** + * Security request timeout. + */ + TIMEOUT_SRC_SECURITY_REQUEST = 0x01, + + /** + * Scanning timeout. + */ + TIMEOUT_SRC_SCAN = 0x02, + + /** + * Connection timeout. + */ + TIMEOUT_SRC_CONN = 0x03, }; /** - * Enumeration for disconnection reasons. The values for these reasons are - * derived from Nordic's implementation, but the reasons are meant to be - * independent of the transport. If you are returned a reason that is not - * covered by this enumeration, please refer to the underlying - * transport library. + * Enumeration of disconnection reasons. + * + * @important There might be a mismatch between the disconnection reason + * passed to disconnect() and the disconnection event generated locally + * because the disconnection reason passed to disconnect() is the + * disconnection reason to be transmitted to the peer. */ enum DisconnectionReason_t { - CONNECTION_TIMEOUT = 0x08, - REMOTE_USER_TERMINATED_CONNECTION = 0x13, - REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES = 0x14, /**< Remote device terminated connection due to low resources.*/ - REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF = 0x15, /**< Remote device terminated connection due to power off. */ - LOCAL_HOST_TERMINATED_CONNECTION = 0x16, - CONN_INTERVAL_UNACCEPTABLE = 0x3B, + /** + * The connection timed out. + * + * @important shall not be used as a reason in disconnect(). + */ + CONNECTION_TIMEOUT = 0x08, + + /** + * Connection terminated by the user. + */ + REMOTE_USER_TERMINATED_CONNECTION = 0x13, + + /** + * Remote device terminated connection due to low resources. + */ + REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES = 0x14, + + /** + * Remote device terminated connection due to power off. + */ + REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF = 0x15, + + /** + * Indicate that the local user or the internal + * Bluetooth subsystem terminated the connection. + * + * @important shall not be used as a reason in disconnect(). + */ + LOCAL_HOST_TERMINATED_CONNECTION = 0x16, + + /** + * Connection parameters were unacceptable. + */ + CONN_INTERVAL_UNACCEPTABLE = 0x3B, }; /** - * Enumeration for whitelist advertising policy filter modes. The possible - * filter modes were obtained from the Bluetooth Core Specification - * 4.2 (Vol. 6), Part B, Section 4.3.2. + * Advertising policy filter modes. * - * @experimental + * @see Bluetooth Core Specification 4.2 (Vol. 6), Part B, Section 4.3.2. */ enum AdvertisingPolicyMode_t { + /** + * The whitelist is not used to filter peer request during advertising. + */ ADV_POLICY_IGNORE_WHITELIST = 0, + + /** + * The whitelist is used to filter peer scan requests. + */ ADV_POLICY_FILTER_SCAN_REQS = 1, + + /** + * The whitelist is used to filter peer connection requests. + */ ADV_POLICY_FILTER_CONN_REQS = 2, + + /** + * The whitelist is used to filter peer scan and connection requests. + */ ADV_POLICY_FILTER_ALL_REQS = 3, }; /** - * Enumeration for whitelist scanning policy filter modes. The possible - * filter modes were obtained from the Bluetooth Core Specification - * 4.2 (Vol. 6), Part B, Section 4.3.3. + * Scanning policy filter mode. * - * @experimental + * @see Bluetooth Core Specification 4.2 (Vol. 6), Part B, Section 4.3.3. */ enum ScanningPolicyMode_t { + /** + * The whitelist is not used for scanning operations. + */ SCAN_POLICY_IGNORE_WHITELIST = 0, - SCAN_POLICY_FILTER_ALL_ADV = 1, + + /** + * The whitelist is used to filter incoming advertising. + */ + SCAN_POLICY_FILTER_ALL_ADV = 1, }; /** - * Enumeration for the whitelist initiator policy fiter modes. The possible - * filter modes were obtained from the Bluetooth Core Specification - * 4.2 (vol. 6), Part B, Section 4.4.4. + * Connection initiation policy filter mode. * - * @experimental + * @see Bluetooth Core Specification 4.2 (vol. 6), Part B, Section 4.4.4. */ enum InitiatorPolicyMode_t { + /** + * Connection can be initiated to any device. + */ INIT_POLICY_IGNORE_WHITELIST = 0, - INIT_POLICY_FILTER_ALL_ADV = 1, + + /** + * Connection initiation is restricted to the devices present in the + * whitelist. + */ + INIT_POLICY_FILTER_ALL_ADV = 1, }; /** - * Representation of a Bluetooth Low Enery Whitelist containing addresses. - * - * @experimental + * Representation of a whitelist of addresses. */ struct Whitelist_t { - BLEProtocol::Address_t *addresses; /**< List of BLE addresses in the whitelist. */ - uint8_t size; /**< Total number of BLE addresses in this whitelist */ - uint8_t capacity; /**< Maximum number of BLE addresses that can be added to this whitelist. */ - }; + /** + * Pointer to the array of the addresses composing the whitelist. + */ + BLEProtocol::Address_t *addresses; + + /** + * Number addresses in this whitelist. + */ + uint8_t size; + /** + * Capacity of the array holding the addresses. + */ + uint8_t capacity; + }; /** - * Describes the current state of the device (more than one bit can be set). + * Description of the states of the device. */ struct GapState_t { - unsigned advertising : 1; /**< Peripheral is currently advertising. */ - unsigned connected : 1; /**< Peripheral is connected to a central. */ + /** + * If set, the device is currently advertising. + */ + unsigned advertising : 1; + + /** + * If set, the device is connected to at least one other peer. + */ + unsigned connected : 1; }; /** - * Type for connection handle. + * Opaque value type representing a connection handle. + * + * It is used to identify to refer to a specific connection across Gap, + * GattClient and GattEvent API. + * + * @note instances are generated by in the connection callback. */ typedef ble::connection_handle_t Handle_t; /** - * Structure containing GAP connection parameters. When in peripheral role - * the connection parameters are suggestions. The choice of the connection - * parameters is eventually up to the central. + * Parameters of a BLE connection. */ typedef struct { - uint16_t minConnectionInterval; /**< Minimum Connection Interval in 1.25 ms units, see BLE_GAP_CP_LIMITS.*/ - uint16_t maxConnectionInterval; /**< Maximum Connection Interval in 1.25 ms units, see BLE_GAP_CP_LIMITS.*/ - uint16_t slaveLatency; /**< Slave Latency in number of connection events, see BLE_GAP_CP_LIMITS.*/ - uint16_t connectionSupervisionTimeout; /**< Connection Supervision Timeout in 10 ms units, see BLE_GAP_CP_LIMITS.*/ + /** + * Minimum interval between two connection events allowed for a + * connection. + * + * It shall be less than or equal to maxConnectionInterval. This value, + * in units of 1.25ms, is included in the range [0x0006 : 0x0C80]. + */ + uint16_t minConnectionInterval; + + /** + * Maximum interval between two connection events allowed for a + * connection. + * + * It shall be greater than or equal to minConnectionInterval. This + * value is in unit of 1.25ms and is in the range [0x0006 : 0x0C80]. + */ + uint16_t maxConnectionInterval; + + /** + * Number of connection events the slave can drop if it has nothing to + * communicate to the master. + * + * This value shall be in the range [0x0000 : 0x01F3]. + */ + uint16_t slaveLatency; + + /** + * Link supervision timeout for the connection. + * + * Time after which the connection is considered lost if the device + * didn't receive a packet from its peer. + * + * It is larger than: + * (1 + slaveLatency) * maxConnectionInterval * 2 + * + * This value is in the range [0x000A : 0x0C80] and is in unit of + * 10 ms. + * + * @note maxConnectionInterval is in ms in the formulae above. + */ + uint16_t connectionSupervisionTimeout; } ConnectionParams_t; /** - * Enumeration for the possible GAP roles of a BLE device. + * Enumeration of GAP roles. + * + * @note The BLE API does not express the broadcaster and scanner roles. + * + * @important A device can fulfill different roles concurrently. */ enum Role_t { - PERIPHERAL = 0x1, /**< Peripheral Role. */ - CENTRAL = 0x2, /**< Central Role. */ + /** + * Peripheral Role. + * + * The device can advertise and it can be connected by a central. It + * acts as a slave when connected. + * + * @note A peripheral is a broadcaster. + */ + PERIPHERAL = 0x1, + + /** + * Central Role. + * + * The device can scan and initiate connection to peripherals. It + * acts as the master when a connection is established. + * + * @note A central is a scanner. + */ + CENTRAL = 0x2, }; /** - * Structure containing data and metadata of a scanned advertising packet. + * Representation of a scanned advertising packet. + * + * Instances of this type are passed to the callback registered in + * startScan(). */ struct AdvertisementCallbackParams_t { - BLEProtocol::AddressBytes_t peerAddr; /**< The peer's BLE address. */ - int8_t rssi; /**< The advertisement packet RSSI value. */ - bool isScanResponse; /**< Whether this packet is the response to a scan request. */ - GapAdvertisingParams::AdvertisingType_t type; /**< The type of advertisement. */ - uint8_t advertisingDataLen; /**< Length of the advertisement data. */ - const uint8_t *advertisingData; /**< Pointer to the advertisement packet's data. */ + /** + * BLE address of the device that has advertised the packet. + */ + BLEProtocol::AddressBytes_t peerAddr; + + /** + * RSSI value of the packet. + */ + int8_t rssi; + + /** + * Flag indicating if the packet is a response to a scan request. + */ + bool isScanResponse; + + /** + * Type of advertisement. + */ + GapAdvertisingParams::AdvertisingType_t type; + + /** + * Length of the advertisement data. + */ + uint8_t advertisingDataLen; + + /** + * Pointer to the advertisement packet's data. + */ + const uint8_t *advertisingData; }; /** - * Type for the handlers of advertisement callback events. Refer to - * Gap::startScan(). + * Type of the callback handling scanned advertisement packets. + * + * @see Gap::startScan(). */ - typedef FunctionPointerWithContext AdvertisementReportCallback_t; + typedef FunctionPointerWithContext + AdvertisementReportCallback_t; /** - * Encapsulates the parameters of a connection. This information is passed - * to the registered handler of connection events. Refer to Gap::onConnection(). + * Connection events. + * + * It contains all the information related to a newly established connection. + * + * Instances of this structure are passed to handlers that + * Gap::onConnection() registers when a connection is established. */ struct ConnectionCallbackParams_t { - Handle_t handle; /**< The ID for this connection */ - Role_t role; /**< This device's role in the connection */ - BLEProtocol::AddressType_t peerAddrType; /**< The peer's BLE address type */ - BLEProtocol::AddressBytes_t peerAddr; /**< The peer's BLE address */ - BLEProtocol::AddressType_t ownAddrType; /**< This device's BLE address type */ - BLEProtocol::AddressBytes_t ownAddr; /**< This devices's BLE address */ - const ConnectionParams_t *connectionParams; /**< The currently configured connection parameters */ + /** + * Connection handle. + */ + Handle_t handle; + + /** + * Connection Role of the local device. + */ + Role_t role; + + /** + * Type of the address the peer uses. + */ + BLEProtocol::AddressType_t peerAddrType; + + /** + * Address of the peer. + */ + BLEProtocol::AddressBytes_t peerAddr; + + /** + * Address type of the local device. + */ + BLEProtocol::AddressType_t ownAddrType; + + /** + * Address of the local device. + */ + BLEProtocol::AddressBytes_t ownAddr; /** - * Constructor for ConnectionCallbackParams_t. + * Connection parameters. + */ + const ConnectionParams_t *connectionParams; + + /** + * Construct an instance of ConnectionCallbackParams_t. + * + * @param[in] handleIn Value to assign to handle. + * @param[in] roleIn Value to assign to role. + * @param[in] peerAddrTypeIn Value to assign to peerAddrType. + * @param[in] peerAddrIn Value to assign to peerAddr. + * @param[in] ownAddrTypeIn Value to assign to ownAddrType. + * @param[in] ownAddrIn Value to assign to ownAddr. + * @param[in] connectionParamsIn Value to assign to connectionParams. * - * @param[in] handleIn - * Value for ConnectionCallbackParams_t::handle - * @param[in] roleIn - * Value for ConnectionCallbackParams_t::role - * @param[in] peerAddrTypeIn - * Value for ConnectionCallbackParams_t::peerAddrType - * @param[in] peerAddrIn - * Value for ConnectionCallbackParams_t::peerAddr - * @param[in] ownAddrTypeIn - * Value for ConnectionCallbackParams_t::ownAddrType - * @param[in] ownAddrIn - * Value for ConnectionCallbackParams_t::ownAddr - * @param[in] connectionParamsIn - * Value for ConnectionCallbackParams_t::connectionParams + * @note Constructor is not meant to be called by user code. + * The BLE API vendor code generates ConnectionCallbackParams_t. */ - ConnectionCallbackParams_t(Handle_t handleIn, - Role_t roleIn, - BLEProtocol::AddressType_t peerAddrTypeIn, - const uint8_t *peerAddrIn, - BLEProtocol::AddressType_t ownAddrTypeIn, - const uint8_t *ownAddrIn, - const ConnectionParams_t *connectionParamsIn) : - handle(handleIn), + ConnectionCallbackParams_t( + Handle_t handleIn, + Role_t roleIn, + BLEProtocol::AddressType_t peerAddrTypeIn, + const uint8_t *peerAddrIn, + BLEProtocol::AddressType_t ownAddrTypeIn, + const uint8_t *ownAddrIn, + const ConnectionParams_t *connectionParamsIn + ) : handle(handleIn), role(roleIn), peerAddrType(peerAddrTypeIn), peerAddr(), ownAddrType(ownAddrTypeIn), ownAddr(), - connectionParams(connectionParamsIn) { + connectionParams(connectionParamsIn) + { memcpy(peerAddr, peerAddrIn, ADDR_LEN); memcpy(ownAddr, ownAddrIn, ADDR_LEN); } }; /** - * Structure that encapsulates information about a disconnection event. - * Refer to Gap::onDisconnection(). + * Disconnection event. + * + * Instances of this event are passed to callbacks registered with + * Gap::onDisconnection() when a connection ends. + * + * @note Constructor is not meant to be called by user code. + * The BLE API vendor code generates ConnectionCallbackParams_t. */ struct DisconnectionCallbackParams_t { - Handle_t handle; /**< The ID of the connection that caused the disconnection event */ - DisconnectionReason_t reason; /**< The reason of the disconnection event */ + /** + * ID of the connection that has ended. + */ + Handle_t handle; + + /** + * Reason of the disconnection. + */ + DisconnectionReason_t reason; /** - * Constructor for DisconnectionCallbackParams_t. + * Construct a DisconnectionCallbackParams_t. * - * @param[in] handleIn - * Value for DisconnectionCallbackParams_t::handle. - * @param[in] reasonIn - * Value for DisconnectionCallbackParams_t::reason. + * @param[in] handleIn Value assigned to handle. + * @param[in] reasonIn Value assigned to reason. */ - DisconnectionCallbackParams_t(Handle_t handleIn, - DisconnectionReason_t reasonIn) : - handle(handleIn), + DisconnectionCallbackParams_t( + Handle_t handleIn, + DisconnectionReason_t reasonIn + ) : handle(handleIn), reason(reasonIn) {} }; - static const uint16_t UNIT_1_25_MS = 1250; /**< Number of microseconds in 1.25 milliseconds. */ /** - * Helper function to convert from units of milliseconds to GAP duration - * units. + * Number of microseconds in 1.25 milliseconds. + */ + static const uint16_t UNIT_1_25_MS = 1250; + + /** + * Convert milliseconds into 1.25ms units. + * + * This function may be used to convert ms time of connection intervals into + * the format expected for connection parameters. * - * @param[in] durationInMillis - * The duration in milliseconds. + * @param[in] durationInMillis The duration in milliseconds. * - * @return The duration in GAP duration units. + * @return The duration in unit of 1.25ms. */ - static uint16_t MSEC_TO_GAP_DURATION_UNITS(uint32_t durationInMillis) { + static uint16_t MSEC_TO_GAP_DURATION_UNITS(uint32_t durationInMillis) + { return (durationInMillis * 1000) / UNIT_1_25_MS; } /** - * Type for the registered callbacks added to the timeout event callchain. - * Refer to Gap::onTimeout(). + * Timeout event handler. + * + * @see Gap::onTimeout(). */ typedef FunctionPointerWithContext TimeoutEventCallback_t; + /** - * Type for the timeout event callchain. Refer to Gap::onTimeout(). + * Callchain of timeout event handlers. + * + * @see Gap::onTimeout(). */ - typedef CallChainOfFunctionPointersWithContext TimeoutEventCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + TimeoutEventCallbackChain_t; /** - * Type for the registered callbacks added to the connection event - * callchain. Refer to Gap::onConnection(). + * Connection event handler. + * + * @see Gap::onConnection(). */ - typedef FunctionPointerWithContext ConnectionEventCallback_t; + typedef FunctionPointerWithContext + ConnectionEventCallback_t; + /** - * Type for the connection event callchain. Refer to Gap::onConnection(). + * Callchain of connection event handlers. + * + * @see Gap::onConnection(). */ - typedef CallChainOfFunctionPointersWithContext ConnectionEventCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + ConnectionEventCallbackChain_t; /** - * Type for the registered callbacks added to the disconnection event - * callchain. Refer to Gap::onDisconnection(). + * Disconnection event handler. + * + * @see Gap::onDisconnection(). */ - typedef FunctionPointerWithContext DisconnectionEventCallback_t; + typedef FunctionPointerWithContext + DisconnectionEventCallback_t; + /** - * Type for the disconnection event callchain. Refer to Gap::onDisconnection(). + * Callchain of disconnection event handlers. + * + * @see Gap::onDisconnection(). */ - typedef CallChainOfFunctionPointersWithContext DisconnectionEventCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + DisconnectionEventCallbackChain_t; /** - * Type for the handlers of radio notification callback events. Refer to - * Gap::onRadioNotification(). + * Radio notification event handler. + * + * @see Gap::onRadioNotification(). */ typedef FunctionPointerWithContext RadioNotificationEventCallback_t; /** - * Type for the handlers of shutdown callback events. Refer to - * Gap::onShutdown(). + * Gap shutdown event handler. + * + * @see Gap::onShutdown(). */ typedef FunctionPointerWithContext GapShutdownCallback_t; + /** - * Type for the shutdown event callchain. Refer to Gap::onShutdown(). + * Callchain of gap shutdown event handler. + * + * @see Gap::onShutdown(). */ - typedef CallChainOfFunctionPointersWithContext GapShutdownCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + GapShutdownCallbackChain_t; /* - * The following functions are meant to be overridden in the platform-specific sub-class. + * The following functions are meant to be overridden in the platform-specific subclass. */ public: /** - * Set the BTLE MAC address and type. Please note that the address format is - * least significant byte first (LSB). Please refer to BLEProtocol::AddressBytes_t. + * Set the device MAC address and type. + * + * The address set is used in subsequent GAP operations: scanning, + * advertising and connection initiation. + * + * @param[in] type Type of the address to set. + * @param[in] address Value of the address to set. It is ordered in + * little endian. This parameter is not considered if the address type + * is RANDOM_PRIVATE_RESOLVABLE or RANDOM_PRIVATE_NON_RESOLVABLE. For those + * types of address, the BLE API itself generates the address. * - * @param[in] type - * The type of the BLE address to set. - * @param[in] address - * The BLE address to set. + * @note Some implementation may refuse to set a new PUBLIC address. + * @note Random static address set does not change. * * @return BLE_ERROR_NONE on success. */ - virtual ble_error_t setAddress(BLEProtocol::AddressType_t type, const BLEProtocol::AddressBytes_t address) { + virtual ble_error_t setAddress( + BLEProtocol::AddressType_t type, + const BLEProtocol::AddressBytes_t address + ) { /* avoid compiler warnings about unused variables */ (void)type; (void)address; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Fetch the BTLE MAC address and type. + * Fetch the current address and its type. * - * @param[out] typeP - * The current BLE address type. - * @param[out] address - * The current BLE address. + * @param[out] typeP Type of the current address set. + * @param[out] address Value of the current address. * * @return BLE_ERROR_NONE on success. */ - virtual ble_error_t getAddress(BLEProtocol::AddressType_t *typeP, BLEProtocol::AddressBytes_t address) { + virtual ble_error_t getAddress( + BLEProtocol::AddressType_t *typeP, + BLEProtocol::AddressBytes_t address + ) { /* Avoid compiler warnings about unused variables. */ (void)typeP; (void)address; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Get the minimum advertising interval in milliseconds for connectable - * undirected and connectable directed event types supported by the - * underlying BLE stack. + * Get the minimum advertising interval in milliseconds, which can be used + * for connectable advertising types. * * @return Minimum Advertising interval in milliseconds for connectable - * undirected and connectable directed event types. + * undirected and connectable directed advertising types. */ - virtual uint16_t getMinAdvertisingInterval(void) const { - return 0; /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual uint16_t getMinAdvertisingInterval(void) const + { + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return 0; } /** - * Get the minimum advertising interval in milliseconds for scannable - * undirected and non-connectable undirected even types supported by the - * underlying BLE stack. + * Get the minimum advertising interval in milliseconds, which can be + * used for nonconnectable advertising type. * * @return Minimum Advertising interval in milliseconds for scannable - * undirected and non-connectable undirected event types. + * undirected and nonconnectable undirected event types. */ - virtual uint16_t getMinNonConnectableAdvertisingInterval(void) const { - return 0; /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual uint16_t getMinNonConnectableAdvertisingInterval(void) const + { + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return 0; } /** - * Get the maximum advertising interval in milliseconds for all event types - * supported by the underlying BLE stack. + * Get the maximum advertising interval in milliseconds. * * @return Maximum Advertising interval in milliseconds. */ - virtual uint16_t getMaxAdvertisingInterval(void) const { - return 0xFFFF; /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual uint16_t getMaxAdvertisingInterval(void) const + { + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return 0xFFFF; } /** - * Stop advertising. The current advertising parameters remain in effect. + * Stop the ongoing advertising procedure. * - * @retval BLE_ERROR_NONE if successfully stopped advertising procedure. + * @note The current advertising parameters remain in effect. + * + * @retval BLE_ERROR_NONE if the advertising procedure has been successfully + * stopped. */ - virtual ble_error_t stopAdvertising(void) { - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual ble_error_t stopAdvertising(void) + { + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Stop scanning. The current scanning parameters remain in effect. + * Stop the ongoing scanning procedure. + * + * The current scanning parameters remain in effect. * * @retval BLE_ERROR_NONE if successfully stopped scanning procedure. */ - virtual ble_error_t stopScan() { - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual ble_error_t stopScan() + { + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Create a connection (GAP Link Establishment). + * Initiate a connection to a peer. * - * @param[in] peerAddr - * 48-bit address, LSB format. - * @param[in] peerAddrType - * Address type of the peer. - * @param[in] connectionParams - * Connection parameters. - * @param[in] scanParams - * Parameters to be used while scanning for the peer. + * Once the connection is established, a ConnectionCallbackParams_t event is + * emitted to handlers that have been registered with onConnection(). * - * @return BLE_ERROR_NONE if connection establishment procedure is started - * successfully. The connectionCallChain (if set) will be invoked upon - * a connection event. + * @param[in] peerAddr MAC address of the peer. It must be in LSB format. + * @param[in] peerAddrType Address type of the peer. + * @param[in] connectionParams Connection parameters to use. + * @param[in] scanParams Scan parameters used to find the peer. + * + * @return BLE_ERROR_NONE if connection establishment procedure is started + * successfully. The connectionCallChain (if set) is invoked upon + * a connection event. */ - virtual ble_error_t connect(const BLEProtocol::AddressBytes_t peerAddr, - BLEProtocol::AddressType_t peerAddrType, - const ConnectionParams_t *connectionParams, - const GapScanningParams *scanParams) { + virtual ble_error_t connect( + const BLEProtocol::AddressBytes_t peerAddr, + BLEProtocol::AddressType_t peerAddrType, + const ConnectionParams_t *connectionParams, + const GapScanningParams *scanParams + ) { /* Avoid compiler warnings about unused variables. */ (void)peerAddr; (void)peerAddrType; (void)connectionParams; (void)scanParams; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Create a connection (GAP Link Establishment). + * Initiate a connection to a peer. + * + * @see connect() * - * @deprecated This funtion overloads Gap::connect(const BLEProtocol::Address_t peerAddr, - * BLEProtocol::AddressType_t peerAddrType, - * const ConnectionParams_t *connectionParams, - * const GapScanningParams *scanParams) - * to maintain backward compatibility for change from Gap::AddressType_t to - * BLEProtocol::AddressType_t. + * @deprecated This funtion overloads Gap::connect( + * const BLEProtocol::Address_t peerAddr, + * BLEProtocol::AddressType_t peerAddrType, + * const ConnectionParams_t *connectionParams, + * const GapScanningParams *scanParams + * ) + * to maintain backward compatibility for changes from Gap::AddressType_t to + * BLEProtocol::AddressType_t. */ - ble_error_t connect(const BLEProtocol::AddressBytes_t peerAddr, - DeprecatedAddressType_t peerAddrType, - const ConnectionParams_t *connectionParams, - const GapScanningParams *scanParams) - __deprecated_message("Gap::DeprecatedAddressType_t is deprecated, use BLEProtocol::AddressType_t instead") { - return connect(peerAddr, (BLEProtocol::AddressType_t) peerAddrType, connectionParams, scanParams); + MBED_DEPRECATED("Gap::DeprecatedAddressType_t is deprecated, use BLEProtocol::AddressType_t instead") + ble_error_t connect( + const BLEProtocol::AddressBytes_t peerAddr, + DeprecatedAddressType_t peerAddrType, + const ConnectionParams_t *connectionParams, + const GapScanningParams *scanParams + ) { + return connect( + peerAddr, + (BLEProtocol::AddressType_t) + peerAddrType, + connectionParams, + scanParams + ); } /** - * This call initiates the disconnection procedure, and its completion will - * be communicated to the application with an invocation of the - * disconnectionCallback. + * Initiate a disconnection procedure. * - * @param[in] reason - * The reason for disconnection; to be sent back to the peer. - * @param[in] connectionHandle - * The handle of the connection to disconnect from. + * Once the disconnection procedure has completed a + * DisconnectionCallbackParams_t, the event is emitted to handlers that + * have been registered with onDisconnection(). * - * @return BLE_ERROR_NONE if disconnection was successful. + * @param[in] reason Reason of the disconnection transmitted to the peer. + * @param[in] connectionHandle Handle of the connection to end. + * + * @return BLE_ERROR_NONE if the disconnection procedure successfully + * started. */ - virtual ble_error_t disconnect(Handle_t connectionHandle, DisconnectionReason_t reason) { + virtual ble_error_t disconnect( + Handle_t connectionHandle, DisconnectionReason_t reason + ) { /* avoid compiler warnings about unused variables */ (void)connectionHandle; (void)reason; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * This call initiates the disconnection procedure, and its completion will - * be communicated to the application with an invocation of the - * disconnectionCallback. + * Initiate a disconnection procedure. * - * @param[in] reason - * The reason for disconnection; to be sent back to the peer. + * @deprecated This version of disconnect() doesn't take a connection handle. + * It works reliably only for stacks that are limited to a single connection. + * Use Gap::disconnect(Handle_t connectionHandle, DisconnectionReason_t reason) + * instead. * - * @return BLE_ERROR_NONE if disconnection was successful. + * @param[in] reason The reason for disconnection; to be sent back to the peer. * - * @deprecated This version of disconnect() doesn't take a connection handle. It - * works reliably only for stacks that are limited to a single - * connection. Use Gap::disconnect(Handle_t connectionHandle, - * DisconnectionReason_t reason) instead. + * @return BLE_ERROR_NONE if disconnection was successful. */ + MBED_DEPRECATED("Use disconnect(Handle_t, DisconnectionReason_t) instead.") virtual ble_error_t disconnect(DisconnectionReason_t reason) { /* Avoid compiler warnings about unused variables. */ (void)reason; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Get the GAP peripheral preferred connection parameters. These are the - * defaults that the peripheral would like to have in a connection. The - * choice of the connection parameters is eventually up to the central. + * Returned the preferred connection parameters exposed in the GATT Generic + * Access Service. * - * @param[out] params - * The structure where the parameters will be stored. Memory - * for this is owned by the caller. + * @param[out] params Structure where the parameters are stored. * * @return BLE_ERROR_NONE if the parameters were successfully filled into - * the given structure pointed to by params. + * @p params. */ - virtual ble_error_t getPreferredConnectionParams(ConnectionParams_t *params) { + virtual ble_error_t getPreferredConnectionParams(ConnectionParams_t *params) + { /* Avoid compiler warnings about unused variables. */ (void)params; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Set the GAP peripheral preferred connection parameters. These are the - * defaults that the peripheral would like to have in a connection. The - * choice of the connection parameters is eventually up to the central. + * Set the value of the preferred connection parameters exposed in the GATT + * Generic Access Service. + * + * A connected peer may read the characteristic exposing these parameters + * and request an update of the connection parameters to accomodate the + * local device. * - * @param[in] params - * The structure containing the desired parameters. + * @param[in] params Value of the preferred connection parameters. * * @return BLE_ERROR_NONE if the preferred connection params were set - * correctly. + * correctly. */ - virtual ble_error_t setPreferredConnectionParams(const ConnectionParams_t *params) { + virtual ble_error_t setPreferredConnectionParams( + const ConnectionParams_t *params + ) { /* Avoid compiler warnings about unused variables. */ (void)params; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Update connection parameters. In the central role this will initiate a - * Link Layer connection parameter update procedure. In the peripheral role, - * this will send the corresponding L2CAP request and wait for the central - * to perform the procedure. + * Update connection parameters of an existing connection. + * + * In the central role, this initiates a Link Layer connection parameter + * update procedure. In the peripheral role, this sends the corresponding + * L2CAP request and waits for the central to perform the procedure. * - * @param[in] handle - * Connection Handle. - * @param[in] params - * Pointer to desired connection parameters. If NULL is provided on a peripheral role, - * the parameters in the PPCP characteristic of the GAP service will be used instead. + * @param[in] handle Connection Handle. + * @param[in] params Pointer to desired connection parameters. * * @return BLE_ERROR_NONE if the connection parameters were updated correctly. */ - virtual ble_error_t updateConnectionParams(Handle_t handle, const ConnectionParams_t *params) { + virtual ble_error_t updateConnectionParams( + Handle_t handle, + const ConnectionParams_t *params + ) { /* avoid compiler warnings about unused variables */ (void)handle; (void)params; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Set the device name characteristic in the GAP service. + * Set the value of the device name characteristic in the Generic Access + * Service. * - * @param[in] deviceName - * The new value for the device-name. This is a UTF-8 encoded, NULL-terminated string. + * @param[in] deviceName The new value for the device-name. This is a + * UTF-8 encoded, NULL-terminated string. * * @return BLE_ERROR_NONE if the device name was set correctly. */ @@ -598,100 +1134,113 @@ class Gap { /* Avoid compiler warnings about unused variables. */ (void)deviceName; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Get the value of the device name characteristic in the GAP service. + * Get the value of the device name characteristic in the Generic Access + * Service. + * + * To obtain the length of the deviceName value, this function is + * invoked with the @p deviceName parameter set to NULL. * - * @param[out] deviceName - * Pointer to an empty buffer where the UTF-8 *non NULL- - * terminated* string will be placed. Set this - * value to NULL in order to obtain the deviceName-length - * from the 'length' parameter. + * @param[out] deviceName Pointer to an empty buffer where the UTF-8 + * non NULL-terminated string is placed. * - * @param[in,out] lengthP - * (on input) Length of the buffer pointed to by deviceName; - * (on output) the complete device name length (without the - * null terminator). + * @param[in,out] lengthP Length of the @p deviceName buffer. If the device + * name is successfully copied, then the length of the device name + * string (excluding the null terminator) replaces this value. * * @return BLE_ERROR_NONE if the device name was fetched correctly from the - * underlying BLE stack. + * underlying BLE stack. * * @note If the device name is longer than the size of the supplied buffer, - * length will return the complete device name length, and not the - * number of bytes actually returned in deviceName. The application may - * use this information to retry with a suitable buffer size. + * length returns the complete device name length and not the number of + * bytes actually returned in deviceName. The application may use this + * information to retry with a suitable buffer size. */ - virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP) { + virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP) + { /* avoid compiler warnings about unused variables */ (void)deviceName; (void)lengthP; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Set the appearance characteristic in the GAP service. + * Set the value of the appearance characteristic in the GAP service. * - * @param[in] appearance - * The new value for the device-appearance. + * @param[in] appearance The new value for the device-appearance. * * @return BLE_ERROR_NONE if the new appearance was set correctly. */ - virtual ble_error_t setAppearance(GapAdvertisingData::Appearance appearance) { + virtual ble_error_t setAppearance(GapAdvertisingData::Appearance appearance) + { /* Avoid compiler warnings about unused variables. */ (void)appearance; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Get the appearance characteristic in the GAP service. + * Get the value of the appearance characteristic in the GAP service. * - * @param[out] appearance - * The current device-appearance value. + * @param[out] appearance The current device-appearance value. * * @return BLE_ERROR_NONE if the device-appearance was fetched correctly - * from the underlying BLE stack. + * from the underlying BLE stack. */ - virtual ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP) { + virtual ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP) + { /* Avoid compiler warnings about unused variables. */ (void)appearanceP; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** * Set the radio's transmit power. * - * @param[in] txPower - * Radio's transmit power in dBm. + * @param[in] txPower Radio's transmit power in dBm. * * @return BLE_ERROR_NONE if the new radio's transmit power was set - * correctly. + * correctly. */ - virtual ble_error_t setTxPower(int8_t txPower) { + virtual ble_error_t setTxPower(int8_t txPower) + { /* Avoid compiler warnings about unused variables. */ (void)txPower; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Query the underlying stack for permitted arguments for setTxPower(). + * Query the underlying stack for allowed Tx power values. * - * @param[out] valueArrayPP - * Out parameter to receive the immutable array of Tx values. - * @param[out] countP - * Out parameter to receive the array's size. + * @param[out] valueArrayPP Receive the immutable array of Tx values. + * @param[out] countP Receive the array's size. */ - virtual void getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP) { + virtual void getPermittedTxPowerValues( + const int8_t **valueArrayPP, size_t *countP + ) { /* Avoid compiler warnings about unused variables. */ (void)valueArrayPP; (void)countP; - *countP = 0; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + *countP = 0; } /** @@ -699,11 +1248,8 @@ class Gap { * * @return Maximum size of the whitelist. * - * @note If using mbed OS the size of the whitelist can be configured by - * setting the YOTTA_CFG_WHITELIST_MAX_SIZE macro in your yotta - * config file. - * - * @experimental + * @note If using Mbed OS, you can configure the size of the whitelist by + * setting the YOTTA_CFG_WHITELIST_MAX_SIZE macro in your yotta config file. */ virtual uint8_t getMaxWhitelistSize(void) const { @@ -711,17 +1257,14 @@ class Gap { } /** - * Get the internal whitelist to be used by the Link Layer when scanning, + * Get the Link Layer to use the internal whitelist when scanning, * advertising or initiating a connection depending on the filter policies. * - * @param[in,out] whitelist - * (on input) whitelist.capacity contains the maximum number - * of addresses to be returned. - * (on output) The populated whitelist with copies of the - * addresses in the implementation's whitelist. + * @param[in,out] whitelist Define the whitelist instance which is used + * to store the whitelist requested. In input, the caller provisions memory. * * @return BLE_ERROR_NONE if the implementation's whitelist was successfully - * copied into the supplied reference. + * copied into the supplied reference. * * @experimental */ @@ -732,25 +1275,22 @@ class Gap { } /** - * Set the internal whitelist to be used by the Link Layer when scanning, - * advertising or initiating a connection depending on the filter policies. + * Set the value of the whitelist to be used during GAP procedures. * - * @param[in] whitelist - * A reference to a whitelist containing the addresses to - * be added to the internal whitelist. + * @param[in] whitelist A reference to a whitelist containing the addresses + * to be copied to the internal whitelist. * * @return BLE_ERROR_NONE if the implementation's whitelist was successfully - * populated with the addresses in the given whitelist. + * populated with the addresses in the given whitelist. * * @note The whitelist must not contain addresses of type @ref - * BLEProtocol::AddressType_t::RANDOM_PRIVATE_NON_RESOLVABLE, this - * this will result in a @ref BLE_ERROR_INVALID_PARAM since the - * remote peer might change its private address at any time and it - * is not possible to resolve it. - * @note If the input whitelist is larger than @ref getMaxWhitelistSize() - * the @ref BLE_ERROR_PARAM_OUT_OF_RANGE is returned. + * BLEProtocol::AddressType_t::RANDOM_PRIVATE_NON_RESOLVABLE. This + * results in a @ref BLE_ERROR_INVALID_PARAM because the remote peer might + * change its private address at any time, and it is not possible to resolve + * it. * - * @experimental + * @note If the input whitelist is larger than @ref getMaxWhitelistSize(), + * then @ref BLE_ERROR_PARAM_OUT_OF_RANGE is returned. */ virtual ble_error_t setWhitelist(const Whitelist_t &whitelist) { @@ -759,16 +1299,13 @@ class Gap { } /** - * Set the advertising policy filter mode to be used in the next call - * to startAdvertising(). + * Set the advertising policy filter mode to be used during the next + * advertising procedure. * - * @param[in] mode - * The new advertising policy filter mode. + * @param[in] mode New advertising policy filter mode. * * @return BLE_ERROR_NONE if the specified policy filter mode was set - * successfully. - * - * @experimental + * successfully. */ virtual ble_error_t setAdvertisingPolicyMode(AdvertisingPolicyMode_t mode) { @@ -777,16 +1314,12 @@ class Gap { } /** - * Set the scan policy filter mode to be used in the next call - * to startScan(). + * Set the scan policy filter mode to be used during the next scan procedure. * - * @param[in] mode - * The new scan policy filter mode. + * @param[in] mode New scan policy filter mode. * * @return BLE_ERROR_NONE if the specified policy filter mode was set - * successfully. - * - * @experimental + * successfully. */ virtual ble_error_t setScanningPolicyMode(ScanningPolicyMode_t mode) { @@ -795,15 +1328,13 @@ class Gap { } /** - * Set the initiator policy filter mode to be used. + * Set the initiator policy filter mode to be used during the next connection + * initiation. * - * @param[in] mode - * The new initiator policy filter mode. + * @param[in] mode New initiator policy filter mode. * * @return BLE_ERROR_NONE if the specified policy filter mode was set - * successfully. - * - * @experimental + * successfully. */ virtual ble_error_t setInitiatorPolicyMode(InitiatorPolicyMode_t mode) { @@ -812,12 +1343,9 @@ class Gap { } /** - * Get the advertising policy filter mode that will be used in the next - * call to startAdvertising(). + * Get the current advertising policy filter mode. * - * @return The set advertising policy filter mode. - * - * @experimental + * @return The current advertising policy filter mode. */ virtual AdvertisingPolicyMode_t getAdvertisingPolicyMode(void) const { @@ -825,12 +1353,9 @@ class Gap { } /** - * Get the scan policy filter mode that will be used in the next - * call to startScan(). - * - * @return The set scan policy filter mode. + * Get the current scan policy filter mode. * - * @experimental + * @return The current scan policy filter mode. */ virtual ScanningPolicyMode_t getScanningPolicyMode(void) const { @@ -838,11 +1363,9 @@ class Gap { } /** - * Get the initiator policy filter mode that will be used. - * - * @return The set scan policy filter mode. + * Get the current initiator policy filter mode. * - * @experimental + * @return The current scan policy filter mode. */ virtual InitiatorPolicyMode_t getInitiatorPolicyMode(void) const { @@ -850,69 +1373,66 @@ class Gap { } protected: - /* Override the following in the underlying adaptation layer to provide the functionality of scanning. */ + /* Override the following in the underlying adaptation layer to provide the + functionality of scanning. */ /** * Start scanning procedure in the underlying BLE stack. * - * @param[in] scanningParams - * The GAP scanning parameters. + * @param[in] scanningParams Parameters of the scan procedure. * - * @return BLE_ERROR_NONE if the scan procedure started successfully. + * @return BLE_ERROR_NONE if the scan procedure was successfully started. */ - virtual ble_error_t startRadioScan(const GapScanningParams &scanningParams) { + virtual ble_error_t startRadioScan(const GapScanningParams &scanningParams) + { (void)scanningParams; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /* - * APIs with non-virtual implementations. + * APIs with nonvirtual implementations. */ public: /** - * Get the current GAP state of the device using a bitmask that - * describes whether the device is advertising or connected. + * Get the current advertising and connection states of the device. * * @return The current GAP state of the device. */ - GapState_t getState(void) const { + GapState_t getState(void) const + { return state; } /** - * Set the GAP advertising mode to use for this device. + * Set the advertising type to use during the advertising procedure. * - * @param[in] advType - * The new type of the advertising packets. + * @param[in] advType New type of advertising to use. */ - void setAdvertisingType(GapAdvertisingParams::AdvertisingType_t advType) { + void setAdvertisingType(GapAdvertisingParams::AdvertisingType_t advType) + { _advParams.setAdvertisingType(advType); } /** * Set the advertising interval. * - * @param[in] interval - * Advertising interval in units of milliseconds. Advertising - * is disabled if interval is 0. If interval is smaller than - * the minimum supported value, then the minimum supported - * value is used instead. This minimum value can be discovered - * using getMinAdvertisingInterval(). - * - * This field must be set to 0 if connectionMode is equal - * to ADV_CONNECTABLE_DIRECTED. + * @param[in] interval Advertising interval in units of milliseconds. + * Advertising is disabled if interval is 0. If interval is smaller than + * the minimum supported value, then the minimum supported value is used + * instead. This minimum value can be discovered using + * getMinAdvertisingInterval(). * - * @note Decreasing this value will allow central devices to detect a - * peripheral faster, at the expense of more power being used by the radio - * due to the higher data transmit rate. + * This field must be set to 0 if connectionMode is equal + * to ADV_CONNECTABLE_DIRECTED. * - * @note [WARNING] This API previously used 0.625ms as the unit for its - * @p interval argument. That required an explicit conversion from - * milliseconds using Gap::MSEC_TO_GAP_DURATION_UNITS(). This conversion is - * no longer required as the new units are milliseconds. Any application - * code depending on the old semantics needs to be updated accordingly. + * @note Decreasing this value allows central devices to detect a + * peripheral faster, at the expense of the radio using more power + * due to the higher data transmit rate. */ - void setAdvertisingInterval(uint16_t interval) { + void setAdvertisingInterval(uint16_t interval) + { if (interval == 0) { stopAdvertising(); } else if (interval < getMinAdvertisingInterval()) { @@ -922,23 +1442,25 @@ class Gap { } /** - * Set the advertising timeout. The length of time to advertise for before - * a timeout event is generated. + * Set the advertising duration. * - * @param[in] timeout - * Advertising timeout (in seconds) between 0x1 and 0x3FFF (1 - * and 16383). Use 0 to disable the advertising timeout. + * A timeout event is genenerated once the advertising period expired. + * + * @param[in] timeout Advertising timeout (in seconds) between 0x1 and 0x3FFF. + * The special value 0 may be used to disable the advertising timeout. */ - void setAdvertisingTimeout(uint16_t timeout) { + void setAdvertisingTimeout(uint16_t timeout) + { _advParams.setTimeout(timeout); } /** - * Start advertising. + * Start the advertising procedure. * * @return BLE_ERROR_NONE if the device started advertising successfully. */ - ble_error_t startAdvertising(void) { + ble_error_t startAdvertising(void) + { ble_error_t rc; if ((rc = startAdvertising(_advParams)) == BLE_ERROR_NONE) { state.advertising = 1; @@ -947,30 +1469,34 @@ class Gap { } /** - * Reset any advertising payload prepared from prior calls to - * accumulateAdvertisingPayload(). This automatically propagates the re- - * initialized advertising payload to the underlying stack. + * Reset the value of the advertising payload advertised. */ - void clearAdvertisingPayload(void) { + void clearAdvertisingPayload(void) + { _advPayload.clear(); setAdvertisingData(_advPayload, _scanResponse); } /** - * Accumulate an AD structure in the advertising payload. Please note that - * the payload is limited to 31 bytes. The SCAN_RESPONSE message may be used - * as an additional 31 bytes if the advertising payload is too - * small. + * Set gap flags in the advertising payload. + * + * A call to this function is equivalent to: + * + * @code + * Gap ⪆ * - * @param[in] flags - * The flags to be added. Please refer to - * GapAdvertisingData::Flags for valid flags. Multiple - * flags may be specified in combination. + * GapAdvertisingData payload = gap.getAdvertisingPayload(); + * payload.addFlags(flags); + * gap.setAdvertisingPayload(payload); + * @endcode + * + * @param[in] flags The flags to be added. * * @return BLE_ERROR_NONE if the data was successfully added to the - * advertising payload. + * advertising payload. */ - ble_error_t accumulateAdvertisingPayload(uint8_t flags) { + ble_error_t accumulateAdvertisingPayload(uint8_t flags) + { GapAdvertisingData advPayloadCopy = _advPayload; ble_error_t rc; if ((rc = advPayloadCopy.addFlags(flags)) != BLE_ERROR_NONE) { @@ -986,18 +1512,25 @@ class Gap { } /** - * Accumulate an AD structure in the advertising payload. Please note that - * the payload is limited to 31 bytes. The SCAN_RESPONSE message may be used - * as an additional 31 bytes if the advertising payload is too - * small. + * Set the appearance field in the advertising payload. + * + * A call to this function is equivalent to: * - * @param[in] app - * The appearance of the peripheral. + * @code + * Gap ⪆ + * + * GapAdvertisingData payload = gap.getAdvertisingPayload(); + * payload.addAppearance(app); + * gap.setAdvertisingPayload(payload); + * @endcode + * + * @param[in] app The appearance to advertise. * * @return BLE_ERROR_NONE if the data was successfully added to the - * advertising payload. + * advertising payload. */ - ble_error_t accumulateAdvertisingPayload(GapAdvertisingData::Appearance app) { + ble_error_t accumulateAdvertisingPayload(GapAdvertisingData::Appearance app) + { GapAdvertisingData advPayloadCopy = _advPayload; ble_error_t rc; if ((rc = advPayloadCopy.addAppearance(app)) != BLE_ERROR_NONE) { @@ -1013,18 +1546,25 @@ class Gap { } /** - * Accumulate an AD structure in the advertising payload. Please note that - * the payload is limited to 31 bytes. The SCAN_RESPONSE message may be used - * as an additional 31 bytes if the advertising payload is too - * small. + * Set the Tx Power field in the advertising payload. * - * @param[in] power - * The max transmit power to be used by the controller (in dBm). + * A call to this function is equivalent to: + * + * @code + * Gap ⪆ + * + * GapAdvertisingData payload = gap.getAdvertisingPayload(); + * payload.addTxPower(power); + * gap.setAdvertisingPayload(payload); + * @endcode + * + * @param[in] power Transmit power in dBm used by the controller to advertise. * * @return BLE_ERROR_NONE if the data was successfully added to the - * advertising payload. + * advertising payload. */ - ble_error_t accumulateAdvertisingPayloadTxPower(int8_t power) { + ble_error_t accumulateAdvertisingPayloadTxPower(int8_t power) + { GapAdvertisingData advPayloadCopy = _advPayload; ble_error_t rc; if ((rc = advPayloadCopy.addTxPower(power)) != BLE_ERROR_NONE) { @@ -1040,29 +1580,34 @@ class Gap { } /** - * Accumulate a variable length byte-stream as an AD structure in the - * advertising payload. Please note that the payload is limited to 31 bytes. - * The SCAN_RESPONSE message may be used as an additional 31 bytes if the - * advertising payload is too small. + * Add a new field in the advertising payload. + * + * A call to this function is equivalent to: + * + * @code + * Gap ⪆ * - * @param[in] type - * The type describing the variable length data. - * @param[in] data - * Data bytes. - * @param[in] len - * Length of data. + * GapAdvertisingData payload = gap.getAdvertisingPayload(); + * payload.addData(type, data, len); + * gap.setAdvertisingPayload(payload); + * @endcode + * + * @param[in] type Identity of the field being added. + * @param[in] data Buffer containing the value of the field. + * @param[in] len Length of the data buffer. * * @return BLE_ERROR_NONE if the advertisement payload was updated based on - * matching AD type; otherwise, an appropriate error. + * matching AD type; otherwise, an appropriate error. * * @note When the specified AD type is INCOMPLETE_LIST_16BIT_SERVICE_IDS, - * COMPLETE_LIST_16BIT_SERVICE_IDS, INCOMPLETE_LIST_32BIT_SERVICE_IDS, - * COMPLETE_LIST_32BIT_SERVICE_IDS, INCOMPLETE_LIST_128BIT_SERVICE_IDS, - * COMPLETE_LIST_128BIT_SERVICE_IDS or LIST_128BIT_SOLICITATION_IDS the - * supplied value is appended to the values previously added to the - * payload. - */ - ble_error_t accumulateAdvertisingPayload(GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len) { + * COMPLETE_LIST_16BIT_SERVICE_IDS, INCOMPLETE_LIST_32BIT_SERVICE_IDS, + * COMPLETE_LIST_32BIT_SERVICE_IDS, INCOMPLETE_LIST_128BIT_SERVICE_IDS, + * COMPLETE_LIST_128BIT_SERVICE_IDS or LIST_128BIT_SOLICITATION_IDS the + * supplied value is appended to the values previously added to the payload. + */ + ble_error_t accumulateAdvertisingPayload( + GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len + ) { GapAdvertisingData advPayloadCopy = _advPayload; ble_error_t rc; if ((rc = advPayloadCopy.addData(type, data, len)) != BLE_ERROR_NONE) { @@ -1078,22 +1623,32 @@ class Gap { } /** - * Update a particular ADV field in the advertising payload (based on - * matching type). + * Update a particular field in the advertising payload. + * + * A call to this function is equivalent to: + * + * @code + * Gap ⪆ + * + * GapAdvertisingData payload = gap.getAdvertisingPayload(); + * payload.updateData(type, data, len); + * gap.setAdvertisingPayload(payload); + * @endcode + * * - * @param[in] type - * The ADV type field describing the variable length data. - * @param[in] data - * Data bytes. - * @param[in] len - * Length of data. + * @param[in] type Id of the field to update. + * @param[in] data data buffer containing the new value of the field. + * @param[in] len Length of the data buffer. * - * @note If advertisements are enabled, then the update will take effect immediately. + * @note If advertisements are enabled, then the update takes effect + * immediately. * * @return BLE_ERROR_NONE if the advertisement payload was updated based on - * matching AD type; otherwise, an appropriate error. + * matching AD type; otherwise, an appropriate error. */ - ble_error_t updateAdvertisingPayload(GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len) { + ble_error_t updateAdvertisingPayload( + GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len + ) { GapAdvertisingData advPayloadCopy = _advPayload; ble_error_t rc; if ((rc = advPayloadCopy.updateData(type, data, len)) != BLE_ERROR_NONE) { @@ -1109,19 +1664,16 @@ class Gap { } /** - * Set up a particular, user-constructed advertisement payload for the - * underlying stack. It would be uncommon for this API to be used directly; - * there are other APIs to build an advertisement payload (refer to - * Gap::accumulateAdvertisingPayload()). + * Set the value of the payload advertised. * - * @param[in] payload - * A reference to a user constructed advertisement - * payload. + * @param[in] payload A reference to a user constructed advertisement + * payload to set. * * @return BLE_ERROR_NONE if the advertisement payload was successfully - * set. + * set. */ - ble_error_t setAdvertisingPayload(const GapAdvertisingData &payload) { + ble_error_t setAdvertisingPayload(const GapAdvertisingData &payload) + { ble_error_t rc = setAdvertisingData(payload, _scanResponse); if (rc == BLE_ERROR_NONE) { _advPayload = payload; @@ -1131,31 +1683,28 @@ class Gap { } /** - * Get a reference to the advertising payload. - * - * @return Read back advertising data. + * Get a reference to the current advertising payload. * - * @note Useful for storing and restoring payload. + * @return A reference to the current advertising payload. */ - const GapAdvertisingData &getAdvertisingPayload(void) const { + const GapAdvertisingData &getAdvertisingPayload(void) const + { return _advPayload; } /** - * Accumulate a variable length byte-stream as an AD structure in the - * scanResponse payload. + * Add a new field in the advertising payload. * - * @param[in] type - * The type describing the variable length data. - * @param[in] data - * Data bytes. - * @param[in] len - * Length of data. + * @param[in] type AD type identifier. + * @param[in] data buffer containing AD data. + * @param[in] len Length of the data buffer. * * @return BLE_ERROR_NONE if the data was successfully added to the scan - * response payload. + * response payload. */ - ble_error_t accumulateScanResponse(GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len) { + ble_error_t accumulateScanResponse( + GapAdvertisingData::DataType type, const uint8_t *data, uint8_t len + ) { GapAdvertisingData scanResponseCopy = _scanResponse; ble_error_t rc; if ((rc = scanResponseCopy.addData(type, data, len)) != BLE_ERROR_NONE) { @@ -1171,11 +1720,10 @@ class Gap { } /** - * Reset any scan response prepared from prior calls to - * Gap::accumulateScanResponse(). + * Reset the content of the scan response. * - * @note This should be followed by a call to Gap::setAdvertisingPayload() or - * Gap::startAdvertising() before the update takes effect. + * @note This should be followed by a call to Gap::setAdvertisingPayload() + * or Gap::startAdvertising() before the update takes effect. */ void clearScanResponse(void) { _scanResponse.clear(); @@ -1183,36 +1731,43 @@ class Gap { } /** - * Set up parameters for GAP scanning (observer mode). + * Set the parameters used during a scan procedure. + * + * @param[in] interval in ms between the start of two consecutive scan windows. + * That value is greater or equal to the scan window value. The + * maximum allowed value is 10.24ms. + * + * @param[in] window Period in ms during which the scanner listens to + * advertising channels. That value is in the range 2.5ms to 10.24s. + * + * @param[in] timeout Duration in seconds of the scan procedure if any. The + * special value 0 disable specific duration of the scan procedure. * - * @param[in] interval - * Scan interval (in milliseconds) [valid values lie between 2.5ms and 10.24s]. - * @param[in] window - * Scan Window (in milliseconds) [valid values lie between 2.5ms and 10.24s]. - * @param[in] timeout - * Scan timeout (in seconds) between 0x0001 and 0xFFFF; 0x0000 disables the timeout. - * @param[in] activeScanning - * Set to True if active-scanning is required. This is used to fetch the - * scan response from a peer if possible. + * @param[in] activeScanning If set to true, then the scanner sends scan + * requests to a scannable or connectable advertiser. If set to false, then the + * scanner does not send any request during the scan procedure. * * @return BLE_ERROR_NONE if the scan parameters were correctly set. * - * @note The scanning window divided by the interval determines the duty cycle for - * scanning. For example, if the interval is 100ms and the window is 10ms, - * then the controller will scan for 10 percent of the time. It is possible - * to have the interval and window set to the same value. In this case, - * scanning is continuous, with a change of scanning frequency once every - * interval. + * @note The scanning window divided by the interval determines the duty + * cycle for scanning. For example, if the interval is 100ms and the window + * is 10ms, then the controller scans for 10 percent of the time. + * + * @note If the interval and the window are set to the same value, then the + * device scans continuously during the scan procedure. The scanning + * frequency changes at every interval. * * @note Once the scanning parameters have been configured, scanning can be - * enabled by using startScan(). + * enabled by using startScan(). * - * @note The scan interval and window are recommendations to the BLE stack. + * @note The scan interval and window are recommendations to the BLE stack. */ - ble_error_t setScanParams(uint16_t interval = GapScanningParams::SCAN_INTERVAL_MAX, - uint16_t window = GapScanningParams::SCAN_WINDOW_MAX, - uint16_t timeout = 0, - bool activeScanning = false) { + ble_error_t setScanParams( + uint16_t interval = GapScanningParams::SCAN_INTERVAL_MAX, + uint16_t window = GapScanningParams::SCAN_WINDOW_MAX, + uint16_t timeout = 0, + bool activeScanning = false + ) { ble_error_t rc; if (((rc = _scanningParams.setInterval(interval)) == BLE_ERROR_NONE) && ((rc = _scanningParams.setWindow(window)) == BLE_ERROR_NONE) && @@ -1225,49 +1780,32 @@ class Gap { } /** - * Set up the scanInterval parameter for GAP scanning (observer mode). + * Set the interval parameter used during scanning procedures. * - * @param[in] interval - * Scan interval (in milliseconds) [valid values lie between 2.5ms and 10.24s]. + * @param[in] interval Interval in ms between the start of two consecutive + * scan windows. That value is greater or equal to the scan window value. + * The maximum allowed value is 10.24ms. * * @return BLE_ERROR_NONE if the scan interval was correctly set. - * - * @note The scanning window divided by the interval determines the duty cycle for - * scanning. For example, if the interval is 100ms and the window is 10ms, - * then the controller will scan for 10 percent of the time. It is possible - * to have the interval and window set to the same value. In this case, - * scanning is continuous, with a change of scanning frequency once every - * interval. - * - * @note Once the scanning parameters have been configured, scanning can be - * enabled by using startScan(). */ - ble_error_t setScanInterval(uint16_t interval) { + ble_error_t setScanInterval(uint16_t interval) + { return _scanningParams.setInterval(interval); } /** - * Set up the scanWindow parameter for GAP scanning (observer mode). + * Set the window parameter used during scanning procedures. * - * @param[in] window - * Scan Window (in milliseconds) [valid values lie between 2.5ms and 10.24s]. + * @param[in] window Period in ms during which the scanner listens to + * advertising channels. That value is in the range 2.5ms to 10.24s. * * @return BLE_ERROR_NONE if the scan window was correctly set. * - * @note The scanning window divided by the interval determines the duty cycle for - * scanning. For example, if the interval is 100ms and the window is 10ms, - * then the controller will scan for 10 percent of the time. It is possible - * to have the interval and window set to the same value. In this case, - * scanning is continuous, with a change of scanning frequency once every - * interval. - * - * @note Once the scanning parameters have been configured, scanning can be - * enabled by using startScan(). - * - * @note If scanning is already active, the updated value of scanWindow will be - * propagated to the underlying BLE stack. + * @note If scanning is already active, the updated value of scanWindow + * is propagated to the underlying BLE stack. */ - ble_error_t setScanWindow(uint16_t window) { + ble_error_t setScanWindow(uint16_t window) + { ble_error_t rc; if ((rc = _scanningParams.setWindow(window)) != BLE_ERROR_NONE) { return rc; @@ -1282,20 +1820,18 @@ class Gap { } /** - * Set up parameters for GAP scanning (observer mode). + * Set the timeout parameter used during scanning procedures. * - * @param[in] timeout - * Scan timeout (in seconds) between 0x0001 and 0xFFFF; 0x0000 disables the timeout. + * @param[in] timeout Duration in seconds of the scan procedure if any. The + * special value 0 disables specific duration of the scan procedure. * * @return BLE_ERROR_NONE if the scan timeout was correctly set. * - * @note Once the scanning parameters have been configured, scanning can be - * enabled by using startScan(). - * - * @note If scanning is already active, the updated value of scanTimeout will be - * propagated to the underlying BLE stack. + * @note If scanning is already active, the updated value of scanTimeout + * is propagated to the underlying BLE stack. */ - ble_error_t setScanTimeout(uint16_t timeout) { + ble_error_t setScanTimeout(uint16_t timeout) + { ble_error_t rc; if ((rc = _scanningParams.setTimeout(timeout)) != BLE_ERROR_NONE) { return rc; @@ -1310,21 +1846,19 @@ class Gap { } /** - * Modify the active scanning parameter for GAP scanning (observer mode). - * This is used to fetch the scan response from a peer if possible. + * Enable or disable active scanning. * - * @param[in] activeScanning - * Set to True if active-scanning is required. + * @param[in] activeScanning If set to true, then the scanner sends scan + * requests to a scannable or connectable advertiser. If set to false then the + * scanner does not send any request during the scan procedure. * * @return BLE_ERROR_NONE if active scanning was successfully set. * - * @note Once the scanning parameters have been configured, scanning can be - * enabled by using startScan(). - * - * @note If scanning is already in progress, then active-scanning will be enabled - * for the underlying BLE stack. + * @note If scanning is already in progress, then active scanning is + * enabled for the underlying BLE stack. */ - ble_error_t setActiveScanning(bool activeScanning) { + ble_error_t setActiveScanning(bool activeScanning) + { _scanningParams.setActiveScanning(activeScanning); /* If scanning is already active, propagate the new settings to the stack. */ @@ -1336,18 +1870,22 @@ class Gap { } /** - * Start scanning (Observer Procedure) based on the parameters currently in - * effect. + * Start the scanning procedure. * - * @param[in] callback - * The application-specific callback to be invoked upon - * receiving every advertisement report. This can be passed in - * as NULL, in which case scanning may not be enabled at all. + * Packets received during the scan procedure are forwarded to the + * scan packet handler passed as argument to this function. + * + * @param[in] callback Advertisement packet event handler. Upon reception + * of an advertising packet, the packet is forwarded to @p callback. * * @return BLE_ERROR_NONE if the device successfully started the scan * procedure. + * + * @note The parameters used by the procedure are defined by setScanParams(). */ - ble_error_t startScan(void (*callback)(const AdvertisementCallbackParams_t *params)) { + ble_error_t startScan( + void (*callback)(const AdvertisementCallbackParams_t *params) + ) { ble_error_t err = BLE_ERROR_NONE; if (callback) { if ((err = startRadioScan(_scanningParams)) == BLE_ERROR_NONE) { @@ -1360,22 +1898,27 @@ class Gap { } /** - * Same as Gap::startScan(), but allows the possibility to add an object - * reference and member function as handler for advertisement event - * callbacks. + * Start the scanning procedure. + * + * Packets received during the scan procedure are forwarded to the + * scan packet handler passed as argument to this function. * - * @param[in] object - * Pointer to the object of a class defining the member callback - * function (@p callbackMember). - * @param[in] callbackMember - * The member callback (within the context of an object) to be - * invoked. + * @param[in] object Instance used to invoke @p callbackMember. + * + * @param[in] callbackMember Advertisement packet event handler. Upon + * reception of an advertising packet, the packet is forwarded to @p + * callback invoked from @p object. * * @return BLE_ERROR_NONE if the device successfully started the scan - * procedure. + * procedure. + * + * @note The parameters used by the procedure are defined by setScanParams(). */ template - ble_error_t startScan(T *object, void (T::*callbackMember)(const AdvertisementCallbackParams_t *params)) { + ble_error_t startScan( + T *object, + void (T::*callbackMember)(const AdvertisementCallbackParams_t *params) + ) { ble_error_t err = BLE_ERROR_NONE; if (object && callbackMember) { if ((err = startRadioScan(_scanningParams)) == BLE_ERROR_NONE) { @@ -1388,307 +1931,295 @@ class Gap { } /** - * Initialize radio-notification events to be generated from the stack. - * This API doesn't need to be called directly. + * Enable radio-notification events. * - * Radio Notification is a feature that enables ACTIVE and INACTIVE - * (nACTIVE) signals from the stack that notify the application when the + * Radio Notification is a feature that notifies the application when the * radio is in use. * * The ACTIVE signal is sent before the radio event starts. The nACTIVE - * signal is sent at the end of the radio event. These signals can be used - * by the application programmer to synchronize application logic with radio + * signal is sent at the end of the radio event. The application programmer can + * use these signals to synchronize application logic with radio * activity. For example, the ACTIVE signal can be used to shut off external - * devices, to manage peak current drawn during periods when the radio is on, + * devices, to manage peak current drawn during periods when the radio is on * or to trigger sensor data collection for transmission in the Radio Event. * * @return BLE_ERROR_NONE on successful initialization, otherwise an error code. */ - virtual ble_error_t initRadioNotification(void) { - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual ble_error_t initRadioNotification(void) + { + /* Requesting action from porter(s): override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } private: /** - * Functionality that is BLE stack-dependent and must be implemented by the - * ported. This is a helper function to set the advertising data in the - * BLE stack. + * Set the advertising data and scan response in the vendor subsytem. * - * @param[in] advData - * The new advertising data. - * @param[in] scanResponse - * The new scan response data. + * @param[in] advData Advertising data to set. + * @param[in] scanResponse Scan response to set. * * @return BLE_ERROR_NONE if the advertising data was set successfully. + * + * @note Must be implemented in vendor port. */ - virtual ble_error_t setAdvertisingData(const GapAdvertisingData &advData, const GapAdvertisingData &scanResponse) = 0; + virtual ble_error_t setAdvertisingData( + const GapAdvertisingData &advData, + const GapAdvertisingData &scanResponse + ) = 0; /** - * Functionality that is BLE stack-dependent and must be implemented by the - * ported. This is a helper function to start the advertising procedure in - * the underlying BLE stack. + * Start the advertising procedure. + * + * @param[in] Advertising parameters to use. * - * @param[in] - * The advertising parameters. + * @return BLE_ERROR_NONE if the advertising procedure successfully + * started. * - * @return BLE_ERROR_NONE if the advertising procedure was successfully - * started. + * @note Must be implemented in vendor port. */ virtual ble_error_t startAdvertising(const GapAdvertisingParams &) = 0; public: /** - * Accessor to read back currently active advertising parameters. + * Get the current advertising parameters. * * @return A reference to the current advertising parameters. */ - GapAdvertisingParams &getAdvertisingParams(void) { + GapAdvertisingParams &getAdvertisingParams(void) + { return _advParams; } /** - * A const alternative to Gap::getAdvertisingParams(). + * Const alternative to Gap::getAdvertisingParams(). * * @return A const reference to the current advertising parameters. */ - const GapAdvertisingParams &getAdvertisingParams(void) const { + const GapAdvertisingParams &getAdvertisingParams(void) const + { return _advParams; } /** - * Set up a particular, user-constructed set of advertisement parameters for - * the underlying stack. It would be uncommon for this API to be used - * directly; there are other APIs to tweak advertisement parameters - * individually. + * Set the advertising parameters. * - * @param[in] newParams - * The new advertising parameters. + * @param[in] newParams The new advertising parameters. */ - void setAdvertisingParams(const GapAdvertisingParams &newParams) { + void setAdvertisingParams(const GapAdvertisingParams &newParams) + { _advParams = newParams; } - /* Event callback handlers. */ + /* Event handlers. */ public: /** - * Set up a callback for timeout events. Refer to TimeoutSource_t for - * possible event types. + * Register a callback handling timeout events. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. * - * @note It is possible to unregister callbacks using onTimeout().detach(callback). + * @note A callback may be unregistered using onTimeout().detach(callback). + * + * @see TimeoutSource_t */ - void onTimeout(TimeoutEventCallback_t callback) { + void onTimeout(TimeoutEventCallback_t callback) + { timeoutCallbackChain.add(callback); } /** - * @brief Provide access to the callchain of timeout event callbacks. + * Get the callchain of registered timeout event handlers. * - * @note It is possible to register callbacks using onTimeout().add(callback). + * @note To register callbacks, use onTimeout().add(callback). * - * @note It is possible to unregister callbacks using onTimeout().detach(callback). + * @note To unregister callbacks, use onTimeout().detach(callback). * * @return A reference to the timeout event callbacks chain. */ - TimeoutEventCallbackChain_t& onTimeout() { + TimeoutEventCallbackChain_t& onTimeout() + { return timeoutCallbackChain; } /** - * Append to a chain of callbacks to be invoked upon GAP connection. + * Register a callback handling connection events. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. * - * @note It is possible to unregister callbacks using onConnection().detach(callback) + * @note A callback may be unregistered using onConnection().detach(callback). */ - void onConnection(ConnectionEventCallback_t callback) { + void onConnection(ConnectionEventCallback_t callback) + { connectionCallChain.add(callback); } /** - * Same as Gap::onConnection(), but allows the possibility to add an object - * reference and member function as handler for connection event - * callbacks. + * Register a callback handling connection events. + * + * @param[in] tptr Instance used to invoke @p mptr. + * @param[in] mptr Event handler being registered. * - * @param[in] tptr - * Pointer to the object of a class defining the member callback - * function (@p mptr). - * @param[in] mptr - * The member callback (within the context of an object) to be - * invoked. + * @note A callback may be unregistered using onConnection().detach(callback). */ template - void onConnection(T *tptr, void (T::*mptr)(const ConnectionCallbackParams_t*)) { + void onConnection(T *tptr, void (T::*mptr)(const ConnectionCallbackParams_t*)) + { connectionCallChain.add(tptr, mptr); } /** - * @brief Provide access to the callchain of connection event callbacks. + * Get the callchain of registered connection event handlers. * - * @return A reference to the connection event callbacks chain. + * @note To register callbacks, use onConnection().add(callback). * - * @note It is possible to register callbacks using onConnection().add(callback). + * @note To unregister callbacks, use onConnection().detach(callback). * - * @note It is possible to unregister callbacks using onConnection().detach(callback). + * @return A reference to the connection event callbacks chain. */ - ConnectionEventCallbackChain_t& onConnection() { + ConnectionEventCallbackChain_t& onConnection() + { return connectionCallChain; } /** - * Append to a chain of callbacks to be invoked upon GAP disconnection. + * Register a callback handling disconnection events. * - * @param[in] callback - Event handler being registered. + * @param[in] callback Event handler being registered. * - * @note It is possible to unregister callbacks using onDisconnection().detach(callback). + * @note A callback may be unregistered using onDisconnection().detach(callback). */ - void onDisconnection(DisconnectionEventCallback_t callback) { + void onDisconnection(DisconnectionEventCallback_t callback) + { disconnectionCallChain.add(callback); } /** - * Same as Gap::onDisconnection(), but allows the possibility to add an object - * reference and member function as handler for disconnection event - * callbacks. + * Register a callback handling disconnection events. + * + * @param[in] tptr Instance used to invoke mptr. + * @param[in] mptr Event handler being registered. * - * @param[in] tptr - * Pointer to the object of a class defining the member callback - * function (@p mptr). - * @param[in] mptr - * The member callback (within the context of an object) to be - * invoked. + * @note A callback may be unregistered using onDisconnection().detach(callback). */ template - void onDisconnection(T *tptr, void (T::*mptr)(const DisconnectionCallbackParams_t*)) { + void onDisconnection(T *tptr, void (T::*mptr)(const DisconnectionCallbackParams_t*)) + { disconnectionCallChain.add(tptr, mptr); } /** - * @brief Provide access to the callchain of disconnection event callbacks. + * Get the callchain of registered disconnection event handlers. * - * @return A reference to the disconnection event callback chain. + * @note To register callbacks use onDisconnection().add(callback). * - * @note It is possible to register callbacks using onDisconnection().add(callback). + * @note To unregister callbacks use onDisconnection().detach(callback). * - * @note It is possible to unregister callbacks using onDisconnection().detach(callback). + * @return A reference to the disconnection event callbacks chain. */ - DisconnectionEventCallbackChain_t& onDisconnection() { + DisconnectionEventCallbackChain_t& onDisconnection() + { return disconnectionCallChain; } /** - * Set the application callback for radio-notification events. + * Set the radio-notification events handler. * * Radio Notification is a feature that enables ACTIVE and INACTIVE * (nACTIVE) signals from the stack that notify the application when the * radio is in use. * * The ACTIVE signal is sent before the radio event starts. The nACTIVE - * signal is sent at the end of the radio event. These signals can be used - * by the application programmer to synchronize application logic with radio + * signal is sent at the end of the radio event. The application programmer can + * use these signals to synchronize application logic with radio * activity. For example, the ACTIVE signal can be used to shut off external - * devices, to manage peak current drawn during periods when the radio is on, + * devices, to manage peak current drawn during periods when the radio is on * or to trigger sensor data collection for transmission in the Radio Event. * - * @param[in] callback - * The application handler to be invoked in response to a radio - * ACTIVE/INACTIVE event. + * @param[in] callback Application handler to be invoked in response to a + * radio ACTIVE/INACTIVE event. */ - void onRadioNotification(void (*callback)(bool param)) { + void onRadioNotification(void (*callback)(bool param)) + { radioNotificationCallback.attach(callback); } /** - * Same as Gap::onRadioNotification(), but allows the posibility to - * register an object reference and member function as handler for radio - * notification events. + * Set the radio-notification events handler. * - * @param[in] tptr - * Pointer to the object of a class defining the member callback - * function (@p mptr). - * @param[in] mptr - * The member callback (within the context of an object) to be - * invoked in response to a radio ACTIVE/INACTIVE event. + * @param[in] tptr Instance to be used to invoke mptr. + * @param[in] mptr Application handler to be invoked in response to a + * radio ACTIVE/INACTIVE event. */ template - void onRadioNotification(T *tptr, void (T::*mptr)(bool)) { + void onRadioNotification(T *tptr, void (T::*mptr)(bool)) + { radioNotificationCallback.attach(tptr, mptr); } /** - * Setup a callback to be invoked to notify the user application that the - * Gap instance is about to shutdown (possibly as a result of a call - * to BLE::shutdown()). + * Register a Gap shutdown event handler. * - * @param[in] callback - * The handler that is being registered to be notified of - * shutdown events. + * The handler is called when the Gap instance is about to shut down. + * It is usually issued after a call to BLE::shutdown(). * - * @note It is possible to chain together multiple onShutdown callbacks - * (potentially from different modules of an application) to be notified - * before the Gap instance is shutdown. + * @param[in] callback Shutdown event handler to register. * - * @note It is also possible to set up a callback into a member function of - * some object. - * - * @note It is possible to unregister a callback using onShutdown().detach(callback) + * @note To unregister a shutdown event handler, use + * onShutdown().detach(callback). */ - void onShutdown(const GapShutdownCallback_t& callback) { + void onShutdown(const GapShutdownCallback_t& callback) + { shutdownCallChain.add(callback); } /** - * Same as Gap::onShutdown(), but allows the posibility to - * register an object reference and member function as handler for shutdown - * events. + * Register a Gap shutdown event handler. * - * @param[in] objPtr - * Pointer to the object of a class defining the member callback - * function (@p memberPtr). - * @param[in] memberPtr - * The member callback (within the context of an object) to be - * invoked in response to a shutdown event. + * @param[in] objPtr Instance used to invoke @p memberPtr. + * @param[in] memberPtr Shutdown event handler to register. */ template - void onShutdown(T *objPtr, void (T::*memberPtr)(const Gap *)) { + void onShutdown(T *objPtr, void (T::*memberPtr)(const Gap *)) + { shutdownCallChain.add(objPtr, memberPtr); } /** - * @brief Provide access to the callchain of shutdown event callbacks. + * Access the callchain of shutdown event handler. * - * @return A reference to the shutdown event callback chain. + * @note To register callbacks, use onShutdown().add(callback). * - * @note It is possible to register callbacks using onShutdown().add(callback). + * @note To unregister callbacks, use onShutdown().detach(callback). * - * @note It is possible to unregister callbacks using onShutdown().detach(callback). + * @return A reference to the shutdown event callback chain. */ - GapShutdownCallbackChain_t& onShutdown() { + GapShutdownCallbackChain_t& onShutdown() + { return shutdownCallChain; } public: /** - * Notify all registered onShutdown callbacks that the Gap instance is - * about to be shutdown and clear all Gap state of the - * associated object. + * Reset the Gap instance. + * + * Reset process starts by notifying all registered shutdown event handlers + * that the Gap instance is about to be shut down. Then, it clears all Gap state + * of the associated object and then cleans the state present in the vendor + * implementation. * * This function is meant to be overridden in the platform-specific - * sub-class. Nevertheless, the sub-class is only expected to reset its - * state and not the data held in Gap members. This shall be achieved by a - * call to Gap::reset() from the sub-class' reset() implementation. + * subclass. Nevertheless, the subclass only resets its + * state and not the data held in Gap members. This is achieved by a + * call to Gap::reset() from the subclass' reset() implementation. * * @return BLE_ERROR_NONE on success. * - * @note Currently a call to reset() does not reset the advertising and + * @note Currently, a call to reset() does not reset the advertising and * scan parameters to default values. */ - virtual ble_error_t reset(void) { - /* Notify that the instance is about to shutdown */ + virtual ble_error_t reset(void) + { + /* Notify that the instance is about to shut down */ shutdownCallChain.call(this); shutdownCallChain.clear(); @@ -1738,52 +2269,57 @@ class Gap { /* Entry points for the underlying stack to report events back to the user. */ public: /** - * Helper function that notifies all registered handlers of an occurrence - * of a connection event. This function is meant to be called from the - * BLE stack specific implementation when a connection event occurs. - * - * @param[in] handle - * The ID of the connection that generated the event. - * @param[in] role - * The role of this BLE device in the connection. - * @param[in] peerAddrType - * The peer's BLE address type. - * @param[in] peerAddr - * The peer's BLE address. - * @param[in] ownAddrType - * This device's BLE address type. - * @param[in] ownAddr - * This device's BLE address. - * @param[in] connectionParams - * The parameters configured for this connection. - */ - void processConnectionEvent(Handle_t handle, - Role_t role, - BLEProtocol::AddressType_t peerAddrType, - const BLEProtocol::AddressBytes_t peerAddr, - BLEProtocol::AddressType_t ownAddrType, - const BLEProtocol::AddressBytes_t ownAddr, - const ConnectionParams_t *connectionParams) { + * Notify all registered connection event handlers of a connection event. + * + * @important This function is meant to be called from the BLE stack specific + * implementation when a connection event occurs. + * + * @param[in] handle Handle of the new connection. + * @param[in] role Role of this BLE device in the connection. + * @param[in] peerAddrType Address type of the connected peer. + * @param[in] peerAddr Address of the connected peer. + * @param[in] ownAddrType Address type this device uses for this + * connection. + * @param[in] ownAddr Address this device uses for this connection. + * @param[in] connectionParams Parameters of the connection. + */ + void processConnectionEvent( + Handle_t handle, + Role_t role, + BLEProtocol::AddressType_t peerAddrType, + const BLEProtocol::AddressBytes_t peerAddr, + BLEProtocol::AddressType_t ownAddrType, + const BLEProtocol::AddressBytes_t ownAddr, + const ConnectionParams_t *connectionParams + ) { /* Update Gap state */ state.advertising = 0; state.connected = 1; ++connectionCount; - ConnectionCallbackParams_t callbackParams(handle, role, peerAddrType, peerAddr, ownAddrType, ownAddr, connectionParams); + ConnectionCallbackParams_t callbackParams( + handle, + role, + peerAddrType, + peerAddr, + ownAddrType, + ownAddr, + connectionParams + ); connectionCallChain.call(&callbackParams); } /** - * Helper function that notifies all registered handlers of an occurrence - * of a disconnection event. This function is meant to be called from the - * BLE stack specific implementation when a disconnection event occurs. + * Notify all registered disconnection event handlers of a disconnection event. * - * @param[in] handle - * The ID of the connection that generated the event. - * @param[in] reason - * The reason for disconnection. + * @important This function is meant to be called from the BLE stack specific + * implementation when a disconnection event occurs. + * + * @param[in] handle Handle of the terminated connection. + * @param[in] reason Reason of the disconnection. */ - void processDisconnectionEvent(Handle_t handle, DisconnectionReason_t reason) { + void processDisconnectionEvent(Handle_t handle, DisconnectionReason_t reason) + { /* Update Gap state */ --connectionCount; if (!connectionCount) { @@ -1795,48 +2331,49 @@ class Gap { } /** - * Helper function that notifies the registered handler of a scanned - * advertisement packet. This function is meant to be called from the - * BLE stack specific implementation when a such event occurs. - * - * @param[in] peerAddr - * The peer's BLE address. - * @param[in] rssi - * The advertisement packet RSSI value. - * @param[in] isScanReponse - * Whether this packet is the response to a scan request. - * @param[in] type - * The type of advertisement. - * @param[in] advertisingDataLen - * Length of the advertisement data. - * @param[in] advertisingData - * Pointer to the advertisement packet's data. - */ - void processAdvertisementReport(const BLEProtocol::AddressBytes_t peerAddr, - int8_t rssi, - bool isScanResponse, - GapAdvertisingParams::AdvertisingType_t type, - uint8_t advertisingDataLen, - const uint8_t *advertisingData) { + * Forward a received advertising packet to all registered event handlers + * listening for scanned packet events. + * + * @important This function is meant to be called from the BLE stack specific + * implementation when a disconnection event occurs. + * + * @param[in] peerAddr Address of the peer that has emitted the packet. + * @param[in] rssi Value of the RSSI measured for the received packet. + * @param[in] isScanReponse If true, then the packet is a response to a scan + * request. + * @param[in] type Advertising type of the packet. + * @param[in] advertisingDataLen Length of the advertisement data received. + * @param[in] advertisingData Pointer to the advertisement packet's data. + */ + void processAdvertisementReport( + const BLEProtocol::AddressBytes_t peerAddr, + int8_t rssi, + bool isScanResponse, + GapAdvertisingParams::AdvertisingType_t type, + uint8_t advertisingDataLen, + const uint8_t *advertisingData + ) { AdvertisementCallbackParams_t params; memcpy(params.peerAddr, peerAddr, ADDR_LEN); - params.rssi = rssi; - params.isScanResponse = isScanResponse; - params.type = type; + params.rssi = rssi; + params.isScanResponse = isScanResponse; + params.type = type; params.advertisingDataLen = advertisingDataLen; - params.advertisingData = advertisingData; + params.advertisingData = advertisingData; onAdvertisementReport.call(¶ms); } /** - * Helper function that notifies all registered handlers of an occurrence - * of a timeout event. This function is meant to be called from the - * BLE stack specific implementation when a timeout event occurs. + * Notify the occurrence of a timeout event to all registered timeout events + * handler. + * + * @important This function is meant to be called from the BLE stack specific + * implementation when a disconnection event occurs. * - * @param[in] source - * The source of the timout event. + * @param[in] source Source of the timout event. */ - void processTimeoutEvent(TimeoutSource_t source) { + void processTimeoutEvent(TimeoutSource_t source) + { if (source == TIMEOUT_SRC_ADVERTISING) { /* Update gap state if the source is an advertising timeout */ state.advertising = 0; @@ -1848,56 +2385,64 @@ class Gap { protected: /** - * Currently set advertising parameters. + * Current advertising parameters. */ - GapAdvertisingParams _advParams; + GapAdvertisingParams _advParams; + /** - * Currently set advertising data. + * Current advertising data. */ - GapAdvertisingData _advPayload; + GapAdvertisingData _advPayload; + /** - * Currently set scanning parameters. + * Current scanning parameters. */ - GapScanningParams _scanningParams; + GapScanningParams _scanningParams; + /** - * Currently set scan response data. + * Current scan response. */ - GapAdvertisingData _scanResponse; + GapAdvertisingData _scanResponse; /** - * Total number of open connections. + * Number of open connections. */ - uint8_t connectionCount; + uint8_t connectionCount; + /** - * The current GAP state. + * Current GAP state. */ - GapState_t state; + GapState_t state; + /** - * Whether active scanning is set. This is used to fetch the scan response - * from a peer if possible. + * Active scanning flag. */ - bool scanningActive; + bool scanningActive; protected: /** * Callchain containing all registered callback handlers for timeout * events. */ - TimeoutEventCallbackChain_t timeoutCallbackChain; + TimeoutEventCallbackChain_t timeoutCallbackChain; + /** * The registered callback handler for radio notification events. */ - RadioNotificationEventCallback_t radioNotificationCallback; + RadioNotificationEventCallback_t radioNotificationCallback; + /** * The registered callback handler for scanned advertisement packet * notifications. */ - AdvertisementReportCallback_t onAdvertisementReport; + AdvertisementReportCallback_t onAdvertisementReport; + /** * Callchain containing all registered callback handlers for connection * events. */ - ConnectionEventCallbackChain_t connectionCallChain; + ConnectionEventCallbackChain_t connectionCallChain; + /** * Callchain containing all registered callback handlers for disconnection * events. @@ -1917,4 +2462,9 @@ class Gap { Gap& operator=(const Gap &); }; -#endif // ifndef __GAP_H__ +/** + * @} + * @} + */ + +#endif // ifndef MBED_BLE_GAP_H__ diff --git a/features/FEATURE_BLE/ble/GapAdvertisingData.h b/features/FEATURE_BLE/ble/GapAdvertisingData.h index 80a6f7c0a49..991c144f57e 100644 --- a/features/FEATURE_BLE/ble/GapAdvertisingData.h +++ b/features/FEATURE_BLE/ble/GapAdvertisingData.h @@ -14,68 +14,110 @@ * limitations under the License. */ -#ifndef __GAP_ADVERTISING_DATA_H__ -#define __GAP_ADVERTISING_DATA_H__ +#ifndef MBED_GAP_ADVERTISING_DATA_H__ +#define MBED_GAP_ADVERTISING_DATA_H__ #include #include #include "blecommon.h" +/** + * @addtogroup ble + * @{ + * @addtogroup gap + * @{ + */ + #define GAP_ADVERTISING_DATA_MAX_PAYLOAD (31) /** - * @brief This class provides several helper functions to generate properly - * formatted GAP Advertising and Scan Response data payloads. + * GAP advertising data builder. + * + * Advertising data are used by broadcaster or peripheral to advertise state + * about the device. This class offers the function to add and update states present + * in an advertisement payload. + * + * After construction, the advertising payload contained in the instance of + * GapAdvertisingData is empty. Adding new states and named fields can be + * achieved by invoking the function addData(), and updating existing state + * involves calling the function updateData(). + * + * Fields present in the payload can be retrieved by a call to the function + * findField. + * + * This class includes shorthand for the most common fields: + * - FLAGS: addFlags(). + * - APPEARANCE: addAppearance(). + * - TX_POWER_LEVEL: addTxPower(). + * + * @code + * + * Gap ⪆ + * + * static const uint8_t device_name[] = "HRM"; + * + * // construct an empty advertising payload + * GapAdvertisingData advertising_data; + * + * // set the flags of the advertising device + * advertising_data.addFlags( + * GapAdvertisingData::LE_GENERAL_DISCOVERABLE | + * GapAdvertisingData::BREDR_NOT_SUPPORTED + * ); + * + * // set the advertised name of the device + * advertising_data.addData( + * GapAdvertisingData::COMPLETE_LOCAL_NAME, + * device_name, + * sizeof(device_name) + * ); + * + * // update the advertising data of the gap payload + * gap.setAdvertisingPayload(advertising_data); + * + * @endcode * * @note See Bluetooth Specification 4.0 (Vol. 3), Part C, Sections 11 and 18 - * for further information on Advertising and Scan Response data. + * for further information on advertising and scan response data. * * @par Advertising and Scan Response Payloads - * Advertising data and Scan Response data are organized around a set of - * data types called 'AD types' in Bluetooth 4.0 (see the Bluetooth Core - * Specification v4.0, Vol. 3, Part C, Sections 11 and 18). + * Advertising data and scan response data are organized around a set of + * data types called 'AD types' in Bluetooth 4.0 (see the Bluetooth Core + * Specification v4.0, Vol. 3, Part C, Sections 11 and 18). * * @par - * Each AD type has its own standardized assigned number, as defined - * by the Bluetooth SIG: - * https://www.bluetooth.org/en-us/specification/assigned-numbers/generic-access-profile. + * Each AD type has its own standardized assigned number, as + * the Bluetooth SIG defines: + * https://www.bluetooth.org/en-us/specification/assigned-numbers/generic-access-profile. * * @par - * For convenience, all appropriate AD types are encapsulated - * in GapAdvertisingData::DataType. + * For convenience, all appropriate AD types are encapsulated in + * GapAdvertisingData::DataType. * * @par - * Before the AD Types and their payload (if any) can be inserted into - * the Advertising or Scan Response frames, they need to be formatted as - * follows: + * Before the AD Types and their payload (if any) can be inserted into + * the advertising or scan response frames, they need to be formatted as + * follows: * * @li @c Record length (1 byte). * @li @c AD Type (1 byte). * @li @c AD payload (optional; only present if record length > 1). * * @par - * This class takes care of properly formatting the payload, performs - * some basic checks on the payload length, and tries to avoid common - * errors like adding an exclusive AD field twice in the Advertising - * or Scan Response payload. - * - * @par EXAMPLE - * - * @code - * - * // ToDo - * - * @endcode + * This class takes care of properly formatting the payload, performs + * some basic checks on the payload length and tries to avoid common + * errors such as adding an exclusive AD field twice in the advertising + * or scan response payload. */ class GapAdvertisingData { public: /*! - * @brief A list of Advertising Data types commonly used by peripherals. - * These AD types are used to describe the capabilities of the - * peripheral, and are inserted inside the advertising or scan - * response payloads. + * List of standard Advertising Data types. + * + * These AD types are used to describe the capabilities of the peripheral + * and are inserted inside the advertising or scan response payloads. * * @par Source * @@ -83,59 +125,150 @@ class GapAdvertisingData * @li @c https://www.bluetooth.org/en-us/specification/assigned-numbers/generic-access-profile. */ enum DataType_t { - FLAGS = 0x01, /**< Flags, refer to GapAdvertisingData::Flags_t. */ - INCOMPLETE_LIST_16BIT_SERVICE_IDS = 0x02, /**< Incomplete list of 16-bit Service IDs. */ - COMPLETE_LIST_16BIT_SERVICE_IDS = 0x03, /**< Complete list of 16-bit Service IDs. */ - INCOMPLETE_LIST_32BIT_SERVICE_IDS = 0x04, /**< Incomplete list of 32-bit Service IDs (not relevant for Bluetooth 4.0). */ - COMPLETE_LIST_32BIT_SERVICE_IDS = 0x05, /**< Complete list of 32-bit Service IDs (not relevant for Bluetooth 4.0). */ - INCOMPLETE_LIST_128BIT_SERVICE_IDS = 0x06, /**< Incomplete list of 128-bit Service IDs. */ - COMPLETE_LIST_128BIT_SERVICE_IDS = 0x07, /**< Complete list of 128-bit Service IDs. */ - SHORTENED_LOCAL_NAME = 0x08, /**< Shortened Local Name. */ - COMPLETE_LOCAL_NAME = 0x09, /**< Complete Local Name. */ - TX_POWER_LEVEL = 0x0A, /**< TX Power Level (in dBm). */ - DEVICE_ID = 0x10, /**< Device ID. */ - SLAVE_CONNECTION_INTERVAL_RANGE = 0x12, /**< Slave Connection Interval Range. */ - LIST_128BIT_SOLICITATION_IDS = 0x15, /**< List of 128 bit service UUIDs the device is looking for. */ - SERVICE_DATA = 0x16, /**< Service Data. */ - APPEARANCE = 0x19, /**< Appearance, refer to GapAdvertisingData::Appearance_t. */ - ADVERTISING_INTERVAL = 0x1A, /**< Advertising Interval. */ - MANUFACTURER_SPECIFIC_DATA = 0xFF /**< Manufacturer Specific Data. */ + /** + * Flags, refer to GapAdvertisingData::Flags_t. + */ + FLAGS = 0x01, + + /** + * Incomplete list of 16-bit Service IDs. + */ + INCOMPLETE_LIST_16BIT_SERVICE_IDS = 0x02, + + /** + * Complete list of 16-bit Service IDs. + */ + COMPLETE_LIST_16BIT_SERVICE_IDS = 0x03, + + /** + * Incomplete list of 32-bit Service IDs (not relevant for Bluetooth 4.0). + */ + INCOMPLETE_LIST_32BIT_SERVICE_IDS = 0x04, + + /** + * Complete list of 32-bit Service IDs (not relevant for Bluetooth 4.0). + */ + COMPLETE_LIST_32BIT_SERVICE_IDS = 0x05, + + /** + * Incomplete list of 128-bit Service IDs. + */ + INCOMPLETE_LIST_128BIT_SERVICE_IDS = 0x06, + + /** + * Complete list of 128-bit Service IDs. + */ + COMPLETE_LIST_128BIT_SERVICE_IDS = 0x07, + + /** + * Shortened Local Name. + */ + SHORTENED_LOCAL_NAME = 0x08, + + /** + * Complete Local Name. + */ + COMPLETE_LOCAL_NAME = 0x09, + + /** + * TX Power Level (in dBm). + */ + TX_POWER_LEVEL = 0x0A, + + /** + * Device ID. + */ + DEVICE_ID = 0x10, + + /** + * Slave Connection Interval Range. + */ + SLAVE_CONNECTION_INTERVAL_RANGE = 0x12, + + /** + * List of 128-bit service UUIDs the device is looking for. + */ + LIST_128BIT_SOLICITATION_IDS = 0x15, + + /** + * Service Data. + */ + SERVICE_DATA = 0x16, + + /** + * Appearance, refer to GapAdvertisingData::Appearance_t. + */ + APPEARANCE = 0x19, + + /** + * Advertising Interval. + */ + ADVERTISING_INTERVAL = 0x1A, + + /** + * Manufacturer Specific Data. + */ + MANUFACTURER_SPECIFIC_DATA = 0xFF + }; + /** - * Type alias for GapAdvertisingData::DataType_t. + * Alias for GapAdvertisingData::DataType_t. * - * @deprecated This type alias will be dropped in future releases. + * @deprecated Future releases will drop this type alias. */ typedef enum DataType_t DataType; /** - * @brief A list of values for the FLAGS AD Type. + * Enumeration of allowed flags for DataType_t::FLAGS. * - * @note You can use more than one value in the FLAGS AD Type (ex. - * LE_GENERAL_DISCOVERABLE and BREDR_NOT_SUPPORTED). + * @note DataType_t::FLAGS may contain several flags that the bitwise + * and operator (ex.LE_GENERAL_DISCOVERABLE & BREDR_NOT_SUPPORTED) assembled. * * @par Source * * @li @c Bluetooth Core Specification 4.0 (Vol. 3), Part C, Section 18.1. */ enum Flags_t { - LE_LIMITED_DISCOVERABLE = 0x01, /**< Peripheral device is discoverable for a limited period of time. */ - LE_GENERAL_DISCOVERABLE = 0x02, /**< Peripheral device is discoverable at any moment. */ - BREDR_NOT_SUPPORTED = 0x04, /**< Peripheral device is LE only. */ - SIMULTANEOUS_LE_BREDR_C = 0x08, /**< Not relevant - central mode only. */ - SIMULTANEOUS_LE_BREDR_H = 0x10 /**< Not relevant - central mode only. */ + /** + * Peripheral device is discoverable for a limited period of time. + */ + LE_LIMITED_DISCOVERABLE = 0x01, + + /** + * Peripheral device is discoverable at any moment. + */ + LE_GENERAL_DISCOVERABLE = 0x02, + + /** + * Peripheral device is LE only and does not support Bluetooth Enhanced + * DataRate. + */ + BREDR_NOT_SUPPORTED = 0x04, + + /** + * Not relevant - dual mode only. + */ + SIMULTANEOUS_LE_BREDR_C = 0x08, + + /** + * Not relevant - dual mode only. + */ + SIMULTANEOUS_LE_BREDR_H = 0x10 + }; + /** - * Type alias for GapAdvertisingData::Flags_t. + * Alias for GapAdvertisingData::Flags_t. * - * @deprecated This type alias will be dropped in future releases. + * @deprecated Future releases will drop this type alias. */ typedef enum Flags_t Flags; /** - * @brief - * A list of values for the APPEARANCE AD Type, which describes the - * physical shape or appearance of the device. + * Enumeration of values for the DataType_t::APPEARANCE. + * + * These values describe the physical shape or appearance of the device. * * @par Source * @@ -144,89 +277,288 @@ class GapAdvertisingData * @li @c https://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml. */ enum Appearance_t { - UNKNOWN = 0, /**< Unknown or unspecified appearance type. */ - GENERIC_PHONE = 64, /**< Generic Phone. */ - GENERIC_COMPUTER = 128, /**< Generic Computer. */ - GENERIC_WATCH = 192, /**< Generic Watch. */ - WATCH_SPORTS_WATCH = 193, /**< Sports Watch. */ - GENERIC_CLOCK = 256, /**< Generic Clock. */ - GENERIC_DISPLAY = 320, /**< Generic Display. */ - GENERIC_REMOTE_CONTROL = 384, /**< Generic Remote Control. */ - GENERIC_EYE_GLASSES = 448, /**< Generic Eye Glasses. */ - GENERIC_TAG = 512, /**< Generic Tag. */ - GENERIC_KEYRING = 576, /**< Generic Keyring. */ - GENERIC_MEDIA_PLAYER = 640, /**< Generic Media Player. */ - GENERIC_BARCODE_SCANNER = 704, /**< Generic Barcode Scanner. */ - GENERIC_THERMOMETER = 768, /**< Generic Thermometer. */ - THERMOMETER_EAR = 769, /**< Ear Thermometer. */ - GENERIC_HEART_RATE_SENSOR = 832, /**< Generic Heart Rate Sensor. */ - HEART_RATE_SENSOR_HEART_RATE_BELT = 833, /**< Belt Heart Rate Sensor. */ - GENERIC_BLOOD_PRESSURE = 896, /**< Generic Blood Pressure. */ - BLOOD_PRESSURE_ARM = 897, /**< Arm Blood Pressure. */ - BLOOD_PRESSURE_WRIST = 898, /**< Wrist Blood Pressure. */ - HUMAN_INTERFACE_DEVICE_HID = 960, /**< Human Interface Device (HID). */ - KEYBOARD = 961, /**< Keyboard. */ - MOUSE = 962, /**< Mouse. */ - JOYSTICK = 963, /**< Joystick. */ - GAMEPAD = 964, /**< Gamepad. */ - DIGITIZER_TABLET = 965, /**< Digitizer Tablet. */ - CARD_READER = 966, /**< Card Reader. */ - DIGITAL_PEN = 967, /**< Digital Pen. */ - BARCODE_SCANNER = 968, /**< Barcode Scanner. */ - GENERIC_GLUCOSE_METER = 1024, /**< Generic Glucose Meter. */ - GENERIC_RUNNING_WALKING_SENSOR = 1088, /**< Generic Running/Walking Sensor. */ - RUNNING_WALKING_SENSOR_IN_SHOE = 1089, /**< In Shoe Running/Walking Sensor. */ - RUNNING_WALKING_SENSOR_ON_SHOE = 1090, /**< On Shoe Running/Walking Sensor. */ - RUNNING_WALKING_SENSOR_ON_HIP = 1091, /**< On Hip Running/Walking Sensor. */ - GENERIC_CYCLING = 1152, /**< Generic Cycling. */ - CYCLING_CYCLING_COMPUTER = 1153, /**< Cycling Computer. */ - CYCLING_SPEED_SENSOR = 1154, /**< Cycling Speed Sensor. */ - CYCLING_CADENCE_SENSOR = 1155, /**< Cycling Cadence Sensor. */ - CYCLING_POWER_SENSOR = 1156, /**< Cycling Power Sensor. */ - CYCLING_SPEED_AND_CADENCE_SENSOR = 1157, /**< Cycling Speed and Cadence Sensor. */ - PULSE_OXIMETER_GENERIC = 3136, /**< Generic Pulse Oximeter. */ - PULSE_OXIMETER_FINGERTIP = 3137, /**< Fingertip Pulse Oximeter. */ - PULSE_OXIMETER_WRIST_WORN = 3138, /**< Wrist Worn Pulse Oximeter. */ - GENERIC_WEIGHT_SCALE = 3200, /**< Generic Weight Scale. */ - OUTDOOR_GENERIC = 5184, /**< Generic Outdoor. */ - OUTDOOR_LOCATION_DISPLAY_DEVICE = 5185, /**< Outdoor Location Display Device. */ - OUTDOOR_LOCATION_AND_NAVIGATION_DISPLAY_DEVICE = 5186, /**< Outdoor Location and Navigation Display Device. */ - OUTDOOR_LOCATION_POD = 5187, /**< Outdoor Location Pod. */ - OUTDOOR_LOCATION_AND_NAVIGATION_POD = 5188 /**< Outdoor Location and Navigation Pod. */ + /** + * Unknown or unspecified appearance type. + */ + UNKNOWN = 0, + + /** + * Generic Phone. + */ + GENERIC_PHONE = 64, + + /** + * Generic Computer. + */ + GENERIC_COMPUTER = 128, + + /** + * Generic Watch. + */ + GENERIC_WATCH = 192, + + /** + * Sports Watch. + */ + WATCH_SPORTS_WATCH = 193, + + /** + * Generic Clock. + */ + GENERIC_CLOCK = 256, + + /** + * Generic Display. + */ + GENERIC_DISPLAY = 320, + + /** + * Generic Remote Control. + */ + GENERIC_REMOTE_CONTROL = 384, + + /** + * Generic Eye Glasses. + */ + GENERIC_EYE_GLASSES = 448, + + /** + * Generic Tag. + */ + GENERIC_TAG = 512, + + /** + * Generic Keyring. + */ + GENERIC_KEYRING = 576, + + /** + * Generic Media Player. + */ + GENERIC_MEDIA_PLAYER = 640, + + /** + * Generic Bar Code Scanner. + */ + GENERIC_BARCODE_SCANNER = 704, + + /** + * Generic Thermometer. + */ + GENERIC_THERMOMETER = 768, + + /** + * Ear Thermometer. + */ + THERMOMETER_EAR = 769, + + /** + * Generic Heart Rate Sensor. + */ + GENERIC_HEART_RATE_SENSOR = 832, + + /** + * Belt Heart Rate Sensor. + */ + HEART_RATE_SENSOR_HEART_RATE_BELT = 833, + + /** + * Generic Blood Pressure. + */ + GENERIC_BLOOD_PRESSURE = 896, + + /** + * Arm Blood Pressure. + */ + BLOOD_PRESSURE_ARM = 897, + + /** + * Wrist Blood Pressure. + */ + BLOOD_PRESSURE_WRIST = 898, + + /** + * Human Interface Device (HID). + */ + HUMAN_INTERFACE_DEVICE_HID = 960, + + /** + * Keyboard. + */ + KEYBOARD = 961, + + /** + * Mouse. + */ + MOUSE = 962, + + /** + * Joystick. + */ + JOYSTICK = 963, + + /** + * Gamepad. + */ + GAMEPAD = 964, + + /** + * Digitizer Tablet. + */ + DIGITIZER_TABLET = 965, + + /** + * Card Reader. + */ + CARD_READER = 966, + + /** + * Digital Pen. + */ + DIGITAL_PEN = 967, + + /** + * Bar Code Scanner. + */ + BARCODE_SCANNER = 968, + + /** + * Generic Glucose Meter. + */ + GENERIC_GLUCOSE_METER = 1024, + + /** + * Generic Running/Walking Sensor. + */ + GENERIC_RUNNING_WALKING_SENSOR = 1088, + + /** + * In Shoe Running/Walking Sensor. + */ + RUNNING_WALKING_SENSOR_IN_SHOE = 1089, + + /** + * On Shoe Running/Walking Sensor. + */ + RUNNING_WALKING_SENSOR_ON_SHOE = 1090, + + /** + * On Hip Running/Walking Sensor. + */ + RUNNING_WALKING_SENSOR_ON_HIP = 1091, + + /** + * Generic Cycling. + */ + GENERIC_CYCLING = 1152, + + /** + * Cycling Computer. + */ + CYCLING_CYCLING_COMPUTER = 1153, + + /** + * Cycling Speed Sensor. + */ + CYCLING_SPEED_SENSOR = 1154, + + /** + * Cycling Cadence Sensor. + */ + CYCLING_CADENCE_SENSOR = 1155, + + /** + * Cycling Power Sensor. + */ + CYCLING_POWER_SENSOR = 1156, + + /** + * Cycling Speed and Cadence Sensor. + */ + CYCLING_SPEED_AND_CADENCE_SENSOR = 1157, + + /** + * Generic Pulse Oximeter. + */ + PULSE_OXIMETER_GENERIC = 3136, + + /** + * Fingertip Pulse Oximeter. + */ + PULSE_OXIMETER_FINGERTIP = 3137, + + /** + * Wrist Worn Pulse Oximeter. + */ + PULSE_OXIMETER_WRIST_WORN = 3138, + + /** + * Generic Weight Scale. + */ + GENERIC_WEIGHT_SCALE = 3200, + + /** + * Generic Outdoor. + */ + OUTDOOR_GENERIC = 5184, + + /** + * Outdoor Location Display Device. + */ + OUTDOOR_LOCATION_DISPLAY_DEVICE = 5185, + + /** + * Outdoor Location and Navigation Display Device. + */ + OUTDOOR_LOCATION_AND_NAVIGATION_DISPLAY_DEVICE = 5186, + + /** + * Outdoor Location Pod. + */ + OUTDOOR_LOCATION_POD = 5187, + + /** + * Outdoor Location and Navigation Pod. + */ + OUTDOOR_LOCATION_AND_NAVIGATION_POD = 5188 + }; + /** - * Type alias for GapAdvertisingData::Appearance_t. + * Alias for GapAdvertisingData::Appearance_t. * - * @deprecated This type alias will be dropped in future releases. + * @deprecated Future releases will drop this type alias. */ typedef enum Appearance_t Appearance; /** - * Empty constructor. + * Construct a GapAdvertising instance with an empty payload. */ - GapAdvertisingData(void) : _payload(), _payloadLen(0), _appearance(GENERIC_TAG) { - /* empty */ + GapAdvertisingData(void) : + _payload(), + _payloadLen(0), + _appearance(GENERIC_TAG) { } /** - * Adds advertising data based on the specified AD type (see GapAdvertisingData::DataType_t). - * If the supplied AD type is already present in the advertising - * payload, then the value is updated. + * Adds a new field into the payload. * - * @param[in] advDataType The Advertising 'DataType' to add. - * @param[in] payload Pointer to the payload contents. - * @param[in] len Size of the payload in bytes. + * If the supplied advertising data type is already present in the + * advertising payload, then the value is updated. * - * @return BLE_ERROR_BUFFER_OVERFLOW if the new value causes the - * advertising buffer to overflow. BLE_ERROR_NONE is returned - * on success. + * @param[in] advDataType The type of the field to add. + * @param[in] payload Pointer to the value of the field to add. + * @param[in] len Size in bytes of the value to add. * - * @note When the specified AD type is INCOMPLETE_LIST_16BIT_SERVICE_IDS, - * COMPLETE_LIST_16BIT_SERVICE_IDS, INCOMPLETE_LIST_32BIT_SERVICE_IDS, - * COMPLETE_LIST_32BIT_SERVICE_IDS, INCOMPLETE_LIST_128BIT_SERVICE_IDS, - * COMPLETE_LIST_128BIT_SERVICE_IDS or LIST_128BIT_SOLICITATION_IDS the - * supplied value is appended to the values previously added to the - * payload. + * @return BLE_ERROR_NONE on success. + * @return BLE_ERROR_BUFFER_OVERFLOW if the new value causes the advertising + * buffer to overflow. + * + * @note When the specified data type is INCOMPLETE_LIST_16BIT_SERVICE_IDS, + * COMPLETE_LIST_16BIT_SERVICE_IDS, INCOMPLETE_LIST_32BIT_SERVICE_IDS, + * COMPLETE_LIST_32BIT_SERVICE_IDS, INCOMPLETE_LIST_128BIT_SERVICE_IDS, + * COMPLETE_LIST_128BIT_SERVICE_IDS or LIST_128BIT_SOLICITATION_IDS, the + * supplied value is appended to the values present in the payload. */ ble_error_t addData(DataType_t advDataType, const uint8_t *payload, uint8_t len) { @@ -234,26 +566,25 @@ class GapAdvertisingData uint8_t* field = findField(advDataType); if (field) { - /* Field type already exist, either add to field or replace */ + /* Field type already exists, either add to field or replace */ return addField(advDataType, payload, len, field); } else { - /* Field doesn't exists, insert new */ + /* Field doesn't exist, insert new */ return appendField(advDataType, payload, len); } } /** - * Update a particular ADV field in the advertising payload (based on - * matching type). + * Update a specific field in the advertising payload. * - * @param[in] advDataType The Advertising 'DataType' to add. - * @param[in] payload Pointer to the payload contents. - * @param[in] len Size of the payload in bytes. + * @param[in] advDataType The type of the field to update. + * @param[in] payload Pointer to the updated value of the field. + * @param[in] len Size of the new value in bytes. * + * @return BLE_ERROR_NONE returned on success. * @return BLE_ERROR_UNSPECIFIED if the specified field is not found, - * BLE_ERROR_BUFFER_OVERFLOW if the new value causes the - * advertising buffer to overflow. BLE_ERROR_NONE is returned - * on success. + * @return BLE_ERROR_BUFFER_OVERFLOW if the new value causes the + * advertising buffer to overflow. */ ble_error_t updateData(DataType_t advDataType, const uint8_t *payload, uint8_t len) { @@ -261,102 +592,122 @@ class GapAdvertisingData uint8_t* field = findField(advDataType); if (field) { - /* Field type already exist, replace field contents */ + /* Field type already exists, replace field contents */ return updateField(advDataType, payload, len, field); } else { - /* field doesn't exists, return an error */ + /* field doesn't exist, return an error */ return BLE_ERROR_UNSPECIFIED; } } /** - * Helper function to add APPEARANCE data to the advertising payload. + * Add device appearance in the advertising payload. * - * @param appearance - * The APPEARANCE value to add. + * @param[in] appearance The appearance to advertise. * + * @return BLE_ERROR_NONE on success. * @return BLE_ERROR_BUFFER_OVERFLOW if the specified data would cause the - * advertising buffer to overflow, else BLE_ERROR_NONE. + * advertising buffer to overflow. + * + * @note This call is equivalent to calling addData() with + * GapAdvertisingData::APPEARANCE as the field type. */ - ble_error_t addAppearance(Appearance appearance = GENERIC_TAG) { + ble_error_t addAppearance(Appearance appearance = GENERIC_TAG) + { _appearance = appearance; return addData(GapAdvertisingData::APPEARANCE, (uint8_t *)&appearance, 2); } /** - * Helper function to add FLAGS data to the advertising payload. + * Add BLE flags in the advertising payload. * - * @param[in] flags - * LE_LIMITED_DISCOVERABLE - * The peripheral is discoverable for a limited period of time. - * LE_GENERAL_DISCOVERABLE - * The peripheral is permanently discoverable. - * BREDR_NOT_SUPPORTED - * This peripheral is a Bluetooth Low Energy only device (no EDR support). + * @param[in] flags Bitfield describing the capability of the device. See + * allowed flags in Flags_t. * + * @return BLE_ERROR_NONE on success. * @return BLE_ERROR_BUFFER_OVERFLOW if the specified data would cause the - * advertising buffer to overflow, else BLE_ERROR_NONE. + * advertising buffer to overflow. + * + * @note This call is equivalent to calling addData() with + * GapAdvertisingData::FLAGS as the field type. */ - ble_error_t addFlags(uint8_t flags = LE_GENERAL_DISCOVERABLE) { + ble_error_t addFlags(uint8_t flags = LE_GENERAL_DISCOVERABLE) + { return addData(GapAdvertisingData::FLAGS, &flags, 1); } /** - * Helper function to add TX_POWER_LEVEL data to the advertising payload. + * Add the advertising TX in the advertising payload. * + * @param[in] txPower Transmission power level in dB. + * + * @return BLE_ERROR_NONE on success. * @return BLE_ERROR_BUFFER_OVERFLOW if the specified data would cause the - * advertising buffer to overflow, else BLE_ERROR_NONE. + * advertising buffer to overflow. + * + * @note This call is equivalent to calling addData() with + * GapAdvertisingData::TX_POWER_LEVEL as the field type. */ - ble_error_t addTxPower(int8_t txPower) { + ble_error_t addTxPower(int8_t txPower) + { /* To Do: Basic error checking to make sure txPower is in range. */ return addData(GapAdvertisingData::TX_POWER_LEVEL, (uint8_t *)&txPower, 1); } /** - * Clears the payload and resets the payload length counter. + * Clears the advertising data payload. + * + * @post getPayloadLen() returns 0. */ - void clear(void) { + void clear(void) + { memset(&_payload, 0, GAP_ADVERTISING_DATA_MAX_PAYLOAD); _payloadLen = 0; } /** - * Access the current payload. + * Get the pointer to the advertising payload bytes. * - * @return A pointer to the current payload. + * @return A pointer to the payload. */ - const uint8_t *getPayload(void) const { + const uint8_t *getPayload(void) const + { return _payload; } /** - * Get the current payload length. + * Get the payload length. * - * @return The current payload length (0..31 bytes). + * @return The payload length in bytes. */ - uint8_t getPayloadLen(void) const { + uint8_t getPayloadLen(void) const + { return _payloadLen; } /** - * Get the current appearance value. + * Get the appearance set. + * + * If no value has been set, this function returns GENERIC_TAG. * - * @return The 16-bit appearance value for this device. + * @return The appearance value set for this device. */ - uint16_t getAppearance(void) const { + uint16_t getAppearance(void) const + { return (uint16_t)_appearance; } /** * Search advertisement data for a specific field. * - * @param[in] type - * The type of the field to find. + * @param[in] type The type of the field to find. * - * @return A pointer to the first element in the field if found, NULL otherwise. - * Where the first element is the length of the field. + * @return A pointer to the first element in the field if found. The first + * element being the length of the field followed by the value of the field. + * @return NULL if the field is not present in the payload. */ - const uint8_t* findField(DataType_t type) const { + const uint8_t* findField(DataType_t type) const + { /* Scan through advertisement data */ for (uint8_t idx = 0; idx < _payloadLen; ) { uint8_t fieldType = _payload[idx + 1]; @@ -375,23 +726,20 @@ class GapAdvertisingData private: /** - * Append advertising data based on the specified AD type (see - * GapAdvertisingData::DataType_t). + * Append advertising data based on the specified type. * - * @param[in] advDataType - * The type of the new data. - * @param[in] payload - * A pointer to the data to be appended to the advertising - * payload. - * @param[in] len - * The length of th data pointed to by @p payload. + * @param[in] advDataType Type of the new data. + * @param[in] payload Pointer to the data to be appended to the advertising + * payload. + * @param[in] len Length of the data pointed to by @p payload. * + * @return BLE_ERROR_NONE on success. * @return BLE_ERROR_BUFFER_OVERFLOW if the specified data would cause the - * advertising buffer to overflow, else BLE_ERROR_NONE. + * advertising buffer to overflow. */ ble_error_t appendField(DataType advDataType, const uint8_t *payload, uint8_t len) { - /* Make sure we don't exceed the 31 byte payload limit */ + /* Make sure we don't exceed the 31-byte payload limit */ if (_payloadLen + len + 2 > GAP_ADVERTISING_DATA_MAX_PAYLOAD) { return BLE_ERROR_BUFFER_OVERFLOW; } @@ -412,48 +760,50 @@ class GapAdvertisingData } /** - * Search advertisement data for field. + * Search advertisement data for a specific field. * - * @param[in] type - * The type of the data to find. + * @param[in] type The type of the field to find. * - * @return A pointer to the first element in the field if found, NULL - * otherwise. Where the first element is the length of the field. + * @return A pointer to the first element in the field if found. The first + * element being the length of the field followed by the value of the field. + * @return NULL if the field is not present in the payload. */ - uint8_t* findField(DataType_t type) { - return const_cast(static_cast(this)->findField(type)); + uint8_t* findField(DataType_t type) + { + return const_cast( + static_cast(this)->findField(type) + ); } /** - * Given the a pointer to a field in the advertising payload it replaces - * the existing data in the field with the supplied data. - * - * @param[in] advDataType - * The type of the new data. - * @param[in] payload - * A pointer to the data to be added to the advertising - * payload. - * @param[in] len - * The length of th data pointed to by @p payload. - * @param[in] field - * A pointer to the field of type @p advDataType in the - * advertising buffer. - * - * When the specified AD type is INCOMPLETE_LIST_16BIT_SERVICE_IDS, + * Update in place the value of a field in the advertising payload. + * + * @param[in] advDataType Type of the new data. + * @param[in] payload Pointer to the data to be added to the advertising + * payload. + * @param[in] len Length of the data pointed to by @p payload. + * @param[in] field Pointer to the field of type @p advDataType in the + * advertising buffer. + * + * @note When the specified AD type is INCOMPLETE_LIST_16BIT_SERVICE_IDS, * COMPLETE_LIST_16BIT_SERVICE_IDS, INCOMPLETE_LIST_32BIT_SERVICE_IDS, * COMPLETE_LIST_32BIT_SERVICE_IDS, INCOMPLETE_LIST_128BIT_SERVICE_IDS, - * COMPLETE_LIST_128BIT_SERVICE_IDS or LIST_128BIT_SOLICITATION_IDS the + * COMPLETE_LIST_128BIT_SERVICE_IDS or LIST_128BIT_SOLICITATION_IDS, the * supplied value is appended to the values previously added to the * payload. * * @return BLE_ERROR_NONE on success. */ - ble_error_t addField(DataType_t advDataType, const uint8_t *payload, uint8_t len, uint8_t* field) - { + ble_error_t addField( + DataType_t advDataType, + const uint8_t *payload, + uint8_t len, + uint8_t* field + ) { ble_error_t result = BLE_ERROR_BUFFER_OVERFLOW; switch(advDataType) { - /* These fields will have the new data appended if there is sufficient space */ + /* These fields have the new data appended if there is sufficient space. */ case INCOMPLETE_LIST_16BIT_SERVICE_IDS: case COMPLETE_LIST_16BIT_SERVICE_IDS: case INCOMPLETE_LIST_32BIT_SERVICE_IDS: @@ -489,7 +839,7 @@ class GapAdvertisingData break; } - /* These fields will be overwritten with the new value */ + /* These fields are overwritten with the new value */ default: { result = updateField(advDataType, payload, len, field); @@ -501,24 +851,23 @@ class GapAdvertisingData } /** - * Given the a pointer to a field in the advertising payload it replaces - * the existing data in the field with the supplied data. - * - * @param[in] advDataType - * The type of the data to be updated. - * @param[in] payload - * A pointer to the data to be updated to the advertising - * payload. - * @param[in] len - * The length of th data pointed to by @p payload. - * @param[in] field - * A pointer to the field of type @p advDataType in the - * advertising buffer. + * Update in place the value of a field in the advertising payload. + * + * @param[in] advDataType Type of the new data. + * @param[in] payload Pointer to the data to be added to the advertising + * payload. + * @param[in] len Length of the data pointed to by @p payload. + * @param[in] field Pointer to the field of type @p advDataType in the + * advertising buffer. * * @return BLE_ERROR_NONE on success. */ - ble_error_t updateField(DataType_t advDataType, const uint8_t *payload, uint8_t len, uint8_t* field) - { + ble_error_t updateField( + DataType_t advDataType, + const uint8_t *payload, + uint8_t len, + uint8_t* field + ) { ble_error_t result = BLE_ERROR_BUFFER_OVERFLOW; uint8_t dataLength = field[0] - 1; @@ -551,17 +900,25 @@ class GapAdvertisingData } /** - * The advertising data buffer + * Advertising data buffer. */ - uint8_t _payload[GAP_ADVERTISING_DATA_MAX_PAYLOAD]; + uint8_t _payload[GAP_ADVERTISING_DATA_MAX_PAYLOAD]; + /** - * The length of the data added to the advertising buffer. + * Length of the data added to the advertising buffer. */ - uint8_t _payloadLen; + uint8_t _payloadLen; + /** * Appearance value. */ uint16_t _appearance; }; -#endif /* ifndef __GAP_ADVERTISING_DATA_H__ */ +/** + * @} + * @} + */ + + +#endif /* ifndef MBED_GAP_ADVERTISING_DATA_H__ */ diff --git a/features/FEATURE_BLE/ble/GapAdvertisingParams.h b/features/FEATURE_BLE/ble/GapAdvertisingParams.h index a1938268183..2b8e74d94f5 100644 --- a/features/FEATURE_BLE/ble/GapAdvertisingParams.h +++ b/features/FEATURE_BLE/ble/GapAdvertisingParams.h @@ -14,50 +14,101 @@ * limitations under the License. */ -#ifndef __GAP_ADVERTISING_PARAMS_H__ -#define __GAP_ADVERTISING_PARAMS_H__ +#ifndef MBED_GAP_ADVERTISING_PARAMS_H__ +#define MBED_GAP_ADVERTISING_PARAMS_H__ /** - * This class provides a wrapper for the core advertising parameters, - * including the advertising type (Connectable Undirected, - * Non Connectable Undirected and so on), as well as the advertising and - * timeout intervals. + * @addtogroup ble + * @{ + * @addtogroup gap + * @{ + */ + +/** + * Parameters defining the advertising process. + * + * Advertising parameters are a triplet of three value: + * - The Advertising mode modeled after AdvertisingType_t. It defines + * if the device is connectable and scannable. This value can be set at + * construction time, updated with setAdvertisingType() and queried by + * getAdvertisingType(). + * - Time interval between advertisement. It can be set at construction time, + * updated by setInterval() and obtained from getInterval(). + * - Duration of the advertising process. As others, it can be set at + * construction time, modified by setTimeout() and retrieved by getTimeout(). */ class GapAdvertisingParams { public: + /** * Minimum Advertising interval for connectable undirected and connectable - * directed events in 625us units - 20ms. + * directed events in 625us units. + * + * @note Equal to 20 ms. */ - static const unsigned GAP_ADV_PARAMS_INTERVAL_MIN = 0x0020; + static const unsigned GAP_ADV_PARAMS_INTERVAL_MIN = 0x0020; + /** - * Minimum Advertising interval for scannable and non-connectable - * undirected events in 625us units - 100ms. + * Minimum Advertising interval for scannable and nonconnectable + * undirected events in 625us units. + * + * @note Equal to 100ms. */ static const unsigned GAP_ADV_PARAMS_INTERVAL_MIN_NONCON = 0x00A0; + /** - * Maximum Advertising interval in 625us units - 10.24s. + * Maximum Advertising interval in 625us units. + * + * @note Equal to 10.24s. */ - static const unsigned GAP_ADV_PARAMS_INTERVAL_MAX = 0x4000; + static const unsigned GAP_ADV_PARAMS_INTERVAL_MAX = 0x4000; + /** - * Maximum advertising timeout seconds. + * Maximum advertising timeout allowed; in seconds. */ - static const unsigned GAP_ADV_PARAMS_TIMEOUT_MAX = 0x3FFF; + static const unsigned GAP_ADV_PARAMS_TIMEOUT_MAX = 0x3FFF; /** - * Encapsulates the peripheral advertising modes, which determine how - * the device appears to other central devices in hearing range. + * Encapsulates the peripheral advertising modes. + * + * It determine how the device appears to other scanner and peripheral + * devices in the scanning range. */ enum AdvertisingType_t { - ADV_CONNECTABLE_UNDIRECTED, /**< Vol 3, Part C, Section 9.3.4 and Vol 6, Part B, Section 2.3.1.1. */ - ADV_CONNECTABLE_DIRECTED, /**< Vol 3, Part C, Section 9.3.3 and Vol 6, Part B, Section 2.3.1.2. */ - ADV_SCANNABLE_UNDIRECTED, /**< Include support for Scan Response payloads, see Vol 6, Part B, Section 2.3.1.4. */ - ADV_NON_CONNECTABLE_UNDIRECTED /**< Vol 3, Part C, Section 9.3.2 and Vol 6, Part B, Section 2.3.1.3. */ + /** + * Device is connectable, scannable and doesn't expect connection from a + * specific peer. + * + * @see Vol 3, Part C, Section 9.3.4 and Vol 6, Part B, Section 2.3.1.1. + */ + ADV_CONNECTABLE_UNDIRECTED, + + /** + * Device is connectable and expects connection from a specific peer. + * + * @see Vol 3, Part C, Section 9.3.3 and Vol 6, Part B, Section 2.3.1.2. + */ + ADV_CONNECTABLE_DIRECTED, + + /** + * Device is scannable but not connectable. + * + * @see Vol 6, Part B, Section 2.3.1.4. + */ + ADV_SCANNABLE_UNDIRECTED, + + /** + * Device is not connectable and not scannable. + * + * @see Vol 3, Part C, Section 9.3.2 and Vol 6, Part B, Section 2.3.1.3. + */ + ADV_NON_CONNECTABLE_UNDIRECTED }; + /** - * Type alias for GapAdvertisingParams::AdvertisingType_t. + * Alias for GapAdvertisingParams::AdvertisingType_t. * - * @deprecated This type alias will be dropped in future releases. + * @deprecated Future releases will drop this type alias. */ typedef enum AdvertisingType_t AdvertisingType; @@ -65,18 +116,23 @@ class GapAdvertisingParams { /** * Construct an instance of GapAdvertisingParams. * - * @param[in] advType - * Type of advertising. Default is - * GapAdvertisingParams::ADV_CONNECTABLE_UNDIRECTED. - * @param[in] interval - * Advertising interval in units of 0.625ms. Default is - * GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN_NONCON. - * @param[in] timeout - * Advertising timeout. Default is 0. - */ - GapAdvertisingParams(AdvertisingType_t advType = ADV_CONNECTABLE_UNDIRECTED, - uint16_t interval = GAP_ADV_PARAMS_INTERVAL_MIN_NONCON, - uint16_t timeout = 0) : _advType(advType), _interval(interval), _timeout(timeout) { + * @param[in] advType Type of advertising. + * @param[in] interval Time interval between two advertisement in units of + * 0.625ms. + * @param[in] timeout Duration in seconds of the advertising process. A + * value of 0 indicate that there is no timeout of the advertising process. + * + * @note If value in input are out of range, they will be normalized. + */ + GapAdvertisingParams( + AdvertisingType_t advType = ADV_CONNECTABLE_UNDIRECTED, + uint16_t interval = GAP_ADV_PARAMS_INTERVAL_MIN_NONCON, + uint16_t timeout = 0 + ) : + _advType(advType), + _interval(interval), + _timeout(timeout) + { /* Interval checks. */ if (_advType == ADV_CONNECTABLE_DIRECTED) { /* Interval must be 0 in directed connectable mode. */ @@ -108,27 +164,32 @@ class GapAdvertisingParams { } } - static const uint16_t UNIT_0_625_MS = 625; /**< Number of microseconds in 0.625 milliseconds. */ + /** + * Number of microseconds in 0.625 milliseconds. + */ + static const uint16_t UNIT_0_625_MS = 625; + /** * Convert milliseconds to units of 0.625ms. * - * @param[in] durationInMillis - * The number of milliseconds to convert. + * @param[in] durationInMillis Number of milliseconds to convert. * * @return The value of @p durationInMillis in units of 0.625ms. */ - static uint16_t MSEC_TO_ADVERTISEMENT_DURATION_UNITS(uint32_t durationInMillis) { + static uint16_t MSEC_TO_ADVERTISEMENT_DURATION_UNITS(uint32_t durationInMillis) + { return (durationInMillis * 1000) / UNIT_0_625_MS; } + /** * Convert units of 0.625ms to milliseconds. * - * @param[in] gapUnits - * The number of units of 0.625ms to convert. + * @param[in] gapUnits The number of units of 0.625ms to convert. * * @return The value of @p gapUnits in milliseconds. */ - static uint16_t ADVERTISEMENT_DURATION_UNITS_TO_MS(uint16_t gapUnits) { + static uint16_t ADVERTISEMENT_DURATION_UNITS_TO_MS(uint16_t gapUnits) + { return (gapUnits * UNIT_0_625_MS) / 1000; } @@ -137,7 +198,8 @@ class GapAdvertisingParams { * * @return The advertising type. */ - AdvertisingType_t getAdvertisingType(void) const { + AdvertisingType_t getAdvertisingType(void) const + { return _advType; } @@ -146,16 +208,19 @@ class GapAdvertisingParams { * * @return The advertisement interval (in milliseconds). */ - uint16_t getInterval(void) const { + uint16_t getInterval(void) const + { return ADVERTISEMENT_DURATION_UNITS_TO_MS(_interval); } /** * Get the advertisement interval in units of 0.625ms. * - * @return The advertisement interval in advertisement duration units (0.625ms units). + * @return The advertisement interval in advertisement duration units + * (0.625ms units). */ - uint16_t getIntervalInADVUnits(void) const { + uint16_t getIntervalInADVUnits(void) const + { return _interval; } @@ -164,44 +229,63 @@ class GapAdvertisingParams { * * @return The advertising timeout (in seconds). */ - uint16_t getTimeout(void) const { + uint16_t getTimeout(void) const + { return _timeout; } /** - * Set the advertising type. + * Update the advertising type. * - * @param[in] newAdvType - * The new advertising type. + * @param[in] newAdvType The new advertising type. */ - void setAdvertisingType(AdvertisingType_t newAdvType) { + void setAdvertisingType(AdvertisingType_t newAdvType) + { _advType = newAdvType; } /** - * Set the advertising interval in milliseconds. + * Update the advertising interval in milliseconds. * - * @param[in] newInterval - * The new advertising interval in milliseconds. + * @param[in] newInterval The new advertising interval in milliseconds. */ - void setInterval(uint16_t newInterval) { + void setInterval(uint16_t newInterval) + { _interval = MSEC_TO_ADVERTISEMENT_DURATION_UNITS(newInterval); } /** - * Set the advertising timeout. + * Update the advertising timeout. * - * @param[in] newTimeout - * The new advertising timeout (in seconds). + * @param[in] newTimeout The new advertising timeout (in seconds). + * + * @note 0 is a special value meaning the advertising process never ends. */ - void setTimeout(uint16_t newTimeout) { + void setTimeout(uint16_t newTimeout) + { _timeout = newTimeout; } private: - AdvertisingType_t _advType; /**< The advertising type. */ - uint16_t _interval; /**< The advertising interval in ADV duration units (i.e. 0.625ms). */ - uint16_t _timeout; /**< The advertising timeout in seconds. */ + /** + * The advertising type. + */ + AdvertisingType_t _advType; + + /** + * The advertising interval in ADV duration units (in other words, 0.625ms). + */ + uint16_t _interval; + + /** + * The advertising timeout in seconds. + */ + uint16_t _timeout; }; -#endif /* ifndef __GAP_ADVERTISING_PARAMS_H__ */ +/** + * @} + * @} + */ + +#endif /* ifndef MBED_GAP_ADVERTISING_PARAMS_H__ */ diff --git a/features/FEATURE_BLE/ble/GapEvents.h b/features/FEATURE_BLE/ble/GapEvents.h index fda5b15aa2b..15db125dfbf 100644 --- a/features/FEATURE_BLE/ble/GapEvents.h +++ b/features/FEATURE_BLE/ble/GapEvents.h @@ -14,28 +14,30 @@ * limitations under the License. */ -#ifndef __GAP_EVENTS_H__ -#define __GAP_EVENTS_H__ +#ifndef MBED_GAP_EVENTS_H__ +#define MBED_GAP_EVENTS_H__ #include "blecommon.h" -/**************************************************************************/ +/// @cond 0 + /*! \brief The base class used to abstract away the callback events that can be triggered with the GAP. + + @deprecated Do not use; it is not used by BLE API. */ -/**************************************************************************/ class GapEvents { public: - /******************************************************************/ /*! \brief Identifies GAP events generated by the radio HW when an event callback occurs. + + @deprecated Do not use; it is not used by BLE API. */ - /******************************************************************/ typedef enum gapEvent_e { GAP_EVENT_TIMEOUT = 1, /**< Advertising timed out before a connection could be established. */ GAP_EVENT_CONNECTED = 2, /**< A connection was established with a central device. */ @@ -43,4 +45,6 @@ class GapEvents } gapEvent_t; }; -#endif // ifndef __GAP_EVENTS_H__ +/// @endcond + +#endif // ifndef MBED_GAP_EVENTS_H__ diff --git a/features/FEATURE_BLE/ble/GapScanningParams.h b/features/FEATURE_BLE/ble/GapScanningParams.h index 9f88b20309d..7ff43295c02 100644 --- a/features/FEATURE_BLE/ble/GapScanningParams.h +++ b/features/FEATURE_BLE/ble/GapScanningParams.h @@ -14,89 +14,154 @@ * limitations under the License. */ -#ifndef __GAP_SCANNING_PARAMS_H__ -#define __GAP_SCANNING_PARAMS_H__ +#ifndef MBED_GAP_SCANNING_PARAMS_H__ +#define MBED_GAP_SCANNING_PARAMS_H__ +/** + * @addtogroup ble + * @{ + * @addtogroup gap + * @{ + */ + +/** + * Parameters defining the scan process. + * + * Four distinct parameters define the scan procedure: + * - Scan window: Period during which the scanner listens to advertising + * channels. That value is in the range of 2.5ms to 10.24s. This value + * can be set at construction time, updated by calling setWindow() and + * retrieved by invoking getWindow(). + * + * - Scan interval: Interval between the start of two consecutive scan windows. + * That value shall be greater or equal to the scan window value. The + * maximum allowed value is 10.24ms. The scan interval value can be set at + * construction time, updated with a call to setInterval() and queried by a + * call to getInterval(). + * + * - Timeout: The duration of the scan procedure if any. It can be set at + * construction time, updated with setTimeout() and obtained from + * getTimeout(). + * + * - Active scanning: If set, then the scanner sends scan requests to a scannable + * or connectable advertiser. Advertisers may respond to the scan request + * by a scan response containing the scan response payload. If not set, then + * the scanner does not send any request. This flag is set at construction + * time, may be updated with the help of setActiveScanning() and retrieved + * by getActiveScanning(). + * + * @note If the scan window's duration is equal to the scan interval, then the + * device listens continuously during the scan procedure. + */ class GapScanningParams { public: - static const unsigned SCAN_INTERVAL_MIN = 0x0004; /**< Minimum Scan interval in 625us units - 2.5ms. */ - static const unsigned SCAN_INTERVAL_MAX = 0x4000; /**< Maximum Scan interval in 625us units - 10.24s. */ - static const unsigned SCAN_WINDOW_MIN = 0x0004; /**< Minimum Scan window in 625us units - 2.5ms. */ - static const unsigned SCAN_WINDOW_MAX = 0x4000; /**< Maximum Scan window in 625us units - 10.24s. */ - static const unsigned SCAN_TIMEOUT_MIN = 0x0001; /**< Minimum Scan timeout in seconds. */ - static const unsigned SCAN_TIMEOUT_MAX = 0xFFFF; /**< Maximum Scan timeout in seconds. */ + /** + * Minimum Scan interval in 625us units - 2.5ms. + */ + static const unsigned SCAN_INTERVAL_MIN = 0x0004; + + /** + * Maximum Scan interval in 625us units - 10.24s. + */ + static const unsigned SCAN_INTERVAL_MAX = 0x4000; + + /** + * Minimum Scan window in 625us units - 2.5ms. + */ + static const unsigned SCAN_WINDOW_MIN = 0x0004; + + /** + * Maximum Scan window in 625us units - 10.24s. + */ + static const unsigned SCAN_WINDOW_MAX = 0x4000; + + /** + * Minimum Scan duration in seconds. + */ + static const unsigned SCAN_TIMEOUT_MIN = 0x0001; + + /** + * Maximum Scan duration in seconds. + */ + static const unsigned SCAN_TIMEOUT_MAX = 0xFFFF; public: /** * Construct an instance of GapScanningParams. * - * @param[in] interval - * The scan interval in milliseconds. Default is - * GapScanningParams::SCAN_INTERVAL_MIN. - * @param[in] window - * The scan window in milliseconds. Default is - * GapScanningParams::SCAN_WINDOW_MAX. - * @param[in] timeout - * The scan timeout in seconds. Default is 0. - * @param[in] activeScanning - * Set to True if active-scanning is required. This is used to - * fetch the scan response from a peer if possible. Default is - * false. - */ - GapScanningParams(uint16_t interval = SCAN_INTERVAL_MAX, - uint16_t window = SCAN_WINDOW_MAX, - uint16_t timeout = 0, - bool activeScanning = false); - - static const uint16_t UNIT_0_625_MS = 625; /**< Number of microseconds in 0.625 milliseconds. */ + * @param[in] interval Milliseconds interval between the start of two + * consecutive scan windows. The value passed is between the scan + * window value and 10.24 seconds. + * + * @param[in] window Milliseconds period during which the device + * listens to advertising channels. The value of the scan window is in + * the range of 2.5ms to 10.24s. + * + * @param[in] timeout Duration in seconds of the scan procedure. The special + * value 0 may be used when the scan procedure is not time bounded. + * + * @param[in] activeScanning If true, then the scanner sends scan requests to + * to scannable or connectable advertiser. Advertisers may respond to the + * scan request by a scan response containing the scan response payload. If + * false, the scanner does not send any request. + * + * @note If interval is equal to window + */ + GapScanningParams( + uint16_t interval = SCAN_INTERVAL_MAX, + uint16_t window = SCAN_WINDOW_MAX, + uint16_t timeout = 0, + bool activeScanning = false + ); + + /** + * Number of microseconds in 0.625 milliseconds. + */ + static const uint16_t UNIT_0_625_MS = 625; + /** * Convert milliseconds to units of 0.625ms. * - * @param[in] durationInMillis - * The number of milliseconds to convert. + * @param[in] durationInMillis Milliseconds to convert. * * @return The value of @p durationInMillis in units of 0.625ms. */ - static uint16_t MSEC_TO_SCAN_DURATION_UNITS(uint32_t durationInMillis) { + static uint16_t MSEC_TO_SCAN_DURATION_UNITS(uint32_t durationInMillis) + { return (durationInMillis * 1000) / UNIT_0_625_MS; } /** - * Set the scan interval. + * Update the scan interval. * - * @param[in] newIntervalInMS - * New scan interval in milliseconds. + * @param[in] newIntervalInMS New scan interval in milliseconds. * * @return BLE_ERROR_NONE if the new scan interval was set successfully. */ ble_error_t setInterval(uint16_t newIntervalInMS); /** - * Set the scan window. + * Update the scan window. * - * @param[in] newWindowInMS - * New scan window in milliseconds. + * @param[in] newWindowInMS New scan window in milliseconds. * * @return BLE_ERROR_NONE if the new scan window was set successfully. */ ble_error_t setWindow(uint16_t newWindowInMS); /** - * Set the scan timeout. + * Update the scan timeout. * - * @param[in] newTimeout - * New scan timeout in seconds. + * @param[in] newTimeout New scan timeout in seconds. * * @return BLE_ERROR_NONE if the new scan window was set successfully. */ ble_error_t setTimeout(uint16_t newTimeout); /** - * Set active scanning. This is used to fetch the scan response from a peer - * if possible. + * Update the active scanning flag. * - * @param[in] activeScanning - * The new boolean value of active scanning. + * @param[in] activeScanning New boolean value of active scanning. */ void setActiveScanning(bool activeScanning); @@ -106,7 +171,8 @@ class GapScanningParams { * * @return the scan interval in units of 0.625ms. */ - uint16_t getInterval(void) const { + uint16_t getInterval(void) const + { return _interval; } @@ -115,7 +181,8 @@ class GapScanningParams { * * @return the scan window in units of 0.625ms. */ - uint16_t getWindow(void) const { + uint16_t getWindow(void) const + { return _window; } @@ -124,7 +191,8 @@ class GapScanningParams { * * @return The scan timeout in seconds. */ - uint16_t getTimeout(void) const { + uint16_t getTimeout(void) const + { return _timeout; } @@ -133,15 +201,31 @@ class GapScanningParams { * * @return True if active scanning is set, false otherwise. */ - bool getActiveScanning(void) const { + bool getActiveScanning(void) const + { return _activeScanning; } private: - uint16_t _interval; /**< Scan interval in units of 625us (between 2.5ms and 10.24s). */ - uint16_t _window; /**< Scan window in units of 625us (between 2.5ms and 10.24s). */ - uint16_t _timeout; /**< Scan timeout between 0x0001 and 0xFFFF in seconds; 0x0000 disables timeout. */ - bool _activeScanning; /**< Obtain the peer device's advertising data and (if possible) scanResponse. */ + /** + * Scan interval in units of 625us (between 2.5ms and 10.24s). + */ + uint16_t _interval; + + /** + * Scan window in units of 625us (between 2.5ms and 10.24s). + */ + uint16_t _window; + + /** + * Scan timeout between 0x0001 and 0xFFFF in seconds; 0x0000 disables timeout. + */ + uint16_t _timeout; + + /** + * Obtain the peer device's advertising data and (if possible) scanResponse. + */ + bool _activeScanning; private: /* Disallow copy constructor. */ @@ -149,4 +233,9 @@ class GapScanningParams { GapScanningParams& operator =(const GapScanningParams &in); }; -#endif /* ifndef __GAP_SCANNING_PARAMS_H__ */ +/** + * @} + * @} + */ + +#endif /* ifndef MBED_GAP_SCANNING_PARAMS_H__ */ diff --git a/features/FEATURE_BLE/ble/GattAttribute.h b/features/FEATURE_BLE/ble/GattAttribute.h index 1011bc0d53c..2423301464d 100644 --- a/features/FEATURE_BLE/ble/GattAttribute.h +++ b/features/FEATURE_BLE/ble/GattAttribute.h @@ -14,74 +14,132 @@ * limitations under the License. */ -#ifndef __GATT_ATTRIBUTE_H__ -#define __GATT_ATTRIBUTE_H__ +#ifndef MBED_GATT_ATTRIBUTE_H__ +#define MBED_GATT_ATTRIBUTE_H__ #include "UUID.h" #include "BLETypes.h" /** - * Instances of this class encapsulate the data that belongs to a Bluetooth Low - * Energy attribute. + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup server + * @{ + */ + +/** + * Representation of a GattServer attribute. + * + * Attributes are the building block of GATT servers: services are attributes, + * characteristics are groups of attributes and characteristic descriptors are + * attributes, too. + * + * @par Typed values + * + * Attributes are typed values composed of a type and its associated value. The + * attribute type identifies the attribute purpose. A UUID read by the client + * during the discovery of the GATT server models the attribute type. The value of the + * attribute is an array of bytes; its length may be fixed or variable. + * + * As an example, a primary service is declared by an attribute with the type + * 0x2800, and the value of the attribute is the UUID of the service. + * + * @par Attribute Access + * + * The GATT server is an array of attributes in which a unique index identifies + * each of the attributes within the array. That index is called the attribute + * handle, and clients use it to access to attributes within the server. + * + * @note Attributes do not contain information related to their permissions, + * grouping or semantic. Higher level specifications define these concepts. */ class GattAttribute { public: /** - * Type for the handle or ID of the attribute in the ATT table. These are - * unique and are usually generated by the underlying BLE stack. + * Representation of an attribute handle. + * + * Each attribute in a GattServer has a unique handle that clients can use + * to identify the attribute. The underlying BLE stack usually + * generates and assigns handles to attributes. */ typedef ble::attribute_handle_t Handle_t; + /** - * Define the value of an invalid attribute handle. + * Invalid attribute handle. */ static const Handle_t INVALID_HANDLE = 0x0000; public: /** - * @brief Creates a new GattAttribute using the specified - * UUID, value length, and inital value. - * - * @param[in] uuid - * The UUID to use for this attribute. - * @param[in] valuePtr - * The memory holding the initial value. - * @param[in] len - * The length in bytes of this attribute's value. - * @param[in] maxLen - * The max length in bytes of this attribute's value. - * @param[in] hasVariableLen - * Whether the attribute's value length changes overtime. + * Construct an attribute. * - * @section EXAMPLE + * Application code uses attributes to model characteristic descriptors and + * characteristics values. * - * @code + * @param[in] uuid The type of the attribute. + * @param[in] valuePtr Pointer to the memory buffer, which contains the + * initial value of the attribute. The constructor does not make a copy of + * the attribute buffer; as a consequence, the memory buffer must remain + * valid during the lifetime of the attribute. + * @param[in] len The length in bytes of this attribute's value. + * @param[in] maxLen The length in bytes of the memory buffer containing the + * attribute value. It must be greater than or equal to @p len. + * @param[in] hasVariableLen Flag that indicates whether the attribute's value + * length can change throughout time. * - * // UUID = 0x2A19, Min length 2, Max len = 2 - * GattAttribute attr = GattAttribute(0x2A19, &someValue, 2, 2); + * @par Example * - * @endcode - */ - GattAttribute(const UUID &uuid, uint8_t *valuePtr = NULL, uint16_t len = 0, uint16_t maxLen = 0, bool hasVariableLen = true) : - _uuid(uuid), _valuePtr(valuePtr), _lenMax(maxLen), _len(len), _hasVariableLen(hasVariableLen), _handle() { - /* Empty */ + * @code + * // declare a value of 2 bytes within a 10 bytes buffer + * const uint8_t attribute_value[10] = { 10, 50 }; + * GattAttribute attr = GattAttribute( + * 0x2A19, // attribute type + * attribute_value, + * 2, // length of the current value + * sizeof(attribute_value), // length of the buffer containing the value + * true // variable length + * ); + * @endcode + */ + GattAttribute( + const UUID &uuid, + uint8_t *valuePtr = NULL, + uint16_t len = 0, + uint16_t maxLen = 0, + bool hasVariableLen = true + ) : _uuid(uuid), + _valuePtr(valuePtr), + _lenMax(maxLen), + _len(len), + _hasVariableLen(hasVariableLen), + _handle() { } public: /** * Get the attribute's handle in the ATT table. * + * @note The GattServer sets the attribute's handle when services are + * inserted. + * * @return The attribute's handle. */ - Handle_t getHandle(void) const { + Handle_t getHandle(void) const + { return _handle; } /** - * The UUID of the characteristic that this attribute belongs to. + * Get the UUID of the attribute. * - * @return The characteristic's UUID. + * The UUID identifies the type of the attribute. + * + * @return The attribute. */ - const UUID &getUUID(void) const { + const UUID &getUUID(void) const + { return _uuid; } @@ -90,7 +148,8 @@ class GattAttribute { * * @return The current length of the attribute value. */ - uint16_t getLength(void) const { + uint16_t getLength(void) const + { return _len; } @@ -99,26 +158,33 @@ class GattAttribute { * * The maximum length of the attribute value. */ - uint16_t getMaxLength(void) const { + uint16_t getMaxLength(void) const + { return _lenMax; } /** * Get a pointer to the current length of the attribute value. * + * @important note Do not use this function. + * * @return A pointer to the current length of the attribute value. */ - uint16_t *getLengthPtr(void) { + uint16_t *getLengthPtr(void) + { return &_len; } /** * Set the attribute handle. * - * @param[in] id - * The new attribute handle. + * @important The GattServer uses this function internally. + * Application code must not use it. + * + * @param[in] id The new attribute handle. */ - void setHandle(Handle_t id) { + void setHandle(Handle_t id) + { _handle = id; } @@ -127,16 +193,19 @@ class GattAttribute { * * @return A pointer to the attribute value. */ - uint8_t *getValuePtr(void) { + uint8_t *getValuePtr(void) + { return _valuePtr; } /** - * Check whether the length of the attribute's value can change over time. + * Check whether the length of the attribute's value can change throughout time. * - * @return true if the attribute has variable length, false otherwise. + * @return true if the attribute value has a variable length and false + * otherwise. */ - bool hasVariableLength(void) const { + bool hasVariableLength(void) const + { return _hasVariableLen; } @@ -144,27 +213,32 @@ class GattAttribute { /** * Characteristic's UUID. */ - UUID _uuid; + UUID _uuid; + /** * Pointer to the attribute's value. */ - uint8_t *_valuePtr; + uint8_t *_valuePtr; + /** - * Maximum length of the value pointed to by GattAttribute::_valuePtr. + * Length in byte of the buffer containing the attribute value. */ - uint16_t _lenMax; + uint16_t _lenMax; + /** * Current length of the value pointed to by GattAttribute::_valuePtr. */ - uint16_t _len; + uint16_t _len; + /** - * Whether the length of the value can change over time. + * Whether the length of the value can change throughout time. */ - bool _hasVariableLen; + bool _hasVariableLen; + /** * The attribute's handle in the ATT table. */ - Handle_t _handle; + Handle_t _handle; private: /* Disallow copy and assignment. */ @@ -172,4 +246,10 @@ class GattAttribute { GattAttribute& operator=(const GattAttribute &); }; -#endif /* ifndef __GATT_ATTRIBUTE_H__ */ +/** + * @} + * @} + * @} + */ + +#endif /* ifndef MBED_GATT_ATTRIBUTE_H__ */ diff --git a/features/FEATURE_BLE/ble/GattCallbackParamTypes.h b/features/FEATURE_BLE/ble/GattCallbackParamTypes.h index d8eb362235d..50c16ba938c 100644 --- a/features/FEATURE_BLE/ble/GattCallbackParamTypes.h +++ b/features/FEATURE_BLE/ble/GattCallbackParamTypes.h @@ -14,139 +14,377 @@ * limitations under the License. */ -#ifndef __GATT_CALLBACK_PARAM_TYPES_H__ -#define __GATT_CALLBACK_PARAM_TYPES_H__ +#ifndef MBED_BLE_GATT_CALLBACK_PARAM_TYPES_H__ +#define MBED_BLE_GATT_CALLBACK_PARAM_TYPES_H__ /** - * Parameter of the callback invoked on a write operation. - * This parameter is used whether a GattServer as received a write operation or - * if the GattClient has completed a write operation. + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + */ + +/** + * GATT Write event definition. + * + * Instances of this type are created and passed to user registered callbacks + * whether the GattServer has received a write request or a GattClient has + * received a write response. + * + * @important The GattServer only populates the fields offset, len and data + * when it has received a write request. Callbacks attached to the GattClient + * do not use those fields. * - * @important The fields connHandle, handle and writeOp are used in both - * callbacks while: - * - offset, len and data are reserved for GattServer write callbacks. - * - status and error_code are reserved for GattClient write callbacks. + * @important The GattClient only populates the fields status and error_code + * when it has received a write response. Callbacks attached to the GattServer + * do not use those fields. */ struct GattWriteCallbackParams { /** - * Enumeration for write operations. + * Enumeration of allowed write operations. */ enum WriteOp_t { - OP_INVALID = 0x00, /**< Invalid operation. */ - OP_WRITE_REQ = 0x01, /**< Write request. */ - OP_WRITE_CMD = 0x02, /**< Write command. */ - OP_SIGN_WRITE_CMD = 0x03, /**< Signed write command. */ - OP_PREP_WRITE_REQ = 0x04, /**< Prepare write request. */ - OP_EXEC_WRITE_REQ_CANCEL = 0x05, /**< Execute write request: cancel all prepared writes. */ - OP_EXEC_WRITE_REQ_NOW = 0x06, /**< Execute write request: immediately execute all prepared writes. */ + /** + * Invalid operation. + */ + OP_INVALID = 0x00, + + /** + * Write request. + */ + OP_WRITE_REQ = 0x01, + + /** + * Write command. + */ + OP_WRITE_CMD = 0x02, + + /** + * Signed write command. + */ + OP_SIGN_WRITE_CMD = 0x03, + + /** + * Prepare write request. + */ + OP_PREP_WRITE_REQ = 0x04, + + /** + * Execute write request: cancel all prepared writes. + */ + OP_EXEC_WRITE_REQ_CANCEL = 0x05, + + /** + * Execute write request: immediately execute all prepared writes. + */ + OP_EXEC_WRITE_REQ_NOW = 0x06, }; - Gap::Handle_t connHandle; /**< The handle of the connection that triggered the event. */ - GattAttribute::Handle_t handle; /**< Attribute Handle to which the write operation applies. */ - WriteOp_t writeOp; /**< Type of write operation. */ + /** + * Handle of the connection that triggered the event. + */ + Gap::Handle_t connHandle; + + /** + * Handle of the attribute to which the write operation applies. + */ + GattAttribute::Handle_t handle; + + /** + * Type of the write operation. + */ + WriteOp_t writeOp; - // Note: offset is used in GattServer while status is used in GattClient union { - uint16_t offset; /**< Offset for the GattServer write operation. */ - ble_error_t status; /**< Status of the GattClient Write operation */ + /** + * Offset within the attribute value to be written. + * + * @important Reserved for GattServer registered callbacks. + */ + uint16_t offset; + + /** + * Status of the GattClient Write operation. + * + * @important Reserved for GattClient registered callbacks. + */ + ble_error_t status; }; - // Note: len is used in GattServer while error_code is used in GattClient union { - uint16_t len; /**< Length (in bytes) of the data to write (GattServer). */ - uint8_t error_code; /**< Error code of the GattClient Write operation */ + /** + * Length (in bytes) of the data to write. + * + * @important Reserved for GattServer registered callbacks. + */ + uint16_t len; + + /** + * Error code of the GattClient Write operation. + * + * @important Reserved for GattClient registered callbacks. + */ + uint8_t error_code; }; /** * Pointer to the data to write. * - * @note Data might not persist beyond the callback; make a local copy if - * needed. - * @note This field is not used by callbacks invoked by the GattClient module. + * @important Data may not persist beyond the callback scope. + * + * @important Reserved for GattServer registered callbacks. */ - const uint8_t *data; + const uint8_t *data; }; /** - * Parameter of the callback invoked on a read operation. - * This parameter is used whether a GattServer as received a read operation or - * if the GattClient has completed a read operation. + * GATT Read event definition. * - * @important The fields connHandle, handle and offset are used in both - * callbacks while: - * - len and data are reserved for GattServer read callbacks. - * - status and error_code are reserved for GattClient read callbacks. + * Instances of this type are created and passed to user registered callbacks + * whether the GattServer has received a read request or a GattClient has + * received a read response. + * + * @important The GattClient only populates the fields status and error_code + * when it has received a read response. Callbacks attached to the GattServer + * do not use those fields. */ struct GattReadCallbackParams { - Gap::Handle_t connHandle; /**< The handle of the connection that triggered the event. */ - GattAttribute::Handle_t handle; /**< Attribute Handle to which the read operation applies. */ - uint16_t offset; /**< Offset for the read operation. */ + /** + * Handle of the connection that triggered the event. + */ + Gap::Handle_t connHandle; + + /** + * Attribute Handle to which the read operation applies. + */ + GattAttribute::Handle_t handle; + + /** + * Offset within the attribute value read. + */ + uint16_t offset; + union { - uint16_t len; /**< Length (in bytes) of the data to read. */ - uint8_t error_code; /**< Error code if any (GattClient) */ + /** + * Length in bytes of the data read. + */ + uint16_t len; + + /** + * Error code of the GattClient read operation. + * + * @important Reserved for GattClient registered callbacks. + * + * @important set if status is not equal to BLE_ERROR_NONE; otherwise, + * this field is interpreted as len. + */ + uint8_t error_code; }; /** * Pointer to the data read. * - * @note Data might not persist beyond the callback; make a local copy if - * needed. + * @important Data may not persist beyond the callback scope. */ - const uint8_t *data; - ble_error_t status; /**< Status of the operation BLE_ERROR_NONE in case of success or the error in case of error */ + const uint8_t *data; + + /** + * Status of the GattClient Read operation. + * + * @important Reserved for GattClient registered callbacks. + */ + ble_error_t status; }; +/** + * @addtogroup server + * @{ + */ + +/** + * Enumeration of allowed values returned by read or write authorization process. + */ enum GattAuthCallbackReply_t { - AUTH_CALLBACK_REPLY_SUCCESS = 0x00, /**< Success. */ - AUTH_CALLBACK_REPLY_ATTERR_INVALID_HANDLE = 0x0101, /**< ATT Error: Invalid attribute handle. */ - AUTH_CALLBACK_REPLY_ATTERR_READ_NOT_PERMITTED = 0x0102, /**< ATT Error: Read not permitted. */ - AUTH_CALLBACK_REPLY_ATTERR_WRITE_NOT_PERMITTED = 0x0103, /**< ATT Error: Write not permitted. */ - AUTH_CALLBACK_REPLY_ATTERR_INSUF_AUTHENTICATION = 0x0105, /**< ATT Error: Authenticated link required. */ - AUTH_CALLBACK_REPLY_ATTERR_INVALID_OFFSET = 0x0107, /**< ATT Error: The specified offset was past the end of the attribute. */ - AUTH_CALLBACK_REPLY_ATTERR_INSUF_AUTHORIZATION = 0x0108, /**< ATT Error: Used in ATT as "insufficient authorization". */ - AUTH_CALLBACK_REPLY_ATTERR_PREPARE_QUEUE_FULL = 0x0109, /**< ATT Error: Used in ATT as "prepare queue full". */ - AUTH_CALLBACK_REPLY_ATTERR_ATTRIBUTE_NOT_FOUND = 0x010A, /**< ATT Error: Used in ATT as "attribute not found". */ - AUTH_CALLBACK_REPLY_ATTERR_ATTRIBUTE_NOT_LONG = 0x010B, /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */ - AUTH_CALLBACK_REPLY_ATTERR_INVALID_ATT_VAL_LENGTH = 0x010D, /**< ATT Error: Invalid value size. */ - AUTH_CALLBACK_REPLY_ATTERR_INSUF_RESOURCES = 0x0111, /**< ATT Error: Encrypted link required. */ + /** + * Success. + */ + AUTH_CALLBACK_REPLY_SUCCESS = 0x00, + + /** + * ATT Error: Invalid attribute handle. + */ + AUTH_CALLBACK_REPLY_ATTERR_INVALID_HANDLE = 0x0101, + + /** + * ATT Error: Read not permitted. + */ + AUTH_CALLBACK_REPLY_ATTERR_READ_NOT_PERMITTED = 0x0102, + + /** + * ATT Error: Write not permitted. + */ + AUTH_CALLBACK_REPLY_ATTERR_WRITE_NOT_PERMITTED = 0x0103, + + /** + * ATT Error: Authenticated link required. + */ + AUTH_CALLBACK_REPLY_ATTERR_INSUF_AUTHENTICATION = 0x0105, + + /** + * ATT Error: The specified offset was past the end of the attribute. + */ + AUTH_CALLBACK_REPLY_ATTERR_INVALID_OFFSET = 0x0107, + + /** + * ATT Error: Used in ATT as "insufficient authorization". + */ + AUTH_CALLBACK_REPLY_ATTERR_INSUF_AUTHORIZATION = 0x0108, + + /** + * ATT Error: Used in ATT as "prepare queue full". + */ + AUTH_CALLBACK_REPLY_ATTERR_PREPARE_QUEUE_FULL = 0x0109, + + /** + * ATT Error: Used in ATT as "attribute not found". + */ + AUTH_CALLBACK_REPLY_ATTERR_ATTRIBUTE_NOT_FOUND = 0x010A, + + /** + * ATT Error: Attribute cannot be read or written using read/write blob + * requests. + */ + AUTH_CALLBACK_REPLY_ATTERR_ATTRIBUTE_NOT_LONG = 0x010B, + + /** + * ATT Error: Invalid value size. + */ + AUTH_CALLBACK_REPLY_ATTERR_INVALID_ATT_VAL_LENGTH = 0x010D, + + /** + * ATT Error: Encrypted link required. + */ + AUTH_CALLBACK_REPLY_ATTERR_INSUF_RESOURCES = 0x0111, }; +/** + * GATT write authorization request event. + */ struct GattWriteAuthCallbackParams { - Gap::Handle_t connHandle; /**< The handle of the connection that triggered the event. */ - GattAttribute::Handle_t handle; /**< Attribute Handle to which the write operation applies. */ - uint16_t offset; /**< Offset for the write operation. */ - uint16_t len; /**< Length of the incoming data. */ - const uint8_t *data; /**< Incoming data, variable length. */ /** - * This is the out parameter that the callback needs to set to - * AUTH_CALLBACK_REPLY_SUCCESS for the request to proceed. + * Handle of the connection that triggered the event. + */ + Gap::Handle_t connHandle; + + /** + * Attribute Handle to which the write operation applies. */ - GattAuthCallbackReply_t authorizationReply; + GattAttribute::Handle_t handle; + + /** + * Offset for the write operation. + */ + uint16_t offset; + + /** + * Length of the incoming data. + */ + uint16_t len; + + /** + * Incoming data. + */ + const uint8_t *data; + + /** + * Authorization result. + * + * The callback sets this parameter. If the value is set to + * AUTH_CALLBACK_REPLY_SUCCESS, then the write request is accepted; + * otherwise, an error code is returned to the peer client. + */ + GattAuthCallbackReply_t authorizationReply; }; +/** + * GATT read authorization request event. + */ struct GattReadAuthCallbackParams { - Gap::Handle_t connHandle; /**< The handle of the connection that triggered the event. */ - GattAttribute::Handle_t handle; /**< Attribute Handle to which the read operation applies. */ - uint16_t offset; /**< Offset for the read operation. */ - uint16_t len; /**< Optional: new length of the outgoing data. */ - uint8_t *data; /**< Optional: new outgoing data. Leave at NULL if data is unchanged. */ /** - * This is the out parameter that the callback needs to set to - * AUTH_CALLBACK_REPLY_SUCCESS for the request to proceed. + * The handle of the connection that triggered the event. + */ + Gap::Handle_t connHandle; + + /** + * Attribute Handle to which the read operation applies. */ - GattAuthCallbackReply_t authorizationReply; + GattAttribute::Handle_t handle; + + /** + * Offset for the read operation. + */ + uint16_t offset; + + /** + * Optional: new length of the outgoing data. + */ + uint16_t len; + + /** + * Optional: new outgoing data. Leave at NULL if data is unchanged. + */ + uint8_t *data; + + /** + * Authorization result. + * + * The callback sets this parameter. If the value is set to + * AUTH_CALLBACK_REPLY_SUCCESS, then the read request is accepted; + * otherwise, an error code is returned to the peer client. + */ + GattAuthCallbackReply_t authorizationReply; }; /** - * For encapsulating handle-value update events (notifications or indications) - * generated at the remote server. + * Handle Value Notification/Indication event. + * + * The GattClient generates this type of event upon the reception of a + * Handle Value Notification or Indication. + * + * The event is passed to callbacks registered by GattClient::onHVX(). */ struct GattHVXCallbackParams { - Gap::Handle_t connHandle; /**< The handle of the connection that triggered the event. */ - GattAttribute::Handle_t handle; /**< Attribute Handle to which the HVx operation applies. */ - HVXType_t type; /**< Indication or Notification, see HVXType_t. */ - uint16_t len; /**< Attribute data length. */ - const uint8_t *data; /**< Attribute data, variable length. */ + /** + * The handle of the connection that triggered the event. + */ + Gap::Handle_t connHandle; + + /** + * Attribute Handle to which the HVx operation applies. + */ + GattAttribute::Handle_t handle; + + /** + * Indication or Notification, see HVXType_t. + */ + HVXType_t type; + + /** + * Attribute value length. + */ + uint16_t len; + + /** + * Attribute value. + */ + const uint8_t *data; + }; -#endif /*__GATT_CALLBACK_PARAM_TYPES_H__*/ +/** + * @} + * @} + * @} + */ + +#endif /*MBED_BLE_GATT_CALLBACK_PARAM_TYPES_H__*/ diff --git a/features/FEATURE_BLE/ble/GattCharacteristic.h b/features/FEATURE_BLE/ble/GattCharacteristic.h index c21d99111b7..a192563e2ff 100644 --- a/features/FEATURE_BLE/ble/GattCharacteristic.h +++ b/features/FEATURE_BLE/ble/GattCharacteristic.h @@ -23,319 +23,1353 @@ #include "GattCallbackParamTypes.h" #include "FunctionPointerWithContext.h" +/** + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup server + * @{ + */ + +/** + * Representation of a GattServer characteristic. + * + * A characteristic is a typed value enclosed in a GATT service (GattService). + * + * @par Type + * + * The type of the value defines the purpose of the characteristic, and a + * UUID represents it. Standard characteristic types may be consulted at + * https://www.bluetooth.com/specifications/gatt/characteristics + * + * @par Supported operations + * A set of properties define what client operations the characteristic + * supports. See GattServer::Properties_t + * + * @par Descriptors + * + * Additional information, such as the unit of the characteristic value, a + * description string or a client control point, can be added to the + * characteristic. + * + * See BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] - 3.3.1.1 + * + * One of the most important types of descriptor is the Client Characteristic + * Configuration Descriptor (CCCD) that must be present if the characteristic + * properties allow a client to subscribe to updates of the characteristic + * value. + * + * @par Characteristic breakdown + * + * A characteristic is composed of several GATT attributes (GattAttribute): + * - Characteristic declaration: It contains the properties of the + * characteristic, its type and the handle of its value. + * - Characteristic value: The value of the characteristic. + * - Descriptors: A single GATT attribute stores each descriptor. + * + * When the GattService containing the characteristic is registered in the + * GattServer, a unique attribute handle is assigned to the various attributes + * of the characteristic. Clients use this handle to interact with the + * characteristic. This handle is used locally in GattServer APIs. + * + * + * + * + * + * + * + * + * Representation of a GattServer characteristic. + * + * A characteristic is a typed value used in a service. It contains a set of + * properties that define client operations supported by the characteristic. + * A characteristic may also include descriptors; a descriptor exposes + * metainformation associated to a characteristic, such as the unit of its value, + * its human readable name or a control point attribute that allows the client to + * subscribe to the characteristic notifications. + * + * The GattCharacteristic class allows application code to construct + * and monitor characteristics presents in a GattServer. + */ class GattCharacteristic { public: + + /* + * Enumeration of characteristic UUID defined by the Bluetooth body. + */ enum { - UUID_BATTERY_LEVEL_STATE_CHAR = 0x2A1B, - UUID_BATTERY_POWER_STATE_CHAR = 0x2A1A, - UUID_REMOVABLE_CHAR = 0x2A3A, - UUID_SERVICE_REQUIRED_CHAR = 0x2A3B, - UUID_ALERT_CATEGORY_ID_CHAR = 0x2A43, - UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR = 0x2A42, - UUID_ALERT_LEVEL_CHAR = 0x2A06, - UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR = 0x2A44, - UUID_ALERT_STATUS_CHAR = 0x2A3F, - UUID_BATTERY_LEVEL_CHAR = 0x2A19, - UUID_BLOOD_PRESSURE_FEATURE_CHAR = 0x2A49, - UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR = 0x2A35, - UUID_BODY_SENSOR_LOCATION_CHAR = 0x2A38, - UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR = 0x2A22, - UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR = 0x2A32, - UUID_BOOT_MOUSE_INPUT_REPORT_CHAR = 0x2A33, - UUID_CURRENT_TIME_CHAR = 0x2A2B, - UUID_DATE_TIME_CHAR = 0x2A08, - UUID_DAY_DATE_TIME_CHAR = 0x2A0A, - UUID_DAY_OF_WEEK_CHAR = 0x2A09, - UUID_DST_OFFSET_CHAR = 0x2A0D, - UUID_EXACT_TIME_256_CHAR = 0x2A0C, - UUID_FIRMWARE_REVISION_STRING_CHAR = 0x2A26, - UUID_GLUCOSE_FEATURE_CHAR = 0x2A51, - UUID_GLUCOSE_MEASUREMENT_CHAR = 0x2A18, - UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR = 0x2A34, - UUID_HARDWARE_REVISION_STRING_CHAR = 0x2A27, - UUID_HEART_RATE_CONTROL_POINT_CHAR = 0x2A39, - UUID_HEART_RATE_MEASUREMENT_CHAR = 0x2A37, - UUID_HID_CONTROL_POINT_CHAR = 0x2A4C, - UUID_HID_INFORMATION_CHAR = 0x2A4A, - UUID_HUMIDITY_CHAR = 0x2A6F, + /** + * Not used in actual BLE service. + */ + UUID_BATTERY_LEVEL_STATE_CHAR = 0x2A1B, + + /** + * Not used in actual BLE service. + */ + UUID_BATTERY_POWER_STATE_CHAR = 0x2A1A, + + /** + * Not used in actual BLE service. + */ + UUID_REMOVABLE_CHAR = 0x2A3A, + + /** + * Not used in actual BLE service. + */ + UUID_SERVICE_REQUIRED_CHAR = 0x2A3B, + + /** + * Not used as a characteristic UUID. + */ + UUID_ALERT_CATEGORY_ID_CHAR = 0x2A43, + + /** + * Not used as a characteristic UUID. + */ + UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR = 0x2A42, + + /** + * Control point of the Immediate Alert service that allows the client to + * command the server to alert to a given level. + */ + UUID_ALERT_LEVEL_CHAR = 0x2A06, + + /** + * Control point of the Alert Notification service that allows the client + * finely tune the notification configuration. + */ + UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR = 0x2A44, + + /** + * Part of the Alert Notification service, which exposes the count of + * unread alert events existing in the server. + */ + UUID_ALERT_STATUS_CHAR = 0x2A3F, + + /** + * Characteristic of the Battery service, which exposes the current + * battery level as a percentage. + */ + UUID_BATTERY_LEVEL_CHAR = 0x2A19, + + /** + * Describe the features supported by the blood pressure sensor exposed + * by the Blood Pressure service. + */ + UUID_BLOOD_PRESSURE_FEATURE_CHAR = 0x2A49, + + /** + * Characteristic of the Blood Pressure service that exposes the + * measurement of the blood sensor. + */ + UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR = 0x2A35, + + /** + * Characteristic of the Heart Rate service that indicate the intended + * location of the heart rate monitor. + */ + UUID_BODY_SENSOR_LOCATION_CHAR = 0x2A38, + + /** + * Part of the Human Interface Device service. + */ + UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR = 0x2A22, + + /** + * Part of the Human Interface Device service. + */ + UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR = 0x2A32, + + /** + * Part of the Human Interface Device service. + */ + UUID_BOOT_MOUSE_INPUT_REPORT_CHAR = 0x2A33, + + /** + * Characteristic of the Current Time service that contains the current + * time. + */ + UUID_CURRENT_TIME_CHAR = 0x2A2B, + + /** + * Not used in a service as a characteristic. + */ + UUID_DATE_TIME_CHAR = 0x2A08, + + /** + * Not used in a service as a characteristic. + */ + UUID_DAY_DATE_TIME_CHAR = 0x2A0A, + + /** + * Not used in a service as a characteristic. + */ + UUID_DAY_OF_WEEK_CHAR = 0x2A09, + + /** + * Not used in a service as a characteristic. + */ + UUID_DST_OFFSET_CHAR = 0x2A0D, + + /** + * Not used in a service as a characteristic. + */ + UUID_EXACT_TIME_256_CHAR = 0x2A0C, + + /** + * Characteristic of the Device Information Service that contains a + * UTF8 string representing the firmware revision for the firmware within + * the device. + */ + UUID_FIRMWARE_REVISION_STRING_CHAR = 0x2A26, + + /** + * Characteristic of the Glucose service that exposes features supported + * by the server. + */ + UUID_GLUCOSE_FEATURE_CHAR = 0x2A51, + + /** + * Characteristic of the Glucose service that exposes glucose + * measurements. + */ + UUID_GLUCOSE_MEASUREMENT_CHAR = 0x2A18, + + /** + * Characteristic of the Glucose service that sends additional + * information related to the glucose measurements. + */ + UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR = 0x2A34, + + /** + * Characteristic of the Device Information Service that contains a + * UTF8 string representing the hardware revision of the device. + */ + UUID_HARDWARE_REVISION_STRING_CHAR = 0x2A27, + + /** + * Characteristic of the Heart Rate service used by the client to control + * the service behavior. + */ + UUID_HEART_RATE_CONTROL_POINT_CHAR = 0x2A39, + + /** + * Characteristic of the Heart Rate that sends heart rate measurements to + * registered clients. + */ + UUID_HEART_RATE_MEASUREMENT_CHAR = 0x2A37, + + /** + * Part of the Human Interface Device service. + */ + UUID_HID_CONTROL_POINT_CHAR = 0x2A4C, + + /** + * Part of the Human Interface Device service. + */ + UUID_HID_INFORMATION_CHAR = 0x2A4A, + + /** + * Characteristic of the Environmental Sensing service, which exposes + * humidity measurements. + */ + UUID_HUMIDITY_CHAR = 0x2A6F, + + /** + * Characteristic of the Device Information Service, which exposes + * various regulatory or certification compliance items to which the + * device claims adherence. + */ UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR = 0x2A2A, - UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR = 0x2A36, - UUID_INTERMEDIATE_TEMPERATURE_CHAR = 0x2A1E, - UUID_LOCAL_TIME_INFORMATION_CHAR = 0x2A0F, - UUID_MANUFACTURER_NAME_STRING_CHAR = 0x2A29, - UUID_MEASUREMENT_INTERVAL_CHAR = 0x2A21, - UUID_MODEL_NUMBER_STRING_CHAR = 0x2A24, - UUID_UNREAD_ALERT_CHAR = 0x2A45, - UUID_NEW_ALERT_CHAR = 0x2A46, - UUID_PNP_ID_CHAR = 0x2A50, - UUID_PRESSURE_CHAR = 0x2A6D, - UUID_PROTOCOL_MODE_CHAR = 0x2A4E, - UUID_RECORD_ACCESS_CONTROL_POINT_CHAR = 0x2A52, - UUID_REFERENCE_TIME_INFORMATION_CHAR = 0x2A14, - UUID_REPORT_CHAR = 0x2A4D, - UUID_REPORT_MAP_CHAR = 0x2A4B, - UUID_RINGER_CONTROL_POINT_CHAR = 0x2A40, - UUID_RINGER_SETTING_CHAR = 0x2A41, - UUID_SCAN_INTERVAL_WINDOW_CHAR = 0x2A4F, - UUID_SCAN_REFRESH_CHAR = 0x2A31, - UUID_SERIAL_NUMBER_STRING_CHAR = 0x2A25, - UUID_SOFTWARE_REVISION_STRING_CHAR = 0x2A28, - UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR = 0x2A47, - UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR = 0x2A48, - UUID_SYSTEM_ID_CHAR = 0x2A23, - UUID_TEMPERATURE_CHAR = 0x2A6E, - UUID_TEMPERATURE_MEASUREMENT_CHAR = 0x2A1C, - UUID_TEMPERATURE_TYPE_CHAR = 0x2A1D, - UUID_TIME_ACCURACY_CHAR = 0x2A12, - UUID_TIME_SOURCE_CHAR = 0x2A13, - UUID_TIME_UPDATE_CONTROL_POINT_CHAR = 0x2A16, - UUID_TIME_UPDATE_STATE_CHAR = 0x2A17, - UUID_TIME_WITH_DST_CHAR = 0x2A11, - UUID_TIME_ZONE_CHAR = 0x2A0E, - UUID_TX_POWER_LEVEL_CHAR = 0x2A07, - UUID_CSC_FEATURE_CHAR = 0x2A5C, - UUID_CSC_MEASUREMENT_CHAR = 0x2A5B, - UUID_RSC_FEATURE_CHAR = 0x2A54, - UUID_RSC_MEASUREMENT_CHAR = 0x2A53 + + /** + * Characteristic of the Blood Pressure service, which exposes intermediate + * cuff pressure measurements. + */ + UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR = 0x2A36, + + /** + * Characteristic of the Health Thermometer service that sends intermediate + * temperature values while the measurement is in progress. + */ + UUID_INTERMEDIATE_TEMPERATURE_CHAR = 0x2A1E, + + /** + * Characteristic of the current Time service that exposes information + * about the local time. + */ + UUID_LOCAL_TIME_INFORMATION_CHAR = 0x2A0F, + + /** + * Characteristic of the Device Information Service that contains a + * UTF8 string representing the manufacturer name of the device. + */ + UUID_MANUFACTURER_NAME_STRING_CHAR = 0x2A29, + + /** + * Characteristic of the Health Thermometer service that exposes the + * interval time between two measurements. + */ + UUID_MEASUREMENT_INTERVAL_CHAR = 0x2A21, + + /** + * Characteristic of the Device Information Service that contains a + * UTF8 string representing the model number of the device assigned by + * the vendor. + */ + UUID_MODEL_NUMBER_STRING_CHAR = 0x2A24, + + /** + * Characteristic of the Alert Notification Service that shows how many + * numbers of unread alerts exist in the specific category in the device. + */ + UUID_UNREAD_ALERT_CHAR = 0x2A45, + + /** + * Characteristic of the Alert Notification Service that defines the + * category of the alert and how many new alerts of that category have + * occurred in the server. + */ + UUID_NEW_ALERT_CHAR = 0x2A46, + + /** + * Characteristic of the Device Information Service; it is a set of + * values used to create a device ID that is unique for this device. + */ + UUID_PNP_ID_CHAR = 0x2A50, + + /** + * Characteristic of the Environmental Sensing Service that exposes the + * pressure measured. + */ + UUID_PRESSURE_CHAR = 0x2A6D, + + /** + * Part of the Human Interface Device service. + */ + UUID_PROTOCOL_MODE_CHAR = 0x2A4E, + + /** + * Pulse Oxymeter, Glucose and Continuous Glucose Monitoring services + * use this control point to provide basic management of the patient + * record database. + */ + UUID_RECORD_ACCESS_CONTROL_POINT_CHAR = 0x2A52, + + /** + * Characteristic of the Current Time service that exposes information + * related to the current time served (accuracy, source, hours since + * update and so on). + */ + UUID_REFERENCE_TIME_INFORMATION_CHAR = 0x2A14, + + /** + * Part of the Human Interface Device service. + */ + UUID_REPORT_CHAR = 0x2A4D, + + /** + * Part of the Human Interface Device service. + */ + UUID_REPORT_MAP_CHAR = 0x2A4B, + + /** + * Characteristic of the Phone Alert Status service that allows a client + * to configure operating mode. + */ + UUID_RINGER_CONTROL_POINT_CHAR = 0x2A40, + + /** + * Characteristic of the Phone Alert Status service that returns the + * ringer setting when read. + */ + UUID_RINGER_SETTING_CHAR = 0x2A41, + + /** + * Characteristic of the Scan Parameter service that stores the client's + * scan parameters (scan interval and scan window). + */ + UUID_SCAN_INTERVAL_WINDOW_CHAR = 0x2A4F, + + /** + * Characteristic of the Scan Parameter service that sends a notification + * to a client when the server requires its latest scan parameters. + */ + UUID_SCAN_REFRESH_CHAR = 0x2A31, + + /** + * Characteristic of the Device Information Service that contains a + * UTF8 string representing the serial number of the device. + */ + UUID_SERIAL_NUMBER_STRING_CHAR = 0x2A25, + + /** + * Characteristic of the Device Information Service that contains an + * UTF8 string representing the software revision of the device. + */ + UUID_SOFTWARE_REVISION_STRING_CHAR = 0x2A28, + + /** + * Characteristic of the Alert Notification Service that notifies the + * count of new alerts for a given category to a subscribed client. + */ + UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR = 0x2A47, + + /** + * Characteristic of the Alert Notification service, which exposes + * categories of unread alert supported by the server. + */ + UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR = 0x2A48, + + /** + * Characteristic of the Device Information Service that exposes a + * structure containing an Organizationally Unique Identifier (OUI) + * followed by a manufacturer-defined identifier. The value of the + * structure is unique for each individual instance of the product. + */ + UUID_SYSTEM_ID_CHAR = 0x2A23, + + /** + * Characteristic of the Environmental Sensing service that exposes the + * temperature measurement with a resolution of 0.01 degree Celsius. + */ + UUID_TEMPERATURE_CHAR = 0x2A6E, + + /** + * Characteristic of the Health Thermometer service that sends temperature + * measurement to clients. + */ + UUID_TEMPERATURE_MEASUREMENT_CHAR = 0x2A1C, + + /** + * Characteristic of the Health Thermometer service that describes + * where the measurement takes place. + */ + UUID_TEMPERATURE_TYPE_CHAR = 0x2A1D, + + /** + * Not used in a service as a characteristic. + */ + UUID_TIME_ACCURACY_CHAR = 0x2A12, + + /** + * Not used in a service as a characteristic. + */ + UUID_TIME_SOURCE_CHAR = 0x2A13, + + /** + * Characteristic of the Reference Time service that allows clients to + * control time update. + */ + UUID_TIME_UPDATE_CONTROL_POINT_CHAR = 0x2A16, + + /** + * Characteristic of the Reference Time service that informs clients of + * the status of the time update operation. + */ + UUID_TIME_UPDATE_STATE_CHAR = 0x2A17, + + /** + * Characteristic of the Next DST Change service that returns to clients + * the time with DST. + */ + UUID_TIME_WITH_DST_CHAR = 0x2A11, + + /** + * Not used in a service as a characteristic. + */ + UUID_TIME_ZONE_CHAR = 0x2A0E, + + /** + * Characteristic of the TX Power service that exposes the current + * transmission power in dBm. + */ + UUID_TX_POWER_LEVEL_CHAR = 0x2A07, + + /** + * Characteristic of the Cycling Speed and Cadence (CSC) service that + * exposes features supported by the server. + */ + UUID_CSC_FEATURE_CHAR = 0x2A5C, + + /** + * Characteristic of the Cycling Speed and Cadence (CSC) service that + * exposes measurements made by the server. + */ + UUID_CSC_MEASUREMENT_CHAR = 0x2A5B, + + /** + * Characteristic of the Running Speed and Cadence (RSC) service that + * exposes features supported by the server. + */ + UUID_RSC_FEATURE_CHAR = 0x2A54, + + /** + * Characteristic of the Running Speed and Cadence (RSC) service that + * exposes measurements made by the server. + */ + UUID_RSC_MEASUREMENT_CHAR = 0x2A53 }; /** - * @brief Standard GATT characteristic presentation format unit types. - * These unit types are used to describe what the raw numeric - * data in a characteristic actually represents. + * Unit type of a characteristic value. * - * @note See https://developer.bluetooth.org/gatt/units/Pages/default.aspx + * These unit types are used to describe what the raw numeric data in a + * characteristic actually represents. A server can expose that information + * to its clients by adding a Characteristic Presentation Format descriptor + * to relevant characteristics. + * + * @note See https://developer.bluetooth.org/gatt/units/Pages/default.aspx */ enum { - BLE_GATT_UNIT_NONE = 0x2700, /**< No specified unit type. */ - BLE_GATT_UNIT_LENGTH_METRE = 0x2701, /**< Length, metre. */ - BLE_GATT_UNIT_MASS_KILOGRAM = 0x2702, /**< Mass, kilogram. */ - BLE_GATT_UNIT_TIME_SECOND = 0x2703, /**< Time, second. */ - BLE_GATT_UNIT_ELECTRIC_CURRENT_AMPERE = 0x2704, /**< Electric current, ampere. */ - BLE_GATT_UNIT_THERMODYNAMIC_TEMPERATURE_KELVIN = 0x2705, /**< Thermodynamic temperature, kelvin. */ - BLE_GATT_UNIT_AMOUNT_OF_SUBSTANCE_MOLE = 0x2706, /**< Amount of substance, mole. */ - BLE_GATT_UNIT_LUMINOUS_INTENSITY_CANDELA = 0x2707, /**< Luminous intensity, candela. */ - BLE_GATT_UNIT_AREA_SQUARE_METRES = 0x2710, /**< Area, square metres. */ - BLE_GATT_UNIT_VOLUME_CUBIC_METRES = 0x2711, /**< Volume, cubic metres. */ - BLE_GATT_UNIT_VELOCITY_METRES_PER_SECOND = 0x2712, /**< Velocity, metres per second. */ - BLE_GATT_UNIT_ACCELERATION_METRES_PER_SECOND_SQUARED = 0x2713, /**< Acceleration, metres per second squared. */ - BLE_GATT_UNIT_WAVENUMBER_RECIPROCAL_METRE = 0x2714, /**< Wave number reciprocal, metre. */ - BLE_GATT_UNIT_DENSITY_KILOGRAM_PER_CUBIC_METRE = 0x2715, /**< Density, kilogram per cubic metre. */ - BLE_GATT_UNIT_SURFACE_DENSITY_KILOGRAM_PER_SQUARE_METRE = 0x2716, /**< */ - BLE_GATT_UNIT_SPECIFIC_VOLUME_CUBIC_METRE_PER_KILOGRAM = 0x2717, /**< */ - BLE_GATT_UNIT_CURRENT_DENSITY_AMPERE_PER_SQUARE_METRE = 0x2718, /**< */ - BLE_GATT_UNIT_MAGNETIC_FIELD_STRENGTH_AMPERE_PER_METRE = 0x2719, /**< Magnetic field strength, ampere per metre. */ - BLE_GATT_UNIT_AMOUNT_CONCENTRATION_MOLE_PER_CUBIC_METRE = 0x271A, /**< */ - BLE_GATT_UNIT_MASS_CONCENTRATION_KILOGRAM_PER_CUBIC_METRE = 0x271B, /**< */ - BLE_GATT_UNIT_LUMINANCE_CANDELA_PER_SQUARE_METRE = 0x271C, /**< */ - BLE_GATT_UNIT_REFRACTIVE_INDEX = 0x271D, /**< */ - BLE_GATT_UNIT_RELATIVE_PERMEABILITY = 0x271E, /**< */ - BLE_GATT_UNIT_PLANE_ANGLE_RADIAN = 0x2720, /**< */ - BLE_GATT_UNIT_SOLID_ANGLE_STERADIAN = 0x2721, /**< */ - BLE_GATT_UNIT_FREQUENCY_HERTZ = 0x2722, /**< Frequency, hertz. */ - BLE_GATT_UNIT_FORCE_NEWTON = 0x2723, /**< Force, newton. */ - BLE_GATT_UNIT_PRESSURE_PASCAL = 0x2724, /**< Pressure, pascal. */ - BLE_GATT_UNIT_ENERGY_JOULE = 0x2725, /**< Energy, joule. */ - BLE_GATT_UNIT_POWER_WATT = 0x2726, /**< Power, watt. */ - BLE_GATT_UNIT_ELECTRIC_CHARGE_COULOMB = 0x2727, /**< Electrical charge, coulomb. */ - BLE_GATT_UNIT_ELECTRIC_POTENTIAL_DIFFERENCE_VOLT = 0x2728, /**< Electrical potential difference, voltage. */ - BLE_GATT_UNIT_CAPACITANCE_FARAD = 0x2729, /**< */ - BLE_GATT_UNIT_ELECTRIC_RESISTANCE_OHM = 0x272A, /**< */ - BLE_GATT_UNIT_ELECTRIC_CONDUCTANCE_SIEMENS = 0x272B, /**< */ - BLE_GATT_UNIT_MAGNETIC_FLEX_WEBER = 0x272C, /**< */ - BLE_GATT_UNIT_MAGNETIC_FLEX_DENSITY_TESLA = 0x272D, /**< */ - BLE_GATT_UNIT_INDUCTANCE_HENRY = 0x272E, /**< */ - BLE_GATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_CELSIUS = 0x272F, /**< */ - BLE_GATT_UNIT_LUMINOUS_FLUX_LUMEN = 0x2730, /**< */ - BLE_GATT_UNIT_ILLUMINANCE_LUX = 0x2731, /**< */ - BLE_GATT_UNIT_ACTIVITY_REFERRED_TO_A_RADIONUCLIDE_BECQUEREL = 0x2732, /**< */ - BLE_GATT_UNIT_ABSORBED_DOSE_GRAY = 0x2733, /**< */ - BLE_GATT_UNIT_DOSE_EQUIVALENT_SIEVERT = 0x2734, /**< */ - BLE_GATT_UNIT_CATALYTIC_ACTIVITY_KATAL = 0x2735, /**< */ - BLE_GATT_UNIT_DYNAMIC_VISCOSITY_PASCAL_SECOND = 0x2740, /**< */ - BLE_GATT_UNIT_MOMENT_OF_FORCE_NEWTON_METRE = 0x2741, /**< */ - BLE_GATT_UNIT_SURFACE_TENSION_NEWTON_PER_METRE = 0x2742, /**< */ - BLE_GATT_UNIT_ANGULAR_VELOCITY_RADIAN_PER_SECOND = 0x2743, /**< */ - BLE_GATT_UNIT_ANGULAR_ACCELERATION_RADIAN_PER_SECOND_SQUARED = 0x2744, /**< */ - BLE_GATT_UNIT_HEAT_FLUX_DENSITY_WATT_PER_SQUARE_METRE = 0x2745, /**< */ - BLE_GATT_UNIT_HEAT_CAPACITY_JOULE_PER_KELVIN = 0x2746, /**< */ - BLE_GATT_UNIT_SPECIFIC_HEAT_CAPACITY_JOULE_PER_KILOGRAM_KELVIN = 0x2747, /**< */ - BLE_GATT_UNIT_SPECIFIC_ENERGY_JOULE_PER_KILOGRAM = 0x2748, /**< */ - BLE_GATT_UNIT_THERMAL_CONDUCTIVITY_WATT_PER_METRE_KELVIN = 0x2749, /**< */ - BLE_GATT_UNIT_ENERGY_DENSITY_JOULE_PER_CUBIC_METRE = 0x274A, /**< */ - BLE_GATT_UNIT_ELECTRIC_FIELD_STRENGTH_VOLT_PER_METRE = 0x274B, /**< */ - BLE_GATT_UNIT_ELECTRIC_CHARGE_DENSITY_COULOMB_PER_CUBIC_METRE = 0x274C, /**< */ - BLE_GATT_UNIT_SURFACE_CHARGE_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274D, /**< */ - BLE_GATT_UNIT_ELECTRIC_FLUX_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274E, /**< */ - BLE_GATT_UNIT_PERMITTIVITY_FARAD_PER_METRE = 0x274F, /**< */ - BLE_GATT_UNIT_PERMEABILITY_HENRY_PER_METRE = 0x2750, /**< */ - BLE_GATT_UNIT_MOLAR_ENERGY_JOULE_PER_MOLE = 0x2751, /**< */ - BLE_GATT_UNIT_MOLAR_ENTROPY_JOULE_PER_MOLE_KELVIN = 0x2752, /**< */ - BLE_GATT_UNIT_EXPOSURE_COULOMB_PER_KILOGRAM = 0x2753, /**< */ - BLE_GATT_UNIT_ABSORBED_DOSE_RATE_GRAY_PER_SECOND = 0x2754, /**< */ - BLE_GATT_UNIT_RADIANT_INTENSITY_WATT_PER_STERADIAN = 0x2755, /**< */ - BLE_GATT_UNIT_RADIANCE_WATT_PER_SQUARE_METRE_STERADIAN = 0x2756, /**< */ - BLE_GATT_UNIT_CATALYTIC_ACTIVITY_CONCENTRATION_KATAL_PER_CUBIC_METRE = 0x2757, /**< */ - BLE_GATT_UNIT_TIME_MINUTE = 0x2760, /**< Time, minute. */ - BLE_GATT_UNIT_TIME_HOUR = 0x2761, /**< Time, hour. */ - BLE_GATT_UNIT_TIME_DAY = 0x2762, /**< Time, day. */ - BLE_GATT_UNIT_PLANE_ANGLE_DEGREE = 0x2763, /**< */ - BLE_GATT_UNIT_PLANE_ANGLE_MINUTE = 0x2764, /**< */ - BLE_GATT_UNIT_PLANE_ANGLE_SECOND = 0x2765, /**< */ - BLE_GATT_UNIT_AREA_HECTARE = 0x2766, /**< */ - BLE_GATT_UNIT_VOLUME_LITRE = 0x2767, /**< */ - BLE_GATT_UNIT_MASS_TONNE = 0x2768, /**< */ - BLE_GATT_UNIT_PRESSURE_BAR = 0x2780, /**< Pressure, bar. */ - BLE_GATT_UNIT_PRESSURE_MILLIMETRE_OF_MERCURY = 0x2781, /**< Pressure, millimetre of mercury. */ - BLE_GATT_UNIT_LENGTH_ANGSTROM = 0x2782, /**< */ - BLE_GATT_UNIT_LENGTH_NAUTICAL_MILE = 0x2783, /**< */ - BLE_GATT_UNIT_AREA_BARN = 0x2784, /**< */ - BLE_GATT_UNIT_VELOCITY_KNOT = 0x2785, /**< */ - BLE_GATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_NEPER = 0x2786, /**< */ - BLE_GATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_BEL = 0x2787, /**< */ - BLE_GATT_UNIT_LENGTH_YARD = 0x27A0, /**< Length, yard. */ - BLE_GATT_UNIT_LENGTH_PARSEC = 0x27A1, /**< Length, parsec. */ - BLE_GATT_UNIT_LENGTH_INCH = 0x27A2, /**< Length, inch. */ - BLE_GATT_UNIT_LENGTH_FOOT = 0x27A3, /**< Length, foot. */ - BLE_GATT_UNIT_LENGTH_MILE = 0x27A4, /**< Length, mile. */ - BLE_GATT_UNIT_PRESSURE_POUND_FORCE_PER_SQUARE_INCH = 0x27A5, /**< */ - BLE_GATT_UNIT_VELOCITY_KILOMETRE_PER_HOUR = 0x27A6, /**< Velocity, kilometre per hour. */ - BLE_GATT_UNIT_VELOCITY_MILE_PER_HOUR = 0x27A7, /**< Velocity, mile per hour. */ - BLE_GATT_UNIT_ANGULAR_VELOCITY_REVOLUTION_PER_MINUTE = 0x27A8, /**< Angular Velocity, revolution per minute. */ - BLE_GATT_UNIT_ENERGY_GRAM_CALORIE = 0x27A9, /**< Energy, gram calorie. */ - BLE_GATT_UNIT_ENERGY_KILOGRAM_CALORIE = 0x27AA, /**< Energy, kilogram calorie. */ - BLE_GATT_UNIT_ENERGY_KILOWATT_HOUR = 0x27AB, /**< Energy, killowatt hour. */ - BLE_GATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_FAHRENHEIT = 0x27AC, /**< */ - BLE_GATT_UNIT_PERCENTAGE = 0x27AD, /**< Percentage. */ - BLE_GATT_UNIT_PER_MILLE = 0x27AE, /**< */ - BLE_GATT_UNIT_PERIOD_BEATS_PER_MINUTE = 0x27AF, /**< */ - BLE_GATT_UNIT_ELECTRIC_CHARGE_AMPERE_HOURS = 0x27B0, /**< */ - BLE_GATT_UNIT_MASS_DENSITY_MILLIGRAM_PER_DECILITRE = 0x27B1, /**< */ - BLE_GATT_UNIT_MASS_DENSITY_MILLIMOLE_PER_LITRE = 0x27B2, /**< */ - BLE_GATT_UNIT_TIME_YEAR = 0x27B3, /**< Time, year. */ - BLE_GATT_UNIT_TIME_MONTH = 0x27B4, /**< Time, month. */ - BLE_GATT_UNIT_CONCENTRATION_COUNT_PER_CUBIC_METRE = 0x27B5, /**< */ - BLE_GATT_UNIT_IRRADIANCE_WATT_PER_SQUARE_METRE = 0x27B6 /**< */ + + /** + * No specified unit type. + */ + BLE_GATT_UNIT_NONE = 0x2700, + + /** + * Length, meter. + */ + BLE_GATT_UNIT_LENGTH_METRE = 0x2701, + + /** + * Mass, kilogram. + */ + BLE_GATT_UNIT_MASS_KILOGRAM = 0x2702, + + /** + * Time, second. + */ + BLE_GATT_UNIT_TIME_SECOND = 0x2703, + + /** + * Electric current, ampere. + */ + BLE_GATT_UNIT_ELECTRIC_CURRENT_AMPERE = 0x2704, + + /** + * Thermodynamic temperature, kelvin. + */ + BLE_GATT_UNIT_THERMODYNAMIC_TEMPERATURE_KELVIN = 0x2705, + + /** Amount of substance, mole. + * + */ + BLE_GATT_UNIT_AMOUNT_OF_SUBSTANCE_MOLE = 0x2706, + + /** + * Luminous intensity, candela. + */ + BLE_GATT_UNIT_LUMINOUS_INTENSITY_CANDELA = 0x2707, + + /** + * Area, square meters. + */ + BLE_GATT_UNIT_AREA_SQUARE_METRES = 0x2710, + + /** + * Volume, cubic meters. + */ + BLE_GATT_UNIT_VOLUME_CUBIC_METRES = 0x2711, + + /** + * Velocity, meters per second. + */ + BLE_GATT_UNIT_VELOCITY_METRES_PER_SECOND = 0x2712, + + /** + * Acceleration, meters per second squared. + */ + BLE_GATT_UNIT_ACCELERATION_METRES_PER_SECOND_SQUARED = 0x2713, + + /** + * Wave number reciprocal, meter. + */ + BLE_GATT_UNIT_WAVENUMBER_RECIPROCAL_METRE = 0x2714, + + /** + * Density, kilogram per cubic meter. + */ + BLE_GATT_UNIT_DENSITY_KILOGRAM_PER_CUBIC_METRE = 0x2715, + + /** + * Surface density (kilogram per square meter). + */ + BLE_GATT_UNIT_SURFACE_DENSITY_KILOGRAM_PER_SQUARE_METRE = 0x2716, + + /** + * Specific volume (cubic meter per kilogram). + */ + BLE_GATT_UNIT_SPECIFIC_VOLUME_CUBIC_METRE_PER_KILOGRAM = 0x2717, + + /** + * Current density (ampere per square meter). + */ + BLE_GATT_UNIT_CURRENT_DENSITY_AMPERE_PER_SQUARE_METRE = 0x2718, + + /** + * Magnetic field strength, ampere per meter. + */ + BLE_GATT_UNIT_MAGNETIC_FIELD_STRENGTH_AMPERE_PER_METRE = 0x2719, + + /** + * Amount concentration (mole per cubic meter). + */ + BLE_GATT_UNIT_AMOUNT_CONCENTRATION_MOLE_PER_CUBIC_METRE = 0x271A, + + /** + * Mass concentration (kilogram per cubic meter). + */ + BLE_GATT_UNIT_MASS_CONCENTRATION_KILOGRAM_PER_CUBIC_METRE = 0x271B, + + /** + * Luminance (candela per square meter). + */ + BLE_GATT_UNIT_LUMINANCE_CANDELA_PER_SQUARE_METRE = 0x271C, + + /** + * Refractive index. + */ + BLE_GATT_UNIT_REFRACTIVE_INDEX = 0x271D, + + /** + * Relative permeability. + */ + BLE_GATT_UNIT_RELATIVE_PERMEABILITY = 0x271E, + + /** + * Plane angle (radian). + */ + BLE_GATT_UNIT_PLANE_ANGLE_RADIAN = 0x2720, + + /** + * Solid angle (steradian). + */ + BLE_GATT_UNIT_SOLID_ANGLE_STERADIAN = 0x2721, + + /** + * Frequency, hertz. + */ + BLE_GATT_UNIT_FREQUENCY_HERTZ = 0x2722, + + /** + * Force, newton. + */ + BLE_GATT_UNIT_FORCE_NEWTON = 0x2723, + + /** + * Pressure, pascal. + */ + BLE_GATT_UNIT_PRESSURE_PASCAL = 0x2724, + + /** + * Energy, joule. + */ + BLE_GATT_UNIT_ENERGY_JOULE = 0x2725, + + /** + * Power, watt. + */ + BLE_GATT_UNIT_POWER_WATT = 0x2726, + + /** + * Electrical charge, coulomb. + */ + BLE_GATT_UNIT_ELECTRIC_CHARGE_COULOMB = 0x2727, + + /** + * Electrical potential difference, voltage. + */ + BLE_GATT_UNIT_ELECTRIC_POTENTIAL_DIFFERENCE_VOLT = 0x2728, + + /** + * Capacitance, farad. + */ + BLE_GATT_UNIT_CAPACITANCE_FARAD = 0x2729, + + /** + * Electric resistance, ohm. + */ + BLE_GATT_UNIT_ELECTRIC_RESISTANCE_OHM = 0x272A, + + /** + * Electric conductance, siemens. + */ + BLE_GATT_UNIT_ELECTRIC_CONDUCTANCE_SIEMENS = 0x272B, + + /** + * Magnetic flux, weber. + */ + BLE_GATT_UNIT_MAGNETIC_FLEX_WEBER = 0x272C, + + /** + * Magnetic flux density, tesla. + */ + BLE_GATT_UNIT_MAGNETIC_FLEX_DENSITY_TESLA = 0x272D, + + /** + * Inductance, henry. + */ + BLE_GATT_UNIT_INDUCTANCE_HENRY = 0x272E, + + /** + * Celsius temperature, degree Celsius. + */ + BLE_GATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_CELSIUS = 0x272F, + + /** + * Luminous flux, lumen. + */ + BLE_GATT_UNIT_LUMINOUS_FLUX_LUMEN = 0x2730, + + /** + * Illuminance, lux. + */ + BLE_GATT_UNIT_ILLUMINANCE_LUX = 0x2731, + + /** + * Activity referred to a radionuclide, becquerel. + */ + BLE_GATT_UNIT_ACTIVITY_REFERRED_TO_A_RADIONUCLIDE_BECQUEREL = 0x2732, + + /** + * Absorbed dose, gray. + */ + BLE_GATT_UNIT_ABSORBED_DOSE_GRAY = 0x2733, + + /** + * Dose equivalent, sievert. + */ + BLE_GATT_UNIT_DOSE_EQUIVALENT_SIEVERT = 0x2734, + + /** + * Catalytic activity, katal. + */ + BLE_GATT_UNIT_CATALYTIC_ACTIVITY_KATAL = 0x2735, + + /** + * Dynamic viscosity, pascal second. + */ + BLE_GATT_UNIT_DYNAMIC_VISCOSITY_PASCAL_SECOND = 0x2740, + + /** + * Moment of force, newton meter. + */ + BLE_GATT_UNIT_MOMENT_OF_FORCE_NEWTON_METRE = 0x2741, + + /** + * Surface tension, newton per meter. + */ + BLE_GATT_UNIT_SURFACE_TENSION_NEWTON_PER_METRE = 0x2742, + + /** + * Angular velocity, radian per second. + */ + BLE_GATT_UNIT_ANGULAR_VELOCITY_RADIAN_PER_SECOND = 0x2743, + + /** + * Angular acceleration, radian per second squared. + */ + BLE_GATT_UNIT_ANGULAR_ACCELERATION_RADIAN_PER_SECOND_SQUARED = 0x2744, + + /** + * Heat flux density, watt per square meter. + */ + BLE_GATT_UNIT_HEAT_FLUX_DENSITY_WATT_PER_SQUARE_METRE = 0x2745, + + /** + * Heat capacity, joule per kelvin. + */ + BLE_GATT_UNIT_HEAT_CAPACITY_JOULE_PER_KELVIN = 0x2746, + + /** + * Specific heat capacity, joule per kilogram kelvin. + */ + BLE_GATT_UNIT_SPECIFIC_HEAT_CAPACITY_JOULE_PER_KILOGRAM_KELVIN = 0x2747, + + /** + * Specific energy, joule per kilogram. + */ + BLE_GATT_UNIT_SPECIFIC_ENERGY_JOULE_PER_KILOGRAM = 0x2748, + + /** + * Thermal conductivity, watt per meter kelvin. + */ + BLE_GATT_UNIT_THERMAL_CONDUCTIVITY_WATT_PER_METRE_KELVIN = 0x2749, + + /** + * Energy density, joule per cubic meter. + */ + BLE_GATT_UNIT_ENERGY_DENSITY_JOULE_PER_CUBIC_METRE = 0x274A, + + /** + * Electric field strength, volt per meter. + */ + BLE_GATT_UNIT_ELECTRIC_FIELD_STRENGTH_VOLT_PER_METRE = 0x274B, + + /** + * Electric charge density, coulomb per cubic meter. + */ + BLE_GATT_UNIT_ELECTRIC_CHARGE_DENSITY_COULOMB_PER_CUBIC_METRE = 0x274C, + + /** + * Surface charge density, coulomb per square meter. + */ + BLE_GATT_UNIT_SURFACE_CHARGE_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274D, + + /** + * Electric flux density, coulomb per square meter. + */ + BLE_GATT_UNIT_ELECTRIC_FLUX_DENSITY_COULOMB_PER_SQUARE_METRE = 0x274E, + + /** + * Permittivity, farad per meter. + */ + BLE_GATT_UNIT_PERMITTIVITY_FARAD_PER_METRE = 0x274F, + + /** + * Permeability, henry per meter. + */ + BLE_GATT_UNIT_PERMEABILITY_HENRY_PER_METRE = 0x2750, + + /** + * Molar energy, joule per mole. + */ + BLE_GATT_UNIT_MOLAR_ENERGY_JOULE_PER_MOLE = 0x2751, + + /** + * Molar entropy, joule per mole kelvin. + */ + BLE_GATT_UNIT_MOLAR_ENTROPY_JOULE_PER_MOLE_KELVIN = 0x2752, + + /** + * Exposure, coulomb per kilogram. + */ + BLE_GATT_UNIT_EXPOSURE_COULOMB_PER_KILOGRAM = 0x2753, + + /** + * Absorbed dose rate, gray per second. + */ + BLE_GATT_UNIT_ABSORBED_DOSE_RATE_GRAY_PER_SECOND = 0x2754, + + /** + * Radiant intensity, watt per steradian. + */ + BLE_GATT_UNIT_RADIANT_INTENSITY_WATT_PER_STERADIAN = 0x2755, + + /** + * Radiance, watt per square meter steradian. + */ + BLE_GATT_UNIT_RADIANCE_WATT_PER_SQUARE_METRE_STERADIAN = 0x2756, + + /** + * Catalytic activity concentration, katal per cubic meter. + */ + BLE_GATT_UNIT_CATALYTIC_ACTIVITY_CONCENTRATION_KATAL_PER_CUBIC_METRE = 0x2757, + + /** + * Time, minute. + */ + BLE_GATT_UNIT_TIME_MINUTE = 0x2760, + + /** + * Time, hour. + */ + BLE_GATT_UNIT_TIME_HOUR = 0x2761, + + /** + * Time, day. + */ + BLE_GATT_UNIT_TIME_DAY = 0x2762, + + /** + * Plane angle, degree. + */ + BLE_GATT_UNIT_PLANE_ANGLE_DEGREE = 0x2763, + + /** + * Plane angle, minute. + */ + BLE_GATT_UNIT_PLANE_ANGLE_MINUTE = 0x2764, + + /** + * Plane angle, seconds. + */ + BLE_GATT_UNIT_PLANE_ANGLE_SECOND = 0x2765, + + /** + * Area, hectare. + */ + BLE_GATT_UNIT_AREA_HECTARE = 0x2766, + + /** + * Volume, liter. + */ + BLE_GATT_UNIT_VOLUME_LITRE = 0x2767, + + /** + * Mass, ton. + */ + BLE_GATT_UNIT_MASS_TONNE = 0x2768, + + /** + * Pressure, bar. + */ + BLE_GATT_UNIT_PRESSURE_BAR = 0x2780, + + /** + * Pressure, millimeter of mercury. + */ + BLE_GATT_UNIT_PRESSURE_MILLIMETRE_OF_MERCURY = 0x2781, + + /** + * Length, ngstrm. + */ + BLE_GATT_UNIT_LENGTH_ANGSTROM = 0x2782, + + /** + * Length, nautical mile. + */ + BLE_GATT_UNIT_LENGTH_NAUTICAL_MILE = 0x2783, + + /** + * Area, barn. + */ + BLE_GATT_UNIT_AREA_BARN = 0x2784, + + /** + * Velocity, knot. + */ + BLE_GATT_UNIT_VELOCITY_KNOT = 0x2785, + + /** + * Logarithmic radio quantity, neper. + */ + BLE_GATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_NEPER = 0x2786, + + /** + * Logarithmic radio quantity, bel. + */ + BLE_GATT_UNIT_LOGARITHMIC_RADIO_QUANTITY_BEL = 0x2787, + + /** + * Length, yard. + */ + BLE_GATT_UNIT_LENGTH_YARD = 0x27A0, + + /** + * Length, parsec. + */ + BLE_GATT_UNIT_LENGTH_PARSEC = 0x27A1, + + /** + * Length, inch. + */ + BLE_GATT_UNIT_LENGTH_INCH = 0x27A2, + + /** + * Length, foot. + */ + BLE_GATT_UNIT_LENGTH_FOOT = 0x27A3, + + /** + * Length, mile. + */ + BLE_GATT_UNIT_LENGTH_MILE = 0x27A4, + + /** + * Pressure, pound-force per square inch. + */ + BLE_GATT_UNIT_PRESSURE_POUND_FORCE_PER_SQUARE_INCH = 0x27A5, + + /** + * Velocity, kilometer per hour. + */ + BLE_GATT_UNIT_VELOCITY_KILOMETRE_PER_HOUR = 0x27A6, + + /** Velocity, mile per hour. + * + */ + BLE_GATT_UNIT_VELOCITY_MILE_PER_HOUR = 0x27A7, + + /** + * Angular Velocity, revolution per minute. + */ + BLE_GATT_UNIT_ANGULAR_VELOCITY_REVOLUTION_PER_MINUTE = 0x27A8, + + /** + * Energy, gram calorie. + */ + BLE_GATT_UNIT_ENERGY_GRAM_CALORIE = 0x27A9, + + /** + * Energy, kilogram calorie. + */ + BLE_GATT_UNIT_ENERGY_KILOGRAM_CALORIE = 0x27AA, + + /** + * Energy, killowatt hour. + */ + BLE_GATT_UNIT_ENERGY_KILOWATT_HOUR = 0x27AB, + + /** + * Thermodynamic temperature, degree Fahrenheit. + */ + BLE_GATT_UNIT_THERMODYNAMIC_TEMPERATURE_DEGREE_FAHRENHEIT = 0x27AC, + + /** + * Percentage. + */ + BLE_GATT_UNIT_PERCENTAGE = 0x27AD, + + /** + * Per mille. + */ + BLE_GATT_UNIT_PER_MILLE = 0x27AE, + + /** + * Period, beats per minute. + */ + BLE_GATT_UNIT_PERIOD_BEATS_PER_MINUTE = 0x27AF, + + /** + * Electric charge, ampere hours. + */ + BLE_GATT_UNIT_ELECTRIC_CHARGE_AMPERE_HOURS = 0x27B0, + + /** + * Mass density, milligram per deciliter. + */ + BLE_GATT_UNIT_MASS_DENSITY_MILLIGRAM_PER_DECILITRE = 0x27B1, + + /** + * Mass density, millimole per liter. + */ + BLE_GATT_UNIT_MASS_DENSITY_MILLIMOLE_PER_LITRE = 0x27B2, + + /** + * Time, year. + */ + BLE_GATT_UNIT_TIME_YEAR = 0x27B3, + + /** + * Time, month. + */ + BLE_GATT_UNIT_TIME_MONTH = 0x27B4, + + /** + * Concentration, count per cubic meter. + */ + BLE_GATT_UNIT_CONCENTRATION_COUNT_PER_CUBIC_METRE = 0x27B5, + + /** + * Irradiance, watt per square meter. + */ + BLE_GATT_UNIT_IRRADIANCE_WATT_PER_SQUARE_METRE = 0x27B6 }; /** - * @brief Standard GATT number types. + * Presentation format of a characteristic. * - * @note See Bluetooth Specification 4.0 (Vol. 3), Part G, Section 3.3.3.5.2. + * It determines how the value of a characteristic is formatted. A server + * can expose that information to its clients by adding a Characteristic + * Presentation Format descriptor to relevant characteristics. * - * @note See http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + * @note See Bluetooth Specification 4.0 (Vol. 3), Part G, Section 3.3.3.5.2. */ enum { - BLE_GATT_FORMAT_RFU = 0x00, /**< Reserved for future use. */ - BLE_GATT_FORMAT_BOOLEAN = 0x01, /**< Boolean. */ - BLE_GATT_FORMAT_2BIT = 0x02, /**< Unsigned 2-bit integer. */ - BLE_GATT_FORMAT_NIBBLE = 0x03, /**< Unsigned 4-bit integer. */ - BLE_GATT_FORMAT_UINT8 = 0x04, /**< Unsigned 8-bit integer. */ - BLE_GATT_FORMAT_UINT12 = 0x05, /**< Unsigned 12-bit integer. */ - BLE_GATT_FORMAT_UINT16 = 0x06, /**< Unsigned 16-bit integer. */ - BLE_GATT_FORMAT_UINT24 = 0x07, /**< Unsigned 24-bit integer. */ - BLE_GATT_FORMAT_UINT32 = 0x08, /**< Unsigned 32-bit integer. */ - BLE_GATT_FORMAT_UINT48 = 0x09, /**< Unsigned 48-bit integer. */ - BLE_GATT_FORMAT_UINT64 = 0x0A, /**< Unsigned 64-bit integer. */ - BLE_GATT_FORMAT_UINT128 = 0x0B, /**< Unsigned 128-bit integer. */ - BLE_GATT_FORMAT_SINT8 = 0x0C, /**< Signed 2-bit integer. */ - BLE_GATT_FORMAT_SINT12 = 0x0D, /**< Signed 12-bit integer. */ - BLE_GATT_FORMAT_SINT16 = 0x0E, /**< Signed 16-bit integer. */ - BLE_GATT_FORMAT_SINT24 = 0x0F, /**< Signed 24-bit integer. */ - BLE_GATT_FORMAT_SINT32 = 0x10, /**< Signed 32-bit integer. */ - BLE_GATT_FORMAT_SINT48 = 0x11, /**< Signed 48-bit integer. */ - BLE_GATT_FORMAT_SINT64 = 0x12, /**< Signed 64-bit integer. */ - BLE_GATT_FORMAT_SINT128 = 0x13, /**< Signed 128-bit integer. */ - BLE_GATT_FORMAT_FLOAT32 = 0x14, /**< IEEE-754 32-bit floating point. */ - BLE_GATT_FORMAT_FLOAT64 = 0x15, /**< IEEE-754 64-bit floating point. */ - BLE_GATT_FORMAT_SFLOAT = 0x16, /**< IEEE-11073 16-bit SFLOAT. */ - BLE_GATT_FORMAT_FLOAT = 0x17, /**< IEEE-11073 32-bit FLOAT. */ - BLE_GATT_FORMAT_DUINT16 = 0x18, /**< IEEE-20601 format. */ - BLE_GATT_FORMAT_UTF8S = 0x19, /**< UTF-8 string. */ - BLE_GATT_FORMAT_UTF16S = 0x1A, /**< UTF-16 string. */ - BLE_GATT_FORMAT_STRUCT = 0x1B /**< Opaque Structure. */ + /** + * Reserved for future use. + */ + BLE_GATT_FORMAT_RFU = 0x00, + + /** + * Boolean. + */ + BLE_GATT_FORMAT_BOOLEAN = 0x01, + + /** + * Unsigned 2-bit integer. + */ + BLE_GATT_FORMAT_2BIT = 0x02, + + /** + * Unsigned 4-bit integer. + */ + BLE_GATT_FORMAT_NIBBLE = 0x03, + + /** + * Unsigned 8-bit integer. + */ + BLE_GATT_FORMAT_UINT8 = 0x04, + + /** + * Unsigned 12-bit integer. + */ + BLE_GATT_FORMAT_UINT12 = 0x05, + + /** + * Unsigned 16-bit integer. + */ + BLE_GATT_FORMAT_UINT16 = 0x06, + + /** + * Unsigned 24-bit integer. + */ + BLE_GATT_FORMAT_UINT24 = 0x07, + + /** + * Unsigned 32-bit integer. + */ + BLE_GATT_FORMAT_UINT32 = 0x08, + + /** + * Unsigned 48-bit integer. + */ + BLE_GATT_FORMAT_UINT48 = 0x09, + + /** + * Unsigned 64-bit integer. + */ + BLE_GATT_FORMAT_UINT64 = 0x0A, + + /** + * Unsigned 128-bit integer. + */ + BLE_GATT_FORMAT_UINT128 = 0x0B, + + /** + * Signed 8-bit integer. + */ + BLE_GATT_FORMAT_SINT8 = 0x0C, + + /** + * Signed 12-bit integer. + */ + BLE_GATT_FORMAT_SINT12 = 0x0D, + + /** + * Signed 16-bit integer. + */ + BLE_GATT_FORMAT_SINT16 = 0x0E, + + /** + * Signed 24-bit integer. + */ + BLE_GATT_FORMAT_SINT24 = 0x0F, + + /** + * Signed 32-bit integer. + */ + BLE_GATT_FORMAT_SINT32 = 0x10, + + /** + * Signed 48-bit integer. + */ + BLE_GATT_FORMAT_SINT48 = 0x11, + + /** + * Signed 64-bit integer. + */ + BLE_GATT_FORMAT_SINT64 = 0x12, + + /** + * Signed 128-bit integer. + */ + BLE_GATT_FORMAT_SINT128 = 0x13, + + /** + * IEEE-754 32-bit floating point. + */ + BLE_GATT_FORMAT_FLOAT32 = 0x14, + + /** + * IEEE-754 64-bit floating point. + */ + BLE_GATT_FORMAT_FLOAT64 = 0x15, + + /** + * IEEE-11073 16-bit SFLOAT. + */ + BLE_GATT_FORMAT_SFLOAT = 0x16, + + /** + * IEEE-11073 32-bit FLOAT. + */ + BLE_GATT_FORMAT_FLOAT = 0x17, + + /** + * IEEE-20601 format. + */ + BLE_GATT_FORMAT_DUINT16 = 0x18, + + /** + * UTF8 string. + */ + BLE_GATT_FORMAT_UTF8S = 0x19, + + /** + * UTF16 string. + */ + BLE_GATT_FORMAT_UTF16S = 0x1A, + + /** + * Opaque Structure. + */ + BLE_GATT_FORMAT_STRUCT = 0x1B }; /*! - * @brief Standard GATT characteristic properties. + * Characteristic properties. + * + * It is a bitfield that determines how a characteristic value can be used. * - * @note See Bluetooth Specification 4.0 (Vol. 3), Part G, Section 3.3.1.1 - * and Section 3.3.3.1 for Extended Properties. + * @note See Bluetooth Specification 4.0 (Vol. 3), Part G, Section 3.3.1.1 + * and Section 3.3.3.1 for Extended Properties. */ enum Properties_t { - BLE_GATT_CHAR_PROPERTIES_NONE = 0x00, - BLE_GATT_CHAR_PROPERTIES_BROADCAST = 0x01, /**< Permits broadcasts of the characteristic value using the Server Characteristic Configuration descriptor. */ - BLE_GATT_CHAR_PROPERTIES_READ = 0x02, /**< Permits reads of the characteristic value. */ - BLE_GATT_CHAR_PROPERTIES_WRITE_WITHOUT_RESPONSE = 0x04, /**< Permits writes of the characteristic value without response. */ - BLE_GATT_CHAR_PROPERTIES_WRITE = 0x08, /**< Permits writes of the characteristic value with response. */ - BLE_GATT_CHAR_PROPERTIES_NOTIFY = 0x10, /**< Permits notifications of a characteristic value without acknowledgment. */ - BLE_GATT_CHAR_PROPERTIES_INDICATE = 0x20, /**< Permits indications of a characteristic value with acknowledgment. */ - BLE_GATT_CHAR_PROPERTIES_AUTHENTICATED_SIGNED_WRITES = 0x40, /**< Permits signed writes to the characteristic value. */ - BLE_GATT_CHAR_PROPERTIES_EXTENDED_PROPERTIES = 0x80 /**< Additional characteristic properties are defined in the Characteristic Extended Properties descriptor */ + /** + * No property defined. + */ + BLE_GATT_CHAR_PROPERTIES_NONE = 0x00, + + /** + * Permits broadcasts of the characteristic value using the Server + * Characteristic Configuration descriptor. + */ + BLE_GATT_CHAR_PROPERTIES_BROADCAST = 0x01, + + /** + * Permits reads of the characteristic value. + */ + BLE_GATT_CHAR_PROPERTIES_READ = 0x02, + + /** + * Permits writes of the characteristic value without response. + */ + BLE_GATT_CHAR_PROPERTIES_WRITE_WITHOUT_RESPONSE = 0x04, + + /** + * Permits writes of the characteristic value with response. + */ + BLE_GATT_CHAR_PROPERTIES_WRITE = 0x08, + + /** + * Permits notifications of a characteristic value without acknowledgment. + */ + BLE_GATT_CHAR_PROPERTIES_NOTIFY = 0x10, + + /** + * Permits indications of a characteristic value with acknowledgment. + */ + BLE_GATT_CHAR_PROPERTIES_INDICATE = 0x20, + + /** + * Permits signed writes to the characteristic value. + */ + BLE_GATT_CHAR_PROPERTIES_AUTHENTICATED_SIGNED_WRITES = 0x40, + + /** + * The Characteristic Extended Properties descriptor + * defines additional characteristic properties. + */ + BLE_GATT_CHAR_PROPERTIES_EXTENDED_PROPERTIES = 0x80 + }; /** - * @brief GATT presentation format wrapper. + * Value of a Characteristic Presentation Format descriptor. * - * @note See Bluetooth Specification 4.0 (Vol. 3), Part G, Section 3.3.3.5. + * Characteristic Presentation Format descriptor expresses the format of a + * characteristic value. * - * @note See https://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml + * @note See Bluetooth Specification 4.0 (Vol. 3), Part G, Section 3.3.3.5. */ struct PresentationFormat_t { - uint8_t gatt_format; /**< Format of the value. */ - int8_t exponent; /**< Exponent for integer data types. Example: if Exponent = -3 and the char value is 3892, the actual value is 3.892 */ - uint16_t gatt_unit; /**< UUID from Bluetooth Assigned Numbers. */ - uint8_t gatt_namespace; /**< Namespace from Bluetooth Assigned Numbers, normally '1'. */ - uint16_t gatt_nsdesc; /**< Namespace description from Bluetooth Assigned Numbers, normally '0'. */ + /** + * Format of the value. + */ + uint8_t gatt_format; + + /** + * Exponent for integer data types. + * + * Example: if Exponent = -3 and the char value is 3892, the actual + * value is 3.892 + */ + int8_t exponent; + + /** + * Unit of the characteristic value. + * + * It is a UUID from Bluetooth Assigned Numbers. + */ + uint16_t gatt_unit; + + /** + * Namespace of the description field. + * + * This field identifies the organization that is responsible for + * defining the enumerations for the description field. + * + * The namespace of the Bluetooth Body is 0x01. + */ + uint8_t gatt_namespace; + + /** + * Description. + * + * @note The value 0x0000 means unknown in the Bluetooth namespace. + */ + uint16_t gatt_nsdesc; + }; /** - * @brief Creates a new GattCharacteristic using the specified 16-bit - * UUID, value length, and properties. - * - * @param[in] uuid - * The UUID to use for this characteristic. - * @param[in] valuePtr - * The memory holding the initial value. The value is copied - * into the stack when the enclosing service is added, and - * is thereafter maintained internally by the stack. - * @param[in] len - * The length in bytes of this characteristic's value. - * @param[in] maxLen - * The max length in bytes of this characteristic's value. - * @param[in] props - * The 8-bit field containing the characteristic's properties. - * @param[in] descriptors - * A pointer to an array of descriptors to be included within - * this characteristic. The memory for the descriptor array is - * owned by the caller, and should remain valid at least until - * the enclosing service is added to the GATT table. - * @param[in] numDescriptors - * The number of descriptors in the previous array. - * @param[in] hasVariableLen - * Whether the attribute's value length changes over time. - * - * @note The UUID value must be unique in the service and is normally >1. - * - * @note If valuePtr == NULL, length == 0, and properties == READ - * for the value attribute of a characteristic, then that particular - * characteristic may be considered optional and dropped while - * instantiating the service with the underlying BLE stack. - * - * @note A CCCD should not be allocated if either the notify or indicate - * flag is set, as it is handled by the underlying BLE stack. In such - * a case, the param descriptors could be empty and the param - * numDescriptors equal to zero. - */ - GattCharacteristic(const UUID &uuid, - uint8_t *valuePtr = NULL, - uint16_t len = 0, - uint16_t maxLen = 0, - uint8_t props = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0, - bool hasVariableLen = true) : - _valueAttribute(uuid, valuePtr, len, maxLen, hasVariableLen), + * @brief Constructs a new GattCharacteristic. + * + * @param[in] uuid The UUID of this characteristic. + * @param[in] valuePtr Memory buffer holding the initial value. The value is + * copied into the Bluetooth subsytem when the enclosing service is added. + * Thereafter, the stack maintains it internally. + * @param[in] len The length in bytes of this characteristic's value. + * @param[in] maxLen The capacity in bytes of the characteristic value + * buffer. + * @param[in] props An 8-bit field that contains the characteristic's + * properties. + * @param[in] descriptors A pointer to an array of descriptors to be included + * within this characteristic. The caller owns the memory for the descriptor + * array, which must remain valid at least until the enclosing service is + * added to the GATT table. + * @param[in] numDescriptors The number of descriptors presents in @p + * descriptors array. + * @param[in] hasVariableLen Flag that indicates if the attribute's value + * length can change throughout time. + * + * @note If valuePtr is NULL, length is equal to 0 and the characteristic + * is readable, then that particular characteristic may be considered + * optional and dropped while instantiating the service with the underlying + * BLE stack. + * + * @note A Client Characteristic Configuration Descriptor (CCCD) should not + * be allocated if either the notify or indicate flag in the @p props bit + * field; the underlying BLE stack handles it. + * + * @important GattCharacteristic registered in a GattServer must remain + * valid for the lifetime of the GattServer. + */ + GattCharacteristic( + const UUID &uuid, + uint8_t *valuePtr = NULL, + uint16_t len = 0, + uint16_t maxLen = 0, + uint8_t props = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0, + bool hasVariableLen = true + ) : _valueAttribute(uuid, valuePtr, len, maxLen, hasVariableLen), _properties(props), _requiredSecurity(SecurityManager::SECURITY_MODE_ENCRYPTION_OPEN_LINK), _descriptors(descriptors), @@ -344,7 +1378,6 @@ class GattCharacteristic { enabledWriteAuthorization(false), readAuthorizationCallback(), writeAuthorizationCallback() { - /* empty */ } public: @@ -352,126 +1385,147 @@ class GattCharacteristic { * Set up the minimum security (mode and level) requirements for access to * the characteristic's value attribute. * - * @param[in] securityMode - * Can be one of encryption or signing, with or without - * protection for man in the middle attacks (MITM). + * @param[in] securityMode Can be one of encryption or signing, with or + * without protection for man in the middle attacks (MITM). */ - void requireSecurity(SecurityManager::SecurityMode_t securityMode) { + void requireSecurity(SecurityManager::SecurityMode_t securityMode) + { _requiredSecurity = securityMode; } public: /** - * Set up callback that will be triggered before the GATT Client is allowed - * to write this characteristic. The handler will determine the - * authorization reply for the write. + * Register a callback handling client's write requests or commands. + * + * The callback registered is invoked when the client attempts to write the + * characteristic value; the event handler can accept or reject the write + * request with the appropriate error code. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. */ - void setWriteAuthorizationCallback(void (*callback)(GattWriteAuthCallbackParams *)) { + void setWriteAuthorizationCallback( + void (*callback)(GattWriteAuthCallbackParams *) + ) { writeAuthorizationCallback.attach(callback); enabledWriteAuthorization = true; } /** - * Same as GattCharacrteristic::setWriteAuthorizationCallback(), but allows - * the possibility to add an object reference and member function as - * handler for connection event callbacks. + * Register a callback handling client's write requests or commands. * - * @param[in] object - * Pointer to the object of a class defining the member callback - * function (@p member). - * @param[in] member - * The member callback (within the context of an object) to be - * invoked. + * The callback registered is invoked when the client attempts to write the + * characteristic value; the event handler can accept or reject the write + * request with the appropriate error code. + * + * @param[in] object Pointer to the object of a class defining the event + * handler (@p member). It must remain valid for the lifetime of the + * GattCharacteristic. + * @param[in] member The member function that handles the write event. */ template - void setWriteAuthorizationCallback(T *object, void (T::*member)(GattWriteAuthCallbackParams *)) { + void setWriteAuthorizationCallback( + T *object, + void (T::*member)(GattWriteAuthCallbackParams *) + ) { writeAuthorizationCallback.attach(object, member); enabledWriteAuthorization = true; } /** - * Set up callback that will be triggered before the GATT Client is allowed - * to read this characteristic. The handler will determine the - * authorization reply for the read. + * Register the read requests event handler. + * + * The callback registered is invoked when the client attempts to read the + * characteristic value; the event handler can accept or reject the read + * request with the appropriate error code. It can also set specific outgoing + * data. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. */ - void setReadAuthorizationCallback(void (*callback)(GattReadAuthCallbackParams *)) { + void setReadAuthorizationCallback( + void (*callback)(GattReadAuthCallbackParams *) + ) { readAuthorizationCallback.attach(callback); enabledReadAuthorization = true; } /** - * Same as GattCharacrteristic::setReadAuthorizationCallback(), but allows - * the possibility to add an object reference and member function as - * handler for connection event callbacks. + * Register the read requests event handler. * - * @param[in] object - * Pointer to the object of a class defining the member callback - * function (@p member). - * @param[in] member - * The member callback (within the context of an object) to be - * invoked. + * The callback registered is invoked when the client attempts to read the + * characteristic value; the event handler can accept or reject the read + * request with the appropriate error code. It can also set specific outgoing + * data. + * + * @param[in] object Pointer to the object of a class defining the event + * handler (@p member). It must remain valid for the lifetime of the + * GattCharacteristic. + * @param[in] member The member function that handles the read event. */ template - void setReadAuthorizationCallback(T *object, void (T::*member)(GattReadAuthCallbackParams *)) { + void setReadAuthorizationCallback( + T *object, + void (T::*member)(GattReadAuthCallbackParams *) + ) { readAuthorizationCallback.attach(object, member); enabledReadAuthorization = true; } /** - * Helper that calls the registered handler to determine the authorization - * reply for a write request. This function is meant to be called from the - * BLE stack specific implementation. + * Invoke the write authorization callback. + * + * This function is a helper that calls the registered write handler to + * determine the authorization reply for a write request. * - * @param[in] params - * To capture the context of the write-auth request. Also - * contains an out-parameter for reply. + * @important This function is not meant to be called by user code. + * + * @param[in] params Context of the write-auth request; it contains an + * out-parameter used as a reply. * * @return A GattAuthCallbackReply_t value indicating whether authorization - * is granted. + * is granted. */ - GattAuthCallbackReply_t authorizeWrite(GattWriteAuthCallbackParams *params) { + GattAuthCallbackReply_t authorizeWrite(GattWriteAuthCallbackParams *params) + { if (!isWriteAuthorizationEnabled()) { return AUTH_CALLBACK_REPLY_SUCCESS; } - params->authorizationReply = AUTH_CALLBACK_REPLY_SUCCESS; /* Initialized to no-error by default. */ + /* Initialized to no-error by default. */ + params->authorizationReply = AUTH_CALLBACK_REPLY_SUCCESS; writeAuthorizationCallback.call(params); return params->authorizationReply; } /** - * Helper that calls the registered handler to determine the authorization - * reply for a read request. This function is meant to be called from the - * BLE stack specific implementation. + * Invoke the read authorization callback. * - * @param[in] params - * To capture the context of the read-auth request. + * This function is a helper that calls the registered read handler to + * determine the authorization reply for a read request. * - * @return A GattAuthCallbackReply_t value indicating whether authorization - * is granted. + * @important This function is not meant to be called by user code. * - * @note To authorize or deny the read the params->authorizationReply field - * should be set to AUTH_CALLBACK_REPLY_SUCCESS (authorize) or any - * of the AUTH_CALLBACK_REPLY_ATTERR_* values (deny). + * @param[in] params Context of the read-auth request; it contains an + * out-parameter used as a reply and the handler can fill it with outgoing + * data. * - * @note If the read is approved and params->data is unchanged (NULL), - * the current characteristic value will be used. + * @return A GattAuthCallbackReply_t value indicating whether authorization + * is granted. * - * @note If the read is approved, a new value can be provided by setting - * the params->data pointer and params->len fields. + * @note If the read request is approved and params->data remains NULL, then + * the current characteristic value is used in the read response payload. + * + * @note If the read is approved, the event handler can specify an outgoing + * value directly with the help of the fields + * GattReadAuthCallbackParams::data and GattReadAuthCallbackParams::len. */ - GattAuthCallbackReply_t authorizeRead(GattReadAuthCallbackParams *params) { + GattAuthCallbackReply_t authorizeRead(GattReadAuthCallbackParams *params) + { if (!isReadAuthorizationEnabled()) { return AUTH_CALLBACK_REPLY_SUCCESS; } - params->authorizationReply = AUTH_CALLBACK_REPLY_SUCCESS; /* Initialized to no-error by default. */ + /* Initialized to no-error by default. */ + params->authorizationReply = AUTH_CALLBACK_REPLY_SUCCESS; readAuthorizationCallback.call(params); return params->authorizationReply; } @@ -482,16 +1536,18 @@ class GattCharacteristic { * * @return A reference to the characteristic's value attribute. */ - GattAttribute& getValueAttribute() { + GattAttribute& getValueAttribute() + { return _valueAttribute; } /** - * A const alternative to GattCharacteristic::getValueAttribute(). + * Get the characteristic's value attribute. * * @return A const reference to the characteristic's value attribute. */ - const GattAttribute& getValueAttribute() const { + const GattAttribute& getValueAttribute() const + { return _valueAttribute; } @@ -500,20 +1556,23 @@ class GattCharacteristic { * * @return The value attribute handle. * - * @note The attribute handle is typically assigned by the underlying BLE - * stack. + * @note The underlying BLE stack assigns the attribute handle when the + * enclosing service is added. */ - GattAttribute::Handle_t getValueHandle(void) const { + GattAttribute::Handle_t getValueHandle(void) const + { return getValueAttribute().getHandle(); } /** - * Get the characteristic's properties. Refer to - * GattCharacteristic::Properties_t. + * Get the characteristic's properties. + * + * @note Refer to GattCharacteristic::Properties_t. * * @return The characteristic's properties. */ - uint8_t getProperties(void) const { + uint8_t getProperties(void) const + { return _properties; } @@ -522,7 +1581,8 @@ class GattCharacteristic { * * @return The characteristic's required security. */ - SecurityManager::SecurityMode_t getRequiredSecurity() const { + SecurityManager::SecurityMode_t getRequiredSecurity() const + { return _requiredSecurity; } @@ -531,43 +1591,48 @@ class GattCharacteristic { * * @return The total number of descriptors. */ - uint8_t getDescriptorCount(void) const { + uint8_t getDescriptorCount(void) const + { return _descriptorCount; } /** - * Check whether read authorization is enabled i.e. check whether a - * read authorization callback was previously registered. Refer to - * GattCharacteristic::setReadAuthorizationCallback(). + * Check whether read authorization is enabled. * - * @return true if read authorization is enabled, false otherwise. + * Read authorization is enabled when a read authorization event handler is + * set up. + * + * @return true if read authorization is enabled and false otherwise. */ - bool isReadAuthorizationEnabled() const { + bool isReadAuthorizationEnabled() const + { return enabledReadAuthorization; } /** - * Check whether write authorization is enabled i.e. check whether a - * write authorization callback was previously registered. Refer to - * GattCharacteristic::setWriteAuthorizationCallback(). + * Check whether write authorization is enabled. + * + * Write authorization is enabled when a write authorization event handler is + * set up. * * @return true if write authorization is enabled, false otherwise. */ - bool isWriteAuthorizationEnabled() const { + bool isWriteAuthorizationEnabled() const + { return enabledWriteAuthorization; } /** * Get this characteristic's descriptor at a specific index. * - * @param[in] index - * The descriptor's index. + * @param[in] index The index of the descriptor to get. * - * @return A pointer the requested descriptor if @p index contains a valid - * descriptor, or NULL otherwise. + * @return A pointer the requested descriptor if @p index is within the + * range of the descriptor array or NULL otherwise. */ - GattAttribute *getDescriptor(uint8_t index) { - if (index >= _descriptorCount) { + GattAttribute *getDescriptor(uint8_t index) + { + if (index = _descriptorCount) { return NULL; } @@ -578,45 +1643,50 @@ class GattCharacteristic { /** * Attribute that contains the actual value of this characteristic. */ - GattAttribute _valueAttribute; + GattAttribute _valueAttribute; + /** * The characteristic's properties. Refer to * GattCharacteristic::Properties_t. */ - uint8_t _properties; + uint8_t _properties; + /** * The characteristic's required security. */ - SecurityManager::SecurityMode_t _requiredSecurity; + SecurityManager::SecurityMode_t _requiredSecurity; + /** * The characteristic's descriptor attributes. - * This contains only CCCDs that has neither the notify nor the indicate - * flag set, as those are handled by the underlying BLE stack. */ - GattAttribute **_descriptors; + GattAttribute **_descriptors; + /** * The number of descriptors in this characteristic. */ - uint8_t _descriptorCount; + uint8_t _descriptorCount; /** - * Whether read authorization is enabled i.e. whether there is a registered - * callback to determine read authorization reply. + * Whether read authorization is enabled. */ bool enabledReadAuthorization; + /** - * Whether write authorization is enabled i.e. whether there is a registered - * callback to determine write authorization reply. + * Whether write authorization is enabled. */ bool enabledWriteAuthorization; + /** * The registered callback handler for read authorization reply. */ - FunctionPointerWithContext readAuthorizationCallback; + FunctionPointerWithContext + readAuthorizationCallback; + /** * The registered callback handler for write authorization reply. */ - FunctionPointerWithContext writeAuthorizationCallback; + FunctionPointerWithContext + writeAuthorizationCallback; private: /* Disallow copy and assignment. */ @@ -625,7 +1695,7 @@ class GattCharacteristic { }; /** - * Helper class to construct a read-only GattCharacteristic. + * Helper class that represents a read only GattCharacteristic. */ template class ReadOnlyGattCharacteristic : public GattCharacteristic { @@ -633,37 +1703,42 @@ class ReadOnlyGattCharacteristic : public GattCharacteristic { /** * Construct a ReadOnlyGattCharacteristic. * - * @param[in] uuid - * The characteristic's UUID. - * @param[in] valuePtr - * Pointer to the characteristic's initial value. - * @param[in] additionalProperties - * Additional characteristic properties. By default, the - * properties are set to - * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. - * @param[in] descriptors - * An array of pointers to descriptors to be added to the new - * characteristic. - * @param[in] numDescriptors - * The total number of descriptors in @p descriptors. + * @param[in] uuid The characteristic's UUID. + * @param[in] valuePtr Pointer to the characteristic's initial value. The + * pointer is reinterpreted as a pointer to an uint8_t buffer. + * @param[in] additionalProperties Additional characteristic properties. By + * default, the properties are set to + * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. + * @param[in] descriptors An array of pointers to descriptors to be added + * to the new characteristic. + * @param[in] numDescriptors The total number of descriptors in @p + * descriptors. * * @note Instances of ReadOnlyGattCharacteristic have a fixed length - * attribute value that equals sizeof(T). For a variable length - * alternative use GattCharacteristic directly. - */ - ReadOnlyGattCharacteristic(const UUID &uuid, - T *valuePtr, - uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0) : - GattCharacteristic(uuid, reinterpret_cast(valuePtr), sizeof(T), sizeof(T), - BLE_GATT_CHAR_PROPERTIES_READ | additionalProperties, descriptors, numDescriptors, false) { - /* empty */ + * attribute value that equals sizeof(T). For a variable length alternative, + * use GattCharacteristic directly. + */ + ReadOnlyGattCharacteristic( + const UUID &uuid, + T *valuePtr, + uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0 + ) : GattCharacteristic( + uuid, + reinterpret_cast(valuePtr), + sizeof(T), + sizeof(T), + BLE_GATT_CHAR_PROPERTIES_READ | additionalProperties, + descriptors, + numDescriptors, + false + ) { } }; /** - * Helper class to construct a write-only GattCharacteristic. + * Helper class that represents a write only GattCharacteristic. */ template class WriteOnlyGattCharacteristic : public GattCharacteristic { @@ -671,37 +1746,41 @@ class WriteOnlyGattCharacteristic : public GattCharacteristic { /** * Construct a WriteOnlyGattCharacteristic. * - * @param[in] uuid - * The characteristic's UUID. - * @param[in] valuePtr - * Pointer to the characteristic's initial value. - * @param[in] additionalProperties - * Additional characteristic properties. By default, the - * properties are set to - * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE. - * @param[in] descriptors - * An array of pointers to descriptors to be added to the new - * characteristic. - * @param[in] numDescriptors - * The total number of descriptors in @p descriptors. + * @param[in] uuid The characteristic's UUID. + * @param[in] valuePtr Pointer to the characteristic's initial value. The + * pointer is reinterpreted as a pointer to an uint8_t buffer. + * @param[in] additionalProperties Additional characteristic properties. By + * default, the properties are set to + * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE. + * @param[in] descriptors An array of pointers to descriptors to be added to + * the new characteristic. + * @param[in] numDescriptors The total number of descriptors in @p + * descriptors. * * @note Instances of WriteOnlyGattCharacteristic have variable length - * attribute value with maximum size equal to sizeof(T). For a fixed length - * alternative use GattCharacteristic directly. - */ - WriteOnlyGattCharacteristic(const UUID &uuid, - T *valuePtr, - uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0) : - GattCharacteristic(uuid, reinterpret_cast(valuePtr), sizeof(T), sizeof(T), - BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, descriptors, numDescriptors) { - /* empty */ + * attribute value with maximum size equal to sizeof(T). For a fixed length + * alternative, use GattCharacteristic directly. + */ + WriteOnlyGattCharacteristic( + const UUID &uuid, + T *valuePtr, + uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0 + ) : GattCharacteristic( + uuid, + reinterpret_cast(valuePtr), + sizeof(T), + sizeof(T), + BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, + descriptors, + numDescriptors + ) { } }; /** - * Helper class to construct a readable and writable GattCharacteristic. + * Helper class that represents a readable and writable GattCharacteristic. */ template class ReadWriteGattCharacteristic : public GattCharacteristic { @@ -709,38 +1788,41 @@ class ReadWriteGattCharacteristic : public GattCharacteristic { /** * Construct a ReadWriteGattCharacteristic. * - * @param[in] uuid - * The characteristic's UUID. - * @param[in] valuePtr - * Pointer to the characteristic's initial value. - * @param[in] additionalProperties - * Additional characteristic properties. By default, the - * properties are set to - * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE | - * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. - * @param[in] descriptors - * An array of pointers to descriptors to be added to the new - * characteristic. - * @param[in] numDescriptors - * The total number of descriptors in @p descriptors. + * @param[in] uuid The characteristic's UUID. + * @param[in] valuePtr Pointer to the characteristic's initial value. The + * pointer is reinterpreted as a pointer to an uint8_t buffer. + * @param[in] additionalProperties Additional characteristic properties. By + * default, the properties are set to + * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE and + * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. + * @param[in] descriptors An array of pointers to descriptors to be added to + * the new characteristic. + * @param[in] numDescriptors The total number of descriptors in @p descriptors. * * @note Instances of ReadWriteGattCharacteristic have variable length - * attribute value with maximum size equal to sizeof(T). For a fixed length - * alternative use GattCharacteristic directly. - */ - ReadWriteGattCharacteristic(const UUID &uuid, - T *valuePtr, - uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0) : - GattCharacteristic(uuid, reinterpret_cast(valuePtr), sizeof(T), sizeof(T), - BLE_GATT_CHAR_PROPERTIES_READ | BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, descriptors, numDescriptors) { - /* empty */ + * attribute value with maximum size equal to sizeof(T). For a fixed length + * alternative, use GattCharacteristic directly. + */ + ReadWriteGattCharacteristic( + const UUID &uuid, + T *valuePtr, + uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0 + ) : GattCharacteristic( + uuid, + reinterpret_cast(valuePtr), + sizeof(T), + sizeof(T), + BLE_GATT_CHAR_PROPERTIES_READ | BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, + descriptors, + numDescriptors + ) { } }; /** - * Helper class to construct a write-only GattCharacteristic with an array + * Helper class that represents a write-only GattCharacteristic with an array * value. */ template @@ -749,38 +1831,41 @@ class WriteOnlyArrayGattCharacteristic : public GattCharacteristic { /** * Construct a WriteOnlyGattCharacteristic. * - * @param[in] uuid - * The characteristic's UUID. - * @param[in] valuePtr - * Pointer to an array of length NUM_ELEMENTS containing the - * characteristic's intitial value. - * @param[in] additionalProperties - * Additional characteristic properties. By default, the - * properties are set to - * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE. - * @param[in] descriptors - * An array of pointers to descriptors to be added to the new - * characteristic. - * @param[in] numDescriptors - * The total number of descriptors in @p descriptors. + * @param[in] uuid The characteristic's UUID. + * @param[in] valuePtr Pointer to an array of length NUM_ELEMENTS containing + * the characteristic's initial value. The pointer is reinterpreted as a + * pointer to an uint8_t buffer. + * @param[in] additionalProperties Additional characteristic properties. By + * default, the properties are set to + * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE. + * @param[in] descriptors An array of pointers to descriptors to be added to + * the new characteristic. + * @param[in] numDescriptors The total number of descriptors in @p descriptors. * * @note Instances of WriteOnlyGattCharacteristic have variable length - * attribute value with maximum size equal to sizeof(T) * NUM_ELEMENTS. - * For a fixed length alternative use GattCharacteristic directly. - */ - WriteOnlyArrayGattCharacteristic(const UUID &uuid, - T valuePtr[NUM_ELEMENTS], - uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0) : - GattCharacteristic(uuid, reinterpret_cast(valuePtr), sizeof(T) * NUM_ELEMENTS, sizeof(T) * NUM_ELEMENTS, - BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, descriptors, numDescriptors) { - /* empty */ + * attribute value with maximum size equal to sizeof(T) * NUM_ELEMENTS. + * For a fixed length alternative, use GattCharacteristic directly. + */ + WriteOnlyArrayGattCharacteristic( + const UUID &uuid, + T valuePtr[NUM_ELEMENTS], + uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0 + ) : GattCharacteristic( + uuid, + reinterpret_cast(valuePtr), + sizeof(T) * NUM_ELEMENTS, + sizeof(T) * NUM_ELEMENTS, + BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, + descriptors, + numDescriptors + ) { } }; /** - * Helper class to construct a read-only GattCharacteristic with an array + * Helper class that represents a read-only GattCharacteristic with an array * value. */ template @@ -789,39 +1874,44 @@ class ReadOnlyArrayGattCharacteristic : public GattCharacteristic { /** * Construct a ReadOnlyGattCharacteristic. * - * @param[in] uuid - * The characteristic's UUID. - * @param[in] valuePtr - * Pointer to an array of length NUM_ELEMENTS containing the - * characteristic's intitial value. - * @param[in] additionalProperties - * Additional characteristic properties. By default, the - * properties are set to - * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. - * @param[in] descriptors - * An array of pointers to descriptors to be added to the new - * characteristic. - * @param[in] numDescriptors - * The total number of descriptors in @p descriptors. + * @param[in] uuid The characteristic's UUID. + * @param[in] valuePtr Pointer to an array of length NUM_ELEMENTS containing + * the characteristic's initial value. The pointer is reinterpreted as a + * pointer to an uint8_t buffer. + * @param[in] additionalProperties Additional characteristic properties. By + * default, the properties are set to + * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. + * @param[in] descriptors An array of pointers to descriptors to be added to + * the new characteristic. + * @param[in] numDescriptors The total number of descriptors in @p + * descriptors. * * @note Instances of ReadOnlyGattCharacteristic have fixed length - * attribute value that equals sizeof(T) * NUM_ELEMENTS. - * For a variable length alternative use GattCharacteristic directly. - */ - ReadOnlyArrayGattCharacteristic(const UUID &uuid, - T valuePtr[NUM_ELEMENTS], - uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0) : - GattCharacteristic(uuid, reinterpret_cast(valuePtr), sizeof(T) * NUM_ELEMENTS, sizeof(T) * NUM_ELEMENTS, - BLE_GATT_CHAR_PROPERTIES_READ | additionalProperties, descriptors, numDescriptors, false) { - /* empty */ + * attribute value that equals sizeof(T) * NUM_ELEMENTS. For a variable + * length alternative, use GattCharacteristic directly. + */ + ReadOnlyArrayGattCharacteristic( + const UUID &uuid, + T valuePtr[NUM_ELEMENTS], + uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0 + ) : GattCharacteristic( + uuid, + reinterpret_cast(valuePtr), + sizeof(T) * NUM_ELEMENTS, + sizeof(T) * NUM_ELEMENTS, + BLE_GATT_CHAR_PROPERTIES_READ | additionalProperties, + descriptors, + numDescriptors, + false + ) { } }; /** - * Helper class to construct a readable and writable GattCharacteristic with an array - * value. + * Helper class that represents a readable and writable GattCharacteristic with + * an array value. */ template class ReadWriteArrayGattCharacteristic : public GattCharacteristic { @@ -829,35 +1919,44 @@ class ReadWriteArrayGattCharacteristic : public GattCharacteristic { /** * Construct a ReadWriteGattCharacteristic. * - * @param[in] uuid - * The characteristic's UUID. - * @param[in] valuePtr - * Pointer to an array of length NUM_ELEMENTS containing the - * characteristic's intitial value. - * @param[in] additionalProperties - * Additional characteristic properties. By default, the - * properties are set to - * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE | - * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. - * @param[in] descriptors - * An array of pointers to descriptors to be added to the new - * characteristic. - * @param[in] numDescriptors - * The total number of descriptors in @p descriptors. + * @param[in] uuid The characteristic's UUID. + * @param[in] valuePtr Pointer to an array of length NUM_ELEMENTS containing + * the characteristic's initial value. The pointer is reinterpreted as a + * pointer to an uint8_t buffer. + * @param[in] additionalProperties Additional characteristic properties. By + * default, the properties are set to + * Properties_t::BLE_GATT_CHAR_PROPERTIES_WRITE | + * Properties_t::BLE_GATT_CHAR_PROPERTIES_READ. + * @param[in] descriptors An array of pointers to descriptors to be added to + * the new characteristic. + * @param[in] numDescriptors The total number of descriptors in @p descriptors. * * @note Instances of ReadWriteGattCharacteristic have variable length - * attribute value with maximum size equal to sizeof(T) * NUM_ELEMENTS. - * For a fixed length alternative use GattCharacteristic directly. - */ - ReadWriteArrayGattCharacteristic(const UUID &uuid, - T valuePtr[NUM_ELEMENTS], - uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, - GattAttribute *descriptors[] = NULL, - unsigned numDescriptors = 0) : - GattCharacteristic(uuid, reinterpret_cast(valuePtr), sizeof(T) * NUM_ELEMENTS, sizeof(T) * NUM_ELEMENTS, - BLE_GATT_CHAR_PROPERTIES_READ | BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, descriptors, numDescriptors) { - /* empty */ + * attribute value with maximum size equal to sizeof(T) * NUM_ELEMENTS. + * For a fixed length alternative, use GattCharacteristic directly. + */ + ReadWriteArrayGattCharacteristic( + const UUID &uuid, + T valuePtr[NUM_ELEMENTS], + uint8_t additionalProperties = BLE_GATT_CHAR_PROPERTIES_NONE, + GattAttribute *descriptors[] = NULL, + unsigned numDescriptors = 0 + ) : GattCharacteristic( + uuid, + reinterpret_cast(valuePtr), + sizeof(T) * NUM_ELEMENTS, + sizeof(T) * NUM_ELEMENTS, + BLE_GATT_CHAR_PROPERTIES_READ | BLE_GATT_CHAR_PROPERTIES_WRITE | additionalProperties, + descriptors, + numDescriptors + ) { } }; +/** + * @} + * @} + * @} + */ + #endif /* ifndef __GATT_CHARACTERISTIC_H__ */ diff --git a/features/FEATURE_BLE/ble/GattClient.h b/features/FEATURE_BLE/ble/GattClient.h index 5f043ebb22a..9dcbd2a4f5b 100644 --- a/features/FEATURE_BLE/ble/GattClient.h +++ b/features/FEATURE_BLE/ble/GattClient.h @@ -14,8 +14,8 @@ * limitations under the License. */ -#ifndef __GATT_CLIENT_H__ -#define __GATT_CLIENT_H__ +#ifndef MBED_GATT_CLIENT_H__ +#define MBED_GATT_CLIENT_H__ #include "Gap.h" #include "GattAttribute.h" @@ -26,122 +26,212 @@ #include "CallChainOfFunctionPointersWithContext.h" +/** + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup client + * @{ + */ + +/** + * Define procedures required for interacting with a distant GATT server. + * + * @par Discovery procedures + * + * A GATT server hosts a fixed set of services. These services are a logical + * composition of characteristics that may be discovered, read, written or also + * broadcast their state to a connected client. These characteristics may also + * contain metainformation named characteristic descriptors. A characteristic + * descriptor may be used to indicate the unit used for a characteristic value, + * describe in a textual form the characterisic purpose or allow a client to + * register for notification of updates of the characteristic value. + * + * Prior to any interaction with server characteristic, a GATT client + * discovers the layout of the services and characteristics present on the + * server. + * + * The layout of the descriptors of a characteristic may also be issued to + * as an extra discovery step. + * + * @par Attribute manipulation + * + * As a result of the discovery process, the client can start interacting with + * the characteristic discovered. Depending on the characteristic properties + * (acquired during discovery), a client can read or write the value of a given + * characteristic. + * + * Mbed BLE abstracts most read and write operations to offer a single API that + * can be used to read or write characteristics values. Application code does not + * have to handle the fragmentation/reassembly process necessary if the attribute + * value to transported cannot fit in a single data packet. + * + * @par Server Initiated events + * + * If a characteristic has to notify or indicate a property set; then, a client may + * register to a notification or indication from the characteristic. When the + * server updates the characteristic value, the server can forward the + * new value to the registered clients. The notification/indication mechanism + * prevents polling from the client and therefore minimize the transactions + * involved between a client and a server. + * + * Registration is made by writing the Client Characteristic Configuration + * Descriptor, which is present in the characteristic if the notify or + * indicate properties are set. The client discovers that descriptor + * if it intends to register to server initiated events. + */ class GattClient { public: /** - * Type for the registered callbacks added to the data read callchain. - * Refer to GattClient::onDataRead(). + * Attribute read event handler. + * + * @see GattClient::onDataRead(). */ - typedef FunctionPointerWithContext ReadCallback_t; + typedef FunctionPointerWithContext + ReadCallback_t; + /** - * Type for the data read event callchain. Refer to GattClient::onDataRead(). + * Callchain of attribute read event handlers. */ - typedef CallChainOfFunctionPointersWithContext ReadCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + ReadCallbackChain_t; /** - * Enumerator for write operations. + * GATT write operations. */ enum WriteOp_t { - GATT_OP_WRITE_REQ = 0x01, /**< Write request. */ - GATT_OP_WRITE_CMD = 0x02, /**< Write command. */ + /** + * Write request. + * + * It is used to request the server to write the value of an attribute + * and acknowledge that this has been achieved in a Write Response. + */ + GATT_OP_WRITE_REQ = 0x01, + + /** + * Write command. + * + * It is used to request the server to write the value of an attribute. + * The server does not acknowledge the status of the operation. + */ + GATT_OP_WRITE_CMD = 0x02, }; /** - * Type for the registered callbacks added to the data write callchain. - * Refer to GattClient::onDataWrite(). + * Attribute write event handler. + * + * @see GattClient::onDataWrite(). */ - typedef FunctionPointerWithContext WriteCallback_t; + typedef FunctionPointerWithContext + WriteCallback_t; + /** - * Type for the data write event callchain. Refer to GattClient::onDataWrite(). + * Callchain of attribute write event handlers. + * + * @see GattClient::onDataWrite(). */ - typedef CallChainOfFunctionPointersWithContext WriteCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + WriteCallbackChain_t; /** - * Type for the registered callbacks added to the update event callchain. - * Refer to GattClient::onHVX(). + * Handle value notification/indication event handler. + * + * @see to GattClient::onHVX(). */ - typedef FunctionPointerWithContext HVXCallback_t; + typedef FunctionPointerWithContext + HVXCallback_t; + /** - * Type for the update event callchain. Refer to GattClient::onHVX(). + * Callchain of handle value notification/indication event handlers. + * + * @see GattClient::onHVX(). */ - typedef CallChainOfFunctionPointersWithContext HVXCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + HVXCallbackChain_t; /** - * Type for the registered callbacks added to the shutdown callchain. - * Refer to GattClient::onShutdown(). + * Shutdown event handler. + * + * @see GattClient::onShutdown(). */ - typedef FunctionPointerWithContext GattClientShutdownCallback_t; + typedef FunctionPointerWithContext + GattClientShutdownCallback_t; + + /** - * Type for the shutdown event callchain. Refer to GattClient::onShutown(). + * Callchain of shutdown event handlers. + * + * @see to GattClient::onShutown(). */ - typedef CallChainOfFunctionPointersWithContext GattClientShutdownCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + GattClientShutdownCallbackChain_t; /* - * The following functions are meant to be overridden in the platform-specific sub-class. + * The following functions are meant to be overridden in the platform + * specific subclass. */ public: virtual ~GattClient() { } /** - * Launch service discovery. Once launched, application callbacks will be - * invoked for matching services or characteristics. isServiceDiscoveryActive() - * can be used to determine status, and a termination callback (if one was set up) - * will be invoked at the end. Service discovery can be terminated prematurely, - * if needed, using terminateServiceDiscovery(). - * - * @param[in] connectionHandle - * Handle for the connection with the peer. - * @param[in] sc - * This is the application callback for a matching service. Taken as - * NULL by default. Note: service discovery may still be active - * when this callback is issued; calling asynchronous BLE-stack - * APIs from within this application callback might cause the - * stack to abort service discovery. If this becomes an issue, it - * may be better to make a local copy of the discoveredService and - * wait for service discovery to terminate before operating on the - * service. - * @param[in] cc - * This is the application callback for a matching characteristic. - * Taken as NULL by default. Note: service discovery may still be - * active when this callback is issued; calling asynchronous - * BLE-stack APIs from within this application callback might cause - * the stack to abort service discovery. If this becomes an issue, - * it may be better to make a local copy of the discoveredCharacteristic - * and wait for service discovery to terminate before operating on the - * characteristic. - * @param[in] matchingServiceUUID - * UUID-based filter for specifying a service in which the application is - * interested. By default it is set as the wildcard UUID_UNKNOWN, - * in which case it matches all services. If characteristic-UUID - * filter (below) is set to the wildcard value, then a service - * callback will be invoked for the matching service (or for every - * service if the service filter is a wildcard). - * @param[in] matchingCharacteristicUUIDIn - * UUID-based filter for specifying characteristic in which the application - * is interested. By default it is set as the wildcard UUID_UKNOWN - * to match against any characteristic. If both service-UUID - * filter and characteristic-UUID filter are used with non-wildcard - * values, then only a single characteristic callback is - * invoked for the matching characteristic. - * - * @note Using wildcard values for both service-UUID and characteristic- - * UUID will result in complete service discovery: callbacks being - * called for every service and characteristic. - * - * @note Providing NULL for the characteristic callback will result in - * characteristic discovery being skipped for each matching - * service. This allows for an inexpensive method to discover only - * services. - * - * @return - * BLE_ERROR_NONE if service discovery is launched successfully; else an appropriate error. - */ - virtual ble_error_t launchServiceDiscovery(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t sc = NULL, - ServiceDiscovery::CharacteristicCallback_t cc = NULL, - const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN), - const UUID &matchingCharacteristicUUIDIn = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) { + * Launch the service and characteristic discovery procedure of a GATT server + * peer. + * + * The procedure invokes application callbacks for matching services or + * characteristics. The process ends after all the services and + * characteristics present on the distant GATT server have been discovered. + * Termination callbacks registered with onServiceDiscoveryTermination() are + * invoked to notify the application of the termination of the procedure. + * + * Application code can track the status of the procedure by invoking the + * function isServiceDiscoveryActive(), which returns true if the + * procedure is ongoing. + * + * At any point, application code can prematurely terminate the discovery + * procedure by calling terminateServiceDiscovery(). + * + * @param[in] connectionHandle Handle of the connection with the peer GATT + * server. + * @param[in] sc Service discovered event handler invoked when a matching + * service has been discovered. This parameter may be NULL. + * @param[in] cc Characteristic discovered event handler invoked when a + * matching characteristic has been found. This parameter may be NULL. + * @param[in] matchingServiceUUID UUID of the service the caller is + * interested in. If a service discovered matches this filter, then @p sc is + * invoked with it. The special value BLE_UUID_UNKNOWN acts as a wildcard, + * which can be used to discover all services present on the peer GATT + * server. + * @param[in] matchingCharacteristicUUIDIn UUID of the characteristic the + * caller is interested in. If a characteristic discovered matches this + * filter, then @p cc is invoked with it. The special value BLE_UUID_UNKNOWN + * acts as a wildcard, which can be used to discover all services present on + * the peer GATT server. + * + * @par Discovery procedure implementation detail + * + * It is recommended to implement several strategies based on the + * combination of callbacks and filters passed in input to efficiently + * realize the discovery procedure: + * - If @p sc and @p cc are NULL, then it is not necessay to initiate any + * discovery, and the termination handlers can be invoked immediately. + * - If @p matchingServiceUUID is set, then the GATT discover services by + * service UUID procedure should be used; otherwise, the GATT discover primary + * services procedure should be used. + * - If @p cc is NULL, then the discovery process should end after the discovery + * of the services. + * + * @return BLE_ERROR_NONE if the discovery procedure has been successfully + * started and an appropriate error otherwise. + */ + virtual ble_error_t launchServiceDiscovery( + Gap::Handle_t connectionHandle, + ServiceDiscovery::ServiceCallback_t sc = NULL, + ServiceDiscovery::CharacteristicCallback_t cc = NULL, + const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN), + const UUID &matchingCharacteristicUUIDIn = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN) + ) { /* Avoid compiler warnings about unused variables. */ (void)connectionHandle; (void)sc; @@ -149,147 +239,213 @@ class GattClient { (void)matchingServiceUUID; (void)matchingCharacteristicUUIDIn; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Launch service discovery for services. Once launched, service discovery will remain - * active with service-callbacks being issued back into the application for matching - * services. isServiceDiscoveryActive() can be used to - * determine status, and a termination callback (if set up) will be invoked - * at the end. Service discovery can be terminated prematurely, if needed, - * using terminateServiceDiscovery(). - * - * @param[in] connectionHandle - * Handle for the connection with the peer. - * @param[in] callback - * This is the application callback for a matching service. - * Note: service discovery may still be active - * when this callback is issued; calling asynchronous BLE-stack - * APIs from within this application callback might cause the - * stack to abort service discovery. If this becomes an issue, it - * may be better to make a local copy of the discoveredService and - * wait for service discovery to terminate before operating on the - * service. - * @param[in] matchingServiceUUID - * UUID-based filter for specifying a service in which the application is - * interested. By default it is set as the wildcard UUID_UNKNOWN, - * in which case it matches all services. - * - * @return - * BLE_ERROR_NONE if service discovery is launched successfully; else an appropriate error. - */ - virtual ble_error_t discoverServices(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t callback, - const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) { - return launchServiceDiscovery(connectionHandle, callback, NULL, matchingServiceUUID); /* We take advantage of the property - * that providing NULL for the characteristic callback will result in - * characteristic discovery being skipped for each matching - * service. This allows for an inexpensive method to discover only - * services. Porters are free to override this. */ + * Launch the service discovery procedure of a GATT server peer. + * + * The procedure invokes the application callback for matching services. + * The process ends after all the services present on the distant GATT + * server have been discovered. + * Termination callbacks registered with onServiceDiscoveryTermination() are + * invoked to notify the application of the termination of the procedure. + * + * Application code can track the status of the procedure by invoking the + * function isServiceDiscoveryActive(), which returns true if the + * procedure is ongoing. + * + * At any point, application code can prematurely terminate the discovery + * procedure by calling terminateServiceDiscovery(). + * + * @param[in] connectionHandle Handle of the connection with the peer GATT + * server. + * @param[in] callback Service discovered event handler invoked when a + * matching service has been discovered. This parameter may be NULL. + * @param[in] matchingServiceUUID UUID of the service the caller is + * interested in. If a service discovered matches this filter, then @p sc is + * invoked with it. The special value BLE_UUID_UNKNOWN act is a wildcard, + * which can be used to discover all services present on the peer GATT + * server. + * + * @return BLE_ERROR_NONE if the discovery procedure has been successfully + * started and an appropriate error otherwise. + */ + virtual ble_error_t discoverServices( + Gap::Handle_t connectionHandle, + ServiceDiscovery::ServiceCallback_t callback, + const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN) + ) { + /* We take advantage of the property + * that providing NULL for the characteristic callback results in + * characteristic discovery being skipped for each matching + * service. This allows for an inexpensive method to discover only + * services. Porters are free to override this. */ + return launchServiceDiscovery( + connectionHandle, callback, NULL, matchingServiceUUID + ); } /** - * Launch service discovery for services. Once launched, service discovery will remain - * active with service-callbacks being issued back into the application for matching - * services. isServiceDiscoveryActive() can be used to - * determine status, and a termination callback (if set up) will be invoked - * at the end. Service discovery can be terminated prematurely, if needed, - * using terminateServiceDiscovery(). - * - * @param[in] connectionHandle - * Handle for the connection with the peer. - * @param[in] callback - * This is the application callback for a matching service. - * Note: service discovery may still be active - * when this callback is issued; calling asynchronous BLE-stack - * APIs from within this application callback might cause the - * stack to abort service discovery. If this becomes an issue, it - * may be better to make a local copy of the discoveredService and - * wait for service discovery to terminate before operating on the - * service. - * @param[in] startHandle, endHandle - * Handle range within which to limit the search. - * - * @return - * BLE_ERROR_NONE if service discovery is launched successfully; else an appropriate error. - */ - virtual ble_error_t discoverServices(Gap::Handle_t connectionHandle, - ServiceDiscovery::ServiceCallback_t callback, - GattAttribute::Handle_t startHandle, - GattAttribute::Handle_t endHandle) { + * Launch the service discovery procedure of a GATT server peer. + * + * The process ends after all the services present in the attribute range @p + * startHandle to @p endHandle have been discovered. + * + * Termination callbacks registered with onServiceDiscoveryTermination() are + * invoked to notify the application of the termination of the procedure. + * + * Application code can track the status of the procedure by invoking the + * function isServiceDiscoveryActive(), which returns true if the + * procedure is ongoing. + * + * At any point, application code can prematurely terminate the discovery + * procedure by calling terminateServiceDiscovery(). + * + * @param[in] connectionHandle Handle of the connection with the peer GATT + * server. + * @param[in] callback Service discovered event handler invoked when a + * matching service has been discovered. This parameter may be NULL. + * @param[in] startHandle First attribute handle of the discovery range. + * @param[in] endHandle end Lasr attribute handle of the discovery range. + * + * @return BLE_ERROR_NONE if the discovery procedure has been successfully + * started and an appropriate error otherwise. + */ + virtual ble_error_t discoverServices( + Gap::Handle_t connectionHandle, + ServiceDiscovery::ServiceCallback_t callback, + GattAttribute::Handle_t startHandle, + GattAttribute::Handle_t endHandle + ) { /* Avoid compiler warnings about unused variables. */ (void)connectionHandle; (void)callback; (void)startHandle; (void)endHandle; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Check if service-discovery is currently active. + * Check if the service discovery procedure is currently active. * - * @return true if service-discovery is active, false otherwise. + * @return true if service discovery procedure is active and false otherwise. */ - virtual bool isServiceDiscoveryActive(void) const { - return false; /* Requesting action from porters: override this API if this capability is supported. */ + virtual bool isServiceDiscoveryActive(void) const + { + /* Requesting action from porters: override this API if this capability + is supported. */ + return false; } /** - * Terminate an ongoing service discovery. This should result in an - * invocation of TerminationCallback if service-discovery is active. + * Terminate all ongoing service discovery procedures. + * + * It results in an invocation of the service discovery termination handler + * registered with onServiceDiscoveryTermination(). */ - virtual void terminateServiceDiscovery(void) { - /* Requesting action from porters: override this API if this capability is supported. */ + virtual void terminateServiceDiscovery(void) + { + /* Requesting action from porters: override this API if this capability + is supported. */ } /** - * Initiate a GATT Client read procedure by attribute-handle. + * Initiate the read procedure of an attribute handle. + * + * Once the attribute value has been read in its entirety, the process issues + * an attribute read event and passes it to all events handlers registered + * by onDataRead. + * + * @param[in] connHandle Handle of the connection used to send the read + * request. + * @param[in] attributeHandle Handle of the attribute to read data from. + * @param[in] offset The offset from the start of the attribute value to be + * read. + * + * @return BLE_ERROR_NONE if read procedure successfully started. + * + * @par Implementation notes: * - * @param[in] connHandle - * Handle for the connection with the peer. - * @param[in] attributeHandle - * Handle of the attribute to read data from. - * @param[in] offset - * The offset from the start of the attribute value to be read. + * Reading the attribute value in its entirety may involve sending several + * GATT requests to the peer. The following algorithm may be used to + * implement the process: * - * @return - * BLE_ERROR_NONE if read procedure was successfully started. + * If the offset is equal to 0, then send a read request; otherwise, send a + * read blob request at the specified offset. + * + * While the attribute data in the response are MTU - 1 long: + * - Concat the response to the value containing the previous responses. + * - Increment the value of the offset by MTU - 1. + * - Send a read blob request with the updated offset. + * + * Finally, concat the last response with the value containing all the + * previous responses and forward that value to the event handlers. */ - virtual ble_error_t read(Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, uint16_t offset) const { + virtual ble_error_t read( + Gap::Handle_t connHandle, + GattAttribute::Handle_t attributeHandle, + uint16_t offset + ) const { /* Avoid compiler warnings about unused variables. */ (void)connHandle; (void)attributeHandle; (void)offset; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Initiate a GATT Client write procedure. - * - * @param[in] cmd - * Command can be either a write-request (which generates a - * matching response from the peripheral), or a write-command - * (which doesn't require the connected peer to respond). - * @param[in] connHandle - * Connection handle. - * @param[in] attributeHandle - * Handle for the target attribtue on the remote GATT server. - * @param[in] length - * Length of the new value. - * @param[in] value - * New value being written. - * - * @return - * BLE_ERROR_NONE if write procedure was successfully started. - */ - virtual ble_error_t write(GattClient::WriteOp_t cmd, - Gap::Handle_t connHandle, - GattAttribute::Handle_t attributeHandle, - size_t length, - const uint8_t *value) const { + * Initiate a write procedure on an attribute value. + * + * If @p cmd is equal to GATT_OP_WRITE_REQ, then the status of the operation + * is reported to the event handlers registered through onDataWritten(). + * + * @param[in] cmd Type of the write procedure used. If GATT_OP_WRITE_CMD + * is set, then value length is not greater than the size of the mtu + * of connHandle minus three. + * @param[in] connHandle Handle of the connection used to send the write + * request or command. + * @param[in] attributeHandle Handle of the attribute value to write. + * @param[in] length Number of bytes present in @p value. + * @param[in] value Data buffer to write to attributeHandle. + * + * @return BLE_ERROR_NONE if the write procedure successfully started. + * + * @par Implementation notes: + * + * If the operation is a write command, then an implementation uses the + * GATT write without response procedure and an error is returned if + * the data buffer to write is larger than the size of the MTU - 3. + * + * If the operation is a write command and the size of the data buffer to + * write is less than than the size of the MTU - 3, then the ATT write request + * procedure is used, and the response is reported to the handlers + * listening for write response. + * + * Otherwise, the data buffer to write is divided in chunks with a + * maximum size of MTU - 5. Those chunks are sent sequentially to the + * peer in ATT prepare write requests. If an error response is received + * during the process, the procedure ends immediately, the prepared + * write is discarded and an error is reported to the application handlers. + * Once all the chunks have been sent, the transaction is completed + * by sending an execute write request to the peer. The peer response is + * forwarded to the application handlers. + */ + virtual ble_error_t write( + GattClient::WriteOp_t cmd, + Gap::Handle_t connHandle, + GattAttribute::Handle_t attributeHandle, + size_t length, + const uint8_t *value + ) const { /* Avoid compiler warnings about unused variables. */ (void)cmd; (void)connHandle; @@ -297,217 +453,238 @@ class GattClient { (void)length; (void)value; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /* Event callback handlers. */ public: + /** - * Set up a callback for read response events. - * - * @param[in] callback - * Event handler being registered. - * - * @note It is possible to chain together multiple onDataRead callbacks - * (potentially from different modules of an application). + * Register an attribute read event handler. * * @note It is possible to unregister a callback using * onDataRead().detach(callbackToRemove). + * + * @param[in] callback Event handler being registered. */ - void onDataRead(ReadCallback_t callback) { + void onDataRead(ReadCallback_t callback) + { onDataReadCallbackChain.add(callback); } /** - * @brief Provide access to the callchain of read event callbacks. + * Get the callchain of attribute read event handlers. * * @return A reference to the read event callback chain. * - * @note It is possible to register callbacks using onDataRead().add(callback). + * @note It is possible to register new handlers using + * onDataRead().add(callback). * - * @note It is possible to unregister callbacks using onDataRead().detach(callback). + * @note It is possible to unregister an handler by using + * onDataRead().detach(callback). */ - ReadCallbackChain_t& onDataRead() { + ReadCallbackChain_t& onDataRead() + { return onDataReadCallbackChain; } /** - * Set up a callback for write response events. + * Register an attribute write event handler. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. * - * @note It is possible to remove registered callbacks using + * @note It is possible to remove registered handlers using * onDataWritten().detach(callbackToRemove). * - * @note Write commands (issued using writeWoResponse) don't generate a response. + * @note Write commands (issued using writeWoResponse) don't generate a + * response. */ - void onDataWritten(WriteCallback_t callback) { + void onDataWritten(WriteCallback_t callback) + { onDataWriteCallbackChain.add(callback); } /** - * @brief Provide access to the callchain of data written callbacks. + * Get the callchain of attribute write event handlers. * * @return A reference to the data written callbacks chain. * - * @note It is possible to register callbacks using onDataWritten().add(callback). + * @note It is possible to register new handlers by using + * onDataWritten().add(callback). * - * @note It is possible to unregister callbacks using onDataWritten().detach(callback). + * @note It is possible to unregister an handler by using + * onDataWritten().detach(callback). */ - WriteCallbackChain_t& onDataWritten() { + WriteCallbackChain_t& onDataWritten() + { return onDataWriteCallbackChain; } /** - * Set up a callback for write response events. + * Register an attribute write event handler. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. * - * @note Write commands (issued using writeWoResponse) don't generate a response. + * @note It is possible to remove registered handlers using + * onDataWritten().detach(callbackToRemove). + * + * @note Write commands (issued using writeWoResponse) don't generate a + * response. * - * @deprecated Please use GattServer::onDataWritten() instead. + * @deprecated Use GattServer::onDataWritten(). */ - void onDataWrite(WriteCallback_t callback) { + MBED_DEPRECATED("Use GattServer::onDataWritten()") + void onDataWrite(WriteCallback_t callback) + { onDataWritten(callback); } /** - * Set up a callback for when serviceDiscovery terminates. + * Register a service discovery termination event handler. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. */ - virtual void onServiceDiscoveryTermination(ServiceDiscovery::TerminationCallback_t callback) { + virtual void onServiceDiscoveryTermination( + ServiceDiscovery::TerminationCallback_t callback + ) { (void)callback; /* Avoid compiler warnings about ununsed variables. */ - /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ } /** - * @brief Launch discovery of descriptors for a given characteristic. + * Initiate the descriptor discovery procedure for a given characteristic. * - * @details This function will discover all descriptors available for a - * specific characteristic. + * When a descriptor is discovered the discovered descriptor is forwarded + * to @p discoveryCallback. After the discovery of all the descriptors, the + * procedure ends and send a descriptor discovery termination event to @p + * termination callback. * - * @param[in] characteristic - * The characteristic targeted by this discovery procedure. - * @param[in] discoveryCallback - * User function called each time a descriptor is found during - * the procedure. - * @param[in] terminationCallback - * User provided function which will be called once the - * discovery procedure is terminating. This will get called - * when all the descriptors have been discovered or if an - * error occur during the discovery procedure. + * Application code may monitor the discovery process by querying its status + * with isCharacteristicDescriptorDiscoveryActive(). It can also end the + * discovery process by calling terminateCharacteristicDescriptorDiscovery(). * - * @return - * BLE_ERROR_NONE if characteristic descriptor discovery is launched - * successfully; else an appropriate error. + * @param[in] characteristic The characteristic owning the descriptors to + * discover. + * @param[in] discoveryCallback Handle descriptor discovered events for the + * duration of the procedure. + * @param[in] terminationCallback Handle descriptor discovery termination + * event of the procedure. + * + * @return BLE_ERROR_NONE if the characteristic descriptor discovery + * procedure has been launched successfully otherwise an appropriate error. */ virtual ble_error_t discoverCharacteristicDescriptors( const DiscoveredCharacteristic& characteristic, const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback, - const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback) { + const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback + ) { (void) characteristic; (void) discoveryCallback; (void) terminationCallback; - /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this + capability is supported. */ return BLE_ERROR_NOT_IMPLEMENTED; } /** - * @brief Indicate if the discovery of characteristic descriptors is active - * for a given characteristic or not. + * Query status of the descriptor discovery procedure for a given + * characteristic. * - * @param[in] characteristic - * The characteristic concerned by the descriptors discovery. + * @param[in] characteristic The characteristic concerned by the descriptors + * discovery. * * @return true if a descriptors discovery is active for the characteristic - * in input; otherwise false. + * in input otherwise false. */ - virtual bool isCharacteristicDescriptorDiscoveryActive(const DiscoveredCharacteristic& characteristic) const - { + virtual bool isCharacteristicDescriptorDiscoveryActive( + const DiscoveredCharacteristic& characteristic + ) const { (void) characteristic; - return false; /* Requesting action from porter(s): override this API if this capability is supported. */ + /* Requesting action from porter(s): override this API if this + capability is supported. */ + return false; } /** - * @brief Terminate an ongoing characteristic descriptor discovery. + * @brief Terminate an ongoing characteristic descriptor discovery procedure. * - * @details This should result in an invocation of the TerminationCallback if - * the characteristic descriptor discovery is active. + * If the procedure is active, then it ends, and the termination handler + * associated with the procedure is called. * - * @param[in] characteristic - * The characteristic on which the running descriptors - * discovery should be stopped. + * @param[in] characteristic The characteristic containing the descriptors + * being discovered. */ - virtual void terminateCharacteristicDescriptorDiscovery(const DiscoveredCharacteristic& characteristic) { - /* Requesting action from porter(s): override this API if this capability is supported. */ + virtual void terminateCharacteristicDescriptorDiscovery( + const DiscoveredCharacteristic& characteristic + ) { + /* Requesting action from porter(s): override this API if this + capability is supported. */ (void) characteristic; } /** - * Set up a callback for when the GATT Client receives an update event - * corresponding to a change in the value of a characteristic on the remote - * GATT Server. + * Register an handler for Handle Value Notification/Indication events. + * + * @param callback Event handler to register. * - * @note It is possible to unregister callbacks using - * onHVX().detach(callbackToRemove). + * @note It is possible to unregister a callback by using + * onHVX().detach(callbackToRemove). */ - void onHVX(HVXCallback_t callback) { + void onHVX(HVXCallback_t callback) + { onHVXCallbackChain.add(callback); } /** - * Setup a callback to be invoked to notify the user application that the - * GattClient instance is about to shutdown (possibly as a result of a call - * to BLE::shutdown()). + * Register a shutdown event handler. * - * @param[in] callback - * Event handler being registered. + * The registered handler is invoked when the GattClient instance is + * about to be shut down. * - * @note It is possible to chain together multiple onShutdown callbacks - * (potentially from different modules of an application) to be notified - * before the GattClient is shutdown. + * @param[in] callback Event handler to invoke when a shutdown event is + * available. * - * @note It is also possible to set up a callback into a member function of - * some object. + * @note onShutdown().detach(callback) may be used to unregister a given + * callback. * - * @note It is possible to unregister a callback using onShutdown().detach(callback). + * @see BLE::shutdown() */ - void onShutdown(const GattClientShutdownCallback_t& callback) { + void onShutdown(const GattClientShutdownCallback_t& callback) + { shutdownCallChain.add(callback); } /** - * Same as GattClient::onShutdown(), but allows the possibility to add an object - * reference and member function as handler for shutdown event - * callbacks. + * Register a shutdown event handler. * - * @param[in] objPtr - * Pointer to the object of a class defining the member callback - * function (@p memberPtr). - * @param[in] memberPtr - * The member callback (within the context of an object) to be - * invoked. + * The registered handler is invoked when the GattClient instance is + * about to be shut down. + * + * @param[in] objPtr Instance that will be used to invoke @p memberPtr. + * @param[in] memberPtr Event handler to invoke when a shutdown event is + * available. */ template - void onShutdown(T *objPtr, void (T::*memberPtr)(const GattClient *)) { + void onShutdown(T *objPtr, void (T::*memberPtr)(const GattClient *)) + { shutdownCallChain.add(objPtr, memberPtr); } /** - * @brief Provide access to the callchain of shutdown event callbacks. + * Get the callchain of shutdown event handlers. * * @return A reference to the shutdown event callbacks chain. * - * @note It is possible to register callbacks using onShutdown().add(callback). + * @note onShutdown().add(callback) may be used to register new handlers. * - * @note It is possible to unregister callbacks using onShutdown().detach(callback). + * @note onShutdown().detach(callback) may be used to unregister an handler. */ - GattClientShutdownCallbackChain_t& onShutdown() { + GattClientShutdownCallbackChain_t& onShutdown() + { return shutdownCallChain; } @@ -526,20 +703,25 @@ class GattClient { public: /** - * Notify all registered onShutdown callbacks that the GattClient is - * about to be shutdown and clear all GattClient state of the - * associated object. + * Reset the state of the GattClient instance. + * + * Prior to any state modification, shutdown event handlers are notified + * that the GattClient instance is about to be shut down. Then, running + * procedures end. Finally, the state of the instance is reset. + * + * @par implementation note * * This function is meant to be overridden in the platform-specific - * sub-class. Nevertheless, the sub-class is only expected to reset its - * state and not the data held in GattClient members. This shall be achieved - * by a call to GattClient::reset() from the sub-class' reset() + * subclass. Nevertheless, the subclass only resets its + * state and not the data held in GattClient members. This is achieved + * by a call to GattClient::reset() from the subclass' reset() * implementation. * * @return BLE_ERROR_NONE on success. */ - virtual ble_error_t reset(void) { - /* Notify that the instance is about to shutdown */ + virtual ble_error_t reset(void) + { + /* Notify that the instance is about to shut down. */ shutdownCallChain.call(this); shutdownCallChain.clear(); @@ -551,48 +733,52 @@ class GattClient { } protected: - GattClient() { + GattClient() + { /* Empty */ } /* Entry points for the underlying stack to report events back to the user. */ public: /** - * Helper function that notifies all registered handlers of an occurrence - * of a data read event. This function is meant to be called from the - * BLE stack specific implementation when a data read event occurs. + * Forward an attribute read event to all registered handlers. + * + * @important This function is meant to be called from the vendor + * implementation when an attribute read event occurs. * - * @param[in] params - * The data read parameters passed to the registered - * handlers. + * @param[in] params Attribute read event to pass to the registered handlers. */ - void processReadResponse(const GattReadCallbackParams *params) { + void processReadResponse(const GattReadCallbackParams *params) + { onDataReadCallbackChain(params); } /** - * Helper function that notifies all registered handlers of an occurrence - * of a data written event. This function is meant to be called from the - * BLE stack specific implementation when a data written event occurs. + * Forward an attribute written event to all registered handlers. * - * @param[in] params - * The data written parameters passed to the registered - * handlers. + * @important This function is meant to be called from the vendor + * implementation when an attribute written event occurs. + * + * @param[in] params Attribute written event to pass to the registered + * handlers. */ - void processWriteResponse(const GattWriteCallbackParams *params) { + void processWriteResponse(const GattWriteCallbackParams *params) + { onDataWriteCallbackChain(params); } /** - * Helper function that notifies all registered handlers of an occurrence - * of an update event. This function is meant to be called from the - * BLE stack specific implementation when an update event occurs. + * Forward a handle value notification or indication event to all registered + * handlers. + * + * @important This function is meant to be called from the vendor + * implementation when a notification or indication event is available. * - * @param[in] params - * The update event parameters passed to the registered - * handlers. + * @param[in] params Notification or Indication event to pass to the + * registered handlers. */ - void processHVXEvent(const GattHVXCallbackParams *params) { + void processHVXEvent(const GattHVXCallbackParams *params) + { if (onHVXCallbackChain) { onHVXCallbackChain(params); } @@ -600,22 +786,25 @@ class GattClient { protected: /** - * Callchain containing all registered callback handlers for data read + * Callchain containing all registered event handlers for data read * events. */ - ReadCallbackChain_t onDataReadCallbackChain; + ReadCallbackChain_t onDataReadCallbackChain; + /** - * Callchain containing all registered callback handlers for data write + * Callchain containing all registered event handlers for data write * events. */ - WriteCallbackChain_t onDataWriteCallbackChain; + WriteCallbackChain_t onDataWriteCallbackChain; + /** - * Callchain containing all registered callback handlers for update + * Callchain containing all registered event handlers for update * events. */ - HVXCallbackChain_t onHVXCallbackChain; + HVXCallbackChain_t onHVXCallbackChain; + /** - * Callchain containing all registered callback handlers for shutdown + * Callchain containing all registered event handlers for shutdown * events. */ GattClientShutdownCallbackChain_t shutdownCallChain; @@ -626,4 +815,10 @@ class GattClient { GattClient& operator=(const GattClient &); }; -#endif /* ifndef __GATT_CLIENT_H__ */ +/** + * @} + * @} + * @} + */ + +#endif /* ifndef MBED_GATT_CLIENT_H__ */ diff --git a/features/FEATURE_BLE/ble/GattServer.h b/features/FEATURE_BLE/ble/GattServer.h index 9264b87a00f..63e91539bb0 100644 --- a/features/FEATURE_BLE/ble/GattServer.h +++ b/features/FEATURE_BLE/ble/GattServer.h @@ -14,8 +14,8 @@ * limitations under the License. */ -#ifndef __GATT_SERVER_H__ -#define __GATT_SERVER_H__ +#ifndef MBED_GATT_SERVER_H__ +#define MBED_GATT_SERVER_H__ #include "Gap.h" #include "GattService.h" @@ -24,52 +24,138 @@ #include "GattCallbackParamTypes.h" #include "CallChainOfFunctionPointersWithContext.h" +/** + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup server + * @{ + */ + +/** + * Construct and operates a GATT server. + * + * A Gatt server is a collection of GattService; these services contain + * characteristics that a peer connected to the device may read or write. + * These characteristics may also emit updates to subscribed clients when their + * values change. + * + * @p Server Layout + * + * Application code can add a GattService object to the server with the help of + * the function addService(). That function registers all the GattCharacteristic + * enclosed in the service, as well as all the characteristics descriptors (see + * GattAttribute) these characteristics contain. Service registration assigns + * a unique handle to the various attributes being part of the service; this + * handle should be used for subsequent read or write of these components. + * + * There are no primitives defined to remove a single service; however, a call to + * the function reset() removes all services previously registered in the + * GattServer. + * + * @p Characteristic and attributes access + * + * Values of the characteristic and the characteristic descriptor present in the + * GattServer must be accessed through the handle assigned to them when the service + * has been registered; the GattServer class offers several flavors of read() + * and write() functions that retrieve or mutate an attribute value. + * + * Application code can query if a client has subscribed to a given + * characteristic's value update by invoking the function areUpdatesEnabled(). + * + * @p Events + * + * The GattServer allows application code to register several event handlers that + * can be used to monitor client and server activities: + * - onDataSent(): Register an event handler that is called when a + * characteristic value update has been sent to a client. + * - onDataWriten(): Register an event handler that is called when a + * client has written an attribute of the server. + * - onDataRead(): Register an event handler that is called when a + * client has read an attribute of the server. + * - onUpdatesEnabled: Register an event handler that is called when a + * client subscribes to updates of a characteristic. + * - onUpdatesDisabled: Register an event handler that is called when a + * client unsubscribes from updates of a characteristic. + * - onConfimationReceived: Register an event handler that is called + * when a client acknowledges a characteristic value notification. + * + * @note The term characteristic value update is used to represent + * Characteristic Value Notification and Characteristic Value Indication when + * the nature of the server initiated is not relevant. + */ class GattServer { public: /** - * Type for the registered callbacks added to the data sent callchain. - * Refer to GattServer::onDataSent(). + * Event handler invoked when the server has sent data to a client. + * + * @see onDataSent(). */ typedef FunctionPointerWithContext DataSentCallback_t; + /** - * Type for the data sent event callchain. Refer to GattServer::onDataSent(). + * Callchain of DataSentCallback_t objects. + * + * @see onDataSent(). */ - typedef CallChainOfFunctionPointersWithContext DataSentCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + DataSentCallbackChain_t; /** - * Type for the registered callbacks added to the data written callchain. - * Refer to GattServer::onDataWritten(). + * Event handler invoked when the client has written an attribute of the + * server. + * + * @see onDataWritten(). */ - typedef FunctionPointerWithContext DataWrittenCallback_t; + typedef FunctionPointerWithContext + DataWrittenCallback_t; + /** - * Type for the data written event callchain. Refer to GattServer::onDataWritten(). + * Callchain of DataWrittenCallback_t objects. + * + * @see onDataWritten(). */ - typedef CallChainOfFunctionPointersWithContext DataWrittenCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + DataWrittenCallbackChain_t; /** - * Type for the registered callbacks added to the data read callchain. - * Refer to GattServer::onDataRead(). + * Event handler invoked when the client has read an attribute of the server. + * + * @see onDataRead(). */ - typedef FunctionPointerWithContext DataReadCallback_t; + typedef FunctionPointerWithContext + DataReadCallback_t; + /** - * Type for the data read event callchain. Refer to GattServer::onDataRead(). + * Callchain of DataReadCallback_t. + * + * @see onDataRead(). */ - typedef CallChainOfFunctionPointersWithContext DataReadCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + DataReadCallbackChain_t; /** - * Type for the registered callbacks added to the shutdown callchain. - * Refer to GattServer::onShutdown(). + * Event handler invoked when the GattServer is reset. + * + * @see onShutdown() reset() */ - typedef FunctionPointerWithContext GattServerShutdownCallback_t; + typedef FunctionPointerWithContext + GattServerShutdownCallback_t; + /** - * Type for the shutdown event callchain. Refer to GattServer::onShutdown(). + * Callchain of GattServerShutdownCallback_t. + * + * @see onShutdown() reset() */ - typedef CallChainOfFunctionPointersWithContext GattServerShutdownCallbackChain_t; + typedef CallChainOfFunctionPointersWithContext + GattServerShutdownCallbackChain_t; /** - * Type for the registered callback for various events. Refer to - * GattServer::onUpdatesEnabled(), GattServer::onUpdateDisabled() and - * GattServer::onConfirmationReceived(). + * Event handler that handles subscription to characteristic updates, + * unsubscription from characteristic updates and notification confirmation. + * + * @see onUpdatesEnabled() onUpdateDisabled() onConfirmationReceived() */ typedef FunctionPointerWithContext EventCallback_t; @@ -86,138 +172,175 @@ class GattServer { updatesEnabledCallback(NULL), updatesDisabledCallback(NULL), confirmationReceivedCallback(NULL) { - /* empty */ } /* - * The following functions are meant to be overridden in the platform-specific sub-class. + * The following functions are meant to be overridden in the platform + * specific subclass. */ public: /** - * Add a service declaration to the local server ATT table. Also add the - * characteristics contained within. + * Add a service declaration to the local attribute server table. + * + * This functions inserts a service declaration in the attribute table + * followed by the characteristic declarations (including characteristic + * descriptors) present in @p service. * - * @param[in] service - * The service to be added. + * The process assigns a unique attribute handle to all the elements added + * into the attribute table. This handle is an ID that must be used for + * subsequent interractions with the elements. + * + * @note There is no mirror function that removes a single service. + * Application code can remove all the registered services by calling + * reset(). + * + * @important Service, characteristics and descriptors objects registered + * within the GattServer must remain reachable until reset() is called. + * + * @param[in] service The service to be added; attribute handle of services, + * characteristic and characteristic descriptors are updated by the + * process. * * @return BLE_ERROR_NONE if the service was successfully added. */ - virtual ble_error_t addService(GattService &service) { + virtual ble_error_t addService(GattService &service) + { /* Avoid compiler warnings about unused variables. */ (void)service; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Read the value of a characteristic from the local GATT server. + * Read the value of an attribute present in the local GATT server. * - * @param[in] attributeHandle - * Attribute handle for the value attribute of the characteristic. - * @param[out] buffer - * A buffer to hold the value being read. - * @param[in,out] lengthP - * Length of the buffer being supplied. If the attribute - * value is longer than the size of the supplied buffer, - * this variable will hold upon return the total attribute value length - * (excluding offset). The application may use this - * information to allocate a suitable buffer size. + * @param[in] attributeHandle Handle of the attribute to read. + * @param[out] buffer A buffer to hold the value being read. + * @param[in,out] lengthP Length of the buffer being supplied. If the + * attribute value is longer than the size of the supplied buffer, this + * variable holds upon return the total attribute value length (excluding + * offset). The application may use this information to allocate a suitable + * buffer size. * * @return BLE_ERROR_NONE if a value was read successfully into the buffer. + * + * @important read(Gap::Handle_t, GattAttribute::Handle_t, uint8_t *, uint16_t *) + * must be used to read Client Characteristic Configuration Descriptor (CCCD) + * because the value of this type of attribute depends on the connection. */ - virtual ble_error_t read(GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP) { + virtual ble_error_t read( + GattAttribute::Handle_t attributeHandle, + uint8_t buffer[], + uint16_t *lengthP + ) { /* Avoid compiler warnings about unused variables. */ (void)attributeHandle; (void)buffer; (void)lengthP; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Read the value of a characteristic from the local GATT server. + * Read the value of an attribute present in the local GATT server. * - * @param[in] connectionHandle - * Connection handle. - * @param[in] attributeHandle - * Attribute handle for the value attribute of the characteristic. - * @param[out] buffer - * A buffer to hold the value being read. - * @param[in,out] lengthP - * Length of the buffer being supplied. If the attribute - * value is longer than the size of the supplied buffer, - * this variable will hold upon return the total attribute value length - * (excluding offset). The application may use this - * information to allocate a suitable buffer size. + * The connection handle allows application code to read the value of a + * Client Characteristic Configuration Descriptor for a given connection. * - * @return BLE_ERROR_NONE if a value was read successfully into the buffer. + * @param[in] connectionHandle Connection handle. + * @param[in] attributeHandle Attribute handle for the value attribute of + * the characteristic. + * @param[out] buffer A buffer to hold the value being read. + * @param[in,out] lengthP Length of the buffer being supplied. If the + * attribute value is longer than the size of the supplied buffer, this + * variable holds upon return the total attribute value length (excluding + * offset). The application may use this information to allocate a suitable + * buffer size. * - * @note This API is a version of the above, with an additional connection handle - * parameter to allow fetches for connection-specific multivalued - * attributes (such as the CCCDs). + * @return BLE_ERROR_NONE if a value was read successfully into the buffer. */ - virtual ble_error_t read(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t *buffer, uint16_t *lengthP) { + virtual ble_error_t read( + Gap::Handle_t connectionHandle, + GattAttribute::Handle_t attributeHandle, + uint8_t *buffer, + uint16_t *lengthP + ) { /* Avoid compiler warnings about unused variables. */ (void)connectionHandle; (void)attributeHandle; (void)buffer; (void)lengthP; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Update the value of a characteristic on the local GATT server. + * Update the value of an attribute present in the local GATT server. * - * @param[in] attributeHandle - * Handle for the value attribute of the characteristic. - * @param[in] value - * A pointer to a buffer holding the new value. - * @param[in] size - * Size of the new value (in bytes). - * @param[in] localOnly - * Should this update be kept on the local - * GATT server regardless of the state of the - * notify/indicate flag in the CCCD for this - * Characteristic? If set to true, no notification - * or indication is generated. + * @param[in] attributeHandle Handle of the attribute to write. + * @param[in] value A pointer to a buffer holding the new value. + * @param[in] size Size in bytes of the new value (in bytes). + * @param[in] localOnly If this flag is false and the attribute handle + * written is a characteristic value, then the server sends an update + * containing the new value to all clients that have subscribed to the + * characteristic's notifications or indications. Otherwise, the update does + * not generate a single server initiated event. * - * @return BLE_ERROR_NONE if we have successfully set the value of the attribute. + * @return BLE_ERROR_NONE if the attribute value has been successfully + * updated. */ - virtual ble_error_t write(GattAttribute::Handle_t attributeHandle, const uint8_t *value, uint16_t size, bool localOnly = false) { + virtual ble_error_t write( + GattAttribute::Handle_t attributeHandle, + const uint8_t *value, + uint16_t size, + bool localOnly = false + ) { /* Avoid compiler warnings about unused variables. */ (void)attributeHandle; (void)value; (void)size; (void)localOnly; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Update the value of a characteristic on the local GATT server. A version - * of the same as the above, with a connection handle parameter to allow updates - * for connection-specific multivalued attributes (such as the CCCDs). - * - * @param[in] connectionHandle - * Connection handle. - * @param[in] attributeHandle - * Handle for the value attribute of the characteristic. - * @param[in] value - * A pointer to a buffer holding the new value. - * @param[in] size - * Size of the new value (in bytes). - * @param[in] localOnly - * Should this update be kept on the local - * GattServer regardless of the state of the - * notify/indicate flag in the CCCD for this - * Characteristic? If set to true, no notification - * or indication is generated. - * - * @return BLE_ERROR_NONE if we have successfully set the value of the attribute. - */ - virtual ble_error_t write(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, const uint8_t *value, uint16_t size, bool localOnly = false) { + * Update the value of an attribute present in the local GATT server. + * + * The connection handle parameter allows application code to direct + * notification or indication resulting from the update to a specific client. + * + * @param[in] connectionHandle Connection handle. + * @param[in] attributeHandle Handle for the value attribute of the + * characteristic. + * @param[in] value A pointer to a buffer holding the new value. + * @param[in] size Size of the new value (in bytes). + * @param[in] localOnly If this flag is false and the attribute handle + * written is a characteristic value, then the server sends an update + * containing the new value to the client identified by the parameter + * @p connectionHandle if it is subscribed to the characteristic's + * notifications or indications. Otherwise, the update does not generate a + * single server initiated event. + * + * @return BLE_ERROR_NONE if the attribute value has been successfully + * updated. + */ + virtual ble_error_t write( + Gap::Handle_t connectionHandle, + GattAttribute::Handle_t attributeHandle, + const uint8_t *value, + uint16_t size, + bool localOnly = false + ) { /* Avoid compiler warnings about unused variables. */ (void)connectionHandle; (void)attributeHandle; @@ -225,185 +348,189 @@ class GattServer { (void)size; (void)localOnly; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Determine the updates-enabled status (notification or indication) for the current connection from a characteristic's CCCD. + * Determine if one of the connected clients has subscribed to notifications + * or indications of the characteristic in input. * - * @param[in] characteristic - * The characteristic. - * @param[out] enabledP - * Upon return, *enabledP is true if updates are enabled, else false. + * @param[in] characteristic The characteristic. + * @param[out] enabledP Upon return, *enabledP is true if updates are + * enabled for a connected client; otherwise, *enabledP is false. * - * @return BLE_ERROR_NONE if the connection and handle are found. False otherwise. + * @return BLE_ERROR_NONE if the connection and handle are found. False + * otherwise. */ - virtual ble_error_t areUpdatesEnabled(const GattCharacteristic &characteristic, bool *enabledP) { + virtual ble_error_t areUpdatesEnabled( + const GattCharacteristic &characteristic, + bool *enabledP + ) { /* Avoid compiler warnings about unused variables. */ (void)characteristic; (void)enabledP; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * Determine the connection-specific updates-enabled status (notification or indication) from a characteristic's CCCD. + * Determine if an identified client has subscribed to notifications or + * indications of a given characteristic. * - * @param[in] connectionHandle - * The connection handle. - * @param[in] characteristic - * The characteristic. - * @param[out] enabledP - * Upon return, *enabledP is true if updates are enabled, else false. + * @param[in] connectionHandle The connection handle. + * @param[in] characteristic The characteristic. + * @param[out] enabledP Upon return, *enabledP is true if the client + * identified by @p connectionHandle has subscribed to notifications or + * indications of @p characteristic; otherwise, *enabledP is false. * - * @return BLE_ERROR_NONE if the connection and handle are found. False otherwise. + * @return BLE_ERROR_NONE if the connection and handle are found. False + * otherwise. */ - virtual ble_error_t areUpdatesEnabled(Gap::Handle_t connectionHandle, const GattCharacteristic &characteristic, bool *enabledP) { + virtual ble_error_t areUpdatesEnabled( + Gap::Handle_t connectionHandle, + const GattCharacteristic &characteristic, + bool *enabledP + ) { /* Avoid compiler warnings about unused variables. */ (void)connectionHandle; (void)characteristic; (void)enabledP; - return BLE_ERROR_NOT_IMPLEMENTED; /* Requesting action from porters: override this API if this capability is supported. */ + /* Requesting action from porters: override this API if this capability + is supported. */ + return BLE_ERROR_NOT_IMPLEMENTED; } /** - * A virtual function to allow underlying stacks to indicate if they support - * onDataRead(). It should be overridden to return true as applicable. + * Indicate if the underlying stack emit events when an attribute is read by + * a client. + * + * @important This function should be overridden to return true if + * applicable. * - * @return true if onDataRead is supported, false otherwise. + * @return true if onDataRead is supported; false otherwise. */ - virtual bool isOnDataReadAvailable() const { - return false; /* Requesting action from porters: override this API if this capability is supported. */ + virtual bool isOnDataReadAvailable() const + { + /* Requesting action from porters: override this API if this capability + is supported. */ + return false; } /* - * APIs with non-virtual implementations. + * APIs with nonvirtual implementations. */ public: /** - * Add a callback for the GATT event DATA_SENT (which is triggered when - * updates are sent out by GATT in the form of notifications). + * Add an event handler that monitors emission of characteristic value + * updates. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. * * @note It is possible to chain together multiple onDataSent callbacks - * (potentially from different modules of an application) to receive updates - * to characteristics. - * - * @note It is also possible to set up a callback into a member function of - * some object. + * (potentially from different modules of an application). */ - void onDataSent(const DataSentCallback_t& callback) { + void onDataSent(const DataSentCallback_t &callback) + { dataSentCallChain.add(callback); } /** - * Same as GattServer::onDataSent(), but allows the possibility to add an object - * reference and member function as handler for DATA_SENT event - * callbacks. + * Add an event handler that monitors emission of characteristic value + * updates. * - * @param[in] objPtr - * Pointer to the object of a class defining the member callback - * function (@p memberPtr). - * @param[in] memberPtr - * The member callback (within the context of an object) to be - * invoked. + * @param[in] objPtr Pointer to the instance that is used to invoke the + * event handler. + * @param[in] memberPtr Event handler being registered. It is a member + * function. */ template - void onDataSent(T *objPtr, void (T::*memberPtr)(unsigned count)) { + void onDataSent(T *objPtr, void (T::*memberPtr)(unsigned count)) + { dataSentCallChain.add(objPtr, memberPtr); } /** - * @brief Provide access to the callchain of DATA_SENT event callbacks. + * Access the callchain of data sent event handlers. * * @return A reference to the DATA_SENT event callback chain. */ - DataSentCallbackChain_t& onDataSent() { + DataSentCallbackChain_t &onDataSent() + { return dataSentCallChain; } /** - * Set up a callback for when an attribute has its value updated by or at the - * connected peer. For a peripheral, this callback is triggered when the local - * GATT server has an attribute updated by a write command from the peer. - * For a central, this callback is triggered when a response is received for - * a write request. - * - * @param[in] callback - * Event handler being registered. + * Set an event handler that is called after + * a connected peer has written an attribute. * - * @note It is possible to chain together multiple onDataWritten callbacks - * (potentially from different modules of an application) to receive updates - * to characteristics. Many services, such as DFU and UART, add their own - * onDataWritten callbacks behind the scenes to trap interesting events. + * @param[in] callback The event handler being registered. * - * @note It is also possible to set up a callback into a member function of - * some object. - * - * @note It is possible to unregister a callback using onDataWritten().detach(callback) + * @important It is possible to set multiple event handlers. Registered + * handlers may be removed with onDataWritten().detach(callback). */ - void onDataWritten(const DataWrittenCallback_t& callback) { + void onDataWritten(const DataWrittenCallback_t &callback) + { dataWrittenCallChain.add(callback); } /** - * Same as GattServer::onDataWritten(), but allows the possibility to add an object - * reference and member function as handler for data written event - * callbacks. + * Set an event handler that is called after + * a connected peer has written an attribute. * - * @param[in] objPtr - * Pointer to the object of a class defining the member callback - * function (@p memberPtr). - * @param[in] memberPtr - * The member callback (within the context of an object) to be - * invoked. + * @param[in] objPtr Pointer to the instance that is used to invoke the + * event handler (@p memberPtr). + * @param[in] memberPtr Event handler being registered. It is a member + * function. */ template - void onDataWritten(T *objPtr, void (T::*memberPtr)(const GattWriteCallbackParams *context)) { + void onDataWritten( + T *objPtr, + void (T::*memberPtr)(const GattWriteCallbackParams *context) + ) { dataWrittenCallChain.add(objPtr, memberPtr); } /** - * @brief Provide access to the callchain of data written event callbacks. + * Access the callchain of data written event handlers. * * @return A reference to the data written event callbacks chain. * - * @note It is possible to register callbacks using onDataWritten().add(callback). + * @note It is possible to register callbacks using + * onDataWritten().add(callback). * - * @note It is possible to unregister callbacks using onDataWritten().detach(callback). + * @note It is possible to unregister callbacks using + * onDataWritten().detach(callback). */ - DataWrittenCallbackChain_t& onDataWritten() { + DataWrittenCallbackChain_t &onDataWritten() + { return dataWrittenCallChain; } /** - * Setup a callback to be invoked on the peripheral when an attribute is - * being read by a remote client. + * Set an event handler that monitors attribute reads from connected clients. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. * * @return BLE_ERROR_NOT_IMPLEMENTED if this functionality isn't available; - * else BLE_ERROR_NONE. + * else BLE_ERROR_NONE. * * @note This functionality may not be available on all underlying stacks. - * You could use GattCharacteristic::setReadAuthorizationCallback() as an - * alternative. Refer to isOnDataReadAvailable(). - * - * @note It is possible to chain together multiple onDataRead callbacks - * (potentially from different modules of an application) to receive updates - * to characteristics. Services may add their own onDataRead callbacks - * behind the scenes to trap interesting events. + * Application code may work around that limitation by monitoring read + * requests instead of read events. * - * @note It is also possible to set up a callback into a member function of - * some object. + * @see GattCharacteristic::setReadAuthorizationCallback() + * @see isOnDataReadAvailable(). * - * @note It is possible to unregister a callback using onDataRead().detach(callback). + * @important It is possible to set multiple event handlers. Registered + * handlers may be removed with onDataRead().detach(callback). */ - ble_error_t onDataRead(const DataReadCallback_t& callback) { + ble_error_t onDataRead(const DataReadCallback_t &callback) + { if (!isOnDataReadAvailable()) { return BLE_ERROR_NOT_IMPLEMENTED; } @@ -413,19 +540,18 @@ class GattServer { } /** - * Same as GattServer::onDataRead(), but allows the possibility to add an object - * reference and member function as handler for data read event - * callbacks. + * Set an event handler that monitors attribute reads from connected clients. * - * @param[in] objPtr - * Pointer to the object of a class defining the member callback - * function (@p memberPtr). - * @param[in] memberPtr - * The member callback (within the context of an object) to be - * invoked. + * @param[in] objPtr Pointer to the instance that is used to invoke the + * event handler (@p memberPtr). + * @param[in] memberPtr Event handler being registered. It is a member + * function. */ template - ble_error_t onDataRead(T *objPtr, void (T::*memberPtr)(const GattReadCallbackParams *context)) { + ble_error_t onDataRead( + T *objPtr, + void (T::*memberPtr)(const GattReadCallbackParams *context) + ) { if (!isOnDataReadAvailable()) { return BLE_ERROR_NOT_IMPLEMENTED; } @@ -435,99 +561,104 @@ class GattServer { } /** - * @brief Provide access to the callchain of data read event callbacks. + * Access the callchain of data read event handlers. * * @return A reference to the data read event callbacks chain. * - * @note It is possible to register callbacks using onDataRead().add(callback). + * @note It is possible to register callbacks using + * onDataRead().add(callback). * - * @note It is possible to unregister callbacks using onDataRead().detach(callback). + * @note It is possible to unregister callbacks using + * onDataRead().detach(callback). */ - DataReadCallbackChain_t& onDataRead() { + DataReadCallbackChain_t &onDataRead() + { return dataReadCallChain; } /** - * Setup a callback to be invoked to notify the user application that the - * GattServer instance is about to shutdown (possibly as a result of a call - * to BLE::shutdown()). + * Set an event handler that monitors shutdown or reset of the GattServer. * - * @param[in] callback - * Event handler being registered. + * The event handler is invoked when the GattServer instance is about + * to be shut down. This can result in a call to reset() or BLE::reset(). * - * @note It is possible to chain together multiple onShutdown callbacks - * (potentially from different modules of an application) to be notified - * before the GattServer is shutdown. + * @param[in] callback Event handler being registered. * - * @note It is also possible to set up a callback into a member function of - * some object. + * @note It is possible to set up multiple shutdown event handlers. * - * @note It is possible to unregister a callback using onShutdown().detach(callback) + * @note It is possible to unregister a callback using + * onShutdown().detach(callback) */ - void onShutdown(const GattServerShutdownCallback_t& callback) { + void onShutdown(const GattServerShutdownCallback_t &callback) + { shutdownCallChain.add(callback); } /** - * Same as GattServer::onShutdown(), but allows the possibility to add an object - * reference and member function as handler for shutdown event - * callbacks. + * Set an event handler that monitors shutdown or reset of the GattServer. * - * @param[in] objPtr - * Pointer to the object of a class defining the member callback - * function (@p memberPtr). - * @param[in] memberPtr - * The member callback (within the context of an object) to be - * invoked. + * The event handler is invoked when the GattServer instance is about + * to be shut down. This can result of a call to reset() or BLE::reset(). + * + * @param[in] objPtr Pointer to the instance that is used to invoke the + * event handler (@p memberPtr). + * @param[in] memberPtr Event handler being registered. It is a member + * function. */ template - void onShutdown(T *objPtr, void (T::*memberPtr)(const GattServer *)) { + void onShutdown(T *objPtr, void (T::*memberPtr)(const GattServer *)) + { shutdownCallChain.add(objPtr, memberPtr); } /** - * @brief Provide access to the callchain of shutdown event callbacks. + * Access the callchain of shutdown event handlers. * * @return A reference to the shutdown event callbacks chain. * - * @note It is possible to register callbacks using onShutdown().add(callback). + * @note It is possible to register callbacks using + * onShutdown().add(callback). * - * @note It is possible to unregister callbacks using onShutdown().detach(callback). + * @note It is possible to unregister callbacks using + * onShutdown().detach(callback). */ - GattServerShutdownCallbackChain_t& onShutdown() { + GattServerShutdownCallbackChain_t& onShutdown() + { return shutdownCallChain; } /** - * Set up a callback for when notifications or indications are enabled for a - * characteristic on the local GATT server. + * Set up an event handler that monitors subscription to characteristic + * updates. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. */ - void onUpdatesEnabled(EventCallback_t callback) { + void onUpdatesEnabled(EventCallback_t callback) + { updatesEnabledCallback = callback; } /** - * Set up a callback for when notifications or indications are disabled for a - * characteristic on the local GATT server. + * Set up an event handler that monitors unsubscription from characteristic + * updates. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. */ - void onUpdatesDisabled(EventCallback_t callback) { + void onUpdatesDisabled(EventCallback_t callback) + { updatesDisabledCallback = callback; } /** - * Set up a callback for when the GATT server receives a response for an - * indication event sent previously. + * Set up an event handler that monitors notification acknowledgment. + * + * The event handler is called when a client sends a confirmation that it has + * correctly received a notification from the server. * - * @param[in] callback - * Event handler being registered. + * @param[in] callback Event handler being registered. */ - void onConfirmationReceived(EventCallback_t callback) { + void onConfirmationReceived(EventCallback_t callback) + { confirmationReceivedCallback = callback; } @@ -535,42 +666,50 @@ class GattServer { protected: /** * Helper function that notifies all registered handlers of an occurrence - * of a data written event. This function is meant to be called from the - * BLE stack specific implementation when a data written event occurs. + * of a data written event. + * + * @important Vendor implementation must invoke this function after one of + * the GattServer attributes has been written. * - * @param[in] params - * The data written parameters passed to the registered - * handlers. + * @param[in] params The data written parameters passed to the registered + * handlers. */ - void handleDataWrittenEvent(const GattWriteCallbackParams *params) { + void handleDataWrittenEvent(const GattWriteCallbackParams *params) + { dataWrittenCallChain.call(params); } /** * Helper function that notifies all registered handlers of an occurrence - * of a data read event. This function is meant to be called from the - * BLE stack specific implementation when a data read event occurs. + * of a data read event. * - * @param[in] params - * The data read parameters passed to the registered - * handlers. + * @important Vendor implementation must invoke this function after one of + * the GattServer attributes has been read. + * + * @param[in] params The data read parameters passed to the registered + * handlers. */ - void handleDataReadEvent(const GattReadCallbackParams *params) { + void handleDataReadEvent(const GattReadCallbackParams *params) + { dataReadCallChain.call(params); } /** * Helper function that notifies the registered handler of an occurrence - * of updates enabled, updates disabled and confirmation received events. - * This function is meant to be called from the BLE stack specific - * implementation when any of these events occurs. + * of updates enabled, updates disabled or confirmation received events. + * + * @important Vendor implementation must invoke this function when a client + * subscribes to characteristic updates, unsubscribes from characteristic + * updates or a notification confirmation has been received. * - * @param[in] type - * The type of event that occurred. - * @param[in] attributeHandle - * The handle of the attribute that was modified. + * @param[in] type The type of event that occurred. + * @param[in] attributeHandle The handle of the attribute concerned by the + * event. */ - void handleEvent(GattServerEvents::gattEvent_e type, GattAttribute::Handle_t attributeHandle) { + void handleEvent( + GattServerEvents::gattEvent_e type, + GattAttribute::Handle_t attributeHandle + ) { switch (type) { case GattServerEvents::GATT_EVENT_UPDATES_ENABLED: if (updatesEnabledCallback) { @@ -594,31 +733,33 @@ class GattServer { /** * Helper function that notifies all registered handlers of an occurrence - * of a data sent event. This function is meant to be called from the - * BLE stack specific implementation when a data sent event occurs. + * of a data sent event. * - * @param[in] count - * Number of packets sent. + * @important Vendor implementation must invoke this function after the + * emission of a notification or an indication. + * + * @param[in] count Number of packets sent. */ - void handleDataSentEvent(unsigned count) { + void handleDataSentEvent(unsigned count) + { dataSentCallChain.call(count); } public: /** - * Notify all registered onShutdown callbacks that the GattServer is - * about to be shutdown and clear all GattServer state of the - * associated object. + * Shut down the GattServer instance. + * + * This function notifies all event handlers listening for shutdown events + * that the GattServer is about to be shut down; then it clears all + * GattServer state. * - * This function is meant to be overridden in the platform-specific - * sub-class. Nevertheless, the sub-class is only expected to reset its - * state and not the data held in GattServer members. This shall be achieved - * by a call to GattServer::reset() from the sub-class' reset() - * implementation. + * @note This function is meant to be overridden in the platform-specific + * subclass. Overides must call the parent function before any cleanup. * * @return BLE_ERROR_NONE on success. */ - virtual ble_error_t reset(void) { + virtual ble_error_t reset(void) + { /* Notify that the instance is about to shutdown */ shutdownCallChain.call(this); shutdownCallChain.clear(); @@ -641,6 +782,7 @@ class GattServer { * The total number of services added to the ATT table. */ uint8_t serviceCount; + /** * The total number of characteristics added to the ATT table. */ @@ -651,34 +793,40 @@ class GattServer { * Callchain containing all registered callback handlers for data sent * events. */ - DataSentCallbackChain_t dataSentCallChain; + DataSentCallbackChain_t dataSentCallChain; + /** * Callchain containing all registered callback handlers for data written * events. */ - DataWrittenCallbackChain_t dataWrittenCallChain; + DataWrittenCallbackChain_t dataWrittenCallChain; + /** * Callchain containing all registered callback handlers for data read * events. */ - DataReadCallbackChain_t dataReadCallChain; + DataReadCallbackChain_t dataReadCallChain; + /** * Callchain containing all registered callback handlers for shutdown * events. */ GattServerShutdownCallbackChain_t shutdownCallChain; + /** * The registered callback handler for updates enabled events. */ - EventCallback_t updatesEnabledCallback; + EventCallback_t updatesEnabledCallback; + /** * The registered callback handler for updates disabled events. */ - EventCallback_t updatesDisabledCallback; + EventCallback_t updatesDisabledCallback; + /** * The registered callback handler for confirmation received events. */ - EventCallback_t confirmationReceivedCallback; + EventCallback_t confirmationReceivedCallback; private: /* Disallow copy and assignment. */ @@ -686,4 +834,10 @@ class GattServer { GattServer& operator=(const GattServer &); }; -#endif /* ifndef __GATT_SERVER_H__ */ +/** + * @} + * @} + * @} + */ + +#endif /* ifndef MBED_GATT_SERVER_H__ */ diff --git a/features/FEATURE_BLE/ble/GattServerEvents.h b/features/FEATURE_BLE/ble/GattServerEvents.h index d28d5680330..00fb68d3419 100644 --- a/features/FEATURE_BLE/ble/GattServerEvents.h +++ b/features/FEATURE_BLE/ble/GattServerEvents.h @@ -14,28 +14,73 @@ * limitations under the License. */ -#ifndef __GATT_SERVER_EVENTS_H__ -#define __GATT_SERVER_EVENTS_H__ +#ifndef MBED_BLE_GATT_SERVER_EVENTS_H__ +#define MBED_BLE_GATT_SERVER_EVENTS_H__ /** - * @brief The base class used to abstract away the callback events that can be - * triggered with the GATT Server. + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup server + * @{ + */ + +/** + * Abstract events generated by a GattServer vendor port. + * + * @important This class is not part of the public API. */ class GattServerEvents { public: /** - * Enumeration for GattServer events. + * Enumeration of events, which a GattServer + * implementation can generate. */ typedef enum gattEvent_e { - GATT_EVENT_DATA_SENT = 1, /**< Fired when a message was successfully sent out (notify only?) */ - GATT_EVENT_DATA_WRITTEN = 2, /**< Client wrote data to the server (separate into char and descriptor writes?) */ - GATT_EVENT_UPDATES_ENABLED = 3, /**< Notify/Indicate enabled in CCCD. */ - GATT_EVENT_UPDATES_DISABLED = 4, /**< Notify/Indicate disabled in CCCD. */ - GATT_EVENT_CONFIRMATION_RECEIVED = 5, /**< Response received from Indicate message. */ - GATT_EVENT_READ_AUTHORIZATION_REQ = 6, /**< Request application to authorize read. */ - GATT_EVENT_WRITE_AUTHORIZATION_REQ = 7, /**< Request application to authorize write. */ + /** + * Fired when a server event was successfully sent. + */ + GATT_EVENT_DATA_SENT = 1, + + /** + * Client has written a server attribute. + */ + GATT_EVENT_DATA_WRITTEN = 2, + + /** + * Notification or indication enabled in CCCD. + */ + GATT_EVENT_UPDATES_ENABLED = 3, + + /** + * Notification or Indication disabled in CCCD. + */ + GATT_EVENT_UPDATES_DISABLED = 4, + + /** + * Response received from Characteristic Value Indication message. + */ + GATT_EVENT_CONFIRMATION_RECEIVED = 5, + + /** + * Request application to authorize read. + */ + GATT_EVENT_READ_AUTHORIZATION_REQ = 6, + + /** + * Request application to authorize write. + */ + GATT_EVENT_WRITE_AUTHORIZATION_REQ = 7, + } gattEvent_t; }; -#endif /* ifndef __GATT_SERVER_EVENTS_H__ */ +/** + * @} + * @} + * @} + */ + +#endif /* ifndef MBED_BLE_GATT_SERVER_EVENTS_H__ */ diff --git a/features/FEATURE_BLE/ble/GattService.h b/features/FEATURE_BLE/ble/GattService.h index d638b3c9167..5918cffb4bb 100644 --- a/features/FEATURE_BLE/ble/GattService.h +++ b/features/FEATURE_BLE/ble/GattService.h @@ -14,56 +14,147 @@ * limitations under the License. */ -#ifndef __GATT_SERVICE_H__ -#define __GATT_SERVICE_H__ +#ifndef MBED_GATT_SERVICE_H__ +#define MBED_GATT_SERVICE_H__ #include "UUID.h" #include "GattCharacteristic.h" +/** + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup server + * @{ + */ + +/** + * Representation of a GattServer service. + * + * A service is a cohesive collection of characteristics. It is identified by a + * UUID and starts at a specific handle of its GattServer. + */ class GattService { public: enum { - UUID_ALERT_NOTIFICATION_SERVICE = 0x1811, - UUID_BATTERY_SERVICE = 0x180F, - UUID_BLOOD_PRESSURE_SERVICE = 0x1810, - UUID_CURRENT_TIME_SERVICE = 0x1805, - UUID_CYCLING_SPEED_AND_CADENCE = 0x1816, - UUID_DEVICE_INFORMATION_SERVICE = 0x180A, - UUID_ENVIRONMENTAL_SERVICE = 0x181A, - UUID_GLUCOSE_SERVICE = 0x1808, - UUID_HEALTH_THERMOMETER_SERVICE = 0x1809, - UUID_HEART_RATE_SERVICE = 0x180D, + /** + * UUID of the Alert Notification service. + */ + UUID_ALERT_NOTIFICATION_SERVICE = 0x1811, + + /** + * UUID of the Battery service. + */ + UUID_BATTERY_SERVICE = 0x180F, + + /** + * UUID of the Blood Pressure service. + */ + UUID_BLOOD_PRESSURE_SERVICE = 0x1810, + + /** + * UUID of the Current Time service. + */ + UUID_CURRENT_TIME_SERVICE = 0x1805, + + /** + * UUID of the Cycling Speed and Cadence (CSC) service. + */ + UUID_CYCLING_SPEED_AND_CADENCE = 0x1816, + + /** + * UUID of the Device Information Service (DIS). + */ + UUID_DEVICE_INFORMATION_SERVICE = 0x180A, + + /** + * UUID of the environmental service. + */ + UUID_ENVIRONMENTAL_SERVICE = 0x181A, + + /** + * UUID of the Glucose service. + */ + UUID_GLUCOSE_SERVICE = 0x1808, + + /** + * UUID of the health thermometer. + */ + UUID_HEALTH_THERMOMETER_SERVICE = 0x1809, + + /** + * UUID of the Heart Rate service. + */ + UUID_HEART_RATE_SERVICE = 0x180D, + + /** + * UUID of the Human Interface Device (HID) service. + */ UUID_HUMAN_INTERFACE_DEVICE_SERVICE = 0x1812, - UUID_IMMEDIATE_ALERT_SERVICE = 0x1802, - UUID_LINK_LOSS_SERVICE = 0x1803, - UUID_NEXT_DST_CHANGE_SERVICE = 0x1807, - UUID_PHONE_ALERT_STATUS_SERVICE = 0x180E, - UUID_REFERENCE_TIME_UPDATE_SERVICE = 0x1806, - UUID_RUNNING_SPEED_AND_CADENCE = 0x1814, - UUID_SCAN_PARAMETERS_SERVICE = 0x1813, - UUID_TX_POWER_SERVICE = 0x1804 + + /** + * UUID of the Immediate Alert service. + */ + UUID_IMMEDIATE_ALERT_SERVICE = 0x1802, + + /** + * UUID of the Link Loss service. + */ + UUID_LINK_LOSS_SERVICE = 0x1803, + + /** + * UUID of the Next DST change service. + */ + UUID_NEXT_DST_CHANGE_SERVICE = 0x1807, + + /** + * UUID of the Phone Alert Status service. + */ + UUID_PHONE_ALERT_STATUS_SERVICE = 0x180E, + + /** + * UUID of the Reference Time Update service. + */ + UUID_REFERENCE_TIME_UPDATE_SERVICE = 0x1806, + + /** + * UUID of the Running Speed and Cadence (RSC) service. + */ + UUID_RUNNING_SPEED_AND_CADENCE = 0x1814, + + /** + * UUID of the Scan Parameter service. + */ + UUID_SCAN_PARAMETERS_SERVICE = 0x1813, + + /** + * UUID of the TX power service. + */ + UUID_TX_POWER_SERVICE = 0x1804 }; public: /** - * @brief Creates a new GattService using the specified 16-bit - * UUID, value length, and properties. + * Construct a GattService. * - * @note The UUID value must be unique and is normally >1. + * @param[in] uuid The UUID assigned to this service. + * @param[in] characteristics A pointer to the array of characteristics that + * belongs to the service. + * @param[in] numCharacteristics The number of characteristics. * - * @param[in] uuid - * The UUID to use for this service. - * @param[in] characteristics - * A pointer to an array of characteristics to be included within this service. - * @param[in] numCharacteristics - * The number of characteristics. + * @important The characteristics of the service must remain valid while the + * GattServer uses the service. */ - GattService(const UUID &uuid, GattCharacteristic *characteristics[], unsigned numCharacteristics) : + GattService( + const UUID &uuid, + GattCharacteristic *characteristics[], + unsigned numCharacteristics + ) : _primaryServiceID(uuid), _characteristicCount(numCharacteristics), _characteristics(characteristics), _handle(0) { - /* empty */ } /** @@ -71,16 +162,18 @@ class GattService { * * @return A reference to the service's UUID. */ - const UUID &getUUID(void) const { + const UUID &getUUID(void) const + { return _primaryServiceID; } /** - * Get handle of the service declaration attribute in the ATT table. + * Get the handle of the service declaration attribute in the ATT table. * * @return The service's handle. */ - uint16_t getHandle(void) const { + uint16_t getHandle(void) const + { return _handle; } @@ -89,29 +182,32 @@ class GattService { * * @return The total number of characteristics within this service. */ - uint8_t getCharacteristicCount(void) const { + uint8_t getCharacteristicCount(void) const + { return _characteristicCount; } /** * Set the handle of the service declaration attribute in the ATT table. * - * @param[in] handle - * The service's handle. + * @important Application code must not use this API. + * + * @param[in] handle The service's handle. */ - void setHandle(uint16_t handle) { + void setHandle(uint16_t handle) + { _handle = handle; } /** * Get this service's characteristic at a specific index. * - * @param[in] index - * The index of the characteristic. + * @param[in] index The index of the characteristic. * * @return A pointer to the characteristic at index @p index. */ - GattCharacteristic *getCharacteristic(uint8_t index) { + GattCharacteristic *getCharacteristic(uint8_t index) + { if (index >= _characteristicCount) { return NULL; } @@ -123,22 +219,31 @@ class GattService { /** * This service's UUID. */ - UUID _primaryServiceID; + UUID _primaryServiceID; + /** * Total number of characteristics within this service. */ - uint8_t _characteristicCount; + uint8_t _characteristicCount; + /** * An array with pointers to the characteristics added to this service. */ GattCharacteristic **_characteristics; + /** * Handle of the service declaration attribute in the ATT table. * - * @note This handle is generally assigned by the underlying BLE stack when the - * service is added to the ATT table. + * @note The underlying BLE stack generally assigns this handle when the + * service is added to the ATT table. */ - uint16_t _handle; + uint16_t _handle; }; -#endif /* ifndef __GATT_SERVICE_H__ */ +/** + * @} + * @} + * @} + */ + +#endif /* ifndef MBED_GATT_SERVICE_H__ */ diff --git a/features/FEATURE_BLE/ble/SafeBool.h b/features/FEATURE_BLE/ble/SafeBool.h index 9c9cbf8ac54..9a4836b5633 100644 --- a/features/FEATURE_BLE/ble/SafeBool.h +++ b/features/FEATURE_BLE/ble/SafeBool.h @@ -17,12 +17,25 @@ #ifndef BLE_API_SAFE_BOOL_H_ #define BLE_API_SAFE_BOOL_H_ -/* Safe bool idiom, see : http://www.artima.com/cppsource/safebool.html */ +/* Safe bool idiom, see: http://www.artima.com/cppsource/safebool.html */ +/** + * @file + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ + +/** + * Private namespace used to host details of the SafeBool implementation. + */ namespace SafeBool_ { /** - * @brief Base class for all intances of SafeBool. - * This base class reduces instantiation of trueTag function. + * Base class of all SafeBool instances. + * + * This nontemplate base class exists to reduce the number of instantiation of + * the trueTag function. */ class base { template @@ -30,17 +43,17 @@ class base { protected: /** - * The bool type is a pointer to method which can be used in boolean context. + * The bool type is a pointer to method that can be used in boolean context. */ typedef void (base::*BoolType_t)() const; /** - * Non implemented call, use to disallow conversion between unrelated types. + * Nonimplemented call, use to disallow conversion between unrelated types. */ void invalidTag() const; /** - * Member function which indicate true value. + * Special member function that indicates a true value. */ void trueTag() const {} }; @@ -49,9 +62,14 @@ class base { } /** - * @brief template class SafeBool use CRTP to made boolean conversion easy and correct. - * Derived class should implement the function bool toBool() const to make this work. Inheritance - * should be public. + * Safe conversion of objects in boolean context. + * + * Classes wanting evaluation of their instances in boolean context must derive + * publicly from this class rather than implementing the easy to misuse + * operator bool(). + * + * Descendant classes must implement the function bool toBool() const to enable + * the safe conversion in boolean context. * * @tparam T Type of the derived class * @@ -61,7 +79,7 @@ class base { * public: * * // boolean conversion - * bool toBool() { + * bool toBool() const { * * } * }; @@ -87,17 +105,17 @@ class base { * if(a == b) { * * } - * - * * @endcode */ template class SafeBool : public SafeBool_::base { public: /** - * Bool operator implementation, derived class has to provide bool toBool() const function. + * Bool operator implementation, derived class must provide a bool + * toBool() const function. */ - operator BoolType_t() const { + operator BoolType_t() const + { return (static_cast(this))->toBool() ? &SafeBool::trueTag : 0; } @@ -105,20 +123,32 @@ class SafeBool : public SafeBool_::base { /** * Avoid conversion to bool between different classes. + * + * @important Will generate a compile time error if instantiated. */ template -void operator==(const SafeBool& lhs,const SafeBool& rhs) { +void operator==(const SafeBool& lhs,const SafeBool& rhs) +{ lhs.invalidTag(); // return false; } /** * Avoid conversion to bool between different classes. + * + * @important Will generate a compile time error if instantiated. */ template -void operator!=(const SafeBool& lhs,const SafeBool& rhs) { +void operator!=(const SafeBool& lhs,const SafeBool& rhs) +{ lhs.invalidTag(); // return false; } +/** + * @} + * @} + */ + + #endif /* BLE_API_SAFE_BOOL_H_ */ diff --git a/features/FEATURE_BLE/ble/SafeEnum.h b/features/FEATURE_BLE/ble/SafeEnum.h new file mode 100644 index 00000000000..0f9a0a55540 --- /dev/null +++ b/features/FEATURE_BLE/ble/SafeEnum.h @@ -0,0 +1,155 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_SAFE_ENUM_H_ +#define BLE_SAFE_ENUM_H_ + +#include +#include + +namespace ble { + +/** + * Helper class used to define safe enumerations. + * + * C++ 98 enums expose different security holes: + * - Scope The scope of the enum is the scope defining it. In other words, + * enumerator defined at namespace scope are in the same scope that other + * enumerator defined in that namespace even if they belong to a different + * enumeration. + * As a result it is really easy to collide names between two different + * enumerators. At the end, the programmer has to protect its declaration + * with long prefixing. + * - Unsafe comparison: enumerators really just are named integer and can be + * implicitly converted to integer. As a result it is possible to compare + * value of different enum type. + * - Layout: The layout type of enumerations is implementation defined. + * + * This template class expose a framework to overcome those issues: + * + * First enum has to be defined in a structure which inherit from this class. + * The target type is the name of the structure containing the enumeration + * while LayoutType is the inner type used to stored the enum. + * + * Comparison operator are provided so it is not possible to compare a SafeEnum + * of a type to another SafeEnum of a different type. + * + * Implicit conversion to integer is not defined, users have to either use the + * value function which return the integer value stored in an EnumType. Client + * class can also define their own conversion operation. + * + * @tparam Target structure containing the enumeration definition. + * @tparam LayoutType Inner type used to store enumeration value. + * + * @code + + struct color_t : SafeEnum { + enum type { + RED, + GREEN, + BLACK + }; + + color_t(type) : SafeEnum(type) { } + }; + + // use an uint8_t to store the enumeration value + struct shape_t : SafeEnum { + enum type { + RECTANGLE, + CIRCLE, + TRIANGLE + }; + + shape_t(type) : SafeEnum(type) { } + }; + + // shape enumerator is in the shape_t scope. + shape_t shape = shape_t::RECTANGLE; + + shape_t shape = color_t::RED; // Compilation error + + if (shape == shape_t::CIRCLE) { + } + + // compilation error + if (shape == color_t::RED) { + + } + + void sink(shape_t); (1) + void sink(color_t); (2) + + sink(shape); // use overload (1) + sink(color); // use overload (2) + + // explicit access to the value is mandatory when a SafeEnum value is used + // as the condition in a switch statement + switch(shape.value()) { + case shape_t::RECTANGLE: + break; + } + + * @endcode + */ +template +struct SafeEnum { + + /** + * Construction of an enumeration value. + */ + SafeEnum(LayoutType value) : _value(value) { } + + /** + * Equal to operator for SafeEnum instances. + * + * @param lhs left hand side of the comparison + * @param rhs right hand side of the comparison + * + * @return true if the inner value of lhs and rhs are equal and false + * otherwise. + */ + friend bool operator==(SafeEnum lhs, SafeEnum rhs) { + return lhs._value == rhs._value; + } + + /** + * Not equal to operator for SafeEnum instances. + * + * @param lhs left hand side of the comparison + * @param rhs right hand side of the comparison + * + * @return true if the inner value of lhs and rhs are not equal and false + * otherwise. + */ + friend bool operator!=(SafeEnum lhs, SafeEnum rhs) { + return !(lhs == rhs); + } + + /** + * Explicit access to the inner value of the SafeEnum instance. + */ + LayoutType value() const { + return _value; + } + +private: + LayoutType _value; +}; + +} // namespace ble + +#endif /* BLE_SAFE_ENUM_H_ */ diff --git a/features/FEATURE_BLE/ble/ServiceDiscovery.h b/features/FEATURE_BLE/ble/ServiceDiscovery.h index 5e56f59f62b..7712d5e90e2 100644 --- a/features/FEATURE_BLE/ble/ServiceDiscovery.h +++ b/features/FEATURE_BLE/ble/ServiceDiscovery.h @@ -14,8 +14,8 @@ * limitations under the License. */ -#ifndef __SERVICE_DISOVERY_H__ -#define __SERVICE_DISOVERY_H__ +#ifndef MBED_BLE_SERVICE_DISOVERY_H__ +#define MBED_BLE_SERVICE_DISOVERY_H__ #include "UUID.h" #include "Gap.h" @@ -24,43 +24,68 @@ class DiscoveredService; class DiscoveredCharacteristic; +/** + * @addtogroup ble + * @{ + * @addtogroup gatt + * @{ + * @addtogroup client + * @{ + */ + +/** + * Host callback types needed by the service discovery procedure. + * + * This class is also an interface that may be used in vendor port to model + * the service discovery process. This interface is not used in user code. + * + * @important Implementing this interface is not a requirement for the + * implementation of the service discover process. + */ class ServiceDiscovery { public: - /* - * Exposed application callback types. - */ - /** - * Callback type for when a matching service is found during service- - * discovery. The receiving function is passed in a pointer to a - * DiscoveredService object, which will remain valid for the lifetime of the - * callback. Memory for this object is owned by the BLE_API eventing - * framework. The application can safely make a persistent shallow-copy of - * this object to work with the service beyond the callback. + * Service discovered event handler. + * + * The callback accepts a pointer to a DiscoveredService as parameter. + * + * @important The argument passed to the callback may not persist after the + * callback invocation; therefore, the callbacks must make a shallow copy + * of the DiscoveredService passed as parameter to access its value beyond + * the callback scope. */ - typedef FunctionPointerWithContext ServiceCallback_t; + typedef FunctionPointerWithContext + ServiceCallback_t; /** - * Callback type for when a matching characteristic is found during service- - * discovery. The receiving function is passed in a pointer to a - * DiscoveredCharacteristic object, which will remain valid for the lifetime - * of the callback. Memory for this object is owned by the BLE_API eventing - * framework. The application can safely make a persistent shallow-copy of - * this object to work with the characteristic beyond the callback. + * Characteristic discovered event handler. + * + * The callback accepts a pointer to a DiscoveredCharacteristic as + * parameter. + * + * @important The argument passed to the callback may not persist after the + * callback invocation; therefore, the callbacks must make a shallow copy + * of the DiscoveredCharacteristic passed as parameter to access its value + * beyond the callback scope. */ - typedef FunctionPointerWithContext CharacteristicCallback_t; + typedef FunctionPointerWithContext + CharacteristicCallback_t; /** - * Callback type for when serviceDiscovery terminates. + * Service discovery ended event. + * + * The callback accepts a connection handle as parameter. This + * parameter is used to identify on which connection the service discovery + * process ended. */ typedef FunctionPointerWithContext TerminationCallback_t; public: /** - * Launch service discovery. Once launched, service discovery will remain + * Launch service discovery. Once launched, service discovery remains * active with callbacks being issued back into the application for matching * services or characteristics. isActive() can be used to determine status, and - * a termination callback (if set up) will be invoked at the end. Service + * a termination callback (if set up) is invoked at the end. Service * discovery can be terminated prematurely, if needed, using terminate(). * * @param connectionHandle @@ -85,24 +110,24 @@ class ServiceDiscovery { * characteristic. * @param matchingServiceUUID * UUID-based filter for specifying a service in which the application is - * interested. By default it is set as the wildcard UUID_UNKNOWN, + * interested. By default, it is set as the wildcard UUID_UNKNOWN, * in which case it matches all services. If characteristic-UUID * filter (below) is set to the wildcard value, then a service - * callback will be invoked for the matching service (or for every + * callback is invoked for the matching service (or for every * service if the service filter is a wildcard). * @param matchingCharacteristicUUIDIn * UUID-based filter for specifying a characteristic in which the application - * is interested. By default it is set as the wildcard UUID_UKNOWN + * is interested. By default, it is set as the wildcard UUID_UKNOWN * to match against any characteristic. If both service-UUID - * filter and characteristic-UUID filter are used with non-wildcard + * filter and characteristic-UUID filter are used with nonwildcard * values, then only a single characteristic callback is * invoked for the matching characteristic. * * @note Using wildcard values for both service-UUID and characteristic- - * UUID will result in complete service discovery: callbacks being + * UUID result in complete service discovery: callbacks being * called for every service and characteristic. * - * @note Providing NULL for the characteristic callback will result in + * @note Providing NULL for the characteristic callback results in * characteristic discovery being skipped for each matching * service. This allows for an inexpensive method to discover only * services. @@ -136,9 +161,9 @@ class ServiceDiscovery { * Clear all ServiceDiscovery state of the associated object. * * This function is meant to be overridden in the platform-specific - * sub-class. Nevertheless, the sub-class is only expected to reset its - * state and not the data held in ServiceDiscovery members. This shall be - * achieved by a call to ServiceDiscovery::reset() from the sub-class' + * subclass. Nevertheless, the subclass is only expected to reset its + * state and not the data held in ServiceDiscovery members. This is + * achieved by a call to ServiceDiscovery::reset() from the subclass' * reset() implementation. * * @return BLE_ERROR_NONE on success. @@ -180,4 +205,10 @@ class ServiceDiscovery { CharacteristicCallback_t characteristicCallback; }; -#endif /* ifndef __SERVICE_DISOVERY_H__ */ +/** + * @} + * @} + * @} + */ + +#endif /* ifndef MBED_BLE_SERVICE_DISOVERY_H__ */ diff --git a/features/FEATURE_BLE/ble/UUID.h b/features/FEATURE_BLE/ble/UUID.h index 2379412e2b0..6e89f91a9cb 100644 --- a/features/FEATURE_BLE/ble/UUID.h +++ b/features/FEATURE_BLE/ble/UUID.h @@ -14,8 +14,8 @@ * limitations under the License. */ -#ifndef __UUID_H__ -#define __UUID_H__ +#ifndef MBED_UUID_H__ +#define MBED_UUID_H__ #include #include @@ -24,14 +24,22 @@ #include "blecommon.h" /** - * A trivial converter for single hexadecimal character to an unsigned integer. + * @file + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ + +/** + * Convert a character containing an hexadecimal digit into an unsigned integer. * - * @param c - * Hexadecimal character. + * @param[in] c Hexadecimal digit in a character representation. * * @return The corresponding value as unsigned integer. */ -static uint8_t char2int(char c) { +static uint8_t char2int(char c) +{ if ((c >= '0') && (c <= '9')) { return c - '0'; } else if ((c >= 'a') && (c <= 'f')) { @@ -44,72 +52,110 @@ static uint8_t char2int(char c) { } /** - * An instance of this class represents a Universally Unique Identifier (UUID) - * in the BLE API. + * Representation of a Universally Unique Identifier (UUID). + * + * UUIDs are 128-bit wide numbers used to identify data type and elements in + * many layers of the Bluetooth specification. + * + * Two representations of UUIDS exist: + * - 16-bit UUIDs: Shortened representation of the 128 bit UUID + * 0000xxxx-0000-1000-8000-00805F9B34FB where xxxx is the 16 bit UUID. + * Values of those UUIDs are defined by the Bluetooth body. The short + * representation saves bandwidth during protocol transactions. + * - 128-bit UUIDs: Complete representation of a UUID. They are commonly + * used for user defined UUID. + * + * This class acts as an adapter over these two kinds of UUIDs to allow + * indiscriminate use of both forms in Mbed BLE APIs. + * + * @note 32-bit UUID representation is not supported currently. */ class UUID { public: + /** - * Enumeration of the possible types of UUIDs in BLE with regards to length. + * Enumeration of the types of UUIDs. */ enum UUID_Type_t { - UUID_TYPE_SHORT = 0, /**< Short 16-bit UUID. */ - UUID_TYPE_LONG = 1 /**< Full 128-bit UUID. */ + /** + * 16-bit wide UUID representation. + */ + UUID_TYPE_SHORT = 0, + + /** + * 128-bit wide UUID representation. + */ + UUID_TYPE_LONG = 1 }; /** - * Enumeration to specify byte ordering of the long version of the UUID. + * Enumeration of byte ordering. + * + * It is used to construct 128-byte UUIDs. */ typedef enum { - MSB, /**< Most-significant byte first (at the smallest address) */ - LSB /**< least-significant byte first (at the smallest address) */ + /** + * Most significant byte first (at the smallest address). + */ + MSB, + + /** + * Least significant byte first (at the smallest address). + */ + LSB } ByteOrder_t; /** * Type for a 16-bit UUID. */ - typedef uint16_t ShortUUIDBytes_t; + typedef uint16_t ShortUUIDBytes_t; /** - * Length of a long UUID in bytes. + * Length in bytes of a long UUID. */ static const unsigned LENGTH_OF_LONG_UUID = 16; + /** * Type for a 128-bit UUID. */ - typedef uint8_t LongUUIDBytes_t[LENGTH_OF_LONG_UUID]; + typedef uint8_t LongUUIDBytes_t[LENGTH_OF_LONG_UUID]; /** - * Maximum length of a string representation of a UUID not including the - * null termination ('\0'): two characters per - * byte plus four '-' characters. + * Maximum length for the string representation of a UUID excluding the null + * terminator. + * + * The string is composed of two characters per byte plus four '-' + * characters. */ static const unsigned MAX_UUID_STRING_LENGTH = LENGTH_OF_LONG_UUID * 2 + 4; public: /** - * Creates a new 128-bit UUID. + * Construct a 128-bit UUID from a string. * - * @note The UUID is a unique 128-bit (16 byte) ID used to identify - * different service or characteristics on the BLE device. + * @param[in] stringUUID Human readable representation of the UUID following + * the format XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX. * - * @param stringUUID - * The 128-bit (16-byte) UUID as a human readable const-string. - * Format: XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX - * Upper and lower case supported. Hyphens are optional, but only - * upto four of them. The UUID is stored internally as a 16 byte - * array, LSB (little endian), which is opposite from the string. + * @note Upper and lower case are supported. + * @note Hyphens are optional. The string must include at most four hyphens. + * + * @note Internally, the UUID is stored in the little endian order as a + * 16-byte array. */ - UUID(const char* stringUUID) : type(UUID_TYPE_LONG), baseUUID(), shortUUID(0) { + UUID(const char* stringUUID) : + type(UUID_TYPE_LONG), + baseUUID(), + shortUUID(0) + { bool nibble = false; uint8_t byte = 0; size_t baseIndex = 0; uint8_t tempUUID[LENGTH_OF_LONG_UUID]; /* - * Iterate through string, abort if NULL is encountered prematurely. - * Ignore upto four hyphens. + * Iterate through string; abort if NULL is encountered prematurely. + * Ignore up to four hyphens. */ for (size_t index = 0; (index < MAX_UUID_STRING_LENGTH) && (baseIndex < LENGTH_OF_LONG_UUID); index++) { if (stringUUID[index] == '\0') { @@ -143,15 +189,10 @@ class UUID { } /** - * Creates a new 128-bit UUID. - * - * @param[in] longUUID - * The 128-bit (16-byte) UUID value. - * @param[in] order - * The bit order of the UUID, MSB by default. + * Construct a new UUID from a 128-bit representation. * - * @note The UUID is a unique 128-bit (16 byte) ID used to identify - * different service or characteristics on the BLE device. + * @param[in] longUUID The 128-bit (16-byte) of the UUID value. + * @param[in] order Bytes order of @p longUUID. */ UUID(const LongUUIDBytes_t longUUID, ByteOrder_t order = UUID::MSB) : type(UUID_TYPE_LONG), baseUUID(), shortUUID(0) { setupLong(longUUID, order); @@ -160,69 +201,59 @@ class UUID { /** * Creates a new 16-bit UUID. * - * For efficiency, and because 16 bytes would take a large chunk of the - * 27-byte data payload length of the Link Layer, the BLE specification adds - * two additional UUID formats: 16-bit and 32-bit UUIDs. These shortened - * formats can be used only with UUIDs that are defined in the Bluetooth - * specification (listed by the Bluetooth SIG as standard - * Bluetooth UUIDs). + * The Bluetooth standard body defines 16-bit wide UUIDs. They are the + * shortened version of the UUID 0000xxxx-0000-1000-8000-00805F9B34FB, where + * xxxx is the value of the 16-bit UUID. * - * To reconstruct the full 128-bit UUID from the shortened version, insert - * the 16-bit short value (indicated by xxxx, including leading zeros) into - * the Bluetooth Base UUID: + * @important 16-bit UUIDs are not used in user defined data type or + * user defined element ID. * - * 0000xxxx-0000-1000-8000-00805F9B34FB - * - * @param[in] _shortUUID + * @param[in] _shortUUID 16-bit part of the standard UUID. * The short UUID value. * - * @note Shortening is not available for UUIDs that are not derived from the - * Bluetooth Base UUID. Such non-standard UUIDs are commonly called - * vendor-specific UUIDs. In these cases, you’ll need to use the full - * 128-bit UUID value at all times. - * - * @note The UUID is a unique 16-bit (2 byte) ID used to identify - * different service or characteristics on the BLE device. - * - * @note We do not yet support 32-bit shortened UUIDs. + * @note User defined UUIDs are commonly named vendor-specific UUIDs across + * the Bluetooth literature. */ - UUID(ShortUUIDBytes_t _shortUUID) : type(UUID_TYPE_SHORT), baseUUID(), shortUUID(_shortUUID) { - /* Empty */ + UUID(ShortUUIDBytes_t _shortUUID) : + type(UUID_TYPE_SHORT), + baseUUID(), + shortUUID(_shortUUID) { } /** - * Copy constructor. + * UUID copy constructor. * - * @param[in] source - * The UUID to copy. + * @param[in] source The UUID to copy. */ - UUID(const UUID &source) { + UUID(const UUID &source) + { type = source.type; shortUUID = source.shortUUID; memcpy(baseUUID, source.baseUUID, LENGTH_OF_LONG_UUID); } /** - * The empty constructor. + * Default constructor. * - * @note The type of the resulting UUID instance is UUID_TYPE_SHORT and the - * value BLE_UUID_UNKNOWN. + * Construct an invalid UUID. + * + * @post shortOrLong() returns the value UUID_TYPE_SHORT. + * @post getShortUUID() returns the value BLE_UUID_UNKNOWN. */ - UUID(void) : type(UUID_TYPE_SHORT), shortUUID(BLE_UUID_UNKNOWN) { - /* empty */ + UUID(void) : + type(UUID_TYPE_SHORT), + shortUUID(BLE_UUID_UNKNOWN) { } /** - * Fill in a 128-bit UUID; this is useful when the UUID is not known at the - * time of the object construction. + * Replace existing value with a 128-bit UUID. * - * @param[in] longUUID - * The UUID value to copy. - * @param[in] order - * The byte ordering of the UUID at @p longUUID. + * @param[in] longUUID New 16-byte wide UUID value. + * @param[in] order Byte ordering of @p longUUID. */ - void setupLong(const LongUUIDBytes_t longUUID, ByteOrder_t order = UUID::MSB) { - type = UUID_TYPE_LONG; + void setupLong(const LongUUIDBytes_t longUUID, ByteOrder_t order = UUID::MSB) + { + type = UUID_TYPE_LONG; if (order == UUID::MSB) { /* * Switch endian. Input is big-endian, internal representation @@ -237,22 +268,24 @@ class UUID { public: /** - * Check whether this UUID is short or long. + * Return the internal type of the UUID. * - * @return UUID_TYPE_SHORT if the UUID is short, UUID_TYPE_LONG otherwise. + * @return UUID_TYPE_SHORT if the UUID is 16-bit wide. + * @return UUID_TYPE_LONG if the UUID is 128-bit wide. */ - UUID_Type_t shortOrLong(void) const { + UUID_Type_t shortOrLong(void) const + { return type; } /** * Get a pointer to the UUID value based on the current UUID type. * - * @return A pointer to the short UUID if the type is set to - * UUID_TYPE_SHORT. Otherwise, a pointer to the long UUID if the - * type is set to UUID_TYPE_LONG. + * @return A pointer to an uint16_t object if the UUID is 16 bits long. + * @return A pointer to an array of 16 bytes if the UUID is 128 bits long. */ - const uint8_t *getBaseUUID(void) const { + const uint8_t *getBaseUUID(void) const + { if (type == UUID_TYPE_SHORT) { return (const uint8_t*)&shortUUID; } else { @@ -261,33 +294,39 @@ class UUID { } /** - * Get the short UUID. + * Get the uint16_t value of the UUID. + * + * @important This function is not used on long UUIDs. * - * @return The short UUID. + * @return The value of the shortened UUID. */ - ShortUUIDBytes_t getShortUUID(void) const { + ShortUUIDBytes_t getShortUUID(void) const + { return shortUUID; } /** - * Get the length (in bytes) of the UUID based on its type. + * Get the length (in bytes) of the internal UUID representation. * - * @retval sizeof(ShortUUIDBytes_t) if the UUID type is UUID_TYPE_SHORT. - * @retval LENGTH_OF_LONG_UUID if the UUID type is UUID_TYPE_LONG. + * @return sizeof(ShortUUIDBytes_t) if the UUID type is UUID_TYPE_SHORT. + * @return LENGTH_OF_LONG_UUID if the UUID type is UUID_TYPE_LONG. */ - uint8_t getLen(void) const { - return ((type == UUID_TYPE_SHORT) ? sizeof(ShortUUIDBytes_t) : LENGTH_OF_LONG_UUID); + uint8_t getLen(void) const + { + return ((type == UUID_TYPE_SHORT) ? + sizeof(ShortUUIDBytes_t) : + LENGTH_OF_LONG_UUID); } /** - * Overload == operator to enable UUID comparisons. + * Equal to operator between UUIDs. * - * @param[in] other - * The other UUID in the comparison. + * @param[in] other The UUID to compare to this. * - * @return true if this == @p other, false otherwise. + * @return true if both UUIDs are equal and false otherwise. */ - bool operator== (const UUID &other) const { + bool operator== (const UUID &other) const + { if ((this->type == UUID_TYPE_SHORT) && (other.type == UUID_TYPE_SHORT) && (this->shortUUID == other.shortUUID)) { return true; @@ -302,30 +341,37 @@ class UUID { } /** - * Overload != operator to enable UUID comparisons. + * Not equal to operator. * - * @param[in] other - * The other UUID in the comparison. + * @param[in] other The UUID compared to this. * - * @return true if this != @p other, false otherwise. + * @return true if both UUIDs are not equal and false otherwise. */ - bool operator!= (const UUID &other) const { + bool operator!= (const UUID &other) const + { return !(*this == other); } private: /** - * The UUID type. Refer to UUID_Type_t. + * Representation type of the UUID. */ - UUID_Type_t type; + UUID_Type_t type; + /** - * The long UUID value. + * Container of UUID value if the UUID type is equal to UUID_TYPE_LONG. */ LongUUIDBytes_t baseUUID; + /** - * The short UUID value. + * Container of UUID value if the UUID type is equal to UUID_TYPE_SHORT. */ ShortUUIDBytes_t shortUUID; }; -#endif // ifndef __UUID_H__ +/** + * @} + * @} + */ + +#endif // ifndef MBED_UUID_H__ diff --git a/features/FEATURE_BLE/ble/blecommon.h b/features/FEATURE_BLE/ble/blecommon.h index 16fdec0580e..971f10c6aac 100644 --- a/features/FEATURE_BLE/ble/blecommon.h +++ b/features/FEATURE_BLE/ble/blecommon.h @@ -14,68 +14,234 @@ * limitations under the License. */ -#ifndef __BLE_COMMON_H__ -#define __BLE_COMMON_H__ +#ifndef MBED_BLE_COMMON_H__ +#define MBED_BLE_COMMON_H__ #ifdef __cplusplus extern "C" { #endif +/** + * @addtogroup ble + * @{ + * @addtogroup common + * @{ + */ -/*! @brief Assigned values for BLE UUIDs. */ +/** + * Assigned values for BLE UUIDs. + */ enum { - BLE_UUID_UNKNOWN = 0x0000, /**< Reserved UUID. */ - BLE_UUID_SERVICE_PRIMARY = 0x2800, /**< Primary Service. */ - BLE_UUID_SERVICE_SECONDARY = 0x2801, /**< Secondary Service. */ - BLE_UUID_SERVICE_INCLUDE = 0x2802, /**< Include. */ - BLE_UUID_CHARACTERISTIC = 0x2803, /**< Characteristic. */ - BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP = 0x2900, /**< Characteristic Extended Properties Descriptor. */ - BLE_UUID_DESCRIPTOR_CHAR_USER_DESC = 0x2901, /**< Characteristic User Description Descriptor. */ - BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG = 0x2902, /**< Client Characteristic Configuration Descriptor. */ - BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG = 0x2903, /**< Server Characteristic Configuration Descriptor. */ - BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT = 0x2904, /**< Characteristic Presentation Format Descriptor. */ - BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT = 0x2905, /**< Characteristic Aggregate Format Descriptor. */ + /** + * Reserved UUID. + */ + BLE_UUID_UNKNOWN = 0x0000, + + /** + * Primary Service. + */ + BLE_UUID_SERVICE_PRIMARY = 0x2800, + + /** + * Secondary Service. + */ + BLE_UUID_SERVICE_SECONDARY = 0x2801, + + /** + * Included service. + */ + BLE_UUID_SERVICE_INCLUDE = 0x2802, + + /** + * Characteristic. + */ + BLE_UUID_CHARACTERISTIC = 0x2803, + + /** + * Characteristic Extended Properties Descriptor. + */ + BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP = 0x2900, + + /** + * Characteristic User Description Descriptor. + */ + BLE_UUID_DESCRIPTOR_CHAR_USER_DESC = 0x2901, + + /** + * Client Characteristic Configuration Descriptor. + */ + BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG = 0x2902, + + /** + * Server Characteristic Configuration Descriptor. + */ + BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG = 0x2903, + + /** + * Characteristic Presentation Format Descriptor. + */ + BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT = 0x2904, + + /** + * Characteristic Aggregate Format Descriptor. + */ + BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT = 0x2905, /* GATT specific UUIDs */ - BLE_UUID_GATT = 0x1801, /**< Generic Attribute Profile. */ - BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED = 0x2A05, /**< Service Changed Characteristic. */ + /** + * Generic Attribute Profile. + */ + BLE_UUID_GATT = 0x1801, + + /** + * Service Changed Characteristic. + */ + BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED = 0x2A05, /* GAP specific UUIDs */ - BLE_UUID_GAP = 0x1800, /**< Generic Access Profile. */ - BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME = 0x2A00, /**< Device Name Characteristic. */ - BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE = 0x2A01, /**< Appearance Characteristic. */ - BLE_UUID_GAP_CHARACTERISTIC_PPF = 0x2A02, /**< Peripheral Privacy Flag Characteristic. */ - BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR = 0x2A03, /**< Reconnection Address Characteristic. */ - BLE_UUID_GAP_CHARACTERISTIC_PPCP = 0x2A04, /**< Peripheral Preferred Connection Parameters Characteristic. */ + + /** + * Generic Access Profile. + */ + BLE_UUID_GAP = 0x1800, + + /** + * Device Name Characteristic. + */ + BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME = 0x2A00, + + /** + * Appearance Characteristic. + */ + BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE = 0x2A01, + + /** + * Peripheral Privacy Flag Characteristic. + */ + BLE_UUID_GAP_CHARACTERISTIC_PPF = 0x2A02, + + /** + * Reconnection Address Characteristic. + */ + BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR = 0x2A03, + + /** + * Peripheral Preferred Connection Parameters Characteristic. + */ + BLE_UUID_GAP_CHARACTERISTIC_PPCP = 0x2A04, }; -/*! @brief Error codes for the BLE API. */ +/** + * Error codes for the BLE API. + * + * The value 0 means that no error was reported; therefore, it allows an API + * user to cleanly test for errors. + * + * @code + * ble_error_t error = some_ble_api_function(); + * if (error) { + * // handle the error + * } + * @endcode + */ enum ble_error_t { - BLE_ERROR_NONE = 0, /**< No error. */ - BLE_ERROR_BUFFER_OVERFLOW = 1, /**< The requested action would cause a buffer overflow and has been aborted. */ - BLE_ERROR_NOT_IMPLEMENTED = 2, /**< Requested a feature that isn't yet implemented or isn't supported by the target HW. */ - BLE_ERROR_PARAM_OUT_OF_RANGE = 3, /**< One of the supplied parameters is outside the valid range. */ - BLE_ERROR_INVALID_PARAM = 4, /**< One of the supplied parameters is invalid. */ - BLE_STACK_BUSY = 5, /**< The stack is busy. */ - BLE_ERROR_INVALID_STATE = 6, /**< Invalid state. */ - BLE_ERROR_NO_MEM = 7, /**< Out of memory */ - BLE_ERROR_OPERATION_NOT_PERMITTED = 8, + /** + * No error. + */ + BLE_ERROR_NONE = 0, + + /** + * The requested action would cause a buffer overflow and has been aborted. + */ + BLE_ERROR_BUFFER_OVERFLOW = 1, + + /** + * Requested a feature that isn't yet implemented or isn't supported by the + * target HW. + */ + BLE_ERROR_NOT_IMPLEMENTED = 2, + + /** + * One of the supplied parameters is outside the valid range. + */ + BLE_ERROR_PARAM_OUT_OF_RANGE = 3, + + /** + * One of the supplied parameters is invalid. + */ + BLE_ERROR_INVALID_PARAM = 4, + + /** + * The stack is busy. + */ + BLE_STACK_BUSY = 5, + + /** + * Invalid state. + */ + BLE_ERROR_INVALID_STATE = 6, + + /** + * Out of memory. + */ + BLE_ERROR_NO_MEM = 7, + + /** + * The operation requested is not permitted. + */ + BLE_ERROR_OPERATION_NOT_PERMITTED = 8, + + /** + * The BLE subsystem has not completed its initialization. + */ BLE_ERROR_INITIALIZATION_INCOMPLETE = 9, - BLE_ERROR_ALREADY_INITIALIZED = 10, - BLE_ERROR_UNSPECIFIED = 11, /**< Unknown error. */ - BLE_ERROR_INTERNAL_STACK_FAILURE = 12, /**< The platform-specific stack failed */ + + /** + * The BLE system has already been initialized. + */ + BLE_ERROR_ALREADY_INITIALIZED = 10, + + /** + * Unknown error. + */ + BLE_ERROR_UNSPECIFIED = 11, + + /** + * The platform-specific stack failed. + */ + BLE_ERROR_INTERNAL_STACK_FAILURE = 12, }; -/** @brief Default MTU size. */ +/** + * Default MTU size. + */ static const unsigned BLE_GATT_MTU_SIZE_DEFAULT = 23; +/** + * Handle Value Notification/Indication event. + * + * Emmitted when a notification or indication has been received from a GATT + * server. + */ enum HVXType_t { - BLE_HVX_NOTIFICATION = 0x01, /**< Handle Value Notification. */ - BLE_HVX_INDICATION = 0x02, /**< Handle Value Indication. */ + /** + * Handle Value Notification. + */ + BLE_HVX_NOTIFICATION = 0x01, + + /** + * Handle Value Indication. + */ + BLE_HVX_INDICATION = 0x02, }; +/** + * @} + * @} + */ + #ifdef __cplusplus } #endif -#endif // ifndef __BLE_COMMON_H__ +#endif // ifndef MBED_BLE_COMMON_H__ diff --git a/features/FEATURE_BLE/ble/deprecate.h b/features/FEATURE_BLE/ble/deprecate.h index f0b7d38cb87..e3b1edb7ee1 100644 --- a/features/FEATURE_BLE/ble/deprecate.h +++ b/features/FEATURE_BLE/ble/deprecate.h @@ -14,12 +14,15 @@ * limitations under the License. */ -#ifndef __DEPRECATE_H__ -#define __DEPRECATE_H__ +#ifndef MBED_BLE_DEPRECATE_H__ +#define MBED_BLE_DEPRECATE_H__ #ifdef YOTTA_CFG_MBED_OS #include "compiler-polyfill/attributes.h" #else + /** + * Deprecated, use MBED_DEPRECATED instead. + */ #define __deprecated_message(msg) #endif diff --git a/features/FEATURE_BLE/ble/pal/GapEvents.h b/features/FEATURE_BLE/ble/pal/GapEvents.h new file mode 100644 index 00000000000..34b7c7487a8 --- /dev/null +++ b/features/FEATURE_BLE/ble/pal/GapEvents.h @@ -0,0 +1,443 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_PAL_GAP_MESSAGE_H_ +#define BLE_PAL_GAP_MESSAGE_H_ + +#include "GapTypes.h" +#include "ble/ArrayView.h" + +namespace ble { +namespace pal { + +/** + * Enumeration of GAP event types + */ +struct GapEventType : SafeEnum { + enum type { + /** + * Event type used by GapUnexpectedErrorEvent + */ + UNEXPECTED_ERROR, + + /** + * Event type used by GapConnectionCompleteEvent + */ + CONNECTION_COMPLETE, + + /** + * Event type used by GapAdvertisingReportEvent + */ + ADVERTISING_REPORT, + + /** + * Event type used by GapConnectionUpdateEvent + * */ + CONNECTION_UPDATE, + + /** + * Event type used by GapRemoteConnectionParameterRequestEvent + */ + REMOTE_CONNECTION_PARAMETER_REQUEST, + + /** + * Event type used by GapDisconnectionCompleteEvent + */ + DISCONNECTION_COMPLETE + }; + + GapEventType(type event_type) : SafeEnum(event_type) { } +}; + + +/** + * Base class of a Gap Event. + * + * Client should use the field type to deduce the actual type of the event. + */ +struct GapEvent { + + const GapEventType type; + +protected: + GapEvent(GapEventType type) : type(type) { } + + // Disable copy construction and copy assignement operations. + GapEvent(const GapEvent&); + GapEvent& operator=(const GapEvent&); +}; + + +/** + * Model an unexpected error that happen during a gap procedure. + * + * This class is mainly used to notify user code of an unexpected error returned + * in an HCI command complete event. + */ +struct GapUnexpectedErrorEvent : public GapEvent { + GapUnexpectedErrorEvent(uint16_t opcode, uint8_t error_code) : + GapEvent(GapEventType::UNEXPECTED_ERROR), + opcode(opcode), error_code(error_code) { } + + /** + * Opcode composed of the OCF and OGF of the command which has returned an + * error. + */ + const uint16_t opcode; + + /** + * Error code + */ + const uint8_t error_code; +}; + + +/** + * Indicate to both ends (slave or master) the end of the connection process. + * + * This structure should be used for Connection Complete Events and Enhanced + * Connection Complete Event. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.1 LE Connection Complete Event + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.10 LE Enhanced Connection + */ +struct GapConnectionCompleteEvent : public GapEvent { + /** + * Construct a new GapConnectionCompleteEvent. + * + * @param status Status of the operation: 0x00 in case of success otherwise + * the error code associated with the failure. + * + * @param connection_handle handle of the connection created. This handle + * will be used to address the connection in any connection oriented + * operation. + * + * @param role Role of the LE subsystem in the connection. + * + * @param address_type Type of address used by the peer for this connection. + * + * @param address Address of the peer used to establish the connection. + * + * @param connection_interval Connection interval used on this connection. + * It shall be in a range [0x0006 : 0x0C80]. A unit is equal to 1.25ms. + * + * @param connection_latency Number of connection events the slave can + * drop. + * + * @param supervision_timeout Supervision timeout of the connection. It + * shall be in the range [0x000A : 0x0C80] where a unit represent 10ms. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.1 LE Connection Complete Event + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.10 LE Enhanced Connection + * Complete Event + */ + GapConnectionCompleteEvent( + uint8_t status, + connection_handle_t connection_handle, + connection_role_t role, + advertising_peer_address_type_t peer_address_type, + const address_t& peer_address, + uint16_t connection_interval, + uint16_t connection_latency, + uint16_t supervision_timeout + ) : + GapEvent(GapEventType::CONNECTION_COMPLETE), + status(status), + connection_handle(connection_handle), + role(role), + peer_address_type(peer_address_type), + peer_address(peer_address), + connection_interval(connection_interval), + connection_latency(connection_latency), + supervision_timeout(supervision_timeout) { + } + + /* + * @param status Indicate if the connection succesfully completed or not: + * - 0: Connection successfuly completed + * - [0x01 : 0xFF] Connection failed to complete, the value represent + * the code for the error. + */ + const uint8_t status; + + /** + * Handle of the connection created, valid if status is equal to 0. + * @important Valid if status is equal to 0. + */ + const connection_handle_t connection_handle; + + /** + * Role of the device in the connection + * @important Valid if status is equal to 0. + */ + const connection_role_t role; + + /** + * Peer address type. + */ + const advertising_peer_address_type_t peer_address_type; + + /** + * Peer address. + */ + const address_t peer_address; + + /** + * Connection interval used in this connection. + * It shall be in a range [0x0006 : 0x0C80]. A unit is equal to 1.25ms. + */ + const uint16_t connection_interval; + + /** + * Number of connection events the slave can drop. + */ + const uint16_t connection_latency; + + /** + * Supervision timeout of the connection + * It shall be in the range [0x000A : 0x0C80] where a unit represent 10ms. + */ + const uint16_t supervision_timeout; +}; + + +/** + * Report advertising from one or more LE device. + * + * @important This class has to be implemented by the BLE port. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.2 LE Advertising Report Event + */ +struct GapAdvertisingReportEvent : public GapEvent { + + /** + * POD representing an advertising captured by the LE subsystem. + */ + struct advertising_t { + received_advertising_type_t type; + connection_peer_address_type_t address_type; + const address_t& address; + ArrayView data; + int8_t rssi; + }; + + GapAdvertisingReportEvent() : GapEvent(GapEventType::ADVERTISING_REPORT) { } + + virtual ~GapAdvertisingReportEvent() { } + + /** + * Count of advertising in this event. + */ + virtual uint8_t size() const = 0; + + /** + * Access the advertising at index i. + */ + virtual advertising_t operator[](uint8_t i) const = 0; +}; + + +/** + * Indicates the connection update process completion. + * + * If no parameters are updated after a connection update request from the peer + * then this event shall not be emmited. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.3 LE Connection Update Complete + * Event. + */ +struct GapConnectionUpdateEvent : public GapEvent { + + /** + * Construct a connection update event for a successful process. + * + * @param status Status of the connection update event operation. If equal + * to 0x00 then the process was successful, otherwise the status indicates + * the reason of the faillure. + * + * @param connection_handle Handle of the connection updated. + * + * @param connection_interval New connection interval used by the connection. + * + * @param Connection_latency New connection latency used by the connection. + * + * @param supervision_timeout New connection supervision timeout. + */ + GapConnectionUpdateEvent( + uint8_t status, + connection_handle_t connection_handle, + uint16_t connection_interval, + uint16_t connection_latency, + uint16_t supervision_timeout + ) : + GapEvent(GapEventType::CONNECTION_UPDATE), + status(status), + connection_handle(connection_handle), + connection_interval(connection_interval), + connection_latency(connection_latency), + supervision_timeout(supervision_timeout) { + } + + /** + * If equal to 0, the connection update has succesfully completed otherwise + * the process has failled and this field represent the error associated to + * the faillure. + */ + const uint8_t status; + + /** + * Handle of the connection which has completed the connection update + * process. + */ + const connection_handle_t connection_handle; + + /** + * New connection interval used by the connection. + * It shall be in a range [0x0006 : 0x0C80]. A unit is equal to 1.25ms. + */ + const uint16_t connection_interval; + + /* + * New number of connection events the slave can drop. + */ + const uint16_t connection_latency; + + /* + * New supervision timeout of the connection. + * It shall be in the range [0x000A : 0x0C80] where a unit represent 10ms. + */ + const uint16_t supervision_timeout; +}; + + +/** + * indicate a request from the peer to change the connection parameters. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.65.6 LE Remote Connection Parameter + * Request Event. + */ +struct GapRemoteConnectionParameterRequestEvent : public GapEvent { + /** + * Construct a new remote connection parameter request event. + * + * @param connection_handle Handle of the connection with the peer + * requesting the parameter update + * + * @param min_connection_interval Minimum value of the connection interval + * requested by the peer. + * + * @param max_connection_interval Maximum value of the connection interval + * requested by the peer. + * + * @param connection_latency Slave latency requested by the peer. + * + * @param supervision_timeout Supervision timeout requested by the peer. + */ + GapRemoteConnectionParameterRequestEvent( + connection_handle_t connection_handle, + uint16_t min_connection_interval, + uint16_t max_connection_interval, + uint16_t connection_latency, + uint16_t supervision_timeout + ) : GapEvent(GapEventType::REMOTE_CONNECTION_PARAMETER_REQUEST), + connection_handle(connection_handle), + min_connection_interval(min_connection_interval), + max_connection_interval(max_connection_interval), + connection_latency(connection_latency), + supervision_timeout(supervision_timeout) { + } + + /** + * Handle of the connection with the peer requesting the parameter update. + */ + const connection_handle_t connection_handle; + + /** + * Minimum value of the connection interval requested by the peer. + * It shall be in a range [0x0006 : 0x0C80]. A unit is equal to 1.25ms. + */ + const uint16_t min_connection_interval; + + /** + * Maximum value of the connection interval requested by the peer. + * It shall be in a range [0x0006 : 0x0C80]. A unit is equal to 1.25ms. + */ + const uint16_t max_connection_interval; + + /* + * Slave latency requested by the peer. + */ + const uint16_t connection_latency; + + /* + * Supervision timeout requested by the peer. + * It shall be in the range [0x000A : 0x0C80] where a unit represent 10ms. + */ + const uint16_t supervision_timeout; +}; + + +/** + * Indicate the end of a disconnection process. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.7.5 Disconnection Complete Event. + */ +struct GapDisconnectionCompleteEvent : public GapEvent { + /** + * Construct a disconnection complete event. + * + * @param status Status of the procedure. If equal to 0 then the + * disconnection process complete successfully. Otherwise it represents the + * error code associated with the faillure. + * + * @param connection_handle Handle of the connection disconnected. + * + * @param reason Reason of the disconnection + */ + GapDisconnectionCompleteEvent( + uint8_t status, + connection_handle_t connection_handle, + uint8_t reason + ) : GapEvent(GapEventType::DISCONNECTION_COMPLETE), + status(status), + connection_handle(connection_handle), + reason(reason) { + } + + /** + * Status of the procedure. If equal to 0 then the procedure was a success + * otherwise this variable contains the error code associated with the + * faillure. + */ + const uint8_t status; + + /** + * Handle of the connection used for the procedure. + */ + const connection_handle_t connection_handle; + + /** + * Reason for disconnection. + * + * @important ignored in case of faillure. + */ + const uint8_t reason; +}; + +} // namespace pal +} // namespace ble + +#endif /* BLE_PAL_GAP_MESSAGE_H_ */ diff --git a/features/FEATURE_BLE/ble/pal/GapTypes.h b/features/FEATURE_BLE/ble/pal/GapTypes.h new file mode 100644 index 00000000000..405b7c1d1b1 --- /dev/null +++ b/features/FEATURE_BLE/ble/pal/GapTypes.h @@ -0,0 +1,610 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_PAL_GAP_TYPES_H_ +#define BLE_PAL_GAP_TYPES_H_ + +#include +#include "ble/BLETypes.h" +#include "ble/SafeEnum.h" + +namespace ble { +namespace pal { + +/** + * Type of advertising the LE subsystem can use when it advertise. + */ +struct advertising_type_t : SafeEnum { + enum type { + /** + * Connectable and scannable undirected advertising . + */ + ADV_IND = 0x00, + + /** + * Connectable high duty cycle directed advertising + */ + ADV_DIRECT_IND = 0x01, + + /** + * Scannable undirected advertising + */ + ADV_SCAN_IND = 0x02, + + /** + * Non connectable undirected advertising + */ + ADV_NONCONN_IND = 0x03, + + /** + * Connectable low duty cycle directed advertising + */ + ADV_DIRECT_IND_LOW_DUTY_CYCLE = 0x04 + }; + + /** + * Construct a new advertising_type_t value. + */ + advertising_type_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Type used to model the own address used during the following GAP operations: + * advertising, scanning and initiating + */ +struct own_address_type_t : SafeEnum { + enum type { + /** + * Use the public device address + */ + PUBLIC_ADDRESS = 0x00, + + /** + * Use the random device address + */ + RANDOM_ADDRESS = 0x01, + + /** + * Generated resolvable private address based on the local IRK from the + * resolving list. Use the public address if no entry match in the resolving + * list. + */ + RESOLVABLE_PRIVATE_ADDRESS_PUBLIC_FALLBACK = 0x02, + + /** + * Generated resolvable private address based on the local IRK from the + * resolving list. Use the random address if no entry match in the resolving + * list. + */ + RESOLVABLE_PRIVATE_ADDRESS_RANDOM_FALLBACK = 0x03, + }; + + /** + * Construct a new instance of own_address_type_t. + */ + own_address_type_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Type modeling the peer address type during direct advertising. + */ +struct advertising_peer_address_type_t : + SafeEnum { + enum type { + /** + * Public device address or identity address. + */ + PUBLIC_ADDRESS = 0x00, + + /** + * Random device address or random (static) identity address. + */ + RANDOM_ADDRESS = 0x01 + }; + + /** + * Construct a new instance of advertising_peer_address_type_t. + */ + advertising_peer_address_type_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Peer address type used during connection initiating. + */ +struct connection_peer_address_type_t : + SafeEnum { + enum type { + /** + * Public device address + */ + PUBLIC_ADDRESS = 0x00, + + /** + * Random device address + */ + RANDOM_ADDRESS = 0x01, + + /** + * Public identity address. + * @note remove once privacy mode is supported. + */ + PUBLIC_IDENTITY_ADDRESS = 0x02, + + /** + * Random (static) identity address. + * @note remove once privacy mode is supported. + */ + RANDOM_IDENTITY_ADDRESS = 0x03 + }; + + /** + * Construct a new connection_peer_address_type_t instance. + */ + connection_peer_address_type_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Address type used in whitelist operations + */ +struct whitelist_address_type_t : SafeEnum { + enum type { + PUBLIC_DEVICE_ADDRESS = 0x00, + RANDOM_DEVICE_ADDRESS = 0x01, + /* TODO: to be added with bluetooth 5 support: + ANONYMOUS_ADVERTISEMENT_DEVICE_ADRESS + */ + }; + + /** + * Construct a new whitelist_address_type_t instance. + */ + whitelist_address_type_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Channel map which can be used during advertising. + */ +struct advertising_channel_map_t : SafeEnum { + enum type { + ADVERTISING_CHANNEL_37 = (1 << 0), + ADVERTISING_CHANNEL_38 = (1 << 1), + ADVERTISING_CHANNEL_37_AND_38 = + ADVERTISING_CHANNEL_37 | ADVERTISING_CHANNEL_38, + ADVERTISING_CHANNEL_39 = (1 << 2), + ADVERTISING_CHANNEL_37_AND_39 = + ADVERTISING_CHANNEL_37 | ADVERTISING_CHANNEL_39, + ADVERTISING_CHANNEL_38_AND_39 = + ADVERTISING_CHANNEL_38 | ADVERTISING_CHANNEL_39, + ALL_ADVERTISING_CHANNELS = + ADVERTISING_CHANNEL_37 | ADVERTISING_CHANNEL_38 | ADVERTISING_CHANNEL_39 + }; + + /** + * Construct a new advertising_channel_map_t instance. + */ + advertising_channel_map_t(type value) : + SafeEnum(value) { } +}; + + +/** + * HCI Error codes. + */ +struct hci_error_code_t : SafeEnum { + enum type { + SUCCESS = 0x00, + UNKNOWN_HCI_COMMAND = 0x01, + UNKNOWN_CONNECTION_IDENTIFIER = 0x02, + HARDWARE_FAILLURE = 0x03, + PAGE_TIMEOUT = 0x04, + AUTHENTICATION_FAILLURE = 0x05, + PIN_OR_KEY_MISSING = 0x06, + MEMORY_CAPACITY_EXCEEDED = 0x07, + CONNECTION_TIMEOUT = 0x08, + CONNECTION_LIMIT_EXCEEDED = 0x09, + SYNCHRONOUS_CONNECTION_LIMIT_TO_A_DEVICE_EXCEEDED = 0x0A, + CONNECTION_ALREADY_EXIST = 0x0B, + COMMAND_DISALLOWED = 0x0C, + CONNECTION_REJECTED_DUE_TO_LIMITED_RESOURCES = 0x0D, + CONNECTION_REJECTED_DUE_TO_SECURITY_REASONS = 0x0E, + CONNECTION_REJECTED_DUE_TO_UNACCEPTABLE_BD_ADDR = 0x0F, + CONNECTION_ACCEPT_TIMEOUT_EXCEEDED = 0x10, + UNSUPPORTED_FEATURE_OR_PARAMETER_VALUE = 0x11, + INVALID_HCI_COMMAND_PARAMETERS = 0x12, + REMOTE_USER_TERMINATED_CONNECTION = 0x13, + REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES = 0x14, + REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_POWER_OFF = 0x15, + CONNECTION_TERMINATED_BY_LOCAL_HOST = 0x16, + REPEATED_ATTEMPTS = 0x17, + PAIRING_NOT_ALLOWED = 0x18, + UNKNOWN_LMP_PDU = 0x19, + UNSUPPORTED_REMOTE_FEATURE = 0x1A, + UNSUPPORTED_LMP_FEATURE = 0x1A, + SCO_OFFSET_REJECTED = 0x1B, + SCO_INTERVAL_REJECTED = 0x1C, + SCO_AIR_MODE_REJECTED = 0x1D, + INVALID_LMP_PARAMETERS = 0x1E, + INVALID_LL_PARAMETERS = 0x1E, + UNSPECIFIED_ERROR = 0x1F, + UNSUPPORTED_LMP_PARAMETER_VALUE = 0x20, + UNSUPPORTED_LL_PARAMETER_VALUE = 0x20, + ROLE_CHANGE_NOT_ALLOWED = 0x21, + LMP_RESPONSE_TIMEOUT = 0x22, + LL_RESPONSE_TIMEOUT = 0x22, + LMP_ERROR_TRANSACTION_COLLISION = 0x23, + LL_PROCEDURE_COLLISION = 0x23, + LMP_PDU_NOT_ALLOWED = 0x24, + ENCRYPTION_MODE_NOT_ACCEPTABLE = 0x25, + LINK_KEY_CANNOT_BE_CHANGED = 0x26, + REQUESTED_QOS_NOT_SUPPORTED = 0x27, + INSTANT_PASSED = 0x28, + PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED = 0x29, + DIFFERENT_TRANSACTION_COLLISION = 0x2A, + RESERVED_FOR_FUTURE_USE = 0x2B, + QOS_UNACCEPTABLE_PARAMETER = 0x2C, + QOS_REJECTED = 0x2D, + CHANNEL_CLASSIFICATION_NOT_SUPPORTED = 0x2E, + INSUFFICIENT_SECURITY = 0x2F, + PARAMETER_OUT_OF_MANDATORY_RANGE = 0x30, + //RESERVED_FOR_FUTURE_USE = 0x31, + ROLE_SWITCH_PENDING = 0x32, + //RESERVED_FOR_FUTURE_USE = 0x33, + RESERVED_SLOT_VIOLATION = 0x34, + ROLE_SWITCH_FAILED = 0x35, + EXTENDED_INQUIRY_RESPONSE_TOO_LARGE = 0x36, + SECURE_SIMPLE_PAIRING_NOT_SUPPORTED_BY_HOST = 0x37, + HOST_BUSY_PAIRING = 0x38, + CONNECTION_REJECTED_DUE_TO_NO_SUITABLE_CHANNEL_FOUND = 0x39, + CONTROLLER_BUSY = 0x3A, + UNACCEPTABLE_CONNECTION_PARAMETERS = 0x3B, + ADVERTISING_TIMEOUT = 0x3C, + CONNECTION_TERMINATED_DUE_TO_MIC_FAILURE = 0x3D, + CONNECTION_FAILED_TO_BE_ESTABLISHED = 0x3E, + MAC_CONNECTION_FAILED = 0x3F, + COARSE_CLOCK_ADJUSTMENT_REJECTED_BUT_WILL_TRY_TO_ADJUST_USING_CLOCK_DRAGGING = 0x40, + TYPE0_SUBMAP_NOT_DEFINED = 0x41, + UNKNOWN_ADVERTISING_IDENTIFIER = 0x42, + LIMIT_REACHED = 0x43, + OPERATION_CANCELLED_BY_HOST = 0x44 + }; + + /** + * Construct a new hci_error_code_t instance. + */ + hci_error_code_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Reasons which can be used to end a connection. + */ +struct disconnection_reason_t : SafeEnum { + enum type { + AUTHENTICATION_FAILLURE = 0x05, + REMOTE_USER_TERMINATED_CONNECTION = 0x13, + REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_LOW_RESOURCES = 0x14, + REMOTE_DEVICE_TERMINATED_CONNECTION_DUE_TO_POWER_OFF = 0x15, + UNSUPPORTED_REMOTE_FEATURE = 0x1A, + PAIRING_WITH_UNIT_KEY_NOT_SUPPORTED = 0x29, + UNACCEPTABLE_CONNECTION_PARAMETERS = 0x3B + }; + + /** + * Construct a new disconnection_reason_t instance. + */ + disconnection_reason_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Filter policy which can be used during advertising. + */ +struct advertising_filter_policy_t : + SafeEnum { + enum type { + /** + * Process connection and scan requests from all devices. The whitelist is + * not used. + */ + NO_FILTER = 0x00, + + /** + * Process connection requests from all devices but filter out scan requests + * of devices which are not in the whitelist. + */ + FILTER_SCAN_REQUESTS = 0x01, + + /** + * Process scan requests from all devices but filter out connection requests + * of devices which are not in the whitelist. + */ + FILTER_CONNECTION_REQUEST = 0x02, + + /** + * Filter out scan or connection requests of devices which are not in the + * whitelist. + */ + FILTER_SCAN_AND_CONNECTION_REQUESTS = 0x03 + }; + + /** + * Construct a new instance of advertising_filter_policy_t. + */ + advertising_filter_policy_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Filter policy which can be used during a scan. + */ +struct scanning_filter_policy_t : SafeEnum { + enum type { + /** + * Accept all advertising packets except directed advertising packet not + * addressed to this device. + */ + NO_FILTER = 0x00, + + /** + * Accept only advertising packets from devices in the whitelist except + * directed advertising packet not addressed to this device. + */ + FILTER_ADVERTISING = 0x01 + + // EXTENDED ADVERTISING FILTER POLICY (accept private resolvable direct advertising) + }; + + /** + * Construct a new instance of scanning_filter_policy_t. + */ + scanning_filter_policy_t(type value) : + SafeEnum(value) { } + +}; + + +/** + * Filter policy which can be used during connection initiation. + */ +struct initiator_policy_t : SafeEnum { + enum type { + /** + * The whitelist is not used to determine which advertiser to connect to. + */ + NO_FILTER, + + /** + * Whitelist is used to determine which advertiser to connect to. + */ + USE_WHITE_LIST + }; + + initiator_policy_t(type value) : + SafeEnum(value) { } +}; + + +/** + * MAC address data type. + */ +struct address_t { + /** + * Create an invalid mac address, equal to FF:FF:FF:FF:FF:FF + */ + address_t() { + memset(value, 0xFF, sizeof(value)); + } + + /** + * Initialize a mac address from an array of bytes. + * + * @param input_value value of the MAC address. + */ + address_t(const uint8_t (&input_value)[6]) { + memcpy(value, input_value, sizeof(value)); + } + + /** + * Initialize a mac address from a pointer to a buffer. + * + * @param input_value Buffer containing the mac address. It shall be at + * least 6 long. + * + * @param tag Tag used to select this constructor. The value does not matter. + */ + address_t(const uint8_t* input_value, bool tag) { + memcpy(value, input_value, sizeof(value)); + } + + /** + * Equal operator between two addresses. + */ + friend bool operator==(const address_t& lhs, const address_t& rhs) { + return memcmp(lhs.value, rhs.value, sizeof(lhs.value)) == 0; + } + + /** + * Non equal operator between two addresses. + */ + friend bool operator!=(const address_t& lhs, const address_t& rhs) { + return !(lhs == rhs); + } + + /** + * Subscript operator to access mac address content + */ + uint8_t operator[](uint8_t i) const { + return value[i]; + } + + /** + * Return the pointer to the buffer holding mac address. + */ + const uint8_t* data() const { + return value; + } + + /** + * Size in byte of a mac address. + */ + static uint8_t size() { + return sizeof(value); + } + +private: + uint8_t value[6]; +}; + + +/** + * Hold advertising data. + */ +struct advertising_data_t { + /** + * Construct advertising data from an array. + * + * @param input_value Reference to the array containing the advertising data + */ + advertising_data_t(const uint8_t (&input_value)[31]) { + memcpy(value, input_value, sizeof(value)); + } + + /** + * Construct advertising data from a pointer to a buffer. + * + * @param input_value Pointer to the buffer containing the advertising data. + * + * @param len Length of the buffer. + */ + advertising_data_t(const uint8_t* input_value, size_t len) { + const size_t actual_len = std::min(len, sizeof(value)); + memcpy(value, input_value, actual_len); + memset(value + actual_len, 0x00, sizeof(value) - actual_len); + } + + /** + * Equal operator between two advertising data. + */ + friend bool operator==( + const advertising_data_t& lhs, const advertising_data_t& rhs + ) { + return memcmp(lhs.value, rhs.value, sizeof(lhs.value)) == 0; + } + + /** + * Non equal operator between two advertising data. + */ + friend bool operator!=( + const advertising_data_t& lhs, const advertising_data_t& rhs + ) { + return !(lhs == rhs); + } + + /** + * Subscript operator used to access the content of the advertising data. + */ + uint8_t operator[](uint8_t i) const { + return value[i]; + } + + /** + * Return a pointer to the advertising data buffer. + */ + const uint8_t* data() const { + return value; + } + + /** + * Return (fixed) size of advertising data. + */ + static uint8_t size() { + return sizeof(value); + } + +private: + uint8_t value[31]; +}; + + +/** + * Type of advertising the LE subsystem can use when it advertise. + */ +struct received_advertising_type_t : + SafeEnum { + enum type { + /** + * Connectable and scannable undirected advertising . + */ + ADV_IND = 0x00, + + /** + * Connectable high duty cycle directed advertising + */ + ADV_DIRECT_IND = 0x01, + + /** + * Scannable undirected advertising + */ + ADV_SCAN_IND = 0x02, + + /** + * Non connectable undirected advertising + */ + ADV_NONCONN_IND = 0x03, + + /** + * Response to a scan request. + */ + SCAN_RESPONSE = 0x04 + }; + + /** + * Construct a new received_advertising_type_t value. + */ + received_advertising_type_t(type value) : + SafeEnum(value) { } +}; + + +/** + * Model connection role. Used in GapConnectionCompleteEvent. + */ +struct connection_role_t : SafeEnum { + enum type { + MASTER, + SLAVE + }; + + connection_role_t(type value) : SafeEnum(value) { } +}; + +} // namespace pal +} // namespace ble + +#endif /* BLE_PAL_GAP_TYPES_H_ */ diff --git a/features/FEATURE_BLE/ble/pal/GenericAccessService.h b/features/FEATURE_BLE/ble/pal/GenericAccessService.h new file mode 100644 index 00000000000..14c05e15337 --- /dev/null +++ b/features/FEATURE_BLE/ble/pal/GenericAccessService.h @@ -0,0 +1,162 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_PAL_GENERIC_ACCESS_SERVICE_H_ +#define BLE_PAL_GENERIC_ACCESS_SERVICE_H_ + +#include "GapTypes.h" +#include "ble/ArrayView.h" +#include "ble/blecommon.h" +#include "ble/GapAdvertisingData.h" +#include "ble/Gap.h" + +namespace ble { +namespace pal { + +/** + * Manage state of the GAP service exposed by the GATT server. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12 - GAP service and characteristics for GATT + * server. + */ +struct GenericAccessService { + + /** + * Empty, default, constructor + */ + GenericAccessService() { } + + /** + * Virtual destructor + */ + virtual ~GenericAccessService() { } + + /** + * Acquire the length of the device name. + * The length can range from 0 (no device name) to 248 octets + * + * @param length The length of the device name currently stored in the GAP + * service. + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.1 - Device Name Characteristic + */ + virtual ble_error_t get_device_name_length(uint8_t& length) = 0; + + /** + * Get the current device name. + * The result is stored in the array pass in input if the operation + * succeed. Prior to this call the length of the device name can be acquired + * with a call to get_device_name_length. + * + * @param The array which will host the device name + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.1 - Device Name Characteristic + */ + virtual ble_error_t get_device_name(ArrayView& array) = 0; + + /** + * Set the value of the device name characteristic exposed by the GAP GATT + * service. + * + * @param device_name The name of the device. If NULL the device name + * value has a length of 0. + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.1 - Device Name Characteristic + */ + virtual ble_error_t set_device_name(const uint8_t* device_name) = 0; + + /** + * Acquire the appearance stored in the appearance characteristic of the GAP + * GATT service. + * + * @param appearance: If the call succeed will contain the value of the + * appearance characteristic. + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.2 - Appearance Characteristic + */ + virtual ble_error_t get_appearance( + GapAdvertisingData::Appearance& appearance + ) = 0; + + /** + * Set the value of the appearance characteristic of the GAP GATT service. + * + * @param appearance: The appearance to set. + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.2 - Appearance Characteristic + */ + virtual ble_error_t set_appearance( + GapAdvertisingData::Appearance appearance + ) = 0; + + /** + * Acquire the peripheral prefered connection parameters stored in the GAP + * GATT service. + * + * @param parameters: If the call succeed will contain the value of + * the peripheral prefered connection parameters characteristic. + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.3 - Peripheral Preferred Connection + * Parameters Characteristic + */ + virtual ble_error_t get_peripheral_prefered_connection_parameters( + ::Gap::ConnectionParams_t& parameters + ) = 0; + + /** + * set the value of the peripheral prefered connection parameters stored in + * the GAP GATT service. + * + * @param parameters: If the peripheral prefered connection parameters + * to set. + * + * @return BLE_ERROR_NONE in case of success or the appropriate error code + * otherwise. + * + * @see Bluetooth 4.2 Vol 3 PartC: 12.3 - Peripheral Preferred Connection + * Parameters Characteristic + */ + virtual ble_error_t set_peripheral_prefered_connection_parameters( + const ::Gap::ConnectionParams_t& parameters + ) = 0; + +private: + GenericAccessService(const GenericAccessService&); + GenericAccessService& operator=(const GenericAccessService&); +}; + +} // namespace pal +} // namespace ble + +#endif /* BLE_PAL_GENERIC_ACCESS_SERVICE_H_ */ diff --git a/features/FEATURE_BLE/ble/pal/PalGap.h b/features/FEATURE_BLE/ble/pal/PalGap.h new file mode 100644 index 00000000000..288b0f9d082 --- /dev/null +++ b/features/FEATURE_BLE/ble/pal/PalGap.h @@ -0,0 +1,696 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_PAL_GAP_H_ +#define BLE_PAL_GAP_H_ + +#include "platform/Callback.h" +#include "GapTypes.h" +#include "GapEvents.h" + +namespace ble { +namespace pal { + +/** + * Adaptation interface for the GAP layer. + * + * Define the primitive necessary to realize GAP operations. the API and event + * follow closely the definition of the HCI commands and events used + * by that layer. + */ +struct Gap { + /** + * Initialisation of the instance. An implementation can use this function + * to initialise the subsystems needed to realize the operations of this + * interface. + * + * This function has to be called before any other operations. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + */ + virtual ble_error_t initialize() = 0; + + /** + * Termination of the instance. An implementation can use this function + * to release the subsystems initialised to realise the operations of + * this interface. + * + * After a call to this function, initialise should be called again to + * allow use of the interface. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + */ + virtual ble_error_t terminate() = 0; + + /** + * Return the public device address. + * + * @note The public device address is usually acquired at initialization and + * stored in the instance. + * + * @return the public device address. + */ + virtual address_t get_device_address() = 0; + + /** + * Return the current random address. + * + * @note The random address is usually acquired at initialization and stored + * in the instance. + * + * @return the random device address. + */ + virtual address_t get_random_address() = 0; + + /** + * Set the random address which will used be during scan, connection or + * advertising process if the own address type selected is random. + * + * Changing the address during scan, connection or advertising process is + * forbiden. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.4 LE set random address command. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + */ + virtual ble_error_t set_random_address(const address_t& address) = 0; + + /** + * Set the advertising parameters which will be used during the advertising + * process. + * + * @param advertising_interval_min: Minimum advertising interval which can + * be used during undirected and low duty cycle directed advertising. This + * parameter shall be less than or equal to advertising_interval_max. This + * parameter shall be in the range [0x20 : 0x4000] where each unit is equal + * to 0.625ms. + * This parameter is not used by directed high duty cycle advertising. + * + * @param advertising_interval_max: Maximum advertising interval which can + * be used during undirected and low duty cycle directed advertising. This + * parameter shall be more than or equal to advertising_interval_min. This + * parameter shall be in the range [0x20 : 0x4000] where each unit is equal + * to 0.625ms. + * This parameter is not used by directed high duty cycle advertising. + * + * @param advertising_type Packet type that is used during the + * advertising process. Direct advertising require valid peer addresses + * parameters and ignore the filter policy set. + * If the High duty cycle advertising is used then the advertising parameter + * intervals are ignored. + * + * @param own_address_type Own address type used during advertising. + * If own address type is equal to RESOLVABLE_PRIVATE_ADDRESS_PUBLIC_FALLBACK + * or RESOLVABLE_PRIVATE_ADDRESS_RANDOM_FALLBACK then the peer address + * parameters (type and address) will be used to find the local IRK. + * + * @param peer_address_type Address type of the peer. + * This parameter shall be valid if directed advertising is used ( + * ADV_DIRECT_IND or ADV_DIRECT_IND_LOW_DUTY_CYCLE). This parameter should + * be valid if the own address type is equal to 0x02 or 0x03. + * In other cases, this parameter is ignored. + * + * @param peer_address Public device address, Random device addres, Public + * identity address or Random static identity address of the device targeted + * by the advertising. + * This parameter shall be valid if directed advertising is used ( + * ADV_DIRECT_IND or ADV_DIRECT_IND_LOW_DUTY_CYCLE). This parameter should + * be valid if the own address type is equal to 0x02 or 0x03. + * In other cases, this parameter is ignored. + * + * @param advertising_channel_map Map of the channel used to send + * advertising data. + * + * @param advertising_filter_policy Filter policy applied during the + * advertising process. The subsystem should use the whitelist to apply the + * policy. This parameter is ignored if the advertising type is directed ( + * ADV_DIRECT_IND or ADV_DIRECT_IND_LOW_DUTY_CYCLE). + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.5 LE set advertising parameters + * command. + */ + virtual ble_error_t set_advertising_parameters( + uint16_t advertising_interval_min, + uint16_t advertising_interval_max, + advertising_type_t advertising_type, + own_address_type_t own_address_type, + advertising_peer_address_type_t peer_address_type, + const address_t& peer_address, + advertising_channel_map_t advertising_channel_map, + advertising_filter_policy_t advertising_filter_policy + ) = 0; + + /** + * Set the data sends in advertising packet. If the advertising is + * currently enabled, the data shall be used when a new advertising packet + * is issued. + * + * @param advertising_data_length Number of significant bytes in the + * advertising data. + * + * @param advertising_data The data sends in advertising packets. Non + * significant bytes shall be equal to 0. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.5 LE set advertising data + * command. + */ + virtual ble_error_t set_advertising_data( + uint8_t advertising_data_length, + const advertising_data_t& advertising_data + ) = 0; + + /** + * Set the data sends in scan response packets. If the advertising is + * currently enabled, the data shall be used when a new scan response is + * issued. + * + * @param scan_response_data_length Number of significant bytes in the + * scan response data. + * + * @param scan_response_data The data sends in scan response packets. Non + * significant bytes shall be equal to 0. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.8 LE set scan response data + * command. + */ + virtual ble_error_t set_scan_response_data( + uint8_t scan_response_data_length, + const advertising_data_t& scan_response_data + ) = 0; + + /** + * Start or stop advertising. + * + * The process use advertising and scan response data set with + * set_advertising_data and set_scan_response_data while the parameters used + * are the one set by set_advertising_parameters. + * + * The advertising shall continue until: + * - The advertising is manually disabled (advertising_enable(false)). + * - A connection is created. + * - Time out in case of high duty cycle directed advertising. + * + * If the random address has not been set and the advertising parameter + * own_address_type is set to 0x01 then the procedure shall fail. + * + * If the random address has not been set and the advertising parameter + * own_address_type is set to RESOLVABLE_PRIVATE_ADDRESS_RANDOM_FALLBACK and + * the peer address is not in the resolving list then the procedure shall + * fail. + * + * @param enable If true start the advertising process, if the process was + * already runing and own_address_type is equal to 0x02 or 0x03, the + * subsystem can change the random address. + * If false and the advertising is running then the process should be + * stoped. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.9 LE set advertising enable + * command. + * + * @note If the advertising type is ADV_DIRECT_IND and the connection is not + * created during the time allowed to the procedure then a + * ConnectionComplete event shall be emmited with its error code set to + * ADVERTISING_TIMEOUT. + * + * @note Successfull connection shall emit a ConnectionComplete event. It + * also means advertising is disabled. + */ + virtual ble_error_t advertising_enable(bool enable) = 0; + + /** + * Set the parameter of the scan process. + * + * This command shall not be effective when the scanning process is running. + * + * @param active_scanning If true the subsystem does active scanning and + * the bluetooth subsystem shall send scanning PDUs. It shall also listen + * to scan responses. If false no scanning PDUs are sent during the scan + * process. + * + * @param scan_interval The time interval between two subsequent LE scans in + * unit of 0.625ms. This parameter shall be in the range [0x0004 : 0x4000]. + * + * @param scan_window Duration of the LE scan. It shall be less than or + * equal to scan_interval value. This parameter shall be in the range + * [0x0004 : 0x4000] and is in unit of 0.625ms. + * + * @param own_address_type Own address type used in scan request packets. + * + * @param filter_policy Filter policy applied when scanning. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.10 LE set scan parameters + * command. + */ + virtual ble_error_t set_scan_parameters( + bool active_scanning, + uint16_t scan_interval, + uint16_t scan_window, + own_address_type_t own_address_type, + scanning_filter_policy_t filter_policy + ) = 0; + + /** + * Start/stop scanning process. + * + * Parameters of the scanning process shall be set before the scan launch + * by using the function set_scan_parameters. + * + * @parameter enable Start the scanning process if true and stop it if + * false. If the scan process is already started, enabling it again will + * only update the duplicate filtering; based on the new parameter. + * + * @parameter filter_duplicates Enable duplicate filtering if true, + * otherwise disable it. + * + * @important advertising data or scan response data is not considered + * significant when determining duplicate advertising reports. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.11 LE set scan enable command. + */ + virtual ble_error_t scan_enable( + bool enable, + bool filter_duplicates + ) = 0; + + /** + * Create a new le connection to a connectable advertiser. + * + * @param scan_interval Hint to the le subsystem indicating how + * frequently it should scan for the peer address. It represent the time + * interval between two subsequent scan for the peer. It shall be in the + * range [0x0004 : 0x4000] and the time is in unit of 0.625ms. + * + * @param scan_window Hint to the le subsystem indicating for how long it + * should scan during a scan interval. The value shall be smaller or equal + * to scan_interval. If it is equal to scan_interval then scanning should + * run continuously. It shall be in the range [0x0004 : 0x4000] and the time + * is in unit of 0.625ms. + * + * @param initiator_policy Used to determine if the whitelist is used to + * determine the address to connect to. If the whitelist is not used, the + * connection shall be made against an advertiser matching the peer_address + * and the peer_address_type parameters. Otherwise those parameters are + * ignored. + * + * @param peer_address_type Type of address used by the advertiser. Not used + * if initiator_policy use the whitelist. + * + * @param Address used by the advertiser in its advertising packets. Not + * used if initiator_policy use the whitelist. + * + * @param own_address_type Type of address used in the connection request + * packet. + * + * @param connection_interval_min Minimum interval between two connection + * events allowed for the connection. It shall be less than or equal to + * connection_interval_max. This value shall be in range [0x0006 : 0x0C80] + * and is in unit of 1.25ms. + * + * @param connection_interval_max Maximum interval between two connection + * events allowed for the connection. It shall be greater than or equal to + * connection_interval_min. This value shall be in range [0x0006 : 0x0C80] + * and is in unit of 1.25ms. + * + * @param connection_latency Number of connection events the slave can drop + * if it has nothing to communicate to the master. This value shall be in + * the range [0x0000 : 0x01F3]. + * + * @param supervision_timeout Link supervision timeout for the connection. + * It shall be larger than: + * (1 + connection_latency) * connection_interval_max * 2 + * Note: connection_interval_max is in ms in this formulae. + * Everytime the master or the slave receive a valid packet from the peer, + * the supervision timer is reset. If the supervision timer reaches + * supervision_timeout then the connection is considered lost and a + * disconnect event shall be emmited. + * This value shall be in the range [0x000A : 0x0C80] and is in unit of 10 + * ms. + * + * @param minimum_connection_event_length Informative parameter of the + * minimum length a connection event. It shall be less than or equal to + * maximum_connection_event_length. It shall be in the range + * [0x0000 : 0xFFFF]. It should also be less than the expected connection + * interval. The unit is 0.625ms. + * + * @param maximum_connection_event_length Informative parameter of the + * maximum length a connection event. It shall be more than or equal to + * minimum_connection_event_length. It shall be in the range + * [0x0000 : 0xFFFF]. It should also be less than the expected connection + * interval. The unit is 0.625ms. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.12 LE create connection command. + */ + virtual ble_error_t create_connection( + uint16_t scan_interval, + uint16_t scan_window, + initiator_policy_t initiator_policy, + connection_peer_address_type_t peer_address_type, + const address_t& peer_address, + own_address_type_t own_address_type, + uint16_t connection_interval_min, + uint16_t connection_interval_max, + uint16_t connection_latency, + uint16_t supervision_timeout, + uint16_t minimum_connection_event_length, + uint16_t maximum_connection_event_length + ) = 0; + + /** + * Cancel the ongoing connection creation process. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.13 LE create connection cancel + * command. + */ + virtual ble_error_t cancel_connection_creation() = 0; + + /** + * Return the number of total whitelist entries that can be stored in the + * le subsystem. + * + * @note The value returned can change over time. + * + * @return The number of entries that can be stored in the LE subsystem. It + * range from 0x01 to 0xFF. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.14 LE read white list size + * command. + */ + virtual uint8_t read_white_list_capacity() = 0; + + /** + * Clear the whitelist stored in the LE subsystem. + * + * @important This command shall not be issued if the whitelist is being + * used by the advertising, scanning or connection creation procedure. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.15 LE clear white list command. + */ + virtual ble_error_t clear_whitelist() = 0; + + /** + * Add a device to the LE subsystem Whitelist. + * + * @param address_type address_type Type of the address to add in the + * whitelist. + * + * @param address Address of the device. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @important This command shall not be issued if the whitelist is being + * used by the advertising, scanning or connection creation procedure. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.16 LE add device to white list + * command. + */ + virtual ble_error_t add_device_to_whitelist( + whitelist_address_type_t address_type, + address_t address + ) = 0; + + /** + * Remove a device from the LE subsystem Whitelist. + * + * @param address_type address_type Type of the address of the device to + * remove from the whitelist. + * + * @param address Address of the device to remove from the whitelist + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @important This command shall not be issued if the whitelist is being + * used by the advertising, scanning or connection creation procedure. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.17 LE remove device from white + * list command. + */ + virtual ble_error_t remove_device_from_whitelist( + whitelist_address_type_t address_type, + address_t address + ) = 0; + + /** + * Start a connection update procedure. + * + * This procedure change the parameter used for a connection it can be + * master or slave initiated. + * + * The peer will received a connection parameters request and will either + * accept or reject the new parameters for the connection. + * + * Once the peer response has been received, the procedure ends and a + * Connection update complete event is emmited. + * + * @param connection Handle of the connection. + * + * @param connection_interval_min Minimum interval between two connection + * events allowed for the connection. It shall be less than or equal to + * connection_interval_max. This value shall be in range [0x0006 : 0x0C80] + * and is in unit of 1.25ms. + * + * @param connection_interval_max Maximum interval between two connection + * events allowed for the connection. It shall be greater than or equal to + * connection_interval_min. This value shall be in range [0x0006 : 0x0C80] + * and is in unit of 1.25ms. + * + * @param connection_latency Number of connection events the slave can drop + * if it has nothing to communicate to the master. This value shall be in + * the range [0x0000 : 0x01F3]. + * + * @param supervision_timeout Link supervision timeout for the connection. + * It shall be larger than: + * (1 + connection_latency) * connection_interval_max * 2 + * Note: connection_interval_max is in ms in this formulae. + * Everytime the master or the slave receive a valid packet from the peer, + * the supervision timer is reset. If the supervision timer reaches + * supervision_timeout then the connection is considered lost and a + * disconnect event shall be emmited. + * This value shall be in the range [0x000A : 0x0C80] and is in unit of 10 + * ms. + * + * @param minimum_connection_event_length Informative parameter of the + * minimum length a connection event. It shall be less than or equal to + * maximum_connection_event_length. It shall be in the range + * [0x0000 : 0xFFFF]. It should also be less than the expected connection + * interval. The unit is 0.625ms. + * + * @param maximum_connection_event_length Informative parameter of the + * maximum length a connection event. It shall be more than or equal to + * minimum_connection_event_length. It shall be in the range + * [0x0000 : 0xFFFF]. It should also be less than the expected connection + * interval. The unit is 0.625ms. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.18 LE Connection update command. + * + */ + virtual ble_error_t connection_parameters_update( + connection_handle_t connection, + uint16_t connection_interval_min, + uint16_t connection_interval_max, + uint16_t connection_latency, + uint16_t supervision_timeout, + uint16_t minimum_connection_event_length, + uint16_t maximum_connection_event_length + ) = 0; + + /** + * Accept connection parameter request. + * + * This command sends a positive response to a connection parameter request + * from a peer. + * + * @param connection Handle of the connection. + * + * @param connection_interval_min Minimum interval between two connection + * events allowed for the connection. It shall be less than or equal to + * connection_interval_max. This value shall be in range [0x0006 : 0x0C80] + * and is in unit of 1.25ms. + * + * @param connection_interval_max Maximum interval between two connection + * events allowed for the connection. It shall be greater than or equal to + * connection_interval_min. This value shall be in range [0x0006 : 0x0C80] + * and is in unit of 1.25ms. + * + * @param connection_latency Number of connection events the slave can drop + * if it has nothing to communicate to the master. This value shall be in + * the range [0x0000 : 0x01F3]. + * + * @param supervision_timeout Link supervision timeout for the connection. + * It shall be larger than: + * (1 + connection_latency) * connection_interval_max * 2 + * Note: connection_interval_max is in ms in this formulae. + * Everytime the master or the slave receive a valid packet from the peer, + * the supervision timer is reset. If the supervision timer reaches + * supervision_timeout then the connection is considered lost and a + * disconnect event shall be emmited. + * This value shall be in the range [0x000A : 0x0C80] and is in unit of 10 + * ms. + * + * @param minimum_connection_event_length Informative parameter of the + * minimum length a connection event. It shall be less than or equal to + * maximum_connection_event_length. It shall be in the range + * [0x0000 : 0xFFFF]. It should also be less than the expected connection + * interval. The unit is 0.625ms. + * + * @param maximum_connection_event_length Informative parameter of the + * maximum length a connection event. It shall be more than or equal to + * minimum_connection_event_length. It shall be in the range + * [0x0000 : 0xFFFF]. It should also be less than the expected connection + * interval. The unit is 0.625ms. + * + * @note Usually parameters of this function match the connection parameters + * received in the connection parameter request event. + * + * @important: Once the new connection parameters are in used a Connection + * Update Complete event shall be emmited. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.31 LE remote connection parameter + * request reply command. + */ + virtual ble_error_t accept_connection_parameter_request( + connection_handle_t connection_handle, + uint16_t interval_min, + uint16_t interval_max, + uint16_t latency, + uint16_t supervision_timeout, + uint16_t minimum_connection_event_length, + uint16_t maximum_connection_event_length + ) = 0; + + /** + * Reject a connection parameter update request. + * + * @param connection_handle handle to the peer which has issued the + * connection parameter request. + * + * @param rejection_reason Indicate to the peer why the proposed connection + * parameters were rejected. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.8.32 LE Remote Connection Parameter + * Request Negative Reply Command. + */ + virtual ble_error_t reject_connection_parameter_request( + connection_handle_t connection_handle, + hci_error_code_t rejection_reason + ) = 0; + + /** + * Start a disconnection procedure. + * + * Once the procedure is complete it should emit a disconnection complete + * event. + * + * @param connection Handle of the connection to terminate. + * + * @param disconnection_reason Indicates the reason for ending the + * connection. + * + * @return BLE_ERROR_NONE if the request has been successfully sent or the + * appropriate error otherwise. + * + * @note: See Bluetooth 5 Vol 2 PartE: 7.1.6 disconenct command. + */ + virtual ble_error_t disconnect( + connection_handle_t connection, + disconnection_reason_t disconnection_reason + ) = 0; + + /** + * Register a callback which will handle Gap events. + * + * @param cb The callback object which will handle Gap events from the + * LE subsystem. + * It accept a single parameter in input: The event received. + */ + void when_gap_event_received(mbed::Callback cb) + { + _gap_event_cb = cb; + } + +protected: + Gap() { } + + virtual ~Gap() { } + + /** + * Implementation shall call this function whenever the LE subsystem + * generate a Gap event. + * + * @param gap_event The event to emit to higher layer. + */ + void emit_gap_event(const GapEvent& gap_event) + { + if (_gap_event_cb) { + _gap_event_cb(gap_event); + } + } + +private: + /** + * Callback called when an event is emitted by the LE subsystem. + */ + mbed::Callback _gap_event_cb; + + // Disallow copy construction and copy assignment. + Gap(const Gap&); + Gap& operator=(const Gap&); +}; + +} // namespace pal +} // namespace ble + +#endif /* BLE_PAL_GAP_H_ */ diff --git a/features/FEATURE_BLE/ble/services/BatteryService.h b/features/FEATURE_BLE/ble/services/BatteryService.h index 5aa419a4690..e6025af5152 100644 --- a/features/FEATURE_BLE/ble/services/BatteryService.h +++ b/features/FEATURE_BLE/ble/services/BatteryService.h @@ -14,64 +14,119 @@ * limitations under the License. */ -#ifndef __BLE_BATTERY_SERVICE_H__ -#define __BLE_BATTERY_SERVICE_H__ +#ifndef MBED_BLE_BATTERY_SERVICE_H__ +#define MBED_BLE_BATTERY_SERVICE_H__ +#include "platform/mbed_assert.h" #include "ble/BLE.h" /** -* @class BatteryService -* @brief BLE Battery Service. This service displays the battery level from 0% to 100%, represented as an 8bit number. -* Service: https://developer.bluetooth.org/gatt/services/Pages/ServiceViewer.aspx?u=org.bluetooth.service.battery_service.xml -* Battery Level Char: https://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.battery_level.xml -*/ + * BLE Battery service. + * + * @par purpose + * + * The battery service exposes the charge level of the battery of the device. + * This information is exposed as a percentage from 0% to 100%; a value of 0% + * represents a fully discharged battery, and a value of 100% represents a + * fully charged battery. + * + * Clients can read the current charge level and subscribe to server initiated + * updates of the charge level. The server delivers these updates to the subscribed + * client in a notification packet. + * + * The subscription mechanism is useful to save power; it avoids unecessary data + * traffic between the client and the server, which may be induced by polling the + * battery level characteristic value. + * + * @par usage + * + * When this class is instantiated, it adds a battery service in the GattServer. + * + * The application code can use the function updateBatteryLevel() to update the + * charge level that the service exposes and to notify the subscribed client that the + * value changed. + * + * @note You can find specification of the battery service here: + * https://www.bluetooth.com/specifications/gatt + * + * @important Multiple instances of this battery service are not supported. + */ class BatteryService { public: /** - * @param[in] _ble - * BLE object for the underlying controller. - * @param[in] level - * 8bit batterly level. Usually used to represent percentage of batterly charge remaining. + * Instantiate a battery service. + * + * The construction of a BatteryService adds a GATT battery service in @p + * _ble GattServer and sets the initial charge level of the battery to @p + * level. + * + * @param[in] _ble BLE device which will host the battery service. + * @param[in] level Initial charge level of the battery. It is a percentage + * where 0% means that the battery is fully discharged and 100% means that + * the battery is fully charged. */ BatteryService(BLE &_ble, uint8_t level = 100) : ble(_ble), batteryLevel(level), - batteryLevelCharacteristic(GattCharacteristic::UUID_BATTERY_LEVEL_CHAR, &batteryLevel, GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) { - - GattCharacteristic *charTable[] = {&batteryLevelCharacteristic}; - GattService batteryService(GattService::UUID_BATTERY_SERVICE, charTable, sizeof(charTable) / sizeof(GattCharacteristic *)); + batteryLevelCharacteristic( + GattCharacteristic::UUID_BATTERY_LEVEL_CHAR, + &batteryLevel, + GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY + ) + { + MBED_ASSERT(level <= 100); + GattCharacteristic *charTable[] = { &batteryLevelCharacteristic }; + GattService batteryService( + GattService::UUID_BATTERY_SERVICE, + charTable, + sizeof(charTable) / sizeof(GattCharacteristic *) + ); ble.addService(batteryService); } /** - * @brief Update the battery level with a new value. Valid values lie between 0 and 100, - * anything outside this range will be ignored. + * Update the battery charge level that the service exposes. * - * @param newLevel - * Update to battery level. + * The server sends a notification of the new value to clients that have + * subscribed to the battery level characteristic updates, and clients + * reading the charge level after the update obtain the updated value. + * + * @param newLevel Charge level of the battery. It is a percentage of the + * remaining charge between 0% and 100%. + * + * @important This function must be called in the execution context of the + * BLE stack. */ - void updateBatteryLevel(uint8_t newLevel) { + void updateBatteryLevel(uint8_t newLevel) + { + MBED_ASSERT(newLevel <= 100); batteryLevel = newLevel; - ble.gattServer().write(batteryLevelCharacteristic.getValueHandle(), &batteryLevel, 1); + ble.gattServer().write( + batteryLevelCharacteristic.getValueHandle(), + &batteryLevel, + 1 + ); } protected: /** - * A reference to the underlying BLE instance that this object is attached to. - * The services and characteristics will be registered in this BLE instance. + * Reference to the underlying BLE instance that this object is attached to. + * + * The services and characteristics are registered in the GattServer of + * this BLE instance. */ BLE &ble; /** * The current battery level represented as an integer from 0% to 100%. */ - uint8_t batteryLevel; + uint8_t batteryLevel; + /** - * A ReadOnlyGattCharacteristic that allows access to the peer device to the - * batteryLevel value through BLE. + * The GATT characteristic, which exposes the charge level. */ ReadOnlyGattCharacteristic batteryLevelCharacteristic; }; -#endif /* #ifndef __BLE_BATTERY_SERVICE_H__*/ +#endif /* #ifndef MBED_BLE_BATTERY_SERVICE_H__*/ diff --git a/features/FEATURE_BLE/ble/services/HeartRateService.h b/features/FEATURE_BLE/ble/services/HeartRateService.h index 6b802bb83f0..7f5f240ff41 100644 --- a/features/FEATURE_BLE/ble/services/HeartRateService.h +++ b/features/FEATURE_BLE/ble/services/HeartRateService.h @@ -14,181 +14,218 @@ * limitations under the License. */ -#ifndef __BLE_HEART_RATE_SERVICE_H__ -#define __BLE_HEART_RATE_SERVICE_H__ +#ifndef MBED_BLE_HEART_RATE_SERVICE_H__ +#define MBED_BLE_HEART_RATE_SERVICE_H__ #include "ble/BLE.h" /** -* @class HeartRateService -* @brief BLE Service for HeartRate. This BLE Service contains the location of the sensor and the heart rate in beats per minute. -* Service: https://developer.bluetooth.org/gatt/services/Pages/ServiceViewer.aspx?u=org.bluetooth.service.heart_rate.xml -* HRM Char: https://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.heart_rate_measurement.xml -* Location: https://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.body_sensor_location.xml -*/ + * BLE Heart Rate Service. + * + * @purpose + * + * Fitness applications use the heart rate service to expose the heart + * beat per minute measured by a heart rate sensor. + * + * Clients can read the intended location of the sensor and the last heart rate + * value measured. Additionally, clients can subscribe to server initiated + * updates of the heart rate value measured by the sensor. The service delivers + * these updates to the subscribed client in a notification packet. + * + * The subscription mechanism is useful to save power; it avoids unecessary data + * traffic between the client and the server, which may be induced by polling the + * value of the heart rate measurement characteristic. + * + * @par usage + * + * When this class is instantiated, it adds a heart rate service in the GattServer. + * The service contains the location of the sensor and the initial value measured + * by the sensor. + * + * Application code can invoke updateHeartRate() when a new heart rate measurement + * is acquired; this function updates the value of the heart rate measurement + * characteristic and notifies the new value to subscribed clients. + * + * @note You can find specification of the heart rate service here: + * https://www.bluetooth.com/specifications/gatt + * + * @important The service does not expose information related to the sensor + * contact, the accumulated energy expanded or the interbeat intervals. + * + * @important The heart rate profile limits the number of instantiations of the + * heart rate services to one. + */ class HeartRateService { public: /** - * @enum SensorLocation - * @brief Location of the heart rate sensor on body. - */ - enum { - LOCATION_OTHER = 0, /*!< Other location. */ - LOCATION_CHEST, /*!< Chest. */ - LOCATION_WRIST, /*!< Wrist. */ - LOCATION_FINGER, /*!< Finger. */ - LOCATION_HAND, /*!< Hand. */ - LOCATION_EAR_LOBE, /*!< Earlobe. */ - LOCATION_FOOT, /*!< Foot. */ + * Intended location of the heart rate sensor. + */ + enum BodySensorLocation { + /** + * Other location. + */ + LOCATION_OTHER = 0, + + /** + * Chest. + */ + LOCATION_CHEST = 1, + + /** + * Wrist. + */ + LOCATION_WRIST = 2, + + /** + * Finger. + */ + LOCATION_FINGER, + + /** + * Hand. + */ + LOCATION_HAND, + + /** + * Earlobe. + */ + LOCATION_EAR_LOBE, + + /** + * Foot. + */ + LOCATION_FOOT, }; public: /** - * @brief Constructor with 8-bit HRM Counter value. + * Construct and initialize a heart rate service. * - * @param[ref] _ble - * Reference to the underlying BLE. - * @param[in] hrmCounter (8-bit) - * Initial value for the HRM counter. - * @param[in] location - * Sensor's location. - */ - HeartRateService(BLE &_ble, uint8_t hrmCounter, uint8_t location) : - ble(_ble), - valueBytes(hrmCounter), - hrmRate(GattCharacteristic::UUID_HEART_RATE_MEASUREMENT_CHAR, valueBytes.getPointer(), - valueBytes.getNumValueBytes(), HeartRateValueBytes::MAX_VALUE_BYTES, - GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY), - hrmLocation(GattCharacteristic::UUID_BODY_SENSOR_LOCATION_CHAR, &location), - controlPoint(GattCharacteristic::UUID_HEART_RATE_CONTROL_POINT_CHAR, &controlPointValue) { - setupService(); - } - - /** - * @brief Constructor with a 16-bit HRM Counter value. + * The construction process adds a GATT heart rate service in @p _ble + * GattServer, sets the value of the heart rate measurement characteristic + * to @p hrmCounter and the value of the body sensor location characteristic + * to @p location. * - * @param[in] _ble - * Reference to the underlying BLE. - * @param[in] hrmCounter (8-bit) - * Initial value for the HRM counter. - * @param[in] location - * Sensor's location. + * @param[in] _ble BLE device that hosts the heart rate service. + * @param[in] hrmCounter Heart beats per minute measured by the heart rate + * sensor. + * @param[in] location Intended location of the heart rate sensor. */ - HeartRateService(BLE &_ble, uint16_t hrmCounter, uint8_t location) : + HeartRateService(BLE &_ble, uint16_t hrmCounter, BodySensorLocation location) : ble(_ble), valueBytes(hrmCounter), - hrmRate(GattCharacteristic::UUID_HEART_RATE_MEASUREMENT_CHAR, valueBytes.getPointer(), - valueBytes.getNumValueBytes(), HeartRateValueBytes::MAX_VALUE_BYTES, - GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY), - hrmLocation(GattCharacteristic::UUID_BODY_SENSOR_LOCATION_CHAR, &location), - controlPoint(GattCharacteristic::UUID_HEART_RATE_CONTROL_POINT_CHAR, &controlPointValue) { + hrmRate( + GattCharacteristic::UUID_HEART_RATE_MEASUREMENT_CHAR, + valueBytes.getPointer(), + valueBytes.getNumValueBytes(), + HeartRateValueBytes::MAX_VALUE_BYTES, + GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY + ), + hrmLocation( + GattCharacteristic::UUID_BODY_SENSOR_LOCATION_CHAR, + reinterpret_cast(&location) + ) + { setupService(); } /** - * @brief Set a new 8-bit value for the heart rate. + * Update the heart rate that the service exposes. * - * @param[in] hrmCounter - * Heart rate in BPM. - */ - void updateHeartRate(uint8_t hrmCounter) { - valueBytes.updateHeartRate(hrmCounter); - ble.gattServer().write(hrmRate.getValueHandle(), valueBytes.getPointer(), valueBytes.getNumValueBytes()); - } - - /** - * Set a new 16-bit value for the heart rate. + * The server sends a notification of the new value to clients that have + * subscribed to updates of the heart rate measurement characteristic; clients + * reading the heart rate measurement characteristic after the update obtain + * the updated value. + * + * @param[in] hrmCounter Heart rate measured in BPM. * - * @param[in] hrmCounter - * Heart rate in BPM. + * @important This function must be called in the execution context of the + * BLE stack. */ void updateHeartRate(uint16_t hrmCounter) { valueBytes.updateHeartRate(hrmCounter); - ble.gattServer().write(hrmRate.getValueHandle(), valueBytes.getPointer(), valueBytes.getNumValueBytes()); + ble.gattServer().write( + hrmRate.getValueHandle(), + valueBytes.getPointer(), + valueBytes.getNumValueBytes() + ); } +protected: /** - * This callback allows the heart rate service to receive updates to the - * controlPoint characteristic. - * - * @param[in] params - * Information about the characteristic being updated. + * Construct and add to the GattServer the heart rate service. */ - virtual void onDataWritten(const GattWriteCallbackParams *params) { - if (params->handle == controlPoint.getValueAttribute().getHandle()) { - /* Do something here if the new value is 1; else you can override this method by - * extending this class. - * @NOTE: If you are extending this class, be sure to also call - * ble.onDataWritten(this, &ExtendedHRService::onDataWritten); in - * your constructor. - */ - } - } - -protected: void setupService(void) { - GattCharacteristic *charTable[] = {&hrmRate, &hrmLocation, &controlPoint}; - GattService hrmService(GattService::UUID_HEART_RATE_SERVICE, charTable, sizeof(charTable) / sizeof(GattCharacteristic *)); - - ble.addService(hrmService); - ble.onDataWritten(this, &HeartRateService::onDataWritten); + GattCharacteristic *charTable[] = { + &hrmRate, + &hrmLocation + }; + GattService hrmService( + GattService::UUID_HEART_RATE_SERVICE, + charTable, + sizeof(charTable) / sizeof(GattCharacteristic*) + ); + + ble.gattServer().addService(hrmService); } protected: - /* Private internal representation for the bytes used to work with the value of the heart rate characteristic. */ + /* + * Heart rate measurement value. + */ struct HeartRateValueBytes { - static const unsigned MAX_VALUE_BYTES = 3; /* Flags, and up to two bytes for heart rate. */ + /* 1 byte for the Flags, and up to two bytes for heart rate value. */ + static const unsigned MAX_VALUE_BYTES = 3; static const unsigned FLAGS_BYTE_INDEX = 0; static const unsigned VALUE_FORMAT_BITNUM = 0; - static const uint8_t VALUE_FORMAT_FLAG = (1 << VALUE_FORMAT_BITNUM); - - HeartRateValueBytes(uint8_t hrmCounter) : valueBytes() { - updateHeartRate(hrmCounter); - } + static const uint8_t VALUE_FORMAT_FLAG = (1 << VALUE_FORMAT_BITNUM); - HeartRateValueBytes(uint16_t hrmCounter) : valueBytes() { + HeartRateValueBytes(uint16_t hrmCounter) : valueBytes() + { updateHeartRate(hrmCounter); } - void updateHeartRate(uint8_t hrmCounter) { - valueBytes[FLAGS_BYTE_INDEX] &= ~VALUE_FORMAT_FLAG; - valueBytes[FLAGS_BYTE_INDEX + 1] = hrmCounter; - } - - void updateHeartRate(uint16_t hrmCounter) { - valueBytes[FLAGS_BYTE_INDEX] |= VALUE_FORMAT_FLAG; - valueBytes[FLAGS_BYTE_INDEX + 1] = (uint8_t)(hrmCounter & 0xFF); - valueBytes[FLAGS_BYTE_INDEX + 2] = (uint8_t)(hrmCounter >> 8); + void updateHeartRate(uint16_t hrmCounter) + { + if (hrmCounter <= 255) { + valueBytes[FLAGS_BYTE_INDEX] &= ~VALUE_FORMAT_FLAG; + valueBytes[FLAGS_BYTE_INDEX + 1] = hrmCounter; + } else { + valueBytes[FLAGS_BYTE_INDEX] |= VALUE_FORMAT_FLAG; + valueBytes[FLAGS_BYTE_INDEX + 1] = (uint8_t)(hrmCounter & 0xFF); + valueBytes[FLAGS_BYTE_INDEX + 2] = (uint8_t)(hrmCounter >> 8); + } } - uint8_t *getPointer(void) { + uint8_t *getPointer(void) + { return valueBytes; } - const uint8_t *getPointer(void) const { + const uint8_t *getPointer(void) const + { return valueBytes; } - unsigned getNumValueBytes(void) const { - return 1 + ((valueBytes[FLAGS_BYTE_INDEX] & VALUE_FORMAT_FLAG) ? sizeof(uint16_t) : sizeof(uint8_t)); + unsigned getNumValueBytes(void) const + { + if (valueBytes[FLAGS_BYTE_INDEX] & VALUE_FORMAT_FLAG) { + return 1 + sizeof(uint16_t); + } else { + return 1 + sizeof(uint8_t); + } } private: - /* First byte: 8-bit values, no extra info. Second byte: uint8_t HRM value */ - /* See https://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.heart_rate_measurement.xml */ uint8_t valueBytes[MAX_VALUE_BYTES]; }; protected: - BLE &ble; - - HeartRateValueBytes valueBytes; - uint8_t controlPointValue; - - GattCharacteristic hrmRate; - ReadOnlyGattCharacteristic hrmLocation; - WriteOnlyGattCharacteristic controlPoint; + BLE &ble; + HeartRateValueBytes valueBytes; + GattCharacteristic hrmRate; + ReadOnlyGattCharacteristic hrmLocation; }; -#endif /* #ifndef __BLE_HEART_RATE_SERVICE_H__*/ +#endif /* #ifndef MBED_BLE_HEART_RATE_SERVICE_H__*/ diff --git a/features/FEATURE_BLE/ble/services/iBeacon.h b/features/FEATURE_BLE/ble/services/iBeacon.h index 0bdaf4dc657..bc520d3a0ae 100644 --- a/features/FEATURE_BLE/ble/services/iBeacon.h +++ b/features/FEATURE_BLE/ble/services/iBeacon.h @@ -13,63 +13,230 @@ * See the License for the specific language governing permissions and * limitations under the License. */ -#ifndef __BLE_IBEACON_H__ -#define __BLE_IBEACON_H__ +#ifndef MBED_BLE_IBEACON_H__ +#define MBED_BLE_IBEACON_H__ #include "cmsis_compiler.h" #include "ble/BLE.h" /** -* @class iBeacon -* @brief iBeacon Service. This sets up a device to broadcast advertising packets to mimic an iBeacon. -*/ + * iBeacon Service. + * + * @par Purpose + * + * iBeacons are Bluetooth Low Energy (BLE) devices advertising an identification + * number generally used to determine the location of devices or physical objects + * near a mobile phone user. + * + * iOS scans for iBeacon devices in a background task and notifies Apps + * subscribed to a specific region when the area is entered or left. Apps may + * use this information to display context-aware content to users. + * + * As an example, a museum can deploy an app that informs the user when one of + * its exhibitions is entered and then displays specific information about exposed + * pieces of art when the user is sufficiently close to them. + * + * @par Positioning + * + * Location information is hierarchically structured. A UUID specific to the + * application and its deployment is used to identify a region. That region + * usually identifies an organization. The region is divided into subregions + * identified by a major ID. The subregion contains related points of interest + * which a minor ID distinguishes. + * + * As an example, a city willing to improve tourist's experience can deploy a fleet + * of iBeacons in relevant touristic locations it operates. The UUID may + * identify a place managed by the city. The major ID would identify the place; + * it can be a museum, a historic monument, a metro station and so on. The minor ID + * would locate a specific spot within a specific city place. It can be a + * piece of art, a ticket dispenser or a relevant point of interest. + * + * Each iBeacon device is physically attached to the spot it locates and + * advertises the triplet UUID, major ID and minor ID. + * + * @par Proximity + * + * The beacon advertises the signal strength measured by an iOS device at a + * distance of one meter. iOS uses this information to approximate the + * proximity to a given beacon: + * - Immediate: The beacon is less than one meter away from the user. + * - Near: The beacon is one to three meters away from the user. + * - Far: The user is not near the beacon; the distance highly depends on + * the physical environment. + * + * Ideally, beacons should be calibrated at their deployment location because the + * surrounding environment affects the strength of the advertised signal. + * + * @par Usage + * + * Mbed OS applications can use this class to configure a device to broadcast + * advertising packets mimicking an iBeacon. The construction automatically + * creates the payload identifying the beacon and registers it as part of the + * advertising payload of the device. + * + * Beacon configuration and advertising commencement is left to the user. + * + * @important If you are interested in manufacturing iBeacons, you must obtain a + * license from Apple. More information at https://developer.apple.com/ibeacon/. + * The licence also grant access to the iBeacons technical specification. + * + * @note More information at https://developer.apple.com/ibeacon/Getting-Started-with-iBeacon.pdf + */ class iBeacon { public: + /** + * Data buffer of a location UUID. + */ typedef const uint8_t LocationUUID_t[16]; + /** + * iBeacon payload builder. + * + * This data structure contains the payload of an iBeacon. The payload is + * built at construction time and application code can set up an iBeacon by + * injecting the raw field into the GAP advertising payload as a + * GapAdvertisingData::MANUFACTURER_SPECIFIC_DATA. + */ union Payload { + /** + * Raw data of the payload. + */ uint8_t raw[25]; struct { + /** + * Beacon manufacturer identifier. + */ uint16_t companyID; + + /** + * Packet ID; Equal to 2 for an iBeacon. + */ uint8_t ID; + + /** + * Length of the remaining data presents in the payload. + */ uint8_t len; + + /** + * Beacon UUID. + */ uint8_t proximityUUID[16]; + + /** + * Beacon Major group ID. + */ uint16_t majorNumber; + + /** + * Beacon minor ID. + */ uint16_t minorNumber; + + /** + * Tx power received at 1 meter; in dBm. + */ uint8_t txPower; }; - Payload(LocationUUID_t uuid, uint16_t majNum, uint16_t minNum, uint8_t transmitPower, uint16_t companyIDIn) : - companyID(companyIDIn), ID(0x02), len(0x15), majorNumber(__REV16(majNum)), minorNumber(__REV16(minNum)), txPower(transmitPower) + /** + * Assemble an iBeacon payload. + * + * @param[in] uuid Beacon network ID. iBeacon operators use this value + * to group their iBeacons into a single network, a single region and + * identify their organization among others. + * + * @param[in] majNum Beacon major group ID. iBeacon exploitants may use + * this field to divide the region into subregions, their network into + * subnetworks. + * + * @param[in] minNum Identifier of the Beacon in its subregion. + * + * @param[in] transmitPower Measured transmit power of the beacon at 1 + * meter. Scanners use this parameter to approximate the distance + * to the beacon. + * + * @param[in] companyIDIn ID of the beacon manufacturer. + */ + Payload( + LocationUUID_t uuid, + uint16_t majNum, + uint16_t minNum, + uint8_t transmitPower, + uint16_t companyIDIn + ) : companyID(companyIDIn), + ID(0x02), + len(0x15), + majorNumber(__REV16(majNum)), + minorNumber(__REV16(minNum)), + txPower(transmitPower) { memcpy(proximityUUID, uuid, sizeof(LocationUUID_t)); } }; public: - iBeacon(BLE &_ble, - LocationUUID_t uuid, - uint16_t majNum, - uint16_t minNum, - uint8_t txP = 0xC8, - uint16_t compID = 0x004C) : - ble(_ble), data(uuid, majNum, minNum, txP, compID) + /** + * Construct an iBeacon::Payload and register it into Gap. + * + * @param[in] _ble The BLE interface to configure with the iBeacon payload. + * + * @param[in] uuid Beacon network ID. iBeacon operators use this value + * to group their iBeacons into a single network, a single region and + * identify their organization among others. + * + * @param[in] majNum Beacon major group ID. iBeacon exploitants may use + * this field to divide the region into subregions, their network into + * subnetworks. + * + * @param[in] minNum Identifier of the Beacon in its subregion. + * + * @param[in] txP Measured transmit power of the beacon at 1 + * meter. Scanners use this parameter to approximate the distance + * to the beacon. + * + * @param[in] compID ID of the beacon manufacturer. + */ + iBeacon( + BLE &_ble, + LocationUUID_t uuid, + uint16_t majNum, + uint16_t minNum, + uint8_t txP = 0xC8, + uint16_t compID = 0x004C + ) : ble(_ble), + data(uuid, majNum, minNum, txP, compID) { // Generate the 0x020106 part of the iBeacon Prefix. - ble.accumulateAdvertisingPayload(GapAdvertisingData::BREDR_NOT_SUPPORTED | GapAdvertisingData::LE_GENERAL_DISCOVERABLE ); + ble.accumulateAdvertisingPayload( + GapAdvertisingData::BREDR_NOT_SUPPORTED | + GapAdvertisingData::LE_GENERAL_DISCOVERABLE + ); // Generate the 0x1AFF part of the iBeacon Prefix. - ble.accumulateAdvertisingPayload(GapAdvertisingData::MANUFACTURER_SPECIFIC_DATA, data.raw, sizeof(data.raw)); + ble.accumulateAdvertisingPayload( + GapAdvertisingData::MANUFACTURER_SPECIFIC_DATA, + data.raw, + sizeof(data.raw) + ); // Set advertising type. - ble.setAdvertisingType(GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED); + ble.setAdvertisingType( + GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED + ); } protected: - BLE &ble; - Payload data; + BLE &ble; + Payload data; }; -typedef iBeacon iBeaconService; /* This type-alias is deprecated. Please use iBeacon directly. This alias may be dropped from a future release. */ +/** + * iBeacon alias. + * + * @deprecated Please use iBeacon directly. This alias may be dropped from a + * future release. + */ +typedef iBeacon iBeaconService; -#endif //__BLE_IBEACON_H__ +#endif //MBED_BLE_IBEACON_H__ diff --git a/features/FEATURE_BLE/source/BLE.cpp b/features/FEATURE_BLE/source/BLE.cpp index d9349477a5b..2d90b083bf6 100644 --- a/features/FEATURE_BLE/source/BLE.cpp +++ b/features/FEATURE_BLE/source/BLE.cpp @@ -14,6 +14,7 @@ * limitations under the License. */ +#include #include "ble/BLE.h" #include "ble/BLEInstanceBase.h" @@ -139,7 +140,8 @@ void defaultSchedulingCallback(BLE::OnEventsToProcessCallbackContext* params) { BLE::BLE(InstanceID_t instanceIDIn) : instanceID(instanceIDIn), transport(), - whenEventsToProcess(defaultSchedulingCallback) + whenEventsToProcess(defaultSchedulingCallback), + event_signaled(false) { static BLEInstanceBase *transportInstances[NUM_INSTANCES]; @@ -168,6 +170,7 @@ ble_error_t BLE::shutdown(void) error("bad handle to underlying transport"); } + event_signaled = false; return transport->shutdown(); } @@ -263,20 +266,41 @@ void BLE::waitForEvent(void) void BLE::processEvents() { + if (event_signaled == false) { + return; + } + if (!transport) { error("bad handle to underlying transport"); } + event_signaled = false; + transport->processEvents(); } void BLE::onEventsToProcess(const BLE::OnEventsToProcessCallback_t& callback) { whenEventsToProcess = callback; + + // If events were previously signaled but the handler was not in place then + // signal immediately events availability + if (event_signaled && whenEventsToProcess) { + OnEventsToProcessCallbackContext params = { + *this + }; + whenEventsToProcess(¶ms); + } } void BLE::signalEventsToProcess() { + if (event_signaled == true) { + return; + } + + event_signaled = true; + if (whenEventsToProcess) { OnEventsToProcessCallbackContext params = { *this diff --git a/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp index 057b151edac..c2445472990 100644 --- a/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp +++ b/features/FEATURE_BLE/targets/TARGET_ARM_SSG/TARGET_BEETLE/source/ArmGattServer.cpp @@ -130,6 +130,9 @@ ble_error_t ArmGattServer::addService(GattService &service) currAtt->pLen = p_char->getValueAttribute().getLengthPtr(); currAtt->maxLen = p_char->getValueAttribute().getMaxLength(); currAtt->settings = ATTS_SET_WRITE_CBACK | ATTS_SET_READ_CBACK; + if (p_char->getValueAttribute().hasVariableLength()) { + currAtt->settings |= ATTS_SET_VARIABLE_LEN; + } if (p_char->getValueAttribute().getUUID().shortOrLong() == UUID::UUID_TYPE_LONG) { currAtt->settings |= ATTS_SET_UUID_128; } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/source/btle/btle_discovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/source/btle/btle_discovery.cpp index fdf0ec76ca5..a93a27c32e5 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/source/btle/btle_discovery.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/source/btle/btle_discovery.cpp @@ -87,12 +87,13 @@ void bleGattcEventHandler(const ble_evt_t *p_ble_evt) break; case BLE_GATTC_EVT_HVX: { - GattHVXCallbackParams params; - /* params.connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle; - /* params.handle = */ p_ble_evt->evt.gattc_evt.params.hvx.handle; - /* params.type = */ static_cast(p_ble_evt->evt.gattc_evt.params.hvx.type); - /* params.len = */ p_ble_evt->evt.gattc_evt.params.hvx.len; - /* params.data = */ p_ble_evt->evt.gattc_evt.params.hvx.data; + GattHVXCallbackParams params = { + /* connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, + /* handle = */ p_ble_evt->evt.gattc_evt.params.hvx.handle, + /* type = */ static_cast(p_ble_evt->evt.gattc_evt.params.hvx.type), + /* len = */ p_ble_evt->evt.gattc_evt.params.hvx.len, + /* data = */ p_ble_evt->evt.gattc_evt.params.hvx.data + }; gattClient.processHVXEvent(¶ms); } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp index 8090e8498b0..5f7c899ae92 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp @@ -87,12 +87,13 @@ void bleGattcEventHandler(const ble_evt_t *p_ble_evt) break; case BLE_GATTC_EVT_HVX: { - GattHVXCallbackParams params; - /* params.connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle; - /* params.handle = */ p_ble_evt->evt.gattc_evt.params.hvx.handle; - /* params.type = */ static_cast(p_ble_evt->evt.gattc_evt.params.hvx.type); - /* params.len = */ p_ble_evt->evt.gattc_evt.params.hvx.len; - /* params.data = */ p_ble_evt->evt.gattc_evt.params.hvx.data; + GattHVXCallbackParams params = { + /* connHandle = */ p_ble_evt->evt.gattc_evt.conn_handle, + /* handle = */ p_ble_evt->evt.gattc_evt.params.hvx.handle, + /* type = */ static_cast(p_ble_evt->evt.gattc_evt.params.hvx.type), + /* len = */ p_ble_evt->evt.gattc_evt.params.hvx.len, + /* data = */ p_ble_evt->evt.gattc_evt.params.hvx.data + }; gattClient.processHVXEvent(¶ms); } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c index 32918059f61..2e747a60ef5 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_eth.c @@ -215,10 +215,15 @@ static void __eth_clk_pin_init() /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ // Configure RMII pins - SYS->GPA_MFPL = SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR | SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV; - SYS->GPC_MFPL = SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 | SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0; - SYS->GPC_MFPH = SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK; - SYS->GPE_MFPH = SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC | + SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA6MFP_Msk | SYS_GPA_MFPL_PA7MFP_Msk); + SYS->GPA_MFPL |= SYS_GPA_MFPL_PA6MFP_EMAC_RMII_RXERR | SYS_GPA_MFPL_PA7MFP_EMAC_RMII_CRSDV; + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC7MFP_Msk); + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC6MFP_EMAC_RMII_RXD1 | SYS_GPC_MFPL_PC7MFP_EMAC_RMII_RXD0; + SYS->GPC_MFPH &= ~SYS_GPC_MFPH_PC8MFP_Msk; + SYS->GPC_MFPH |= SYS_GPC_MFPH_PC8MFP_EMAC_RMII_REFCLK; + SYS->GPE_MFPH &= ~(SYS_GPE_MFPH_PE8MFP_Msk | SYS_GPE_MFPH_PE9MFP_Msk | SYS_GPE_MFPH_PE10MFP_Msk | + SYS_GPE_MFPH_PE11MFP_Msk | SYS_GPE_MFPH_PE12MFP_Msk); + SYS->GPE_MFPH |= SYS_GPE_MFPH_PE8MFP_EMAC_RMII_MDC | SYS_GPE_MFPH_PE9MFP_EMAC_RMII_MDIO | SYS_GPE_MFPH_PE10MFP_EMAC_RMII_TXD0 | SYS_GPE_MFPH_PE11MFP_EMAC_RMII_TXD1 | diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c index 1101f5b1e50..6c22b03bb57 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_NUC472/nuc472_eth.c @@ -207,6 +207,9 @@ static void __eth_clk_pin_init() /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ // Configure RMII pins + SYS->GPC_MFPL &= ~( SYS_GPC_MFPL_PC0MFP_Msk | SYS_GPC_MFPL_PC1MFP_Msk | + SYS_GPC_MFPL_PC2MFP_Msk | SYS_GPC_MFPL_PC3MFP_Msk | + SYS_GPC_MFPL_PC4MFP_Msk | SYS_GPC_MFPL_PC6MFP_Msk | SYS_GPC_MFPL_PC7MFP_Msk ); SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK | SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR | SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV | @@ -215,12 +218,13 @@ static void __eth_clk_pin_init() SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 | SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1; - + SYS->GPC_MFPH &= ~SYS_GPC_MFPH_PC8MFP_Msk; SYS->GPC_MFPH |= SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN; // Enable high slew rate on all RMII pins PC->SLEWCTL |= 0x1DF; // Configure MDC, MDIO at PB14 & PB15 + SYS->GPB_MFPH &= ~(SYS_GPB_MFPH_PB14MFP_Msk | SYS_GPB_MFPH_PB15MFP_Msk); SYS->GPB_MFPH |= SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c index a9aef9a524c..5b3b326435a 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/lpc17_emac.c @@ -63,6 +63,12 @@ * @{ */ +#if defined(TARGET_LPC1768) || defined(TARGET_LPC1769) +/** \brief Group LPC17xx processors into one definition + */ +#define TARGET_LPC17XX +#endif + #if NO_SYS == 0 /** \brief Driver transmit and receive thread priorities * @@ -146,8 +152,8 @@ struct lpc_enetdata { # else # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned)) # endif -#elif defined(TARGET_LPC1768) -# if defined(TOOLCHAIN_GCC_ARM) +#elif defined(TARGET_LPC17XX) +# if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM) # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned)) # endif #endif @@ -370,7 +376,7 @@ static struct pbuf *lpc_low_level_input(struct netif *netif) LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE, ("lpc_low_level_input: Packet index %"U32_F" dropped for OOM\n", idx)); - + #ifdef LOCK_RX_THREAD #if NO_SYS == 0 sys_mutex_unlock(&lpc_enetif->TXLockMutex); @@ -428,7 +434,7 @@ void lpc_enetif_input(struct netif *netif) */ static s32_t lpc_packet_addr_notsafe(void *addr) { /* Check for legal address ranges */ -#if defined(TARGET_LPC1768) +#if defined(TARGET_LPC17XX) if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) { #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) { @@ -790,7 +796,7 @@ static err_t low_level_init(struct netif *netif) /* Enable MII clocking */ LPC_SC->PCONP |= CLKPWR_PCONP_PCENET; -#if defined(TARGET_LPC1768) +#if defined(TARGET_LPC17XX) LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */ LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005; #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c new file mode 100644 index 00000000000..56f754a4f4c --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_conf.c @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "stm32f4xx_hal.h" + +void _eth_config_mac(ETH_HandleTypeDef *heth) +{ + ETH_MACInitTypeDef macconf = + { + .Watchdog = ETH_WATCHDOG_ENABLE, + .Jabber = ETH_JABBER_ENABLE, + .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, + .CarrierSense = ETH_CARRIERSENCE_ENABLE, + .ReceiveOwn = ETH_RECEIVEOWN_ENABLE, + .LoopbackMode = ETH_LOOPBACKMODE_DISABLE, + .ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE, + .RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE, + .AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE, + .BackOffLimit = ETH_BACKOFFLIMIT_10, + .DeferralCheck = ETH_DEFFERRALCHECK_DISABLE, + .ReceiveAll = ETH_RECEIVEAll_DISABLE, + .SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE, + .PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL, + .BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE, + .DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL, + .PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE, + .MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter + .UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT, + .HashTableHigh = 0x0U, + .HashTableLow = 0x0U, + .PauseTime = 0x0U, + .ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE, + .PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4, + .UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE, + .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, + .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, + .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, + .VLANTagIdentifier = 0x0U + }; + + if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } else { + macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + + (void) HAL_ETH_ConfigMAC(heth, &macconf); +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c new file mode 100644 index 00000000000..f9ee0771e7a --- /dev/null +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_MBED_CONNECT_ODIN/stm32f4_eth_init.c @@ -0,0 +1,143 @@ +#include +#include "stm32f4xx_hal.h" +#include "mbed_toolchain.h" + +#define C029_OTP_START_ADDRESS (0x1FFF7800U) +#define C029_OTP_END_ADDRESS (C029_OTP_START_ADDRESS + (16*32)) +#define C029_MAC_ETHERNET_ID (3) + +typedef MBED_PACKED(struct) C029_OTP_Header { + uint8_t id; + uint8_t len; + uint8_t data[]; +} C029_OTP_Header; + +static int _macRetrieved = 0; +static char _macAddr[6] = { 0x02, 0x02, 0xF7, 0xF0, 0x00, 0x00 }; + +static C029_OTP_Header *increment(C029_OTP_Header *pTemp) +{ + uint8_t len = 0; + uint8_t id = 0; + uint8_t *p = (uint8_t*)pTemp; + + memcpy((void*)&id, (void*)pTemp, 1); + + if (id == 0xFF){ + p++; + } else { + p++; + memcpy((void*)&len, (void*)p++, 1); + p += len; + } + return (C029_OTP_Header*)p; +} + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) +{ + GPIO_InitTypeDef GPIO_InitStructure; + if (heth->Instance == ETH) { + + /* Enable GPIOs clocks */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + /* Configure PA1, PA2 and PA7 */ + GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_PULLUP; + GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7; + GPIO_InitStructure.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Pin = GPIO_PIN_1; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + /* Configure PB13 */ + GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + /* Configure PC1, PC4 and PC5 */ + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Enable the Ethernet global Interrupt */ + HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); + HAL_NVIC_EnableIRQ(ETH_IRQn); + + /* Enable ETHERNET clock */ + __HAL_RCC_ETH_CLK_ENABLE(); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth) +{ + if (heth->Instance == ETH) { + /* Peripheral clock disable */ + __HAL_RCC_ETH_CLK_DISABLE(); + + /** ETH GPIO Configuration + RMII_REF_CLK ----------------------> PA1 + RMII_MDIO -------------------------> PA2 + RMII_MDC --------------------------> PC1 + RMII_MII_CRS_DV -------------------> PA7 + RMII_MII_RXD0 ---------------------> PC4 + RMII_MII_RXD1 ---------------------> PC5 + RMII_MII_RXER ---------------------> PG2 + RMII_MII_TX_EN --------------------> PB11 + RMII_MII_TXD0 ---------------------> PB12 + RMII_MII_TXD1 ---------------------> PB13 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7); + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12); + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5); + + /* Disable the Ethernet global Interrupt */ + NVIC_DisableIRQ(ETH_IRQn); + } +} + +uint8_t mbed_otp_mac_address(char *mac) +{ + C029_OTP_Header *pFound = NULL; + C029_OTP_Header *pTemp = (C029_OTP_Header*)C029_OTP_START_ADDRESS; + C029_OTP_Header temp; + + if (_macRetrieved == 0) { + while ((pTemp >= (C029_OTP_Header*)C029_OTP_START_ADDRESS) && (pTemp < (C029_OTP_Header*)C029_OTP_END_ADDRESS)){ + memcpy((void*)&temp, (void*)pTemp, sizeof(temp)); + if (temp.id == C029_MAC_ETHERNET_ID){ + pFound = pTemp; + break; + } + pTemp = increment(pTemp); + } + if (pFound != NULL) { + memcpy(_macAddr, pFound->data, 6); + _macRetrieved = 1; + } + } + memcpy(mac, _macAddr, 6); + + return 1; +} diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c index 7325f42caf3..56f754a4f4c 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_conf.c @@ -19,7 +19,7 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) { ETH_MACInitTypeDef macconf = - { + { .Watchdog = ETH_WATCHDOG_ENABLE, .Jabber = ETH_JABBER_ENABLE, .InterFrameGap = ETH_INTERFRAMEGAP_96BIT, @@ -48,8 +48,8 @@ void _eth_config_mac(ETH_HandleTypeDef *heth) .ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE, .TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE, .VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT, - .VLANTagIdentifier = 0x0U, - }; + .VLANTagIdentifier = 0x0U + }; if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) { macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c index 89fd896139d..f9ee0771e7a 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_EVK_ODIN_W2/stm32f4_eth_init.c @@ -25,8 +25,7 @@ static C029_OTP_Header *increment(C029_OTP_Header *pTemp) if (id == 0xFF){ p++; - } - else { + } else { p++; memcpy((void*)&len, (void*)p++, 1); p += len; @@ -59,31 +58,30 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef* heth) RMII_MII_TXD0 ---------------------> PB12 RMII_MII_TXD1 ---------------------> PB13 */ - /* Configure PA1, PA2 and PA7 */ + /* Configure PA1, PA2 and PA7 */ GPIO_InitStructure.Speed = GPIO_SPEED_HIGH; GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; GPIO_InitStructure.Pull = GPIO_PULLUP; GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_7; GPIO_InitStructure.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); - + GPIO_InitStructure.Pull = GPIO_NOPULL; GPIO_InitStructure.Pin = GPIO_PIN_1; HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); /* Configure PB13 */ - GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_11 | GPIO_PIN_12; HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); /* Configure PC1, PC4 and PC5 */ GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; - HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); - + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); /* Enable the Ethernet global Interrupt */ HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0); HAL_NVIC_EnableIRQ(ETH_IRQn); - + /* Enable ETHERNET clock */ __HAL_RCC_ETH_CLK_ENABLE(); } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c index 5d3319e446c..134cea811d8 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_STM/stm32xx_emac.c @@ -46,6 +46,10 @@ static sys_mutex_t tx_lock_mutex; /* function */ static void _eth_arch_rx_task(void *arg); static void _eth_arch_phy_task(void *arg); +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ + || defined (STM32F779xx) +static void _rmii_watchdog(void *arg); +#endif #if LWIP_IPV4 static err_t _eth_arch_netif_output_ipv4(struct netif *netif, struct pbuf *q, const ip4_addr_t *ipaddr); @@ -95,9 +99,6 @@ void ETH_IRQHandler(void) */ static void _eth_arch_low_level_init(struct netif *netif) { - uint32_t regvalue = 0; - HAL_StatusTypeDef hal_eth_init_status; - /* Init ETH */ uint8_t MACAddr[6]; EthHandle.Instance = ETH; @@ -119,7 +120,7 @@ static void _eth_arch_low_level_init(struct netif *netif) EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE; EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE; EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; - hal_eth_init_status = HAL_ETH_Init(&EthHandle); + HAL_ETH_Init(&EthHandle); /* Initialize Tx Descriptors list: Chain Mode */ HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); @@ -375,6 +376,36 @@ static void _eth_arch_phy_task(void *arg) } } +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ + || defined (STM32F779xx) +/** + * workaround for the ETH RMII bug in STM32F76x and STM32F77x revA + * + * \param[in] netif the lwip network interface structure + */ +static void _rmii_watchdog(void *arg) +{ + while(1) { + /* some good packets are received */ + if (EthHandle.Instance->MMCRGUFCR > 0) { + /* RMII Init is OK - would need service to terminate or suspend + * the thread */ + while(1) { + /* don't do anything anymore */ + osDelay(0xFFFFFFFF); + } + } else if (EthHandle.Instance->MMCRFCECR > 10) { + /* ETH received too many packets with CRC errors, resetting RMII */ + SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL; + SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; + EthHandle.Instance->MMCCR |= ETH_MMCCR_CR; + } else { + osDelay(100); + } + } +} +#endif + /** * This function is the ethernet IPv4 packet send function. It calls * etharp_output after checking link status. @@ -468,6 +499,11 @@ err_t eth_arch_enetif_init(struct netif *netif) /* initialize the hardware */ _eth_arch_low_level_init(netif); +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ + || defined (STM32F779xx) + sys_thread_new("stm32_rmii_watchdog", _rmii_watchdog, netif, DEFAULT_THREAD_STACKSIZE, osPriorityLow); +#endif + return ERR_OK; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c index ec2e1f92cef..17b681e5901 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/core/lwip_tcp.c @@ -358,7 +358,6 @@ tcp_close_shutdown_fin(struct tcp_pcb *pcb) default: /* Has already been closed, do nothing. */ return ERR_OK; - break; } if (err == ERR_OK) { diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c index 064612ba6fc..7325703f5ec 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c @@ -32,8 +32,10 @@ #include "lwip/tcp.h" #include "lwip/ip.h" #include "lwip/mld6.h" +#include "lwip/igmp.h" #include "lwip/dns.h" #include "lwip/udp.h" +#include "lwip_errno.h" #include "netif/lwip_ethernet.h" #include "emac_api.h" #include "ppp_lwip.h" @@ -46,6 +48,10 @@ static nsapi_error_t mbed_lwip_err_remap(err_t err); #define MBED_NETIF_INIT_FN eth_arch_enetif_init #endif +#ifndef LWIP_SOCKET_MAX_MEMBERSHIPS + #define LWIP_SOCKET_MAX_MEMBERSHIPS 4 +#endif + /* Static arena of sockets */ static struct lwip_socket { bool in_use; @@ -56,6 +62,12 @@ static struct lwip_socket { void (*cb)(void *); void *data; + + // Track multicast addresses subscribed to by this socket + nsapi_ip_mreq_t *multicast_memberships; + uint32_t multicast_memberships_count; + uint32_t multicast_memberships_registry; + } lwip_arena[MEMP_NUM_NETCONN]; static bool lwip_inited = false; @@ -63,6 +75,26 @@ static bool lwip_connected = false; static bool netif_inited = false; static bool netif_is_ppp = false; +static nsapi_error_t mbed_lwip_setsockopt(nsapi_stack_t *stack, nsapi_socket_t handle, int level, int optname, const void *optval, unsigned optlen); + +static inline uint32_t next_registered_multicast_member(const struct lwip_socket *s, uint32_t index) { + while (!(s->multicast_memberships_registry & (0x0001 << index))) { index++; } + return index; +} + +static inline uint32_t next_free_multicast_member(const struct lwip_socket *s, uint32_t index) { + while ((s->multicast_memberships_registry & (0x0001 << index))) { index++; } + return index; +} + +static inline void set_multicast_member_registry_bit(struct lwip_socket *s, uint32_t index) { + s->multicast_memberships_registry |= (0x0001 << index); +} + +static inline void clear_multicast_member_registry_bit(struct lwip_socket *s, uint32_t index) { + s->multicast_memberships_registry &= ~(0x0001 << index); +} + static struct lwip_socket *mbed_lwip_arena_alloc(void) { sys_prot_t prot = sys_arch_protect(); @@ -84,6 +116,18 @@ static struct lwip_socket *mbed_lwip_arena_alloc(void) static void mbed_lwip_arena_dealloc(struct lwip_socket *s) { s->in_use = false; + + while (s->multicast_memberships_count > 0) { + uint32_t index = 0; + index = next_registered_multicast_member(s, index); + + mbed_lwip_setsockopt(NULL, s, NSAPI_SOCKET, NSAPI_DROP_MEMBERSHIP, &s->multicast_memberships[index], + sizeof(s->multicast_memberships[index])); + index++; + } + + free(s->multicast_memberships); + s->multicast_memberships = NULL; } static void mbed_lwip_socket_callback(struct netconn *nc, enum netconn_evt eh, u16_t len) @@ -293,7 +337,9 @@ static int get_ip_addr_type(const ip_addr_t *ip_addr) return IPADDR_TYPE_V4; } #endif +#if LWIP_IPV6 && LWIP_IPV4 return IPADDR_TYPE_ANY; +#endif } void add_dns_addr(struct netif *lwip_netif) @@ -658,7 +704,7 @@ nsapi_error_t mbed_lwip_bringup_2(bool dhcp, bool ppp, const char *ip, const cha if (!netif_is_link_up(&lwip_netif)) { if (sys_arch_sem_wait(&lwip_netif_linked, 15000) == SYS_ARCH_TIMEOUT) { if (ppp) { - ppp_lwip_disconnect(); + (void) ppp_lwip_disconnect(); } return NSAPI_ERROR_NO_CONNECTION; } @@ -686,7 +732,7 @@ nsapi_error_t mbed_lwip_bringup_2(bool dhcp, bool ppp, const char *ip, const cha if (!mbed_lwip_get_ip_addr(true, &lwip_netif)) { if (sys_arch_sem_wait(&lwip_netif_has_any_addr, DHCP_TIMEOUT * 1000) == SYS_ARCH_TIMEOUT) { if (ppp) { - ppp_lwip_disconnect(); + (void) ppp_lwip_disconnect(); } return NSAPI_ERROR_DHCP_FAILURE; } @@ -1081,6 +1127,24 @@ static nsapi_size_or_error_t mbed_lwip_socket_recvfrom(nsapi_stack_t *stack, nsa return recv; } +static int32_t find_multicast_member(const struct lwip_socket *s, const nsapi_ip_mreq_t *imr) { + uint32_t count = 0; + uint32_t index = 0; + // Set upper limit on while loop, should break out when the membership pair is found + while (count < s->multicast_memberships_count) { + index = next_registered_multicast_member(s, index); + + if (memcmp(&s->multicast_memberships[index].imr_multiaddr, &imr->imr_multiaddr, sizeof(nsapi_addr_t)) == 0 && + memcmp(&s->multicast_memberships[index].imr_interface, &imr->imr_interface, sizeof(nsapi_addr_t)) == 0) { + return index; + } + count++; + index++; + } + + return -1; +} + static nsapi_error_t mbed_lwip_setsockopt(nsapi_stack_t *stack, nsapi_socket_t handle, int level, int optname, const void *optval, unsigned optlen) { struct lwip_socket *s = (struct lwip_socket *)handle; @@ -1124,6 +1188,103 @@ static nsapi_error_t mbed_lwip_setsockopt(nsapi_stack_t *stack, nsapi_socket_t h } return 0; + case NSAPI_ADD_MEMBERSHIP: + case NSAPI_DROP_MEMBERSHIP: { + if (optlen != sizeof(nsapi_ip_mreq_t)) { + return NSAPI_ERROR_PARAMETER; + } + err_t igmp_err; + const nsapi_ip_mreq_t *imr = optval; + + /* Check interface address type matches group, or is unspecified */ + if (imr->imr_interface.version != NSAPI_UNSPEC && imr->imr_interface.version != imr->imr_multiaddr.version) { + return NSAPI_ERROR_PARAMETER; + } + + ip_addr_t if_addr; + ip_addr_t multi_addr; + + /* Convert the group address */ + if (!convert_mbed_addr_to_lwip(&multi_addr, &imr->imr_multiaddr)) { + return NSAPI_ERROR_PARAMETER; + } + + /* Convert the interface address, or make sure it's the correct sort of "any" */ + if (imr->imr_interface.version != NSAPI_UNSPEC) { + if (!convert_mbed_addr_to_lwip(&if_addr, &imr->imr_interface)) { + return NSAPI_ERROR_PARAMETER; + } + } else { + ip_addr_set_any(IP_IS_V6(&if_addr), &if_addr); + } + + igmp_err = ERR_USE; // Maps to NSAPI_ERROR_UNSUPPORTED + int32_t member_pair_index = find_multicast_member(s, imr); + + if (optname == NSAPI_ADD_MEMBERSHIP) { + if (!s->multicast_memberships) { + // First multicast join on this socket, allocate space for membership tracking + s->multicast_memberships = malloc(sizeof(nsapi_ip_mreq_t) * LWIP_SOCKET_MAX_MEMBERSHIPS); + if (!s->multicast_memberships) { + return NSAPI_ERROR_NO_MEMORY; + } + } else if(s->multicast_memberships_count == LWIP_SOCKET_MAX_MEMBERSHIPS) { + return NSAPI_ERROR_NO_MEMORY; + } + + if (member_pair_index != -1) { + return NSAPI_ERROR_ADDRESS_IN_USE; + } + + member_pair_index = next_free_multicast_member(s, 0); + + sys_prot_t prot = sys_arch_protect(); + + #if LWIP_IPV4 + if (IP_IS_V4(&if_addr)) { + igmp_err = igmp_joingroup(ip_2_ip4(&if_addr), ip_2_ip4(&multi_addr)); + } + #endif + #if LWIP_IPV6 + if (IP_IS_V6(&if_addr)) { + igmp_err = mld6_joingroup(ip_2_ip6(&if_addr), ip_2_ip6(&multi_addr)); + } + #endif + + sys_arch_unprotect(prot); + + if (igmp_err == ERR_OK) { + set_multicast_member_registry_bit(s, member_pair_index); + s->multicast_memberships[member_pair_index] = *imr; + s->multicast_memberships_count++; + } + } else { + if (member_pair_index == -1) { + return NSAPI_ERROR_NO_ADDRESS; + } + + clear_multicast_member_registry_bit(s, member_pair_index); + s->multicast_memberships_count--; + + sys_prot_t prot = sys_arch_protect(); + + #if LWIP_IPV4 + if (IP_IS_V4(&if_addr)) { + igmp_err = igmp_leavegroup(ip_2_ip4(&if_addr), ip_2_ip4(&multi_addr)); + } + #endif + #if LWIP_IPV6 + if (IP_IS_V6(&if_addr)) { + igmp_err = mld6_leavegroup(ip_2_ip6(&if_addr), ip_2_ip6(&multi_addr)); + } + #endif + + sys_arch_unprotect(prot); + } + + return mbed_lwip_err_remap(igmp_err); + } + default: return NSAPI_ERROR_UNSUPPORTED; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwipopts.h b/features/FEATURE_LWIP/lwip-interface/lwipopts.h index 0b422627c9f..608cc994e78 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwipopts.h +++ b/features/FEATURE_LWIP/lwip-interface/lwipopts.h @@ -137,10 +137,25 @@ #define LWIP_RAM_HEAP_POINTER lwip_ram_heap // Number of pool pbufs. -// Each requires 684 bytes of RAM. +// Each requires 684 bytes of RAM (if MSS=536 and PBUF_POOL_BUFSIZE defaulting to be based on MSS) +#ifdef MBED_CONF_LWIP_PBUF_POOL_SIZE +#undef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE MBED_CONF_LWIP_PBUF_POOL_SIZE +#else #ifndef PBUF_POOL_SIZE #define PBUF_POOL_SIZE 5 #endif +#endif + +#ifdef MBED_CONF_LWIP_PBUF_POOL_BUFSIZE +#undef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE MBED_CONF_LWIP_PBUF_POOL_BUFSIZE +#endif + +#ifdef MBED_CONF_LWIP_MEM_SIZE +#undef MEM_SIZE +#define MEM_SIZE MBED_CONF_LWIP_MEM_SIZE +#endif // One tcp_pcb_listen is needed for each TCPServer. // Each requires 72 bytes of RAM. diff --git a/features/FEATURE_LWIP/lwip-interface/mbed_lib.json b/features/FEATURE_LWIP/lwip-interface/mbed_lib.json index d1e4feff039..6d9def2aa17 100644 --- a/features/FEATURE_LWIP/lwip-interface/mbed_lib.json +++ b/features/FEATURE_LWIP/lwip-interface/mbed_lib.json @@ -72,6 +72,18 @@ "help": "Maximum number of open UDPSocket instances allowed, including one used internally for DNS. Each requires 84 bytes of pre-allocated RAM", "value": 4 }, + "pbuf-pool-size": { + "help": "Number of pbufs in pool - usually used for received packets, so this determines how much data can be buffered between reception and the application reading. If a driver uses PBUF_RAM for reception, less pool may be needed. Current default (used if null here) is set to 5 in lwipopts.h, unless overridden by target Ethernet drivers.", + "value": null + }, + "pbuf-pool-bufsize": { + "help": "Size of pbufs in pool. If set to null, lwIP will base the size on the TCP MSS, which is 536 unless overridden by the target", + "value": null + }, + "mem-size": { + "help": "Size of heap (bytes) - used for outgoing packets, and also used by some drivers for reception. Current default (used if null here) is set to 1600 in opt.h, unless overridden by target Ethernet drivers.", + "value": null + }, "tcpip-thread-stacksize": { "help": "Stack size for lwip TCPIP thread", "value": 1200 diff --git a/features/FEATURE_UVISOR/AUTHORS.txt b/features/FEATURE_UVISOR/AUTHORS.txt index b736cbbd739..e4a33f3291b 100644 --- a/features/FEATURE_UVISOR/AUTHORS.txt +++ b/features/FEATURE_UVISOR/AUTHORS.txt @@ -1,25 +1,26 @@ 600 Alessandro Angelino 592 Milosch Meriac - 190 Jaeden Amero + 213 Jaeden Amero 89 Niklas Hauser - 10 Fangyi Zhou - 6 Michael Schwarcz - 5 Irit Arkin - 5 Alexander Zilberkant - 4 Amir Cohen - 3 Hugo Vincent + 27 Fangyi Zhou + 14 Michael Schwarcz + 8 Alexander Zilberkant + 7 Irit Arkin + 6 Amir Cohen + 6 Roman Kuznetsov + 4 Amanda Butler + 4 Oren Cohen 3 AnotherButler - 3 Roman Kuznetsov + 3 Danny Shavit + 3 Hugo Vincent + 3 Jan Jongboom 3 JaredCJR 3 Jim Huang - 2 tonyyanxuan - 2 Amanda Butler - 2 Jan Jongboom + 2 Jethro Hsu 2 Nathan Chong - 2 Oren Cohen 2 Vincenzo Frascino 2 ccli8 - 1 Russ Butler - 1 Jethro Hsu + 2 tonyyanxuan 1 Aksel Skauge Mellbye - 1 Danny Shavit + 1 Michael Bartling + 1 Russ Butler diff --git a/features/FEATURE_UVISOR/README.md b/features/FEATURE_UVISOR/README.md index d4531ba5b94..f458f244be6 100644 --- a/features/FEATURE_UVISOR/README.md +++ b/features/FEATURE_UVISOR/README.md @@ -248,7 +248,7 @@ static void private_button_on_press(void) for (int i = 0; i < PRIVATE_BUTTON_BUFFER_COUNT; ++i) { uvisor_ctx->pc->printf("%lu ", uvisor_ctx->buffer[i]); } - uvisor_ctx->pc->printf("\r\n"); + uvisor_ctx->pc->printf("\n"); } } @@ -265,7 +265,7 @@ static void private_button_main_thread(const void *) /* Create the buffer and cache its pointer to the private static memory. */ uvisor_ctx->buffer = (uint32_t *) malloc(PRIVATE_BUTTON_BUFFER_COUNT * sizeof(uint32_t)); if (uvisor_ctx->buffer == NULL) { - uvisor_ctx->pc->printf("ERROR: Failed to allocate memory for the button buffer\r\n"); + uvisor_ctx->pc->printf("ERROR: Failed to allocate memory for the button buffer\n"); mbed_die(); } uvisor_ctx->index = 0; @@ -408,7 +408,7 @@ int main(void) { while (true) { led = !led; - printf("Secure index is %d\r\n", secure_get_index()); + printf("Secure index is %d\n", secure_get_index()); Thread::wait(500); } } @@ -482,5 +482,6 @@ Repeat the process multiple times until all ACLs have been added to the list. Wh - [uVisor API documentation](API.md). - [Debugging uVisor on mbed OS](DEBUGGING.md). +- [Using nonvolatile storage from uVisor on mbed OS](manual/Flash.md). If you found any bug or inconsistency in this guide, please [raise an issue](https://github.com/ARMmbed/uvisor/issues/new). diff --git a/features/FEATURE_UVISOR/VERSION.txt b/features/FEATURE_UVISOR/VERSION.txt index 9388ecbd52f..7021025f318 100644 --- a/features/FEATURE_UVISOR/VERSION.txt +++ b/features/FEATURE_UVISOR/VERSION.txt @@ -1 +1 @@ -v0.30.0 +v0.31.0 diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h index de3b2644a24..46c29c3e255 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/api.h @@ -65,7 +65,6 @@ typedef struct { int (*box_namespace)(int box_id, char *box_namespace, size_t length); int (*box_id_for_namespace)(int * const box_id, const char * const box_namespace); - void (*debug_init)(const TUvisorDebugDriver * const driver); void (*error)(THaltUserError reason); void (*start)(void); void (*vmpu_mem_invalidate)(void); @@ -74,8 +73,8 @@ typedef struct { int (*pool_queue_init)(uvisor_pool_queue_t *, uvisor_pool_t *, void *, size_t, size_t); uvisor_pool_slot_t (*pool_allocate)(uvisor_pool_t *); uvisor_pool_slot_t (*pool_try_allocate)(uvisor_pool_t *); - void (*pool_queue_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t); - int (*pool_queue_try_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t); + uvisor_pool_slot_t (*pool_queue_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t); + uvisor_pool_slot_t (*pool_queue_try_enqueue)(uvisor_pool_queue_t *, uvisor_pool_slot_t); uvisor_pool_slot_t (*pool_free)(uvisor_pool_t *, uvisor_pool_slot_t); uvisor_pool_slot_t (*pool_try_free)(uvisor_pool_t *, uvisor_pool_slot_t); uvisor_pool_slot_t (*pool_queue_dequeue)(uvisor_pool_queue_t *, uvisor_pool_slot_t); diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h index a75ba03cfc9..1f21d6554f3 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/box_config.h @@ -18,6 +18,7 @@ #define __UVISOR_API_BOX_CONFIG_H__ #include "api/inc/uvisor_exports.h" +#include "api/inc/debug_exports.h" #include "api/inc/page_allocator_exports.h" #include "api/inc/rpc_exports.h" #include @@ -169,4 +170,22 @@ UVISOR_EXTERN void const * const public_box_cfg_ptr; #define __uvisor_ctx (((UvisorBoxIndex *) __uvisor_ps)->bss.address_of.context) + +/* Use this macro after calling the box configuration macro, in order to register your box as a debug box. + * It will create a valid debug driver struct with the halt_error_func parameter as its halt_error() function */ +#define UVISOR_DEBUG_DRIVER(box_name, halt_error_func) \ + UVISOR_EXTERN TUvisorDebugDriver const __uvisor_debug_driver; \ + TUvisorDebugDriver const __uvisor_debug_driver = { \ + UVISOR_DEBUG_BOX_MAGIC, \ + UVISOR_DEBUG_BOX_VERSION, \ + &box_name ## _cfg, \ + halt_error_func \ + }; + +/* Use this macro after calling the box configuration macro, in order to + * register the public box as a debug box. */ +#define UVISOR_PUBLIC_BOX_DEBUG_DRIVER(halt_error_func) \ + UVISOR_DEBUG_DRIVER(public_box, halt_error_func) + + #endif /* __UVISOR_API_BOX_CONFIG_H__ */ diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h index a269ba32087..2c8fc3395e0 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/debug_exports.h @@ -19,12 +19,19 @@ #include "api/inc/halt_exports.h" #include +#include "api/inc/vmpu_exports.h" -/* Debug box driver -- Version 0 + +#define UVISOR_DEBUG_BOX_VERSION (1) + + +/* Debug box driver * A constant instance of this struct must be instantiated by the unprivileged * code to setup a debug box.*/ typedef struct TUvisorDebugDriver { - uint32_t (*get_version)(void); + const uint32_t magic; + const uint32_t version; + const UvisorBoxConfig * const box_cfg_ptr; void (*halt_error)(THaltError, const THaltInfo *); } TUvisorDebugDriver; diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h index 5ea9d4f6742..ab173ea8efd 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/halt_exports.h @@ -17,6 +17,8 @@ #ifndef __UVISOR_API_HALT_EXPORTS_H__ #define __UVISOR_API_HALT_EXPORTS_H__ +#include "uvisor_exports.h" + #define UVISOR_ERROR_INVALID_BOX_ID (-2) #define UVISOR_ERROR_BUFFER_TOO_SMALL (-3) #define UVISOR_ERROR_BOX_NAMESPACE_ANONYMOUS (-4) diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h index 19a737a2b50..4186df4c5a3 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/ipc.h @@ -51,10 +51,12 @@ UVISOR_EXTERN int ipc_waitforall(uint32_t wait_tokens, uint32_t * done_tokens, u /** Asynchronously send an IPC message * - * @note The memory used for sending the message (pointed to by msg) must be - * valid until after the send is complete. + * @note The memory used for receiving the message (pointed to by msg) and the + * IPC descriptor (pointed to by desc) must be valid until after the send is + * complete. In addition, each IPC message should use its own IPC descriptor. + * Reusing an IPC descriptor will lead to unpredictable behaviours. * - * @param[in] desc an IPC descriptor for the message + * @param[inout] desc an IPC descriptor for the message * @param[in] msg the message to send * * @return 0 on success, non-zero error code otherwise @@ -63,8 +65,10 @@ UVISOR_EXTERN int ipc_send(uvisor_ipc_desc_t * desc, const void * msg); /** Asynchronously receive an IPC message * - * @note The memory used for receiving the message (pointed to by msg) must be - * valid until after the receive is complete. + * @note The memory used for receiving the message (pointed to by msg) and the + * IPC descriptor (pointed to by desc) must be valid until after the receive is + * complete. In addition, each IPC message should use its own IPC descriptor. + * Reusing an IPC descriptor will lead to unpredictable behaviours. * * @param[inout] desc an IPC descriptor for the message * @param[out] msg the memory to copy the message to diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h index ff8bd38e558..7ebe8579e8d 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/magic_exports.h @@ -37,6 +37,7 @@ #define UVISOR_RPC_GATEWAY_MAGIC_SYNC UDF_OPCODE(0x07C3) #define UVISOR_POOL_MAGIC UDF_OPCODE(0x07C4) #define UVISOR_POOL_QUEUE_MAGIC UDF_OPCODE(0x07C5) +#define UVISOR_DEBUG_BOX_MAGIC UDF_OPCODE(0x07C6) #else #error "Unsupported instruction set. The ARM Thumb-2 instruction set must be supported." #endif /* __thumb__ && __thumb2__ */ diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h index 7175e81d1df..d9764fb3f3d 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/pool_queue_exports.h @@ -19,7 +19,6 @@ #include "api/inc/magic_exports.h" #include "api/inc/uvisor_exports.h" -#include "api/inc/uvisor_semaphore_exports.h" #include "api/inc/uvisor_spinlock_exports.h" #include #include @@ -115,8 +114,8 @@ UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_allocate(uvisor_pool_t * pool); UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_try_allocate(uvisor_pool_t * pool); /* Enqueue the specified slot into the queue. */ -UVISOR_EXTERN void uvisor_pool_queue_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot); -UVISOR_EXTERN int uvisor_pool_queue_try_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot); +UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_queue_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot); +UVISOR_EXTERN uvisor_pool_slot_t uvisor_pool_queue_try_enqueue(uvisor_pool_queue_t * pool_queue, uvisor_pool_slot_t slot); /* Free the specified slot back into the pool. Invalid slots are ignored. * Return the slot that was freed, or UVISOR_POOL_SLOT_IS_FREE if the slot was diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h index 4cfbd950549..ab42ba24700 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor-lib.h @@ -28,7 +28,6 @@ #include "api/inc/api.h" #include "api/inc/box_config.h" #include "api/inc/box_id.h" -#include "api/inc/debug.h" #include "api/inc/disabled.h" #include "api/inc/error.h" #include "api/inc/interrupts.h" diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h index 996db28fde0..3723c4d0998 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/uvisor_exports.h @@ -133,6 +133,12 @@ #define UVISOR_MACRO_REGS_RETVAL(type, name) \ register type name asm("r0"); +UVISOR_FORCEINLINE void uvisor_noreturn(void) +{ + volatile int var = 1; + while(var); +} + /* declare callee-saved input/output operands for gcc-style inline asm */ /* note: this macro requires that a C variable having the same name of the * corresponding callee-saved register is declared; these operands follow diff --git a/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h b/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h index af94dd94fe5..a241c01a457 100644 --- a/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h +++ b/features/FEATURE_UVISOR/includes/uvisor/api/inc/vmpu_exports.h @@ -18,7 +18,6 @@ #define __UVISOR_API_VMPU_EXPORTS_H__ #include "api/inc/uvisor_exports.h" -#include "api/inc/pool_queue_exports.h" #include /* The maximum box namespace length is 37 so that it is exactly big enough for diff --git a/features/FEATURE_UVISOR/source/page_allocator.c_inc b/features/FEATURE_UVISOR/source/page_allocator.c_inc index 7957567ed2d..e432710432c 100644 --- a/features/FEATURE_UVISOR/source/page_allocator.c_inc +++ b/features/FEATURE_UVISOR/source/page_allocator.c_inc @@ -138,7 +138,7 @@ void page_allocator_init(void * const heap_start, void * const heap_end, const u g_page_map_shift -= (g_page_head_end_rounded - (uint32_t) g_page_heap_end) / g_page_size; DPRINTF( - "page heap: [0x%08x, 0x%08x] %ukB -> %u %ukB pages\r\n", + "page heap: [0x%08x, 0x%08x] %ukB -> %u %ukB pages\n", (unsigned int) g_page_heap_start, (unsigned int) g_page_heap_end, (unsigned int) (g_page_count_free * g_page_size / 1024), diff --git a/features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_ARM_BEETLE_SOC/TARGET_DEBUG/TARGET_M3/libconfiguration_beetle_cortex_m3_0x20000000_0x140.a b/features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_ARM_BEETLE_SOC/TARGET_DEBUG/TARGET_M3/libconfiguration_beetle_cortex_m3_0x20000000_0x140.a index 3c0db8ecc27..a0b184a689f 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a/features/FEATURE_UVISOR/uvisor-tests.txt b/features/FEATURE_UVISOR/uvisor-tests.txt index ed2bf8e0e43..241f957279e 100644 --- a/features/FEATURE_UVISOR/uvisor-tests.txt +++ b/features/FEATURE_UVISOR/uvisor-tests.txt @@ -1 +1 @@ -e3b1385c7facc7fdab472440293c4c87ed2b2999 +36664e60639dda2b364e6e8b5ecf9a23116d280a diff --git a/features/filesystem/bd/ChainingBlockDevice.cpp b/features/filesystem/bd/ChainingBlockDevice.cpp index 9dcfbae562a..f9f5c9a29f9 100644 --- a/features/filesystem/bd/ChainingBlockDevice.cpp +++ b/features/filesystem/bd/ChainingBlockDevice.cpp @@ -109,7 +109,7 @@ int ChainingBlockDevice::read(void *b, bd_addr_t addr, bd_size_t size) size -= read; } - addr -= size; + addr -= bdsize; } return 0; @@ -140,7 +140,7 @@ int ChainingBlockDevice::program(const void *b, bd_addr_t addr, bd_size_t size) size -= program; } - addr -= size; + addr -= bdsize; } return 0; @@ -169,7 +169,7 @@ int ChainingBlockDevice::erase(bd_addr_t addr, bd_size_t size) size -= erase; } - addr -= size; + addr -= bdsize; } return 0; diff --git a/features/filesystem/bd/HeapBlockDevice.h b/features/filesystem/bd/HeapBlockDevice.h index 1844bdddf38..afdaeef7440 100644 --- a/features/filesystem/bd/HeapBlockDevice.h +++ b/features/filesystem/bd/HeapBlockDevice.h @@ -34,13 +34,16 @@ * #include "mbed.h" * #include "HeapBlockDevice.h" * - * HeapBlockDevice bd(2048, 512); // 2048 bytes with a block size of 512 bytes - * uint8_t block[512] = "Hello World!\n"; + * #define BLOCK_SIZE 512 + * + * HeapBlockDevice bd(2048, BLOCK_SIZE); // 2048 bytes with a block size of 512 bytes + * uint8_t block[BLOCK_SIZE] = "Hello World!\n"; * * int main() { * bd.init(); - * bd.program(block, 0); - * bd.read(block, 0); + * bd.erase(0, BLOCK_SIZE); + * bd.program(block, 0, BLOCK_SIZE); + * bd.read(block, 0, BLOCK_SIZE); * printf("%s", block); * bd.deinit(); * } @@ -53,7 +56,8 @@ class HeapBlockDevice : public BlockDevice /** Lifetime of the memory block device * * @param size Size of the Block Device in bytes - * @param block Block size in bytes + * @param block Block size in bytes. Minimum read, program, and erase sizes are + * configured to this value */ HeapBlockDevice(bd_size_t size, bd_size_t block=512); /** Lifetime of the memory block device diff --git a/features/filesystem/bd/ProfilingBlockDevice.h b/features/filesystem/bd/ProfilingBlockDevice.h index 9bfa08d33c6..c019fa7300d 100644 --- a/features/filesystem/bd/ProfilingBlockDevice.h +++ b/features/filesystem/bd/ProfilingBlockDevice.h @@ -42,6 +42,7 @@ * printf("read count: %lld\n", profiler.get_read_count()); * printf("program count: %lld\n", profiler.get_program_count()); * printf("erase count: %lld\n", profiler.get_erase_count()); + * @endcode */ class ProfilingBlockDevice : public BlockDevice { diff --git a/features/filesystem/bd/SlicingBlockDevice.cpp b/features/filesystem/bd/SlicingBlockDevice.cpp index f7b3482d061..249acf81b69 100644 --- a/features/filesystem/bd/SlicingBlockDevice.cpp +++ b/features/filesystem/bd/SlicingBlockDevice.cpp @@ -17,17 +17,6 @@ #include "SlicingBlockDevice.h" -SlicingBlockDevice::SlicingBlockDevice(BlockDevice *bd, bd_addr_t start) - : _bd(bd) - , _start_from_end(false), _start(start) - , _stop_from_end(true), _stop(0) -{ - if ((int64_t)_start < 0) { - _start_from_end = true; - _start = -_start; - } -} - SlicingBlockDevice::SlicingBlockDevice(BlockDevice *bd, bd_addr_t start, bd_addr_t stop) : _bd(bd) , _start_from_end(false), _start(start) @@ -38,7 +27,7 @@ SlicingBlockDevice::SlicingBlockDevice(BlockDevice *bd, bd_addr_t start, bd_addr _start = -_start; } - if ((int64_t)_stop < 0) { + if ((int64_t)_stop <= 0) { _stop_from_end = true; _stop = -_stop; } diff --git a/features/filesystem/bd/SlicingBlockDevice.h b/features/filesystem/bd/SlicingBlockDevice.h index ed00b1fce54..e219f77480b 100644 --- a/features/filesystem/bd/SlicingBlockDevice.h +++ b/features/filesystem/bd/SlicingBlockDevice.h @@ -49,15 +49,6 @@ class SlicingBlockDevice : public BlockDevice { public: - /** Lifetime of the memory block device - * - * @param bd Block device to back the SlicingBlockDevice - * @param start Start block address to map to block 0, negative addresses - * are calculated from the end of the underlying block device - * @note This is the same as SlicingBlockDevice(bd, start, bd->size()) - */ - SlicingBlockDevice(BlockDevice *bd, bd_addr_t start); - /** Lifetime of the memory block device * * @param bd Block device to back the SlicingBlockDevice @@ -65,9 +56,10 @@ class SlicingBlockDevice : public BlockDevice * are calculated from the end of the underlying block device * @param end End block address to mark the end of the block device, * this block is not mapped, negative addresses are - * calculated from the end of the underlying block device + * calculated from the end of the underlying block device. + * The default stops at end of the underlying block device. */ - SlicingBlockDevice(BlockDevice *bd, bd_addr_t start, bd_addr_t end); + SlicingBlockDevice(BlockDevice *bd, bd_addr_t start, bd_addr_t end = 0); /** Lifetime of a block device */ diff --git a/features/filesystem/fat/FATFileSystem.cpp b/features/filesystem/fat/FATFileSystem.cpp index 1829bbda8e4..aa365efd15b 100644 --- a/features/filesystem/fat/FATFileSystem.cpp +++ b/features/filesystem/fat/FATFileSystem.cpp @@ -660,7 +660,24 @@ void FATFileSystem::dir_seek(fs_dir_t dir, off_t offset) { FATFS_DIR *dh = static_cast(dir); lock(); - dh->index = offset; + if (offset < dh->index) { + f_rewinddir(dh); + } + while (dh->index < offset) { + FILINFO finfo; + FRESULT res; +#if _USE_LFN + char lfname[NAME_MAX]; + finfo.lfname = lfname; + finfo.lfsize = NAME_MAX; +#endif // _USE_LFN + res = f_readdir(dh, &finfo); + if (res != FR_OK) { + break; + } else if (finfo.fname[0] == 0) { + break; + } + } unlock(); } @@ -678,7 +695,7 @@ void FATFileSystem::dir_rewind(fs_dir_t dir) { FATFS_DIR *dh = static_cast(dir); lock(); - dh->index = 0; + f_rewinddir(dh); unlock(); } diff --git a/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/mbedtls_device.h b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/mbedtls_device.h new file mode 100644 index 00000000000..dfbc82055ef --- /dev/null +++ b/features/mbedtls/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/mbedtls_device.h @@ -0,0 +1,31 @@ +/* + * mbedtls_device.h + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ +#ifndef MBEDTLS_DEVICE_H +#define MBEDTLS_DEVICE_H + +#define MBEDTLS_AES_ALT + +#define MBEDTLS_SHA256_ALT + +#define MBEDTLS_SHA1_ALT + +#define MBEDTLS_MD5_ALT + +#endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/aes_aes.c b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_aes.c new file mode 100644 index 00000000000..822c7e6f468 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_aes.c @@ -0,0 +1,466 @@ +/* + * Hardware-accelerated AES implementation for Silicon Labs devices + * containing an AES peripheral. + * + * Copyright 2017, Silicon Laboratories, Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "mbedtls/aes.h" +#include "em_device.h" + +#if defined(AES_PRESENT) && (AES_COUNT == 1) +#if defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_AES_ALT) +#include "em_aes.h" +#include "em_cmu.h" +#include "em_bus.h" +#include + +#if defined(MBEDTLS_THREADING_C) +#include "mbedtls/threading.h" +#include "em_core.h" +/* Mutex for protecting access to the AES instance */ +static mbedtls_threading_mutex_t aes_mutex; +static volatile bool aes_mutex_inited = false; +#endif + +static void aes_lock( void ) +{ +#if defined(MBEDTLS_THREADING_C) + if ( !aes_mutex_inited ) { + /* Turn off interrupts that can cause preemption */ + CORE_irqState_t critical_irq_state = CORE_EnterCritical(); + if ( !aes_mutex_inited ) { + mbedtls_mutex_init(&aes_mutex); + aes_mutex_inited = true; + } + CORE_ExitCritical(critical_irq_state); + } + mbedtls_mutex_lock(&aes_mutex); +#endif + BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_AES_SHIFT, 1); + return; +} + +static void aes_unlock( void ) +{ +#if defined(MBEDTLS_THREADING_C) + if ( aes_mutex_inited ) { + mbedtls_mutex_unlock(&aes_mutex); + } +#endif + BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_AES_SHIFT, 0); + return; +} + +/* + * Initialize AES context + */ +void mbedtls_aes_init( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) + return; + + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); +} + +/* + * Clear AES context + */ +void mbedtls_aes_free( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) + return; + + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); +} + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits ) +{ + if ( ( 128 != keybits ) && ( 256 != keybits ) ) + { + /* Unsupported key size */ + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + ctx->keybits = keybits; + memcpy( ctx->key, key, keybits/8 ); + + return 0; +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits ) +{ + if ( ( 128 != keybits ) && ( 256 != keybits ) ) + /* Unsupported key size */ + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + + ctx->keybits = keybits; + switch (keybits) + { + case 128: + aes_lock(); + AES_DecryptKey128( ctx->key, key ); + aes_unlock(); + break; + case 256: + aes_lock(); + AES_DecryptKey256( ctx->key, key ); + aes_unlock(); + break; + default: + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + return 0; +} + +/* + * AES-ECB block encryption + */ +int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, input, output); +} + +/* + * AES-ECB block decryption + */ +int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_DECRYPT, input, output); +} + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + switch ( ctx->keybits ) + { + case 128: + aes_lock(); + AES_ECB128( output, + input, + 16, + ctx->key, + mode == MBEDTLS_AES_ENCRYPT ? true : false ); + aes_unlock(); + break; + case 256: + aes_lock(); + AES_ECB256( output, + input, + 16, + ctx->key, + mode == MBEDTLS_AES_ENCRYPT ? true : false ); + aes_unlock(); + break; + default: + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + return( 0 ); +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + uint8_t tmpIv[16]; + + if( length % 16 ) + { + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( mode == MBEDTLS_AES_DECRYPT ) + { + if ( length >= 16 ) + memcpy( tmpIv, &input[length-16], 16 ); + } + + switch ( ctx->keybits ) + { + case 128: + aes_lock(); + AES_CBC128( output, + input, + length, + ctx->key, + iv, + mode == MBEDTLS_AES_ENCRYPT ? true : false ); + aes_unlock(); + break; + case 256: + aes_lock(); + AES_CBC256( output, + input, + length, + ctx->key, + iv, + mode == MBEDTLS_AES_ENCRYPT ? true : false ); + aes_unlock(); + break; + default: + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( length >= 16 ) + { + if ( mode == MBEDTLS_AES_ENCRYPT ) + memcpy( iv, &output[length-16], 16 ); + else + memcpy( iv, tmpIv, 16 ); + } + + return( 0 ); +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + size_t n = ( iv_off != NULL ) ? *iv_off : 0; + + if ( ( n > 0 ) || ( length & 0xf ) ) + { + // IV offset or length not aligned to block size + int c; + + if( mode == MBEDTLS_AES_DECRYPT ) + { + while( length-- ) + { + if( n == 0 ) + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + c = *input++; + *output++ = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + + n = ( n + 1 ) & 0x0F; + } + } + else + { + while( length-- ) + { + if( n == 0 ) + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + iv[n] = *output++ = (unsigned char)( iv[n] ^ *input++ ); + + n = ( n + 1 ) & 0x0F; + } + } + + if (iv_off) + { + *iv_off = n; + } + return( 0 ); + } + else + { + switch( ctx->keybits ) + { + case 128: + aes_lock(); + AES_CFB128(output, + input, + length, + ctx->key, + iv, + mode == MBEDTLS_AES_ENCRYPT ? true : false ); + aes_unlock(); + break; + + case 256: + aes_lock(); + AES_CFB256(output, + input, + length, + ctx->key, + iv, + mode == MBEDTLS_AES_ENCRYPT ? true : false ); + aes_unlock(); + break; + + default: + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + return( 0 ); + } +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + + while( length-- ) + { + memcpy( ov, iv, 16 ); + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ); + + if( mode == MBEDTLS_AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return( 0 ); +} +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR Nonce update function + */ +static void aes_ctr_update_nonce( uint8_t *nonce_counter ) +{ + for( size_t i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; +} + +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + size_t n = ( nc_off != NULL ) ? *nc_off : 0; + + if ( ( n > 0 ) || ( length & 0xf ) ) + { + // IV offset or length not aligned to block size + int c, i; + + while( length-- ) + { + if( n == 0 ) + { + mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block ); + + for( i = 16; i > 0; i-- ) + if( ++nonce_counter[i - 1] != 0 ) + break; + } + c = *input++; + *output++ = (unsigned char)( c ^ stream_block[n] ); + + n = ( n + 1 ) & 0x0F; + } + + if (nc_off) + { + *nc_off = n; + } + return( 0 ); + } + else + { + switch( ctx->keybits ) + { + case 128: + aes_lock(); + AES_CTR128( output, + input, + length, + ctx->key, + nonce_counter, + &aes_ctr_update_nonce ); + aes_unlock(); + break; + + case 256: + aes_lock(); + AES_CTR256( output, + input, + length, + ctx->key, + nonce_counter, + &aes_ctr_update_nonce ); + aes_unlock(); + break; + + default: + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + break; + } + + return( 0 ); + } +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#endif /* MBEDTLS_AES_ALT */ +#endif /* MBEDTLS_AES_C */ +#endif /* AES_PRESENT && (AES_COUNT == 1) */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/aes_alt.h b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_alt.h new file mode 100644 index 00000000000..6b18a334e64 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/aes_alt.h @@ -0,0 +1,318 @@ +/* + * AES block cipher + * + * Copyright (C) 2015-2017, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_AES_ALT_H +#define MBEDTLS_AES_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_aes AES block cipher + * \brief Hardware accelerated AES block cipher. + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_AES_ALT) +/* SiliconLabs CRYPTO hardware acceleration implementation */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief AES context structure + */ +typedef struct +{ + unsigned int keybits; /*!< size of key */ + unsigned char key[32]; /*!< AES key 128 or 256 bits */ +} +mbedtls_aes_context; + +/** + * \brief Initialize AES context + * + * \param ctx AES context to be initialized + */ +void mbedtls_aes_init( mbedtls_aes_context *ctx ); + +/** + * \brief Clear AES context + * + * \param ctx AES context to be cleared + */ +void mbedtls_aes_free( mbedtls_aes_context *ctx ); + +/** + * \brief AES key schedule (encryption) + * + * \param ctx AES context to be initialized + * \param key encryption key + * \param keybits must be 128 or 256 + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief AES key schedule (decryption) + * + * \param ctx AES context to be initialized + * \param key decryption key + * \param keybits must be 128 or 256 + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_KEY_LENGTH + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, const unsigned char *key, + unsigned int keybits ); + +/** + * \brief AES-ECB block encryption/decryption + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param input 16-byte input block + * \param output 16-byte output block + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ); + +#if defined(MBEDTLS_CIPHER_MODE_CBC) +/** + * \brief AES-CBC buffer encryption/decryption + * Length should be a multiple of the block + * size (16 bytes) + * + * \note Upon exit, the content of the IV is updated so that you can + * call the same function again on the following block(s) of + * data and get the same result as if it was encrypted in one + * call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful, or MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/** + * \brief AES-CFB128 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv_off offset in IV (updated after use) + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); + +/** + * \brief AES-CFB8 buffer encryption/decryption. + * + * Note: Due to the nature of CFB you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \note Upon exit, the content of the IV is updated so that you can + * call the function same function again on the following + * block(s) of data and get the same result as if it was + * encrypted in one call. This allows a "streaming" usage. + * If on the other hand you need to retain the contents of the + * IV, you should either save it manually or use the cipher + * module instead. + * + * \param ctx AES context + * \param mode MBEDTLS_AES_ENCRYPT or MBEDTLS_AES_DECRYPT + * \param length length of the input data + * \param iv initialization vector (updated after use) + * \param input buffer holding the input data + * \param output buffer holding the output data + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ); +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/** + * \brief AES-CTR buffer encryption/decryption + * + * Warning: You have to keep the maximum use of your counter in mind! + * + * Note: Due to the nature of CTR you should use the same key schedule for + * both encryption and decryption. So a context initialized with + * mbedtls_aes_setkey_enc() for both MBEDTLS_AES_ENCRYPT and MBEDTLS_AES_DECRYPT. + * + * \param ctx AES context + * \param length The length of the data + * \param nc_off The offset in the current stream_block (for resuming + * within current cipher stream). The offset pointer to + * should be 0 at the start of a stream. + * \param nonce_counter The 128-bit nonce and counter. + * \param stream_block The saved stream-block for resuming. Is overwritten + * by the function. + * \param input The input data stream + * \param output The output data stream + * + * \return 0 if successful + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ); +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_ENCRYPT_ALT) + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + * + * \return 0 if successful + */ +int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_DECRYPT_ALT) + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + * + * \return 0 if successful + */ +int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ); + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif +/** + * \brief Internal AES block encryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_ENCRYPT_ALT) + * + * \deprecated Superseded by mbedtls_aes_encrypt_ext() in 2.5.0 + * + * \param ctx AES context + * \param input Plaintext block + * \param output Output (ciphertext) block + */ +MBEDTLS_DEPRECATED static inline void mbedtls_aes_encrypt( + mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + mbedtls_internal_aes_encrypt( ctx, input, output ); +} + +/** + * \brief Internal AES block decryption function + * (Only exposed to allow overriding it, + * see MBEDTLS_AES_DECRYPT_ALT) + * + * \deprecated Superseded by mbedtls_aes_decrypt_ext() in 2.5.0 + * + * \param ctx AES context + * \param input Ciphertext block + * \param output Output (plaintext) block + */ +MBEDTLS_DEPRECATED static inline void mbedtls_aes_decrypt( + mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + mbedtls_internal_aes_decrypt( ctx, input, output ); +} + +#undef MBEDTLS_DEPRECATED +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_AES_ALT */ + +/** \} (end addtogroup sl_crypto_aes) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* MBEDTLS_AES_ALT_H */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_aes.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_aes.c new file mode 100644 index 00000000000..8b3c75aba58 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_aes.c @@ -0,0 +1,557 @@ +/* + * FIPS-197 compliant AES implementation + * + * Copyright (C) 2017, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file includes alternative plugin implementations of various + * functions in aes.c using the CRYPTO hardware accelerator incorporated + * in MCU devices from Silicon Laboratories. + */ + +/* + * The AES block cipher was designed by Vincent Rijmen and Joan Daemen. + * + * http://csrc.nist.gov/encryption/aes/rijndael/Rijndael.pdf + * http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf + */ + +#include "mbedtls/aes.h" +#include "em_device.h" + +#if defined(CRYPTO_PRESENT) +#if defined(MBEDTLS_AES_C) +#if defined(MBEDTLS_AES_ALT) + +#include "crypto_management.h" +#include "em_crypto.h" +#include "em_core.h" +#include + +__STATIC_INLINE void CRYPTO_DataReadUnaligned(volatile uint32_t * reg, + uint8_t * const val) +{ + /* Check data is 32bit aligned, if not, read into temporary buffer and + then move to user buffer. */ + if ((uint32_t)val & 0x3) + { + uint32_t temp[4]; + CRYPTO_DataRead(reg, temp); + memcpy(val, temp, 16); + } + else + { + CRYPTO_DataRead(reg, (uint32_t* const)val); + } +} + +__STATIC_INLINE void CRYPTO_DataWriteUnaligned(volatile uint32_t * reg, + uint8_t * const val) +{ + /* Check data is 32bit aligned, if not move to temporary buffer before + writing.*/ + if ((uint32_t)val & 0x3) + { + uint32_t temp[4]; + memcpy(temp, val, 16); + CRYPTO_DataWrite(reg, temp); + } + else + { + CRYPTO_DataWrite(reg, (uint32_t* const)val); + } +} + +/* + * Initialize AES context + */ +void mbedtls_aes_init( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) { + return; + } + + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); +} + +/* + * Clear AES context + */ +void mbedtls_aes_free( mbedtls_aes_context *ctx ) +{ + if( ctx == NULL ) { + return; + } + + memset( ctx, 0, sizeof( mbedtls_aes_context ) ); +} + +/* + * AES key schedule (encryption) + */ +int mbedtls_aes_setkey_enc( mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits ) +{ + if( ctx == NULL || key == NULL ) { + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ( 128UL != keybits ) && ( 256UL != keybits ) ) { + /* Unsupported key size */ + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + ctx->keybits = keybits; + memcpy(ctx->key, key, keybits/8); + + return 0; +} + +/* + * AES key schedule (decryption) + */ +int mbedtls_aes_setkey_dec( mbedtls_aes_context *ctx, + const unsigned char *key, + unsigned int keybits ) +{ + CORE_DECLARE_IRQ_STATE; + + if( ctx == NULL || key == NULL ) { + return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ( 128UL != keybits ) && ( 256UL != keybits ) ) { + /* Unsupported key size */ + return( MBEDTLS_ERR_AES_INVALID_KEY_LENGTH ); + } + + ctx->keybits = keybits; + + CRYPTO_TypeDef *device = crypto_management_acquire(); + device->WAC = 0; + device->CTRL = 0; + + CORE_ENTER_CRITICAL(); + CRYPTO_KeyBufWrite(device, (uint32_t*)key, (keybits == 128) ? cryptoKey128Bits : cryptoKey256Bits); + CORE_EXIT_CRITICAL(); + + /* Busy-wait here to allow context-switching to occur */ + device->CMD = CRYPTO_CMD_INSTR_AESENC; + while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0); + + CORE_ENTER_CRITICAL(); + CRYPTO_KeyRead(device, (uint32_t*)ctx->key, (keybits == 128) ? cryptoKey128Bits : cryptoKey256Bits); + CORE_EXIT_CRITICAL(); + + crypto_management_release(device); + + return 0; +} + +/* TODO: underneath these, we should swap out the em_crypto-provided library + * functions with in-place implemented functions, to get much shorter + * critical sections */ + +/* + * AES-ECB block encryption + */ +int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, input, output); +} + +/* + * AES-ECB block decryption + */ +int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, + const unsigned char input[16], + unsigned char output[16] ) +{ + return mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_DECRYPT, input, output); +} + +/* + * AES-ECB block encryption/decryption + */ +int mbedtls_aes_crypt_ecb( mbedtls_aes_context *ctx, + int mode, + const unsigned char input[16], + unsigned char output[16] ) +{ + int ret = 0; + CORE_DECLARE_IRQ_STATE; + + if( ctx == NULL || input == NULL || output == NULL ) { + return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ctx->keybits != 128UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + CRYPTO_TypeDef *device = crypto_management_acquire(); + device->WAC = 0; + device->CTRL = 0; + + CORE_ENTER_CRITICAL(); + CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits); + CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)input); + CORE_EXIT_CRITICAL(); + + if ( mode == MBEDTLS_AES_ENCRYPT ) { + device->CMD = CRYPTO_CMD_INSTR_AESENC; + } else { + device->CMD = CRYPTO_CMD_INSTR_AESDEC; + } + while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0); + + CORE_ENTER_CRITICAL(); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)output); + CORE_EXIT_CRITICAL(); + + crypto_management_release(device); + + return ret; +} + +#if defined(MBEDTLS_CIPHER_MODE_CBC) + +/* + * AES-CBC buffer encryption/decryption + */ +int mbedtls_aes_crypt_cbc( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + int ret = 0; + CORE_DECLARE_IRQ_STATE; + size_t processed = 0; + + if( ctx == NULL || input == NULL || output == NULL || iv == NULL ) { + return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + /* Input length must be a multiple of 16 bytes which is the AES block + length. */ + if( length & 0xf ) { + return( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ctx->keybits != 128UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + CRYPTO_TypeDef *device = crypto_management_acquire(); + device->WAC = 0; + device->CTRL = 0; + + CORE_ENTER_CRITICAL(); + CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits); + if ( mode == MBEDTLS_AES_ENCRYPT ) { + CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)iv); + } else { + CRYPTO_DataWriteUnaligned(&device->DATA2, (uint8_t *)iv); + } + CORE_EXIT_CRITICAL(); + + while ( processed < length ) { + if ( mode == MBEDTLS_AES_ENCRYPT ) { + CORE_ENTER_CRITICAL(); + CRYPTO_DataWriteUnaligned(&device->DATA0XOR, (uint8_t *)(&input[processed])); + device->CMD = CRYPTO_CMD_INSTR_AESENC; + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed])); + CORE_EXIT_CRITICAL(); + } else { + /* Decrypt input block, XOR IV to decrypted text, set ciphertext as next IV */ + CORE_ENTER_CRITICAL(); + CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)(&input[processed])); + CRYPTO_EXECUTE_4( device, + CRYPTO_CMD_INSTR_DATA0TODATA1, + CRYPTO_CMD_INSTR_AESDEC, + CRYPTO_CMD_INSTR_DATA2TODATA0XOR, + CRYPTO_CMD_INSTR_DATA1TODATA2); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed])); + CORE_EXIT_CRITICAL(); + } + processed += 16; + } + + if ( processed >= 16 ) { + if ( mode == MBEDTLS_AES_ENCRYPT ) { + memcpy(iv, &output[processed-16], 16); + } else { + CORE_ENTER_CRITICAL(); + CRYPTO_DataReadUnaligned(&device->DATA2, (uint8_t *)(iv)); + CORE_EXIT_CRITICAL(); + } + } + + crypto_management_release(device); + + return ret; +} +#endif /* MBEDTLS_CIPHER_MODE_CBC */ + +#if defined(MBEDTLS_CIPHER_MODE_CFB) +/* + * AES-CFB128 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb128( mbedtls_aes_context *ctx, + int mode, + size_t length, + size_t *iv_off, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + size_t n = iv_off ? *iv_off : 0; + size_t processed = 0; + int ret = 0; + CORE_DECLARE_IRQ_STATE; + + if( ctx == NULL || input == NULL || output == NULL || iv == NULL ) { + return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ctx->keybits != 128UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + if( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)( iv[n] ^ input[processed] ); + } else { + int c = input[processed]; + output[processed] = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + n = ( n + 1 ) & 0x0F; + processed++; + continue; + } else { + /* process one ore more blocks of data */ + CRYPTO_TypeDef *device = crypto_management_acquire(); + device->WAC = 0; + device->CTRL = 0; + + CORE_ENTER_CRITICAL(); + CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits); + CRYPTO_DataWriteUnaligned(&device->DATA0, (uint8_t *)iv); + CORE_EXIT_CRITICAL(); + + /* Encryption: encrypt IV, encIV xor input -> output and IV */ + /* Decryption: encrypt IV, encIV xor input -> output, input -> IV */ + size_t iterations = (length - processed) / 16; + for (size_t i = 0; i < iterations; i++ ) { + device->CMD = CRYPTO_CMD_INSTR_AESENC; + while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0); + + CORE_ENTER_CRITICAL(); + if ( mode == MBEDTLS_AES_ENCRYPT ) { + CRYPTO_DataWriteUnaligned(&device->DATA0XOR, (uint8_t *)(&input[processed])); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed])); + } else { + CRYPTO_DataWriteUnaligned(&device->DATA1, (uint8_t *)(&input[processed])); + device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0XOR; + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed])); + device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0; + } + CORE_EXIT_CRITICAL(); + processed += 16; + } + + CORE_ENTER_CRITICAL(); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)iv); + CORE_EXIT_CRITICAL(); + + while ( length - processed > 0 ) { + if ( n == 0 ) { + device->CMD = CRYPTO_CMD_INSTR_AESENC; + while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0); + CORE_ENTER_CRITICAL(); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)iv); + CORE_EXIT_CRITICAL(); + } + /* Save remainder to iv */ + if( mode == MBEDTLS_AES_ENCRYPT ) { + iv[n] = output[processed] = (unsigned char)( iv[n] ^ input[processed] ); + } else { + int c = input[processed]; + output[processed] = (unsigned char)( c ^ iv[n] ); + iv[n] = (unsigned char) c; + } + n = ( n + 1 ) & 0x0F; + processed++; + } + + crypto_management_release(device); + } + } + + if ( iv_off ) { + *iv_off = n; + } + + return ret; +} + +/* + * AES-CFB8 buffer encryption/decryption + */ +int mbedtls_aes_crypt_cfb8( mbedtls_aes_context *ctx, + int mode, + size_t length, + unsigned char iv[16], + const unsigned char *input, + unsigned char *output ) +{ + unsigned char c; + unsigned char ov[17]; + int ret = 0; + + if( ctx == NULL || input == NULL || output == NULL || iv == NULL ) { + return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ctx->keybits != 128UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + while( length-- ) + { + memcpy( ov, iv, 16 ); + if ( (ret = mbedtls_aes_crypt_ecb( ctx, MBEDTLS_AES_ENCRYPT, iv, iv ) ) != 0 ) { + return ret; + } + + if( mode == MBEDTLS_AES_DECRYPT ) + ov[16] = *input; + + c = *output++ = (unsigned char)( iv[0] ^ *input++ ); + + if( mode == MBEDTLS_AES_ENCRYPT ) + ov[16] = c; + + memcpy( iv, ov + 1, 16 ); + } + + return ret; +} +#endif /*MBEDTLS_CIPHER_MODE_CFB */ + +#if defined(MBEDTLS_CIPHER_MODE_CTR) +/* + * AES-CTR buffer encryption/decryption + */ +int mbedtls_aes_crypt_ctr( mbedtls_aes_context *ctx, + size_t length, + size_t *nc_off, + unsigned char nonce_counter[16], + unsigned char stream_block[16], + const unsigned char *input, + unsigned char *output ) +{ + size_t n = nc_off ? *nc_off : 0; + size_t processed = 0; + int ret = 0; + CORE_DECLARE_IRQ_STATE; + + if( ctx == NULL || input == NULL || output == NULL || nonce_counter == NULL || stream_block == NULL ) { + return ( MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH ); + } + + if ( ctx->keybits != 128UL && ctx->keybits != 256UL) { + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + while ( processed < length ) { + if ( n > 0 ) { + /* start by filling up the IV */ + output[processed] = (unsigned char)( input[processed] ^ stream_block[n] ); + n = ( n + 1 ) & 0x0F; + processed++; + continue; + } else { + /* process one ore more blocks of data */ + CRYPTO_TypeDef *device = crypto_management_acquire(); + device->WAC = 0; + device->CTRL = CRYPTO_CTRL_INCWIDTH_INCWIDTH4; + + CORE_ENTER_CRITICAL(); + CRYPTO_KeyBufWrite(device, (uint32_t*)ctx->key, (ctx->keybits == 128UL) ? cryptoKey128Bits : cryptoKey256Bits); + CRYPTO_DataWriteUnaligned(&device->DATA1, (uint8_t *)nonce_counter); + CORE_EXIT_CRITICAL(); + + /* strategy: encrypt nonce, encNonce xor input -> output, inc(nonce) */ + size_t iterations = (length - processed) / 16; + for (size_t i = 0; i < iterations; i++ ) { + device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0; + device->CMD = CRYPTO_CMD_INSTR_AESENC; + while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0); + device->CMD = CRYPTO_CMD_INSTR_DATA1INC; + + CORE_ENTER_CRITICAL(); + CRYPTO_DataWriteUnaligned(&device->DATA0XOR, (uint8_t *)(&input[processed])); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)(&output[processed])); + CORE_EXIT_CRITICAL(); + processed += 16; + } + + while ( length - processed > 0 ) { + if ( n == 0 ) { + device->CMD = CRYPTO_CMD_INSTR_DATA1TODATA0; + device->CMD = CRYPTO_CMD_INSTR_AESENC; + while ((device->STATUS & CRYPTO_STATUS_INSTRRUNNING) != 0); + device->CMD = CRYPTO_CMD_INSTR_DATA1INC; + + CORE_ENTER_CRITICAL(); + CRYPTO_DataReadUnaligned(&device->DATA0, (uint8_t *)stream_block); + CORE_EXIT_CRITICAL(); + } + /* Save remainder to iv */ + output[processed] = (unsigned char)( input[processed] ^ stream_block[n] ); + n = ( n + 1 ) & 0x0F; + processed++; + } + + CORE_ENTER_CRITICAL(); + CRYPTO_DataReadUnaligned(&device->DATA1, (uint8_t *)nonce_counter); + CORE_EXIT_CRITICAL(); + + crypto_management_release(device); + } + } + + if ( nc_off ) { + *nc_off = n; + } + + return ret; +} +#endif /* MBEDTLS_CIPHER_MODE_CTR */ + +#endif /* MBEDTLS_AES_ALT */ +#endif /* MBEDTLS_AES_C */ +#endif /* CRYPTO_PRESENT */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_ecp.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_ecp.c new file mode 100644 index 00000000000..48fe271e8fc --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_ecp.c @@ -0,0 +1,1725 @@ +/* + * Elliptic curves over GF(p): CRYPTO hw acceleration functions + * + * Copyright (C) 2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file includes alternative plugin implementations of various + * functions in ecp.c using the CRYPTO hardware accelerator incorporated + * in MCU devices from Silicon Laboratories. + */ +/* + * References: + * + * SEC1 http://www.secg.org/index.php?action=secg,docs_secg + * GECC = Guide to Elliptic Curve Cryptography - Hankerson, Menezes, Vanstone + * FIPS 186-3 http://csrc.nist.gov/publications/fips/fips186-3/fips_186-3.pdf + * RFC 4492 for the related TLS structures and constants + * + * [Curve25519] http://cr.yp.to/ecdh/curve25519-20060209.pdf + * + * [2] CORON, Jean-S'ebastien. Resistance against differential power analysis + * for elliptic curve cryptosystems. In : Cryptographic Hardware and + * Embedded Systems. Springer Berlin Heidelberg, 1999. p. 292-302. + * + * + * [3] HEDABOU, Mustapha, PINEL, Pierre, et B'EN'ETEAU, Lucien. A comb method to + * render ECC resistant against Side Channel Attacks. IACR Cryptology + * ePrint Archive, 2004, vol. 2004, p. 342. + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "em_device.h" + +#if defined( CRYPTO_PRESENT ) + +#if defined( MBEDTLS_ECP_C ) +#if defined( MBEDTLS_ECP_INTERNAL_ALT ) + +#include "mbedtls/ecp.h" +#include "mbedtls/ecp_internal.h" +#include "mbedtls/platform.h" +#include "em_crypto.h" +#include "em_core.h" +#include "crypto_management.h" + +#include +#include + +/** ECC big integer type. */ +#define ECC_BIGINT_SIZE_IN_BITS (256) +#define ECC_BIGINT_SIZE_IN_BYTES (ECC_BIGINT_SIZE_IN_BITS/8) +#define ECC_BIGINT_SIZE_IN_32BIT_WORDS (ECC_BIGINT_SIZE_IN_BYTES/sizeof(uint32_t)) +#define EC_BIGINT_COPY(X, Y) memcpy((X), (Y), sizeof(ecc_bigint_t)); +typedef uint32_t ecc_bigint_t[ECC_BIGINT_SIZE_IN_32BIT_WORDS]; + +#define SLCL_ECP_CHK(f) do { if( ( ret = (f) ) != 0 ) goto cleanup; } while( 0 ) + +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) || defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) +#define MPI_TO_BIGINT(bigint, mpi) mpitobigint((bigint), (mpi)); + +/***************************************************************************//** + * @brief + * Convert an mpi number representation to a 32bit word array used by crypto. + ******************************************************************************/ +__STATIC_INLINE void mpitobigint( ecc_bigint_t bigint, const mbedtls_mpi* mpi ) +{ + uint32_t* bi = bigint; + + if ( mpi->n < ECC_BIGINT_SIZE_IN_32BIT_WORDS ) + { + memcpy(bigint, mpi->p, mpi->n * sizeof(uint32_t)); + memset(&bi[mpi->n], + 0, + ECC_BIGINT_SIZE_IN_BYTES - ( mpi->n * sizeof(uint32_t) ) ); + } + else + { + /* mpi has more room than bigint, so only store up to sizeof(bigint) */ + memcpy(bigint, mpi->p, ECC_BIGINT_SIZE_IN_BYTES); + } +} + +/***************************************************************************//** + * @brief + * Returns true if the value of the DDATA0 register is equal to zero. + ******************************************************************************/ +__STATIC_INLINE bool crypto_ddata0_is_zero(CRYPTO_TypeDef* crypto, + uint32_t* status_reg) +{ + CORE_DECLARE_IRQ_STATE; + CORE_ENTER_CRITICAL(); + CRYPTO_EXECUTE_3(crypto, + CRYPTO_CMD_INSTR_CCLR, + CRYPTO_CMD_INSTR_DEC, /* Decrement by one which will set + carry bit if DDATA0 is zero. */ + CRYPTO_CMD_INSTR_INC /* Increment in order to restore + original value. */ + ); + + *status_reg = crypto->DSTATUS; + CORE_EXIT_CRITICAL(); + + return (*status_reg & CRYPTO_DSTATUS_CARRY) == CRYPTO_DSTATUS_CARRY; +} + +/***************************************************************************//** + * @brief + * Modular division using CRYPTO hardware acceleration. + * + * @details + * This function computes R = X/Y mod(N) using CRYPTO hardware acceleration. + * The implementation is not a direct replacement plugin, i.e. alternative + * implementation, of an existing mbedtls function. This function is used + * internally in other CRYPTO plugin functions indirectly replacing + * mbedtls_mpi_inv_mod. + * + * @param[in] X Dividend of modular division operation + * @param[in] Y Divisor of modular division operation + * @param[in] N Modulus + * @param[out] R The destination of the result + * + * @return N/A + ******************************************************************************/ +static void crypto_mpi_div_mod(CRYPTO_TypeDef *crypto, + ecc_bigint_t X, + ecc_bigint_t Y, + ecc_bigint_t N, + ecc_bigint_t R) +{ + uint32_t D[9]; + uint32_t status_reg; + uint8_t rdata; + uint8_t lsb_C; + uint8_t lsb_D; + uint8_t lsb_U; + int t; + int k; + CORE_DECLARE_IRQ_STATE; + + /************** Initialize and organize data in crypto module **************/ + + /* + ** Register usage: + ** + ** DDATA0 - holds temporary results and loads 260 bit variables in/out + ** DDATA1 - variable referred to as 'C' in the following algorithm + ** DDATA2 - variable referred to as 'U' in the following algorithm + ** DDATA3 - variable referred to as 'D' in the following algorithm + ** DDATA4 - variable referred to as 'W' in the following algorithm + */ + + EC_BIGINT_COPY(D, N); /* D will hold the modulus (n) initially */ + D[8]=0; /* Set MSWord of D to 0. */ + + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA1, Y); /* Set C to Y (divisor) initially */ + CRYPTO_DDataWrite(&crypto->DDATA2, X); /* Set U to X (dividend)initially */ + CRYPTO_DDataWrite(&crypto->DDATA3, N); /* Set D to modulus p initially */ + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_3(crypto, + CRYPTO_CMD_INSTR_CLR, /* DDATA0 = 0 */ + CRYPTO_CMD_INSTR_DDATA0TODDATA4, /* Set W to zero initially*/ + CRYPTO_CMD_INSTR_DDATA1TODDATA0);/* DDATA0 = C initially */ + + t = 0; + k = 1; + + /******************* Run main loop while 'C' is non-zero ********************/ + + /* while (C != 1024'd0) */ + while ( !crypto_ddata0_is_zero(crypto, &status_reg) ) + { + + lsb_C = (status_reg & _CRYPTO_DSTATUS_DDATA0LSBS_MASK) >> _CRYPTO_DSTATUS_DDATA0LSBS_SHIFT; + if ((lsb_C & 0x1) == 0) + { + CRYPTO_EXECUTE_3(crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA1, + CRYPTO_CMD_INSTR_SHRA, + CRYPTO_CMD_INSTR_DDATA0TODDATA1 + ); + t = t-1; + } + else + { + if (t<0) + { + CRYPTO_EXECUTE_6(crypto, + CRYPTO_CMD_INSTR_DDATA2TODDATA0, + CRYPTO_CMD_INSTR_DDATA4TODDATA2, + CRYPTO_CMD_INSTR_DDATA0TODDATA4, + CRYPTO_CMD_INSTR_DDATA1TODDATA0, + CRYPTO_CMD_INSTR_DDATA3TODDATA1, + CRYPTO_CMD_INSTR_DDATA0TODDATA3); + CORE_ENTER_CRITICAL(); + CRYPTO_DDATA0_260_BITS_READ(crypto, D); + CORE_EXIT_CRITICAL(); + t = -t; + } + + k = 1; + + CRYPTO_EXECUTE_2(crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_ADD); + + rdata = CRYPTO_DData0_4LSBitsRead(crypto); + + if((rdata & 0x3) != 0x0) + k = -1; + else + t = t-1; + + /* R1 = C >> 1 */ + crypto->CMD = CRYPTO_CMD_INSTR_DDATA1TODDATA0; /* to get the lsb of C */ + + lsb_C = CRYPTO_DData0_4LSBitsRead(crypto); + CRYPTO_EXECUTE_4(crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA1, + CRYPTO_CMD_INSTR_SHRA, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_DDATA3TODDATA0); /* to get the lsb of D(R3) */ + + /* R3 = D >> 1 */ + lsb_D = CRYPTO_DData0_4LSBitsRead(crypto); + + CRYPTO_EXECUTE_2(crypto, + CRYPTO_CMD_INSTR_SELDDATA3DDATA3, + CRYPTO_CMD_INSTR_SHRA); + + if(k == 1) + { + if (((lsb_C & 0x1)==0x1) && ((lsb_D & 0x1)==0x1)) + { + CRYPTO_EXECUTE_7(crypto, + /* C = R1+R3+1 */ + CRYPTO_CMD_INSTR_SELDDATA0DDATA1, + CRYPTO_CMD_INSTR_CSET, + CRYPTO_CMD_INSTR_ADDC, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + /* U = mod(R2+R4,n) */ + CRYPTO_CMD_INSTR_SELDDATA2DDATA4, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA2 + ); + } + else + { + CRYPTO_EXECUTE_6(crypto, + /* C = R1+R3 */ + CRYPTO_CMD_INSTR_SELDDATA0DDATA1, + CRYPTO_CMD_INSTR_ADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + /* U = mod(R2+R4,n) */ + CRYPTO_CMD_INSTR_SELDDATA2DDATA4, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA2 + ); + } + } + else + { + if (k == -1) + { + if (((lsb_C & 0x1)==0x0) && ((lsb_D & 0x1)==0x1)) + { + CRYPTO_EXECUTE_8(crypto, + /* C = R1-R3-1 */ + CRYPTO_CMD_INSTR_DDATA0TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_CSET, + CRYPTO_CMD_INSTR_SUBC, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + /* U = mod(R2-R4,p) */ + CRYPTO_CMD_INSTR_SELDDATA2DDATA4, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA2 + ); + } + else + { + CRYPTO_EXECUTE_7(crypto, + /* C = R1+R3 */ + CRYPTO_CMD_INSTR_DDATA0TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_SUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + /* U = mod(R2-R4,p) */ + CRYPTO_CMD_INSTR_SELDDATA2DDATA4, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA2 + ); + } + + CRYPTO_DDATA0_260_BITS_WRITE(crypto, D); + crypto->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA3; + + } /* if (k == -1) */ + } + } /* else: !if((C[31:0] & 0x1) == 0x0) */ + + crypto->CMD = CRYPTO_CMD_INSTR_DDATA2TODDATA0; + + lsb_U = CRYPTO_DData0_4LSBitsRead(crypto); + + /* if ((U[31:0] & 0x1) == 0x1) */ + if((lsb_U & 0x1) == 0x1) + { + CRYPTO_EXECUTE_3( crypto, + CRYPTO_CMD_INSTR_SELDDATA2DDATA2, + CRYPTO_CMD_INSTR_SHRA, + CRYPTO_CMD_INSTR_DDATA0TODDATA2); + + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA0, N); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_6( crypto, + CRYPTO_CMD_INSTR_SELDDATA0DDATA0, + CRYPTO_CMD_INSTR_SHR, + CRYPTO_CMD_INSTR_SELDDATA0DDATA2, + CRYPTO_CMD_INSTR_CSET, + CRYPTO_CMD_INSTR_ADDC, + CRYPTO_CMD_INSTR_DDATA0TODDATA2); + } + else + { + CRYPTO_EXECUTE_3(crypto, + CRYPTO_CMD_INSTR_SELDDATA2DDATA2, + CRYPTO_CMD_INSTR_SHRA, + CRYPTO_CMD_INSTR_DDATA0TODDATA2); + } + + /* DDATA0 = C */ + crypto->CMD = CRYPTO_CMD_INSTR_DDATA1TODDATA0; + + } /* End of main loop: while (C != 0) */ + + /* if (D == 1): */ + /* Decrement D by 1 and test if zero. */ + CRYPTO_EXECUTE_2(crypto, + CRYPTO_CMD_INSTR_DDATA3TODDATA0, + CRYPTO_CMD_INSTR_DEC); + + if (crypto_ddata0_is_zero(crypto, &status_reg)) + { + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead(&crypto->DDATA4, R); + CORE_EXIT_CRITICAL(); + } + else + { + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA0, N); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_2(crypto, + CRYPTO_CMD_INSTR_SELDDATA0DDATA4, + CRYPTO_CMD_INSTR_SUB + ); + + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead(&crypto->DDATA0, R); + CORE_EXIT_CRITICAL(); + } + return; +} /* crypto_mpi_div_mod */ +#endif /* MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT || MBEDTLS_ECP_NORMALIZE_JAC_ALT */ + +/***************************************************************************//** + * @brief + * Enable CRYPTO by setting up control registers for given ecc curve. + ******************************************************************************/ +static int crypto_device_init( CRYPTO_TypeDef *device, const mbedtls_ecp_group *grp) +{ + int ret = 0; + + /* Setup CRYPTO registers for ECC operation */ + device->CTRL = 0; + device->SEQCTRL = CRYPTO_SEQCTRL_BLOCKSIZE_32BYTES | 32; + device->SEQCTRLB = 0; + + switch( grp->id ) + { +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + case MBEDTLS_ECP_DP_SECP192R1: + CRYPTO_ModulusSet( device, cryptoModulusEccP192 ); + CRYPTO_MulOperandWidthSet( device, cryptoMulOperandModulusBits ); + CRYPTO_ResultWidthSet( device, cryptoResult256Bits ); + break; +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + case MBEDTLS_ECP_DP_SECP224R1: + CRYPTO_ModulusSet( device, cryptoModulusEccP224 ); + CRYPTO_MulOperandWidthSet( device, cryptoMulOperandModulusBits ); + CRYPTO_ResultWidthSet( device, cryptoResult256Bits ); + break; +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + case MBEDTLS_ECP_DP_SECP256R1: + CRYPTO_ModulusSet( device, cryptoModulusEccP256 ); + CRYPTO_MulOperandWidthSet( device, cryptoMulOperandModulusBits ); + CRYPTO_ResultWidthSet( device, cryptoResult260Bits ); + break; +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + + default: + ret = MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE; + break; + } + + return( ret ); +} + +/***************************************************************************//** + * @brief + * Write 256 bits of data to a DDATAX register in the CRYPTO module. + * + * @details + * Write 256 bits of data into a DDATAX (Double Data) register in the crypto + * module. + * + * @param[in] ddataReg Data register identifier + * @param[in] val Value of the data to write to the DDATA register. + ******************************************************************************/ +__STATIC_INLINE void ecp_crypto_ddata_write(CRYPTO_DDataReg_TypeDef ddataReg, + const mbedtls_mpi* mpi) +{ + uint32_t volatile* regPtr = (volatile uint32_t *) ddataReg; + uint32_t* pVal = mpi->p; + register uint32_t v0; + register uint32_t v1; + register uint32_t v2; + register uint32_t v3; + int i; + + if (mpi->n <4) + { + /* Non optimal write of data. */ + for (i=0; i<(int)mpi->n; i++) + *regPtr = *pVal++; + for (; i<8; i++) + *regPtr = 0; + } + else + { + if (mpi->n < 8) + { + /* Optimal write of first 4 words. */ + v0 = *pVal++; + v1 = *pVal++; + v2 = *pVal++; + v3 = *pVal++; + *regPtr = v0; + *regPtr = v1; + *regPtr = v2; + *regPtr = v3; + + /* Non optimal write of remaining words */ + for (i=4; i<(int)mpi->n; i++) + *regPtr = *pVal++; + for (; i<8; i++) + *regPtr = 0; + } + else + { + /* Optimal write of all data. */ + v0 = *pVal++; + v1 = *pVal++; + v2 = *pVal++; + v3 = *pVal++; + *regPtr = v0; + *regPtr = v1; + *regPtr = v2; + *regPtr = v3; + + v0 = *pVal++; + v1 = *pVal++; + v2 = *pVal++; + v3 = *pVal++; + *regPtr = v0; + *regPtr = v1; + *regPtr = v2; + *regPtr = v3; + } + } +} + +/***************************************************************************//** + * @brief + * Read 256 bits of data from a DDATAX register in the CRYPTO module. + * + * @details + * Read 256 bits of data from a DDATAX (Double Data) register in the crypto + * module. + * + * @param[in] ddataReg Data register identifier + * @param[out] val Location where to store the value in memory. + ******************************************************************************/ + +__STATIC_INLINE int ecp_crypto_ddata_read(CRYPTO_DDataReg_TypeDef ddataReg, + mbedtls_mpi* mpi) +{ + CRYPTO_DData_TypeDef ddata; + uint32_t val32; + int i; + int used; + int ret = 0; + CORE_DECLARE_IRQ_STATE; + + if (mpi->n == 8) + { + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead(ddataReg, mpi->p); + CORE_EXIT_CRITICAL(); + } + else + { + if (mpi->n > 8) + { + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead(ddataReg, mpi->p); + CORE_EXIT_CRITICAL(); + memset(&mpi->p[8], 0, sizeof(uint32_t)*(mpi->n-8)); + } + else + { + uint32_t volatile* regPtr = (volatile uint32_t*) ddataReg; + used = 0; + for (i=0; i<8; i++) + { + ddata[i] = val32 = *regPtr; + if (val32) + used = i+1; + } + if (used > (int)mpi->n) + { + SLCL_ECP_CHK( mbedtls_mpi_grow(mpi, used) ); + memcpy(mpi->p, ddata, used*sizeof(uint32_t)); + mpi->s = 1; + } + else + { + memcpy(mpi->p, ddata, mpi->n*sizeof(uint32_t)); + } + } + } + cleanup: + return( ret ); +} + +/** + * \brief Indicate if the Elliptic Curve Point module extension can + * handle the group. + * + * \param grp The pointer to the elliptic curve group that will be the + * basis of the cryptographic computations. + * + * \return Non-zero if successful. + */ +unsigned char mbedtls_internal_ecp_grp_capable( const mbedtls_ecp_group *grp ) +{ + switch( grp->id ) + { +#if defined(MBEDTLS_ECP_DP_SECP192R1_ENABLED) + case MBEDTLS_ECP_DP_SECP192R1: + return( true ); +#endif /* MBEDTLS_ECP_DP_SECP192R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP224R1_ENABLED) + case MBEDTLS_ECP_DP_SECP224R1: + return( true ); +#endif /* MBEDTLS_ECP_DP_SECP224R1_ENABLED */ + +#if defined(MBEDTLS_ECP_DP_SECP256R1_ENABLED) + case MBEDTLS_ECP_DP_SECP256R1: + return( true ); +#endif /* MBEDTLS_ECP_DP_SECP256R1_ENABLED */ + + default: + return( false ); + } +} + +/** + * \brief Initialise the Elliptic Curve Point module extension. + * + * If mbedtls_internal_ecp_grp_capable returns true for a + * group, this function has to be able to initialise the + * module for it. + * + * This module can be a driver to a crypto hardware + * accelerator, for which this could be an initialise function. + * + * \param grp The pointer to the group the module needs to be + * initialised for. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) +{ + /* Crypto operations are atomic, so no need to setup any context here */ + (void) grp; + return 0; +} + +/** + * \brief Frees and deallocates the Elliptic Curve Point module + * extension. + * + * \param grp The pointer to the group the module was initialised for. + */ +void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) +{ + /* Crypto operations are atomic, so no need to free any context here */ + (void) grp; +} + +#if defined(MBEDTLS_ECP_RANDOMIZE_JAC_ALT) +/** + * \brief Randomize jacobian coordinates: + * (X, Y, Z) -> (l^2 X, l^3 Y, l Z) for random l. + * + * \param grp Pointer to the group representing the curve. + * + * \param pt The point on the curve to be randomised, given with Jacobian + * coordinates. + * + * \param f_rng A function pointer to the random number generator. + * + * \param p_rng A pointer to the random number generator state. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_randomize_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng ) +{ + int ret; + ecc_bigint_t l; + CORE_DECLARE_IRQ_STATE; + CRYPTO_TypeDef *crypto; + + /* Strategy: + * 1) Generate l such that 1 < l < p + * 2) Z = l (R1) * Z (R4) + * 3) ll (R1) = l (R4) * l + * 4) X = ll (R1) * X (R2) + * 5) lll (R1) = ll (R1) * l (R4) + * 6) Y = lll (R1) * Y (R3) + */ + + /* Acquire entropy before grabbing crypto, since the entropy function might use crypto */ + /* Generate l such that 1 < l < p */ + ret = f_rng(p_rng, (unsigned char *)l, sizeof(l)); + if ( ret != 0 ) { + return( ret ); + } + + crypto = crypto_management_acquire(); + crypto_device_init(crypto, grp); + + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA1, l); + ecp_crypto_ddata_write(&crypto->DDATA2, &pt->X); + ecp_crypto_ddata_write(&crypto->DDATA3, &pt->Y); + ecp_crypto_ddata_write(&crypto->DDATA4, &pt->Z); + CORE_EXIT_CRITICAL(); + + /* Z = l * Z */ + CRYPTO_EXECUTE_2 ( crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL ); + CRYPTO_InstructionSequenceWait(crypto); + + MBEDTLS_MPI_CHK( ecp_crypto_ddata_read(&crypto->DDATA0, &pt->Z) ); + + /* X = l^2 * X */ + CRYPTO_EXECUTE_6 ( crypto, + CRYPTO_CMD_INSTR_DDATA1TODDATA4, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL ); + CRYPTO_InstructionSequenceWait(crypto); + + MBEDTLS_MPI_CHK( ecp_crypto_ddata_read(&crypto->DDATA0, &pt->X) ); + + /* Y = l^3 * Y */ + CRYPTO_EXECUTE_5 ( crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL ); + CRYPTO_InstructionSequenceWait(crypto); + + MBEDTLS_MPI_CHK( ecp_crypto_ddata_read(&crypto->DDATA0, &pt->Y) ); + +cleanup: + crypto_management_release( crypto ); + return( ret ); +} +#endif + +#if defined(MBEDTLS_ECP_ADD_MIXED_ALT) +/** + * \brief Addition: R = P + Q, mixed affine-Jacobian coordinates. + * + * The coordinates of Q must be normalized (= affine), + * but those of P don't need to. R is not normalized. + * + * This function is used only as a subrutine of + * ecp_mul_comb(). + * + * Special cases: (1) P or Q is zero, (2) R is zero, + * (3) P == Q. + * None of these cases can happen as intermediate step in + * ecp_mul_comb(): + * - at each step, P, Q and R are multiples of the base + * point, the factor being less than its order, so none of + * them is zero; + * - Q is an odd multiple of the base point, P an even + * multiple, due to the choice of precomputed points in the + * modified comb method. + * So branches for these cases do not leak secret information. + * + * We accept Q->Z being unset (saving memory in tables) as + * meaning 1. + * + * Cost in field operations if done by [5] 3.22: + * 1A := 8M + 3S + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the first summand, given with Jacobian + * coordinates + * + * \param Q Pointer to the second summand, given with affine + * coordinates. + * + * \return 0 if successful. + */ +int mbedtls_internal_ecp_add_mixed( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_ecp_point *P, + const mbedtls_ecp_point *Q ) +{ + int ret; + CORE_DECLARE_IRQ_STATE; + CRYPTO_TypeDef *crypto = crypto_management_acquire(); + + crypto_device_init(crypto, grp); + + /* + STEP 1: + + Goals: + A = Qx*Pz^2 + B = Qy*Pz^3 + + Write Operations: + + R0 = Pz + R0 = Qx + R0 = Qy + + Instructions to be executed: + + 1. R0 = DMA = Pz + 2. R1 = R0 = Pz + 3. R2 = R0 = Pz + 4. Select R1, R2 + 5. R0 = R1 * R2 = Pz^2 + 6. R1 = R0 = Pz^2 + + 7. R0 = DMA = Qx + 8. R3 = R0 = Qx + 9. Select R1, R3 + 10. R0 = R1 * R3 = Qx * Pz^2 + 11. R3 = R0 = Qx * Pz^2 + + 12. Select R1, R2 + 13. R0 = R1 * R2 = Pz^3 + 14. R1 = R0 = Pz^3 + + 15. R0 = DMA = Qy + 16. R4 = R0 = Qx + 17. Select R1, R4 + 18. R0 = R1 * R4 = Qy * Pz^3 + 19. Select R0, R1 (for MSUB in step 2) + + Output State: + R0 = B + R1 = FREE + R2 = FREE + R3 = A + R4 = Pz + + STEP 1: + */ + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &P->Z); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_5(crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_DDATA0TODDATA4, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA1); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &Q->X); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_4 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA3); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA1); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &Q->Y); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL + ); + CRYPTO_InstructionSequenceWait(crypto); + + /* + STEP 2: + + Goals: + C = A - Px + D = B - Py + R->Z = Pz * C + + Write Operations: + + R1 = Py + R0 = Px (via DMA) + + Input State: + R0 = B + R1 = Py + R2 = FREE + R3 = A + R4 = Pz + + Instructions to be executed: + + 0. Select R0, R1 + 1. R0 = R0 - R1 = B - Py = D + 2. R2 = R0 = D + 3. R1 = R3 = A + 4. R0 = DMA = Px + 5. R3 = R0 = Px + 6. Select R1, R3 + 7. R0 = R1 - R3 = A - Px = C + 8. R1 = R0 = C + 9. Select R1, R4 + 10. R0 = R1 * R4 = Pz * C = R->Z + + Read Operations: + + R->Z = R0 = Pz * C + + Output State: + R0 = FREE + R1 = C + R2 = D + R3 = Px + R4 = FREE + + STEP 2: + */ + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA1, &P->Y); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_SELDDATA0DDATA1, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA2); /* R2 = D */ + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &P->X); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_7 (crypto, + CRYPTO_CMD_INSTR_DDATA3TODDATA1, + CRYPTO_CMD_INSTR_DDATA0TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, /* R1 = C */ + + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL + ); + CRYPTO_InstructionSequenceWait(crypto); + + ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Z); + + if (ret != 0) goto cleanup; + + /* + STEP 3: + + Goals: + X1C2 = Px * C^2 + C3 = C^3 + D2 = D^2 + + Input State: + R0 = FREE + R1 = C + R2 = D + R3 = Px + R4 = FREE + + Instructions to be executed: + + 1. R4 = R1 = C + 2. Select R1, R4 + 3. R0 = R1 * R4 = C^2 + 4. R1 = R0 = C^2 + 5. R0 = R1 * R4 = C^3 + 6. R4 = R0 = C^3 + 7. Select R1, R3 + 8. R0 = R1 * R3 = Px * C^2 + 9. R3 = R0 = Px * C^2 + 10. R1 = R2 = D + 11. Select R1, R1 + 12. R0 = R1 * R1 = D^2 + 13. Select R0, R4 + 14. R0 = R0 - R4 = D2 - C3 + + Output state: + + R0 = D2 - C3 + R1 = FREE + R2 = D + R3 = X1C2 = Px * C^2 + R4 = C3 = C^3 + + STEP 3: + */ + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA1TODDATA4, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA4); + CRYPTO_InstructionSequenceWait(crypto); + + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA3); + CRYPTO_InstructionSequenceWait(crypto); + + CRYPTO_EXECUTE_5 (crypto, + CRYPTO_CMD_INSTR_DDATA2TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_SELDDATA0DDATA4, + CRYPTO_CMD_INSTR_MSUB + ); + CRYPTO_InstructionSequenceWait(crypto); + + /* + STEP 3: + + Goals: + R->X = D2 - (C3 + 2 * X1C2) = D2 - C3 - X1C2- X1C2 + Y1C3 = Py * C3 + R->Y = D * (X1C2 - R->X) - Y1C3 + + Write Operations: + R1 = Py + + Input State: + R0 = D2 - C3 + R1 = FREE + R2 = D + R3 = X1C2 + R4 = C3 + + Instructions to be executed: + + 1. Select R0, R3 + 2. R0 = R0 - R3 = D2 - C3 - X1C2 + 3. R0 = R0 - R3 = D2 - C3 - X1C2 - X1C2 = R->X + 4. DMA = R0 = R->X + 5. R1 = R0 = R->X + + 6. Select R3, R1 + 7. R0 = R3 - R1 = X1C2 - R->X + 8. R1 = R0 = X1C2 - R->X + 9. Select R1, R2 + 10. R0 = R1 * R2 = D *(X1C2 - R->X) + 11. R2 = R0 + + 12. R0 = DMA = Py + 13. R1 = R0 = Py + 14. Select R1, R4 + 15. R0 = R1 * R4 = Py * C3 = Y1C3 + 16. R4 = R0 = Y1C3 + + 17. Select R2, R4 + 18. R0 = R2 - R4 + + Read Operations: + + R->X = R2 = D2 - (C3 + 2 * X1C2) + R->Y = R0 = D * (X1C2 - R->X) - Y1C3 + + STEP 4: + */ + + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_SELDDATA0DDATA3, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_MSUB); + CRYPTO_InstructionSequenceWait(crypto); + + ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->X); + if ( ret != 0 ) goto cleanup; + + CRYPTO_EXECUTE_7 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + + CRYPTO_CMD_INSTR_SELDDATA3DDATA1, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA2); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &P->Y); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_6 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA4, + + CRYPTO_CMD_INSTR_SELDDATA2DDATA4, + CRYPTO_CMD_INSTR_MSUB + ); + CRYPTO_InstructionSequenceWait(crypto); + + ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Y); + if ( ret != 0 ) goto cleanup; + + cleanup: + crypto_management_release( crypto ); + return ( ret ); +} +#endif + +/** + * \brief Point doubling R = 2 P, Jacobian coordinates. + * + * Cost: 1D := 3M + 4S (A == 0) + * 4M + 4S (A == -3) + * 3M + 6S + 1a otherwise + * when the implementation is based on the "dbl-1998-cmo-2" + * doubling formulas in [8] and standard optimizations are + * applied when curve parameter A is one of { 0, -3 }. + * + * \param grp Pointer to the group representing the curve. + * + * \param R Pointer to a point structure to hold the result. + * + * \param P Pointer to the point that has to be doubled, given with + * Jacobian coordinates. + * + * \return 0 if successful. + */ +#if defined(MBEDTLS_ECP_DOUBLE_JAC_ALT) +int mbedtls_internal_ecp_double_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *R, + const mbedtls_ecp_point *P ) +{ + int ret; + CORE_DECLARE_IRQ_STATE; + CRYPTO_TypeDef *crypto = crypto_management_acquire(); + + crypto_device_init(crypto, grp); + + ecc_bigint_t _2YY; + /* + STEP 1: + + Goals: + ZZ = Z^2 + R->Z = 2 * Y * Z + YY = Y^2 + 4YY = 4 * Y^2 + + Write Operations: + + R2 = Y + R3 = Z + + Instructions to be executed: + + 1. R0 = DMA = Z + 2. R1 = R0 = Z + 3. R2 = R0 = Z + 4. Select R1, R2 + 5. R0 = R1 * R2 = Z^2 = ZZ + 6. R3 = R0 = ZZ + + 7. R0 = DMA = Y + 8. R2 = R0 = Y + 9. R0 = R1 * R2 = Y * Z + 10. Select R0, R0 + 11. R0 = R0 + R0 = 2 * Y * Z = R->Z + + 12. DMA = R0 = R->Z + + 13. R1 = R2 = Y + 14. Select R1, R2 + 15. R0 = R1 * R2 = Y^2 = YY + 16. Select R0, R0 + 17. R0 = R0 + R0 = 2YY + + Read Operations: + + R->Z = R0 = 2 * Y * Z + 2YY = R0 + + Output State: + R0 = 2YY + R1 = FREE + R2 = FREE + R3 = ZZ + R4 = FREE + + STEP 1: + */ + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &P->Z); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_5 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA3); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA0, &P->Y); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_4 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_SELDDATA0DDATA0, + CRYPTO_CMD_INSTR_MADD); + CRYPTO_InstructionSequenceWait(crypto); + + ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Z); + if ( ret != 0 ) goto cleanup; + + CRYPTO_EXECUTE_5 (crypto, + CRYPTO_CMD_INSTR_DDATA2TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_SELDDATA0DDATA0, + CRYPTO_CMD_INSTR_MADD + ); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA4, &P->X); + CRYPTO_DDataRead(&crypto->DDATA0, _2YY); + CORE_EXIT_CRITICAL(); + + /* + STEP 2: + + Goals: + A = 4YY * X + C = 3(X - ZZ)(X + ZZ) + + Write Operations: + + R4 = X + + Input State: + R0 = 2YY + R1 = FREE + R2 = FREE + R3 = ZZ + R4 = X + + Instructions to be executed: + + 1. R0 = R0 + R0 = 4YY + 2. R1 = R0 = 4YY + 3. Select R1, R4 + 4. R0 = R1 * R4 = 4YY * X = A + 5. R2 = R0 = A + 6. Select R4, R3 + 7. R0 = R4 + R3 = X + ZZ + 8. R1 = R0 = X + ZZ + 9. R0 = R4 - R3 = X - ZZ + 0. R2 = R0 = X - ZZ + 11. Select R1, R2 + 12. R0 = R1 * R2 = (X + ZZ)(X - ZZ) + 13. R1 = R0 = (X + ZZ)(X - ZZ) + 14. Select R0, R1 + 15. R0 = R0 + R1 = 2(X + ZZ)(X - ZZ) + 16. R0 = R0 + R1 = 3(X + ZZ)(X - ZZ) = C + 17. R1 = R0 = C + + Output State: + R0 = FREE + R1 = C + R2 = A + R3 = FREE + R4 = FREE + + STEP 2: + */ + CRYPTO_EXECUTE_11(crypto, + CRYPTO_CMD_INSTR_SELDDATA0DDATA0, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA4DDATA3, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA4); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_7 (crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA0DDATA1, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA1 + ); + CRYPTO_InstructionSequenceWait(crypto); + /* + STEP 3: + + Goals: + R->X = C^2 - 2A + D = C(A - R->X) + + Input State: + R0 = FREE + R1 = C + R2 = A + R3 = FREE + R4 = FREE + + Instructions to be executed: + + 1. R4 = R1 = C + 2. Select R1, R4 + 3. R0 = R1 * R4 = C^2 + 4. Select R0, R2 + 5. R0 = R0 - R2 = C^2 - 2A = R->X + 6. R4 = R0 = R->X + 7. Select R3, R4 + 8. R0 = R3 - R4 = A - R->X + 9. R2 = R0 = A - R->X + 10 Select R1, R2 + 11. R0 = R1 * R2 = C(A - R->X) = D + + Read Operations: + + R->X = R4 = C^2 - 2A + + Output State: + R0 = FREE + R1 = FREE + R2 = FREE + R3 = D + R4 = FREE + + STEP 3: + */ + + CRYPTO_EXECUTE_8 (crypto, + CRYPTO_CMD_INSTR_SELDDATA2DDATA2, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA4, + + CRYPTO_CMD_INSTR_DDATA1TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL, + + CRYPTO_CMD_INSTR_SELDDATA0DDATA4, + CRYPTO_CMD_INSTR_MSUB); + CRYPTO_InstructionSequenceWait(crypto); + + ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->X); + if ( ret != 0 ) goto cleanup; + + CRYPTO_EXECUTE_7 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA4, + + CRYPTO_CMD_INSTR_SELDDATA2DDATA4, + CRYPTO_CMD_INSTR_MSUB, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA3 + ); + CRYPTO_InstructionSequenceWait(crypto); + + + /* + STEP 4: + + Goals: + B = 8 * Y^4 + R->Y = D - B + + Write Operations: + + R1 = YY + + Input State: + R0 = FREE + R1 = YY + R2 = FREE + R3 = D + R4 = FREE + + Instructions to be executed: + + 2. R0 = DMA0 + 3. R1 = R0 = Y^2 + 4. R2 = R0 = Y^2 + 5. Select R1, R2 + 6. R0 = R1 * R2 = Y^4 + 7. Select R0, R0 + 8. R0 = R0 + R0 = 2 * Y^4 + 9. R0 = R0 + R0 = 4 * Y^4 + 10. R0 = R0 + R0 = 8 * Y^4 + 11. R2 = R0 + 12. Select R3, R2 + 13. R0 = R3 - R2 = D - B = R->Y + + Read Operations: + + R->Y = R0 = D - B + + STEP 4: + */ + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA0, _2YY); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_9 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + + CRYPTO_CMD_INSTR_SELDDATA0DDATA0, + CRYPTO_CMD_INSTR_MADD, + CRYPTO_CMD_INSTR_DDATA0TODDATA2, + + CRYPTO_CMD_INSTR_SELDDATA3DDATA2, + CRYPTO_CMD_INSTR_MSUB + ); + CRYPTO_InstructionSequenceWait(crypto); + + ret = ecp_crypto_ddata_read(&crypto->DDATA0, &R->Y); + if ( ret != 0 ) goto cleanup; + + cleanup: + crypto_management_release( crypto ); + + return ( ret ); +} +#endif + +/** + * \brief Normalize jacobian coordinates of an array of (pointers to) + * points. + * + * Using Montgomery's trick to perform only one inversion mod P + * the cost is: + * 1N(t) := 1I + (6t - 3)M + 1S + * (See for example Algorithm 10.3.4. in [9]) + * + * This function is used only as a subrutine of + * ecp_mul_comb(). + * + * Warning: fails (returning an error) if one of the points is + * zero! + * This should never happen, see choice of w in ecp_mul_comb(). + * + * \param grp Pointer to the group representing the curve. + * + * \param T Array of pointers to the points to normalise. + * + * \param t_len Number of elements in the array. + * + * \return 0 if successful, + * an error if one of the points is zero. + */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT) +int mbedtls_internal_ecp_normalize_jac_many( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *T[], + size_t t_len ) +{ + int ret = 0; + size_t i; + ecc_bigint_t* cc; + ecc_bigint_t uu; + ecc_bigint_t one; + ecc_bigint_t modulus; + CORE_DECLARE_IRQ_STATE; + + if( t_len < 2 ) + return( mbedtls_internal_ecp_normalize_jac( grp, *T ) ); + + if( ( cc = mbedtls_calloc( t_len, sizeof( ecc_bigint_t ) ) ) == NULL ) + return( MBEDTLS_ERR_ECP_ALLOC_FAILED ); + + /* + * c[i] = Z_0 * ... * Z_i + */ + MPI_TO_BIGINT( cc[0], &T[0]->Z ); + + CRYPTO_TypeDef *crypto = crypto_management_acquire(); + crypto_device_init(crypto, grp); + + for( i = 1; i < t_len; i++ ) + { + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write( &crypto->DDATA1, &T[i]->Z ); + CRYPTO_DDataWrite( &crypto->DDATA2, cc[i-1] ); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_2(crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead( &crypto->DDATA0, cc[i] ); + CORE_EXIT_CRITICAL(); + } + + memset(one, 0, sizeof(one)); + one[0]=1; + MPI_TO_BIGINT( modulus, &grp->P ); + + /* + * u = 1 / (Z_0 * ... * Z_n) mod P + */ + crypto_mpi_div_mod(crypto, one, cc[t_len-1], modulus, uu); + + for( i = t_len - 1; ; i-- ) + { + /* + * Zi = 1 / Z_i mod p + * u = 1 / (Z_0 * ... * Z_i) mod P + */ + if( i == 0 ) + { + /* Z_inv (DDATA2) = uu */ + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA2, uu); + CORE_EXIT_CRITICAL(); + } + else + { + /* Z_inv (DDATA1) = uu x cc[i-1] modulo p */ + /* uu = uu x T[i]->Z modulo p */ + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA1, uu); + CRYPTO_DDataWrite(&crypto->DDATA2, cc[i-1]); + ecp_crypto_ddata_write( &crypto->DDATA3, &T[i]->Z ); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_3(crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL, + CRYPTO_CMD_INSTR_DDATA0TODDATA2); /* Z_inv (DDATA2) */ + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_2(crypto, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead(&crypto->DDATA0, uu); + CORE_EXIT_CRITICAL(); + } + + /* + * proceed as in normalize() + */ + CORE_ENTER_CRITICAL(); + ecp_crypto_ddata_write(&crypto->DDATA3, &T[i]->X); + ecp_crypto_ddata_write(&crypto->DDATA4, &T[i]->Y); + CORE_EXIT_CRITICAL(); + + /* Z_inv already in DDATA2 */ + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA2TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + + ecp_crypto_ddata_read(&crypto->DDATA0, &T[i]->Y); + ecp_crypto_ddata_read(&crypto->DDATA3, &T[i]->X); + + /* + * Post-precessing: reclaim some memory by shrinking coordinates + * - not storing Z (always 1) + * - shrinking other coordinates, but still keeping the same number of + * limbs as P, as otherwise it will too likely be regrown too fast. + */ + SLCL_ECP_CHK( mbedtls_mpi_shrink( &T[i]->X, grp->P.n ) ); + SLCL_ECP_CHK( mbedtls_mpi_shrink( &T[i]->Y, grp->P.n ) ); + mbedtls_mpi_free( &T[i]->Z ); + + if( i == 0 ) + break; + } + + cleanup: + crypto_management_release( crypto ); + mbedtls_free( cc ); + + return( ret ); +} +#endif + +/** + * \brief Normalize jacobian coordinates so that Z == 0 || Z == 1. + * + * Cost in field operations if done by [5] 3.2.1: + * 1N := 1I + 3M + 1S + * + * \param grp Pointer to the group representing the curve. + * + * \param pt pointer to the point to be normalised. This is an + * input/output parameter. + * + * \return 0 if successful. + */ +#if defined(MBEDTLS_ECP_NORMALIZE_JAC_ALT) +int mbedtls_internal_ecp_normalize_jac( const mbedtls_ecp_group *grp, + mbedtls_ecp_point *pt ) +{ + int ret = 0; + CORE_DECLARE_IRQ_STATE; + CRYPTO_TypeDef *crypto = crypto_management_acquire(); + + crypto_device_init(crypto, grp); + + ecc_bigint_t one; + ecc_bigint_t Z; + ecc_bigint_t modulus; + ecc_bigint_t Z_inv; + + memset(one, 0, sizeof(one)); + one[0]=1; + + MPI_TO_BIGINT( Z, &pt->Z ); + MPI_TO_BIGINT( modulus, &grp->P ); + + crypto_mpi_div_mod(crypto, one, Z, modulus, Z_inv); + + /* + + Goals: + R->X = P->X * Z_inv ^2 + R->Y = P->Y * Z_inv ^3 + + Write Operations: + + R1 = Z_inv + R3 = P->X + R4 = P->Y + + Instructions to be executed: + + 1. R2 = R1 = Z_inv + 2. Select R1, R2 + 3. R0 = R1 * R2 = Z_inv^2 + 4. R1 = R0 = Z_inv^2 + 5. Select R1, R3 + 6. R0 = R1 * R3 = P->X * Z_inv^2 = R->X + 7. R3 = R0 + 8. Select R1, R2 + 9. R0 = R1 * R2 = Z_inv^3 + 10. R1 = R0 = Z_inv^3 + 11. Select R1, R4 + 12. R0 = R1 * R4 = P->Y * Z_inv^3 = R->Y + + Read Operations: + + R->Y = R0 = P->Y * P->Z_inv^3 + R->X = R3 = P->X * P->Z_inv^2 + + */ + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA1, Z_inv); + ecp_crypto_ddata_write(&crypto->DDATA3, &pt->X); + ecp_crypto_ddata_write(&crypto->DDATA4, &pt->Y); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA1TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA3, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA3, + CRYPTO_CMD_INSTR_SELDDATA1DDATA2, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + CRYPTO_EXECUTE_3 (crypto, + CRYPTO_CMD_INSTR_DDATA0TODDATA1, + CRYPTO_CMD_INSTR_SELDDATA1DDATA4, + CRYPTO_CMD_INSTR_MMUL); + CRYPTO_InstructionSequenceWait(crypto); + + ecp_crypto_ddata_read(&crypto->DDATA0, &pt->Y); + ecp_crypto_ddata_read(&crypto->DDATA3, &pt->X); + + crypto_management_release( crypto ); + + /* + * Z = 1 + */ + SLCL_ECP_CHK( mbedtls_mpi_lset( &pt->Z, 1 ) ); + + cleanup: + return( ret ); +} +#endif + +#endif /* #if defined( MBEDTLS_ECP_INTERNAL_ALT ) */ + +#endif /* #if defined( MBEDTLS_ECP_C ) */ + +#endif /* #if defined( CRYPTO_PRESENT ) */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.c new file mode 100644 index 00000000000..b49fe089313 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.c @@ -0,0 +1,403 @@ +/* + * Silicon Labs CRYPTO device management interface. + * + * Copyright (C) 2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "crypto_management.h" +#include "em_core.h" +#include "em_bus.h" + +#if defined( CRYPTO_PRESENT ) + +/* Conversion macro for compatibility with the 5.3.x release of the Gecko SDK */ +#if defined( MBEDTLS_CRYPTO_DEVICE_PREEMPTION ) +#warning "MBEDTLS_CRYPTO_DEVICE_PREEMPTION is deprecated, please define " \ + "CRYPTO_DEVICE_PREEMPTION instead." +#endif + +#if defined( MBEDTLS_THREADING_C ) +#include "mbedtls/threading.h" +static mbedtls_threading_mutex_t crypto_locks[CRYPTO_COUNT]; +static volatile bool crypto_locks_initialized = false; +static unsigned int acquire_count = 0U; +#endif /* MBEDTLS_THREADING_C */ + +#if defined( CRYPTO_DEVICE_PREEMPTION ) +/** Preemptable context of CRYPTO hardware module. */ +typedef struct +{ + uint32_t CTRL; /*!< Control Register */ + uint32_t WAC; /*!< Wide Arithmetic Configuration */ + uint32_t SEQCTRL; /*!< Sequence Control */ + uint32_t SEQCTRLB; /*!< Sequence Control B */ + uint32_t IEN; /*!< Interrupt Enable Register */ + uint32_t SEQ[5]; /*!< Instruction Sequence registers */ + CRYPTO_Data260_TypeDef DDATA[5]; /*!< DDATA registers. Covers all data + registers + of CRYPTO, including DATA(128 bit), + DDATA (256bit/260bit), + QDATA (512bit) registers. */ + uint32_t regmask; /*!< Bitmask for which registers to save */ + uint32_t operands; /*!< Saving the currently selected operands */ + bool carry; /*!< Saving the status of the carry flag */ +} crypto_context_t; + +static crypto_context_t preemption_context; +static bool is_preempted = false; +static CORE_DECLARE_IRQ_STATE; +#endif /* CRYPTO_DEVICE_PREEMPTION */ + +typedef enum +{ +#if defined( CRYPTO0 ) + CRYPTO0_ID = 0, +#elif defined( CRYPTO ) + CRYPTO_ID = 0, +#endif +#if defined( CRYPTO1 ) + CRYPTO1_ID = 1, +#endif +} crypto_instance_number_t; + +typedef struct { + CRYPTO_TypeDef *device; + uint32_t clockMask; +} crypto_device_t; + +static const crypto_device_t crypto_devices[CRYPTO_COUNT] = +{ +#if defined( CRYPTO0 ) + { + CRYPTO0, + _CMU_HFBUSCLKEN0_CRYPTO0_SHIFT + }, +#elif defined( CRYPTO ) + { + CRYPTO, + _CMU_HFBUSCLKEN0_CRYPTO_SHIFT + }, +#endif +#if defined( CRYPTO1 ) + { + CRYPTO1, + _CMU_HFBUSCLKEN0_CRYPTO1_SHIFT + }, +#endif +}; + +static inline int crypto_management_index_by_device( CRYPTO_TypeDef *device ) +{ +#if defined( CRYPTO0 ) + if ( device == CRYPTO0 ) return 0; +#elif defined( CRYPTO ) + if ( device == CRYPTO ) return 0; +#endif +#if defined( CRYPTO1 ) + if ( device == CRYPTO1 ) return 1; +#endif + return -1; +} + +/* Use bitband for clock enable/disable operations, such that they are atomic */ +#define CRYPTO_CLOCK_ENABLE(clk) BUS_RegBitWrite(&(CMU->HFBUSCLKEN0), (clk), 1) +#define CRYPTO_CLOCK_DISABLE(clk) BUS_RegBitWrite(&(CMU->HFBUSCLKEN0), (clk), 0) +#define CRYPTO_CLOCK_ENABLED(clk) BUS_RegBitRead(&(CMU->HFBUSCLKEN0), (clk)) + +/* Get ownership of an available crypto device */ +CRYPTO_TypeDef *crypto_management_acquire( void ) +{ + CRYPTO_TypeDef *device = NULL; + +#if defined( MBEDTLS_THREADING_C ) + /* Initialize mutexes if that hasn't happened yet */ + CORE_DECLARE_IRQ_STATE; + + if ( !crypto_locks_initialized ) { + CORE_ENTER_CRITICAL(); + if ( !crypto_locks_initialized ) { + for ( int i = 0; i < CRYPTO_COUNT; i++ ) { + mbedtls_mutex_init(&crypto_locks[i]); + } + crypto_locks_initialized = true; + } + CORE_EXIT_CRITICAL(); + } + +/* Wrapping this in SL_THREADING_ALT pending non-blocking mutex in official + * threading API. */ +#if defined( SL_THREADING_ALT ) + /* Try to take an available crypto instance */ + unsigned int devno = 0; + for ( ; devno < CRYPTO_COUNT; devno++ ) { + if ( 0 == THREADING_TakeMutexNonBlocking(&crypto_locks[devno]) ) { + device = crypto_devices[devno].device; + break; + } + } +#endif // SL_THREADING_ALT + + /* If no device immediately available, do naieve round-robin */ + if ( device == NULL ) { + devno = acquire_count % CRYPTO_COUNT; + mbedtls_mutex_lock( &crypto_locks[devno] ); + device = crypto_devices[devno].device; + } + + /* Doing this outside of critical section is safe, since we own the lock + * and are using bitband to poke the clock enable bit */ + CRYPTO_CLOCK_ENABLE( crypto_devices[devno].clockMask ); + + acquire_count++; +#else // !MBEDTLS_THREADING_C + device = crypto_devices[0].device; + CRYPTO_CLOCK_ENABLE( crypto_devices[0].clockMask ); +#endif // MBEDTLS_THREADING_C + + return device; +} + +/* Get ownership of the default crypto device (CRYPTO0/CRYPTO) */ +CRYPTO_TypeDef *crypto_management_acquire_default( void ) +{ + CRYPTO_TypeDef *device = NULL; + +#if defined( MBEDTLS_THREADING_C ) + /* Initialize mutexes if that hasn't happened yet */ + CORE_DECLARE_IRQ_STATE; + + if ( !crypto_locks_initialized ) { + CORE_ENTER_CRITICAL(); + if ( !crypto_locks_initialized ) { + for ( int i = 0; i < CRYPTO_COUNT; i++ ) { + mbedtls_mutex_init(&crypto_locks[i]); + } + crypto_locks_initialized = true; + } + CORE_EXIT_CRITICAL(); + } + + mbedtls_mutex_lock( &crypto_locks[0] ); + device = crypto_devices[0].device; + + /* Doing this outside of critical section is safe, since we own the lock + * and are using bitband to poke the clock enable bit */ + CRYPTO_CLOCK_ENABLE( crypto_devices[0].clockMask ); +#else // !MBEDTLS_THREADING_C + device = crypto_devices[0].device; + CRYPTO_CLOCK_ENABLE( crypto_devices[0].clockMask ); +#endif // MBEDTLS_THREADING_C + + return device; +} + +/* Release ownership of an available crypto device */ +void crypto_management_release( CRYPTO_TypeDef *device ) +{ + int devno = crypto_management_index_by_device( device ); + if ( devno < 0 ) { + return; + } + + /* Doing this outside of critical section is safe, since we still own the lock + * and are using bitband to poke the clock enable bit */ + CRYPTO_CLOCK_DISABLE( crypto_devices[devno].clockMask ); + +#if defined ( MBEDTLS_THREADING_C ) + mbedtls_mutex_unlock( &crypto_locks[devno] ); +#endif +} + +/* Acquire a device with preemption. NOT thread-safe! */ +CRYPTO_TypeDef *crypto_management_acquire_preemption( uint32_t regmask ) +{ +#if defined( CRYPTO_DEVICE_PREEMPTION ) + CRYPTO_TypeDef *device = NULL; + /* Turn off interrupts */ + CORE_ENTER_CRITICAL(); + + /* Check if there is an unused CRYPTO instance */ + for ( int i = 0; i < CRYPTO_COUNT; i++ ) { + if ( !CRYPTO_CLOCK_ENABLED( crypto_devices[i].clockMask ) ) { + /* Found an unused device */ + CRYPTO_CLOCK_ENABLE( crypto_devices[i].clockMask ); + device = crypto_devices[i].device; + break; + } + } + + /* If there is no unused instance, preempt the last one */ + if ( device == NULL ) { + is_preempted = true; + device = crypto_devices[CRYPTO_COUNT - 1].device; + + /* In case this instance is still working on anything */ + CRYPTO_InstructionSequenceWait(device); + + /* Store operational context */ + preemption_context.regmask = regmask; + preemption_context.WAC = device->WAC; + preemption_context.CTRL = device->CTRL; + preemption_context.SEQCTRL = device->SEQCTRL; + preemption_context.SEQCTRLB = device->SEQCTRLB; + preemption_context.IEN = device->IEN; + preemption_context.operands = device->CSTATUS; + preemption_context.carry = (device->DSTATUS & CRYPTO_DSTATUS_CARRY) != 0; + + if ( (preemption_context.WAC & _CRYPTO_WAC_RESULTWIDTH_MASK) == CRYPTO_WAC_RESULTWIDTH_260BIT) + { + CRYPTO_DData0Read260(device, preemption_context.DDATA[0]); /* Always save DDATA0 because it'll get clobbered in 260-bit mode*/ + + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 ) { + device->CMD = CRYPTO_CMD_INSTR_DDATA1TODDATA0; /* Move DDATA1 to DDATA0 + in order to read. */ + CRYPTO_DData0Read260(device, preemption_context.DDATA[1]); + } + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 ) { + device->CMD = CRYPTO_CMD_INSTR_DDATA2TODDATA0; /* Move DDATA2 to DDATA0 + in order to read. */ + CRYPTO_DData0Read260(device, preemption_context.DDATA[2]); + } + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 ) { + device->CMD = CRYPTO_CMD_INSTR_DDATA3TODDATA0; /* Move DDATA3 to DDATA0 + in order to read. */ + CRYPTO_DData0Read260(device, preemption_context.DDATA[3]); + } + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 ) { + device->CMD = CRYPTO_CMD_INSTR_DDATA4TODDATA0; /* Move DDATA4 to DDATA0 + in order to read. */ + CRYPTO_DData0Read260(device, preemption_context.DDATA[4]); + } + } + else + { + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA0) != 0 ) + CRYPTO_DDataRead(&device->DDATA0, preemption_context.DDATA[0]); + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 ) + CRYPTO_DDataRead(&device->DDATA1, preemption_context.DDATA[1]); + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 ) + CRYPTO_DDataRead(&device->DDATA2, preemption_context.DDATA[2]); + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 ) + CRYPTO_DDataRead(&device->DDATA3, preemption_context.DDATA[3]); + if ( (regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 ) + CRYPTO_DDataRead(&device->DDATA4, preemption_context.DDATA[4]); + } + + /* Search for possible EXEC commands and replace with END. */ + for ( size_t j = 0; j < (regmask & 0x7U)*sizeof(uint32_t); j++ ) { + if ( (j & 0x03) == 0 ) { + preemption_context.SEQ[j / sizeof(uint32_t)] = *((&device->SEQ0) + (j / sizeof(uint32_t))); + } + if ( ((uint8_t*)preemption_context.SEQ)[j] == CRYPTO_CMD_INSTR_EXEC ) { + ((uint8_t*)preemption_context.SEQ)[j] = CRYPTO_CMD_INSTR_END; + } + } + } + + return device; +#else + (void) regmask; + return crypto_management_acquire(); +#endif +} + +/* Release a device from preemption */ +void crypto_management_release_preemption( CRYPTO_TypeDef *device ) +{ + if ( crypto_management_index_by_device( device ) < 0 ) { + return; + } +#if defined( CRYPTO_DEVICE_PREEMPTION ) + + if ( is_preempted ) { + /* If we preempted something, put their context back */ + device->WAC = preemption_context.WAC; + device->CTRL = preemption_context.CTRL; + device->SEQCTRL = preemption_context.SEQCTRL; + device->SEQCTRLB = preemption_context.SEQCTRLB; + device->IEN = preemption_context.IEN; + + if ( (preemption_context.WAC & _CRYPTO_WAC_RESULTWIDTH_MASK) == CRYPTO_WAC_RESULTWIDTH_260BIT) + { + /* Start by writing the DDATA1 value to DDATA0 and move to DDATA1. */ + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 ) { + CRYPTO_DData0Write260(device, preemption_context.DDATA[1]); + device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA1; + } + + /* Write the DDATA2 value to DDATA0 and move to DDATA2. */ + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 ) { + CRYPTO_DData0Write260(device, preemption_context.DDATA[2]); + device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA2; + } + + /* Write the DDATA3 value to DDATA0 and move to DDATA3. */ + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 ) { + CRYPTO_DData0Write260(device, preemption_context.DDATA[3]); + device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA3; + } + + /* Write the DDATA4 value to DDATA0 and move to DDATA4. */ + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 ) { + CRYPTO_DData0Write260(device, preemption_context.DDATA[4]); + device->CMD = CRYPTO_CMD_INSTR_DDATA0TODDATA4; + } + + /* Finally write DDATA0 */ + CRYPTO_DData0Write260(device, preemption_context.DDATA[0]); + } + else + { + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA0) != 0 ) + CRYPTO_DDataWrite(&device->DDATA0, preemption_context.DDATA[0]); + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA1) != 0 ) + CRYPTO_DDataWrite(&device->DDATA1, preemption_context.DDATA[1]); + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA2) != 0 ) + CRYPTO_DDataWrite(&device->DDATA2, preemption_context.DDATA[2]); + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA3) != 0 ) + CRYPTO_DDataWrite(&device->DDATA3, preemption_context.DDATA[3]); + if ( (preemption_context.regmask & CRYPTO_MANAGEMENT_SAVE_DDATA4) != 0 ) + CRYPTO_DDataWrite(&device->DDATA4, preemption_context.DDATA[4]); + } + + if (preemption_context.carry) { + device->CMD = CRYPTO_CMD_INSTR_CSET; + } else { + device->CMD = CRYPTO_CMD_INSTR_CCLR; + } + + device->CMD = (preemption_context.operands & 0x7U) | + (((preemption_context.operands >> 8) & 0x7U) << 3) | + 0xC0; + + for (size_t i = 0; i < (preemption_context.regmask & 0x7U); i++ ) { + *((&device->SEQ0) + i) = preemption_context.SEQ[i]; + } + + is_preempted = false; + } else { + /* If we didn't preempt anything, turn crypto clock back off */ + CRYPTO_CLOCK_DISABLE( crypto_devices[crypto_management_index_by_device( device )].clockMask ); + } + + /* Turn interrupts back on */ + CORE_EXIT_CRITICAL(); +#else + crypto_management_release(device); +#endif +} + +#endif /* CRYPTO_PRESENT */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.h b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.h new file mode 100644 index 00000000000..b1a4e9f151f --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_management.h @@ -0,0 +1,128 @@ +/* + * Silicon Labs CRYPTO device management interface. + * + * Copyright (C) 2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CRYPTO_MANAGEMENT_H +#define CRYPTO_MANAGEMENT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_management CRYPTO peripheral instance management + * \brief Management functions for CRYPTO peripherals. These functions take care + * of not having two 'owners' simultaneously for the same peripheral, + * potentially messing up the internal state of said peripheral. + * \{ + ******************************************************************************/ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include + +#include "em_device.h" + +#if defined( CRYPTO_PRESENT ) +#include "em_crypto.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Save DDATA0 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_DDATA0 (0x1U << 3) +/** Save DDATA1 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_DDATA1 (0x1U << 4) +/** Save DDATA2 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_DDATA2 (0x1U << 5) +/** Save DDATA3 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_DDATA3 (0x1U << 6) +/** Save DDATA4 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_DDATA4 (0x1U << 7) +/** Save SEQ0 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ0 (0x1U) +/** Save SEQ0 through SEQ1 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ1 (0x2U) +/** Save SEQ0 through SEQ2 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ2 (0x3U) +/** Save SEQ0 through SEQ3 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ3 (0x4U) +/** Save SEQ0 through SEQ4 register when preempting */ +#define CRYPTO_MANAGEMENT_SAVE_UPTO_SEQ4 (0x5U) + +/** + * \brief Get ownership of a CRYPTO peripheral + * + * \return Handle of assigned CRYPTO peripheral + */ +CRYPTO_TypeDef *crypto_management_acquire( void ); + +/** + * \brief Get ownership of the default CRYPTO peripheral + * + * \return Handle of default CRYPTO peripheral + */ +CRYPTO_TypeDef *crypto_management_acquire_default( void ); + +/** + * \brief Release ownership of a CRYPTO peripheral + * + * \param device Handle of CRYPTO peripheral to be released + */ +void crypto_management_release( CRYPTO_TypeDef *device ); + +/** + * \brief Acquire preempting ownership of a CRYPTO peripheral. + * NOTE: this function is not meant for general use, it + * is not thread-safe, and must be called form the + * highest priority thread/interrupt allowed to use mbed TLS. + * + * \param regmask Bitmask of CRYPTO_MANAGEMENT_ defines instructing what + * parts of the device state will be clobbered during + * preemption. + * + * \return Handle of assigned CRYPTO peripheral + */ +CRYPTO_TypeDef *crypto_management_acquire_preemption( uint32_t regmask ); + +/** + * \brief Releasing preempting ownership of a CRYPTO peripheral. + * NOTE: this function is not meant for general use, it + * is not thread-safe, and must be called form the + * highest priority thread/interrupt allowed to use mbed TLS. + * + * \param device Handle of preempted CRYPTO peripheral to be released + */ +void crypto_management_release_preemption( CRYPTO_TypeDef *device ); + +#ifdef __cplusplus +} +#endif + +#endif /* CRYPTO_PRESENT */ + +/** \} (end addtogroup sl_crypto_management) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* CRYPTO_MANAGEMENT_H */ \ No newline at end of file diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_sha.c b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_sha.c new file mode 100644 index 00000000000..64d03989237 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/crypto_sha.c @@ -0,0 +1,467 @@ +/* + * FIPS-180-2 compliant SHA-1 & SHA-256 implementation + * + * Copyright (C) 2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +/* + * This file includes an alternative implementation of the standard + * mbedtls/libary/sha[1][256].c using the CRYPTO hardware accelerator incorporated + * in MCU devices from Silicon Laboratories. + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + * + * The SHA-256 Secure Hash Standard was published by NIST in 2002. + * + * http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" + +#if ( defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) ) || ( defined(MBEDTLS_SHA1_ALT) && defined (MBEDTLS_SHA1_C) ) + +#include "em_device.h" + +#if defined(CRYPTO_PRESENT) +#include "em_crypto.h" +#include "em_core.h" +#include "crypto_management.h" +#include "em_assert.h" +#include + +#define CRYPTO_SHA_BLOCK_SIZE (64) + +#if defined(MBEDTLS_SHA1_C) +static const uint32_t init_state_sha1[8] = +{ + 0x67452301UL, + 0xEFCDAB89UL, + 0x98BADCFEUL, + 0x10325476UL, + 0xC3D2E1F0UL, + 0x0UL, + 0x0UL, + 0x0UL +}; +#endif /* defined(MBEDTLS_SHA1_C) */ + +#if defined(MBEDTLS_SHA256_C) +static const uint32_t init_state_sha256[8] = +{ + 0x6A09E667UL, + 0xBB67AE85UL, + 0x3C6EF372UL, + 0xA54FF53AUL, + 0x510E527FUL, + 0x9B05688CUL, + 0x1F83D9ABUL, + 0x5BE0CD19UL +}; + +static const uint32_t init_state_sha224[8] = +{ + 0xC1059ED8UL, + 0x367CD507UL, + 0x3070DD17UL, + 0xF70E5939UL, + 0xFFC00B31UL, + 0x68581511UL, + 0x64F98FA7UL, + 0xBEFA4FA4UL +}; +#endif /* defined(MBEDTLS_SHA256_C) */ + +static const unsigned char sha_padding[64] = +{ + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +typedef enum { +#if defined(MBEDTLS_SHA1_C) + CRYPTO_SHA1, +#endif /* defined(MBEDTLS_SHA1_C) */ +#if defined(MBEDTLS_SHA256_C) + CRYPTO_SHA2 +#endif /* defined(MBEDTLS_SHA256_C) */ +} crypto_sha_mode_t; + +/* + * 32-bit integer manipulation macros (big endian) + */ +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) \ +do { \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} while( 0 ) +#endif + +/** + * @brief unified SHA acceleration function. + * + * @param[inout] state State context for SHA hashing + * @param[in] data Input block(s). Must contain N blocks + * of SHA1/SHA256 block size (64 bytes) + * @param blocks Amount of blocks pointed to by data + * @param mode SHA operation mode + */ +static void crypto_sha_update_state( uint32_t state[8], + const unsigned char *data, + size_t blocks, + crypto_sha_mode_t mode ) +{ + CORE_DECLARE_IRQ_STATE; + CRYPTO_TypeDef *crypto = crypto_management_acquire(); + + switch ( mode ) { +#if defined(MBEDTLS_SHA1_C) + case CRYPTO_SHA1: + crypto->CTRL = CRYPTO_CTRL_SHA_SHA1; + break; +#endif /* defined(MBEDTLS_SHA1_C) */ +#if defined(MBEDTLS_SHA256_C) + case CRYPTO_SHA2: + crypto->CTRL = CRYPTO_CTRL_SHA_SHA2; + break; +#endif /* defined(MBEDTLS_SHA256_C) */ + } + + crypto->WAC = 0; + crypto->IEN = 0; + + /* Set result width of MADD32 operation. */ + CRYPTO_ResultWidthSet(crypto, cryptoResult256Bits); + + /* Clear sequence control registers */ + crypto->SEQCTRL = 0; + crypto->SEQCTRLB = 0; + + /* Put the state back */ + CORE_ENTER_CRITICAL(); + CRYPTO_DDataWrite(&crypto->DDATA1, state); + CORE_EXIT_CRITICAL(); + + CRYPTO_EXECUTE_3( crypto, + CRYPTO_CMD_INSTR_DDATA1TODDATA0, + CRYPTO_CMD_INSTR_DDATA1TODDATA2, + CRYPTO_CMD_INSTR_SELDDATA0DDATA1 ); + + /* Load the data block(s) */ + for ( size_t i = 0; i < blocks; i++ ) { + if ((uint32_t)(&data[i*CRYPTO_SHA_BLOCK_SIZE]) & 0x3) + { + uint32_t temp[CRYPTO_SHA_BLOCK_SIZE/sizeof(uint32_t)]; + memcpy(temp, &data[i*CRYPTO_SHA_BLOCK_SIZE], CRYPTO_SHA_BLOCK_SIZE); + CORE_ENTER_CRITICAL(); + CRYPTO_QDataWrite(&crypto->QDATA1BIG, temp); + CORE_EXIT_CRITICAL(); + } + else + { + CORE_ENTER_CRITICAL(); + CRYPTO_QDataWrite(&crypto->QDATA1BIG, + (uint32_t*) &data[i*CRYPTO_SHA_BLOCK_SIZE]); + CORE_EXIT_CRITICAL(); + } + + /* Process the data block */ + CRYPTO_EXECUTE_3( crypto, + CRYPTO_CMD_INSTR_SHA, + CRYPTO_CMD_INSTR_MADD32, + CRYPTO_CMD_INSTR_DDATA0TODDATA1 ); + } + CORE_ENTER_CRITICAL(); + CRYPTO_DDataRead(&crypto->DDATA0, state); + CORE_EXIT_CRITICAL(); + + crypto_management_release( crypto ); +} + +#if defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ) +{ + if( ctx == NULL ) { + return; + } + + memset( ctx, 0, sizeof( mbedtls_sha256_context ) ); +} + +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ) +{ + if( ctx == NULL ) { + return; + } + + memset( ctx, 0, sizeof( mbedtls_sha256_context ) ); +} + +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src ) +{ + if ( dst != NULL && src != NULL ) { + *dst = *src; + } +} + +/* + * SHA-256 context setup + */ +void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 ) +{ + ctx->total[0] = 0; + ctx->total[1] = 0; + + if ( is224 != 0 ) { + ctx->is224 = true; + memcpy(ctx->state, init_state_sha224, sizeof(ctx->state)); + } else { + ctx->is224 = false; + memcpy(ctx->state, init_state_sha256, sizeof(ctx->state)); + } +} + +void mbedtls_sha256_process( mbedtls_sha256_context *ctx, + const unsigned char data[64] ) +{ + crypto_sha_update_state( ctx->state, data, 1, CRYPTO_SHA2 ); +} + +/* + * SHA-256 process buffer + */ +void mbedtls_sha256_update( mbedtls_sha256_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + size_t fill; + uint32_t left; + + if( ilen == 0 ) { + return; + } + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += (uint32_t) ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if( ctx->total[0] < (uint32_t) ilen ) { + ctx->total[1]++; + } + + if( left && ilen >= fill ) { + memcpy( (void *) (ctx->buffer + left), input, fill ); + mbedtls_sha256_process( ctx, ctx->buffer ); + input += fill; + ilen -= fill; + left = 0; + } + + while( ilen >= 64 ) { + size_t blocks = ilen / 64; + crypto_sha_update_state( ctx->state, input, blocks, CRYPTO_SHA2 ); + input += blocks * 64; + ilen -= blocks * 64; + } + + if( ilen > 0 ) { + memcpy( (void *) (ctx->buffer + left), input, ilen ); + } +} + +/* + * SHA-256 final digest + */ +void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, + unsigned char output[32] ) +{ + uint32_t last, padn; + uint32_t high, low; + unsigned char msglen[8]; + + high = ( ctx->total[0] >> 29 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT32_BE( high, msglen, 0 ); + PUT_UINT32_BE( low, msglen, 4 ); + + last = ctx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + mbedtls_sha256_update( ctx, sha_padding, padn ); + mbedtls_sha256_update( ctx, msglen, 8 ); + + for ( size_t i = 0; i < (ctx->is224 ? 28 : 32); i+=4) { + *((uint32_t*)(&output[i])) = __REV(ctx->state[i >> 2]); + } +} +#endif /* #if defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) */ + +#if defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C) + +/** + * \brief Initialize SHA-1 context + */ +void mbedtls_sha1_init( mbedtls_sha1_context *ctx ) +{ + if( ctx == NULL ) { + return; + } + memset( ctx, 0, sizeof( mbedtls_sha1_context ) ); +} + +/** + * \brief Clear SHA-1 context + */ +void mbedtls_sha1_free( mbedtls_sha1_context *ctx ) +{ + if( ctx == NULL ) { + return; + } + memset( ctx, 0, sizeof( mbedtls_sha1_context ) ); +} + +/** + * \brief Clone (the state of) a SHA-1 context + */ +void mbedtls_sha1_clone( mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src ) +{ + if ( dst != NULL && src != NULL ) { + *dst = *src; + } +} + +/** + * \brief SHA-1 context setup + * + * \param ctx context to be initialized + */ +void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ) +{ + ctx->total[0] = 0; + ctx->total[1] = 0; + memcpy(ctx->state, init_state_sha1, 32); +} + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void mbedtls_sha1_update( mbedtls_sha1_context *ctx, + const unsigned char *input, + size_t ilen ) +{ + size_t fill; + uint32_t left; + + if( ilen == 0 ) { + return; + } + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += (uint32_t) ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if( ctx->total[0] < (uint32_t) ilen ) { + ctx->total[1]++; + } + + if( left && ilen >= fill ) { + memcpy( (void *) (ctx->buffer + left), input, fill ); + mbedtls_sha1_process( ctx, ctx->buffer ); + input += fill; + ilen -= fill; + left = 0; + } + + while( ilen >= 64 ) { + size_t blocks = ilen / 64; + crypto_sha_update_state( ctx->state, input, blocks, CRYPTO_SHA1 ); + input += blocks * 64; + ilen -= blocks * 64; + } + + if( ilen > 0 ) { + memcpy( (void *) (ctx->buffer + left), input, ilen ); + } +} + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, + unsigned char output[20] ) +{ + uint32_t last, padn; + uint32_t high, low; + unsigned char msglen[8]; + + high = ( ctx->total[0] >> 29 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT32_BE( high, msglen, 0 ); + PUT_UINT32_BE( low, msglen, 4 ); + + last = ctx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + mbedtls_sha1_update( ctx, sha_padding, padn ); + mbedtls_sha1_update( ctx, msglen, 8 ); + + for ( size_t i = 0; i < 20; i+=4) { + *((uint32_t*)(&output[i])) = __REV(ctx->state[i >> 2]); + } +} + +/* Internal use */ +void mbedtls_sha1_process( mbedtls_sha1_context *ctx, + const unsigned char data[64] ) +{ + crypto_sha_update_state( ctx->state, data, 1, CRYPTO_SHA1 ); +} + +#endif /* defined(MBEDTLS_SHA1_ALT) && defined(MBEDTLS_SHA1_C) */ + +#endif /* #if defined(CRYPTO_PRESENT) */ + +#endif /* #if ( defined(MBEDTLS_SHA256_ALT) && defined(MBEDTLS_SHA256_C) ) || ( defined(MBEDTLS_SHA1_ALT) && defined (MBEDTLS_SHA1_C) ) */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/mbedtls_device.h b/features/mbedtls/targets/TARGET_Silicon_Labs/mbedtls_device.h new file mode 100644 index 00000000000..d76aba13c6f --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/mbedtls_device.h @@ -0,0 +1,42 @@ +/* + * mbed OS configuration header for mbed TLS HW acceleration + * + * Copyright (C) 2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_DEVICE_H +#define MBEDTLS_DEVICE_H + +#include "em_device.h" + +#if defined ( AES_PRESENT ) +#define MBEDTLS_AES_ALT +#endif + +#if defined ( CRYPTO_PRESENT ) +#define MBEDTLS_AES_ALT + +#define MBEDTLS_ECP_INTERNAL_ALT +#define MBEDTLS_ECP_ADD_MIXED_ALT +#define MBEDTLS_ECP_DOUBLE_JAC_ALT +#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT +#define MBEDTLS_ECP_NORMALIZE_JAC_ALT +#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT + +#define MBEDTLS_SHA1_ALT +#define MBEDTLS_SHA256_ALT +#endif + +#endif /* MBEDTLS_DEVICE_H */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/sha1_alt.h b/features/mbedtls/targets/TARGET_Silicon_Labs/sha1_alt.h new file mode 100644 index 00000000000..891b0655c88 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/sha1_alt.h @@ -0,0 +1,113 @@ +/** + * \file sha1_alt.h + * + * \brief SHA-1 cryptographic hash function + * + * Copyright (C) 2015-2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SHA1_ALT_H +#define MBEDTLS_SHA1_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_sha1 SHA-1 cryptographic hash function + * \brief CRYPTO hardware accelerated SHA-1 cryptographic hash function. + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA1_ALT) + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-1 context structure + */ +typedef struct +{ + uint32_t state[8]; /*!< intermediate digest state */ + uint32_t total[2]; /*!< number of bytes processed */ + unsigned char buffer[64]; /*!< data block being processed */ +} +mbedtls_sha1_context; + +/** + * \brief Initialize SHA-1 context + * + * \param ctx SHA-1 context to be initialized + */ +void mbedtls_sha1_init( mbedtls_sha1_context *ctx ); + +/** + * \brief Clear SHA-1 context + * + * \param ctx SHA-1 context to be cleared + */ +void mbedtls_sha1_free( mbedtls_sha1_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-1 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void mbedtls_sha1_clone( mbedtls_sha1_context *dst, + const mbedtls_sha1_context *src ); + +/** + * \brief SHA-1 context setup + * + * \param ctx context to be initialized + */ +void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void mbedtls_sha1_update( mbedtls_sha1_context *ctx, const unsigned char *input, size_t ilen ); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void mbedtls_sha1_finish( mbedtls_sha1_context *ctx, unsigned char output[20] ); + +/* Internal use */ +void mbedtls_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] ); + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_SHA1_ALT) */ + +/** \} (end addtogroup sl_crypto_sha1) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* #ifndef MBEDTLS_SHA1_ALT_H */ diff --git a/features/mbedtls/targets/TARGET_Silicon_Labs/sha256_alt.h b/features/mbedtls/targets/TARGET_Silicon_Labs/sha256_alt.h new file mode 100644 index 00000000000..5a7bf9a6766 --- /dev/null +++ b/features/mbedtls/targets/TARGET_Silicon_Labs/sha256_alt.h @@ -0,0 +1,120 @@ +/** + * \file sha256_alt.h + * + * \brief SHA-224 and SHA-256 cryptographic hash function + * + * Copyright (C) 2015-2016, Silicon Labs, http://www.silabs.com + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBEDTLS_SHA256_ALT_H +#define MBEDTLS_SHA256_ALT_H + +/***************************************************************************//** + * \addtogroup sl_crypto + * \{ + ******************************************************************************/ + +/***************************************************************************//** + * \addtogroup sl_crypto_sha256 SHA-224 and SHA-256 cryptographic hash function + * \brief CRYPTO hardware accelerated SHA-224 and SHA-256 cryptographic hash function. + * \{ + ******************************************************************************/ + +#if defined(MBEDTLS_SHA256_ALT) + +/* SiliconLabs CRYPTO hardware acceleration implementation */ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SHA-256 context structure + */ +typedef struct +{ + uint32_t state[8]; /*!< intermediate digest state */ + uint32_t total[2]; /*!< number of bytes processed */ + unsigned char buffer[64]; /*!< data block being processed */ + bool is224; /*!< false => SHA-256, else SHA-224 */ +} +mbedtls_sha256_context; + +/** + * \brief Initialize SHA-256 context + * + * \param ctx SHA-256 context to be initialized + */ +void mbedtls_sha256_init( mbedtls_sha256_context *ctx ); + +/** + * \brief Clear SHA-256 context + * + * \param ctx SHA-256 context to be cleared + */ +void mbedtls_sha256_free( mbedtls_sha256_context *ctx ); + +/** + * \brief Clone (the state of) a SHA-256 context + * + * \param dst The destination context + * \param src The context to be cloned + */ +void mbedtls_sha256_clone( mbedtls_sha256_context *dst, + const mbedtls_sha256_context *src ); + +/** + * \brief SHA-256 context setup + * + * \param ctx context to be initialized + * \param is224 0 = use SHA256, 1 = use SHA224 + */ +void mbedtls_sha256_starts( mbedtls_sha256_context *ctx, int is224 ); + +/** + * \brief SHA-256 process buffer + * + * \param ctx SHA-256 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void mbedtls_sha256_update( mbedtls_sha256_context *ctx, const unsigned char *input, + size_t ilen ); + +/** + * \brief SHA-256 final digest + * + * \param ctx SHA-256 context + * \param output SHA-224/256 checksum result + */ +void mbedtls_sha256_finish( mbedtls_sha256_context *ctx, unsigned char output[32] ); + +/* Internal use */ +void mbedtls_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] ); + +#ifdef __cplusplus +} +#endif + +#endif /* #if defined(MBEDTLS_SHA256_ALT) */ + +/** \} (end addtogroup sl_crypto_sha256) */ +/** \} (end addtogroup sl_crypto) */ + +#endif /* #ifndef MBEDTLS_SHA256_ALT_H */ diff --git a/features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar b/features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar index 6538cddcd4a..ddd60a6b1f3 100644 Binary files a/features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar and b/features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar differ diff --git a/features/nanostack/FEATURE_ETHERNET_HOST/TOOLCHAIN_ARM/TARGET_M3/libnanostack.ar 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files a/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_M3/libnanostack.a and b/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_M3/libnanostack.a differ diff --git a/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a b/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a index 31b0ce5c865..321bfb8782b 100644 Binary files a/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a and b/features/nanostack/FEATURE_LOWPAN_ROUTER/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/libnanostack.a differ diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c index 5b589d8842c..e3eab47677e 100644 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c +++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/source/nd_tasklet.c @@ -23,6 +23,7 @@ #include "include/nd_tasklet.h" #include "include/mesh_system.h" #include "ns_event_loop.h" +#include "multicast_api.h" // For tracing we need to define flag, have include and define group #define HAVE_DEBUG 1 @@ -265,6 +266,13 @@ void nd_tasklet_configure_and_connect_to_network(void) tasklet_data_ptr->network_interface_id, MBED_CONF_MBED_MESH_API_6LOWPAN_ND_PANID_FILTER); + // Enable MPL by default + const uint8_t all_mpl_forwarders[16] = {0xff, 0x03, [15]=0xfc}; + multicast_mpl_domain_subscribe(tasklet_data_ptr->network_interface_id, + all_mpl_forwarders, + MULTICAST_MPL_SEED_ID_DEFAULT, + NULL); + status = arm_nwk_interface_up(tasklet_data_ptr->network_interface_id); if (status >= 0) { tasklet_data_ptr->tasklet_state = TASKLET_STATE_BOOTSTRAP_STARTED; diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h index b0c0375bc34..8a7c84c05be 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/nanostack/net_test_api.h @@ -23,7 +23,7 @@ #include "ns_types.h" /** - * \brief Makes TCP protocol drop given number of packets from a particular state (TX side, tcp_down()). + * \brief Makes TCP protocol drop given number of packets from a particular state (TX side). * * Testing API for TCP retransmission mechanism after a packet is dropped in a particular state. * @@ -35,7 +35,7 @@ int8_t arm_nwk_test_tcp_drop_tx(int state, uint8_t count); /** - * \brief Makes TCP protocol drop given number of packets from a particular state (RX side, tcp_up()). + * \brief Makes TCP protocol drop given number of packets from a particular state (RX side). * * Testing API for TCP to drop received packets. * diff --git a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp index 875abbb48a7..3b91b01aa66 100644 --- a/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp +++ b/features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp @@ -14,15 +14,66 @@ * limitations under the License. */ #include "NanostackRfPhyEfr32.h" + +#include + +#include "mbed.h" #include "ns_types.h" #include "platform/arm_hal_interrupt.h" #include "nanostack/platform/arm_hal_phy.h" #include "mbed_toolchain.h" -#include #include "mbed-trace/mbed_trace.h" #define TRACE_GROUP "SLRF" +/* Enable debug printing with SL_RADIO_DEBUG, override debug printer with SL_DEBUG_PRINT. */ +#ifdef SL_RADIO_DEBUG +#ifndef SL_DEBUG_PRINT +#define SL_DEBUG_PRINT(...) tr_debug(__VA_ARGS__) +#endif +#else +#define SL_DEBUG_PRINT(...) +#endif + +/* RF_THREAD_STACK_SIZE defines tack size for the RF adaptor thread */ +#ifndef RF_THREAD_STACK_SIZE +#define RF_THREAD_STACK_SIZE 1024 +#endif + +/* RF_QUEUE_SIZE defines queue size for incoming messages */ +#ifndef RF_QUEUE_SIZE +#define RF_QUEUE_SIZE 8 +#endif + + +/* RFThreadSignal used to signal from interrupts to the adaptor thread */ +enum RFThreadSignal { + SL_RX_DONE = (1 << 1), + SL_TX_DONE = (1 << 2), + SL_TX_ERR = (1 << 3), + SL_TX_TIMEOUT = (1 << 4), + SL_ACK_RECV = (1 << 5), + SL_ACK_TIMEOUT = (1 << 6), + SL_TXFIFO_ERR = (1 << 7), + SL_RXFIFO_ERR = (1 << 8), + SL_CAL_REQ = (1 << 9), + SL_RSSI_DONE = (1 << 10), + SL_QUEUE_FULL = (1 << 11), + + // ACK pend flag can be signalled in addition to RX_DONE + SL_ACK_PEND = (1 << 31), +}; + +/* Adaptor thread definitions */ +static void rf_thread_loop(const void *arg); +static osThreadDef(rf_thread_loop, osPriorityRealtime, RF_THREAD_STACK_SIZE); +static osThreadId rf_thread_id; + +/* Queue for passing messages from interrupt to adaptor thread */ +static volatile void* rx_queue[8]; +static volatile size_t rx_queue_head; +static volatile size_t rx_queue_tail; + /* Silicon Labs headers */ extern "C" { #include "rail/rail.h" @@ -64,10 +115,11 @@ typedef enum { static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_GHz_OQPSK_CSMA; -#if defined(TARGET_EFR32MG1) +#if defined(TARGET_EFR32MG1) || defined(TARGET_EFR32FG1) #include "ieee802154_subg_efr32xg1_configurator_out.h" #include "ieee802154_efr32xg1_configurator_out.h" -#elif defined(TARGET_EFR32MG12) +#elif defined(TARGET_EFR32MG12) || defined(TARGET_EFR32FG12) +#include "ieee802154_efr32xg12_configurator_out.h" #include "ieee802154_efr32xg12_configurator_out.h" #else #error "Not a valid target." @@ -152,6 +204,75 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h /* Local function prototypes */ static bool rail_checkAndSwitchChannel(uint8_t channel); +static void rf_thread_loop(const void *arg) +{ + SL_DEBUG_PRINT("rf_thread_loop: starting (id: %d)\n", rf_thread_id); + for (;;) { + osEvent event = osSignalWait(0, osWaitForever); + + if (event.status != osEventSignal) { + continue; + } + + platform_enter_critical(); + + if (event.value.signals & SL_RX_DONE) { + while(rx_queue_tail != rx_queue_head) { + void* handle = (void*) rx_queue[rx_queue_tail]; + RAIL_RxPacketInfo_t* info = (RAIL_RxPacketInfo_t*) memoryPtrFromHandle(handle); + device_driver.phy_rx_cb( + info->dataPtr + 1, + info->dataLength - 1, + info->appendedInfo.lqi, + info->appendedInfo.rssiLatch, + rf_radio_driver_id); + + memoryFree(handle); + rx_queue[rx_queue_tail] = NULL; + rx_queue_tail = (rx_queue_tail + 1) % RF_QUEUE_SIZE; + } + + } else if (event.value.signals & SL_TX_DONE) { + device_driver.phy_tx_done_cb(rf_radio_driver_id, + current_tx_handle, + PHY_LINK_TX_SUCCESS, + 1, + 1); + } else if (event.value.signals & SL_ACK_RECV) { + device_driver.phy_tx_done_cb( rf_radio_driver_id, + current_tx_handle, + (event.value.signals & SL_ACK_PEND) ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, + 1, + 1); + } else if (event.value.signals & SL_ACK_TIMEOUT) { + waiting_for_ack = false; + device_driver.phy_tx_done_cb(rf_radio_driver_id, + current_tx_handle, + PHY_LINK_TX_FAIL, + 1, + 1); + } else if(event.value.signals & SL_TX_ERR) { + device_driver.phy_tx_done_cb( rf_radio_driver_id, + current_tx_handle, + PHY_LINK_CCA_FAIL, + 8, + 1); + } else if(event.value.signals & SL_CAL_REQ) { + SL_DEBUG_PRINT("rf_thread_loop: SL_CAL_REQ signal received (unhandled)\n"); + } else if(event.value.signals & SL_RXFIFO_ERR) { + SL_DEBUG_PRINT("rf_thread_loop: SL_RXFIFO_ERR signal received (unhandled)\n"); + } else if(event.value.signals & SL_TXFIFO_ERR) { + SL_DEBUG_PRINT("rf_thread_loop: SL_TXFIFO_ERR signal received (unhandled)\n"); + } else if(event.value.signals & SL_QUEUE_FULL) { + SL_DEBUG_PRINT("rf_thread_loop: SL_QUEUE_FULL signal received (packet dropped)\n"); + } else { + SL_DEBUG_PRINT("rf_thread_loop unhandled event status: %d value: %d\n", event.status, event.value.signals); + } + + platform_exit_critical(); + } +} + /*============ CODE =========*/ /* @@ -168,6 +289,8 @@ static int8_t rf_device_register(void) return -1; } + SL_DEBUG_PRINT("rf_device_register: entry\n"); + #if MBED_CONF_SL_RAIL_BAND == 2400 RADIO_PA_Init((RADIO_PAInit_t*)&paInit2p4); #elif (MBED_CONF_SL_RAIL_BAND == 915) || (MBED_CONF_SL_RAIL_BAND == 868) @@ -254,6 +377,12 @@ static int8_t rf_device_register(void) radio_state = RADIO_INITING; } +#ifdef MBED_CONF_RTOS_PRESENT + rx_queue_head = 0; + rx_queue_tail = 0; + rf_thread_id = osThreadCreate(osThread(rf_thread_loop), NULL); +#endif + return rf_radio_driver_id; } @@ -288,29 +417,31 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h switch(radio_state) { case RADIO_UNINIT: - tr_debug("Radio uninit\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio uninit\n"); return -1; case RADIO_INITING: - tr_debug("Radio initing\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio initing\n"); return -1; case RADIO_CALIBRATION: - tr_debug("Radio calibrating\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio calibrating\n"); return -1; case RADIO_TX: - tr_debug("Radio in TX mode\n"); + SL_DEBUG_PRINT("rf_start_cca: Radio in TX mode\n"); return -1; case RADIO_IDLE: case RADIO_RX: // If we're still waiting for an ACK, don't mess up the internal state if(waiting_for_ack || RAIL_RfStateGet() == RAIL_RF_STATE_TX) { if((RAIL_GetTime() - last_tx) < 30000) { - tr_debug("Still waiting on previous ACK\n"); + SL_DEBUG_PRINT("rf_start_cca: Still waiting on previous ACK\n"); return -1; } else { - tr_debug("TXerr\n"); + SL_DEBUG_PRINT("rf_start_cca: TXerr\n"); } } + platform_enter_critical(); + data_ptr[0] = data_length + 2; RAIL_RfIdleExt(RAIL_IDLE_ABORT , true); RAIL_TxDataLoad(&txData); @@ -325,21 +456,24 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h txOpt.waitForAck = false; } - //tr_debug("Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); + SL_DEBUG_PRINT("rf_start_cca: Called TX, len %d, chan %d, ack %d\n", data_length, channel, waiting_for_ack ? 1 : 0); if(RAIL_TxStartWithOptions(channel, &txOpt, &RAIL_CcaCsma, (RAIL_CsmaConfig_t*) &csma_config) == 0) { //Save packet number and sequence current_tx_handle = tx_handle; current_tx_sequence = data_ptr[3]; + platform_exit_critical(); return 0; } else { RAIL_RfIdle(); RAIL_RxStart(channel); radio_state = RADIO_RX; + platform_exit_critical(); return -1; } } //Should never get here... + platform_exit_critical(); return -1; } @@ -378,7 +512,7 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_ break; /* Enable wireless interface ED scan mode */ case PHY_INTERFACE_RX_ENERGY_STATE: - tr_debug("Energy det req\n"); + SL_DEBUG_PRINT("rf_interface_state_control: Energy det req\n"); // TODO: implement energy detection break; /* Enable RX in promiscuous mode (aka no address filtering) */ @@ -435,12 +569,15 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt /* Read status of the link */ case PHY_EXTENSION_READ_LINK_STATUS: // TODO: return accurate value here - tr_debug("Trying to read link status\n"); + SL_DEBUG_PRINT("rf_extension: Trying to read link status\n"); break; /* Convert between LQI and RSSI */ case PHY_EXTENSION_CONVERT_SIGNAL_INFO: // TODO: return accurate value here - tr_debug("Trying to read signal info\n"); + SL_DEBUG_PRINT("rf_extension: Trying to read signal info\n"); + break; + case PHY_EXTENSION_ACCEPT_ANY_BEACON: + SL_DEBUG_PRINT("rf_extension: Trying to accept any beacon\n"); break; } return 0; @@ -468,11 +605,11 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address case PHY_MAC_64BIT: /* Store MAC in MSB order */ memcpy(MAC_address, address_ptr, 8); - tr_debug("MACw "); + SL_DEBUG_PRINT("rf_address_write: MACw "); for(unsigned int i = 0; i < sizeof(MAC_address); i ++) { - tr_debug("%02x:", MAC_address[i]); + SL_DEBUG_PRINT("%02x:", MAC_address[i]); } - tr_debug("\n"); + SL_DEBUG_PRINT("\n"); /* Pass MAC to the RF driver in LSB order */ uint8_t MAC_reversed[8]; for(unsigned int i = 0; i < sizeof(MAC_address); i ++) { @@ -483,13 +620,11 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address /*Set 16-bit address*/ case PHY_MAC_16BIT: short_address = address_ptr[0] << 8 | address_ptr[1]; - tr_debug("Filter EUI16 %04x\n", short_address); RAIL_IEEE802154_SetShortAddress(short_address); break; /*Set PAN Id*/ case PHY_MAC_PANID: PAN_address = address_ptr[0] << 8 | address_ptr[1]; - tr_debug("Filter PAN %04x\n", PAN_address); RAIL_IEEE802154_SetPanId(PAN_address); break; } @@ -618,14 +753,19 @@ void RAILCb_TxRadioStatus(uint8_t status) { status == RAIL_TX_CONFIG_TX_ABORTED || status == RAIL_TX_CONFIG_TX_BLOCKED) { waiting_for_ack = false; - device_driver.phy_tx_done_cb( rf_radio_driver_id, +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_TX_ERR); + } +#else + device_driver.phy_tx_done_cb(rf_radio_driver_id, current_tx_handle, PHY_LINK_CCA_FAIL, 8, 1); } else { - tr_debug("Packet TX error %d\n", status); + SL_DEBUG_PRINT("Packet TX error %d\n", status); } +#endif } radio_state = RADIO_RX; } @@ -648,7 +788,6 @@ void RAILCb_RxRadioStatus(uint8_t status) { case RAIL_RX_CONFIG_ADDRESS_FILTERED: break; default: - tr_debug("RXE %d\n", status); break; } } @@ -663,7 +802,11 @@ void RAILCb_RxRadioStatus(uint8_t status) { */ void RAILCb_CalNeeded(void) { // TODO: Implement on-the-fly recalibration - tr_debug("!!!! Calling for calibration\n"); +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_CAL_REQ); +#else + SL_DEBUG_PRINT("!!!! Calling for calibration\n"); +#endif } /** @@ -691,6 +834,9 @@ void RAILCb_TimerExpired(void) { * callback. */ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo) { +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_TX_DONE); +#else if(device_driver.phy_tx_done_cb != NULL) { device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, @@ -700,6 +846,7 @@ void RAILCb_TxPacketSent(RAIL_TxPacketInfo_t *txPacketInfo) { 1, 1); } +#endif last_tx = RAIL_GetTime(); radio_state = RADIO_RX; } @@ -731,12 +878,16 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { /* Save the pending bit */ last_ack_pending_bit = (rxPacketInfo->dataPtr[1] & (1 << 4)) != 0; /* Tell the stack we got an ACK */ - //tr_debug("rACK\n"); +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_ACK_RECV | SL_ACK_PEND); +#else + SL_DEBUG_PRINT("rACK\n"); device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, last_ack_pending_bit ? PHY_LINK_TX_DONE_PENDING : PHY_LINK_TX_DONE, 1, 1); +#endif } else { /* Figure out whether we want to not ACK this packet */ @@ -752,14 +903,24 @@ void RAILCb_RxPacketReceived(void *rxPacketHandle) { RAIL_AutoAckCancelAck(); } - //tr_debug("rPKT %d\n", rxPacketInfo->dataLength); /* Feed the received packet into the stack */ +#ifdef MBED_CONF_RTOS_PRESENT + if (((rx_queue_head + 1) % RF_QUEUE_SIZE) != rx_queue_tail) { + memoryTakeReference(rxPacketHandle); + rx_queue[rx_queue_head] = rxPacketHandle; + rx_queue_head = (rx_queue_head + 1) % RF_QUEUE_SIZE; + osSignalSet(rf_thread_id, SL_RX_DONE); + } else { + osSignalSet(rf_thread_id, SL_QUEUE_FULL); + } +#else + SL_DEBUG_PRINT("rPKT %d\n", rxPacketInfo->dataLength); device_driver.phy_rx_cb(rxPacketInfo->dataPtr + 1, rxPacketInfo->dataLength - 1, - //TODO: take a new RAIL release that exposes LQI, or have LQI as function of RSSI - 255, + rxPacketInfo->appendedInfo.lqi, rxPacketInfo->appendedInfo.rssiLatch, rf_radio_driver_id); +#endif } } } @@ -792,13 +953,16 @@ void RAILCb_IEEE802154_DataRequestCommand(RAIL_IEEE802154_Address_t *address) { */ void RAILCb_RxAckTimeout(void) { if(waiting_for_ack) { - tr_debug("nACK\n"); waiting_for_ack = false; +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_ACK_TIMEOUT); +#else device_driver.phy_tx_done_cb( rf_radio_driver_id, current_tx_handle, PHY_LINK_TX_FAIL, 1, 1); +#endif } } @@ -849,7 +1013,11 @@ static bool rail_checkAndSwitchChannel(uint8_t newChannel) { * time of the callback dispatch. */ void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { - tr_debug("RX near full (%d)\n", bytesAvailable); +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_RXFIFO_ERR); +#else + SL_DEBUG_PRINT("RX near full (%d)\n", bytesAvailable); +#endif } /** @@ -871,7 +1039,11 @@ void RAILCb_RxFifoAlmostFull(uint16_t bytesAvailable) { * callback dispatch. */ void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { - tr_debug("TX near empty (%d)\n", spaceAvailable); +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_TXFIFO_ERR); +#else + SL_DEBUG_PRINT("TX near empty (%d)\n", spaceAvailable); +#endif } /** @@ -886,5 +1058,9 @@ void RAILCb_TxFifoAlmostEmpty(uint16_t spaceAvailable) { * get the result. */ void RAILCb_RssiAverageDone(int16_t avgRssi) { - tr_debug("RSSI done (%d)\n", avgRssi); +#ifdef MBED_CONF_RTOS_PRESENT + osSignalSet(rf_thread_id, SL_RSSI_DONE); +#else + SL_DEBUG_PRINT("RSSI done (%d)\n", avgRssi); +#endif } \ No newline at end of file diff --git a/features/nanostack/FEATURE_NANOSTACK_FULL/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar b/features/nanostack/FEATURE_NANOSTACK_FULL/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar index f86e07432fc..c6ba1183041 100644 Binary files a/features/nanostack/FEATURE_NANOSTACK_FULL/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar and b/features/nanostack/FEATURE_NANOSTACK_FULL/TOOLCHAIN_ARM/TARGET_LIKE_CORTEX_M0/libnanostack.ar differ diff --git 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b/features/netsocket/Socket.cpp index fd50083bc7e..7317648b65c 100644 --- a/features/netsocket/Socket.cpp +++ b/features/netsocket/Socket.cpp @@ -70,6 +70,28 @@ nsapi_error_t Socket::close() return ret; } +int Socket::modify_multicast_group(const SocketAddress &address, nsapi_socket_option_t socketopt) +{ + nsapi_ip_mreq_t mreq; + + // Set up group address + mreq.imr_multiaddr = address.get_addr(); + mreq.imr_interface = nsapi_addr_t(); // Default address, NSAPI_UNSPEC + + return this->setsockopt(NSAPI_SOCKET, socketopt, &mreq, sizeof(mreq)); +} + +int Socket::join_multicast_group(const SocketAddress &address) +{ + return modify_multicast_group(address, NSAPI_ADD_MEMBERSHIP); +} + +int Socket::leave_multicast_group(const SocketAddress &address) +{ + return modify_multicast_group(address, NSAPI_DROP_MEMBERSHIP); +} + + nsapi_error_t Socket::bind(uint16_t port) { // Underlying bind is thread safe diff --git a/features/netsocket/Socket.h b/features/netsocket/Socket.h index 7edeeb8033a..4040abe5be7 100644 --- a/features/netsocket/Socket.h +++ b/features/netsocket/Socket.h @@ -62,6 +62,20 @@ class Socket { */ nsapi_error_t close(); + /** Subscribes to an IP multicast group + * + * @param address Multicast group IP address + * @return Negative error code on failure + */ + int join_multicast_group(const SocketAddress &address); + + /** Leave an IP multicast group + * + * @param address Multicast group IP address + * @return Negative error code on failure + */ + int leave_multicast_group(const SocketAddress &address); + /** Bind a specific address to a socket * * Binding a socket specifies the address and port on which to recieve @@ -203,6 +217,7 @@ class Socket { Socket(); virtual nsapi_protocol_t get_proto() = 0; virtual void event() = 0; + int modify_multicast_group(const SocketAddress &address, nsapi_socket_option_t socketopt); NetworkStack *_stack; nsapi_socket_t _socket; diff --git a/features/netsocket/TCPSocket.h b/features/netsocket/TCPSocket.h index 8f7de421168..6005121484b 100644 --- a/features/netsocket/TCPSocket.h +++ b/features/netsocket/TCPSocket.h @@ -57,6 +57,11 @@ class TCPSocket : public Socket { */ virtual ~TCPSocket(); + /** Override multicast functions to return error for TCP + * + */ + int join_multicast_group(const SocketAddress &address) { return NSAPI_ERROR_UNSUPPORTED; } + /** Connects TCP socket to a remote host * * Initiates a connection to a remote server specified by either diff --git a/features/netsocket/UDPSocket.cpp b/features/netsocket/UDPSocket.cpp index 5b9f510d30a..cb6fbd67ce1 100644 --- a/features/netsocket/UDPSocket.cpp +++ b/features/netsocket/UDPSocket.cpp @@ -37,6 +37,7 @@ nsapi_protocol_t UDPSocket::get_proto() return NSAPI_UDP; } + nsapi_size_or_error_t UDPSocket::sendto(const char *host, uint16_t port, const void *data, nsapi_size_t size) { SocketAddress address; diff --git a/features/netsocket/nsapi_types.h b/features/netsocket/nsapi_types.h index 162c4082566..80663a80b38 100644 --- a/features/netsocket/nsapi_types.h +++ b/features/netsocket/nsapi_types.h @@ -53,6 +53,7 @@ enum nsapi_error { NSAPI_ERROR_IS_CONNECTED = -3015, /*!< socket is already connected */ NSAPI_ERROR_CONNECTION_LOST = -3016, /*!< connection lost */ NSAPI_ERROR_CONNECTION_TIMEOUT = -3017, /*!< connection timed out */ + NSAPI_ERROR_ADDRESS_IN_USE = -3018, /*!< Address already in use */ }; /** Type used to represent error codes @@ -158,7 +159,7 @@ typedef void *nsapi_socket_t; /** Enum of socket protocols * * The socket protocol specifies a particular protocol to - * be used with a newly created socket. + * be used with a newly created socket. * * @enum nsapi_protocol */ @@ -207,13 +208,15 @@ typedef enum nsapi_socket_level { * @enum nsapi_socket_option */ typedef enum nsapi_socket_option { - NSAPI_REUSEADDR, /*!< Allow bind to reuse local addresses */ - NSAPI_KEEPALIVE, /*!< Enables sending of keepalive messages */ - NSAPI_KEEPIDLE, /*!< Sets timeout value to initiate keepalive */ - NSAPI_KEEPINTVL, /*!< Sets timeout value for keepalive */ - NSAPI_LINGER, /*!< Keeps close from returning until queues empty */ - NSAPI_SNDBUF, /*!< Sets send buffer size */ - NSAPI_RCVBUF, /*!< Sets recv buffer size */ + NSAPI_REUSEADDR, /*!< Allow bind to reuse local addresses */ + NSAPI_KEEPALIVE, /*!< Enables sending of keepalive messages */ + NSAPI_KEEPIDLE, /*!< Sets timeout value to initiate keepalive */ + NSAPI_KEEPINTVL, /*!< Sets timeout value for keepalive */ + NSAPI_LINGER, /*!< Keeps close from returning until queues empty */ + NSAPI_SNDBUF, /*!< Sets send buffer size */ + NSAPI_RCVBUF, /*!< Sets recv buffer size */ + NSAPI_ADD_MEMBERSHIP, /*!< Add membership to multicast address */ + NSAPI_DROP_MEMBERSHIP, /*!< Drop membership to multicast address */ } nsapi_socket_option_t; /** Supported IP protocol versions of IP stack @@ -265,6 +268,13 @@ typedef struct nsapi_stack { unsigned _stack_buffer[16]; } nsapi_stack_t; +/** nsapi_ip_mreq structure + */ +typedef struct nsapi_ip_mreq { + nsapi_addr_t imr_multiaddr; /* IP multicast address of group */ + nsapi_addr_t imr_interface; /* local IP address of interface */ +} nsapi_ip_mreq_t; + /** nsapi_stack_api structure * * Common api structure for network stack operations. A network stack @@ -286,9 +296,9 @@ typedef struct nsapi_stack_api * * The hostname may be either a domain name or an IP address. If the * hostname is an IP address, no network transactions will be performed. - * + * * If no stack-specific DNS resolution is provided, the hostname - * will be resolve using a UDP socket on the stack. + * will be resolve using a UDP socket on the stack. * * @param stack Stack handle * @param addr Destination for the host IP address @@ -333,7 +343,7 @@ typedef struct nsapi_stack_api * @param optval Destination for option value * @param optlen Length of the option value * @return 0 on success, negative error code on failure - */ + */ nsapi_error_t (*getstackopt)(nsapi_stack_t *stack, int level, int optname, void *optval, unsigned *optlen); @@ -534,7 +544,7 @@ typedef struct nsapi_stack_api * @param optval Option value * @param optlen Length of the option value * @return 0 on success, negative error code on failure - */ + */ nsapi_error_t (*setsockopt)(nsapi_stack_t *stack, nsapi_socket_t socket, int level, int optname, const void *optval, unsigned optlen); @@ -551,7 +561,7 @@ typedef struct nsapi_stack_api * @param optval Destination for option value * @param optlen Length of the option value * @return 0 on success, negative error code on failure - */ + */ nsapi_error_t (*getsockopt)(nsapi_stack_t *stack, nsapi_socket_t socket, int level, int optname, void *optval, unsigned *optlen); } nsapi_stack_api_t; diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h index e79e01be476..594920d5e89 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h @@ -27,7 +27,8 @@ #define TARGET_DISCO_F746NG_OTG_HS #endif -#if defined(TARGET_DISCO_F769NI) || \ +#if defined(TARGET_DISCO_F429ZI) || \ + defined(TARGET_DISCO_F769NI) || \ defined(TARGET_DISCO_F746NG_OTG_HS) #define USBHAL_IRQn OTG_HS_IRQn #else @@ -101,6 +102,11 @@ USBHAL::USBHAL(void) { hpcd.Init.phy_itface = PCD_PHY_ULPI; hpcd.Init.Sof_enable = 0; hpcd.Init.speed = PCD_SPEED_HIGH; +#elif defined(TARGET_DISCO_F429ZI) + hpcd.Instance = USB_OTG_HS; + hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd.Init.Sof_enable = 0; + hpcd.Init.speed = PCD_SPEED_HIGH; #else hpcd.Instance = USB_OTG_FS; hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; @@ -151,6 +157,13 @@ USBHAL::USBHAL(void) { pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // SOF __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); +#elif defined(TARGET_DISCO_F429ZI) + __HAL_RCC_GPIOB_CLK_ENABLE(); + pin_function(PB_14, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_OTG_HS_FS)); // DM + pin_function(PB_15, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_OTG_HS_FS)); // DP + pin_function(PB_13, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); // VBUS + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + #elif defined(TARGET_DISCO_L475VG_IOT01A) || \ defined(TARGET_DISCO_L476VG) __HAL_RCC_GPIOA_CLK_ENABLE(); diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h index 1ed92bad54d..c9caa9c3d92 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h @@ -28,6 +28,7 @@ defined(TARGET_NUCLEO_F767ZI) || \ defined(TARGET_NUCLEO_F746ZG) || \ defined(TARGET_DISCO_F407VG) || \ + defined(TARGET_DISCO_F429ZI) || \ defined(TARGET_DISCO_F469NI) || \ defined(TARGET_DISCO_F746NG) || \ defined(TARGET_DISCO_F769NI) || \ diff --git a/features/unsupported/dsp/cmsis_dsp/arm_math.h b/features/unsupported/dsp/cmsis_dsp/arm_math.h index b1393de1a07..370c6fddd07 100644 --- a/features/unsupported/dsp/cmsis_dsp/arm_math.h +++ b/features/unsupported/dsp/cmsis_dsp/arm_math.h @@ -659,47 +659,6 @@ extern "C" return (signBits + 1); } - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - } -#endif /* end of ARM_MATH_CM0_FAMILY */ - - /* * @brief C custom defined intrinsic function for M3 and M0 processors */ diff --git a/hal/lp_ticker_api.h b/hal/lp_ticker_api.h index 73d8eb5a07d..d1ce69a102b 100644 --- a/hal/lp_ticker_api.h +++ b/hal/lp_ticker_api.h @@ -34,6 +34,20 @@ extern "C" { * @{ */ +typedef void (*ticker_irq_handler_type)(const ticker_data_t *const); + +/** Set low power ticker IRQ handler + * + * @param ticker_irq_handler IRQ handler to be connected + * + * @return previous ticker IRQ handler + * + * @note by default IRQ handler is set to ticker_irq_handler() + * @note this function is primarily for testing purposes and it's not required part of HAL implementation + * + */ +ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler); + /** Get low power ticker's data * * @return The low power ticker data @@ -80,6 +94,11 @@ void lp_ticker_clear_interrupt(void); */ void lp_ticker_fire_interrupt(void); +/** Get frequency and counter bits of this ticker. + * + */ +const ticker_info_t* lp_ticker_get_info(void); + /**@}*/ #ifdef __cplusplus diff --git a/hal/mbed_lp_ticker_api.c b/hal/mbed_lp_ticker_api.c index 501f7f9487f..6303247568e 100644 --- a/hal/mbed_lp_ticker_api.c +++ b/hal/mbed_lp_ticker_api.c @@ -19,6 +19,8 @@ static ticker_event_queue_t events = { 0 }; +static ticker_irq_handler_type irq_handler = ticker_irq_handler; + static const ticker_interface_t lp_interface = { .init = lp_ticker_init, .read = lp_ticker_read, @@ -26,6 +28,7 @@ static const ticker_interface_t lp_interface = { .clear_interrupt = lp_ticker_clear_interrupt, .set_interrupt = lp_ticker_set_interrupt, .fire_interrupt = lp_ticker_fire_interrupt, + .get_info = lp_ticker_get_info, }; static const ticker_data_t lp_data = { @@ -38,9 +41,20 @@ const ticker_data_t* get_lp_ticker_data(void) return &lp_data; } +ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler) +{ + ticker_irq_handler_type prev_irq_handler = irq_handler; + + irq_handler = ticker_irq_handler; + + return prev_irq_handler; +} + void lp_ticker_irq_handler(void) { - ticker_irq_handler(&lp_data); + if (irq_handler) { + irq_handler(&lp_data); + } } #endif diff --git a/hal/mbed_ticker_api.c b/hal/mbed_ticker_api.c index f4f8cfe7cc6..114a5a46289 100644 --- a/hal/mbed_ticker_api.c +++ b/hal/mbed_ticker_api.c @@ -17,6 +17,7 @@ #include #include "hal/ticker_api.h" #include "platform/mbed_critical.h" +#include "mbed_assert.h" static void schedule_interrupt(const ticker_data_t *const ticker); static void update_present_time(const ticker_data_t *const ticker); @@ -33,9 +34,31 @@ static void initialize(const ticker_data_t *ticker) } ticker->interface->init(); - + + const ticker_info_t *info = ticker->interface->get_info(); + uint32_t frequency = info->frequency; + if (info->frequency == 0) { + MBED_ASSERT(0); + frequency = 1000000; + } + + uint32_t bits = info->bits; + if ((info->bits > 32) || (info->bits < 4)) { + MBED_ASSERT(0); + bits = 32; + } + uint32_t max_delta = 0x7 << (bits - 4); // 7/16th + uint64_t max_delta_us = + ((uint64_t)max_delta * 1000000 + frequency - 1) / frequency; + ticker->queue->event_handler = NULL; ticker->queue->head = NULL; + ticker->queue->tick_last_read = ticker->interface->read(); + ticker->queue->tick_remainder = 0; + ticker->queue->frequency = frequency; + ticker->queue->bitmask = ((uint64_t)1 << bits) - 1; + ticker->queue->max_delta = max_delta; + ticker->queue->max_delta_us = max_delta_us; ticker->queue->present_time = 0; ticker->queue->initialized = true; @@ -86,53 +109,143 @@ static us_timestamp_t convert_timestamp(us_timestamp_t ref, timestamp_t timestam * Update the present timestamp value of a ticker. */ static void update_present_time(const ticker_data_t *const ticker) -{ - ticker->queue->present_time = convert_timestamp( - ticker->queue->present_time, - ticker->interface->read() - ); +{ + + ticker_event_queue_t *queue = ticker->queue; + uint32_t ticker_time = ticker->interface->read(); + if (ticker_time == ticker->queue->tick_last_read) { + // No work to do + return; + } + + uint64_t elapsed_ticks = (ticker_time - queue->tick_last_read) & queue->bitmask; + queue->tick_last_read = ticker_time; + + uint64_t elapsed_us; + if (1000000 == queue->frequency) { + // Optimized for 1MHz + + elapsed_us = elapsed_ticks; + } else if (32768 == queue->frequency) { + // Optimized for 32KHz + + uint64_t us_x_ticks = elapsed_ticks * 1000000; + elapsed_us = us_x_ticks >> 15; + + // Update remainder + queue->tick_remainder += us_x_ticks - (elapsed_us << 15); + if (queue->tick_remainder >= queue->frequency) { + elapsed_us += 1; + queue->tick_remainder -= queue->frequency; + } + } else { + // General case + + uint64_t us_x_ticks = elapsed_ticks * 1000000; + elapsed_us = us_x_ticks / queue->frequency; + + // Update remainder + queue->tick_remainder += us_x_ticks - elapsed_us * queue->frequency; + if (queue->tick_remainder >= queue->frequency) { + elapsed_us += 1; + queue->tick_remainder -= queue->frequency; + } + } + + // Update current time + queue->present_time += elapsed_us; +} + +/** + * Given the absolute timestamp compute the hal tick timestamp. + */ +static timestamp_t compute_tick(const ticker_data_t *const ticker, us_timestamp_t timestamp) +{ + ticker_event_queue_t *queue = ticker->queue; + us_timestamp_t delta_us = timestamp - queue->present_time; + + timestamp_t delta = ticker->queue->max_delta; + if (delta_us <= ticker->queue->max_delta_us) { + // Checking max_delta_us ensures the operation will not overflow + + if (1000000 == queue->frequency) { + // Optimized for 1MHz + + delta = delta_us; + if (delta > ticker->queue->max_delta) { + delta = ticker->queue->max_delta; + } + } else if (32768 == queue->frequency) { + // Optimized for 32KHz + + delta = (delta_us << 15) / 1000000; + if (delta > ticker->queue->max_delta) { + delta = ticker->queue->max_delta; + } + } else { + // General case + + delta = delta_us * queue->frequency / 1000000; + if (delta > ticker->queue->max_delta) { + delta = ticker->queue->max_delta; + } + } + } + return (queue->tick_last_read + delta) & queue->bitmask; +} + +/** + * Return 1 if the tick has incremented to or past match_tick, otherwise 0. + */ +int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick) +{ + if (match_tick > prev_tick) { + return (cur_tick >= match_tick) || (cur_tick < prev_tick); + } else { + return (cur_tick < prev_tick) && (cur_tick >= match_tick); + } } /** * Compute the time when the interrupt has to be triggered and schedule it. * * If there is no event in the queue or the next event to execute is in more - * than MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA us from now then the ticker - * irq will be scheduled in MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA us. - * Otherwise the irq will be scheduled to happen when the running counter reach - * the timestamp of the first event in the queue. + * than ticker.queue.max_delta ticks from now then the ticker irq will be + * scheduled in ticker.queue.max_delta ticks. Otherwise the irq will be + * scheduled to happen when the running counter reach the timestamp of the + * first event in the queue. * * @note If there is no event in the queue then the interrupt is scheduled to - * in MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA. This is necessary to keep track + * in ticker.queue.max_delta. This is necessary to keep track * of the timer overflow. */ static void schedule_interrupt(const ticker_data_t *const ticker) { + ticker_event_queue_t *queue = ticker->queue; update_present_time(ticker); - uint32_t relative_timeout = MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA; if (ticker->queue->head) { us_timestamp_t present = ticker->queue->present_time; - us_timestamp_t next_event_timestamp = ticker->queue->head->timestamp; + us_timestamp_t match_time = ticker->queue->head->timestamp; // if the event at the head of the queue is in the past then schedule // it immediately. - if (next_event_timestamp <= present) { + if (match_time <= present) { ticker->interface->fire_interrupt(); return; - } else if ((next_event_timestamp - present) < MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA) { - relative_timeout = next_event_timestamp - present; } - } - us_timestamp_t new_match_time = ticker->queue->present_time + relative_timeout; - ticker->interface->set_interrupt(new_match_time); - // there could be a delay, reread the time, check if it was set in the past - // As result, if it is already in the past, we fire it immediately - update_present_time(ticker); - us_timestamp_t present = ticker->queue->present_time; - if (present >= new_match_time) { - ticker->interface->fire_interrupt(); + timestamp_t match_tick = compute_tick(ticker, match_time); + ticker->interface->set_interrupt(match_tick); + timestamp_t cur_tick = ticker->interface->read(); + + if (_ticker_match_interval_passed(queue->tick_last_read, cur_tick, match_tick)) { + ticker->interface->fire_interrupt(); + } + } else { + uint32_t match_tick = + (queue->tick_last_read + queue->max_delta) & queue->bitmask; + ticker->interface->set_interrupt(match_tick); } } @@ -263,6 +376,7 @@ timestamp_t ticker_read(const ticker_data_t *const ticker) us_timestamp_t ticker_read_us(const ticker_data_t *const ticker) { + initialize(ticker); update_present_time(ticker); return ticker->queue->present_time; } diff --git a/hal/mbed_us_ticker_api.c b/hal/mbed_us_ticker_api.c index fb1663a5d38..69b533482bd 100644 --- a/hal/mbed_us_ticker_api.c +++ b/hal/mbed_us_ticker_api.c @@ -17,6 +17,8 @@ static ticker_event_queue_t events = { 0 }; +static ticker_irq_handler_type irq_handler = ticker_irq_handler; + static const ticker_interface_t us_interface = { .init = us_ticker_init, .read = us_ticker_read, @@ -24,6 +26,7 @@ static const ticker_interface_t us_interface = { .clear_interrupt = us_ticker_clear_interrupt, .set_interrupt = us_ticker_set_interrupt, .fire_interrupt = us_ticker_fire_interrupt, + .get_info = us_ticker_get_info, }; static const ticker_data_t us_data = { @@ -36,7 +39,18 @@ const ticker_data_t* get_us_ticker_data(void) return &us_data; } +ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler) +{ + ticker_irq_handler_type prev_irq_handler = irq_handler; + + irq_handler = ticker_irq_handler; + + return prev_irq_handler; +} + void us_ticker_irq_handler(void) { - ticker_irq_handler(&us_data); + if (irq_handler) { + irq_handler(&us_data); + } } diff --git a/hal/ticker_api.h b/hal/ticker_api.h index fceba2db87e..605fa235ed9 100644 --- a/hal/ticker_api.h +++ b/hal/ticker_api.h @@ -23,11 +23,6 @@ #include #include "device.h" -/** - * Maximum delta (in us) between too interrupts. - */ -#define MBED_TICKER_INTERRUPT_TIMESTAMP_MAX_DELTA 0x70000000ULL - /** * Legacy format representing a timestamp in us. * Given it is modeled as a 32 bit integer, this type can represent timestamp @@ -52,6 +47,14 @@ typedef struct ticker_event_s { typedef void (*ticker_event_handler)(uint32_t id); +/** Information about the ticker implementation + */ +typedef struct { + uint32_t frequency; /**< Frequency in Hz this ticker runs at */ + uint32_t bits; /**< Number of bits this ticker supports */ +} ticker_info_t; + + /** Ticker's interface structure - required API for a ticker */ typedef struct { @@ -61,6 +64,7 @@ typedef struct { void (*clear_interrupt)(void); /**< Clear interrupt function */ void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */ void (*fire_interrupt)(void); /**< Fire interrupt right-away */ + const ticker_info_t *(*get_info)(void); /**< Return info about this ticker's implementation */ } ticker_interface_t; /** Ticker's event queue structure @@ -68,6 +72,12 @@ typedef struct { typedef struct { ticker_event_handler event_handler; /**< Event handler */ ticker_event_t *head; /**< A pointer to head */ + uint32_t frequency; /**< Frequency of the timer in Hz */ + uint32_t bitmask; /**< Mask to be applied to time values read */ + uint32_t max_delta; /**< Largest delta in ticks that can be used when scheduling */ + uint64_t max_delta_us; /**< Largest delta in us that can be used when scheduling */ + uint32_t tick_last_read; /**< Last tick read */ + uint64_t tick_remainder; /**< Ticks that have not been added to base_time */ us_timestamp_t present_time; /**< Store the timestamp used for present time */ bool initialized; /**< Indicate if the instance is initialized */ } ticker_event_queue_t; @@ -132,8 +142,9 @@ void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, * * The event will be executed in timestamp - ticker_read_us() us. * - * @warning If an event is inserted with a timestamp less than the current - * timestamp then the event will **not** be inserted. + * @note If an event is inserted with a timestamp less than the current + * timestamp then the event will be scheduled immediately resulting in + * an instant call to event handler. * * @param ticker The ticker object. * @param obj The event object to be inserted to the queue @@ -170,6 +181,19 @@ us_timestamp_t ticker_read_us(const ticker_data_t *const ticker); */ int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp); +/* Private functions + * + * @cond PRIVATE + * + */ + +int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick); + +/* + * @endcond PRIVATE + * + */ + /**@}*/ #ifdef __cplusplus diff --git a/hal/us_ticker_api.h b/hal/us_ticker_api.h index b22fcc1d7bb..f880a555644 100644 --- a/hal/us_ticker_api.h +++ b/hal/us_ticker_api.h @@ -31,6 +31,20 @@ extern "C" { * @{ */ +typedef void (*ticker_irq_handler_type)(const ticker_data_t *const); + +/** Set ticker IRQ handler + * + * @param ticker_irq_handler IRQ handler to be connected + * + * @return previous ticker IRQ handler + * + * @note by default IRQ handler is set to ticker_irq_handler() + * @note this function is primarily for testing purposes and it's not required part of HAL implementation + * + */ +ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler); + /** Get ticker's data * * @return The low power ticker data @@ -78,6 +92,11 @@ void us_ticker_clear_interrupt(void); */ void us_ticker_fire_interrupt(void); +/** Get frequency and counter bits of this ticker. + * + */ +const ticker_info_t* us_ticker_get_info(void); + /**@}*/ #ifdef __cplusplus diff --git a/platform/ATCmdParser.cpp b/platform/ATCmdParser.cpp index 6200f1fa4b6..a787b58b2a2 100644 --- a/platform/ATCmdParser.cpp +++ b/platform/ATCmdParser.cpp @@ -380,3 +380,44 @@ void ATCmdParser::abort() { _aborted = true; } + +bool ATCmdParser::process_oob() +{ + if (!_fh->readable()) { + return false; + } + + int i = 0; + while (true) { + // Receive next character + int c = getc(); + if (c < 0) { + return false; + } + _buffer[i++] = c; + _buffer[i] = 0; + + // Check for oob data + struct oob *oob = _oobs; + while (oob) { + if (i == (int)oob->len && memcmp( + oob->prefix, _buffer, oob->len) == 0) { + debug_if(_dbg_on, "AT! %s\r\n", oob->prefix); + oob->cb(); + return true; + } + oob = oob->next; + } + + // Clear the buffer when we hit a newline or ran out of space + // running out of space usually means we ran into binary data + if (i+1 >= _buffer_size || + strcmp(&_buffer[i-_output_delim_size], _output_delimiter) == 0) { + + debug_if(_dbg_on, "AT< %s", _buffer); + i = 0; + } + } +} + + diff --git a/platform/ATCmdParser.h b/platform/ATCmdParser.h index 03b1ef6b2ac..c8fb0406340 100644 --- a/platform/ATCmdParser.h +++ b/platform/ATCmdParser.h @@ -24,6 +24,15 @@ #include #include "Callback.h" +namespace mbed { + +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_ATCmdParser ATCmdParser class + * @{ + */ + /** * Parser class for parsing AT commands * @@ -43,8 +52,6 @@ * @endcode */ -namespace mbed { - class ATCmdParser : private NonCopyable { private: @@ -288,7 +295,22 @@ class ATCmdParser : private NonCopyable * recv operation. */ void abort(); + + /** + * Process out-of-band data + * + * Process out-of-band data in the receive buffer. This function + * returns immediately if there is no data to process. + * + * @return true if oob data processed, false otherwise + */ + bool process_oob(void); }; + +/**@}*/ + +/**@}*/ + } //namespace mbed #endif //MBED_ATCMDPARSER_H diff --git a/platform/CThunk.h b/platform/CThunk.h index 90e150b6a9c..9942249c352 100644 --- a/platform/CThunk.h +++ b/platform/CThunk.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_CThunk CThunk class + * @{ + */ /* General C++ Object Thunking class * * - allows direct callbacks to non-static C++ class functions @@ -73,13 +77,11 @@ /* IRQ/Exception compatible thunk entry function */ typedef void (*CThunkEntry)(void); -/** @}*/ /** * Class for created a pointer with data bound to it * * @note Synchronization level: Not protected - * @ingroup platform */ template class CThunk @@ -220,15 +222,15 @@ class CThunk uint32_t start_addr = (uint32_t)&m_thunk & 0xFFFFFFE0; uint32_t end_addr = (uint32_t)&m_thunk + sizeof(m_thunk); uint32_t addr; - + /* Data cache clean and invalid */ for (addr = start_addr; addr < end_addr; addr += 0x20) { - __v7_clean_inv_dcache_mva((void *)addr); + L1C_CleanInvalidateDCacheMVA((void *)addr); } /* Instruction cache invalid */ - __v7_inv_icache_all(); - __ca9u_inv_tlb_all(); - __v7_inv_btac(); + L1C_InvalidateICacheAll(); + MMU_InvalidateTLB(); + L1C_InvalidateBTAC(); } #endif #if defined(__CORTEX_M7) @@ -243,5 +245,9 @@ class CThunk } }; +/**@}*/ + +/**@}*/ + #endif/*__CTHUNK_H__*/ diff --git a/platform/CallChain.cpp b/platform/CallChain.cpp index c9ee38c6e2e..ebddc0fedcb 100644 --- a/platform/CallChain.cpp +++ b/platform/CallChain.cpp @@ -1,3 +1,10 @@ + +// Suppress deprecation warnings since this whole +// class is deprecated already +#include "mbed_toolchain.h" +#undef MBED_DEPRECATED_SINCE +#define MBED_DEPRECATED_SINCE(...) + #include "platform/CallChain.h" #include "cmsis.h" #include "platform/mbed_critical.h" diff --git a/platform/CallChain.h b/platform/CallChain.h index 42e97e6d288..025a4a7a9eb 100644 --- a/platform/CallChain.h +++ b/platform/CallChain.h @@ -22,7 +22,17 @@ #include namespace mbed { + + +typedef Callback *pFunctionPointer_t; +class CallChainLink; + /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_CallChain CallChain class + * @{ + */ /** Group one or more functions in an instance of a CallChain, then call them in * sequence using CallChain::call(). Used mostly by the interrupt chaining code, @@ -60,19 +70,19 @@ namespace mbed { * chain.call(); * } * @endcode - * @ingroup platform */ - -typedef Callback *pFunctionPointer_t; -class CallChainLink; - class CallChain : private NonCopyable { public: /** Create an empty chain * * @param size (optional) Initial size of the chain */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") CallChain(int size = 4); + + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") virtual ~CallChain(); /** Add a function at the end of the chain @@ -82,6 +92,8 @@ class CallChain : private NonCopyable { * @returns * The function object created for 'func' */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t add(Callback func); /** Add a function at the end of the chain @@ -111,6 +123,8 @@ class CallChain : private NonCopyable { * @returns * The function object created for 'func' */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t add_front(Callback func); /** Add a function at the beginning of the chain @@ -135,6 +149,8 @@ class CallChain : private NonCopyable { /** Get the number of functions in the chain */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") int size() const; /** Get a function object from the chain @@ -144,6 +160,8 @@ class CallChain : private NonCopyable { * @returns * The function object at position 'i' in the chain */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t get(int i) const; /** Look for a function object in the call chain @@ -153,10 +171,14 @@ class CallChain : private NonCopyable { * @returns * The index of the function object if found, -1 otherwise. */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") int find(pFunctionPointer_t f) const; /** Clear the call chain (remove all functions in the chain). */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") void clear(); /** Remove a function object from the chain @@ -166,15 +188,24 @@ class CallChain : private NonCopyable { * @returns * true if the function object was found and removed, false otherwise. */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") bool remove(pFunctionPointer_t f); /** Call all the functions in the chain in sequence */ + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") void call(); + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") void operator ()(void) { call(); } + + MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the " + "public API of mbed-os and is being removed in the future.") pFunctionPointer_t operator [](int i) const { return get(i); } @@ -183,6 +214,10 @@ class CallChain : private NonCopyable { CallChainLink *_chain; }; +/**@}*/ + +/**@}*/ + } // namespace mbed #endif diff --git a/platform/Callback.h b/platform/Callback.h index cb2c5a95b30..b300afefadc 100644 --- a/platform/Callback.h +++ b/platform/Callback.h @@ -24,12 +24,15 @@ namespace mbed { /** \addtogroup platform */ - +/** @{*/ +/** + * \defgroup platform_Callback Callback class + * @{ + */ /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback; @@ -67,7 +70,6 @@ namespace detail { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -642,7 +644,6 @@ class Callback { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -1218,7 +1219,6 @@ class Callback { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -1795,7 +1795,6 @@ class Callback { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -2373,7 +2372,6 @@ class Callback { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -2952,7 +2950,6 @@ class Callback { /** Callback class based on template specialization * * @note Synchronization level: Not protected - * @ingroup platform */ template class Callback { @@ -4546,6 +4543,9 @@ Callback callback(const volatile U *obj, R (*func)(const return Callback(func, obj); } +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/CircularBuffer.h b/platform/CircularBuffer.h index bb7fd38c547..c6de50f066d 100644 --- a/platform/CircularBuffer.h +++ b/platform/CircularBuffer.h @@ -20,11 +20,15 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_CircularBuffer CircularBuffer functions + * @{ + */ /** Templated Circular buffer class * * @note Synchronization level: Interrupt safe - * @ingroup platform */ template class CircularBuffer { @@ -105,6 +109,23 @@ class CircularBuffer { core_util_critical_section_exit(); } + /** Get the number of elements currently stored in the circular_buffer */ + CounterType size() const { + core_util_critical_section_enter(); + CounterType elements; + if (!_full) { + if (_head < _tail) { + elements = BufferSize + _head - _tail; + } else { + elements = _head - _tail; + } + } else { + elements = BufferSize; + } + core_util_critical_section_exit(); + return elements; + } + private: T _pool[BufferSize]; volatile CounterType _head; @@ -112,6 +133,10 @@ class CircularBuffer { volatile bool _full; }; +/**@}*/ + +/**@}*/ + } #endif diff --git a/platform/CriticalSectionLock.h b/platform/CriticalSectionLock.h index 5199fbaf691..cb619769c8e 100644 --- a/platform/CriticalSectionLock.h +++ b/platform/CriticalSectionLock.h @@ -22,6 +22,13 @@ namespace mbed { +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_CriticalSectionLock CriticalSectionLock functions + * @{ + */ + /** RAII object for disabling, then restoring, interrupt state * Usage: * @code @@ -65,6 +72,9 @@ class CriticalSectionLock { } }; +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/DeepSleepLock.h b/platform/DeepSleepLock.h index ff5149d2e37..6b64022fc06 100644 --- a/platform/DeepSleepLock.h +++ b/platform/DeepSleepLock.h @@ -16,10 +16,18 @@ #ifndef MBED_DEEPSLEEPLOCK_H #define MBED_DEEPSLEEPLOCK_H +#include #include "platform/mbed_sleep.h" +#include "platform/mbed_critical.h" namespace mbed { +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_DeepSleepLock DeepSleepLock functions + * @{ + */ /** RAII object for disabling, then restoring the deep sleep mode * Usage: @@ -36,32 +44,55 @@ namespace mbed { * @endcode */ class DeepSleepLock { +private: + uint16_t _lock_count; + public: - DeepSleepLock() + DeepSleepLock(): _lock_count(1) { sleep_manager_lock_deep_sleep(); } ~DeepSleepLock() { - sleep_manager_unlock_deep_sleep(); + if (_lock_count) { + sleep_manager_unlock_deep_sleep(); + } } /** Mark the start of a locked deep sleep section */ void lock() { - sleep_manager_lock_deep_sleep(); + uint16_t count = core_util_atomic_incr_u16(&_lock_count, 1); + if (1 == count) { + sleep_manager_lock_deep_sleep(); + } + if (0 == count) { + error("DeepSleepLock overflow (> USHRT_MAX)"); + } } /** Mark the end of a locked deep sleep section */ void unlock() { - sleep_manager_unlock_deep_sleep(); + uint16_t count = core_util_atomic_decr_u16(&_lock_count, 1); + if (count == 0) { + sleep_manager_unlock_deep_sleep(); + } + if (count == USHRT_MAX) { + core_util_critical_section_exit(); + error("DeepSleepLock underflow (< 0)"); + } } }; +/**@}*/ + +/**@}*/ + + } #endif diff --git a/platform/DirHandle.h b/platform/DirHandle.h index b1dcfe2b1f0..116ebf581dc 100644 --- a/platform/DirHandle.h +++ b/platform/DirHandle.h @@ -23,6 +23,11 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_DirHandle DirHandle functions + * @{ + */ /** Represents a directory stream. Objects of this type are returned @@ -40,7 +45,6 @@ namespace mbed { * * @note to create a directory, @see Dir * @note Synchronization level: Set by subclass - * @ingroup platform */ class DirHandle : private NonCopyable { public: @@ -142,7 +146,9 @@ class DirHandle : private NonCopyable { virtual void seekdir(off_t location) { seek(location); } }; +/**@}*/ +/**@}*/ } // namespace mbed #endif /* MBED_DIRHANDLE_H */ diff --git a/platform/FileBase.h b/platform/FileBase.h index 5df9ef8550d..4f6371923b2 100644 --- a/platform/FileBase.h +++ b/platform/FileBase.h @@ -27,19 +27,22 @@ typedef int FILEHANDLE; #include "platform/NonCopyable.h" namespace mbed { -/** \addtogroup platform */ -/** @{*/ - + typedef enum { FilePathType, FileSystemPathType } PathType; -/** @}*/ +/** \addtogroup platform */ +/** @{*/ /** - * @class FileBase - * @ingroup platform + * \defgroup platform_FileBase FileBase class + * @{ */ +/** Class FileBase + * + */ + class FileBase : private NonCopyable { public: FileBase(const char *name, PathType t); @@ -62,6 +65,10 @@ class FileBase : private NonCopyable { const PathType _path_type; }; +/**@}*/ + +/**@}*/ + } // namespace mbed #endif diff --git a/platform/FileHandle.h b/platform/FileHandle.h index a6b306b3fa6..6a769b4b8f2 100644 --- a/platform/FileHandle.h +++ b/platform/FileHandle.h @@ -26,6 +26,11 @@ typedef int FILEHANDLE; namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_FileHandle FileHandle functions + * @{ + */ /** Class FileHandle @@ -36,7 +41,6 @@ namespace mbed { * * @note to create a file, @see File * @note Synchronization level: Set by subclass - * @ingroup platform */ class FileHandle : private NonCopyable { public: @@ -254,6 +258,11 @@ class FileHandle : private NonCopyable { std::FILE *fdopen(FileHandle *fh, const char *mode); +/**@}*/ + +/**@}*/ + + } // namespace mbed #endif diff --git a/platform/FileLike.h b/platform/FileLike.h index 91a3f304d09..e75be50bfd3 100644 --- a/platform/FileLike.h +++ b/platform/FileLike.h @@ -23,14 +23,17 @@ namespace mbed { /** \addtogroup platform */ - - -/* Class FileLike +/** @{*/ +/** + * \defgroup platform_FileLike FileLike class + * @{ + */ +/** Class FileLike + * * A file-like object is one that can be opened with fopen by * fopen("/name", mode). * * @note Synchronization level: Set by subclass - * @ingroup platform */ class FileLike : public FileHandle, public FileBase, private NonCopyable { public: @@ -42,6 +45,9 @@ class FileLike : public FileHandle, public FileBase, private NonCopyable { */ virtual int mkdir(const char *path, mode_t mode); }; +/**@}*/ +/**@}*/ } // namespace mbed diff --git a/platform/FileSystemLike.h b/platform/FileSystemLike.h index d8923391d6a..aef7913cf67 100644 --- a/platform/FileSystemLike.h +++ b/platform/FileSystemLike.h @@ -25,6 +25,11 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_FileSystemLike FileSystemLike functions + * @{ + */ /** A filesystem-like object is one that can be used to open file-like @@ -34,7 +39,6 @@ namespace mbed { * of the rest of the functions just return error values). * * @note Synchronization level: Set by subclass - * @ingroup platform */ class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopyable { public: @@ -79,6 +83,9 @@ class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopy } }; +/**@}*/ + +/**@}*/ } // namespace mbed diff --git a/platform/FunctionPointer.h b/platform/FunctionPointer.h index a57195f7a83..18c34c2106e 100644 --- a/platform/FunctionPointer.h +++ b/platform/FunctionPointer.h @@ -23,13 +23,14 @@ namespace mbed { /** \addtogroup platform */ - +/** @{*/ +/** + * \defgroup platform_FunctionPointer FunctionPointer class + * @{ + */ // Declarations for backwards compatibility // To be foward compatible, code should adopt the Callback class -/** - * @ingroup platform - */ template class FunctionPointerArg1 : public Callback { public: @@ -61,9 +62,6 @@ class FunctionPointerArg1 : public Callback { } }; -/** - * @ingroup platform - */ template class FunctionPointerArg1 : public Callback { public: @@ -97,6 +95,10 @@ class FunctionPointerArg1 : public Callback { typedef FunctionPointerArg1 FunctionPointer; +/**@}*/ + +/**@}*/ + } // namespace mbed diff --git a/platform/LocalFileSystem.h b/platform/LocalFileSystem.h index 3bd64d8377e..ce0baafaf07 100644 --- a/platform/LocalFileSystem.h +++ b/platform/LocalFileSystem.h @@ -27,9 +27,12 @@ namespace mbed { /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_LocalFileSystem LocalFileSystem functions + * @{ + */ FILEHANDLE local_file_open(const char* name, int flags); -/** @}*/ /** * @class LocalFileHandle @@ -112,6 +115,10 @@ class LocalFileSystem : public FileSystemLike, private NonCopyable { - * public: + * class Foo : private NonCopyable { + * public: * Foo() : _resource(new Resource()) { } - * ~Foo() { delete _resource; } + * ~Foo() { delete _resource; } * private: * Resource* _resource; * } - * - * @tparam T The type that should be made non copyable. It prevent cases where - * the empty base optimization cannot be applied and therefore ensure that the - * cost of this semantic sugar is null. - * - * As an example, the empty base optimization is prohibited if one of the empty - * base class is also a base type of the first non static data member: - * - * @code + * + * @tparam T The type that should be made non copyable. It prevent cases where + * the empty base optimization cannot be applied and therefore ensure that the + * cost of this semantic sugar is null. + * + * As an example, the empty base optimization is prohibited if one of the empty + * base class is also a base type of the first non static data member: + * + * @code * struct A { }; - * struct B : A { + * struct B : A { * int foo; * }; * // thanks to empty base optimization, sizeof(B) == sizeof(int) - * - * struct C : A { + * + * struct C : A { * B b; * }; - * + * * // empty base optimization cannot be applied here because A from C and A from - * // B shall have a different address. In that case, with the alignement + * // B shall have a different address. In that case, with the alignement * // sizeof(C) == 2* sizeof(int) * @endcode - * - * The solution to that problem is to templatize the empty class to makes it - * unique to the type it is applied to: - * - * @code + * + * The solution to that problem is to templatize the empty class to makes it + * unique to the type it is applied to: + * + * @code * template * struct A { }; - * struct B : A { + * struct B : A { * int foo; * }; - * struct C : A { + * struct C : A { * B b; * }; - * - * // empty base optimization can be applied B and C does not refer to the same + * + * // empty base optimization can be applied B and C does not refer to the same * // kind of A. sizeof(C) == sizeof(B) == sizeof(int). * @endcode + * + * @note Compile time errors are disabled if the develop or the release profile + * is used. To override this behavior and force compile time errors in all profile + * set the configuration parameter "platform.force-non-copyable-error" to true. */ template -class NonCopyable { +class NonCopyable { protected: - /** + /** * Disalow construction of NonCopyable objects from outside of its hierarchy. */ NonCopyable() { } - /** + /** * Disalow destruction of NonCopyable objects from outside of its hierarchy. */ ~NonCopyable() { } -private: +#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0)) + /** + * NonCopyable copy constructor. + * + * A compile time warning is issued when this function is used and a runtime + * warning is printed when the copy construction of the non copyable happens. + * + * If you see this warning, your code is probably doing something unspecified. + * Copy of non copyable resources can lead to resource leak and random error. + */ + MBED_DEPRECATED("Invalid copy construction of a NonCopyable resource.") + NonCopyable(const NonCopyable&) + { + debug("Invalid copy construction of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION); + } + + /** + * NonCopyable copy assignment operator. + * + * A compile time warning is issued when this function is used and a runtime + * warning is printed when the copy construction of the non copyable happens. + * + * If you see this warning, your code is probably doing something unspecified. + * Copy of non copyable resources can lead to resource leak and random error. + */ + MBED_DEPRECATED("Invalid copy assignment of a NonCopyable resource.") + NonCopyable& operator=(const NonCopyable&) + { + debug("Invalid copy assignment of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION); + return *this; + } + +#else +private: /** - * Declare copy constructor as private, any attempt to copy construct + * Declare copy constructor as private, any attempt to copy construct * a NonCopyable will fail at compile time. */ NonCopyable(const NonCopyable&); /** - * Declare copy assignement operator as private, any attempt to copy assign + * Declare copy assignement operator as private, any attempt to copy assign * a NonCopyable will fail at compile time. */ NonCopyable& operator=(const NonCopyable&); +#endif }; -} // namespace mbed +} // namespace mbed #endif /* MBED_NONCOPYABLE_H_ */ diff --git a/platform/PlatformMutex.h b/platform/PlatformMutex.h index 517fd3ad050..dc3b82bee6a 100644 --- a/platform/PlatformMutex.h +++ b/platform/PlatformMutex.h @@ -1,5 +1,10 @@ /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_PlatformMutex PlatformMutex class + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -25,7 +30,6 @@ typedef rtos::Mutex PlatformMutex; #else /** A stub mutex for when an RTOS is not present - * @ingroup platform */ class PlatformMutex : private mbed::NonCopyable { public: @@ -50,3 +54,6 @@ class PlatformMutex : private mbed::NonCopyable { #endif +/**@}*/ + +/**@}*/ diff --git a/platform/SingletonPtr.h b/platform/SingletonPtr.h index 369d6dbe2f1..848fd099f46 100644 --- a/platform/SingletonPtr.h +++ b/platform/SingletonPtr.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_SingletonPtr SingletonPtr class + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -55,7 +59,6 @@ inline static void singleton_unlock(void) osMutexRelease (singleton_mutex_id); #endif } -/** @}*/ /** Utility class for creating an using a singleton * @@ -68,7 +71,6 @@ inline static void singleton_unlock(void) * @note: This class is lazily initialized on first use. * This class is a POD type so if it is not used it will * be garbage collected. - * @ingroup platform */ template struct SingletonPtr { @@ -108,4 +110,6 @@ struct SingletonPtr { }; #endif +/**@}*/ +/**@}*/ diff --git a/platform/Stream.h b/platform/Stream.h index fd74b0520f1..20b7e44afcb 100644 --- a/platform/Stream.h +++ b/platform/Stream.h @@ -26,16 +26,18 @@ namespace mbed { /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_Stream Stream class + * @{ + */ extern void mbed_set_unbuffered_stream(std::FILE *_file); extern int mbed_getc(std::FILE *_file); extern char* mbed_gets(char *s, int size, std::FILE *_file); -/** @}*/ /** File stream * * @note Synchronization level: Set by subclass - * @ingroup platform */ class Stream : public FileLike, private NonCopyable { @@ -82,7 +84,9 @@ class Stream : public FileLike, private NonCopyable { // Stub } }; +/**@}*/ +/**@}*/ } // namespace mbed #endif diff --git a/platform/Transaction.h b/platform/Transaction.h index 8e262368800..23f03e07f22 100644 --- a/platform/Transaction.h +++ b/platform/Transaction.h @@ -21,9 +21,13 @@ namespace mbed { /** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_Transaction Transaction class + * @{ + */ /** Transaction structure - * @ingroup platform */ typedef struct { void *tx_buffer; /**< Tx buffer */ @@ -38,7 +42,6 @@ typedef struct { /** Transaction class defines a transaction. * * @note Synchronization level: Not protected - * @ingroup platform */ template class Transaction { @@ -72,7 +75,9 @@ class Transaction { Class* _obj; transaction_t _data; }; +/**@}*/ +/**@}*/ } #endif diff --git a/platform/mbed_application.h b/platform/mbed_application.h index 633b6a8572e..43b4813f755 100644 --- a/platform/mbed_application.h +++ b/platform/mbed_application.h @@ -1,6 +1,3 @@ - -/** \addtogroup platform */ -/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017-2017 ARM Limited * @@ -16,6 +13,7 @@ * See the License for the specific language governing permissions and * limitations under the License. */ + #ifndef MBED_APPLICATION_H #define MBED_APPLICATION_H @@ -52,4 +50,3 @@ void mbed_start_application(uintptr_t address); #endif -/** @}*/ diff --git a/platform/mbed_assert.h b/platform/mbed_assert.h index bd86983fc8b..8aecdcc3fa8 100644 --- a/platform/mbed_assert.h +++ b/platform/mbed_assert.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_Assert Assert macros + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -39,6 +43,19 @@ void mbed_assert_internal(const char *expr, const char *file, int line); } #endif +/** MBED_ASSERT + * Declare runtime assertions: results in runtime error if condition is false + * + * @note + * Use of MBED_ASSERT is limited to Debug and Develop builds. + * + * @code + * + * int Configure(serial_t *obj) { + * MBED_ASSERT(obj); + * } + * @endcode + */ #ifdef NDEBUG #define MBED_ASSERT(expr) ((void)0) @@ -110,4 +127,7 @@ do { \ #endif -/** @}*/ +/**@}*/ + +/**@}*/ + diff --git a/platform/mbed_critical.c b/platform/mbed_critical.c index 6afb48e5a99..db6c05bb2a0 100644 --- a/platform/mbed_critical.c +++ b/platform/mbed_critical.c @@ -39,10 +39,10 @@ bool core_util_is_isr_active(void) { #if defined(__CORTEX_A9) switch(__get_CPSR() & 0x1FU) { - case MODE_USR: - case MODE_SYS: + case CPSR_M_USR: + case CPSR_M_SYS: return false; - case MODE_SVC: + case CPSR_M_SVC: default: return true; } diff --git a/platform/mbed_critical.h b/platform/mbed_critical.h index 8aa314a8e99..0b7cb2a8b1a 100644 --- a/platform/mbed_critical.h +++ b/platform/mbed_critical.h @@ -1,6 +1,4 @@ -/** \addtogroup platform */ -/** @{*/ /* * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved * SPDX-License-Identifier: Apache-2.0 @@ -29,6 +27,12 @@ extern "C" { #endif +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_critical critical section function + * @{ + */ /** Determine the current interrupts enabled state * @@ -363,8 +367,11 @@ void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta); #ifdef __cplusplus } // extern "C" #endif +/**@}*/ +/**@}*/ #endif // __MBED_UTIL_CRITICAL_H__ -/** @}*/ + + diff --git a/platform/mbed_debug.h b/platform/mbed_debug.h index 761c1eb99f6..5f9a19805d6 100644 --- a/platform/mbed_debug.h +++ b/platform/mbed_debug.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_debug Debug functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -68,4 +73,7 @@ static inline void debug_if(int condition, const char *format, ...) { #endif -/** @}*/ +/**@}*/ + +/**@}*/ + diff --git a/platform/mbed_error.h b/platform/mbed_error.h index 1da55135b9e..8f5cd9baff1 100644 --- a/platform/mbed_error.h +++ b/platform/mbed_error.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_error Error functions + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -75,3 +79,4 @@ void error(const char* format, ...); #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_interface.h b/platform/mbed_interface.h index 538a6a7cbfd..94baa34f775 100644 --- a/platform/mbed_interface.h +++ b/platform/mbed_interface.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_interface Network interface and other utility functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -42,6 +47,11 @@ extern "C" { #if DEVICE_SEMIHOST +/** + * \defgroup platform_interface interface functions + * @{ + */ + /** Functions to control the mbed interface * * mbed Microcontrollers have a built-in interface to provide functionality such as @@ -137,6 +147,7 @@ void mbed_error_printf(const char* format, ...); * */ void mbed_error_vfprintf(const char * format, va_list arg); +/** @}*/ #ifdef __cplusplus } diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index 3185ed1886c..479b76cb907 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -19,6 +19,11 @@ "default-serial-baud-rate": { "help": "Default baud rate for a Serial or RawSerial instance (if not specified in the constructor)", "value": 9600 + }, + + "force-non-copyable-error": { + "help": "Force compile time error when a NonCopyable object is copied", + "value": false } }, "target_overrides": { diff --git a/platform/mbed_mem_trace.h b/platform/mbed_mem_trace.h index 0267255ba78..59da721e2fe 100644 --- a/platform/mbed_mem_trace.h +++ b/platform/mbed_mem_trace.h @@ -1,6 +1,7 @@ /** \addtogroup platform */ /** @{*/ + /* mbed Microcontroller Library * Copyright (c) 2006-2016 ARM Limited * @@ -35,6 +36,11 @@ enum { MBED_MEM_TRACE_FREE }; +/** + * \defgroup platform_mem_trace mem_trace functions + * @{ + */ + /* Prefix for the output of the default tracer */ #define MBED_MEM_DEFAULT_TRACER_PREFIX "#" @@ -133,6 +139,8 @@ void mbed_mem_trace_free(void *ptr, void *caller); */ void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...); +/** @}*/ + #ifdef __cplusplus } #endif diff --git a/platform/mbed_mktime.h b/platform/mbed_mktime.h index b28525224c4..dd302702e40 100644 --- a/platform/mbed_mktime.h +++ b/platform/mbed_mktime.h @@ -28,6 +28,11 @@ extern "C" { #endif +/** + * \defgroup platform_mktime mktime functions + * @{ + */ + /** Compute if a year is a leap year or not. * * @param year The year to test it shall be in the range [70:138]. Year 0 is @@ -89,6 +94,8 @@ time_t _rtc_mktime(const struct tm* calendar_time); */ bool _rtc_localtime(time_t timestamp, struct tm* calendar_time); +/** @}*/ + #ifdef __cplusplus } #endif diff --git a/platform/mbed_poll.cpp b/platform/mbed_poll.cpp index 28492010d42..c2a08fa3ddb 100644 --- a/platform/mbed_poll.cpp +++ b/platform/mbed_poll.cpp @@ -66,7 +66,7 @@ int poll(pollfh fhs[], unsigned nfhs, int timeout) #ifdef MBED_CONF_RTOS_PRESENT // TODO - proper blocking // wait for condition variable, wait queue whatever here - rtos::Thread::yield(); + rtos::Thread::wait(1); #endif } return count; diff --git a/platform/mbed_poll.h b/platform/mbed_poll.h index 635733bb98f..f9c894c21f6 100644 --- a/platform/mbed_poll.h +++ b/platform/mbed_poll.h @@ -27,7 +27,11 @@ namespace mbed { class FileHandle; /** \addtogroup platform */ - +/** @{*/ +/** + * \defgroup platform_poll poll functions + * @{ + */ struct pollfh { FileHandle *fh; @@ -47,6 +51,10 @@ struct pollfh { */ int poll(pollfh fhs[], unsigned nfhs, int timeout); +/**@}*/ + +/**@}*/ + } // namespace mbed #endif //MBED_POLL_H diff --git a/platform/mbed_preprocessor.h b/platform/mbed_preprocessor.h index 5e72d99f873..63312e8b13b 100644 --- a/platform/mbed_preprocessor.h +++ b/platform/mbed_preprocessor.h @@ -1,5 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_preprocessor preprocessor macros + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -51,3 +56,4 @@ #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_retarget.cpp b/platform/mbed_retarget.cpp index c9632c4c29b..124c6571da4 100644 --- a/platform/mbed_retarget.cpp +++ b/platform/mbed_retarget.cpp @@ -27,6 +27,8 @@ #include "platform/mbed_stats.h" #include "platform/mbed_critical.h" #include "platform/PlatformMutex.h" +#include "us_ticker_api.h" +#include "lp_ticker_api.h" #include #include #include @@ -61,7 +63,6 @@ static SingletonPtr _mutex; # define STDERR_FILENO 2 #else -# include # include # define PREFIX(x) x #endif @@ -252,7 +253,7 @@ extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) { /* The first part of the filename (between first 2 '/') is not a * registered mount point in the namespace. */ - return handle_open_errors(-ENOENT, fh_i); + return handle_open_errors(-ENODEV, fh_i); } if (path.isFile()) { @@ -260,7 +261,7 @@ extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) { } else { FileSystemHandle *fs = path.fileSystem(); if (fs == NULL) { - return handle_open_errors(-ENOENT, fh_i); + return handle_open_errors(-ENODEV, fh_i); } int posix_mode = openmode_to_posix(openmode); int err = fs->open(&res, path.fileName(), posix_mode); @@ -451,6 +452,7 @@ int _lseek(FILEHANDLE fh, int offset, int whence) #if defined(__ARMCC_VERSION) int whence = SEEK_SET; #endif + if (fh < 3) { errno = ESPIPE; return -1; @@ -541,13 +543,21 @@ extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uin #if !defined(__ARMCC_VERSION) && !defined(__ICCARM__) -extern "C" int _fstat(int fd, struct stat *st) { - if (fd < 3) { +extern "C" int _fstat(int fh, struct stat *st) { + if (fh < 3) { st->st_mode = S_IFCHR; return 0; } - errno = EBADF; - return -1; + + FileHandle* fhc = filehandles[fh-3]; + if (fhc == NULL) { + errno = EBADF; + return -1; + } + + st->st_mode = fhc->isatty() ? S_IFCHR : S_IFREG; + st->st_size = fhc->size(); + return 0; } #endif @@ -556,7 +566,7 @@ extern "C" int remove(const char *path) { FilePath fp(path); FileSystemHandle *fs = fp.fileSystem(); if (fs == NULL) { - errno = ENOENT; + errno = ENODEV; return -1; } @@ -576,7 +586,7 @@ extern "C" int rename(const char *oldname, const char *newname) { FileSystemHandle *fsNew = fpNew.fileSystem(); if (fsOld == NULL) { - errno = ENOENT; + errno = ENODEV; return -1; } @@ -616,7 +626,7 @@ extern "C" DIR *opendir(const char *path) { FilePath fp(path); FileSystemHandle* fs = fp.fileSystem(); if (fs == NULL) { - errno = ENOENT; + errno = ENODEV; return NULL; } @@ -668,7 +678,10 @@ extern "C" void seekdir(DIR *dir, off_t off) { extern "C" int mkdir(const char *path, mode_t mode) { FilePath fp(path); FileSystemHandle *fs = fp.fileSystem(); - if (fs == NULL) return -1; + if (fs == NULL) { + errno = ENODEV; + return -1; + } int err = fs->mkdir(fp.fileName(), mode); if (err < 0) { @@ -682,7 +695,10 @@ extern "C" int mkdir(const char *path, mode_t mode) { extern "C" int stat(const char *path, struct stat *st) { FilePath fp(path); FileSystemHandle *fs = fp.fileSystem(); - if (fs == NULL) return -1; + if (fs == NULL) { + errno = ENODEV; + return -1; + } int err = fs->stat(fp.fileName(), st); if (err < 0) { @@ -925,7 +941,11 @@ extern "C" WEAK void __iar_file_Mtxdst(__iar_Rmtx *mutex) {} extern "C" WEAK void __iar_file_Mtxlock(__iar_Rmtx *mutex) {} extern "C" WEAK void __iar_file_Mtxunlock(__iar_Rmtx *mutex) {} #if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ >= 8000000) -extern "C" WEAK void *__aeabi_read_tp (void) { return NULL ;} +#pragma section="__iar_tls$$DATA" +extern "C" WEAK void *__aeabi_read_tp (void) { + // Thread Local storage is not supported, using main thread memory for errno + return __section_begin("__iar_tls$$DATA"); +} #endif #elif defined(__CC_ARM) // Do nothing @@ -1049,9 +1069,28 @@ void operator delete[](void *ptr) extern "C" clock_t clock() { _mutex->lock(); - clock_t t = us_ticker_read(); + clock_t t = ticker_read(get_us_ticker_data()); t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time _mutex->unlock(); return t; } +// temporary - Default to 1MHz at 32 bits if target does not have us_ticker_get_info +MBED_WEAK const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + 1000000, + 32 + }; + return &info; +} + +// temporary - Default to 1MHz at 32 bits if target does not have lp_ticker_get_info +MBED_WEAK const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + 1000000, + 32 + }; + return &info; +} diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index 90d19fb0943..ac1abc04ed9 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -28,33 +28,45 @@ /* We can get the following standard types from sys/types for gcc, but we * need to define the types ourselves for the other compilers that normally * target embedded systems */ -#if defined(__ARMCC_VERSION) || defined(__ICCARM__) -typedef int ssize_t; ///< Signed size type, usually encodes negative errors -typedef long off_t; ///< Offset in a data stream -typedef int mode_t; ///< Mode for opening files - -#define O_RDONLY 0 -#define O_WRONLY 1 -#define O_RDWR 2 -#define O_CREAT 0x0200 -#define O_TRUNC 0x0400 -#define O_APPEND 0x0008 +typedef signed int ssize_t; ///< Signed size type, usually encodes negative errors +typedef signed long off_t; ///< Offset in a data stream +#if defined(__ARMCC_VERSION) || !defined(__GNUC__) +typedef unsigned int mode_t; ///< Mode for opening files +typedef unsigned int dev_t; ///< Device ID type +typedef unsigned long ino_t; ///< File serial number +typedef unsigned int nlink_t; ///< Number of links to a file +typedef unsigned int uid_t; ///< User ID +typedef unsigned int gid_t; ///< Group ID +#endif + +#define O_RDONLY 0 ///< Open for reading +#define O_WRONLY 1 ///< Open for writing +#define O_RDWR 2 ///< Open for reading and writing +#define O_CREAT 0x0200 ///< Create file if it does not exist +#define O_TRUNC 0x0400 ///< Truncate file to zero length +#define O_EXCL 0x0800 ///< Fail if file exists +#define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write +#define O_BINARY 0x8000 ///< Open file in binary mode #define NAME_MAX 255 ///< Maximum size of a name in a file path -#else -#include -#include -#include -#endif +#include +/** \addtogroup platform */ +/** @{*/ +/** + * \defgroup platform_retarget Retarget functions + * @{ + */ /* DIR declarations must also be here */ #if __cplusplus namespace mbed { + class FileHandle; class DirHandle; std::FILE *mbed_fdopen(FileHandle *fh, const char *mode); + } typedef mbed::DirHandle DIR; #else @@ -76,114 +88,363 @@ extern "C" { #endif -#if defined(__ARMCC_VERSION) || defined(__ICCARM__) /* The intent of this section is to unify the errno error values to match * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some * symbol definitions used by the POSIX filesystem API to return errno codes. * Note also that ARMCC errno.h defines some symbol values differently from * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against - * this and future changes by changing the symbol definition as shown below. */ -#undef ENOENT -#define ENOENT 2 /* No such file or directory. */ - -#undef EIO -#define EIO 5 /* I/O error */ - -#undef ENXIO -#define ENXIO 6 /* No such device or address */ - -#undef ENOEXEC -#define ENOEXEC 8 /* Exec format error */ - -#undef EBADF -#define EBADF 9 /* Bad file number */ - -#undef EAGAIN -#define EAGAIN 11 /* Resource unavailable, try again */ - -#undef EWOULDBLOCK -#define EWOULDBLOCK EAGAIN /* Operation would block */ - -#undef ENOMEM -#define ENOMEM 12 /* Not enough space */ - -#undef EACCES -#define EACCES 13 /* Permission denied */ - -#undef EFAULT -#define EFAULT 14 /* Bad address */ - -#undef EEXIST -#define EEXIST 17 /* File exists */ - -#undef EXDEV -#define EXDEV 18 /* Cross-device link */ - -#undef ENODEV -#define ENODEV 19 - -#undef EINVAL -#define EINVAL 22 /* Invalid argument */ - -#undef ENFILE -#define ENFILE 23 /* Too many open files in system */ - -#undef EMFILE -#define EMFILE 24 /* File descriptor value too large */ - -#undef ESPIPE -#define ESPIPE 29 /* Invalid seek */ - -#undef ENOSYS -#define ENOSYS 38 /* Function not implemented */ - -#undef EOVERFLOW -#define EOVERFLOW 75 /* Value too large to be stored in data type */ + * this and future changes by changing the symbol definition as shown below. + */ +#undef EPERM +#define EPERM 1 /* Operation not permitted */ +#undef ENOENT +#define ENOENT 2 /* No such file or directory */ +#undef ESRCH +#define ESRCH 3 /* No such process */ +#undef EINTR +#define EINTR 4 /* Interrupted system call */ +#undef EIO +#define EIO 5 /* I/O error */ +#undef ENXIO +#define ENXIO 6 /* No such device or address */ +#undef E2BIG +#define E2BIG 7 /* Argument list too long */ +#undef ENOEXEC +#define ENOEXEC 8 /* Exec format error */ +#undef EBADF +#define EBADF 9 /* Bad file number */ +#undef ECHILD +#define ECHILD 10 /* No child processes */ +#undef EAGAIN +#define EAGAIN 11 /* Try again */ +#undef ENOMEM +#define ENOMEM 12 /* Out of memory */ +#undef EACCES +#define EACCES 13 /* Permission denied */ +#undef EFAULT +#define EFAULT 14 /* Bad address */ +#undef ENOTBLK +#define ENOTBLK 15 /* Block device required */ +#undef EBUSY +#define EBUSY 16 /* Device or resource busy */ +#undef EEXIST +#define EEXIST 17 /* File exists */ +#undef EXDEV +#define EXDEV 18 /* Cross-device link */ +#undef ENODEV +#define ENODEV 19 /* No such device */ +#undef ENOTDIR +#define ENOTDIR 20 /* Not a directory */ +#undef EISDIR +#define EISDIR 21 /* Is a directory */ +#undef EINVAL +#define EINVAL 22 /* Invalid argument */ +#undef ENFILE +#define ENFILE 23 /* File table overflow */ +#undef EMFILE +#define EMFILE 24 /* Too many open files */ +#undef ENOTTY +#define ENOTTY 25 /* Not a typewriter */ +#undef ETXTBSY +#define ETXTBSY 26 /* Text file busy */ +#undef EFBIG +#define EFBIG 27 /* File too large */ +#undef ENOSPC +#define ENOSPC 28 /* No space left on device */ +#undef ESPIPE +#define ESPIPE 29 /* Illegal seek */ +#undef EROFS +#define EROFS 30 /* Read-only file system */ +#undef EMLINK +#define EMLINK 31 /* Too many links */ +#undef EPIPE +#define EPIPE 32 /* Broken pipe */ +#undef EDOM +#define EDOM 33 /* Math argument out of domain of func */ +#undef ERANGE +#define ERANGE 34 /* Math result not representable */ +#undef EDEADLK +#define EDEADLK 35 /* Resource deadlock would occur */ +#undef ENAMETOOLONG +#define ENAMETOOLONG 36 /* File name too long */ +#undef ENOLCK +#define ENOLCK 37 /* No record locks available */ +#undef ENOSYS +#define ENOSYS 38 /* Function not implemented */ +#undef ENOTEMPTY +#define ENOTEMPTY 39 /* Directory not empty */ +#undef ELOOP +#define ELOOP 40 /* Too many symbolic links encountered */ +#undef EWOULDBLOCK +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#undef ENOMSG +#define ENOMSG 42 /* No message of desired type */ +#undef EIDRM +#define EIDRM 43 /* Identifier removed */ +#undef ECHRNG +#define ECHRNG 44 /* Channel number out of range */ +#undef EL2NSYNC +#define EL2NSYNC 45 /* Level 2 not synchronized */ +#undef EL3HLT +#define EL3HLT 46 /* Level 3 halted */ +#undef EL3RST +#define EL3RST 47 /* Level 3 reset */ +#undef ELNRNG +#define ELNRNG 48 /* Link number out of range */ +#undef EUNATCH +#define EUNATCH 49 /* Protocol driver not attached */ +#undef ENOCSI +#define ENOCSI 50 /* No CSI structure available */ +#undef EL2HLT +#define EL2HLT 51 /* Level 2 halted */ +#undef EBADE +#define EBADE 52 /* Invalid exchange */ +#undef EBADR +#define EBADR 53 /* Invalid request descriptor */ +#undef EXFULL +#define EXFULL 54 /* Exchange full */ +#undef ENOANO +#define ENOANO 55 /* No anode */ +#undef EBADRQC +#define EBADRQC 56 /* Invalid request code */ +#undef EBADSLT +#define EBADSLT 57 /* Invalid slot */ +#undef EDEADLOCK +#define EDEADLOCK EDEADLK /* Resource deadlock would occur */ +#undef EBFONT +#define EBFONT 59 /* Bad font file format */ +#undef ENOSTR +#define ENOSTR 60 /* Device not a stream */ +#undef ENODATA +#define ENODATA 61 /* No data available */ +#undef ETIME +#define ETIME 62 /* Timer expired */ +#undef ENOSR +#define ENOSR 63 /* Out of streams resources */ +#undef ENONET +#define ENONET 64 /* Machine is not on the network */ +#undef ENOPKG +#define ENOPKG 65 /* Package not installed */ +#undef EREMOTE +#define EREMOTE 66 /* Object is remote */ +#undef ENOLINK +#define ENOLINK 67 /* Link has been severed */ +#undef EADV +#define EADV 68 /* Advertise error */ +#undef ESRMNT +#define ESRMNT 69 /* Srmount error */ +#undef ECOMM +#define ECOMM 70 /* Communication error on send */ +#undef EPROTO +#define EPROTO 71 /* Protocol error */ +#undef EMULTIHOP +#define EMULTIHOP 72 /* Multihop attempted */ +#undef EDOTDOT +#define EDOTDOT 73 /* RFS specific error */ +#undef EBADMSG +#define EBADMSG 74 /* Not a data message */ +#undef EOVERFLOW +#define EOVERFLOW 75 /* Value too large for defined data type */ +#undef ENOTUNIQ +#define ENOTUNIQ 76 /* Name not unique on network */ +#undef EBADFD +#define EBADFD 77 /* File descriptor in bad state */ +#undef EREMCHG +#define EREMCHG 78 /* Remote address changed */ +#undef ELIBACC +#define ELIBACC 79 /* Can not access a needed shared library */ +#undef ELIBBAD +#define ELIBBAD 80 /* Accessing a corrupted shared library */ +#undef ELIBSCN +#define ELIBSCN 81 /* .lib section in a.out corrupted */ +#undef ELIBMAX +#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ +#undef ELIBEXEC +#define ELIBEXEC 83 /* Cannot exec a shared library directly */ +#undef EILSEQ +#define EILSEQ 84 /* Illegal byte sequence */ +#undef ERESTART +#define ERESTART 85 /* Interrupted system call should be restarted */ +#undef ESTRPIPE +#define ESTRPIPE 86 /* Streams pipe error */ +#undef EUSERS +#define EUSERS 87 /* Too many users */ +#undef ENOTSOCK +#define ENOTSOCK 88 /* Socket operation on non-socket */ +#undef EDESTADDRREQ +#define EDESTADDRREQ 89 /* Destination address required */ +#undef EMSGSIZE +#define EMSGSIZE 90 /* Message too long */ +#undef EPROTOTYPE +#define EPROTOTYPE 91 /* Protocol wrong type for socket */ +#undef ENOPROTOOPT +#define ENOPROTOOPT 92 /* Protocol not available */ +#undef EPROTONOSUPPORT +#define EPROTONOSUPPORT 93 /* Protocol not supported */ +#undef ESOCKTNOSUPPORT +#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ +#undef EOPNOTSUPP +#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ +#undef EPFNOSUPPORT +#define EPFNOSUPPORT 96 /* Protocol family not supported */ +#undef EAFNOSUPPORT +#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ +#undef EADDRINUSE +#define EADDRINUSE 98 /* Address already in use */ +#undef EADDRNOTAVAIL +#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ +#undef ENETDOWN +#define ENETDOWN 100 /* Network is down */ +#undef ENETUNREACH +#define ENETUNREACH 101 /* Network is unreachable */ +#undef ENETRESET +#define ENETRESET 102 /* Network dropped connection because of reset */ +#undef ECONNABORTED +#define ECONNABORTED 103 /* Software caused connection abort */ +#undef ECONNRESET +#define ECONNRESET 104 /* Connection reset by peer */ +#undef ENOBUFS +#define ENOBUFS 105 /* No buffer space available */ +#undef EISCONN +#define EISCONN 106 /* Transport endpoint is already connected */ +#undef ENOTCONN +#define ENOTCONN 107 /* Transport endpoint is not connected */ +#undef ESHUTDOWN +#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ +#undef ETOOMANYREFS +#define ETOOMANYREFS 109 /* Too many references: cannot splice */ +#undef ETIMEDOUT +#define ETIMEDOUT 110 /* Connection timed out */ +#undef ECONNREFUSED +#define ECONNREFUSED 111 /* Connection refused */ +#undef EHOSTDOWN +#define EHOSTDOWN 112 /* Host is down */ +#undef EHOSTUNREACH +#define EHOSTUNREACH 113 /* No route to host */ +#undef EALREADY +#define EALREADY 114 /* Operation already in progress */ +#undef EINPROGRESS +#define EINPROGRESS 115 /* Operation now in progress */ +#undef ESTALE +#define ESTALE 116 /* Stale NFS file handle */ +#undef EUCLEAN +#define EUCLEAN 117 /* Structure needs cleaning */ +#undef ENOTNAM +#define ENOTNAM 118 /* Not a XENIX named type file */ +#undef ENAVAIL +#define ENAVAIL 119 /* No XENIX semaphores available */ +#undef EISNAM +#define EISNAM 120 /* Is a named type file */ +#undef EREMOTEIO +#define EREMOTEIO 121 /* Remote I/O error */ +#undef EDQUOT +#define EDQUOT 122 /* Quota exceeded */ +#undef ENOMEDIUM +#define ENOMEDIUM 123 /* No medium found */ +#undef EMEDIUMTYPE +#define EMEDIUMTYPE 124 /* Wrong medium type */ +#undef ECANCELED +#define ECANCELED 125 /* Operation Canceled */ +#undef ENOKEY +#define ENOKEY 126 /* Required key not available */ +#undef EKEYEXPIRED +#define EKEYEXPIRED 127 /* Key has expired */ +#undef EKEYREVOKED +#define EKEYREVOKED 128 /* Key has been revoked */ +#undef EKEYREJECTED +#define EKEYREJECTED 129 /* Key was rejected by service */ +#undef EOWNERDEAD +#define EOWNERDEAD 130 /* Owner died */ +#undef ENOTRECOVERABLE +#define ENOTRECOVERABLE 131 /* State not recoverable */ /* Missing stat.h defines. * The following are sys/stat.h definitions not currently present in the ARMCC * errno.h. Note, ARMCC errno.h defines some symbol values differing from * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future - * changes by changing the symbol definition for filesystem use. */ -#define _IFDIR 0040000 /* directory */ -#define _IFREG 0100000 /* regular */ - -#define S_IFDIR _IFDIR -#define S_IFREG _IFREG + * changes by changing the symbol definition for filesystem use. + */ +#define _IFMT 0170000 //< type of file +#define _IFSOCK 0140000 //< socket +#define _IFLNK 0120000 //< symbolic link +#define _IFREG 0100000 //< regular +#define _IFBLK 0060000 //< block special +#define _IFDIR 0040000 //< directory +#define _IFCHR 0020000 //< character special +#define _IFIFO 0010000 //< fifo special + +#define S_IFMT _IFMT //< type of file +#define S_IFSOCK _IFSOCK //< socket +#define S_IFLNK _IFLNK //< symbolic link +#define S_IFREG _IFREG //< regular +#define S_IFBLK _IFBLK //< block special +#define S_IFDIR _IFDIR //< directory +#define S_IFCHR _IFCHR //< character special +#define S_IFIFO _IFIFO //< fifo special #define S_IRWXU (S_IRUSR | S_IWUSR | S_IXUSR) -#define S_IRUSR 0000400 /* read permission, owner */ -#define S_IWUSR 0000200 /* write permission, owner */ -#define S_IXUSR 0000100/* execute/search permission, owner */ +#define S_IRUSR 0000400 ///< read permission, owner +#define S_IWUSR 0000200 ///< write permission, owner +#define S_IXUSR 0000100 ///< execute/search permission, owner #define S_IRWXG (S_IRGRP | S_IWGRP | S_IXGRP) -#define S_IRGRP 0000040 /* read permission, group */ -#define S_IWGRP 0000020 /* write permission, grougroup */ -#define S_IXGRP 0000010/* execute/search permission, group */ +#define S_IRGRP 0000040 ///< read permission, group +#define S_IWGRP 0000020 ///< write permission, grougroup +#define S_IXGRP 0000010 ///< execute/search permission, group #define S_IRWXO (S_IROTH | S_IWOTH | S_IXOTH) -#define S_IROTH 0000004 /* read permission, other */ -#define S_IWOTH 0000002 /* write permission, other */ -#define S_IXOTH 0000001/* execute/search permission, other */ +#define S_IROTH 0000004 ///< read permission, other +#define S_IWOTH 0000002 ///< write permission, other +#define S_IXOTH 0000001 ///< execute/search permission, other -#endif /* defined(__ARMCC_VERSION) || defined(__ICCARM__) */ +/* Refer to sys/stat standard + * Note: Not all fields may be supported by the underlying filesystem + */ +struct stat { + dev_t st_dev; ///< Device ID containing file + ino_t st_ino; ///< File serial number + mode_t st_mode; ///< Mode of file + nlink_t st_nlink; ///< Number of links to file + + uid_t st_uid; ///< User ID + gid_t st_gid; ///< Group ID + + off_t st_size; ///< Size of file in bytes + + time_t st_atime; ///< Time of last access + time_t st_mtime; ///< Time of last data modification + time_t st_ctime; ///< Time of last status change +}; + +#if __cplusplus +extern "C" { +#endif + int stat(const char *path, struct stat *st); +#if __cplusplus +}; +#endif /* The following are dirent.h definitions are declared here to garuntee - * consistency where structure may be different with different toolchains */ + * consistency where structure may be different with different toolchains + */ struct dirent { - char d_name[NAME_MAX+1]; - uint8_t d_type; + char d_name[NAME_MAX+1]; ///< Name of file + uint8_t d_type; ///< Type of file }; enum { - DT_UNKNOWN, // The file type could not be determined. - DT_FIFO, // This is a named pipe (FIFO). - DT_CHR, // This is a character device. - DT_DIR, // This is a directory. - DT_BLK, // This is a block device. - DT_REG, // This is a regular file. - DT_LNK, // This is a symbolic link. - DT_SOCK, // This is a UNIX domain socket. + DT_UNKNOWN, ///< The file type could not be determined. + DT_FIFO, ///< This is a named pipe (FIFO). + DT_CHR, ///< This is a character device. + DT_DIR, ///< This is a directory. + DT_BLK, ///< This is a block device. + DT_REG, ///< This is a regular file. + DT_LNK, ///< This is a symbolic link. + DT_SOCK, ///< This is a UNIX domain socket. }; +/**@}*/ + +/**@}*/ + #endif /* RETARGET_H */ diff --git a/platform/mbed_rtc_time.h b/platform/mbed_rtc_time.h index 84a3739ec32..ee3e7ec7a1e 100644 --- a/platform/mbed_rtc_time.h +++ b/platform/mbed_rtc_time.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_rtc_time rtc_time functions + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -90,3 +94,4 @@ void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_semihost_api.h b/platform/mbed_semihost_api.h index 9127c5ff006..611cce69c07 100644 --- a/platform/mbed_semihost_api.h +++ b/platform/mbed_semihost_api.h @@ -1,6 +1,4 @@ -/** \addtogroup platform */ -/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -95,4 +93,4 @@ int semihost_disabledebug(void); #endif -/** @}*/ + diff --git a/platform/mbed_sleep.h b/platform/mbed_sleep.h index a7dfb37d2c1..23fa5150f42 100644 --- a/platform/mbed_sleep.h +++ b/platform/mbed_sleep.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_sleep Sleep functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2017 ARM Limited * @@ -62,13 +67,13 @@ extern "C" { /** Lock the deep sleep mode * - * This locks the automatic deep mode selection. + * This locks the automatic deep mode selection. * sleep_manager_sleep_auto() will ignore deepsleep mode if * this function is invoked at least once (the internal counter is non-zero) * * Use this locking mechanism for interrupt driven API that are * running in the background and deepsleep could affect their functionality - * + * * The lock is a counter, can be locked up to USHRT_MAX * This function is IRQ and thread safe */ @@ -76,8 +81,8 @@ void sleep_manager_lock_deep_sleep(void); /** Unlock the deep sleep mode * - * Use unlocking in pair with sleep_manager_lock_deep_sleep(). - * + * Use unlocking in pair with sleep_manager_lock_deep_sleep(). + * * The lock is a counter, should be equally unlocked as locked * This function is IRQ and thread safe */ @@ -97,7 +102,7 @@ bool sleep_manager_can_deep_sleep(void); * @note * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger * to be active for debug modes. - * + * */ void sleep_manager_sleep_auto(void); @@ -106,6 +111,10 @@ void sleep_manager_sleep_auto(void); * @note This function can be a noop if not implemented by the platform. * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined). * @note This function will be a noop while uVisor is in use. + * @note This function will be a noop if the following conditions are met: + * - The RTOS is present + * - The processor turn off the Systick clock during sleep + * - The target does not implement tickless mode * * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates @@ -123,7 +132,9 @@ __INLINE static void sleep(void) { #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) #if DEVICE_SLEEP +#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) sleep_manager_sleep_auto(); +#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */ #endif /* DEVICE_SLEEP */ #endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */ } @@ -163,3 +174,4 @@ __INLINE static void deepsleep(void) #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_stats.h b/platform/mbed_stats.h index 99662af4142..c997baefab2 100644 --- a/platform/mbed_stats.h +++ b/platform/mbed_stats.h @@ -1,6 +1,10 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_stats stats functions + * @{ + */ /* mbed Microcontroller Library * Copyright (c) 2016-2016 ARM Limited * @@ -25,6 +29,9 @@ extern "C" { #endif +/** + * struct mbed_stats_heap_t definition + */ typedef struct { uint32_t current_size; /**< Bytes allocated currently. */ uint32_t max_size; /**< Max bytes allocated at a given time. */ @@ -41,6 +48,9 @@ typedef struct { */ void mbed_stats_heap_get(mbed_stats_heap_t *stats); +/** + * struct mbed_stats_stack_t definition + */ typedef struct { uint32_t thread_id; /**< Identifier for thread that owns the stack or 0 if multiple threads. */ uint32_t max_size; /**< Maximum number of bytes used on the stack. */ @@ -73,3 +83,5 @@ size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count); #endif /** @}*/ + +/** @}*/ diff --git a/platform/mbed_toolchain.h b/platform/mbed_toolchain.h index c5bec189bcd..f51e1f4c110 100644 --- a/platform/mbed_toolchain.h +++ b/platform/mbed_toolchain.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_toolchain Toolchain functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -58,7 +63,7 @@ * * @note * IAR does not support alignment greater than word size on the stack - * + * * @code * #include "mbed_toolchain.h" * @@ -92,6 +97,26 @@ #endif #endif +/** MBED_USED + * Inform the compiler that a static variable is to be retained in the object file, even if it is unreferenced. + * + * @code + * #include "mbed_toolchain.h" + * + * MBED_USED int foo; + * + * @endcode + */ +#ifndef MBED_USED +#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) +#define MBED_USED __attribute__((used)) +#elif defined(__ICCARM__) +#define MBED_USED __root +#else +#define MBED_USED +#endif +#endif + /** MBED_WEAK * Mark a function as being weak. * @@ -100,16 +125,16 @@ * should contain a regular function declaration to insure the function is emitted. * A function marked weak will not be emitted if an alternative non-weak * implementation is defined. - * + * * @note * Weak functions are not friendly to making code re-usable, as they can only * be overridden once (and if they are multiply overridden the linker will emit * no warning). You should not normally use weak symbols as part of the API to * re-usable modules. - * + * * @code * #include "mbed_toolchain.h" - * + * * MBED_WEAK void foo() { * // a weak implementation of foo that can be overriden by a definition * // without __weak @@ -148,9 +173,9 @@ * * @code * #include "mbed_toolchain.h" - * + * * MBED_NOINLINE void foo() { - * + * * } * @endcode */ @@ -170,9 +195,9 @@ * * @code * #include "mbed_toolchain.h" - * + * * MBED_FORCEINLINE void foo() { - * + * * } * @endcode */ @@ -191,7 +216,7 @@ * * @code * #include "mbed_toolchain.h" - * + * * MBED_NORETURN void foo() { * // must never return * while (1) {} @@ -241,7 +266,7 @@ * * @code * #include "mbed_toolchain.h" - * + * * MBED_DEPRECATED("don't foo any more, bar instead") * void foo(int arg); * @endcode @@ -305,6 +330,20 @@ #endif #endif +/** + * Macro expanding to a string literal of the enclosing function name. + * + * The string returned takes into account language specificity and yield human + * readable content. + * + * As an example, if the macro is used within a C++ function then the string + * literal containing the function name will contain the complete signature of + * the function - including template parameters - and namespace qualifications. + */ +#ifndef MBED_PRETTY_FUNCTION +#define MBED_PRETTY_FUNCTION __PRETTY_FUNCTION__ +#endif + #ifndef MBED_PRINTF #if defined(__GNUC__) || defined(__CC_ARM) #define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx))) @@ -362,3 +401,4 @@ typedef int FILEHANDLE; #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_wait_api.h b/platform/mbed_wait_api.h index 91619def4ac..a58509f741a 100644 --- a/platform/mbed_wait_api.h +++ b/platform/mbed_wait_api.h @@ -1,6 +1,11 @@ /** \addtogroup platform */ /** @{*/ +/** + * \defgroup platform_wait_api wait_api functions + * @{ + */ + /* mbed Microcontroller Library * Copyright (c) 2006-2013 ARM Limited * @@ -70,3 +75,4 @@ void wait_us(int us); #endif /** @}*/ +/** @}*/ diff --git a/platform/mbed_wait_api_no_rtos.c b/platform/mbed_wait_api_no_rtos.c index 55820a4b99a..a78dd8bc799 100644 --- a/platform/mbed_wait_api_no_rtos.c +++ b/platform/mbed_wait_api_no_rtos.c @@ -30,8 +30,9 @@ void wait_ms(int ms) { } void wait_us(int us) { - uint32_t start = us_ticker_read(); - while ((us_ticker_read() - start) < (uint32_t)us); + const ticker_data_t *const ticker = get_us_ticker_data(); + uint32_t start = ticker_read(ticker); + while ((ticker_read(ticker) - start) < (uint32_t)us); } #endif // #ifndef MBED_CONF_RTOS_PRESENT diff --git a/platform/mbed_wait_api_rtos.cpp b/platform/mbed_wait_api_rtos.cpp index 7ed609a1439..d89b139cf2b 100644 --- a/platform/mbed_wait_api_rtos.cpp +++ b/platform/mbed_wait_api_rtos.cpp @@ -22,6 +22,7 @@ #include "hal/us_ticker_api.h" #include "rtos/rtos.h" #include "platform/mbed_critical.h" +#include "platform/mbed_sleep.h" void wait(float s) { wait_us(s * 1000000.0f); @@ -32,15 +33,19 @@ void wait_ms(int ms) { } void wait_us(int us) { - uint32_t start = us_ticker_read(); + const ticker_data_t *const ticker = get_us_ticker_data(); + + uint32_t start = ticker_read(ticker); // Use the RTOS to wait for millisecond delays if possible int ms = us / 1000; if ((ms > 0) && core_util_are_interrupts_enabled()) { + sleep_manager_lock_deep_sleep(); Thread::wait((uint32_t)ms); + sleep_manager_unlock_deep_sleep(); } // Use busy waiting for sub-millisecond delays, or for the whole // interval if interrupts are not enabled - while ((us_ticker_read() - start) < (uint32_t)us); + while ((ticker_read(ticker) - start) < (uint32_t)us); } #endif // #if MBED_CONF_RTOS_PRESENT diff --git a/rtos/ConditionVariable.cpp b/rtos/ConditionVariable.cpp new file mode 100644 index 00000000000..69be38b9366 --- /dev/null +++ b/rtos/ConditionVariable.cpp @@ -0,0 +1,135 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "rtos/ConditionVariable.h" +#include "rtos/Thread.h" + +#include "mbed_error.h" +#include "mbed_assert.h" + +namespace rtos { + + +ConditionVariable::Waiter::Waiter(): sem(0), prev(NULL), next(NULL), in_list(false) +{ + // No initialization to do +} + +ConditionVariable::ConditionVariable(Mutex &mutex): _mutex(mutex), _wait_list(NULL) +{ + // No initialization to do +} + +void ConditionVariable::wait() +{ + wait_for(osWaitForever); +} + +bool ConditionVariable::wait_for(uint32_t millisec) +{ + Waiter current_thread; + MBED_ASSERT(_mutex.get_owner() == Thread::gettid()); + MBED_ASSERT(_mutex._count == 1); + _add_wait_list(&_wait_list, ¤t_thread); + + _mutex.unlock(); + + int32_t sem_count = current_thread.sem.wait(millisec); + bool timeout = (sem_count > 0) ? false : true; + + _mutex.lock(); + + if (current_thread.in_list) { + _remove_wait_list(&_wait_list, ¤t_thread); + } + + return timeout; +} + +void ConditionVariable::notify_one() +{ + MBED_ASSERT(_mutex.get_owner() == Thread::gettid()); + if (_wait_list != NULL) { + _wait_list->sem.release(); + _remove_wait_list(&_wait_list, _wait_list); + } +} + +void ConditionVariable::notify_all() +{ + MBED_ASSERT(_mutex.get_owner() == Thread::gettid()); + while (_wait_list != NULL) { + _wait_list->sem.release(); + _remove_wait_list(&_wait_list, _wait_list); + } +} + +void ConditionVariable::_add_wait_list(Waiter **wait_list, Waiter *waiter) +{ + if (NULL == *wait_list) { + // Nothing in the list so add it directly. + // Update prev and next pointer to reference self + *wait_list = waiter; + waiter->next = waiter; + waiter->prev = waiter; + } else { + // Add after the last element + Waiter *first = *wait_list; + Waiter *last = (*wait_list)->prev; + + // Update new entry + waiter->next = first; + waiter->prev = last; + + // Insert into the list + first->prev = waiter; + last->next = waiter; + } + waiter->in_list = true; +} + +void ConditionVariable::_remove_wait_list(Waiter **wait_list, Waiter *waiter) +{ + Waiter *prev = waiter->prev; + Waiter *next = waiter->next; + + // Remove from list + prev->next = waiter->next; + next->prev = waiter->prev; + *wait_list = waiter->next; + + if (*wait_list == waiter) { + // This was the last element in the list + *wait_list = NULL; + } + + // Invalidate pointers + waiter->next = NULL; + waiter->prev = NULL; + waiter->in_list = false; +} + +ConditionVariable::~ConditionVariable() +{ + MBED_ASSERT(NULL == _wait_list); +} + +} diff --git a/rtos/ConditionVariable.h b/rtos/ConditionVariable.h new file mode 100644 index 00000000000..dd091ec3d4e --- /dev/null +++ b/rtos/ConditionVariable.h @@ -0,0 +1,214 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017-2017 ARM Limited + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef CONDITIONVARIABLE_H +#define CONDITIONVARIABLE_H + +#include +#include "cmsis_os.h" +#include "rtos/Mutex.h" +#include "rtos/Semaphore.h" + +#include "platform/NonCopyable.h" + +namespace rtos { +/** \addtogroup rtos */ +/** @{*/ + +struct Waiter; + +/** This class provides a safe way to wait for or send notifications of condition changes + * + * This class is used in conjunction with a mutex to safely wait for or + * notify waiters of condition changes to a resource accessible by multiple + * threads. + * + * # Defined behavior + * - All threads waiting on the condition variable wake when + * ConditionVariable::notify_all is called. + * - If one or more threads are waiting on the condition variable at least + * one of them wakes when ConditionVariable::notify is called. + * + * # Undefined behavior + * - The thread which is unblocked on ConditionVariable::notify_one is + * undefined if there are multiple waiters. + * - The order which in which waiting threads acquire the condition variable's + * mutex after ConditionVariable::notify_all is called is undefined. + * - When ConditionVariable::notify_one or ConditionVariable::notify_all is + * called and there are one or more waiters and one or more threads attempting + * to acquire the condition variable's mutex the order in which the mutex is + * acquired is undefined. + * - The behavior of ConditionVariable::wait and ConditionVariable::wait_for + * is undefined if the condition variable's mutex is locked more than once by + * the calling thread. + * - Spurious notifications (not triggered by the application) can occur + * and it is not defined when these occur. + * + * @note Synchronization level: Thread safe + * + * Example: + * @code + * #include "mbed.h" + * + * Mutex mutex; + * ConditionVariable cond(mutex); + * + * // These variables are protected by locking mutex + * uint32_t count = 0; + * bool done = false; + * + * void worker_thread() + * { + * mutex.lock(); + * do { + * printf("Worker: Count %lu\r\n", count); + * + * // Wait for a condition to change + * cond.wait(); + * + * } while (!done); + * printf("Worker: Exiting\r\n"); + * mutex.unlock(); + * } + * + * int main() { + * Thread thread; + * thread.start(worker_thread); + * + * for (int i = 0; i < 5; i++) { + * + * mutex.lock(); + * // Change count and notify waiters of this + * count++; + * printf("Main: Set count to %lu\r\n", count); + * cond.notify_all(); + * mutex.unlock(); + * + * wait(1.0); + * } + * + * mutex.lock(); + * // Change done and notify waiters of this + * done = true; + * printf("Main: Set done\r\n"); + * cond.notify_all(); + * mutex.unlock(); + * + * thread.join(); + * } + * @endcode + */ +class ConditionVariable : private mbed::NonCopyable { +public: + /** Create and Initialize a ConditionVariable object */ + ConditionVariable(Mutex &mutex); + + /** Wait for a notification + * + * Wait until a notification occurs. + * + * @note - The thread calling this function must be the owner of the + * ConditionVariable's mutex and it must be locked exactly once + * @note - Spurious notifications can occur so the caller of this API + * should check to make sure the condition they are waiting on has + * been met + * + * Example: + * @code + * mutex.lock(); + * while (!condition_met) { + * cond.wait(); + * } + * + * function_to_handle_condition(); + * + * mutex.unlock(); + * @endcode + */ + void wait(); + + /** Wait for a notification or timeout + * + * @param millisec timeout value or osWaitForever in case of no time-out. + * @return true if a timeout occurred, false otherwise. + * + * @note - The thread calling this function must be the owner of the + * ConditionVariable's mutex and it must be locked exactly once + * @note - Spurious notifications can occur so the caller of this API + * should check to make sure the condition they are waiting on has + * been met + * + * Example: + * @code + * mutex.lock(); + * Timer timer; + * timer.start(); + * + * bool timed_out = false; + * uint32_t time_left = TIMEOUT; + * while (!condition_met && !timed_out) { + * timed_out = cond.wait_for(time_left); + * uint32_t elapsed = timer.read_ms(); + * time_left = elapsed > TIMEOUT ? 0 : TIMEOUT - elapsed; + * } + * + * if (condition_met) { + * function_to_handle_condition(); + * } + * + * mutex.unlock(); + * @endcode + */ + bool wait_for(uint32_t millisec); + + /** Notify one waiter on this condition variable that a condition changed. + * + * @note - The thread calling this function must be the owner of the ConditionVariable's mutex + */ + void notify_one(); + + /** Notify all waiters on this condition variable that a condition changed. + * + * @note - The thread calling this function must be the owner of the ConditionVariable's mutex + */ + void notify_all(); + + ~ConditionVariable(); + +protected: + struct Waiter { + Waiter(); + Semaphore sem; + Waiter *prev; + Waiter *next; + bool in_list; + }; + + static void _add_wait_list(Waiter **wait_list, Waiter *waiter); + static void _remove_wait_list(Waiter **wait_list, Waiter *waiter); + Mutex &_mutex; + Waiter *_wait_list; +}; + +} +#endif + +/** @}*/ diff --git a/rtos/EventFlags.cpp b/rtos/EventFlags.cpp index abd88a1142e..3d6b79321f1 100644 --- a/rtos/EventFlags.cpp +++ b/rtos/EventFlags.cpp @@ -39,11 +39,11 @@ EventFlags::EventFlags(const char *name) void EventFlags::constructor(const char *name) { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.name = name ? name : "application_unnamed_event_flags"; - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osEventFlagsNew(&_attr); + osEventFlagsAttr_t attr; + attr.name = name ? name : "application_unnamed_event_flags"; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osEventFlagsNew(&attr); MBED_ASSERT(_id); } diff --git a/rtos/EventFlags.h b/rtos/EventFlags.h index 8f0e2b20ed2..5beb5e5ef17 100644 --- a/rtos/EventFlags.h +++ b/rtos/EventFlags.h @@ -32,7 +32,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_EventFlags EventFlags class + * @{ + */ + /** The EventFlags class is used to signal or wait for an arbitrary event or events. @note EventFlags support 31 flags so the MSB flag is ignored, it is used to return an error code (@a osFlagsError) @@ -90,11 +94,12 @@ class EventFlags : private mbed::NonCopyable { void constructor(const char *name = NULL); uint32_t wait(uint32_t flags, uint32_t opt, uint32_t timeout, bool clear); osEventFlagsId_t _id; - osEventFlagsAttr_t _attr; mbed_rtos_storage_event_flags_t _obj_mem; }; +/** @}*/ +/** @}*/ + } #endif -/** @}*/ diff --git a/rtos/Mail.h b/rtos/Mail.h index 602907e34e3..c9ae7f372f1 100644 --- a/rtos/Mail.h +++ b/rtos/Mail.h @@ -38,7 +38,11 @@ using namespace rtos; namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_Mail Mail class + * @{ + */ + /** The Mail class allow to control, send, receive, or wait for mail. A mail is a memory block that is send to a thread or interrupt service routine. @tparam T data type of a single message element. @@ -54,6 +58,22 @@ class Mail : private mbed::NonCopyable > { /** Create and Initialise Mail queue. */ Mail() { }; + /** Check if the mail queue is empty + * + * @return True if the mail queue is empty, false if not + */ + bool empty() const { + return _queue.empty(); + } + + /** Check if the mail queue is full + * + * @return True if the mail queue is full, false if not + */ + bool full() const { + return _queue.full(); + } + /** Allocate a memory block of type T @param millisec timeout value or 0 in case of no time-out. (default: 0). @return pointer to memory block that can be filled with mail or NULL in case error. @@ -103,9 +123,12 @@ class Mail : private mbed::NonCopyable > { MemoryPool _pool; }; +/** @}*/ +/** @}*/ + } #endif -/** @}*/ + diff --git a/rtos/MemoryPool.h b/rtos/MemoryPool.h index 361ae6518fa..d76a99e794f 100644 --- a/rtos/MemoryPool.h +++ b/rtos/MemoryPool.h @@ -33,7 +33,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_MemoryPool MemoryPool class + * @{ + */ + /** Define and manage fixed-size memory pools of objects of a given type. @tparam T data type of a single object (element). @tparam queue_sz maximum number of objects (elements) in the memory pool. @@ -50,12 +54,12 @@ class MemoryPool : private mbed::NonCopyable > { MemoryPool() { memset(_pool_mem, 0, sizeof(_pool_mem)); memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.mp_mem = _pool_mem; - _attr.mp_size = sizeof(_pool_mem); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osMemoryPoolNew(pool_sz, sizeof(T), &_attr); + osMemoryPoolAttr_t attr = { 0 }; + attr.mp_mem = _pool_mem; + attr.mp_size = sizeof(_pool_mem); + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osMemoryPoolNew(pool_sz, sizeof(T), &attr); MBED_ASSERT(_id); } @@ -95,13 +99,14 @@ class MemoryPool : private mbed::NonCopyable > { private: osMemoryPoolId_t _id; - osMemoryPoolAttr_t _attr; /* osMemoryPoolNew requires that pool block size is a multiple of 4 bytes. */ char _pool_mem[((sizeof(T) + 3) & ~3) * pool_sz]; mbed_rtos_storage_mem_pool_t _obj_mem; }; +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Mutex.cpp b/rtos/Mutex.cpp index 359af105368..44fefa0759f 100644 --- a/rtos/Mutex.cpp +++ b/rtos/Mutex.cpp @@ -27,7 +27,7 @@ namespace rtos { -Mutex::Mutex() +Mutex::Mutex(): _count(0) { constructor(); } @@ -40,27 +40,41 @@ Mutex::Mutex(const char *name) void Mutex::constructor(const char *name) { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.name = name ? name : "aplication_unnamed_mutex"; - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; - _id = osMutexNew(&_attr); + osMutexAttr_t attr = { 0 }; + attr.name = name ? name : "aplication_unnamed_mutex"; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + attr.attr_bits = osMutexRecursive | osMutexPrioInherit | osMutexRobust; + _id = osMutexNew(&attr); MBED_ASSERT(_id); } osStatus Mutex::lock(uint32_t millisec) { - return osMutexAcquire(_id, millisec); + osStatus status = osMutexAcquire(_id, millisec); + if (osOK == status) { + _count++; + } + return status; } bool Mutex::trylock() { - return (osMutexAcquire(_id, 0) == osOK); + if (osMutexAcquire(_id, 0) == osOK) { + _count++; + return true; + } else { + return false; + } } osStatus Mutex::unlock() { + _count--; return osMutexRelease(_id); } +osThreadId Mutex::get_owner() { + return osMutexGetOwner(_id); +} + Mutex::~Mutex() { osMutexDelete(_id); } diff --git a/rtos/Mutex.h b/rtos/Mutex.h index 4f1ed8a6aae..1b9e22a27ff 100644 --- a/rtos/Mutex.h +++ b/rtos/Mutex.h @@ -32,7 +32,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_Mutex Mutex class + * @{ + */ + /** The Mutex class is used to synchronize the execution of threads. This is for example used to protect access to a shared resource. @@ -76,17 +80,24 @@ class Mutex : private mbed::NonCopyable { */ osStatus unlock(); + /** Get the owner the this mutex + @return the current owner of this mutex. + */ + osThreadId get_owner(); + ~Mutex(); private: void constructor(const char *name = NULL); + friend class ConditionVariable; osMutexId_t _id; - osMutexAttr_t _attr; mbed_rtos_storage_mutex_t _obj_mem; + uint32_t _count; }; - +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Queue.h b/rtos/Queue.h index 56739522ae9..67a04653dbd 100644 --- a/rtos/Queue.h +++ b/rtos/Queue.h @@ -34,7 +34,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_EventFlags EventFlags class + * @{ + */ + /** The Queue class allow to control, send, receive, or wait for messages. A message can be a integer or pointer value to a certain type T that is send to a thread or interrupt service routine. @@ -51,12 +55,12 @@ class Queue : private mbed::NonCopyable > { /** Create and initialize a message Queue. */ Queue() { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.mq_mem = _queue_mem; - _attr.mq_size = sizeof(_queue_mem); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osMessageQueueNew(queue_sz, sizeof(T*), &_attr); + osMessageQueueAttr_t attr = { 0 }; + attr.mq_mem = _queue_mem; + attr.mq_size = sizeof(_queue_mem); + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osMessageQueueNew(queue_sz, sizeof(T*), &attr); MBED_ASSERT(_id); } @@ -64,6 +68,22 @@ class Queue : private mbed::NonCopyable > { osMessageQueueDelete(_id); } + /** Check if the queue is empty + * + * @return True if the queue is empty, false if not + */ + bool empty() const { + return osMessageQueueGetCount(_id) == 0; + } + + /** Check if the queue is full + * + * @return True if the queue is full, false if not + */ + bool full() const { + return osMessageQueueGetSpace(_id) == 0; + } + /** Put a message in a Queue. @param data message pointer. @param millisec timeout value or 0 in case of no time-out. (default: 0) @@ -115,12 +135,12 @@ class Queue : private mbed::NonCopyable > { private: osMessageQueueId_t _id; - osMessageQueueAttr_t _attr; char _queue_mem[queue_sz * (sizeof(T*) + sizeof(mbed_rtos_storage_message_t))]; mbed_rtos_storage_msg_queue_t _obj_mem; }; +/** @}*/ +/** @}*/ } #endif -/** @}*/ diff --git a/rtos/RtosTimer.cpp b/rtos/RtosTimer.cpp index acec84ed98c..3e6c19718be 100644 --- a/rtos/RtosTimer.cpp +++ b/rtos/RtosTimer.cpp @@ -31,10 +31,10 @@ namespace rtos { void RtosTimer::constructor(mbed::Callback func, os_timer_type type) { _function = func; memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osTimerNew((void (*)(void *))Callback::thunk, type, &_function, &_attr); + osTimerAttr_t attr = { 0 }; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osTimerNew((void (*)(void *))Callback::thunk, type, &_function, &attr); MBED_ASSERT(_id); } diff --git a/rtos/RtosTimer.h b/rtos/RtosTimer.h index 3abef47c942..c5e6276468b 100644 --- a/rtos/RtosTimer.h +++ b/rtos/RtosTimer.h @@ -33,7 +33,11 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ - +/** + * \defgroup rtos_RtosTimer RtosTimer class + * @{ + */ + /** The RtosTimer class allow creating and and controlling of timer functions in the system. A timer function is called when a time period expires whereby both on-shot and periodic timers are possible. A timer can be started, restarted, or stopped. @@ -131,13 +135,21 @@ class RtosTimer : private mbed::NonCopyable { } /** Stop the timer. - @return status code that indicates the execution status of the function. + @return status code that indicates the execution status of the function: + @a osOK the timer has been stopped. + @a osErrorISR @a stop cannot be called from interrupt service routines. + @a osErrorParameter internal error. + @a osErrorResource the timer is not running. */ osStatus stop(void); - /** Start the timer. - @param millisec time delay value of the timer. - @return status code that indicates the execution status of the function. + /** Start or restart the timer. + @param millisec non-zero value of the timer. + @return status code that indicates the execution status of the function: + @a osOK the timer has been started or restarted. + @a osErrorISR @a start cannot be called from interrupt service routines. + @a osErrorParameter internal error or incorrect parameter value. + @a osErrorResource internal error (the timer is in an invalid timer state). */ osStatus start(uint32_t millisec); @@ -149,13 +161,14 @@ class RtosTimer : private mbed::NonCopyable { void constructor(mbed::Callback func, os_timer_type type); osTimerId_t _id; - osTimerAttr_t _attr; mbed_rtos_storage_timer_t _obj_mem; mbed::Callback _function; }; +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/Semaphore.cpp b/rtos/Semaphore.cpp index 107dccb33fc..fb082d3c449 100644 --- a/rtos/Semaphore.cpp +++ b/rtos/Semaphore.cpp @@ -36,10 +36,10 @@ Semaphore::Semaphore(int32_t count, uint16_t max_count) { void Semaphore::constructor(int32_t count, uint16_t max_count) { memset(&_obj_mem, 0, sizeof(_obj_mem)); - memset(&_attr, 0, sizeof(_attr)); - _attr.cb_mem = &_obj_mem; - _attr.cb_size = sizeof(_obj_mem); - _id = osSemaphoreNew(max_count, count, &_attr); + osSemaphoreAttr_t attr = { 0 }; + attr.cb_mem = &_obj_mem; + attr.cb_size = sizeof(_obj_mem); + _id = osSemaphoreNew(max_count, count, &attr); MBED_ASSERT(_id != NULL); } diff --git a/rtos/Semaphore.h b/rtos/Semaphore.h index 80dc928ede4..88b479c5e4f 100644 --- a/rtos/Semaphore.h +++ b/rtos/Semaphore.h @@ -31,6 +31,10 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ +/** + * \defgroup rtos_Semaphore Semaphore class + * @{ + */ /** The Semaphore class is used to manage and protect access to a set of shared resources. * @@ -71,11 +75,11 @@ class Semaphore : private mbed::NonCopyable { void constructor(int32_t count, uint16_t max_count); osSemaphoreId_t _id; - osSemaphoreAttr_t _attr; mbed_rtos_storage_semaphore_t _obj_mem; }; - +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/TARGET_CORTEX/mbed_rtx_conf.h b/rtos/TARGET_CORTEX/mbed_rtx_conf.h index 48a4456340c..a6cd655d9f3 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_conf.h +++ b/rtos/TARGET_CORTEX/mbed_rtx_conf.h @@ -41,6 +41,10 @@ #define OS_DYNAMIC_MEM_SIZE 0 +#if defined(OS_TICK_FREQ) && (OS_TICK_FREQ != 1000) +#error "OS Tickrate must be 1000 for system timing" +#endif + #if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) /* ARM toolchain uses up to 8 static mutexes, any further mutexes will be allocated on the heap. */ #define OS_MUTEX_OBJ_MEM 1 diff --git a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp index 1ea59c5b793..32d5ead975e 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp +++ b/rtos/TARGET_CORTEX/mbed_rtx_idle.cpp @@ -24,7 +24,7 @@ #include "platform/mbed_sleep.h" #include "TimerEvent.h" #include "lp_ticker_api.h" -#include "core_cm.h" +#include "rtx_core_cm.h" #include "mbed_critical.h" #include "mbed_assert.h" #include @@ -58,7 +58,7 @@ class RtosTimer : private TimerEvent { // Ensure SysTick has the correct priority as it is still used // to trigger software interrupts on each tick. The period does // not matter since it will never start counting. - SysTick_Setup(16); + OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER); #endif }; @@ -138,41 +138,57 @@ class RtosTimer : private TimerEvent { static RtosTimer *os_timer; static uint64_t os_timer_data[sizeof(RtosTimer) / 8]; -/// Setup System Timer. -int32_t osRtxSysTimerSetup (void) +/// Enable System Timer. +int32_t OS_Tick_Enable (void) { // Do not use SingletonPtr since this relies on the RTOS if (NULL == os_timer) { os_timer = new (os_timer_data) RtosTimer(); } - return -1; -} -/// Enable System Timer. -void osRtxSysTimerEnable (void) -{ // set to fire interrupt on next tick os_timer->schedule_tick(); + + return 0; } /// Disable System Timer. -void osRtxSysTimerDisable (void) +int32_t OS_Tick_Disable (void) { os_timer->cancel_tick(); + + return 0; } /// Acknowledge System Timer IRQ. -void osRtxSysTimerAckIRQ (void) +int32_t OS_Tick_AcknowledgeIRQ (void) { os_timer->schedule_tick(); + + return 0; } /// Get System Timer count. -uint32_t osRtxSysTimerGetCount (void) +uint32_t OS_Tick_GetCount (void) { return os_timer->get_time() & 0xFFFFFFFF; } +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return -1; +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return 0; +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return 1000; +} + static void default_idle_hook(void) { uint32_t elapsed_ticks = 0; diff --git a/rtos/TARGET_CORTEX/rtx4/cmsis_os.h b/rtos/TARGET_CORTEX/rtx4/cmsis_os.h index 4f7ba115df9..af78fd3bf98 100644 --- a/rtos/TARGET_CORTEX/rtx4/cmsis_os.h +++ b/rtos/TARGET_CORTEX/rtx4/cmsis_os.h @@ -17,8 +17,8 @@ * * ---------------------------------------------------------------------- * - * $Date: 10. January 2017 - * $Revision: V2.1.0 + * $Date: 9. June 2017 + * $Revision: V2.1.1 * * Project: CMSIS-RTOS API * Title: cmsis_os.h RTX header file @@ -118,6 +118,11 @@ * - added: osKernelRestoreLock * Updated Thread and Event Flags: * - changed flags parameter and return type from int32_t to uint32_t + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil *---------------------------------------------------------------------------*/ #ifndef CMSIS_OS_H_ @@ -430,7 +435,6 @@ uint32_t osKernelSysTick (void); /// Create a Thread Definition with function, priority, and stack requirements. /// \param name name of the thread function. /// \param priority initial priority of the thread function. -/// \param instances number of possible thread instances. /// \param stacksz stack size (in bytes) requirements for the thread function. #if defined (osObjectsExternal) // object is external #define osThreadDef(name, priority, stacksz) \ @@ -439,7 +443,7 @@ extern const osThreadDef_t os_thread_def_##name #if (osCMSIS < 0x20000U) #define osThreadDef(name, priority, stacksz) \ const osThreadDef_t os_thread_def_##name = \ -{ (name), (priority), (1), (stacksz) } +{ (name), (priority), 1, (stacksz) } #else #define osThreadDef(name, priority, stacksz) \ uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1] __attribute__((section(".bss.os.thread.stack"))); \ @@ -447,7 +451,7 @@ static osRtxThread_t os_thread_cb_##name __attribute__((section(".bss.os.thread. const osThreadDef_t os_thread_def_##name = \ { (name), \ { NULL, osThreadDetached, \ - (&os_thread_cb_##name),\ + &os_thread_cb_##name,\ osRtxThreadCbSize, \ (stacksz) ? (&os_thread_stack##name) : NULL, \ 8*((stacksz+7)/8), \ diff --git a/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h b/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h similarity index 96% rename from rtos/TARGET_CORTEX/rtx5/cmsis_os2.h rename to rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h index 6ae65137b7c..2cbb2930417 100644 --- a/rtos/TARGET_CORTEX/rtx5/cmsis_os2.h +++ b/rtos/TARGET_CORTEX/rtx5/Include/cmsis_os2.h @@ -1,5 +1,3 @@ -/** \addtogroup rtos */ -/** @{*/ /* * Copyright (c) 2013-2017 ARM Limited. All rights reserved. * @@ -19,12 +17,17 @@ * * ---------------------------------------------------------------------- * - * $Date: 10. January 2017 - * $Revision: V2.1.0 + * $Date: 9. June 2017 + * $Revision: V2.1.1 * * Project: CMSIS-RTOS2 API * Title: cmsis_os2.h header file * + * Version 2.1.1 + * Additional functions allowed to be called from Interrupt Service Routines: + * - osKernelGetTickCount, osKernelGetTickFreq + * Changed Kernel Tick type to uint32_t: + * - updated: osKernelGetTickCount, osDelayUntil * Version 2.1.0 * Support for critical and uncritical sections (nesting safe): * - updated: osKernelLock, osKernelUnlock @@ -151,7 +154,7 @@ typedef enum { /// Entry point of a thread. typedef void (*osThreadFunc_t) (void *argument); -/// Entry point of a timer call back function. +/// Timer callback function. typedef void (*osTimerFunc_t) (void *argument); /// Timer type. @@ -160,15 +163,15 @@ typedef enum { osTimerPeriodic = 1 ///< Repeating timer. } osTimerType_t; -/// Timeout value. +// Timeout value. #define osWaitForever 0xFFFFFFFFU ///< Wait forever timeout value. -/// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). +// Flags options (\ref osThreadFlagsWait and \ref osEventFlagsWait). #define osFlagsWaitAny 0x00000000U ///< Wait for any flag (default). #define osFlagsWaitAll 0x00000001U ///< Wait for all flags. #define osFlagsNoClear 0x00000002U ///< Do not clear flags which have been specified to wait for. -/// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). +// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx). #define osFlagsError 0x80000000U ///< Error indicator. #define osFlagsErrorUnknown 0xFFFFFFFFU ///< osError (-1). #define osFlagsErrorTimeout 0xFFFFFFFEU ///< osErrorTimeout (-2). @@ -176,11 +179,11 @@ typedef enum { #define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4). #define osFlagsErrorISR 0xFFFFFFFAU ///< osErrorISR (-6). -/// Thread attributes (attr_bits in \ref osThreadAttr_t). -#define osThreadDetached 0x00000000U ///< Thread created in detached state (default) -#define osThreadJoinable 0x00000001U ///< Thread created in joinable state +// Thread attributes (attr_bits in \ref osThreadAttr_t). +#define osThreadDetached 0x00000000U ///< Thread created in detached mode (default) +#define osThreadJoinable 0x00000001U ///< Thread created in joinable mode -/// Mutex attributes (attr_bits in \ref osMutexAttr_t). +// Mutex attributes (attr_bits in \ref osMutexAttr_t). #define osMutexRecursive 0x00000001U ///< Recursive mutex. #define osMutexPrioInherit 0x00000002U ///< Priority inherit protocol. #define osMutexRobust 0x00000008U ///< Robust mutex. @@ -337,10 +340,10 @@ void osKernelResume (uint32_t sleep_ticks); /// Get the RTOS kernel tick count. /// \return RTOS kernel current tick count. -uint64_t osKernelGetTickCount (void); +uint32_t osKernelGetTickCount (void); /// Get the RTOS kernel tick frequency. -/// \return frequency of the kernel tick. +/// \return frequency of the kernel tick in hertz, i.e. kernel ticks per second. uint32_t osKernelGetTickFreq (void); /// Get the RTOS kernel system timer count. @@ -348,7 +351,7 @@ uint32_t osKernelGetTickFreq (void); uint32_t osKernelGetSysTimerCount (void); /// Get the RTOS kernel system timer frequency. -/// \return frequency of the system timer. +/// \return frequency of the system timer in hertz, i.e. timer ticks per second. uint32_t osKernelGetSysTimerFreq (void); @@ -475,15 +478,15 @@ osStatus_t osDelay (uint32_t ticks); /// Wait until specified time. /// \param[in] ticks absolute time in ticks /// \return status code that indicates the execution status of the function. -osStatus_t osDelayUntil (uint64_t ticks); +osStatus_t osDelayUntil (uint32_t ticks); // ==== Timer Management Functions ==== /// Create and Initialize a timer. -/// \param[in] func start address of a timer call back function. -/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. -/// \param[in] argument argument to the timer call back function. +/// \param[in] func function pointer to callback function. +/// \param[in] type \ref osTimerOnce for one-shot or \ref osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer callback function. /// \param[in] attr timer attributes; NULL: default values. /// \return timer ID for reference by other functions or NULL in case of error. osTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); @@ -612,7 +615,7 @@ const char *osSemaphoreGetName (osSemaphoreId_t semaphore_id); /// \return status code that indicates the execution status of the function. osStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout); -/// Release a Semaphore token that was acquired by \ref osSemaphoreAcquire. +/// Release a Semaphore token up to the initial maximum count. /// \param[in] semaphore_id semaphore ID obtained by \ref osSemaphoreNew. /// \return status code that indicates the execution status of the function. osStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id); @@ -746,5 +749,3 @@ osStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id); #endif #endif // CMSIS_OS2_H_ - -/** @}*/ diff --git a/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h b/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h new file mode 100644 index 00000000000..391f729ca06 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/Include/os_tick.h @@ -0,0 +1,74 @@ +/**************************************************************************//** + * @file os_tick.h + * @brief CMSIS OS Tick header file + * @version V1.0.0 + * @date 05. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef OS_TICK_H +#define OS_TICK_H + +#include + +/// IRQ Handler. +#ifndef IRQHANDLER_T +#define IRQHANDLER_T +typedef void (*IRQHandler_t) (void); +#endif + +/// Setup OS Tick. +/// \param[in] freq tick frequency in Hz +/// \param[in] handler tick IRQ handler +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler); + +/// Enable OS Tick. +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Enable (void); + +/// Disable OS Tick. +/// \return 0 on success, -1 on error. +int32_t OS_Tick_Disable (void); + +/// Acknowledge OS Tick IRQ. +/// \return 0 on success, -1 on error. +int32_t OS_Tick_AcknowledgeIRQ (void); + +/// Get OS Tick IRQ number. +/// \return OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void); + +/// Get OS Tick clock. +/// \return OS Tick clock in Hz. +uint32_t OS_Tick_GetClock (void); + +/// Get OS Tick interval. +/// \return OS Tick interval. +uint32_t OS_Tick_GetInterval (void); + +/// Get OS Tick count value. +/// \return OS Tick count value. +uint32_t OS_Tick_GetCount (void); + +/// Get OS Tick overflow status. +/// \return OS Tick overflow status (1 - overflow, 0 - no overflow). +uint32_t OS_Tick_GetOverflow (void); + +#endif /* OS_TICK_H */ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX_Config.c b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/RTX_Config.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c index 6572cf0a498..69c8179dfb1 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX_Config.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c @@ -24,7 +24,7 @@ * * ----------------------------------------------------------------------------- */ - + #include "cmsis_compiler.h" #include "rtx_os.h" diff --git a/rtos/TARGET_CORTEX/rtx5/RTX_Config.h b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/RTX_Config.h rename to rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h index 1a0ea44b782..4cd0f84a0e8 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX_Config.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h @@ -1,5 +1,3 @@ -/** \addtogroup rtos */ -/** @{*/ /* * Copyright (c) 2013-2017 ARM Limited. All rights reserved. * @@ -381,4 +379,3 @@ //------------- <<< end of configuration section >>> --------------------------- #endif // RTX_CONFIG_H_ -/** @}*/ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c b/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c new file mode 100644 index 00000000000..861ab0513f0 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Exception handlers (C functions) + * + * ----------------------------------------------------------------------------- + */ + +#include + +//Fault Status Register (IFSR/DFSR) definitions +#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup +#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external +#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external +#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external +#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal +#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal +#define FSR_PERMISSION_FAULT_FIRST 0x0f //MMU Fault - internal +#define FSR_PERMISSION_FAULT_SECOND 0x0d //MMU Fault - internal +#define FSR_DEBUG_EVENT 0x02 //internal +#define FSR_SYNC_EXT_ABORT 0x08 //sync/external +#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external +#define FSR_LOCKDOWN 0x14 //internal +#define FSR_COPROCESSOR_ABORT 0x1a //internal +#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external +#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external +#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external + +void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { + uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in DFAR is invalid for some fault statuses. + case FSR_ALIGNMENT_FAULT: + case FSR_INSTRUCTION_CACHE_MAINTENANCE: + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISSION_FAULT_FIRST: + case FSR_PERMISSION_FAULT_SECOND: + case FSR_DEBUG_EVENT: + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid + case FSR_ASYNC_PARITY_ERROR: //DFAR invalid + default: + while(1); + } +} + +void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { + uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in IFAR is invalid for some fault statuses. + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISSION_FAULT_FIRST: + case FSR_PERMISSION_FAULT_SECOND: + case FSR_DEBUG_EVENT: //IFAR invalid + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + default: + while(1); + } +} + + +//returns amount to decrement lr by +//this will be 0 when we have emulated the instruction and want to execute the next instruction +//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) +//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) +uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { + const int THUMB = 2; + const int ARM = 4; + //Lazy VFP/NEON initialisation and switching + + // (ARM ARM section A7.5) VFP data processing instruction? + // (ARM ARM section A7.6) VFP/NEON register load/store instruction? + // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? + // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? + if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || + (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { + if (((opcode & 0x00000E00) >> 9) == 5) { + __FPU_Enable(); + return state; + } + } + + // (ARM ARM section A7.4) NEON data processing instruction? + if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || + (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || + // (ARM ARM section A7.7) NEON load/store instruction? + (state == ARM && ((opcode >> 24) == 0xF4)) || + (state == THUMB && ((opcode >> 24) == 0xF9))) { + __FPU_Enable(); + return state; + } + + //Add code here for other Undef cases + while(1); +} diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_evr.h b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/rtx_evr.h rename to rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h index 5bc4baa89fe..897d4de63ae 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_evr.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_evr.h @@ -1,5 +1,3 @@ -/** \addtogroup rtos */ -/** @{*/ /* * Copyright (c) 2013-2017 ARM Limited. All rights reserved. * @@ -310,7 +308,7 @@ extern void EvrRtxKernelResumed (void); \param[in] count RTOS kernel current tick count. */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE)) -extern void EvrRtxKernelGetTickCount (uint64_t count); +extern void EvrRtxKernelGetTickCount (uint32_t count); #else #define EvrRtxKernelGetTickCount(count) #endif @@ -762,7 +760,7 @@ extern void EvrRtxThreadDelay (uint32_t ticks); \param[in] ticks absolute time in ticks */ #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_UNTIL_DISABLE)) -extern void EvrRtxThreadDelayUntil (uint64_t ticks); +extern void EvrRtxThreadDelayUntil (uint32_t ticks); #else #define EvrRtxThreadDelayUntil(ticks) #endif @@ -1844,4 +1842,3 @@ extern void EvrRtxMessageQueueDestroyed (osMessageQueueId_t mq_id); #endif // RTX_EVR_H_ -/** @}*/ diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_os.h b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h similarity index 94% rename from rtos/TARGET_CORTEX/rtx5/rtx_os.h rename to rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h index fbc243c4194..0c2df7e6a3d 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_os.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Include/rtx_os.h @@ -37,9 +37,9 @@ extern "C" /// Kernel Information -#define osRtxVersionAPI 20010000 ///< API version (2.1.0) -#define osRtxVersionKernel 50010001 ///< Kernel version (5.1.1) -#define osRtxKernelId "RTX V5.1.1" ///< Kernel identification string +#define osRtxVersionAPI 20010001 ///< API version (2.1.1) +#define osRtxVersionKernel 50020002 ///< Kernel version (5.2.2) +#define osRtxKernelId "RTX V5.2.2" ///< Kernel identification string // ==== Common definitions ==== @@ -283,10 +283,9 @@ typedef struct { struct { ///< Kernel Info uint8_t state; ///< State volatile uint8_t blocked; ///< Blocked - uint8_t pendISR; ///< Pending ISR (SV and SysTick) uint8_t pendSV; ///< Pending SV - uint32_t sys_freq; ///< System Frequency - uint64_t tick; ///< Tick counter + uint8_t reserved; + uint32_t tick; ///< Tick counter } kernel; int32_t tick_irqn; ///< Tick Timer IRQ Number struct { ///< Thread Info @@ -341,7 +340,6 @@ typedef struct { osRtxMpInfo_t *memory_pool; ///< Memory Pool Control Blocks osRtxMpInfo_t *message_queue; ///< Message Queue Control Blocks } mpi; - uint32_t padding; } osRtxInfo_t; extern osRtxInfo_t osRtxInfo; ///< OS Runtime Information @@ -398,30 +396,6 @@ extern void PendSV_Handler (void); extern void SysTick_Handler (void); -/// OS System Timer functions (default implementation uses SysTick) - -/// Setup System Timer. -/// \return system timer IRQ number. -extern int32_t osRtxSysTimerSetup (void); - -/// Enable System Timer. -extern void osRtxSysTimerEnable (void); - -/// Disable System Timer. -extern void osRtxSysTimerDisable (void); - -/// Acknowledge System Timer IRQ. -extern void osRtxSysTimerAckIRQ (void); - -/// Get System Timer count. -/// \return system timer count. -extern uint32_t osRtxSysTimerGetCount (void); - -/// Get System Timer frequency. -/// \return system timer frequency. -extern uint32_t osRtxSysTimerGetFreq (void); - - // ==== OS External Configuration ==== /// OS Configuration flags diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S new file mode 100644 index 00000000000..7963fdefc09 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S @@ -0,0 +1,447 @@ +;/* +; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-A Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + +MODE_FIQ EQU 0x11 +MODE_IRQ EQU 0x12 +MODE_SVC EQU 0x13 +MODE_ABT EQU 0x17 +MODE_UND EQU 0x1B + +CPSR_BIT_T EQU 0x20 + +K_STATE_RUNNING EQU 2 ; osKernelState_t::osKernelRunning +I_K_STATE_OFS EQU 8 ; osRtxInfo.kernel.state offset +I_TICK_IRQN_OFS EQU 16 ; osRtxInfo.tick_irqn offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SP_FRAME EQU 34 ; osRtxThread_t.stack_frame offset +TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset + + + PRESERVE8 + ARM + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.data|, DATA, READWRITE + EXPORT IRQ_PendSV +IRQ_NestLevel DCD 0 ; IRQ nesting level counter +IRQ_PendSV DCB 0 ; Pending SVC flag +SVC_Active DCB 0 ; SVC handler execution active flag + + + AREA |.text|, CODE, READONLY + + +Undef_Handler\ + PROC + EXPORT Undef_Handler + IMPORT CUndefHandler + + SRSFD SP!, #MODE_UND + PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack + + MRS R0, SPSR + TST R0, #CPSR_BIT_T ; Check mode + MOVEQ R1, #4 ; R1 = 4 ARM mode + MOVNE R1, #2 ; R1 = 2 Thumb mode + SUB R0, LR, R1 + LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction + BEQ Undef_Cont + + ; Thumb instruction + ; Determine if it is a 32-bit Thumb instruction + LDRH R0, [R0] + MOV R2, #0x1C + CMP R2, R0, LSR #11 + BHS Undef_Cont ; 16-bit Thumb instruction + + ; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +Undef_Cont + MOV R2, LR ; Set LR to third argument + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + ; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM) + BL CUndefHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry + SUB LR, LR, R0 + LDR R0, [SP, #28] ; Restore stacked SPSR + MSR SPSR_CXSF, R0 + POP {R0-R4, R12} ; Restore stacked APCS registers + ADD SP, SP, #8 ; Adjust SP for already-restored banked registers + MOVS PC, LR + + ENDP + + +PAbt_Handler\ + PROC + EXPORT PAbt_Handler + IMPORT CPAbtHandler + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + MRC p15, 0, R0, c5, c0, 1 ; IFSR + MRC p15, 0, R1, c6, c0, 2 ; IFAR + + MOV R2, LR ; Set LR to third argument + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CPAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stack APCS registers + RFEFD SP! ; Return from exception + + ENDP + + +DAbt_Handler\ + PROC + EXPORT DAbt_Handler + IMPORT CDAbtHandler + + SUB LR, LR, #8 ; Pre-adjust LR + SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + CLREX ; State of exclusive monitors unknown after taken data abort + MRC p15, 0, R0, c5, c0, 0 ; DFSR + MRC p15, 0, R1, c6, c0, 0 ; DFAR + + MOV R2, LR ; Set LR to third argument + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CDAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + + ENDP + + +IRQ_Handler\ + PROC + EXPORT IRQ_Handler + IMPORT osRtxInfo + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPRS_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + LDR R1, =IRQ_NestLevel + LDR R3, [R1] ; Load IRQ nest level and increment it + ADD R3, R3, #1 + STR R3, [R1] + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + LDR R2, =IRQ_NestLevel + LDR R1, [R2] ; Load IRQ nest level and + SUBS R1, R1, #1 ; decrement it + STR R1, [R2] + BNE IRQ_Exit ; Not zero, exit from IRQ handler + + LDR R0, =SVC_Active + LDRB R0, [R0] ; Load SVC_Active flag + CMP R0, #0 + BNE IRQ_SwitchCheck ; Skip post processing when SVC active + + ; RTX IRQ post processing check + PUSH {R5, R6} ; Save user R5 and R6 + MOV R6, #0 + LDR R5, =IRQ_PendSV ; Load address of IRQ_PendSV flag + B IRQ_PendCheck +IRQ_PendExec + STRB R6, [R5] ; Clear PendSV flag + CPSIE i ; Re-enable interrupts + BLX osRtxPendSV_Handler ; Post process pending objects + CPSID i ; Disable interrupts +IRQ_PendCheck + LDRB R0, [R5] ; Load PendSV flag + CMP R0, #1 ; Compare PendSV value + BEQ IRQ_PendExec ; Branch to IRQ_PendExec if PendSV is set + POP {R5, R6} ; Restore user R5 and R6 + +IRQ_SwitchCheck + ; RTX IRQ context switch check + LDR R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run + LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next + CMP R0, R1 ; Check if context switch is required + BEQ IRQ_Exit + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + B osRtxContextSwitch + +IRQ_Exit + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + ENDP + + +SVC_Handler\ + PROC + EXPORT SVC_Handler + IMPORT IRQ_Disable + IMPORT IRQ_Enable + IMPORT osRtxPendSV_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + + SRSFD SP!, #MODE_SVC ; Store SPSR_svc and LR_svc onto SVC stack + PUSH {R12, LR} + + MRS R12, SPSR ; Load SPSR + TST R12, #CPSR_BIT_T ; Thumb bit set? + LDRHNE R12, [LR,#-2] ; Thumb: load halfword + BICNE R12, R12, #0xFF00 ; extract SVC number + LDREQ R12, [LR,#-4] ; ARM: load word + BICEQ R12, R12, #0xFF000000 ; extract SVC number + CMP R12, #0 ; Compare SVC number + BNE SVC_User ; Branch if User SVC + + PUSH {R0-R3} + + LDR R3, =osRtxInfo + LDR R1, [R3, #I_K_STATE_OFS] ; Load RTX5 kernel state + CMP R1, #K_STATE_RUNNING ; Check osKernelRunning + BLT SVC_FuncCall ; Continue if kernel is not running + LDR R0, [R3, #I_TICK_IRQN_OFS] ; Load OS Tick irqn + BLX IRQ_Disable ; Disable OS Tick interrupt +SVC_FuncCall + LDR R0, =SVC_Active + MOV R1, #1 + STRB R1, [R0] ; Set SVC_Active flag + POP {R0-R3} + + LDR R12, [SP] ; Reload R12 from stack + + CPSIE i ; Re-enable interrupts + BLX R12 ; Branch to SVC function + CPSID i ; Disable interrupts + + SUB SP, SP, #4 ; Adjust SP + STM SP, {SP}^ ; Store SP_usr onto stack + POP {R12} ; Pop SP_usr into R12 + SUB R12, R12, #16 ; Adjust pointer to SP_usr + LDMDB R12, {R2,R3} ; Load return values from SVC function + PUSH {R0-R3} ; Push return values to stack + + PUSH {R4, R5} ; Save R4 and R5 + MOV R5, #0 + LDR R4, =IRQ_PendSV ; Load address of IRQ_PendSV + B SVC_PendCheck +SVC_PendExec + STRB R5, [R4] ; Clear IRQ_PendSV flag + CPSIE i ; Re-enable interrupts + BLX osRtxPendSV_Handler ; Post process pending objects + CPSID i ; Disable interrupts +SVC_PendCheck + LDRB R0, [R4] ; Load IRQ_PendSV flag + CMP R0, #1 ; Compare IRQ_PendSV value + BEQ SVC_PendExec ; Branch to SVC_PendExec if IRQ_PendSV is set + POP {R4, R5} ; Restore R4 and R5 + + LDR R0, =SVC_Active + MOV R1, #0 + STRB R1, [R0] ; Clear SVC_Active flag + + LDR R12, =osRtxInfo + LDR R1, [R12, #I_K_STATE_OFS] ; Load RTX5 kernel state + CMP R1, #K_STATE_RUNNING ; Check osKernelRunning + BLT SVC_ContextCheck ; Continue if kernel is not running + LDR R0, [R12, #I_TICK_IRQN_OFS] ; Load OS Tick irqn + BLX IRQ_Enable ; Enable OS Tick interrupt +SVC_ContextCheck + ADD R12, R12, #I_T_RUN_OFS ; Load address of osRtxInfo.thread.run + LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next + CMP R0, R1 ; Check if context switch is required + BEQ osRtxContextExit ; Exit if curr and next are equal + B osRtxContextSwitch ; Continue in context switcher + +SVC_User + PUSH {R4, R5} + LDR R5,=osRtxUserSVC ; Load address of SVC table + LDR R4,[R5] ; Load SVC maximum number + CMP R12,R4 ; Check SVC number range + BHI SVC_Done ; Branch if out of range + + LDR R12,[R5,R12,LSL #2] ; Load SVC Function Address + BLX R12 ; Call SVC Function + +SVC_Done + POP {R4, R5, R12, LR} + RFEFD SP! ; Return from exception + + ENDP + + +osRtxContextSwitch\ + PROC + EXPORT osRtxContextSwitch + + ; R0 = osRtxInfo.thread.run.curr + ; R1 = osRtxInfo.thread.run.next + ; R12 = &osRtxInfo.thread.run + + CMP R0, #0 ; Is osRtxInfo.thread.run.curr == 0 + ADDEQ SP, SP, #32 ; Equal, curr deleted, adjust current SP + BEQ osRtxContextRestore ; Restore context, run.curr = run.next; + +osRtxContextSave + SUB SP, SP, #4 + STM SP, {SP}^ ; Save SP_usr to current stack + POP {R3} ; Pop SP_usr into R3 + + SUB R3, R3, #64 ; Adjust user sp to end of basic frame (R4) + STMIA R3!, {R4-R11} ; Save R4-R11 to user + POP {R4-R8} ; Pop current R0-R12 into R4-R8 + STMIA R3!, {R4-R8} ; Store them to user stack + STM R3, {LR}^ ; Store LR_usr directly + ADD R3, R3, #4 ; Adjust user sp to PC + POP {R4-R6} ; Pop current LR, PC, CPSR + STMIA R3!, {R5-R6} ; Restore user PC and CPSR + + SUB R3, R3, #64 ; Adjust user sp to R4 + + ; Check if VFP state need to be saved + MRC p15, 0, R2, c1, c0, 2 ; VFP/NEON access enabled? (CPACR) + AND R2, R2, #0x00F00000 + CMP R2, #0x00F00000 + BNE osRtxContextSave1 ; Continue, no VFP + + VMRS R2, FPSCR + STMDB R3!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16 + VSTMDB R3!, {D0-D15} + LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that VFP/D16 state is stacked + ORR R2, R2, #2 + STRB R2, [R0, #TCB_SP_FRAME] + ENDIF + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + VSTMDB R3!, {D0-D15} + VSTMDB R3!, {D16-D31} + LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that NEON/D32 state is stacked + ORR R2, R2, #4 + STRB R2, [R0, #TCB_SP_FRAME] + ENDIF + +osRtxContextSave1 + STR R3, [R0, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr + +osRtxContextRestore + STR R1, [R12] ; Store run.next to run.curr + LDR R3, [R1, #TCB_SP_OFS] ; Load next osRtxThread_t.sp + LDRB R2, [R1, #TCB_SP_FRAME] ; Load next osRtxThread_t.stack_frame + + ANDS R2, R2, #0x6 ; Check stack frame for VFP context + MRC p15, 0, R2, c1, c0, 2 ; Read CPACR + ANDEQ R2, R2, #0xFF0FFFFF ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state + ORRNE R2, R2, #0x00F00000 ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state + MCR p15, 0, R2, c1, c0, 2 ; Write CPACR + BEQ osRtxContextRestore1 ; No VFP + ISB ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + VLDMIA R3!, {D16-D31} + ENDIF + VLDMIA R3!, {D0-D15} + LDR R2, [R3] + VMSR FPSCR, R2 + ADD R3, R3, #8 + +osRtxContextRestore1 + LDMIA R3!, {R4-R11} ; Restore R4-R11 + MOV R12, R3 ; Move sp pointer to R12 + ADD R3, R3, #32 ; Adjust sp + PUSH {R3} ; Push sp onto stack + LDMIA SP, {SP}^ ; Restore SP_usr + ADD SP, SP, #4 ; Adjust SP_svc + LDMIA R12!, {R0-R3} ; Restore User R0-R3 + LDR LR, [R12, #12] ; Load SPSR into LR + MSR SPSR_CXSF, LR ; Restore SPSR + ADD R12, R12, #4 ; Adjust pointer to LR + LDM R12, {LR}^ ; Restore LR_usr directly into LR + LDR LR, [R12, #4] ; Restore LR + LDR R12, [R12, #-4] ; Restore R12 + + MOVS PC, LR ; Return from exception + +osRtxContextExit + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + + ENDP + + END diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S index 74c8a84a45c..8fab32aabe7 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S @@ -24,7 +24,7 @@ ; */ -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S index 74c8a84a45c..8fab32aabe7 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S @@ -24,7 +24,7 @@ ; */ -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S similarity index 94% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S index 41e4beb713f..1586a95549d 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_ARM/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S @@ -23,7 +23,12 @@ ; * ----------------------------------------------------------------------------- ; */ -I_T_RUN_OFS EQU 28 ; osInfo.thread.run offset + + IF :LNOT::DEF:__DOMAIN_NS +__DOMAIN_NS EQU 0 + ENDIF + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SM_OFS EQU 48 ; TCB.stack_mem offset TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset @@ -46,10 +51,10 @@ SVC_Handler PROC EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S -#endif + ENDIF MRS R0,PSP ; Get PSP LDR R1,[R0,#24] ; Load saved PC from stack @@ -74,7 +79,7 @@ SVC_Context CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -82,7 +87,7 @@ SVC_ContextSave BL TZ_StoreContext_S ; Store secure context MOV LR,R7 ; Set EXC_RETURN POP {R1,R2,R3,R7} ; Restore registers -#endif + ENDIF SVC_ContextSave1 MRS R0,PSP ; Get PSP @@ -105,13 +110,13 @@ SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers -#endif + ENDIF SVC_ContextRestore1 MOV R1,R2 @@ -122,16 +127,16 @@ SVC_ContextRestore1 ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 LSLS R0,R0,#25 ; Check domain of interrupted thread BPL SVC_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP MSR PSP,R0 ; Set PSP BX LR ; Exit from handler -#else + ELSE LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base MSR PSPLIM,R0 ; Set PSPLIM -#endif + ENDIF SVC_ContextRestore2 LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -201,10 +206,10 @@ SysTick_Handler PROC Sys_Context PROC EXPORT Sys_Context IMPORT osRtxInfo -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S -#endif + ENDIF LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run LDM R3!,{R1,R2} ; Load osRtxInfo.thread.run: curr & next @@ -212,7 +217,7 @@ Sys_Context PROC BEQ Sys_ContextExit ; Branch when threads are the same Sys_ContextSave -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -225,7 +230,7 @@ Sys_ContextSave MRS R0,PSP ; Get PSP STR R0,[R1,#TCB_SP_OFS] ; Store SP B Sys_ContextSave2 -#endif + ENDIF Sys_ContextSave1 MRS R0,PSP ; Get PSP @@ -248,13 +253,13 @@ Sys_ContextSwitch STR R2,[R3] ; osRtxInfo.run: curr = next Sys_ContextRestore -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers BL TZ_LoadContext_S ; Load secure context POP {R2,R3} ; Restore registers -#endif + ENDIF Sys_ContextRestore1 MOV R1,R2 @@ -265,16 +270,16 @@ Sys_ContextRestore1 ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN -#ifdef __DOMAIN_NS + IF __DOMAIN_NS = 1 LSLS R0,R0,#25 ; Check domain of interrupted thread BPL Sys_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP MSR PSP,R0 ; Set PSP BX LR ; Exit from handler -#else + ELSE LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base MSR PSPLIM,R0 ; Set PSPLIM -#endif + ENDIF Sys_ContextRestore2 LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -295,4 +300,4 @@ Sys_ContextExit ENDP - END \ No newline at end of file + END diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl_ns.S new file mode 100644 index 00000000000..10d31709212 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl_ns.S @@ -0,0 +1,3 @@ +__DOMAIN_NS EQU 1 + INCLUDE irq_armv8mbl.s + END diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_ARM/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_ARM/irq_cm3.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S index b951538c826..2fd6618f03a 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_ARM/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S @@ -24,7 +24,7 @@ ; */ -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S new file mode 100644 index 00000000000..b8b25a1a324 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S @@ -0,0 +1,277 @@ +;/* +; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: ARMv8M Mainline Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + + IF :LNOT::DEF:__DOMAIN_NS +__DOMAIN_NS EQU 0 + ENDIF + + IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16") +__FPU_USED EQU 1 + ELSE +__FPU_USED EQU 0 + ENDIF + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SM_OFS EQU 48 ; TCB.stack_mem offset +TCB_SP_OFS EQU 56 ; TCB.SP offset +TCB_SF_OFS EQU 34 ; TCB.stack_frame offset +TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset + + + PRESERVE8 + THUMB + + + AREA |.constdata|, DATA, READONLY + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + AREA |.text|, CODE, READONLY + + +SVC_Handler PROC + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + IF __DOMAIN_NS = 1 + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + ENDIF + + MRS R0,PSP ; Get PSP + LDR R1,[R0,#24] ; Load saved PC from stack + LDRB R1,[R1,#-2] ; Load SVC number + CMP R1,#0 + BNE SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save PSP and EXC_RETURN + LDM R0,{R0-R3,R12} ; Load function parameters and address from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore PSP and EXC_RETURN + STM R12,{R0-R1} ; Store function return values + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + BXEQ LR ; Exit when threads are the same + + IF __FPU_USED = 1 + CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted + TST LR,#0x10 ; Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 ; FPCCR Address + LDR R0,[R1] ; Load FPCCR + BIC R0,#1 ; Clear LSPACT (Lazy state) + STR R0,[R1] ; Store FPCCR + B SVC_ContextSwitch + ELSE + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted + ENDIF + +SVC_ContextSave + IF __DOMAIN_NS = 1 + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + ENDIF + +SVC_ContextSave1 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 + IF __FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 + ENDIF + +SVC_ContextSave2 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +SVC_ContextSwitch + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + +SVC_ContextRestore + IF __DOMAIN_NS = 1 + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + ENDIF + +SVC_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + + IF __DOMAIN_NS = 1 + TST LR,#0x40 ; Check domain of interrupted thread + BNE SVC_ContextRestore2 ; Branch if secure + ENDIF + + IF __FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 + ENDIF + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +SVC_ContextRestore2 + MSR PSP,R0 ; Set PSP + +SVC_Exit + BX LR ; Exit from handler + +SVC_User + PUSH {R4,LR} ; Save registers + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Done ; Branch if out of range + + LDR R4,[R2,R1,LSL #2] ; Load address of SVC function + + LDM R0,{R0-R3} ; Load function parameters from stack + BLX R4 ; Call service function + MRS R4,PSP ; Get PSP + STR R0,[R4] ; Store function return value + +SVC_Done + POP {R4,PC} ; Return from handler + + ALIGN + ENDP + + +PendSV_Handler PROC + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R4,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R4,LR} ; Restore EXC_RETURN + B Sys_Context + + ALIGN + ENDP + + +SysTick_Handler PROC + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R4,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R4,LR} ; Restore EXC_RETURN + B Sys_Context + + ALIGN + ENDP + + +Sys_Context PROC + EXPORT Sys_Context + IMPORT osRtxInfo + IF __DOMAIN_NS = 1 + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S + ENDIF + + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + BXEQ LR ; Exit when threads are the same + +Sys_ContextSave + IF __DOMAIN_NS = 1 + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + TST LR,#0x40 ; Check domain of interrupted thread + MRSNE R0,PSP ; Get PSP + BNE Sys_ContextSave2 ; Branch if secure + ENDIF + +Sys_ContextSave1 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 + IF __FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 + ENDIF + +Sys_ContextSave2 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +Sys_ContextSwitch + STR R2,[R3] ; osRtxInfo.run: curr = next + +Sys_ContextRestore + IF __DOMAIN_NS = 1 + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers + ENDIF + +Sys_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + + IF __DOMAIN_NS = 1 + TST LR,#0x40 ; Check domain of interrupted thread + BNE Sys_ContextRestore2 ; Branch if secure + ENDIF + + IF __FPU_USED = 1 + TST LR,#0x10 ; Check if extended stack frame + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 + ENDIF + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +Sys_ContextRestore2 + MSR PSP,R0 ; Set PSP + +Sys_ContextExit + BX LR ; Exit from handler + + ALIGN + ENDP + + + END diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml_ns.S new file mode 100644 index 00000000000..b868bab6a31 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml_ns.S @@ -0,0 +1,3 @@ +__DOMAIN_NS EQU 1 + INCLUDE irq_armv8mml.s + END diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S index 84ad0b53618..44d0c7cb4a9 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_ARM/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -24,7 +24,7 @@ ; */ -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S new file mode 100644 index 00000000000..aa40e0d3649 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Exception handlers + * + * ----------------------------------------------------------------------------- + */ + + .file "irq_ca.S" + .syntax unified + + .equ MODE_FIQ, 0x11 + .equ MODE_IRQ, 0x12 + .equ MODE_SVC, 0x13 + .equ MODE_ABT, 0x17 + .equ MODE_UND, 0x1B + + .equ CPSR_BIT_T, 0x20 + + .equ K_STATE_RUNNING, 2 // osKernelState_t::osKernelRunning + .equ I_K_STATE_OFS, 8 // osRtxInfo.kernel.state offset + .equ I_TICK_IRQN_OFS, 16 // osRtxInfo.tick_irqn offset + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset + .equ TCB_SP_FRAME, 34 // osRtxThread_t.stack_frame offset + .equ TCB_SP_OFS, 56 // osRtxThread_t.sp offset + + + .section ".rodata" + .global irqRtxLib // Non weak library reference +irqRtxLib: + .byte 0 + + .section ".data" + .global IRQ_PendSV +IRQ_NestLevel: + .word 0 // IRQ nesting level counter +IRQ_PendSV: + .byte 0 // Pending SVC flag +SVC_Active: + .byte 0 // SVC handler execution active flag + + .arm + .section ".text" + .align 4 + + + .type Undef_Handler, %function + .global Undef_Handler + .fnstart + .cantunwind +Undef_Handler: + + SRSFD SP!, #MODE_UND + PUSH {R0-R4, R12} // Save APCS corruptible registers to UND mode stack + + MRS R0, SPSR + TST R0, #CPSR_BIT_T // Check mode + MOVEQ R1, #4 // R1 = 4 ARM mode + MOVNE R1, #2 // R1 = 2 Thumb mode + SUB R0, LR, R1 + LDREQ R0, [R0] // ARM mode - R0 points to offending instruction + BEQ Undef_Cont + + // Thumb instruction + // Determine if it is a 32-bit Thumb instruction + LDRH R0, [R0] + MOV R2, #0x1C + CMP R2, R0, LSR #11 + BHS Undef_Cont // 16-bit Thumb instruction + + // 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +Undef_Cont: + MOV R2, LR // Set LR to third argument + + AND R12, SP, #4 // Ensure stack is 8-byte aligned + SUB SP, SP, R12 // Adjust stack + PUSH {R12, LR} // Store stack adjustment and dummy LR + + // R0 =Offending instruction, R1 =2(Thumb) or =4(ARM) + BL CUndefHandler + + POP {R12, LR} // Get stack adjustment & discard dummy LR + ADD SP, SP, R12 // Unadjust stack + + LDR LR, [SP, #24] // Restore stacked LR and possibly adjust for retry + SUB LR, LR, R0 + LDR R0, [SP, #28] // Restore stacked SPSR + MSR SPSR_cxsf, R0 + POP {R0-R4, R12} // Restore stacked APCS registers + ADD SP, SP, #8 // Adjust SP for already-restored banked registers + MOVS PC, LR + + .fnend + .size Undef_Handler, .-Undef_Handler + + + .type PAbt_Handler, %function + .global PAbt_Handler + .fnstart + .cantunwind +PAbt_Handler: + + SUB LR, LR, #4 // Pre-adjust LR + SRSFD SP!, #MODE_ABT // Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} // Save APCS corruptible registers to ABT mode stack + MRC p15, 0, R0, c5, c0, 1 // IFSR + MRC p15, 0, R1, c6, c0, 2 // IFAR + + MOV R2, LR // Set LR to third argument + + AND R12, SP, #4 // Ensure stack is 8-byte aligned + SUB SP, SP, R12 // Adjust stack + PUSH {R12, LR} // Store stack adjustment and dummy LR + + BL CPAbtHandler + + POP {R12, LR} // Get stack adjustment & discard dummy LR + ADD SP, SP, R12 // Unadjust stack + + POP {R0-R4, R12} // Restore stack APCS registers + RFEFD SP! // Return from exception + + .fnend + .size PAbt_Handler, .-PAbt_Handler + + + .type DAbt_Handler, %function + .global DAbt_Handler + .fnstart + .cantunwind +DAbt_Handler: + SUB LR, LR, #8 // Pre-adjust LR + SRSFD SP!, #MODE_ABT // Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} // Save APCS corruptible registers to ABT mode stack + CLREX // State of exclusive monitors unknown after taken data abort + MRC p15, 0, R0, c5, c0, 0 // DFSR + MRC p15, 0, R1, c6, c0, 0 // DFAR + + MOV R2, LR // Set LR to third argument + + AND R12, SP, #4 // Ensure stack is 8-byte aligned + SUB SP, SP, R12 // Adjust stack + PUSH {R12, LR} // Store stack adjustment and dummy LR + + BL CDAbtHandler + + POP {R12, LR} // Get stack adjustment & discard dummy LR + ADD SP, SP, R12 // Unadjust stack + + POP {R0-R4, R12} // Restore stacked APCS registers + RFEFD SP! // Return from exception + + .fnend + .size DAbt_Handler, .-DAbt_Handler + + + .type IRQ_Handler, %function + .global IRQ_Handler + .fnstart + .cantunwind +IRQ_Handler: + + SUB LR, LR, #4 // Pre-adjust LR + SRSFD SP!, #MODE_SVC // Save LR_irq and SPRS_irq on to the SVC stack + CPS #MODE_SVC // Change to SVC mode + PUSH {R0-R3, R12, LR} // Save APCS corruptible registers + + MOV R3, SP // Move SP into R3 + AND R3, R3, #4 // Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 // Adjust stack + PUSH {R3, R4} // Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ // Retrieve interrupt ID into R0 + MOV R4, R0 // Move interrupt ID to R4 + + LDR R1, =IRQ_NestLevel + LDR R3, [R1] // Load IRQ nest level and increment it + ADD R3, R3, #1 + STR R3, [R1] + + BLX IRQ_GetHandler // Retrieve interrupt handler address for current ID + CMP R0, #0 // Check if handler address is 0 + BEQ IRQ_End // If 0, end interrupt and return + + CPSIE i // Re-enable interrupts + BLX R0 // Call IRQ handler + CPSID i // Disable interrupts + +IRQ_End: + MOV R0, R4 // Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt // Signal end of interrupt + + LDR R2, =IRQ_NestLevel + LDR R1, [R2] // Load IRQ nest level and + SUBS R1, R1, #1 // decrement it + STR R1, [R2] + BNE IRQ_Exit // Not zero, exit from IRQ handler + + LDR R0, =SVC_Active + LDRB R0, [R0] // Load SVC_Active flag + CMP R0, #0 + BNE IRQ_SwitchCheck // Skip post processing when SVC active + + // RTX IRQ post processing check + PUSH {R5, R6} // Save user R5 and R6 + MOV R6, #0 + LDR R5, =IRQ_PendSV // Load address of IRQ_PendSV flag + B IRQ_PendCheck +IRQ_PendExec: + STRB R6, [R5] // Clear PendSV flag + CPSIE i // Re-enable interrupts + BLX osRtxPendSV_Handler // Post process pending objects + CPSID i // Disable interrupts +IRQ_PendCheck: + LDRB R0, [R5] // Load PendSV flag + CMP R0, #1 // Compare PendSV value + BEQ IRQ_PendExec // Branch to IRQ_PendExec if PendSV is set + POP {R5, R6} // Restore user R5 and R6 + +IRQ_SwitchCheck: + // RTX IRQ context switch check + LDR R12, =osRtxInfo+I_T_RUN_OFS // Load address of osRtxInfo.run + LDM R12, {R0, R1} // Load osRtxInfo.thread.run: curr & next + CMP R0, R1 // Check if context switch is required + BEQ IRQ_Exit + + POP {R3, R4} // Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 // Unadjust stack + B osRtxContextSwitch + +IRQ_Exit: + POP {R3, R4} // Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 // Unadjust stack + + POP {R0-R3, R12, LR} // Restore stacked APCS registers + RFEFD SP! // Return from IRQ handler + + .fnend + .size IRQ_Handler, .-IRQ_Handler + + + .type SVC_Handler, %function + .global SVC_Handler + .fnstart + .cantunwind +SVC_Handler: + + SRSFD SP!, #MODE_SVC // Store SPSR_svc and LR_svc onto SVC stack + PUSH {R12, LR} + + MRS R12, SPSR // Load SPSR + TST R12, #CPSR_BIT_T // Thumb bit set? + LDRHNE R12, [LR,#-2] // Thumb: load halfword + BICNE R12, R12, #0xFF00 // extract SVC number + LDREQ R12, [LR,#-4] // ARM: load word + BICEQ R12, R12, #0xFF000000 // extract SVC number + CMP R12, #0 // Compare SVC number + BNE SVC_User // Branch if User SVC + + PUSH {R0-R3} + + LDR R3, =osRtxInfo + LDR R1, [R3, #I_K_STATE_OFS] // Load RTX5 kernel state + CMP R1, #K_STATE_RUNNING // Check osKernelRunning + BLT SVC_FuncCall // Continue if kernel is not running + LDR R0, [R3, #I_TICK_IRQN_OFS] // Load OS Tick irqn + BLX IRQ_Disable // Disable OS Tick interrupt +SVC_FuncCall: + LDR R0, =SVC_Active + MOV R1, #1 + STRB R1, [R0] // Set SVC_Active flag + POP {R0-R3} + + LDR R12, [SP] // Reload R12 from stack + + CPSIE i // Re-enable interrupts + BLX R12 // Branch to SVC function + CPSID i // Disable interrupts + + SUB SP, SP, #4 // Adjust SP + STM SP, {SP}^ // Store SP_usr onto stack + POP {R12} // Pop SP_usr into R12 + SUB R12, R12, #16 // Adjust pointer to SP_usr + LDMDB R12, {R2,R3} // Load return values from SVC function + PUSH {R0-R3} // Push return values to stack + + PUSH {R4, R5} // Save R4 and R5 + MOV R5, #0 + LDR R4, =IRQ_PendSV // Load address of IRQ_PendSV + B SVC_PendCheck +SVC_PendExec: + STRB R5, [R4] // Clear IRQ_PendSV flag + CPSIE i // Re-enable interrupts + BLX osRtxPendSV_Handler // Post process pending objects + CPSID i // Disable interrupts +SVC_PendCheck: + LDRB R0, [R4] // Load IRQ_PendSV flag + CMP R0, #1 // Compare IRQ_PendSV value + BEQ SVC_PendExec // Branch to SVC_PendExec if IRQ_PendSV is set + POP {R4, R5} // Restore R4 and R5 + + LDR R0, =SVC_Active + MOV R1, #0 + STRB R1, [R0] // Clear SVC_Active flag + + LDR R12, =osRtxInfo + LDR R1, [R12, #I_K_STATE_OFS] // Load RTX5 kernel state + CMP R1, #K_STATE_RUNNING // Check osKernelRunning + BLT SVC_ContextCheck // Continue if kernel is not running + LDR R0, [R12, #I_TICK_IRQN_OFS] // Load OS Tick irqn + BLX IRQ_Enable // Enable OS Tick interrupt +SVC_ContextCheck: + ADD R12, R12, #I_T_RUN_OFS // Load address of osRtxInfo.thread.run + LDM R12, {R0, R1} // Load osRtxInfo.thread.run: curr & next + CMP R0, R1 // Check if context switch is required + BEQ osRtxContextExit // Exit if curr and next are equal + B osRtxContextSwitch // Continue in context switcher + +SVC_User: + PUSH {R4, R5} + LDR R5,=osRtxUserSVC // Load address of SVC table + LDR R4,[R5] // Load SVC maximum number + CMP R12,R4 // Check SVC number range + BHI SVC_Done // Branch if out of range + + LDR R12,[R5,R12,LSL #2] // Load SVC Function Address + BLX R12 // Call SVC Function + +SVC_Done: + POP {R4, R5, R12, LR} + RFEFD SP! // Return from exception + + .fnend + .size SVC_Handler, .-SVC_Handler + + + .type osRtxContextSwitch, %function + .global osRtxContextSwitch + .fnstart + .cantunwind +osRtxContextSwitch: + + // R0 = osRtxInfo.thread.run.curr + // R1 = osRtxInfo.thread.run.next + // R12 = &osRtxInfo.thread.run + + CMP R0, #0 // Is osRtxInfo.thread.run.curr == 0 + ADDEQ SP, SP, #32 // Equal, curr deleted, adjust current SP + BEQ osRtxContextRestore // Restore context, run.curr = run.next; + +osRtxContextSave: + SUB SP, SP, #4 + STM SP, {SP}^ // Save SP_usr to current stack + POP {R3} // Pop SP_usr into R3 + + SUB R3, R3, #64 // Adjust user sp to end of basic frame (R4) + STMIA R3!, {R4-R11} // Save R4-R11 to user + POP {R4-R8} // Pop current R0-R12 into R4-R8 + STMIA R3!, {R4-R8} // Store them to user stack + STM R3, {LR}^ // Store LR_usr directly + ADD R3, R3, #4 // Adjust user sp to PC + POP {R4-R6} // Pop current LR, PC, CPSR + STMIA R3!, {R5-R6} // Restore user PC and CPSR + + SUB R3, R3, #64 // Adjust user sp to R4 + + // Check if VFP state need to be saved + MRC p15, 0, R2, c1, c0, 2 // VFP/NEON access enabled? (CPACR) + AND R2, R2, #0x00F00000 + CMP R2, #0x00F00000 + BNE osRtxContextSave1 // Continue, no VFP + + VMRS R2, FPSCR + STMDB R3!, {R2,R12} // Push FPSCR, maintain 8-byte alignment + #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 16 + VSTMDB R3!, {D0-D15} + LDRB R2, [R0, #TCB_SP_FRAME] // Record in TCB that VFP/D16 state is stacked + ORR R2, R2, #2 + STRB R2, [R0, #TCB_SP_FRAME] + #endif + #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 + VSTMDB R3!, {D0-D15} + VSTMDB R3!, {D16-D31} + LDRB R2, [R0, #TCB_SP_FRAME] // Record in TCB that NEON/D32 state is stacked + ORR R2, R2, #4 + STRB R2, [R0, #TCB_SP_FRAME] + #endif + +osRtxContextSave1: + STR R3, [R0, #TCB_SP_OFS] // Store user sp to osRtxInfo.thread.run.curr + +osRtxContextRestore: + STR R1, [R12] // Store run.next to run.curr + LDR R3, [R1, #TCB_SP_OFS] // Load next osRtxThread_t.sp + LDRB R2, [R1, #TCB_SP_FRAME] // Load next osRtxThread_t.stack_frame + + ANDS R2, R2, #0x6 // Check stack frame for VFP context + MRC p15, 0, R2, c1, c0, 2 // Read CPACR + ANDEQ R2, R2, #0xFF0FFFFF // Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state + ORRNE R2, R2, #0x00F00000 // Enable VFP/NEON access if incoming task does have stacked VFP/NEON state + MCR p15, 0, R2, c1, c0, 2 // Write CPACR + BEQ osRtxContextRestore1 // No VFP + ISB // Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway + #if TARGET_FEATURE_EXTENSION_REGISTER_COUNT == 32 + VLDMIA R3!, {D16-D31} + #endif + VLDMIA R3!, {D0-D15} + LDR R2, [R3] + VMSR FPSCR, R2 + ADD R3, R3, #8 + +osRtxContextRestore1: + LDMIA R3!, {R4-R11} // Restore R4-R11 + MOV R12, R3 // Move sp pointer to R12 + ADD R3, R3, #32 // Adjust sp + PUSH {R3} // Push sp onto stack + LDMIA SP, {SP}^ // Restore SP_usr + ADD SP, SP, #4 // Adjust SP_svc + LDMIA R12!, {R0-R3} // Restore User R0-R3 + LDR LR, [R12, #12] // Load SPSR into LR + MSR SPSR_cxsf, LR // Restore SPSR + ADD R12, R12, #4 // Adjust pointer to LR + LDM R12, {LR}^ // Restore LR_usr directly into LR + LDR LR, [R12, #4] // Restore LR + LDR R12, [R12, #-4] // Restore R12 + + MOVS PC, LR // Return from exception + +osRtxContextExit: + POP {R0-R3, R12, LR} // Restore stacked APCS registers + RFEFD SP! // Return from exception + + .fnend + .size osRtxContextSwitch, .-osRtxContextSwitch + + .end diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_GCC/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_GCC/irq_cm0.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S index 5362c196960..59288e24336 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_GCC/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S @@ -27,7 +27,7 @@ .file "irq_cm0.S" .syntax unified - .equ I_T_RUN_OFS, 28 // osRtxInfo.thread.run offset + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SP_OFS, 56 // TCB.SP offset .section ".rodata" diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_GCC/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_GCC/irq_cm0.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S index 5362c196960..59288e24336 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_GCC/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S @@ -27,7 +27,7 @@ .file "irq_cm0.S" .syntax unified - .equ I_T_RUN_OFS, 28 // osRtxInfo.thread.run offset + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SP_OFS, 56 // TCB.SP offset .section ".rodata" diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_GCC/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S similarity index 95% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_GCC/irq_armv8mbl.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S index 1b6b119e536..497e5c917f1 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_GCC/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S @@ -27,7 +27,11 @@ .file "irq_armv8mbl.S" .syntax unified - .equ I_T_RUN_OFS, 28 // osRtxInfo.thread.run offset + .ifndef __DOMAIN_NS + .equ __DOMAIN_NS, 0 + .endif + + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SM_OFS, 48 // TCB.stack_mem offset .equ TCB_SP_OFS, 56 // TCB.SP offset .equ TCB_SF_OFS, 34 // TCB.stack_frame offset @@ -50,6 +54,7 @@ irqRtxLib: .fnstart .cantunwind SVC_Handler: + MRS R0,PSP // Get PSP LDR R1,[R0,#24] // Load saved PC from stack SUBS R1,R1,#2 // Point to SVC instruction @@ -73,7 +78,7 @@ SVC_Context: CBZ R1,SVC_ContextSwitch // Branch if running thread is deleted SVC_ContextSave: -#ifdef __DOMAIN_NS + .if __DOMAIN_NS == 1 LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 // Branch if there is no secure context PUSH {R1,R2,R3,R7} // Save registers @@ -81,7 +86,7 @@ SVC_ContextSave: BL TZ_StoreContext_S // Store secure context MOV LR,R7 // Set EXC_RETURN POP {R1,R2,R3,R7} // Restore registers -#endif + .endif SVC_ContextSave1: MRS R0,PSP // Get PSP @@ -104,13 +109,13 @@ SVC_ContextSwitch: STR R2,[R3] // osRtxInfo.thread.run: curr = next SVC_ContextRestore: -#ifdef __DOMAIN_NS + .if __DOMAIN_NS == 1 LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 // Branch if there is no secure context PUSH {R2,R3} // Save registers BL TZ_LoadContext_S // Load secure context POP {R2,R3} // Restore registers -#endif + .endif SVC_ContextRestore1: MOV R1,R2 @@ -121,16 +126,16 @@ SVC_ContextRestore1: ORRS R0,R1 MOV LR,R0 // Set EXC_RETURN -#ifdef __DOMAIN_NS + .if __DOMAIN_NS == 1 LSLS R0,R0,#25 // Check domain of interrupted thread BPL SVC_ContextRestore2 // Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] // Load SP MSR PSP,R0 // Set PSP BX LR // Exit from handler -#else + .else LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base MSR PSPLIM,R0 // Set PSPLIM -#endif + .endif SVC_ContextRestore2: LDR R0,[R2,#TCB_SP_OFS] // Load SP @@ -216,7 +221,7 @@ Sys_Context: BEQ Sys_ContextExit // Branch when threads are the same Sys_ContextSave: -#ifdef __DOMAIN_NS + .if __DOMAIN_NS == 1 LDR R0,[R1,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 // Branch if there is no secure context PUSH {R1,R2,R3,R7} // Save registers @@ -229,7 +234,7 @@ Sys_ContextSave: MRS R0,PSP // Get PSP STR R0,[R1,#TCB_SP_OFS] // Store SP B Sys_ContextSave2 -#endif + .endif Sys_ContextSave1: MRS R0,PSP // Get PSP @@ -252,13 +257,13 @@ Sys_ContextSwitch: STR R2,[R3] // osRtxInfo.run: curr = next Sys_ContextRestore: -#ifdef __DOMAIN_NS + .if __DOMAIN_NS == 1 LDR R0,[R2,#TCB_TZM_OFS] // Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 // Branch if there is no secure context PUSH {R2,R3} // Save registers BL TZ_LoadContext_S // Load secure context POP {R2,R3} // Restore registers -#endif + .endif Sys_ContextRestore1: MOV R1,R2 @@ -269,16 +274,16 @@ Sys_ContextRestore1: ORRS R0,R1 MOV LR,R0 // Set EXC_RETURN -#ifdef __DOMAIN_NS + .if __DOMAIN_NS == 1 LSLS R0,R0,#25 // Check domain of interrupted thread BPL Sys_ContextRestore2 // Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] // Load SP MSR PSP,R0 // Set PSP BX LR // Exit from handler -#else + .else LDR R0,[R2,#TCB_SM_OFS] // Load stack memory base MSR PSPLIM,R0 // Set PSPLIM -#endif + .endif Sys_ContextRestore2: LDR R0,[R2,#TCB_SP_OFS] // Load SP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl_ns.S new file mode 100644 index 00000000000..b8bd9c4a49e --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl_ns.S @@ -0,0 +1,3 @@ + .equ __DOMAIN_NS, 1 + .include "../Source/GCC/irq_armv8mbl.S" + .end diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_GCC/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_GCC/irq_cm3.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S index f8684da2e41..875b03bc6fc 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_GCC/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S @@ -27,7 +27,7 @@ .file "irq_cm3.S" .syntax unified - .equ I_T_RUN_OFS, 28 // osRtxInfo.thread.run offset + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SP_OFS, 56 // TCB.SP offset .section ".rodata" diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S index c01721b1521..3248b9eb3b1 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M33/TOOLCHAIN_GCC/irq_armv8mml.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S @@ -35,7 +35,7 @@ .equ __FPU_USED, 0 .endif - .equ I_T_RUN_OFS, 28 // osRtxInfo.thread.run offset + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SM_OFS, 48 // TCB.stack_mem offset .equ TCB_SP_OFS, 56 // TCB.SP offset .equ TCB_SF_OFS, 34 // TCB.stack_frame offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp.S new file mode 100644 index 00000000000..4e78031ed42 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp.S @@ -0,0 +1,3 @@ + .equ __FPU_USED, 1 + .include "../Source/GCC/irq_armv8mml.S" + .end diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp_ns.S new file mode 100644 index 00000000000..3f7c7243324 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_fp_ns.S @@ -0,0 +1,4 @@ + .equ __FPU_USED, 1 + .equ __DOMAIN_NS, 1 + .include "../Source/GCC/irq_armv8mml.S" + .end diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_ns.S new file mode 100644 index 00000000000..fdd030e6472 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml_ns.S @@ -0,0 +1,3 @@ + .equ __DOMAIN_NS, 1 + .include "../Source/GCC/irq_armv8mml.S" + .end diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S index fd57b7fd58e..b38f9d5de76 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_GCC/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -27,7 +27,7 @@ .file "irq_cm4f.S" .syntax unified - .equ I_T_RUN_OFS, 28 // osRtxInfo.thread.run offset + .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SP_OFS, 56 // TCB.SP offset .equ TCB_SF_OFS, 34 // TCB.stack_frame offset @@ -80,7 +80,6 @@ SVC_Context: SVC_ContextSave: STMDB R12!,{R4-R11} // Save R4..R11 - #ifdef __FPU_PRESENT TST LR,#0x10 // Check if extended stack frame IT EQ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S new file mode 100644 index 00000000000..acb2b12344d --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S @@ -0,0 +1,431 @@ +;/* +; * Copyright (c) 2013-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: Cortex-A Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + NAME irq_ca.s + +MODE_FIQ EQU 0x11 +MODE_IRQ EQU 0x12 +MODE_SVC EQU 0x13 +MODE_ABT EQU 0x17 +MODE_UND EQU 0x1B + +CPSR_BIT_T EQU 0x20 + +K_STATE_RUNNING EQU 2 ; osKernelState_t::osKernelRunning +I_K_STATE_OFS EQU 8 ; osRtxInfo.kernel.state offset +I_TICK_IRQN_OFS EQU 16 ; osRtxInfo.tick_irqn offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SP_FRAME EQU 34 ; osRtxThread_t.stack_frame offset +TCB_SP_OFS EQU 56 ; osRtxThread_t.sp offset + + + PRESERVE8 + ARM + + + SECTION .rodata:DATA:NOROOT(2) + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + SECTION .data:DATA:NOROOT(2) + EXPORT IRQ_PendSV +IRQ_NestLevel DCD 0 ; IRQ nesting level counter +IRQ_PendSV DCB 0 ; Pending SVC flag +SVC_Active DCB 0 ; SVC handler execution active flag + + + SECTION .text:CODE:NOROOT(2) + + +Undef_Handler + EXPORT Undef_Handler + IMPORT CUndefHandler + + SRSFD SP!, #MODE_UND + PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack + + MRS R0, SPSR + TST R0, #CPSR_BIT_T ; Check mode + MOVEQ R1, #4 ; R1 = 4 ARM mode + MOVNE R1, #2 ; R1 = 2 Thumb mode + SUB R0, LR, R1 + LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction + BEQ Undef_Cont + + ; Thumb instruction + ; Determine if it is a 32-bit Thumb instruction + LDRH R0, [R0] + MOV R2, #0x1C + CMP R2, R0, LSR #11 + BHS Undef_Cont ; 16-bit Thumb instruction + + ; 32-bit Thumb instruction. Unaligned - reconstruct the offending instruction + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +Undef_Cont + MOV R2, LR ; Set LR to third argument + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + ; R0 =Offending instruction, R1 =2(Thumb) or =4(ARM) + BL CUndefHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry + SUB LR, LR, R0 + LDR R0, [SP, #28] ; Restore stacked SPSR + MSR SPSR_CXSF, R0 + POP {R0-R4, R12} ; Restore stacked APCS registers + ADD SP, SP, #8 ; Adjust SP for already-restored banked registers + MOVS PC, LR + + +PAbt_Handler + EXPORT PAbt_Handler + IMPORT CPAbtHandler + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + MRC p15, 0, R0, c5, c0, 1 ; IFSR + MRC p15, 0, R1, c6, c0, 2 ; IFAR + + MOV R2, LR ; Set LR to third argument + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CPAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stack APCS registers + RFEFD SP! ; Return from exception + + +DAbt_Handler + EXPORT DAbt_Handler + IMPORT CDAbtHandler + + SUB LR, LR, #8 ; Pre-adjust LR + SRSFD SP!, #MODE_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + CLREX ; State of exclusive monitors unknown after taken data abort + MRC p15, 0, R0, c5, c0, 0 ; DFSR + MRC p15, 0, R1, c6, c0, 0 ; DFAR + + MOV R2, LR ; Set LR to third argument + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CDAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + + +IRQ_Handler + EXPORT IRQ_Handler + IMPORT osRtxInfo + IMPORT IRQ_GetActiveIRQ + IMPORT IRQ_GetHandler + IMPORT IRQ_EndOfInterrupt + + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #MODE_SVC ; Save LR_irq and SPRS_irq on to the SVC stack + CPS #MODE_SVC ; Change to SVC mode + PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers + + MOV R3, SP ; Move SP into R3 + AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment + SUB SP, SP, R3 ; Adjust stack + PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4) + + BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0 + MOV R4, R0 ; Move interrupt ID to R4 + + LDR R1, =IRQ_NestLevel + LDR R3, [R1] ; Load IRQ nest level and increment it + ADD R3, R3, #1 + STR R3, [R1] + + BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID + CMP R0, #0 ; Check if handler address is 0 + BEQ IRQ_End ; If 0, end interrupt and return + + CPSIE i ; Re-enable interrupts + BLX R0 ; Call IRQ handler + CPSID i ; Disable interrupts + +IRQ_End + MOV R0, R4 ; Move interrupt ID to R0 + BLX IRQ_EndOfInterrupt ; Signal end of interrupt + + LDR R2, =IRQ_NestLevel + LDR R1, [R2] ; Load IRQ nest level and + SUBS R1, R1, #1 ; decrement it + STR R1, [R2] + BNE IRQ_Exit ; Not zero, exit from IRQ handler + + LDR R0, =SVC_Active + LDRB R0, [R0] ; Load SVC_Active flag + CMP R0, #0 + BNE IRQ_SwitchCheck ; Skip post processing when SVC active + + ; RTX IRQ post processing check + PUSH {R5, R6} ; Save user R5 and R6 + MOV R6, #0 + LDR R5, =IRQ_PendSV ; Load address of IRQ_PendSV flag + B IRQ_PendCheck +IRQ_PendExec + STRB R6, [R5] ; Clear PendSV flag + CPSIE i ; Re-enable interrupts + BLX osRtxPendSV_Handler ; Post process pending objects + CPSID i ; Disable interrupts +IRQ_PendCheck + LDRB R0, [R5] ; Load PendSV flag + CMP R0, #1 ; Compare PendSV value + BEQ IRQ_PendExec ; Branch to IRQ_PendExec if PendSV is set + POP {R5, R6} ; Restore user R5 and R6 + +IRQ_SwitchCheck + ; RTX IRQ context switch check + LDR R12, =osRtxInfo+I_T_RUN_OFS ; Load address of osRtxInfo.run + LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next + CMP R0, R1 ; Check if context switch is required + BEQ IRQ_Exit + + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + B osRtxContextSwitch + +IRQ_Exit + POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4) + ADD SP, SP, R3 ; Unadjust stack + + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from IRQ handler + + +SVC_Handler + EXPORT SVC_Handler + IMPORT IRQ_Disable + IMPORT IRQ_Enable + IMPORT osRtxPendSV_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo + + SRSFD SP!, #MODE_SVC ; Store SPSR_svc and LR_svc onto SVC stack + PUSH {R12, LR} + + MRS R12, SPSR ; Load SPSR + TST R12, #CPSR_BIT_T ; Thumb bit set? + LDRHNE R12, [LR,#-2] ; Thumb: load halfword + BICNE R12, R12, #0xFF00 ; extract SVC number + LDREQ R12, [LR,#-4] ; ARM: load word + BICEQ R12, R12, #0xFF000000 ; extract SVC number + CMP R12, #0 ; Compare SVC number + BNE SVC_User ; Branch if User SVC + + PUSH {R0-R3} + + LDR R3, =osRtxInfo + LDR R1, [R3, #I_K_STATE_OFS] ; Load RTX5 kernel state + CMP R1, #K_STATE_RUNNING ; Check osKernelRunning + BLT SVC_FuncCall ; Continue if kernel is not running + LDR R0, [R3, #I_TICK_IRQN_OFS] ; Load OS Tick irqn + BLX IRQ_Disable ; Disable OS Tick interrupt +SVC_FuncCall + LDR R0, =SVC_Active + MOV R1, #1 + STRB R1, [R0] ; Set SVC_Active flag + POP {R0-R3} + + LDR R12, [SP] ; Reload R12 from stack + + CPSIE i ; Re-enable interrupts + BLX R12 ; Branch to SVC function + CPSID i ; Disable interrupts + + SUB SP, SP, #4 ; Adjust SP + STM SP, {SP}^ ; Store SP_usr onto stack + POP {R12} ; Pop SP_usr into R12 + SUB R12, R12, #16 ; Adjust pointer to SP_usr + LDMDB R12, {R2,R3} ; Load return values from SVC function + PUSH {R0-R3} ; Push return values to stack + + PUSH {R4, R5} ; Save R4 and R5 + MOV R5, #0 + LDR R4, =IRQ_PendSV ; Load address of IRQ_PendSV + B SVC_PendCheck +SVC_PendExec + STRB R5, [R4] ; Clear IRQ_PendSV flag + CPSIE i ; Re-enable interrupts + BLX osRtxPendSV_Handler ; Post process pending objects + CPSID i ; Disable interrupts +SVC_PendCheck + LDRB R0, [R4] ; Load IRQ_PendSV flag + CMP R0, #1 ; Compare IRQ_PendSV value + BEQ SVC_PendExec ; Branch to SVC_PendExec if IRQ_PendSV is set + POP {R4, R5} ; Restore R4 and R5 + + LDR R0, =SVC_Active + MOV R1, #0 + STRB R1, [R0] ; Clear SVC_Active flag + + LDR R12, =osRtxInfo + LDR R1, [R12, #I_K_STATE_OFS] ; Load RTX5 kernel state + CMP R1, #K_STATE_RUNNING ; Check osKernelRunning + BLT SVC_ContextCheck ; Continue if kernel is not running + LDR R0, [R12, #I_TICK_IRQN_OFS] ; Load OS Tick irqn + BLX IRQ_Enable ; Enable OS Tick interrupt +SVC_ContextCheck + ADD R12, R12, #I_T_RUN_OFS ; Load address of osRtxInfo.thread.run + LDM R12, {R0, R1} ; Load osRtxInfo.thread.run: curr & next + CMP R0, R1 ; Check if context switch is required + BEQ osRtxContextExit ; Exit if curr and next are equal + B osRtxContextSwitch ; Continue in context switcher + +SVC_User + PUSH {R4, R5} + LDR R5,=osRtxUserSVC ; Load address of SVC table + LDR R4,[R5] ; Load SVC maximum number + CMP R12,R4 ; Check SVC number range + BHI SVC_Done ; Branch if out of range + + LDR R12,[R5,R12,LSL #2] ; Load SVC Function Address + BLX R12 ; Call SVC Function + +SVC_Done + POP {R4, R5, R12, LR} + RFEFD SP! ; Return from exception + + +osRtxContextSwitch + EXPORT osRtxContextSwitch + + ; R0 = osRtxInfo.thread.run.curr + ; R1 = osRtxInfo.thread.run.next + ; R12 = &osRtxInfo.thread.run + + CMP R0, #0 ; Is osRtxInfo.thread.run.curr == 0 + ADDEQ SP, SP, #32 ; Equal, curr deleted, adjust current SP + BEQ osRtxContextRestore ; Restore context, run.curr = run.next; + +osRtxContextSave + SUB SP, SP, #4 + STM SP, {SP}^ ; Save SP_usr to current stack + POP {R3} ; Pop SP_usr into R3 + + SUB R3, R3, #64 ; Adjust user sp to end of basic frame (R4) + STMIA R3!, {R4-R11} ; Save R4-R11 to user + POP {R4-R8} ; Pop current R0-R12 into R4-R8 + STMIA R3!, {R4-R8} ; Store them to user stack + STM R3, {LR}^ ; Store LR_usr directly + ADD R3, R3, #4 ; Adjust user sp to PC + POP {R4-R6} ; Pop current LR, PC, CPSR + STMIA R3!, {R5-R6} ; Restore user PC and CPSR + + SUB R3, R3, #64 ; Adjust user sp to R4 + + ; Check if VFP state need to be saved + MRC p15, 0, R2, c1, c0, 2 ; VFP/NEON access enabled? (CPACR) + AND R2, R2, #0x00F00000 + CMP R2, #0x00F00000 + BNE osRtxContextSave1 ; Continue, no VFP + + VMRS R2, FPSCR + STMDB R3!, {R2,R12} ; Push FPSCR, maintain 8-byte alignment + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 16 + VSTMDB R3!, {D0-D15} + LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that VFP/D16 state is stacked + ORR R2, R2, #2 + STRB R2, [R0, #TCB_SP_FRAME] + ENDIF + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + VSTMDB R3!, {D0-D15} + VSTMDB R3!, {D16-D31} + LDRB R2, [R0, #TCB_SP_FRAME] ; Record in TCB that NEON/D32 state is stacked + ORR R2, R2, #4 + STRB R2, [R0, #TCB_SP_FRAME] + ENDIF + +osRtxContextSave1 + STR R3, [R0, #TCB_SP_OFS] ; Store user sp to osRtxInfo.thread.run.curr + +osRtxContextRestore + STR R1, [R12] ; Store run.next to run.curr + LDR R3, [R1, #TCB_SP_OFS] ; Load next osRtxThread_t.sp + LDRB R2, [R1, #TCB_SP_FRAME] ; Load next osRtxThread_t.stack_frame + + ANDS R2, R2, #0x6 ; Check stack frame for VFP context + MRC p15, 0, R2, c1, c0, 2 ; Read CPACR + ANDEQ R2, R2, #0xFF0FFFFF ; Disable VFP/NEON access if incoming task does not have stacked VFP/NEON state + ORRNE R2, R2, #0x00F00000 ; Enable VFP/NEON access if incoming task does have stacked VFP/NEON state + MCR p15, 0, R2, c1, c0, 2 ; Write CPACR + BEQ osRtxContextRestore1 ; No VFP + ISB ; Only sync if we enabled VFP, otherwise we will context switch before next VFP instruction anyway + IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32 + VLDMIA R3!, {D16-D31} + ENDIF + VLDMIA R3!, {D0-D15} + LDR R2, [R3] + VMSR FPSCR, R2 + ADD R3, R3, #8 + +osRtxContextRestore1 + LDMIA R3!, {R4-R11} ; Restore R4-R11 + MOV R12, R3 ; Move sp pointer to R12 + ADD R3, R3, #32 ; Adjust sp + PUSH {R3} ; Push sp onto stack + LDMIA SP, {SP}^ ; Restore SP_usr + ADD SP, SP, #4 ; Adjust SP_svc + LDMIA R12!, {R0-R3} ; Restore User R0-R3 + LDR LR, [R12, #12] ; Load SPSR into LR + MSR SPSR_CXSF, LR ; Restore SPSR + ADD R12, R12, #4 ; Adjust pointer to LR + LDM R12, {LR}^ ; Restore LR_usr directly into LR + LDR LR, [R12, #4] ; Restore LR + LDR R12, [R12, #-4] ; Restore R12 + + MOVS PC, LR ; Return from exception + +osRtxContextExit + POP {R0-R3, R12, LR} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + + END diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S index 023aae3a9e7..9d116999318 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S @@ -27,7 +27,7 @@ NAME irq_cm0.s -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S index 023aae3a9e7..9d116999318 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S @@ -27,7 +27,7 @@ NAME irq_cm0.s -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl.S new file mode 100644 index 00000000000..3b4e9f3652e --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl.S @@ -0,0 +1,5 @@ + NAME irq_armv8mbl.s +#define __DOMAIN_NS 0 + INCLUDE irq_armv8mbl_common.s + + END diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_IAR/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S similarity index 96% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_IAR/irq_armv8mbl.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S index 080814f1ec2..7cce8f567f5 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M23/TOOLCHAIN_IAR/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S @@ -24,9 +24,11 @@ ; */ - NAME irq_armv8mbl.s +#ifndef __DOMAIN_NS +#define __DOMAIN_NS 0 +#endif -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SM_OFS EQU 48 ; TCB.stack_mem offset TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset @@ -34,21 +36,23 @@ TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset PRESERVE8 - SECTION .rodata:DATA:NOROOT(2) + SECTION .rodata:DATA:NOROOT(2) EXPORT irqRtxLib irqRtxLib DCB 0 ; Non weak library reference + + SECTION .text:CODE:NOROOT(2) + THUMB - SECTION .text:CODE:NOROOT(2) SVC_Handler EXPORT SVC_Handler IMPORT osRtxUserSVC IMPORT osRtxInfo -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S #endif @@ -76,7 +80,7 @@ SVC_Context CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted SVC_ContextSave -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -107,7 +111,7 @@ SVC_ContextSwitch STR R2,[R3] ; osRtxInfo.thread.run: curr = next SVC_ContextRestore -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers @@ -124,7 +128,7 @@ SVC_ContextRestore1 ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) LSLS R0,R0,#25 ; Check domain of interrupted thread BPL SVC_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -191,10 +195,11 @@ SysTick_Handler B Sys_Context + Sys_Context EXPORT Sys_Context IMPORT osRtxInfo -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) IMPORT TZ_LoadContext_S IMPORT TZ_StoreContext_S #endif @@ -204,9 +209,8 @@ Sys_Context CMP R1,R2 ; Check if thread switch is required BEQ Sys_ContextExit ; Branch when threads are the same - Sys_ContextSave -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context PUSH {R1,R2,R3,R7} ; Save registers @@ -242,7 +246,7 @@ Sys_ContextSwitch STR R2,[R3] ; osRtxInfo.run: curr = next Sys_ContextRestore -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context PUSH {R2,R3} ; Save registers @@ -259,7 +263,7 @@ Sys_ContextRestore1 ORRS R0,R1 MOV LR,R0 ; Set EXC_RETURN -#ifdef __DOMAIN_NS +#if (__DOMAIN_NS == 1) LSLS R0,R0,#25 ; Check domain of interrupted thread BPL Sys_ContextRestore2 ; Branch if non-secure LDR R0,[R2,#TCB_SP_OFS] ; Load SP @@ -284,5 +288,3 @@ Sys_ContextRestore2 Sys_ContextExit BX LR ; Exit from handler - - END diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_ns.S new file mode 100644 index 00000000000..7ee9d0465d8 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_ns.S @@ -0,0 +1,5 @@ + NAME irq_armv8mbl_ns.s +#define __DOMAIN_NS 1 + INCLUDE irq_armv8mbl_common.s + + END diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_IAR/irq_cm3.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_IAR/irq_cm3.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S index bfc3b33d410..0bffcb34689 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_M3/TOOLCHAIN_IAR/irq_cm3.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S @@ -27,7 +27,7 @@ NAME irq_cm3.s -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml.S new file mode 100644 index 00000000000..8a8bd8a0f18 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml.S @@ -0,0 +1,5 @@ + NAME irq_armv8mml.s +#define __DOMAIN_NS 0 + INCLUDE irq_armv8mml_common.s + END + diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S new file mode 100644 index 00000000000..5edbf07bcf6 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S @@ -0,0 +1,267 @@ +;/* +; * Copyright (c) 2016-2017 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; * +; * ----------------------------------------------------------------------------- +; * +; * Project: CMSIS-RTOS RTX +; * Title: ARMv8M Mainline Exception handlers +; * +; * ----------------------------------------------------------------------------- +; */ + + + +#ifndef __DOMAIN_NS +#define __DOMAIN_NS 0 +#endif + +#ifdef __ARMVFP__ +__FPU_USED EQU 1 +#else +__FPU_USED EQU 0 +#endif + +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset +TCB_SM_OFS EQU 48 ; TCB.stack_mem offset +TCB_SP_OFS EQU 56 ; TCB.SP offset +TCB_SF_OFS EQU 34 ; TCB.stack_frame offset +TCB_TZM_OFS EQU 64 ; TCB.tz_memory offset + + + PRESERVE8 + + + SECTION .rodata:DATA:NOROOT(2) + EXPORT irqRtxLib +irqRtxLib DCB 0 ; Non weak library reference + + + SECTION .text:CODE:NOROOT(2) + THUMB + + +SVC_Handler + EXPORT SVC_Handler + IMPORT osRtxUserSVC + IMPORT osRtxInfo +#if (__DOMAIN_NS == 1) + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S +#endif + + MRS R0,PSP ; Get PSP + LDR R1,[R0,#24] ; Load saved PC from stack + LDRB R1,[R1,#-2] ; Load SVC number + CMP R1,#0 + BNE SVC_User ; Branch if not SVC 0 + + PUSH {R0,LR} ; Save PSP and EXC_RETURN + LDM R0,{R0-R3,R12} ; Load function parameters and address from stack + BLX R12 ; Call service function + POP {R12,LR} ; Restore PSP and EXC_RETURN + STM R12,{R0-R1} ; Store function return values + +SVC_Context + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same + +#if (__FPU_USED == 1) + CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted + TST LR,#0x10 ; Check if extended stack frame + BNE SVC_ContextSwitch + LDR R1,=0xE000EF34 ; FPCCR Address + LDR R0,[R1] ; Load FPCCR + BIC R0,#1 ; Clear LSPACT (Lazy state) + STR R0,[R1] ; Store FPCCR + B SVC_ContextSwitch +#else + CBZ R1,SVC_ContextSwitch ; Branch if running thread is deleted +#endif + +SVC_ContextSave +#if (__DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN +#endif + +SVC_ContextSave1 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 +#if (__FPU_USED == 1) + TST LR,#0x10 ; Check if extended stack frame + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 +#endif + +SVC_ContextSave2 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +SVC_ContextSwitch + STR R2,[R3] ; osRtxInfo.thread.run: curr = next + +SVC_ContextRestore +#if (__DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,SVC_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers +#endif + +SVC_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + +#if (__DOMAIN_NS == 1) + TST LR,#0x40 ; Check domain of interrupted thread + BNE SVC_ContextRestore2 ; Branch if secure +#endif + +#if (__FPU_USED == 1) + TST LR,#0x10 ; Check if extended stack frame + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 +#endif + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +SVC_ContextRestore2 + MSR PSP,R0 ; Set PSP + +SVC_Exit + BX LR ; Exit from handler + +SVC_User + PUSH {R4,LR} ; Save registers + LDR R2,=osRtxUserSVC ; Load address of SVC table + LDR R3,[R2] ; Load SVC maximum number + CMP R1,R3 ; Check SVC number range + BHI SVC_Done ; Branch if out of range + + LDR R4,[R2,R1,LSL #2] ; Load address of SVC function + + LDM R0,{R0-R3} ; Load function parameters from stack + BLX R4 ; Call service function + MRS R4,PSP ; Get PSP + STR R0,[R4] ; Store function return value + +SVC_Done + POP {R4,PC} ; Return from handler + + +PendSV_Handler + EXPORT PendSV_Handler + IMPORT osRtxPendSV_Handler + + PUSH {R4,LR} ; Save EXC_RETURN + BL osRtxPendSV_Handler ; Call osRtxPendSV_Handler + POP {R4,LR} ; Restore EXC_RETURN + B Sys_Context + + +SysTick_Handler + EXPORT SysTick_Handler + IMPORT osRtxTick_Handler + + PUSH {R4,LR} ; Save EXC_RETURN + BL osRtxTick_Handler ; Call osRtxTick_Handler + POP {R4,LR} ; Restore EXC_RETURN + B Sys_Context + + + +Sys_Context + EXPORT Sys_Context + IMPORT osRtxInfo +#if (__DOMAIN_NS == 1) + IMPORT TZ_LoadContext_S + IMPORT TZ_StoreContext_S +#endif + + LDR R3,=osRtxInfo+I_T_RUN_OFS; Load address of osRtxInfo.run + LDM R3,{R1,R2} ; Load osRtxInfo.thread.run: curr & next + CMP R1,R2 ; Check if thread switch is required + IT EQ + BXEQ LR ; Exit when threads are the same + +Sys_ContextSave +#if (__DOMAIN_NS == 1) + LDR R0,[R1,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextSave1 ; Branch if there is no secure context + PUSH {R1,R2,R3,LR} ; Save registers and EXC_RETURN + BL TZ_StoreContext_S ; Store secure context + POP {R1,R2,R3,LR} ; Restore registers and EXC_RETURN + TST LR,#0x40 ; Check domain of interrupted thread + IT NE + MRSNE R0,PSP ; Get PSP + BNE Sys_ContextSave2 ; Branch if secure +#endif + +Sys_ContextSave1 + MRS R0,PSP ; Get PSP + STMDB R0!,{R4-R11} ; Save R4..R11 +#if (__FPU_USED == 1) + TST LR,#0x10 ; Check if extended stack frame + VSTMDBEQ R0!,{S16-S31} ; Save VFP S16.S31 +#endif + +Sys_ContextSave2 + STR R0,[R1,#TCB_SP_OFS] ; Store SP + STRB LR,[R1,#TCB_SF_OFS] ; Store stack frame information + +Sys_ContextSwitch + STR R2,[R3] ; osRtxInfo.run: curr = next + +Sys_ContextRestore +#if (__DOMAIN_NS == 1) + LDR R0,[R2,#TCB_TZM_OFS] ; Load TrustZone memory identifier + CBZ R0,Sys_ContextRestore1 ; Branch if there is no secure context + PUSH {R2,R3} ; Save registers + BL TZ_LoadContext_S ; Load secure context + POP {R2,R3} ; Restore registers +#endif + +Sys_ContextRestore1 + LDR R0,[R2,#TCB_SM_OFS] ; Load stack memory base + LDRB R1,[R2,#TCB_SF_OFS] ; Load stack frame information + MSR PSPLIM,R0 ; Set PSPLIM + LDR R0,[R2,#TCB_SP_OFS] ; Load SP + ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN + +#if (__DOMAIN_NS == 1) + TST LR,#0x40 ; Check domain of interrupted thread + BNE Sys_ContextRestore2 ; Branch if secure +#endif + +#if (__FPU_USED == 1) + TST LR,#0x10 ; Check if extended stack frame + VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 +#endif + LDMIA R0!,{R4-R11} ; Restore R4..R11 + +Sys_ContextRestore2 + MSR PSP,R0 ; Set PSP + +Sys_ContextExit + BX LR ; Exit from handler diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_ns.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_ns.S new file mode 100644 index 00000000000..827abb49208 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_ns.S @@ -0,0 +1,5 @@ + NAME irq_armv8mml_ns.s +#define __DOMAIN_NS 1 + INCLUDE irq_armv8mml_common.s + END + diff --git a/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.S rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S index e194af196c1..d44f4017c4d 100644 --- a/rtos/TARGET_CORTEX/rtx5/TARGET_RTOS_M4_M7/TOOLCHAIN_IAR/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -27,7 +27,7 @@ NAME irq_cm4f.s -I_T_RUN_OFS EQU 28 ; osRtxInfo.thread.run offset +I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SP_OFS EQU 56 ; TCB.SP offset TCB_SF_OFS EQU 34 ; TCB.stack_frame offset diff --git a/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.c similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.c diff --git a/rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.h similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rt_OsEventObserver.h rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rt_OsEventObserver.h diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h new file mode 100644 index 00000000000..8b95bc3c2fe --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_c.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_C_H_ +#define RTX_CORE_C_H_ + +#include + +#ifndef __ARM_ARCH_6M__ +#define __ARM_ARCH_6M__ 0U +#endif +#ifndef __ARM_ARCH_7A__ +#define __ARM_ARCH_7A__ 0U +#endif +#ifndef __ARM_ARCH_7M__ +#define __ARM_ARCH_7M__ 0U +#endif +#ifndef __ARM_ARCH_7EM__ +#define __ARM_ARCH_7EM__ 0U +#endif +#ifndef __ARM_ARCH_8M_BASE__ +#define __ARM_ARCH_8M_BASE__ 0U +#endif +#ifndef __ARM_ARCH_8M_MAIN__ +#define __ARM_ARCH_8M_MAIN__ 0U +#endif + +#if ((__ARM_ARCH_6M__ + \ + __ARM_ARCH_7A__ + \ + __ARM_ARCH_7M__ + \ + __ARM_ARCH_7EM__ + \ + __ARM_ARCH_8M_BASE__ + \ + __ARM_ARCH_8M_MAIN__) != 1U) +#error "Unknown ARM Architecture!" +#endif + +#if (__ARM_ARCH_7A__ != 0U) +#include "rtx_core_ca.h" +#else +#include "rtx_core_cm.h" +#endif + +#endif // RTX_CORE_C_H_ diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h new file mode 100644 index 00000000000..c3ee341889b --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_ca.h @@ -0,0 +1,1099 @@ +/* + * Copyright (c) 2013-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * Project: CMSIS-RTOS RTX + * Title: Cortex-A Core definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CORE_CA_H_ +#define RTX_CORE_CA_H_ + +#include + +#define __DOMAIN_NS 0U +#define __EXCLUSIVE_ACCESS 1U + +/* CPSR bit definitions */ +#define CPSR_T_BIT 0x20U +#define CPSR_I_BIT 0x80U +#define CPSR_F_BIT 0x40U + +/* CPSR mode bitmasks */ +#define CPSR_MODE_USER 0x10U +#define CPSR_MODE_SYSTEM 0x1FU + +/* Determine privilege level */ +#define IS_PRIVILEGED() (__get_mode() != CPSR_MODE_USER) +#define IS_IRQ_MODE() ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM)) +#define IS_IRQ_MASKED() (0U) + +#define xPSR_INIT(privileged, thumb) \ + ((privileged) != 0U) ? (CPSR_MODE_SYSTEM | (((thumb) != 0U) ? CPSR_T_BIT : 0U)) : \ + (CPSR_MODE_USER | (((thumb) != 0U) ? CPSR_T_BIT : 0U)) + +#define STACK_FRAME_INIT 0x00U + +// Stack Frame: +// - VFP-D32: D16-31, D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR +// - VFP-D16: D0-D15, FPSCR, Reserved, R4-R11, R0-R3, R12, LR, PC, CPSR +// - Basic: R4-R11, R0-R3, R12, LR, PC, CPSR +#define STACK_OFFSET_R0(stack_frame) \ + ((((stack_frame) & 0x04U) != 0U) ? ((32U*8U) + (2U*4U) + (8U*4U)) : \ + (((stack_frame) & 0x02U) != 0U) ? ((16U*8U) + (2U*4U) + (8U*4U)) : \ + (8U*4U)) + +#define OS_TICK_HANDLER osRtxTick_Handler + +/* Emulate M profile get_PSP: SP_usr - (8*4) */ +#if defined(__CC_ARM) +static __asm uint32_t __get_PSP (void) { + arm + sub sp, sp, #4 + stm sp, {sp}^ + pop {r0} + sub r0, r0, #32 + bx lr +} +#else +__STATIC_INLINE uint32_t __get_PSP (void) { + register uint32_t ret; + + __asm volatile ( + ".syntax unified\n\t" + ".arm\n\t" + "sub sp,sp,#4\n\t" + "stm sp,{sp}^\n\t" + "pop {%[ret]}\n\t" + "sub %[ret],%[ret],#32\n\t" + : [ret] "=&l" (ret) + : + : "memory" + ); + + return ret; +} +#endif + +__STATIC_INLINE void __set_CONTROL(uint32_t control) { +} + + +// ==== Service Calls definitions ==== + +#if defined(__CC_ARM) + +#define __SVC_INDIRECT(n) __svc_indirect(n) + +#define SVC0_0N(f,t) \ +__SVC_INDIRECT(0) t svc##f (t(*)()); \ + t svcRtx##f (void); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + svc##f(svcRtx##f); \ +} + +#define SVC0_0(f,t) \ +__SVC_INDIRECT(0) t svc##f (t(*)()); \ + t svcRtx##f (void); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + return svc##f(svcRtx##f); \ +} + +#define SVC0_1N(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ + t svcRtx##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + svc##f(svcRtx##f,a1); \ +} + +#define SVC0_1(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ + t svcRtx##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + return svc##f(svcRtx##f,a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2),t1,t2); \ + t svcRtx##f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + return svc##f(svcRtx##f,a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3),t1,t2,t3); \ + t svcRtx##f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + return svc##f(svcRtx##f,a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__SVC_INDIRECT(0) t svc##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ + t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + return svc##f(svcRtx##f,a1,a2,a3,a4); \ +} + +#define SVC0_0M SVC0_0 +#define SVC0_1M SVC0_1 +#define SVC0_2M SVC0_2 +#define SVC0_3M SVC0_3 +#define SVC0_4M SVC0_4 + +#elif defined(__ICCARM__) + +#define SVC_Setup(f) \ + __asm( \ + "mov r12,%0\n" \ + :: "r"(&f): "r12" \ + ); + +#define STRINGIFY(a) #a +#define __SVC_INDIRECT(n) _Pragma(STRINGIFY(swi_number = n)) __swi + +#define SVC0_0N(f,t) \ +__SVC_INDIRECT(0) t svc##f (); \ + t svcRtx##f (void); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_Setup(svcRtx##f); \ + svc##f(); \ +} + +#define SVC0_0(f,t) \ +__SVC_INDIRECT(0) t svc##f (); \ + t svcRtx##f (void); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_Setup(svcRtx##f); \ + return svc##f(); \ +} + +#define SVC0_1N(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t1 a1); \ + t svcRtx##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_Setup(svcRtx##f); \ + svc##f(a1); \ +} + +#define SVC0_1(f,t,t1) \ +__SVC_INDIRECT(0) t svc##f (t1 a1); \ + t svcRtx##f (t1 a1); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_Setup(svcRtx##f); \ + return svc##f(a1); \ +} + +#define SVC0_2(f,t,t1,t2) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2); \ + t svcRtx##f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_Setup(svcRtx##f); \ + return svc##f(a1,a2); \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3); \ + t svcRtx##f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_Setup(svcRtx##f); \ + return svc##f(a1,a2,a3); \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__SVC_INDIRECT(0) t svc##f (t1 a1, t2 a2, t3 a3, t4 a4); \ + t svcRtx##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_Setup(svcRtx##f); \ + return svc##f(a1,a2,a3,a4); \ +} + +#define SVC0_0M SVC0_0 +#define SVC0_1M SVC0_1 +#define SVC0_2M SVC0_2 +#define SVC0_3M SVC0_3 +#define SVC0_4M SVC0_4 + +#else // !(defined(__CC_ARM) || defined(__ICCARM__)) + +#define SVC_RegF "r12" + +#define SVC_ArgN(n) \ +register uint32_t __r##n __ASM("r"#n) + +#define SVC_ArgR(n,a) \ +register uint32_t __r##n __ASM("r"#n) = (uint32_t)a + +#define SVC_ArgF(f) \ +register uint32_t __rf __ASM(SVC_RegF) = (uint32_t)f + +#define SVC_In0 "r"(__rf) +#define SVC_In1 "r"(__rf),"r"(__r0) +#define SVC_In2 "r"(__rf),"r"(__r0),"r"(__r1) +#define SVC_In3 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2) +#define SVC_In4 "r"(__rf),"r"(__r0),"r"(__r1),"r"(__r2),"r"(__r3) + +#define SVC_Out0 +#define SVC_Out1 "=r"(__r0) +#define SVC_Out2 "=r"(__r0),"=r"(__r1) + +#define SVC_CL0 +#define SVC_CL1 "r1" +#define SVC_CL2 "r0","r1" + +#define SVC_Call0(in, out, cl) \ + __ASM volatile ("svc 0" : out : in : cl) + +#define SVC0_0N(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out0, SVC_CL2); \ +} + +#define SVC0_0(f,t) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (void) { \ + SVC_ArgN(0); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In0, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_1N(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out0, SVC_CL1); \ +} + +#define SVC0_1(f,t,t1) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1) { \ + SVC_ArgR(0,a1); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In1, SVC_Out1, SVC_CL1); \ + return (t) __r0; \ +} + +#define SVC0_2(f,t,t1,t2) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In2, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_3(f,t,t1,t2,t3) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In3, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_4(f,t,t1,t2,t3,t4) \ +__attribute__((always_inline)) \ +__STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_ArgR(0,a1); \ + SVC_ArgR(1,a2); \ + SVC_ArgR(2,a3); \ + SVC_ArgR(3,a4); \ + SVC_ArgF(svcRtx##f); \ + SVC_Call0(SVC_In4, SVC_Out1, SVC_CL0); \ + return (t) __r0; \ +} + +#define SVC0_0M SVC0_0 +#define SVC0_1M SVC0_1 +#define SVC0_2M SVC0_2 +#define SVC0_3M SVC0_3 +#define SVC0_4M SVC0_4 + +#endif + + +// ==== Core Peripherals functions ==== + +extern uint8_t IRQ_PendSV; + +/// Initialize SVC and PendSV System Service Calls (not needed on Cortex-A) +__STATIC_INLINE void SVC_Initialize (void) { +} + +/// Get Pending SV (Service Call) Flag +/// \return Pending SV Flag +__STATIC_INLINE uint8_t GetPendSV (void) { + return (IRQ_PendSV); +} + +/// Clear Pending SV (Service Call) Flag +__STATIC_INLINE void ClrPendSV (void) { + IRQ_PendSV = 0U; +} + +/// Set Pending SV (Service Call) Flag +__STATIC_INLINE void SetPendSV (void) { + IRQ_PendSV = 1U; +} + + +// ==== Exclusive Access Operation ==== + +#if (__EXCLUSIVE_ACCESS == 1U) + +/// Atomic Access Operation: Write (8-bit) +/// \param[in] mem Memory address +/// \param[in] val Value to write +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { + mov r2,r0 +1 + ldrexb r0,[r2] + strexb r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint8_t atomic_wr8 (uint8_t *mem, uint8_t val) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint8_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexb %[ret],[%[mem]]\n\t" + "strexb %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n\t" + : [ret] "=&l" (ret), + [res] "=&l" (res) + : [mem] "l" (mem), + [val] "l" (val) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Set bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return New value +#if defined(__CC_ARM) +static __asm uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { + mov r2,r0 +1 + ldrex r0,[r2] + orr r0,r0,r1 + strex r3,r0,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_set32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[val],[%[mem]]\n\t" + "orr %[ret],%[val],%[bits]\n\t" + "strex %[res],%[ret],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Clear bits (32-bit) +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + bic r4,r0,r1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_clr32 (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "bic %[val],%[ret],%[bits]\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if all specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + and r4,r0,r1 + cmp r4,r1 + beq %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_all (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "and %[val],%[ret],%[bits]\n\t" + "cmp %[val],%[bits]\n\t" + "beq 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" + "bic %[val],%[ret],%[bits]\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Check if any specified bits (32-bit) are active and clear them +/// \param[in] mem Memory address +/// \param[in] bits Bit mask +/// \return Active bits before clearing or 0 if not active +#if defined(__CC_ARM) +static __asm uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + tst r0,r1 + bne %F2 + clrex + movs r0,#0 + pop {r4,pc} +2 + bic r4,r0,r1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_chk32_any (uint32_t *mem, uint32_t bits) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "tst %[ret],%[bits]\n\t" + "bne 2f\n\t" + "clrex\n\t" + "movs %[ret],#0\n\t" + "b 3f\n" + "2:\n\t" + "bic %[val],%[ret],%[bits]\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [bits] "l" (bits) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (32-bit) +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_inc32 (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + adds r1,r0,#1 + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_inc32 (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// atomic Access Operation: Increment (32-bit) if Less Than +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) { + push {r4,lr} + mov r2,r0 +1 + ldrex r0,[r2] + cmp r1,r0 + bhi %F2 + clrex + pop {r4,pc} +2 + adds r4,r0,#1 + strex r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint32_t atomic_inc32_lt (uint32_t *mem, uint32_t max) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "cmp %[max],%[ret]\n\t" + "bhi 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "adds %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [max] "l" (max) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) if Less Than +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + cmp r1,r0 + bhi %F2 + clrex + pop {r4,pc} +2 + adds r4,r0,#1 + strexh r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lt (uint16_t *mem, uint16_t max) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cmp %[max],%[ret]\n\t" + "bhi 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "adds %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [max] "l" (max) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Increment (16-bit) and clear on Limit +/// \param[in] mem Memory address +/// \param[in] max Maximum value +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { + push {r4,lr} + mov r2,r0 +1 + ldrexh r0,[r2] + adds r4,r0,#1 + cmp r1,r4 + bhi %F2 + movs r4,#0 +2 + strexh r3,r4,[r2] + cmp r3,#0 + bne %B1 + pop {r4,pc} +} +#else +__STATIC_INLINE uint16_t atomic_inc16_lim (uint16_t *mem, uint16_t lim) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "adds %[val],%[ret],#1\n\t" + "cmp %[lim],%[val]\n\t" + "bhi 2f\n\t" + "movs %[val],#0\n" + "2:\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem), + [lim] "l" (lim) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (32-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint32_t atomic_dec32_nz (uint32_t *mem) { + mov r2,r0 +1 + ldrex r0,[r2] + cmp r0,#0 + bne %F2 + clrex + bx lr +2 + subs r1,r0,#1 + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint32_t atomic_dec32_nz (uint32_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint32_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[mem]]\n\t" + "cmp %[ret],#0\n\t" + "bne 2f\n" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strex %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Decrement (16-bit) if Not Zero +/// \param[in] mem Memory address +/// \return Previous value +#if defined(__CC_ARM) +static __asm uint16_t atomic_dec16_nz (uint16_t *mem) { + mov r2,r0 +1 + ldrexh r0,[r2] + cmp r0,#0 + bne %F2 + clrex + bx lr +2 + subs r1,r0,#1 + strexh r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE uint16_t atomic_dec16_nz (uint16_t *mem) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register uint16_t ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrexh %[ret],[%[mem]]\n\t" + "cmp %[ret],#0\n\t" + "bne 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "subs %[val],%[ret],#1\n\t" + "strexh %[res],%[val],[%[mem]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [mem] "l" (mem) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Get +/// \param[in] root Root address +/// \return Link +#if defined(__CC_ARM) +static __asm void *atomic_link_get (void **root) { + mov r2,r0 +1 + ldrex r0,[r2] + cmp r0,#0 + bne %F2 + clrex + bx lr +2 + ldr r1,[r0] + strex r3,r1,[r2] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE void *atomic_link_get (void **root) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + register void *ret; + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldrex %[ret],[%[root]]\n\t" + "cmp %[ret],#0\n\t" + "bne 2f\n\t" + "clrex\n\t" + "b 3f\n" + "2:\n\t" + "ldr %[val],[%[ret]]\n\t" + "strex %[res],%[val],[%[root]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + "3:" + : [ret] "=&l" (ret), + [val] "=&l" (val), + [res] "=&l" (res) + : [root] "l" (root) + : "cc", "memory" + ); + + return ret; +} +#endif + +/// Atomic Access Operation: Link Put +/// \param[in] root Root address +/// \param[in] lnk Link +#if defined(__CC_ARM) +static __asm void atomic_link_put (void **root, void *link) { +1 + ldr r2,[r0] + str r2,[r1] + dmb + ldrex r2,[r0] + ldr r3,[r1] + cmp r3,r2 + bne %B1 + strex r3,r1,[r0] + cmp r3,#0 + bne %B1 + bx lr +} +#else +__STATIC_INLINE void atomic_link_put (void **root, void *link) { +#ifdef __ICCARM__ +#pragma diag_suppress=Pe550 +#endif + register uint32_t val1, val2, res; +#ifdef __ICCARM__ +#pragma diag_default=Pe550 +#endif + + __ASM volatile ( +#ifndef __ICCARM__ + ".syntax unified\n\t" +#endif + "1:\n\t" + "ldr %[val1],[%[root]]\n\t" + "str %[val1],[%[link]]\n\t" + "dmb\n\t" + "ldrex %[val1],[%[root]]\n\t" + "ldr %[val2],[%[link]]\n\t" + "cmp %[val2],%[val1]\n\t" + "bne 1b\n\t" + "strex %[res],%[link],[%[root]]\n\t" + "cmp %[res],#0\n\t" + "bne 1b\n" + : [val1] "=&l" (val1), + [val2] "=&l" (val2), + [res] "=&l" (res) + : [root] "l" (root), + [link] "l" (link) + : "cc", "memory" + ); +} +#endif + +#endif // (__EXCLUSIVE_ACCESS == 1U) + + +#endif // RTX_CORE_CA_H_ diff --git a/rtos/TARGET_CORTEX/rtx5/core_cm.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h similarity index 90% rename from rtos/TARGET_CORTEX/rtx5/core_cm.h rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h index 1590bd6c65a..fafe0981ed8 100644 --- a/rtos/TARGET_CORTEX/rtx5/core_cm.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_core_cm.h @@ -1,5 +1,3 @@ -/** \addtogroup rtos */ -/** @{*/ /* * Copyright (c) 2013-2017 ARM Limited. All rights reserved. * @@ -25,37 +23,10 @@ * ----------------------------------------------------------------------------- */ -#ifndef CORE_CM_H_ -#define CORE_CM_H_ +#ifndef RTX_CORE_CM_H_ +#define RTX_CORE_CM_H_ -#include -#include "cmsis.h" -#include "cmsis_compiler.h" -#include "arm_math.h" - -#ifndef __ARM_ARCH_6M__ -#define __ARM_ARCH_6M__ 0U -#endif -#ifndef __ARM_ARCH_7M__ -#define __ARM_ARCH_7M__ 0U -#endif -#ifndef __ARM_ARCH_7EM__ -#define __ARM_ARCH_7EM__ 0U -#endif -#ifndef __ARM_ARCH_8M_BASE__ -#define __ARM_ARCH_8M_BASE__ 0U -#endif -#ifndef __ARM_ARCH_8M_MAIN__ -#define __ARM_ARCH_8M_MAIN__ 0U -#endif - -#if ((__ARM_ARCH_6M__ + \ - __ARM_ARCH_7M__ + \ - __ARM_ARCH_7EM__ + \ - __ARM_ARCH_8M_BASE__ + \ - __ARM_ARCH_8M_MAIN__) != 1U) -#error "Unknown ARM Architecture!" -#endif +#include #ifdef RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS #define __DOMAIN_NS 1U @@ -81,7 +52,6 @@ #endif #endif - #define IS_PRIVILEGED() ((__get_CONTROL() & 1U) == 0U) #define IS_IRQ_MODE() (__get_IPSR() != 0U) @@ -94,7 +64,7 @@ #define IS_IRQ_MASKED() (__get_PRIMASK() != 0U) #endif -#define XPSR_INITIAL_VALUE 0x01000000U +#define xPSR_INIT(...) 0x01000000U #if (__DOMAIN_NS == 1U) #define STACK_FRAME_INIT 0xBCU @@ -102,7 +72,18 @@ #define STACK_FRAME_INIT 0xFDU #endif -#define IS_EXTENDED_STACK_FRAME(n) (((n) & 0x10U) == 0U) +// Stack Frame: +// - Extended: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR +// - Basic: R4-R11, R0-R3, R12, LR, PC, xPSR +#if (__FPU_USED == 1U) +#define STACK_OFFSET_R0(stack_frame) \ + ((((stack_frame) & 0x10U) == 0U) ? ((16U+8U)*4U) : \ + (8U *4U)) +#else +#define STACK_OFFSET_R0(stack_frame) (8U *4U) +#endif + +#define OS_TICK_HANDLER SysTick_Handler // ==== Service Calls definitions ==== @@ -157,8 +138,6 @@ __STATIC_INLINE t __svc##f (void) { \ return svc##f(svcRtx##f); \ } -#define SVC0_0D SVC0_0 - #define SVC0_1N(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t(*)(t1),t1); \ t svcRtx##f (t1 a1); \ @@ -299,8 +278,6 @@ __STATIC_INLINE t __svc##f (void) { \ return svc##f(); \ } -#define SVC0_0D SVC0_0 - #define SVC0_1N(f,t,t1) \ __SVC_INDIRECT(0) t svc##f (t1 a1); \ t svcRtx##f (t1 a1); \ @@ -504,16 +481,6 @@ __STATIC_INLINE t __svc##f (void) { \ return (t) __r0; \ } -#define SVC0_0D(f,t) \ -__attribute__((always_inline)) \ -__STATIC_INLINE t __svc##f (void) { \ - SVC_ArgN(0); \ - SVC_ArgN(1); \ - SVC_ArgF(svcRtx##f); \ - SVC_Call0(SVC_In0, SVC_Out2, SVC_CL0); \ - return (((t) __r0) | (((t) __r1) << 32)); \ -} - #define SVC0_1N(f,t,t1) \ __attribute__((always_inline)) \ __STATIC_INLINE t __svc##f (t1 a1) { \ @@ -611,9 +578,6 @@ __STATIC_INLINE t __svc##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ // ==== Core Peripherals functions ==== -extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) - - /// Initialize SVC and PendSV System Service Calls __STATIC_INLINE void SVC_Initialize (void) { #if ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U))) @@ -627,8 +591,11 @@ __STATIC_INLINE void SVC_Initialize (void) { } SCB->SHPR[7] = (uint8_t)(0xFEU << n); #elif (__ARM_ARCH_8M_BASE__ == 1U) + uint32_t n; + SCB->SHPR[1] |= 0x00FF0000U; - SCB->SHPR[0] |= (SCB->SHPR[1] << (8+1)) & 0xFC000000U; + n = SCB->SHPR[1]; + SCB->SHPR[0] |= (n << (8+1)) & 0xFC000000U; #elif ((__ARM_ARCH_7M__ == 1U) || \ (__ARM_ARCH_7EM__ == 1U)) uint32_t p, n; @@ -640,110 +607,25 @@ __STATIC_INLINE void SVC_Initialize (void) { n = p + 1U; } -/* Only change the SVCall priority if uVisor is not present. */ -#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) + /* Only change the SVCall priority if uVisor is not present. */ + #if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) SCB->SHP[7] = (uint8_t)(0xFEU << n); -#endif + #endif #elif (__ARM_ARCH_6M__ == 1U) - SCB->SHP[1] |= 0x00FF0000U; - SCB->SHP[0] |= (SCB->SHP[1] << (8+1)) & 0xFC000000U; -#endif -} + uint32_t n; -/// Setup SysTick Timer -/// \param[in] period Timer Load value -__STATIC_INLINE void SysTick_Setup (uint32_t period) { - SysTick->LOAD = period - 1U; - SysTick->VAL = 0U; -#if ((__ARM_ARCH_8M_MAIN__ == 1U) || (defined(__CORTEX_M) && (__CORTEX_M == 7U))) - SCB->SHPR[11] = 0xFFU; -#elif (__ARM_ARCH_8M_BASE__ == 1U) - SCB->SHPR[1] |= 0xFF000000U; -#elif ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U)) - SCB->SHP[11] = 0xFFU; -#elif (__ARM_ARCH_6M__ == 1U) - SCB->SHP[1] |= 0xFF000000U; -#endif -} - -/// Get SysTick Period -/// \return SysTick Period -__STATIC_INLINE uint32_t SysTick_GetPeriod (void) { - return (SysTick->LOAD + 1U); -} - -/// Get SysTick Value -/// \return SysTick Value -__STATIC_INLINE uint32_t SysTick_GetVal (void) { - uint32_t load = SysTick->LOAD; - return (load - SysTick->VAL); -} - -/// Get SysTick Overflow (Auto Clear) -/// \return SysTick Overflow flag -__STATIC_INLINE uint32_t SysTick_GetOvf (void) { - return ((SysTick->CTRL >> 16) & 1U); -} - -/// Enable SysTick Timer -__STATIC_INLINE void SysTick_Enable (void) { - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_CLKSOURCE_Msk; -} - -/// Disable SysTick Timer -__STATIC_INLINE void SysTick_Disable (void) { - SysTick->CTRL = 0U; -} - -/// Setup External Tick Timer Interrupt -/// \param[in] irqn Interrupt number -__STATIC_INLINE void ExtTick_SetupIRQ (int32_t irqn) { -#if (__ARM_ARCH_8M_MAIN__ == 1U) - NVIC->IPR[irqn] = 0xFFU; -#elif (__ARM_ARCH_8M_BASE__ == 1U) - NVIC->IPR[irqn >> 2] = (NVIC->IPR[irqn >> 2] & ~(0xFFU << ((irqn & 3) << 3))) | - (0xFFU << ((irqn & 3) << 3)); -#elif ((__ARM_ARCH_7M__ == 1U) || \ - (__ARM_ARCH_7EM__ == 1U)) - NVIC->IP[irqn] = 0xFFU; -#elif (__ARM_ARCH_6M__ == 1U) - NVIC->IP[irqn >> 2] = (NVIC->IP[irqn >> 2] & ~(0xFFU << ((irqn & 3) << 3))) | - (0xFFU << ((irqn & 3) << 3)); + SCB->SHP[1] |= 0x00FF0000U; + n = SCB->SHP[1]; + SCB->SHP[0] |= (n << (8+1)) & 0xFC000000U; #endif } -/// Enable External Tick Timer Interrupt -/// \param[in] irqn Interrupt number -__STATIC_INLINE void ExtTick_EnableIRQ (int32_t irqn) { - NVIC->ISER[irqn >> 5] = 1U << (irqn & 0x1F); -} - -/// Disable External Tick Timer Interrupt -/// \param[in] irqn Interrupt number -__STATIC_INLINE void ExtTick_DisableIRQ (int32_t irqn) { - NVIC->ICER[irqn >> 5] = 1U << (irqn & 0x1F); -} - -/// Get Pending SV (Service Call) and ST (SysTick) Flags -/// \return Pending SV&ST Flags -__STATIC_INLINE uint8_t GetPendSV_ST (void) { - return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk | SCB_ICSR_PENDSTSET_Msk)) >> 24)); -} - /// Get Pending SV (Service Call) Flag /// \return Pending SV Flag __STATIC_INLINE uint8_t GetPendSV (void) { return ((uint8_t)((SCB->ICSR & (SCB_ICSR_PENDSVSET_Msk)) >> 24)); } -/// Clear Pending SV (Service Call) and ST (SysTick) Flags -__STATIC_INLINE void ClrPendSV_ST (void) { - SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk | SCB_ICSR_PENDSTCLR_Msk; -} - /// Clear Pending SV (Service Call) Flag __STATIC_INLINE void ClrPendSV (void) { SCB->ICSR = SCB_ICSR_PENDSVCLR_Msk; @@ -754,12 +636,6 @@ __STATIC_INLINE void SetPendSV (void) { SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; } -/// Set Pending Flags -/// \param[in] flags Flags to set -__STATIC_INLINE void SetPendFlags (uint8_t flags) { - SCB->ICSR = ((uint32_t)flags << 24); -} - // ==== Exclusive Access Operation ==== @@ -1529,6 +1405,4 @@ __STATIC_INLINE void atomic_link_put (void **root, void *link) { #endif // (__EXCLUSIVE_ACCESS == 1U) -#endif // CORE_CM_H_ - -/** @}*/ +#endif // RTX_CORE_CM_H_ diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_delay.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c similarity index 83% rename from rtos/TARGET_CORTEX/rtx5/rtx_delay.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c index a7e71b7777b..17e90c28587 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_delay.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_delay.c @@ -30,7 +30,7 @@ // Service Calls definitions SVC0_1(Delay, osStatus_t, uint32_t) -SVC0_2(DelayUntil, osStatus_t, uint32_t, uint32_t) +SVC0_1(DelayUntil, osStatus_t, uint32_t) /// Wait for Timeout (Time Delay). /// \note API identical to osDelay @@ -47,11 +47,10 @@ osStatus_t svcRtxDelay (uint32_t ticks) { /// Wait until specified time. /// \note API identical to osDelayUntil -osStatus_t svcRtxDelayUntil (uint32_t ticks_l, uint32_t ticks_h) { - uint64_t ticks = ((uint64_t)ticks_l) | ((uint64_t)ticks_h << 32); +osStatus_t svcRtxDelayUntil (uint32_t ticks) { ticks -= osRtxInfo.kernel.tick; - if (ticks >= 0xFFFFFFFFU) { + if (ticks == 0xFFFFFFFFU) { EvrRtxThreadError(NULL, osErrorParameter); return osErrorParameter; } @@ -59,7 +58,7 @@ osStatus_t svcRtxDelayUntil (uint32_t ticks_l, uint32_t ticks_h) { return osOK; } - osRtxThreadWaitEnter(osRtxThreadWaitingDelay, (uint32_t)ticks); + osRtxThreadWaitEnter(osRtxThreadWaitingDelay, ticks); return osOK; } @@ -78,11 +77,11 @@ osStatus_t osDelay (uint32_t ticks) { } /// Wait until specified time. -osStatus_t osDelayUntil (uint64_t ticks) { +osStatus_t osDelayUntil (uint32_t ticks) { EvrRtxThreadDelayUntil(ticks); if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { EvrRtxThreadError(NULL, osErrorISR); return osErrorISR; } - return __svcDelayUntil((uint32_t)ticks, (uint32_t)(ticks >> 32)); + return __svcDelayUntil(ticks); } diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_evflags.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rtx_evflags.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evflags.c diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_evr.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/rtx_evr.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c index f368df828a8..2507d303806 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_evr.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_evr.c @@ -501,9 +501,9 @@ __WEAK void EvrRtxKernelResumed (void) { #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_KERNEL != 0) && !defined(EVR_RTX_KERNEL_GET_TICK_COUNT_DISABLE)) -__WEAK void EvrRtxKernelGetTickCount (uint64_t count) { +__WEAK void EvrRtxKernelGetTickCount (uint32_t count) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxKernelGetTickCount, (uint32_t)count, (uint32_t)(count>>32)); + EventRecord2(EvtRtxKernelGetTickCount, count, 0U); #else (void)count; #endif @@ -958,9 +958,9 @@ __WEAK void EvrRtxThreadDelay (uint32_t ticks) { #endif #if (!defined(EVR_RTX_DISABLE) && (OS_EVR_THREAD != 0) && !defined(EVR_RTX_THREAD_DELAY_UNTIL_DISABLE)) -__WEAK void EvrRtxThreadDelayUntil (uint64_t ticks) { +__WEAK void EvrRtxThreadDelayUntil (uint32_t ticks) { #if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtRtxThreadDelayUntil, (uint32_t)ticks, (uint32_t)(ticks >> 32)); + EventRecord2(EvtRtxThreadDelayUntil, ticks, 0U); #else (void)ticks; #endif diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c similarity index 95% rename from rtos/TARGET_CORTEX/rtx5/rtx_kernel.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c index 1f9a91f7d14..8284034f2f1 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_kernel.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_kernel.c @@ -37,18 +37,14 @@ osRtxInfo_t osRtxInfo __attribute__((section(".data.os"))) = /// Block Kernel (disable: thread switching, time tick, post ISR processing). static void KernelBlock (void) { - if (osRtxInfo.tick_irqn >= 0) { - ExtTick_DisableIRQ(osRtxInfo.tick_irqn); - } - osRtxSysTimerDisable(); + OS_Tick_Disable(); + osRtxInfo.kernel.blocked = 1U; __DSB(); - if (osRtxInfo.tick_irqn < 0) { - osRtxInfo.kernel.pendISR = GetPendSV_ST(); - ClrPendSV_ST(); - } else { - osRtxInfo.kernel.pendISR = GetPendSV(); + + if (GetPendSV() != 0U) { ClrPendSV(); + osRtxInfo.kernel.pendSV = 1U; } } @@ -57,17 +53,13 @@ static void KernelUnblock (void) { osRtxInfo.kernel.blocked = 0U; __DSB(); + if (osRtxInfo.kernel.pendSV != 0U) { osRtxInfo.kernel.pendSV = 0U; SetPendSV(); } - if (osRtxInfo.kernel.pendISR != 0U) { - SetPendFlags(osRtxInfo.kernel.pendISR); - } - if (osRtxInfo.tick_irqn >= 0) { - ExtTick_EnableIRQ(osRtxInfo.tick_irqn); - } - osRtxSysTimerEnable(); + + OS_Tick_Enable(); } @@ -83,7 +75,7 @@ SVC0_1 (KernelRestoreLock, int32_t, int32_t) SVC0_0 (KernelSuspend, uint32_t) SVC0_1N(KernelResume, void, uint32_t) SVC0_0 (KernelGetState, osKernelState_t) -SVC0_0D(KernelGetTickCount, uint64_t) +SVC0_0 (KernelGetTickCount, uint32_t) SVC0_0 (KernelGetTickFreq, uint32_t) SVC0_0 (KernelGetSysTimerCount, uint32_t) SVC0_0 (KernelGetSysTimerFreq, uint32_t) @@ -272,6 +264,17 @@ osStatus_t svcRtxKernelStart (void) { } } + // Setup RTOS Tick + if (OS_Tick_Setup(osRtxConfig.tick_freq, OS_TICK_HANDLER) != 0U) { + return osError; + } + osRtxInfo.tick_irqn = OS_Tick_GetIRQn(); + + // Enable RTOS Tick + if (OS_Tick_Enable() != 0U) { + return osError; + } + // Switch to Ready Thread with highest Priority thread = osRtxThreadListGet(&osRtxInfo.thread.ready); if (thread == NULL) { @@ -288,16 +291,6 @@ osStatus_t svcRtxKernelStart (void) { __set_CONTROL(0x03U); } - osRtxInfo.kernel.sys_freq = SystemCoreClock; - - // Setup and Enable System Timer - osRtxInfo.tick_irqn = osRtxSysTimerSetup(); - if (osRtxInfo.tick_irqn >= 0) { - ExtTick_SetupIRQ (osRtxInfo.tick_irqn); - ExtTick_EnableIRQ(osRtxInfo.tick_irqn); - } - osRtxSysTimerEnable(); - osRtxInfo.kernel.state = osRtxKernelRunning; EvrRtxKernelStarted(); @@ -467,7 +460,7 @@ void svcRtxKernelResume (uint32_t sleep_ticks) { /// Get the RTOS kernel tick count. /// \note API identical to osKernelGetTickCount -uint64_t svcRtxKernelGetTickCount (void) { +uint32_t svcRtxKernelGetTickCount (void) { EvrRtxKernelGetTickCount(osRtxInfo.kernel.tick); return osRtxInfo.kernel.tick; } @@ -482,7 +475,16 @@ uint32_t svcRtxKernelGetTickFreq (void) { /// Get the RTOS kernel system timer count. /// \note API identical to osKernelGetSysTimerCount uint32_t svcRtxKernelGetSysTimerCount (void) { - uint32_t count = osRtxSysTimerGetCount(); + uint32_t tick; + uint32_t count; + + tick = (uint32_t)osRtxInfo.kernel.tick; + count = OS_Tick_GetCount(); + if (OS_Tick_GetOverflow()) { + count = OS_Tick_GetCount(); + tick++; + } + count += tick * OS_Tick_GetInterval(); EvrRtxKernelGetSysTimerCount(count); return count; } @@ -490,7 +492,7 @@ uint32_t svcRtxKernelGetSysTimerCount (void) { /// Get the RTOS kernel system timer frequency. /// \note API identical to osKernelGetSysTimerFreq uint32_t svcRtxKernelGetSysTimerFreq (void) { - uint32_t freq = osRtxSysTimerGetFreq(); + uint32_t freq = OS_Tick_GetClock(); EvrRtxKernelGetSysTimerFreq(freq); return freq; } @@ -605,7 +607,7 @@ void osKernelResume (uint32_t sleep_ticks) { } /// Get the RTOS kernel tick count. -uint64_t osKernelGetTickCount (void) { +uint32_t osKernelGetTickCount (void) { if (IS_IRQ_MODE() || IS_IRQ_MASKED()) { return svcRtxKernelGetTickCount(); } else { diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_lib.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/rtx_lib.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c index 70b18e917a8..26325c507b9 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_lib.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.c @@ -609,33 +609,27 @@ __WEAK int _mutex_initialize(mutex *m) { } // Acquire mutex -#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED -#endif void _mutex_acquire(mutex *m); -__WEAK void _mutex_acquire(mutex *m) { +void _mutex_acquire(mutex *m) { if (os_kernel_is_active()) { osMutexAcquire(*m, osWaitForever); } } // Release mutex -#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED -#endif void _mutex_release(mutex *m); -__WEAK void _mutex_release(mutex *m) { +void _mutex_release(mutex *m) { if (os_kernel_is_active()) { osMutexRelease(*m); } } // Free mutex -#if !defined(__ARMCC_VERSION) || __ARMCC_VERSION < 6010050 __USED -#endif void _mutex_free(mutex *m); -__WEAK void _mutex_free(mutex *m) { +void _mutex_free(mutex *m) { osMutexDelete(*m); } diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_lib.h b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h similarity index 97% rename from rtos/TARGET_CORTEX/rtx5/rtx_lib.h rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h index fb7423db1d7..e5863f1b224 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_lib.h +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_lib.h @@ -1,5 +1,3 @@ -/** \addtogroup rtos */ -/** @{*/ /* * Copyright (c) 2013-2017 ARM Limited. All rights reserved. * @@ -30,8 +28,11 @@ #include #include -#include "core_cm.h" // Cortex-M definitions +#include "rtx_core_c.h" // Cortex core definitions +#if ((__ARM_ARCH_8M_BASE__ != 0) || (__ARM_ARCH_8M_MAIN__ != 0)) #include "tz_context.h" // TrustZone Context API +#endif +#include "os_tick.h" #include "cmsis_os2.h" // CMSIS RTOS API #include "rtx_os.h" // RTX OS definitions #include "rtx_evr.h" // RTX Event Recorder definitions @@ -124,7 +125,7 @@ extern int32_t svcRtxKernelUnlock (void); extern int32_t svcRtxKernelRestoreLock (int32_t lock); extern uint32_t svcRtxKernelSuspend (void); extern void svcRtxKernelResume (uint32_t sleep_ticks); -extern uint64_t svcRtxKernelGetTickCount (void); +extern uint32_t svcRtxKernelGetTickCount (void); extern uint32_t svcRtxKernelGetTickFreq (void); extern uint32_t svcRtxKernelGetSysTimerCount (void); extern uint32_t svcRtxKernelGetSysTimerFreq (void); @@ -154,7 +155,7 @@ extern uint32_t svcRtxThreadFlagsWait (uint32_t flags, uint32_t optio // Delay Service Calls extern osStatus_t svcRtxDelay (uint32_t ticks); -extern osStatus_t svcRtxDelayUntil (uint32_t ticks_l, uint32_t ticks_h); +extern osStatus_t svcRtxDelayUntil (uint32_t ticks); // Timer Service Calls extern osTimerId_t svcRtxTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr); @@ -212,5 +213,5 @@ extern uint32_t svcRtxMessageQueueGetSpace (osMessageQueueId_t mq_i extern osStatus_t svcRtxMessageQueueReset (osMessageQueueId_t mq_id); extern osStatus_t svcRtxMessageQueueDelete (osMessageQueueId_t mq_id); + #endif // RTX_LIB_H_ -/** @}*/ diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_memory.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_memory.c similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rtx_memory.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_memory.c diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_mempool.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rtx_mempool.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mempool.c diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c similarity index 99% rename from rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c index d147e81c2f2..ae33f641f88 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_msgqueue.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_msgqueue.c @@ -252,8 +252,7 @@ osMessageQueueId_t svcRtxMessageQueueNew (uint32_t msg_count, uint32_t msg_size, EvrRtxMessageQueueError(NULL, osErrorParameter); return NULL; } - msg_size = (msg_size + 3U) & ~3UL; - block_size = msg_size + sizeof(os_message_t); + block_size = ((msg_size + 3U) & ~3UL) + sizeof(os_message_t); if ((__CLZ(msg_count) + __CLZ(block_size)) < 32) { EvrRtxMessageQueueError(NULL, osErrorParameter); return NULL; diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_mutex.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c similarity index 93% rename from rtos/TARGET_CORTEX/rtx5/rtx_mutex.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c index 4a274f8616b..2151c0251d0 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_mutex.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_mutex.c @@ -161,10 +161,10 @@ const char *svcRtxMutexGetName (osMutexId_t mutex_id) { /// \note API identical to osMutexAcquire osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { os_mutex_t *mutex = (os_mutex_t *)mutex_id; - os_thread_t *running_thread; + os_thread_t *runnig_thread; - running_thread = osRtxThreadGetRunning(); - if (running_thread == NULL) { + runnig_thread = osRtxThreadGetRunning(); + if (runnig_thread == NULL) { EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning); return osError; } @@ -184,20 +184,20 @@ osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { // Check if Mutex is not locked if (mutex->lock == 0U) { // Acquire Mutex - mutex->owner_thread = running_thread; - mutex->owner_next = running_thread->mutex_list; + mutex->owner_thread = runnig_thread; + mutex->owner_next = runnig_thread->mutex_list; mutex->owner_prev = NULL; - if (running_thread->mutex_list != NULL) { - running_thread->mutex_list->owner_prev = mutex; + if (runnig_thread->mutex_list != NULL) { + runnig_thread->mutex_list->owner_prev = mutex; } - running_thread->mutex_list = mutex; + runnig_thread->mutex_list = mutex; mutex->lock = 1U; EvrRtxMutexAcquired(mutex, mutex->lock); return osOK; } // Check if Mutex is recursive and running Thread is the owner - if ((mutex->attr & osMutexRecursive) && (mutex->owner_thread == running_thread)) { + if ((mutex->attr & osMutexRecursive) && (mutex->owner_thread == runnig_thread)) { // Increment lock counter if (mutex->lock == osRtxMutexLockLimit) { EvrRtxMutexError(mutex, osRtxErrorMutexLockLimit); @@ -213,14 +213,14 @@ osStatus_t svcRtxMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) { // Check if Priority inheritance protocol is enabled if (mutex->attr & osMutexPrioInherit) { // Raise priority of owner Thread if lower than priority of running Thread - if (mutex->owner_thread->priority < running_thread->priority) { - mutex->owner_thread->priority = running_thread->priority; + if (mutex->owner_thread->priority < runnig_thread->priority) { + mutex->owner_thread->priority = runnig_thread->priority; osRtxThreadListSort(mutex->owner_thread); } } EvrRtxMutexAcquirePending(mutex, timeout); // Suspend current Thread - osRtxThreadListPut((os_object_t*)mutex, running_thread); + osRtxThreadListPut((os_object_t*)mutex, runnig_thread); osRtxThreadWaitEnter(osRtxThreadWaitingMutex, timeout); return osErrorTimeout; } @@ -237,11 +237,11 @@ osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { os_mutex_t *mutex = (os_mutex_t *)mutex_id; os_mutex_t *mutex0; os_thread_t *thread; - os_thread_t *running_thread; + os_thread_t *runnig_thread; int8_t priority; - running_thread = osRtxThreadGetRunning(); - if (running_thread == NULL) { + runnig_thread = osRtxThreadGetRunning(); + if (runnig_thread == NULL) { EvrRtxMutexError(mutex, osRtxErrorKernelNotRunning); return osError; } @@ -259,7 +259,7 @@ osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { } // Check if running Thread is not the owner - if (mutex->owner_thread != running_thread) { + if (mutex->owner_thread != runnig_thread) { EvrRtxMutexError(mutex, osRtxErrorMutexNotOwned); return osErrorResource; } @@ -286,13 +286,13 @@ osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { if (mutex->owner_prev != NULL) { mutex->owner_prev->owner_next = mutex->owner_next; } else { - running_thread->mutex_list = mutex->owner_next; + runnig_thread->mutex_list = mutex->owner_next; } // Restore running Thread priority if (mutex->attr & osMutexPrioInherit) { - priority = running_thread->priority_base; - mutex0 = running_thread->mutex_list; + priority = runnig_thread->priority_base; + mutex0 = runnig_thread->mutex_list; while (mutex0) { // Mutexes owned by running Thread if ((mutex0->thread_list != NULL) && (mutex0->thread_list->priority > priority)) { @@ -301,7 +301,7 @@ osStatus_t svcRtxMutexRelease (osMutexId_t mutex_id) { } mutex0 = mutex0->owner_next; } - running_thread->priority = priority; + runnig_thread->priority = priority; } // Check if Thread is waiting for a Mutex diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_semaphore.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rtx_semaphore.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_semaphore.c diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_system.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c similarity index 84% rename from rtos/TARGET_CORTEX/rtx5/rtx_system.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c index c8715cd54d5..fc64c931c5b 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_system.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_system.c @@ -120,7 +120,7 @@ static void *isr_queue_get (void) { void osRtxTick_Handler (void) { os_thread_t *thread; - osRtxSysTimerAckIRQ(); + OS_Tick_AcknowledgeIRQ(); osRtxInfo.kernel.tick++; // Process Timers @@ -207,51 +207,3 @@ void osRtxPostProcess (os_object_t *object) { osRtxErrorNotify(osRtxErrorISRQueueOverflow, object); } } - - -// ==== Public API ==== - -/// Setup System Timer. -__WEAK int32_t osRtxSysTimerSetup (void) { - - // Setup SysTick Timer - SysTick_Setup(osRtxInfo.kernel.sys_freq / osRtxConfig.tick_freq); - - return SysTick_IRQn; // Return IRQ number of SysTick -} - -/// Enable System Timer. -__WEAK void osRtxSysTimerEnable (void) { - SysTick_Enable(); -} - -/// Disable System Timer. -__WEAK void osRtxSysTimerDisable (void) { - SysTick_Disable(); -} - -/// Acknowledge System Timer IRQ. -__WEAK void osRtxSysTimerAckIRQ (void) { - SysTick_GetOvf(); -} - -/// Get System Timer count. -__WEAK uint32_t osRtxSysTimerGetCount (void) { - uint32_t tick; - uint32_t val; - - tick = (uint32_t)osRtxInfo.kernel.tick; - val = SysTick_GetVal(); - if (SysTick_GetOvf()) { - val = SysTick_GetVal(); - tick++; - } - val += tick * SysTick_GetPeriod(); - - return val; -} - -/// Get System Timer frequency. -__WEAK uint32_t osRtxSysTimerGetFreq (void) { - return osRtxInfo.kernel.sys_freq; -} diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_thread.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c similarity index 98% rename from rtos/TARGET_CORTEX/rtx5/rtx_thread.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c index aae22a07ed4..6e15a4c4fa6 100644 --- a/rtos/TARGET_CORTEX/rtx5/rtx_thread.c +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_thread.c @@ -26,7 +26,6 @@ #include "rtx_lib.h" #include "rt_OsEventObserver.h" - // ==== Helper functions ==== /// Set Thread Flags. @@ -378,19 +377,7 @@ void osRtxThreadDelayTick (void) { /// \param[in] thread thread object. /// \return pointer to registers R0-R3. uint32_t *osRtxThreadRegPtr (os_thread_t *thread) { - -#if (__FPU_USED == 1U) - if (IS_EXTENDED_STACK_FRAME(thread->stack_frame)) { - // Extended Stack Frame: S16-S31, R4-R11, R0-R3, R12, LR, PC, xPSR, S0-S15, FPSCR - return ((uint32_t *)(thread->sp + (16U+8U)*4U)); - } else { - // Basic Stack Frame: R4-R11, R0-R3, R12, LR, PC, xPSR - return ((uint32_t *)(thread->sp + 8U *4U)); - } -#else - // Stack Frame: R4-R11, R0-R3, R12, LR, PC, xPSR - return ((uint32_t *)(thread->sp + 8U*4U)); -#endif + return ((uint32_t *)(thread->sp + STACK_OFFSET_R0(thread->stack_frame))); } /// Block running Thread execution and register it as Ready to Run. @@ -443,6 +430,12 @@ void osRtxThreadDispatch (os_thread_t *thread) { kernel_state = osRtxKernelGetState(); thread_running = osRtxThreadGetRunning(); +#if (__ARM_ARCH_7A__ != 0U) + // On Cortex-A PendSV_Handler is executed before final context switch. + if ((thread_running != NULL) && (thread_running->state != osRtxThreadRunning)) { + thread_running = osRtxInfo.thread.run.next; + } +#endif if (thread == NULL) { thread = osRtxInfo.thread.ready.thread_list; @@ -769,7 +762,10 @@ osThreadId_t svcRtxThreadNew (osThreadFunc_t func, void *argument, const osThrea } *ptr++ = (uint32_t)osThreadExit; // LR *ptr++ = (uint32_t)func; // PC - *ptr++ = XPSR_INITIAL_VALUE; // xPSR + *ptr++ = xPSR_INIT( + (osRtxConfig.flags & osRtxConfigPrivilegedMode), + ((uint32_t)func & 1U) + ); // xPSR *(ptr-8) = (uint32_t)argument; // R0 // Register post ISR processing function diff --git a/rtos/TARGET_CORTEX/rtx5/rtx_timer.c b/rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c similarity index 100% rename from rtos/TARGET_CORTEX/rtx5/rtx_timer.c rename to rtos/TARGET_CORTEX/rtx5/RTX/Source/rtx_timer.c diff --git a/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c b/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c new file mode 100644 index 00000000000..16bf53c0a41 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/Source/os_systick.c @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file os_systick.c + * @brief CMSIS OS Tick SysTick implementation + * @version V1.0.0 + * @date 05. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "os_tick.h" + +#include + +#ifdef SysTick + +#ifndef SYSTICK_IRQ_PRIORITY +#define SYSTICK_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PendST; + +// Setup OS Tick. +__WEAK int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + (void)handler; + + if (freq == 0U) { + return (-1); + } + + load = (SystemCoreClock / freq) - 1U; + if (load > 0x00FFFFFFU) { + return (-1); + } + + // Set SysTick Interrupt Priority +#if ((defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1U)) || \ + (defined(__CORTEX_M) && (__CORTEX_M == 7U))) + SCB->SHPR[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1U)) + SCB->SHPR[1] |= (SYSTICK_IRQ_PRIORITY << 24); +#elif ((defined(__ARM_ARCH_7M__) && (__ARM_ARCH_7M__ == 1U)) || \ + (defined(__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1U))) + SCB->SHP[11] = SYSTICK_IRQ_PRIORITY; +#elif (defined(__ARM_ARCH_6M__) && (__ARM_ARCH_6M__ == 1U)) + SCB->SHP[1] |= (SYSTICK_IRQ_PRIORITY << 24); +#else +#error "Unknown ARM Core!" +#endif + + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk; + SysTick->LOAD = load; + SysTick->VAL = 0U; + + PendST = 0U; + + return (0); +} + +/// Enable OS Tick. +__WEAK int32_t OS_Tick_Enable (void) { + + if (PendST != 0U) { + PendST = 0U; + SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; + } + + SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; + + return (0); +} + +/// Disable OS Tick. +__WEAK int32_t OS_Tick_Disable (void) { + + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + + if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0U) { + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + PendST = 1U; + } + + return (0); +} + +// Acknowledge OS Tick IRQ. +__WEAK int32_t OS_Tick_AcknowledgeIRQ (void) { + (void)SysTick->CTRL; + return (0); +} + +// Get OS Tick IRQ number. +__WEAK int32_t OS_Tick_GetIRQn (void) { + return (SysTick_IRQn); +} + +// Get OS Tick clock. +__WEAK uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +__WEAK uint32_t OS_Tick_GetInterval (void) { + return (SysTick->LOAD + 1U); +} + +// Get OS Tick count value. +__WEAK uint32_t OS_Tick_GetCount (void) { + uint32_t load = SysTick->LOAD; + return (load - SysTick->VAL); +} + +// Get OS Tick overflow status. +__WEAK uint32_t OS_Tick_GetOverflow (void) { + return ((SysTick->CTRL >> 16) & 1U); +} + +#endif // SysTick diff --git a/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c b/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c new file mode 100644 index 00000000000..b909e7e3302 --- /dev/null +++ b/rtos/TARGET_CORTEX/rtx5/Source/os_tick_ptim.c @@ -0,0 +1,169 @@ +/**************************************************************************//** + * @file os_tick_ptim.c + * @brief CMSIS OS Tick implementation for Private Timer + * @version V1.0.0 + * @date 29. June 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(PTIM) + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include + +#ifndef PTIM_IRQ_PRIORITY +#define PTIM_IRQ_PRIORITY 0xFFU +#endif + +static uint8_t PTIM_PendIRQ; // Timer interrupt pending flag + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) { + uint32_t load; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + PTIM_PendIRQ = 0U; + + // Private Timer runs with the system frequency + load = (SystemCoreClock / freq) - 1U; + + // Disable Private Timer and set load value + PTIM_SetControl (0U); + PTIM_SetLoadValue (load); + + // Disable corresponding IRQ + IRQ_Disable (PrivTimer_IRQn); + IRQ_ClearPending(PrivTimer_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (PrivTimer_IRQn, 0xFFU); + + prio = IRQ_GetPriority (PrivTimer_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (PTIM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set Private Timer interrupt priority + IRQ_SetPriority(PrivTimer_IRQn, prio-1U); + + // Set edge-triggered IRQ + IRQ_SetMode(PrivTimer_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(PrivTimer_IRQn, handler); + + // Enable corresponding interrupt + IRQ_Enable (PrivTimer_IRQn); + + // Set bits: IRQ enable and Auto reload + PTIM_SetControl (0x06U); + + return (0); +} + +/// Enable OS Tick. +int32_t OS_Tick_Enable (void) { + uint32_t ctrl; + + // Set pending interrupt if flag set + if (PTIM_PendIRQ != 0U) { + PTIM_PendIRQ = 0U; + IRQ_SetPending (PrivTimer_IRQn); + } + + // Start the Private Timer + ctrl = PTIM_GetControl(); + // Set bit: Timer enable + ctrl |= 1U; + PTIM_SetControl (ctrl); + + return (0); +} + +/// Disable OS Tick. +int32_t OS_Tick_Disable (void) { + uint32_t ctrl; + + // Stop the Private Timer + ctrl = PTIM_GetControl(); + // Clear bit: Timer enable + ctrl &= ~1U; + PTIM_SetControl (ctrl); + + // Remember pending interrupt flag + if (IRQ_GetPending(PrivTimer_IRQn) != 0) { + IRQ_ClearPending (PrivTimer_IRQn); + PTIM_PendIRQ = 1U; + } + + return (0); +} + +// Acknowledge OS Tick IRQ. +int32_t OS_Tick_AcknowledgeIRQ (void) { + PTIM_ClearEventFlag(); + return (0); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) { + return (PrivTimer_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) { + return (SystemCoreClock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) { + return (PTIM_GetLoadValue() + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) { + uint32_t load = PTIM_GetLoadValue(); + return (load - PTIM_GetCurrentValue()); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) { + return (PTIM->ISR & 1); +} + +#endif // PTIM diff --git a/rtos/TARGET_CORTEX/rtx5/TESTS/memory/heap_and_stack/main.cpp b/rtos/TARGET_CORTEX/rtx5/TESTS/memory/heap_and_stack/main.cpp deleted file mode 100644 index 7e273504d14..00000000000 --- a/rtos/TARGET_CORTEX/rtx5/TESTS/memory/heap_and_stack/main.cpp +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2016-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include -#include -#include "greentea-client/test_env.h" -#include "cmsis.h" -#include "mbed.h" -#include "rtos.h" -#include "mbed_assert.h" - -// Amount to malloc for each iteration -#define MALLOC_TEST_SIZE 256 -// Malloc fill pattern -#define MALLOC_FILL 0x55 - -extern uint32_t mbed_heap_start; -extern uint32_t mbed_heap_size; -extern uint32_t mbed_stack_isr_start; -extern uint32_t mbed_stack_isr_size; - -static uint32_t max_allocation_size = 0; - -static bool inrange(uint32_t addr, uint32_t start, uint32_t size); -static bool rangeinrange(uint32_t addr, uint32_t size, uint32_t start, uint32_t len); -static bool valid_fill(uint8_t * data, uint32_t size, uint8_t fill); -static bool allocate_and_fill_heap(void); -static bool check_and_free_heap(void); - -int main (void) { - GREENTEA_SETUP(30, "default_auto"); - - char c; - char * initial_stack = &c; - char *initial_heap; - - // Sanity check malloc - initial_heap = (char*)malloc(1); - if (initial_heap == NULL) { - printf("Unable to malloc a single byte\n"); - GREENTEA_TESTSUITE_RESULT(false); - } - - if (!inrange((uint32_t)initial_heap, mbed_heap_start, mbed_heap_size)) { - printf("Heap in wrong location\n"); - GREENTEA_TESTSUITE_RESULT(false); - } - // MSP stack should be very near end (test using within 128 bytes) - uint32_t msp = __get_MSP(); - if (!inrange(msp, mbed_stack_isr_start + mbed_stack_isr_size - 128, 128)) { - printf("Interrupt stack in wrong location\n"); - GREENTEA_TESTSUITE_RESULT(false); - } - - // Fully allocate the heap and stack - bool ret = true; - ret = ret && allocate_and_fill_heap(); - ret = ret && check_and_free_heap(); - - // Force a task switch so a stack check is performed - Thread::wait(10); - - printf("Total size dynamically allocated: %lu\n", max_allocation_size); - - GREENTEA_TESTSUITE_RESULT(ret); -} - -/* - * Return true if addr is in range [start:start+size) - */ -static bool inrange(uint32_t addr, uint32_t start, uint32_t size) -{ - return (addr >= start) && (addr < start + size) ? true : false; -} - -/* - * Return true if [addr:addr+size] is inside [start:start+len] - */ -static bool rangeinrange(uint32_t addr, uint32_t size, uint32_t start, uint32_t len) -{ - if (addr + size > start + len) { - return false; - } - if (addr < start) { - return false; - } - return true; -} - -/* - * Return true of the region is filled only the the specified fill value - */ -static bool valid_fill(uint8_t * data, uint32_t size, uint8_t fill) -{ - for (uint32_t i = 0; i < size; i++) { - if (data[i] != fill) { - return false; - } - } - return true; -} - -struct linked_list { - linked_list * next; - uint8_t data[MALLOC_TEST_SIZE]; -}; - -static linked_list *head = NULL; -static bool allocate_and_fill_heap() -{ - - linked_list *current; - - current = (linked_list*)malloc(sizeof(linked_list)); - if (0 == current) { - return false; - } - current->next = NULL; - memset((void*)current->data, MALLOC_FILL, sizeof(current->data)); - - // Allocate until malloc returns NULL - bool pass = true; - head = current; - while (true) { - - // Allocate - linked_list *temp = (linked_list*)malloc(sizeof(linked_list)); - if (NULL == temp) { - break; - } - if (!rangeinrange((uint32_t)temp, sizeof(linked_list), mbed_heap_start, mbed_heap_size)) { - printf("Memory allocation out of range\n"); - pass = false; - break; - } - - // Init - temp->next = NULL; - memset((void*)temp->data, MALLOC_FILL, sizeof(current->data)); - - // Add to list - current->next = temp; - current = temp; - } - return pass; -} - -static bool check_and_free_heap() -{ - uint32_t total_size = 0; - linked_list * current = head; - bool pass = true; - while (current != NULL) { - total_size += sizeof(linked_list); - if (!valid_fill(current->data, sizeof(current->data), MALLOC_FILL)) { - pass = false; - } - linked_list * next = current->next; - free(current); - current = next; - } - - max_allocation_size = total_size; - return pass; -} diff --git a/rtos/Thread.cpp b/rtos/Thread.cpp index f01f1b1502d..20c1a083de6 100644 --- a/rtos/Thread.cpp +++ b/rtos/Thread.cpp @@ -23,6 +23,15 @@ #include "mbed.h" #include "rtos/rtos_idle.h" +#include "mbed_assert.h" + +#define ALIGN_UP(pos, align) ((pos) % (align) ? (pos) + ((align) - (pos) % (align)) : (pos)) +MBED_STATIC_ASSERT(ALIGN_UP(0, 8) == 0, "ALIGN_UP macro error"); +MBED_STATIC_ASSERT(ALIGN_UP(1, 8) == 8, "ALIGN_UP macro error"); + +#define ALIGN_DOWN(pos, align) ((pos) - ((pos) % (align))) +MBED_STATIC_ASSERT(ALIGN_DOWN(7, 8) == 0, "ALIGN_DOWN macro error"); +MBED_STATIC_ASSERT(ALIGN_DOWN(8, 8) == 8, "ALIGN_DOWN macro error"); static void (*terminate_hook)(osThreadId_t id) = 0; extern "C" void thread_terminate_hook(osThreadId_t id) @@ -36,15 +45,21 @@ namespace rtos { void Thread::constructor(osPriority priority, uint32_t stack_size, unsigned char *stack_mem, const char *name) { + + const uintptr_t unaligned_mem = reinterpret_cast(stack_mem); + const uintptr_t aligned_mem = ALIGN_UP(unaligned_mem, 8); + const uint32_t offset = aligned_mem - unaligned_mem; + const uint32_t aligned_size = ALIGN_DOWN(stack_size - offset, 8); + _tid = 0; _dynamic_stack = (stack_mem == NULL); _finished = false; memset(&_obj_mem, 0, sizeof(_obj_mem)); memset(&_attr, 0, sizeof(_attr)); _attr.priority = priority; - _attr.stack_size = stack_size; + _attr.stack_size = aligned_size; _attr.name = name ? name : "application_unnamed_thread"; - _attr.stack_mem = (uint32_t*)stack_mem; + _attr.stack_mem = reinterpret_cast(aligned_mem); } void Thread::constructor(Callback task, diff --git a/rtos/Thread.h b/rtos/Thread.h index 7aa4faa2762..d67ad3acf81 100644 --- a/rtos/Thread.h +++ b/rtos/Thread.h @@ -35,6 +35,10 @@ namespace rtos { /** \addtogroup rtos */ /** @{*/ +/** + * \defgroup rtos_Thread Thread class + * @{ + */ /** The Thread class allow defining, creating, and controlling thread functions in the system. * @@ -246,7 +250,7 @@ class Thread : private mbed::NonCopyable { /** Set the specified Thread Flags for the thread. @param signals specifies the signal flags of the thread that should be set. - @return previous signal flags of the specified thread or osFlagsError in case of incorrect parameters. + @return signal flags after setting or osFlagsError in case of incorrect parameters. */ int32_t signal_set(int32_t signals); @@ -305,7 +309,7 @@ class Thread : private mbed::NonCopyable { /** Clears the specified Thread Flags of the currently running thread. @param signals specifies the signal flags of the thread that should be cleared. - @return resultant signal flags of the specified thread or osFlagsError in case of incorrect parameters. + @return signal flags before clearing or osFlagsError in case of incorrect parameters. */ static int32_t signal_clr(int32_t signals); @@ -370,8 +374,9 @@ class Thread : private mbed::NonCopyable { mbed_rtos_storage_thread_t _obj_mem; bool _finished; }; - +/** @}*/ +/** @}*/ } #endif -/** @}*/ + diff --git a/rtos/rtos.h b/rtos/rtos.h index 7a10c8e60b5..0856dd408a5 100644 --- a/rtos/rtos.h +++ b/rtos/rtos.h @@ -34,6 +34,7 @@ #include "rtos/MemoryPool.h" #include "rtos/Queue.h" #include "rtos/EventFlags.h" +#include "rtos/ConditionVariable.h" using namespace rtos; diff --git a/rtos/rtos_idle.h b/rtos/rtos_idle.h index 5fa9fb776c0..c2894c23e30 100644 --- a/rtos/rtos_idle.h +++ b/rtos/rtos_idle.h @@ -31,7 +31,17 @@ extern "C" { #endif +/** + * \defgroup rtos_Idle Idle hook function + * @{ + */ +/** + @note + Sets the hook function called by idle task + @param fptr Hook function pointer. + */ void rtos_attach_idle_hook(void (*fptr)(void)); +/** @}*/ #ifdef __cplusplus } @@ -40,3 +50,4 @@ void rtos_attach_idle_hook(void (*fptr)(void)); #endif /** @}*/ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/PinNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/PinNames.h new file mode 100755 index 00000000000..032050d1176 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/PinNames.h @@ -0,0 +1,206 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#include "adi_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +//update + +#define GPIO_PORT_SHIFT 12 + + +typedef enum { + P0_00 = (0 << GPIO_PORT_SHIFT | 0 ), + P0_01 = (0 << GPIO_PORT_SHIFT | 1 ), + P0_02 = (0 << GPIO_PORT_SHIFT | 2 ), + P0_03 = (0 << GPIO_PORT_SHIFT | 3 ), + P0_04 = (0 << GPIO_PORT_SHIFT | 4 ), + P0_05 = (0 << GPIO_PORT_SHIFT | 5 ), + P0_06 = (0 << GPIO_PORT_SHIFT | 6 ), + P0_07 = (0 << GPIO_PORT_SHIFT | 7 ), + P0_08 = (0 << GPIO_PORT_SHIFT | 8 ), + P0_09 = (0 << GPIO_PORT_SHIFT | 9 ), + P0_10 = (0 << GPIO_PORT_SHIFT | 10), + P0_11 = (0 << GPIO_PORT_SHIFT | 11), + P0_12 = (0 << GPIO_PORT_SHIFT | 12), + P0_13 = (0 << GPIO_PORT_SHIFT | 13), + P0_14 = (0 << GPIO_PORT_SHIFT | 14), + P0_15 = (0 << GPIO_PORT_SHIFT | 15), + P1_00 = (1 << GPIO_PORT_SHIFT | 0 ), + P1_01 = (1 << GPIO_PORT_SHIFT | 1 ), + P1_02 = (1 << GPIO_PORT_SHIFT | 2 ), + P1_03 = (1 << GPIO_PORT_SHIFT | 3 ), + P1_04 = (1 << GPIO_PORT_SHIFT | 4 ), + P1_05 = (1 << GPIO_PORT_SHIFT | 5 ), + P1_06 = (1 << GPIO_PORT_SHIFT | 6 ), + P1_07 = (1 << GPIO_PORT_SHIFT | 7 ), + P1_08 = (1 << GPIO_PORT_SHIFT | 8 ), + P1_09 = (1 << GPIO_PORT_SHIFT | 9 ), + P1_10 = (1 << GPIO_PORT_SHIFT | 10), + P1_11 = (1 << GPIO_PORT_SHIFT | 11), + P1_12 = (1 << GPIO_PORT_SHIFT | 12), + P1_13 = (1 << GPIO_PORT_SHIFT | 13), + P1_14 = (1 << GPIO_PORT_SHIFT | 14), + P1_15 = (1 << GPIO_PORT_SHIFT | 15), + P2_00 = (2 << GPIO_PORT_SHIFT | 0 ), + P2_01 = (2 << GPIO_PORT_SHIFT | 1 ), + P2_02 = (2 << GPIO_PORT_SHIFT | 2 ), + P2_03 = (2 << GPIO_PORT_SHIFT | 3 ), + P2_04 = (2 << GPIO_PORT_SHIFT | 4 ), + P2_05 = (2 << GPIO_PORT_SHIFT | 5 ), + P2_06 = (2 << GPIO_PORT_SHIFT | 6 ), + P2_07 = (2 << GPIO_PORT_SHIFT | 7 ), + P2_08 = (2 << GPIO_PORT_SHIFT | 8 ), + P2_09 = (2 << GPIO_PORT_SHIFT | 9 ), + P2_10 = (2 << GPIO_PORT_SHIFT | 10), + P2_11 = (2 << GPIO_PORT_SHIFT | 11), + + // USB Pins + USBTX = P0_10, + USBRX = P0_11, + USBTX1 = P1_15, + USBRX1 = P2_00, + + // mbed original LED naming + LED1 = P2_02, + LED2 = P2_10, + LED3 = LED2, + LED4 = LED1, + + //Push buttons + PB0 = P1_00, // BTN1 + PB1 = P0_09, // BTN2 + BOOT = P1_01, + WAKE0 = P0_15, // JP15 to select + WAKE1 = P1_00, // JP8 (BTN1 jumper) to select + WAKE2 = P0_13, // JP4 to select + WAKE3 = P2_01, // JP15 to select + + // SPI Pins + SPI0_SCLK = P0_00, + SPI0_MOSI = P0_01, + SPI0_MISO = P0_02, + SPI0_CS0 = P0_03, + SPI0_CS1 = P1_10, + SPI0_CS2 = P2_08, + SPI0_CS3 = P2_09, + + SPI1_SCLK = P1_06, + SPI1_MOSI = P1_07, + SPI1_MISO = P1_08, + SPI1_CS0 = P1_09, + SPI1_CS1 = P2_11, + SPI1_CS2 = P2_02, + SPI1_CS3 = P1_10, + + SPI2_SCLK = P1_02, + SPI2_MOSI = P1_03, + SPI2_MISO = P1_04, + SPI2_CS0 = P1_05, + SPI2_CS1 = P0_09, + SPI2_CS2 = P2_10, + SPI2_CS3 = P2_07, + + // ADC Pins + ADC_VIN0 = P2_03, + ADC_VIN1 = P2_04, + ADC_VIN2 = P2_05, + ADC_VIN3 = P2_06, + ADC_VIN4 = P2_07, + ADC_VIN5 = P2_08, + ADC_VIN6 = P2_09, + ADC_VIN7 = P2_10, + + // Arduino Headers + D0 = P0_10, // UART0_TXD + D1 = P0_11, // UART0_RXD + D2 = P0_15, // INT_WAKE0 + D3 = P0_13, // EXT_INT_WAKE2 + D4 = P0_09, // EXT_SPI2_CS1 + D5 = P2_01, // INT_WAKE3 or EXT_RTC1_SS1 via JP8 + D6 = P1_11, // GPIO_27 + D7 = P0_12, // GPIO_08 or GPIO_12 via JP7 + + D8 = P1_12, // GPIO_28 + D9 = P1_14, // GPIO_30 + D10 = SPI0_CS2, // P2_08 + D11 = SPI0_MOSI, // P0_01 + D12 = SPI0_MISO, // P0_02 + D13 = SPI0_SCLK, // P0_00 + I2C_SCL = P0_04, // I2C_SCL + I2C_SDA = P0_05, // I2C_SDA + + A0 = P2_03, // ADC0 + A1 = P2_04, // EXT_ADC1 + A2 = P2_05, // EXT_ADC2 + A3 = P2_06, // ADC3 + A4 = P2_07, // SPI2_CS3/ADC_VIN4 + A5 = P2_10, // EXT_GPIO42/ADC_VIN7 + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c new file mode 100755 index 00000000000..be30d4c5e74 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c @@ -0,0 +1,272 @@ +/*! + ***************************************************************************** + * @file: startup_ADuCM3029.c + * @brief: Interrupt table and default handlers for ADuCM302x + * @version: $Revision: $ + * @date: $Date: $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#include +#ifdef __CC_ARM +#include +#endif +#include +#include +#include + + +/*---------------------------------------------------------------------------- + External function Declaration + *----------------------------------------------------------------------------*/ +extern void SramInit(void); + +/*---------------------------------------------------------------------------- + Checksum options + *----------------------------------------------------------------------------*/ + #if defined (__CC_ARM) +__attribute__ ((at(0x000001A0u))) +#elif defined( __ICCARM__) +__root +#endif /* __ICCARM__ */ +const uint32_t SECTION_PLACE(blank_checksum[],".checksum") = +{ + BLANKX60,BLANKX600 +}; + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +WEAK_FUNCTION( NMI_Handler ) +WEAK_FUNCTION( HardFault_Handler ) +WEAK_FUNCTION( MemManage_Handler ) +WEAK_FUNCTION( BusFault_Handler ) +WEAK_FUNCTION( UsageFault_Handler ) +WEAK_FUNCTION( SVC_Handler ) +WEAK_FUNCTION( DebugMon_Handler ) +WEAK_FUNCTION( PendSV_Handler ) +WEAK_FUNCTION( SysTick_Handler ) +WEAK_FUNCTION( RTC1_Int_Handler ) +WEAK_FUNCTION( Ext_Int0_Handler ) +WEAK_FUNCTION( Ext_Int1_Handler ) +WEAK_FUNCTION( Ext_Int2_Handler ) +WEAK_FUNCTION( Ext_Int3_Handler ) +WEAK_FUNCTION( WDog_Tmr_Int_Handler ) +WEAK_FUNCTION( Vreg_over_Int_Handler ) +WEAK_FUNCTION( Battery_Voltage_Int_Handler ) +WEAK_FUNCTION( RTC0_Int_Handler ) +WEAK_FUNCTION( GPIO_A_Int_Handler ) +WEAK_FUNCTION( GPIO_B_Int_Handler ) +WEAK_FUNCTION( GP_Tmr0_Int_Handler ) +WEAK_FUNCTION( GP_Tmr1_Int_Handler ) +WEAK_FUNCTION( Flash0_Int_Handler ) +WEAK_FUNCTION( UART_Int_Handler ) +WEAK_FUNCTION( SPI0_Int_Handler ) +WEAK_FUNCTION( SPI2_Int_Handler ) +WEAK_FUNCTION( I2C0_Slave_Int_Handler ) +WEAK_FUNCTION( I2C0_Master_Int_Handler ) +WEAK_FUNCTION( DMA_Err_Int_Handler ) +WEAK_FUNCTION( DMA_SPI2_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI2_RX_Int_Handler ) +WEAK_FUNCTION( DMA_SPORT0A_Int_Handler ) +WEAK_FUNCTION( DMA_SPORT0B_Int_Handler ) +WEAK_FUNCTION( DMA_SPI0_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI0_RX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI1_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI1_RX_Int_Handler ) +WEAK_FUNCTION( DMA_UART_TX_Int_Handler ) +WEAK_FUNCTION( DMA_UART_RX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_STX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_SRX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_MX_Int_Handler ) +WEAK_FUNCTION( DMA_AES0_IN_Int_Handler ) +WEAK_FUNCTION( DMA_AES0_OUT_Int_Handler ) +WEAK_FUNCTION( DMA_FLASH0_Int_Handler ) +WEAK_FUNCTION( SPORT0A_Int_Handler ) +WEAK_FUNCTION( SPORT0B_Int_Handler ) +WEAK_FUNCTION( Crypto_Int_Handler ) +WEAK_FUNCTION( DMA_ADC0_Int_Handler ) +WEAK_FUNCTION( GP_Tmr2_Int_Handler ) +WEAK_FUNCTION( Crystal_osc_Int_Handler ) +WEAK_FUNCTION( SPI1_Int_Handler ) +WEAK_FUNCTION( PLL_Int_Handler ) +WEAK_FUNCTION( RNG_Int_Handler ) +WEAK_FUNCTION( Beep_Int_Handler ) +WEAK_FUNCTION( ADC_Int_Handler ) +WEAK_FUNCTION( DMA_SIP0_Int_Handler ) +WEAK_FUNCTION( DMA_SIP1_Int_Handler ) +WEAK_FUNCTION( DMA_SIP2_Int_Handler ) +WEAK_FUNCTION( DMA_SIP3_Int_Handler ) +WEAK_FUNCTION( DMA_SIP4_Int_Handler ) +WEAK_FUNCTION( DMA_SIP5_Int_Handler ) +WEAK_FUNCTION( DMA_SIP6_Int_Handler ) +WEAK_FUNCTION( DMA_SIP7_Int_Handler ) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) = +{ + (pFunc) INITIAL_SP, /* Initial Stack Pointer */ + ADUCM3029_VECTORS +}; + +/*---------------------------------------------------------------------------- +* Initialize .bss and .data for GNU +*----------------------------------------------------------------------------*/ +#if defined( __GNUC__) && !defined (__CC_ARM) +void zero_bss(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = (uint32_t*)(&__etext); + pDest = (uint32_t*)(&__data_start__); + + for ( ; pDest < (uint32_t*)(&__data_end__) ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = (uint32_t*)(&__zero_table_start__); + + for (; pTable < (uint32_t*)(&__zero_table_end__); pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0ul; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ +} +#endif + +/*---------------------------------------------------------------------------- +* Function : Reset_Handler (-15) +* Description : Reset event handler +*----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + /* Configure the SRAM first. This is done first because the bss section + may reside in DSRAM bank B. */ + SramInit(); + +#if defined(__GNUC__) && !defined (__CC_ARM) + /* Clear the bss section for GCC build only */ + zero_bss(); +#endif + + /* initialize system */ + SystemInit(); + + /* branch to other initialization routines before main */ + RESET_EXCPT_HNDLR(); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +#if defined(__CC_ARM) || defined (__GNUC__) +void Default_Handler(void) +{ + while(1); +} +#endif + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h new file mode 100755 index 00000000000..32232566acf --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h @@ -0,0 +1,210 @@ +/*! +***************************************************************************** + * @file: startup_ADuCM3029.h + * @brief: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * ADI ADuCxxx Device Series + * @version: $Revision: $ + * @date: $Date: $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/* +WEAK_FUNC(func) + If this is available for a compiler, apply whatever attributes are needed + to a function definition ("func") to flag that the function is a "weak" one. +VECTOR_SECTION + A particular setup may have a requirement that the vector table be placed + in a particular section. This specifies the name of that section +RESET_EXCPT_HNDLR + A particular setup may have a requirement for a different reset handler. + This specifies the name of that handler. +*/ + +#ifndef __STARTUP_H__ +#define __STARTUP_H__ + +#define VECTOR_SECTION ".vectors" + +#ifdef __CC_ARM +extern unsigned Image$$ADUCM_HEAP$$Base[]; +extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[]; +void Default_Handler(void); +#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define IVT_NAME __Vectors +#define RESET_EXCPT_HNDLR __main +#define COMPILER_NAME "ARMCC" +#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); + +#elif defined(__ICCARM__) +#pragma diag_suppress=Pm093,Pm140 +#define SECTION_PLACE(def,sectionname) def @ sectionname +#define IVT_NAME __vector_table +#define WEAK_FUNC(func) __weak func +#define RESET_EXCPT_HNDLR __iar_program_start +#define COMPILER_NAME "ICCARM" +#define WEAK_FUNCTION(x) WEAK_FUNC ( void x (void)) { while(1){} } + +#elif defined(__GNUC__) +extern unsigned __etext; +extern unsigned __data_start__; +extern unsigned __data_end__; +extern unsigned __copy_table_start__; +extern unsigned __copy_table_end__; +extern unsigned __zero_table_start__; +extern unsigned __zero_table_end__; +extern unsigned __bss_start__; +extern unsigned __bss_end__; +extern unsigned __StackTop; +void Default_Handler(void); +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#define RESET_EXCPT_HNDLR _start +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#define RESET_EXCPT_HNDLR __START +#endif +#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define IVT_NAME __Vectors +#define COMPILER_NAME "GNUC" +#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#define __STARTUP_CLEAR_BSS_MULTIPLE +#endif // __GNUC__ +#define LASTCRCPAGE 0 +#define BLANKX4 0xFFFFFFFF +#define BLANKX20 BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4 +#define BLANKX100 BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20 +#define BLANKX600 BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100 +#define BLANKX60 BLANKX20,BLANKX20,BLANKX20 +void RESET_EXCPT_HNDLR(void); +void Reset_Handler(void); +/* IVT typedefs. */ +typedef void( *pFunc )( void ); + +#define ADUCM3029_VECTORS /* Cortex-M3 Exceptions Handler */ \ + Reset_Handler, /* -15 */ \ + NMI_Handler, /* -14 */ \ + HardFault_Handler, /* -13 */ \ + MemManage_Handler, /* -12 */ \ + BusFault_Handler, /* -11 */ \ + UsageFault_Handler, /* -10 */ \ + 0, /* -9 */ \ + 0, /* -8 */ \ + 0, /* -7 */ \ + 0, /* -6 */ \ + SVC_Handler, /* -5 */ \ + DebugMon_Handler, /* -4 */ \ + 0, /* -3 */ \ + PendSV_Handler, /* -2 */ \ + SysTick_Handler, /* -1 */ \ + /* External interrupts */ \ + RTC1_Int_Handler, /* 0 */ \ + Ext_Int0_Handler, /* 1 */ \ + Ext_Int1_Handler, /* 2 */ \ + Ext_Int2_Handler, /* 3 */ \ + Ext_Int3_Handler, /* 4 */ \ + WDog_Tmr_Int_Handler, /* 5 */ \ + Vreg_over_Int_Handler, /* 6 */ \ + Battery_Voltage_Int_Handler, /* 7 */ \ + RTC0_Int_Handler, /* 8 */ \ + GPIO_A_Int_Handler, /* 9 */ \ + GPIO_B_Int_Handler, /* 10 */ \ + GP_Tmr0_Int_Handler, /* 11 */ \ + GP_Tmr1_Int_Handler, /* 12 */ \ + Flash0_Int_Handler, /* 13 */ \ + UART_Int_Handler, /* 14 */ \ + SPI0_Int_Handler, /* 15 */ \ + SPI2_Int_Handler, /* 16 */ \ + I2C0_Slave_Int_Handler, /* 17 */ \ + I2C0_Master_Int_Handler, /* 18 */ \ + DMA_Err_Int_Handler, /* 19 */ \ + DMA_SPI2_TX_Int_Handler, /* 20 */ \ + DMA_SPI2_RX_Int_Handler, /* 21 */ \ + DMA_SPORT0A_Int_Handler, /* 22 */ \ + DMA_SPORT0B_Int_Handler, /* 23 */ \ + DMA_SPI0_TX_Int_Handler, /* 24 */ \ + DMA_SPI0_RX_Int_Handler, /* 25 */ \ + DMA_SPI1_TX_Int_Handler, /* 26 */ \ + DMA_SPI1_RX_Int_Handler, /* 27 */ \ + DMA_UART_TX_Int_Handler, /* 28 */ \ + DMA_UART_RX_Int_Handler, /* 29 */ \ + DMA_I2C0_STX_Int_Handler, /* 30 */ \ + DMA_I2C0_SRX_Int_Handler, /* 31 */ \ + DMA_I2C0_MX_Int_Handler, /* 32 */ \ + DMA_AES0_IN_Int_Handler, /* 33 */ \ + DMA_AES0_OUT_Int_Handler, /* 34 */ \ + DMA_FLASH0_Int_Handler, /* 35 */ \ + SPORT0A_Int_Handler, /* 36 */ \ + SPORT0B_Int_Handler, /* 37 */ \ + Crypto_Int_Handler, /* 38 */ \ + DMA_ADC0_Int_Handler, /* 39 */ \ + GP_Tmr2_Int_Handler, /* 40 */ \ + Crystal_osc_Int_Handler, /* 41 */ \ + SPI1_Int_Handler, /* 42 */ \ + PLL_Int_Handler, /* 43 */ \ + RNG_Int_Handler, /* 44 */ \ + Beep_Int_Handler, /* 45 */ \ + ADC_Int_Handler, /* 46 */ \ + 0, /* 47 */ \ + 0, /* 48 */ \ + 0, /* 49 */ \ + 0, /* 50 */ \ + 0, /* 51 */ \ + 0, /* 52 */ \ + 0, /* 53 */ \ + 0, /* 54 */ \ + 0, /* 55 */ \ + DMA_SIP0_Int_Handler, /* 56 */ \ + DMA_SIP1_Int_Handler, /* 57 */ \ + DMA_SIP2_Int_Handler, /* 58 */ \ + DMA_SIP3_Int_Handler, /* 59 */ \ + DMA_SIP4_Int_Handler, /* 60 */ \ + DMA_SIP5_Int_Handler, /* 61 */ \ + DMA_SIP6_Int_Handler, /* 62 */ \ + DMA_SIP7_Int_Handler, /* 63 */ \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 64 - 79 */ \ + (pFunc)BLANKX4, (pFunc)BLANKX4, /* security_options */ \ + (pFunc)BLANKX4, (pFunc)BLANKX4, \ + (pFunc)0xA79C3203u, (pFunc)LASTCRCPAGE, \ + (pFunc)BLANKX4, (pFunc)BLANKX4 /* 80 - 87 */ + +#endif /* __STARTUP_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c new file mode 100755 index 00000000000..0bfbdfc5eb4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c @@ -0,0 +1,286 @@ +/****************************************************************************** + * @file system_ADuCM3029.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for + * Device ADuCM3029 + * @version V3.10 + * @date 23. November 2012 + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + Portions Copyright (c) 2016 - 2017 Analog Devices, Inc. + ---------------------------------------------------------------------------*/ +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef ADI_DEBUG +/* only needed in debug mode */ +uint32_t lfClock = 0u; /* "lf_clk" coming out of LF mux */ +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/* Note that these variables will be re-initialized to the value set here by the + LIBC startup code, so if other clock values are required, make sure set them + here. +*/ +uint32_t hfClock = __HFOSC; /* "root_clk" output of HF mux */ +uint32_t gpioClock = 0; /* external GPIO clock */ +uint32_t SystemCoreClock = __HFOSC; /*!< System Clock Frequency (Core Clock) */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ + +/*! + * Update the clock. + * + * @param none + * @return none + * + * @brief Updates the variable SystemCoreClock and must be called whenever + * the core clock is changed during program execution. + */ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t val; + uint16_t div2; + float mul2, nDivisor, nMulfactor; + +#ifdef ADI_DEBUG + /* "lfclock" is only used during debug checks... */ + /* LF clock is always 32k, whether osc or xtal */ + lfClock = __LFCLK; /* for beep, wdt and lcd */ + if( lfClock == 0 ) + { + while( 1 ); + } +#endif + + /* Update Core Clock sources */ + /* update the HF clock */ + switch( pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) { + + case HFMUX_INTERNAL_OSC_VAL: + hfClock = __HFOSC; + break; + + case HFMUX_EXTERNAL_XTAL_VAL: + hfClock = __HFXTAL; + break; + + case HFMUX_SYSTEM_SPLL_VAL: + /* Calculate System PLL output frequency */ + if( pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_SPLLIPSEL ) + { + /* PLL input from HFXTAL */ + val = __HFXTAL; + } + else + { + /* PLL input from HFOSC */ + val = __HFOSC; + } + + /* PLL NSEL multiplier */ + nMulfactor = ( ( pADI_CLKG0_CLK->CTL3 &BITM_CLKG_CLK_CTL3_SPLLNSEL ) >> BITP_CLKG_CLK_CTL3_SPLLNSEL ); + + /* PLL MSEL divider */ + nDivisor = ( ( pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL ) >> BITP_CLKG_CLK_CTL3_SPLLMSEL ); + + /* PLL NSEL multiplier */ + div2 = ( ( pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2 ) >> BITP_CLKG_CLK_CTL3_SPLLDIV2 ); + + /* PLL MSEL divider */ + mul2 = ( ( pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2 ) >> BITP_CLKG_CLK_CTL3_SPLLMUL2 ); + + val = ( ( (uint32_t)( ( nMulfactor * ( mul2 + 1.0 ) * (float) val ) / nDivisor ) ) >> div2 ); + + hfClock = val; + break; + + case HFMUX_GPIO_VAL: + hfClock = gpioClock; + break; + + default: + return; + } /* end switch */ + + SystemCoreClock = hfClock; +} + + +/*! + * Configure the SRAM banks + * + * @return none + * + * @brief Setup the SRAM banks. + * Initialize the SRAM configuration and retention. + */ +void SramInit(void) +{ + /* SRAM Bank1 and Banck2 are hibernate-preserved */ + adi_system_EnableRetention(ADI_SRAM_BANK_1, true); + adi_system_EnableRetention(ADI_SRAM_BANK_2, true); + /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */ + adi_system_EnableISRAM(false); + /* To disable the instruction cache */ + adi_system_EnableCache(false); +} + + +/*! + * Initialize the system + * + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the relocate vector table. + */ +void SystemInit (void) +{ + uint32_t IntStatus; + + /* Turn off Tile 3029 LED */ + pADI_GPIO1->OEN |= ADI_GPIO_PIN_10; + pADI_GPIO2->OEN |= ADI_GPIO_PIN_2; + pADI_GPIO1->SET = ADI_GPIO_PIN_10; + pADI_GPIO2->SET = ADI_GPIO_PIN_2; + + IntStatus = __get_PRIMASK(); + __disable_irq(); + + /* Set boot ROM IVT. */ + SCB->VTOR = (uint32_t)NVIC_FLASH_VECTOR_ADDRESS; + + /* Set all three (USGFAULTENA, BUSFAULTENA, and MEMFAULTENA) fault enable bits + * in the System Control Block, System Handler Control and State Register + * otherwise these faults are handled as hard faults. + */ + SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk ; + adi_pwr_Init(); + adi_pwr_SetClockDivider(ADI_CLOCK_HCLK,1); + adi_pwr_SetClockDivider(ADI_CLOCK_PCLK,1); + + /* Set up the LF clock source */ + adi_pwr_SetLFClockMux(ADI_CLOCK_MUX_LFCLK_LFXTAL); + adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFXTAL,true); + + __set_PRIMASK(IntStatus); +} + +/*! + * @brief This enables or disables the cache. + * \n @param bEnable : To specify whether to enable/disable cache. + * \n true : To enable cache. + * \n + * \n false : To disable cache. + * \n + * @return none + * + */ +void adi_system_EnableCache(bool bEnable) +{ + pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY; + if(bEnable) + { + pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN; + } + else + { + pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN; + } +} + +/*! + * @brief This enables or disables instruction SRAM + * + * @param bEnable: To enable/disable the instruction SRAM. + * \n true : To enable cache. + * \n + * \n false : To disable cache. + * \n + * @return none + * @note: Please note that respective linker file need to support the configuration. + */ +void adi_system_EnableISRAM(bool bEnable) +{ + + if(bEnable) + { + pADI_PMG0_TST->SRAM_CTL |= BITM_PMG_TST_SRAM_CTL_INSTREN; + } + else + { + pADI_PMG0_TST->SRAM_CTL &= ~BITM_PMG_TST_SRAM_CTL_INSTREN; + } +} + +/*! + * @brief This enables/disable SRAM retention during the hibernation. + * @param eBank: Specify which SRAM bank. Only BANK1 and BANK2 are valid. + * @param bEnable: To enable/disable the retention for specified SRAM bank. + * \n true : To enable retention during the hibernation. + * \n + * \n false :To disable retention during the hibernation. + * \n + * @return : SUCCESS : Configured successfully. + * FAILURE : For invalid bank. + * @note: Please note that respective linker file need to support the configuration. Only BANK-1 and + BANK-2 of SRAM is valid. + */ +uint32_t adi_system_EnableRetention(ADI_SRAM_BANK eBank,bool bEnable) +{ +#ifdef ADI_DEBUG + if((eBank != ADI_SRAM_BANK_1) && (eBank != ADI_SRAM_BANK_2)) + { + return FAILURE; + } +#endif + pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY; + if(bEnable) + { + pADI_PMG0->SRAMRET |= (uint32_t)eBank>>1; + } + else + { + pADI_PMG0->SRAMRET &= ~((uint32_t)eBank >> 1); + } + + return SUCCESS; +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct new file mode 100755 index 00000000000..f7087cac097 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct @@ -0,0 +1,65 @@ +;****************************************************************************** +; File: ADuCM3029.sct +; Scatter loading file for Analog Devices ADuCM3029 processor +; +; Copyright (c) 2011 - 2014 ARM LIMITED +; Copyright (c) 2016 - 2017 Analog Devices, Inc. +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; +; Portions Copyright (c) 2017 Analog Devices, Inc. +; +;****************************************************************************** + +LR_IROM1 0x00000000 0x00040000 { + ADUCM_IROM1 0x00000000 0x00040000 { ; romflash start address + *(.vectors, +First) + *(.checksum) + *(InRoot$$Sections) + .ANY (+RO) + } + + RW_IRAM1 0x20000200 { ; data section + .ANY (+RW) + } + + ADUCM_HEAP AlignExpr(+0, 16) EMPTY + (0x20003000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; heap + } + + ADUCM_STACK AlignExpr(+0, 16) EMPTY 0x1000 { ; stack + } + + ADUCM_IRAM2 0x20004000 0x4000 { ; bss section + .ANY (+RW +ZI) + } + + ADUCM_IRAM3 0x20040000 0x8000 { ; non-retainable memory region + .ANY (+RW +ZI) + } +} + +ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20002000) + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld new file mode 100755 index 00000000000..23208ce7cd7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld @@ -0,0 +1,225 @@ +/* + * Portions Copyright (c) 2016 - 2017 Analog Devices, Inc. + * + * Based on Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld file in + * ARM.CMSIS.4.5.0.pack. + */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + /* Flash bank0 */ + FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800 + /* Flash bank0 - bank127*/ + FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 256k - 0x800 + /* SRAM bank 0+1 */ + DSRAM_V (rwx) : ORIGIN = 0x20000000, LENGTH = 0x200 + DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 16k - 0x200 + DSRAM_C (rwx) : ORIGIN = 0x20004000, LENGTH = 16k + /* SRAM bank 3 */ + DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 32k +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) +/* Custom stack and heap sizes */ +__stack_size__ = 0x1000; +__heap_size__ = 0x2000; + +/* select custom or default sizes for stack and heap */ +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0C00; + +/* Linker script to place sections and symbol values. + * It references the following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines the following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + KEEP(*(.checksum)) + } > FLASH0 + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > DSRAM_A + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + KEEP(*(.bss.gChannelControlDataArray)) + KEEP(*(.bss.thread_stack_main)) + KEEP(*(.bss.UartDeviceMem)) + KEEP(*(.bss.os_thread_def_stack_event_loop_thread)) + *(COMMON) + *(.bss) + . = ALIGN(4); + __bss_end__ = .; + } > DSRAM_C + + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss*) + . = ALIGN(4); + __bss2_end__ = .; + } > DSRAM_B + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + . += HEAP_SIZE; + __HeapLimit = .; + } > DSRAM_A + + /* Set stack top to end of DSRAM_A, and move stack limit down by + * size of stack_dummy section */ + __StackTop = ORIGIN(DSRAM_C); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds DSRAM_A limit when they are both in DSRAM_A + ASSERT(__StackLimit >= __HeapLimit, "region DSRAM_A overflowed with stack") */ +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf new file mode 100755 index 00000000000..8c15cd0b5c3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf @@ -0,0 +1,49 @@ +/****************************************************************************** +* File: ADuCM3029.icf +* ILINK Configuration File for Analog Devices ADuCM3029 processor +* +* Copyright (c) 2011 - 2014 ARM LIMITED +* Copyright (c) 2016 - 2017 Analog Devices, Inc. +* +* All rights reserved. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* - Neither the name of ARM nor the names of its contributors may be used +* to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ +define memory mem with size = 4G; +define region ROM_PAGE0_INTVEC = mem:[from 0x00000000 size 0x000001A0]; +define region ROM_PAGE0_CHECKSUM = mem:[from 0x000001A0 size 0x00000660]; +define region ROM_REGION = mem:[from 0x00000800 size 254K]; +define region RAM_bank1_region = mem:[from 0x20000200 size 0x00003E00]; +define region RAM_bank2_region = mem:[from 0x20004000 size 0x00004000] + | mem:[from 0x20040000 size 0x00008000]; +define block CSTACK with alignment = 16, size = 0x1000 { }; +define block HEAP with alignment = 16, size = 0x2000 { }; +do not initialize { section .noinit }; +initialize by copy { rw }; +place at start of ROM_PAGE0_INTVEC { ro section .vectors }; +place in ROM_PAGE0_CHECKSUM { ro section .checksum }; +place in ROM_REGION { ro }; +place at end of RAM_bank1_region { block CSTACK }; +place in RAM_bank1_region { rw section .data }; +place in RAM_bank1_region { block HEAP }; +place in RAM_bank2_region { rw }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralNames.h new file mode 100755 index 00000000000..c1cfd6c14ae --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralNames.h @@ -0,0 +1,136 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + // could be 4 or could be 3... not sure what register + // this is for... too much abstraction + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +typedef enum { + ADC0_VIN0 = 0, + ADC0_VIN1 = 1, + ADC0_VIN2 = 2, + ADC0_VIN3 = 3, + ADC0_VIN4 = 4, + ADC0_VIN5 = 5, + ADC0_VIN6 = 6, + ADC0_VIN7 = 7 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.c new file mode 100755 index 00000000000..80df8caa617 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.c @@ -0,0 +1,111 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "PeripheralPins.h" + + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_10, UART_0, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_11, UART_0, 1}, + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P0_00, SPI_0, 1}, + {P1_06, SPI_1, 1}, + {P1_02, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P0_01, SPI_0, 1}, + {P1_07, SPI_1, 1}, + {P1_03, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P0_02, SPI_0, 1}, + {P1_08, SPI_1, 1}, + {P1_04, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P0_03, SPI_0, 1}, + {P1_09, SPI_1, 1}, + {P2_10, SPI_2, 1}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P2_03, ADC0_VIN0, 1}, + {P2_04, ADC0_VIN1, 1}, + {P2_05, ADC0_VIN2, 1}, + {P2_06, ADC0_VIN3, 1}, + {P2_07, ADC0_VIN4, 1}, + {P2_08, ADC0_VIN5, 1}, + {P2_09, ADC0_VIN6, 1}, + {P2_10, ADC0_VIN7, 1}, + {NC, NC, 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_05, I2C_0, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_04, I2C_0, 1}, + {NC, NC, 0} +}; + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.h new file mode 100755 index 00000000000..40ef7f85b12 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/PeripheralPins.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c new file mode 100755 index 00000000000..91905d61bd5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/analogin_api.c @@ -0,0 +1,227 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "adi_adc_def.h" +#include "pinmap.h" +#include "PeripheralPins.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +/* ADC Device number */ +#define ADC_DEV_NUM (0u) + +/* Memory Required for adc driver */ +static uint32_t DeviceMemory[(ADI_ADC_MEMORY_SIZE+3)/4]; +/* Active channel */ +static uint32_t adi_pin2channel(PinName pin); + +/** + * \defgroup hal_analogin Analogin hal functions + * @{ + */ + +/** Initialize the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param pin The analogin pin name + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + ADI_ADC_HANDLE hDevice; + bool bCalibrationDone = false; + bool bReady = false; + + ADCName peripheral; + uint32_t function, channel; + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + MBED_ASSERT(peripheral != (ADCName)NC); + + /* verify read function */ + function = pinmap_function(pin, &PinMap_ADC[0]); + MBED_ASSERT(function == 1); + + /* Configure PORT2_MUX registers */ + pin_function(pin, function); + + /* Configure active channel */ + channel = adi_pin2channel(pin); + MBED_ASSERT(channel != 0xFFFFFFFF); + obj->UserBuffer.nChannels = channel; + + /* Set ACLK to CCLK/16 */ + adi_pwr_SetClockDivider(ADI_CLOCK_ACLK,16); + + /* Set default values for conversion and delay cycles. This sets up a sampling rate of + 16kHz. The sampling frequency is worked out from the following: + + if delay time > 0: + Fs = ACLK / [((14 + sampling time) * oversample factor) + (delay time + 2)] + if delay time = 0: + Fs = ACLK / ((14 + sampling time) * oversample factor) + + The sampling (or acquisition) and delay times are in number of ACLK clock cycles. + */ + obj->DelayCycles = 0; + obj->SampleCycles = 88; + + /* Open the ADC device */ + adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice); + obj->hDevice = hDevice; + + /* Power up ADC */ + adi_adc_PowerUp(hDevice, true); + + /* Set ADC reference */ + adi_adc_SetVrefSource(hDevice, ADI_ADC_VREF_SRC_INT_2_50_V); + + /* Enable ADC sub system */ + adi_adc_EnableADCSubSystem(hDevice, true); + + /* Wait untilthe ADC is ready for sampling */ + while(bReady == false) { + adi_adc_IsReady(hDevice, &bReady); + } + + /* Start calibration */ + adi_adc_StartCalibration(hDevice); + + /* Wait until calibration is done */ + while (!bCalibrationDone) { + adi_adc_IsCalibrationDone(hDevice, &bCalibrationDone); + } + + /* Set the delay time */ + adi_adc_SetDelayTime(hDevice, obj->DelayCycles); + + /* Set the acquisition time. (Application need to change it based on the impedence) */ + adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles); +} + +/** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @param obj The analogin object + * @return A floating value representing the current input voltage + */ +float analogin_read(analogin_t *obj) +{ + float fl32 = (float)analogin_read_u16(obj)/(float)4095.0; + + return(fl32); +} + +/** Read the value from analogin pin, represented as an unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16bit value representing the current input voltage + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + ADI_ADC_HANDLE hDevice = obj->hDevice; + ADI_ADC_BUFFER *pAdcBuffer; + + /* Submit the buffer to the driver */ + adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); + + /* Enable the ADC */ + adi_adc_Enable(hDevice, true); + + adi_adc_GetBuffer(hDevice, &pAdcBuffer); + MBED_ASSERT(pAdcBuffer == &obj->UserBuffer); + + return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); +} + +/* Retrieve te active channel correspondoing to the input pin */ +static uint32_t adi_pin2channel(PinName pin) { + + uint32_t activech; + + switch(pin) { + case ADC_VIN0: + activech = ADI_ADC_CHANNEL_0; + break; + case ADC_VIN1: + activech = ADI_ADC_CHANNEL_1; + break; + case ADC_VIN2: + activech = ADI_ADC_CHANNEL_2; + break; + case ADC_VIN3: + activech = ADI_ADC_CHANNEL_3; + break; + case ADC_VIN4: + activech = ADI_ADC_CHANNEL_4; + break; + case ADC_VIN5: + activech = ADI_ADC_CHANNEL_5; + break; + case ADC_VIN6: + activech = ADI_ADC_CHANNEL_6; + break; + case ADC_VIN7: + activech = ADI_ADC_CHANNEL_7; + break; + default: + activech = (uint32_t) 0xFFFFFFFF; + break; + } + + return ((uint32_t)activech); +} + + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif // #if DEVICE_ANALOGIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis.h new file mode 100755 index 00000000000..b0439b1db09 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H +#define __C +#include "adi_processor.h" +#include "cmsis_nvic.h" +#undef __C +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h new file mode 100755 index 00000000000..8310b5fbbea --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h @@ -0,0 +1,78 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_USER_IRQ_OFFSET 16 +#define NVIC_USER_IRQ_NUMBER 64 +#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) + +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 +#define NVIC_FLASH_VECTOR_ADDRESS 0x0 + +#ifdef __cplusplus +extern "C" { +#endif + +/** Set the ISR for IRQn + * + * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM + * the first time this function is called + * @param[in] IRQn The Interrupt Request number for which a vector will be registered + * @param[in] vector The ISR vector to register for IRQn + */ +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); + +/** Get the ISR registered for IRQn + * + * Reads the Interrupt Service Routine currently registered for IRQn + * @param[in] IRQn The Interrupt Request number the vector of which will be read + * @return Returns the ISR registered for IRQn + */ +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/device.h new file mode 100755 index 00000000000..0d46738ec1a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/device.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c new file mode 100755 index 00000000000..feae0e3d982 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c @@ -0,0 +1,91 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifdef DEVICE_FLASH +#include "flash_api.h" +#include "flash_data.h" +#include "mbed_critical.h" + +// This file is automagically generated + +// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM + +static unsigned FLASH_ALGO[] = { + 0x2000B508,0x4A5B1E41,0x495B6011,0x21076211,0xBF006091,0x68094957,0x99009100,0x0104F001, + 0xD0F72900,0xF0019900,0xB1010130,0x21002001,0x62114A50,0xB5F0BD08,0x460F4606,0x4D4D4614, + 0x20013554,0x20007028,0x6048494A,0xD1072C01,0x6D004608,0x0001F000,0xF7FFB110,0xBDF0FFD1, + 0xE7FC2000,0x20004601,0x62104A42,0xB5084770,0x20004601,0x4B3F1E42,0x461A601A,0x4A3E6191, + 0x2206621A,0xBF00609A,0x68124A3A,0x9A009200,0x0204F002,0xD0F72A00,0xF0029A00,0xB1020230, + 0x22002001,0x621A4B33,0xB5FEBD08,0x460B4604,0x46252600,0x48304611,0x62384F2E,0xF04FE052, + 0x4F2C30FF,0x2B086038,0x6808D304,0x68486138,0xE02F6178,0x3CFFF04F,0xC000F8CD,0xC004F8CD, + 0x2B084668,0xE8DFD21A,0x1619F003,0x0A0D1013,0x798F0407,0xBF007187,0x7147794F,0x790FBF00, + 0xBF007107,0x70C778CF,0x788FBF00,0xBF007087,0x7047784F,0x780FBF00,0xE0007007,0xBF00BF00, + 0xC050F8DF,0xF8CC9F00,0x9F017010,0x7014F8CC,0xBF002308,0x60C5480F,0x4F0E2004,0x463860B8, + 0xF0006800,0xB1080030,0xE00D2601,0x4809BF00,0x90026800,0xF0009802,0x28000004,0x3B08D0F7, + 0x35083108,0xD1AA2B00,0x2000BF00,0x62384F01,0xBDFE4630,0x40018000,0x676C7565,0 +}; + +static const flash_algo_t flash_algo_config = { + .init = 0x00000037, + .uninit = 0x00000065, + .erase_sector = 0x0000006F, + .program_page = 0x000000AB, + .static_base = 0x0000017C, + .algo_blob = FLASH_ALGO +}; + +static const sector_info_t sectors_info[] = { + {0x0, 0x800}, +}; + +static const flash_target_config_t flash_target_config = { + .page_size = 0x800, + .flash_start = 0x0, + .flash_size = 0x00040000, + .sectors = sectors_info, + .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) +}; + +void flash_set_target_config(flash_t *obj) +{ + obj->flash_algo = &flash_algo_config; + obj->target_config = &flash_target_config; +} +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c new file mode 100755 index 00000000000..fdaa7d603c2 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_api.c @@ -0,0 +1,147 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "adi_gpio.h" + + +#define MUX_FUNC_0 0x0 +#define NUM_GPIO_PORTS 4 + +extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +extern uint8_t gpio_initialized; + +static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0}; +static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0}; + + +/****************************************************************************** + Function definitions + *****************************************************************************/ +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_num = pin & 0xFF; + + pin_function(pin, MUX_FUNC_0); + + return (1 << pin_num); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + if (pin == (PinName)NC) { + return; + } + + // Initialize the GPIO driver. This function + // initializes the GPIO driver only once globally. + if (!gpio_initialized) { + adi_gpio_Init(gpioMemory, ADI_GPIO_MEMORY_SIZE); + } + + pin_function(pin, MUX_FUNC_0); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + uint32_t pin = obj->pin; + + pin_mode((PinName)pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + + if (direction == PIN_OUTPUT) { + adi_gpio_OutputEnable(port, 1 << pin_num, true); + // save the input/output configuration + gpio_oen[port] |= (1 << pin_num); + } else { + adi_gpio_InputEnable(port, 1 << pin_num, true); + // save the input/output configuration + gpio_oen[port] &= (~(1 << pin_num)); + } +} + +void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + + if (value & 1) { + adi_gpio_SetHigh(port, (1 << pin_num)); + + // save the output port value + gpio_output_val[port] |= ((value & 1) << pin_num); + } else { + adi_gpio_SetLow(port, (1 << pin_num)); + + // save the output port value + gpio_output_val[port] &= (~(1 << pin_num)); + } +} + + +int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + uint16_t Data; + + // check whether the pin is configured as input or output + if ((gpio_oen[port] >> pin_num) & 1) { + Data = gpio_output_val[port] & (1 << pin_num); + } else { + // otherwise call GetData + adi_gpio_GetData(port, (1 << pin_num), &Data); + } + + return ((((uint32_t)Data) >> pin_num) & 1); +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c new file mode 100755 index 00000000000..5e0d99ad8b0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_dev_mem.c @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include + +// ADI GPIO device driver state memory. Only one state memory is required globally. +uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; + +// Flag to indicate whether the GPIO driver has been initialized +uint8_t gpio_initialized = 0; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c new file mode 100755 index 00000000000..ea62c3d3bae --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_irq_api.c @@ -0,0 +1,327 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "gpio_irq_api.h" +#include "adi_gpio.h" +#include "adi_gpio_def.h" +#include "ADuCM302x_device.h" + +#ifdef DEVICE_INTERRUPTIN + +#define MAX_GPIO_LINES 16 +#define MAX_GPIO_PORTS ADI_GPIO_NUM_PORTS + +typedef struct { + unsigned int id; + gpio_irq_event event; + uint8_t int_enable; +} gpio_chan_info_t; + +extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +extern uint8_t gpio_initialized; +static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; +static gpio_irq_handler irq_handler = NULL; + + +/** Local interrupt callback routine. + */ +static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg) +{ + uint16_t pin = *(ADI_GPIO_DATA*)pArg; + int index = 0; + + // determine the index of the pin that caused the interrupt + while (pin) { + if (pin & 0x01) { + // call the user ISR. The argument Event is the port number of the GPIO line. + if (irq_handler != NULL) + irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event); + } + index++; + pin >>= 1; + } +} + + +/** Function to get the IENA and IENB register values. + * Added here temporarily until these are available in the BSP + */ +static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPins(const ADI_GPIO_PORT Port, const IRQn_Type eIrq, + const ADI_GPIO_DATA Pins, uint16_t* const pValue) +{ + ADI_GPIO_TypeDef *pReg[MAX_GPIO_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2}; + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + uint16_t Value = 0u; + + pPort = pReg[Port]; + + switch (eIrq) { + case SYS_GPIO_INTA_IRQn: + Value = pPort->IENA; + break; + case SYS_GPIO_INTB_IRQn: + Value = pPort->IENB; + break; + default: + break; /* This shall never reach */ + } + + *pValue = (Value & Pins); + return (ADI_GPIO_SUCCESS); +} + + +/** Function to get the interrupt polarity register content. + * Added here temporarily until these are available in the BSP + */ +static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, + uint16_t* const pValue) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_GPIO_TypeDef *pReg[MAX_GPIO_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2}; + + pPort = pReg[Port]; + + *pValue = (pPort->POL & Pins); + + return (ADI_GPIO_SUCCESS); +} + + +/** Function to clear the relevant interrupt enable bits in both the IENA and IENB registers + * for the given GPIO pin. + */ +static void disable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number) +{ + uint16_t int_reg_val; + + // Read the current content of the IENA register + adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, 1 << pin_number, &int_reg_val); + + // clear the bit for the pin + int_reg_val &= ~(1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, int_reg_val); + + // Do the same to IENB + adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, 1 << pin_number, &int_reg_val); + + // clear the bit for the pin + int_reg_val &= ~(1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, int_reg_val); +} + + +/** Function to set the relevant interrupt enable bits in either the IENA and IENB registers + * for the given GPIO pin. + */ +static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_Type eIrq) +{ + uint16_t int_reg_val; + + // Read the current interrupt enable register content + adi_gpio_GetGroupInterruptPins(port, eIrq, 1 << pin_number, &int_reg_val); + + // set the bit for the pin + int_reg_val |= (1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, eIrq, int_reg_val); +} + + +/** Initialize the GPIO IRQ pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin name + * @param handler The handler to be attached to GPIO IRQ + * @param id The object ID (id != 0, 0 is reserved) + * @return -1 if pin is NC, 0 otherwise + */ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint32_t port = pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = pin & 0xFF; + + // check for valid pin and ID + if ((pin == NC) || (id == 0)) { + return -1; + } + + // make sure gpio driver has been initialized + if (!gpio_initialized) { + adi_gpio_Init(gpioMemory,ADI_GPIO_MEMORY_SIZE); + gpio_initialized = 1; + } + + // save the handler + if (handler) { + irq_handler = handler; + } + + // disable the interrupt for the given pin + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + + // set the port pin as input + adi_gpio_InputEnable(port, 1 << pin_num, true); + + // save the ID for future reference + channel_ids[port][pin_num].id = (uint32_t)id; + channel_ids[port][pin_num].event = IRQ_NONE; + channel_ids[port][pin_num].int_enable = 0; + obj->id = id; + obj->pinname = pin; + + return 0; +} + +/** Release the GPIO IRQ PIN + * + * @param obj The gpio object + */ +void gpio_irq_free(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + // disable interrupt for the given pin + gpio_irq_disable(obj); + + // clear the status table + channel_ids[port][pin_num].id = (uint32_t)0; + channel_ids[port][pin_num].event = IRQ_NONE; + channel_ids[port][pin_num].int_enable = 0; +} + +/** Enable/disable pin IRQ event + * + * @param obj The GPIO object + * @param event The GPIO IRQ event + * @param enable The enable flag + */ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint16_t int_polarity_reg; + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (event == IRQ_NONE) { + return; + } + + // read the current polarity register + adi_gpio_GetGroupInterruptPolarity((ADI_GPIO_PORT)port, 1 << pin_num, &int_polarity_reg); + + if (event == IRQ_RISE) { + int_polarity_reg |= (1 << pin_num); + } else { + int_polarity_reg &= ~(1 << pin_num); + } + + // set the polarity register + adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg); + + channel_ids[port][pin_num].event = event; + + // enable interrupt for this pin if enable flag is set + if (enable) { + gpio_irq_enable(obj); + } else { + gpio_irq_disable(obj); + } +} + +/** Enable GPIO IRQ + * + * This is target dependent, as it might enable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_enable(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (channel_ids[port][pin_num].event == IRQ_NONE) { + return; + } + + // Group all RISE interrupts in INTA and FALL interrupts in INTB + if (channel_ids[port][pin_num].event == IRQ_RISE) { + // set the callback routine + adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj); + enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn); + } else if (channel_ids[port][pin_num].event == IRQ_FALL) { + // set the callback routine + adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj); + enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn); + } + + channel_ids[port][pin_num].int_enable = 1; +} + +/** Disable GPIO IRQ + * + * This is target dependent, as it might disable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_disable(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (channel_ids[port][pin_num].event == IRQ_NONE) { + return; + } + + // Group all RISE interrupts in INTA and FALL interrupts in INTB + if (channel_ids[port][pin_num].event == IRQ_RISE) { + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + } + else if (channel_ids[port][pin_num].event == IRQ_FALL) { + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + } + + channel_ids[port][pin_num].int_enable = 0; +} + +#endif // #ifdef DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_object.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_object.h new file mode 100755 index 00000000000..8d59616b7f7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/gpio_object.h @@ -0,0 +1,61 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; +} gpio_t; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c new file mode 100755 index 00000000000..7f0b1c09837 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/i2c_api.c @@ -0,0 +1,220 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "drivers/i2c/adi_i2c.h" + + + +#if defined(BUILD_I2C_MI_DYNAMIC) +#if defined(ADI_DEBUG) +#warning "BUILD_I2C_MI_DYNAMIC is defined. Memory allocation for I2C will be dynamic" +int adi_i2c_memtype = 0; +#endif +#else +static uint8_t i2c_Mem[ADI_I2C_MEMORY_SIZE]; +static ADI_I2C_HANDLE i2c_Handle; +#if defined(ADI_DEBUG) +#warning "BUILD_I2C_MI_DYNAMIC is NOT defined. Memory allocation for I2C will be static" +int adi_i2c_memtype = 1; +#endif +#endif + + + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + ADI_I2C_HANDLE *pI2C_Handle; + uint8_t *I2C_Mem; + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + uint32_t I2C_DevNum = I2C_0; /* ADuCM3029 only has 1 I2C port */ + + +#if defined(BUILD_I2C_MI_DYNAMIC) + I2C_DevNum = I2C_0; + pI2C_Handle = &obj->I2C_Handle; + obj->pI2C_Handle = pI2C_Handle; + I2C_Mem = obj->I2C_Mem; +#else + I2C_DevNum = I2C_0; + pI2C_Handle = &i2c_Handle; + obj->pI2C_Handle = pI2C_Handle; + I2C_Mem = &i2c_Mem[0]; +#endif + + + obj->instance = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->instance != NC); + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + SystemCoreClockUpdate(); + I2C_Return = adi_i2c_Open(I2C_DevNum, I2C_Mem, ADI_I2C_MEMORY_SIZE, pI2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } + I2C_Return = adi_i2c_Reset(*pI2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_start(i2c_t *obj) +{ + /* The Hardware does not support this feature. */ + return -1; +} + + +int i2c_stop(i2c_t *obj) +{ + /* The Hardware does not support this feature. */ + return -1; +} + + +void i2c_frequency(i2c_t *obj, int hz) +{ + ADI_I2C_HANDLE I2C_Handle; + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetBitRate(I2C_Handle, (uint32_t) hz); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + ADI_I2C_RESULT I2C_Return; + ADI_I2C_TRANSACTION I2C_inst; + uint8_t I2C_PrologueData = 0x00; + uint32_t I2C_Errors; /* HW Error result */ + ADI_I2C_HANDLE I2C_Handle; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF)); + I2C_inst.pPrologue = &I2C_PrologueData; + I2C_inst.nPrologueSize = 0; + I2C_inst.pData = (uint8_t*) data; + I2C_inst.nDataSize = length; + I2C_inst.bReadNotWrite = true; + I2C_inst.bRepeatStart = stop; + I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return -1; + } else { + return length; + } +} + + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + ADI_I2C_TRANSACTION I2C_inst; + uint8_t I2C_PrologueData = 0x00; + uint32_t I2C_Errors; /* HW Error result */ + ADI_I2C_HANDLE I2C_Handle; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF)); + I2C_inst.pPrologue = &I2C_PrologueData; + I2C_inst.nPrologueSize = 0; + I2C_inst.pData = (uint8_t*) data; + I2C_inst.nDataSize = length; + I2C_inst.bReadNotWrite = false; + I2C_inst.bRepeatStart = stop; + I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return -1; + } else { + return length; + } +} + + +void i2c_reset(i2c_t *obj) +{ + ADI_I2C_RESULT I2C_Return; + ADI_I2C_HANDLE I2C_Handle = *obj->pI2C_Handle; + + I2C_Return = adi_i2c_Reset(I2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_byte_read(i2c_t *obj, int last) +{ + /* The Hardware does not support this feature. */ + return -1; +} + + +int i2c_byte_write(i2c_t *obj, int data) +{ + /* The Hardware does not support this feature. */ + return -1; +} + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h new file mode 100755 index 00000000000..d57a3b21ded --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/objects.h @@ -0,0 +1,111 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "adi_adc.h" +#include "adi_rng.h" + +#include "adi_i2c.h" +#include "adi_spi.h" +#ifdef __cplusplus +extern "C" { +#endif + +/* Add your custom header content here */ +struct gpio_irq_s { + unsigned int id; + PinName pinname; +}; + +struct sleep_s { + int temp; +}; + +struct serial_s { + int index; +}; + +struct trng_s { + ADI_RNG_HANDLE RNGhDevice; +}; + +#define BUILD_I2C_MI_DYNAMIC +struct i2c_s { + uint32_t instance; + uint32_t error; + ADI_I2C_HANDLE *pI2C_Handle; +#if defined(BUILD_I2C_MI_DYNAMIC) + ADI_I2C_HANDLE I2C_Handle; + uint8_t I2C_Mem[ADI_I2C_MEMORY_SIZE]; +#endif +}; + +#define BUILD_SPI_MI_DYNAMIC +struct spi_s { + uint32_t instance; + uint32_t error; + ADI_SPI_HANDLE *pSPI_Handle; +#if defined(BUILD_SPI_MI_DYNAMIC) + ADI_SPI_HANDLE SPI_Handle; + uint8_t SPI_Mem[ADI_SPI_MEMORY_SIZE]; +#endif +}; + +struct analogin_s { + ADI_ADC_HANDLE hDevice; + ADI_ADC_BUFFER UserBuffer; + uint8_t DelayCycles; + uint8_t SampleCycles; +}; + +#include "gpio_object.h" + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/pinmap.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/pinmap.c new file mode 100755 index 00000000000..eed31f176e7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/pinmap.c @@ -0,0 +1,105 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +#include "PinNames.h" +#include "adi_gpio.h" + +void pin_function(PinName pin, int function) +{ + // pin is composed of port and pin + // function is the function number (the mux selection number shifted by the pin value + // and written to pin mux register, each pin mux takes 2 bits hence multiplying by 2) + + MBED_ASSERT(pin != (PinName)NC); + + uint8_t port = pin >> GPIO_PORT_SHIFT; + uint32_t cfg_reg, mask; + volatile uint32_t *pGPIO_CFG; + + switch (port) { + case 0: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO0_CFG; + break; + case 1: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO1_CFG; + break; + case 2: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO2_CFG; + break; + + default: + return; + } + + cfg_reg = *pGPIO_CFG; + // clear the corresponding 2 bit field first before writing the function + // bits + mask = ~(3 << (pin * 2)); + cfg_reg = (cfg_reg & mask) | (function << (pin*2)); + *pGPIO_CFG = cfg_reg; +} + +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + + uint8_t port = pin >> GPIO_PORT_SHIFT; + uint32_t pin_reg_value = 2 ^ (0xFF & pin); + + switch (mode) { + case PullNone: + adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA)pin_reg_value,false); + break; + + case PullDown: + case PullUp: + adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA)pin_reg_value,true); + break; + + default: + break; + + } + +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c new file mode 100755 index 00000000000..a1d6c95243c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/rtc_api.c @@ -0,0 +1,93 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "adi_rtc.h" +#include "adi_pwr.h" + +#define RTC_DEVICE_NUM 0 +static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE]; +static ADI_RTC_HANDLE hDevice0 = NULL; + + +void rtc_init(void) +{ + /* initialize driver */ + adi_rtc_Open(RTC_DEVICE_NUM,aRtcDevMem0,ADI_RTC_MEMORY_SIZE,&hDevice0); + + adi_rtc_Enable(hDevice0, true); +} + +void rtc_free(void) +{ + adi_rtc_Close(hDevice0); +} + +/* + * Little check routine to see if the RTC has been enabled + * 0 = Disabled, 1 = Enabled + */ +int rtc_isenabled(void) +{ + uint32_t ControlReg; + + adi_rtc_GetControl (hDevice0, ADI_RTC_CONTROL_REGISTER_0,&ControlReg); + + return((int) (ControlReg & BITM_RTC_CR0_CNTEN)); +} + +time_t rtc_read(void) +{ + time_t currentCount; + + adi_rtc_GetCount(hDevice0, (uint32_t *)(¤tCount)); + + return(currentCount); +} + +void rtc_write(time_t t) +{ + adi_rtc_SetCount (hDevice0, t); +} + +#endif // #if DEVICE_RTC diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c new file mode 100755 index 00000000000..f54b390f713 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/serial_api.c @@ -0,0 +1,295 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "drivers/uart/adi_uart.h" + +#define ADI_UART_MEMORY_SIZE (ADI_UART_BIDIR_MEMORY_SIZE) + +static ADI_UART_HANDLE hDevice; +static uint32_t UartDeviceMem[(ADI_UART_MEMORY_SIZE + 3)/4]; +static uint32_t serial_irq_ids[2] = {0}; +static uart_irq_handler irq_handler = NULL; +int stdio_uart_inited = 0; +serial_t stdio_uart; +static int rxbuffer[1]; +static int txbuffer[1]; + +static void uart_callback(void *pCBParam, uint32_t Event, void *pArg) +{ + MBED_ASSERT(irq_handler); + + if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + irq_handler(serial_irq_ids[0], TxIrq); + else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED) + irq_handler(serial_irq_ids[0], RxIrq); +} + + +void serial_free(serial_t *obj) +{ + adi_uart_Close(hDevice); +} + +void serial_baud(serial_t *obj, int baudrate) +{ + uint32_t uartdivc,uartdivm,uartdivn,uartosr; + switch (baudrate) { + default: + case 9600: + uartdivc= 22; + uartdivm= 3; + uartdivn= 1734; + uartosr= 3; + break; + case 19200: + uartdivc= 11; + uartdivm= 3; + uartdivn= 1735; + uartosr= 3; + break; + case 38400: + uartdivc= 17; + uartdivm= 1; + uartdivn= 0501; + uartosr= 3; + break; + case 57600: + uartdivc= 07; + uartdivm= 2; + uartdivn= 0031; + uartosr= 3; + break; + case 115200: + uartdivc= 07; + uartdivm= 2; + uartdivn= 0031; + uartosr= 2; + break; + case 230400: + uartdivc= 07; + uartdivm= 2; + uartdivn= 0031; + uartosr= 1; + break; + case 460800: + uartdivc= 07; + uartdivm= 2; + uartdivn= 0031; + uartosr= 0; + break; + case 921600: + uartdivc= 01; + uartdivm= 1; + uartdivn= 1563; + uartosr= 2; + break; + case 1000000: + uartdivc= 01; + uartdivm= 1; + uartdivn= 1280; + uartosr= 2; + break; + case 1500000: + uartdivc= 01; + uartdivm= 2; + uartdivn= 0341; + uartosr= 1; + break; + case 3000000: + uartdivc= 01; + uartdivm= 2; + uartdivn= 0341; + uartosr= 0; + break; + case 4000000: + uartdivc= 01; + uartdivm= 1; + uartdivn= 1280; + uartosr= 0; + break; + case 5000000: + uartdivc= 01; + uartdivm= 1; + uartdivn= 0614; + uartosr= 0; + break; + case 6000000: + uartdivc= 01; + uartdivm= 1; + uartdivn= 0171; + uartosr= 0; + break; + case 6500000: + uartdivc= 01; + uartdivm= 1; + uartdivn= 0000; + uartosr= 0; + break; + } + adi_uart_ConfigBaudRate(hDevice,uartdivc,uartdivm,uartdivn,uartosr); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + int convertedparity = ADI_UART_NO_PARITY; + int convertedstopbits = ADI_UART_ONE_STOPBIT; + + if (stop_bits) + convertedstopbits = ADI_UART_ONE_AND_HALF_TWO_STOPBITS; + + if (parity == ParityOdd) + convertedparity = ADI_UART_ODD_PARITY; + else if (parity == ParityEven) + convertedparity = ADI_UART_EVEN_PARITY; + else if (parity == ParityForced1) + convertedparity = ADI_UART_ODD_PARITY_STICKY; + else if (parity == ParityForced0) + convertedparity = ADI_UART_EVEN_PARITY_STICKY; + + adi_uart_SetConfiguration(hDevice,convertedparity,convertedstopbits, (data_bits - 5)); +} + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + + adi_uart_Open(0,ADI_UART_DIR_BIDIRECTION,UartDeviceMem,ADI_UART_MEMORY_SIZE,&hDevice); + + serial_baud(obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +int serial_getc(serial_t *obj) +{ + void *pBuff; + uint32_t hw_error; + + adi_uart_SubmitRxBuffer(hDevice, rxbuffer, 1, true); + adi_uart_GetRxBuffer(hDevice, &pBuff, &hw_error); + return rxbuffer[0]; +} + +void serial_putc(serial_t *obj, int c) +{ + void *pBuff; + uint32_t hw_error; + + txbuffer[0] = c; + adi_uart_SubmitTxBuffer(hDevice,txbuffer, 1, true); + adi_uart_GetTxBuffer(hDevice, &pBuff, &hw_error); + return; +} + +int serial_readable(serial_t *obj) +{ + bool bAvailable = false; + adi_uart_IsRxBufferAvailable(hDevice, &bAvailable); + return bAvailable; +} + +int serial_writable(serial_t *obj) +{ + bool bAvailable = false; + adi_uart_IsTxBufferAvailable(hDevice, &bAvailable); + return bAvailable; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj); + + adi_uart_RegisterCallback(hDevice, &uart_callback, obj); +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + adi_uart_ForceTxBreak(hDevice, true); +} + +void serial_break_clear(serial_t *obj) +{ + adi_uart_ForceTxBreak(hDevice, false); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + + MBED_ASSERT(obj); + + irq_handler = handler; + serial_irq_ids[0] = id; +} +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.c new file mode 100755 index 00000000000..daf5e06738c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.c @@ -0,0 +1,221 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "sleep_api.h" + +#ifdef DEVICE_SLEEP + +#include "adi_pwr.h" +#include "adi_pwr_def.h" +#include "adi_rtos_map.h" +#include "ADuCM3029_device.h" +#include "sleep.h" + +/** + * Function to put processor into sleep (FLEXI mode only). + */ +static void go_into_WFI(const ADI_PWR_POWER_MODE PowerMode) +{ + uint32_t savedPriority; + uint16_t savedWDT; + uint32_t scrSetBits = 0u; + uint32_t scrClrBits = 0u; + ADI_INT_STATUS_ALLOC(); + + /* pre-calculate the sleep-on-exit set/clear bits, FLEXI mode only */ + scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk; + + /* wfi without deepsleep or sleep-on-exit */ + scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + + /* put all the power mode and system control mods inside a critical section */ + ADI_ENTER_CRITICAL_REGION(); + + { /* these three lines must be in a success-checking loop if they are not inside critical section */ + /* Uninterruptable unlock sequence */ + pADI_PMG0->PWRKEY = ADI_PMG_KEY; + + /* Clear the previous mode and set new mode */ + pADI_PMG0->PWRMOD =(uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode ); + } + + /* Update the SCR (sleepdeep and sleep-on-exit bits) */ + SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits); + + /* save current Base Priority Level */ + savedPriority = __get_BASEPRI(); + + /* NOTE: the watchdog timer (WDT) of the GlueMicro (ADuCM302x) is reset + by the core hardware with every exit from low-power mode. Therefore, + even though we may have disabled it during startup, it will reset + itself on exit from every hibernation state. Therefore, to avoid + unintended system resets every 30 seconds because of unexpected WDT + timeouts, we save/restore the WDT control register around + hibernation entry and exit. + */ + + /* save WDT control register */ + savedWDT = pADI_WDT0->CTL; + + /* Set caller's priority threshold (left-justified) */ + __set_BASEPRI(0); + + /* bus sync to insure register writes from interrupt handlers are always complete before WFI */ + __DSB(); + + /* Wait for interrupt */ + __WFI(); + + ADI_EXIT_CRITICAL_REGION(); + + ADI_ENTER_CRITICAL_REGION(); + + /* Restore previous base priority */ + __set_BASEPRI(savedPriority); + + /* restore WDT control register */ + pADI_WDT0->CTL = savedWDT; + + /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + + __DSB(); /* bus sync before re-enabling interrupts */ + + ADI_EXIT_CRITICAL_REGION(); +} + + +/** + * Function to enable/disable clock gating for the available clocks. + * PCLK overrides all the other clocks. + */ +void set_clock_gating(peripheral_clk_t eClk, int enable) +{ + uint32_t flag; + + switch (eClk) { + case PCLK: + flag = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF; + break; + case I2C_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF; + break; + case GPIO_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF; + break; + case GPT0_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF; + break; + case GPT1_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF; + break; + case GPT2_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF; + break; + default: + return; + } + + // if enable, set the bit otherwise clear the bit + if (enable) { + pADI_CLKG0_CLK->CTL5 |= flag; + } else { + pADI_CLKG0_CLK->CTL5 &= (~flag); + } +} + + + +/** Send the microcontroller to sleep + * + * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + * + * This mode puts the processor into FLEXI mode however the peripheral clocks are not gated + * hence they are still active. + */ +void hal_sleep(void) +{ + // set to go into the FLEXI mode where the processor is asleep and all peripherals are + // still active + go_into_WFI(ADI_PWR_MODE_FLEXI); +} + + +/** Send the microcontroller to deep sleep + * + * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode + * has the same sleep features as sleep plus it powers down peripherals and clocks. All state + * is still maintained. + * + * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + * + * This mode puts the processor into FLEXI mode and all the peripheral clocks are clock gated + * hence they are inactive until interrupts are generated in which case the processor is awaken + * from sleep. + */ +void hal_deepsleep(void) +{ + // set clock gating to all the peripheral clocks + set_clock_gating(PCLK, 1); + + // set to go into the FLEXI mode with peripheral clocks gated. + go_into_WFI(ADI_PWR_MODE_FLEXI); + + // when exiting, clear all peripheral clock gating bits. This is done to enable clocks that aren't + // automatically re-enabled out of sleep such as the GPIO clock. + pADI_CLKG0_CLK->CTL5 = 0; +} + +#endif // #ifdef DEVICE_SLEEP diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.h new file mode 100755 index 00000000000..6d379a78009 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/sleep.h @@ -0,0 +1,68 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef __SLEEP__H__ +#define __SLEEP__H__ + + +/* Enumeration to specify peripheral clock types: + General purpose timer clocks 0-2, + I2C clock, + GPIO clock, + RGB timer clock. + Peripheral clock (PCLK) controls all the peripheral clocks, including + all the clocks mentioned previously +*/ +typedef enum { + GPT0_CLOCK = 0, + GPT1_CLOCK, + GPT2_CLOCK, + I2C_CLOCK, + GPIO_CLOCK, + PCLK +} peripheral_clk_t; + + +/* Function to enable/disable clock gating for the available clocks. + PCLK overrides all the other clocks. +*/ +void set_clock_gating(peripheral_clk_t eClk, int enable); + +#endif // #ifndef __SLEEP_H__ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c new file mode 100755 index 00000000000..f5ef0bc4157 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c @@ -0,0 +1,366 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include "mbed_assert.h" + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "drivers/spi/adi_spi.h" + + + +#if defined(BUILD_SPI_MI_DYNAMIC) +#if defined(ADI_DEBUG) +#warning "BUILD_SPI_MI_DYNAMIC is defined. Memory allocation for SPI will be dynamic" +int adi_spi_memtype = 0; +#endif +#else +ADI_SPI_HANDLE spi_Handle0; +uint8_t spi_Mem0[ADI_SPI_MEMORY_SIZE]; +ADI_SPI_HANDLE spi_Handle1; +uint8_t spi_Mem1[ADI_SPI_MEMORY_SIZE]; +ADI_SPI_HANDLE spi_Handle2; +uint8_t spi_Mem2[ADI_SPI_MEMORY_SIZE]; +#if defined(ADI_DEBUG) +#warning "BUILD_SPI_MI_DYNAMIC is NOT defined. Memory allocation for SPI will be static" +int adi_spi_memtype = 1; +#endif +#endif + + + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + * @param[in] mosi The pin to use for MOSI + * @param[in] miso The pin to use for MISO + * @param[in] sclk The pin to use for SCLK + * @param[in] ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + ADI_SPI_HANDLE *pSPI_Handle; + uint8_t *SPI_Mem; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + uint32_t nDeviceNum = 0; + ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE; + + +#if defined(BUILD_SPI_MI_DYNAMIC) + if (mosi == SPI0_MOSI) { + nDeviceNum = SPI_0; + } else if (mosi == SPI1_MOSI) { + nDeviceNum = SPI_1; + } else if (mosi == SPI2_MOSI) { + nDeviceNum = SPI_2; + } + pSPI_Handle = &obj->SPI_Handle; + obj->pSPI_Handle = pSPI_Handle; + SPI_Mem = obj->SPI_Mem; +#else + if (mosi == SPI0_MOSI) { + nDeviceNum = SPI_0; + pSPI_Handle = &spi_Handle0; + SPI_Mem = &spi_Mem0[0]; + } else if (mosi == SPI1_MOSI) { + nDeviceNum = SPI_1; + pSPI_Handle = &spi_Handle1; + SPI_Mem = &spi_Mem1[0]; + } else if (mosi == SPI2_MOSI) { + nDeviceNum = SPI_2; + pSPI_Handle = &spi_Handle2; + SPI_Mem = &spi_Mem2[0]; + } + obj->pSPI_Handle = pSPI_Handle; +#endif + + + obj->instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + SystemCoreClockUpdate(); + SPI_Return = adi_spi_Open(nDeviceNum, SPI_Mem, ADI_SPI_MEMORY_SIZE, pSPI_Handle); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + + if (ssel != NC) { + if ( (ssel == SPI0_CS0) || (ssel == SPI1_CS0) || (ssel == SPI2_CS0)) { + spi_cs = ADI_SPI_CS0; + } else if ( (ssel == SPI0_CS1) || (ssel == SPI1_CS1) || (ssel == SPI2_CS1)) { + spi_cs = ADI_SPI_CS1; + } else if ( (ssel == SPI0_CS2) || (ssel == SPI1_CS2) || (ssel == SPI2_CS2)) { + spi_cs = ADI_SPI_CS2; + } else if ( (ssel == SPI0_CS3) || (ssel == SPI1_CS3) || (ssel == SPI2_CS3)) { + spi_cs = ADI_SPI_CS3; + } + + SPI_Return = adi_spi_SetChipSelect(*pSPI_Handle, spi_cs); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + } +} + + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * @param[in] obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_Close(SPI_Handle); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. + * The default bit order is MSB. + * @param[in,out] obj The SPI object to configure + * @param[in] bits The number of bits per frame + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] slave Zero for master mode or non-zero for slave mode + * + ** Configure the data transmission format + * + * @param bits Number of bits per SPI frame (4 - 16) + * @param mode Clock polarity and phase mode (0 - 3) + * + * @code + * mode | POL PHA + * -----+-------- + * 0 | 0 0 + * 1 | 0 1 + * 2 | 1 0 + * 3 | 1 1 + * @endcode + + bool phase; + true : trailing-edge + false : leading-edge + + bool polarity; + true : CPOL=1 (idle high) polarity + false : CPOL=0 (idle-low) polarity + */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + bool phase; + bool polarity; + bool master; + + + SPI_Handle = *obj->pSPI_Handle; + + if ((uint32_t)mode & 0x1) { + phase = true; + } + else { + phase = false; + } + SPI_Return = adi_spi_SetClockPhase(SPI_Handle, phase); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + + if ((uint32_t)mode & 0x2) { + polarity = true; + } + else { + polarity = false; + } + SPI_Return = adi_spi_SetClockPolarity(SPI_Handle, polarity); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + + master = !((bool)slave); + SPI_Return = adi_spi_SetMasterMode(SPI_Handle, master); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_SetBitrate(SPI_Handle, (uint32_t) hz); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Write a byte out in master mode and receive a value + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value) +{ + ADI_SPI_TRANSCEIVER transceive; + uint8_t TxBuf; + uint8_t RxBuf; + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + TxBuf = (uint8_t)value; + + transceive.pReceiver = &RxBuf; + transceive.ReceiverBytes = 1; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = &TxBuf; /* initialize data attributes */ + transceive.TransmitterBytes = 1; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ + + transceive.bDMA = false; + transceive.bRD_CTL = false; + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return 1; + } + + return((int)RxBuf); +} + + +/** Write a block out in master mode and receive a value + * + * The total number of bytes sent and recieved will be the maximum of + * tx_length and rx_length. The bytes written will be padded with the + * value 0xff. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx_buffer Pointer to the byte-array of data to write to the device + * @param[in] tx_length Number of bytes to write, may be zero + * @param[in] rx_buffer Pointer to the byte-array of data to read from the device + * @param[in] rx_length Number of bytes to read, may be zero + * @param[in] write_fill Default data transmitted while performing a read + * @returns + * The number of bytes written and read from the device. This is + * maximum of tx_length and rx_length. + */ +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + ADI_SPI_TRANSCEIVER transceive; + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + transceive.pReceiver = (uint8_t*)rx_buffer; + transceive.ReceiverBytes = rx_length; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = (uint8_t*)tx_buffer; /* initialize data attributes */ + transceive.TransmitterBytes = tx_length; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ + + transceive.bDMA = false; + transceive.bRD_CTL = false; + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return -1; + } + else { + return((int)tx_length); + } +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c new file mode 100755 index 00000000000..cb346f9342f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/trng_api.c @@ -0,0 +1,136 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#if defined(DEVICE_TRNG) + +#include +#include +#include +#include "adi_rng_def.h" +#include "cmsis.h" +#include "trng_api.h" +#include "objects.h" + +// Sampling counter values +// Prescaler: 0 - 10 +// LenReload: 0 - 4095 +#define TRNG_CNT_VAL 4095 +#define TRNG_PRESCALER 2 + +/* RNG Device memory */ +static uint8_t RngDevMem[ADI_RNG_MEMORY_SIZE]; + +void trng_init(trng_t *obj) +{ + ADI_RNG_HANDLE RNGhDevice; + + // Open the device + adi_rng_Open(0,RngDevMem,sizeof(RngDevMem),&RNGhDevice); + + // Set sample length for the H/W RN accumulator + adi_rng_SetSampleLen(RNGhDevice, TRNG_PRESCALER, TRNG_CNT_VAL); + + // Disable buffering - single byte generation only + adi_rng_EnableBuffering(RNGhDevice, false); + + // Enable the TRNG + adi_rng_Enable(RNGhDevice, true); + + // Save device handle + obj->RNGhDevice = RNGhDevice; +} + +void trng_free(trng_t *obj) +{ + ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; + + adi_rng_Enable(RNGhDevice, false); + adi_rng_Close(RNGhDevice); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; + bool bRNGRdy, bStuck; + uint32_t i; + volatile uint32_t nRandomNum; + ADI_RNG_RESULT result; + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)RNGhDevice; + + for (i = 0; i < length; i++) { + // Loop until the device has data to be read + do { + result = adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); + if (result != ADI_RNG_SUCCESS) { + return -1; + } + } while (!bRNGRdy); + + // Check the STUCK bit to make sure the oscillator output isn't stuck + result = adi_rng_GetStuckStatus(RNGhDevice, &bStuck); + + // If the stuck bit is set, this means there may be a problem with RNG hardware, + // exit with an error + if ( (result != ADI_RNG_SUCCESS) || ((result == ADI_RNG_SUCCESS) && (bStuck)) ) { + // Clear the STUCK bit by writing a 1 to it + pDevice->pRNG->STAT |= BITM_RNG_STAT_STUCK; + return -1; + } + + // Read the RNG + result = adi_rng_GetRngData(RNGhDevice, (uint32_t*)(&nRandomNum)); + + if (result != ADI_RNG_SUCCESS) { + return -1; + } + + // Save the output + output[i] = (uint8_t)(nRandomNum & 0xFF); + } + + *output_length = length; + + // Clear nRandomNum on the stack before exiting + nRandomNum = 0; + + return 0; +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c new file mode 100755 index 00000000000..82ca488f5f5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c @@ -0,0 +1,348 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include +#include +#include +#include + +#ifndef BITM_TMR_RGB_CTL_EN +#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN +#endif + +typedef uint32_t timestamp_t; + +// defined in mbed_us_ticker_api.c which calls the ticker_irq_handler() routine +// defined in mbed_ticker_api.c +void us_ticker_irq_handler(void); + +static int us_ticker_inited = 0; + +static ADI_TMR_CONFIG tmrConfig, tmr2Config; + +static volatile uint32_t Upper_count = 0, largecnt = 0; + +static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2}; + +#if defined(__ADUCM302x__) + static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn}; +#elif defined(__ADUCM4x50__) + static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn}; +#else +#error TMR is not ported for this processor +#endif + + +/*---------------------------------------------------------------------------* + Local functions + *---------------------------------------------------------------------------*/ +static void GP1CallbackFunction(void *pCBParam, uint32_t Event, void * pArg) +{ + Upper_count++; +} + + +static uint32_t get_current_time(void) +{ + uint16_t tmrcnt0, tmrcnt1; + uint32_t totaltmr0, totaltmr1; + uint32_t uc1, tmrpend0, tmrpend1; + + do { + volatile uint32_t *ucptr = &Upper_count; + + /* + * Carefully coded to prevent race conditions. Do not make changes unless you understand all the + * implications. + * + * Note this function can be called with interrupts globally disabled or enabled. It has been coded to work in both cases. + * + * TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz. + * TMR1 generates an interrupt every time it overflows its 16 bit counter. TMR0 runs faster and provides + * the lowest 8 bits of the current time count. When TMR0 and TMR1 are combined, they provide 24 bits of + * timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8) + * + * There are several race conditions protected against: + * 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other. + * Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again + * until they do. This ensures that one or the other counters are stable with respect to each other. + * + * 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction). + * Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later. + * + * 3. Race between the TMR1 pend, and the TMR1.CURCNT read. Even with TMR1 interrupt disabled, the pend bit + * may be set while TMR1.CURCNT is being read. We don't know if the pend bit matches the TMR1 state. + * To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again. + * + * Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt, + * thereby clearing any TMR1 pend's. This have no effect if this routine is called with interrupts globally disabled. + */ + + NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // Prevent Upper_count increment + tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); + // Check if there is a pending interrupt for timer 1 + + __DMB(); // memory barrier: read GP0 before GP1 + + tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT; // to minimize skew, read both timers manually + + __DMB(); // memory barrier: read GP0 before GP1 + + tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT; // read both timers manually + + totaltmr0 = tmrcnt0; // expand to u32 bits + totaltmr1 = tmrcnt1; // expand to u32 bits + + tmrcnt0 &= 0xff00u; + tmrcnt1 <<= 8; + + __DMB(); + + uc1 = *ucptr; // Read Upper_count + + tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); + // Check for a pending interrupt again. Only leave loop if they match + + NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // enable interrupt on every loop to allow TMR1 interrupt to run + } while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1)); + + totaltmr1 <<= 8; // Timer1 runs 256x slower + totaltmr1 += totaltmr0 & 0xffu; // Use last 8 bits of Timer0 as it runs faster + // totaltmr1 now contain 24 bits of significance + + if (tmrpend0) { // If an interrupt is pending, then increment local copy of upper count + uc1++; + } + + uint64_t Uc = totaltmr1; // expand out to 64 bits unsigned + Uc += ((uint64_t) uc1) << 24; // Add on the upper count to get the full precision count + + // Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs + + Uc *= 1290555u; // Divide total(1/26) << 25 + Uc >>= 25; // shift back. Fixed point avoid use of floating point divide. + // Compiler does this inline using shifts and adds. + + return Uc; +} + + +static void calc_event_counts(uint32_t timestamp) +{ + uint32_t calc_time, blocks, offset; + uint64_t aa; + + calc_time = get_current_time(); + offset = timestamp - calc_time; // offset in useconds + + if (offset > 0xf0000000u) // if offset is a really big number, assume that timer has already expired (i.e. negative) + offset = 0u; + + if (offset > 10u) { // it takes 10us to user timer routine after interrupt. Offset timer to account for that. + offset -= 10u; + } else + offset = 0u; + + aa = (uint64_t) offset; + aa *= 26u; // convert from 1MHz to 26MHz clock. todo scale for other clock freqs + + blocks = aa >> 7; + blocks++; // round + + largecnt = blocks>>1; // communicate to event_timer() routine +} + +static void event_timer() +{ + if (largecnt) { + uint32_t cnt = largecnt; + + if (cnt > 65535u) { + cnt = 0u; + } else { + cnt = 65536u - cnt; + } + + tmr2Config.nLoad = cnt; + tmr2Config.nAsyncLoad = cnt; + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config); + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true); + } else { + us_ticker_irq_handler(); + } +} + + +/* + * Interrupt routine for timer 2 + * + * largecnt counts how many timer ticks should be counted to reach timer event. + * Each interrupt happens every 65536 timer ticks, unless there are less than 65536 ticks to count. + * In that case do the remaining timers ticks. + * + * largecnt is a global that is used to communicate between event_timer and the interrupt routine + * On entry, largecnt will be any value larger than 0. + */ +static void GP2CallbackFunction(void *pCBParam, uint32_t Event, void * pArg) +{ + if (largecnt >= 65536u) { + largecnt -= 65536u; + } else { + largecnt = 0; + } + + if (largecnt < 65536u) { + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false); + event_timer(); + } +} + + +/*---------------------------------------------------------------------------* + us_ticker HAL APIs + *---------------------------------------------------------------------------*/ +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } + + us_ticker_inited = 1; + + /*--------------------- GP TIMER INITIALIZATION --------------------------*/ + + /* Set up GP0 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP0, NULL, NULL, false); + + /* Set up GP1 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP1, GP1CallbackFunction, NULL, true); + + /* Set up GP1 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP2, GP2CallbackFunction, NULL, true); + + /* Configure GP0 to run at 26MHz */ + tmrConfig.bCountingUp = true; + tmrConfig.bPeriodic = true; + tmrConfig.ePrescaler = ADI_TMR_PRESCALER_1; // TMR0 at 26MHz + tmrConfig.eClockSource = ADI_TMR_CLOCK_PCLK; // TMR source is PCLK (most examples use HFOSC) + tmrConfig.nLoad = 0; + tmrConfig.nAsyncLoad = 0; + tmrConfig.bReloading = false; + tmrConfig.bSyncBypass = true; // Allow x1 prescale: requires PCLK as a clk + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP0, &tmrConfig); + + /* Configure GP1 to have a period 256 times longer than GP0 */ + tmrConfig.nLoad = 0; + tmrConfig.nAsyncLoad = 0; + tmrConfig.ePrescaler = ADI_TMR_PRESCALER_256; // TMR1 = 26MHz/256 + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP1, &tmrConfig); + + /* Configure GP2 for doing event counts */ + tmr2Config.bCountingUp = true; + tmr2Config.bPeriodic = true; + tmr2Config.ePrescaler = ADI_TMR_PRESCALER_256; // TMR2 at 26MHz/256 + tmr2Config.eClockSource = ADI_TMR_CLOCK_PCLK; // TMR source is PCLK (most examples use HFOSC) + tmr2Config.nLoad = 0; + tmr2Config.nAsyncLoad = 0; + tmr2Config.bReloading = false; + tmr2Config.bSyncBypass = true; // Allow x1 prescale + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config); + + + /*------------------------- GP TIMER ENABLE ------------------------------*/ + + /* Manually enable both timers to get them started at the same time + * + */ + adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; + adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; +} + +uint32_t us_ticker_read() +{ + uint32_t curr_time; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + curr_time = get_current_time(); + + return curr_time; +} + +void us_ticker_disable_interrupt(void) +{ + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false); +} + +void us_ticker_clear_interrupt(void) +{ + NVIC_ClearPendingIRQ(TMR2_EVT_IRQn); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + + /* timestamp is when interrupt should fire. + * + * This MUST not be called if another timer event is currently enabled. + * + */ + calc_event_counts(timestamp); // use timestamp to calculate largecnt to control number of timer interrupts + event_timer(); // uses largecnt to initiate timer interrupts +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + * + * This MUST not be called if another timer event is currently enabled. + */ +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(TMR2_EVT_IRQn); +} + + +/* +** EOF +*/ diff --git a/cmsis/TARGET_CORTEX_A/core_caInstr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029.h old mode 100644 new mode 100755 similarity index 58% rename from cmsis/TARGET_CORTEX_A/core_caInstr.h rename to targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029.h index b1d34357650..df6d8c7ee6e --- a/cmsis/TARGET_CORTEX_A/core_caInstr.h +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029.h @@ -1,13 +1,14 @@ /**************************************************************************//** - * @file core_caInstr.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 04. December 2012 + * @file ADuCM3029.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for + * Device ADuCM3029 + * @version V3.10 + * @date 23. November 2012 * - * @note + * @note Modified 14. November 2016 Analog Devices * ******************************************************************************/ -/* Copyright (c) 2009 - 2012 ARM LIMITED +/* Copyright (c) 2012 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -32,14 +33,29 @@ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + Portions Copyright (c) 2016 Analog Devices, Inc. ---------------------------------------------------------------------------*/ -#ifndef __CORE_CAINSTR_H__ -#define __CORE_CAINSTR_H__ - -#define __CORTEX_M 0x3 -#include "core_cmInstr.h" -#undef __CORTEX_M +#ifndef ADUCM3029_H +#define ADUCM3029_H +#ifndef __ADUCM30xx__ +#define __ADUCM30xx__ /*!< PreProcessor feature macro */ #endif +#include +#include + +/* Configuration of the Cortex-M3 Processor and Core Peripherals */ +#define __CM3_REV 0x0201u /*!< Core Revision r2p1 */ +#define __NVIC_PRIO_BITS 3u /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1u /*!< MPU present */ +#define __FPU_PRESENT 0u /*!< FPU not present */ + +#include /* Cortex-M3 processor and core peripherals */ + +#include "system_ADuCM3029.h" + +#endif /* ADUCM3029_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_cdef.h new file mode 100755 index 00000000000..44595e97e08 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_cdef.h @@ -0,0 +1,112 @@ +/*! +***************************************************************************** + * @file: ADuCM3029_cdef.h + * @brief: ADuCM3029 C MMR Pointer Definitions + * @version: $Revision: 36179 $ + * @date: $Date: 2017-02-10 09:56:54 -0500 (Fri, 10 Feb 2017) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2015-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _WRAP_ADUCM3029_CDEF_H +#define _WRAP_ADUCM3029_CDEF_H + +#include + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm081 (rule 19.6): #undef should not be used + * Needed to work around incorrect definitions in sys/ADuCM302x_cdef.h. + */ +#pragma diag_suppress=Pm081 +#endif /* __ICCARM__ */ + +#include +#include + + +/* Backward compatibility shims for renamed UART registers. */ + +#define pREG_UART0_COMRX (pREG_UART0_RX) +#define pREG_UART0_COMTX (pREG_UART0_TX) +#define pREG_UART0_COMIEN (pREG_UART0_IEN) +#define pREG_UART0_COMIIR (pREG_UART0_IIR) +#define pREG_UART0_COMLCR (pREG_UART0_LCR) +#define pREG_UART0_COMMCR (pREG_UART0_MCR) +#define pREG_UART0_COMLSR (pREG_UART0_LSR) +#define pREG_UART0_COMMSR (pREG_UART0_MSR) +#define pREG_UART0_COMSCR (pREG_UART0_SCR) +#define pREG_UART0_COMFCR (pREG_UART0_FCR) +#define pREG_UART0_COMFBR (pREG_UART0_FBR) +#define pREG_UART0_COMDIV (pREG_UART0_DIV) +#define pREG_UART0_COMLCR2 (pREG_UART0_LCR2) +#define pREG_UART0_COMCTL (pREG_UART0_CTL) +#define pREG_UART0_COMRFC (pREG_UART0_RFC) +#define pREG_UART0_COMTFC (pREG_UART0_TFC) +#define pREG_UART0_COMRSC (pREG_UART0_RSC) +#define pREG_UART0_COMACR (pREG_UART0_ACR) +#define pREG_UART0_COMASRL (pREG_UART0_ASRL) +#define pREG_UART0_COMASRH (pREG_UART0_ASRH) + + +/* Backward compatibility shim for renamed RTC registers and fields. */ + +#define pREG_RTC0_CR3OC (pREG_RTC0_CR3SS) +#define pREG_RTC0_CR4OC (pREG_RTC0_CR4SS) +#define pREG_RTC0_OCMSK (pREG_RTC0_SSMSK) +#define pREG_RTC0_OC1ARL (pREG_RTC0_SS1ARL) +#define pREG_RTC0_OC1 (pREG_RTC0_SS1) +#define pREG_RTC0_OC1TGT (pREG_RTC0_SS1TGT) +#define pREG_RTC1_CR3OC (pREG_RTC1_CR3SS) +#define pREG_RTC1_CR4OC (pREG_RTC1_CR4SS) +#define pREG_RTC1_OCMSK (pREG_RTC1_SSMSK) +#define pREG_RTC1_OC1ARL (pREG_RTC1_SS1ARL) +#define pREG_RTC1_OC1 (pREG_RTC1_SS1) +#define pREG_RTC1_OC1TGT (pREG_RTC1_SS1TGT) + + +#ifdef __ICCARM__ +#pragma diag_default=Pm081 +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM3029_CDEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_def.h new file mode 100755 index 00000000000..dd19873c3a0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_def.h @@ -0,0 +1,370 @@ +/*! +***************************************************************************** + * @file: ADuCM3029_def.h + * @brief: ADuCM3029 MMR addresses and fields + * @version: $Revision: 36179 $ + * @date: $Date: 2017-02-10 09:56:54 -0500 (Fri, 10 Feb 2017) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2015-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _WRAP_ADUCM3029_DEF_H +#define _WRAP_ADUCM3029_DEF_H + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Some comments are wrongly identified as code. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * The sys/ADuCM302x.h header relies on more. The IAR compiler supports that. + */ +#pragma diag_suppress=Pm008,Pm009 +#endif /* __ICCARM__ */ + +#ifdef __IASMARM__ +/* Define masks to plain numeric literal for IAR assembler. */ +#define _ADI_MSK_3( mask, smask, type ) (mask) +#endif /* __IASMARM__ */ + +#include + +/* Backward compatibility shims for renamed UART registers. */ + +#define REG_UART0_COMRX (REG_UART0_RX) +#define REG_UART0_COMTX (REG_UART0_TX) +#define REG_UART0_COMIEN (REG_UART0_IEN) +#define REG_UART0_COMIIR (REG_UART0_IIR) +#define REG_UART0_COMLCR (REG_UART0_LCR) +#define REG_UART0_COMMCR (REG_UART0_MCR) +#define REG_UART0_COMLSR (REG_UART0_LSR) +#define REG_UART0_COMMSR (REG_UART0_MSR) +#define REG_UART0_COMSCR (REG_UART0_SCR) +#define REG_UART0_COMFCR (REG_UART0_FCR) +#define REG_UART0_COMFBR (REG_UART0_FBR) +#define REG_UART0_COMDIV (REG_UART0_DIV) +#define REG_UART0_COMLCR2 (REG_UART0_LCR2) +#define REG_UART0_COMCTL (REG_UART0_CTL) +#define REG_UART0_COMRFC (REG_UART0_RFC) +#define REG_UART0_COMTFC (REG_UART0_TFC) +#define REG_UART0_COMRSC (REG_UART0_RSC) +#define REG_UART0_COMACR (REG_UART0_ACR) +#define REG_UART0_COMASRL (REG_UART0_ASRL) +#define REG_UART0_COMASRH (REG_UART0_ASRH) + +#define BITP_UART_COMRX_RBR (BITP_UART_RX_RBR) +#define BITP_UART_COMTX_THR (BITP_UART_TX_THR) +#define BITP_UART_COMIEN_EDMAR (BITP_UART_IEN_EDMAR) +#define BITP_UART_COMIEN_EDMAT (BITP_UART_IEN_EDMAT) +#define BITP_UART_COMIEN_EDSSI (BITP_UART_IEN_EDSSI) +#define BITP_UART_COMIEN_ELSI (BITP_UART_IEN_ELSI) +#define BITP_UART_COMIEN_ETBEI (BITP_UART_IEN_ETBEI) +#define BITP_UART_COMIEN_ERBFI (BITP_UART_IEN_ERBFI) +#define BITP_UART_COMIIR_FEND (BITP_UART_IIR_FEND) +#define BITP_UART_COMIIR_STA (BITP_UART_IIR_STAT) +#define BITP_UART_COMIIR_NIRQ (BITP_UART_IIR_NIRQ) +#define BITP_UART_COMLCR_BRK (BITP_UART_LCR_BRK) +#define BITP_UART_COMLCR_SP (BITP_UART_LCR_SP) +#define BITP_UART_COMLCR_EPS (BITP_UART_LCR_EPS) +#define BITP_UART_COMLCR_PEN (BITP_UART_LCR_PEN) +#define BITP_UART_COMLCR_STOP (BITP_UART_LCR_STOP) +#define BITP_UART_COMLCR_WLS (BITP_UART_LCR_WLS) +#define BITP_UART_COMMCR_LOOPBACK (BITP_UART_MCR_LOOPBACK) +#define BITP_UART_COMMCR_OUT2 (BITP_UART_MCR_OUT2) +#define BITP_UART_COMMCR_OUT1 (BITP_UART_MCR_OUT1) +#define BITP_UART_COMMCR_RTS (BITP_UART_MCR_RTS) +#define BITP_UART_COMMCR_DTR (BITP_UART_MCR_DTR) +#define BITP_UART_COMLSR_FIFOERR (BITP_UART_LSR_FIFOERR) +#define BITP_UART_COMLSR_TEMT (BITP_UART_LSR_TEMT) +#define BITP_UART_COMLSR_THRE (BITP_UART_LSR_THRE) +#define BITP_UART_COMLSR_BI (BITP_UART_LSR_BI) +#define BITP_UART_COMLSR_FE (BITP_UART_LSR_FE) +#define BITP_UART_COMLSR_PE (BITP_UART_LSR_PE) +#define BITP_UART_COMLSR_OE (BITP_UART_LSR_OE) +#define BITP_UART_COMLSR_DR (BITP_UART_LSR_DR) +#define BITP_UART_COMMSR_DCD (BITP_UART_MSR_DCD) +#define BITP_UART_COMMSR_RI (BITP_UART_MSR_RI) +#define BITP_UART_COMMSR_DSR (BITP_UART_MSR_DSR) +#define BITP_UART_COMMSR_CTS (BITP_UART_MSR_CTS) +#define BITP_UART_COMMSR_DDCD (BITP_UART_MSR_DDCD) +#define BITP_UART_COMMSR_TERI (BITP_UART_MSR_TERI) +#define BITP_UART_COMMSR_DDSR (BITP_UART_MSR_DDSR) +#define BITP_UART_COMMSR_DCTS (BITP_UART_MSR_DCTS) +#define BITP_UART_COMSCR_SCR (BITP_UART_SCR_SCR) +#define BITP_UART_COMFCR_RFTRIG (BITP_UART_FCR_RFTRIG) +#define BITP_UART_COMFCR_FDMAMD (BITP_UART_FCR_FDMAMD) +#define BITP_UART_COMFCR_TFCLR (BITP_UART_FCR_TFCLR) +#define BITP_UART_COMFCR_RFCLR (BITP_UART_FCR_RFCLR) +#define BITP_UART_COMFCR_FIFOEN (BITP_UART_FCR_FIFOEN) +#define BITP_UART_COMFBR_FBEN (BITP_UART_FBR_FBEN) +#define BITP_UART_COMFBR_DIVM (BITP_UART_FBR_DIVM) +#define BITP_UART_COMFBR_DIVN (BITP_UART_FBR_DIVN) +#define BITP_UART_COMDIV_DIV (BITP_UART_DIV_DIV) +#define BITP_UART_COMLCR2_OSR (BITP_UART_LCR2_OSR) +#define BITP_UART_COMCTL_REV (BITP_UART_CTL_REV) +#define BITP_UART_COMCTL_RXINV (BITP_UART_CTL_RXINV) +#define BITP_UART_COMCTL_FORCECLKON (BITP_UART_CTL_FORCECLK) +#define BITP_UART_COMRFC_RFC (BITP_UART_RFC_RFC) +#define BITP_UART_COMTFC_TFC (BITP_UART_TFC_TFC) +#define BITP_UART_COMRSC_DISTX (BITP_UART_RSC_DISTX) +#define BITP_UART_COMRSC_DISRX (BITP_UART_RSC_DISRX) +#define BITP_UART_COMRSC_OENSP (BITP_UART_RSC_OENSP) +#define BITP_UART_COMRSC_OENP (BITP_UART_RSC_OENP) +#define BITP_UART_COMACR_EEC (BITP_UART_ACR_EEC) +#define BITP_UART_COMACR_SEC (BITP_UART_ACR_SEC) +#define BITP_UART_COMACR_TOIEN (BITP_UART_ACR_TOIEN) +#define BITP_UART_COMACR_DNIEN (BITP_UART_ACR_DNIEN) +#define BITP_UART_COMACR_ABE (BITP_UART_ACR_ABE) +#define BITP_UART_COMASRL_CNT (BITP_UART_ASRL_CNT) +#define BITP_UART_COMASRL_NEETO (BITP_UART_ASRL_NEETO) +#define BITP_UART_COMASRL_NSETO (BITP_UART_ASRL_NSETO) +#define BITP_UART_COMASRL_BRKTO (BITP_UART_ASRL_BRKTO) +#define BITP_UART_COMASRL_DONE (BITP_UART_ASRL_DONE) +#define BITP_UART_COMASRH_CNT (BITP_UART_ASRH_CNT) + +#define BITM_UART_COMRX_RBR (BITM_UART_RX_RBR) +#define BITM_UART_COMTX_THR (BITM_UART_TX_THR) +#define BITM_UART_COMIEN_EDMAR (BITM_UART_IEN_EDMAR) +#define BITM_UART_COMIEN_EDMAT (BITM_UART_IEN_EDMAT) +#define BITM_UART_COMIEN_EDSSI (BITM_UART_IEN_EDSSI) +#define BITM_UART_COMIEN_ELSI (BITM_UART_IEN_ELSI) +#define BITM_UART_COMIEN_ETBEI (BITM_UART_IEN_ETBEI) +#define BITM_UART_COMIEN_ERBFI (BITM_UART_IEN_ERBFI) +#define BITM_UART_COMIIR_FEND (BITM_UART_IIR_FEND) +#define BITM_UART_COMIIR_STA (BITM_UART_IIR_STAT) +#define BITM_UART_COMIIR_NIRQ (BITM_UART_IIR_NIRQ) +#define BITM_UART_COMLCR_BRK (BITM_UART_LCR_BRK) +#define BITM_UART_COMLCR_SP (BITM_UART_LCR_SP) +#define BITM_UART_COMLCR_EPS (BITM_UART_LCR_EPS) +#define BITM_UART_COMLCR_PEN (BITM_UART_LCR_PEN) +#define BITM_UART_COMLCR_STOP (BITM_UART_LCR_STOP) +#define BITM_UART_COMLCR_WLS (BITM_UART_LCR_WLS) +#define BITM_UART_COMMCR_LOOPBACK (BITM_UART_MCR_LOOPBACK) +#define BITM_UART_COMMCR_OUT2 (BITM_UART_MCR_OUT2) +#define BITM_UART_COMMCR_OUT1 (BITM_UART_MCR_OUT1) +#define BITM_UART_COMMCR_RTS (BITM_UART_MCR_RTS) +#define BITM_UART_COMMCR_DTR (BITM_UART_MCR_DTR) +#define BITM_UART_COMLSR_FIFOERR (BITM_UART_LSR_FIFOERR) +#define BITM_UART_COMLSR_TEMT (BITM_UART_LSR_TEMT) +#define BITM_UART_COMLSR_THRE (BITM_UART_LSR_THRE) +#define BITM_UART_COMLSR_BI (BITM_UART_LSR_BI) +#define BITM_UART_COMLSR_FE (BITM_UART_LSR_FE) +#define BITM_UART_COMLSR_PE (BITM_UART_LSR_PE) +#define BITM_UART_COMLSR_OE (BITM_UART_LSR_OE) +#define BITM_UART_COMLSR_DR (BITM_UART_LSR_DR) +#define BITM_UART_COMMSR_DCD (BITM_UART_MSR_DCD) +#define BITM_UART_COMMSR_RI (BITM_UART_MSR_RI) +#define BITM_UART_COMMSR_DSR (BITM_UART_MSR_DSR) +#define BITM_UART_COMMSR_CTS (BITM_UART_MSR_CTS) +#define BITM_UART_COMMSR_DDCD (BITM_UART_MSR_DDCD) +#define BITM_UART_COMMSR_TERI (BITM_UART_MSR_TERI) +#define BITM_UART_COMMSR_DDSR (BITM_UART_MSR_DDSR) +#define BITM_UART_COMMSR_DCTS (BITM_UART_MSR_DCTS) +#define BITM_UART_COMSCR_SCR (BITM_UART_SCR_SCR) +#define BITM_UART_COMFCR_RFTRIG (BITM_UART_FCR_RFTRIG) +#define BITM_UART_COMFCR_FDMAMD (BITM_UART_FCR_FDMAMD) +#define BITM_UART_COMFCR_TFCLR (BITM_UART_FCR_TFCLR) +#define BITM_UART_COMFCR_RFCLR (BITM_UART_FCR_RFCLR) +#define BITM_UART_COMFCR_FIFOEN (BITM_UART_FCR_FIFOEN) +#define BITM_UART_COMFBR_FBEN (BITM_UART_FBR_FBEN) +#define BITM_UART_COMFBR_DIVM (BITM_UART_FBR_DIVM) +#define BITM_UART_COMFBR_DIVN (BITM_UART_FBR_DIVN) +#define BITM_UART_COMDIV_DIV (BITM_UART_DIV_DIV) +#define BITM_UART_COMLCR2_OSR (BITM_UART_LCR2_OSR) +#define BITM_UART_COMCTL_REV (BITM_UART_CTL_REV) +#define BITM_UART_COMCTL_RXINV (BITM_UART_CTL_RXINV) +#define BITM_UART_COMCTL_FORCECLKON (BITM_UART_CTL_FORCECLK) +#define BITM_UART_COMRFC_RFC (BITM_UART_RFC_RFC) +#define BITM_UART_COMTFC_TFC (BITM_UART_TFC_TFC) +#define BITM_UART_COMRSC_DISTX (BITM_UART_RSC_DISTX) +#define BITM_UART_COMRSC_DISRX (BITM_UART_RSC_DISRX) +#define BITM_UART_COMRSC_OENSP (BITM_UART_RSC_OENSP) +#define BITM_UART_COMRSC_OENP (BITM_UART_RSC_OENP) +#define BITM_UART_COMACR_EEC (BITM_UART_ACR_EEC) +#define BITM_UART_COMACR_SEC (BITM_UART_ACR_SEC) +#define BITM_UART_COMACR_TOIEN (BITM_UART_ACR_TOIEN) +#define BITM_UART_COMACR_DNIEN (BITM_UART_ACR_DNIEN) +#define BITM_UART_COMACR_ABE (BITM_UART_ACR_ABE) +#define BITM_UART_COMASRL_CNT (BITM_UART_ASRL_CNT) +#define BITM_UART_COMASRL_NEETO (BITM_UART_ASRL_NEETO) +#define BITM_UART_COMASRL_NSETO (BITM_UART_ASRL_NSETO) +#define BITM_UART_COMASRL_BRKTO (BITM_UART_ASRL_BRKTO) +#define BITM_UART_COMASRL_DONE (BITM_UART_ASRL_DONE) +#define BITM_UART_COMASRH_CNT (BITM_UART_ASRH_CNT) + + +/* Backward compatibility shim for corrected RTC_SR5.WPENDSR3 bit name. */ + +#define BITP_RTC_SR5_WPNDSR0 (BITP_RTC_SR5_WPENDSR3) +#define BITM_RTC_SR5_WPNDSR0 (BITM_RTC_SR5_WPENDSR3) + + +/* Backward compatibility shim for renamed RTC registers and fields. */ + +#define REG_RTC0_CR3OC (REG_RTC0_CR3SS) +#define REG_RTC0_CR4OC (REG_RTC0_CR4SS) +#define REG_RTC0_OCMSK (REG_RTC0_SSMSK) +#define REG_RTC0_OC1ARL (REG_RTC0_SS1ARL) +#define REG_RTC0_OC1 (REG_RTC0_SS1) +#define REG_RTC0_OC1TGT (REG_RTC0_SS1TGT) +#define REG_RTC1_CR3OC (REG_RTC1_CR3SS) +#define REG_RTC1_CR4OC (REG_RTC1_CR4SS) +#define REG_RTC1_OCMSK (REG_RTC1_SSMSK) +#define REG_RTC1_OC1ARL (REG_RTC1_SS1ARL) +#define REG_RTC1_OC1 (REG_RTC1_SS1) +#define REG_RTC1_OC1TGT (REG_RTC1_SS1TGT) + +#define BITP_RTC_CR1_RTCTRMINTEN (BITP_RTC_CR1_TRMINTEN) +#define BITP_RTC_SR3_RTCOC1IRQ (BITP_RTC_SR3_SS1IRQ) +#define BITP_RTC_SR3_RTCIC4IRQ (BITP_RTC_SR3_IC4IRQ) +#define BITP_RTC_SR3_RTCIC3IRQ (BITP_RTC_SR3_IC3IRQ) +#define BITP_RTC_SR3_RTCIC2IRQ (BITP_RTC_SR3_IC2IRQ) +#define BITP_RTC_SR3_RTCIC0IRQ (BITP_RTC_SR3_IC0IRQ) +#define BITP_RTC_CR2IC_RTCICOWUSEN (BITP_RTC_CR2IC_ICOWUSEN) +#define BITP_RTC_CR2IC_RTCIC4IRQEN (BITP_RTC_CR2IC_IC4IRQEN) +#define BITP_RTC_CR2IC_RTCIC3IRQEN (BITP_RTC_CR2IC_IC3IRQEN) +#define BITP_RTC_CR2IC_RTCIC2IRQEN (BITP_RTC_CR2IC_IC2IRQEN) +#define BITP_RTC_CR2IC_RTCIC0IRQEN (BITP_RTC_CR2IC_IC0IRQEN) +#define BITP_RTC_CR2IC_RTCIC4LH (BITP_RTC_CR2IC_IC4LH) +#define BITP_RTC_CR2IC_RTCIC3LH (BITP_RTC_CR2IC_IC3LH) +#define BITP_RTC_CR2IC_RTCIC2LH (BITP_RTC_CR2IC_IC2LH) +#define BITP_RTC_CR2IC_RTCIC0LH (BITP_RTC_CR2IC_IC0LH) +#define BITP_RTC_CR2IC_RTCIC4EN (BITP_RTC_CR2IC_IC4EN) +#define BITP_RTC_CR2IC_RTCIC3EN (BITP_RTC_CR2IC_IC3EN) +#define BITP_RTC_CR2IC_RTCIC2EN (BITP_RTC_CR2IC_IC2EN) +#define BITP_RTC_CR2IC_RTCIC0EN (BITP_RTC_CR2IC_IC0EN) +#define BITP_RTC_CR3OC_RTCOC1IRQEN (BITP_RTC_CR3SS_SS1IRQEN) +#define BITP_RTC_CR3OC_RTCOC1EN (BITP_RTC_CR3SS_SS1EN) +#define BITP_RTC_CR4OC_RTCOC1ARLEN (BITP_RTC_CR4SS_SS1ARLEN) +#define BITP_RTC_CR4OC_RTCOC1MSKEN (BITP_RTC_CR4SS_SS1MSKEN) +#define BITP_RTC_OCMSK_RTCOCMSK (BITP_RTC_SSMSK_SSMSK) +#define BITP_RTC_OC1ARL_RTCOC1ARL (BITP_RTC_SS1ARL_SS1ARL) +#define BITP_RTC_IC2_RTCIC2 (BITP_RTC_IC2_IC2) +#define BITP_RTC_IC3_RTCIC3 (BITP_RTC_IC3_IC3) +#define BITP_RTC_IC4_RTCIC4 (BITP_RTC_IC4_IC4) +#define BITP_RTC_OC1_RTCOC1 (BITP_RTC_SS1_SS1) +#define BITP_RTC_SR4_WSYNCOC1 (BITP_RTC_SR4_WSYNCSS1) +#define BITP_RTC_SR4_WSYNCOC1ARL (BITP_RTC_SR4_WSYNCSS1ARL) +#define BITP_RTC_SR4_WSYNCOCMSK (BITP_RTC_SR4_WSYNCSSMSK) +#define BITP_RTC_SR4_WSYNCCR4OC (BITP_RTC_SR4_WSYNCCR4SS) +#define BITP_RTC_SR4_WSYNCCR3OC (BITP_RTC_SR4_WSYNCCR3SS) +#define BITP_RTC_SR5_WPENDOC1 (BITP_RTC_SR5_WPENDSS1) +#define BITP_RTC_SR5_WPENDOC1ARL (BITP_RTC_SR5_WPENDSS1ARL) +#define BITP_RTC_SR5_WPENDOCMSK (BITP_RTC_SR5_WPENDSSMSK) +#define BITP_RTC_SR5_WPENDCR4OC (BITP_RTC_SR5_WPENDCR4SS) +#define BITP_RTC_SR5_WPENDCR3OC (BITP_RTC_SR5_WPENDCR3SS) +#define BITP_RTC_SR6_RTCFRZCNTPTR (BITP_RTC_SR6_FRZCNTPTR) +#define BITP_RTC_SR6_RTCIC0SNAP (BITP_RTC_SR6_IC0SNAP) +#define BITP_RTC_SR6_RTCIC4UNR (BITP_RTC_SR6_IC4UNR) +#define BITP_RTC_SR6_RTCIC3UNR (BITP_RTC_SR6_IC3UNR) +#define BITP_RTC_SR6_RTCIC2UNR (BITP_RTC_SR6_IC2UNR) +#define BITP_RTC_SR6_RTCIC0UNR (BITP_RTC_SR6_IC0UNR) +#define BITP_RTC_OC1TGT_RTCOC1TGT (BITP_RTC_SS1TGT_SS1TGT) +#define BITP_RTC_FRZCNT_RTCFRZCNT (BITP_RTC_FRZCNT_FRZCNT) + +#define BITM_RTC_CR1_RTCTRMINTEN (BITM_RTC_CR1_TRMINTEN) +#define BITM_RTC_SR3_RTCOC1IRQ (BITM_RTC_SR3_SS1IRQ) +#define BITM_RTC_SR3_RTCIC4IRQ (BITM_RTC_SR3_IC4IRQ) +#define BITM_RTC_SR3_RTCIC3IRQ (BITM_RTC_SR3_IC3IRQ) +#define BITM_RTC_SR3_RTCIC2IRQ (BITM_RTC_SR3_IC2IRQ) +#define BITM_RTC_SR3_RTCIC0IRQ (BITM_RTC_SR3_IC0IRQ) +#define BITM_RTC_CR2IC_RTCICOWUSEN (BITM_RTC_CR2IC_ICOWUSEN) +#define BITM_RTC_CR2IC_RTCIC4IRQEN (BITM_RTC_CR2IC_IC4IRQEN) +#define BITM_RTC_CR2IC_RTCIC3IRQEN (BITM_RTC_CR2IC_IC3IRQEN) +#define BITM_RTC_CR2IC_RTCIC2IRQEN (BITM_RTC_CR2IC_IC2IRQEN) +#define BITM_RTC_CR2IC_RTCIC0IRQEN (BITM_RTC_CR2IC_IC0IRQEN) +#define BITM_RTC_CR2IC_RTCIC4LH (BITM_RTC_CR2IC_IC4LH) +#define BITM_RTC_CR2IC_RTCIC3LH (BITM_RTC_CR2IC_IC3LH) +#define BITM_RTC_CR2IC_RTCIC2LH (BITM_RTC_CR2IC_IC2LH) +#define BITM_RTC_CR2IC_RTCIC0LH (BITM_RTC_CR2IC_IC0LH) +#define BITM_RTC_CR2IC_RTCIC4EN (BITM_RTC_CR2IC_IC4EN) +#define BITM_RTC_CR2IC_RTCIC3EN (BITM_RTC_CR2IC_IC3EN) +#define BITM_RTC_CR2IC_RTCIC2EN (BITM_RTC_CR2IC_IC2EN) +#define BITM_RTC_CR2IC_RTCIC0EN (BITM_RTC_CR2IC_IC0EN) +#define BITM_RTC_CR3OC_RTCOC1IRQEN (BITM_RTC_CR3SS_SS1IRQEN) +#define BITM_RTC_CR3OC_RTCOC1EN (BITM_RTC_CR3SS_SS1EN) +#define BITM_RTC_CR4OC_RTCOC1ARLEN (BITM_RTC_CR4SS_SS1ARLEN) +#define BITM_RTC_CR4OC_RTCOC1MSKEN (BITM_RTC_CR4SS_SS1MSKEN) +#define BITM_RTC_OCMSK_RTCOCMSK (BITM_RTC_SSMSK_SSMSK) +#define BITM_RTC_OC1ARL_RTCOC1ARL (BITM_RTC_SS1ARL_SS1ARL) +#define BITM_RTC_IC2_RTCIC2 (BITM_RTC_IC2_IC2) +#define BITM_RTC_IC3_RTCIC3 (BITM_RTC_IC3_IC3) +#define BITM_RTC_IC4_RTCIC4 (BITM_RTC_IC4_IC4) +#define BITM_RTC_OC1_RTCOC1 (BITM_RTC_SS1_SS1) +#define BITM_RTC_SR4_WSYNCOC1 (BITM_RTC_SR4_WSYNCSS1) +#define BITM_RTC_SR4_WSYNCOC1ARL (BITM_RTC_SR4_WSYNCSS1ARL) +#define BITM_RTC_SR4_WSYNCOCMSK (BITM_RTC_SR4_WSYNCSSMSK) +#define BITM_RTC_SR4_WSYNCCR4OC (BITM_RTC_SR4_WSYNCCR4SS) +#define BITM_RTC_SR4_WSYNCCR3OC (BITM_RTC_SR4_WSYNCCR3SS) +#define BITM_RTC_SR5_WPENDOC1 (BITM_RTC_SR5_WPENDSS1) +#define BITM_RTC_SR5_WPENDOC1ARL (BITM_RTC_SR5_WPENDSS1ARL) +#define BITM_RTC_SR5_WPENDOCMSK (BITM_RTC_SR5_WPENDSSMSK) +#define BITM_RTC_SR5_WPENDCR4OC (BITM_RTC_SR5_WPENDCR4SS) +#define BITM_RTC_SR5_WPENDCR3OC (BITM_RTC_SR5_WPENDCR3SS) +#define BITM_RTC_SR6_RTCFRZCNTPTR (BITM_RTC_SR6_FRZCNTPTR) +#define BITM_RTC_SR6_RTCIC0SNAP (BITM_RTC_SR6_IC0SNAP) +#define BITM_RTC_SR6_RTCIC4UNR (BITM_RTC_SR6_IC4UNR) +#define BITM_RTC_SR6_RTCIC3UNR (BITM_RTC_SR6_IC3UNR) +#define BITM_RTC_SR6_RTCIC2UNR (BITM_RTC_SR6_IC2UNR) +#define BITM_RTC_SR6_RTCIC0UNR (BITM_RTC_SR6_IC0UNR) +#define BITM_RTC_OC1TGT_RTCOC1TGT (BITM_RTC_SS1TGT_SS1TGT) +#define BITM_RTC_FRZCNT_RTCFRZCNT (BITM_RTC_FRZCNT_FRZCNT) + +#define ENUM_RTC_CR4OC_NO_MSK (ENUM_RTC_CR4SS_NO_MSK) +#define ENUM_RTC_CR4OC_THERM_MSK (ENUM_RTC_CR4SS_THERM_MSK) + +/* Backward compatibility shim for renamed crypto registers. */ + +#define BITP_CRYPT_CFG_KEYLEN (BITP_CRYPT_CFG_AESKEYLEN) +#define BITP_CRYPT_CFG_ENDIAN (BITP_CRYPT_CFG_AES_BYTESWAP) + +#define BITM_CRYPT_CFG_KEYLEN (BITM_CRYPT_CFG_AESKEYLEN) +#define BITM_CRYPT_CFG_ENDIAN (BITM_CRYPT_CFG_AES_BYTESWAP) + +#define ENUM_CRYPT_CFG_LITTLE_ENDIAN (_ADI_MSK_3(0x00000000, 0x00000000UL, uint32_t)) +#define ENUM_CRYPT_CFG_BIG_ENDIAN (_ADI_MSK_3(0x00000040, 0x00000040UL, uint32_t)) + + +#ifdef __ICCARM__ +#pragma diag_default=Pm008,Pm009 +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM3029_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_device.h new file mode 100755 index 00000000000..75b5f887967 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_device.h @@ -0,0 +1,261 @@ +/*! +***************************************************************************** + * @file: ADuCM3029_device.h + * @brief: ADuCM3029 C Register Definitions + * @version: $Revision: 36179 $ + * @date: $Date: 2017-02-10 09:56:54 -0500 (Fri, 10 Feb 2017) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2015-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _WRAP_ADUCM3029_DEVICE_H +#define _WRAP_ADUCM3029_DEVICE_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm093 (rule 18.4): use of union - overlapping storage shall not be used. + * Unions are required by sys/ADUCM302x_device.h. + */ +#pragma diag_suppress=Pm093 +#endif /* __ICCARM__ */ + +/* UART and RTC structs need to be redefined with backward compatibility names. */ +#define __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ +#define __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ + +/* The generated header. */ +#include + +typedef struct _ADI_UART_TypeDef +{ + union { + __I __C uint16_t RX; /*!< Receive Buffer Register */ + __I __C uint16_t COMRX; + __O uint16_t TX; /*!< Transmit Holding Register */ + __O uint16_t COMTX; + }; + __I __C uint8_t RESERVED0[2]; + union { + __IO uint16_t IEN; /*!< Interrupt Enable */ + __IO uint16_t COMIEN; + }; + __I __C uint8_t RESERVED1[2]; + union { + __I __C uint16_t IIR; /*!< Interrupt ID */ + __I __C uint16_t COMIIR; + }; + __I __C uint8_t RESERVED2[2]; + union { + __IO uint16_t LCR; /*!< Line Control */ + __IO uint16_t COMLCR; + }; + __I __C uint8_t RESERVED3[2]; + union { + __IO uint16_t MCR; /*!< Modem Control */ + __IO uint16_t COMMCR; + }; + __I __C uint8_t RESERVED4[2]; + union { + __I __C uint16_t LSR; /*!< Line Status */ + __I __C uint16_t COMLSR; + }; + __I __C uint8_t RESERVED5[2]; + union { + __I __C uint16_t MSR; /*!< Modem Status */ + __I __C uint16_t COMMSR; + }; + __I __C uint8_t RESERVED6[2]; + union { + __IO uint16_t SCR; /*!< Scratch buffer */ + __IO uint16_t COMSCR; + }; + __I __C uint8_t RESERVED7[2]; + union { + __IO uint16_t FCR; /*!< FIFO Control */ + __IO uint16_t COMFCR; + }; + __I __C uint8_t RESERVED8[2]; + union { + __IO uint16_t FBR; /*!< Fractional Baud Rate */ + __IO uint16_t COMFBR; + }; + __I __C uint8_t RESERVED9[2]; + union { + __IO uint16_t DIV; /*!< Baudrate divider */ + __IO uint16_t COMDIV; + }; + __I __C uint8_t RESERVED10[2]; + union { + __IO uint16_t LCR2; /*!< second Line Control */ + __IO uint16_t COMLCR2; + }; + __I __C uint8_t RESERVED11[2]; + union { + __IO uint16_t CTL; /*!< UART control register */ + __IO uint16_t COMCTL; + }; + __I __C uint8_t RESERVED12[2]; + union { + __I __C uint16_t RFC; /*!< RX FIFO byte count */ + __I __C uint16_t COMRFC; + }; + __I __C uint8_t RESERVED13[2]; + union { + __I __C uint16_t TFC; /*!< TX FIFO byte count */ + __I __C uint16_t COMTFC; + }; + __I __C uint8_t RESERVED14[2]; + union { + __IO uint16_t RSC; /*!< RS485 half-duplex Control */ + __IO uint16_t COMRSC; + }; + __I __C uint8_t RESERVED15[2]; + union { + __IO uint16_t ACR; /*!< Auto Baud Control */ + __IO uint16_t COMACR; + }; + __I __C uint8_t RESERVED16[2]; + union { + __I __C uint16_t ASRL; /*!< Auto Baud Status (Low) */ + __I __C uint16_t COMASRL; + }; + __I __C uint8_t RESERVED17[2]; + union { + __I __C uint16_t ASRH; /*!< Auto Baud Status (High) */ + __I __C uint16_t COMASRH; + }; +} ADI_UART_TypeDef; + + +typedef struct _ADI_RTC_TypeDef +{ + __IO uint16_t CR0; /*!< RTC Control 0 */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t SR0; /*!< RTC Status 0 */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t SR1; /*!< RTC Status 1 */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNT0; /*!< RTC Count 0 */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNT1; /*!< RTC Count 1 */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALM0; /*!< RTC Alarm 0 */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ALM1; /*!< RTC Alarm 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t TRM; /*!< RTC Trim */ + __I __C uint8_t RESERVED7[2]; + __O uint16_t GWY; /*!< RTC Gateway */ + __I __C uint8_t RESERVED8[6]; + __IO uint16_t CR1; /*!< RTC Control 1 */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SR2; /*!< RTC Status 2 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t SNAP0; /*!< RTC Snapshot 0 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SNAP1; /*!< RTC Snapshot 1 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t SNAP2; /*!< RTC Snapshot 2 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t MOD; /*!< RTC Modulo */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CNT2; /*!< RTC Count 2 */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ALM2; /*!< RTC Alarm 2 */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t SR3; /*!< RTC Status 3 */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t CR2IC; /*!< RTC Control 2 for Configuring Input Capture Channels */ + __I __C uint8_t RESERVED18[2]; + union { + __IO uint16_t CR3SS; /*!< RTC Control 3 for Configuring SensorStrobe Channel */ + __IO uint16_t CR3OC; + }; + __I __C uint8_t RESERVED19[2]; + union { + __IO uint16_t CR4SS; /*!< RTC Control 4 for Configuring SensorStrobe Channel */ + __IO uint16_t CR4OC; + }; + __I __C uint8_t RESERVED20[2]; + union { + __IO uint16_t SSMSK; /*!< RTC Mask for SensorStrobe Channel */ + __IO uint16_t OCMSK; + }; + __I __C uint8_t RESERVED21[2]; + union { + __IO uint16_t SS1ARL; /*!< RTC Auto-Reload for SensorStrobe Channel 1 */ + __IO uint16_t OC1ARL; + }; + __I __C uint8_t RESERVED22[6]; + __I __C uint16_t IC2; /*!< RTC Input Capture Channel 2 */ + __I __C uint8_t RESERVED23[2]; + __I __C uint16_t IC3; /*!< RTC Input Capture Channel 3 */ + __I __C uint8_t RESERVED24[2]; + __I __C uint16_t IC4; /*!< RTC Input Capture Channel 4 */ + __I __C uint8_t RESERVED25[2]; + union { + __IO uint16_t SS1; /*!< RTC SensorStrobe Channel 1 */ + __IO uint16_t OC1; + }; + __I __C uint8_t RESERVED26[14]; + __I __C uint16_t SR4; /*!< RTC Status 4 */ + __I __C uint8_t RESERVED27[2]; + __I __C uint16_t SR5; /*!< RTC Status 5 */ + __I __C uint8_t RESERVED28[2]; + __I __C uint16_t SR6; /*!< RTC Status 6 */ + __I __C uint8_t RESERVED29[2]; + union { + __I __C uint16_t SS1TGT; /*!< RTC SensorStrobe Channel 1 Target */ + __I __C uint16_t OC1TGT; + }; + __I __C uint8_t RESERVED30[2]; + __I __C uint16_t FRZCNT; /*!< RTC Freeze Count */ +} ADI_RTC_TypeDef; + + +#ifdef __ICCARM__ +#pragma diag_default=Pm093 +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM3029_DEVICE_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h new file mode 100755 index 00000000000..f9a61b742d0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/ADuCM3029_typedefs.h @@ -0,0 +1,122 @@ +/*! + ***************************************************************************** + * @file: ADuCM3029_typedefs.h + * @brief: ADuCM3029 C Register Structures + * @version: $Revision: 36131 $ + * @date: $Date: 2017-01-09 10:00:32 -0500 (Mon, 09 Jan 2017) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2015-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _WRAP_ADUCM3029_TYPEDEFS_H +#define _WRAP_ADUCM3029_TYPEDEFS_H + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Some comments are wrongly identified as code. + * + * Pm093 (rule 18.4): use of union - overlapping storage shall not be used. + * Unions are required by sys/ADUCM302x_typedefs.h. + */ +#pragma diag_suppress=Pm008,Pm093 +#endif /* __ICCARM__ */ + +#if defined (__CC_ARM) +#pragma anon_unions +#endif /* __CC_ARM */ + +#define __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ + +#include + + +/* Redefine ADI_CRYPT_CFG_t with backward compatibility names. */ + +typedef struct _ADI_CRYPT_CFG_t { + union { + struct { + unsigned int BLKEN : 1; /**< Enable BIT for the Crypto Block */ + unsigned int ENCR : 1; /**< Encrypt or Decrypt */ + unsigned int INDMAEN : 1; /**< Enable DMA for Input Buffer */ + unsigned int OUTDMAEN : 1; /**< Enable DMA for Output Buffer */ + unsigned int INFLUSH : 1; /**< Input Buffer Flush */ + unsigned int OUTFLUSH : 1; /**< Output Buffer Flush */ + union { + unsigned int AES_BYTESWAP : 1; /**< Byte Swap 32 Bit AES Input Data */ + unsigned int ENDIAN : 1; + }; + unsigned int reserved7 : 1; + union { + unsigned int AESKEYLEN : 2; /**< Select Key Length for AES Cipher */ + unsigned int KEYLEN : 2; /**< Select Key Length for AES Cipher */ + }; + unsigned int reserved10 : 6; + unsigned int ECBEN : 1; /**< Enable ECB Mode Operation */ + unsigned int CTREN : 1; /**< Enable CTR Mode Operation */ + unsigned int CBCEN : 1; /**< Enable CBC Mode Operation */ + unsigned int CCMEN : 1; /**< Enable CCM/CCM* Mode Operation */ + unsigned int CMACEN : 1; /**< Enable CMAC Mode Operation */ + unsigned int reserved21 : 1; + unsigned int RES : 3; /**< Reserved */ + unsigned int SHA256EN : 1; /**< Enable SHA-256 Operation */ + unsigned int SHAINIT : 1; /**< Restarts SHA Computation */ + unsigned int reserved27 : 1; + unsigned int RevID : 4; /**< Rev ID for Crypto */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CFG_t; + +typedef enum +{ + CRYPT_CFG_LITTLE_ENDIAN = 0, + CRYPT_CFG_BIG_ENDIAN = 1 +} ADI_CRYPT_CFG_ENDIAN; + + +#ifdef __ICCARM__ +#pragma diag_default=Pm008,Pm093 +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM3029_TYPEDEFS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc.c new file mode 100755 index 00000000000..094e53d0485 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc.c @@ -0,0 +1,2385 @@ +/*! ***************************************************************************** + * @file: adi_adc.c + * @brief: ADC device driver global file. + * @details: This file contain the ADC device driver implementation. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/** @addtogroup ADC_Driver ADC Driver + * @{ + * @brief ADC Driver + * @details The ADC driver manages all instances of the ADC peripheral. + * @note - The application must include drivers/adc/adi_adc.h to use this driver. + * @note - This driver also requires the DMA driver. The application must include + the DMA driver sources to avoid link errors. + */ + +#ifndef ADI_ADC_C +/*! \cond PRIVATE */ +#define ADI_ADC_C + +/*============= I N C L U D E S =============*/ + + +/* Header file with definitions specific to ADC driver implementation */ + +/*============= A D C I M P L E M E N T A T I O N S O U R C E F I L E S =============*/ +#include +#include +#include +#include +#include +#include +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors + +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152 +#endif /* __ICCARM__ */ + +#include "adi_adc_def.h" +#include "adi_adc_data.c" + +/*============== D E F I N E S ===============*/ +#ifdef ADI_DEBUG +#define ADI_ADC_INVALID_HANDLE(h) (AdcDevInfo[0].hDevice != (h)) +#endif + +/* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */ +#define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u) + +/* The 12bit maximum sample value */ +#define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u)) + +/*============= C O D E =============*/ + +/*============= D E B U G F U N C T I O N P R O T O T Y P E S =============*/ + +/* Override "weak" default binding in startup_*.c */ +/*! \cond PRIVATE */ +#if defined(__ADUCM302x__) +extern void ADC_Int_Handler(void); +#else +extern void ADC0_Int_Handler(void); +#endif + +/* macro definition for ADuCM3029 */ +#if defined(__ADUCM302x__) +#define BITM_ADC_CFG_VREFVBAT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* VRef VBAT */ +#endif + +extern void DMA_ADC0_Int_Handler (void); + +/*! \endcond */ + +/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */ +/*============= L O C A L F U N C T I O N S P R O T O T Y P E S =============*/ +static uint16_t ReadOutReg(uint32_t nChannelNum); + +/* ADC management functions, based on transfer method */ +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 +static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); +#else +static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); +#endif + +/* Channel helper functions */ +static uint32_t GetNumChannels(uint32_t nChannels); +static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel); + +/* Buffer management functions */ +static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice); +static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice); +static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels); + +/* Internal configuration functions */ +static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable); +static void StaticConfiguration(ADI_ADC_DEVICE *pDevice); + +/*! \endcond */ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Opens an ADC device instance. + * + * @param [in] nDeviceNum Device number to open + * @param [in] pMemory Pointer to a #ADI_ADC_MEMORY_SIZE sized buffer to manage the device + * instance. + * @param [in] nMemorySize Size of the buffer to which "pMemory" points + * @param [out] phDevice Pointer to a location where ADC device handle is to be written. + * + * @return Status + * - #ADI_ADC_SUCCESS Call completed successfully + * - #ADI_ADC_INVALID_DEVICE_NUM [D] Invalid Device Number + * - #ADI_ADC_INSUFFICIENT_MEMORY [D] Memory passed is not sufficient + * - #ADI_ADC_IN_USE [D] ADC driver was already opened + */ +ADI_ADC_RESULT adi_adc_Open ( + uint32_t nDeviceNum, + void *pMemory, + uint32_t nMemorySize, + ADI_ADC_HANDLE *phDevice) +{ + ADI_INT_STATUS_ALLOC(); + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory; + +#ifdef ADI_DEBUG + if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0]))) + { + return ADI_ADC_INVALID_DEVICE_NUM; + } + + if (nMemorySize < ADI_ADC_MEMORY_SIZE) + { + return ADI_ADC_INSUFFICIENT_MEMORY; + } + + if (AdcDevInfo[nDeviceNum].hDevice != NULL) + { + return ADI_ADC_IN_USE; + } + + assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE)); +#endif /* ADI_DEBUG */ + + memset (pMemory, 0, nMemorySize); + + ADI_ENTER_CRITICAL_REGION(); + AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice; + pDevice->pReg = AdcDevInfo[nDeviceNum].pReg; + ADI_EXIT_CRITICAL_REGION(); + + /* Reset the ADC */ + pDevice->pReg->CFG = BITM_ADC_CFG_RST; + + /* Enable the IRQs */ + NVIC_ClearPendingIRQ(ADC0_EVT_IRQn); + NVIC_EnableIRQ(ADC0_EVT_IRQn); + + /* Initialize the registers to known value */ + pDevice->pReg->IRQ_EN = BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE; + + /* Do the static configuration */ + StaticConfiguration(pDevice); + + /* Create a semaphore for buffer management */ + SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS); + + /* Set the default FIFO Manage function */ +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 + pDevice->pfManageFifo = DmaFIFOManage; + /* Make sure the DMA controller and its SRAM based descriptors are initialized */ + adi_dma_Init(); +#else + pDevice->pfManageFifo = InterruptFIFOManage; +#endif + + /* Return the device handle back to the application */ + *phDevice = AdcDevInfo[nDeviceNum].hDevice; + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Close the given device instance + * + * @param [in] hDevice Handle to the device instance + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully closed the device + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle based to the function + */ +ADI_ADC_RESULT adi_adc_Close (ADI_ADC_HANDLE hDevice) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + ADI_ADC_RESULT eResult; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + /* Power down the device */ + if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) { + return eResult; + } + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 + /* Close the DMA if configured */ + NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn); +#endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */ + + /* Disable the ADC interrupt */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + /* Destroy the semaphore */ + SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS); + + /* Finally, zero the device */ + AdcDevInfo[0].hDevice = (NULL); + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Power up ADC + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bPowerUp 'true' to power up and 'false' to power down the ADC. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully closed the device + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain PCLK which is needed to calculate + * powerup values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nClock = 0u; + uint16_t nCount = 0u; + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bPowerUp == true) + { + if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP)) + { + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* We need the cycles equivelent of 20us entered here, based on the PCLK + * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us + * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/ + nCount = (uint16_t)(nClock / 50000u); + + /* Powering up ADC */ + pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP; + + /* Set ADC_PWRUP.WAIT bits for the new count */ + pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) & BITM_ADC_PWRUP_WAIT); + + SET_STATE(ADC_STATUS_POWERED_UP); + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + } + } + else + { + if (IS_IN_STATE(ADC_STATUS_POWERED_UP)) + { + /* If the ADC system is up then disable the ADC subsystem */ + if ( IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) ) + { + eResult = adi_adc_EnableADCSubSystem (hDevice, false); + if (eResult != ADI_ADC_SUCCESS) + { + return eResult; + } + } + + /* Powering down ADC */ + pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP)); + CLR_STATE(ADC_STATUS_POWERED_UP); + } + } + + return eResult; +} + + +/** + * @brief Registering a callback function + * + * @param [in] hDevice Handle to the device instance + * @param [in] pfCallback Function pointer to callback function. Passing a NULL pointer will + * unregister the call back function. + * @param [in] pCBParam Call back function parameter + * + * @details This function registers a call back function. Registered function will be called when + * the given computation is over. It will also be called when the digital comparitor is being + * used and a limit has been broken. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully registerd the callback + * - #ADI_ADC_INVALID_SEQUENCE [D] Callback cannot be registered when ADC is enabled for sampling. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_RegisterCallback ( + ADI_ADC_HANDLE hDevice, + ADI_CALLBACK pfCallback, + void *pCBParam) +{ + ADI_INT_STATUS_ALLOC(); + + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + +#endif /* ADI_DEBUG */ + + ADI_ENTER_CRITICAL_REGION(); + pDevice->pfCallback = pfCallback; + pDevice->pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Enable/Disables the ADC Subsystem + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to Disable` + * + * @details Enables/Disables the ADC Subsystem. The ADC subsystem need to be enabled before using the ADC + * for sampling the signal. The driver should check whether the ADC is ready by calling adi_adc_IsReady + * API before continuing. If internal reference buffer is used as voltage reference then application + * has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled the ADC subsystem + * - #ADI_ADC_INVALID_SEQUENCE [D] Can only be called if the ADC is powered up, + * and cannot be disabled when sampling or using + * the camparator. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_EnableADCSubSystem ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (bEnable == true) { + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + } else { + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= BITM_ADC_CFG_EN; + SET_STATE(ADC_STATUS_SUB_SYSTEM_EN); + } + else + { + pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN); + CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Returns whether the ADC Subsystem is ready + * + * @param [in] hDevice Handle to the device instance + * + +* @param [in] pbReady Pointer to a bool variable. The variable will be set to 'true' if the ADC is ready else 'false' + * + * @details Returns whether the ADC is ready for sampling. This API should be called after enabling the ADC sub-system using + * adi_adc_EnableADCSubSystem API. If internal reference buffer is used as voltage reference then application + * has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the ready status + * - #ADI_ADC_INVALID_SEQUENCE [D] Cannot be called if the subsystem is not enabled. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + * - #ADI_ADC_NULL_POINTER [D] pbReady is NULL + */ + +ADI_ADC_RESULT adi_adc_IsReady ( + ADI_ADC_HANDLE hDevice, + bool *pbReady +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (pbReady == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY)) + { + *pbReady = true; + } + else + { + *pbReady = false; + } + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the Voltage Reference source + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eVrefSrc Voltage Reference source to be used + * + * @details The API can be used to select the voltage reference to be used by the ADC. This option need to be + * set before enabling the ADC subsystem. + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully set the Vref source + * - #ADI_ADC_INVALID_PARAMETER Vref source enum passed is invalid. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle based to the function. + * - #ADI_ADC_INVALID_SEQUENCE [D] VREF cannot be changed once the ADC subsystem is enabled. + */ + +ADI_ADC_RESULT adi_adc_SetVrefSource ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_VREF_SRC eVrefSrc) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT)); + + switch (eVrefSrc) + { + case ADI_ADC_VREF_SRC_INT_1_25_V: + pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL; + break; + + case ADI_ADC_VREF_SRC_INT_2_50_V: + pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN; + break; + + case ADI_ADC_VREF_SRC_VBAT: + pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT; + break; + + case ADI_ADC_VREF_SRC_EXT: + break; + + default: + eResult = ADI_ADC_INVALID_PARAMETER; + break; + } + + return eResult; +} + + +/** + * @brief Enable/Disable Current Sink + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to Disable current sink + * + * @details If the volatage reference is required to sink current then this option need to be enabled. + * The ADC subsystem has the capability to sink upto 50uA at Vref of 1.25V and 100uA at Vref of 2.5V + + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled sink + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + */ + +ADI_ADC_RESULT adi_adc_SinkEnable ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN; + } + else + { + pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Start the ADC calibration + * + * @param [in] hDevice Handle to the device instance + * + * @details The call to this function initiate calibration of the ADC. The user is recommended to do calibration of the ADC after + * enabling the ADC subsystem. The status of the calibration can be checked using adi_adc_IsCalibrationDone API. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully initiated calibration of ADC + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Sampling cannot be enabled if the ADC is enabled. + */ +ADI_ADC_RESULT adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + /* Calibration cannot be done when ADC is processing the buffers */ + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + +#endif /* ADI_DEBUG */ + + /* Clear the calibration done state */ + CLR_STATE(ADC_STATUS_CALIBRATION_DONE); + + /* Clear ADC_STAT.CALDONE */ + pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE; + + /* Set the state as calibration enabled. This state will be cleared when we get the + calibration done interrupt. */ + SET_STATE(ADC_STATUS_CALIBRATION_EN); + + /* Start ADC calibration */ + pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Returns the status of the calibration which was initiated. + * + * @param [in] hDevice Handle to the device instance + * + * @param [out] pbCalibrationDone Pointer to the location to which the status of calibration is written. + * 'true' if the calibration started by call to is done else 'false' + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the status of ADC calibration. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pbCalibrationDone is NULL + */ + +ADI_ADC_RESULT adi_adc_IsCalibrationDone ( + ADI_ADC_HANDLE hDevice, + bool *pbCalibrationDone) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (pbCalibrationDone == NULL) + { + return ADI_ADC_NULL_POINTER; + } +#endif /* ADI_DEBUG */ + + /* The driver will check whether the driver is set to calibration done state. This state will + * be set in the driver when the calibration done interrupt is received by the driver + */ + if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE)) + { + *pbCalibrationDone = true; + } + else + { + *pbCalibrationDone = false; + } + + return ADI_ADC_SUCCESS; +} + + + +/** + * @brief Set the acquisition time of ADC in ADC clock cycles + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nAcqTimeInAClkCycles Acquisition time in ADC clock cycles. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the acquisition time of ADC + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Acquisition time cannot be set when the ADC is enabled for sampling + * - #ADI_ADC_INVALID_PARAMETER [D] nAcqTimeInAClkCycles is not in the valid range + */ +ADI_ADC_RESULT adi_adc_SetAcquisitionTime ( + ADI_ADC_HANDLE hDevice, + uint32_t nAcqTimeInAClkCycles + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + /* A valid range is 1u to the width of the SAMPTIME field + 1. */ + if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME))) + { + return ADI_ADC_INVALID_PARAMETER; + } + +#endif /* ADI_DEBUG */ + + /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */ + nCnvTime = pDevice->pReg->CNV_TIME; + nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME); + nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME); + pDevice->pReg->CNV_TIME = nCnvTime; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the delay time of ADC in ADC cycles for multi iteration mode. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nDelayInAClkCycles Delay time in ADC clock cycles. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set delay time + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] nDelayInAClkCycles is not in the valid range + */ +ADI_ADC_RESULT adi_adc_SetDelayTime ( + ADI_ADC_HANDLE hDevice, + uint32_t nDelayInAClkCycles) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nCnvTime = pDevice->pReg->CNV_TIME; + nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY); + nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY); + pDevice->pReg->CNV_TIME = nCnvTime; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolution + * by oversampling. Averaging will be disabled when the resolution is more than 12-bits. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eResolution Enum of ADC resolution + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the resolution of the ADC. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Resolution cannot be changed when the ADC is enabled for sampling + * - #ADI_ADC_INVALID_STATE [D] Resolution cannot be changed from 12-bit if averaging is enabled + * - #ADI_ADC_INVALID_PARAMETER eResolution parameter passed is invalid. + */ +ADI_ADC_RESULT adi_adc_SetResolution ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_RESOLUTION eResolution) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nFactor; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT)) + { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + switch (eResolution) + { + case ADI_ADC_RESOLUTION_12_BIT: + pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS); + if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) { + pDevice->pReg->AVG_CFG = 0u; + } + CLR_STATE(ADC_STATUS_OVERSAMPLING_EN); + break; + + case ADI_ADC_RESOLUTION_13_BIT: + case ADI_ADC_RESOLUTION_14_BIT: + case ADI_ADC_RESOLUTION_15_BIT: + case ADI_ADC_RESOLUTION_16_BIT: + /* factor = 0x02 for 13-bit + 0x08 for 14-bit + 0x20 for 15-bit + 0x80 for 16-bit */ + nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u)); + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN + | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR); + SET_STATE(ADC_STATUS_OVERSAMPLING_EN); + + break; + + default: + return ADI_ADC_INVALID_PARAMETER; + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Enable Averaging for all ADC channels. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nAveragingSamples Specifies the number of samples used for averaging. The valid value is between 1-256, in the steps of power of 2. 1 is for disabling averaging. + * The averaging require that the resolution of ADC is 12-bit. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled averaging. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Averaging cannot be enabled if the resolution is above 12bits + * - #ADI_ADC_INVALID_PARAMETER [D] nAveragingSamples parameter passed is invalid. + */ +ADI_ADC_RESULT adi_adc_EnableAveraging ( + ADI_ADC_HANDLE hDevice, + uint16_t nAveragingSamples + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nFactor; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u) + /* Or nAveragingSamples is not a power of 2 */ + || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u)) + { + return ADI_ADC_INVALID_PARAMETER; + } + if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN)) + { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + /* Disable averaging */ + if (nAveragingSamples == 1u) + { + pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN); + CLR_STATE(ADC_STATUS_AVGERAGING_EN); + } + else + { + nFactor = nAveragingSamples >> 1; + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR); + SET_STATE(ADC_STATUS_AVGERAGING_EN); + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure low limit for an ADC channel when it is used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the low limit of the digital comparator + * + * @param [in] nLowLimit The low limit of the digital comparator. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured set the low limit. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetLowLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nLowLimit + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) | + (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE); + + /* Now enable this channel comparitor - unused until the comparitor is enabled */ + pDevice->ComparitorLo |= (1u << nChannelNum); + } + else { + pDevice->ComparitorLo &= ~(1u << nChannelNum); + } + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure high limit for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the high limit of the digital comparator + * + * @param [in] nHighLimit The high limit of the digital comparator. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the high limit + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetHighLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHighLimit) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + /* Set the given high value - only relevant if the limit is enabled. */ + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE)) + | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE); + + /* Now enable this channel comparitor - unused until the comparitor is enabled */ + pDevice->ComparitorHi |= (1u << nChannelNum); + } + else { + pDevice->ComparitorHi &= ~(1u << nChannelNum); + } + } + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure hysteresis for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the hysteresis of the digital comparator + * + * @param [in] nHysteresis The hysteresis to be used. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured the comparator + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetHysteresis ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHysteresis) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3 + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE)) + | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE); + + /* Now enable this channel hysteresis - unused until the comparitor is enabled */ + pDevice->ComparitorHys |= (1u << nChannelNum); + } + else { + pDevice->ComparitorHys &= ~(1u << nChannelNum); + } + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] nNumMonitorCycles Number of Monitor cycles before giving interrupt + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured the comparator + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetNumMonitorCycles( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + uint32_t nNumMonitorCycles) +{ + #ifdef ADI_DEBUG + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#endif /* ADI_DEBUG */ + + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3 + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC)) + | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC); + } + return ADI_ADC_SUCCESS; +} + + + +/** + * @brief Enable/Disable digital comparator for the given channel(s) + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnableComparator 'true' to Enable and 'false' to disable + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled digital comparator for the given channels + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Digital comparator cannot be enabled if sampling resolution is more than 12-bit or + * averaging is enabled. Comparator for a given channel cannot be enbaled if none of the limits + * are enabled for the given channel. + * - #ADI_ADC_INVALID_SEQUENCE [D] Comparator cannot be enabled when ADC is enabled for sampling. + * - #ADI_ADC_INVALID_OPERATION [D] Comparator require callback to be registered. + */ +ADI_ADC_RESULT adi_adc_EnableDigitalComparator ( + ADI_ADC_HANDLE hDevice, + bool bEnableComparator +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN)) + { + return ADI_ADC_INVALID_STATE; + } + + if (pDevice->pfCallback == NULL) { + return ADI_ADC_INVALID_OPERATION; + } + + if (bEnableComparator == true) { + if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) { + return ADI_ADC_INVALID_STATE; + } + } +#endif /* ADI_DEBUG */ + + EnableComparator(pDevice, bEnableComparator); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Submit the ADC buffer for processing to the ADC Module + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pBuffer Pointer to the #ADI_ADC_BUFFER structure which contains details + * of the buffers required by the driver. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully submitted the buffer + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pBuffer is NULL + * - #ADI_ADC_INVALID_BUFFER [D] Buffer parameters are invalid. + * + * @note The driver will take ownership of the ADI_ADC_BUFFER structure passed to the driver. + * The application has to make sure the structure is not used and it's scope is valid till + * the structure is returned back to the application. + */ +ADI_ADC_RESULT adi_adc_SubmitBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER* pBuffer +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nNumChannels = 0u; + + ADC_INT_BUFFER* pIntBuffer; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pBuffer == NULL) { + return ADI_ADC_NULL_POINTER; + } + if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u)) + { + return ADI_ADC_INVALID_BUFFER; + } +#endif /* ADI_DEBUG */ + + nNumChannels = GetNumChannels(pBuffer->nChannels); + + pIntBuffer = &pDevice->s_Buffer; + + pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN; + pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK; + if (pBuffer->nNumConversionPasses == 1u) + { + pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN; + } + pIntBuffer->pUserBuffer = pBuffer; + pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer; + pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses; + pIntBuffer->nChannels = pBuffer->nChannels; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Get a processed buffer from the ADC Driver. This function is a blocking call and will only return + * once it has the buffer or if any error occurred. If a callback is registered then any call to this + * function will fail. + * + * @param [in] hDevice Handle to the device instance. + * @param [out] ppBuffer Pointer to a pointer to ADI_ADC_BUFFER structure. The returned pointer + * to ADI_ADC_BUFFER is written here. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the buffer + * - #ADI_ADC_INVALID_STATE adi_adc_GetBuffer cannot be called when no buffer is given to the driver for processing. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_OPERATION [D] adi_adc_GetBuffer cannot be used when callback is registered. + * - #ADI_ADC_NULL_POINTER [D] ppBuffer is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] adi_adc_GetBuffer cannot be used if non-blocking is not enabled. + * + */ +ADI_ADC_RESULT adi_adc_GetBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER **ppBuffer) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (ppBuffer == NULL) { + return ADI_ADC_NULL_POINTER; + } + if (pDevice->pfCallback != NULL) { + return ADI_ADC_INVALID_OPERATION; + } + if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if (pDevice->s_Buffer.pUserBuffer == NULL) { + return ADI_ADC_INVALID_STATE; + } + + /* Wait for read completion */ + SEM_PEND(pDevice, ADI_ADC_ERR_RTOS); + + if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) { + eADCresult = ADI_ADC_BUFFER_OVERFLOW; + } + *ppBuffer = pDevice->s_Buffer.pUserBuffer; + pDevice->s_Buffer.pUserBuffer = NULL; + CLR_STATE(ADC_STATUS_NON_BLOCKING_EN); + + return eADCresult; +} + +/** + * @brief Enable/Disable ADC for sampling + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to disable + * + * @details + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully Enabled or disabled ADC for sampling + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Non-blocking cannot be enabled if comparator is enabled or any blocking API is in progress. + */ +ADI_ADC_RESULT adi_adc_Enable ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) { + /* Set the driver to be in non-blocking mode */ + SET_STATE(ADC_STATUS_NON_BLOCKING_EN); + + /* Enable the IRQs */ + NVIC_EnableIRQ(ADC0_EVT_IRQn); + + /* Try to submit possible number of buffers */ + InitBufferProcessing(pDevice); + } else { + /* Disble the IRQs */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + /* Abort any transaction if present */ + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT); + + CLR_STATE(ADC_STATUS_NON_BLOCKING_EN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief This function return whether a filled buffer is available to be returned to the user. + * If this function return true, then a call to adi_adc_GetBuffer will not block + * + * @param [in] hDevice Handle to the device instance. + * @param [out] pbIsBufferAvailable Pointer to a bool variable to which the availability of buffer will be written. + * The variable will be set to 'true' if buffer is available else 'false' + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the status of the buffer availability + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pbIsBufferAvailable is valid + * - #ADI_ADC_INVALID_OPERATION [D] adi_adc_IsBufferAvailable cannot be used when callback is registered. + * + */ +ADI_ADC_RESULT adi_adc_IsBufferAvailable ( + ADI_ADC_HANDLE hDevice, + bool *pbIsBufferAvailable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pbIsBufferAvailable == NULL) + { + return ADI_ADC_NULL_POINTER; + } + if (pDevice->pfCallback != NULL) { + return ADI_ADC_INVALID_OPERATION; + } +#endif /* ADI_DEBUG */ + + if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) + { + *pbIsBufferAvailable = false; + } + else + { + *pbIsBufferAvailable = true; + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Sample the given channels for the given number of conversion passes and put it into the given buffer. This function only return after + * the channels are sampled the given number of conversion times or if any error occurs. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nChannels Channels to sample. Should be an ORed value of ADI_ADC_CHANNEL types. + * + * @param [in] nNumConversionPasses Number of conversion passes. In one conversion pass, the ADC will sample all the given channel(s) once. + * + * @param [in] pBuffer Pointer to the buffer to which the sampled data is put. + * + * @param [in] nBuffLength Length of the buffer. The length of the buffer should be at least + * 2*(Num of Channels)*nNumConversionPasses bytes. + * + * @details Sample all the given channels for the given number of conversion passes and put the samples values into the given buffers. + * The channels will be sampled starting from the lower number. This function only return after + * the channels are sampled the given number of conversion times or if any error occurs. + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully Enabled or disabled ADC for sampling + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Some parameter passed to the function is not valid + * - #ADI_ADC_INVALID_SEQUENCE [D] adi_adc_ReadChannels cannot be called if camparator is enabled or if + * Non-blocking is enabled or if another blocking API is in progress. + */ + +ADI_ADC_RESULT adi_adc_ReadChannels ( + ADI_ADC_HANDLE hDevice, + uint32_t nChannels, + uint32_t nNumConversionPasses, + void *pBuffer, + uint32_t nBuffLength) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nNumChannels = 0u; + ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS; + + ADC_INT_BUFFER* pIntBuffer; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL)) + { + return ADI_ADC_INVALID_PARAMETER; + } + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + nNumChannels = GetNumChannels(nChannels); + + if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses)) + { + return ADI_ADC_INSUFFICIENT_MEMORY; + } + + /* Clear ADC status */ + pDevice->pReg->STAT = 0xFFFFu; + + /* Set the driver to be in blocking mode */ + SET_STATE(ADC_STATUS_BLOCKING_EN); + + /* Get the buffer */ + pIntBuffer = &pDevice->s_Buffer; + + pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN; + if (nNumConversionPasses == 1u) { + pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN; + } + + pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK; + pIntBuffer->pUserBuffer = NULL; + pIntBuffer->pCurDataBuffer = pBuffer; + pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses; + pIntBuffer->nChannels = nChannels; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT); + + InitBufferProcessing(pDevice); + + /* Wait for read completion */ + SEM_PEND(pDevice, ADI_ADC_ERR_RTOS); + + if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) { + eADCresult = ADI_ADC_BUFFER_OVERFLOW; + } + + /* Driver is no longer in blocking mode */ + CLR_STATE(ADC_STATUS_BLOCKING_EN); + + /* Enable the IRQs */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + return eADCresult; +} + + +/** + * @brief Returns the battery voltage. + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] nRefVoltage Reference voltage in fixed point(16.16) format. + * + * @param [out] pnBatVoltage Pointer to a variable to which the voltage of the battery will be written. + * The battery voltage will be in fixed point (16.16) format. + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the battery voltage. + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain CLK which is needed to calculate + * voltage conversion timing values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pnBatVoltage is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] ADC sub system should be up and ADC should be free for getting the battery voltage. + */ +ADI_ADC_RESULT adi_adc_GetBatteryVoltage ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + uint32_t *pnBatVoltage) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nConvTimeBackup; + uint16_t nAvgCfgBackup; + uint32_t nAdcValue = 0u; + uint32_t nClock = 0u; + uint32_t nACLKDIVCNT; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pnBatVoltage == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* Take the backup of registers that need to be changed */ + nConvTimeBackup = pDevice->pReg->CNV_TIME; + nAvgCfgBackup = pDevice->pReg->AVG_CFG; + + /* Set the required value in the registers. */ + nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + + /* Calculate the number of cycles required for conversion. + * The conversion time required is 500ns = 2000000Hz + */ + nClock = nClock/nACLKDIVCNT; /* nClock = ACLK frequency Hz */ + pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u)); + pDevice->pReg->AVG_CFG = 0u; + + /* Clear the battery done status */ + pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE; + + /* Clear the battery done state */ + CLR_STATE(ADC_STATUS_BATTERY_DONE); + + /* Set the registers */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT); + + /* Wait for the Battery done status */ + while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; } + + /* Clear the conversion register */ + pDevice->pReg->CNV_CFG = 0u; + + /* Restore the changed registers */ + pDevice->pReg->CNV_TIME = nConvTimeBackup; + pDevice->pReg->AVG_CFG = nAvgCfgBackup; + + /* Calculate the battery voltage */ + + /* From HRM: converting ADC result to battery voltage, following calculations should be done: + * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */ + nAdcValue = pDevice->pReg->BAT_OUT; + *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX; + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + + return eResult; +} +/** + * @brief Enable or disable the temperature sensor + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] bEnable 'true' to enable and 'false' to disable the temperature sensor + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled the temperature sensor + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + */ +ADI_ADC_RESULT adi_adc_EnableTemperatureSensor ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN; + SET_STATE(ADC_STATUS_TEMP_SENSOR_EN); + } + else + { + pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN); + CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Return the temperature in fixed point format in degree Celcius. + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] nRefVoltage Reference voltage in fixed point(16.16) format. + * + * @param [out] pnTemperature Pointer to a variable to which the ADC die temperature (in degree Celsius) will be written. + * The temperature will be in fixed point (16.16) format. + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the die temperature + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain CLK which is needed to calculate + * temperature conversion timing values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pnBatVoltage is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] ADC sub system should be up and ADC should be free for getting the battery voltage. The Temperator + * sensor also need to be enabled. + * - #ADI_ADC_INVALID_STATE [D] Temperature sensor require an aquisition time of 65us and that cannot be set with the current + * ACLK since only ACLK of 255 can be stored to the sampling register. Decrease the ACLK clock to + * rectify this. + */ +ADI_ADC_RESULT adi_adc_GetTemperature ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + int32_t* pnTemperature + ) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nConvTimeBackup; + uint16_t nAvgCfgBackup; + uint32_t nAdcTmpValue = 0u; + uint32_t nAdcTmp2Value = 0u; + uint32_t nClock = 0u; + uint32_t nACLKDIVCNT; + uint32_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pnTemperature == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif + + + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* Calculate the conversion time */ + nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u; /* 65us acquisition time required = 15385Hz sample */ + + #ifdef ADI_DEBUG + if (nCnvTime >= 256u) { + return ADI_ADC_INVALID_STATE; + } + #endif + /* Take the backup of registers that need to be changed */ + nConvTimeBackup = pDevice->pReg->CNV_TIME; + nAvgCfgBackup = pDevice->pReg->AVG_CFG; + + /* Set the required value in the registers. */ + + pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME); + pDevice->pReg->AVG_CFG = 0u; + + /* Clear the temperature done status */ + pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE; + + /* Clear the temperature done state */ + CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE); + + /* Sample Tmp register */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP); + while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; } + nAdcTmpValue = pDevice->pReg->TMP_OUT; + pDevice->pReg->CNV_CFG = 0u; + + + /* Sample Tmp2 register */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2); + while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; } + pDevice->pReg->CNV_CFG = 0u; + nAdcTmp2Value = pDevice->pReg->TMP2_OUT; + + /* Restore the changed registers */ + pDevice->pReg->CNV_TIME = nConvTimeBackup; + pDevice->pReg->AVG_CFG = nAvgCfgBackup; + + /* Calculate the temperature voltage. + * From the HRM: Temperature can be calculated as: + * + * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15 + * + * Some of these values are constants, and some have been read from registers. + * The above formula, when populated with variables and constants, would look like this: + * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15 + */ + { + uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */ + + uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */ + uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */ + + uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */ + uint32_t nOffset = (161u * nOffsetPart); /* 12.12 format */ + + uint32_t nTmp3 = ((nAdcTmpValue << 12) - nOffset) << 8u; /* Format 12.20 */ + uint32_t nRatio = (nTmp3/(nTmp2 >> 10u)); /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */ + uint32_t nTemp = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u; /* Temperature in degree kelvin in 16.16 format */ + + int32_t iTemp = (int32_t)nTemp - ((int32_t)17901158); /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */ + *pnTemperature = iTemp; + } + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + + return eResult; +} + + +/*! \cond PRIVATE */ + +/*========== S T A T I C F U N C T I O N S ==========*/ +/* Read the output register for the given channel number */ +static uint16_t ReadOutReg(uint32_t nChannelNum) +{ + const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT; + pOutRegister += nChannelNum*2u; + return *pOutRegister; +} + +/* Init buffer processing */ +static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice) +{ + uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN); + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) + { + /* Clear conversion done flags */ + pDevice->pReg->STAT = 0xFFFFu; + + /* Clear the overflow and alert register */ + pDevice->pReg->OVF = 0xFFFFu; + } + + /* Calculate the conversion register value for the given configuration */ + nCnvReg |= pIntBuffer->nChannels; + if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) { + nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE; + } + if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) { + nCnvReg |= BITM_ADC_CNV_CFG_SINGLE; + } else { + nCnvReg |= BITM_ADC_CNV_CFG_MULTI; + } + + SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED); + + return true; +} + + +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 +/* DMA Callback Handler */ +void DMA_ADC0_Int_Handler (void) +{ + ISR_PROLOG(); + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice; + + DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS); + + ISR_EPILOG(); +} + +static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode) +{ + uint16_t nCount = 0u; + uint16_t chanNum = ADC0_CHANn; + uint16_t IRQ_Backup; + + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if(pDevice->s_Buffer.pCurDataBuffer == NULL) { + /* If there is nothing active... */ + if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) { + /* ...it's something leftover, so cleanup. */ + uint16_t nStat = pDevice->pReg->STAT & 0x00FFu; + FlushFifo(pDevice, (uint32_t)nStat); + pDevice->pReg->STAT = nStat; + } + } + else { + switch (eFifoMode) + { + case ADC_FIFO_MODE_INIT: + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn); + + pADI_DMA0->SRCADDR_CLR = 1U << chanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << chanNum; + + /* Enables peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << chanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << chanNum; /* Should be default */ + + /* Setup the DMA registers */ + nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining; + + /* Point to the end of the DMA source */ + pPrimaryCCD[chanNum].DMASRCEND = (uint32_t)(&(pDevice->pReg->DMA_OUT)); + + /* Point to the end of the DMA write-to destination */ + pPrimaryCCD[chanNum].DMADSTEND = (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u); + + /* Configure the DMA itself */ + pPrimaryCCD[chanNum].DMACDC = ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | /* Increment destination address */ + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | /* Don't increment the source address */ + ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | /* 16bit transfers */ + ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) | /* Data size? */ + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) | /* Basic only */ + ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER)); /* Arbitration */ + + /* Enable DMA */ + pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN; + break; + + case ADC_FIFO_MODE_ENABLED: + break; + + case ADC_FIFO_MODE_INTERRUPT_PROCESS: + /* Clear the status registers */ + pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu); + break; + + case ADC_FIFO_MODE_INTERRUPT_OVERFLOW: + pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW; + break; + + case ADC_FIFO_MODE_DMA_BUFFER_PROCESS: + pIntBuffer->nNumSamplesRemaining = 0u; + ManageFifoCompletion(pDevice); + break; + + case ADC_FIFO_MODE_ABORT: + + /* Take backup of IRQ */ + IRQ_Backup = pDevice->pReg->IRQ_EN; + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + + /* Disable the DMA channel */ + pADI_DMA0->EN_CLR = 1U << chanNum; + + /* Clear the status bits */ + pDevice->pReg->STAT = pDevice->pReg->STAT; + + /* Clear the sampling in progress state */ + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + /* Read and flush all the buffers */ + FlushFifo(pDevice, 0x00FFu); + + /* Restore the IRQ */ + pDevice->pReg->IRQ_EN = IRQ_Backup; + + break; + + default: + break; + } + } + + return ADI_ADC_SUCCESS; +} +#else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */ + +static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode) +{ + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if(pDevice->s_Buffer.pCurDataBuffer == NULL) { + if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) { + uint16_t nStat = pDevice->pReg->STAT & 0x00FFu; + FlushFifo(pDevice, (uint32_t)nStat); + pDevice->pReg->STAT = nStat; + } + return ADI_ADC_SUCCESS; + } + + switch (eFifoMode) + { + case ADC_FIFO_MODE_INIT: + { + /* Enable the conversion done and overflow interrupt */ + pDevice->ActData.nCurChannel = 0u; + } + break; + + case ADC_FIFO_MODE_ENABLED: + break; + + case ADC_FIFO_MODE_INTERRUPT_PROCESS: + { + while (pIntBuffer->nNumSamplesRemaining > 0u) { + uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu); + if ((nConvStatus & 0x00FFu) == 0u) + { + break; + } + + uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel); + while ((nCurChannelBitM & nConvStatus) == 0u) { + pDevice->ActData.nCurChannel++; + if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) { + pDevice->ActData.nCurChannel = 0u; + } + nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel); + } + + assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u); + + *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel); + pIntBuffer->pCurDataBuffer++; + + + pDevice->pReg->STAT = (uint16_t)nCurChannelBitM; + pIntBuffer->nNumSamplesRemaining -= 1u; + + pDevice->ActData.nCurChannel += 1u; + if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) { + pDevice->ActData.nCurChannel = 0u; + } + } + + if (pIntBuffer->nNumSamplesRemaining == 0u) { + ManageFifoCompletion(pDevice); + } + } + break; + + case ADC_FIFO_MODE_INTERRUPT_OVERFLOW: + { + pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW; + } + break; + + case ADC_FIFO_MODE_ABORT: + { + uint16_t IRQ_Backup; + + /* Take backup of IRQ */ + IRQ_Backup = pDevice->pReg->IRQ_EN; + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + + /* Clear the status bits */ + pDevice->pReg->STAT = pDevice->pReg->STAT; + + /* Clear the sampling in progress state */ + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + /* Read and flush all the buffers */ + FlushFifo(pDevice, 0x00FFu); + + /* Restore the IRQ */ + pDevice->pReg->IRQ_EN = IRQ_Backup; + } + break; + + default: + break; + } + + return ADI_ADC_SUCCESS; +} +#endif + +static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels) +{ + uint32_t x; + for (x = 0u; x < 8u; x++) { + if ((nChannels & ((uint32_t)1u << x)) != 0u) { + ReadOutReg(x); + } + } +} + + +/* Called when a transfer is complete */ +static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice) +{ + /* Clear the conversion configuration */ + pDevice->pReg->CNV_CFG = 0u; + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + SEM_POST(pDevice); +} + + +/* Internal function to extract the number of channels + * in a 32bit word. */ +static uint32_t GetNumChannels(uint32_t nChannels) +{ + uint32_t n = nChannels & 0x000000FFu; + + n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u); + n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u); + n = (n + (n >> 4u)) & (0x0000000Fu); + + return n; +} + +/* Returns the channel number based on the ADI_ADC_CHANNEL type. + * i.e. ADI_ADC_CHANNEL1 returns 1. */ +static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel) +{ + int32_t retVal = 0; + uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu; + + if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) { + return -1; + } + if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; } + if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; } + if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; } + + return retVal; +} + +/* Internal function to set static configuration options. */ +static void StaticConfiguration(ADI_ADC_DEVICE *pDevice) +{ + uint16_t nCfgReg = 0u; + + /* Configure the resolution */ +#if ADI_ADC_CFG_RESOLUTION == 12 + pDevice->pReg->AVG_CFG = 0u; +#else + +#if ADI_ADC_CFG_RESOLUTION == 13 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 14 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 15 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 16 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR); +#else +#error "Invalid Resolution" +#endif + + SET_STATE(ADC_STATUS_OVERSAMPLING_EN); +#endif + + /* Configure the VREF */ +#if ADI_ADC_CFG_VREF == 0 /* 1.25V Internal Reference*/ + nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL; +#elif ADI_ADC_CFG_VREF == 1 /* 2.5V Internal Reference */ + nCfgReg |= BITM_ADC_CFG_REFBUFEN; +#elif ADI_ADC_CFG_VREF == 2 /* Battery Voltage */ + nCfgReg |= BITM_ADC_CFG_VREFVBAT; +#endif + + pDevice->pReg->CFG = nCfgReg; + +#if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1 + /* High limit registers */ +#if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1 + pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1 + pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1 + pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1 + pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3; +#endif + /* Low limit registers */ +#if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1 + pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1 + pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1 + pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1 + pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3; +#endif + + /* Hysteresis registers */ +#if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1 + pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1 + pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1 + pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1 + pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3; +#endif +#endif + +} + +/* Internal function to enable the comparitor for previously-configured channels + * Does not set the limits, only enables. +*/ +static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable) +{ + uint32_t x; + uint16_t nCnvCfg = 0u; + volatile uint16_t* pLO_Register[4] = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO}; + volatile uint16_t* pHI_Register[4] = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI}; + volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3}; + + if (bEnable == true) + { + /* Loop round all the channels enabling each part if required. */ + for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) { + if((pDevice->ComparitorHi & (1u << x)) > 0u) { + *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN; + } + if((pDevice->ComparitorLo & (1u << x)) > 0u) { + *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN; + } + if((pDevice->ComparitorHys & (1u << x)) > 0u) { + *pHYS_Register[x] |= BITM_ADC_HYS0_EN; + } + } + nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo); + + pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE); + pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE); + SET_STATE(ADC_STATUS_COMPARATOR_EN); + } + else { + /* Loop round disabling all. */ + for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) { + *pHI_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN)); + *pLO_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN)); + *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN)); + } + pDevice->pReg->CNV_CFG = 0u; + pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu; + CLR_STATE(ADC_STATUS_COMPARATOR_EN); + pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE; + } +} + + +/* In Handler handles the following cases: + * ADI_ADC_EVENT_ADC_READY + * ADI_ADC_EVENT_CALIBRATION_DONE + * ADC_STATUS_BATTERY_DONE + * ADC_STATUS_TMP_DONE + * ADC_STATUS_TMP2_DONE + * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED + * ADI_ADC_EVENT_LOW_LIMIT_CROSSED +*/ +#if defined(__ADUCM302x__) +void ADC_Int_Handler(void) +#else +void ADC0_Int_Handler(void) +#endif +{ + ADI_ADC_DEVICE *pDevice; + ISR_PROLOG(); + + pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice; + + if ((pDevice->pReg->STAT & 0x00FFu) != 0u) { + if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) { + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS); + } else { + pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu); + } + } + if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) { + if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) { + SET_STATE(ADC_STATUS_SUB_SYSTEM_READY); + pDevice->pReg->STAT = BITM_ADC_STAT_RDY; + if (pDevice->pfCallback != NULL) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL); + } + } + if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) { + SET_STATE(ADC_STATUS_CALIBRATION_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE; + if (pDevice->pfCallback != NULL) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL); + } + } + if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) { + SET_STATE(ADC_STATUS_BATTERY_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE; + } + + if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) { + SET_STATE(ADC_STATUS_TMP_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE; + } + + if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) { + SET_STATE(ADC_STATUS_TMP2_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE; + } + } + if (pDevice->pReg->OVF) { + uint16_t nOvrFlowValue = pDevice->pReg->OVF; + if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) { + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW); + } + pDevice->pReg->OVF = nOvrFlowValue; + } + if (pDevice->pReg->ALERT) { + uint32_t nAlertValue = pDevice->pReg->ALERT; + uint32_t channel; + if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) { + for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) { + /* Alert bit positions: hi limits are 0b01, + * lo limit alerts are 0b10. + */ + if((nAlertValue & (1u << (2u * channel))) > 0u) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel); + } + if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u) + { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel); + } + } + } + pDevice->pReg->ALERT = (uint16_t)nAlertValue; + } + ISR_EPILOG(); +} + + +/*! \endcond */ + +#endif /* ADI_ADC_C */ + +/*****/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_data.c new file mode 100755 index 00000000000..7157d9c0a27 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_data.c @@ -0,0 +1,20 @@ +#ifndef ADI_ADC_DATA_C +#define ADI_ADC_DATA_C + +#include +#include +#include +#include "adi_adc_def.h" + +/*! \cond PRIVATE */ + +static ADI_ADC_INFO AdcDevInfo[] = { + { + NULL, + (ADI_ADC_TypeDef*)REG_ADC0_CFG + } +}; + +/*! \endcond */ + +#endif /* ADI_ADC_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_def.h new file mode 100755 index 00000000000..6568f6f277e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adc/adi_adc_def.h @@ -0,0 +1,120 @@ +/*! \cond PRIVATE */ + +#ifndef ADI_ADC_DEF +#define ADI_ADC_DEF + +#include +#include + +#if defined(__ECC__) +#define ALIGN +#define ALIGN4 _Pragma("align(4)") +#elif defined(__ICCARM__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#elif defined (__GNUC__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#endif + + +#define IS_IN_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X)) +#define IS_NOT_IN_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u) +#define IS_IN_ALL_STATES(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X)) +#define IS_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) != 0u) +#define IS_NOT_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u) + +#define SET_STATE(X) (pDevice->nDriverStatus |= (uint32_t)(X)) +#define CLR_STATE(X) (pDevice->nDriverStatus &= ~((uint32_t)(X))) + +#define NUM_ADC_CHANNELS (8u) +#define NUM_ADC_COMPARATOR_CHANNELS (4u) + +/* To keep state for the driver for error checking */ +typedef enum __ADC_STATUS { + ADC_STATUS_POWERED_UP = (1u << 0), + ADC_STATUS_SUB_SYSTEM_EN = (1u << 1), + ADC_STATUS_SUB_SYSTEM_READY = (1u << 2), + + ADC_STATUS_NON_BLOCKING_EN = (1u << 3), + ADC_STATUS_BLOCKING_EN = (1u << 4), + ADC_STATUS_COMPARATOR_EN = (1u << 5), + + ADC_STATUS_SAMPLING_IN_PROGRESS = (1u << 6), + ADC_STATUS_CALIBRATION_EN = (1u << 7), + ADC_STATUS_CALIBRATION_DONE = (1u << 8), + + ADC_STATUS_BATTERY_DONE = (1u << 9), + + ADC_STATUS_OVERSAMPLING_EN = (1u << 10), + ADC_STATUS_AVGERAGING_EN = (1u << 11), + + ADC_STATUS_TEMP_SENSOR_EN = (1u << 12), + + ADC_STATUS_TMP_DONE = (1u << 13), + ADC_STATUS_TMP2_DONE = (1u << 14), +} ADC_STATUS; + +typedef enum __ADC_FIFO_MODE { + ADC_FIFO_MODE_INIT, + ADC_FIFO_MODE_ENABLED, + ADC_FIFO_MODE_INTERRUPT_PROCESS, + ADC_FIFO_MODE_INTERRUPT_OVERFLOW, + ADC_FIFO_MODE_DMA_BUFFER_PROCESS, + ADC_FIFO_MODE_DMA_INVALID_DESC, + ADC_FIFO_MODE_ABORT +} ADC_FIFO_MODE; + +typedef enum __ADC_BUFFER_CONFIG { + ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN = ((uint32_t)1u << 1u), + ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN = ((uint32_t)1u << 0u), +} ADC_BUFFER_CONFIG; + + +typedef enum __ADC_BUFFER_STATUS { + ADC_BUFFER_STATUS_OK = ((uint32_t)1u << 0u), + ADC_BUFFER_STATUS_OVERFLOW = ((uint32_t)1u << 1u) +} ADC_BUFFER_STATUS; + +typedef struct __ADC_INT_BUFFER { + uint16_t nConfig; + uint16_t nStatus; + ADI_ADC_BUFFER *pUserBuffer; + uint16_t* pCurDataBuffer; + uint32_t nNumSamplesRemaining; + uint32_t nChannels; +} ADC_INT_BUFFER; + +typedef struct __ADC_ACTIVE_DATA { + uint32_t nCurChannel; +} ADC_ACTIVE_DATA; + +typedef ADI_ADC_RESULT (*ADC_MANAGE_FIFO_FUNC)(struct __ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); + +typedef struct __ADI_ADC_DEVICE +{ + volatile uint32_t nDriverStatus; + ADI_ADC_TypeDef *pReg; + void* pCBParam; + ADI_CALLBACK pfCallback; + + ADC_ACTIVE_DATA ActData; + ADC_MANAGE_FIFO_FUNC pfManageFifo; + + ADC_INT_BUFFER s_Buffer; + uint8_t ComparitorHi; + uint8_t ComparitorLo; + uint8_t ComparitorHys; + + SEM_VAR_DECLR +} ADI_ADC_DEVICE; + +typedef struct __ADI_ADC_INFO +{ + ADI_ADC_HANDLE hDevice; + ADI_ADC_TypeDef* pReg; +} ADI_ADC_INFO; + +#endif /* ADI_ADC_DEF */ + +/*! \endcond */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_callback.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_callback.h new file mode 100755 index 00000000000..fd2e04f282b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_callback.h @@ -0,0 +1,60 @@ +/*! + ***************************************************************************** + @file: adi_callback.h + @brief: callback APIs. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#ifndef ADI_CALLBACK_H +#define ADI_CALLBACK_H + +#include + +/** + * @brief Device Drivers Callback function definition + */ +typedef void (* ADI_CALLBACK) ( /*!< Callback function pointer */ + void *pCBParam, /*!< Client supplied callback param */ + uint32_t Event, /*!< Event ID specific to the Driver/Service */ + void *pArg); /*!< Pointer to the event specific argument */ + +#endif /* ADI_CALLBACK_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_cyclecount.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_cyclecount.h new file mode 100755 index 00000000000..9e4a82aa2af --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_cyclecount.h @@ -0,0 +1,139 @@ +/* + ******************************************************************************* + * @brief: Framework to preform cycle count measurements + * + * @details this is a framework for monitoring the cycle counts + * for ISRs and APIs. The framework uses systick. + +******************************************************************************* + + Copyright(c) 2016 Analog Devices, Inc. All Rights Reserved. + + This software is proprietary and confidential. By using this software you agree + to the terms of the associated Analog Devices License Agreement. + + ******************************************************************************/ + +#ifndef ADI_CYCLECOUNT_H +#define ADI_CYCLECOUNT_H + +#include +#include +#include + + + /** @addtogroup cyclecount_logging Cycle Counting Framework + * @{ + */ + +/*! + * 64-bit integer to record cycle counts. + * Since UINT32_MAX = 4,294,967,296 cycles + * at 26 MHz this would allow us to record for 165 seconds + * before the system would wrap around. + * By moving to a 64-bit integer we can record for 11,248 years. + */ +typedef uint64_t adi_cyclecount_t; + + +/*! + * The systick timer is a 24-bit count down timer + * The initial value can, therefore, be up to 0xFFFFFF + * The larger the value the fewer interrupts that will be taken + * and the less impact cycle counting will have on the system + */ +#define ADI_CYCLECOUNT_SYSTICKS (0xFFFFFFu) + +/*! + * Cycle counting nesting is supported via a cycle counting stack. The initial + * value of the stack index is one less than the starting stack + * index (0) + */ +#define ADI_CYCLECOUNT_INITIAL_STACK_INDEX (-1) + +/*! + * Cycle Count API function return values. + */ +typedef enum { + + ADI_CYCLECOUNT_SUCCESS, /*!< API completed successfully */ + ADI_CYCLECOUNT_ADD_ENTITY_FAILURE, /*!< There is not enough space in the cycle counting entity array. Consider increasing the size via the #ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS static configuration macro */ + ADI_CYCLECOUNT_INVALID_ID, /*!< The API/ISR ID is invalid. */ + ADI_CYCLECOUNT_FAILURE /*!< API did not complete successfully. */ +} ADI_CYCLECOUNT_RESULT; + + +/*! + * List of cycle counting IDs for the ISRs and APIs that can record cycle counts. + * Items enumerated here must be aligned with adi_cyclecounting_identifiers + * + * Note that the ID numbering starts at 1. ID==0 is not used. + * Note that the application can extend this list via static configuration (see adi_cycle_counting_config.h) and + * via the adi_cyclecount_addEntity() API. + */ +#define ADI_CYCLECOUNT_ISR_EXT_3 1u /*!< Cycle count ID for EXT3 Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_UART 2u /*!< Cycle count ID for UART Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_DMA_UART_TX 3u /*!< Cycle count ID for UART DMA TX Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_DMA_UART_RX 4u /*!< Cycle count ID for UART DMA RX Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_TMR_COMMON 5u /*!< Cycle count ID for Timer Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_RTC 6u /*!< Cycle count ID for RTC Interrupt Handler.*/ +#define ADI_CYCLECOUNT_ISR_SPI 7u /*!< Cycle count ID for SPI Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_CRC 8u /*!< Cycle count ID for CRC Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_SPORT 9u /*!< Cycle count ID for SPORT Interrupt Handler. */ +#define ADI_CYCLECOUNT_ID_COUNT 10u /*!< Number of cycle count ISRs and APIs. Must be one greater than the last ID. */ + + +/*! + * The following are tracked when cycle counting + * Maximum number of cycle counts + * Minimum number of cycle counts + * Average number of cycle counts + */ +typedef struct +{ + adi_cyclecount_t max_cycles_adjusted; /*!< Tracks the adjusted max cycle count */ + adi_cyclecount_t min_cycles_adjusted; /*!< Tracks the adjusted min cycle count */ + adi_cyclecount_t average_cycles_adjusted; /*!< Tracks the adjusted average cycle count */ + + adi_cyclecount_t max_cycles_unadjusted; /*!< Tracks the unadjusted max cycle count */ + adi_cyclecount_t min_cycles_unadjusted; /*!< Tracks the unadjusted min cycle count */ + adi_cyclecount_t average_cycles_unadjusted; /*!< Tracks the unadjusted average cycle count */ + + uint32_t sample_count; /*!< Number of cycle count samples recorded, used to compute the average */ + +} ADI_CYCLECOUNT_LOG; + +/*! + * Cycle counting has to be enabled in the cycle counting configuration file + * If enabled then cycle counting related macros map to the cycle counting APIs. + * If not enabled, then the macros maps to a NOP + */ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) + + #define ADI_CYCLECOUNT_INITIALIZE() adi_cyclecount_init() /*!< Initialize the cycle counting data structures */ + #define ADI_CYCLECOUNT_STORE(id) adi_cyclecount_store(id) /*!< Record the number of cycles for the specified ISR or API */ + #define ADI_CYCLECOUNT_REPORT() adi_cyclecount_report() /*!< Generate a cycle counting report */ + +#else + + #define ADI_CYCLECOUNT_INITIALIZE() do{}while(0) /*!< Initialize the cycle counting data structures */ + #define ADI_CYCLECOUNT_STORE(id) do{}while(0) /*!< Record the number of cycles for the specified ISR or API */ + #define ADI_CYCLECOUNT_REPORT() do{}while(0) /*!< Generate a cycle counting report */ +#endif + + +/* Forward API declarations */ +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_start(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_stop(void); +extern adi_cyclecount_t adi_cyclecount_get(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_store(uint32_t id); +extern void adi_cyclecount_init(void); +extern void adi_cyclecount_report(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_addEntity(const char *EntityName, uint32_t *pid); + +//extern void SysTick_Handler(void); + +/**@}*/ + +#endif /* ADI_CYCLECOUNT_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_processor.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_processor.h new file mode 100755 index 00000000000..46a40e01e7e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_processor.h @@ -0,0 +1,66 @@ +/*! + ***************************************************************************** + * @file: adi_processor.h + * @brief: Include appropriate CMSIS device header. + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ADI_PROCESSOR_H__ +#define __ADI_PROCESSOR_H__ + +#if defined(__ADUCM3029__) +#include +#define __ADUCM302x__ +#endif + +#if defined(__ADUCM3027__) +#include +#define __ADUCM302x__ +#endif + +/* Include CMSIS device header for selected target processor. */ + +#if defined(__ADUCM4050__) +#include +#define __ADUCM4x50__ +#endif + +#endif /* __ADI_PROCESSOR_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_version.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_version.h new file mode 100755 index 00000000000..6dd08f49bb7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/adi_version.h @@ -0,0 +1,63 @@ +/*! + ***************************************************************************** + * @file: adi_version.h + * @brief: Version macros for ADI ADuCMxxx Device Series + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + + THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ADI_VERSION_H__ +#define __ADI_VERSION_H__ + +/* use a 32-bit versioning scheme that supports numerical compares */ +#define ADI_VERSION_MAJOR 1u /* must be <= 255 */ +#define ADI_VERSION_MINOR 0u /* must be <= 255 */ +#define ADI_VERSION_BUILD 0u /* must be <= 255 */ +#define ADI_VERSION_PATCH 0u /* must be <= 255 */ + +#define ADI_CONSTRUCT_VERSION(a,b,c,d) (((a) << 24u) | ((b) << 16u) | ((c) << 8u) | (d)) + +/* known versions */ +#define ADI_VERSION_1_0_0_0 ADI_CONSTRUCT_VERSION(1u,0u,0u,0u) + +/* test current version against known predefines (see SystemInit() example in system.c) */ +#define ADI_VERSION_CURRENT ADI_CONSTRUCT_VERSION(ADI_VERSION_MAJOR, ADI_VERSION_MINOR, ADI_VERSION_BUILD, ADI_VERSION_PATCH) + +#endif /* __ADI_VERSION_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep.c new file mode 100755 index 00000000000..0d0054c432e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep.c @@ -0,0 +1,751 @@ +/*! ***************************************************************************** + * @file: adi_beep.c + * @brief: BEEP device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This included file will be containing BEEP device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#include + +#include +#include + +#include +#include +#include "adi_beep_def.h" + +/** @addtogroup BEEP_Driver BEEP Driver + * @{ + * @brief Beeper Driver + * @note The application must include drivers/beep/adi_beep.h to use this driver. + */ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit. +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function. +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Required for MMR addresses and callback parameters. +* +* Pm031: (MISRA C 2004 rule 12.7) bitwise operations shall not be performed on signed integer types +* Required for MMR manipulations. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Required for adi_beep_PlaySequence() to access the user-supplied array of notes. +* +* Pm141: (MISRA C 2004 rule 11.4) a cast should not be performed between a pointer to object type and a +* different pointer to object type, this casts from type. +* Required to store a an array of varying size in a device structure. +* +* Required for adi_beep_PlaySequence() to access the user-supplied array of notes. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm140,Pm031,Pm152,Pm141 +#endif /* __ICCARM__ */ + +/*========== D A T A ==========*/ +static ADI_BEEP_DRIVER adi_beep_Device[1]; + +/*! \cond PRIVATE */ +/* Handler for the BEEP interrupt */ +void Beep_Int_Handler(void); + +/* debug handle checker */ +#ifdef ADI_DEBUG +#define ADI_BEEP_INVALID_HANDLE(h) (&adi_beep_Device[0] != (h)) +#endif + +/* definition for the BEEP IRQ - there is only ever one instance of the + * BEEP driver, so reducing space by using a #define rather than including + * it in the device structure. */ +#define BEEP_IRQ (BEEP_EVT_IRQn) + +#if ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE == 0 +/* A single note is requested. Only enable the AEND int. */ +#define INTERRUPT_ON_SEQEND (0) +#define INTERRUPT_ON_AEND (1) +#else +/* A two-tone sequence is requested. Only enable the SEQEND int. */ +#define INTERRUPT_ON_SEQEND (1) +#define INTERRUPT_ON_AEND (0) +#endif + +/*! \endcond */ + +static const ADI_BEEP_STATIC_INIT gBeeperStaticConfigData[ADI_BEEP_MAX_DEVID] = { + /* single instance of Beeper device */ + { + /* configuration register */ + ( (INTERRUPT_ON_SEQEND << BITP_BEEP_CFG_SEQATENDIRQ) + | (INTERRUPT_ON_AEND << BITP_BEEP_CFG_AENDIRQ) + | (ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE << BITP_BEEP_CFG_SEQREPEAT) + ), + + /* Status register (interrupt clears) */ + (ADI_BEEP_ALL_INTERRUPTS), + + /* ToneA control register */ + ( ((uint32_t)ADI_BEEP_TONEA_DISABLE << BITP_BEEP_TONEA_DIS) + | ((uint32_t)ADI_BEEP_TONEA_FREQUENCY << BITP_BEEP_TONEA_FREQ) + | ((uint32_t)ADI_BEEP_TONEA_DURATION << BITP_BEEP_TONEA_DUR) + ), + + /* ToneB control register */ + ( ((uint32_t)ADI_BEEP_TONEB_DISABLE << BITP_BEEP_TONEB_DIS) + | ((uint32_t)ADI_BEEP_TONEB_FREQUENCY << BITP_BEEP_TONEB_FREQ) + | ((uint32_t)ADI_BEEP_TONEB_DURATION << BITP_BEEP_TONEB_DUR) + ) + } +}; + +/*! \endcond */ + + +/*! + * @brief BEEP Initialization + * + * @param[in] DeviceNum Integer specifying the ID of Beeper to use. + * @param[in] pMemory Pointer to the memory to be used by the driver. + * Size of the memory should be at least #ADI_BEEP_MEMORY_SIZE bytes. + * @param[in] MemorySize Size of the memory passed in pMemory parameter. + * @param[out] phDevice Pointer to a location that the device data pointer + * will be written upon successful initialization. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: BEEP device driver initialized successfully. + * - #ADI_BEEP_SEMAPHORE_FAILED The BEEP sempahore could not be created. + * - #ADI_BEEP_ALREADY_INITIALIZED [D] The BEEP is already initialized. + * - #ADI_BEEP_NULL_PTR [D] Null pointer. + * - #ADI_BEEP_BAD_DEV_ID [D] The device number is invalid. + * + * Initialize the BEEP device for use. The core NVIC BEEP interrupt is enabled. This API + * must preceed all other beeper API calls and the handle returned must be passed to all other beeper API + * calls. + * + * + * @note The contents of \a phDevice will be set to NULL upon failure.\n\n + * + * @note The BEEP device driver will clear all pending interrupts and disable all beeper + * interrupts during beeper device initialization. + * + * @note CALLBACKS: If a callback is registered, it will be called on + * completion of the note or sequence. The "Event" parameter will + * contain which event occurred, either ADI_BEEP_INTERRUPT_SEQUENCE_END + * or ADI_BEEP_INTERRUPT_NOTE_END. + * + * @warning This API will put the beeper in preconfigured mode as defined in + * adi_beep_config.h file. + * Refer adi_beep_config.h file to see which all features can be preconfigured. + * + * @sa adi_beep_Close(). + */ +ADI_BEEP_RESULT adi_beep_Open(ADI_BEEP_DEV_ID const DeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_BEEP_HANDLE* const phDevice) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_DEV_DATA *pData; + /* store a bad handle in case of failure */ + *phDevice = (ADI_BEEP_HANDLE) NULL; + +#ifdef ADI_DEBUG + if (DeviceNum >= ADI_BEEP_MAX_DEVID) + { + return ADI_BEEP_BAD_DEV_ID; + } + + if (pMemory == NULL) + { + return ADI_BEEP_NULL_PTR; + } + + assert (MemorySize >= sizeof(ADI_BEEP_DRIVER)); +#endif + + /* local pointer to instance data */ + pDevice = &adi_beep_Device[DeviceNum]; + pDevice->pReg = pADI_BEEP0; + pDevice->pData = (ADI_BEEP_DEV_DATA*)pMemory; + pData = pDevice->pData; + +#ifdef ADI_DEBUG + if (ADI_BEEP_STATE_UNINITIALIZED != adi_beep_Device[DeviceNum].pData->state) + { + return ADI_BEEP_ALREADY_INITIALIZED; + } +#endif + + pData->cbFunc = NULL; + pData->cbParam = NULL; + SEM_CREATE(pDevice->pData, "BEEP_SEM", ADI_BEEP_SEMAPHORE_FAILED); + + /* set statically configured initialization data */ + ADI_BEEP_STATIC_INIT const* pInitData = &gBeeperStaticConfigData[DeviceNum]; + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + + pReg->CFG = pInitData->BEEP_CFG; + pReg->STAT = pInitData->BEEP_STAT; + pReg->TONEA = pInitData->BEEP_TONEA; + pReg->TONEB = pInitData->BEEP_TONEB; + + /* enable beeper interrupts in NVIC */ + NVIC_EnableIRQ(BEEP_IRQ); + + /* mark driver initialized */ + pData->state = ADI_BEEP_STATE_INITIALIZED; + + /* store handle at application handle pointer */ + *phDevice = (ADI_BEEP_HANDLE)pDevice; + + return ADI_BEEP_SUCCESS; /* initialized */ +} + + +/*! + * @brief Uninitialize and deallocate a BEEP device. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Uninitialize and release an allocated BEEP device for other use. The core NVIC BEEP interrupt is disabled. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Close(ADI_BEEP_HANDLE const hDevice) +{ + + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_DEV_DATA *pData; + ADI_BEEP_TypeDef *pReg; + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pData = pDevice->pData; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) + { + return ADI_BEEP_BAD_DEV_HANDLE; + } + if (ADI_BEEP_STATE_UNINITIALIZED == pData->state) + { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ(BEEP_IRQ); + + pData->state = ADI_BEEP_STATE_UNINITIALIZED; + pData->cbFunc = NULL; + pReg->CFG = 0u; + pReg->STAT = 0u; + pReg->TONEA = 0u; + pReg->TONEB = 0u; + SEM_DELETE(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED); + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Register a callback for the beeper driver. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] pfCallback The application supplied callback which will be called to notify device + * related events. + * @param[in] pCBParam The application supplied callback parameter which can be passed back in + * the callback function. + * + * @return Status + * - #ADI_BEEP_SUCCESS Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_beep_Open(). + * + * Registers a callback for the beeper interrupts. When an interrupt occurs, the + * driver will handle any required interaction with the hardware and then call + * the registered callback. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_RegisterCallback(ADI_BEEP_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void* const pCBParam) +{ + ADI_BEEP_DRIVER *pDevice = (ADI_BEEP_DRIVER*)hDevice; + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + /* Assign the callback within a critical region. */ + ADI_ENTER_CRITICAL_REGION(); + pDevice->pData->cbFunc = pfCallback; + pDevice->pData->cbParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + + +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 +/*! + * @brief Play a beeper tone sequence. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] aSequence The sequence of notes to be played by the beeper. + * @param[in] count The number of notes in the sequence, must be a multiple + * of two, and a maximum size of 254 notes. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_INVALID_COUNT Sequence count must be multiples of two. + * - #ADI_BEEP_NULL_PTR [D] Null pointer. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the A/B tone pair to play a sequence of notes. The sequnce can be + * stopped by calling adi_beep_Enable(..., false). The beeper will be enabled + * and disabled internally by the driver. This code, and supporting data, can + * be removed by setting ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 0 in the + * adi_beep_config.h configuration file. + * + * @sa adi_beep_Open(). + * @sa adi_beep_Enable() + */ +ADI_BEEP_RESULT adi_beep_PlaySequence(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE aSequence[], + uint8_t count) +{ + ADI_BEEP_DRIVER *pDevice = (ADI_BEEP_DRIVER*)hDevice; + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + uint16_t nSeqCnt = 0u; + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } + + if (NULL == aSequence) { + return ADI_BEEP_NULL_PTR; + } + + /* The sequence count must be a multiple of two, be greater than 1 + * and must be a maximum of (127 * 2) notes in length. The hardware supports a + * sequence of up to 127, and there are two notes associated with that. */ + if (((127u * 2u) < count) || + ((count % 2u) != 0u) || + (count < 2u)) { + return ADI_BEEP_INVALID_COUNT; + } +#endif + + /* Two notes are loaded at a time, and the sequence count refers to + * the number of times that both tone registers should be played. */ + nSeqCnt = ((uint16_t)count) >> 1u; + + ADI_ENTER_CRITICAL_REGION(); + + /* make a hole, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ | BITM_BEEP_CFG_EN); + + pReg->TONEA = ( (uint16_t)((uint16_t)aSequence[0].frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)aSequence[0].duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)aSequence[1].frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)aSequence[1].duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | + BITM_BEEP_CFG_BSTARTIRQ | + BITM_BEEP_CFG_SEQATENDIRQ | + (uint16_t)((uint16_t)(nSeqCnt) << BITP_BEEP_CFG_SEQREPEAT)); + + pDevice->pData->pSeqArray = (ADI_BEEP_NOTE(*)[])aSequence; + pDevice->pData->nSeqMax = count; + pDevice->pData->nSeqIndex = 2u; + + /* We're now playing, but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} +#endif + +/*! + * @brief Play a single note/beep. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] note The note to play. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the A tone to play a single note. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_PlayNote(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE note) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + /* Clear any previous sequence setup, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_EN); + + /* Set Tone A */ + pReg->TONEA = ( (uint16_t)((uint16_t)note.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)note.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_AENDIRQ); + + /* We're now playing but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + + +/*! + * @brief Play a a repeating two-tone beep. Similar to an alarm. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] noteA The note to play first. + * @param[in] noteB The note to play second. + * @param[in] count The number of times to repeat the two-note signal, + * maximum of 127. + * + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the beeper to play a repeating two-tone signal. + * The count argument refers to the number of iterations of both notes, not + * just a single note. + * + * @sa adi_beep_Open(). + * @sa adi_beep_PlayNote(). + * @sa adi_beep_PlayNSequence(). + */ +ADI_BEEP_RESULT adi_beep_PlayTwoTone(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE noteA, + ADI_BEEP_NOTE noteB, + uint8_t count) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + /* make a hole, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ |BITM_BEEP_CFG_EN); + + pReg->TONEA = ( (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_SEQATENDIRQ |(uint16_t)((uint16_t)count << BITP_BEEP_CFG_SEQREPEAT)); + + /* We're now playing but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Enable or disable the beeper. Other APIs will automatically enable the beeper if required, + * so this function is best used in the following situations: + * - when only using static configuration, i.e. start playing the notes + * set up in static adi_beep_config.h. + * - Otherwise, this can be used to stop the beeper during playback, + * when started from any other API. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] bFlag true to enable the device, false to stop playback. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Enable(ADI_BEEP_HANDLE const hDevice, bool const bFlag) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + if (bFlag == true) { + /* All the registers should already be set - just enable the beep */ + pReg->CFG |= BITM_BEEP_CFG_EN; + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + } + else { + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_EN); + pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING); + } + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Wait for the current playback to finish. This is a blocking call, + * that will not return until the current playback (if any) has finished. + * If there is no current playback, it will return immediately. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_FAILURE Error: Semaphore failure. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Wait(ADI_BEEP_HANDLE const hDevice) +{ + ADI_BEEP_DRIVER *pDevice; + bool wait = false; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + if((pDevice->pData->state | ADI_BEEP_STATE_PLAYING) > 0u) { + /* We are going to pend on the semaphore, no matter what. */ + pDevice->pData->state |= ADI_BEEP_STATE_BLOCKED; + wait = true; + } + + ADI_EXIT_CRITICAL_REGION(); + + if(wait == true) { + /* Wait for the completion interrupt to post */ + SEM_PEND(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED); + } + + return ADI_BEEP_SUCCESS; +} + +/*! \cond PRIVATE */ + +/*! @brief BEEP device driver interrupt handler. Overrides weakly-bound + * default interrupt handler in the startup file. */ +void Beep_Int_Handler(void) +{ + ISR_PROLOG(); +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + ADI_BEEP_DEV_DATA *pData; + ADI_BEEP_NOTE noteA, noteB; +#endif + ADI_BEEP_DRIVER *pDevice = &adi_beep_Device[ADI_BEEP_DEVID_0]; /* so far, there is only one BEEP, so this is safe */ + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + uint16_t fired = ADI_BEEP_ALL_INTERRUPTS; + register uint16_t candidate; + + /* Make sure our driver is up and running. */ + if (ADI_BEEP_STATE_UNINITIALIZED != pDevice->pData->state) { + + /* read both status and mask registers */ + candidate = pReg->CFG & ADI_BEEP_ALL_INTERRUPTS; /* Take the fired interrupts */ + fired = candidate; /* ...and a copy. */ + candidate = candidate & pReg->STAT; /* ...and remove the unused set interrupt bits */ + + /* From this driver's perspective, there are only two states + * to watch for - finished playing, or continuing the playing sequence. + * Finished will be handled here. */ + if((candidate & (BITM_BEEP_CFG_SEQATENDIRQ | BITM_BEEP_CFG_AENDIRQ)) > 0u) { + + /* If we are blocked, unblock by posting the semaphore */ + if((pDevice->pData->state | ADI_BEEP_STATE_BLOCKED) > 0u) { + SEM_POST(pDevice->pData); + } + + /* Reset the device playing status. */ + pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING | ADI_BEEP_STATE_BLOCKED); + + /* ...and disable the device. */ + pReg->CFG &= (uint16_t)(~(BITM_BEEP_CFG_EN)); + + /* forward the interrupt to the user if they are watching it and it has fired */ + /* pass the interrupt as the event. */ + if (pDevice->pData->cbFunc != NULL) { + pDevice->pData->cbFunc (pDevice->pData->cbParam, (uint32_t)candidate, NULL); + } + } + + #if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + /* The second state is if we are playing a longer sequence, so this + * interrupt may be to move the sequence along. */ + if ((BITM_BEEP_CFG_BSTARTIRQ & candidate) != 0u) { + + /* Get a local copy of data, to shorten the following code. */ + pData = pDevice->pData; + + /* If there's still data to play */ + if(pData->nSeqIndex < pData->nSeqMax) { + /* Move the sequence along.*/ + noteA = (*pData->pSeqArray)[pData->nSeqIndex]; + pData->nSeqIndex++; + noteB = (*pData->pSeqArray)[pData->nSeqIndex]; + pData->nSeqIndex++; + + /* Any values written will not impact the current tones, + * they will take effect after the current tone is completed */ + pReg->TONEA = ( (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + | (uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + | (uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + } + } +#endif + } + + /* clear the watched interrupt(s) that fired */ + pReg->STAT |= (uint16_t)(fired & ADI_BEEP_ALL_INTERRUPTS); /* only write allowed interrupt bits */ + ISR_EPILOG(); +} +/*! \endcond */ + +/*@}*/ + + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep_def.h new file mode 100755 index 00000000000..22e0b3a949c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/beep/adi_beep_def.h @@ -0,0 +1,128 @@ +/*! + ***************************************************************************** + * @file: adi_beep_def.h + * @brief: BEEP Device Driver definition + *----------------------------------------------------------------------------- + * + * Copyright (c) 2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _ADI_BEEP_DEF_H_ +#define _ADI_BEEP_DEF_H_ + +/*! \cond PRIVATE */ +#include + +/*! + ***************************************************************************** + * An interrupt mask covering all Beeper interrupts. + *****************************************************************************/ +#define ADI_BEEP_ALL_INTERRUPTS ( BITM_BEEP_CFG_SEQATENDIRQ \ + | BITM_BEEP_CFG_SEQNEARENDIRQ \ + | BITM_BEEP_CFG_BENDIRQ \ + | BITM_BEEP_CFG_BSTARTIRQ \ + | BITM_BEEP_CFG_AENDIRQ \ + | BITM_BEEP_CFG_ASTARTIRQ) + +#define ADI_BEEP_TONE_DISABLE (BITM_BEEP_TONEA_DIS) /*!< Beeper tone disable bit */ + +#define ADI_BEEP_TONE_FREQ_BITPOS (BITP_BEEP_TONEA_FREQ) /*!< Beeper tone frequency bitfield position */ +#define ADI_BEEP_TONE_DUR_BITPOS (BITP_BEEP_TONEA_DUR) /*!< Beeper tone duration bitfield position */ + +#define ADI_BEEP_TONE_FREQ_MASK (BITM_BEEP_TONEA_FREQ) /*!< Beeper tone frequency bitfield mask */ +#define ADI_BEEP_TONE_DUR_MASK (BITM_BEEP_TONEA_DUR) /*!< Beeper tone duration bitfield mask */ + +/*! + ***************************************************************************** + * ADI_BEEP_STATE + * + * BEEP driver state. Used for internal tracking of the BEEP device initialization + * progress during the adi_beep_Open(). Also used to insure the BEEP device has been + * properly initialized as a prerequisite to using the balance of the BEEP API. + * + *****************************************************************************/ +typedef uint8_t ADI_BEEP_STATE; +#define ADI_BEEP_STATE_UNINITIALIZED 0u /*!< BEEP is not initialized. */ +#define ADI_BEEP_STATE_INITIALIZED (1u << 1u) /*!< BEEP is initialized. */ +#define ADI_BEEP_STATE_PLAYING (1u << 2u) /*!< BEEP is currently playing. */ +#define ADI_BEEP_STATE_BLOCKED (1u << 3u) /*!< BEEP has blocked, waiting completion. */ + +/*! + * \struct ADI_BEEP_DEV_DATA + * Beeper device internal instance data structure. + */ +typedef struct _ADI_BEEP_DEV_DATA +{ + volatile ADI_BEEP_STATE state; /*!< Device state */ + ADI_CALLBACK cbFunc; /*!< Callback function */ + void *cbParam; /*!< Callback parameter */ +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + ADI_BEEP_NOTE (*pSeqArray)[]; /*!< Pointer to a user-allocated array of notes. */ + volatile uint8_t nSeqIndex; /*!< Index for incrementing sequence */ + uint8_t nSeqMax; /*!< Size of the sequence */ +#endif + SEM_VAR_DECLR +} ADI_BEEP_DEV_DATA; + + +/*! \struct ADI_BEEP_DRIVER_STRUCT + * BEEP Device Structure + */ +typedef struct _ADI_BEEP_DRIVER_STRUCT +{ + ADI_BEEP_TypeDef *pReg; /*!< Pointer to register base */ + ADI_BEEP_DEV_DATA *pData; /*!< Pointer to device data structure */ +} ADI_BEEP_DRIVER_STRUCT; + +/*! \struct ADI_BEEP_STATIC_INIT + * conditionally create static initialization data based on adi_beep_config.h settings + */ +typedef struct { + uint16_t BEEP_CFG; /*!< Beeper configuration register */ + uint16_t BEEP_STAT; /*!< Beeper status register */ + uint16_t BEEP_TONEA; /*!< Beeper ToneA register */ + uint16_t BEEP_TONEB; /*!< Beeper ToneB register */ +} ADI_BEEP_STATIC_INIT; + +/* alias for the actual device structure */ +typedef ADI_BEEP_DRIVER_STRUCT ADI_BEEP_DRIVER; + +/*! \endcond */ + +#endif /* _ADI_BEEP_DEF_H_ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/common.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/common.h new file mode 100755 index 00000000000..30eb56d97d1 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/common.h @@ -0,0 +1,128 @@ +/*! + ***************************************************************************** + * @file: common.h + * @brief: Common include file for all example + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + + +#ifndef COMMON_H +#define COMMON_H + +#ifdef __ICCARM__ +/* +* Pm106 (rule 20.9): the input/output library shall not be used in + production code +* The purpose of this header is to provide I/O facilities based on stdio. +*/ +#pragma diag_suppress=Pm106 +#endif /* __ICCARM__ */ + +#include +#include +#include +#include +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): The basic types of char, int, short, long, float shall not be used. +* Pm064 (rule 16.1): functions with variable number of arguments shall not be used. +*/ +#pragma diag_suppress=Pm011,Pm064 +#endif /* __ICCARM__ */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Enable REDIRECT_OUTPUT_TO_UART to send the output to UART terminal. +This requires the UART Driver(adi_uart.c) to be included in the project */ +/* #define REDIRECT_OUTPUT_TO_UART */ + +extern char aDebugString[150]; + +#ifdef __ICCARM__ +/* +* Pm154 (rule 19.10): in the definition of a function-like macro, each instance +* of a parameter shall be enclosed in parentheses +* The __VA_ARGS__ macro cannot be enclosed in parentheses. +*/ +#pragma diag_suppress=Pm154 +#endif /* __ICCARM__ */ + +#define DEBUG_MESSAGE(...) \ + do { \ + sprintf(aDebugString,__VA_ARGS__); \ + common_Perf(aDebugString); \ + } while(0) + +#ifdef __ICCARM__ +#pragma diag_default=Pm154 +#endif /* __ICCARM__ */ + +#define DEBUG_RESULT(s,result,expected_value) \ + do { \ + if ((result) != (expected_value)) { \ + sprintf(aDebugString,"%s %d", __FILE__,__LINE__); \ + common_Fail(aDebugString); \ + sprintf(aDebugString,"%s Error Code: 0x%08X\n\rFailed\n\r",(s),(result)); \ + common_Perf(aDebugString); \ + exit(0); \ + } \ + } while (0) + +/******************************************************************************** +* API function prototypes +*********************************************************************************/ +void common_Init(void); +void common_Pass(void); +void common_Fail(char *FailureReason); +void common_Perf(char *InfoString); + +#ifdef __cplusplus +} +#endif + +#endif /* COMMON_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_adc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_adc_config.h new file mode 100755 index 00000000000..527c172d706 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_adc_config.h @@ -0,0 +1,342 @@ +/*! + ***************************************************************************** + @file: adi_adc_config.h + @brief: Configuration options for ADC driver. + This is specific to the ADC driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_ADC_CONFIG_H +#define ADI_ADC_CONFIG_H +#include +/** @defgroup ADC_Driver_Cfg Static Configuration + * @ingroup ADC_Driver + */ + +/** @addtogroup ADC_Driver_Cfg Static Configuration +* @{ +*/ + +/************* ADC Driver configurations ***************/ + + +/*! Configure the default ADC configuration. Oversampling support must be enabled for resolution >12-bits.\n + Valid values are 12 to 16 +*/ +#define ADI_ADC_CFG_RESOLUTION (12) + +/*! Configure the default Vref\n + 3 - External Reference + 2 - Battery Voltage + 1 - 2.5V Internal Reference\n + 0 - 1.25V Internal Reference\n + +*/ +#define ADI_ADC_CFG_VREF (1) + +/*! Enable/Disable MULTI acquisitions of ADC data. + When enabled, DMA will be used for ADC readings which is + the preferred transfer method for multiple transactions. + Otherwise all will be interrupt driven. \n + 1 - Enable MULTI (DMA) acquisitions \n + 0 - Disable MULTI (use Interrupt) acquisitions \n +*/ +#define ADI_ADC_ENABLE_MULTI_ACQUIRE (1) + +/*! Enable/Disable HI/LO Digital Comparator limits \n + 1 - Enable HI/LO Digital Comparator limits\n + 0 - Disable HI/LO Digital Comparator limits\n +*/ +#define ADI_ADC_ENABLE_STATIC_COMPARATOR (0) + +/*! Enable/Disable Channel0 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HI_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel0 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel0 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel0 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel1 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel1 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel1 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel1 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel2 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel2 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel2 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel2 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel3 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel3 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel3 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel3 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC (0) /* 3 bits, 0 to 7 */ + + +/************** Macro validation *****************************/ + +#if (ADI_ADC_CFG_RESOLUTION < 12) || (ADI_ADC_CFG_RESOLUTION > 16) +#error "ADI_ADC_CFG_RESOLUTION is invalid" +#endif + +#if (ADI_ADC_CFG_VREF < 0) || (ADI_ADC_CFG_VREF > 3) +#error "ADI_ADC_CFG_VREF is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN0_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN0_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN1_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN2_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN0_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN1_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN2_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN0_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN1_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN2_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN3_HYS_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN0_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN1_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN2_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN3_HYS_CYC is invalid" +#endif + + + + +/*! @} */ + +#endif /* ADI_ADC_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_beep_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_beep_config.h new file mode 100755 index 00000000000..a78814b0c72 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_beep_config.h @@ -0,0 +1,164 @@ +/*! + ***************************************************************************** + @file: adi_beep_config.h + @brief: Configuration options for BEEP driver. + This is specific to the BEEP driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_BEEP_CONFIG_H +#define ADI_BEEP_CONFIG_H +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * IAR compiler supports longer identifiers. + */ +#pragma diag_suppress=Pm009 +#endif /* __ICCARM__ */ + +/** @addtogroup BEEP_Driver_Config Static Configuration + * @ingroup BEEP_Driver + * @{ + */ + +/************* BEEP Driver configurations ***************/ +/*! Enable the inclusion of adi_beep_PlaySequence(). This \n + API requires more data in the device structures to manage \n + the longer playing sequences, along with extra code in \n + the interrupt handler. \n + 0 - adi_beep_PlaySequence() omitted.\n + 1 - adi_beep_PlaySequence() is included. */ +#define ADI_BEEP_INCLUDE_PLAY_SEQUENCE 1 + +/************* BEEP controller static configurations ***************/ + +/*! Configure beeper disable.\n + 0 - Beeper enabled.\n + 1 - Beeper disabled. */ +#define ADI_BEEP_CFG_BEEPER_DISABLE 0 + +/*! Configure beeper sequence, when using static configuration. \n + 0 - Single note (Tone A only).\n + 1-255 - Sequence mode repeat count (Tone A then B sequentially). */ +#define ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE 5 + + +/* TONEA CONTROL REGISTER */ + +/*! Initial ToneA Disable.\n + 0 - ToneA Enabled.\n + 1 - ToneA Disabled. */ +#define ADI_BEEP_TONEA_DISABLE 0 + +/*! Initial ToneA Frequency.\n + 0-3 - Rest Tone (no oscillation).\n + 4-127 - Oscillate at 32kHz/freq Hz. */ +#define ADI_BEEP_TONEA_FREQUENCY 20 + +/*! Initial ToneA Duration.\n + 0-254 - Play for 4ms*duration.\n + 255 - Play for infinite duration. */ +#define ADI_BEEP_TONEA_DURATION 2 + + + +/* TONEB CONTROL REGISTER */ + +/*! Initial ToneB Disable.\n + 0 - ToneB Enabled.\n + 1 - ToneB Disabled. */ +#define ADI_BEEP_TONEB_DISABLE 0 + +/*! Initial ToneB Frequency. \n + 0-3 - Rest Tone (no oscillation).\n + 4-127 - Oscillate at 32kHz/freq Hz. */ +#define ADI_BEEP_TONEB_FREQUENCY 50 + +/*! Initial ToneB Duration.\n + 0-254 - Play for 4ms*duration.\n + 255 - Play for infinite duration. */ +#define ADI_BEEP_TONEB_DURATION 2 + + + +#ifdef __ICCARM__ +/* +* Pm085 (rule 19.11): identifiers in pre-processor directives should be defined before use +* The macros in the the following #if directives are defined to enum constants by default. +*/ +#pragma diag_suppress=Pm085 +#endif /* __ICCARM__ */ + +#if (ADI_BEEP_TONEA_DISABLE > 1) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEA_FREQUENCY > 127 ) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEA_DURATION > 255 ) +#error "Invalid configuration" +#endif + +#if (ADI_BEEP_TONEB_DISABLE > 1) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEB_FREQUENCY > 127 ) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEB_DURATION > 255 ) +#error "Invalid configuration" +#endif + +#ifdef __ICCARM__ +#pragma diag_default=Pm009,Pm085 +#endif /* __ICCARM__ */ + +/*! @} */ + +#endif /* ADI_BEEP_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crc_config.h new file mode 100755 index 00000000000..19737e3a883 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crc_config.h @@ -0,0 +1,100 @@ +/*! + ***************************************************************************** + @file: adi_crc_config.h + @brief: Configuration options for CRC driver. + This is specific to the CRC driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_CONFIG_H +#define ADI_CRC_CONFIG_H + +#include + +/** @defgroup CRC_Driver_Cfg Static Configuration + * @ingroup CRC_Driver + */ + +/** @addtogroup CRC_Driver_Cfg Static Configuration +* @{ +*/ + +/************* CRC Driver configurations ***************/ +/*! + Enable DMA support in the driver code.\n + 1 - To have the DMA support code in the driver.\n + 0 - To eliminate the DMA support. Operates in core mode.\n +*/ +#define ADI_CRC_CFG_ENABLE_DMA_SUPPORT 0 + +/*! + Enable Byte mirroring option\n + 1 - To enable byte mirroring \n + 0 - To disable the byte mirroring. +*/ +#define ADI_CFG_CRC_ENABLE_BYTE_MIRRORING 0 +/*! + Enable Bit mirroring option\n + 1 - To enable bit mirroring \n + 0 - To disable the bit mirroring. +*/ +#define ADI_CFG_CRC_ENABLE_BIT_MIRRORING 0 + +/*! + To specify the seed value for CRC computation +*/ + +#define ADI_CFG_CRC_SEED_VALUE (0xFFFFFFFFu) + +/*! + To specify the polynomial to be used for CRC computation +*/ +#define ADI_CFG_CRC_POLYNOMIAL (0x04C11DB7u) + +/*! + To specify the Software DMA channel to be used for the CRC computation + 0 -> DMA channel SIP0, ..., 7 -> DMA channel SIP7 +*/ +#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7 + +#endif /* ADI_CRC_CONFIG_H */ +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crypto_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crypto_config.h new file mode 100755 index 00000000000..c36d5ea4d36 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_crypto_config.h @@ -0,0 +1,150 @@ +/*! + ***************************************************************************** + @file: adi_crypto_config.h + @brief: Configuration options for Crypto driver. + This is specific to the Crypto driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2014-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef __ADI_CRYPTO_CONFIG_H__ +#define __ADI_CRYPTO_CONFIG_H__ +#include + +/** @addtogroup Crypto_Driver_Config Static Configuration + * @ingroup Crypto_Driver + * @{ + */ + +/************* Crypto Driver configurations ***************/ + +/*! Enable/Disable ECB Support\n + 1 - Enable ECB Support\n + 0 - Disable ECB Support\n +*/ +#define ADI_CRYPTO_ENABLE_ECB_SUPPORT (1) + +/*! Enable/Disable CTR Support\n + 1 - Enable CTR Support\n + 0 - Disable CTR Support\n +*/ +#define ADI_CRYPTO_ENABLE_CTR_SUPPORT (1) + +/*! Enable/Disable CBC Support\n + 1 - Enable CBC Support\n + 0 - Disable CBC Support\n +*/ +#define ADI_CRYPTO_ENABLE_CBC_SUPPORT (1) + +/*! Enable/Disable CCM Support\n + 1 - Enable CCM Support\n + 0 - Disable CCM Support\n +*/ +#define ADI_CRYPTO_ENABLE_CCM_SUPPORT (1) + +/*! Enable/Disable CMAC Support\n + 1 - Enable CMAC Support\n + 0 - Disable CMAC Support\n +*/ +#define ADI_CRYPTO_ENABLE_CMAC_SUPPORT (1) + +/*! Enable/Disable HMAC Support\n + 1 - Enable HMAC Support\n + 0 - Disable HMAC Support\n +*/ +#if defined (__ADUCM4x50__) +#define ADI_CRYPTO_ENABLE_HMAC_SUPPORT (1) +#endif /*ADuCM4x50*/ +/*! Enable/Disable SHA Support\n + 1 - Enable SHA Support\n + 0 - Disable SHA Support\n +*/ +#define ADI_CRYPTO_ENABLE_SHA_SUPPORT (1) + + +/*! Enable/Disable DMA Support\n + 1 - Enable DMA Support\n + 0 - Disable DMA Support +*/ +#define ADI_CRYPTO_ENABLE_DMA_SUPPORT (1) + +/*! Enable/Disable DMA Transfer by default\n + 1 - Enable DMA \n + 0 - Disable DMA +*/ +#define ADI_CRYPTO_ENABLE_DMA (1) + +/*! SHA output format\n + 1 - Big-Endian \n + 0 - Little-Endian +*/ +#define ADI_CRYPTO_SHA_OUTPUT_FORMAT (1) + + +/*! Enable/Disable PKSTOR Support\n + 1 - Enable PKSTOR Support\n + 0 - Disable PKSTOR Support\n +*/ +#define ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT (0) + + + +/************** Macro validation *****************************/ + +#if ((ADI_CRYPTO_ENABLE_DMA_SUPPORT != 0) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT != 1)) +#error "ADI_CRYPTO_ENABLE_DMA_SUPPORT is invalid" +#endif + +#if ((ADI_CRYPTO_ENABLE_DMA != 0) && (ADI_CRYPTO_ENABLE_DMA != 1)) +#error "ADI_CRYPTO_ENABLE_DMA is invalid" +#endif + +#if ((ADI_CRYPTO_ENABLE_DMA == 1) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 0)) +#error "DMA cannot be enabled if DMA support is disabled" +#endif + +#if (!defined(__ADUCM4x50__) && (ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT == 1)) +#error "PKSTOR extensions only supported on ADuCM4x50 platform" +#endif + +/*! @} */ + +#endif /* __ADI_CRYPTO_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_cycle_counting_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_cycle_counting_config.h new file mode 100755 index 00000000000..4b83c46fd7b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_cycle_counting_config.h @@ -0,0 +1,105 @@ +/*! ***************************************************************************** + * @file adi_cycle_counting_config.h + * @brief Cycle Counting Framework configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_CYCLE_COUNTING_CONFIG_H +#define ADI_CYCLE_COUNTING_CONFIG_H + +/** @addtogroup CYCLE_COUNTING_Config Static Configuration + * @ingroup cyclecount_logging + * @{ + */ + + +/************* Cycle Counting Configuration ***************/ + +/*! Global enable. This must be enabled for any other functionality to work\n + 0u disabled + 1u enabled +*/ +#define ADI_CYCLECOUNT_ENABLED (0u) + +/*! SPI Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of SPI ISR cycle counting. + 1 - Enables the recording of SPI ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_SPI_ISR_ENABLED (0u) + + +/*! CRC Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of CRC ISR cycle counting. + 1 - Enables the recording of CRC ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_CRC_ISR_ENABLED (0u) + + +/*! SPORT Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of SPORT ISR cycle counting. + 1 - Enables the recording of SPORT ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_SPORT_ISR_ENABLED (0u) + +/*! UART Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of UART ISR cycle counting. + 1 - Enables the recording of UART ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_UART_ISR_ENABLED (0u) + + +/*! A user application may desire/require cycle counting in an application defined API + or ISR. Set this macro to the number of required. +*/ +#define ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS (0u) + +/*! + * Cycle count 'stack' nesting depth. Adjust as needed. + * This should map to the maximum number of nested interrupts an application might experience. + */ +#define ADI_CYCLECOUNT_STACK_SIZE 10 + +/** + * @} + */ + +#endif /* ADI_CYCLE_COUNTING_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_flash_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_flash_config.h new file mode 100755 index 00000000000..dcb2c82fb0f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_flash_config.h @@ -0,0 +1,307 @@ +/*! + ***************************************************************************** + @file: adi_flash_config.h + @brief: Configuration options for flash driver. + This is specific to the flash driver and will be included by the driver. + It is not required for the application to include this header file. + @version: $Revision: 33205 $ + @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FLASH_CONFIG_H +#define ADI_FLASH_CONFIG_H +#include + +/** @addtogroup Flash_Driver_Config Static Configuration + * @ingroup Flash_Driver + * @{ + */ + + +/****SETTINGS THAT LIVE IN FEE INTERRUPT ENABLE (IEN) REGISTER****/ + + +/*! + * Configure a response to the 2-bit ECC ERROR events (in IEN). + * - 0 Do not generate a response to ECC Error Events. + * - 1 Generate Bus Errors in response to ECC Error Events. + * - 2 Generate IRQs in response to ECC Error Events. + */ +#define ADI_FEE_CFG_ECC_ERROR_RESPONSE (1u) +/*! + * Configure a response to the 1-bit ECC CORRECTION events (in IEN). + * - 0 Do not generate a response to ECC correction Events. + * - 1 Generate Bus Errors in response to ECC correction Events. + * - 2 Generate IRQs in response to ECC correction Events. + */ + +#if defined(__ADUCM4x50__) +#define ADI_FEE_CFG_ECC_CORRECTION_RESPONSE (2u) +#endif + + +/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 0 (TIME_PARAM0) REGISTER****/ + + +/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */ +/*! + * Configure flash non-volatile mass erase hold time.\n + * Upper 4-bits of 11-bit value.\n + * (Lower bits are hard-coded to 0x14.)\n + * Hardware default value is 0xb. + */ +#define ADI_FEE_CFG_PARAM0_TNVH1 (0xbu) + +/*! + * Configure flash erase time.\n + * Upper 4-bits of 19-bit value.\n + * (Lower bits are hard-coded to 0x7370.)\n + * Hardware default value is 0x8. + */ +#define ADI_FEE_CFG_PARAM0_TERASE (0x8u) + +/*! + * Configure flash recovery time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x2.)\n + * Hardware default value is 0x9. + */ +#define ADI_FEE_CFG_PARAM0_TRCV (0x9u) + +/*! + * Configure flash non-volatile hold time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x1.)\n + * Hardware default value is 0x5. + */ +#define ADI_FEE_CFG_PARAM0_TNVH (0x5u) + +/*! + * Configure flash program time.\n + * Upper 4-bits of 10-bit value.\n + * (Lower bits are hard-coded to 0x7.)\n + * Hardware default value is 0x0. + */ +#if defined(__ADUCM302x__) +#define ADI_FEE_CFG_PARAM0_TPROG (0x5u) +#elif defined(__ADUCM4x50__) +#define ADI_FEE_CFG_PARAM0_TPROG (0x0u) +#else +#error Flash Driver is not ported for this processor +#endif +/*! + * Configure flash NVSTR-to-program setup time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x2.)\n + * Hardware default value is 0x9. + */ +#define ADI_FEE_CFG_PARAM0_TPGS (0x9u) + +/*! + * Configure flash program/erase-to-NVSTR setup time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x1.)\n + * Hardware default value is 0x5. + */ +#define ADI_FEE_CFG_PARAM0_TNVS (0x5u) + +/*! + * Configure flash reference clock divide-by-2 setting.\n + * All timing parameters are referenced to this parameter. + * - 0 Reference clock is not divided. + * - 1 Reference clock is divided by 2.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM0_CLKDIV (0x0u) + + + +/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 1 (TIME_PARAM1) REGISTER****/ + + +/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */ +/*! + * Configure flash read access wait states.\n + * Number of 3-bit read access wait states to use.\n + * Maximum allowed value is 0x4.\n + * Hardware default value is 0x0. + */ +#if defined (__ADUCM4x50__) +#define ADI_FEE_CFG_PARAM1_WAITESTATES (0x0u) +#endif +/*! + * Configure flash sleep mode wake-up time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0xb.)\n + * Hardware default value is 0x4. + */ +#define ADI_FEE_CFG_PARAM1_TWK (0x4u) + + + +/****SETTINGS THAT LIVE IN FEE SYSTEM ABOUT ENABLE (ABOUT_EN_XX) REGISTERS****/ + + +/*! + * Configure lower (0-31) flash system interrupt abort enables.\n + * Allows system interrupts to abort an ongoing flash command.\n + * Only 64 system interrupts are supported.\n + * Lower interrupts (0-31) are encoded in ADI_FEE_CFG_ABORT_EN_LO, + * - 0 Corresponding interrupt is prevented from aborting flash command. + * - 1 Corresponding interrupt is allowed to abort flash command.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_ABORT_EN_LO (0x0u) + +/*! + * Configure upper (32-63) flash system interrupt abort enables.\n + * Allows system interrupts to abort an ongoing flash command.\n + * Only 64 system interrupts are supported.\n + * Upper interrupts (32-63) are encoded in ADI_FEE_CFG_ABORT_EN_HI. + * - 0 Corresponding interrupt is prevented from aborting flash command. + * - 1 Corresponding interrupt is allowed to abort flash command.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_ABORT_EN_HI (0x0u) + + + +/****SETTINGS THAT LIVE IN ECC CONFIG REGISTER (ECC_CFG) REGISTER****/ + + +/*! + * ECC Start Page Pointer (in ECC_CFG). + */ +#define ADI_FEE_CFG_ECC_START_PAGE (0u) + +/*! + * Enable/Disable ECC for info space (in ECC_CFG). + * - 1 Enable Info Space. + * - 0 Disable Info Space. + */ +#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE (0u) + +/*! + * Enable/Disable ECC (in ECC_CFG). + * - 1 Enable ECC. + * - 0 Disable ECC. + */ +#define ADI_FEE_CFG_ENABLE_ECC (0u) + + + +/************* Flash Driver Configuration Settings Checkers ***************/ + + + +/* IEN CHECKS */ +#if ((ADI_FEE_CFG_ECC_ERROR_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_ERROR_RESPONSE > 2u)) +#error "ADI_FEE_CFG_ECC_ERROR_RESPONSE should be in the range 0-2." +#endif +#if ((ADI_FEE_CFG_ECC_CORRECTION_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE > 2u)) +#error "ADI_FEE_CFG_ECC_CORRECTION_RESPONSE should be in the range 0-2." +#endif + + + +/* PARAM0 CHECKS */ +#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TERASE < 0u) || (ADI_FEE_CFG_PARAM0_TERASE > 15u)) +#error "ADI_FEE_CFG_PARAM0_TERASE should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TRCV < 0u) || (ADI_FEE_CFG_PARAM0_TRCV > 15u)) +#error "ADI_FEE_CFG_PARAM0_TRCV should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TPROG < 0u) || (ADI_FEE_CFG_PARAM0_TPROG > 15u)) +#error "ADI_FEE_CFG_PARAM0_TPROG should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TPGS < 0u) || (ADI_FEE_CFG_PARAM0_TPGS > 15u)) +#error "ADI_FEE_CFG_PARAM0_TPGS should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TNVS < 0u) || (ADI_FEE_CFG_PARAM0_TNVS > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVS should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_CLKDIV < 0u) || (ADI_FEE_CFG_PARAM0_CLKDIV > 1u)) +#error "ADI_FEE_CFG_PARAM0_CLKDIV should be in the range 0-1." +#endif + + + +/* PARAM1 CHECKS */ +#if ((ADI_FEE_CFG_PARAM1_WAITESTATES < 0u) || (ADI_FEE_CFG_PARAM1_WAITESTATES > 4u)) +#error "ADI_FEE_CFG_PARAM1_WAITESTATES should be in the range 0-4." +#endif +#if ((ADI_FEE_CFG_PARAM1_TWK < 0u) || (ADI_FEE_CFG_PARAM1_TWK > 15u)) +#error "ADI_FEE_CFG_PARAM1_TWK should be in the range 0-15." +#endif + + + +/* ABORT_EN_XX CHECKS */ +#if ((ADI_FEE_CFG_ABORT_EN_LO < 0u) || (ADI_FEE_CFG_ABORT_EN_LO > 0XFFFFu)) +#error "ADI_FEE_CFG_ABORT_EN_LO should be in 32-bit range." +#endif +#if ((ADI_FEE_CFG_ABORT_EN_HI < 0u) || (ADI_FEE_CFG_ABORT_EN_HI > 0XFFFFu)) +#error "ADI_FEE_CFG_ABORT_EN_HI should be in 32-bit range." +#endif + + + +/* ECC_CFG CHECKS */ +#if (((ADI_FEE_CFG_ECC_START_PAGE >> 8u) << 8) != ADI_FEE_CFG_ECC_START_PAGE) +#error "ADI_FEE_CFG_ECC_START_PAGE has invalid bits set in lower 8-bits." +#endif +#if ((ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 0u) && (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 1u)) +#error "ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE should be 1 or 0." +#endif +#if ((ADI_FEE_CFG_ENABLE_ECC != 0u) && (ADI_FEE_CFG_ENABLE_ECC != 1u)) +#error "ADI_FEE_CFG_ENABLE_ECC should be 1 or 0." +#endif + +/*! @} */ + +#endif /* ADI_FLASH_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_global_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_global_config.h new file mode 100755 index 00000000000..6d205577a3b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_global_config.h @@ -0,0 +1,131 @@ +/*! + ***************************************************************************** + @file: adi_global_config.h + @brief: Configuration options for all the drivers. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_GLOBAL_CONFIG_H +#define ADI_GLOBAL_CONFIG_H + +/** @addtogroup GLOBAL_Driver_Config Global Static Configuration + * @brief Configuration options for all the drivers. + * @{ + */ + +/*! @name RTOS used + * In order to be used in a multi-threaded application, the device drivers + * may require the use of some RTOS-specific signals like semaphores or actions + * may be required when entering/exiting an interrupt. By specifying the RTOS + * that the application uses, the drivers can map their requirements to the + * specific RTOS, without requiring an OS abstraction layer. + * @note This macros do not add the RTOS sources to the application, users need + * to set up the source and include paths in their application themselves + * @note If the RTOS specified is not in the list of supported RTOS the build + * mechanism fails + */ +/**@{*/ + +/*! @hideinitializer Indicates that no RTOS is used (bare-metal applications) */ +#define ADI_CFG_RTOS_NO_OS (1) +/*! @hideinitializer Indicates that Micrium uCOS-III is used */ +#define ADI_CFG_RTOS_MICRIUM_III (2) +/*! @hideinitializer Indicates that Micrium FreeRTOS is used */ +#define ADI_CFG_RTOS_FREERTOS (3) + +/*! Configure the RTOS required across the project. + It can be configured to one of the following macros: + - #ADI_CFG_RTOS_NO_OS + - #ADI_CFG_RTOS_MICRIUM_III + - #ADI_CFG_RTOS_FREERTOS + */ +#define ADI_CFG_RTOS ADI_CFG_RTOS_NO_OS + +/**@}*/ + +/*! @name Low power mode support + All applications may have to block when a buffer is being processed. In the + case of an RTOS application, when a task is blocked waiting for a buffer, a + different task can run. If no tasks are available then the idle task runs. + In many RTOS the idle task can be configured so it perform actions like + entering low power modes. + + In the case of a bare-metal (no RTOS) application, since there are no other + tasks to be run, the driver can enter low power modes itself when it blocks. + */ + +/*! Configures the drivers to enter low power mode (Flexi mode) + when waiting for a buffer to be processed. This macro is applicable + only when the drivers are operating in the bare metal mode (No RTOS). + + The possible values it can be configured to are: + + - 1 : Low power mode support required. + - 0 : Low power mode support not required. +*/ +#define ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT (1) +/**@}*/ + + + +/* +** Verify the macro configuration +*/ +#if ((ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_MICRIUM_III) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_FREERTOS)) +#error "ADI_CFG_RTOS macro wrongly configured" +#endif /* ADI_CFG_RTOS verification */ + +#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 0) && \ + (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 1)) +#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT macro is wrongly configured" +#endif + +#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS)) +#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT cannot be set to 1 in multi-threaded applications" +#endif +/** + * @} + */ + +#endif /* ADI_GLOBAL_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_i2c_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_i2c_config.h new file mode 100755 index 00000000000..0f6bbca875a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_i2c_config.h @@ -0,0 +1,226 @@ +/*! + ***************************************************************************** + @file: adi_i2c_config.h + @brief: Configuration options for I2C driver. + This is specific to the I2C driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_I2C_CONFIG_H +#define ADI_I2C_CONFIG_H +#include + +/** @addtogroup I2C_Driver_Config Static Configuration + * @ingroup I2C_Driver + * @{ + */ + +/************* I2C Driver configurations ***************/ + +/*! Master control register TX FIFO decrement control bit.\n + 1 - Decrement master TX FIFO status when a byte has been fully serialized.\n + 0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO, + but not yet serialized on the bus. */ +#define ADI_I2C_CFG_MCTL_MXMITDEC (0) + +/*! Master control register STOP condition interrupt enable.\n + 1 - Enable completion interrupt when a STOP condition is detected.\n + 0 - Disable completion interrupt when a STOP condition is detected. */ +#define ADI_I2C_CFG_MCTL_IENCMP (1) + +/*! Master control register NACK (NotACKnowledge) interrupt enable.\n + 1 - Enable NACK interrupt when an acknowledge is not received.\n + 0 - Disable NACK interrupt when an acknowledge is not received. */ +#define ADI_I2C_CFG_MCTL_IENACK (1) + +/*! Master control register ALOST (Arbitration LOST) interrupt enable.\n + 1 - Enable ALOST interrupt when bus arbitration is lost.\n + 0 - Disable ALOST interrupt when bus arbitration is lost. */ +#define ADI_I2C_CFG_MCTL_IENALOST (1) + +/*! Master control register clock stretch enable.\n + 1 - Enable clock stretch by slave device.\n + 0 - Disable clock stretch by slave device. */ +#define ADI_I2C_CFG_MCTL_STRETCHSCL (0) + +/*! Master control register internal loopback enable.\n + 1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.\n + 0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs. */ +#define ADI_I2C_CFG_MCTL_LOOPBACK (0) + +/*! Master control register start condition back-off disable.\n + 1 - Enables controller to compete for bus ownership even if another device is driving a START condition.\n + 0 - Disables controller to compete for bus ownership even if another device is driving a START condition. */ +#define ADI_I2C_CFG_MCTL_COMPLETE (0) + +/*! Master control register device enable.\n + 1 - Enable controller as a Master device.\n + 0 - Disables controller as a Master device. */ +#define ADI_I2C_CFG_MCTL_MASEN (0) + +/*! + * Standard Clock divider Clock-HI settings. + * Assuming a 26 MHz core clock, the following settings + * will be useful: \n + * - For STANDARD (100 kHz) rate, use: HI= 25, LO= 31. \n + * - For FAST (400 kHz) rate, use: HI=123, LO=129. \n + * \n + * @note The clock high setting varies with pull-up loading, + * board layout, slew-rate, etc., so exact settings are somewhat + * empirical. The clock high counter does not start until + * a logic high transition is sensed on the clock line, so + * variability in this logic transaction will alter the + * effective clock rate. This results from the internal + * clock-stretch hardware feature supporting a slave slow device + * that may hold off the master by holding the clock line low. + * + * @sa ADI_I2C_CFG_DIV_LOW + */ +#define ADI_I2C_CFG_DIV_HIGH (25) + +/*! Standard Clock divider Clock-LO setting + * + * @sa ADI_I2C_CFG_DIV_HIGH + */ +#define ADI_I2C_CFG_DIV_LOW (31) + +/*! Shared control reset START/STOP detect circuit.\n + 1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.\n + 0 - Do nothing. */ +#define ADI_I2C_CFG_SHCTL_RST (0) + +/*! Timing control filter disable.\n + 1 - Disable digital input clock filter.\n + 0 - Enable digital input clock filter (1 PCLK). */ +#define ADI_I2C_CFG_TCTL_FILTEROFF (0) + +/*! Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).\n + Value - Minimum data input hold time count in units of PCLK period. (Value = Thd/PCLK-period) */ +#define ADI_I2C_CFG_TCTL_THDATIN (1) + +/*! Master automatic stretch mode duration (4-bit), e.g., (in binary):\n + - 0b0000 - No SCL clock stretching.\n + - 0b0001 - Timeout after hold SCL LOW 2^1 = 2 bit-times.\n + - 0b0010 - Timeout after hold SCL LOW 2^2 = 4 bit-times.\n + - ...\n + - 0b1110 - Timeout after hold SCL LOW 2^14 = 16,384 bit-times.\n + - 0b1111 - Hold SCL LOW with no timeout.\n +\n + Where "bit-time" is computed by CLKDIV values and incoming UCLK (see HRM). */ +#define ADI_I2C_CFG_ASTRETCH_MST (0) + +/*! Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).\n + For example, the value:\n + 0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.\n + It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:\n + - 0xA0 for write operations, or\n + - 0xA1 for read operations */ +#define ADI_I2C_CFG_SLAVE_ADDRESS (0x50) + + +/***********************************\ +|* Check for overflowing values... *| +\***********************************/ + +#if (ADI_I2C_CFG_MCTL_MXMITDEC >> 1) +#error "Decrement TX FIFO status config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENCMP >> 1) +#error "Transaction complete (STOP) interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENACK >> 1) +#error "NACK interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENALOST >> 1) +#error "ALOST interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_STRETCHSCL >> 1) +#error "Clock stretch enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_LOOPBACK >> 1) +#error "Loopback enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_COMPLETE >> 1) +#error "Start back-off disable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_MASEN >> 1) +#error "Master device enable config value too wide" +#endif + +#if (ADI_I2C_CFG_DIV_HIGH >> 8) +#error "Clock HIGH time config value too wide" +#endif + +#if (ADI_I2C_CFG_DIV_LOW >> 8) +#error "Clock LOW time config value too wide" +#endif + +#if (ADI_I2C_CFG_SHCTL_RST >> 1) +#error "Shared control reset config value too wide" +#endif + +#if (ADI_I2C_CFG_TCTL_FILTEROFF >> 1) +#error "Timing control filter-off config value too wide" +#endif + +#if (ADI_I2C_CFG_TCTL_THDATIN >> 5) +#error "Timing control filter-off config value too wide" +#endif + +#if (ADI_I2C_CFG_ASTRETCH_MST >> 4) +#error "Master clock stretch config value too wide" +#endif + +#if (ADI_I2C_CFG_SLAVE_ADDRESS >> 7) +#error "Slave address config value too wide" +#endif + +/*! @} */ + +#endif /* ADI_I2C_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_pwr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_pwr_config.h new file mode 100755 index 00000000000..2eb5a38d17c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_pwr_config.h @@ -0,0 +1,668 @@ +/* + ***************************************************************************** + @file: adi_pwr_config.h + @brief: Configuration options for PWR driver. + This is specific to the PWR driver and will be included by the source file. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_PWR_CONFIG_H +#define ADI_PWR_CONFIG_H +#include +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. +* +* Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. +* The YODA-generated headers rely on more. The IAR compiler supports that. +*/ +#pragma diag_suppress=Pm009 +#endif /* __ICCARM__ */ + +/** @addtogroup PWR_Driver_Config Static Configuration + * @ingroup Power_Driver + * @{ + */ + +/*! Enable the code to support input clock through the GPIO pin + 0 - No support for input clock through the GPIO pin. + 1 - Support for input clock through the GPIO pin. + +*/ +#define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO 0 + +/*------------------------------------------------------------------------------- + Set of MACROs for configuring the clock +--------------------------------------------------------------------------------*/ +/* Oscillator Control Register */ + +/*! + 32 KHz clock select mux. This clock connects to beeper, RTC.\n + 0 - Internal 32 KHz oscillator is selected.\n + 1 - External 32 KHz crystal is selected.. +*/ +#define ADI_PWR_LF_CLOCK_MUX 0 + + +/*! + High frequency internal oscillator enable\n + 0 - The HFOSC oscillator is disabled and placed in a low power state\n + 1 - The HFOSC oscillator is enabled. +*/ +#define ADI_PWR_HFOSC_CLOCK_ENABLE 1 + +/*! + Low frequency external oscillator enable and placed in a low power state\n + 0 - The LFXTAL oscillator is disabled\n + 1 - The LFXTAL oscillator is enabled. + +*/ +#define ADI_PWR_LFXTAL_CLOCK_ENABLE 0 + +/*! + High frequency external oscillator enable\n + 0 - The HFXTAL oscillator is disabled and placed in a low power state\n + 1 - The HFXTAL oscillator is enabled. +*/ +#define ADI_PWR_HFXTAL_CLOCK_ENABLE 0 + +/*! + Low frequency external clock fail interrupt enable \n + 0 - The LFXTAL clock monitor and clock fail interrupt disabled \n + 1 - The LFXTAL clock monitor and clock fail interrupt enabled.\n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE 0 + +/*! + Automatic switching of the LF Mux to LF Oscillator on LFXTAL failure. \n + 0 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure \n + 1 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure.\n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE 0 + +/*! + Low frequency crystal Robust mode enable. The Robust mode enables the LFXTAL oscillator to work also when an + additional resistive load is placed between the crystal pins and GND. \n + 0 - Selects Normal mode \n + 1 - Selects Robust mode \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE 0 + +/*! + Low frequency crystal Robust mode load select. The amount of loading tolerated when robust mode is enabled. \n + 0 - No Trim, and big resistive loads not tolerated. \n + 1 - 20 Mohm load mode, greater than 20 Mohm load allowed. \n + 2 - 10 Mohm load mode, greater than 10 Mohm load allowed. \n + 3 - 5 Mohm load mode, 5 Mohm load allowed on both IO pins. \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT 0 + + +/*! + Root clock monitor and Clock Fail interrupt enable. + 0 - Disable Root Clock Monitor and Clock Fail interrupt. \n + 1 - Enable Root Clock Monitor and Clock Fail interrupt. \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE 0 + + +/*! + Enable Auto switch to High Frequency Oscillator (HFOSC) when Root Clock Fails. + 0 - Disable Automatic switching of the Root Clock. \n + 1 - Enable Automatic switching of the Root Clock. \n + \n +*/ +#define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE 0 + + +/********** Miscellaneous clock setting register CTL0 *************/ + +/*! + Selecting the input clock for Root Clock mux. Determines which single shared clock source + is used by the PCLK, and HCLK dividers. \n + 0 - HFOSC High frequency internal oscillator \n + 1 - HFXTAL High frequency external oscillator\n + 2 - SPLL Output of System PLL is selected\n + 3 - External GPIO port is selected +*/ +#define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX 0 + +/*! + GPIO clock out select. Selects the clock to be routed to the GPIO clock out pin. \n + 0 - Root Clock (ROOT_CLK)\n + 1 - Low Frequency Clock (LF_CLK) \n + 2 - ADC Clock (ACLK) \n + 3 - HCLK_BUS \n + 4 - HCLK_CORE \n + 5 - Peripheral Clock (PCLK) + 6 - Reference Clock for Flash controller timer (RCLK)\n + 7 - Mux of HFOSC, HFXTAL clock (RHP_CLK)\n + 8 - GP Timer 0 clock (GPT0_CLK)\n + 9 - GP Timer 1 clock (GPT1_CLK)\n + 10 - Peripherals operating at HCLK (HCLK_P)\n + 11 - PLL Clock out (PCLK)\n + 12 - RTC0 Clock \n + 13 - HP Buck Clock (HPBUCK_CLK)\n + 14 - HP Buck Non overlap clock\n + 15 - RTC1 generated clock \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_GPIO_CLOCK_OUT_SELECT 0 + +/*! + Flash reference clock and HPBUCK clock source mux. \n + 0 - sourcing from HFOSC (High frequency internal oscillator) \n + 2 - sourcing from external HFXTAL( High frequency external oscillator 26M Hz )\n + 3 - sourcing from external HFXTAL( High frequency external oscillator 16M Hz ) + +*/ +#define ADI_PWR_INPUT_TO_RCLK_MUX 0 + +/*! + Selecting the input clock for the system PLL clock. \n + 0 - sourcing from HFOSC (High frequency internal oscillator) \n + 1 - sourcing from HFXTAL(High frequency external oscillator) \n + 2 - GPIO Input clock. \n + 3 - GPIO Input clock. +*/ +#define ADI_PWR_INPUT_TO_SPLL_MUX 0 + +/*! + External Low frequency crystal interrupt enable.\n + 0 - Disable the interrupt for LF clock \n + 1 - Enable the interrupt for LF clock +*/ +#define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE 0 + +/*! + External Hight frequency crystal interrupt enable.\n + 0 - Disable the interrupt for HFXTAL clock \n + 1 - Enable the interrupt for HFXTAL clock +*/ +#define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE 0 + + + +/********** Clock divider register CTL1 ***************/ + +/*! + HCLK divide count.Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/HCLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_HCLK_DIVIDE_COUNT 4 + +/*! + PCLK divide count.Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/PCLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_PCLK_DIVIDE_COUNT 4 + +/*! + ACLK divide count.Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/ACLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_ACLK_DIVIDE_COUNT 16 + + + +/************* HF Oscillator divide clock select register CTL2 ***********/ + +/*! + HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode. + + When enabled enabled (Set to 1), the frequency undivided 26MHz HF oscillator clock itself will be used during the wake up. + The undivided HFOSC clock is selected automatically by clearing the HFOSCDIVCLKSEL register content to 0, which selects the HFOSC/1 clock.This updated divided by 1 clock selection will remain same until the new divider value is written to this register. + + When disabled (Set to 0), this fast wake up feature will be disabled and the HFOSCDIVCLKSEL register will remain unchanged + during the wakeup. + + 0 - Auto select HFOSC/1 clock during wakeup from Flexi mode is disable. \n + 1 - Auto select HFOSC/1 clock during wakeup from Flexi mode is enabled. \n + + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_HFOSC_AUTO_DIV_BY_1 0 + +/*! + HF Oscillator divide select. + 0 - HFOSC/1. \n + 1 - HFOSC/2. \n + 2 - HFOSC/4. \n + 3 - HFOSC/8. \n + 4 - HFOSC/16. \n + 5 - HFOSC/32. \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_HFOSC_DIVIDE_SELECT 0 + + + +/****** System PLL Register CTL3 *****/ +/*! + System PLL N multiplier(SPLL_NSEL). Sets the N value used to obtain the multiplication + factor N/M of the PLL. + 8 - 31 is valid range. +*/ +#define ADI_PWR_SPLL_MUL_FACTOR 26 + +/*! + System PLL division by 2. Controls if an optional divide by two is placed on the PLL output.\n + 0 - The System PLL is not divided. Its output frequency equals that selected by the N/M ratio \n + 1 - The System PLL is divided by two. Its output frequency equals that selected by the N/M ratio + with an additional divide by 2 +*/ +#define ADI_PWR_SPLL_ENABLE_DIV2 0 + +/*! + System PLL enable. Controls if the PLL should be enabled or placed in its low power state. \n + 0 - The system PLL is disabled and is in its power down state\n + 1 - The system PLL is enabled. +*/ +#define ADI_PWR_SPLL_ENABLE 0 + +/*! + System PLL interrupt enable.Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt generated.\n + 0 - Disable the SPLL interrupt generation\n + 1 - Enable the SPLL interrupt generation +*/ +#define ADI_PWR_SPLL_INTERRUPT_ENABLE 0 + +/*! + System PLL M Divider(SPLL_MSEL). Sets the M value used to obtain the multiplication + factor N/M of the PLL. + 2 - 15 is valid range. +*/ +#define ADI_PWR_SPLL_DIV_FACTOR 13 + +/*! + system PLL multiply by 2. This bit is used to configure if the VCO clock frequency should be multiplied by 2 or 1.\n + 0 - The System PLL is multiplied by 1.\n + 1 - The System PLL is multiplied by 2. +*/ +#define ADI_PWR_SPLL_ENABLE_MUL2 0 + + +/********** User Clock Gating Control CTL5 ********************/ + +/*! + This can be used to enable/disable clock to GPT0. \n + 0 - Disable the clock to GPT0\n + 1 - Enable the clock to GPT0 +*/ +#define ADI_PWR_GPT0_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to GPT1. \n + 0 - Disable the clock to GPT1\n + 1 - Enable the clock to GPT1 +*/ +#define ADI_PWR_GPT1_CLOCK_ENABLE 1 +/*! + This can be used to enable/disable clock to GPT2. \n + 0 - Disable the clock to GPT2\n + 1 - Enable the clock to GPT2 +*/ +#define ADI_PWR_GPT2_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to I2C. \n + 0 - Disable the clock to I2C\n + 1 - Enable the clock to I2C\n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_I2C_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to GPIO. \n + 0 - Disable the clock to GPIO\n + 1 - Enable the clock to GPIO \n + + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_GPIO_CLOCK_ENABLE 1 + + +/*! + This can be used to enable/disable all clocks connected to peripherals. \n + 0 - Disable the Clock supply to peripherals\n + 1 - Enable the Clock supply to peripherals \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_PCLK_ENABLE 0 + +/*! + This can be used to enable/disable clocks to Timer RGB. \n + 0 - Disable the Clock supply to Timer RGB \n + 1 - Enable the Clock supply to Timer RGB \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_TIMER_RGB_ENABLE 1 + +/*------------------------------------------------------------------------------- + Set of macros for configuring the power management module +--------------------------------------------------------------------------------*/ + +/********* Interrupt enable register IEN ********/ + +/*! + Enabling the interrupt if the Battery voltage falls below 1.8V.\n + 0 - Disable Battery voltage interrupt \n + 1 - Enable Battery voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VBAT_INTERRUPT 0 + +/*! + Enabling the interrupt for under VREG voltage (i.e less than 1V).\n + 0 - Disable VREG under voltage interrupt \n + 1 - Enable VREG under voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT 0 + +/*! + Enabling the interrupt for over VREG voltage (i.e above than 1.32V).\n + 0 - Disable VREG over voltage interrupt \n + 1 - Enable VREG over voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT 0 + +/*! + Enabling the interrupt for Battery range.\n + 0 - Disable battery voltage range interrupt \n + 1 - Enable battery voltage range interrupt +*/ +#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT 0 + +/*! + Battery voltage range for generating the interrupt.\n + 0 - Configure to generate interrupt if VBAT > 2.75V \n + 1 - Configure to generate interrupt if VBAT is between 2.75 and 1.6V \n + 2 - Configure to generate interrupt if VBAT is between 2.3V and 1.6V +*/ +#define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT 0 + +/********* HP Buck control register CTL1 ********/ +/*! + Enable or disable HP Buck.\n + 0 - Disable HP Buck. + 1 - Enable HP Buck. +*/ +#define ADI_PWR_HP_BUCK_ENABLE 0 + +/*! + HP Buck Load mode.\n + 0 - HP Buck low load mode. Can be set when the system is running at + less than 26 Mhz. \n + 1 - HP Buck High load mode. Can be set when the system is running at + more than 26 Mh. \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_HP_BUCK_LOAD_MODE 0 + +/*! + HP Buck low power mode.\n + The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode + and low power modules such as Timer, Beeper only are enabled + + 0 - HPBUCK Low power mode is disabled. \n + 1 - HPBUCK Low power mode is enabled. \n + \n + Note: This feature is available only in ADuCM4x50 processor. +*/ +#define ADI_PWR_HP_BUCK_LOW_POWER_MODE 0 + + +/********* Power mode register ********/ + +/*! + Enable or disable monitoring battery voltage (VBAT) during HIBERNATE Mode. \n + 0 - Battery voltage monitoring is enabled. + 1 - Battery voltage monitoring is disabled. + + By default battery voltage monitoring during hibernate is enabled. +*/ +#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING 0 + + +/******************************************************************************* + M A C R O V A L I D A T I O N +*******************************************************************************/ + +#if ( ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO > 1 ) +#error "Invalid configuration set for ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO" +#endif + +#if ( ADI_PWR_LF_CLOCK_MUX > 1 ) +#error "Invalid configuration set for ADI_PWR_LF_CLOCK_MUX" +#endif + +#if ( ADI_PWR_HFOSC_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_HFXTAL_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_MON_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_MON_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT > 3 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT" +#endif + +#if ( ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE" +#endif + +#if ( ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE" +#endif + +#if ( ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX" +#endif + +#if ( ADI_PWR_GPIO_CLOCK_OUT_SELECT > 15 ) +#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_OUT_SELECT" +#endif + +#if ( ADI_PWR_INPUT_TO_RCLK_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_RCLK_MUX" +#endif + +#if ( ADI_PWR_INPUT_TO_SPLL_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_SPLL_MUX" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_HCLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_HCLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_PCLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_PCLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_ACLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_ACLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_HFOSC_AUTO_DIV_BY_1 > 1 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_AUTO_DIV_BY_1" +#endif + +#if ( ADI_PWR_HFOSC_DIVIDE_SELECT > 5 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_DIVIDE_SELECT" +#endif + +#if ( ADI_PWR_SPLL_MUL_FACTOR < 8 || ADI_PWR_SPLL_MUL_FACTOR > 31 ) +#error "Invalid configuration set for ADI_PWR_SPLL_MUL_FACTOR" +#endif + +#if ( ADI_PWR_SPLL_ENABLE_DIV2 > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_DIV2" +#endif + +#if ( ADI_PWR_SPLL_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE" +#endif + +#if ( ADI_PWR_SPLL_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_SPLL_DIV_FACTOR < 2 || ADI_PWR_SPLL_DIV_FACTOR > 15 ) +#error "Invalid configuration set for ADI_PWR_SPLL_DIV_FACTOR" +#endif + +#if ( ADI_PWR_SPLL_ENABLE_MUL2 > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_MUL2" +#endif + +#if ( ADI_PWR_GPT0_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT0_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPT1_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT1_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPT2_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT2_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_I2C_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_I2C_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPIO_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_PCLK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_PCLK_ENABLE" +#endif + +#if ( ADI_PWR_TIMER_RGB_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_TIMER_RGB_ENABLE" +#endif + +#if ( ADI_PWR_ENABLE_VBAT_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VBAT_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT" +#endif + +#if ( ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT > 2 ) +#error "Invalid configuration set for ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT" +#endif + +#if ( ADI_PWR_HP_BUCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_ENABLE" +#endif + +#if ( ADI_PWR_HP_BUCK_LOAD_MODE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOAD_MODE" +#endif + +#if ( ADI_PWR_HP_BUCK_LOW_POWER_MODE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOW_POWER_MODE" +#endif + +#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING" +#endif + + + +/*! @} */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm009 +#endif /* __ICCARM__ */ + +#endif /* ADI_PWR_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rng_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rng_config.h new file mode 100755 index 00000000000..76afe147cfb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rng_config.h @@ -0,0 +1,106 @@ +/*! + ***************************************************************************** + @file: adi_rng_config.h + @brief: Configuration options for RNG driver. + This is specific to the RNG driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_RNG_CONFIG_H__ +#define ADI_RNG_CONFIG_H__ +#include +/** @defgroup RNG_Driver_Cfg RNG Driver Configuration + * @ingroup RNG_Driver + + */ + +/*! \addtogroup RNG_Driver_Cfg RNG Driver Configuration + * @{ + */ + +/************* RNG Driver configurations ***************/ + +/************* RNG controller configurations ***************/ + +/*! RNG Control Register, bit 3\n + Enable only 8-bit generation\n + 0 - Generate 32-bit random number\n + 1 - Generate only 8-bit random number +*/ +#define RNG0_CFG_ONLY_8_BIT 1 + +/*! RNG Sample Length Register, bits [11:0]\n + The register defines the number of samples to accumulate in the + CRC register when generating a random number.\n + + Bits [11:0] contains the reload value of the sample counter + + */ +#define RNG0_CFG_LENGTH_RELOAD 256u + +/*! RNG Sample Length Register, bits [15:12]\n + The register defines the number of samples to accumulate in the + CRC register when generating a random number. The number of values + accumulated in the counter reload value is scaled by 2^prescaler.\n + + Bits [15:12] contains the prescaler for the sample counter + + */ +#define RNG0_CFG_LENGTH_PRESCALER 0u + +/************** Macro validation *****************************/ + +#if ( RNG0_CFG_ONLY_8_BIT > 1 ) +#error "Invalid configuration" +#endif + +#if ( RNG0_CFG_LENGTH_RELOAD > 4095u ) +#error "Invalid value for reload" +#endif + +#if ( RNG0_CFG_LENGTH_PRESCALER > 10u ) +#error "Invalid value for prescaler" +#endif + +/*! @} */ + +#endif /* __ADI_RNG_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rtc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rtc_config.h new file mode 100755 index 00000000000..ef97a3b0a48 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_rtc_config.h @@ -0,0 +1,397 @@ +/*! + ***************************************************************************** + @file: adi_rtc_config.h + @brief: Configuration options for Real Time Clock device driver. + This is specific to the RTC driver and will be included by the driver. + It is not required for the application to include this header file. + @version: $Revision: 33005 $ + @date: $Date: 2015-12-12 10:43:13 -0500 (Sat, 12 Dec 2015) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_RTC_CONFIG_H__ +#define ADI_RTC_CONFIG_H__ +#include + +/** @addtogroup RTC_Driver_Config Static Configuration + * @ingroup RTC_Driver + * @{ + */ + +/*! + * The safe write mode insures any pending writes that have not yet synchronized between the faster core clock + * domain and the internal RTC 32kHz clock domain are reconciled before multiple writes to the same RTC register + * are allowed +*/ + +#define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1 + + +/** @addtogroup RTC_Driver_Config_RTC0 RTC0 Static Configuration + * @ingroup RTC_Driver_Config + * @{ + */ + +/* +=================================================================== + ------------------------RTC-0 CONFIGURATION MACRO----------------- +=================================================================== +*/ +/*! Enable the Alarm */ +#define RTC0_CFG_ENABLE_ALARM 0 + +/*! Enable the Alarm interrupt*/ +#define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0 + +/*! Enable the Trim */ +#define RTC0_CFG_ENABLE_TRIM 0 + +/*! Enable the PENDERROR interrupt*/ +#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0 + +/*! Enable the write sync interrupt*/ +#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0 + +/*! Enable the pend write interrupt*/ +#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0 + +/*! Initial the count Value*/ +#define RTC0_CFG_COUNT_VALUE 0 + +/*! Initial the count Value-0*/ +#define RTC0_CFG_COUNT_VALUE_0 0 + +/*! Initial the count Value-1*/ +#define RTC0_CFG_COUNT_VALUE_1 0 + +/*! Alarm-0 Value*/ +#define RTC0_CFG_ALARM_VALUE_0 0 + +/*! Alarm-1 Value*/ +#define RTC0_CFG_ALARM_VALUE_1 0 + +/*! Trim interval*/ +#define RTC0_CFG_TRIM_INTERVAL 0 + +/*! Trim interval with power of 2*/ +#define RTC0_CFG_POW2_TRIM_INTERVAL 0 + +/*! Trim operation to be performed for RTC0*/ +#define RTC0_CFG_TRIM_OPERATION 0 + +/*! Trim Value for RTC-0*/ +#define RTC0_CFG_TRIM_VALUE 0 + +/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 3. + * Enables sampling of Sensor Strobe GPIO inputs around rising edge of Sensor Strobe Channel 3 pulse. + * + * 0 No sampling of input around rising edge. + * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. + * 10 Input sampled at rising edge of Sensor Strobe. + * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. + */ +#define RTC0_SS3_SMPONRE 0 + +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 3. + * Enables sampling of Sensor Strobe GPIO inputs around falling edge of Sensor Strobe Channel 3 pulse. + * + * 0 No sampling of input around rising edge. + * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. + * 10 Input sampled at rising edge of Sensor Strobe. + * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. + */ +#define RTC0_SS3_SMPONFE 0 +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 2. */ +#define RTC0_SS2_SMPONFE 0 +/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 1. */ +#define RTC0_SS1_SMPONRE 0 +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 1. */ +#define RTC0_SS1_SMPONFE 0 + + +/*! Sensor Strobe's GP Input Sampling Mux + * SS 2 GPIO Pin 1 + * + * GPMUX0/1.SSxGPINySEL 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 + * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] + */ +#define RTC0_SS2_GPIN1SEL 0x4 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ +#define RTC0_SS2_GPIN0SEL 0x3 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ +#define RTC0_SS1_GPIN2SEL 0x2 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ +#define RTC0_SS1_GPIN1SEL 0x1 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ +#define RTC0_SS1_GPIN0SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ +#define RTC0_SS3_GPIN2SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ +#define RTC0_SS3_GPIN1SEL 0x7 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ +#define RTC0_SS3_GPIN0SEL 0x6 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ +#define RTC0_SS2_GPIN2SEL 0x5 + +/*! Differential output option for Sensor Strobe channel 3. + * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out + * for this channel is available in corresponding GPIO. + * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. + */ +#define RTC0_SS3_DIFFOUT 0 +/*! Differential output option for Sensor Strobe channel 1. + * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out + * for this channel is available in corresponding GPIO. + * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. + */ +#define RTC0_SS1_DIFFOUT 0 + + + +/*! @} */ + +/* +=================================================================== + ------------------------RTC-1 CONFIGURATION MACRO----------------- +=================================================================== +*/ + +/** @addtogroup RTC_Driver_Config_RTC1 RTC1 Static Configuration + * @ingroup RTC_Driver_Config + * @{ + */ + + + +/*! Enable the Alarm */ +#define RTC1_CFG_ENABLE_ALARM 0 + +/*! Enable the Alarm interrupt*/ +#define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0 + +/*! Enable the Trim */ +#define RTC1_CFG_ENABLE_TRIM 0 + +/*! Enable the mod-60 Alarm */ +#define RTC1_CFG_ENABLE_MOD60_ALARM 0 + +/*! Enable the mod-60 Alarm period*/ +#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0 + +/*! Enable the Alarm interrupt*/ +#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0 + +/*! Enable the ISOINT interrupt*/ +#define RTC1_CFG_ENABLE_ISO_INTERRUPT 0 + +/*! Enable the PENDERROR interrupt*/ +#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0 + +/*! Enable the write sync interrupt*/ +#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0 + +/*! Enable the pend write interrupt*/ +#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0 + +/*! Enable the RTC count interrupt*/ +#define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0 + +/*! Enable the prescaled modulo-1 interrupt*/ +#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0 + +/*! Enable the Trim interrupt*/ +#define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0 + +/*! Enable the Mod60 roll over interrupt*/ +#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0 + +/*! Prescale value for the RTC1*/ +#define RTC1_CFG_PRESCALE 0 + +/*! Enable the counter roll over interrupt*/ +#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0 + +/*! Initial the count Value-0*/ +#define RTC1_CFG_COUNT_VALUE_0 0 + +/*! Initial the count Value-1*/ +#define RTC1_CFG_COUNT_VALUE_1 0 + +/*! Alarm Value-0*/ +#define RTC1_CFG_ALARM_VALUE_0 0 + +/*! Alarm Value-1*/ +#define RTC1_CFG_ALARM_VALUE_1 0 + +/*! Alarm Value-2*/ +#define RTC1_CFG_ALARM_VALUE_2 0 + +/*! Trim interval*/ +#define RTC1_CFG_TRIM_INTERVAL 0 + +/*! Trim interval with power of 2*/ +#define RTC1_CFG_POW2_TRIM_INTERVAL 0 + +/*! Trim operation to be performed for RTC1*/ +#define RTC1_CFG_TRIM_OPERATION 0 + +/*! Trim Value for RTC-1*/ +#define RTC1_CFG_TRIM_VALUE 0 + +/*! Enable the input capture channel-0*/ +#define RTC1_CFG_IC0_ENABLE 0 + +/*! Enable the input capture channel-2*/ +#define RTC1_CFG_IC2_ENABLE 0 + +/*! Enable the input capture channel-3*/ +#define RTC1_CFG_IC3_ENABLE 0 + +/*! Enable the input capture channel-4*/ +#define RTC1_CFG_IC4_ENABLE 0 + +/*! Enable the Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_ENABLE 0 +/*! Enable the Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_ENABLE 0 +/*! Enable the Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_ENABLE 0 +/*! Enable the Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_ENABLE 0 + +/*! Enable the interrupt for input capture channel-0*/ +#define RTC1_CFG_IC0_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-2*/ +#define RTC1_CFG_IC2_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-3*/ +#define RTC1_CFG_IC3_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-4*/ +#define RTC1_CFG_IC4_INT_ENABLE 0 + +/*! Enable the over write input capture channels*/ +#define RTC1_CFG_IC_OVER_WRITE_ENABLE 0 + +/*! Polarity for input capture channel-0*/ +#define RTC1_CFG_IC0_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-2*/ +#define RTC1_CFG_IC2_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-3*/ +#define RTC1_CFG_IC3_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-4*/ +#define RTC1_CFG_IC4_EDGE_POLARITY 0 + +/*! Enable the interrupt for Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_INT_ENABLE 0 + +/*! Enable the masking for Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_MASK_ENABLE 0 + +/*! Enable the auto-reloading for Sensor Strobe channel-0*/ +#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0 + +/*! Mask for Sensor Strobe channel-0 */ +#define RTC1_CFG_SS1_MASK_VALUE 0 + + +/*! Auto reload value for Sensor Strobe channel-0 */ +#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2 + + +/*! Sensor Strobe GP Input Sampling Mux + * SS2 GPIO Pin 1 + * + * GPMUX0/1.SSxGPINySEL 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 + * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] + */ +#define RTC1_SS2_GPIN1SEL 0x4 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ +#define RTC1_SS2_GPIN0SEL 0x3 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ +#define RTC1_SS1_GPIN2SEL 0x2 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ +#define RTC1_SS1_GPIN1SEL 0x1 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ +#define RTC1_SS1_GPIN0SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ +#define RTC1_SS3_GPIN2SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ +#define RTC1_SS3_GPIN1SEL 0x7 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ +#define RTC1_SS3_GPIN0SEL 0x6 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ +#define RTC1_SS2_GPIN2SEL 0x5 + +/*! Differential output option for Sensor Strobe channel 3. + * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out + * for this channel is available in corresponding GPIO. + * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. + */ +#define RTC1_SS3_DIFFOUT 0 +/*! Differential output option for Sensor Strobe channel 1. + * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out + * for this channel is available in corresponding GPIO. + * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. + */ +#define RTC1_SS1_DIFFOUT 0 + + +/*! @} */ + +/*! @} */ +#endif /* ADI_RTC_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_spi_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_spi_config.h new file mode 100755 index 00000000000..e2a8ccd572b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_spi_config.h @@ -0,0 +1,592 @@ +/*! + ***************************************************************************** + @file: adi_spi_config.h + @brief: Configuration options for SPI driver. + This is specific to the SPI driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_SPI_CONFIG_H__ +#define ADI_SPI_CONFIG_H__ +#include +/** @addtogroup SPI_Driver_Config Static Configuration + * @ingroup SPI_Driver + * @{ + */ + + +/*! Set this macro to the system clock frequency in hertz*/ +#define ADI_CFG_SYSTEM_CLOCK_HZ (26000000u) + +/************* SPI controller configurations ***************/ + +/* There are three SPI instances SPI0, SPI1 and SPI2 */ +/* Each SPI has its own configuration macros */ + + +/*----------------------------------------------------------*/ +/* -------------------- SPI0 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration + * @ingroup SPI_Driver_Config + * @{ + */ + + /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI0_MASTER_MODE (1u) + + +/*! Set this macro to the SPI0 bit rate in hertz */ +#define ADI_SPI0_CFG_BIT_RATE (2000000u) + +/*! SPI0 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI0_CFG_ENABLE (0u) + +/*! SPI0 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI0_CFG_CLK_PHASE (0u) + + + + + +/*! SPI0 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI0_CFG_CLK_POLARITY (0u) + + +/*! SPI0 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI0_CFG_WIRED_OR (0u) + + +/*! SPI0 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI0_CFG_LSB_MSB (0u) + + +/*! SPI0 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI0_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI0_CFG_TX_UNDERFLOW (0u) + + +/*! SPI0 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI0_CFG_RX_OVERFLOW (0u) + + +/*! SPI0 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI0_CFG_MISO_ENABLE (0u) + + +/*! SPI0 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI0_CFG_LOOPBACK (0u) + +/*! SPI0 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI0_CFG_CONTINUOUS (0u) + +/*! SPI0 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI0_CFG_RX_FLUSH (0u) + + +/*! SPI0 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI0_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI0 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI0_CFG_CSERR_RESET (0u) + + +/*! SPI0 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI0_CFG_CLK_DIV (0u) + + +/*! SPI0 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI0_CFG_HFM (0u) + + +/*! SPI0 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI0_CFG_CS_ERR (0u) + + +/*! SPI0 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI0_CFG_CS_IRQ (0u) + + +/*! @} */ + +/*----------------------------------------------------------*/ +/* -------------------- SPI1 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration + * @ingroup SPI_Driver_Config + * @{ + */ + + /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI1_MASTER_MODE (1u) + +/*! Set this macro to the SPI1 bit rate in hertz */ +#define ADI_SPI1_CFG_BIT_RATE (2000000u) + +/*! SPI1 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI1_CFG_ENABLE (0u) + +/*! SPI1 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI1_CFG_CLK_PHASE (0u) + + + + + +/*! SPI1 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI1_CFG_CLK_POLARITY (0u) + + +/*! SPI1 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI1_CFG_WIRED_OR (0u) + + +/*! SPI1 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI1_CFG_LSB_MSB (0u) + + +/*! SPI1 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI1_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI1_CFG_TX_UNDERFLOW (0u) + + +/*! SPI1 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI1_CFG_RX_OVERFLOW (0u) + + +/*! SPI1 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI1_CFG_MISO_ENABLE (0u) + + +/*! SPI1 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI1_CFG_LOOPBACK (0u) + +/*! SPI1 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI1_CFG_CONTINUOUS (0u) + +/*! SPI1 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI1_CFG_RX_FLUSH (0u) + + +/*! SPI1 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI1_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI1 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI1_CFG_CSERR_RESET (0u) + + +/*! SPI1 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI1_CFG_CLK_DIV (0u) + + +/*! SPI1 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI1_CFG_HFM (0u) + + +/*! SPI1 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI1_CFG_CS_ERR (0u) + + +/*! SPI1 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI1_CFG_CS_IRQ + +/*! @} */ + +/*----------------------------------------------------------*/ +/* -------------------- SPI2 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration + * @ingroup SP2_Driver_Config + * @{ + */ + +/*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI2_MASTER_MODE (1u) + +/*! Set this macro to the SPI2 bit rate in hertz */ +#define ADI_SPI2_CFG_BIT_RATE (2000000u) + +/*! SPI2 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI2_CFG_ENABLE (0u) + +/*! SPI2 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI2_CFG_CLK_PHASE (0u) + + + + + +/*! SPI2 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI2_CFG_CLK_POLARITY (0u) + + +/*! SPI2 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI2_CFG_WIRED_OR (0u) + + +/*! SPI2 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI2_CFG_LSB_MSB (0u) + + +/*! SPI2 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI2_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI2_CFG_TX_UNDERFLOW (0u) + + +/*! SPI2 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI2_CFG_RX_OVERFLOW (0u) + + +/*! SPI2 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI2_CFG_MISO_ENABLE (0u) + + +/*! SPI2 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI2_CFG_LOOPBACK (0u) + +/*! SPI2 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI2_CFG_CONTINUOUS (0u) + +/*! SPI2 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI2_CFG_RX_FLUSH (0u) + + +/*! SPI2 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI2_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI2 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI2_CFG_CSERR_RESET (0u) + + +/*! SPI2 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI2_CFG_CLK_DIV (0u) + + +/*! SPI2 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI2_CFG_HFM (0u) + + +/*! SPI2 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI2_CFG_CS_ERR (0u) + + +/*! SPI2 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI2_CFG_CS_IRQ + +/*! @} */ + +/************** Macro validation *****************************/ + +#if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ + ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ + ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_ENABLE > 1u ) || \ + ( ADI_SPI1_CFG_ENABLE > 1u ) || \ + ( ADI_SPI2_CFG_ENABLE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \ + ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \ + ( ADI_SPI2_CFG_CLK_PHASE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \ + ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \ + ( ADI_SPI2_CFG_CLK_POLARITY > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \ + ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \ + ( ADI_SPI2_CFG_WIRED_OR > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \ + ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \ + ( ADI_SPI2_CFG_LSB_MSB > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \ + ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \ + ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \ + ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \ + ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \ + ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \ + ( ADI_SPI2_CFG_RX_OVERFLOW > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \ + ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \ + ( ADI_SPI2_CFG_MISO_ENABLE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \ + ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \ + ( ADI_SPI2_CFG_LOOPBACK > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \ + ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \ + ( ADI_SPI2_CFG_CONTINUOUS > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \ + ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \ + ( ADI_SPI2_CFG_RX_FLUSH > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \ + ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \ + ( ADI_SPI2_CFG_TX_FLUSH > 1u ) +#error "Invalid configuration" +#endif + + +/*! @} */ + +#endif /* ADI_SPI_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h new file mode 100755 index 00000000000..db0fdb6636a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_sport_config.h @@ -0,0 +1,355 @@ +/*! **************************************************************************** + * @file adi_sport_config.h + * @brief Configuration options for SPORT driver. + * @details This is specific to the SPORT driver and will be included by the + * driver. It is not required for the application to include this + * header file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_SPORT_CONFIG_H +#define ADI_SPORT_CONFIG_H +#include + +/** @addtogroup SPORT_Driver_Config Static Configuration + * @ingroup SPORT_Driver + * @{ + */ + +/************* SPORT Driver configurations FOR SPORT-0-A ***************/ +/*! + Frame Sync Multiplexer Select.\n + 0 - Disable frame sync multiplexing\n + 1 - Enable frame sync multiplexing. +*/ +#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL (0u) + +/*! + Clock Multiplexer Select.\n + 0 - Disable serial clock multiplexing\n + 1 - Enable serial clock multiplexing. +*/ +#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL (1u) + +/*! + Least-Significant Bit First.\n + 0 - MSB first sent/received.\n + 1 - LSB first sent/received. +*/ +#define ADI_CFG_SPORT0A_LSB_FIRST (0u) + + +/*! + Serial Word Length in bits.\n + 1 - 32 - SPORT word length +*/ +#define ADI_CFG_SPORT0A_SERIAL_WLEN (32u) + + +/*! + Internal Clock.\n + 0 - External clock.\n + 1 - Internal clock. +*/ +#define ADI_CFG_SPORT0A_INTERNAL_CLK (1u) + +/*! + Operation Mode\n + 0 - DSP standard.\n + 1 - Timer_enable mode. +*/ +#define ADI_CFG_SPORT0A_OPERATION_MODE (0u) + + +/*! + Clock Rising Edge\n + 0 - Clock falling edge\n + 1 - Clock rising edge. +*/ +#define ADI_CFG_SPORT0A_CLOCK_EDGE (0u) + +/*! + Frame Sync Required\n + 0 - No frame sync required \n + 1 - Frame sync required. +*/ +#define ADI_CFG_SPORT0A_FS_REQUIRED (1u) + +/*! + Internal Frame Sync\n + 0 - External frame sync\n + 1 - Internal frame sync +*/ +#define ADI_CFG_SPORT0A_INTERNAL_FS (0u) + + +/*! + Data-Independent Frame Sync\n + 0 - Data-dependent frame sync\n + 1 - Data-independent frame +*/ +#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS (0u) + +/*! + Active-Low Frame Sync\n + 0 - Active high frame sync\n + 1 - Active low frame sync +*/ +#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS (0u) + +/*! + Late Frame Sync\n + 0 - Early frame sync\n + 1 - Late frame sync +*/ +#define ADI_CFG_SPORT0A_LATE_FS (0u) + +/*! + Enable Packing \n + 0 - Disable\n + 1 - 8-bit packing enable\n + 2 - 16-bit packing enable +*/ +#define ADI_CFG_SPORT0A_ENABLE_PACKING (0u) + +/*! + Frame Sync Error Operation + 0 - Flag the Frame Sync error\n + 1 - When frame Sync error occurs, discard the receive data +*/ +#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION (1u) + +/*! + Enabling Gated Clock\n + 0 - Disable Gated Clock\n + 1 - Enable Gated Clock +*/ +#define ADI_CFG_SPORT0A_GATED_CLOCK (0u) + +/*! + Serial Clock divisor.\n + 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial + clock (ACLK) from the processor system clock (PCLK). +*/ +#define ADI_CFG_SPORT0A_CLOCK_DIVISOR (2u) + +/*! + Frame Sync Divisor.\n + 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock + cycles that the half SPORT counts before generating a frame sync pulse. +*/ +#define ADI_CFG_SPORT0A_FS_DIVISOR (0x40u) + + +/*! + CONVT to FS duration.\n + 0 - 128 - Specify the value of the number of clocks which would be programmed + corresponding to the desired time duration from assertion of CONVT + signal to Frame sync signal +*/ +#define ADI_CFG_SPORT0A_CONVT_FS_DURATION (1u) + +/*! + Polarity of the Convt signal.\n + 0 - Active High Polarity\n + 1 - Active low Polarity +*/ +#define ADI_CFG_SPORT0A_CONVT_POLARITY (0u) + +/*! + CONVT signal width.\n + 0 - 15 - Specify the value of the number of serial clocks for which CONVT + signal should be active + +*/ +#define ADI_CFG_SPORT0A_CONVT_WIDTH (1u) + +#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) +#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " +#endif + +/************* SPORT Driver configurations FOR SPORT-0-B ***************/ +/*! + Least-Significant Bit First.\n + 0 - MSB first sent/received.\n + 1 - LSB first sent/received. +*/ +#define ADI_CFG_SPORT0B_LSB_FIRST (0u) + + +/*! + Serial Word Length in bits.\n + 1 - 32 - SPORT word length +*/ +#define ADI_CFG_SPORT0B_SERIAL_WLEN (32u) + + +/*! + Internal Clock.\n + 0 - External clock.\n + 1 - Internal clock. +*/ +#define ADI_CFG_SPORT0B_INTERNAL_CLK (1u) + +/*! + Operation Mode\n + 0 - DSP standard.\n + 1 - Timer_enable mode. +*/ +#define ADI_CFG_SPORT0B_OPERATION_MODE (0u) + + +/*! + Clock Rising Edge\n + 0 - Clock falling edge\n + 1 - Clock rising edge. +*/ +#define ADI_CFG_SPORT0B_CLOCK_EDGE (0u) + +/*! + Frame Sync Required\n + 0 - No frame sync required \n + 1 - Frame sync required. +*/ +#define ADI_CFG_SPORT0B_FS_REQUIRED (1u) + +/*! + Internal Frame Sync\n + 0 - External frame sync\n + 1 - Internal frame sync +*/ +#define ADI_CFG_SPORT0B_INTERNAL_FS (1u) + + +/*! + Data-Independent Frame Sync\n + 0 - Data-dependent frame sync\n + 1 - Data-independent frame +*/ +#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS (0u) + +/*! + Active-Low Frame Sync\n + 0 - Active high frame sync\n + 1 - Active low frame sync +*/ +#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS (0u) + +/*! + Late Frame Sync\n + 0 - Early frame sync\n + 1 - Late frame sync +*/ +#define ADI_CFG_SPORT0B_LATE_FS (0u) + +/*! + Enable Packing \n + 0 - Disable\n + 1 - 8-bit packing enable\n + 2 - 16-bit packing enable\n +*/ +#define ADI_CFG_SPORT0B_ENABLE_PACKING (0u) + +/*! + Frame Sync Error Operation\n + 0 - Flag the Frame Sync error\n + 1 - When frame Sync error occurs, discard the receive data +*/ +#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION (1u) + +/*! + Enabling Gated Clock\n + 0 - Disable Gated Clock\n + 1 - Enable Gated Clock +*/ +#define ADI_CFG_SPORT0B_GATED_CLOCK (0u) + +/*! + Serial Clock divisor.\n + 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial + clock (ACLK) from the processor system clock (PCLK). +*/ +#define ADI_CFG_SPORT0B_CLOCK_DIVISOR (2u) + +/*! + Frame Sync Divisor.\n + 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock + cycles that the half SPORT counts before generating a frame sync pulse. +*/ +#define ADI_CFG_SPORT0B_FS_DIVISOR (0x40u) + + +/*! + CONVT to FS duration.\n + 0 - 128 - Specify the value of the number of clocks which would be programmed + corresponding to the desired time duration from assertion of CONVT + signal to Frame sync signal +*/ +#define ADI_CFG_SPORT0B_CONVT_FS_DURATION (1u) + +/*! + Polarity of the Convt signal.\n + 0 - Active High Polarity\n + 1 - Active low Polarity +*/ +#define ADI_CFG_SPORT0B_CONVT_POLARITY (0u) + +/*! + CONVT signal width.\n + 0-15 - Specify the value of the number of serial clocks for which CONVT + signal should be active + +*/ +#define ADI_CFG_SPORT0B_CONVT_WIDTH (1u) + +#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) +#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " +#endif + +/*! @} */ + +#endif /* ADI_SPORT_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_tmr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_tmr_config.h new file mode 100755 index 00000000000..f03ff59484f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_tmr_config.h @@ -0,0 +1,942 @@ +/*! ***************************************************************************** + * @file adi_tmr_config.h + * @brief GP and RGB timer device driver configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_CONFIG_H +#define ADI_TMR_CONFIG_H + +#include +#include + +/** @addtogroup TMR_Driver_Config Static Configuration + * @ingroup TMR_Driver + * @{ + */ + + +/*! Static configuration allows all 3 GP timers and the RGB timer to be configured + with the parameters in this file by simply calling #adi_tmr_Init. The user can + then call any of the configuration API's to override the static configuration, + or simply call #adi_tmr_Enable to start the timer. Since all of these parameters + must be stored in arrays for abstraction, using static configuration will increase the + data footprint. If the user doesn't call any of the runtime configuration API's, the + linker will throw them out and the code footprint will be reduced significantly. Using + static configuration also reduces cycle count and simplifies the user application. + Static configuration should be used if the timers need to be configured once and do not + need to be changed during the system lifetime. + + 0 - Disable static confiscation support. User must call #adi_tmr_ConfigTimer and other + configuration API's after calling #adi_tmr_Init and prior to calling #adi_tmr_Enable + in order to set up the timer. + + 1 - Enable static configuration support. The timer registers will be set based on the + settings in this file when #adi_tmr_Init is called. +*/ + + +/************************************************************* + GP Timer 0 Configuration + *************************************************************/ + + /** @addtogroup GPTimer0_Driver_Config GP Timer 0 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR0_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR0_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR0_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR0_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR0_CFG_LOAD_VALUE (0x8F9Cu) + +/*! Timer asynchrounous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR0_CFG_ASYNC_LOAD_VALUE (0x8F9Cu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR0_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR0_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + GP Timer 0 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR0_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR0_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#if defined(__ADUCM302x__) +#define TMR0_CFG_EVENT_CAPTURE (9u) +#elif defined(__ADUCM4x50__) +#define TMR0_CFG_EVENT_CAPTURE (27u) +#else +#error TMR is not ported for this processor +#endif + +/************************************************************* + GP Timer 0 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This vlaue can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR0_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR0_CFG_PWM0_MATCH_VALUE (0x0E5Cu) + +/*! @} */ + + +/************************************************************* + GP Timer 1 Configuration + *************************************************************/ + + /** @addtogroup GPTimer1_Driver_Config GP Timer 1 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR1_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR1_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR1_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR1_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR1_CFG_LOAD_VALUE (0x23E7u) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR1_CFG_ASYNC_LOAD_VALUE (0x23E7u) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR1_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR1_CFG_ENABLE_SYNC_BYPASS (0u) + + +/************************************************************* + GP Timer 1 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR1_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR1_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#if defined(__ADUCM302x__) +#define TMR1_CFG_EVENT_CAPTURE (15u) +#elif defined(__ADUCM4x50__) +#define TMR1_CFG_EVENT_CAPTURE (28u) +#else +#error TMR is not ported for this processor +#endif +/************************************************************* + GP Timer 1 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR1_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR1_CFG_PWM0_MATCH_VALUE (0x08F9u) + +/*! @} */ + +/************************************************************* + GP Timer 2 Configuration + *************************************************************/ + + /** @addtogroup GPTimer2_Driver_Config GP Timer 2 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR2_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR2_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR2_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR2_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR2_CFG_LOAD_VALUE (0x0E5Cu) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR2_CFG_ASYNC_LOAD_VALUE (0x0E5Cu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR2_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR2_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + GP Timer 2 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR2_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR2_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#if defined(__ADUCM302x__) +#define TMR2_CFG_EVENT_CAPTURE (6u) +#elif defined(__ADUCM4x50__) +#define TMR2_CFG_EVENT_CAPTURE (27u) +#else +#error TMR is not ported for this processor +#endif +/************************************************************* + GP Timer 2 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR2_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR2_CFG_PWM0_MATCH_VALUE (0x02DFu) + +/*! @} */ + +#if defined(__ADUCM4x50__) +/************************************************************* + RGB Timer Configuration + *************************************************************/ + +/** @addtogroup RGBTimer_Driver_Config RGB Timer Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR3_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR3_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR3_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR3_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR3_CFG_LOAD_VALUE (0x47CEu) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR3_CFG_ASYNC_LOAD_VALUE (0x47CEu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR3_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR3_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + RGB Timer Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR3_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR3_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR3_CFG_EVENT_CAPTURE (28u) + +/************************************************************* + RGB Timer PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM0_MATCH_VALUE (0x23E7u) + +/************************************************************* + RGB Timer PWM1 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE (0u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM1_IDLE_STATE (0u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM1_MATCH_VALUE (0u) + +/************************************************************* + RGB Timer PWM2 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE (0u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM2_IDLE_STATE (0u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM2_MATCH_VALUE (0u) + +/*! @} */ +#endif + +/************************************************************* + GP Timer 0 Macro Validation +**************************************************************/ + +#if TMR0_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if defined(__ADUCM302x__) +#if TMR0_CFG_EVENT_CAPTURE > 15u +#error "Invalid configuration" +#endif +#elif defined(__ADUCM4x50__) +#if TMR0_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif +#else +#error TMR is not ported for this processor +#endif + +#if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + GP Timer 1 Macro Validation +**************************************************************/ + +#if TMR1_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if defined(__ADUCM302x__) +#if TMR1_CFG_EVENT_CAPTURE > 15u +#error "Invalid configuration" +#endif +#elif defined(__ADUCM4x50__) +#if TMR1_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif +#else +#error TMR is not ported for this processor +#endif + +#if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + GP Timer 2 Macro Validation +**************************************************************/ + +#if TMR2_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if defined(__ADUCM302x__) +#if TMR2_CFG_EVENT_CAPTURE > 15u +#error "Invalid configuration" +#endif +#elif defined(__ADUCM4x50__) +#if TMR2_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif +#else +#error TMR is not ported for this processor +#endif + +#if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if defined(__ADUCM4x50__) +/************************************************************* + RGB Timer Macro Validation +**************************************************************/ +#if TMR3_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM1_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM2_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#endif +/*! @} */ + + +#endif /* ADI_TMR_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_uart_config.h new file mode 100755 index 00000000000..1cf72a4b91a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_uart_config.h @@ -0,0 +1,496 @@ +/*! + ***************************************************************************** + @file: adi_uart_config.h + @brief: Configuration options for UART driver. + This is specific to the UART driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_UART_CONFIG_H +#define ADI_UART_CONFIG_H + +/** @addtogroup UART_Driver_Config Static Configuration + * @ingroup UART_Driver + * @{ + */ + + +#include + +/************** Common UART Driver configurations ************** */ +/*! + Enable the autobaud detection. \n + Range: 0 to 1. +*/ +#define ADI_UART_CFG_ENABLE_AUTOBAUD 1 + + +/** @addtogroup UART0_Driver_Config UART0 Static Configuration + * @ingroup UART_Driver_Config + * @{ + */ + +/************** UART Driver configurations FOR UART 0 ************** */ +/*! + Word length Select. \n + 0 - 5 Bits word length. \n + 1 - 6 Bits word length. \n + 2 - 7 Bits word length. \n + 3 - 8 Bits word length. +*/ +#define ADI_UART0_CFG_WORD_LENGTH 3 + + +/*! + Stop bit selection. \n + 0 - Send 1 stop bit regardless of the word length. \n + 1 - Send a number of stop bits based on the word length. \n + WORD-LENGTH 5 Bits => 1.5 Stop Bits. \n + WORD-LENGTH (6/7/8) Bits => 2 Stop Bits. +*/ +#define ADI_UART0_CFG_STOP_BIT 1 + + +/*! + Parity Enable. Used to control the parity bit. \n + 0 - Parity will not be transmitted or checked. \n + 1 - Parity will be transmitted and checked. +*/ +#define ADI_UART0_CFG_ENABLE_PARITY 0 + + +/*! + Parity Select. This bit only has meaning if parity is enabled. \n + 0 - Odd parity will be transmitted and checked. \n + 1 - Even parity will be transmitted and checked. +*/ +#define ADI_UART0_CFG_PARITY_SELECTION 0 + + +/*! + Stick Parity. Used to force parity to defined values. \n + 0 - Parity will not be forced. \n + 1 - Set parity based on the following bit settings: \n + EPS = 1 and PEN = 1, parity will be forced to 0. \n + EPS = 0 and PEN = 1, parity will be forced to 1. \n + EPS = 1/0 and PEN = 0, no parity will be transmitted. +*/ +#define ADI_UART0_CFG_ENABLE_STICKY_PARITY 0 + + +/* + Table 21-2: Baud Rate Examples Based on 26 MHz PCLK + Baud Rate OSR COMDIV DIVM DIVN + 9600 3 24 3 1078 + 19200 3 12 3 1078 + 38400 3 8 2 1321 + 57600 3 4 3 1078 + 115200 3 4 1 1563 + 230400 3 2 1 1563 + 460800 3 1 1 1563 + 921,600 2 1 1 1563 + 1,000,000 2 1 1 1280 + 1,500,000 2 1 1 171 + +These are calculated with the UarDivCalculator tool. +*/ + +/*! + Fractional baud rate N divide value. \n + Range: 0 to 2047. +*/ +#define ADI_UART0_CFG_DIVN 1078 + + +/*! + Fractional baud rate M divide value. \n + Range: 1 to 3. +*/ +#define ADI_UART0_CFG_DIVM 3 + + +/*! + Fractional baud rate C divide value. \n + Range: 1 to 65535. +*/ +#define ADI_UART0_CFG_DIVC 24 + + +/*! + Over Sample Rate value. \n + Range: 0 to 3. \n + 0 - Over sample by 4. \n + 1 - Over sample by 8. \n + 2 - Over sample by 16. \n + 3 - Over sample by 32. + +*/ +#define ADI_UART0_CFG_OSR 3 + + +/*! + Enable Internal FIFO. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_FIFO 1 + + +/*! + TRIG Level for UART device. \n + Range: 0 to 3. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. \n + 2 - 8 bytes to trig RX interrupt. \n + 3 - 14 bytes to trig RX interrupt. +*/ +#define ADI_UART0_CFG_TRIG_LEVEL 0 + + +/*! + Hold TX while RX is active. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_HOLD_TX 0 + + +/*! + Disable RX when TX is active. \n + Range: 0 to 1. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. +*/ +#define ADI_UART0_CFG_DISABLE_RX 0 + + +/*! + Configure the SOUT de-assertion earlier than full stop bit(s). \n + Range: 0 to 1. \n + 0 - SOUT_EN de-assert same time as full stop bit(s). \n + 1 - SOUT_EN de-assert half-bit earlier than full stop bit(s). +*/ +#define ADI_UART0_CFG_DEASSERTION 0 + + +/*! + Set the SOUT polarity low. \n + Range: 0 to 1. \n + 0 - Active high. \n + 1 - Active low. +*/ +#define ADI_UART0_CFG_SOUT_POLARITY 0 + +/*! + Enable the RX status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT 1 + + +/*! + Enable the Modem status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT 0 + +/*! @} */ + + +/*************** UART Driver configurations FOR UART 1 **************/ + +/** @addtogroup UART1_Driver_Config UART1 Static Configuration + * @ingroup UART_Driver_Config + * @{ + */ + +/*! + Word length Select. \n + 0 - 5 Bits word length. \n + 1 - 6 Bits word length. \n + 2 - 7 Bits word length. \n + 3 - 8 Bits word length. +*/ +#define ADI_UART1_CFG_WORD_LENGTH 3 + + +/*! + Stop bit selection.\n + 0 - Send 1 stop bit regardless of the word length. \n + 1 - Send a number of stop bits based on the word length. \n + WORD-LENGTH 5 Bits => 1.5 Stop Bits. \n + WORD-LENGTH (6/7/8) Bits => 2 Stop Bits. +*/ +#define ADI_UART1_CFG_STOP_BIT 1 + + +/*! + Parity Enable. Used to control the parity bit. \n + 0 - Parity will not be transmitted or checked. \n + 1 - Parity will be transmitted and checked. +*/ +#define ADI_UART1_CFG_ENABLE_PARITY 0 + + +/*! + Parity Select. This bit only has meaning if parity is enabled. \n + 0 - Odd parity will be transmitted and checked. \n + 1 - Even parity will be transmitted and checked. +*/ +#define ADI_UART1_CFG_PARITY_SELECTION 0 + + +/*! + Stick Parity. Used to force parity to defined values. \n + 0 - Parity will not be forced. \n + 1 - Set parity based on the following bit settings: \n + EPS = 1 and PEN = 1, parity will be forced to 0. \n + EPS = 0 and PEN = 1, parity will be forced to 1. \n + EPS = 1/0 and PEN = 0, no parity will be transmitted. +*/ +#define ADI_UART1_CFG_ENABLE_STICKY_PARITY 0 + + +/* + Table 21-2: Baud Rate Examples Based on 26 MHz PCLK + Baud Rate OSR COMDIV DIVM DIVN + 9600 3 24 3 1078 + 19200 3 12 3 1078 + 38400 3 8 2 1321 + 57600 3 4 3 1078 + 115200 3 4 1 1563 + 230400 3 2 1 1563 + 460800 3 1 1 1563 + 921,600 2 1 1 1563 + 1,000,000 2 1 1 1280 + 1,500,000 2 1 1 171 + +These are calculated with the UarDivCalculator tool. +*/ + +/*! + Fractional baud rate N divide value. \n + Range: 0 to 2047. +*/ +#define ADI_UART1_CFG_DIVN 1563 + + +/*! + Fractional baud rate M divide value. \n + Range: 1 to 3. +*/ +#define ADI_UART1_CFG_DIVM 1 + + +/*! + Fractional baud rate C divide value. \n + Range: 1 to 65535. +*/ +#define ADI_UART1_CFG_DIVC 1 + + +/*! + Over Sample Rate value. \n + Range: 0 to 3. \n + 0 - Over sample by 4. \n + 1 - Over sample by 8. \n + 2 - Over sample by 16. \n + 3 - Over sample by 32. + +*/ +#define ADI_UART1_CFG_OSR 3 + + +/*! + Enable Internal FIFO. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_FIFO 1 + + +/*! + TRIG Level for UART device. \n + Range: 0 to 3. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. \n + 2 - 8 bytes to trig RX interrupt. \n + 3 - 14 bytes to trig RX interrupt. +*/ +#define ADI_UART1_CFG_TRIG_LEVEL 0 + + +/*! + Hold TX while RX is active. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_HOLD_TX 0 + + +/*! + Disable RX when TX is active. \n + Range: 0 to 1. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. +*/ +#define ADI_UART1_CFG_DISABLE_RX 0 + + +/*! + Configure the SOUT de-assertion earlier than full stop bit(s). \n + Range: 0 to 1. \n + 0 - SOUT_EN de-assert same time as full stop bit(s). \n + 1 - SOUT_EN de-assert half-bit earlier than full stop bit(s). +*/ +#define ADI_UART1_CFG_DEASSERTION 0 + + +/*! + Set the SOUT polarity low. \n + Range: 0 to 1. \n + 0 - Active high. \n + 1 - Active low. +*/ +#define ADI_UART1_CFG_SOUT_POLARITY 0 + +/*! + Enable the RX status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT 1 + + +/*! + Enable the Modem status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT 0 +/*! @} */ + +/*! @} */ + + +/*************** UART Driver Debug Checks ************** */ + +/* Check word length */ +#if (((ADI_UART0_CFG_WORD_LENGTH < 0) || (ADI_UART0_CFG_WORD_LENGTH > 3)) || ((ADI_UART1_CFG_WORD_LENGTH < 0) || (ADI_UART1_CFG_WORD_LENGTH > 3))) +#error "Word length needs to be between 0 and 3" +#endif + +/* Check stop bit */ +#if (((ADI_UART0_CFG_STOP_BIT < 0) || (ADI_UART0_CFG_STOP_BIT > 1)) || ((ADI_UART1_CFG_STOP_BIT < 0) || (ADI_UART1_CFG_STOP_BIT > 1))) +#error "Stop bit selection needs to be 0 or 1" +#endif + +/* Check parity enable */ +#if (((ADI_UART0_CFG_ENABLE_PARITY < 0) || (ADI_UART0_CFG_ENABLE_PARITY > 1)) || ((ADI_UART1_CFG_ENABLE_PARITY < 0) || (ADI_UART1_CFG_ENABLE_PARITY > 1))) +#error "Parity Enable bit needs to be 0 or 1" +#endif + +/* Check parity select */ +#if (((ADI_UART0_CFG_PARITY_SELECTION < 0) || (ADI_UART0_CFG_PARITY_SELECTION > 1)) || ((ADI_UART1_CFG_PARITY_SELECTION < 0) || (ADI_UART1_CFG_PARITY_SELECTION > 1))) +#error "Parity bit selection needs to be 0 or 1" +#endif + +/* Check enable sticky parity */ +#if (((ADI_UART0_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART0_CFG_ENABLE_STICKY_PARITY > 1)) || ((ADI_UART1_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART1_CFG_ENABLE_STICKY_PARITY > 1))) +#error "Sticky parity enable needs to be 0 or 1" +#endif + +/* Check fractional baudrate N divider value */ +#if (((ADI_UART0_CFG_DIVN < 0) || (ADI_UART0_CFG_DIVN > 2047)) || ((ADI_UART1_CFG_DIVN < 0) || (ADI_UART1_CFG_DIVN > 2047))) +#error "Fractional baudrate N divider value needs to be between 0 and 2047" +#endif + +/* Check fractional baudrate M divider value */ +#if (((ADI_UART0_CFG_DIVM < 1) || (ADI_UART0_CFG_DIVM > 3)) || ((ADI_UART1_CFG_DIVM < 1) || (ADI_UART1_CFG_DIVM > 3))) +#error "Fractional baudrate M divider value needs to be between 1 and 3" +#endif + +/* Check fractional baudrate C divider value */ +#if (((ADI_UART0_CFG_DIVC < 1) || (ADI_UART0_CFG_DIVC > 65535)) || ((ADI_UART1_CFG_DIVC < 1) || (ADI_UART1_CFG_DIVC > 65535))) +#error "Fractional baudrate C divider value needs to be between 1 and 65535" +#endif + +/* Check over same rate value */ +#if (((ADI_UART0_CFG_OSR < 0) || (ADI_UART0_CFG_OSR > 3)) || ((ADI_UART1_CFG_OSR < 0) || (ADI_UART1_CFG_OSR > 3))) +#error "over sample rate value needs to be between 0 and 3" +#endif + +/* Check enable internal FIFO */ +#if (((ADI_UART0_CFG_ENABLE_FIFO < 0) || (ADI_UART0_CFG_ENABLE_FIFO > 1)) || ((ADI_UART1_CFG_ENABLE_FIFO < 0) || (ADI_UART1_CFG_ENABLE_FIFO > 1))) +#error "Enable internal FIFO needs to be 0 or 1" +#endif + +/* Check UART trig level */ +#if (((ADI_UART0_CFG_TRIG_LEVEL < 0) || (ADI_UART0_CFG_TRIG_LEVEL > 3)) || ((ADI_UART1_CFG_TRIG_LEVEL < 0) || (ADI_UART1_CFG_TRIG_LEVEL > 3))) +#error "Trig level for the UART device needs to be 0 or 1" +#endif + +/* Check value for holding tx while rx is active */ +#if (((ADI_UART0_CFG_HOLD_TX < 0) || (ADI_UART0_CFG_HOLD_TX > 1)) || ((ADI_UART1_CFG_HOLD_TX < 0) || (ADI_UART1_CFG_HOLD_TX > 1))) +#error "Value for holding Tx while Rx is active needs to be 0 or 1" +#endif + +/* Check value de-assertion */ +#if (((ADI_UART0_CFG_DEASSERTION < 0) || (ADI_UART0_CFG_DEASSERTION > 1)) || ((ADI_UART1_CFG_DEASSERTION < 0) || (ADI_UART1_CFG_DEASSERTION > 1))) +#error "Value for de-assertion needs to be 0 or 1" +#endif + +/* Check value for SOUT polarity */ +#if (((ADI_UART0_CFG_SOUT_POLARITY < 0) || (ADI_UART0_CFG_SOUT_POLARITY > 1)) || ((ADI_UART1_CFG_SOUT_POLARITY < 0) || (ADI_UART1_CFG_SOUT_POLARITY > 1))) +#error "Value for SOUT polarity needs to be 0 or 1" +#endif + +/* Check value to enable autobaud detection */ +#if ((ADI_UART_CFG_ENABLE_AUTOBAUD < 0) || (ADI_UART_CFG_ENABLE_AUTOBAUD > 1)) +#error "Value for autobaud enable needs to be 0 or 1" +#endif + +/* Check value to enable Rx status interrupt */ +#if (((ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT > 1)) || ((ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT > 1))) +#error "Value to enable Rx status interrupt needs to be 0 or 1" +#endif + +/* Check value to enable modem status interrupt */ +#if (((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1)) || ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1))) +#error "Value to enable modem status interrupt needs to be 0 or 1" +#endif + +#endif /* ADI_UART_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_wdt_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_wdt_config.h new file mode 100755 index 00000000000..25e47a78509 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/config/adi_wdt_config.h @@ -0,0 +1,119 @@ +/*! ***************************************************************************** + * @file adi_wdt_config.h + * @brief WDT device driver configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_WDT_CONFIG_H +#define ADI_WDT_CONFIG_H + + +/** @addtogroup WDT_Driver_Config Static Configuration + * @ingroup WDT_Driver + * @{ + */ + + +/************* WDT Static Configuration ***************/ + +/*! WDT Timer Reload Value\n + Value used to reload the WDT count register after count expires.\n + 0-65535 - WDT reload value (default is 0x0100). +*/ +#define ADI_WDT_LOAD_VALUE (0x1000u) + +/*! WDT Timer Mode\n + Selects WDT operating mode.\n + 0 - WDT operates in free-running mode.\n + 1 - WDT operates in periodic mode (default). +*/ +#define ADI_WDT_CONTROL_TIMER_MODE (1u) + +/*! WDT Clock Prescaler\n + Controls WDT clock prescale.\n + 0 - WDT operates at (source clock)/1.\n + 1 - WDT operates at (source clock)/16.\n + 2 - WDT operates at (source clock)/256 (default).\n +*/ +#define ADI_WDT_CONTROL_CLOCK_PRESCALER (2u) + +/*! WDT Timeout Mode\n + Controls WDT timeout behaviour.\n + 0 - WDT issues RESET on timeout (default).\n + 1 - WDT issues INTERRUPT on timeout. +*/ +#define ADI_WDT_CONTROL_TIMEOUT_MODE (0u) + +/*! WDT Power Mode Disable\n + Controls WDT countdown in hibernate or halted mode.\n + 0 - WDT continues to count down when core is halted or in hibernate.\n + 1 - WDT pauses count down when core is halted or in hibernate (default).\n +*/ +#define ADI_WDT_CONTROL_POWER_MODE (1u) + +/************** Macro Validation *****************************/ + +#if ( ADI_WDT_LOAD_VALUE > 65535u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_TIMER_MODE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_CLOCK_PRESCALER > 2u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_TIMEOUT_MODE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_POWER_MODE > 1u ) +#error "Invalid configuration" +#endif + +/** + * @} + */ + +#endif /* ADI_WDT_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc.c new file mode 100755 index 00000000000..4ea2233205c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc.c @@ -0,0 +1,1279 @@ +/*! **************************************************************************** + * @file: adi_crc.c + * @brief: CRC device driver global file. + * @details: This file contain the CRC device driver impelementation. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#include +#include + + +/** @addtogroup CRC_Driver CRC Device Driver + * @{ + +@brief Cyclic Redundancy Check (CRC) peripheral driver +@details + +The CRC peripheral is used to perform the Cyclic Redundancy Check (CRC) of the +block of data that is presented to the peripheral. The peripheral provides a +means to periodically verify the integrity of the system memory and it is based +on a CRC32 engine that computes the signature of 32-bit data presented to the +hardware engine. CRC operations can be core driven or DMA driven depending on +static configuration. + + - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to 0 defines a core driven CRC driver + - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to a non 0 value defines a DMA driven + CRC driver + +Core driven CRC operations + +The adi_crc_Compute function executes core driven CRC operations to calculate the +CRC on the buffer input with the CRC parameters set in the driver. In this mode, +data in the submitted buffer is transmitted to the CRC directly by the core. + +Memory DMA driver CRC operations + +The adi_crc_Compute function executes DMA driven CRC operations to calculate the +CRC on the buffer input with the CRC parameters set in the driver. In this mode, +data in the submitted buffer is transmitted to the CRC through DMA transfers. + +The software DMA channel reserved for the CRC driver is defined by a macro, +ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID, which can take a value between 0 and 7. +If this macro is not defined, e.g. in a configuration file, then its value +is defaulted to 7: in this case, DMA channel SIP7 is used by the CRC driver +and DMA_SIP7_Int_Handler becomes the interrupt used by the DMA when a transfer +to the CRC is complete. + +Computing CRC + +The CRC engine performs a 32-bit CRC operation on the incoming data stream. + +Sequence of function calls for Computing CRC :\n + - #adi_crc_Open() to open CRC device and get a valid CRC handle. + - #adi_crc_SetPolynomialVal() to set the polynomial value to be used in CRC operations. + - #adi_crc_SetBitMirroring() to enable/disable bit mirroring + - #adi_crc_SetByteMirroring() to enable/disable byte mirroring + - #adi_crc_SetLSBFirst() to indicate if data is Big or Little Endian. + - #adi_crc_IsCrcInProgress() to poll the current status of CRC operation or + wait for callback event. + - #adi_crc_GetFinalCrcVal() to get the CRC value of the data stream if its + CRC value is unknown. (Note that #adi_crc_GetFinalCrcVal resets the CRC + seed to the #ADI_CFG_CRC_SEED_VALUE default value.) + + Note that using statically configured parameters such as + #ADI_CFG_CRC_ENABLE_BYTE_MIRRORING, #ADI_CFG_CRC_ENABLE_BIT_MIRRORING, + #ADI_CFG_CRC_POLYNOMIAL and #ADI_CFG_CRC_SEED_VALUE, functions + #adi_crc_SetBitMirroring, #adi_crc_SetByteMirroring, #adi_crc_SetPolynomialVal + and #adi_crc_SetBitMirroring don't need to be called explicitly in your + application: the parameters will be assigned when opening the driver. + + @note - The application must include drivers/crc/adi_crc.h to use this driver. + @note - This driver also requires the DMA driver. The application must include + the DMA driver sources to avoid link errors. + */ + +/*! \cond PRIVATE */ +/*============= I N C L U D E S =============*/ + +#include +#include +#include "adi_crc_def.h" + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Casts from pointer to uint32_t needed to determine pointer alignment. +*/ +#pragma diag_suppress=Pm123,Pm088,Pm152,Pm140 +#endif /* __ICCARM__ */ + +/*============== D E F I N E S ===============*/ + +/* CRC Peripheral specific information */ +#define ADI_CRC_NUM_DEVICES (1u) + +/*! \endcond */ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0) + +/** + * If a DMA channel has not been configured for the CRC driver, +* then a default software DMA channel is assigned: SIP7. + */ + +#ifndef ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID +#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7 +#pragma message("ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID implicitly defaulted to 7!") +#endif + +/** + * The following macros define + * - the Software DMA channel identifier to be used in CRC DMA driven operations + * - the ISR used by the CRC, which depends on the Software DMA channel + * selected to drive the CRC in DMA driven CRC operations. + * - the interrupt identifier mapped to the software DMA channel; selected for + * the CRC operations + */ +#if (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 0) +#define ADI_CFG_CRC_DMA_CHANNEL SIP0_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP0_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH16_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 1) +#define ADI_CFG_CRC_DMA_CHANNEL SIP1_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP1_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH17_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 2) +#define ADI_CFG_CRC_DMA_CHANNEL SIP2_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP2_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH18_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 3) +#define ADI_CFG_CRC_DMA_CHANNEL SIP3_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP3_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH19_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 4) +#define ADI_CFG_CRC_DMA_CHANNEL SIP4_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP4_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH20_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 5) +#define ADI_CFG_CRC_DMA_CHANNEL SIP5_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP5_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH21_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 6) +#define ADI_CFG_CRC_DMA_CHANNEL SIP6_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP6_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH22_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 7) +#define ADI_CFG_CRC_DMA_CHANNEL SIP7_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP7_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH23_DONE_IRQn +#else +#error "Invalid Software DMA channel identifier ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID: it must be between 0 and 7" +#endif + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/*! \cond PRIVATE */ + +/** Check the validity of a CRC device identifier */ +#define ADI_CRC_VALID_DEVICE_ID(DEVNUM) ((DEVNUM)<(ADI_CRC_NUM_DEVICES)) + +/** Check that a CRC driver is in idle state */ +#define ADI_CRC_DEVICE_IS_IDLE(DEV) (((DEV)->eCrcOpStatus == ADI_CRC_OP_IDLE) ? true : false) + +/*============== D A T A ===============*/ + +/** + * Information for managing all the CRC devices available + */ +static ADI_CRC_INFO crc_device_info[ADI_CRC_NUM_DEVICES] = +{ + { pADI_CRC0, NULL } /* CRC 0 */ +}; + +/*============== M O R E D E F I N E S ===============*/ + +/** Check the validity of a CRC handle for debug mode */ +#define ADI_CRC_INVALID_HANDLE(h) ((NULL == (h)) || (crc_device_info[0].hDevice != (h))) + +/** Condition used to indicate if a CRC driver is already in use */ +#define ADI_CRC_DEVICE_IN_USE(DEVNUM) ((NULL) != crc_device_info[(DEVNUM)].hDevice) + +#ifdef ADI_DEBUG +#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_INVALID_HANDLE(HDL)) ? (NULL) : ((ADI_CRC_DEVICE*) (HDL))) +#else +#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_DEVICE*) (HDL)) +#endif + +/*============= C O D E =============*/ + +#if (ADI_CRC_NUM_DEVICES!=1u) +#error "!!! Current CRC driver implementation can deal with a unique CRC instance !!!" +#endif + +/*============= L O C A L F U N C T I O N S =============*/ + +/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */ + +static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice); + +static void crc_ResetRegisters (ADI_CRC_DEVICE *pDevice); + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + +/* Functions specific to core driven CRC operations */ + +static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation (ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits); + +#else + +/* Functions specific to DMA driven CRC operations */ + +static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits); +static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits); +static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg); +void ADI_DMA_CRC_ISR(void); + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + +/** + * @brief return a pointer to the CRC device information mapped to the CRC + * device identified by a handle + * + * @param [in] hDevice CRC device handle + * + * @return pointer to CRC device information identified by hDevice + * (NULL if the CRC device handle is invalid) + */ +static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice) +{ + ADI_CRC_INFO *pCrcInfo = (ADI_CRC_INVALID_HANDLE(hDevice)) + ? NULL + : (&(crc_device_info[0])); + return pCrcInfo; +} + + +/** + * @brief Reset CRC registers to default values + * + * @details Reset CRC registers to default values as defined in configuration. + * + * @param [in] pDevice Pointer to CRC device + * + * @return None + */ +static void crc_ResetRegisters(ADI_CRC_DEVICE *pDevice) +{ + /* Cast the values to be assigned to the targetted types */ + const uint32_t byte_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BYTE_MIRRORING; + const uint32_t byte_mirroring_pos = (uint32_t) BITP_CRC_CTL_BYTMIRR; + const uint32_t bit_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BIT_MIRRORING; + const uint32_t bit_mirroring_pos = (uint32_t) BITP_CRC_CTL_BITMIRR; + const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE; + const uint32_t polynomial = (uint32_t) ADI_CFG_CRC_POLYNOMIAL; + + /* Set byte mirroring and bit mirroring in CTL register as configured */ + pDevice->pReg->CTL = ( (byte_mirroring_val << byte_mirroring_pos) + | (bit_mirroring_val << bit_mirroring_pos) + ); + pDevice->pReg->RESULT = seed_value; + pDevice->pReg->POLY = polynomial; +} + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + +/* + * @brief Starts core driven CRC operation. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pCrcBuf Address of data buffer. + * @param [in] NumBytes Number of bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - ADI_CRC_SUCCESS: Successfully set expected CRC result. + */ +static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation( + ADI_CRC_DEVICE *pDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + uint8_t *pData = (uint8_t *)pCrcBuf; /* initialize the pointer to data to the start of the data buffer */ + uint32_t lsbFirst = pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST; + + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /*! enable CRC peripheral */ + + if (((uint32_t)pData & 0x3u) != 0u) /* If the buffer is not 4-byte aligned */ + { + /* feed the CRC byte per byte as long as there are data in the input buffer AND + * the data left in the buffer are not 4-byte aligned */ + while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u)) + { + pDevice->pReg->IPBYTE = *pData; /* feed the CRC with the first byte in the buffer */ + pData++; /* get the next byte to feed into CRC */ + NumBytes--; /* decrease the number of bytes to be processed */ + } + } + + /* data left in the input buffer are now 4-byte aligned */ + + while (NumBytes >= 4u) /* if the number of bytes left is greater than 4 bytes */ + { /* feed CRC peripheral with 4-byte data */ + uint32_t nData; /* 32-bit variable to be used to feed the CRC peripheral */ + + /* + * Here we assume memory is little endian. We need change the following + * code if we produce a Cortex-M processor with big endian memory. + */ + if (lsbFirst != 0u) + { + nData = pData[3]; + nData = (nData << 8) | pData[2]; + nData = (nData << 8) | pData[1]; + nData = (nData << 8) | pData[0]; + } + else + { + nData = pData[0]; + nData = (nData << 8) | pData[1]; + nData = (nData << 8) | pData[2]; + nData = (nData << 8) | pData[3]; + } + pDevice->pReg->IPDATA = nData; /* feed the CRC peripheral with 32-bit data input */ + pData += 4; /* move the data pointer in the data buffer */ + NumBytes -= 4u; /* decrease the number of data to be processed */ + } + + while (NumBytes > 0u) /* if the number of data left in the input buffer is smaller than 4 */ + { + pDevice->pReg->IPBYTE = *pData; /* feed the CRC peripheral with the remaining bytes */ + pData++; /* move the pointer to the next byte in input data buffer */ + NumBytes--; /* decrease the number of data to be fed into the CRC peripheral */ + } + + if (NumBits > 0u) /* if the last byte is a partial byte containing less than 8 bits */ + { + pDevice->pReg->IPBITS[NumBits] = *pData;/* feed the CRC peripheral with the remaining bits (use IPBITS[N] to feed N bits) */ + } + + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); /* All the data have been fed into the CRC peripheral : disable it */ + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC back in idle state */ + return result; +} + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/** + * @brief Send a Memory DMA request to the CRC, which triggers a DMA driven + * CRC operation. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pCrcBuf Address of data buffer. + * @param [in] NumBytes Number of whole bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set expected CRC result. + * - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC + */ +static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation( + ADI_CRC_DEVICE *pDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + uint8_t *pData = (uint8_t *)pCrcBuf; + bool bUseDma = false; /* assume core driven CRC by default */ + +#ifdef ADI_DEBUG + if (!ADI_CRC_VALID_DMA_CHANNEL(ADI_CFG_CRC_DMA_CHANNEL)) + { + /* Report error as Memory DMA not open */ + result = ADI_CRC_INVALID_DMA_CHANNEL; + } + else +#endif /* ADI_DEBUG */ + { + /* If LSBFIRST, it's easy. */ + if ((pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST) != 0u) + { + /* If the buffer is not 4-byte aligned */ + if (((uint32_t)pData & 0x3u) != 0u) + { + /* process the first bytes until a 4-byte aligned data location is reached */ + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /* enable CRC */ + while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u)) + { + pDevice->pReg->IPBYTE = *pData; /* feed byte into CRC */ + pData++; /* get to the next byte */ + NumBytes--; /* decrease the number of bytes still to be processed */ + } + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); /* disable CRC */ + } + + /* 4-byte aligned data transfer */ + if (NumBytes >= 4u) + { + /* there are enough data for kicking off a DMA driven CRC operation */ + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + const uint32_t numData = NumBytes / 4u; /* number of 4-byte data to be transferred */ + const uint32_t src = (uint32_t) pData; /* DMA source address */ + const uint32_t dst = (uint32_t) &pDevice->pReg->IPDATA; /* destination is CRC IPDATA 32-bit register */ + const uint32_t numTransData = ( (numData > DMA_TRANSFER_LIMIT) + ? DMA_TRANSFER_LIMIT + : numData + ); + const uint32_t numTransBytes = (numTransData << 2u); + const uint32_t lastDataPos = (numTransBytes - 4u); /* position of last 32-bit data to be transferred in current DMA request */ + + pDevice->pReg->CTL |= ((uint32_t) BITM_CRC_CTL_EN); /* enable CRC (leave other bits unmodified) */ + + pADI_DMA0->EN_SET = channelBit; /* Enable the channel */ + pADI_DMA0->ALT_CLR = channelBit; /* Set the primary as the current DMA descriptor */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* Ensure decrement for source is cleared */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* Ensure decrement for destination is cleared */ + + pPrimaryCCD[channelId].DMADSTEND = dst; /* destination is CRC IPDATA 32-bit register */ + pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos; /* source end address */ + + pPrimaryCCD[channelId].DMACDC = + ( (((uint32_t) ADI_DMA_INCR_NONE) << ((uint32_t) DMA_BITP_CTL_DST_INC)) /* destination address not incremented */ + | (((uint32_t) ADI_DMA_INCR_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_INC)) /* source address incremented by 4 bytes */ + | (((uint32_t) ADI_DMA_WIDTH_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 4-byte */ + | ((numTransData - 1u) << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */ + | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL) /* DMA Auto Request transmission */ + ); + pDevice->pRemainingData = (void*)(src + numTransBytes); /* remaining data start address */ + pDevice->RemainingBytes = NumBytes - numTransBytes; /* remaining bytes that cannot be processed in this DMA batch */ + pDevice->RemainingBits = NumBits; /* remaining bits if last byte is a partial byte */ + bUseDma = true; /* there are enough data to run 4-byte DMA transfers to CRC */ + } + } + /* + * If ! LSBFIRST, we need the DMA controller support byte swap for fixed destination address. + * But we don't have such luck, although it supports byte swap for fixed source address. + * So we have to set DMA size to one byte, which is slower. + * + * Another option is using mirroring feature of CRC unit, which would be more complicated. + */ + else + { + if (NumBytes > 0u) + { + /** + * There are enough data for kicking off a DMA driven CRC operation. + * DMA transfers are limited to 1024 bytes : if the buffer is larger + * than 1024 then generate repeated DMA request through the CRC DMA + * interrupt handler, i.e. the interrupt handler used by the software + * DMA channel driving the CRC operations. + */ + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + const uint32_t src = (uint32_t) pData; /* DMA source address */ + const uint32_t dst = (uint32_t) &pDevice->pReg->IPBYTE; /* destination is CRC IPBYTE 8-bit register */ + const uint32_t numTransData = ( (NumBytes > DMA_TRANSFER_LIMIT) + ? DMA_TRANSFER_LIMIT + : NumBytes + ); + const uint32_t lastDataPos = (numTransData - 1u); /* position of last data to be transferred in buffer */ + + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /* enable CRC (leave other bits unmodified) */ + + pADI_DMA0->EN_SET = channelBit; /* Enable the channel */ + pADI_DMA0->ALT_CLR = channelBit; /* Set the primary as the current DMA descriptor */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* Ensure decrement for source is cleared */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* Ensure decrement for destination is cleared */ + + pPrimaryCCD[channelId].DMADSTEND = dst; /* destination is CRC IPBYTE 8-bit register */ + pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos; /* source end address */ + pPrimaryCCD[channelId].DMACDC = + ( (((uint32_t) ADI_DMA_INCR_NONE) << ((uint32_t) DMA_BITP_CTL_DST_INC)) /* destination address not incremented */ + | (((uint32_t) ADI_DMA_INCR_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_INC)) /* source address incremented by 1 byte */ + | (((uint32_t) ADI_DMA_WIDTH_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 1-byte */ + | ((numTransData - 1u) << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */ + | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL) /* DMA Auto Request transmission */ + ); + pDevice->pRemainingData = (void*) (src + numTransData); /* remaining data start address */ + pDevice->RemainingBytes = NumBytes - numTransData; /* remaining bytes */ + pDevice->RemainingBits = NumBits; /* remaining bits if last byte is a partial byte */ + bUseDma = true; /* there are enough data to run 4-byte DMA transfers to CRC */ + } + } + + /* if we are in a position to use the DMA to transfer data to the CRC */ + if (bUseDma== true) + { + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + pADI_DMA0->SWREQ = channelBit; /* Issue a software DMA request */ + } + else + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); + crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits); + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); + if(pDevice->pfCallback != NULL) + { + pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, pData); + } + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC calculation completed */ + } + } + return result; +} + +/** + * @brief Completes a DMA driven CRC operation by dealing with remaining + * data, usually when the number of bytes left is smaller than 4. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pData Address of data buffer. + * @param [in] NumBytes Number of whole bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + */ +static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits) +{ + /* process the remaining bytes */ + while (NumBytes > 0u) + { + pDevice->pReg->IPBYTE = *pData; + pData++; + NumBytes--; + } + + /* process the remaining bits in the last byte if the number of bits is smaller than 8 */ + if (NumBits > 0u) + { + pDevice->pReg->IPBITS[NumBits] = *pData; + } +} + +/** + * @brief Callback function used by the DMA when a DMA error occurs + * + * @details Callback function used by the DMA when a DMA error must be reported + * to the CRC driver because it affects the DMA channel driving the CRC. + */ +static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg) +{ + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(pcbparam); + + if (NULL != pDevice) + { + /* DMA error detected */ + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* mark the CRC peripheral as IDLE */ + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_EN)); /* disable CRC peripheral */ + } +} + +/** + * @brief interrupt handler used by the software DMA channel driving the CRC + * + * @details interrupt handler used by the software DMA channel driving the CRC + * ADI_DMA_CRC_ISR is a macro with the final interrupt handler name + * being DMA_SIP0_Int_Handler, ..., DMA_SIP7_Int_Handler, depending + * on the software DMA channel driving the CRC. + */ +void ADI_DMA_CRC_ISR(void) +{ + ISR_PROLOG(); + + if (ADI_CRC_DEVICE_IN_USE(0)) + { + ADI_CRC_DEVICE * pDevice = HDL_TO_DEVICE_PTR(crc_device_info[0].hDevice); + if (NULL != pDevice) + { + uint8_t *pData = (uint8_t *)(pDevice->pRemainingData); + uint32_t NumBytes = pDevice->RemainingBytes; + uint32_t NumBits = pDevice->RemainingBits; + bool finishing = (NumBytes < 4u); + + if (!finishing) + { + /* there's enough data left for another DMA transfer */ + ADI_CRC_RESULT result = pDevice->pfSubmitBuffer(pDevice, pData, NumBytes, NumBits); + if (ADI_CRC_SUCCESS != result) + { + /* buffer submission failed: complete the task through core driven operations */ + finishing = true; + } + } + + if (finishing) + { + /* There are a very few bytes/bits left to be processed or + * a DMA transfer request could not be sent */ + crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits); + + /* if a callback function is registered with the interrupt handler + * associated with the software DMA channel driving the CRC */ + if(pDevice->pfCallback != NULL) + { + pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, NULL); + } + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC back in idle state */ + + } + } + } + +#if defined(ADI_CYCLECOUNT_CRC_ISR_ENABLED) && (ADI_CYCLECOUNT_CRC_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_CRC); +#endif + + ISR_EPILOG(); +} + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/*! \endcond */ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Opens a CRC device instance. + * + * @param [in] DeviceNum Number identifying the CRC Device to open. + * @param [in] pMemory Pointer to a #ADI_CRC_MEMORY_SIZE. + * sized buffer to manage the device instance. + * @param [in] MemorySize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where CRC device handle to be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully opened a CRC device. + * - #ADI_CRC_BAD_DEVICE_NUMBER [D]: Supplied CRC Device ID is invalid. + * - #ADI_CRC_IN_USE [D]: Supplied CRC Device ID is already in use. + * - #ADI_CRC_INSUFFICIENT_MEMORY [D]: Supplied memory is not sufficient to handle a CRC device instance. + * - #ADI_CRC_FAILURE [D]: callback registration failed for CRC function used by DMA Error Interrupt Handler. + * + * @note For the device memory should be of size #ADI_CRC_MEMORY_SIZE. + * + */ +ADI_CRC_RESULT adi_crc_Open( + uint32_t DeviceNum, + void *pMemory, + uint32_t MemorySize, + ADI_CRC_HANDLE *phDevice) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = (ADI_CRC_DEVICE*) pMemory;/* memory block to be used to manage a CRC driver instance */ + +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (!ADI_CRC_VALID_DEVICE_ID(DeviceNum)) /* IF (This is not a valid CRC device number) */ + { + result = ADI_CRC_BAD_DEVICE_NUMBER; /* Report failure as bad device number */ + } + else if (ADI_CRC_DEVICE_IN_USE(DeviceNum)) /* IF (The device is in use) */ + { + result = ADI_CRC_IN_USE; /* return CRC Device in use error */ + } + else if ( (MemorySize < ADI_CRC_MEMORY_SIZE) /* IF (Supplied memory size is insufficient) */ + || (ADI_CRC_MEMORY_SIZE < sizeof(ADI_CRC_DEVICE)) + ) + { + result = ADI_CRC_INSUFFICIENT_MEMORY; /* Report failure as insufficient memory */ + } + else +#endif /* ADI_DEBUG */ + { + /* check that ADI_CRC_MEMORY_SIZE is accurately defined */ + assert(ADI_CRC_MEMORY_SIZE == sizeof(ADI_CRC_DEVICE)); + + memset(pMemory, 0, MemorySize); /* Clear the given memory */ + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); /* Entering critical region, disable interrupts */ + + /* Save the supplied device memory address */ + crc_device_info[DeviceNum].hDevice = (ADI_CRC_HANDLE)pDevice; + pDevice->pReg = crc_device_info[DeviceNum].pReg; + + ADI_EXIT_CRITICAL_REGION(); /* Re-enable interrupts */ + + crc_ResetRegisters(pDevice); /* Reset CRC registers */ + *phDevice = crc_device_info[DeviceNum].hDevice; /* Pass a valid handle to this CRC device */ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + + pDevice->pfSubmitBuffer = &crc_ExecuteCoreDrivenOperation; + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + pDevice->pfSubmitBuffer = &crc_ExecuteDmaDrivenOperation; + adi_dma_Init(); + + /* Register CRC DMA callback */ +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice)) + { + result = ADI_CRC_FAILURE; + } +#else + adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice); +#endif + NVIC_EnableIRQ(ADI_CRC_IRQ_ID); /* Enable the interrupt for the DMA channel used by CRC */ +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + } + return result; +} + +/** + * @brief Closes CRC device instance opened for use. + * + * @param [in] hDevice Handle to CRC Device instance to close. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully closed CRC device. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FAILURE [D]: callback un-registration failed for CRC function used by DMA Error Interrupt Handler. + */ +ADI_CRC_RESULT adi_crc_Close(ADI_CRC_HANDLE const hDevice) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_INFO *pCrcInfo = crc_DeviceInfo(hDevice); /* get CRC info pointer from CRC handle */ +#ifdef ADI_DEBUG + if (NULL == pCrcInfo) + { + result = ADI_CRC_BAD_HANDLE; /* invalid CRC handle being used */ + } + else +#endif + { +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0) + NVIC_DisableIRQ(ADI_CRC_IRQ_ID); /* Disable the interrupt for the DMA channel used by CRC. */ + /* Register CRC DMA callback */ +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL)) + { + result = ADI_CRC_FAILURE; + } +#else + adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL); +#endif +#endif + pCrcInfo->hDevice = NULL; /* Mark CRC driver as closed */ + } + return result; +} +/*! + * @brief Set the bit mirroring. This function should be called only when device is idle, + * i.e. when no data are being processd by the CRC. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable bit mirroring. + * true : To Enable bit mirroring. + * false : To Disable bit mirroring. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D] :Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * @sa adi_crc_SetByteMirroring(). + * @sa adi_crc_SetWordSwap(). + */ +ADI_CRC_RESULT adi_crc_SetBitMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* Function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_BITMIRR); /* enable bit mirroring */ + } + else + { + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BITMIRR)); /* disable bit mirroring */ + } + return result; +} +/*! + * @brief Set the byte mirroring. This function should be called only when device is disabled. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable byte mirroring. + * true : To Enable byte mirroring. + * false : To Disable byte mirroring. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_EnableBitMirroring(). + * @sa adi_crc_EnableWordSwap(). + */ +ADI_CRC_RESULT adi_crc_SetByteMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* Function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_BYTMIRR); /* enable byte mirroring */ + } + else + { + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BYTMIRR)); /* disable byte mirroring */ + } + return result; +} + +/*! + * @brief Enable the LSB first. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag which indicate whether LSB first OR MSB first for CRC calculation. + * true : For LSB First CRC calculation + * false : For MSB First CRC calculation + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_EnableBitmirroring(). + * @sa adi_crc_EnableWordSwap(). + */ + +ADI_CRC_RESULT adi_crc_SetLSBFirst(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_LSBFIRST); /* enable LSB first (MSB first disable) */ + } + else + { + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_LSBFIRST); /* disable LSB first (MSB first enable) */ + } + return result; +} +/*! + * @brief To enable/disable the word Swap. This function should be called only when device is disabled. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable word swap. + * true : To Enable word swap. + * false : To Disable word swap. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_SetBitMirroring(). + * @sa adi_crc_SetByteMirroring(). + */ +ADI_CRC_RESULT adi_crc_EnableWordSwap(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= BITM_CRC_CTL_W16SWP; /* enable word swap */ + } + else + { + pDevice->pReg->CTL &= ~BITM_CRC_CTL_W16SWP; /* disable word swap */ + } + + return result; +} +/** + * @brief Sets the initial seed value for the CRC operation that is about to take place. + * + * @param [in] hDevice Handle to CRC device instance to work on. + * @param [in] CrcSeedVal Initial seed value for the CRC operation that is about to take place. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set CRC seed value. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_PERMITTED [D] : Function not permitted when CRC operation is in progress. + * + */ +ADI_CRC_RESULT adi_crc_SetCrcSeedVal( + ADI_CRC_HANDLE const hDevice, + uint32_t CrcSeedVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->pReg->RESULT = CrcSeedVal; /* Load the CRC seed value */ + } + return result; +} + +/** + * @brief Sets the 32-bit polynomial for CRC operations. + * + * @param [in] hDevice Handle to CRC device instance to work on. + * @param [in] PolynomialVal 32-bit CRC polynomial to use for CRC operation. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set polynomial value. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress. + * + */ +ADI_CRC_RESULT adi_crc_SetPolynomialVal( + ADI_CRC_HANDLE const hDevice, + uint32_t PolynomialVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->pReg->POLY = PolynomialVal; /* Load Polynomial value */ + } + return result; +} + +/** + * @brief Submits data buffer for CRC computation + * + * @details This API can be used to submit data buffer for CRC computation. + * If NumBits is in [0..7] then the number of bytes to be processed + * is NumBytes plus one partial byte containing NumBits bits. + * If DMA mode of operation is selected, buffer is processed using + * the specified DMA channel. + * + * @param [in] hDevice Handle of CRC device + * @param [in] pCrcBuf Address of CRC data buffer + * @param [in] NumBytes Number of whole bytes in CRC data buffer + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully submitted data buffer. + * - #ADI_CRC_INVALID_PARAMETER [D]: one of the parameter used is invalid. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_SUPPORTED [D]: Function not supported by this CRC revision. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress. + * - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC (from crc_DmaDrivenOperation) + */ +ADI_CRC_RESULT adi_crc_Compute( + ADI_CRC_HANDLE const hDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); +#ifdef ADI_DEBUG + if (NumBits >= 8u) + { + result = ADI_CRC_INVALID_PARAMETER; + } + else if (NULL == pDevice) + { + result = ADI_CRC_BAD_HANDLE; + } + else if (((pDevice->pReg->CTL & BITM_CRC_CTL_REVID) == 0u) && (NumBits != 0u)) + { + result = ADI_CRC_FN_NOT_SUPPORTED; /* Partial byte needs CRC unit revision 1 or up */ + } + else + if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->eCrcOpStatus = ADI_CRC_OP_IN_PROGRESS; /* mark the CRC as in progress */ + result = pDevice->pfSubmitBuffer(pDevice, pCrcBuf, NumBytes, NumBits); + + /* CRC returns in IDLE mode when it has processed all its data, not after submitting a request */ + } + return result; +} + +/** + * @brief Gets the current CRC peripheral status. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [in] pbCrcInProgress Pointer to location to store the current status of CRC peripheral. + * 'true' when CRC peripheral is in currently performing a CRC operation. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set expected CRC result. + * - #ADI_CRC_BAD_HANDLE [D}: Supplied CRC handle is invalid. + * + * @note This function is valid only when device is operating in DMA mode. + * + */ +ADI_CRC_RESULT adi_crc_IsCrcInProgress( + ADI_CRC_HANDLE const hDevice, + bool *pbCrcInProgress) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + + if ((pDevice)->eCrcOpStatus == ADI_CRC_OP_IN_PROGRESS) + { + *pbCrcInProgress = true; + + } + else + { + *pbCrcInProgress = false; + + } + } + return result; +} + +/** + * @brief Gets the final CRC result computed for a data stream + * + * @details This API gets the final CRC result computed for a data stream + * and clears the current and final CRC results register. + * The CRC Current result register holds the current or + * intermediate CRC result. Whenever a CRC operation is initiated, + * the CRC peripheral takes the CRC Current register value as + * initial seed for CRC computation. This API clears both results + * register to start a fresh CRC computation. + * Use the adi_crc_GetCurrentCrcVal() API to get an intermediate + * CRC result without clearing the results register. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [out] pFinalCrcVal Pointer to location where the final CRC result of + * a data stream to be processed will be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully read final CRC result. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_GetFinalCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pFinalCrcVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE; + *pFinalCrcVal = pDevice->pReg->RESULT; /* Get the final CRC result */ + pDevice->pReg->RESULT = seed_value; + } + return result; +} + +/** + * @brief Gets the current/intermediate CRC result computed for a data stream. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [out] pCurrentCrcVal Pointer to location where the intermediate CRC result of + * a data stream to be processed will be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully read current CRC result. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_GetCurrentCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pCurrentCrcVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + *pCurrentCrcVal = pDevice->pReg->RESULT; /* Get the current CRC result */ + } + + return result; +} + +/** + * @brief Registers or unregisters a callback with the CRC device + * + * @details It is not required to register a callback for the operation of the + * driver. Data compare or DMA error will be notified via the + * adi_crc_IsCrcInProgress() API. But if an application requires the + * errors/events to be notified immediately it can register a callback + * with the driver which will be called to notify errors/events. + * + * When a callback is registered the API adi_crc_IsCrcInProgress() + * will not return error. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [in] pfCallback Pointer to application callback function. The callback function + * has the prototype + * void callback(void *pCBParam, uint32_t nEvent, void *pArg) + * To unregister a callback pass the the pointer to the callback + * function as NULL. + * @param [in] pCBParam Callback parameter which will be returned back to the + * application when the callback function is called. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully registered callback. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_RegisterCallback( + ADI_CRC_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void *const pCBParam) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); /* Entering critical region, disable interrupts */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + /* Update CRC Callback information */ + pDevice->pfCallback = pfCallback; + pDevice->pCBParam = pCBParam; + } + + ADI_EXIT_CRITICAL_REGION(); /* Re-enable interrupts */ + + return result; +} + + +/*****/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc_def.h new file mode 100755 index 00000000000..73cdd6c9e7e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crc/adi_crc_def.h @@ -0,0 +1,93 @@ +/*! ***************************************************************************** + * @file: adi_crc_def.h + * @brief: Private header file for for CRC driver. + * @details + * This is a private header file for the CRC driver, + * which contains the API declarations, data and + * constant definitions used in driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_DEF_H +#define ADI_CRC_DEF_H + +/* CRC Driver includes */ +#include + +/*! \cond PRIVATE */ + +typedef struct __ADI_CRC_DEVICE ADI_CRC_DEVICE; +typedef ADI_CRC_RESULT (*CRC_BUFFER_SUBMIT) (ADI_CRC_DEVICE *pDevice, void *pBuffer, uint32_t NumBytes, uint32_t NumBits); + +/* Enumeration of CRC operation status */ +typedef enum +{ + ADI_CRC_OP_IDLE = 0u, /* CRC idle */ + ADI_CRC_OP_IN_PROGRESS = 0x01u, /* CRC operation in progress */ +} ADI_CRC_OP_STATUS; + +#pragma pack(push) +#pragma pack() + +/* Structure to handle CRC Peripheral instance */ +struct __ADI_CRC_DEVICE +{ + volatile ADI_CRC_TypeDef *pReg; + CRC_BUFFER_SUBMIT pfSubmitBuffer; /* Function for submitting CRC data buffer for calculation */ + ADI_CALLBACK pfCallback; /* Client supplied callback function */ + void *pCBParam; /* Client supplied callback parameter */ + void *pRemainingData; /* Pointer to the buffer containing remaining bytes */ + uint32_t RemainingBytes; /* Remaining bytes */ + uint32_t RemainingBits; /* Remaining bits */ + ADI_CRC_OP_STATUS eCrcOpStatus; /* Current status of the CRC Operation */ +}; + +/* Structure to hold CRC device specific information */ +typedef struct +{ + volatile ADI_CRC_TypeDef *pReg; /* CRC peripheral Registers */ + ADI_CRC_HANDLE hDevice; /* CRC device handle */ +} ADI_CRC_INFO; + +#pragma pack(pop) +/*! \endcond */ + +#endif /* ADI_CRC_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c new file mode 100755 index 00000000000..458e71a3975 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto.c @@ -0,0 +1,1624 @@ +/*! ***************************************************************************** + * @file: adi_crypto.c + * @brief: CRYPTO device driver source file. + * @details: This is the Crypto driver implementation file. + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup Crypto_Driver Crypto Driver + * @{ + * + * @brief Crypto Driver + * + * @details + * + * The Crypto controller provides hardware acceleration of various AES cryptographic + * cipher modes, including: ECB, CBC, CTR, CMAC, CCM, SHA-256 and Keyed HMAC; as well + * as Protected Key Storage (PKSTOR) operations for safely storing and using encrypted + * keys. The Crypto block works most efficiently in DMA mode due to the large about + * of data I/O which would otherwise incur a lot of PIO-mode interrupt traffic to manually + * pump data. + * + * Crypto Driver Static Configuration + * + * A number of Crypto cipher modes are able to be configured statically, such that + * if particular mode(s) are not required, the resulting driver footprint can be reduced + * internally by blocking out chunks of code that are not needed. + * + * @note - The application must include drivers/crypto/adi_crypto.h to use this driver. + * @note - This driver optionally uses the DMA driver if DMA is selected and active. + * In this case, the application must include the DMA driver sources to resolve + * DMA symbols. + */ + + +/*======== I N C L U D E ========*/ + +/*! \cond PRIVATE */ +#include +#include +#include + +/* main crypto include file */ +#include + +/* private crypto defines */ +#include "adi_crypto_def.h" + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* dma interface */ +#include +#endif + + +/*======== D E F I N E S ========*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type +*/ +#pragma diag_suppress=Pm123,Pm140,Pm050,Pm088,Pm073,Pm143,Pm152 +#endif /* __ICCARM__ */ + +/* Utility Macros */ +#define CLR_BITS(REG,BITS) ((REG) &= ~(BITS)) +#define SET_BITS(REG,BITS) ((REG) |= (BITS)) +#define IS_ANY_BIT_SET(REG,BITS) (((REG) & (BITS)) != 0u) + + +/* Number of crypto device for the given processor */ +#define NUM_DEVICES (1u) + +/* Compiler-specific mapping of assembly-level byte-swap instruction + IAR is "__REV", and we think Keil is "__rev", but lets see how that + goes when it is undefined for Keil. +*/ +#if defined ( __ICCARM__ ) +#define __ADI_BYTE_SWAP(X) __REV(X) +#elif defined (__GNUC__) +#define __ADI_BYTE_SWAP(X) __builtin_bswap32(X) +#elif defined (__CC_ARM) +#define __ADI_BYTE_SWAP(X) __rev(X) +#else +#error "This toolchain is not supported" +#endif + + +/*======== L O C A L F U N C D E C L ========*/ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void dmaCallback (void *pCBParam, uint32_t Event, void *pArg); +#endif + +#ifdef ADI_DEBUG +/* Validatation routines */ +static ADI_CRYPTO_RESULT ValidateHandle (ADI_CRYPTO_HANDLE const hDevice); +static ADI_CRYPTO_RESULT ValidateUserBuffer (ADI_CRYPTO_TRANSACTION * const pBuffer); +#endif + +/* Generate a uint32_t value from a pointer to a uint8_t buffer */ +static uint32_t u32FromU8p (uint8_t * const pFourBytes); + +/* load KEY registers with provided key */ +static void loadAesKey (uint8_t * const pKey, ADI_CRYPTO_AES_KEY_LEN const keyLen); + +/* Initialize the internal device handle object (user memory) */ +static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice); + +/* Initiate the computation for a buffer */ +static void StartCompute (ADI_CRYPTO_HANDLE const hDevice); + +/* Stop the device */ +static void StopCompute (ADI_CRYPTO_HANDLE const hDevice); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void programDMA (ADI_CRYPTO_HANDLE const hDevice); +#endif + +/* PIO mode write input data */ +static void writePioInputData (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status); + +/* PIO mode read output data */ +static void readPioOutputData (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status); + +/* Flush the input and output buffers */ +static void FlushInputOutputRegisters (ADI_CRYPTO_HANDLE const hDevice); + + +/* pre-defined Crypto interrupt handler prototypes, as linked in IVT */ +void Crypto_Int_Handler(void); +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +void DMA_AES0_IN_Int_Handler (void); +void DMA_AES0_OUT_Int_Handler (void); +#endif + + +/*======== D A T A ========*/ +/* Internal device structure */ + +static CRYPTO_INFO CryptoDevInfo[] = { + {pADI_CRYPT0, /* physical device controller pointer */ + NULL, /* hDevice */ +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + DMA0_CH13_DONE_IRQn, /* DMA input interrupt number */ + DMA0_CH14_DONE_IRQn, /* DMA output interrupt number */ + AES0_IN_CHANn, /* DMA input channel */ + AES0_OUT_CHANn, /* DMA output channel */ + ADI_CRYPTO_SUCCESS, /* DMA error state */ +#endif + } +}; + +/*! \endcond */ + +/*======== C O D E ========*/ + + +/* include PKSTOR extensions into CRYPTO driver... */ +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) +#include "adi_pkstor.c" +#endif + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + +/* Internal Crypto registered DMA Callback for receiving DMA + fault notifications from the shared DMA error handler */ +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) +{ + /* recover device handle */ + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + + /* recover failing channel number */ + uint32_t failingChannel = (uint32_t)pCBParam; + + /* save the DMA error */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_INVALID_DESCR; + break; + default: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR; + break; + } + + /* transfer is toast... post semaphore to unblock any waiters */ + SEM_POST(hDevice); + + /* call user's callback */ + if (0u != hDevice->pfCallback) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaErrorCode, (void*)failingChannel); + } + + /* game over... */ + StopCompute(hDevice); +} +#endif + + +#ifdef ADI_DEBUG +/* Validate the given handle */ +static ADI_CRYPTO_RESULT ValidateHandle(ADI_CRYPTO_HANDLE const hDevice) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_ERR_BAD_DEV_HANDLE; + uint32_t x; + + for (x = 0u; x < NUM_DEVICES; x++) { + if (CryptoDevInfo[x].hDevice == hDevice) { + result = ADI_CRYPTO_SUCCESS; + break; + } + } + + return result; +} +#endif + + +#ifdef ADI_DEBUG +static ADI_CRYPTO_RESULT ValidateUserBuffer(ADI_CRYPTO_TRANSACTION * const pBuffer) +{ + + /* null pointer and zero count checks */ + if ( + (pBuffer->pInputData == NULL) + || (pBuffer->numInputBytes == 0u) + || (pBuffer->pOutputData == NULL) + || (pBuffer->numOutputBytes == 0u) + || ( + (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_LITTLE_ENDIAN) + && (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_BIG_ENDIAN)) + ) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + + /* check buffer pointers for 32-bit alignment */ + if ( (0u != (3u & (uint32_t)pBuffer->pAuthData)) || (0u != (3u & (uint32_t)pBuffer->pInputData)) || (0u != (3u & (uint32_t)pBuffer->pOutputData)) ) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* check buffer sizes for max DMA size */ + if ((MAX_CRYPTO_DMA_BYTES < pBuffer->numAuthBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numInputBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numOutputBytes)) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } +#endif + +#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_SHA) + { + /* SHA output digest is 256-bit and hence the output buffer size should be at least 32 bytes */ + if (pBuffer->numOutputBytes < SHA_OUTPUT_SIZE_IN_BYTES) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + +#if ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CMAC) { + /* CMAC output is always a 128-bit block */ + if (pBuffer->numOutputBytes < CRYPTO_INPUT_SIZE_IN_BYTES) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + if ( + (pBuffer->pKey == NULL) + || ( (pBuffer->eAesKeyLen != ADI_CRYPTO_AES_KEY_LEN_128_BIT) + && (pBuffer->eAesKeyLen != ADI_CRYPTO_AES_KEY_LEN_256_BIT)) + || ( (pBuffer->eCodingMode != ADI_CRYPTO_ENCODE) + && (pBuffer->eCodingMode != ADI_CRYPTO_DECODE))) + { + return ADI_CRYPTO_ERR_BAD_CONFIG; + } + +#if ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CTR) + { + if ((pBuffer->CounterInit & (0xFFF00000u)) != 0u) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } +#endif + +#if ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CCM) + { + if ( ((pBuffer->CounterInit & (0xFFFF0000u)) != 0u) + || ( (pBuffer->pAuthData != NULL) + && ( + (pBuffer->numAuthBytes == 0u) + || (pBuffer->numValidBytes == 0u) + || (pBuffer->numValidBytes > CRYPTO_INPUT_SIZE_IN_BYTES) + || (pBuffer->numOutputBytes < (pBuffer->numInputBytes + CRYPTO_INPUT_SIZE_IN_BYTES)) + ) + ) + ) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + if (pBuffer->numOutputBytes < pBuffer->numInputBytes) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + } + } + +/* FIXME: Issue http://labrea.ad.analog.com/browse/MSKEW-299 describes missing support + for HMAC mode, so reject HMAC submits until support for this mode is implemented. + ***REMOVE THIS BLOCK WHEN HMAC SUPPORT IS ADDED*** +*/ +#if defined (__ADUCM4x50__) +#if ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_HMAC) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } +#endif +#endif /*ADUCM4x50__*/ + + return ADI_CRYPTO_SUCCESS; +} +#endif + + +/** + * @brief Opens a Crypto device instance. + * + * @param [in] nDeviceNum Device number to open. + * @param [in] pMemory Pointer to a #ADI_CRYPTO_MEMORY_SIZE sized buffer to manage the device + * instance. + * @param [in] nMemorySize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where the Crypto device handle is to be written. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Call completed successfully. + * - #ADI_CRYPTO_ERR_BAD_DEVICE_NUM [D] Error: The device number is invalid. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: A parameter is invalid. + * - #ADI_CRYPTO_ERR_INSUFFICIENT_MEM [D] Error: The memory passed to the device is insufficient. + * - #ADI_CRYPTO_ERR_ALREADY_INITIALIZED [D] Error: The device is already opened. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Unable to create semaphore. + * - #ADI_CRYPTO_ERR_DMA_REGISTER Error: Unable to register DMA error callback function. + * + * @sa adi_crypto_Close(). + */ +ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice) +{ + ADI_CRYPTO_HANDLE hDevice = NULL; + +#ifdef ADI_DEBUG + if (nDeviceNum >= NUM_DEVICES) { + return ADI_CRYPTO_ERR_BAD_DEVICE_NUM; + } + + if ((pMemory == NULL) || (phDevice == NULL)) { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + + if (nMemorySize < ADI_CRYPTO_MEMORY_SIZE) { + return ADI_CRYPTO_ERR_INSUFFICIENT_MEM; + } + + if (CryptoDevInfo[nDeviceNum].hDevice != NULL) { + return ADI_CRYPTO_ERR_ALREADY_INITIALIZED; + } + + /* reality checks */ + assert (ADI_CRYPTO_MEMORY_SIZE == sizeof(ADI_CRYPTO_DEV_DATA_TYPE)); + assert (sizeof(ADI_CRYPTO_TRANSACTION) == sizeof(CRYPTO_COMPUTE)); + +#endif /* ADI_DEBUG */ + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* point local device handle to the user memory */ + hDevice = (ADI_CRYPTO_HANDLE)pMemory; + + /* link CRYPTO controller register set */ + hDevice->pDev = CryptoDevInfo[nDeviceNum].pDev; + + /* link device info */ + hDevice->pDevInfo = CryptoDevInfo; + + /* cross-link device handle into device info */ + CryptoDevInfo[nDeviceNum].hDevice = hDevice; + + /* Initialize the driver internals */ + InitializeDevData(hDevice); + + /* create the semaphore */ + SEM_CREATE(hDevice, "crypto_sem", ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* initialize DMA core */ + adi_dma_Init(); + + /* register DMA error callback for INPUT channel */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaInputChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize crypto driver and fail */ + adi_crypto_Close(hDevice); + return ADI_CRYPTO_ERR_DMA_REGISTER; + } + /* register DMA error callback for OUTPUT channel */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaOutputChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize crypto driver and fail */ + adi_crypto_Close(hDevice); + return ADI_CRYPTO_ERR_DMA_REGISTER; + } +#endif + + /* Give the handle back to the application */ + *phDevice = hDevice; + + /* Return success */ + return ADI_CRYPTO_SUCCESS; +} + +/** + * @brief Close the given device instance. + * + * @param [in] hDevice Handle to the device instance. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully closed the device. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Unable to delete semaphore. + * + * @sa adi_crypto_Open(). + */ +ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice) +{ + uint32_t x; + ADI_CRYPTO_RESULT result; + +#ifdef ADI_DEBUG + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } +#endif /* ADI_DEBUG */ + + /* IF (The device is enabled) */ + if (hDevice->bDeviceEnabled) { + result = adi_crypto_Enable(hDevice, false); + if (result != ADI_CRYPTO_SUCCESS) { + return result; + } + } + + /* Destroy the semaphore */ + SEM_DELETE(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + + /* Close the device */ + for (x=0u; x < NUM_DEVICES; x++) { + if (CryptoDevInfo[x].hDevice == hDevice) { + CryptoDevInfo[x].hDevice = NULL; + break; + } + } + + return ADI_CRYPTO_SUCCESS; +} + + +/** + * @brief Register a user callback function. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pfCallback Function pointer to user callback function. Passing a NULL pointer will + * unregister the callback function. + * @param [in] pCBParam Callback function parameter. + * + * @details This function registers a user callback function. The registered function will be called when + * the given computation is over. Registering an active user callback function implies use of the + * (non-blocking) CALLBACK mode during which any subsequent calls to the (blocking-mode) + * #adi_crypto_GetBuffer() API will be rejected. + * + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully registered the callback. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + */ + ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam) +{ +#ifdef ADI_DEBUG + ADI_CRYPTO_RESULT result; + + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } +#endif /* ADI_DEBUG */ + + /* store user's callback values (critical section) */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_CRYPTO_SUCCESS; +} + + +/** + * @brief Submit a Crypto transaction buffer for processing. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pBuffer Pointer to the #ADI_CRYPTO_TRANSACTION structure which contains details + * of the cipher-dependent buffer elements required by the driver. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully submitted the buffer. + * - #ADI_CRYPTO_ERR_COMPUTE_ACTIVE Error: Buffer already submitted. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_BAD_BUFFER [D] Error: The buffer passed to the device is invalid or unsupported. + * + * The buffer submitted is queued for eventual CRYPTO processing. A single buffer may be submitted + * prior to initiating CRYPTO buffer processing. Buffer processing is initiated with the + * #adi_crypto_Enable() call. As buffer processing is completed, the buffer (and result info) + * is retrieved with the #adi_crypto_GetBuffer() API or through the user callback notification. + * + * @note The driver takes ownership of the ADI_CRYPTO_TRANSACTION structure passed to the driver. + * The application must insure the structure is not used and its scope is valid until + * the structure is returned back to the application. + * + * @warning The #ADI_CRYPTO_TRANSACTION buffer is a common superset of all possible cipher mode parameters. + * As such, not all parameters pertain to each cipher mode. It is recommended users clear unused + * parameters prior to configuration for the particular cipher mode. The example provided + * illustrates this with a call to: "memset(&Buffer, 0, sizeof(ADI_CRYPTO_TRANSACTION));" + * before configuring and then submitting each transaction. + * + * @sa adi_crypto_Enable(). + * @sa adi_crypto_GetBuffer(). + * @sa adi_crypto_IsBufferAvailable(). + */ + ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + + /* reject if we already have a user buffer */ + if (NULL != hDevice->pUserBuffer) { + /* computation already active */ + return ADI_CRYPTO_ERR_COMPUTE_ACTIVE; + } + +#ifdef ADI_DEBUG + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } + + /* validate user Buffer */ + if (ADI_CRYPTO_SUCCESS != (result = ValidateUserBuffer(pBuffer))) { + return result; + } +#endif + + /* store user buffer pointer to return later */ + hDevice->pUserBuffer = pBuffer; + + /* initialize internal compute state from user buffer */ + memcpy(&hDevice->Computation, pBuffer, sizeof(ADI_CRYPTO_TRANSACTION)); + + /* don't initiate transaction until we get adi_crypto_Enable() */ + + /* reset dma error code */ + hDevice->dmaErrorCode = ADI_CRYPTO_SUCCESS; + + return result; +} + + +/** + * @brief Get the submitted transaction buffer back from the driver. + * + * @param [in] hDevice Handle to the device instance. + * @param [out] ppBuffer Pointer to a location to which the address of the buffer structure is written. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully got a buffer. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: Pointer to the buffer is NULL. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_DMA_BUS_FAULT Error: DMA bus fault was reported. + * - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR Error: Invalid DMA descriptor was reported. + * - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR Error: An unexpected DMA error was reported. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Semaphore pend request failed. + * - #ADI_CRYPTO_ERR_INVALID_STATE Error: Invalid call when using callback mode. + * + * This is a blocking call and will await transaction completion (if not already). + * This function should not be called if a callback function is registered. + * + * @sa adi_crypto_SubmitBuffer(). + * @sa adi_crypto_IsBufferAvailable(). + */ +ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + + if (ppBuffer == NULL) { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } +#endif /* ADI_DEBUG */ + + if (NULL != hDevice->pfCallback) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } + + /* pend on completion (even if already complete) */ + SEM_PEND(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + + /* give back the user's buffer */ + *ppBuffer = hDevice->pUserBuffer; + + /* clear internal user buffer pointer */ + hDevice->pUserBuffer = NULL; + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + + return result; +} + + +/** + * @brief Peek function to know whether a submitted transaction is complete. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pbAvailable Pointer to a Boolean variable. Set to "true" if there is a completed + * buffer and a call to adi_crypto_GetBuffer is ensured to be successful. + * Set to "false" if there is no completed buffer. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully peeked for a buffer. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: The pointer passed is NULL. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_DMA_BUS_FAULT Error: DMA bus fault was reported. + * - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR Error: Invalid DMA descriptor was reported. + * - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR Error: An unexpected DMA error was reported. + * + * @sa adi_crypto_SubmitBuffer(). + * @sa adi_crypto_GetBuffer(). + */ +ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + if (pbAvailable == NULL) + { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } +#endif /* ADI_DEBUG */ + + /* let the respective PIO/DMA interrupts drive completion... just return that state here */ + *pbAvailable = hDevice->bCompletion; + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + + return result; +} + + +/** + * @brief Enable/Disable the device. Enabling the device causes the submitted buffer to be processed. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] bEnable 'true' to enable and 'false' to disable the device. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully enabled/disabled the device. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_INVALID_STATE [D] Error: Calling enable when device is already enabled or + * disable when the device is already disabled. + * + */ +ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } + if (bEnable == hDevice->bDeviceEnabled) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (true == bEnable) { + + /* device enable */ + + /* Enable the IRQs */ + NVIC_EnableIRQ(CRYPT_EVT_IRQn); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* Enable the DMA interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); +#endif + + /* Mark the device as enabled */ + hDevice->bDeviceEnabled = true; + + /* Start processing buffer */ + StartCompute(hDevice); + + } else { + + /* device disable */ + + /* Disable the IRQs */ + NVIC_DisableIRQ(CRYPT_EVT_IRQn); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* Enable the DMA interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); +#endif + + /* Stop the device */ + StopCompute(hDevice); + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + } + + /* Return success */ + return result; +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/** + * @brief Dynamically Enable/Disable DMA mode for the device. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] bEnable 'true' will enable DMA and 'false' disables the DMA. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully enabled/disabled the DMA. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_INVALID_STATE [D] Error: DMA cannot be enabled or disabled when the device is already enabled. + * + * Manage use of DMA mode dynamically. Presupposes DMA support has been enabled statically + * in the static configuration files via the ADI_CRYPTO_ENABLE_DMA_SUPPORT macro. + * + * @note In addition to requiring that DMA support is enabled (see ADI_CRYPTO_ENABLE_DMA_SUPPORT static + * configuration macro) for #adi_crypto_EnableDmaMode() to be available, use of DMA mode may + * also be statically configured (see ADI_CRYPTO_ENABLE_DMA). Both these macros may be set statically + * to both enable DMA support and to activate the DMA mode in a fully static manner, without need of + * calling adi_crypto_EnableDmaMode() at all (in which case, this function may be eliminated by the linker). + */ +ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable) +{ +#ifdef ADI_DEBUG + ADI_CRYPTO_RESULT result; + + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } + if (hDevice->bDeviceEnabled) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (bEnable) + { + /* Enable DMA and map data pump handler */ + hDevice->bDmaEnabled = true; + + /* Enable the DMA interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + } + else + { + /* Disable DMA and map data pump handler */ + hDevice->bDmaEnabled = false; + + /* Disable the DMA interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + } + + /* Return success */ + return ADI_CRYPTO_SUCCESS; +} +#endif + + + +/*! \cond PRIVATE */ + +/*======== L O C A L F U N C T I O N D E F I N I T I O N S ========*/ + + +/* Convert from a (4-byte) byte pointer to a u32 */ +static uint32_t u32FromU8p(uint8_t * const pFourBytes) +{ + return ( (pFourBytes[3] << 24) | (pFourBytes[2] << 16) | (pFourBytes[1] << 8) | (pFourBytes[0]) ); +} + + +/* load KEY register set by length */ +static void loadAesKey(uint8_t * const pKey, ADI_CRYPTO_AES_KEY_LEN const keyLen) +{ + uint32_t volatile *pKeyReg = pREG_CRYPT0_AESKEY0; + uint8_t *pUserKey = pKey; + uint32_t numKeyWords; + + /* set AES KEY length register */ + CLR_BITS(*pREG_CRYPT0_CFG, BITM_CRYPT_CFG_AESKEYLEN); + SET_BITS(*pREG_CRYPT0_CFG, (uint32_t)keyLen); /* pre-shifted */ + + /* Set the number of keywords to write to the 32-bit keyword registers */ + switch (keyLen) { + case ADI_CRYPTO_AES_KEY_LEN_128_BIT: + numKeyWords = 4u; + break; + case ADI_CRYPTO_AES_KEY_LEN_256_BIT: + numKeyWords = 8u; + break; + default: + numKeyWords = 0u; /* hardware only supports only 128-bit and 256-bit key length (no 192-bit) */ + break; + } + + /* load the key (key registers have write-no-read attribute) */ + for (uint32_t count = 0u; count < numKeyWords; count++) { + *pKeyReg = u32FromU8p(pUserKey); + pKeyReg++; + pUserKey += sizeof(uint32_t); + } +} + + +/* Initialize the device structure */ +static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice) +{ + /* Clear the device structure */ + memset(hDevice, 0, sizeof(ADI_CRYPTO_HANDLE)); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + #if (ADI_CRYPTO_ENABLE_DMA == 1) + hDevice->bDmaEnabled = true; + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + #else + hDevice->bDmaEnabled = false; + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + #endif +#else + /* no DMA support */ + hDevice->bDmaEnabled = false; +#endif +} + + +/* initiate buffer processing (called from crypto enable) */ +static void StartCompute(ADI_CRYPTO_HANDLE const hDevice) +{ + /* clear completion flag */ + hDevice->bCompletion = false; + + /* Get pointer to the compute buffer */ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + + /* Clear any pending interrupts (all are R/W1C) */ + hDevice->pDev->STAT = hDevice->pDev->STAT; + + /* reset crypto config register */ + hDevice->pDev->CFG = 0u; + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + /* reset SHA hardware machine state */ + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_SHAINIT); + } +#endif + + /* program main config register settings */ + SET_BITS(hDevice->pDev->CFG, + ( (uint32_t)pCompute->eCipherMode /* cipher mode */ +#if defined (__ADUCM4x50__) + | (uint32_t)pCompute->eKeyByteSwap /* KEY endianness */ + | (uint32_t)pCompute->eShaByteSwap /* SHA endianness */ +#endif /*ADUCM4x50*/ + | (uint32_t)pCompute->eAesByteSwap /* AES endianness */ + | (uint32_t)pCompute->eAesKeyLen /* AES key length */ + | (uint32_t)pCompute->eCodingMode /* encode mode */ + ) + ); + +#if (CRYPTO_SUPPORT_KEY_REQUIRED) + +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) + + /* if PKSTOR extensions enabled... check is actually in use. */ + + /* load AES key indirectly from encrypted key in PKSTOR (no 512-bit keys allowed here) */ + if ( (true == pCompute->bUsePKSTOR) && ((ADI_PK_KUW_LEN_128 == pCompute->pkKuwLen) || (ADI_PK_KUW_LEN_256 == pCompute->pkKuwLen)) ) + { + /* retrieve and unwrap key from PKSTOR and "use" it (load it into AES register set) */ + adi_crypto_pk_EnablePKSTOR (hDevice, true); + adi_crypto_pk_SetKuwLen (hDevice, pCompute->pkKuwLen); + adi_crypto_pk_LoadDeviceKey (hDevice); + adi_crypto_pk_RetrieveKey (hDevice, pCompute->pkIndex); + adi_crypto_pk_UnwrapKuwReg (hDevice); + adi_crypto_pk_UseDecryptedKey (hDevice); + adi_crypto_pk_EnablePKSTOR (hDevice, false); + } + else +#endif /*ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT */ + { + /* load AES key directly from compute block... */ + if (NULL != pCompute->pKey) { + loadAesKey(pCompute->pKey, pCompute->eAesKeyLen); + } + } /* if PKSTOR / else */ + +#endif /* (CRYPTO_SUPPORT_KEY_REQUIRED) */ + +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CMAC == pCompute->eCipherMode) { + /* program CMAC-specific registers */ + /* DATALEN in CMAC mode is number of 128 bit pages (or 16, 8 byte pages) */ + hDevice->pDev->DATALEN = pCompute->numInputBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + } +#endif /* (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) { + /* program CMM-specific registers */ + hDevice->pDev->PREFIXLEN = pCompute->numAuthBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + hDevice->pDev->DATALEN = pCompute->numInputBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + hDevice->pDev->CCM_NUM_VALID_BYTES = pCompute->numValidBytes; + } +#endif /* (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + + if ( (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CTR == pCompute->eCipherMode) ) + { + /* program NONCE/IV for CBC, CCM and CTR modes */ + assert (NULL != pCompute->pNonceIV); + + /* Configure Counter Init and NONCE values */ + hDevice->pDev->CNTRINIT = pCompute->CounterInit; + + hDevice->pDev->NONCE0 = u32FromU8p(&pCompute->pNonceIV[0]); + hDevice->pDev->NONCE1 = u32FromU8p(&pCompute->pNonceIV[4]); + hDevice->pDev->NONCE2 = u32FromU8p(&pCompute->pNonceIV[8]); + + hDevice->pDev->NONCE3 = ((uint32_t)pCompute->pNonceIV[12] << 0u) | ((uint32_t)pCompute->pNonceIV[13] << 8u); + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) { + + /* additionally, CBC mode requires remaining IV data */ + hDevice->pDev->NONCE3 |= ( ((uint32_t)pCompute->pNonceIV[14] << 16u) | ((uint32_t)pCompute->pNonceIV[15] << 24u) ); + } +#endif /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) */ + } +#endif /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + + /* onle enable DMA for non-SHA mode or SHA mode with > 4 bytes of input... */ + if ( ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode)) + || ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) && (4u < pCompute->numInputBytesRemaining)) ) + { + + /* DMA startup... */ + programDMA(hDevice); + + /* mode-specific DMA interrupt enables */ + switch (pCompute->eCipherMode) { +#if defined (__ADUCM4x50__) + case ADI_CRYPTO_MODE_HMAC: + /* enable HMAC done and overrun interrupts (via PIO handler) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_INOVREN)); + break; +#endif /*ADUCM4x50__*/ + case ADI_CRYPTO_MODE_SHA: + /* enable SHA done and overrun interrupts */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN)); + SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN)); + break; + default: + /* enable DMA I/O interrupts */ + SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_OUTDMAEN | BITM_CRYPT_CFG_INDMAEN)); + break; + } + + /* crypto hardware enable */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + } else +#endif + { + /* mode-specific PIO interrupt enables */ + switch (pCompute->eCipherMode) { +#if defined (__ADUCM4x50__) + case ADI_CRYPTO_MODE_HMAC: + /* HMAC done interrupts via PIO handler (do NOT use INRDY in HMAC mode) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INOVREN)); + break; +#endif /*ADUCM4x50__*/ + case ADI_CRYPTO_MODE_SHA: + /* SHA done interrupts via PIO handler (do NOT use INRDY in SHA mode) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN)); + break; + default: + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_INOVREN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INRDYEN)); + break; + } + + /* crypto hardware enable */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + /* manual write of 1st input data batch... (interrupt-driven hereafter...) */ + writePioInputData(hDevice, hDevice->pDev->STAT); + } +} + + +/* halt computation */ +static void StopCompute (ADI_CRYPTO_HANDLE const hDevice) +{ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* disable Crypto DMA */ + CLR_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN | BITM_CRYPT_CFG_OUTDMAEN)); +#endif + + /* clear all interrupt enables */ + hDevice->pDev->INTEN = 0u; + + /* Flush the buffers */ + FlushInputOutputRegisters(hDevice); + + /* device disable */ + CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + /* Mark the device as disabled */ + hDevice->bDeviceEnabled = false; +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void programDMA(ADI_CRYPTO_HANDLE const hDevice) +{ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + ADI_DCC_TypeDef* pCCD; /* pointer to DMA Control Data Descriptor */ + uint32_t channelBit; + uint32_t num32BitWords; + + /* start with INPUT channel */ + channelBit = 1u << hDevice->pDevInfo->dmaInputChanNum; + + /* disable various stuff */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* disable src endpointer decrement mode */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* disable dst endpointer decrement mode */ + pADI_DMA0->EN_SET = channelBit; /* channel enable */ + pADI_DMA0->RMSK_CLR = channelBit; /* allow Crypto to request DMA service */ + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + /* program input descriptor(s) */ + if (0u != pCompute->pNextAuthInput) { + + /* schedule authentication data into primary descriptor (USING ping-pong mode) */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate PRIMARY descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to primary INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextAuthInput + sizeof(uint32_t) * (pCompute->numAuthBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numAuthBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_PING_PONG << DMA_BITP_CTL_CYCLE_CTL) ); + + + /* schedule input data into alternate descriptor (in basic mode) */ + pADI_DMA0->PRI_CLR = channelBit; /* activate ALTERNATE descriptor */ + pCCD = pAlternateCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to alternate INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + } else +#endif /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + { + + /* no authentication data, just schedule input data into primary descriptor (in basic mode) */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate PRIMARY descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to primary INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Stop SHA-mode input writes one short of last 32-bit word so the DMA input interrupt + can manually call PIO write function to handle SHA end flag and last write manually. */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 2u); + num32BitWords = (pCompute->numInputBytesRemaining - (pCompute->numInputBytesRemaining % sizeof(uint32_t))) / sizeof(uint32_t) - 1u; /* count - 1 */ + } + else +#endif + { + /* stop at last write end */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * ( pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); /* count */ + } + + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + } + +/* don't program output DMA in SHA mode... */ +#if CRYPTO_SUPPORT_MODE_ANY_NON_SHA + + if (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode) { + + /* switch to OUTPUT channel */ + channelBit = 1u << hDevice->pDevInfo->dmaOutputChanNum; + + /* disable various stuff */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* disable src endpointer decrement mode */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* disable dst endpointer decrement mode */ + pADI_DMA0->EN_SET = channelBit; /* channel enable */ + pADI_DMA0->RMSK_CLR = channelBit; /* allow Crypto to request DMA service */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate primary descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaOutputChanNum; /* point to crypto OUTPUT descriptor */ + + + /* setup the endpoints (point to output register & last 4 bytes of output array) */ + pCCD->DMASRCEND = (uint32_t)&hDevice->pDev->OUTBUF; + pCCD->DMADSTEND = (uint32_t)pCompute->pNextOutput + sizeof(uint32_t) * (pCompute->numOutputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numOutputBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + } /* end non-SHA mode */ + +#endif /* CRYPTO_SUPPORT_MODE_ANY_NON_SHA */ +} +#endif /* #if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) */ + + +static void writePioInputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status) +{ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + uint32_t numWritable = FIFO_DEPTH - ((status & BITM_CRYPT_STAT_INWORDS) >> BITP_CRYPT_STAT_INWORDS); + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + /* always send authentication data before input payload is sent */ + if (0u != pCompute->numAuthBytesRemaining) { + + /* fill input FIFO with 32-bit authentication data */ + while ((0u != numWritable) && (0u != pCompute->numAuthBytesRemaining)) { + hDevice->pDev->INBUF = *pCompute->pNextAuthInput; + pCompute->pNextAuthInput++; + pCompute->numAuthBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numWritable--; + } + } else +#endif /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + { + /* no authentication data, process payload input data */ + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Drive up to a full "chunk" of SHA input message data. + Chunk size is limited to 512-bits (64-bytes) by AES + hardware compute block. + */ + + if (pCompute->numInputBytesRemaining >= SHA_CHUNK_MAX_BYTES) + { + /* This is the simple case, load up an entire chunk and let it go */ + for (uint8_t i = 0u; i < SHA_CHUNK_MAX_WORDS; i++) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + } + + pCompute->numShaBitsRemaining -= SHA_CHUNK_MAX_BITS; + pCompute->numInputBytesRemaining -= SHA_CHUNK_MAX_BYTES; + } + else + { + /* The final case, we load up any bytes less than a full chunk and trigger the last word */ + while (FIFO_WIDTH_IN_BITS <= pCompute->numShaBitsRemaining) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + pCompute->numShaBitsRemaining -= FIFO_WIDTH_IN_BITS; + } + + hDevice->pDev->SHA_LAST_WORD = (pCompute->numShaBitsRemaining << BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID) | BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD; + + /* Last write is dummy or not, depending on remaining bit count */ + if (0u == pCompute->numShaBitsRemaining) { + /* dummy write */ + hDevice->pDev->INBUF = 0u; + } else { + /* partial data (last remaining message data word) */ + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + } + + pCompute->numShaBitsRemaining = 0u; + pCompute->numInputBytesRemaining = 0u; + + /* Use output bytes as a way of confirming that we are really done (can't use input bytes/bits) */ + pCompute->numOutputBytesRemaining -= SHA_OUTPUT_SIZE_IN_BYTES; + } + } /* end of SHA mode */ + else +#endif + { + /* full input FIFO with normal payload write (non-SHA) */ + while ((0u != numWritable) && (0u != pCompute->numInputBytesRemaining)) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + pCompute->numInputBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numWritable--; + } + } + } +} + + +static void readPioOutputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status) +{ + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + uint32_t numReadable; + +#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1 + /* Copy the SHA output if enabled */ + if (pCompute->eCipherMode == ADI_CRYPTO_MODE_SHA) + { + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_SHADONE)) { + + /* Get 1 SHADONE per block + 1 SHADONE when we trigger the last word */ + if (0u == pCompute->numOutputBytesRemaining) { +#if ADI_CRYPTO_SHA_OUTPUT_FORMAT == 0 /* Little Endian */ + pCompute->pNextOutput[0] = hDevice->pDev->SHAH7; + pCompute->pNextOutput[1] = hDevice->pDev->SHAH6; + pCompute->pNextOutput[2] = hDevice->pDev->SHAH5; + pCompute->pNextOutput[3] = hDevice->pDev->SHAH4; + pCompute->pNextOutput[4] = hDevice->pDev->SHAH3; + pCompute->pNextOutput[5] = hDevice->pDev->SHAH2; + pCompute->pNextOutput[6] = hDevice->pDev->SHAH1; + pCompute->pNextOutput[7] = hDevice->pDev->SHAH0; +#else + pCompute->pNextOutput[0] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH0); + pCompute->pNextOutput[1] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH1); + pCompute->pNextOutput[2] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH2); + pCompute->pNextOutput[3] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH3); + pCompute->pNextOutput[4] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH4); + pCompute->pNextOutput[5] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH5); + pCompute->pNextOutput[6] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH6); + pCompute->pNextOutput[7] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH7); +#endif + } + } + } + else +#endif + { + /* read any ready non-SHA output from output FIFO */ + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_OUTRDY)) { + numReadable = ((status & BITM_CRYPT_STAT_OUTWORDS) >> BITP_CRYPT_STAT_OUTWORDS); + while ((0u != numReadable) && (0u != pCompute->numOutputBytesRemaining)) { + *pCompute->pNextOutput = hDevice->pDev->OUTBUF; + pCompute->pNextOutput++; + pCompute->numOutputBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numReadable--; + } + } + } + + /* if output count has gone to zero, set completion flag */ + if (0u == pCompute->numOutputBytesRemaining) { + hDevice->bCompletion = true; + } +} + + +/* Flush the Crypto input and output buffers */ +static void FlushInputOutputRegisters(ADI_CRYPTO_HANDLE const hDevice) +{ + /* Set and clear the flush bits to flush the input and output buffers */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH); + CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH); +} + + +/*================ INTERRUPT HANDELING ==================*/ + +/* native PIO-mode (non-DMA) interrupt handler */ +void Crypto_Int_Handler(void) +{ + ISR_PROLOG(); + + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + uint32_t status = hDevice->pDev->STAT; + uint32_t event; + + /* clear status */ + hDevice->pDev->STAT = status; + + /* check for overflow */ + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_INOVR)) { + + /* call user's callback */ + if (0u != hDevice->pfCallback) { + hDevice->pfCallback(hDevice->pCBParam, ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, (void *)status); + } + + /* stop */ + StopCompute(hDevice); + + /* post the semaphore */ + SEM_POST(hDevice); + + return; + } + + /* pull outputs (updates completion flag) */ + readPioOutputData(hDevice, status); + + if (false == hDevice->bCompletion) { + + /* push more inputs, but not in SHA DMA mode (except for when it’s perfectly aligned block) */ + if ((pCompute->eCipherMode != ADI_CRYPTO_MODE_SHA) || (hDevice->bDmaEnabled == false) || (pCompute->numInputBytesRemaining == 0u)) + { + writePioInputData(hDevice, status); + } + + } else { + + /* we're done */ + + /* dispatch to user callback if we have one */ + if (0u != hDevice->pfCallback) { + + /* check for overflow first */ + if (0u != (BITM_CRYPT_STAT_INOVR & status)) { + event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW; + } else { + /* completion message depends on mode */ + switch (hDevice->Computation.eCipherMode) { +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CBC: event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + case ADI_CRYPTO_MODE_CCM: event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + case ADI_CRYPTO_MODE_CTR: event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) + case ADI_CRYPTO_MODE_ECB: event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE; break; +#endif +#if defined (__ADUCM4x50__) /* HMAC support is provided only in ADuCM4x50*/ +#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break; +#endif +#endif /*__ADUCM4x50__*/ +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + case ADI_CRYPTO_MODE_SHA: event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE; break; +#endif + default: event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN; break; + } + } + + /* call user's callback and give back buffer pointer */ + hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer); + + /* clear private copy of user buffer pointer */ + /* (this is done in GetBuffer in non-Callback mode) */ + hDevice->pUserBuffer = NULL; + } + + /* disable interrupts */ + hDevice->pDev->INTEN = 0u; + + /* post the semaphore */ + SEM_POST(hDevice); + } + + ISR_EPILOG(); +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* native DMA input interrupt handler */ +void DMA_AES0_IN_Int_Handler (void) +{ + ISR_PROLOG(); + + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Update the compute structure to reflect the "post DMA" state of the transaction */ + uint32_t numTotalBytes = pCompute->numInputBytesRemaining; + uint32_t num32BitWords = (numTotalBytes - (numTotalBytes % sizeof(uint32_t))) / sizeof(uint32_t) - 1u; + pCompute->numInputBytesRemaining -= num32BitWords*4u; + pCompute->numShaBitsRemaining -= num32BitWords*32u; + pCompute->pNextInput += num32BitWords; + + if ((numTotalBytes % SHA_CHUNK_MAX_BYTES) == 0u) + { + /* For perfect block sizes, need to write the last word WITHOUT triggering SHA_LAST_WORD */ + hDevice->pDev->INBUF = *pCompute->pNextInput; + + pCompute->numInputBytesRemaining = 0u; + pCompute->numShaBitsRemaining = 0u; + } + else + { + /* Go ahead and write the remaining word, and it’s okay to trigger SHA_LAST_WORD */ + writePioInputData(hDevice, hDevice->pDev->STAT); + } + } +#endif + + /* defer post to output interrupt... */ + + ISR_EPILOG(); +} +#endif /* ADI_CRYPTO_ENABLE_DMA_SUPPORT */ + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* native DMA output interrupt handler */ +void DMA_AES0_OUT_Int_Handler (void) +{ + ISR_PROLOG(); + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + uint32_t status = hDevice->pDev->STAT; + uint32_t event; + + /* by the time we get here, everything should be complete */ + + /* dispatch to user callback if we have one */ + if (0u != hDevice->pfCallback) { + + /* check for overflow first */ + if (0u != (BITM_CRYPT_STAT_INOVR & status)) { + event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW; + } else { + /* completion message depends on mode */ + switch (hDevice->Computation.eCipherMode) { +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CBC: event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + case ADI_CRYPTO_MODE_CCM: event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + case ADI_CRYPTO_MODE_CTR: event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) + case ADI_CRYPTO_MODE_ECB: event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE; break; +#endif +#if defined (__ADUCM4x50__) +#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break; +#endif +#endif /*__ADUCM4x50__*/ +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + case ADI_CRYPTO_MODE_SHA: event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE; break; +#endif + default: event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN; break; + } + } + + /* call user's callback and give back buffer pointer */ + hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer); + + /* clear private copy of user buffer pointer */ + /* this is done in GetBuffer in non-Callback mode */ + hDevice->pUserBuffer = NULL; + } + + /* mark completion */ + hDevice->bCompletion = true; + + /* clear status */ + hDevice->pDev->STAT = status; + + /* post the semaphore */ + SEM_POST(hDevice); + + ISR_EPILOG(); +} +#endif /* ADI_CRYPTO_ENABLE_DMA_SUPPORT */ + +/*! \endcond */ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto_def.h new file mode 100755 index 00000000000..da8f40eb8a7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/crypto/adi_crypto_def.h @@ -0,0 +1,226 @@ +/*! + ***************************************************************************** + @file: adi_crypto_def.h + @brief: Crypto Device Driver definitions for ADuCM4x50 processor + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_CRYPTO_DEF_H +#define ADI_CRYPTO_DEF_H + +/*! \cond PRIVATE */ + +#include +#include + +/* pick up compiler-specific alignment directives */ +#include +#define ALIGN4 ALIGNED_PRAGMA(4) + +/* Support Check MACROS */ +#define CRYPTO_SUPPORT_KEY_REQUIRED ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_CCM_ONLY ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CTR_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CBC_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + && (ADI_CRYPTO_ENABLE_CMAC_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_SHA_SUPPORT != 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_ANY_NON_CCM ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_ANY_NON_SHA ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + ) + + +/* PKSTOR config bits */ +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) +#define PK_CONFIG_BITS (BITM_CRYPT_CFG_PRKSTOREN | BITM_CRYPT_CFG_BLKEN ) +#define NUM_PKSTOR_VAL_STRING_WORDS (2) +#endif + + +/* define local MIN/MAX macros, if not already... */ +#ifndef MIN +#define MIN(a,b) (((a)<(b))?(a):(b)) +#endif +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* various size macros */ +#define MAX_CRYPTO_DMA_BYTES (DMA_TRANSFER_LIMIT * sizeof(uint32_t)) + +/* SHA hardware max chunk size attributes */ +#define SHA_CHUNK_MAX_BYTES (64u) +#define SHA_CHUNK_MAX_BITS (SHA_CHUNK_MAX_BYTES * 8U) +#define SHA_CHUNK_MAX_WORDS (16u) + +#define FIFO_WIDTH_IN_BITS (32u) +#define FIFO_WIDTH_IN_BYTES (FIFO_WIDTH_IN_BITS/8u) +#define FIFO_DEPTH (4u) + +#define CRYPTO_INPUT_SIZE_IN_BITS (128u) +#define CRYPTO_INPUT_SIZE_IN_BYTES (CRYPTO_INPUT_SIZE_IN_BITS/8u) + +#define SHA_OUTPUT_SIZE_IN_BITS (256u) +#define SHA_OUTPUT_SIZE_IN_BYTES (SHA_OUTPUT_SIZE_IN_BITS/8u) + + +/* MAKE SURE THIS STRUCT REMAINS *******PERFECTLY ALIGNED******* WITH USER + ADI_CRYPTO_TRANSACTION BECAUSE WE USE BCOPY TO INITIALIZE EACH NEW SUBMIT! + + Internal compute structure reflecting mostly, user ADI_CRYPTO_TRANSACTION, + except for moving data pointers and remaining counts. Contents initialized + directly from from ADI_CRYPTO_TRANSACTION during buffer submit. +*/ +typedef struct _CRYPTO_COMPUTE { + ADI_CRYPTO_CIPHER_MODE eCipherMode; /*!< Cipher mode to use */ + ADI_CRYPTO_CODING_MODE eCodingMode; /*!< Coding Mode (Encryption or Decryption) */ +#if defined (__ADUCM4x50__) + ADI_CRYPTO_KEY_BYTE_SWAP eKeyByteSwap; /*!< KEY endianness */ + ADI_CRYPTO_SHA_BYTE_SWAP eShaByteSwap; /*!< SHA endianness */ +#endif /*__ADUCM4x50__*/ + ADI_CRYPTO_AES_BYTE_SWAP eAesByteSwap; /*!< AES endianness */ + + uint8_t *pKey; /*!< Pointer to the key data pre-formatted as a byte array, according to eAesKeyLen. */ + ADI_CRYPTO_AES_KEY_LEN eAesKeyLen; /*!< The length of the key */ + + uint32_t *pNextAuthInput; /* CCM mode: pointer to user prefix buffer */ + uint32_t numAuthBytesRemaining; /* Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */ + + uint32_t *pNextInput; /* Pointer to next user 32-bit input location */ + uint32_t numInputBytesRemaining; /* Number of input bytes remaining */ + + uint32_t *pNextOutput; /* Pointer to next user 32-bit output location */ + uint32_t numOutputBytesRemaining; /* Number of output bytes remaining */ + + uint8_t *pNonceIV; /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode: + CTR mode = 108-bit NONCE + CCM mode = 112-bit NONCE + CBC mode = 128-bit IV (Initialization Vector) + NONCE and IV assume little endian format, for example: CTR NONCE packing is: + NONCE[0] -> 7:0 + NONCE[1] -> 15:8 + ... + NONCE[13] -> 103:96 + NONCE[14](Bits 3:0) -> 107:104 */ + uint32_t CounterInit; /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */ + uint32_t numValidBytes; /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */ + uint32_t numShaBitsRemaining; /*!< SHA mode: Number of bits remaining in the SHA payload, which may be odd-sized */ + +#if defined (__ADUCM4x50__) + /* PKSTOR extensions used only in context of overriding above key info with protected keys stored in flash. */ + /* Assumes previously wrapped keys have already been stored using adi_crypto_pk_Xxx APIs. */ + bool bUsePKSTOR; /* flag controlling use of PKSTOR key overrides */ + ADI_CRYPTO_PK_KUW_LEN pkKuwLen; /* overriding key size */ + uint8_t pkIndex; /* PKSTOR flash index for key to use */ +#endif +} CRYPTO_COMPUTE; + + +/* Crypto device attributes */ +typedef struct _CRYPTO_INFO { + ADI_CRYPT_TypeDef *pDev; /* Pointer to physical Crypto controller */ + ADI_CRYPTO_HANDLE hDevice; /* Device Handle */ +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + IRQn_Type dmaInputIrqNum; + IRQn_Type dmaOutputIrqNum; + DMA_CHANn_TypeDef dmaInputChanNum; + DMA_CHANn_TypeDef dmaOutputChanNum; + volatile ADI_CRYPTO_RESULT dmaError; /* DMA error collector. */ +#endif +} CRYPTO_INFO; + + +#ifdef __ICCARM__ +/* +* Pm123 (RULE 8.5) there shall be no definition of objects or functions in a header file. +* Exception is to allow the Crypto device data type and instance to be declared simultaniously. +*/ +#pragma diag_suppress=Pm123 +#endif /* __ICCARM__ */ + +/* Crypto driver internal data */ +struct __ADI_CRYPTO_DEV_DATA_TYPE { + bool bDeviceEnabled; /* Boolean flag to signify whether the device is enable/disabled */ + bool bDmaEnabled; /* Boolean flag to signify whether the DMA is enable/disabled */ + bool bCompletion; /* Boolean flag to signify whether a transaction is complete */ + + ADI_CRYPT_TypeDef *pDev; /* Pointer to physical Crypto controller */ + + CRYPTO_INFO *pDevInfo; /* access to device info */ + + CRYPTO_COMPUTE Computation; /* Active computation structure */ + + ADI_CRYPTO_TRANSACTION *pUserBuffer; /* saved user buffer pointer from submit */ + ADI_CALLBACK pfCallback; /* User defined callback function */ + void *pCBParam; /* User defined callback param */ + ADI_CRYPTO_RESULT dmaErrorCode; /* saved DMA error code to return via user API */ + + + SEM_VAR_DECLR /* Blocking object abstraction: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos, etc. */ +} ADI_CRYPTO_DEV_DATA_TYPE; + +#ifdef __ICCARM__ +#pragma diag_default=Pm123 +#endif /* __ICCARM__ */ + +/*! \endcond */ + +#endif /* ADI_CRYPTO_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c new file mode 100755 index 00000000000..7ced9f04492 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/dma/adi_dma.c @@ -0,0 +1,346 @@ +/*! ***************************************************************************** + * @file: adi_dma.c + * @brief: DMA manager global file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + + +/*! \addtogroup DMA_Driver DMA Driver + * uDMA Device Driver. + * @{ + */ + +/*============= I N C L U D E S =============*/ +#include +#include +#include +#include +#include + +/*! \cond PRIVATE */ + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): he basic types of char, int, short, long, float, and double should not be used +* Need to use bool. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm011,Pm140 +#endif /* __ICCARM__ */ + +/*============= D E F I N E S =============*/ + +/* CCD array allocation macros */ +#define CCD_ALIGN (0x400) /* Memory alignment required for CCD array */ +#define CCD_SIZE (32u) /* Configure CCD allocation as an integral power of two, + i.e., 24 channels is allocated as 32 */ + +/*============= R E G I S T E R D E F I N E S =============*/ + + + + +/*============= T Y P E D E F I N E S =============*/ + +/*! DMA Channel callback information structure */ +typedef struct _DMA_CHANNEL { + ADI_CALLBACK pfCallback; /*!< Pointer to the callback func */ + void* pCBParam; /*!< Application Callback param */ +} DMA_CHANNEL_CALLBACK_INFO; + +/*! \struct ADI_DMA_DEV_DATA + * DMA Device instance data structure + * + * CallbackInfo[NUM_DMA_CHANNELSn] + * The semantics of indexes used to access CallbackInfo elements is defined by the semantics + * of the bits in registers DMA_ERRCHNL_CLR and DMA_INVALIDDESC_CLR. The position of these + * bits define the channel nodes of the peripheral they map to, e.g. bit N maps to channel + * node N. + */ +typedef struct { + bool Initialized; /*!< track initialization state. See function adi_dma_Init) */ + DMA_CHANNEL_CALLBACK_INFO CallbackInfo[NUM_DMA_CHANNELSn]; + uint32_t ChannelsInUse; /*!< bits 0 to 26 record active channels */ +} ADI_DMA_DEV_DATA; + + +/*============= D A T A =============*/ + +/* DMA descriptor arrays must be contiguous */ +/* AND impose strict alignment requirements */ +/* Each compiler has different alignment directives */ + +/* ALIGNED: DMA channel control data array declaration */ +ADI_ALIGNED_PRAGMA(CCD_ALIGN) +static ADI_DCC_TypeDef gChannelControlDataArray[CCD_SIZE * 2u] ADI_ALIGNED_ATTRIBUTE(CCD_ALIGN) + +#ifdef ADI_DMA_DESCRIPTORS_IN_VOLATILE_MEMORY + /* conditional placement of DMA descriptor table to volatile memory */ + @ "volatile_ram"; +#else + /* default placement to non-volatile memory (no override) */ + ; +#endif + + +/* pointer to the primary CCD array */ +ADI_DCC_TypeDef* const pPrimaryCCD = &gChannelControlDataArray[0]; + +/* pointer to the alternate CCD array */ +ADI_DCC_TypeDef* const pAlternateCCD = &gChannelControlDataArray[CCD_SIZE]; + + +/*! DMA Device Driver Data instance + * 32 Channel Handles initialized to {0, 0}, i.e. call-back function pointer + * set to NULL and call-back function parameters set to NULL + */ +static ADI_DMA_DEV_DATA DMA_DevData = { + + false, /*!< DMA device data not initialized. (See adi_dma_Init) */ + {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}}, + 0ul /*!< channels-in-use bitfield */ +}; + +/*! pointer to the DMA Device Driver Data instance */ +static ADI_DMA_DEV_DATA* const pDMA_DevData = &DMA_DevData; + +/*============= Local function declarations =============*/ + +/*========== DMA HANDLERS ==========*/ + +/*! DMA Error Handler */ +void DMA_Err_Int_Handler(void); + +/*========== U T I L I T Y M A C R O S ==========*/ + +/*! \endcond*/ +/*============= A P I I M P L E M E N T A T I O N S =============*/ + +/*! + * @brief Initialize the DMA peripheral + * + * @return none + * + * The application must call this API once + * + */ +void adi_dma_Init(void) +{ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + + if( false == pDMA_DevData->Initialized ) + { + pDMA_DevData->Initialized = true; + + /* Enable the DMA Controller */ + pADI_DMA0->CFG |= BITM_DMA_CFG_MEN; + + /* Set descriptor memory base pointer on DMA controller */ + pADI_DMA0->PDBPTR = (uint32_t)pPrimaryCCD; + + /* Enable the DMA Error Interrupt */ + NVIC_EnableIRQ(DMA_CHAN_ERR_IRQn); + + /* Reset per-channel, bitmapped control registers (W1C) */ + const uint32_t w1r_value = (uint32_t) ((1 << NUM_DMA_CHANNELSn) - 1); + pADI_DMA0->RMSK_SET = w1r_value; + pADI_DMA0->EN_CLR = w1r_value; + pADI_DMA0->ALT_CLR = w1r_value; + pADI_DMA0->PRI_CLR = w1r_value; + pADI_DMA0->ERRCHNL_CLR = w1r_value; + pADI_DMA0->ERR_CLR = w1r_value; + pADI_DMA0->INVALIDDESC_CLR = w1r_value; + } + + ADI_EXIT_CRITICAL_REGION(); +} + +/** + * @brief Register a call-back function for a DMA channel. + * + * @param [in] eChannelID The ID of the DMA channel being assigned a call-back function. + * @param [in] pfCallback Pointer to the application callback function. + * @param [in] pCBParam Application callback parameter. + * + * @details The function registers a call-back function for the DMA channel node + * identified by eChannelID and stores the extra parameters this call-back function + * may require. A NULL callback function pointer means "DMA channel unused". + * + * @return Status + * - #ADI_DMA_SUCCESS Successfully registered a call-back function for the given DMA channel node. + * - #ADI_DMA_ERR_NOT_INITIALIZED [D] adi_dma_Init must be called prior registering a call-back function. + * - #ADI_DMA_ERR_INVALID_PARAMETER [D] Some parameter(s) passed to the function is invalid. + */ +ADI_DMA_RESULT adi_dma_RegisterCallback ( + DMA_CHANn_TypeDef const eChannelID, + ADI_CALLBACK const pfCallback, + void* const pCBParam + ) +{ + ADI_DMA_RESULT result = ADI_DMA_SUCCESS; + +#ifdef ADI_DEBUG + /* DMA must be initialized first */ + if (false == pDMA_DevData->Initialized) { + result = ADI_DMA_ERR_NOT_INITIALIZED; + }else{ + const size_t numChannelId = sizeof(pDMA_DevData->CallbackInfo) / sizeof(DMA_CHANNEL_CALLBACK_INFO); + if (numChannelId <= eChannelID) /*!< pDMA_DevData->CallbackInfo definition is invalid */ + { + result = ADI_DMA_ERR_INVALID_PARAMETER; + } + } + if (ADI_DMA_SUCCESS == result) /* if no errors previously detected */ +#endif + { + /* eChannelID cannot be out of range by definition (we use DMA_CHANn_TypeDef) */ + DMA_CHANNEL_CALLBACK_INFO * pChannel = &pDMA_DevData->CallbackInfo[eChannelID]; + + /* Set the callback parameters */ + pChannel->pfCallback = pfCallback; /* assign the pointer to a callback function */ + pChannel->pCBParam = pCBParam; /* store the parameters to be used with the callback function */ + + const uint32_t nChannelBit = (1u << eChannelID); + if (NULL != pfCallback) { + pDMA_DevData->ChannelsInUse |= nChannelBit; /* set the bit to mark the channel as "being used" */ + }else{ + pDMA_DevData->ChannelsInUse &= (~nChannelBit); /* clear the bit to mark the channel as "not being used" */ + } + } + return result; +} + +/*! \cond PRIVATE */ + + +#if defined(__ICCARM__) + +/* ARM Cortex-M3/M4, IAR compiler (CMSIS standard) */ +#define ADI_CLZ(X) __CLZ(X) + +#elif defined(__GNUC__) + +/* ARM Cortex-M3/M4, GNU-ARM compiler */ +#define ADI_CLZ(X) __builtin_clz(X) + +#elif defined(__CC_ARM) + +/* ARM Cortex-M3/M4, Keil compiler */ +#define ADI_CLZ(X) __clz(X) + +#else + +#error "Macro ADI_CLZ undefined!!!" + +#endif + +/*! DMA Error Handler + * + * The DMA Error handler looks at the channels in use which are flagged in register ERRCHNL_CLR + * or INVALIDDESC_CLR and calls the associated call-back functions, if defined. If a call-back + * function is undefined (NULL pointer) then it means the associated driver ignores these errors. + * + * Then, all the bits set in ERRCHNL_CLR and INVALIDDESC_CLR at the time the handler is called + * are cleared. + */ +void DMA_Err_Int_Handler(void) +{ + ISR_PROLOG() + + const uint32_t nErrClr = pADI_DMA0->ERR_CLR; /* get all the bits set in ERR_CLR */ + const uint32_t nErrChnClr = pADI_DMA0->ERRCHNL_CLR; /* get all the bits set in ERRCHNL_CLR */ + const uint32_t nInvdDescClr = pADI_DMA0->INVALIDDESC_CLR; /* get all the bits set in INVALIDDESC_CLR */ + + /* if there are invalid channel descriptors or channel errors amongts the channels in use */ + uint32_t functionsToBeCalled = pDMA_DevData->ChannelsInUse & (nErrChnClr | nInvdDescClr); + + if (functionsToBeCalled > 0u) + { + const uint32_t numBits = sizeof(uint32_t) << 3; /* maximum number of bits to be considered */ + uint32_t nlz; /* number of leading zeroes in functionsToBeCalled */ + + /* For all the bits set in functionsToBeCalled, starting from the MSB */ + for (nlz = (uint32_t) ADI_CLZ(functionsToBeCalled); nlz < numBits; nlz = (uint32_t) ADI_CLZ(functionsToBeCalled)) + { + const uint32_t bitSet = numBits - nlz - 1u; /* bit position in functionsToBeCalled */ + const uint32_t selected_bit = ((uint32_t)1u << bitSet); + DMA_CHANNEL_CALLBACK_INFO* pChannel = &pDMA_DevData->CallbackInfo[bitSet]; + + /* if there's a callback function to be called */ + if (NULL != pChannel->pfCallback) + { + /* define the nature of the error: DMA bus error or else invalid descriptor */ + uint32_t nEvent = ((nErrChnClr & selected_bit) != 0u) + ? (uint32_t)ADI_DMA_EVENT_ERR_BUS + : (uint32_t)ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR; + + /* report the error to the peripheral through the callback function */ + pChannel->pfCallback (pChannel->pCBParam, nEvent, NULL ); + } + + functionsToBeCalled &= ~selected_bit; /* clear bit in functionsToBeCalled */ + } + } + + /* Clear the errors processed in the loop above */ + pADI_DMA0->ERRCHNL_CLR = nErrChnClr; /* W1C: clear only all the bits set in nErrChnClr */ + pADI_DMA0->INVALIDDESC_CLR = nInvdDescClr; /* W1C: clear only all the bits set in nInvdDescClr */ + pADI_DMA0->ERR_CLR = nErrClr; /* W1C: clear only all the bits set in nErrClr */ + + ISR_EPILOG() +} + +/*! \endcond*/ + +/**@}*/ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/adc/adi_adc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/adc/adi_adc.h new file mode 100755 index 00000000000..1794f4ab2c4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/adc/adi_adc.h @@ -0,0 +1,346 @@ +/*! ***************************************************************************** + * @file adi_adc.h + * @brief Main include file for ADC Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_ADC_H +#define ADI_ADC_H + +#include +#include +#include +#include /* for ADI_SEM_SIZE */ + +/** @addtogroup ADC_Driver ADC Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! Amount of memory(In bytes) required by the ADC device driver for managing the operation + * of a ADC controller. The memory is passed to the driver when the driver is opended. + * The memory is completely owned by the driver till the the driver is closed. + * + */ +#define ADI_ADC_MEMORY_SIZE (48u + ADI_SEM_SIZE) /*!< Memory Size of the buffer required by the ADC driver */ + + +/*! + * \enum ADI_ADC_RESULT + * ADC API return codes + */ +typedef enum { + ADI_ADC_SUCCESS = 0, /*!< No Error, API suceeded */ + ADI_ADC_INVALID_DEVICE_NUM, /*!< Invalid device number passed */ + ADI_ADC_INVALID_DEVICE_HANDLE, /*!< Invalid device handle passed */ + ADI_ADC_INVALID_STATE, /*!< Invalid State */ + ADI_ADC_INSUFFICIENT_MEMORY, /*!< Insufficient memory passed to the driver */ + ADI_ADC_IN_USE, /*!< ADC is alreaady in use */ + ADI_ADC_INVALID_PARAMETER, /*!< Invalid parameter passed to the driver */ + ADI_ADC_NULL_POINTER, /*!< Null pointer passed when expecting a valid pointer */ + ADI_ADC_FAILURE, /*!< General ADC Failure */ + ADI_ADC_INVALID_SEQUENCE, /*!< Invalid sequence of API calls */ + ADI_ADC_ERR_RTOS, /*!< RTOS error occurred */ + ADI_ADC_INVALID_OPERATION, /*!< API call is an invalid operation */ + ADI_ADC_INVALID_BUFFER, /*!< Buffer passed to the application is invalid */ + ADI_ADC_BUFFER_OVERFLOW, /*!< Buffer overflow occurred */ + ADI_ADC_DMA_ERROR, /*!< DMA Error occurred */ + ADI_ADC_BAD_SYS_CLOCK, /*!< Could not retrieve core clock value. */ +} ADI_ADC_RESULT; + +/*! + * \enum ADI_ADC_VREF_SRC + * Voltage Reference source selection. + */ +typedef enum { + ADI_ADC_VREF_SRC_INT_1_25_V, /*!< 1.25V Internal Voltage Reference */ + ADI_ADC_VREF_SRC_INT_2_50_V, /*!< 2.50V Internal Voltage Reference */ + ADI_ADC_VREF_SRC_EXT, /*!< External Voltage Reference */ + ADI_ADC_VREF_SRC_VBAT, /*!< Battery Voltage as Voltage Reference source */ +} ADI_ADC_VREF_SRC; + +/*! + * \enum ADI_ADC_RESOLUTION + * Resolution of the ADC. + */ +typedef enum { + ADI_ADC_RESOLUTION_12_BIT, /*!< 12-bit ADC Resolution */ + ADI_ADC_RESOLUTION_13_BIT, /*!< 13-bit ADC Resolution */ + ADI_ADC_RESOLUTION_14_BIT, /*!< 14-bit ADC Resolution */ + ADI_ADC_RESOLUTION_15_BIT, /*!< 15-bit ADC Resolution */ + ADI_ADC_RESOLUTION_16_BIT /*!< 16-bit ADC Resolution */ +} ADI_ADC_RESOLUTION; + +/*! + * \typedef ADI_ADC_CHANNEL + * Typedef for ADC Channels + */ +typedef uint32_t ADI_ADC_CHANNEL; + +/*! + * defines for ADC Channels + */ +#define ADI_ADC_CHANNEL_0 (1u << 0u) /*!< ADC Channel 0 */ +#define ADI_ADC_CHANNEL_1 (1u << 1u) /*!< ADC Channel 1 */ +#define ADI_ADC_CHANNEL_2 (1u << 2u) /*!< ADC Channel 2 */ +#define ADI_ADC_CHANNEL_3 (1u << 3u) /*!< ADC Channel 3 */ +#define ADI_ADC_CHANNEL_4 (1u << 4u) /*!< ADC Channel 4 */ +#define ADI_ADC_CHANNEL_5 (1u << 5u) /*!< ADC Channel 5 */ +#define ADI_ADC_CHANNEL_6 (1u << 6u) /*!< ADC Channel 6 */ +#define ADI_ADC_CHANNEL_7 (1u << 7u) /*!< ADC Channel 7 */ + +/*! + * \enum ADI_ADC_EVENT + * Callback events from the ADC driver. + */ +typedef enum { + ADI_ADC_EVENT_CALIBRATION_DONE, /*!< Calibration done event. arg to the callback function will be NULL. */ + ADI_ADC_EVENT_ADC_READY, /*!< ADC Ready event. arg to the callback function will be null */ + ADI_ADC_EVENT_OVERFLOW, /*!< Overflow event occurred. The channel(#ADI_ADC_CHANNEL) for which the overflow occurred will be passed as arg to the callback function. */ + ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, /*!< High Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */ + ADI_ADC_EVENT_LOW_LIMIT_CROSSED, /*!< Low Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */ +} ADI_ADC_EVENT; + +/*! Structure which hold the details of the buffer and sampling details */ +typedef struct __ADI_ADC_BUFFER { + uint32_t nChannels; /*!< Channels to sample. Should be an ORed value of #ADI_ADC_CHANNEL enum */ + void* pDataBuffer; /*!< Pointer to the Buffer to read the sample value into. If single channel(say Channel 0) is selected + then the format of buffer will be .... but if + multiple channels (say Channel 1 and Channel2) are selected then the format of buffer will be + .... + \n The pBuffer should be 2 byte aligned. + \n + \n If N is the number of channels selected then in single iteration mode the number of samples + written to in the buffer will be N and for multiple iteration, the driver will try to fill the whole + buffer with data and it is preferred that the nBuffSize be able to accommodate a multiple of N samples. + */ + uint32_t nNumConversionPasses; /*!< Num of conversion passes */ + uint32_t nBuffSize; /*!< Size of the buffer supplied */ +} ADI_ADC_BUFFER; + +/* Type def for the ADC Handle. */ +typedef struct __ADI_ADC_DEVICE* ADI_ADC_HANDLE; /*!< ADC Device Handler */ + + +/*============= A P I F U N C T I O N S P R O T O T Y P E S =============*/ + +/* Opens an ADC device instance. */ +ADI_ADC_RESULT adi_adc_Open ( + uint32_t nDeviceNum, + void* pMemory, + uint32_t nMemorySize, + ADI_ADC_HANDLE* phDevice +); + +/* Close the given device instance */ +ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice); + +/* Power up or power down the ADC */ +ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp); + +/* Register the callback */ +ADI_ADC_RESULT adi_adc_RegisterCallback( + ADI_ADC_HANDLE hDevice, + ADI_CALLBACK pfCallback, + void *pCBParam +); + +/* Enables/Disables the ADC Subsystem */ + ADI_ADC_RESULT adi_adc_EnableADCSubSystem ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Returns whether the ADC subsytem is ready */ +ADI_ADC_RESULT adi_adc_IsReady ( + ADI_ADC_HANDLE hDevice, + bool *pbReady +); + +/* Set the voltage reference source */ +ADI_ADC_RESULT adi_adc_SetVrefSource ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_VREF_SRC eVrefSrc +); + +/* Enable/Disable current sink */ +ADI_ADC_RESULT adi_adc_SinkEnable ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Start the ADC Calibration */ +ADI_ADC_RESULT adi_adc_StartCalibration ( + ADI_ADC_HANDLE hDevice +); + + ADI_ADC_RESULT adi_adc_IsCalibrationDone ( + ADI_ADC_HANDLE hDevice, + bool* pbCalibrationDone + ); + + +/* Set the acquisition time of ADC in ADC clock cycles */ +ADI_ADC_RESULT adi_adc_SetAcquisitionTime( + ADI_ADC_HANDLE hDevice, + uint32_t nAcqTimeInAClkCycles +); + +/* Set the delay time of ADC in ADC cycles for multi iteration mode */ +ADI_ADC_RESULT adi_adc_SetDelayTime( + ADI_ADC_HANDLE hDevice, + uint32_t nDelayInAClkCycles +); + +/* set the resolution of ADC. The default resolution of ADC is 12-bit and the ADC increases the resolution by oversampling */ +ADI_ADC_RESULT adi_adc_SetResolution ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_RESOLUTION eResolution +); + +/* Enable Averaging for all ADC channels */ +ADI_ADC_RESULT adi_adc_EnableAveraging ( + ADI_ADC_HANDLE hDevice, + uint16_t nAveragingSamples +); + +/* Configure low limit for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetLowLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nLowLimit +); + +/* Configure high limit for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetHighLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHighLimit +); + + +/* Configure hysteresis for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetHysteresis( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHysteresis +); + +/* Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetNumMonitorCycles( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + uint32_t nNumMonitorCycles +); + +/* Enable/Disable digital comparator for the given channel(s) */ +ADI_ADC_RESULT adi_adc_EnableDigitalComparator ( + ADI_ADC_HANDLE hDevice, + bool bEnableComparator +); + +/* Submit buffer for sampling */ +ADI_ADC_RESULT adi_adc_SubmitBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER* pBuffer +); + +/* Get a completed buffer from the driver */ +ADI_ADC_RESULT adi_adc_GetBuffer( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER** ppBuffer +); + +/* Enable/Disable buffer processing */ +ADI_ADC_RESULT adi_adc_Enable ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Check whether a completed buffer is available in the driver */ +ADI_ADC_RESULT adi_adc_IsBufferAvailable( + ADI_ADC_HANDLE hDevice, + bool* pbIsBufferAvailable +); + +/* Read the given channels. This will only return once the given amount of samples are collected */ +ADI_ADC_RESULT adi_adc_ReadChannels ( + ADI_ADC_HANDLE hDevice, + uint32_t nChannels, + uint32_t nNumConversionPasses, + void* pBuffer, + uint32_t nBuffLength +); + +/* Get Battery Voltage */ +ADI_ADC_RESULT adi_adc_GetBatteryVoltage ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + uint32_t* pnBatVoltage +); + +/* Enable/Disable Temperature Sensor */ +ADI_ADC_RESULT adi_adc_EnableTemperatureSensor ( + ADI_ADC_HANDLE hDevice, + bool bEnable + ); + +/* Get the Temperature Value */ +ADI_ADC_RESULT adi_adc_GetTemperature ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + int32_t* pnTemperature + ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + + +#endif /* ADI_ADC_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/beep/adi_beep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/beep/adi_beep.h new file mode 100755 index 00000000000..6fa441895ec --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/beep/adi_beep.h @@ -0,0 +1,277 @@ +/*! ***************************************************************************** + * @file adi_beep.h + * @brief Main include file for BEEP device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/** @addtogroup BEEP_Driver BEEP Driver +* @{ +*/ +#ifndef ADI_BEEP_H +#define ADI_BEEP_H + +#include "adi_processor.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! Amount of memory(In bytes) required by the Beep device driver for managing the operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 +/*! @hideinitializer Indicates the size of the BEEP memory to be used */ +#define ADI_BEEP_MEMORY_SIZE (20u + ADI_SEM_SIZE) +#else +/*! @hideinitializer Indicates the size of the BEEP memory to be used */ +#define ADI_BEEP_MEMORY_SIZE (12u + ADI_SEM_SIZE) +#endif + +/*! + * \enum ADI_BEEP_RESULT + * Beeper API return codes + */ +typedef enum +{ + ADI_BEEP_SUCCESS = 0, /*!< No Error, API suceeded */ + + ADI_BEEP_FAILURE, /*!< An unknown error was detected */ + ADI_BEEP_ALREADY_INITIALIZED, /*!< BEEP is already initialized */ + ADI_BEEP_BAD_DEV_HANDLE, /*!< Invalid device handle passed */ + ADI_BEEP_BAD_DEV_ID, /*!< Asking to initialize an unknown device num */ + ADI_BEEP_NOT_INITIALIZED, /*!< BEEP not yet initialized */ + ADI_BEEP_PARAM_OUT_OF_RANGE, /*!< Parameter is out of range. */ + ADI_BEEP_INVALID_COUNT, /*!< Invalid count for supplied beep sequence */ + ADI_BEEP_NULL_PTR, /*!< Null pointer supplied. */ + ADI_BEEP_SEMAPHORE_FAILED, /*!< BEEP semaphore failure. */ +} ADI_BEEP_RESULT; + + +/*! + * \enum ADI_BEEP_DEV_ID + * @brief Beeper Device IDs. + * @details List of all Beeper Device IDs for the current part + */ +typedef enum +{ + ADI_BEEP_DEVID_0 = 0, /*!< BEEP Timer Device 0 */ + ADI_BEEP_MAX_DEVID /*!< max number of BEEP devices */ +} ADI_BEEP_DEV_ID; + +/*! + * \enum ADI_BEEP_INTERRUPT + * @brief Beeper Interrupt Bits. + * @details List of all Beeper interrupt (enables and status) bits. + */ +typedef enum +{ + ADI_BEEP_INTERRUPT_SEQUENCE_END = BITM_BEEP_CFG_SEQATENDIRQ, /*!< Beeper sequence has finished */ + ADI_BEEP_INTERRUPT_NOTE_END = BITM_BEEP_CFG_AENDIRQ, /*!< Beeper note has finished */ +} ADI_BEEP_INTERRUPT; + + +#define LFCLK_FREQ 32768.0f /*!< Beeper main clock frequency. */ +#define FREQUENCY_ENCODE(x) (uint8_t)(LFCLK_FREQ/(x) + 0.5f) /*!< Beeper tone frequency encoder macro */ + +/*! + * \enum ADI_BEEP_NOTE_FREQUENCY + * @brief Beeper tone frequency list. + * @details List of possible Beeper tone frequencies. + */ +typedef enum { + /* Constants are pre-computed note frequencies (Hz). */ + /* See http://www.phy.mtu.edu/~suits/notefreqs.html. */ + /* Encodings are clock divider values for that note. */ + /* Flats are the same as the lower sharp, so only sharps are listed. */ + /* Even though octaves are simple frequency doublings/halvings */ + /* of adjuacient octaves, we pre-compute each constant (as opposed */ + /* to halving/doubling the encodings between octaves) to */ + /* minimize repeated doubling/halving errors across all octaves. */ + /* !!!ALL ENCODINGS MUST BE IN THE RANGE 4-127!!! */ + + ADI_BEEP_FREQ_REST = (0), /*!< silence */ + + ADI_BEEP_FREQ_C4 = FREQUENCY_ENCODE(261.63f), /*!< Middle C (lowest representable frequency @ 32KHz) */ + ADI_BEEP_FREQ_Cs4 = FREQUENCY_ENCODE(277.18f), + ADI_BEEP_FREQ_D4 = FREQUENCY_ENCODE(293.66f), + ADI_BEEP_FREQ_Ds4 = FREQUENCY_ENCODE(311.13f), + ADI_BEEP_FREQ_E4 = FREQUENCY_ENCODE(329.63f), + ADI_BEEP_FREQ_F4 = FREQUENCY_ENCODE(349.23f), + ADI_BEEP_FREQ_Fs4 = FREQUENCY_ENCODE(369.99f), + ADI_BEEP_FREQ_G4 = FREQUENCY_ENCODE(392.00f), + ADI_BEEP_FREQ_Gs4 = FREQUENCY_ENCODE(415.30f), + ADI_BEEP_FREQ_A4 = FREQUENCY_ENCODE(440.00f), + ADI_BEEP_FREQ_As4 = FREQUENCY_ENCODE(466.16f), + ADI_BEEP_FREQ_B4 = FREQUENCY_ENCODE(493.88f), + + ADI_BEEP_FREQ_C5 = FREQUENCY_ENCODE(523.25f), + ADI_BEEP_FREQ_Cs5 = FREQUENCY_ENCODE(554.37f), + ADI_BEEP_FREQ_D5 = FREQUENCY_ENCODE(587.33f), + ADI_BEEP_FREQ_Ds5 = FREQUENCY_ENCODE(622.25f), + ADI_BEEP_FREQ_E5 = FREQUENCY_ENCODE(659.26f), + ADI_BEEP_FREQ_F5 = FREQUENCY_ENCODE(698.46f), + ADI_BEEP_FREQ_Fs5 = FREQUENCY_ENCODE(739.99f), + ADI_BEEP_FREQ_G5 = FREQUENCY_ENCODE(783.99f), + ADI_BEEP_FREQ_Gs5 = FREQUENCY_ENCODE(830.61f), + ADI_BEEP_FREQ_A5 = FREQUENCY_ENCODE(880.00f), + ADI_BEEP_FREQ_As5 = FREQUENCY_ENCODE(932.33f), + ADI_BEEP_FREQ_B5 = FREQUENCY_ENCODE(987.77f), + + ADI_BEEP_FREQ_C6 = FREQUENCY_ENCODE(1046.50f), + ADI_BEEP_FREQ_Cs6 = FREQUENCY_ENCODE(1108.73f), + ADI_BEEP_FREQ_D6 = FREQUENCY_ENCODE(1174.66f), + ADI_BEEP_FREQ_Ds6 = FREQUENCY_ENCODE(1244.51f), + ADI_BEEP_FREQ_E6 = FREQUENCY_ENCODE(1318.51f), + ADI_BEEP_FREQ_F6 = FREQUENCY_ENCODE(1396.91f), + ADI_BEEP_FREQ_Fs6 = FREQUENCY_ENCODE(1479.98f), + ADI_BEEP_FREQ_G6 = FREQUENCY_ENCODE(1567.98f), + ADI_BEEP_FREQ_Gs6 = FREQUENCY_ENCODE(1661.22f), + ADI_BEEP_FREQ_A6 = FREQUENCY_ENCODE(1760.00f), + ADI_BEEP_FREQ_As6 = FREQUENCY_ENCODE(1864.66f), + ADI_BEEP_FREQ_B6 = FREQUENCY_ENCODE(1975.53f), + + ADI_BEEP_FREQ_C7 = FREQUENCY_ENCODE(2093.00f), + ADI_BEEP_FREQ_Cs7 = FREQUENCY_ENCODE(2217.46f), + ADI_BEEP_FREQ_D7 = FREQUENCY_ENCODE(2349.32f), + ADI_BEEP_FREQ_Ds7 = FREQUENCY_ENCODE(2489.02f), + ADI_BEEP_FREQ_E7 = FREQUENCY_ENCODE(2637.02f), + ADI_BEEP_FREQ_F7 = FREQUENCY_ENCODE(2793.83f), + ADI_BEEP_FREQ_Fs7 = FREQUENCY_ENCODE(2959.96f), + ADI_BEEP_FREQ_G7 = FREQUENCY_ENCODE(3135.96f), + ADI_BEEP_FREQ_Gs7 = FREQUENCY_ENCODE(3322.44f), + ADI_BEEP_FREQ_A7 = FREQUENCY_ENCODE(3520.00f), + ADI_BEEP_FREQ_As7 = FREQUENCY_ENCODE(3729.31f), + ADI_BEEP_FREQ_B7 = FREQUENCY_ENCODE(3951.07f), + + ADI_BEEP_FREQ_C8 = FREQUENCY_ENCODE(4186.01f), + ADI_BEEP_FREQ_Cs8 = FREQUENCY_ENCODE(4434.92f), + ADI_BEEP_FREQ_D8 = FREQUENCY_ENCODE(4698.64f), + ADI_BEEP_FREQ_Ds8 = FREQUENCY_ENCODE(4978.03f), + ADI_BEEP_FREQ_E8 = FREQUENCY_ENCODE(5274.04f), + ADI_BEEP_FREQ_F8 = FREQUENCY_ENCODE(5587.65f), + ADI_BEEP_FREQ_Fs8 = FREQUENCY_ENCODE(5919.91f), + ADI_BEEP_FREQ_G8 = FREQUENCY_ENCODE(6271.93f), +} ADI_BEEP_NOTE_FREQUENCY; + +#define ADI_BEEP_DUR_ZERO (0) /*!< Beeper zero tone duration value */ +#define ADI_BEEP_DUR_MIN (1) /*!< Beeper minimum tone duration value */ +#define ADI_BEEP_DUR_MAX (254) /*!< Beeper maximum tone duration value */ +#define ADI_BEEP_DUR_INFINITE (255) /*!< Beeper infinite tone duration value */ + +/*! A device handle used in all API functions to identify the BEEP device. */ +typedef void * ADI_BEEP_HANDLE; + +#define DURATION_ENCODE(x) (uint8_t)((float)ADI_BEEP_DUR_MAX/(float)(x) + 0.5f) /*!< Beeper tone duration encoder macro */ + +/*! + * \enum ADI_BEEP_NOTE_DURATION + * @brief Beeper tone duration list. + * @details List of possible Beeper tone durations. + */ +typedef enum { + ADI_BEEP_DUR_0 = ADI_BEEP_DUR_ZERO, /*!< stop */ + ADI_BEEP_DUR_32_32 = DURATION_ENCODE(1), /*!< whole note (1.016 seconds) */ + ADI_BEEP_DUR_16_32 = DURATION_ENCODE(2), /*!< half note */ + ADI_BEEP_DUR_12_32 = DURATION_ENCODE(8/3), /*!< three eights note */ + ADI_BEEP_DUR_8_32 = DURATION_ENCODE(4), /*!< one quarter note */ + ADI_BEEP_DUR_6_32 = DURATION_ENCODE(16/3), /*!< three sixteenth note */ + ADI_BEEP_DUR_4_32 = DURATION_ENCODE(8), /*!< one eighth note */ + ADI_BEEP_DUR_2_32 = DURATION_ENCODE(16), /*!< one sixteenth note */ + ADI_BEEP_DUR_1_32 = DURATION_ENCODE(32), /*!< one thirty-secondth note */ + ADI_BEEP_DUR_N = ADI_BEEP_DUR_INFINITE, /*!< continuous play */ +} ADI_BEEP_NOTE_DURATION; + +/*! + * \struct ADI_BEEP_NOTE + * @brief Beeper note structure. + * @details Describes a note in terms of frequency and duration. + */ +typedef struct { + ADI_BEEP_NOTE_FREQUENCY frequency; /*!< Frequency of the note */ + ADI_BEEP_NOTE_DURATION duration; /*!< Duration of the note */ +} ADI_BEEP_NOTE; + + +/*================ E X T E R N A L S ==================*/ + +/* + * Beeper API + */ + +ADI_BEEP_RESULT adi_beep_Open (ADI_BEEP_DEV_ID const DeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_BEEP_HANDLE* const phDevice); + +ADI_BEEP_RESULT adi_beep_RegisterCallback (ADI_BEEP_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void* const pCBParam); + +ADI_BEEP_RESULT adi_beep_PlayNote (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE note); + +ADI_BEEP_RESULT adi_beep_PlayTwoTone (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE noteA, + ADI_BEEP_NOTE noteB, + uint8_t count); + +ADI_BEEP_RESULT adi_beep_PlaySequence (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE aSequence[], + uint8_t count); + +ADI_BEEP_RESULT adi_beep_Enable (ADI_BEEP_HANDLE const hDevice, + bool const bFlag); + +ADI_BEEP_RESULT adi_beep_Wait (ADI_BEEP_HANDLE const hDevice); + +ADI_BEEP_RESULT adi_beep_Close (ADI_BEEP_HANDLE const hDevice); + +#ifdef __cplusplus +} +#endif + + +#endif /* ADI_BEEP_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crc/adi_crc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crc/adi_crc.h new file mode 100755 index 00000000000..9fddbc60858 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crc/adi_crc.h @@ -0,0 +1,236 @@ +/*! ***************************************************************************** + * @file adi_crc.h + * @brief CRC (Cyclic Redundancy Check) Device driver global include file + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_H +#define ADI_CRC_H + +/** @addtogroup CRC_Driver CRC Device Driver + * @{ + */ + +#include + +/*============= I N C L U D E S =============*/ +#include +/* Memory size check */ +#include + +/* DMA Manager includes */ +#include + +/* Include the config file for CRC */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*============== D E F I N E S ===============*/ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + + +/** + * The size of types may vary between building tools (int, char, enumerator, etc.). + * This impacts the memory size required by a CRC driver. + * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent. + */ +#if defined(__ICCARM__) +/** + * The amount of application supplied memory required to operate a core driven CRC device + * using a CRC driver built in IAR environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#else +/** + * The amount of application supplied memory required to operate a core driven CRC device + * using a CRC driver built in a generic built environment. + * Note: Create a new macro definition for your targetted development environment + * if this generic value was not appropriate in your development environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#endif + + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + +/** + * The size of types may vary between building tools (int, char, enumerator, etc.). + * This impacts the memory size required by a CRC driver. + * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent. + */ +#if defined(__ICCARM__) +/** + * The amount of application supplied memory required to operate a DMA driven CRC device + * using a CRC driver built in IAR environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#else +/** + * The amount of application supplied memory required to operate a DMA driven CRC device + * using a CRC driver built in a generic built environment. + * Note: Create a new macro definition for your targetted development environment + * if this generic value was not appropriate in your development environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#endif + +/** Check that a DMA channel can be used with CRC */ +#define ADI_CRC_VALID_DMA_CHANNEL(DMA_CHANNEL_ID) ((SIP0_CHANn<=(DMA_CHANNEL_ID)) && ((DMA_CHANNEL_ID)<=SIP7_CHANn)) + +/** + * CRC events used in CRC callback functions to report + * - the completion of a DMA driven CRC request + * - errors detected when executing a DMA driven CRC request + */ +typedef enum __ADI_CRC_EVENT +{ + /*! DMA driven CRC peripheral has completed processing a request */ + ADI_CRC_EVENT_BUFFER_PROCESSED = ADI_DMA_EVENT_BUFFER_PROCESSED, + + /*! DMA driven CRC peripheral has encountered a problem when processing a request */ + ADI_CRC_EVENT_ERROR +} ADI_CRC_EVENT; + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/** + * A device handle used in all API functions to identify a CRC device. + * This handle is obtained when opening a CRC driver using adi_crc_Open. + * It stops being valid after closing the CRC driver using adi_crc_Close. + */ +typedef struct __ADI_CRC_DEVICE* ADI_CRC_HANDLE; + +/** + * CRC driver return codes + */ +typedef enum +{ + ADI_CRC_SUCCESS = 0, /*!< 0x00 - Generic success */ + ADI_CRC_FAILURE, /*!< 0x01 - Generic failure */ + ADI_CRC_IN_USE, /*!< 0x02 - Supplied CRC device number is already open and in use */ + ADI_CRC_INSUFFICIENT_MEMORY, /*!< 0x03 - Supplied memory is insufficient to operate the CRC device */ + ADI_CRC_FN_NOT_SUPPORTED, /*!< 0x04 - Function not supported */ + ADI_CRC_FN_NOT_PERMITTED, /*!< 0x05 - Function not permitted at current stage */ + ADI_CRC_BAD_HANDLE, /*!< 0x06 - Bad CRC device handle (can be caused by a CRC device not opened)*/ + ADI_CRC_BAD_DEVICE_NUMBER, /*!< 0x07 - There is no CRC device identified by this number */ + ADI_CRC_INVALID_DMA_CHANNEL, /*!< 0x08 - Invalid DMA channel assigned to a CRC driver */ + ADI_CRC_INVALID_PARAMETER, /*!< 0x09 - Invalid parameter used in a CRC function */ +} ADI_CRC_RESULT; + +/*======= P U B L I C P R O T O T Y P E S ========*/ +/* (globally-scoped functions) */ + +/* Opens a CRC device instance */ +ADI_CRC_RESULT adi_crc_Open( + uint32_t DeviceNum, + void *pMemory, + uint32_t MemorySize, + ADI_CRC_HANDLE *phDevice); + +/* Closes a CRC device instance */ +ADI_CRC_RESULT adi_crc_Close( + ADI_CRC_HANDLE const hDevice); + +/* Registers or unregisters a callback, used by the CRC interrupt handler or with DMA driven operations, with the CRC device */ +ADI_CRC_RESULT adi_crc_RegisterCallback( + ADI_CRC_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void *const pCBParam); + +/* Sets the 32-bit polynomial for CRC operations */ +ADI_CRC_RESULT adi_crc_SetPolynomialVal( + ADI_CRC_HANDLE const hDevice, + uint32_t PolynomialVal); + +/* Submits data buffer for CRC operation */ +ADI_CRC_RESULT adi_crc_Compute( + ADI_CRC_HANDLE const hDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits); + +/* Gets the current CRC peripheral status */ +ADI_CRC_RESULT adi_crc_IsCrcInProgress( + ADI_CRC_HANDLE const hDevice, + bool *pbCrcInProgress); + +/* Gets the final CRC result computed for a data stream */ +ADI_CRC_RESULT adi_crc_GetFinalCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pFinalCrcVal); + +/* Gets the current/intermediate CRC result computed for a data stream */ +ADI_CRC_RESULT adi_crc_GetCurrentCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pCurrentCrcVal); + +ADI_CRC_RESULT adi_crc_SetBitMirroring( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_SetByteMirroring( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_EnableWordSwap( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_SetCrcSeedVal( + ADI_CRC_HANDLE const hDevice, + uint32_t CrcSeedVal); + +ADI_CRC_RESULT adi_crc_SetLSBFirst( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* ADI_CRC_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crypto/adi_crypto.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crypto/adi_crypto.h new file mode 100755 index 00000000000..7b34cbcd9e3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/crypto/adi_crypto.h @@ -0,0 +1,326 @@ +/*! ***************************************************************************** + * @file adi_crypto.h + * @brief Main include file for CRYPTO Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +/** @addtogroup Crypto_Driver Crypto Driver +* @{ +*/ + +#ifndef ADI_CRYPTO_H +#define ADI_CRYPTO_H + + /*! \cond PRIVATE */ +#include +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! + * \enum ADI_CRYPTO_RESULT + * Crypto API return codes + */ +typedef enum +{ + ADI_CRYPTO_SUCCESS = 0, /*!< No Error, API suceeded. */ + ADI_CRYPTO_ERR_ALREADY_INITIALIZED, /*!< Crypto is already initialized. */ + ADI_CRYPTO_ERR_BAD_BUFFER, /*!< Invalid buffer parameters. */ + ADI_CRYPTO_ERR_BAD_CONFIG, /*!< Invalid device config parameters passed. */ + ADI_CRYPTO_ERR_BAD_DEVICE_NUM, /*!< Invalid device instance number. */ + ADI_CRYPTO_ERR_BAD_DEV_HANDLE, /*!< Invalid device handle passed. */ + ADI_CRYPTO_ERR_COMPUTE_ACTIVE, /*!< Computation underway. */ + ADI_CRYPTO_ERR_DMA_BUS_FAULT, /*!< Runtime DMA bus fault detected. */ + ADI_CRYPTO_ERR_DMA_INVALID_DESCR, /*!< Runtime DMA invalid descriptor detected. */ + ADI_CRYPTO_ERR_DMA_REGISTER, /*!< Error registering DMA error callback function. */ + ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR, /*!< Unknown runtime DMA error detected. */ + ADI_CRYPTO_ERR_INSUFFICIENT_MEM, /*!< Insufficient memory passed to the driver. */ + ADI_CRYPTO_ERR_INVALID_PARAM, /*!< Invalid function parameter. */ + ADI_CRYPTO_ERR_INVALID_STATE, /*!< Operation failed since the device is in an invalid state. */ + ADI_CRYPTO_ERR_SEMAPHORE_FAILED, /*!< Failure in semaphore functions. */ + ADI_CRYPTO_ERR_INVALID_KEY_SIZE, /*!< bad key size fault detected. */ +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) + ADI_CRYPTO_PK_ALREADY_ENABLED, /*!< PKSTOR is already enabled. */ + ADI_CRYPTO_PK_ALREADY_DISABLED, /*!< PKSTOR is already disabled. */ + ADI_CRYPTO_PK_NOT_ENABLED, /*!< PKSTOR operation attempted while PKSTOR is disabled. */ + ADI_CRYPTO_PK_INVALID_KUWLEN, /*!< Invalid KUW length parameter. */ + ADI_CRYPTO_PK_INVALID_KEY_INDEX, /*!< PKSTOR key index overflow. */ + ADI_CRYPTO_PK_CMD_BUSY, /*!< command busy bit set after PKSTOR command done. */ + ADI_CRYPTO_PK_CMD_FAULT, /*!< command fault bit set during PKSTOR command. */ + ADI_CRYPTO_PK_CMD_ECC_FAULT, /*!< ECC errors detected during PKSTOR command. */ +#endif +} ADI_CRYPTO_RESULT; + +/*! + * \enum ADI_CRYPTO_EVENT + * Crypto callback events + */ +typedef enum +{ + /* successful buffer completion events */ + ADI_CRYPTO_EVENT_STATUS_CBC_DONE, /*!< CBC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CCM_DONE, /*!< CCM operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CMAC_DONE, /*!< CMAC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CTR_DONE, /*!< CTR operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_ECB_DONE, /*!< ECB operation is complete. */ +#if defined (__ADUCM4x50__) + ADI_CRYPTO_EVENT_STATUS_HMAC_DONE, /*!< HMAC operation is complete. */ +#else + ADI_CRYPTO_RESERVED_EVENT, /*!< reserved: preserves ordering */ +#endif /*__ADUCM4x50*/ + ADI_CRYPTO_EVENT_STATUS_SHA_DONE, /*!< SHA operation is complete. */ + + /* other events */ + ADI_CRYPTO_EVENT_DMA_BUS_ERROR, /*!< DMA bus error encountered. */ + ADI_CRYPTO_EVENT_DMA_DESCRIPTOR_ERROR, /*!< DMA descriptor error encountered. */ + ADI_CRYPTO_EVENT_DMA_UNKNOWN_ERROR, /*!< DMA unknown error encountered. */ + ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, /*!< Input overflow error encountered. */ + ADI_CRYPTO_EVENT_STATUS_UNKNOWN, /*!< Unknown error encountered. */ +} ADI_CRYPTO_EVENT; + +/*! The amount of application supplied memory used by the CRYPTO driver to store internal state. */ +#if defined (__ADUCM4x50__) +#define ADI_CRYPTO_MEMORY_SIZE (96u + ADI_SEM_SIZE) /*!< Required user memory size for ADuCM4x50 processor family. */ +#elif defined (__ADUCM302x__) +#define ADI_CRYPTO_MEMORY_SIZE (84u + ADI_SEM_SIZE) /*!< Required user memory size for ADuCM302x processor family. */ +#else +#error Crypto driver is not ported to this proccesor +#endif + +/*! A device handle used in all API functions to identify the flash device. */ +typedef struct __ADI_CRYPTO_DEV_DATA_TYPE* ADI_CRYPTO_HANDLE; + +/*! Number of bytes to allocate for SHA256 hash outputs */ +#define ADI_CRYPTO_SHA_HASH_BYTES (256u/8u) + +/*! Computation mode(Encryption/Decryption) for given buffers */ +typedef enum +{ + ADI_CRYPTO_DECODE = (0u << BITP_CRYPT_CFG_ENCR), /*!< Encoding mode is decryption. */ + ADI_CRYPTO_ENCODE = (1u << BITP_CRYPT_CFG_ENCR), /*!< Encoding mode is encryption. */ +} ADI_CRYPTO_CODING_MODE; + +/*! Enum for the AES KEY Length */ +typedef enum +{ + ADI_CRYPTO_AES_KEY_LEN_128_BIT = (0u << BITP_CRYPT_CFG_AESKEYLEN), /*!< KEY length is 128 bits. */ + ADI_CRYPTO_AES_KEY_LEN_256_BIT = (2u << BITP_CRYPT_CFG_AESKEYLEN), /*!< KEY length is 256 bits. */ +} ADI_CRYPTO_AES_KEY_LEN; + +#if defined (__ADUCM4x50__) +/*! Enable byte swapping for KEY writes */ +typedef enum +{ + ADI_CRYPTO_KEY_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_KEY_BYTESWAP), /*!< Do not apply KEY write byte swaps. */ + ADI_CRYPTO_KEY_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_KEY_BYTESWAP), /*!< Apply KEY write byte swaps. */ +} ADI_CRYPTO_KEY_BYTE_SWAP; +#endif /*__ADUCM4x50__*/ + +#if defined (__ADUCM4x50__) +/*! Byte-swap the SHA Input Data */ +typedef enum +{ + ADI_CRYPTO_SHA_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_SHA_BYTESWAP), /*!< Do not apply SHA data write byte swaps. */ + ADI_CRYPTO_SHA_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_SHA_BYTESWAP), /*!< Apply SHA data write byte swaps. */ +} ADI_CRYPTO_SHA_BYTE_SWAP; +#endif /*__ADUCM4x50__*/ + +/*! Byte-swap the AES Input Data */ +typedef enum +{ + ADI_CRYPTO_AES_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_AES_BYTESWAP), /*!< Do not apply AES data write byte swaps. */ + ADI_CRYPTO_AES_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_AES_BYTESWAP), /*!< Apply AES data write byte swaps. */ +} ADI_CRYPTO_AES_BYTE_SWAP; + +/*! + * \enum ADI_CRYPTO_CIPHER_MODE + * Enum for the cipher modes. + */ +typedef enum { + ADI_CRYPTO_MODE_CBC = BITM_CRYPT_CFG_CBCEN, /*!< Select CBC cipher mode. */ + ADI_CRYPTO_MODE_CCM = BITM_CRYPT_CFG_CCMEN, /*!< Select CCM cipher mode. */ + ADI_CRYPTO_MODE_CMAC = BITM_CRYPT_CFG_CMACEN, /*!< Select CMAC cipher mode. */ + ADI_CRYPTO_MODE_CTR = BITM_CRYPT_CFG_CTREN, /*!< Select CTR cipher mode. */ + ADI_CRYPTO_MODE_ECB = BITM_CRYPT_CFG_ECBEN, /*!< Select ECB cipher mode. */ +#if defined (__ADUCM4x50__) + ADI_CRYPTO_MODE_HMAC = BITM_CRYPT_CFG_HMACEN, /*!< Select HMAC cipher mode. */ +#endif /*__ADUCM4x50__*/ + ADI_CRYPTO_MODE_SHA = BITM_CRYPT_CFG_SHA256EN, /*!< Select SHA cipher mode. */ +} ADI_CRYPTO_CIPHER_MODE; + + +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) +/*! PKSTOR Key Wrap/Unwrap key lengths */ +typedef enum +{ + ADI_PK_KUW_LEN_128 = (1u << BITP_CRYPT_CFG_KUWKEYLEN), /*!< key wrap/unwrap size is 128-bit. */ + ADI_PK_KUW_LEN_256 = (2u << BITP_CRYPT_CFG_KUWKEYLEN), /*!< key wrap/unwrap size is 256-bit. */ + ADI_PK_KUW_LEN_512 = (3u << BITP_CRYPT_CFG_KUWKEYLEN), /*!< key wrap/unwrap size is 512-bit (compute-only; not store). */ +} ADI_CRYPTO_PK_KUW_LEN; +#endif /*ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT*/ + + +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) +/*! PKSTOR commands */ +typedef enum +{ + ADI_PK_CMD_WRAP_KUW = (0x1 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< KUW wrap command. */ + ADI_PK_CMD_UNWRAP_KUW = (0x2 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< KUW unwrap command. */ + ADI_PK_CMD_RESET_KUW = (0x3 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< clear all KUW registers command. */ + ADI_PK_CMD_USE_KEY = (0x4 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< load Key registers from KUW registers command. */ + ADI_PK_CMD_USE_DEV_KEY = (0x5 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< load Key registers with devide key command. */ + /* gap */ + ADI_PK_CMD_RETRIEVE_KEY = (0x8 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< load KUW registers command. */ + ADI_PK_CMD_STORE_KEY = (0x9 << BITP_CRYPT_PRKSTORCFG_CMD), /*!< program KUW registers into flash command. */ + ADI_PK_CMD_ERASE_KEY = (0xA << BITP_CRYPT_PRKSTORCFG_CMD), /*!< erase single key set from flash command. */ + ADI_PK_CMD_ERASE_PAGE = (0xB << BITP_CRYPT_PRKSTORCFG_CMD), /*!< erase entire key page command. */ +} ADI_CRYPTO_PK_CMD; +#endif /*ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT*/ + + +/*! superset user Crypto transaction structure (different elements used for different modes) */ +typedef struct +{ + ADI_CRYPTO_CIPHER_MODE eCipherMode; /*!< Cipher mode to use */ + ADI_CRYPTO_CODING_MODE eCodingMode; /*!< Coding Mode (Encryption or Decryption) */ +#if defined (__ADUCM4x50__) + ADI_CRYPTO_KEY_BYTE_SWAP eKeyByteSwap; /*!< KEY endianness */ + ADI_CRYPTO_SHA_BYTE_SWAP eShaByteSwap; /*!< SHA endianness */ +#endif /*__ADUCM4x50__*/ + ADI_CRYPTO_AES_BYTE_SWAP eAesByteSwap; /*!< AES endianness */ + + uint8_t *pKey; /*!< Pointer to the KEY data: pre-formatted as a byte array, according to eAesKeyLen. */ + ADI_CRYPTO_AES_KEY_LEN eAesKeyLen; /*!< The length of the AES KEY */ + + uint32_t *pAuthData; /*!< CCM mode: pointer to user prefix buffer */ + uint32_t numAuthBytes; /*!< Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */ + + uint32_t *pInputData; /*!< Pointer to user input data buffer */ + uint32_t numInputBytes; /*!< Length of the data buffer in bytes (should be a multiple of 16bytes) */ + + uint32_t *pOutputData; /*!< Pointer to user output buffer */ + uint32_t numOutputBytes; /*!< Length of the output buffer in bytes (should be a multiple of 16bytes) */ + + uint8_t *pNonceIV; /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:\n + - CTR mode = 108-bit NONCE\n + - CCM mode = 112-bit NONCE\n + - CBC mode = 128-bit IV (Initialization Vector)\n\n + NONCE and IV assume little endian format, for example: CTR NONCE packing is:\n + - NONCE[0] -> 7:0\n + - NONCE[1] -> 15:8\n + - ...\n + - NONCE[13] -> 103:96\n + - NONCE[14](Bits 3:0) -> 107:104\n + */ + uint32_t CounterInit; /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */ + uint32_t numValidBytes; /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */ + uint32_t numShaBits; /*!< SHA mode: Number of bits in the SHA payload, which may be odd-sized */ + +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) + /* PKSTOR extensions used only in context of overriding above key info with protected keys stored in flash. */ + /* Assumes previously wrapped keys have already been stored using adi_crypto_pk_Xxx APIs. */ + /* NOTE: Enabeling PKSTOR boolean results in explicit key loads being replaced with PKSTOR keys prior to all Crypto operations */ + /* When enabled, the PKSTOR sequence is to RETRIEVE, UNWRAP and USE whichever key index and size is designated below. */ + + bool bUsePKSTOR; /*!< Flag that controls use of PKSTOR key overrides. */ + ADI_CRYPTO_PK_KUW_LEN pkKuwLen; /*!< KUW key size */ + uint8_t pkIndex; /*!< Flash index within PKSTOR for storing/rettrieving keys. */ +#endif +} ADI_CRYPTO_TRANSACTION; + + +/*================ PUBLIC API ==================*/ + + +ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice); +ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice); +ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam); +ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); + +ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer); +ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer); +ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); +#endif + +#if (1 == ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT) +ADI_CRYPTO_RESULT adi_crypto_pk_EnablePKSTOR (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); + +ADI_CRYPTO_RESULT adi_crypto_pk_SetValString (ADI_CRYPTO_HANDLE const hDevice, uint8_t * const pValStr); +ADI_CRYPTO_RESULT adi_crypto_pk_GetValString (ADI_CRYPTO_HANDLE const hDevice, uint8_t * const pValStr); + +ADI_CRYPTO_RESULT adi_crypto_pk_SetKuwLen (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_PK_KUW_LEN const kuwDataLen); +ADI_CRYPTO_RESULT adi_crypto_pk_SetKuwReg (ADI_CRYPTO_HANDLE const hDevice, uint8_t * const pKuwData); +ADI_CRYPTO_RESULT adi_crypto_pk_WrapKuwReg (ADI_CRYPTO_HANDLE const hDevice); +ADI_CRYPTO_RESULT adi_crypto_pk_UnwrapKuwReg (ADI_CRYPTO_HANDLE const hDevice); +ADI_CRYPTO_RESULT adi_crypto_pk_ResetKuwReg (ADI_CRYPTO_HANDLE const hDevice); + +ADI_CRYPTO_RESULT adi_crypto_pk_UseDecryptedKey (ADI_CRYPTO_HANDLE const hDevice); +ADI_CRYPTO_RESULT adi_crypto_pk_LoadDeviceKey (ADI_CRYPTO_HANDLE const hDevice); + +ADI_CRYPTO_RESULT adi_crypto_pk_RetrieveKey (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index); +ADI_CRYPTO_RESULT adi_crypto_pk_StoreKey (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index); +ADI_CRYPTO_RESULT adi_crypto_pk_DestroyKey (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index); +ADI_CRYPTO_RESULT adi_crypto_pk_ErasePage (ADI_CRYPTO_HANDLE const hDevice, uint8_t const index); +#endif /* ADI_CRYPTO_ENABLE_PKSTOR_SUPPORT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/dma/adi_dma.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/dma/adi_dma.h new file mode 100755 index 00000000000..5b6adde5f86 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/dma/adi_dma.h @@ -0,0 +1,276 @@ +/*! + ***************************************************************************** + * @file: adi_dma.h + * @brief: DMA Device Definitions for ADuCxxx + *----------------------------------------------------------------------------- + * +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ADI_DMA_MODE_PING_PONG +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \addtogroup DMA_Driver DMA Driver + * @{ + * @brief DMA Driver + * @details This driver is intended to be used only by the device drivers and not by the application. + * @note The device drivers must include drivers/dma/adi_dma.h to use this driver + */ + +#ifndef ADI_DMA__H__ +#define ADI_DMA__H__ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*============= D E F I N E S =============*/ +/*! Amount of memory(In bytes) required by the DMA manager for managing the operation + * This memory is completely owned by the driver till the end of the operation. + */ + +/*============= D A T A T Y P E S =============*/ + + +/*! + * Dma Data Increments + */ +typedef enum +{ + ADI_DMA_INCR_1_BYTE = 0x00u, /*!< Byte increment */ + ADI_DMA_INCR_2_BYTE = 0x01u, /*!< Half word increment */ + ADI_DMA_INCR_4_BYTE = 0x02u, /*!< Word increment */ + ADI_DMA_INCR_NONE = 0x03u, /*!< No increment */ + + ADI_DMA_DECR_1_BYTE = 0x10u, /*!< Byte decrement */ + ADI_DMA_DECR_2_BYTE = 0x11u, /*!< Half word decrement */ + ADI_DMA_DECR_4_BYTE = 0x12u /*!< Word decrement */ + +} ADI_DMA_INCR_TYPE; + +/*! + * DMA Callback Events + */ +typedef enum +{ + ADI_DMA_EVENT_BUFFER_PROCESSED, /*!< Buffer processed event */ + ADI_DMA_EVENT_ERR_BUS, /*!< Bus Error Occurred Event */ + ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR /*!< Invalid Descriptor Event */ +} ADI_DMA_EVENT; + + +/*! + * Dma Data Widths + */ +typedef enum +{ + ADI_DMA_WIDTH_1_BYTE = 0x0, /*!< 8-bit */ + ADI_DMA_WIDTH_2_BYTE = 0x1, /*!< 16-bit */ + ADI_DMA_WIDTH_4_BYTE = 0x2 /*!< 32-bit */ +} ADI_DMA_WIDTH_TYPE; + + +/*! + * Dma Rearbitration Intervals (chunk size between bus arbitrations) + */ +typedef enum +{ + ADI_DMA_RPOWER_1 = 0, /*!< Rearbitrate after 1 transfer */ + ADI_DMA_RPOWER_2, /*!< Rearbitrate after 2 transfers */ + ADI_DMA_RPOWER_4, /*!< Rearbitrate after 4 transfers */ + ADI_DMA_RPOWER_8, /*!< Rearbitrate after 8 transfers */ + ADI_DMA_RPOWER_16, /*!< Rearbitrate after 16 transfers */ + ADI_DMA_RPOWER_32, /*!< Rearbitrate after 32 transfers */ + ADI_DMA_RPOWER_64, /*!< Rearbitrate after 64 transfers */ + ADI_DMA_RPOWER_128, /*!< Rearbitrate after 128 transfers */ + ADI_DMA_RPOWER_256, /*!< Rearbitrate after 256 transfers */ + ADI_DMA_RPOWER_512, /*!< Rearbitrate after 512 transfers */ + ADI_DMA_RPOWER_1024 /*!< Rearbitrate after 1024 transfers */ +} ADI_DMA_RPOWER; + + +/*! + * Dma Transfer Modes + */ +typedef enum +{ + ADI_DMA_MODE_BASIC, /*!< Basic mode */ + ADI_DMA_MODE_AUTO, /*!< Auto request mode */ + ADI_DMA_MODE_PING_PONG, /*!< Ping pong mode */ + ADI_DMA_MODE_MSG, /*!< Memory Scatter gather mode (not valid as no Memory DMA support) */ + ADI_DMA_MODE_PSG /*!< Peripheral Scatter mode */ +} ADI_DMA_MODE; + + +/*! + * Dma Channel Priority Settings (only HIGH or DEFAULT priority supported) + */ +typedef enum +{ + ADI_DMA_PRIORITY_DEFAULT = 0, /*!< Use DEFAULT channel priority */ + ADI_DMA_PRIORITY_HIGH /*!< Elevate channel to HIGH priority */ +} ADI_DMA_PRIORITY; + + +/*! + * Result Event Type + */ +typedef enum { + ADI_DMA_SUCCESS, /*!< Successfully Completed */ + ADI_DMA_ERR_NOT_INITIALIZED, /*!< DMA not initialized */ + ADI_DMA_ERR_INVALID_PARAMETER, /*!< Input parameter to the function is invalid */ +} ADI_DMA_RESULT; + +/*! \cond PRIVATE*/ +/*! + * \enum DMA_CHANn_TypeDef + * DMA Channel Assignments + */ +typedef enum +{ + SPI2_TX_CHANn = 0, /*!< SPI2 Transmit DMA channel */ + SPI2_RX_CHANn = 1, /*!< SPI2 Receive DMA channel */ + SPORT0A_CHANn = 2, /*!< SPORT0-A DMA channel */ + SPORT0B_CHANn = 3, /*!< SPORT0-B DMA channel */ + SPI0_TX_CHANn = 4, /*!< SPI0 Transmit DMA channel */ + SPI0_RX_CHANn = 5, /*!< SPI0 Receive DMA channel */ + SPI1_TX_CHANn = 6, /*!< SPI1 Transmit DMA channel */ + SPI1_RX_CHANn = 7, /*!< SPI1 Receive DMA channel */ + UART0_TX_CHANn = 8, /*!< UART0 Transmit DMA channel */ + UART0_RX_CHANn = 9, /*!< UART0 Receive DMA channel */ + I2CS_TX_CHANn = 10, /*!< I2C Slave Transmit DMA channel */ + I2CS_RX_CHANn = 11, /*!< I2C Slave Receive DMA channel */ + I2CM_CHANn = 12, /*!< I2C Master DMA channel */ + AES0_IN_CHANn = 13, /*!< AES0-IN DMA channel */ + AES0_OUT_CHANn = 14, /*!< AES0-OUT DMA channel */ + FLASH_CHANn = 15, /*!< FLASH DMA channel */ + SIP0_CHANn = 16, /*!< SIP-0 DMA channel */ + SIP1_CHANn = 17, /*!< SIP-1 DMA channel */ + SIP2_CHANn = 18, /*!< SIP-2 DMA channel */ + SIP3_CHANn = 19, /*!< SIP-3 DMA channel */ + SIP4_CHANn = 20, /*!< SIP-4 DMA channel */ + SIP5_CHANn = 21, /*!< SIP-5 DMA channel */ + SIP6_CHANn = 22, /*!< SIP-6 DMA channel */ + SIP7_CHANn = 23, /*!< SIP-7 DMA channel */ + ADC0_CHANn = 24, /*!< ADC0 DMA channel */ +#if defined(__ADUCM4x50__) + UART1_TX_CHANn = 25, /*!< UART1 Transmit DMA channel */ + UART1_RX_CHANn = 26, /*!< UART1 Receive DMA channel */ +#endif /* __ADUCM4x50__ */ + NUM_DMA_CHANNELSn = 27 /*!< Total Number of DMA channels */ +} DMA_CHANn_TypeDef; /** typedef name for fixed DMA channel assignments */ +/*! \endcond */ + +/*! + * \struct ADI_DCC_TypeDef + * DMA Channel Control MMR Access Template + */ +typedef struct +{ + __IO uint32_t DMASRCEND; /*!< Source End Pointer */ + __IO uint32_t DMADSTEND; /*!< Destination End Pointer */ + __IO uint32_t DMACDC; /*!< Channel Data Configuration */ + uint32_t RESERVED; /*!< Address gap filler */ +} ADI_DCC_TypeDef; + + +/*! \cond PRIVATE */ +/* Bit Position for DMA Descriptor Control */ +#define DMA_BITP_CTL_DST_INC (30u) +#define DMA_BITP_CTL_SRC_INC (26u) +#define DMA_BITP_CTL_SRC_SIZE (24u) +#define DMA_BITP_CTL_R_POWER (14u) +#define DMA_BITP_CTL_N_MINUS_1 (4u) +#define DMA_BITP_CTL_CYCLE_CTL (0u) + +/* Bit Mask for DMA Descriptor Control */ +#define DMA_BITM_CTL_DST_INC ((0x00000003u) << DMA_BITP_CTL_DST_INC) +#define DMA_BITM_CTL_SRC_INC ((0x00000003u) << DMA_BITP_CTL_SRC_INC) +#define DMA_BITM_CTL_SRC_SIZE ((0x00000003u) << DMA_BITP_CTL_SRC_SIZE) +#define DMA_BITM_CTL_R_POWER ((0x0000000Fu) << DMA_BITP_CTL_R_POWER) +#define DMA_BITM_CTL_N_MINUS_1 ((0x000003FFu) << DMA_BITP_CTL_N_MINUS_1) +#define DMA_BITM_CTL_CYCLE_CTL ((0x00000007u) << DMA_BITP_CTL_CYCLE_CTL) + +/* Enum for the DMA Descriptor Cycle Control */ +#define DMA_ENUM_CTL_CYCLE_CTL_INVALID (0u) +#define DMA_ENUM_CTL_CYCLE_CTL_BASIC (1u) +#define DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ (2u) +#define DMA_ENUM_CTL_CYCLE_CTL_PING_PONG (3u) +#define DMA_ENUM_CTL_CYCLE_CTL_MSG_PRI (4u) +#define DMA_ENUM_CTL_CYCLE_CTL_MSG_ALT (5u) +#define DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI (6u) +#define DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT (7u) + + +#define DMA_BITM_INCR_TYPE_DECR (0x10u) + +#define DMA_BITM_OCTL_SRC_DECR (0x01u) +#define DMA_BITM_OCTL_DST_DECR (0x02u) + +#define DMA_BITM_OCTL_SRC_INCR (0x04u) +#define DMA_BITM_OCTL_DST_INCR (0x08u) + +#define DMA_TRANSFER_LIMIT (1024u) /*!< Maximum number of transfers handled by the DMA in one request */ + +/* pointer to the primary CCD array */ +extern ADI_DCC_TypeDef* const pPrimaryCCD; +/* pointer to the alternate CCD array */ +extern ADI_DCC_TypeDef* const pAlternateCCD; +/*! \endcond */ +/*========== DMA API DECLARATIONS ==========*/ + +extern void adi_dma_Init(void); + +extern ADI_DMA_RESULT adi_dma_RegisterCallback ( + DMA_CHANn_TypeDef const eChannelID, + ADI_CALLBACK const pfCallback, + void* const pCBParam + ); + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/**@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/flash/adi_flash.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/flash/adi_flash.h new file mode 100755 index 00000000000..c72524e3e4d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/flash/adi_flash.h @@ -0,0 +1,185 @@ +/*! + ***************************************************************************** + @file: adi_flash.h + @brief: Flash device driver definitions + @date: $Date: 2016-07-05 00:49:46 -0400 (Tue, 05 Jul 2016) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! @addtogroup Flash_Driver Flash Driver + * @{ + */ + +#ifndef ADI_FLASH_H +#define ADI_FLASH_H + + /*! \cond PRIVATE */ +#include +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_FEE_RESULT + * Flash Controller return codes. + */ + typedef enum { + ADI_FEE_SUCCESS = 0, /*!< The function completed successfully. */ + ADI_FEE_ERR_ALIGNMENT, /*!< The flash write source data pointer is misaligned. */ + ADI_FEE_ERR_ALREADY_INITIALIZED, /*!< The flash device driver is already initialized. */ + ADI_FEE_ERR_BAD_DEVICE_NUM, /*!< Device number passed is invalid. */ + ADI_FEE_ERR_BUFFER_ERR, /*!< An error occurred while processing a write buffer. */ + ADI_FEE_ERR_DEVICE_BUSY, /*!< The device is busy. */ + ADI_FEE_ERR_DMA_BUS_FAULT, /*!< Runtime DMA bus fault detected. */ + ADI_FEE_ERR_DMA_INVALID_DESCR, /*!< Runtime DMA invalid descriptor detected. */ + ADI_FEE_ERR_DMA_REGISTER, /*!< Error registering DMA error callback function. */ + ADI_FEE_ERR_DMA_UNKNOWN_ERROR, /*!< Unknown runtime DMA error detected. */ + ADI_FEE_ERR_HW_ERROR_DETECTED, /*!< An FEE hardware error occurred (pHwErrors param). */ + ADI_FEE_ERR_INSUFFICIENT_MEM, /*!< The memory passed is undersized. */ + ADI_FEE_ERR_INVALID_HANDLE, /*!< Device Handle is invalid. */ + ADI_FEE_ERR_INVALID_PARAM, /*!< A function parameter is invalid. */ + ADI_FEE_ERR_NO_DATA_TO_TRANSFER, /*!< No transfer data detected. */ + ADI_FEE_ERR_TRANSFER_IN_PROGRESS, /*!< Operation already in progress. */ + ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY, /*!< Unmatched read/write vs. submit/get API call. */ + ADI_FEE_ERR_SEMAPHORE_FAILED, /*!< An semaphore operation failed. */ + } ADI_FEE_RESULT; + + +/*! A device handle used in all API functions to identify the flash device. */ +typedef struct __ADI_FEE_DEV_DATA_TYPE* ADI_FEE_HANDLE; + + +/*! Applications use the "ADI_FEE_MEMORY_SIZE" macro to allocate + required flash driver memory. This memory (and size) are passed + to the flash driver during the "adi_fee_Open()" driver initialization + call. This memory is used to store internal flash driver state. +*/ +#define ADI_FEE_MEMORY_SIZE (44u + ADI_SEM_SIZE) + + +/*! + * \enum ADI_FEE_CALLBACK_EVENT + * Enum for the callback events. + */ +typedef enum { + ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, /*!< Buffer processed successfully event. */ + ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, /*!< Device error(s) detected during command. */ +} ADI_FEE_CALLBACK_EVENT; + +/*! + * \enum ADI_FEE_ECC_EVENT_TYPE + * Enum for the Error-Correction-Code event type. + */ +typedef enum { + ADI_FEE_ECC_EVENT_TYPE_ERROR, /*!< ECC Error Event. */ + ADI_FEE_ECC_EVENT_TYPE_CORRECT /*!< ECC correction event. */ +} ADI_FEE_ECC_EVENT_TYPE; + +/*! + * \enum ADI_FEE_ECC_RESPONSE + * Error-Correction-Code configuration codes. + */ +typedef enum { + ADI_FEE_ECC_RESPONSE_NONE = 0x0, /*!< No Response. */ + ADI_FEE_ECC_RESPONSE_BUS_ERROR = 0x1, /*!< Generate a Bus Error. */ + ADI_FEE_ECC_RESPONSE_IRQ = 0x2 /*!< Generate an IRQ. */ +} ADI_FEE_ECC_RESPONSE; + + +/*! + * \struct ADI_FEE_TRANSACTION + * Flash write data transaction block. + */ +typedef struct { + uint32_t *pWriteAddr; /*!< Pointer to flash-space (destination) write location. */ + uint32_t *pWriteData; /*!< Pointer to user-space (source) write Data. */ + uint32_t nSize; /*!< Write data size (in bytes). */ + bool bUseDma; /*!< DMA flag controlling use of DMA or not. */ +} ADI_FEE_TRANSACTION; + + +/*================ E X T E R N A L S ==================*/ +/* Flash Controller API */ + +ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice); +ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice); +ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam); + +ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors); + +ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction); + +ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState); +ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors); + +ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum); +ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum); + +ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum); + +ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep); +ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice); +ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress); + +ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable); +ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable); +ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse); +ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress); +ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections); + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_data_transfer.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_data_transfer.h new file mode 100755 index 00000000000..89ab88d841e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_data_transfer.h @@ -0,0 +1,127 @@ +/*! **************************************************************************** + * @file adi_data_transfer.h + * @brief General data transfer types for drivers + * @details General data transfer types for drivers + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_DATA_TRANSFER_H +#define ADI_DATA_TRANSFER_H + +/*============= I N C L U D E S =============*/ + +#include /* defines types such as uint32_t*/ +#include /* needed for SEM_VAR_DECLR declaration */ + +/*! \cond PRIVATE */ +/** @addtogroup Data_Transfer Common Data Transfer Structures +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*============== D E F I N E S ===============*/ + +#define ADI_DT_BUFNUM (2u) /*!< Number of buffers available for data transfers in each communication channel */ + +/*! + ******************************************************************************* + * \struct ADI_DT_BUFF_INFO + * Structure for managing buffers submitted to drivers. + ******************************************************************************/ +struct _ADI_DT_BUFF_INFO; + +/*! + ******************************************************************************* + * Structure for managing buffers submitted to drivers. + ******************************************************************************/ +typedef struct _ADI_DT_BUFF_INFO +{ + void * pStartAddress; /*!< Address of buffer passed down a driver. */ + uint32_t nCount; /*!< Size of buffer in bytes. */ + uint32_t nIndex; /*!< Position of first byte to be transmitted. */ + bool bInUse; /*!< Buffer in use flag. */ + bool bDMA; /*!< Transaction is using the DMA flag. */ + struct _ADI_DT_BUFF_INFO * pNextBuffer; /*!< Pointer to the next buffer in the list. */ +} ADI_DT_BUFF_INFO; + +/*! + ******************************************************************************* + * Enumeration of different data transfer modes supported by drivers. + ******************************************************************************/ +typedef enum _ADI_DT_MODE +{ + ADI_DT_MODE_NONE, /*!< Mode of data transfer is not selected. */ + ADI_DT_MODE_BLOCKING, /*!< Only calls to adi_xxx_Read or adi_xxx_Write are allowed for transferring data. */ + ADI_DT_MODE_NONBLOCKING /*!< Only calls to adi_xxx_SubmitBuffer are allowed for transferring data. */ +} ADI_DT_MODE; + +typedef void * ADI_DEVICE_HANDLE; /*!< Generic device handle */ + +/*! + ******************************************************************************* + * Structure for managing pool of buffers submitted to drivers. + ******************************************************************************/ +typedef struct +{ + ADI_DT_BUFF_INFO BufInfo[ADI_DT_BUFNUM]; /*!< Ping Pong Buffers. */ + ADI_DT_BUFF_INFO * pFreeBuffer; /*!< Pointer to free buffer. (Next buffer to submit). */ + ADI_DT_BUFF_INFO * pFillBuffer; /*!< Pointer to the next buffer to be filled. (Needed for the case + where many buffers are "submitted" before a "get" is called.) */ + ADI_DT_BUFF_INFO * pActiveBuffer; /*!< Pointer to active buffer. (Next buffer waiting for completion.)*/ + ADI_DT_MODE eDataTranferMode; /*!< Data transfer mode (blocking or non-blockig). */ + + SEM_VAR_DECLR +} ADI_DT_CHANNEL; + + +/*============= P U B L I C F U N C T I O N S =============*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*! \endcond */ + +#endif /* ADI_DATA_TRANSFER_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h new file mode 100755 index 00000000000..0540cea56ed --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/general/adi_drivers_general.h @@ -0,0 +1,98 @@ +/*! + ***************************************************************************** + * @file: adi_drivers_general.h + * @brief: Macros and types used in multiple drivers + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#ifndef ADI_DRIVERS_GENERAL__H +#define ADI_DRIVERS_GENERAL__H + + +/* Macros related to alignment in the different toolchains supported */ + +/* + * These macros are designed to be used as follows: + * ADI_ALIGNED_PRAGMA() + * ADI_ALIGNED_ATTRIBUTE() + */ + +#if defined ( __ICCARM__ ) +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm120 (rule 19.10): In the definition of a function-like macro each parameter +* shall be enclosed in parenthesis. +* This is not possible in attributes and pragmas +* Pm154 (rule 19.13): The # and ## preprocessor operators shall not be used. +* We need to do this to abstract the macros for the +* different toolchains +*/ +#pragma diag_suppress=Pm120,Pm154 +#endif + +#define PRAGMA(x) _Pragma(#x) +#define ATTRIBUTE(x) __attribute__((x)) + +#if defined (__GNUC__) + /* Gcc uses attributes */ + #define ADI_ALIGNED_PRAGMA(num) + #define ADI_ALIGNED_ATTRIBUTE(num) ATTRIBUTE(aligned(num)) + #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) +#elif defined ( __ICCARM__ ) + /* IAR uses a pragma */ + #define ADI_ALIGNED_ATTRIBUTE(num) + #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) + #define ADI_UNUSED_ATTRIBUTE +#elif defined (__CC_ARM) + /* Keil uses a decorator which is placed in the same position as pragmas */ + #define ADI_ALIGNED_ATTRIBUTE(num) + #define ADI_ALIGNED_PRAGMA(num) __align(##num) + #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) +#else +#error "Toolchain not supported" +#endif + + +#if defined ( __ICCARM__ ) +#pragma diag_default=Pm120,Pm154 +#endif +#endif /* ADI_DRIVERS_GENERAL__H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/gpio/adi_gpio.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/gpio/adi_gpio.h new file mode 100755 index 00000000000..8a6042f88e0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/gpio/adi_gpio.h @@ -0,0 +1,178 @@ +/* + ***************************************************************************** + @file: adi_gpio.h + @brief: GPIO definitions and API + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_GPIO_H +#define ADI_GPIO_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Allow code example in doxygen comment. + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm008,Pm011 +#endif /* __ICCARM__ */ + +/*! \addtogroup GPIO_Driver GPIO Driver + * @{ + */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm008 +#endif /* __ICCARM__ */ + +/* C++ linkage */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! Amount of memory(in bytes) required by the GPIO device driver for its operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_GPIO_MEMORY_SIZE (16u) + +/* typedefs for 16-bit Ports */ +typedef uint16_t ADI_GPIO_DATA; /*!< pin data reg type */ + + +/*! GPIO API function return codes */ +typedef enum +{ + ADI_GPIO_SUCCESS = 0, /*!< No error detected. */ + ADI_GPIO_FAILURE, /*!< The API call failed. */ + ADI_GPIO_ALREADY_INITIALIZED, /*!< GPIO device has already been initialized. */ + ADI_GPIO_NOT_INITIALIZED, /*!< GPIO device has not yet been initialized. */ + ADI_GPIO_NULL_PARAMETER, /*!< The given pointer is pointing to NULL. */ + ADI_GPIO_INVALID_MEMORY_SIZE, /*!< The given memory is not sufficient to operate the driver. */ + ADI_GPIO_INVALID_PINS, /*!< Invalid pin combination. */ + ADI_GPIO_INVALID_INTERRUPT, /*!< Invalid interrupt number. */ + ADI_GPIO_INVALID_TRIGGER, /*!< Invalid trigger condition. */ +} ADI_GPIO_RESULT; + + +/*! GPIO trigger condition enumerations */ +typedef enum { + ADI_GPIO_IRQ_RISING_EDGE =(0x0), /*!< Trigger an interrupt on a rising edge. */ + ADI_GPIO_IRQ_FALLING_EDGE =(0x1), /*!< Trigger an interrupt on a falling edge. */ + ADI_GPIO_IRQ_EITHER_EDGE =(0x2), /*!< Trigger an interrupt on either edge. */ + ADI_GPIO_IRQ_HIGH_LEVEL =(0x3), /*!< Trigger an interrupt on a high level. */ + ADI_GPIO_IRQ_LOW_LEVEL =(0x4) /*!< Trigger an interrupt on a low level. */ +} ADI_GPIO_IRQ_TRIGGER_CONDITION; + +/*! GPIO IRQ enumeration */ +typedef enum { + ADI_GPIO_INTA_IRQ = SYS_GPIO_INTA_IRQn, /*!< GPIO Group Interrupt A. */ + ADI_GPIO_INTB_IRQ = SYS_GPIO_INTB_IRQn, /*!< GPIO Group Interrupt B. */ +} ADI_GPIO_IRQ; + + +/*! GPIO port enumerations */ +typedef enum { + ADI_GPIO_PORT0, /*!< Port 0 */ + ADI_GPIO_PORT1, /*!< Port 1 */ + ADI_GPIO_PORT2, /*!< Port 2 */ +#if defined(__ADUCM4x50__) + ADI_GPIO_PORT3, /*!< Port 3 */ +#endif /* __ADUCM4x50__ */ + ADI_GPIO_NUM_PORTS /*!< maximum number of ports */ +} ADI_GPIO_PORT; + +/* 16-bit port pin defs */ +#define ADI_GPIO_PIN_0 ((ADI_GPIO_DATA)(0x0001)) /*!< Pin 0 */ +#define ADI_GPIO_PIN_1 ((ADI_GPIO_DATA)(0x0002)) /*!< Pin 1 */ +#define ADI_GPIO_PIN_2 ((ADI_GPIO_DATA)(0x0004)) /*!< Pin 2 */ +#define ADI_GPIO_PIN_3 ((ADI_GPIO_DATA)(0x0008)) /*!< Pin 3 */ +#define ADI_GPIO_PIN_4 ((ADI_GPIO_DATA)(0x0010)) /*!< Pin 4 */ +#define ADI_GPIO_PIN_5 ((ADI_GPIO_DATA)(0x0020)) /*!< Pin 5 */ +#define ADI_GPIO_PIN_6 ((ADI_GPIO_DATA)(0x0040)) /*!< Pin 6 */ +#define ADI_GPIO_PIN_7 ((ADI_GPIO_DATA)(0x0080)) /*!< Pin 7 */ +#define ADI_GPIO_PIN_8 ((ADI_GPIO_DATA)(0x0100)) /*!< Pin 8 */ +#define ADI_GPIO_PIN_9 ((ADI_GPIO_DATA)(0x0200)) /*!< Pin 9 */ +#define ADI_GPIO_PIN_10 ((ADI_GPIO_DATA)(0x0400)) /*!< Pin 10 */ +#define ADI_GPIO_PIN_11 ((ADI_GPIO_DATA)(0x0800)) /*!< Pin 11 */ +#define ADI_GPIO_PIN_12 ((ADI_GPIO_DATA)(0x1000)) /*!< Pin 12 */ +#define ADI_GPIO_PIN_13 ((ADI_GPIO_DATA)(0x2000)) /*!< Pin 13 */ +#define ADI_GPIO_PIN_14 ((ADI_GPIO_DATA)(0x4000)) /*!< Pin 14 */ +#define ADI_GPIO_PIN_15 ((ADI_GPIO_DATA)(0x8000)) /*!< Pin 15 */ + +/* GPIO port pins availability mask */ +#define ADI_GPIO_PORT0_PIN_AVL (0xFFFFu) /*!< Port 0 pin mask (16 pins)*/ +#define ADI_GPIO_PORT1_PIN_AVL (0xFFFFu) /*!< Port 1 pin mask (16 pins)*/ +#define ADI_GPIO_PORT2_PIN_AVL (0xFFFFu) /*!< Port 2 pin mask (16 pins)*/ + +#if defined(__ADUCM4x50__) +#define ADI_GPIO_PORT3_PIN_AVL (0x000Fu) /*!< Port 2 pin mask (4 pins) */ +#endif /* __ADUCM4x50__ */ + +/* GPIO API functions */ +ADI_GPIO_RESULT adi_gpio_Init (void* const pMemory, uint32_t const MemorySize); +ADI_GPIO_RESULT adi_gpio_UnInit (void); +ADI_GPIO_RESULT adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam ); +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins (const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_OutputEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_InputEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_PullUpEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_SetHigh (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetLow (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_Toggle (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue); + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_GPIO_V1_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/i2c/adi_i2c.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/i2c/adi_i2c.h new file mode 100755 index 00000000000..edd398f3f9b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/i2c/adi_i2c.h @@ -0,0 +1,243 @@ +/*! + ***************************************************************************** + @file: adi_i2c.h + @brief: I2C device driver definitions + @details This is the primary header file for the I2C driver, which contains the + API declarations, data and constant definitions used in the APIs. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_I2C_H +#define ADI_I2C_H + + /*! \cond PRIVATE */ +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ + + +/** @addtogroup I2C_Driver I2C Driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +*/ +#pragma diag_suppress=Pm011 + +#endif + +/*! + ***************************************************************************** + * \enum ADI_I2C_RESULT + * + * I2C Device Error Codes. #ADI_I2C_SUCCESS is always zero + * The return value of all I2C APIs returning #ADI_I2C_RESULT + * should always be tested at the application level for success or failure. + * Specific I2C bus error conditions are returned as elements of + * #ADI_I2C_RESULT. + * + *****************************************************************************/ +typedef enum +{ + ADI_I2C_SUCCESS = 0, /*!< The API call succeeded. */ + ADI_I2C_BAD_BITRATE, /*!< The bit rate is invalid. */ + ADI_I2C_BAD_DEVICE_HANDLE, /*!< The device handle is invalid. */ + ADI_I2C_BAD_DEVICE_NUMBER, /*!< The device number is invalid. */ + ADI_I2C_BAD_SYS_CLOCK, /*!< Unable to obtain system clock rate. */ + ADI_I2C_DEVICE_IN_USE, /*!< The device is in use. */ + ADI_I2C_DEVICE_NOT_OPEN, /*!< The device is not open. */ + ADI_I2C_FAILURE, /*!< Generic API failure code. */ + ADI_I2C_HW_ERROR_DETECTED, /*!< An I2C hardware error occurred. See #ADI_I2C_HW_ERRORS. */ + ADI_I2C_INSUFFICIENT_MEMORY, /*!< The application supplied memory size is insufficient. */ + ADI_I2C_INVALID_PARAMETER, /*!< An invalid parameter is passed to the function. */ + ADI_I2C_INVALID_SLAVE_ADDRESS, /*!< The application supplied slave address is too wide. */ + ADI_I2C_INVALID_SUBMIT_API, /*!< Unmatched read/write vs. submit/get API call. */ + ADI_I2C_SEMAPHORE_FAILED /*!< Semaphore operation failed. */ + +} ADI_I2C_RESULT; + + +/*! + ***************************************************************************** + * \enum ADI_I2C_HW_ERRORS + * + * I2C Device Hardware Error Codes. Contains one or more hardware (I2C protocol) + * errors. Use this enum to decode hardware errors when the main #ADI_I2C_RESULT + * return result value is #ADI_I2C_HW_ERROR_DETECTED. + * + *****************************************************************************/ +typedef enum +{ + ADI_I2C_HW_ERROR_NONE = 0, /*!< No hardware error. */ + ADI_I2C_HW_ERROR_NACK_ADDR = 0x0001, /*!< A no-acknowledgement occurred for the address. */ + ADI_I2C_HW_ERROR_NACK_DATA = 0x0002, /*!< A no-acknowledgement occurred for the data. */ + ADI_I2C_HW_ERROR_ARBITRATION_LOST = 0x0004, /*!< I2C bus arbitration was Lost. */ + ADI_I2C_HW_ERROR_UNEXPECTED_ERROR = 0x0008, /*!< An unexpected error occurred. */ + +} ADI_I2C_HW_ERRORS; + + +/*! A device handle used in all API functions to identify the I2C device. */ +typedef struct __ADI_I2C_DEV_DATA_TYPE* ADI_I2C_HANDLE; + +/*! Use macro "ADI_I2C_MEMORY_SIZE" to know how much memory to + provide the i2c driver during the "adi_i2c_Open()" driver + initialization call. This memory is used to store internal + driver state data. Use map file to verify. +*/ +#define ADI_I2C_MEMORY_SIZE (44u + ADI_SEM_SIZE) + + +/*! + * \struct ADI_I2C_TRANSACTION + ***************************************************************************** + * I2C Device Command/Data Transaction Structure. This is the called-provided + * data structure used by the blocking #adi_i2c_ReadWrite() and non-blocking + * #adi_i2c_SubmitBuffer() calls to describe the caller's transaction parameters, + * consisting of prologue data and size (the addressing phase), transmit/receive + * data pointer and size (the data phase), and various transaction control parameters. + * + * Each transaction may optionally be prefaced with a prologue block, which may + * describe a read/write memory/register address, a slave-specific command, or + * some other slave-specific protocol that may precede the actual read/write + * data. Set the prologue size to zero if no prologue is desired. + * + * Each call to #adi_i2c_ReadWrite or #adi_i2c_SubmitBuffer() must populate the + * following fields of the ADI_I2C_TRANSACTION block: + * + * @par pPrologue + * Byte pointer to an application-supplied prologue byte array. If the value is + * zero, prologue data is ignored. + * + * @par nPrologueSize + * The number of prologue bytes to be transmitted ahead of the data phase. If the + * value is zero, prologue data is ignored. + * + * @par pData + * Byte pointer to the application-supplied data byte array. This buffer is + * either the source or destination address of the data being transmitted or + * received, respectively. + * + * @par nDataSize + * The number of data bytes to be transmitted or received during the data phase. + * If the value is zero, the data phase is ignored. + * + * @par bReadNotWrite + * Direction control for data phase. If "true", data phase is a read (from + * the slave), if "false", data phase is a write (to the slave). Pertains only + * to the data phase. Any prologue data (addressing/command phase) is always + * transmitted (written to the slave) prior to the data phase. + * + * @par bRepeatStart + * Controls suppression of a Stop Condition between the addressing phase and the + * data phase of an I2C transaction. After the prologue (if present), a + * unidirectional data stream (I2C is a half-duplex protocol) is either + * transmitted or received (depending on the transfer direction). Frequently, a + * Repeat-Start Condition (in reality, just the absence of a Stop Condition + * following the prologue/addressing phase) is required between the addressing + * phase (prologue) and the data phase of a transaction to meet slave device + * protocol requirements. The Repeat-Start requirement can be driven by the + * slave device communications protocol, or simply to just prevent any other + * I2C master from rearbitrating the bus between the prologue (addressing) and + * data phases of a so-called "COMBINED FORMAT" (write-followed-by-read). + * When bRepeatStart is set "true", the usual Stop Condition between the addressing + * phase and the data phase is suppressed and the I2C bus controller issues a + * second Start Condition (Repeat-Start) for the data phase. Without + * Repeat-Start (bRepeatStart "false"), the addressing phase ends with a normal + * Stop Condition ahead of the data phase. Repeat-Start conditions are used + * when "turning the bus around" as in writing a read address (for example), + * immediately followed by a data stream from that read address... without + * releasing bus arbitration. + * + *****************************************************************************/ +typedef struct { + uint8_t *pPrologue; /*!< Prologue pointer. */ + uint16_t nPrologueSize; /*!< Prologue byte count. */ + uint8_t *pData; /*!< Data pointer. */ + uint16_t nDataSize; /*!< Data byte count. */ + bool bReadNotWrite; /*!< Read/write flag. */ + bool bRepeatStart; /*!< Repeat start flag. */ +} ADI_I2C_TRANSACTION; + + +/*! Maximum supported bitrate is "FAST" mode (400 kHz). */ +#define ADI_I2C_MAX_RATE (400000u) + +/*************************************************************** + * Eliminable user API that may be optimized out by the linker * + ***************************************************************/ +ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice); +ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice); + +/* blocking calls... */ +ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors); + +/* non-blocking calls... */ +ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction); +ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState); +ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors); + +/* other (blocking) calls... */ +ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice); +ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32); +ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress); +ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors); + + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_I2C_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/pwr/adi_pwr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/pwr/adi_pwr.h new file mode 100755 index 00000000000..3175b7000cd --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/pwr/adi_pwr.h @@ -0,0 +1,723 @@ +/* + ***************************************************************************** + * @file: adi_pwr.h + * @brief: System clock and power management driver. + *----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +/*! \addtogroup Power_Driver Power Driver + * @{ + */ + +#ifndef ADI_PWR_H +#define ADI_PWR_H + +#include +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * IAR compiler supports longer identifiers. + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm009,Pm011 +#endif /* __ICCARM__ */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*! Enumeration of clock sources for various peripherals. */ +typedef enum { + /*! Source for all peripherals SPI, SPORT, SIP, CRC, AES, SIP interface, I2C, UART, optionally for timers. */ + ADI_CLOCK_PCLK, + /*! Source for Core,Bus etc. */ + ADI_CLOCK_HCLK, + /*! Source for the ADC. */ + ADI_CLOCK_ACLK + +} ADI_CLOCK_ID; + +/*! Enumeration of input clock sources */ +typedef enum { + /*! Clock ID for 16 MHz or 26 MHz external crystal oscillator called HFXTAL. */ + ADI_CLOCK_SOURCE_HFXTAL, + /*! Clock ID 32 kHz external crystal oscillator called LFXTAL. */ + ADI_CLOCK_SOURCE_LFXTAL, + /*! Clock ID for 26 MHz internal oscillator called HFOSC. */ + ADI_CLOCK_SOURCE_HFOSC, + /*! Clock ID 32 kHz a 32 kHz internal oscillator called LFXTAL. */ + ADI_CLOCK_SOURCE_LFOSC, + /*! Clock ID for output clock for System PLL. */ + ADI_CLOCK_SOURCE_SPLL, + /*! Clock ID for external clock from GPIO. */ + ADI_CLOCK_SOURCE_GPIO +} ADI_CLOCK_SOURCE_ID; + + +/*! + * Enumeration of clock sources for each clock multiplexer. + * The processor has the following clock multiplexers. + * - SPLL Mux (System PLL). + * - Reference clock Mux. + * - Root Clock Mux. + */ +typedef enum { + + /*! Input clock for system PLL mux is HFOSC. */ + ADI_CLOCK_MUX_SPLL_HFOSC, + /*! Input clock for system PLL mux is HFXTAL. */ + ADI_CLOCK_MUX_SPLL_HFXTAL, + +#if defined(__ADUCM4x50__) + /*! Input clock for system PLL mux is provided through GPIO. */ + ADI_CLOCK_MUX_SPLL_GPIO, +#endif + + /*! Input clock for low frequency clock mux is LFOSC. */ + ADI_CLOCK_MUX_LFCLK_LFOSC, + /*! Input clock for low frequency clock mux is LFXTAL. */ + ADI_CLOCK_MUX_LFCLK_LFXTAL, + + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is HFOSC. */ + ADI_CLOCK_MUX_REF_HFOSC_CLK, + /*! Reserved. */ + ADI_CLOCK_MUX_REF_RESERVED, + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is 26 MHz HFXTAL. */ + ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK, + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is 16 MHz HFXTAL. */ + ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK, + + /*! Input clock to root multiplexer is HFOSC. */ + ADI_CLOCK_MUX_ROOT_HFOSC, + /*! Input clock to root multiplexer is HFXTAL. */ + ADI_CLOCK_MUX_ROOT_HFXTAL, + /*! Input clock to root multiplexer is SPLL. */ + ADI_CLOCK_MUX_ROOT_SPLL, + /*! Input clock to root multiplexer is from GPIO. */ + ADI_CLOCK_MUX_ROOT_GPIO + +} ADI_CLOCK_MUX_ID; + + +/*! + * Enumeration of clock source status. + */ +typedef enum { + /*! Specified clock source is disabled. */ + ADI_CLOCK_SOURCE_DISABLED = 0, + /*! Specified clock source is not stable. */ + ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE, + /*! Specified clock source is enabled and stable. */ + ADI_CLOCK_SOURCE_ENABLED_STABLE, + /*! Invalid clock ID. */ + ADI_CLOCK_SOURCE_ID_NOT_VALID + +} ADI_CLOCK_SOURCE_STATUS; + +/*! Clock output options through GPIO pin. + The GPIO clock output pin can be driven through one of these clocks. +*/ +typedef enum +{ + /*! Root Clock (ROOT_CLK). */ + ADI_CLOCK_OUTPUT_ROOT_CLK, + + /*! Low Frequency Clock (LF_CLK). */ + ADI_CLOCK_OUTPUT_LF_CLK, + + /*! ADC Clock (ACLK). */ + ADI_CLOCK_OUTPUT_ACLK, + + /*! HCLK_BUS. */ + ADI_CLOCK_OUTPUT_HCLK_BUS, + + /*! HCLK_CORE. */ + ADI_CLOCK_OUTPUT_HCLK_CORE, + + /*! Peripheral Clock (PCLK). */ + ADI_CLOCK_OUTPUT_PCLK, + + /*! Reference Clock for Flash controller timer (RCLK). */ + ADI_CLOCK_OUTPUT_RCLK, + + /*! Mux of HFOSC, HFXTAL clock (RHP_CLK). */ + ADI_CLOCK_OUTPUT_RHP_CLK, + + /*! GP Timer 0 clock (GPT0_CLK). */ + ADI_CLOCK_OUTPUT_GPT0_CLK, + + /*! GP Timer 1 clock (GPT1_CLK). */ + ADI_CLOCK_OUTPUT_GPT1_CLK, + + /*! Peripherals operating at HCLK (HCLK_P). */ + ADI_CLOCK_OUTPUT_HCLK_PERIPHERAL, + + /*! PLL Clock out. */ + ADI_CLOCK_OUTPUT_PLL_OUTPUT, + + /*! RTC0 Clock. */ + ADI_CLOCK_OUTPUT_RTC0_CLK, + + /*! HP Buck Clock (HPBUCK_CLK). */ + ADI_CLOCK_OUTPUT_HPBUCK_CLK, + + /*! HP Buck Non overlap clock. */ + ADI_CLOCK_OUTPUT_HPBUCK_NO_OVERLAP_CLK, + + /*! RTC1 generated clock. */ + ADI_CLOCK_OUTPUT_RTC1_CLK + +} ADI_CLOCK_OUTPUT_ID; + + +/*! Enumeration of clock gates using which the clocks can be gated. */ +typedef enum { + /*! Clock Gate for the GP Timer-0. */ + ADI_CLOCK_GATE_GPT0_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF, + /*! Clock Gate for the GP Timer-1. */ + ADI_CLOCK_GATE_GPT1_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF, + /*! Clock Gate for the GP Timer-2. */ + ADI_CLOCK_GATE_GPT2_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF, + /*! Clock Gate for the I2C. */ + ADI_CLOCK_GATE_I2C_CLK = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF, + /*! Clock Gate for the GPIO. */ + ADI_CLOCK_GATE_GPIO_CLK = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF, + /*! Clock Gate for the PCLK. */ + ADI_CLOCK_GATE_PCLK = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF, + +#if defined(__ADUCM4x50__) + /*! Clock Gate for the RGB Timer. */ + ADI_CLOCK_GATE_TMR_RGB_CLK = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF +#endif + +} ADI_CLOCK_GATE; + +#if defined(__ADUCM4x50__) +/*! + * Enumeration of HF oscillator clock divide factor. + */ +typedef enum +{ + /*! Divide by 1. */ + ADI_PWR_HFOSC_DIV_BY_1, + /*! Divide by 2. */ + ADI_PWR_HFOSC_DIV_BY_2, + /*! Divide by 4. */ + ADI_PWR_HFOSC_DIV_BY_4, + /*! Divide by 8. */ + ADI_PWR_HFOSC_DIV_BY_8, + /*! Divide by 16. */ + ADI_PWR_HFOSC_DIV_BY_16, + /*! Divide by 32. */ + ADI_PWR_HFOSC_DIV_BY_32 + +} ADI_PWR_HFOSC_DIV; +#endif /* __ADUCM4x50__ */ + + /*! + ***************************************************************************** + * Power driver API return codes + *****************************************************************************/ +typedef enum +{ + /*! No error detected. */ + ADI_PWR_SUCCESS = 0, + /*! Generic unknown error occurred. */ + ADI_PWR_FAILURE, + /*! If the given pointer is pointing to NULL. */ + ADI_PWR_NULL_POINTER, + /*! Requested divide value is out of range. */ + ADI_PWR_INVALID_CLOCK_DIVIDER, + /*! Invalid ADI_CLOCK_ID specified. */ + ADI_PWR_INVALID_CLOCK_ID, + /*! PDIV:HDIV ratio must be integral. */ + ADI_PWR_INVALID_CLOCK_RATIO, + /*! Invalid low-power mode requested. */ + ADI_PWR_INVALID_POWER_MODE, + /*! Invalid clock speed. */ + ADI_PWR_INVALID_CLOCK_SPEED, + /*! Specified operation is not allowed. */ + ADI_PWR_OPERATION_NOT_ALLOWED, + /*! Parameter is out of range. */ + ADI_PWR_INVALID_PARAM, + /*! System not initialized, call the API SystemInit. */ + ADI_PWR_SYSTEM_NOT_INITIALIZED + +} ADI_PWR_RESULT; + +/*! + * Enumeration of the power modes supported by the processor. + */ +typedef enum +{ + /*! Core Sleep power-down mode. */ + ADI_PWR_MODE_FLEXI = 0 << BITP_PMG_PWRMOD_MODE, + /*! Fully Active. (piggy-back on bitmode value "1", normally reserved) */ + ADI_PWR_MODE_ACTIVE = 1 << BITP_PMG_PWRMOD_MODE, + /*! Full Hibernate power-down mode. */ + ADI_PWR_MODE_HIBERNATE = 2 << BITP_PMG_PWRMOD_MODE, + /*! System Sleep power-down mode. */ + ADI_PWR_MODE_SHUTDOWN = 3 << BITP_PMG_PWRMOD_MODE + +} ADI_PWR_POWER_MODE; + + +/*! + * Enumeration of power management interrupts. + */ +typedef enum +{ + /*! Interrupt when battery voltage drops below 1.8V.*/ + ADI_PWR_LOW_BATTERY_VOLTAGE_IEN = 1 << BITP_PMG_IEN_VBAT, + /*! Interrupt when VREG under-voltage: below 1V. */ + ADI_PWR_UNDER_VOLATAGE_IEN = 1 << BITP_PMG_IEN_VREGUNDR, + /*! Interrupt when VREG over-voltage: over- 1.32V. */ + ADI_PWR_OVER_VOLATAGE_IEN = 1 << BITP_PMG_IEN_VREGOVR, + /*! Interrupt when battery voltage falls to the specified range.Please see #adi_pwr_SetVoltageRange.*/ + ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN = 1 << BITP_PMG_IEN_IENBAT + +} ADI_PWR_PMG_IRQ; + + +/*! + * Enumeration of system clock module interrupts. + */ +typedef enum +{ +#if defined(__ADUCM4x50__) + /*! Interrupt for root clock monitor and Clock Fail. */ + ADI_PWR_ROOT_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_ROOT_MON_EN, + /*! Interrupt for LFXTAL clock monitor and Clock Fail. */ + ADI_PWR_LFXTAL_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_LFX_MON_EN, + /*! Interrupt when LFXTAL clock becomes stable/unstable. */ + ADI_PWR_LFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE, + /*! Interrupt when HFXTAL clock becomes stable/unstable. */ + ADI_PWR_HFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE, + /*! Interrupt when PLL-LOCK/PLL-UNLOCK. */ + ADI_PWR_PLL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL3_SPLLIE +#elif defined(__ADUCM302x__) + /*! Interrupt for LFXTAL clock monitor and Clock Fail. */ + ADI_PWR_LFXTAL_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN, + /*! Interrupt when LFXTAL clock becomes stable/unstable. */ + ADI_PWR_LFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE, + /*! Interrupt when HFXTAL clock becomes stable/unstable. */ + ADI_PWR_HFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE, + /*! Interrupt when PLL-LOCK/PLL-UNLOCK. */ + ADI_PWR_PLL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL3_SPLLIE +#endif + +} ADI_PWR_CLOCK_IRQ; + +/** + * Enumeration of the power driver events notified through the callback. + */ +typedef enum +{ + /*! Event for indicating Over voltage VREG > 1.32v. */ + ADI_PWR_EVENT_VREG_OVER_VOLTAGE, + /*! Event for indicating under voltage VREG < 1V. */ + ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, + + /*! Event for indicating battery voltage below 1.8V. */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_LOW, + +#if defined(__ADUCM4x50__) + /*! Event for indicating battery voltage in specified range-1.VBAT range1 (> 2.75v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_1, + /*! Event for indicating battery voltage in specified range-2.VBAT range2 (2.75v - 2.3v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_2, + /*! Event for indicating battery voltage in specified range-3.VBAT range3 (2.3v - 1.6v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_3, + + /*! Event to indicate that LFXTAL failed and hardware automatically switched to LFOSC. */ + ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, + /*! Event to indicate the LFXTAL clock is not stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, + /*! Event to indicate the Root clock is not stable. */ + ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, + /*! Event to indicate the Root clock failed and hardware automatically switched to HFOSC. */ + ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, +#endif + + /*! Event to indicate HF crystal stable. */ + ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK, + /*! Event to indicate HF crystal is not stable. */ + ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK, + /*! Event to indicate LF crystal is stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK, + /*! Event to indicate LF crystal is not stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK, + /*! Event for indicating PLL is locked. */ + + ADI_PWR_EVENT_PLLC_LOCK, + /*! Event for indicating PLL is unlocked. */ + ADI_PWR_EVENT_PLLC_UNLOCK + +} ADI_PWR_EVENT; + + +/*! + * Enumeration of processor wake up status. +*/ +typedef enum +{ + /*! Interrupt from External Interrupt 0. */ + ADI_PWR_INT_EXT0, + /*! Interrupt from External Interrupt 1. */ + ADI_PWR_INT_EXT1, + /*! Interrupt from External Interrupt 2. */ + ADI_PWR_INT_EXT2, + /*! Interrupt from RTC. */ + ADI_PWR_INT_RTC + +} ADI_PWR_WAKEUP_STATUS; + +/*! + * Enumeration of the battery voltage ranges for voltage monitoring interrupt generation. +*/ +typedef enum +{ + /*! Voltage range is in safe region. */ + ADI_PWR_BAT_VOLTAGE_RANGE_SAFE, + /*! Battery voltage is in the range of 2.2 to 2.75 V. */ + ADI_PWR_VOLTAGE_RANGE_2_2_TO_2_75, + /*! Battery voltage is in the range of 1.6 to 2.2 V. */ + ADI_PWR_VOLTAGE_RANGE_1_6_TO_2_2 +} ADI_PWR_VOLTAGE_RANGE; + +#if defined(__ADUCM4x50__) +/*! + * Enumeration of LFXTAL Robust Mode Load select. The amount of loading tolerated when + * LFXTAL robust mode is selected, that is when LFXTAL robust mode is enabled. + */ +typedef enum +{ + /*! No Trim, and big resistive loads not tolerated. */ + ADI_PWR_LFXTAL_LOAD_NONE, + /*! 20 MOHM Load mode, greater than 20 MOHM load allowed. */ + ADI_PWR_LFXTAL_LOAD_20MOHM, + /*! 10 MOHM Load mode, greater than 10 MOHM load allowed. */ + ADI_PWR_LFXTAL_LOAD_10MOHM, + /*! 5 MOHM load resistance allowed on both IO pins, the user can scale the current + down if the load is expected to be smaller than 5 MOHM. */ + ADI_PWR_LFXTAL_LOAD_5MOHM + +}ADI_PWR_LFXTAL_LOAD; + +/*! +* Enumeration of HP Buck load modes. The modes can be used to choose the loading capability +* of the HPBUCK. The low load mode and high load mode are based on the loading in the system. +*/ +typedef enum +{ + /*! HPBUCK Low load mode. This mode can be set if the maximum system clock(HCLK) frequency + is 26 MHz. */ + ADI_PWR_HPBUCK_LD_MODE_LOW, + + /*! HPBUCK High load mode. This mode can be set if the system clock(HCLK) frequency is greater + than 26 MHz. */ + ADI_PWR_HPBUCK_LD_MODE_HIGH + +}ADI_PWR_HPBUCK_LD_MODE; +#endif /* __ADUCM4x50__ */ + +/* Related clock APIs */ + +/* + * Initialize the dynamic power management service + */ +ADI_PWR_RESULT adi_pwr_Init(void); + +/* + * ================================================================= + * Clock Management related APIs + * ================================================================= +*/ + +/* + * Update the internal clock variable based on current configuration + */ +ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void); + +/* + * Set the external clock frequency. + */ +ADI_PWR_RESULT adi_pwr_SetExtClkFreq( + const uint32_t ExtClkFreq + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetRootClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetPLLClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetLFClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +#if defined(__ADUCM4x50__) +/* + * To Enable/Disable the LFXTAL robust mode. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( + const bool bEnable + ); + +/* + * To configure the LFXTAL robust mode load. + */ +ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( + const ADI_PWR_LFXTAL_LOAD eLoad + ); + + +/* + * To Enable/Disable the LFXTAL Fail Auto switch. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( + const bool bEnable + ); + + +/* + * To enable/disable auto switching of root clock to HFOSC upon detection + * of Root clock failure. + */ +ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( + const bool bEnable + ); + +/* + * To set the HF Oscillator divide factor + */ +ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( + const ADI_PWR_HFOSC_DIV eDivFactor + ); + +/* + * To set the HF oscillator automatic divide by 1 during wakeup from Flexi mode + */ +ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( + const bool bEnable + ); + +#endif /* __ADUCM4x50__ */ + + + +/* + * To Configure the reference clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetRefClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * Get external clock frequency. + */ +ADI_PWR_RESULT adi_pwr_GetExtClkFreq( + uint32_t *pExtClock + ); + +/* + * Get current clock frequency. This API can be used to know PCLK, HCLK. + */ +ADI_PWR_RESULT adi_pwr_GetClockFrequency( + const ADI_CLOCK_ID eClockId, + uint32_t *pClock + ); +/* + * To enable/disable the specific clock. + */ +ADI_PWR_RESULT adi_pwr_EnableClock( + const ADI_CLOCK_GATE eClockGate, + const bool bEnable + ); + +/* + * To enable/disable the specific clock source. + */ +ADI_PWR_RESULT adi_pwr_EnableClockSource( + const ADI_CLOCK_SOURCE_ID eClockSource, + const bool bEnable + ); +/* + * To set the specific clock divider. +*/ +ADI_PWR_RESULT adi_pwr_SetClockDivider( + const ADI_CLOCK_ID eClockId, + const uint16_t nDiv + ); +/* + * To Get the clock status. +*/ +ADI_PWR_RESULT adi_pwr_GetClockStatus( + const ADI_CLOCK_SOURCE_ID eClockSource, + ADI_CLOCK_SOURCE_STATUS *peStatus + ); +/* + * To configure the PLL to generate the SPLL +*/ +ADI_PWR_RESULT adi_pwr_SetPll( + uint8_t nDivFactor, + const uint8_t nMulFactor, + const bool bDiv2, + const bool bMul2 + ); + +/* To enable the interrupt for clock monitoring LFXTAL/HFXTAL/PLL.*/ +ADI_PWR_RESULT adi_pwr_EnableClockInterrupt( + const ADI_PWR_CLOCK_IRQ eIrq, + const bool bEnable + ); + +/* Enabling the LFXTAL bypass mode */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass( + const bool bEnable + ); + + +/* + * ================================================================= + * Power Management related APIs + * ================================================================= +*/ +/* To enable the interrupt for voltage monitoring.*/ +ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt( + const ADI_PWR_PMG_IRQ eIrq, + const bool bEnable + ); + +/* + * To know which is interrupt caused the processor to wake up from SHUTDOWN mode. + */ +ADI_PWR_RESULT adi_pwr_GetWakeUpStatus( + ADI_PWR_WAKEUP_STATUS *peStatus + ); + +/* + * To select the voltage range of the battery for monitoring. +*/ +ADI_PWR_RESULT adi_pwr_SetVoltageRange( + const ADI_PWR_VOLTAGE_RANGE eRange + ); + +/* + * For entering the low power mode. +*/ +ADI_PWR_RESULT adi_pwr_EnterLowPowerMode( + const ADI_PWR_POWER_MODE PowerMode, + uint32_t volatile * pnInterruptOccurred, + const uint8_t PriorityMask + ); + +/* + * For exiting the low power mode. +*/ +ADI_PWR_RESULT adi_pwr_ExitLowPowerMode( + uint32_t volatile * pnInterruptOccurred + ); + +/* To enable the HPBUCK */ +ADI_PWR_RESULT adi_pwr_EnableHPBuck( + const bool bEnable + ); + +#if defined(__ADUCM4x50__) + +/* Set the clock output through the GPIO */ +ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput( + const ADI_CLOCK_OUTPUT_ID eClockOutput + ); + + +/* To enable the HPBUCK Low Power mode */ +ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( + const bool bEnable + ); + +/* To enable the HPBUCK Load mode */ +ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( + const ADI_PWR_HPBUCK_LD_MODE eLoadMode + ); + +#endif /* __ADUCM4x50__ */ +/* + * For registering the call back function . +*/ +ADI_PWR_RESULT adi_pwr_RegisterCallback( + const ADI_CALLBACK pfCallback, + void *pcbParam + ); + +#ifdef __cplusplus +} +#endif + +#endif /* ADI_PWR_H */ + + +/*@}*/ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rng/adi_rng.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rng/adi_rng.h new file mode 100755 index 00000000000..a8375fba1db --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rng/adi_rng.h @@ -0,0 +1,204 @@ +/*! + ***************************************************************************** + @file adi_rng.h + @brief Random Number Generator Driver + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup RNG_Driver RNG Driver + * Random Number Generator Driver + * @{ + */ + +#ifndef ADI_RNG_H +#define ADI_RNG_H + +#include +#include + +#if !defined(__ADUCM4x50__) && !defined(__ADUCM302x__) +#error "Unsupported processor" +#endif + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm011 +#endif /* __ICCARM__ */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_RNG_RESULT + * Random Number Generator API return codes + */ +typedef enum +{ + ADI_RNG_SUCCESS = 0, /*!< No Error, API suceeded */ + ADI_RNG_UNKNOWN_ERROR, /*!< Unknown error detected */ + ADI_RNG_ALREADY_INITIALIZED, /*!< RNG is already initialized */ + ADI_RNG_INVALID_PARAM, /*!< Invalid function parameter */ + ADI_RNG_BAD_DEV_HANDLE, /*!< Invalid device handle passed */ + ADI_RNG_BAD_DEVICE_NUM, /*!< Invalid device instance */ + ADI_RNG_NOT_INITIALIZED, /*!< RNG not yet initialized */ + ADI_RNG_INVALID_STATE /*!< Device is in an invalid state */ +} ADI_RNG_RESULT; + +/*! + * \enum ADI_RNG_EVENT + * Random Number Generator callback events + */ +typedef enum +{ + ADI_RNG_EVENT_READY, /*!< Random number ready event */ + ADI_RNG_EVENT_STUCK /*!< The ring oscillator got stuck event */ +} ADI_RNG_EVENT; + + +/*! The amount of application supplied memory required by the RNG driver */ +#define ADI_RNG_MEMORY_SIZE (12u) + + +/*! RNG Device handle typedef */ +typedef void* ADI_RNG_HANDLE; + +/*================ E X T E R N A L S ==================*/ + +/* + * RNG API + */ + +/* Open a random number generator device */ +extern ADI_RNG_RESULT adi_rng_Open( + uint32_t const nDeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_RNG_HANDLE* const phDevice + ); + +/* Close the RNG Device */ +extern ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice); + +/* Enable/Disable the device */ +extern ADI_RNG_RESULT adi_rng_Enable ( + ADI_RNG_HANDLE const hDevice, + bool const bFlag + ); +/* Enable/Disable buffering */ +extern ADI_RNG_RESULT adi_rng_EnableBuffering ( + ADI_RNG_HANDLE const hDevice, + bool const bFlag + ); + +/* Set the sample length */ +extern ADI_RNG_RESULT adi_rng_SetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t const nLenPrescaler, + uint16_t const nLenReload + ); + +/* Get whether the random number is ready */ +extern ADI_RNG_RESULT adi_rng_GetRdyStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ); + +/* Get whether the ring oscillator output is stuck or not */ +extern ADI_RNG_RESULT adi_rng_GetStuckStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ); + +/* Get the random number */ +extern ADI_RNG_RESULT adi_rng_GetRngData ( + ADI_RNG_HANDLE const hDevice, + uint32_t* const pRegData + ); + +/* Get the oscillator count */ +extern ADI_RNG_RESULT adi_rng_GetOscCount ( + ADI_RNG_HANDLE const hDevice, + uint32_t* const pOscCount + ); + +/* Get the oscillator count difference value */ +extern ADI_RNG_RESULT adi_rng_GetOscDiff ( + ADI_RNG_HANDLE const hDevice, + uint32_t const nIndex, + uint8_t* const pOscDiff + ); + +/* Register a callback */ +extern ADI_RNG_RESULT adi_rng_RegisterCallback ( + ADI_RNG_HANDLE hDevice, + ADI_CALLBACK cbFunc, + void *pCBParam + ); + +/* Retrieve the current RNG sample length prescale and reload value configured in the device. */ +extern ADI_RNG_RESULT adi_rng_GetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t* const pLenPrescaler, + uint16_t* const pLenReload + ); + +#ifdef __cplusplus +} +#endif + +#ifdef __ICCARM__ +#pragma diag_default=Pm011 +#endif /* __ICCARM__ */ +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rtc/adi_rtc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rtc/adi_rtc.h new file mode 100755 index 00000000000..4e235f70583 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/rtc/adi_rtc.h @@ -0,0 +1,522 @@ +/*! + ***************************************************************************** + @file adi_rtc.h + @brief Primary include file for Real Time Clock Services. + @version $Revision: 29004 $ + @date $Date: 2014-12-06 10:37:26 -0500 (Sat, 06 Dec 2014) $ + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_RTC_H__ +#define ADI_RTC_H__ +#include "adi_processor.h" + +#include +#include +#include + +/*! \addtogroup RTC_Driver RTC Driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + + +/*! Amount of memory(In bytes) required by the RTC device driver for managing the operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_RTC_MEMORY_SIZE (24u) + +/*! Emergency flush command to gatweay register */ +#define ADI_RTC_GATEWAY_FLUSH 0xa2c5 + +/*! A device handle used in all API functions to identify the RTC device. */ +typedef void* ADI_RTC_HANDLE; + +/*! Interrupt bit position-1*/ +#define ADI_RTC_INTERRUPT_OFFSET 16 + +/*! Interrupt bit position-2*/ +#define ADI_RTC_INTERRUPT_OFFSET_IO_CAPTURE 21 + +/*! + * RTC API return codes + */ +typedef enum +{ + /*! No Error, API succeeded */ + ADI_RTC_SUCCESS, + /*! Generic failure */ + ADI_RTC_FAILURE, + /*! RTC is in failsafe mode and not reliable */ + ADI_RTC_CLOCK_FAILSAFE, + /*! RTC is already initialized */ + ADI_RTC_IN_USE, + /*! Invalid device handle passed */ + ADI_RTC_INVALID_HANDLE, + /*! Asking to initialize an unknown instance */ + ADI_RTC_INVALID_INSTANCE, + /*! Parameter is out of range */ + ADI_RTC_INVALID_OPTION, + /*! Specified operation not allowed */ + ADI_RTC_OPERATION_NOT_ALLOWED, + /*! One of the parameters is invalid */ + ADI_RTC_INVALID_PARAM, + /*! Input/SensorStrobe channel is invalid for the specified operation */ + ADI_RTC_INVALID_CHANNEL + +} ADI_RTC_RESULT; + + +/*! + * RTC Interrupt Enable Bits. + */ + + +typedef uint32_t ADI_RTC_INT_TYPE; + +#define ADI_RTC_ALARM_INT 0x00000001u /*!< Alarm interrupt enable bit */ +#define ADI_RTC_MOD60ALM_INT 0x00000002u /*!< modulo 60 Alarm interrupt enable */ +#define ADI_RTC_ISO_DONE_INT 0x00000004u /*!< Power isolation done interrupt enable */ +#define ADI_RTC_WRITE_PENDERR_INT 0x00000008u /*!< Write pend error interrupt enable */ +#define ADI_RTC_WRITE_SYNC_INT 0x00000010u /*!< Write sync interrupt enable */ +#define ADI_RTC_WRITE_PEND_INT 0x00000020u /*!< Write pend interrupt enable */ +#define ADI_RTC_COUNT_INT 0x00000040u /*!< RTC count interrupt source enable */ +#define ADI_RTC_PSI_INT 0x00000080u /*!< Precaled Module 1 interrupt */ +#define ADI_RTC_TRIM_INT 0x00000100u /*!< Enable for the RTC trim interrupt source */ +#define ADI_RTC_COUNT_ROLLOVER_INT 0x00000200u /*!< Enable for the RTC count roll-over interrupt source */ +#define ADI_RTC_MOD60_ROLLOVER_INT 0x00000400u /*!< Enable for the RTC modulo-60 count roll-over interrupt source */ +#define ADI_RTC_SENSOR_STROBE_CH1_INT 0x00000800u /*!< Enable interrupt for sensor strobe channel -1*/ +#define ADI_RTC_SENSOR_STROBE_CH2_INT 0x00001000u /*!< Enable interrupt for sensor strobe channel -2*/ +#define ADI_RTC_SENSOR_STROBE_CH3_INT 0x00002000u /*!< Enable interrupt for sensor strobe channel -3*/ +#define ADI_RTC_SENSOR_STROBE_CH4_INT 0x00004000u /*!< Enable interrupt for sensor strobe channel -4*/ +#define ADI_RTC_INPUT_CAPTURE_CH0_INT 0x00008000u /*!< Enable interrupt for input capture channel -0*/ +#define ADI_RTC_INPUT_CAPTURE_CH2_INT 0x00010000u /*!< Enable interrupt for input capture channel -2*/ +#define ADI_RTC_INPUT_CAPTURE_CH3_INT 0x00020000u /*!< Enable interrupt for input capture channel -3*/ +#define ADI_RTC_INPUT_CAPTURE_CH4_INT 0x00040000u /*!< Enable interrupt for input capture channel -4*/ +#define ADI_RTC_LFXTL_FAILURE_INT 0x00080000u /*!< Interrupt for LFXTL failure. LFXTL failure interrupt is mapped to RTC1 interrupt.*/ +#define ADI_RTC_RTCSS4_FE_INT 0x00100000u /*!< Enable interrupt for Sensor Strobe channel 3*/ +#define ADI_RTC_RTCSS3_FE_INT 0x00200000u /*!< Enable interrupt for Sensor Strobe channel 3*/ +#define ADI_RTC_RTCSS2_FE_INT 0x00400000u /*!< Enable interrupt for Sensor Strobe channel 2*/ +#define ADI_RTC_RTCSS1_FE_INT 0x00800000u /*!< Enable interrupt for Sensor Strobe channel 2*/ +#define ADI_RTC_RTCSS4MSKEN 0x01000000u /*!< Enable interrupt for Sensor Strobe channel 4 Mask */ +#define ADI_RTC_RTCSS3MSKEN 0x02000000u /*!< Enable interrupt for Sensor Strobe channel 3 Mask */ +#define ADI_RTC_RTCSS2MSKEN 0x04000000u /*!< Enable interrupt for Sensor Strobe channel 2 Mask */ +#define ADI_RTC_RTCSS1MSKEN 0x08000000u /*!< Enable interrupt for Sensor Strobe channel 1 Mask */ +#define ADI_RTC_CR5OCS_SS3SMPMTCHIRQEN 0x10000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 3 */ +#define ADI_RTC_CR5OCS_SS2SMPMTCHIRQEN 0x20000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 2 */ +#define ADI_RTC_CR5OCS_SS1SMPMTCHIRQEN 0x40000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 1. */ + + +#define ADI_RTC_NUM_INTERRUPTS 31 /*!< Number of RTC interrupts. */ + + +/*! + * RTC Posted Write Status Bits. + */ +typedef enum +{ + /*! Posted write control register-0 status bit */ + ADI_RTC_WRITE_STATUS_CONTROL0 = 1 << BITP_RTC_SR0_WSYNCCR0, + /*! Posted write status0 register status bit */ + ADI_RTC_WRITE_STATUS_STATUS0 = 1 << BITP_RTC_SR0_WSYNCSR0, + /*! Posted write count0 register status bit */ + ADI_RTC_WRITE_STATUS_COUNT0 = 1 << BITP_RTC_SR0_WSYNCCNT0, + /*! Posted write count1 register status bit */ + ADI_RTC_WRITE_STATUS_COUNT1 = 1 << BITP_RTC_SR0_WSYNCCNT1, + /*! Posted write alarm0 register status bit */ + ADI_RTC_WRITE_STATUS_ALARM0 = 1 << BITP_RTC_SR0_WSYNCALM0, + /*! Posted write alarm1 register status bit */ + ADI_RTC_WRITE_STATUS_ALARM1 = 1 << BITP_RTC_SR0_WSYNCALM1, + /*! Posted write trim register status bit */ + ADI_RTC_WRITE_STATUS_TRIM = 1 << BITP_RTC_SR0_WSYNCTRM +} ADI_RTC_WRITE_STATUS; + + +/*! + * RTC Trim intervals. + */ +typedef enum +{ + /*! Trim interval is 2^2 seconds */ + ADI_RTC_TRIM_INTERVAL_2 = (2 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^3 seconds */ + ADI_RTC_TRIM_INTERVAL_3 = (3 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^4 seconds */ + ADI_RTC_TRIM_INTERVAL_4 = (4 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^5 seconds */ + ADI_RTC_TRIM_INTERVAL_5 = (5 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^6 seconds */ + ADI_RTC_TRIM_INTERVAL_6 = (6 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^7 seconds */ + ADI_RTC_TRIM_INTERVAL_7 = (7 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^8 seconds */ + ADI_RTC_TRIM_INTERVAL_8 = (8 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^9 seconds */ + ADI_RTC_TRIM_INTERVAL_9 = (9 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^10 seconds */ + ADI_RTC_TRIM_INTERVAL_10 = (10 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^11 seconds */ + ADI_RTC_TRIM_INTERVAL_11 = (11 << BITP_RTC_TRM_IVL2EXPMIN | 0x1 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^12 seconds */ + ADI_RTC_TRIM_INTERVAL_12 = (12 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^13 seconds */ + ADI_RTC_TRIM_INTERVAL_13 = (13 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^14 seconds */ + ADI_RTC_TRIM_INTERVAL_14 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^15 seconds */ + ADI_RTC_TRIM_INTERVAL_15 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x1 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^16 seconds */ + ADI_RTC_TRIM_INTERVAL_16 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x2 << BITP_RTC_TRM_IVL ), + /*! Trim interval is 2^17 seconds */ + ADI_RTC_TRIM_INTERVAL_17 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x3 << BITP_RTC_TRM_IVL) + +} ADI_RTC_TRIM_INTERVAL; + +/*! + * RTC input capture channels. + */ +typedef enum +{ + /*! Input capture channel-0 */ + ADI_RTC_INPUT_CHANNEL_0 = 1 << BITP_RTC_CR2IC_IC0EN, + /*! Input capture channel-2 */ + ADI_RTC_INPUT_CHANNEL_2 = 1 << BITP_RTC_CR2IC_IC2EN, + /*! Input capture channel-3 */ + ADI_RTC_INPUT_CHANNEL_3 = 1 << BITP_RTC_CR2IC_IC3EN, + /*! Input capture channel-4 */ + ADI_RTC_INPUT_CHANNEL_4 = 1 << BITP_RTC_CR2IC_IC4EN + +}ADI_RTC_INPUT_CHANNEL; + +/*! + * RTC Sensor Strobe channels. + */ +typedef enum +{ + /*! Sensor Strobe channel-1 */ + ADI_RTC_SS_CHANNEL_1 = 1 << BITP_RTC_CR3SS_SS1EN, +#if defined(__ADUCM4x50__) + /*! Sensor Strobe channel-2 */ + ADI_RTC_SS_CHANNEL_2 = 1 << BITP_RTC_CR3SS_SS2EN, + /*! Sensor Strobe channel-3 */ + ADI_RTC_SS_CHANNEL_3 = 1 << BITP_RTC_CR3SS_SS3EN, + /*! Sensor Strobe channel-4 */ + ADI_RTC_SS_CHANNEL_4 = 1 << BITP_RTC_CR3SS_SS4EN, +#endif /* __ADUCM4x50__ */ +}ADI_RTC_SS_CHANNEL; + +/*! + * RTC Trim polarity. + */ +typedef enum +{ + /*! Trim value is added every trim interval */ + ADI_RTC_TRIM_ADD = (1 << BITP_RTC_TRM_ADD), + /*! Trim value is subtracted every trim interval */ + ADI_RTC_TRIM_SUB = (0 << BITP_RTC_TRM_ADD), +} ADI_RTC_TRIM_POLARITY; + +/*! + * RTC Trim values. + */ +typedef enum +{ + /*! Trim value is +/- 0 */ + ADI_RTC_TRIM_0 = (0 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 1 */ + ADI_RTC_TRIM_1 = (1 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 2 */ + ADI_RTC_TRIM_2 = (2 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 3 */ + ADI_RTC_TRIM_3 = (3 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 4 */ + ADI_RTC_TRIM_4 = (4 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 5 */ + ADI_RTC_TRIM_5 = (5 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 6 */ + ADI_RTC_TRIM_6 = (6 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 7 */ + ADI_RTC_TRIM_7 = (7 << BITP_RTC_TRM_VALUE) +} ADI_RTC_TRIM_VALUE; + +/*! + * RTC control register set. + */ +typedef enum +{ + /*! Specify the RTC-Control register-0 */ + ADI_RTC_CONTROL_REGISTER_0, + /*! Specify the RTC-Control register-1 */ + ADI_RTC_CONTROL_REGISTER_1 +} ADI_RTC_CONTROL_REGISTER; + +/*================ E X T E R N A L S ==================*/ + +/* + */ + +/*************************************/ +/* RTC API */ +/*************************************/ +ADI_RTC_RESULT adi_rtc_Open( + uint32_t DeviceNumber, + void *pDeviceMemory, + uint32_t MemorySize, + ADI_RTC_HANDLE *phDevice + ); + +ADI_RTC_RESULT adi_rtc_Close( + ADI_RTC_HANDLE const hDevice + ); + +/*************************************/ +/* Enable APIs for RTC Device */ +/*************************************/ + +ADI_RTC_RESULT adi_rtc_EnableAlarm( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableMod60Alarm( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_Enable( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableInterrupts( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INT_TYPE Interrupts, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableTrim( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableAutoReload( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableInputCapture ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eInpChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot ( + ADI_RTC_HANDLE const hDevice, + bool bEnable); + +/*************************************/ +/* Set APIs for RTC Device */ +/*************************************/ + + +ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod( + ADI_RTC_HANDLE const hDevice, + uint8_t nPeriod + ); + +ADI_RTC_RESULT adi_rtc_SetAlarm( + ADI_RTC_HANDLE const hDevice, + uint32_t nAlarm + ); + +ADI_RTC_RESULT adi_rtc_SetAlarmEx( + ADI_RTC_HANDLE const hDevice, + float fAlarm + ); + + +ADI_RTC_RESULT adi_rtc_SetControlRegister( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_CONTROL_REGISTER eRegister, + uint32_t Control + ); + +ADI_RTC_RESULT adi_rtc_SetCount( + ADI_RTC_HANDLE const hDevice, + uint32_t nCount + ); + +ADI_RTC_RESULT adi_rtc_SetGateway( + ADI_RTC_HANDLE const hDevice, + uint16_t Command + ); + + +ADI_RTC_RESULT adi_rtc_SetPreScale( + ADI_RTC_HANDLE const hDevice, + uint8_t nPreScale + ); + +ADI_RTC_RESULT adi_rtc_SetTrim( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_TRIM_INTERVAL eInterval, + ADI_RTC_TRIM_VALUE eTrimValue, + ADI_RTC_TRIM_POLARITY eOperation + ); + +ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint8_t nMask); + +ADI_RTC_RESULT adi_rtc_SetAutoReloadValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t nValue); + +ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eInpChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t nValue); + +/*************************************/ +/* Get APIs for RTC Device */ +/*************************************/ + +ADI_RTC_RESULT adi_rtc_GetAlarm ( + ADI_RTC_HANDLE hDevice, + uint32_t *pAlarm + ); + +ADI_RTC_RESULT adi_rtc_GetAlarmEx ( + ADI_RTC_HANDLE hDevice, + float *pAlarm); + +ADI_RTC_RESULT adi_rtc_GetControl ( + ADI_RTC_HANDLE hDevice, + ADI_RTC_CONTROL_REGISTER eRegister , + uint32_t *pControl); + +ADI_RTC_RESULT adi_rtc_GetTrim( + ADI_RTC_HANDLE hDevice, + ADI_RTC_TRIM_VALUE *peTrim + ); + +ADI_RTC_RESULT adi_rtc_GetCount( + ADI_RTC_HANDLE const hDevice, + uint32_t *pCount + ); + +ADI_RTC_RESULT adi_rtc_GetCountEx( + ADI_RTC_HANDLE const hDevice, + float *pfCount + ); + +ADI_RTC_RESULT adi_rtc_GetSnapShot( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eChannel, + uint32_t *pValue, + uint16_t *pFraction); + +ADI_RTC_RESULT adi_rtc_GetInputCaptureValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eChannel, + uint16_t *pValue); + +ADI_RTC_RESULT adi_rtc_GetWritePendStatus( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_WRITE_STATUS *pPendBits + ); + +ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_WRITE_STATUS *pSyncBits + ); + +ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t *pValue); + +ADI_RTC_RESULT adi_rtc_GetCountRegs( + ADI_RTC_HANDLE const hDevice, + uint32_t *pnCount, + uint32_t *pfCount); +/************************************************/ +/* RTC APIs for managing interrupt/sync */ +/***********************************************/ + +ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites( + ADI_RTC_HANDLE const hDevice + ); + +ADI_RTC_RESULT adi_rtc_RegisterCallback( + ADI_RTC_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBparam + ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_RTC_H__ */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/spi/adi_spi.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/spi/adi_spi.h new file mode 100755 index 00000000000..31e9b977d91 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/spi/adi_spi.h @@ -0,0 +1,397 @@ +/*! ***************************************************************************** + * @file adi_spi.h + * @brief Main include file for SPI Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here.ADI_SEM_SIZE + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_SPI_H__ +#define ADI_SPI_H__ + +#include +#include +#include + +/** @addtogroup SPI_Driver SPI Driver + * @{ + */ + + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! Amount of memory(In bytes) required by the SPI device driver for managing the operation + * of a SPI controller. The memory is passed to the driver when the driver is opened. + * The memory is completely owned by the driver till the the driver is closed. + * + */ + +#define ADI_SPI_MEMORY_SIZE (40u + ADI_SEM_SIZE) + + +/*! + ***************************************************************************** + * \enum ADI_SPI_RESULT + * + * SPI Device Error Codes. #ADI_SPI_SUCCESS is always zero + * The return value of all SPI APIs returning #ADI_SPI_RESULT + * should always be tested at the application level for success or failure. + * + *****************************************************************************/ +typedef enum +{ + /*! Generic success. */ + ADI_SPI_SUCCESS, + /*! Generic Failure. */ + ADI_SPI_FAILURE, + /*! SPI device is already initialized. */ + ADI_SPI_IN_USE, + /*! Invalid device handle. */ + ADI_SPI_INVALID_HANDLE, + /*! Invalid device ID. */ + ADI_SPI_INVALID_DEVICE_NUM, + /*! DMA configuration failure. */ + ADI_SPI_DMA_ERROR , + /*! NULL data pointer not allowed. */ + ADI_SPI_INVALID_POINTER, + /*! Parameter is out of range. */ + ADI_SPI_INVALID_PARAM, + /*! Unsupported mode of operation. */ + ADI_SPI_UNSUPPORTED_MODE, + /*! Semaphore in error . */ + ADI_SPI_SEMAPHORE_FAILED, + /*! Invalid operation */ + ADI_SPI_INVALID_OPERATION, + /*! Buffer Not submitted */ + ADI_SPI_BUFFER_NOT_SUBMITTED, + /*! Could not obtain the system clock */ + ADI_SPI_BAD_SYS_CLOCK, + /*! Blocking PEND failed */ + ADI_SPI_PEND_FAILED, + /*! DMA callback register failed */ + ADI_SPI_DMA_REG_FAILED, + /*! Hardware error occurred */ + ADI_SPI_HW_ERROR_OCCURRED +} ADI_SPI_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_SPI_HW_ERRORS + * + * Enumeration of events notified in the application provided callback. + * More than one event can be recorded at a time so the enumerator symbols + * have to be assigned values of 2^N + *****************************************************************************/ +typedef enum +{ + /*!< The given buffer is processed. Application can use this event to submit + the next buffer to be transmitted. */ + ADI_SPI_HW_ERROR_NONE = 0u, + /*! Tx-underflow interrupt enable */ + ADI_SPI_HW_ERROR_TX_UNDERFLOW = 1u, + /*! Rx-overflow interrupt enable */ + ADI_SPI_HW_ERROR_RX_OVERFLOW = 2u, + /*! Rx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT = 4u, + /*! Tx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT = 8u, + /*! Rx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR = 16u, + /*! Tx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR = 32u, + /*! Rx DMA channel unkown error detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR = 64u, + /*! Tx DMA channel unkown error detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR = 128u + +} ADI_SPI_HW_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_SPI_CHIP_SELECT + * + * SPI Device Chip Select Enumeration. Allows designation of an external + * SPI slave device chip select pin to be driven by the SPI controller. + * Multiple external slave SPI devices may be present on a shared SPI bus, + * and the chip select pin allows each of them to be assigned dedicated selects. + * Use the #adi_spi_SetChipSelect() API to configure the active chip select. + * Note that SPI0 is an internal channel dedicated to the UHF controller and + * hence, has a dedicated SPI0 chip select pin that is not available externally. + * + *****************************************************************************/ +typedef enum +{ + /*! No Slave Chip Select for SPI. */ + ADI_SPI_CS_NONE = 0, + /*! CS0 Slave Chip Select for SPI. */ + ADI_SPI_CS0 = 1, + /*! CS1 Slave Chip Select for SPI. */ + ADI_SPI_CS1 = 2, + /*! CS2 Slave Chip Select for SPI. */ + ADI_SPI_CS2 = 4, + /*! CS3 Slave Chip Select for SPI. */ + ADI_SPI_CS3 = 8 +} ADI_SPI_CHIP_SELECT; + + +/*! SPI Device instance private data handle typedef. */ +typedef struct __ADI_SPI_DEV_DATA_TYPE* ADI_SPI_HANDLE; +/*! SPI Device instance private data handle typedef. 'const' version */ +typedef const struct __ADI_SPI_DEV_DATA_TYPE* ADI_SPI_CONST_HANDLE; + + +/*! + * \struct ADI_SPI_TRANSCEIVER + ***************************************************************************** + * SPI Device Command/Data Transceiver Structure. Data structure used by + * the #adi_spi_MasterReadWrite(),#adi_spi_MasterSubmitBuffer() + * API to convey all parameters, consisting of + * prologue, transmit and receive data and size, and buffer increment flags. + * DMA and Half-Duplex operation are also specified in this structure as T/F. + * + * Each call to #adi_spi_MasterReadWrite or #adi_spi_MasterSubmitBuffer() must populate the following fields of the + * ADI_SPI_TRANSCEIVER block: + * + * @par TransmitterBytes + * The number of bytes to be transmitted. If the value is zero, data will not be transmitted from the + * buffer pointed by pTransmitter. + * + * @par ReceiverBytes + * The number of bytes to be received. If the value is zero, data will not be stored in the + * buffer pointed by pReceiver. + * + * @par pTransmitter + * Pointer to the application-defined transmit data buffer. This is the data sent out + * over the SPI transmit wire (MOSI for Master-mode, MISO for Slave-mode) during the SPI transaction. + * For SPI DMA mode (which is 16-bit based), the transmit buffer must be 16-bit aligned. + * + * @par pReceiver + * Pointer to the application-defined receive data buffer. This is where the receive data + * will be stored from the SPI receive wire (MISO for Master-mode, MOSI for Slave-mode) + * during the SPI transaction. + * For SPI DMA mode (which is 16-bit based), the receive buffer must be 16-bit aligned. + * + * @par bTxIncrement + * Increment to be done for the transmit buffer after every transaction . The transmit data buffer + * pointer is advanced as each byte is sent. If it is set to zero, the transmit data pointer is stationary. + * A stationary buffer pointer is useful for sending the same data to an external device or if + * the source data is from a fixed memory address. + * + * @par bRxIncrement + * Increment to be done for the receive buffer. The transmit data buffer + * pointer is advanced as each byte is sent. If it is value is set to zero, the receive + * data pointer is stationary. A stationary buffer pointer is useful for monitoring commands + * from an external device or if the receive data is going to a fixed memory address. + * + * @par bDMA + * Indicate whether the transaction is to use DMA (true) or not (false). If using DMA SPI + * transactions are limited to 2048 bytes. If more than 2048 bytes are needed then the application + * must use multiple transactions (DMA ping pong mode is not supported in the driver). + * For SPI DMA mode (which is 16-bit based), TransmitterBytes/ReceiverBytes is rounded up to an + * even number by the SPI driver before submitting to DMA. + * Please align the buffer to 16 bit word boundary since the data transfer is 16bit. + * + * + * @par bRD_CTL + * Indicate whether the transaction should enable RD_CTL (true) or not (false). + * RD_CTL effectively provides half-duplex operation as outlined in the HRM. + + *****************************************************************************/ +typedef struct +{ + /*! Pointer to transmit data. */ + uint8_t* pTransmitter; + /*! Pointer to receive data. */ + uint8_t* pReceiver; + /*! Data size for TX(bytes). */ + uint16_t TransmitterBytes; + /*! Data size for RX(bytes). */ + uint16_t ReceiverBytes; + /*! Transmit pointer increment flag. */ + uint8_t nTxIncrement; + /*! Receive pointer increment flag. */ + uint8_t nRxIncrement; + /*! DMA mode operation */ + bool bDMA; + /*! RD_CTL, half-duplex, operation */ + bool bRD_CTL; + +} ADI_SPI_TRANSCEIVER; + + + +/****************************************************************************** + * SPI Device External API function prototypes + *****************************************************************************/ + +/* Device Initialization and Uninitialization Interfaces */ +ADI_SPI_RESULT adi_spi_Open( + uint32_t nDeviceNum, + void *pDevMemory, + uint32_t nMemorySize, + ADI_SPI_HANDLE* const phDevice + ); + +ADI_SPI_RESULT adi_spi_Close( + ADI_SPI_HANDLE const hDevice + ); + +/****************************************************************** + * Eliminatable functions that may be optimized out by the linker * + *****************************************************************/ + +ADI_SPI_RESULT adi_spi_MasterReadWrite( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + + +ADI_SPI_RESULT adi_spi_SetMasterMode( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +/* Slave Mode APIs */ +ADI_SPI_RESULT adi_spi_SlaveReadWrite( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + +/* Command/Data transceiver API */ +ADI_SPI_RESULT adi_spi_MasterSubmitBuffer( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + +ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* + const pXfr + ); + +ADI_SPI_RESULT adi_spi_RegisterCallback ( + ADI_SPI_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBParam + ); + + +/* Turn a non-blocking call into a blocking call. Wait for the transaction to complete */ +ADI_SPI_RESULT adi_spi_GetBuffer( + ADI_SPI_HANDLE const hDevice, + uint32_t * const pHWErrors + ); + +/* Hardware Configuration Interface */ +ADI_SPI_RESULT adi_spi_SetClockPhase( + ADI_SPI_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetClockPolarity( + ADI_SPI_HANDLE const hDevice, + const bool bFlag + ); + +/* Query function for the data transfer completion */ +ADI_SPI_RESULT adi_spi_isBufferAvailable( + ADI_SPI_CONST_HANDLE const hDevice, + bool* const bComplete + ); + + + +ADI_SPI_RESULT adi_spi_SetContinuousMode( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + + +ADI_SPI_RESULT adi_spi_SetLoopback( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetIrqmode ( + ADI_SPI_CONST_HANDLE const hDevice, + const uint8_t nMode); + +ADI_SPI_RESULT adi_spi_SetReceiveOverflow( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetTransmitUnderflow( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +/* Mode Configuration Interface */ +ADI_SPI_RESULT adi_spi_SetBitrate( + ADI_SPI_CONST_HANDLE const hDevice, + const uint32_t Hertz + ); +ADI_SPI_RESULT adi_spi_SetChipSelect( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_CHIP_SELECT eChipSelect + ); + +ADI_SPI_RESULT adi_spi_GetBitrate( + ADI_SPI_CONST_HANDLE const hDevice, + uint32_t* const pnBitrate + ); + + +#ifdef __cplusplus +} +#endif + + +/**@}*/ + + +#endif /* ADI_SPI_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/sport/adi_sport.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/sport/adi_sport.h new file mode 100755 index 00000000000..aaf32f2cb0a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/sport/adi_sport.h @@ -0,0 +1,236 @@ +/*! **************************************************************************** + * @file adi_sport.h + * @brief SPORT (Serial Port) Device driver definitions + * @details Header File for the SPORT driver API functions and definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_SPORT_H +#define ADI_SPORT_H + +/*============= I N C L U D E S =============*/ + +#include +#include +#include +#include + +/** @addtogroup SPORT_Driver SPORT Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*============== D E F I N E S ===============*/ + +/** + * Amount of memory (bytes) required by the SPORT device driver for managing + * the operation in interrupt mode. This memory is completely owned by the + * driver till the end of the operation. + */ +#define ADI_SPORT_MEMORY_SIZE (76u + ADI_SEM_SIZE) + +typedef void* ADI_SPORT_HANDLE; /*!< Handle to the SPORT Device */ + +/** + * Enumeration of different channels of the SPORT + */ +typedef enum +{ + ADI_HALF_SPORT_A = 0, /*!< First half SPORT */ + ADI_HALF_SPORT_B = 1 /*!< Second half SPORT */ +} ADI_SPORT_CHANNEL; + +/** + * Enumeration for the direction of operation. + */ +typedef enum +{ + ADI_SPORT_DIR_RX, /*!< Sport in Rx mode */ + ADI_SPORT_DIR_TX /*!< Sport in Tx mode */ +} ADI_SPORT_DIRECTION; + +/** + * Enumeration for enabling packing. + */ +typedef enum +{ + ADI_SPORT_NO_PACKING = 0, /*!< No Packing */ + ADI_SPORT_8BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_8BIT, /*!< 8-bit packing */ + ADI_SPORT_16BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_16BIT /*!< 16-Bit packing */ +} ADI_SPORT_PACKING_MODE; + +/** + * Enumeration for Hardware Error encountered by the SPORT device. + */ + typedef enum +{ + ADI_SPORT_HW_NO_ERR = 0x00, /*!< No Hardware error */ + ADI_SPORT_HW_ERR_RX_OVERFLOW = 0x02, /*!< Data overflow for Rx (same value as Tx underflow) */ + ADI_SPORT_HW_ERR_TX_UNDERFLOW = 0x02, /*!< Data underflow for Tx (same value as Rx overflow) */ + ADI_SPORT_HW_ERR_FS = 0x04, /*!< Frame sync error */ + ADI_SPORT_HW_ERR_SYSDATAERR = 0x10, /*!< System Data Error */ + + ADI_SPORT_EVENT_RX_BUFFER_PROCESSED = 0x20, /*!< Processed the submitted RX buffer */ + ADI_SPORT_EVENT_TX_BUFFER_PROCESSED = 0x40, /*!< Processed the submitted TX buffer */ + + ADI_SPORT_DMA_ERR_BUS = 0x100, /*!< SPORT DMA bus error detected */ + ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR = 0x200 /*!< SPORT DMA invalid descriptor error detected */ +}ADI_SPORT_EVENT; + + +/** + * Enumeration for result code returned from the SPORT device driver functions. + */ +typedef enum +{ + ADI_SPORT_SUCCESS, /*!< Success */ + ADI_SPORT_FAILED, /*!< Generic Failure to indicate a call to SPORT driver function returned unsuccessful */ + ADI_SPORT_INVALID_DEVICE_NUM , /*!< Invalid device number */ + ADI_SPORT_INVALID_NULL_POINTER, /*!< Specified pointer is invalid */ + ADI_SPORT_INVALID_HANDLE, /*!< The given handle is invalid */ + ADI_SPORT_INVALID_PARAMETER, /*!< Specified parameter is not valid */ + ADI_SPORT_DMA_REGISTER_FAILED, /*!< Registering DMA error handler failed */ + ADI_SPORT_DEVICE_IN_USE, /*!< The specified SPORT channel is already open and in use */ + ADI_SPORT_INVALID_CONFIGURATION, /*!< The SPORT configuration is invalid */ + ADI_SPORT_BUFFERS_NOT_SUBMITTED, /*!< Buffer submission failed */ + ADI_SPORT_INVALID_WORD_LENGTH, /*!< Invalid word size */ + ADI_SPORT_OPERATION_NOT_ALLOWED, /*!< Specified operation is not allowed when SPORT is transmitting/receiving data */ + ADI_SPORT_HW_ERROR /*!< SPORT hardware or DMA reports an error */ +} ADI_SPORT_RESULT; + +/*============= P U B L I C F U N C T I O N S =============*/ + +/* Opens a SPORT device */ +ADI_SPORT_RESULT adi_sport_Open( + const uint32_t nDevNum, + const ADI_SPORT_CHANNEL eChannel, + const ADI_SPORT_DIRECTION eDirection, + void *pMemory, + const uint32_t nMemSize, + ADI_SPORT_HANDLE * const phDevice + ); + +/* Closes a SPORT device */ +ADI_SPORT_RESULT adi_sport_Close( + ADI_SPORT_HANDLE const hDevice + ); + +/* Submits a buffer to the driver */ +ADI_SPORT_RESULT adi_sport_SubmitBuffer( + ADI_SPORT_HANDLE const hDevice, + void * const pBuffer, + uint32_t const nNumBytes, + bool const bDMA + ); + +/* Get the processed buffer from the driver */ +ADI_SPORT_RESULT adi_sport_GetBuffer( + ADI_SPORT_HANDLE const hDevice, + void ** const ppBuffer, + uint32_t * pHwError + ); + +/* Peek function to know whether an processed buffer is avilable */ +ADI_SPORT_RESULT adi_sport_IsBufferAvailable( + ADI_SPORT_HANDLE const hDevice, + bool * const pbAvailable + ); + +/* To register the callback function */ +ADI_SPORT_RESULT adi_sport_RegisterCallback( + ADI_SPORT_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void * const pCBparam + ); + +/* Configure the data */ +ADI_SPORT_RESULT adi_sport_ConfigData( + ADI_SPORT_HANDLE const hDevice, + const uint8_t nWordLength, + const ADI_SPORT_PACKING_MODE ePackMode, + const bool bLSBFirst + ); + +/* Configure the clock */ +ADI_SPORT_RESULT adi_sport_ConfigClock( + ADI_SPORT_HANDLE const hDevice, + const uint16_t nClockRatio, + const bool bUseIntlClock, + const bool bRisingEdge, + const bool bGatedClk + ); + +/* Configure the frame sync */ +ADI_SPORT_RESULT adi_sport_ConfigFrameSync( + ADI_SPORT_HANDLE const hDevice, + const uint16_t nFsDivisor, + const bool bFSRequired, + const bool bInternalFS, + const bool bDataFS, + const bool bActiveLowFS, + const bool bLateFS, + const bool bFSErrorOperation + ); + +/* To mux the half-SPORT; this makes the device to use FS and Clock from other half-SPORT */ +ADI_SPORT_RESULT adi_sport_MultiplexSportSignal( + ADI_SPORT_HANDLE const hDevice, + const bool bUseOtherFS, + const bool bUseOtherClk + ); + +/* To configure the SPORT in timer mode */ +ADI_SPORT_RESULT adi_sport_ConfigTimerMode( + ADI_SPORT_HANDLE const hDevice, + const uint8_t nFSDuration, + const uint8_t nWidth, + const bool bActiveLow + ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ADI_SPORT_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/tmr/adi_tmr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/tmr/adi_tmr.h new file mode 100755 index 00000000000..33d00dece17 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/tmr/adi_tmr.h @@ -0,0 +1,261 @@ +/*! ***************************************************************************** + * @file adi_tmr.h + * @brief GP and RGB timer device driver public header file + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_H +#define ADI_TMR_H + + +#include +#include +#include +#include + + +/** @addtogroup TMR_Driver Timer Driver + * @{ + */ + + +/*! + ***************************************************************************** + * \enum ADI_TMR_RESULT + * Enumeration for result code returned from the timer device driver functions. + * The return value of all timer APIs returning #ADI_TMR_RESULT should always + * be tested at the application level for success or failure. + *****************************************************************************/ +typedef enum { + /*! Successful operation */ + ADI_TMR_SUCCESS, + /*! Bad device number supplied by user */ + ADI_TMR_BAD_DEVICE_NUM, + /*! Bad PWM output number supplied by user to #adi_tmr_ConfigPwm */ + ADI_TMR_BAD_PWM_NUM, + /*! Bad event number supplied by user to #adi_tmr_ConfigEvent */ + ADI_TMR_BAD_EVENT_ID, + /*! Bad timer configuration, reloading and free running are mutually exclusive options */ + ADI_TMR_BAD_RELOAD_CONFIGURATION, + /*! Setup or enable function called while the timer is running */ + ADI_TMR_OPERATION_NOT_ALLOWED, + /*! Timeout while waiting for busy bit to clear before writing control register */ + ADI_TMR_DEVICE_BUSY, + /*! User attempts to reload the timer when reloading has not been enabled */ + ADI_TMR_RELOAD_DISABLED, + /*! User attempts to read the current or captured count with a NULL pointer */ + ADI_TMR_NULL_POINTER +} ADI_TMR_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_TMR_DEVICE + * Enumeration for the hardware peripheral being used during the API call + *****************************************************************************/ +typedef enum { + /*! General purpose timer 0 */ + ADI_TMR_DEVICE_GP0 = 0u, + /*! General purpose timer 1 */ + ADI_TMR_DEVICE_GP1 = 1u, + /*! General purpose timer 2 */ + ADI_TMR_DEVICE_GP2 = 2u, +#if defined(__ADUCM302x__) + /*! Total number of devices (private) */ + ADI_TMR_DEVICE_NUM = 3u, +#elif defined(__ADUCM4x50__) + /*! RGB timer */ + ADI_TMR_DEVICE_RGB = 3u, + /*! Total number of devices (private) */ + ADI_TMR_DEVICE_NUM = 4u, +#else +#error TMR is not ported for this processor +#endif +} ADI_TMR_DEVICE; + +/*! + ***************************************************************************** + * \enum ADI_TMR_EVENT + * Enumeration of events notified in the application provided callback. + *****************************************************************************/ +typedef enum { + /*! Timeout event occurred */ + ADI_TMR_EVENT_TIMEOUT = 0x01, + /*! Event capture event occurred */ + ADI_TMR_EVENT_CAPTURE = 0x02, +} ADI_TMR_EVENT; + +/*! + ***************************************************************************** + * \enum ADI_TMR_PRESCALER + * Prescale options when configuring the timer + *****************************************************************************/ +typedef enum { + /*! Count every 1 source clock periods */ + ADI_TMR_PRESCALER_1 = 0u, + /*! Count every 16 source clock periods */ + ADI_TMR_PRESCALER_16 = 1u, + /*! Count every 64 source clock periods */ + ADI_TMR_PRESCALER_64 = 2u, + /*! Count every 256 source clock periods */ + ADI_TMR_PRESCALER_256 = 3u, +} ADI_TMR_PRESCALER; + +/*! + ***************************************************************************** + * \enum ADI_TMR_CLOCK_SOURCE + * Source clock options when configuring the timer + *****************************************************************************/ +typedef enum { + /*! Use periphreal clock (PCLK) */ + ADI_TMR_CLOCK_PCLK = 0u, + /*! Use internal high frequency clock (HFOSC) */ + ADI_TMR_CLOCK_HFOSC = 1u, + /*! Use internal low frequency clock (LFOSC) */ + ADI_TMR_CLOCK_LFOSC = 2u, + /*! Use external low frequency clock (LFXTAL) */ + ADI_TMR_CLOCK_LFXTAL = 3u, +} ADI_TMR_CLOCK_SOURCE; + +/*! + ***************************************************************************** + * \enum ADI_TMR_PWM_OUTPUT + * RGB PWM outputs, used to specify which PWM output to configure. For the GP + * timers only #ADI_TMR_PWM_OUTPUT_0 is allowed. The RGB timer has all three + * outputs. + *****************************************************************************/ +typedef enum { + /*! PWM output 0 */ + ADI_TMR_PWM_OUTPUT_0 = 0u, + /*! PWM output 1 */ + ADI_TMR_PWM_OUTPUT_1 = 1u, + /*! PWM output 2 */ + ADI_TMR_PWM_OUTPUT_2 = 2u, + /*! Total number of outputs (private) */ + ADI_TMR_PWM_OUTPUT_NUM = 3u, +} ADI_TMR_PWM_OUTPUT; + +/*! + ***************************************************************************** + * \struct ADI_TMR_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigTimer when + * configuring the GP or RGB timer + *****************************************************************************/ +typedef struct { + /*! True to count up, false to count down */ + bool bCountingUp; + /*! True for periodic (specific load value), false for free running (0xFFFF) */ + bool bPeriodic; + /*! Prescaler */ + ADI_TMR_PRESCALER ePrescaler; + /*! Clock source */ + ADI_TMR_CLOCK_SOURCE eClockSource; + /*! Load value (only relevant in periodic mode) */ + uint16_t nLoad; + /*! Asynchronous load value (only relevant in periodic mode, and when PCLK is used) */ + uint16_t nAsyncLoad; + /*! True to enable reloading, false to disable it (only relevant in periodic mode) */ + bool bReloading; + /*! True to enable sync bypass, false to disable it */ + bool bSyncBypass; +} ADI_TMR_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_TMR_EVENT_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigEvent when + * configuring event capture + *****************************************************************************/ +typedef struct { + /*! True to enable event capture, false to disable it */ + bool bEnable; + /*! True to reset the counter and prescaler when the selected event occurs, false to let it continue */ + bool bPrescaleReset; + /*! Event identifier, see hardware reference manual for details */ + uint8_t nEventID; +} ADI_TMR_EVENT_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_TMR_PWM_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigPwm when + * configuring pulse width modulation output + *****************************************************************************/ +typedef struct { + /*! PWM output */ + ADI_TMR_PWM_OUTPUT eOutput; + /*! True if match mode (configurable duty cycle), false if toggle mode (50% duty cycle) */ + bool bMatch; + /*! True for PWM idle high, false for PWM idle low */ + bool bIdleHigh; + /*! Match value, only applicable if in match mode */ + uint16_t nMatchValue; +} ADI_TMR_PWM_CONFIG; + +/****************************************************************************** + * PUBLIC API + * 1.) Eliminate functions that may be optimized out by the linker + * 2.) Ordered by designed function call sequence + *****************************************************************************/ + +/* Initialize timer driver */ +ADI_TMR_RESULT adi_tmr_Init (ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt); + +/* Configuration interface functions */ +ADI_TMR_RESULT adi_tmr_ConfigTimer (ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG* timerConfig); +ADI_TMR_RESULT adi_tmr_ConfigEvent (ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG* eventConfig); +ADI_TMR_RESULT adi_tmr_ConfigPwm (ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG* pwmConfig ); + +/* Timer start and stop */ +ADI_TMR_RESULT adi_tmr_Enable (ADI_TMR_DEVICE const eDevice, bool bEnable); + +/* Read functions */ +ADI_TMR_RESULT adi_tmr_GetCurrentCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount); +ADI_TMR_RESULT adi_tmr_GetCaptureCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount); + +/* Reload function */ +ADI_TMR_RESULT adi_tmr_Reload (ADI_TMR_DEVICE const eDevice); + + +/*! @} */ + + +#endif /* ADI_TMR_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/uart/adi_uart.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/uart/adi_uart.h new file mode 100755 index 00000000000..abb0bf3109a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/uart/adi_uart.h @@ -0,0 +1,498 @@ +/*! ***************************************************************************** + * @file adi_uart.h + * @brief UART device driver global include file. + * @details This a global file which includes a specific file based on the processor family. + * This included file will be containing UART device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_UART_H +#define ADI_UART_H + +/** @addtogroup UART_Driver UART Driver +* @{ +*/ + +/*! \cond PRIVATE */ + +/*============= I N C L U D E S =============*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! \endcond */ + +/*! Amount of memory(bytes) required by the UART device driver for operating unidirectionally(Either RX or TX). + * This memory is completely owned by the driver until the end of the operation. + */ +#define ADI_UART_UNIDIR_MEMORY_SIZE (48u + (60u + ADI_SEM_SIZE)) + +/*! Amount of memory(bytes) required by the UART device driver for operating bidirectionally(Both RX and TX). + * This memory is completely owned by the driver until the end of the operation. + */ +#define ADI_UART_BIDIR_MEMORY_SIZE (48u + (60u + ADI_SEM_SIZE)*2u) + +/*! + * Handle for managing the UART device typedef. + */ +typedef struct _ADI_UART_DEVICE* ADI_UART_HANDLE; + +/*! + * Handle for managing the UART device typedef 'const' version. + */ +typedef const struct _ADI_UART_DEVICE* ADI_UART_CONST_HANDLE; + +/*! + ***************************************************************************** + * \enum ADI_UART_DIRECTION + * Enumeration for the UART direction. + *****************************************************************************/ +typedef enum +{ + ADI_UART_DIR_TRANSMIT, /*!< UART is only transmitting. */ + + ADI_UART_DIR_RECEIVE, /*!< UART is only receiving. */ + + ADI_UART_DIR_BIDIRECTION /*!< UART in bidirectional. */ + +} ADI_UART_DIRECTION; + + +/*! + ***************************************************************************** + * \enum ADI_UART_EVENT + * Enumeration of events notified in the application provided callback. + *****************************************************************************/ + typedef enum +{ + ADI_UART_EVENT_RX_BUFFER_PROCESSED, /*!< Rx buffer is processed. */ + + ADI_UART_EVENT_TX_BUFFER_PROCESSED, /*!< Tx buffer is processed. */ + + ADI_UART_EVENT_NO_RX_BUFFER_EVENT, /*!< No Rx buffer but data is in FIFO. */ + + ADI_UART_EVENT_AUTOBAUD_COMPLETE, /*!< Autobaud is complete. */ + + ADI_UART_EVENT_HW_ERROR_DETECTED, /*!< Hardware error detected. */ + + ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED /*!< Autobaud error detected. */ + +}ADI_UART_EVENT; + + +/*! + ***************************************************************************** + * \enum ADI_UART_RESULT + * Enumeration for result code returned from the UART device driver functions. + * The return value of all UART APIs returning #ADI_UART_RESULT + * should always be tested at the application level for success or failure. + *****************************************************************************/ + typedef enum +{ + + ADI_UART_SUCCESS, /*!< Generic success. */ + + ADI_UART_FAILED, /*!< Generic failure. */ + + ADI_UART_SEMAPHORE_FAILED, /*!< Semaphore error. */ + + ADI_UART_INVALID_HANDLE, /*!< Invalid device handle. */ + + ADI_UART_DEVICE_IN_USE, /*!< UART device in use. */ + + ADI_UART_INVALID_DEVICE_NUM, /*!< Invalid device number. */ + + ADI_UART_INVALID_POINTER, /*!< NULL data pointer is not allowed. */ + + ADI_UART_INSUFFICIENT_MEMORY, /*!< Insufficent memory. */ + + ADI_UART_INVALID_DIR, /*!< Invalid UART direction. */ + + ADI_UART_OPERATION_NOT_ALLOWED, /*!< Invalid operation. */ + + ADI_UART_INVALID_PARAMETER, /*!< Invalid parameter. */ + + ADI_UART_BUFFER_NOT_SUBMITTED, /*!< Buffer not submitted. */ + + ADI_UART_INVALID_DATA_TRANSFER_MODE, /*!< Invalid transfer mode. + Adi_uart_Read()/adi_uart_Write() is used in nonblocking mode + or adi_uart_SubmitRxBuffer()/adi_uart_SubmitTxBuffer() + is used in blocking mode. */ + + ADI_UART_HW_ERROR_DETECTED, /*!< Hardware error detected. */ + + ADI_UART_AUTOBAUD_ERROR_DETECTED, /*!< Autobaud error detected. */ + + ADI_UART_ERR_DMA_REGISTER, /*!< Error while registering the DMA callback. */ + + ADI_UART_INVALID_DATA_SIZE /*!< Invalid transfer size. Must be less than 1025 bytes */ + +} ADI_UART_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_UART_HW_ERRORS + * Enumeration for UART hardware errors. If hardware error(s) occur in + * either callback or interrupt mode, they are mapped to #ADI_UART_HW_ERRORS. + * Interpretation of the break condition is application specific. + *****************************************************************************/ +typedef enum +{ + ADI_UART_NO_HW_ERROR = 0x00, /*!< No hardware error. */ + + ADI_UART_HW_ERR_FRAMING = 0x10, /*!< Rx framing error. */ + + ADI_UART_HW_ERR_PARITY = 0x20, /*!< Rx parity error. */ + + ADI_UART_HW_ERR_OVERRUN = 0x40, /*!< Receive overrun. */ + + ADI_UART_BREAK_INTERRUPT = 0x80, /*!< Break condition. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT = 0x100, /*!< Rx DMA channel bus fault detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT = 0x200, /*!< Tx DMA channel bus fault detected. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR = 0x400, /*!< Rx DMA channel invalid descriptor detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR = 0x800, /*!< Tx DMA channel invalid descriptor detected. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR = 0x1000, /*!< Rx DMA channel unknown error detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR = 0x2000, /*!< Tx DMA channel unknown error detected. */ + +}ADI_UART_HW_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_UART_AUTOBAUD_ERRORS + * Enumeration for UART autobaud errors. If autobaud related error(s) occur + * they are mapped to #ADI_UART_AUTOBAUD_ERRORS. + *****************************************************************************/ +typedef enum +{ + ADI_UART_AUTOBAUD_NO_ERROR = 0x000, /*!< No autobaud error. */ + + ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE = 0x100, /*!< Timeout due to no valid start edge found during autobaud. */ + + ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK = 0x200, /*!< Timeout due to break condition detected during autobaud. */ + + ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE = 0x400 /*!< Timeout due to no valid end edge found during autobaud. */ + +}ADI_UART_AUTOBAUD_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_UART_TRIG_LEVEL + * Enumeration for the FIFO trigger level. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_RX_FIFO_TRIG_LEVEL_1BYTE = 0 << BITP_UART_FCR_RFTRIG, /*!< 1-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_4BYTE = 1 << BITP_UART_FCR_RFTRIG, /*!< 4-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_8BYTE = 2 << BITP_UART_FCR_RFTRIG, /*!< 8-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE = 3 << BITP_UART_FCR_RFTRIG /*!< 14-byte to trigger RX interrupt. */ + +}ADI_UART_TRIG_LEVEL; + +/*! + ***************************************************************************** + * \enum ADI_UART_WORDLEN + * Enumeration for data width. + *****************************************************************************/ +typedef enum +{ + ADI_UART_WORDLEN_5BITS, /*!< 5 bits wide. */ + + ADI_UART_WORDLEN_6BITS, /*!< 6 bits wide. */ + + ADI_UART_WORDLEN_7BITS, /*!< 7 bits wide. */ + + ADI_UART_WORDLEN_8BITS /*!< 8 bits wide. */ + +} ADI_UART_WORDLEN; + +/*! + ***************************************************************************** + * \enum ADI_UART_PARITY + * Enumeration for parity check. + *****************************************************************************/ +typedef enum +{ + ADI_UART_NO_PARITY = 0x0, /*!< No parity. */ + + ADI_UART_ODD_PARITY = 0x8, /*!< Odd parity. */ + + ADI_UART_EVEN_PARITY = 0x18, /*!< Even Parity. */ + + ADI_UART_ODD_PARITY_STICKY = 0x28, /*!< Sticky odd parity. */ + + ADI_UART_EVEN_PARITY_STICKY = 0x38 /*!< Sticky even parity. */ + +} ADI_UART_PARITY; + +/*! + ***************************************************************************** + * \enum ADI_UART_STOPBITS + * Enumeration for the number of stop bits. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_ONE_STOPBIT = 0x00, /*! One stop bit regardless of the word length */ + + ADI_UART_ONE_AND_HALF_TWO_STOPBITS = 0x04 /*! Number of stop bits based on word length. 1.5 stop bits + for word length of 5 bits and 2 for rest( 6,7,8 bit word length) */ + +} ADI_UART_STOPBITS; + +/*! + ***************************************************************************** + * \enum ADI_UART_TRANSFER_MODE + * Enumeration for data transfer mode. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_DATA_TRANSFER_MODE_NONE, /*! Mode of data transfer is not selected. */ + + ADI_UART_DATA_TRANSFER_MODE_BLOCKING, /*! Blocking mode. Only calls to adi_uart_Read or adi_uart_write + are allowed for sending or receiving data. */ + + ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING /*! Non-Blocking mode. Only calls to adi_uart_SubmitRxBuffer or + adi_uart_SubmitTxBuffer are allowed for sending or receiving data. */ + +} ADI_UART_TRANSFER_MODE; + + +/****************************************************************************** + * UART Device external API function prototypes + *****************************************************************************/ + +/* + * Device initialization and uninitialization interfaces. +*/ +ADI_UART_RESULT adi_uart_Open( + uint32_t const nDeviceNum, + ADI_UART_DIRECTION const eDirection, + void *pMemory, + uint32_t const nMemSize, + ADI_UART_HANDLE *const phDevice +); + +ADI_UART_RESULT adi_uart_Close( + ADI_UART_HANDLE const hDevice +); + + +/****************************************************************************** + * Eliminatable functions that may be optimized out by the linker + *****************************************************************************/ + +/* + * Non-blocking mode functions. +*/ + +ADI_UART_RESULT adi_uart_SubmitTxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA +); + +ADI_UART_RESULT adi_uart_SubmitRxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA +); + +ADI_UART_RESULT adi_uart_GetTxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError +); + +ADI_UART_RESULT adi_uart_GetRxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError +); +ADI_UART_RESULT adi_uart_IsTxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable +); + +ADI_UART_RESULT adi_uart_IsRxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable +); + +/* + * Blocking mode functions. +*/ + +ADI_UART_RESULT adi_uart_Write( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError +); + +ADI_UART_RESULT adi_uart_Read( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError +); + + +/* + * Configuration interface functions. +*/ + +ADI_UART_RESULT adi_uart_EnableLoopBack( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_EnableAutobaud( + ADI_UART_HANDLE const hDevice, + bool const bEnable, + bool const bAutobaudCallbackMode +); + +ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_TRIG_LEVEL const eTriglevel +); + +ADI_UART_RESULT adi_uart_EnableFifo( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_GetBaudRate( + ADI_UART_HANDLE const hDevice, + uint32_t *pnBaudRate, + uint32_t *pAutobaudError +); + +ADI_UART_RESULT adi_uart_ForceTxBreak( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_SetConfiguration( + ADI_UART_HANDLE const hDevice, + ADI_UART_PARITY const eParity, + ADI_UART_STOPBITS const eStopBits, + ADI_UART_WORDLEN const eWordLength +); + +ADI_UART_RESULT adi_uart_ConfigBaudRate( + ADI_UART_HANDLE const hDevice, + uint16_t const nDivC, + uint8_t const nDivM, + uint16_t const nDivN, + uint8_t const nOSR +); + +/* + * Channel data control functions. +*/ + +ADI_UART_RESULT adi_uart_FlushTxFifo( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_FlushRxFifo( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_FlushRxChannel( + ADI_UART_CONST_HANDLE const hDevice +); + + +ADI_UART_RESULT adi_uart_FlushTxChannel( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_IsTxComplete( + ADI_UART_HANDLE const hDevice, + bool *const pbComplete +); + +/* + * Callback functions. +*/ + +ADI_UART_RESULT adi_uart_RegisterCallback( + ADI_UART_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void *const pCBParam +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*@}*/ + +#endif /* ADI_UART_H */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/wdt/adi_wdt.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/wdt/adi_wdt.h new file mode 100755 index 00000000000..834afee018d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/wdt/adi_wdt.h @@ -0,0 +1,77 @@ +/*! ***************************************************************************** + * @file adi_wdt.h + * @brief WDT device driver public header + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_WDT_H +#define ADI_WDT_H + +#include + +/** @addtogroup WDT_Driver WDT Driver + * @{ + */ + +/*! \enum ADI_WDT_RESULT Watchdog Device Error Codes. */ +typedef enum +{ + /*! Generic success. */ + ADI_WDT_SUCCESS, + /*! Timer is locked. */ + ADI_WDT_FAILURE_LOCKED +} ADI_WDT_RESULT; + + +/****************************************************************************** + * PUBLIC API + * 1.) Eliminatable functions that may be optimized out by the linker + * 2.) Ordered by designed function call sequence + *****************************************************************************/ + +ADI_WDT_RESULT adi_wdt_Enable (bool const bEnable, ADI_CALLBACK const pfCallback); +void adi_wdt_Kick (void); +void adi_wdt_GetCount(uint16_t * const pCurCount); + + +/*! @} */ + +#endif /* ADI_WDT_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/xint/adi_xint.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/xint/adi_xint.h new file mode 100755 index 00000000000..15269983940 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/drivers/xint/adi_xint.h @@ -0,0 +1,121 @@ +/* + ***************************************************************************** + @file: adi_xint.h + @brief: External interrupt driver definitions and API + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_XINT_H +#define ADI_XINT_H + +/*! \addtogroup XINT_Driver External Interrupt Driver + * @{ + */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm008 +#endif /* __ICCARM__ */ + +#include +#include + +#if !defined(__ADUCM302x__) && !defined(__ADUCM4x50__) +#error "Unknown processor family" +#endif + + +/* C++ linkage */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! Amount of memory(in bytes) required by the External Interrupt device driver for its operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_XINT_MEMORY_SIZE (48u) + +/*! External Interrupt Driver API function return codes */ +typedef enum +{ + ADI_XINT_SUCCESS = 0, /*!< API successfully returned. */ + ADI_XINT_FAILURE, /*!< The API call failed. */ + ADI_XINT_ALREADY_INITIALIZED, /*!< External interrupt driver has already been initialized. */ + ADI_XINT_NOT_INITIALIZED, /*!< External interrupt driver has not yet been initialized. */ + ADI_XINT_NULL_PARAMETER, /*!< The given pointer is pointing to NULL. */ + ADI_XINT_INVALID_MEMORY_SIZE, /*!< The given memory is not sufficient to operate the driver. */ + ADI_XINT_INVALID_INTERRUPT /*!< Invalid interrupt number. */ +} ADI_XINT_RESULT; + + +/*! External interrupt trigger condition enumerations */ +typedef enum { + ADI_XINT_IRQ_RISING_EDGE = 0x0, /*!< Trigger an interrupt when a rising edge is detected. */ + ADI_XINT_IRQ_FALLING_EDGE = 0x1, /*!< Trigger an interrupt when on a falling edge is detected. */ + ADI_XINT_IRQ_EITHER_EDGE = 0x2, /*!< Trigger an interrupt on either falling or rising edge is detected. */ + ADI_XINT_IRQ_HIGH_LEVEL = 0x3, /*!< Trigger an interrupt on a logic level high is detected. */ + ADI_XINT_IRQ_LOW_LEVEL = 0x4 /*!< Trigger an interrupt on a logic level low is detected. */ +} ADI_XINT_IRQ_MODE; + +/*! External interrupts. */ +typedef enum { + ADI_XINT_EVENT_INT0 = 0x0, /*!< Event for external interrupt-0 */ + ADI_XINT_EVENT_INT1 = 0x1, /*!< Event for external interrupt-1 */ + ADI_XINT_EVENT_INT2 = 0x2, /*!< Event for external interrupt-2 */ + ADI_XINT_EVENT_INT3 = 0x3, /*!< Event for external interrupt-3 */ + ADI_XINT_EVENT_RESERVED = 0x4, /*!< Event is reserved. */ + ADI_XINT_EVENT_UART_RX = 0x5, /*!< Event for UART Rx activity */ + ADI_XINT_EVENT_MAX = 0x6 /*!< Number of external interrupt events */ +} ADI_XINT_EVENT; + + +/* External Interrupt API functions */ +ADI_XINT_RESULT adi_xint_Init (void* const pMemory, uint32_t const MemorySize); +ADI_XINT_RESULT adi_xint_UnInit (void); +ADI_XINT_RESULT adi_xint_EnableIRQ (const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode); +ADI_XINT_RESULT adi_xint_DisableIRQ (const ADI_XINT_EVENT eEvent); +ADI_XINT_RESULT adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_XINT_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash.c new file mode 100755 index 00000000000..2488596cb6c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash.c @@ -0,0 +1,1815 @@ +/*! + ***************************************************************************** + @file: adi_flash.c + @brief: Flash Device Driver Implementation + @date: $Date: 2016-06-30 08:06:37 -0400 (Thu, 30 Jun 2016) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup Flash_Driver Flash Driver + * @{ + * + * @brief Flash (FEE) Driver + * + * @details + * + * The flash controller provides access to the embedded flash memory. The embedded + * flash has a 72-bit wide data bus providing for two 32-bit words of data and + * one corresponding 8-bit ECC byte per access. + * + * Flash Driver Hardware Errors + * + * Many of the Flash Controller APIs can result in hardware errors. Each such API has a + * a hardware error parameter (pHwErrors), which is a pointer to an application-defined + * variable into which the failing API will store the failing hardware error status.\n + * + * APIs failing with hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED + * return code.\n + * + * Hardware error details may be decoded according to the flash controller status register + * ("STAT") bit-map, documented in the Hardware Reference Manual (HRM). Flash hardware + * errors are separate and distinct from DMA errors, which have separate and distinct + * return codes (#ADI_FEE_ERR_DMA_BUS_FAULT, #ADI_FEE_ERR_DMA_INVALID_DESCR, and + * #ADI_FEE_ERR_DMA_UNKNOWN_ERROR). + * + * Flash Driver Static Configuration + * + * A number of flash driver APIs manage configurations that very likely do not require + * dynamic (run-time) management. Such cases are documented with the respective APIs. + * In all such cases, the user is encouraged to consider using the static configuration + * equivalents (provided in the adi_flash_config.h file) in lieu of the dynamic APIs. + * In so doing, linker elimination may reduce the resulting code image footprint + * (provided the API is not called). + * + * @note - The application must include drivers/flash/adi_flash.h to use this driver. + * @note - This driver also requires the DMA driver. The application must include + * the DMA driver sources to avoid link errors. + */ + +/*======== I N C L U D E ========*/ + + /*! \cond PRIVATE */ +#include +#include +#include /* for "memset" */ +/*! \endcond */ + +#include + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Required for MMR accesses, determining pointer alignment, and a callback argument. +* +* Pm026 (rule 12.4): the right hand operand of an && or || operator shall not contain side effects +* Side effects being mis-reported due to added volatile storage class. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm026 +#endif /* __ICCARM__ */ + +/* pull in internal data structures */ +#include "adi_flash_data.c" + +/*======== D E F I N E S ========*/ + +/*! \cond PRIVATE */ + +#ifdef ADI_DEBUG +#define ASSERT(X) assert(X) +#else +#define ASSERT(X) +#endif + +/* internal utility macros */ +#define CLR_BITS(REG, BITS) ((REG) &= ~(BITS)) +#define SET_BITS(REG, BITS) ((REG) |= (BITS)) + +#ifdef ADI_DEBUG +/* Validate Device Handle */ +static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice); +static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice) +{ + if ( (fee_device_info[0].hDevice == (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL) ) { + return true; + } else { + return false; + } +} +#endif + +/* Wait for specified flash status to be clear */ +static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status); +static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status) +{ + while ((hDevice->pDev->STAT & status) != 0u) {} +} + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler */ +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg); +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* recover the device handle */ + ADI_FEE_HANDLE hDevice = (ADI_FEE_HANDLE)pCBParam; + + /* save the DMA error */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->dmaError = ADI_FEE_ERR_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->dmaError = ADI_FEE_ERR_DMA_INVALID_DESCR; + break; + default: + hDevice->dmaError = ADI_FEE_ERR_DMA_UNKNOWN_ERROR; + break; + } + + /* transfer is toast... post and callback any waiters */ + + SEM_POST(hDevice); + + if (0u != hDevice->pfCallback) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, (void*)NULL); + } +} + +/*! \endcond */ + + +/*======== C O D E ========*/ +/* + * API Implementation + */ + + +/** + * @brief Open the flash controller. + * + * @param [in] nDeviceNum The zero-based device instance number of flash controller to be opened. + * @param [in] pMemory Application supplied memory space for use by the driver. + * @param [in] nMemorySize Size of the application supplied memory (in bytes). + * @param [in,out] phDevice The caller's device handle pointer for storing the initialized + * device instance data pointer. + * + * @return Status + * - #ADI_FEE_SUCCESS The device is opened successfully. + * - #ADI_FEE_ERR_BAD_DEVICE_NUM [D] The device number passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Some pointer(s) passed to the function is NULL. + * - #ADI_FEE_ERR_ALREADY_INITIALIZED [D] The device is already initialized and hence cannot be opened. + * - #ADI_FEE_ERR_INSUFFICIENT_MEM [D] The memory passed to the driver is insufficient. + * - #ADI_FEE_ERR_DMA_REGISTER The required DMA common error handler registration failed. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore create operation failed. + * + * Initialize an instance of the flash device driver using default user configuration settings + * (from adi_flash_config.h) and allocate the device for use. + * + * No other flash APIs may be called until the device open function is called. The returned + * device handle is required to be passed to all subsequent flash API calls to identify the + * physical device instance in use. The user device handle (pointed to by phDevice) is set + * to NULL on failure. + * + * @note Currently, only a singular flash physical device instance (device ID "0") exists. + * + * @sa adi_fee_Close(). + */ +ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice) +{ + ADI_FEE_HANDLE hDevice = NULL; /* initially */ + +#ifdef ADI_DEBUG + if (nDeviceNum >= ADI_FEE_NUM_INSTANCES) { + return ADI_FEE_ERR_BAD_DEVICE_NUM; + } + + /* verify device is not already open */ + if (fee_device_info[nDeviceNum].hDevice != NULL) { + return ADI_FEE_ERR_ALREADY_INITIALIZED; + } + + if ((pMemory == NULL) || (phDevice == NULL)) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (nMemorySize < ADI_FEE_MEMORY_SIZE) { + return ADI_FEE_ERR_INSUFFICIENT_MEM; + } + + assert (ADI_FEE_MEMORY_SIZE == sizeof(ADI_FEE_DEV_DATA_TYPE)); +#endif + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* Link user memory (handle) into ADI_FEE_DEVICE_INFO data structure. + * + * ADI_FEE_DEVICE_INFO <==> ADI_FEE_HANDLE + */ + fee_device_info[nDeviceNum].hDevice = (ADI_FEE_DEV_DATA_TYPE *)pMemory; + + /* Clear the ADI_FEE_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bUseDma = false) + */ + memset(pMemory, 0, nMemorySize); + + /* initialize local device handle and link up device info for this device instance */ + hDevice = (ADI_FEE_HANDLE)pMemory; + hDevice->pDevInfo = &fee_device_info[nDeviceNum]; + + /* Although the ADI_FEE_DEVICE_INFO struct has the physical device pointer + * for this instance, copying it to the ADI_FEE_HANDLE struct (in user memory) + * will minimize the runtime footprint and cycle count when accessing the FEE + * registers. + */ + hDevice->pDev = fee_device_info[nDeviceNum].pDev; + + /* store a pointer to user's static configuration settings for this device instance */ + hDevice->pDevInfo->pConfig = (ADI_FEE_CONFIG*)&gConfigInfo[nDeviceNum]; + + /* create the semaphore */ + SEM_CREATE(hDevice, "fee_sem", ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* grant keyed access */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + + /* apply the static initializers */ + hDevice->pDev->IEN = hDevice->pDevInfo->pConfig->eccIrqEnables; + hDevice->pDev->TIME_PARAM0 = hDevice->pDevInfo->pConfig->param0; + hDevice->pDev->TIME_PARAM1 = hDevice->pDevInfo->pConfig->param1; + hDevice->pDev->ABORT_EN_LO = hDevice->pDevInfo->pConfig->abortEnableLo; + hDevice->pDev->ABORT_EN_HI = hDevice->pDevInfo->pConfig->abortEnableHi; + hDevice->pDev->ECC_CFG = hDevice->pDevInfo->pConfig->eccConfig; + + /* clear auto-increment and dma enable bits */ + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + + /* close keyed access */ + hDevice->pDev->KEY = 0u; + + /* store device handle into user handle */ + *phDevice = (ADI_FEE_HANDLE)hDevice; + + /* initialize DMA service */ + adi_dma_Init(); + + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize flash driver and fail */ + adi_fee_Close(hDevice); + return ADI_FEE_ERR_DMA_REGISTER; + } + + /* NVIC enables */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaIrqNum); + + /* return success */ + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Close the flash controller. + * + * @param [in] hDevice The handle to the flash controller device + * + * @return Status + * - #ADI_FEE_SUCCESS The device is closed successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore delete operation failed. + * + * Uninitialize and release an allocated flash device, and memory associated with it + * for other use. + * + * @note The user memory is released from use by the flash driver, but is not freed. + * + * @sa adi_fee_Open(). + */ +ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice) +{ + uint32_t dev; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + + /* Destroy the semaphore */ + SEM_DELETE(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* Remove the device handle from the list of possible device instances */ + for (dev = 0u; dev < ADI_FEE_NUM_INSTANCES; dev++) + { + if (fee_device_info[dev].hDevice == hDevice) + { + fee_device_info[dev].hDevice = NULL; + break; + } + } + + /* NVIC disables */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaIrqNum); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Register an application-defined callback function. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pfCallback A pointer to an application-supplied calllback function + * which is called to notify the application of device-related + * events. A value of NULL disables driver callbacks. + * @param [in] pCBParam An application-supplied callback parameter which will be passed + * back to the callback function. + * + * @return Status + * - #ADI_FEE_SUCCESS The callback is registered successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress and + * the callback registration is ignored. + * + * Links the user-provided callback function into the #adi_fee_SubmitBuffer() API such that + * rather than polling for buffer completion (with #adi_fee_IsBufferAvailable()) and eventually + * reacquiring the buffer (with #adi_fee_GetBuffer()), the user can simply register a callback + * function that will be called upon buffer completion with no further action needed.\n + * + * Error conditions are also passed to the callback, including DMA errors if DMA is active. Make sure + * to always check the event value passed to the callback, just as the various API return codes should + * always be checked.\n + * + * However, callbacks are always made in context of an interrupt, so applications are strongly encouraged + * to exit the callback as quickly as possible so normal interrupt processing is disrupted as little as + * possible. This is also an argument for not using callbacks at at all. + * + * @note When using callbacks to reacquire buffers, DO NOT use the #adi_fee_GetBuffer() API. The two + * methods are mutually exclusive. + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_IsBufferAvailable(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* Set the callback function and param in the device */ + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Erase the given range of (2kB) page(s) within the flash user space memory. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nPageNumStart Start page number. + * @param [in] nPageNumEnd End page number. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The page(s) is(are) cleared successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] The page(s) number(s) is(are) incorrect. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Erases entire page(s). Callers are expected to save/restore any partial page data prior + * to erasure, as needed. Translate literal flash addresses into flash start and end page + * numbers with #adi_fee_GetPageNumber(). + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_GetPageNumber(). + * @sa adi_fee_MassErase(). + */ +ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors) + +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + + uint32_t page; + +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + uint32_t nRelAddrStart = (nPageNumStart << FEE_PAGE_SHIFT); + uint32_t nRelAddrStop = (nPageNumEnd << FEE_PAGE_SHIFT); + + if ( (nPageNumStart > nPageNumEnd) + || (nRelAddrStart >= FEE_FLASH_SIZE) + || (nRelAddrStop >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif /* defined (ADI_DEBUG) */ + + for (page = nPageNumStart; page <= nPageNumEnd; page++) + { + /* Wait until not busy */ + BusyWait(hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Set the page address */ + hDevice->pDev->PAGE_ADDR0 = (page << FEE_PAGE_SHIFT); + + /* Issue a page erase command */ + result = SendCommand (hDevice, ENUM_FLCC_CMD_ERASEPAGE); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + if (result != ADI_FEE_SUCCESS) { + break; + } + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Erase the entire flash user space memory. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The flash is cleared successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * @note Do not call mass erase on or from code that is running from flash. Doing so will leave + * an indeterminate machine state. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_PageErase(). + */ +ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* Call the mass erase command */ + result = SendCommand (hDevice, ENUM_FLCC_CMD_MASSERASE); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Perform a blocking flash data write operation. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pTransaction Pointer to a user-defined control block describing the data to be transferred, containing: + * - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash. + * - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory. + * - nSize; Number of bytes to write (must be an integral multiple of 8). + * - bUseDma; Flag controlling use of DMA to perform the write. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_ALIGNMENT [D] The flash write source data pointer is misaligned. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Buffer size is not a multiple of 8-bytes (or too large for DMA). + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DEVICE_BUSY The flash controller is busy. + * - #ADI_FEE_ERR_DMA_BUS_FAULT A runtime DMA bus fault was detected. + * - #ADI_FEE_ERR_DMA_INVALID_DESCR A runtime DMA invalid descriptor was detected. + * - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR An unknown runtime DMA error was detected. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER Transfer ran out of write data unexpectedly. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Perform a blocking flash data write operation. This API does not return until the write operation is completed. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). Flash hardware errors are separate + * and distinct from DMA errors, which have separate and distinct return codes, as described above. + */ +ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* check address is 64-bit aligned and data pointer is 32-bit aligned */ + if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) ) + { + return ADI_FEE_ERR_ALIGNMENT; + } + + /* make sure size is a multiple of 8 */ + if ((pTransaction->nSize & 0x7u) != 0u) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (true == pTransaction->bUseDma) { + /* check for max DMA units (32-bit chunks, i.e., 4 bytes at a whack) */ + if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) { + return ADI_FEE_ERR_INVALID_PARAM; + } + } +#endif + + /* reset submit/get safeguard flag */ + hDevice->bSubmitCalled = false; + + /* Fill in the transfer params */ + hDevice->pNextWriteAddress = pTransaction->pWriteAddr; + hDevice->pNextReadAddress = pTransaction->pWriteData; + hDevice->nRemainingBytes = pTransaction->nSize; + hDevice->bUseDma = pTransaction->bUseDma; + + /* Initiate a transfer */ + result = InitiateTransfer (hDevice); + + /* Wait for the completed transfer */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* issue any flash DMA error status codes... */ + if (0u != hDevice->dmaError) { + return hDevice->dmaError; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + /* Check for errors in buffer write */ + if (hDevice->nRemainingBytes != 0u) { + return ADI_FEE_ERR_BUFFER_ERR; + } + + return result; +} + + +/** + * @brief Submit a non-blocking flash data write operation for background processing. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pTransaction Pointer to a user-defined control block describing the data to be transferred, containing: + * - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash. + * - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory. + * - nSize; Number of bytes to write (must be an integral multiple of 8). + * - bUseDma; Flag controlling use of DMA to perform the write. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_ALIGNMENT [D] The flash write source data pointer is misaligned. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Buffer size is not a multiple of 8-bytes (or too large for DMA). + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DEVICE_BUSY The flash controller is busy. + * - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER Transfer ran out of write data unexpectedly. + * + * Submit a flash data write transaction. This is a non-blocking function which returns immediately. + * The application may either: poll for transaction completion through the non-blocking #adi_fee_IsBufferAvailable() + * API, and/or await transaction completion through the blocking mode #adi_fee_GetBuffer() API. If an application + * callback has been registered, the application is advised of completion status through the callback. + * + * @note If using callback mode, DO NOT USE the #adi_fee_GetBuffer() API, which are mutually exclusive protocols. + * + * @sa adi_fee_IsBufferAvailable(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* check address is 64-bit aligned and data pointer is 32-bit aligned */ + if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) ) + { + return ADI_FEE_ERR_ALIGNMENT; + } + + /* make sure size is a multiple of 8 */ + if ((pTransaction->nSize & 0x7u) != 0u) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (true == pTransaction->bUseDma) { + /* check for max DMA units (32-bit channel width means 4 bytes at a whack) */ + if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) { + return ADI_FEE_ERR_INVALID_PARAM; + } + } +#endif + + /* set submit/get safeguard flag */ + hDevice->bSubmitCalled = true; + + /* Fill in the transfer params */ + hDevice->pNextWriteAddress = pTransaction->pWriteAddr; + hDevice->pNextReadAddress = pTransaction->pWriteData; + hDevice->nRemainingBytes = pTransaction->nSize; + hDevice->bUseDma = pTransaction->bUseDma; + + /* initiate a transfer */ + result = InitiateTransfer (hDevice); + + /* no pend here... just return */ + + return result; +} + + +/** + * @brief Non-blocking check if a write transaction complete. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pbCompletionState True if transfer is complete, false if not. + * + * @return Status + * - #ADI_FEE_SUCCESS The status of buffer is returned successfully. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Pointer passed is NULL. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY No matching buffer submit call found. + * + * Check if a non-blocking write transaction that was submitted via adi_fee_SubmitBuffer() is complete. + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pbCompletionState == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY; + } + + if (true == hDevice->bTransferInProgress) { + *pbCompletionState = false; + } else { + *pbCompletionState = true; + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Blocking mode call to await transaction completion. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DMA_BUS_FAULT A runtime DMA bus fault was detected. + * - #ADI_FEE_ERR_DMA_INVALID_DESCR A runtime DMA invalid descriptor was detected. + * - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR An unknown runtime DMA error was detected. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY No matching buffer submit call found. + * + * This function blocks until a previously-submitted flash write operation has completed. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_IsBufferAvailable(). + */ +ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY; + } + + /* Pend for the semaphore */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* issue any flash DMA error status codes... */ + if (0u != hDevice->dmaError) { + return hDevice->dmaError; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + /* Check for errors in buffer write or transfer still in progress */ + if ((0u != hDevice->nRemainingBytes) || (true == hDevice->bTransferInProgress)) { + return ADI_FEE_ERR_BUFFER_ERR; + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the (2kB) page number within which a flash address resides. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nAddress The flash address for which the page number is required. + * @param [in,out] pnPageNum Pointer to a variable into which the page number corresponding + * to the provided flash address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The page number is returned successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameter(s) are invalid. + * + * Translates a literal flash address into a page number for use with various page-based flash operations. + * + * @sa adi_fee_PageErase(). + * @sa adi_fee_VerifySignature(). + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_GetBlockNumber(). + * + */ +ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum) +{ +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if ( (pnPageNum == NULL) + || (nAddress >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the page number for the given flash address */ + *pnPageNum = (nAddress >> FEE_PAGE_SHIFT); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the (16kB) block number within which a flash address resides. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nAddress The flash address for which the block number is required. + * @param [in,out] pnBlockNum Pointer to a variable into which the block number corresponding + * to the provided flash address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The block number is returned successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameter(s) are invalid. + * + * Translates a literal flash address into a block number for use with setting flash write protection on a block. + * + * @sa adi_fee_WriteProtectBlock(). + * @sa adi_fee_GetPageNumber(). + */ +ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum) +{ +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if ( (pnBlockNum == NULL) + || (nAddress >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the block number */ + *pnBlockNum = (nAddress >> FEE_BLOCK_SHIFT); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Generate the CRC signature for a range of flash data page(s). This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nStartPage The lower page number of the signature range. + * @param [in] nEndPage The upper page number of the signature range. + * @param [in,out] pSigResult Pointer to a variable into which the computed signature is stored. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The signature is verified successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] The page(s) number(s) is(are) incorrect. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Compute and return a CRC over a range of contiguous whole flash memory pages(s). The computed CRC + * signature may subsequently be written into the most-significant word of the region over which the + * signature was calculated. This is done in context of enabling bootloader enforcement of CRC signature + * verification during system startup. See HRM for signature storage programming requirements and + * bootloader operation. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_GetPageNumber(). + */ +ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors) + +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if ( (pSigResult == NULL) + || (nStartPage > nEndPage) + || (nStartPage >= FEE_MAX_NUM_PAGES) + || (nEndPage >= FEE_MAX_NUM_PAGES) + ) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Wait until not busy */ + BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Set the lower and upper page */ + hDevice->pDev->PAGE_ADDR0 = nStartPage << FEE_PAGE_SHIFT; + hDevice->pDev->PAGE_ADDR1 = nEndPage << FEE_PAGE_SHIFT; + + /* Do a SIGN command */ + result = SendCommand(hDevice, ENUM_FLCC_CMD_SIGN); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* Return the signature to the application */ + if (ADI_FEE_SUCCESS == result) { + *pSigResult = hDevice->pDev->SIGNATURE; + } else { + *pSigResult = 0u; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Set write protection on an (16kB) block. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nBlockNum The block number. + * + * @return Status + * - #ADI_FEE_SUCCESS The block is write protected successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Block number is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Assert memory write-protection for specified block. Note that only entire blocks are protectable, + * with each block spanning 8 pages. + * + * @note Blocks may only be write-protected during user run-time code. Unprotecting is only + * possible with a power-on-reset or a mass erase; write-protection is not otherwise clearable. + * + * @warning Flash-based code that write-protects blocks will cause the write-protection (and data at + * time of write-protect assertion) to apparently not clear... even after a mass erase or power-on-reset. + * This apparently "stuck" write-protection results from the flash-based write-protect code running + * after reset (as usual), but still prior to the debugger halting the target through the debug + * interrupt. The debugger target halt occurs WELL AFTER the flash code has already run, thereby + * relocking the block and making it appear the write-protection was never reset. This can be difficult + * Catch-22 situation to recover from, requiring repeated hardware resets and reflashing new code that + * does not assert the write-protection. + * + * @sa adi_fee_GetBlockNumber(). + */ +ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if (nBlockNum > FEE_MAX_NUM_BLOCKS) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the write protection (by clearing the bit) for the given block */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->WRPROT, 1u << nBlockNum); + hDevice->pDev->KEY = 0u; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Sleep or awake the flash controller. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] bSleep 'true' to enable to sleep the flash device + * and 'false' to wake up the device. + * + * @return Status + * - #ADI_FEE_SUCCESS The flash controller is moved to sleep/wake + * up sate successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Places the flash controller into a low-power sleep mode - see details in Hardware Reference Manual (HRM). + * Default wakeup time is approximately 5us, and is configurable with static configuration parameter + * ADI_FEE_CFG_PARAM1_TWK in adi_flash_config.h file. + */ +ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* TODO: Check that IDLE can take the controller + * out of sleep + */ + + if (true == bSleep) { + result = SendCommand (hDevice, ENUM_FLCC_CMD_SLEEP); + } else { + result = SendCommand (hDevice, ENUM_FLCC_CMD_IDLE); + } + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + return result; +} + + +/** + * @brief Forcefully ABORT an ongoing flash operation. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * + * @return Statuus + * - #ADI_FEE_SUCCESS The command is successfully aborted. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * @warning Use this command sparingly and as a last resort to satisfy critical + * time-sensitive events. Aborting any flash command results in prematurely ending the + * current flash access and may result in corrupted flash data. + * + * @sa adi_fee_GetAbortAddr(). + */ +ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + /* Issue the command (abort is keyed) directly */ + /* (avoid SendCommand() here, as it does a busy wait, which may not clear if we're in a recovery mode) */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + hDevice->pDev->CMD = ENUM_FLCC_CMD_ABORT; + hDevice->pDev->KEY = 0u; + + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the address of recently aborted write command. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnAddress Pointer to which the address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The abort address is retrieved successfully + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid + * - #ADI_FEE_ERR_INVALID_PARAM [D] Pointer passed is NULL + * + * Users may use this result to determine the flash location(s) affected by a write abort command. + * Subsequent flash commands invalidate the write abort address register. + * + * + * @sa adi_fee_Abort(). + */ +ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnAddress == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Write the address of the last write abort to the pointer + * supplied by the application + */ + *pnAddress = hDevice->pDev->WR_ABORT_ADDR; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Configure ECC start page and enablement. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nStartPage The start page for which ECC will be performed. + * @param [in] bInfoECCEnable Info space ECC enable: + * - 'true' to enable info space ECC, or + * - 'false' to disable info space ECC. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC was configured successfully + * - #ADI_FEE_ERR_INVALID_PARAM [D] Start page is invalid + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @warning This API leaves user space ECC disabled. Use #adi_fee_EnableECC() to manage ECC enable/disable. + * + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable) +{ + uint32_t nRelAddress = nStartPage << FEE_PAGE_SHIFT; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if (nStartPage >= FEE_MAX_NUM_PAGES) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Clear the ECC config bits */ + CLR_BITS (hDevice->pDev->ECC_CFG, (BITM_FLCC_ECC_CFG_PTR | BITM_FLCC_ECC_CFG_INFOEN)); + + /* Set the start page address in the ECC Cfg register */ + hDevice->pDev->ECC_CFG |= (nRelAddress & BITM_FLCC_ECC_CFG_PTR); + + /* enable ECC on info space... if requested */ + if (true == bInfoECCEnable) { + SET_BITS (hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_INFOEN); + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Enable/Disable user space ECC for the device. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] bEnable User space ECC enable: + * - 'true' to enable user space ECC, or + * - 'false' to disable user space ECC. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC is enabled/disabled successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Manage enablement of user space ECC function. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* manage flash ECC enable */ + if (true == bEnable) { + SET_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN); + } else { + CLR_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN); + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Confifure ECC event response. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] eEvent ECC event - Either error or correction event. + * @param [in] eResponse The response to the eEvent - One of none, bus error, or interrupt. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC events are configured successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Configures two major aspects of ECC event response: + * - On ECC (2-bit) Error events, generate one of: no response, bus error, or flash interrupt. + * - On ECC (1-bit) Correction events, generate one of: no response, bus error, or flash interrupt. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse) + +{ + uint32_t nBitMask; + int32_t nBitPos; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* Check the function parameters */ + if ( ( (eEvent != ADI_FEE_ECC_EVENT_TYPE_ERROR) + && (eEvent != ADI_FEE_ECC_EVENT_TYPE_CORRECT)) + + || ( (eResponse != ADI_FEE_ECC_RESPONSE_NONE) + && (eResponse != ADI_FEE_ECC_RESPONSE_BUS_ERROR) + && (eResponse != ADI_FEE_ECC_RESPONSE_IRQ)) + ) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Select the correct bit mask and bit pos for the event type */ + if (eEvent == ADI_FEE_ECC_EVENT_TYPE_ERROR) { + nBitMask = BITM_FLCC_IEN_ECC_ERROR; + nBitPos = BITP_FLCC_IEN_ECC_ERROR; + } +#if defined (__ADUCM4x50__) + else { + nBitMask = BITM_FLCC_IEN_ECC_CORRECT; + nBitPos = BITP_FLCC_IEN_ECC_CORRECT; + } +#endif + + /* clear the bits */ + CLR_BITS (hDevice->pDev->IEN, nBitMask); + + /* set the response */ + SET_BITS (hDevice->pDev->IEN, ((uint32_t)eResponse) << nBitPos); + + return ADI_FEE_SUCCESS; +} + + +/** + * `@brief Get the address for which the ECC event is detected. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnAddress Pointer to which the address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC error address is retrieved successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * + * Returns the address of the first ECC error or correction event to generate an + * interrupt since the last time ECC status bits were cleared (or since reset). + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnAddress == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Write the address of the last ECC error/correction */ + *pnAddress = hDevice->pDev->ECC_ADDR; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the number of 1-bit error corrections. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnNumCorrections Pointer to which the number of corrections are written. + * + * @return Status + * - #ADI_FEE_SUCCESS The number of ECC corrections are successfully retrieved. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * + * See HRM for details on how current ECC configuration affects this reporting. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + */ +ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections) +{ + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnNumCorrections == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Get the number of ECC Error corrections */ + *pnNumCorrections = (hDevice->pDev->STAT & BITM_FLCC_STAT_ECCERRCNT) >> BITP_FLCC_STAT_ECCERRCNT; + + return ADI_FEE_SUCCESS; +} + + +/*======== L O C A L F U N C T I O N D E F I N I T I O N S ========*/ + + +/* Send a command to the flash controller... bot don't block on it... + */ +static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd) +{ + /* Wait for the flash to be free */ + BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Clear the command completion status bit + * by acknowledging it + */ + hDevice->pDev->STAT = BITM_FLCC_STAT_CMDCOMP; + + /* Enable command-complete and command-fail interrupt */ + SET_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* Issue the command (most commands are keyed) */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + hDevice->pDev->CMD = cmd; + hDevice->pDev->KEY = 0u; + + return ADI_FEE_SUCCESS; +} + + +static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice) +{ + + /* use PIO interrupt mode in non-burst-mode (burst-mode only spans 256-bytes). + Initiate the 1st write here, then let the interrupt handler feed + the remaining data as we process "almost-complete" interrupts. + */ + + /* write the 1st 64-bits of data */ + if (0u != hDevice->nRemainingBytes) { + + /* enable command interrupts */ + SET_BITS (hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* set initial write address*/ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + hDevice->pNextWriteAddress += 2; + + /* set key-hole data registers */ + hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->nRemainingBytes -= sizeof(uint64_t); + + /* write the command register which launches the burst write */ + hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE; + + } else { + return ADI_FEE_ERR_NO_DATA_TO_TRANSFER; + } + + return ADI_FEE_SUCCESS; +} + + +/* DMA Transfer to FIFO */ +static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice) +{ + ADI_DCC_TypeDef* pCCD = pPrimaryCCD; /* pointer to primary DMA descriptor array */ + + if (0u != hDevice->nRemainingBytes) { + + /* local channel number */ + uint16_t chan = hDevice->pDevInfo->dmaChanNum; + + /* disable endpointer decrement modes */ + pADI_DMA0->SRCADDR_CLR = 1u << chan; + pADI_DMA0->DSTADDR_CLR = 1u << chan; + + /* enable the channel */ + pADI_DMA0->EN_SET = 1u << chan; + + /* allow flash to request DMA service */ + pADI_DMA0->RMSK_CLR = 1u << chan; + + /* activate primary descriptor */ + pADI_DMA0->ALT_CLR = 1u << chan; + + /* Note: DMA width is 32-bit for the flash controller, but flash writes require + 64-bit writes at a whack. Set DMA R_Power (bus rearbitration rate) to two so + we get two uninterrupted 32-bit DMA writes to the flash with each DMA transfer. + */ + + /* set DMA source endpoint */ + pCCD += chan; /* offset descriptor pointer to flash channel */ + pCCD->DMASRCEND = (uint32_t)hDevice->pNextReadAddress + hDevice->nRemainingBytes - sizeof(uint32_t); + + /* set DMA destination endpoint (no increment) */ + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->KH_DATA1; + + /* set the initial write address */ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + + /* set the DMA Control Data Configuration register */ + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_2 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((hDevice->nRemainingBytes/sizeof(uint32_t) - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + /* set auto-increment and DMA enable bits, launching transder */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + SET_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + } else { + return ADI_FEE_ERR_NO_DATA_TO_TRANSFER; + } + + return ADI_FEE_SUCCESS; +} + + +/* Initiate transfer */ +static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + + /* If a transfer is in progress or if the pending buffers are empty + * the return as there is nothing to be done now + */ + if (true == hDevice->bTransferInProgress) + { + return ADI_FEE_ERR_DEVICE_BUSY; + } + + /* Wait for the flash to not be busy */ + BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY); + + /* clear internal errors */ + hDevice->feeError = 0u; + hDevice->dmaError = ADI_FEE_SUCCESS; + + /* Set the bool variable to signify that a transfer is in progress */ + hDevice->bTransferInProgress = true; + + /* clear any command interrupt enables */ + CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* clear any dangeling command-related status */ + hDevice->pDev->STAT = BITM_FLCC_STAT_WRALCOMP | BITM_FLCC_STAT_CMDCOMP | BITM_FLCC_STAT_CMDFAIL; + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* Call the corresponding Transfer functions */ + if (true == hDevice->bUseDma) { + result = InitiateDmaTransfer(hDevice); + } else { + result = InitiatePioTransfer(hDevice); + } + + return result; +} + + +/* hide the interrupt handlers from DoxyGen */ +/*! \cond PRIVATE */ + +/* Flash PIO interrupt handler */ +void Flash0_Int_Handler(void) +{ + ISR_PROLOG(); + + /* post flag */ + bool bPost = false; + bool bError = false; + + /* recover the driver handle */ + ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice; + +#ifdef ADI_DEBUG + /* Return if the device is not opened - spurious interrupts */ + if (hDevice == NULL) { + return; + } +#endif + + /* update status cache and clear it right away on the controller */ + hDevice->FlashStatusCopy = hDevice->pDev->STAT; + hDevice->pDev->STAT = hDevice->FlashStatusCopy; + + /* check for flash device errors */ + hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy); + if (0u != hDevice->feeError) { + bError = true; + } + + /* if no errors */ + if (false == bError) { + + if (0u != (BITM_FLCC_STAT_WRALCOMP & hDevice->FlashStatusCopy)) { + + /* write-almost-complete */ + + /* if more data to write... */ + if (0u != hDevice->nRemainingBytes) { + + /* set next write the address */ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + hDevice->pNextWriteAddress += 2; + + /* set next key-hole data */ + hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->nRemainingBytes -= sizeof(uint64_t); + + /* initiate next write */ + hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE; + + } else { + + /* no more data to write... + wait for current write-almost-complete status to transition to not busy */ + BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY); + + /* set post flag */ + bPost = true; + } + + } else if (0u != (BITM_FLCC_STAT_CMDCOMP & hDevice->FlashStatusCopy)) { + + /* command-complete */ + + /* this path is for blocking-mode commands (erase, verify, abort, etc.) */ + + /* set post flag */ + bPost = true; + + } else { + /* no other interrupt types expected */ + } + } else { + /* error(s) detected... set the post flag */ + bPost = true; + } + + /* singular post */ + if (true == bPost) { + + /* clear the command interrupt enables */ + CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* mark transfer complete */ + hDevice->bTransferInProgress = false; + + /* dispatch callback (if we have one...) */ + if (0u != hDevice->pfCallback) { + if (false == bError) { + /* no error, pass success flag to callback */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL); + } else { + /* error condition, pass error flag and error status to callback */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError); + } + } + + /* post the semaphore */ + SEM_POST(hDevice); + } + + ISR_EPILOG(); +} + + +/* Flash DMA interrupt handler */ +void DMA_FLASH0_Int_Handler (void) +{ + /* rtos prologue */ + ISR_PROLOG() + ; + + /* recover the driver handle */ + ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice; + + /* update status cache and clear it right away on the controller */ + hDevice->FlashStatusCopy = hDevice->pDev->STAT; + hDevice->pDev->STAT = hDevice->FlashStatusCopy; + + /* capture any hw error status */ + hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy); + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* clear the remaining count, as it should all have gone in one swoop */ + hDevice->nRemainingBytes = 0u; + + /* mark transfer complete */ + hDevice->bTransferInProgress = false; + + /* dispatch callback (if we have one...) */ + if (0u != hDevice->pfCallback) { + + /* no errors, notify success */ + if ((0u == hDevice->feeError) && (0u == hDevice->dmaError)) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL); + + /* flash hardware error */ + } else if (0u == hDevice->feeError) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError); + + /* flash dma error */ + } else if (0u == hDevice->dmaError) { + /* DMA error */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, NULL); + } else { + /* no other cases... */ + } + } + + /* post the semaphore */ + SEM_POST(hDevice); + + ISR_EPILOG(); +} + +/*! \endcond */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_data.c new file mode 100755 index 00000000000..7d419b11f02 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_data.c @@ -0,0 +1,129 @@ +/* + ***************************************************************************** + * @file: adi_flash_data.c + * @brief: Data declaration for Flash Device Driver + * @date: $Date$ + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be consciously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FEE_DATA_C +#define ADI_FEE_DATA_C + + /*! \cond PRIVATE */ + +#include +#include "adi_flash_def.h" +#include "adi_flash_config.h" + + +/* Stores the information about the specific device */ +static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] = +{ + /* only one flash instance at this time */ + { pADI_FLCC0, /* Flash controller pointer */ + FLCC_EVT_IRQn, /* Flash PIO interrupt number */ + DMA0_CH15_DONE_IRQn, /* Flash DMA interrupt number */ + FLASH_CHANn, /* Flash DMA channel (15) number */ + NULL, /* Flash static config info */ + NULL /* Flash driver handle */ + }, +}; + + +/* build Flash Application configuration array */ +static ADI_FEE_CONFIG gConfigInfo[ADI_FEE_NUM_INSTANCES] = +{ + /* the one-and-only (so far) instance data for FEE0... */ + { +#if defined (__ADUCM4x50__) + /* ECC interrupt enable settings (IEN register) */ + ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE << BITP_FLCC_IEN_ECC_ERROR) + | (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE << BITP_FLCC_IEN_ECC_CORRECT) + ), + +#elif defined (__ADUCM302x__) + + /* ECC interrupt enable settings (IEN register) */ + ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE << BITP_FLCC_IEN_ECC_ERROR)), + +#endif + /* timing parameter settings (TIME_PARAM0 register) */ + ( (ADI_FEE_CFG_PARAM0_TNVH1 << BITP_FLCC_TIME_PARAM0_TNVH1) + | (ADI_FEE_CFG_PARAM0_TERASE << BITP_FLCC_TIME_PARAM0_TERASE) + | (ADI_FEE_CFG_PARAM0_TRCV << BITP_FLCC_TIME_PARAM0_TRCV) + | (ADI_FEE_CFG_PARAM0_TNVH << BITP_FLCC_TIME_PARAM0_TNVH) + | (ADI_FEE_CFG_PARAM0_TPROG << BITP_FLCC_TIME_PARAM0_TPROG) + | (ADI_FEE_CFG_PARAM0_TPGS << BITP_FLCC_TIME_PARAM0_TPGS) + | (ADI_FEE_CFG_PARAM0_TNVS << BITP_FLCC_TIME_PARAM0_TNVS) + | (ADI_FEE_CFG_PARAM0_CLKDIV << BITP_FLCC_TIME_PARAM0_DIVREFCLK) + ), +#if defined (__ADUCM4x50__) + /* more timing parameter settings (TIME_PARAM1 register) */ + ( (ADI_FEE_CFG_PARAM1_WAITESTATES << BITP_FLCC_TIME_PARAM1_WAITSTATES) + | (ADI_FEE_CFG_PARAM1_TWK << BITP_FLCC_TIME_PARAM1_TWK) + ), + +#elif defined (__ADUCM302x__) + /* more timing parameter settings (TIME_PARAM1 register) */ + ((ADI_FEE_CFG_PARAM1_TWK << BITP_FLCC_TIME_PARAM1_TWK)), + +#endif + /* system interrupt abort enables (ABORT_EN_XX registers) */ + (ADI_FEE_CFG_ABORT_EN_LO), + (ADI_FEE_CFG_ABORT_EN_HI), + + /* ECC configuration register settings (ECC_CFG register) */ + (((ADI_FEE_CFG_ECC_START_PAGE << FEE_PAGE_SHIFT) & BITM_FLCC_ECC_CFG_PTR) +#if (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE == 1u) + | (BITM_FLCC_ECC_CFG_INFOEN) +#endif +#if (ADI_FEE_CFG_ENABLE_ECC == 1u) + | (BITM_FLCC_ECC_CFG_EN) +#endif + ) + } /* end device 0 settings */ +}; + +/*! \endcond */ + + +#endif /* ADI_FEE_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_def.h new file mode 100755 index 00000000000..13a58facae6 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/flash/adi_flash_def.h @@ -0,0 +1,201 @@ +/*! + ***************************************************************************** + @file: adi_flash_def.h + @brief: Internal Flash device driver definitions and macros + @date: $Date: 2014-11-28 01:48:03 -0500 (Fri, 28 Nov 2014) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FLASH_DEF_H +#define ADI_FLASH_DEF_H + +/*! \cond PRIVATE */ + +#include +#include + +#include + +/* fixed number of flash controllers */ +#define ADI_FEE_NUM_INSTANCES (1u) + +#if defined (__ADUCM4x50__) +/* STATUS register error mask */ +#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_ACCESS_MODE \ + | BITM_FLCC_STAT_CACHESRAMPERR \ + | BITM_FLCC_STAT_ECCDCODE \ + | BITM_FLCC_STAT_ECCINFOSIGN \ + | BITM_FLCC_STAT_SIGNERR \ + | BITM_FLCC_STAT_OVERLAP \ + | BITM_FLCC_STAT_ECCRDERR \ + | BITM_FLCC_STAT_ECCERRCMD \ + | BITM_FLCC_STAT_SLEEPING \ + | BITM_FLCC_STAT_CMDFAIL) +#elif defined (__ADUCM302x__) +#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_CACHESRAMPERR \ + | BITM_FLCC_STAT_ECCDCODE \ + | BITM_FLCC_STAT_ECCINFOSIGN \ + | BITM_FLCC_STAT_SIGNERR \ + | BITM_FLCC_STAT_OVERLAP \ + | BITM_FLCC_STAT_ECCRDERR \ + | BITM_FLCC_STAT_ECCERRCMD \ + | BITM_FLCC_STAT_SLEEPING \ + | BITM_FLCC_STAT_CMDFAIL) +#endif + +#if defined(__ECC__) +#define ALIGN +#define ALIGN4 _Pragma("align(4)") +#elif defined(__ICCARM__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#elif defined (__GNUC__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#endif + +/* Flash Size and Page/Block macros: + 512kB total user space, broken up as + 256-pages, 2kB/page + 32-blocks, 16kB/block + 8 pages/block +*/ +#if defined (__ADUCM4x50__) +#define FEE_FLASH_SIZE (0x80000u) /* 512kB total */ +#define FEE_BLOCK_SHIFT (14u) /* 16kB block size */ + +#elif defined (__ADUCM302x__) +#define FEE_FLASH_SIZE (0x40000u) /* 256kB total */ +#define FEE_BLOCK_SHIFT (13u) /* 8kB block size */ +#else +#error Flash driver is not ported to this processor +#endif + +#define FEE_PAGE_SHIFT (11u) /* 2kB page size */ +#define FEE_MAX_NUM_PAGES (FEE_FLASH_SIZE >> FEE_PAGE_SHIFT) /* max number of pages */ +#define FEE_MAX_NUM_BLOCKS (FEE_FLASH_SIZE >> FEE_BLOCK_SHIFT) /* max number of blocks (32) */ + +#if (ADI_FEE_CFG_ECC_START_PAGE >= FEE_MAX_NUM_PAGES) +#error "ADI_FEE_CFG_ECC_START_PAGE range is invalid" +#endif + + +/* INTERNAL DRIVER STATIC FUNCTION PROTOTYPES */ + +/* Send a command to the flash controller, but does no pend on it... */ +static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd); + +/* generic transfer initiator... dispatches to InitiatePioTransfer() or InitiateDmaTransfer() */ +static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice); + +/* PIO initiator */ +static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice); + +/* DMA initiator */ +static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice); + +/* interrupt handlers */ +void Flash0_Int_Handler(void); +void DMA_FLASH0_Int_Handler (void); + +/* INTERNAL DRIVER DATATYPES */ + +/* + ***************************************************************************** + * FEE Configuration structure. + *****************************************************************************/ +typedef struct __ADI_FEE_CONFIG { + uint32_t eccIrqEnables; /* ECC interrupt enables. */ + uint32_t param0; /* TIME_PARAM0 register. */ + uint32_t param1; /* TIME_PARAM1 register. */ + uint32_t abortEnableLo; /* Lower interrupt abort enables (IRQs 0-31). */ + uint32_t abortEnableHi; /* Upper interrupt abort enables (IRQs 32-63.) */ + uint32_t eccConfig; /* ECC_CFG register. */ +} ADI_FEE_CONFIG; + + +/* Flash physical device instance data */ +typedef struct __ADI_FEE_DEVICE_INFO { + + ADI_FLCC_TypeDef *pDev; /* Pointer to the physical controller. */ + IRQn_Type pioIrqNum; /* The flash controller PIO interrupt number. */ + IRQn_Type dmaIrqNum; /* The flash controller DMA interrupt number. */ + DMA_CHANn_TypeDef dmaChanNum; /* The flash controller DMA channel number. */ + ADI_FEE_CONFIG *pConfig; /* Pointer to user config info. */ + ADI_FEE_HANDLE hDevice; /* Pointer the device memory (supplied by the application). */ + +} ADI_FEE_DEVICE_INFO; + + +/* Flash driver instance data structure */ +typedef struct __ADI_FEE_DEV_DATA_TYPE { + + /* make sure to synchronize ANY size changes with ADI_FLASH_MEMORY_SIZE macro in adi_flash.h */ + + /* NOTE: "volatile" storage class on all interrupt-modified valuables */ + + /* device attributes */ + ADI_FLCC_TypeDef *pDev; /* Pointer top physical flash controller. */ + ADI_FEE_DEVICE_INFO *pDevInfo; /* Pointer to hardware device attributes. */ + + /* callback info */ + ADI_CALLBACK pfCallback; /* Registered callback function address. */ + void *pCBParam; /* Registered callback user parameter. */ + + /* internal driver state variables */ + bool bUseDma; /* DMA control flag (from user). */ + bool bSubmitCalled; /* Flag to identify if a buffer was "submitted". */ + volatile uint32_t FlashStatusCopy; /* Clop of latest flash status register. */ + volatile uint32_t feeError; /* Flash error collector. */ + volatile ADI_FEE_RESULT dmaError; /* DMA error collector. */ + volatile bool bTransferInProgress; /* Flag indicating if a transfer is in progress. */ + + /* data info */ + volatile uint32_t *pNextWriteAddress; /* Pointer to next write data in flash space. */ + volatile uint32_t *pNextReadAddress; /* Pointer to next read data in user buffer. */ + volatile uint32_t nRemainingBytes; /* Number of remaining bytes still to transfer. */ + + SEM_VAR_DECLR /* Blocking object: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos. */ + +} ADI_FEE_DEV_DATA_TYPE; + +/*! \endcond */ + +#endif /* ADI_FLASH_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio.c new file mode 100755 index 00000000000..a54c0b2b0be --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio.c @@ -0,0 +1,989 @@ +/* + ***************************************************************************** + @file: adi_gpio.c + @brief: GPIO device driver implementation. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "adi_gpio_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm140 +#endif /* __ICCARM__ */ + +/* Debug function declarations */ +#ifdef ADI_DEBUG +static bool ArePinsValid (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); /*!< tests for pins validity */ +#endif /* ADI_DEBUG */ + + +static void CommonInterruptHandler (const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq); +void GPIO_A_Int_Handler(void); +void GPIO_B_Int_Handler(void); + +/*========== D A T A ==========*/ +static ADI_GPIO_DRIVER adi_gpio_Device = +{ + { + pADI_GPIO0, /* port 0 base address */ + pADI_GPIO1, /* port 1 base address */ + pADI_GPIO2, /* port 2 base address */ +#if defined(__ADUCM4x50__) + pADI_GPIO3, /* port 3 base address */ +#endif /* __ADUCM4x50__ */ + }, + + NULL +}; +/*! \endcond */ + +/*! \addtogroup GPIO_Driver GPIO Driver + * @{ + + @brief GPIO port and pin identifiers + @note The application must include drivers/gpio/adi_gpio.h to use this driver + @details The documented macros can be passed to the following functions: + - adi_gpio_OutputEnable() + - adi_gpio_PullUpEnable() + - adi_gpio_SetHigh() + - adi_gpio_SetLow() + - adi_gpio_Toggle() + - adi_gpio_SetData() + - adi_gpio_GetData() + + To control a single GPIO, these macros can be passed to the functions one + at a time. For example, to set the GPIO on port 2, pin 4 to a logical high + level, the following is used: + + 
+      adi_gpio_SetHigh(ADI_GPIO_PORT2, ADI_GPIO_PIN_4)
+
+ + Multiple GPIOs, so long as they reside on the same port, can be controlled + simultaneously. These macros can be OR-ed together and passed to the + functions. For example, to set the GPIOs on port 2, pins 3, 4 and 7 to + a logical low level, the following is used: + + 
+      adi_gpio_SetLow(ADI_GPIO_PORT2, ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7)
+
+ + For the sensing, or adi_gpio_Getxxx, functions, the passed pValue parameter is written with + a packed value containing the status of the requested GPIO pins on the given port. + + If information is required for a single pin, return value can be directly used + For example to see if pin 4 on port 2 has the pull up enabled, the following is used: + adi_gpio_GetData(ADI_GPIO_PORT2, ADI_GPIO_PIN_4, &pValue) + pValue will contain the required information. + + If information is required for multiple pins, following method is required: + 
+        adi_gpio_GetData(ADI_GPIO_PORT2, (ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7), &pValue)
+
+ To test if pin 4 on port 2 has pull up enabled, the following is used: + 
+        if   (pValue & ADI_GPIO_PIN_4) {
+                    the pull up is enabled for pin 4 on port 2
+        } else {
+                    the pull up is disabled for pin 4 on port 2
+        }
+
+ + */ + +/*! + @brief Initializes the GPIO functions. + + @details This function initializes the GPIO driver. This function should be called before calling any of the GPIO + driver APIs. + + @param[in] pMemory Pointer to the memory required for the driver to operate. + The size of the memory should be at least #ADI_GPIO_MEMORY_SIZE bytes. + + @param[in] MemorySize Size of the memory (in bytes) passed in pMemory parameter. + + @return Status + - ADI_GPIO_SUCCESS If successfully initialized the GPIO driver. + - ADI_GPIO_NULL_PARAMETER [D] If the given pointer to the driver memory is pointing to NULL. + - ADI_GPIO_INVALID_MEMORY_SIZE [D] If the given memory size is not sufficient to operate the driver. + + @note This function clears memory reserved for managing the callback function when it is called + for the first time. It is expected from user to call "adi_gpio_UnInit" function when the GPIO service is no longer required. + + @sa adi_gpio_UnInit +*/ +ADI_GPIO_RESULT adi_gpio_Init( + void* const pMemory, + uint32_t const MemorySize +) +{ + +#ifdef ADI_DEBUG + /* Verify the given memory pointer */ + if(NULL == pMemory) + { + return ADI_GPIO_NULL_PARAMETER; + } + /* Check if the memory size is sufficient to operate the driver */ + if(MemorySize < ADI_GPIO_MEMORY_SIZE) + { + return ADI_GPIO_INVALID_MEMORY_SIZE; + } + assert(ADI_GPIO_MEMORY_SIZE == sizeof(ADI_GPIO_DEV_DATA)); +#endif + + /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */ + if (NULL == adi_gpio_Device.pData) + { + uint32_t i; + + adi_gpio_Device.pData = (ADI_GPIO_DEV_DATA*)pMemory; + + /* Initialize the callback table */ + for (i = 0u; i < ADI_GPIO_NUM_INTERRUPTS; i++) + { + adi_gpio_Device.pData->CallbackTable[i].pfCallback = NULL; + adi_gpio_Device.pData->CallbackTable[i].pCBParam = NULL; + } + + /* Enable the group interrupts */ + NVIC_EnableIRQ(SYS_GPIO_INTA_IRQn); + NVIC_EnableIRQ(SYS_GPIO_INTB_IRQn); + } + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Un-initialize the GPIO driver. + + @details Terminates the GPIO functions, leaving everything unchanged. + + @return Status + - #ADI_GPIO_SUCCESS if successfully uninitialized + - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized + + @sa adi_gpio_Init +*/ +ADI_GPIO_RESULT adi_gpio_UnInit(void) +{ + +#ifdef ADI_DEBUG + /* IF (not initialized) */ + if (NULL == adi_gpio_Device.pData) + { + /* return error if not initialized */ + return (ADI_GPIO_NOT_INITIALIZED); + } +#endif + + /* Disable the group interrupts */ + NVIC_DisableIRQ(SYS_GPIO_INTA_IRQn); + NVIC_DisableIRQ(SYS_GPIO_INTB_IRQn); + + /* Clear the data pointer */ + adi_gpio_Device.pData = NULL; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Group the pins for the given group interrupt. + + @details Group the given pins for the Group A/B interrupt. + Applications can register/unregister a callback using the #adi_gpio_RegisterCallback API + to get a notification when the group interrupt occurs. + + @param[in] Port GPIO port number to be operated on. + @param[in] eIrq Interrupt (Group A/B) to which the pin(s) are to be grouped. + @param[in] Pins The GPIO pins which needs to be grouped. + Pin bits that are set enable the interrupt for the group A/B. + Pin bits that are clear disable the interrupt for the group A/B. + @return Status + - #ADI_GPIO_SUCCESS If successfully grouped the given pins. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver is not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] The given pins are invalid. + + @sa adi_gpio_RegisterCallback + @sa adi_gpio_SetGroupInterruptPolarity +*/ +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins(const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + switch (eIrq) + { + case SYS_GPIO_INTA_IRQn: + pPort->IENA = Pins; + break; + case SYS_GPIO_INTB_IRQn: + pPort->IENB = Pins; + break; + default: + break; /* This shall never reach */ + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + + + + + + + + + +/*! + @brief Set the interrupt polarity for the given pins. + + @details Sets the interrupt polarity for the given pins for the given port. + When the corresponding bit is set an interrupt is generated when the pin transitions from low-to-high. When the corresponding bit is cleared an interrupt is generated when the pin transitions from high-to-low. + + @param[in] Port GPIO port number to be operated on. + @param[in] Pins Pins whose polarity to be set. + + @return Status + - #ADI_GPIO_SUCCESS If successfully set the polarity. + - #ADI_GPIO_NOT_INITIALIZED [D] If not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_RegisterCallback + @sa adi_gpio_SetGroupInterruptPins +*/ +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + pPort->POL = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Output Drivers for GPIO Pin(s) + + @details Enables/disables the output drivers for the given GPIO pin(s) on + the given port. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[in] bFlag Boolean value describing the action to be taken + - true enables the output driver + - false disables the output driver + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_OutputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + /* enable output */ + pPort->OEN |= Pins; + } else + { + /* disable output */ + pPort->OEN &= (uint16_t)~Pins; + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Input Drivers for GPIO Pin(s) + + @details Enables/disables the input drivers for the given GPIO pin(s) on + the given port. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @param[in] bFlag Boolean value describing the action to be taken + - true enables the input driver + - false disables the input driver + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + /* enable input */ + pPort->IEN |= Pins; + } else + { + /* disable input */ + pPort->IEN &= (uint16_t)~Pins; + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Pull-Up for GPIO Pin(s) + + @details Enables/disables the internal pull-up for the given GPIO pin(s) on + the given port. API simply enables/disables whatever the hard-wired + pulls (up/down) are. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[in] bFlag Boolean value describing the action to be taken + - true enables the pull-up + - false disables the pull-up + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + pPort->PE |= Pins; + } else + { + pPort->PE &= (uint16_t)(~Pins); + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + +/*! + + @brief Sets the Given GPIO pin(s) to a Logical High Level + + @details Sets the given GPIO pin(s) on the given port to a logical high + level. + + @param[in] Port GPIO port whose pins need to be set to logical high level. + @param[in] Pins One or more GPIO pins to be set to logical high. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetHigh(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the given GPIOs high */ + pPort->SET = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Sets the Given GPIO pin(s) to a Logical Low Level + + @details Sets the given GPIO pin(s) on the given port to a logical low + level. + + @param[in] Port The GPIO port whose pins need to be set to logical low level. + @param[in] Pins One or more GPIO pins to be whose logic level to be set. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetLow(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the given GPIOs low */ + pPort->CLR = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Toggles the Logical Level of the Given GPIO pin(s) + + @details Toggles the logical level of the given GPIO pin(s) on the given port. + If a given GPIO pin is at a logical low level, this function will + change the level to a logical high value. If a given GPIO pin is + at a logical high level, this function will change the level to a + logical low value. + + @param[in] Port The GPIO port whose pins to be toggled. + @param[in] Pins The GPIO pins whose logic level to be toggled. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_Toggle(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* toggle the given GPIOs */ + pPort->TGL = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Sets the logic level of all GPIO pins on the given port to + a given logic level. + + @details Sets the logic level of all the GPIO pins on the given port to the + given value. + + @param[in] Port The GPIO port whose pins logic level to be set. + @param[in] Pins The GPIO pins whose logic level to be set high. All other + GPIO pins on the port will be set to a logical low level. + For example, to set pins 0 and 1 to a logical high level and + all other pins to a logical low level, this parameter should + be passed as #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_1. + + @return Status + - #ADI_GPIO_SUCCESS If successfully set the given data. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetData(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the GPIOs as directed */ + pPort->OUT = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Gets/Senses the input level of all GPIO Pins on the given port. + + @details Gets the level of all GPIO input pins on the given port. + + @param[in] Port The GPIO port whose input level to be sensed. + @param[in] Pins The GPIO pins to be sensed. To sense a single GPIO pin, a single + GPIO value is passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[out] pValue The passed pValue parameter is written with a packed value containing + the status of all the requested GPIO pins on the given port. + + To get the status of a single GPIO pin, return value can be directly used. + For example to see if pin 4 on port 2 is a logical high level, the following is used: + 
+        adi_gpio_GetData(#ADI_GPIO_PORT2, #ADI_GPIO_PIN_4, &pValue)
+
+ pValue will contain the required information. + + If information is required for multiple pins, following method is required: + 
+        adi_gpio_GetData(#ADI_GPIO_PORT2, (#ADI_GPIO_PIN_3 | #ADI_GPIO_PIN_4 | #ADI_GPIO_PIN_7), &pValue)
+
+ + To test if pin 4 on port 2 is a logical high level, the following is used: + 
+        if  (pValue & ADI_GPIO_PIN_4) {
+            pin 4 on port 2 is a logical high value
+        } else {
+            pin 4 on port 2 is a logical low value
+        }
+
+ + @return Status + - #ADI_GPIO_SUCCESS If successfully sensed the input pins. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData +*/ +ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* return the status of the GPIOs */ + *pValue = (pPort->IN) & Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Register or unregister an application callback function for group (A/B) interrupts. + + @details Applications may register a callback function that will be called when a + GPIO group (A/B) interrupt occurs. + + The driver dispatches calls to registered callback functions when the + properly configured pin(s) latches an external interrupt input on the GPIO + pin(s). The callback is dispatched with the following parameters, respectively: + - application-provided callback parameter (\a pCBParam), + - The GPIO Port, + - The GPIO Pins. + + @param[in] eIrq The interrupt for which the callback is being registered. + @param[in] pfCallback Pointer to the callback function. This can be passed as NULL to + unregister the callback. + @param[in] pCBParam Callback parameter which will be passed back to the application + when the callback is called.. + + @return Status + - #ADI_GPIO_SUCCESS if successfully registered the callback. + - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized + - #ADI_GPIO_INVALID_INTERRUPT [D] if interrupt ID is invalid + + @sa adi_gpio_SetGroupInterruptPolarity +*/ +ADI_GPIO_RESULT adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ + uint16_t index = 0u; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } +#endif + + index = (uint16_t)eIrq - (uint16_t)SYS_GPIO_INTA_IRQn + ADI_GPIO_IRQ_GROUPA_INDEX; + + ADI_ENTER_CRITICAL_REGION(); + + adi_gpio_Device.pData->CallbackTable[index].pfCallback = pfCallback; + adi_gpio_Device.pData->CallbackTable[index].pCBParam = pCBParam; + + ADI_EXIT_CRITICAL_REGION(); + + /* return the status */ + return (ADI_GPIO_SUCCESS); +} + + + +/*@}*/ + +/*! \cond PRIVATE */ +/* All of the following is excluded from the doxygen output... */ + +/* Common group (A/B) interrupt handler */ +static void CommonInterruptHandler(const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq) +{ + ADI_GPIO_PORT Port; + ADI_GPIO_TypeDef *pPort; + ADI_GPIO_DATA Pins; + ADI_GPIO_DATA nIntEnabledPins; + + ADI_GPIO_CALLBACK_INFO *pCallbackInfo = &adi_gpio_Device.pData->CallbackTable[index]; + + /* Loop over all the ports. */ + for(Port=ADI_GPIO_PORT0; PortIENA; + } + else /* Is the interrupt is for GROUP B */ + { + nIntEnabledPins = pPort->IENB; + } + + /* Clear only required interrupts */ + Pins = ((pPort->INT) & nIntEnabledPins); + pPort->INT = Pins; + + /* params list is: application-registered cbParam, Port number, and interrupt status */ + if((pCallbackInfo->pfCallback != NULL) && (Pins != 0u)) + { + pCallbackInfo->pfCallback (pCallbackInfo->pCBParam, (uint32_t)Port, &Pins); + } + } +} + +/* Interrupt A handler */ +void GPIO_A_Int_Handler(void) +{ + ISR_PROLOG() + CommonInterruptHandler(ADI_GPIO_IRQ_GROUPA_INDEX, SYS_GPIO_INTA_IRQn); + ISR_EPILOG() +} + +/* Interrupt B handler */ +void GPIO_B_Int_Handler (void) +{ + ISR_PROLOG() + CommonInterruptHandler(ADI_GPIO_IRQ_GROUPB_INDEX, SYS_GPIO_INTB_IRQn); + ISR_EPILOG() +} + +#ifdef ADI_DEBUG + + +/*! + @brief Tests a Pins Parameter for Validity + + @details A debug function that checks a Pins parameter for validity + + @param[in] Pins Logical OR-ing of one or more ADI_GPIO_PIN_x values + + @return Status + - true the Pins value contains valid data + - false the Pins value contains invalid data +*/ +static bool ArePinsValid(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + uint32_t PinValid = 0u; + + /* test for a valid pin */ + switch (Port) + { + case ADI_GPIO_PORT0: + PinValid = ~ADI_GPIO_PORT0_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT1: + PinValid = ~ADI_GPIO_PORT1_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT2: + PinValid = ~ADI_GPIO_PORT2_PIN_AVL & Pins; + break; +#if defined(__ADUCM4x50__) + case ADI_GPIO_PORT3: + PinValid = ~ADI_GPIO_PORT3_PIN_AVL & Pins; + break; +#endif /* __ADUCM4x50__ */ + default: + break; + } + + if (PinValid == 0u) + { + return true; + } + else + { + return false; + } +} +#endif /* ADI_DEBUG */ + +/*! \endcond */ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio_def.h new file mode 100755 index 00000000000..90282625df8 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/gpio/adi_gpio_def.h @@ -0,0 +1,94 @@ +/*! + ***************************************************************************** + * @file: adi_gpio_def.h + * @brief: GPIO Device Driver definition + ***************************************************************************** +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_GPIO_DEF_H +#define ADI_GPIO_DEF_H +/*! \cond PRIVATE */ + + +/*! local enum for callback table indexing */ +typedef enum +{ + /* Group interrupts */ + ADI_GPIO_IRQ_GROUPA_INDEX = (0x0), /*!< GroupA interrupt index. */ + ADI_GPIO_IRQ_GROUPB_INDEX = (0x1), /*!< GroupB interrupt index. */ + + ADI_GPIO_NUM_INTERRUPTS = (0x2), /*!< Number of GPIO interrupts */ + +} ADI_GPIO_IRQ_INDEX; + + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_GPIO_CALLBACK_INFO +{ + ADI_CALLBACK pfCallback; /*!< Callback function pointer */ + void *pCBParam; /*!< Callback parameter */ +} ADI_GPIO_CALLBACK_INFO; + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_GPIO_DEV_DATA +{ + ADI_GPIO_CALLBACK_INFO CallbackTable[ADI_GPIO_NUM_INTERRUPTS]; /*!< Callback Info for External interrupts */ +} ADI_GPIO_DEV_DATA; + +/*! \struct ADI_GPIO_DEVICE + + GPIO instance data + + This structure contains the "state" information for the + instance of the device. For GPIO there is only one + of these objects. +*/ +typedef struct _ADI_GPIO_DRIVER_STRUCT +{ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS]; /*!< GPIO Ports Register base */ + ADI_GPIO_DEV_DATA *pData; /*!< Pointer to device data */ +} ADI_GPIO_DRIVER_STRUCT; + + +/* alias for the actual device structure */ +typedef ADI_GPIO_DRIVER_STRUCT ADI_GPIO_DRIVER; + +/*! \endcond */ +#endif /* ADI_GPIO_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c.c new file mode 100755 index 00000000000..6319177d18c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c.c @@ -0,0 +1,1192 @@ +/*! ***************************************************************************** + * @file: adi_i2c.c + * @brief: I2C device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This file contains the I2C device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup I2C_Driver I2C Driver + * @{ + * @brief Inter-Integrated Circuit (I2C) Driver + * @details The I2C Master device driver manages the on-chip I2C hardware to + * control the external two-wire I2C Bus interface, allowing communication with + * multiple I2C slave devices through the I2C slave device addressing scheme. + * @note The application must include drivers/i2c/adi_i2c.h to use this driver + */ + + /*! \cond PRIVATE */ +#include +#include +#include /* for "memset" */ +/*! \endcond */ + +#include +#include + + /*! \cond PRIVATE */ + +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* It is used in the _data.h file which isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ + +#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm088,Pm140 +#endif /* __ICCARM__ */ + +/* pull in internal data structures */ +#include "adi_i2c_data.c" + + +/* handy type-safe zero */ +uint16_t uZero16 = 0u; + +/* central busy checker */ +#define I2C_BUSY (uZero16 != ((hDevice->pDev->MSTAT) & (uint16_t)(BITM_I2C_MSTAT_MBUSY | BITM_I2C_MSTAT_LINEBUSY))) + +/*! + * Read/write bit. + */ + #define READ_NOT_WRITE (1u) + +/* Override "weak" default binding in startup.c */ +/*! \cond PRIVATE */ +extern void I2C0_Master_Int_Handler(void); + +/* DS4 and DS5 bits of GPIO Port 0 drive strength select register */ +#define I2C_GPIO_PORT0_DS4 ((uint16_t) ((uint16_t) 1<<4)) +#define I2C_GPIO_PORT0_DS5 ((uint16_t) ((uint16_t) 1<<5)) + +#define ADI_ADUCM302X_CHIPID_SI_1_2 0x284u +/*! \endcond */ + +#if defined(ADI_DEBUG) +/* + * Verifies a pointer to a driver points to one of the driver + * struct's internal to this file. + */ +static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice); +static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice) +{ + if ((i2c_device_info[0].hDevice != (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL)) { + return true; + } else { + return false; + } +} +#endif + +#if defined(__ADUCM302x__) +static ADI_SYS_REGISTERS adi_sys_base = { pADI_SYS }; +#endif + +/*! \endcond */ + + +/**********************************************************************************\ +|**********************************USER INTERFACE**********************************| +\**********************************************************************************/ + + +/*! + * @brief Initialize and allocate an I2C device for use in Master Mode. + * + * @param[in] DeviceNum Zero-based device index designating the I2C device to initialize. + * + * @param [in] pMemory Pointer to a 32-bit aligned buffer of size ADI_I2C_MEMORY_SIZE + * required by the driver for the operation of specified I2C device. + * + * @param [in] MemorySize Size of the buffer to which "pMemory" points. + * + * @param[out] phDevice The caller's device handle pointer for storing the initialized + * device instance data pointer. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_NUMBER [D] Invalid device index. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is already opened. + * - #ADI_I2C_INSUFFICIENT_MEMORY [D] Device memory is not sufficient. + * + * Initialize an I2C device using default user configuration settings (from adi_i2c_config.h) + * and allocate the device for use. Device is opened in Master mode only. + * + * No other I2C APIs may be called until the device open function is called. The returned + * device handle is required to be passed to all subsequent I2C API calls to identify the + * physical device instance to use. The user device handle (pointed to by phDevice) is set + * to NULL on failure. + * + * @note Currently, only a singular I2C physical device instance (device ID "0") exists. + * + * @sa adi_spi_Close(). + */ +ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice) { + + /* make a device handle out of the user memory */ + ADI_I2C_HANDLE hDevice = (ADI_I2C_HANDLE)pMemory; + #if defined(__ADUCM302x__) + /* + * I2C fix for Silicon Version 1.2 + * Enable the drive strength of GPIO pins used for I2C communication. + */ + + /* Get the pointer to the internal structure for System registers*/ + ADI_SYS_REGISTERS *sys = &adi_sys_base; + + if( sys->pReg->CHIPID == ADI_ADUCM302X_CHIPID_SI_1_2 ) + { + *((volatile uint32_t *)REG_GPIO0_DS) |= ( I2C_GPIO_PORT0_DS4 | I2C_GPIO_PORT0_DS5 ); + } + + #endif +#if defined(ADI_DEBUG) + /* check requested device number */ + if (DeviceNum >= (uint32_t)ADI_I2C_NUM_INSTANCES) { + return ADI_I2C_BAD_DEVICE_NUMBER; + } + + /* verify device is not already open */ + if (i2c_device_info[DeviceNum].hDevice != NULL) { + return ADI_I2C_DEVICE_IN_USE; + } + + /* verify memory size macro value */ + assert(ADI_I2C_MEMORY_SIZE == sizeof(ADI_I2C_DEV_DATA_TYPE)); + + /* verify user-provided memory meets requirement */ + if ((NULL == pMemory) || (MemorySize < (uint32_t)ADI_I2C_MEMORY_SIZE)) { + return ADI_I2C_INSUFFICIENT_MEMORY; + } +#endif + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* + * Link user memory (handle) to ADI_I2C_DEVICE_INFO data structure. + * + * ADI_I2C_DEVICE_INFO <==> ADI_I2C_HANDLE + * + * Clear the ADI_I2C_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bRepearStart = false) + */ + i2c_device_info[DeviceNum].hDevice = (ADI_I2C_DEV_DATA_TYPE *)pMemory; + memset(pMemory, 0, MemorySize); + + /* also link device handle within __ADI_I2C_DEV_DATA_TYPE data structure */ + hDevice->pDevInfo = &i2c_device_info[DeviceNum]; + /* + * Although the ADI_I2C_DEVICE_INFO struct has the physical device pointer + * for this instance, copying it to the ADI_I2C_HANDLE struct (in user memory) + * will minimize the runtime footprint and cycle count when accessing the I2C + * registers. + */ + hDevice->pDev = i2c_device_info[DeviceNum].pDev; + + /* store a pointer to user's static configuration settings */ + hDevice->pDevInfo->pConfig = (ADI_I2C_CONFIG*)&gConfigInfo[DeviceNum]; + + /* create the semaphore */ + SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice); + + /* store device handle into user handle */ + *phDevice = (ADI_I2C_HANDLE)hDevice; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Uninitialize and deallocate an I2C device. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * + * Uninitialize and release an allocated I2C device, and memory associated with it + * for other use. + * + * @note The user memory is released from use by the I2C driver, but is not freed. + * + * @sa adi_spi_Open(). + */ +ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* destroy semaphore */ + SEM_DELETE(hDevice,ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice); + + /* stub handle */ + hDevice->pDevInfo->hDevice = NULL; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Blocking I2C Master-Mode data read/write API. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pTransaction Pointer to I2C transaction data struct. + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] An I2C transaction is already underway. + * - #ADI_I2C_INVALID_PARAMETER [D] Invalid data pointer or count is detected. + * - #ADI_I2C_HW_ERROR_DETECTED A hardware error occurred, check \a pHwErrors. + * + * Request a blocking I2C data transfer (read or write, not both as I2C is unidirectional bus) + * with or without preceding prologue transmitted. Control is not returned to the calling + * application until the transfer is complete. Buffer allocations are made by the calling code + * (the application). + * + * The optional prologue (if present) and MANDATORY transaction data pointers are used to read or + * write data over the I2C serial bus according to the prologue and data pointers and corresponding + * size information contained in the \a pTransaction parameter block. The most recently set slave + * target address (set statically with user configuration settings contained in adi_i2c_config.h file + * or set dynamically (at run-time) via the #adi_i2c_SetSlaveAddress() API) is used to address the + * specific destination slave device on the I2C bus. + * + * If present, the prologue (typically, an addressing phase conveying a memory/register address or + * slave device command) is transmitted prior to the data read or write phase, with or without + * an intervening I2C STOP condition. The prologue data is entirely slave device dependent. + * + * In the case of a prologue followed by a data read operation, the I2C bus direction must be + * reversed following the prologue transmit. In this case, The usual I2C STOP condition following + * the prologue (if present) transmit may be suppressed by setting the \a bRepeatStart transaction + * parameter "true". In this case, a second (repeat) START condition is "transmitted" between the + * addressing phase (prologue transmit) and the data phase of the read sequence... \a without an + * intervening STOP condition. This is commonly referred to as the "combined format" in which the + * I2C bus direction is reversed halfway through the transaction without releasing control of the + * I2C bus arbitration. The REPEAT-START condition is a common I2C bus protocol required by many + * I2C slave devices. + * + * In the case of a prologue followed by a data write operation, there is no need to turn the bus + * around and so the \a bRepeatStart parameter is ignored. + * + * @note Application must check the return code to verify if any I2C Bus errors occurred. Hardware + * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and + * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are + * indicated in the value set to user variable pointed to by \a pHwErrors. + * + * @sa adi_i2c_SetSlaveAddress(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + * @sa ADI_I2C_HW_ERRORS. + */ +ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } + /* NULL transaction data pointer or zero transaction data count */ + if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) { + return ADI_I2C_INVALID_PARAMETER; + } +#endif + + /* reset submit/get safeguard flag */ + hDevice->bSubmitCalled = false; + + /* submit/commence the transaction */ + submitTransaction(hDevice, pTransaction); + + /* block on internal transaction completion/error semaphore */ + if (ADI_I2C_SUCCESS == hDevice->result) { + + SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED); + + /* completion interrupt comes as FIFO unloads, but serialization may not be complete yet... */ + /* must also wait for hardware busy status to clear before giving back control */ + /* i.e., allow any transmit serialization to complete after last FIFO unload */ + while (I2C_BUSY) { + ; + } + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->hwErrors; + if (0u != hDevice->hwErrors) { + /* set the HW error return code */ + hDevice->result = ADI_I2C_HW_ERROR_DETECTED; + } + + /* return transaction result code */ + return hDevice->result; +} + + +/*! + * @brief Non-Blocking I2C Master-Mode data read or data write API. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pTransaction Pointer to I2C transaction data struct. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] An I2C transaction is already underway. + * - #ADI_I2C_INVALID_PARAMETER [D] Invalid data pointer or count is detected. + * + * Request a non-blocking I2C data transfer (read or write) with or without preceding prologue + * transmitted. Control is returned to the calling application immediately, allowing the application + * process other tasks. The transaction result code is retrieved by #adi_i2c_GetBuffer(). + * + * The application may optionally poll the I2C driver via the #adi_i2c_IsBufferAvailable() API while + * the transaction is underway to determine if and when the submitted transaction is complete. + * Eventually, the application \a MUST call the \a MANDATORY #adi_i2c_GetBuffer() API to obtain the + * transaction result and complete the transaction. Buffer allocations are made by the calling + * code (the application). + * + * The #adi_i2c_GetBuffer() API may be called at any time, even if the transaction is incomplete; + * the #adi_i2c_GetBuffer() call will simply block in incomplete transactions until the + * transaction does complete... at which point #adi_i2c_GetBuffer() returns control with + * the transaction result code. Submitting background transactions is useful if the application has + * housekeeping chores to perform when the I2C transaction is started, but later the application + * decides to just block until the transaction is complete. + * + * The prologue and data buffers are handled as they are in the blocking #adi_i2c_ReadWrite() call, + * it's just that the #adi_i2c_SubmitBuffer() API does not block on the data phase. + * + * @note The non-blocking #adi_i2c_SubmitBuffer() call \a REQUIRES a matching #adi_i2c_GetBuffer() call + * to obtain the final transaction result code and to inform the driver that the application wants to + * regain ownership of the buffers. The application should be prepared to wait for this ownership + * until the current transaction completes. The matching #adi_i2c_GetBuffer() call is required even if + * the transaction may have already completed. The #adi_i2c_GetBuffer() call allows the driver to block + * on completion or error events and then synchronize its internal blocking object. The intermediate + * #adi_i2c_IsBufferAvailable() API is optional.\n\n + * + * @note The #adi_i2c_SubmitBuffer() API is singular, i.e., only a single transaction may be submitted + * at a time. Simultaneous submits (e.g., ping-pong mode) are not supported by the I2C driver. + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SetSlaveAddress(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + */ +ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } + /* NULL transaction data pointer or zero transaction data count */ + if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) { + return ADI_I2C_INVALID_PARAMETER; + } +#endif + + /* set submit/get safeguard flag */ + hDevice->bSubmitCalled = true; + + /* submit/commence the transaction */ + submitTransaction(hDevice, pTransaction); + + /* no blocking on submit... just return the submit result */ + return hDevice->result; +} + + +/*! + * @brief Query if a non-blocking I2C transfer is complete. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[out] pbCompletionState Pointer to Boolean into which the I2C bus state is written. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_INVALID_SUBMIT_API No matching submit call. + * + * Sets the application-provided Boolean variable pointed to by pbCompletionState either: + * - true, when the non-blocking transactions is complete, or + * - false, while the non-blocking transactions is still underway. + * + * This API is used in conjunction with a non-blocking #adi_i2c_SubmitBuffer() transfer to + * determine when the transaction is complete. Typically, non-blocking calls are used when the + * calling application has other work to do while I2C controller serializes data over the I2C bus, + * which is an interrupt-driven process. The transaction is submitted as a non-blocking call and + * the submitting API returns immediately, allowing the calling application to perform its other tasks. + * The I2C driver services the interrupts to transfer data while the application performs its + * other tasks. + * + * Non-blocking calls can be polled with this API for completion, or if the application has completed + * its other tasks and wants to just wait on the I2C completion without further polling, it may call + * the associated #adi_i2c_GetBuffer() API to convert the currently unblocked transaction to + * a blocking one. + * + * @note This API is inappropriate in context of blocking calls to #adi_i2c_ReadWrite(). + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + */ +ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_I2C_INVALID_SUBMIT_API; + } + + /* return true when bus goes quiet */ + if (I2C_BUSY) { + *pbCompletionState = false; + } else { + *pbCompletionState = true; + } + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Request ownership of a submitted buffer. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_INVALID_SUBMIT_API No matching submit call. + * - #ADI_I2C_HW_ERROR_DETECTED A hardware error occurred, check \a pHwErrors. + * + * This is a potentially blocking MANDATORY call that the application MUST use to reclaim + * ownership of any "submitted" transaction (submitted via a previous #adi_i2c_SubmitBuffer() + * call) and obtain the transaction success/failure result code. This API blocks until the + * transaction is complete and returns the transaction result code. If the transaction is + * already complete, the blocking is trivial and control is returned immediately. + * + * Non-blocking calls can also be (optionally) polled with the non-blocking + * #adi_i2c_IsBufferAvailable() API to see if and when the transaction is complete. + * + * The #adi_i2c_GetBuffer() call is a MANDATORY compliment to #adi_i2c_SubmitBuffer() and + * allows the I2C driver to synchronize its internal blocking object. + * + * @note Application must check the return code to verify if any I2C Bus errors occurred. Hardware + * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and + * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are + * indicated in the value set to user variable pointed to by \a pHwErrors. + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa ADI_I2C_TRANSACTION. + * @sa ADI_I2C_HW_ERRORS. + */ +ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_I2C_INVALID_SUBMIT_API; + } + + /* block until complete or error interrupt sets the semaphore */ + SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED); + + /* delay until bus goes quiet */ + while (I2C_BUSY) { + ; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->hwErrors; + if (0u != hDevice->hwErrors) { + /* set the HW error return code */ + hDevice->result = ADI_I2C_HW_ERROR_DETECTED; + } + + /* return transaction result code */ + return hDevice->result; +} + +/*! + * @brief Reset an I2C device and driver instance. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * + * Reset the I2C physical controller and device driver internals. + */ +ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* destroy/recreate the semaphore to force a clear state */ + SEM_DELETE(hDevice, ADI_I2C_SEMAPHORE_FAILED) + ; + SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + return i2cReset(hDevice); +} + + +/*! + * @brief Set the I2C serial bus speed. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] requestedBitRate32 Requested I2C bus clock rate (in Hz). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * - #ADI_I2C_BAD_SYS_CLOCK Failure to obtain the current PCLK rate. + * - #ADI_I2C_BAD_BITRATE Requested clock speed exceeds operational specification. + * + * Sets the I2C bus clock speed to the requested user parameter, \a requestedBitRate. + * + * @note Any I2C Bus clock rate may be requested up to and including the "FAST" mode I2C clock + * rate (400 kHz), including the "STANDARD" mode (100 kHz). Faster clock rates beyond "FAST" + * mode (e.g., "FAST+" or "HIGH-SPEED" modes) are not supported by the hardware. Slower clock + * rates below approximately 55 kHz (assuming a 26 MHz system clock) are physically unrealizable + * due to the fixed 8-bit field-width of the 8-bit I2C clock rate divide register.\n\n + * + * @note Default clock rate may be specified statically in the default user configuration file, + * "adi_i2c_config.h". + */ +ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32) { + + uint32_t clockFrequency32, halfClock32; + uint16_t halfClock16; + uint16_t highTime16, lowTime16; + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* get input clockrate from power service */ + if (ADI_PWR_SUCCESS != adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &clockFrequency32)) { + return ADI_I2C_BAD_SYS_CLOCK; + } + + /* block requests above max rated 400kHz operation */ + if (ADI_I2C_MAX_RATE < requestedBitRate32) { + return ADI_I2C_BAD_BITRATE; + } + + /* compute half-cycle period in 32-bits (">>1" is divide by 2) */ + halfClock32 = (clockFrequency32 / requestedBitRate32) >> 1; /* HRM equation */ + + /* downcast to 16-bit to match destination field */ + halfClock16 = (uint16_t)(halfClock32 & 0x0000ffffu); + + /* check for lost precision in conversion */ + if (halfClock32 != halfClock16) { + return ADI_I2C_BAD_BITRATE; + } + + /* adjust high and low durations per HRM */ + highTime16 = halfClock16 - 7u; /* empirical: varies with board layout, pullups, etc */ + lowTime16 = halfClock16 - 1u; + + /* shift values into their clock rate divider register positions */ + highTime16 <<= BITP_I2C_DIV_HIGH; + lowTime16 <<= BITP_I2C_DIV_LOW; + + /* check for divider overflows beyond designated (8-bit) field masks */ + if ( (uZero16 != ((uint16_t)highTime16 & (uint16_t)(~(BITM_I2C_DIV_HIGH)))) + || + (uZero16 != ((uint16_t)lowTime16 & (uint16_t)(~(BITM_I2C_DIV_LOW)))) + ) { + return ADI_I2C_BAD_BITRATE; + } + + /* program new values */ + hDevice->pDev->DIV = highTime16 | lowTime16; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Set the I2C serial bus slave address. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] SlaveAddress New 7-bit address for targeting a slave device. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * - #ADI_I2C_INVALID_SLAVE_ADDRESS Slave address exceeds the 7-bit limit. + * + * Sets the 7-bit (unformatted) slave address for which all subsequent I2C bus traffic is directed. + * Read/write address formatting is performed by the driver, depending on bus direction. + * + * @note This driver does not support the I2C 10-bit extended addressing scheme.\n\n + * + * @note Default slave address may be specified statically in the default user configuration file, + * "adi_i2c_config.h". + */ +ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* verify no slave address bits fall outside the 7-bit addressing model (10-bit addressing not supported) */ + if (uZero16 != (SlaveAddress & (uint16_t)(~(BITM_I2C_ADDR1_VALUE >> 1)))) { + return ADI_I2C_INVALID_SLAVE_ADDRESS; + } + + /* save new address */ + hDevice->i2cDeviceAddress = SlaveAddress; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Transmit a General Call command to all slave devices on the I2C bus. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pData Pointer to data buffer to transmit. + * @param[in] nDataSize Size of data buffer to transmit. + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * + * Broadcasts the given command buffer across the I2C bus to reserved General Call (GC) + * address (address zero). All, some, or none of the slave devices on the I2C bus will + * respond, depending on their capabilities. All responding slave devices will process + * the GC command according to their capabilities. + * + * The GC command is a blocking transaction. + * + * The application is responsible for formatting the GC command into the data buffer + * according to various Philips Semiconductor (now, NXP) documents, such as the 2014 + * Revision 6 document: "UM10204 I2C-Bus Specification and User Manual" + * (see www.nxp.com/documents/user_manual/UM10204.pdf). + * + * No prologue precedes the GC command data; the GC command data is transmitted verbatim. + * + * @note The currently active slave address is saved and restored when transmitting GC + * commands to the reserved GC address (address zero). + * + */ +ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors) { + + ADI_I2C_RESULT result; + ADI_I2C_TRANSACTION xfr; + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* force general call reserved target address of zero */ + uint16_t savedSlaveAddress = hDevice->i2cDeviceAddress; + hDevice->i2cDeviceAddress = 0u; + + /* setup the transfer */ + xfr.pPrologue = NULL; + xfr.nPrologueSize = 0u; + xfr.pData = pData; + xfr.nDataSize = nDataSize; + xfr.bReadNotWrite = false; + xfr.bRepeatStart = false; + + /* dispatch as a blocking transmit call */ + result = adi_i2c_ReadWrite(hDevice, &xfr, pHwErrors); + + /* always restore saved slave address */ + hDevice->i2cDeviceAddress = savedSlaveAddress; + + if (ADI_I2C_SUCCESS != result) { + return result; /* read/write failure... */ + } else { + return hDevice->result; /* actual result */ + } +} + + + /*! \cond PRIVATE */ + + +/**********************************************************************************\ +|*****************************static helper functions******************************| +\**********************************************************************************/ + +static void submitTransaction(ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) { + + /* reset internal return code */ + hDevice->result = ADI_I2C_SUCCESS; + + /* reset hardware error code */ + hDevice->hwErrors = ADI_I2C_HW_ERROR_NONE; + + /* wait for HW to be ready */ + while (I2C_BUSY) { + ; + } + + /* save common user parameters */ + hDevice->pNextPrologueByte = pTransaction->pPrologue; + hDevice->remainingPrologueCount = pTransaction->nPrologueSize; + hDevice->bRepeatStart = pTransaction->bRepeatStart; + + /* encode (mask and upshift) the slave address, leaving room for the r/w control bit (LSB) */ + hDevice->i2cEncodedDeviceAddress = (hDevice->i2cDeviceAddress & (BITM_I2C_ADDR1_VALUE >> 1)) << 1; + + /* dispatch */ + if (pTransaction->bReadNotWrite) { + + /* setup read parameters */ + hDevice->pNextReadByte = pTransaction->pData; + hDevice->remainingReadCount = pTransaction->nDataSize; + hDevice->pNextWriteByte = NULL; + hDevice->remainingWriteCount = 0u; + + /* set read bit */ + hDevice->i2cEncodedDeviceAddress |= READ_NOT_WRITE; + + /* commence receive */ + commenceReceive(hDevice); + + } else { + + /* setup write parameters */ + hDevice->pNextReadByte = NULL; + hDevice->remainingReadCount = 0u; + hDevice->pNextWriteByte = pTransaction->pData; + hDevice->remainingWriteCount = pTransaction->nDataSize; + + /* clear read bit */ + hDevice->i2cEncodedDeviceAddress &= (~READ_NOT_WRITE); + + /* commence transmit */ + commenceTransmit(hDevice); + } +} + + +static void commenceTransmit(ADI_I2C_HANDLE const hDevice) { + + /* transmit is always pure transmit, whether we have a prologue or not... */ + + /* enable PIO interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn); + + /* enable i2c for PIO-based transmit interrupts */ + hDevice->pDev->MCTL |= (BITM_I2C_MCTL_IENMTX | BITM_I2C_MCTL_MASEN); + + /* how many bytes are available in the transmit FIFO (2-deep) */ + uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF); + + /* prime transmit FIFO with any prologue data */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* flesh out any remaining FIFO space with transmit data */ + while ((0u < writableBytes) && (hDevice->remainingWriteCount)) { + hDevice->pDev->MTX = *hDevice->pNextWriteByte; + hDevice->pNextWriteByte++; + hDevice->remainingWriteCount--; + writableBytes--; + } + + /* launch the transmit */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; +} + + +/* initiate receive addressing phase */ +static void commenceReceive(ADI_I2C_HANDLE const hDevice) { + + /* receive can be either pure receive (no prologue), + or a transmit (of prologue) followed by a receive */ + + /* enable PIO interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn); + + /* enable i2c for PIO-based receive interrupts */ + hDevice->pDev->MCTL |= (uint16_t)(BITM_I2C_MCTL_IENMRX | BITM_I2C_MCTL_MASEN); + + /* program HW receive count */ + if (hDevice->remainingReadCount > BITM_I2C_MRXCNT_EXTEND) { + hDevice->pDev->MRXCNT = BITM_I2C_MRXCNT_EXTEND; + hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND; + } else { + hDevice->pDev->MRXCNT = hDevice->remainingReadCount - 1u; + hDevice->remainingReadCount = 0u; + } + + /* if we have prologue (the dreaded "COMBINED FORMAT"), transmit the prologue prior to data receive... */ + if (hDevice->remainingPrologueCount) { + + /* -OR- in transmit interrupt enable if we have prologue data to send */ + hDevice->pDev->MCTL |= BITM_I2C_MCTL_IENMTX; + + /* how many bytes are available in the transmit FIFO (should be 2) */ + uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF); + + /* prime transmit FIFO with any prologue data (memory address or command) first */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* initiate prologue transmit with read bit cleared (for prologue write) */ + /* (read sequence is initiated by transmit handler, *after* prologue is transmitted...) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress & (uint16_t)(~READ_NOT_WRITE); + + } else { + + /* no prologue... initiate pure receive (read bit already set) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + } +} + + +/* reset the I2C HW */ +static ADI_I2C_RESULT i2cReset(ADI_I2C_HANDLE const hDevice) { + + volatile uint16_t temp; + /* disable interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn); + + /* reset any pending interrupts and TX FIFO (W1C) */ + temp = hDevice->pDev->MSTAT; + hDevice->pDev->MSTAT = temp; + + /* discard any rogue RX FIFO data */ + while (uZero16 != (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF)) { + volatile uint16_t delme ADI_UNUSED_ATTRIBUTE = hDevice->pDev->MTX; + } + + /* reset i2c control register */ + hDevice->pDev->MCTL = 0u; + + /* reset repeat start logic */ + hDevice->pDev->SHCTL = 1u; + + /* (re)assert controller defaults from user config values */ + hDevice->pDev->MCTL = hDevice->pDevInfo->pConfig->MasterControlRegister; + hDevice->pDev->DIV = hDevice->pDevInfo->pConfig->ClockDividerRegister; + hDevice->pDev->SHCTL = hDevice->pDevInfo->pConfig->SharedControlRegister; + hDevice->pDev->TCTL = hDevice->pDevInfo->pConfig->TimingControlRegister; + hDevice->pDev->ASTRETCH_SCL = hDevice->pDevInfo->pConfig->ClockStretchRegister; + hDevice->i2cDeviceAddress = hDevice->pDevInfo->pConfig->TargetSlaveAddress; + + return ADI_I2C_SUCCESS; +} + + +/**********************************************************************************\ +|********************************interrupt handlers********************************| +\**********************************************************************************/ + + +/* transmit interrupt handler */ +static void transmitHandler(ADI_I2C_HANDLE const hDevice) { + + /* how much room in transmit FIFO? */ + /* DO ***NOT*** USE MSTAT:MTXF... FALSELY INDICATES MOSTLY FULL FIFO! */ + uint16_t writableBytes = 2u - ((hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MTXF) >> BITP_I2C_STAT_MTXF); + + /* for extended prologues, continue pushing prologue data out */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* once the prologue is done... */ + if (0u == hDevice->remainingPrologueCount) { + + /* if we have a completed prologue associated with a read sequence... */ + if (0u < hDevice->remainingReadCount) { + + /* initiate the read (subsequently driven by receive interrupt handler) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + + } else { + + /* normal transmit interrupt: just push transmit data */ + while ((0u < writableBytes) && (hDevice->remainingWriteCount)) { + hDevice->pDev->MTX = *hDevice->pNextWriteByte; + hDevice->pNextWriteByte++; + hDevice->remainingWriteCount--; + writableBytes--; + } + } + } + + /* clear TX interrupt as we complete transmit writes */ + if (0u == hDevice->remainingWriteCount) { + hDevice->pDev->MSTAT = BITM_I2C_MSTAT_MTXREQ; + } +} + + +/* receive interrupt handler */ +static void receiveHandler(ADI_I2C_HANDLE const hDevice) { + + /* note: we never need to deal with prologue data here... it will already be transmitted... */ + + /* how many bytes in receive FIFO? */ + uint16_t readableBytes = (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF) >> BITP_I2C_STAT_MRXF; + + /* pull bytes from fifo */ + while (0u < readableBytes) { + + readableBytes--; + + /* pull one byte */ + *hDevice->pNextReadByte = (uint8_t)hDevice->pDev->MRX; + hDevice->pNextReadByte++; + + if ((0u == hDevice->pDev->MCRXCNT) && (hDevice->remainingReadCount)) { + + /* if HW read counter goes to zero with remaining data to read, reprogram read count */ + if (hDevice->remainingReadCount > BITM_I2C_MRXCNT_EXTEND) { + /* use extended count flag for large remaining counts... */ + hDevice->pDev->MRXCNT = BITM_I2C_MRXCNT_EXTEND; + hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND; + } else { + /* new count fits... no need for extended count */ + hDevice->pDev->MRXCNT = hDevice->remainingReadCount - 1u; + hDevice->remainingReadCount = 0u; + } + } + } +} + +/* completion interrupt handler */ +static void completeHandler(ADI_I2C_HANDLE const hDevice) { + + /* block on busy until all transmit data has both left + the fifo AND has been fully serialized to the bus. */ + while (I2C_BUSY) { + ; + } + + /* disable interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn); + + /* reset controller to default user config state */ + hDevice->pDev->MCTL = (uint16_t)gConfigInfo->MasterControlRegister; +} + + +/* error interrupt handler */ +static void errorHandler(ADI_I2C_HANDLE const hDevice) { + + /* accumulate I2C bus errors */ + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKADDR)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_ADDR; + } + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKDATA)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_DATA; + } + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_ALOST)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_ARBITRATION_LOST; + } + + /* if no other errors exist, note we had an unexpected error */ + if (hDevice->hwErrors == ADI_I2C_HW_ERROR_NONE) { + hDevice->hwErrors = ADI_I2C_HW_ERROR_UNEXPECTED_ERROR; + } +} + + +/**********************************************************************************\ +|*****************************I2C INTERRUPT HANDLER********************************| +\**********************************************************************************/ + + +/* PIO mode I2C interrupt handler */ +void I2C0_Master_Int_Handler(void) { + + bool bPost = false; + + /* rtos prologue */ + ISR_PROLOG() + ; + + /* recover device handle */ + ADI_I2C_HANDLE const hDevice = (ADI_I2C_HANDLE)i2c_device_info[0].hDevice; + + /* save destructive status read... */ + hDevice->hwStatus = hDevice->pDev->MSTAT; + + /* if RepeatStart request is pending, rewrite address register ASAP (and only once) to block stop bit */ + if (hDevice->bRepeatStart) { + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + hDevice->bRepeatStart = false; /* just do it once on 1st interrupt */ + } + + /* forward TX interrupts to TX handler */ + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MTXREQ)) { + transmitHandler(hDevice); + } + + /* forward RX interrupts to RX handler */ + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MRXREQ)) { + receiveHandler(hDevice); + } + + /* dispatch any errors */ + if (uZero16 != (hDevice->hwStatus & ADI_I2C_STATUS_ERROR_MASK)) { + errorHandler(hDevice); + + /* post on bus error */ + bPost = true; + } + + /* transmit complete */ + if (uZero16 != (hDevice->hwStatus & BITM_I2C_MSTAT_TCOMP)) { + completeHandler(hDevice); + + /* post on completion */ + bPost = true; + } + + /* just post once */ + if (true == bPost) { + SEM_POST(hDevice); + } + + /* rtos epilogue */ + ISR_EPILOG() + ; +} + +/*! \endcond */ + + +/* @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_data.c new file mode 100755 index 00000000000..ebd22ecb97f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_data.c @@ -0,0 +1,121 @@ +/* + ***************************************************************************** + * @file: adi_i2c_data.c + * @brief: Data declaration for I2C Device Driver + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be coni2ccuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_I2C_DATA_C +#define ADI_I2C_DATA_C + + /*! \cond PRIVATE */ + +#include +#include "adi_i2c_def.h" +#include "adi_i2c_config.h" + + +/* Stores the information about the specific device */ +static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] = +{ + /* fixed instance data for the singular I2C0 controller */ + { + I2C_MST_EVT_IRQn, /* pio interrupt number */ + (ADI_I2C_TypeDef *)pADI_I2C0, /* i2c controller pointer */ + NULL, /* pointer to user config data */ + NULL /* i2c device handle (user mem) */ + }, + + /* no other i2c instances at this time */ +}; + +/* build I2C Application configuration array */ +static ADI_I2C_CONFIG gConfigInfo[ADI_I2C_NUM_INSTANCES] = +{ + /* the one-and-only (so far) instance data for I2C, I2C0... */ + { + /**** I2C_MCTL Master Control register *** */ + ( + /* note: Master IENMTX and IENMRX (transmit and receive interrupts) are managed dynamically */ + ( ADI_I2C_CFG_MCTL_MXMITDEC << BITP_I2C_MCTL_MXMITDEC ) | + ( ADI_I2C_CFG_MCTL_IENCMP << BITP_I2C_MCTL_IENCMP ) | + ( ADI_I2C_CFG_MCTL_IENACK << BITP_I2C_MCTL_IENACK ) | + ( ADI_I2C_CFG_MCTL_IENALOST << BITP_I2C_MCTL_IENALOST ) | + ( ADI_I2C_CFG_MCTL_STRETCHSCL << BITP_I2C_MCTL_STRETCHSCL ) | + ( ADI_I2C_CFG_MCTL_LOOPBACK << BITP_I2C_MCTL_LOOPBACK ) | + ( ADI_I2C_CFG_MCTL_COMPLETE << BITP_I2C_MCTL_COMPLETE ) | + ( ADI_I2C_CFG_MCTL_MASEN << BITP_I2C_MCTL_MASEN ) + ), + + /**** I2C_DIV Clock Divider register *** */ + ( + ( ADI_I2C_CFG_DIV_HIGH << BITP_I2C_DIV_HIGH ) | + ( ADI_I2C_CFG_DIV_LOW << BITP_I2C_DIV_LOW ) + ), + + /**** I2C_SHCTL Shared Control register *** */ + ( + ( ADI_I2C_CFG_SHCTL_RST << BITP_I2C_TCTL_FILTEROFF ) + ), + + /**** I2C_TCTL Timing control register *** */ + ( + ( ADI_I2C_CFG_TCTL_FILTEROFF << BITP_I2C_SHCTL_RST ) | + ( ADI_I2C_CFG_TCTL_THDATIN << BITP_I2C_TCTL_THDATIN ) + ), + + /**** I2C_ASTRETCH Master Clock Stretch register *** */ + ( + ( ADI_I2C_CFG_ASTRETCH_MST << BITP_I2C_ASTRETCH_SCL_MST ) + ), + + /**** Target Slave configuration value (not a register) *** */ + ( + ( ADI_I2C_CFG_SLAVE_ADDRESS ) + ), + } +}; + +/*! \endcond */ + + +#endif /* ADI_I2C_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_def.h new file mode 100755 index 00000000000..bbf8bc57cba --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/i2c/adi_i2c_def.h @@ -0,0 +1,141 @@ +/*! + ***************************************************************************** + @file: adi_i2c_def.h + @brief: Internal I2C device driver definitions and macros + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ +#ifndef ADI_I2C_DEF_H +#define ADI_I2C_DEF_H + +/*! \cond PRIVATE */ + +#include + +#define ADI_I2C_NUM_INSTANCES (1u) +#define ADI_I2C_STATUS_ERROR_MASK ( (1u << BITP_I2C_MSTAT_NACKADDR) \ + | (1u << BITP_I2C_MSTAT_NACKDATA) \ + | (1u << BITP_I2C_MSTAT_ALOST) ) + +/* Internal Actions */ +static void submitTransaction (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction); +static void commenceTransmit (ADI_I2C_HANDLE const hDevice); +static void commenceReceive (ADI_I2C_HANDLE const hDevice); +static ADI_I2C_RESULT i2cReset (ADI_I2C_HANDLE const hDevice); + +/* interrupt event handlers */ +static void transmitHandler (ADI_I2C_HANDLE const hDevice); +static void receiveHandler (ADI_I2C_HANDLE const hDevice); +static void completeHandler (ADI_I2C_HANDLE const hDevice); +static void errorHandler (ADI_I2C_HANDLE const hDevice); + +#if defined(__ADUCM302x__) +/* + * SYS Device Structure + */ +typedef struct _ADI_SYS_STRUCT +{ + ADI_SYS_TypeDef *pReg; /* Pointer to register base */ +} ADI_SYS_STRUCT; + +/* alias for the actual device structure */ +typedef struct _ADI_SYS_STRUCT ADI_SYS_REGISTERS; + +#endif +/* + ***************************************************************************** + * I2C Configuration structure. + *****************************************************************************/ +typedef struct __ADI_I2C_CONFIG { + uint16_t MasterControlRegister; /* I2C_MCTL register configuration. */ + uint16_t ClockDividerRegister; /* I2C_DIV register. */ + uint16_t SharedControlRegister; /* I2C_DIV register. */ + uint16_t TimingControlRegister; /* I2C_TCTL register. */ + uint16_t ClockStretchRegister; /* I2C_ASTRETCH register. */ + uint16_t TargetSlaveAddress; /* slave address value (not a register). */ +} ADI_I2C_CONFIG; + + +/* I2C physical device instance data */ +typedef struct __ADI_I2C_DEVICE_INFO { + IRQn_Type pioIRQn; /* PIO interrupt number */ + ADI_I2C_TypeDef *pDev; /* pointer to i2c controller */ + ADI_I2C_CONFIG *pConfig; /* pointer to user config info */ + ADI_I2C_HANDLE hDevice; /* I2C handle or NULL if uninitialized */ +} ADI_I2C_DEVICE_INFO; + +/* I2C driver instance data structure */ +typedef struct __ADI_I2C_DEV_DATA_TYPE { + + /* make sure to synchronize ANY size changes with ADI_I2C_MEMORY_SIZE macro in adi_i2c.h */ + + /* device attributes */ + ADI_I2C_TypeDef *pDev; + ADI_I2C_DEVICE_INFO *pDevInfo; + + + /* driver state */ + uint16_t hwStatus; + bool bRepeatStart; + uint16_t i2cDeviceAddress; + uint16_t i2cEncodedDeviceAddress; /* encoded as 7-bit device address + r/w LSB */ + bool bSubmitCalled; + + /* prologue data */ + volatile uint8_t *pNextPrologueByte; + volatile uint16_t remainingPrologueCount; + + /* write data */ + volatile uint8_t *pNextWriteByte; + volatile uint16_t remainingWriteCount; + + /* read data */ + volatile uint8_t *pNextReadByte; + volatile uint16_t remainingReadCount; + + ADI_I2C_RESULT result; /* collector for return status */ + ADI_I2C_HW_ERRORS hwErrors; /* collector for error status */ + + SEM_VAR_DECLR /* blocking object: "Semaphore" for rtos, "nLowPowerExitFlag" for non-rtos */ + +} ADI_I2C_DEV_DATA_TYPE; + +/*! \endcond */ + +#endif /* end of ifndef ADI_I2C_DEF_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr.c new file mode 100755 index 00000000000..0ffe5f76bd6 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr.c @@ -0,0 +1,1918 @@ +/* + ***************************************************************************** + * @file: adi_pwr.c + * @brief: Power Management driver implementation. + *----------------------------------------------------------------------------- + * +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \addtogroup Power_Driver Power Driver + * @{ + * @brief Power Management Driver + * @note The application must include drivers/pwr/adi_pwr.h to use this driver + * @note The API #adi_pwr_EnableClockSource requires the GPIO driver if + * #ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO is set to 1. In that case the + * application must include the GPIO driver sources to avoid link errors. + */ + + +#include /* for 'NULL' */ +#include +#include +#include +#include +#include "adi_pwr_def.h" +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* Pm057 (rule 15.2): Every non-empty case clause in a switch statement shall be terminated with a break statement. +* In some cases we have return statement instead of break. It is not valid to both return and break in MISRA 2012. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057 +#endif /* __ICCARM__ */ + +/*! \cond PRIVATE */ + +/*---------------------------------------------------------------------------- + Internal Clock Variables. The external ones are defined in system.c + *---------------------------------------------------------------------------*/ +#ifdef ADI_DEBUG +/* not needed unless its debug mode */ +extern uint32_t lfClock; /* "lf_clk" coming out of LF mux */ +#endif + +extern uint32_t hfClock; /* "root_clk" output of HF mux */ +extern uint32_t gpioClock; /* external GPIO clock */ + +static ADI_CALLBACK gpfCallbackFunction; +static void *gpPowcbParam = NULL; +static uint32_t gnLowPowerIntOccFlag = 0u; + +/*! \endcond */ + +/*---------------------------------------------------------------------------- + Clock functions + *---------------------------------------------------------------------------*/ +/** + * Initialize the clock configuration register with the default values. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully initialized the power service. + */ +ADI_PWR_RESULT adi_pwr_Init (void) +{ + /* Enable internal HF oscillators */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE; + + gpfCallbackFunction = NULL; + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + /* Switch on the internal HF oscillator */ + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN; + + /* wait for HF OSC to stabilize */ + while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u) + { + } + + /* Switch over to the internal HF oscillator */ + pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX); + + /* complete remaining reset sequence */ + pADI_CLKG0_CLK->CTL0 = CLOCK_CTL0_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL1 = CLOCK_CTL1_CONFIG_VALUE; + +#if defined(__ADUCM4x50__) + pADI_CLKG0_CLK->CTL2 = CLOCK_CTL2_CONFIG_VALUE; +#endif /*__ADUCM4x50__ */ + + pADI_CLKG0_CLK->CTL3 = CLOCK_CTL3_CONFIG_VALUE; + /* No CLK CTL4 */ + pADI_CLKG0_CLK->CTL5 = CLOCK_CTL5_CONFIG_VALUE; + + /* + * Configure the power management registers + */ + pADI_PMG0->IEN = PWM_INTERRUPT_CONFIG; + pADI_PMG0->PWRMOD = PWM_PWRMOD_CONFIG; + pADI_PMG0->CTL1 = PWM_HPBUCK_CONTROL; + + /* disable external HF crystal oscillator */ + /* (don't disable LF crystal or the RTC will lose time */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN; + + NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn); + NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn); + + NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn); + NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn); + + /* compute new internal clocks based on the newly reset controller */ + SystemCoreClockUpdate(); + + return(ADI_PWR_SUCCESS); +} + + +/** + * @brief Updates the internal SystemCoreClock variable with current core + * Clock retrieved from cpu registers. + * + * @return Status + * - #ADI_PWR_SUCCESS : Updated core system core clock variables. + * + * Updates the internal SystemCoreClock variable with current core + * Clock retrieved from cpu registers. + * + * @sa adi_pwr_GetClockFrequency () + */ +ADI_PWR_RESULT adi_pwr_UpdateCoreClock (void) +{ + SystemCoreClockUpdate(); + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Registers or unregister the callback function. + * + * @details Application can register or unregister the callback function which + * will be called to notify the events from the driver. + * + * @param[in] pfCallback : Callback function pointer. + * @param[in] pcbParam : Callback parameter. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully installed the callback function. + * - #ADI_PWR_NULL_POINTER [D] : Failed to install the callback function since the call back function pointer is NULL. + */ +ADI_PWR_RESULT adi_pwr_RegisterCallback( + const ADI_CALLBACK pfCallback, + void *pcbParam + ) +{ + +#ifdef ADI_DEBUG + if(pfCallback == NULL) + { + return(ADI_PWR_NULL_POINTER); + } +#endif + + gpfCallbackFunction = pfCallback; + gpPowcbParam = pcbParam; + + return ADI_PWR_SUCCESS; +} + +/** + * @brief Sets the system external clock frequency + * + * @param[in] ExtClkFreq: External clock frequency in Hz + + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the external clock as source. + * - #ADI_PWR_INVALID_CLOCK_SPEED [D]: Specified clock is out of range. + * + * @sa adi_pwr_GetClockFrequency () + */ +ADI_PWR_RESULT adi_pwr_SetExtClkFreq (const uint32_t ExtClkFreq) +{ +#ifdef ADI_DEBUG + if(ExtClkFreq > MAXIMUM_EXT_CLOCK) + { + return(ADI_PWR_INVALID_CLOCK_SPEED); + } +#endif + gpioClock = ExtClkFreq; + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the input clock source for PLL multiplexer. + * + * @param[in] eClockID: Clock source to the System PLL multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the PLL multiplexer clock source. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* Validate the given clock ID */ + switch (eClockID) + { + case ADI_CLOCK_MUX_SPLL_HFOSC: + case ADI_CLOCK_MUX_SPLL_HFXTAL: + +#if defined(__ADUCM4x50__) + case ADI_CLOCK_MUX_SPLL_GPIO: +#endif /* __ADUCM4x50__ */ + break; + + + /* Any other clock ID is not valid since we are configuring the SPLL clock multiplexer. + * Only valid input clock to the multiplexer is HFOSC, HFXTAL, GPIO */ + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL); + tmp |= (( (uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_SPLL_HFOSC) << BITP_CLKG_CLK_CTL0_PLL_IPSEL); + pADI_CLKG0_CLK->CTL0 = tmp; + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the input clock for low frequency clock multiplexer. + * + * @param[in] eClockID: Clock source to the low frequency clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully LF clock multiplexer clock source. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetRootClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + + case ADI_CLOCK_MUX_LFCLK_LFOSC: + case ADI_CLOCK_MUX_LFCLK_LFXTAL: + break; + /* Any other clock ID is not valid since we are configuring the Low frequency clock multiplexer. + * Only valid input clock to the multiplexer is LFOSC, LFXTAL */ + + default: + return(ADI_PWR_INVALID_CLOCK_ID); + + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX); + tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_LFCLK_LFOSC) << BITP_CLKG_OSC_CTL_LFCLK_MUX); + pADI_CLKG0_OSC->CTL = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets clock source for the Reference clock multiplexer. + * + * @param[in] eClockID: Clock source to the reference clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the source for reference clock multiplexer. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + * @sa adi_pwr_SetRootClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ + +ADI_PWR_RESULT adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + + case ADI_CLOCK_MUX_REF_HFOSC_CLK: + case ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK: + case ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK: + break; + /* Any other clock ID is not valid since we are configuring the out clock multiplexer.*/ + + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX); + tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_REF_HFOSC_CLK) << BITP_CLKG_CLK_CTL0_RCLKMUX); + pADI_CLKG0_CLK->CTL0 = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the source for the root clock multiplexer. + * + * @param[in] eClockID: Clock source to the root clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the source for root clock multiplexer. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + case ADI_CLOCK_MUX_ROOT_HFOSC: + case ADI_CLOCK_MUX_ROOT_HFXTAL: + case ADI_CLOCK_MUX_ROOT_SPLL: + case ADI_CLOCK_MUX_ROOT_GPIO: + break; + /* Any other clock ID is not valid since we are configuring the root clock multiplexer. + * Only valid input clock to the multiplexer is HFOSC, HFXTAL, SPLL, GPIO */ + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX); + tmp |= (((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX); + pADI_CLKG0_CLK->CTL0 = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + +/** + * @brief Gets the system external clock frequency. + * Gets the clock frequency of the source connected to the external GPIO clock input source. + * + * @param [in] pExtClock : Pointer to write the external clock frequency. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully returning the external clock frequency. + * - #ADI_PWR_NULL_POINTER [D] : If the given pointer is pointing to NULL. + * - #ADI_PWR_FAILURE [D] : The system is not initialized yet. Call SystemInit before calling this API. + */ +ADI_PWR_RESULT adi_pwr_GetExtClkFreq (uint32_t *pExtClock) +{ +#ifdef ADI_DEBUG + /* Trap here if the app fails to set the external clock frequency. */ + if (0u == gpioClock) + { + return (ADI_PWR_FAILURE); + } + + if(pExtClock == NULL) + { + return (ADI_PWR_NULL_POINTER); + } +#endif + *pExtClock = gpioClock; + return ADI_PWR_SUCCESS; +} + + +/*! + * @brief Get the frequency of the given clock. + * Obtain individual peripheral clock frequencies + * + * @param[in] eClockId : Clock identifier + * @param[out] pClock : Pointer to a location to store the clock frequency. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully returned the queried clock. + * - #ADI_PWR_SYSTEM_NOT_INITIALIZED [D] : The system is not initialized yet. Call SystemInit before calling this API. + * + * @sa adi_PWR_SetClockDivide + * @sa SystemSetClockDivider +*/ +ADI_PWR_RESULT adi_pwr_GetClockFrequency (const ADI_CLOCK_ID eClockId, uint32_t *pClock ) +{ + uint32_t src, nDiv; + +#ifdef ADI_DEBUG + /* trap here if the app fails to call SystemInit(). */ + if ((0u == hfClock) || (0u == lfClock)) + { + return ADI_PWR_SYSTEM_NOT_INITIALIZED; + } +#endif + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); + src = hfClock; + + switch (eClockId) { + + /* HCLOCK domain */ + case ADI_CLOCK_HCLK: + nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + break; + + /* PCLOCK domain */ + case ADI_CLOCK_PCLK: + nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + break; + + default: + return ADI_PWR_INVALID_CLOCK_ID; + } /* end switch */ + + if(nDiv == 0u) + { + nDiv = 1u; + } + + *pClock = (src/nDiv); + + return ADI_PWR_SUCCESS; +} + + +/*! + @brief Enable/disable individual peripheral clocks. + + @param[in] eClockGate Clock identifier + @param[in] bEnable Flag to indicate whether to enable/disable individual clock. + true - to enable individual clock. + false - to disable individual clock. + + @return Status + - #ADI_PWR_SUCCESS if we have successfully enabled or disabled the clock. + + @details Manage individual peripheral clock gates to enable or disable the clocks to the peripheral. +*/ +ADI_PWR_RESULT adi_pwr_EnableClock (const ADI_CLOCK_GATE eClockGate, const bool bEnable) +{ + uint32_t mask; + ADI_INT_STATUS_ALLOC(); + + mask = (uint16_t)eClockGate; + /* update the Clock Gate register in a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + /* NOTE NEGATIVE LOGIC!!! */ + if (bEnable == true) { + + /* clear disable bit */ + pADI_CLKG0_CLK->CTL5 &= ~mask; + } else { + /* set disable bit */ + pADI_CLKG0_CLK->CTL5 |= mask; + } + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + @brief Sets the clock divide factor for an individual clock group. + + @param[in] eClockId Clock domain identifier. + @param[in] nDiv Clock divide value to be set (right-justified uint16_t). + + @return Status + - #ADI_PWR_SUCCESS if successfully set the given clock divide factor. + - #ADI_PWR_INVALID_CLOCK_DIVIDER [D] if the divider is out of range. + - #ADI_PWR_INVALID_CLOCK_ID [D] if the given clock is invalid. + - #ADI_PWR_INVALID_CLOCK_RATIO [D] if the given clock ratio invalid. + + @details Manage individual peripheral clock dividers. + + @sa SystemGetClockFrequency +*/ +ADI_PWR_RESULT adi_pwr_SetClockDivider (const ADI_CLOCK_ID eClockId, const uint16_t nDiv) +{ + uint32_t mask; + uint32_t value; + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + uint32_t hdiv, pdiv; +#endif /*ADI_DEBUG*/ + + switch (eClockId) + { + case ADI_CLOCK_HCLK: +#ifdef ADI_DEBUG + /* Verify the divide factor is within the range */ + if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify PCLK freq is <= requested HCLK */ + pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + hdiv = nDiv; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + + mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + break; + + case ADI_CLOCK_PCLK: +#ifdef ADI_DEBUG + + /* Verify the divide factor is within the range */ + if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify requested PCLK freq is <= HCLK */ + pdiv = nDiv; + hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + break; + + case ADI_CLOCK_ACLK: +#ifdef ADI_DEBUG + /* Verify the divide factor is within the range */ + if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify requested ACLK freq is <= HCLK */ + pdiv = nDiv; + hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + + mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + break; + + + default: + return ADI_PWR_INVALID_CLOCK_ID; + } /* end switch */ + + /* critical region */ + ADI_ENTER_CRITICAL_REGION(); + + /* read-modify-write without any interrupts */ + /* change in a tmp variable and write entire new value all at once */ + tmp = pADI_CLKG0_CLK->CTL1; + tmp &= ~mask; /* blank the field */ + tmp |= value; /* set the new value */ + pADI_CLKG0_CLK->CTL1 = tmp; /* write the new value */ + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); + + return ADI_PWR_SUCCESS; +} + +/*! + * @brief To Enable/disable clock sources. + * + * @param[in] eClockSource : Clock source identifier. + * @param[in] bEnable : Enable (true) or disable (false) the clock source. + * + * @return Status + * - #ADI_PWR_SUCCESS if the clock source powers up successfully. + * - #ADI_PWR_INVALID_PARAM if the clock source is not valid. + * + * @details Enables or disables clock sources without additional checks, by writing a "1" or "0" to the enable bit. + * + */ +ADI_PWR_RESULT adi_pwr_EnableClockSource (const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable) +{ + uint32_t val = 0u; + volatile uint32_t *pReg = NULL; + uint32_t nMask = 0u; + ADI_INT_STATUS_ALLOC(); + + /* This switch statement does not handle every value in the ADI_CLOCK_SOURCE_ID enumeration + * which results on a gcc warning. This is done intentionally: + * ADI_CLOCK_SOURCE_LFOSC is not checked because it is enabled always and it cannot be disabled + * ADI_CLOCK_SOURCE_GPIO is only checked if a specific configuration macro is defined + */ + switch(eClockSource) + { + case ADI_CLOCK_SOURCE_HFXTAL: + val = (1u << BITP_CLKG_OSC_CTL_HFX_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_HFX_OK; + break; + + case ADI_CLOCK_SOURCE_LFXTAL: + val = (1u << BITP_CLKG_OSC_CTL_LFX_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_LFX_OK; + break; + + case ADI_CLOCK_SOURCE_HFOSC: + val = (1u << BITP_CLKG_OSC_CTL_HFOSC_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_HFOSC_OK; + break; + + case ADI_CLOCK_SOURCE_SPLL: + val = (1u << BITP_CLKG_CLK_CTL3_SPLLEN); + pReg = &pADI_CLKG0_CLK->CTL3; + nMask = BITM_CLKG_CLK_CTL3_SPLLEN; + break; + +#if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1) + case ADI_CLOCK_SOURCE_GPIO: + if(adi_gpio_PullUpEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,false) != ADI_GPIO_SUCCESS) + { + return(ADI_PWR_FAILURE); + } + if(adi_gpio_InputEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,true) != ADI_GPIO_SUCCESS) + { + return ADI_PWR_SUCCESS; + } + break; +#endif + + default: + return(ADI_PWR_INVALID_PARAM); + + } /* end switch */ + + ADI_ENTER_CRITICAL_REGION(); + + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + if (bEnable == true) + { + *pReg |= val; + } + else + { + *pReg &= ~val; + } + + ADI_EXIT_CRITICAL_REGION(); + + if((nMask !=0u) && (bEnable == true)) + { + while(0u== (pADI_CLKG0_OSC->CTL & nMask)){} + } + + return (ADI_PWR_SUCCESS); +} + + +/*! + * @brief Return the status of a clock source. + * + * @param[in] eClockSource : Clock source identifier. + * @param[out] peStatus : Pointer to variable of type #ADI_CLOCK_SOURCE_STATUS for storing clock source status. + * + * @return Status + * - #ADI_PWR_SUCCESS if the clock source is disabled. + * - #ADI_PWR_NULL_POINTER [D] if the given pointer is pointing to NULL. + + * @details Return the status of a clock source. + * + */ +ADI_PWR_RESULT adi_pwr_GetClockStatus (const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus) +{ + uint32_t val = pADI_CLKG0_OSC->CTL; + +#ifdef ADI_DEBUG + if(peStatus == NULL) + { + return ADI_PWR_NULL_POINTER; + } +#endif /* ADI_DEBUG */ + + *peStatus = ADI_CLOCK_SOURCE_DISABLED; + + switch(eClockSource) + { + case ADI_CLOCK_SOURCE_HFOSC: + if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_HFXTAL: + if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_LFXTAL: + if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_LFOSC: + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + break; + + /* Since the clock through GPIO is supplied externally we cannot get + the clock status for GPIO */ + case ADI_CLOCK_SOURCE_GPIO: + default: + *peStatus = ADI_CLOCK_SOURCE_ID_NOT_VALID; + break; + + } /* end switch */ + + return ADI_PWR_SUCCESS; +} + +/*! + * @brief Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL. + * + * @param[in] eIrq : Specify which interrupt need to be enable/disabled. + @param[in] bEnable : Specifies to enable/disable the specified interrupt. + * + * @return Status + * - #ADI_PWR_SUCCESS Enabled the specified interrupt. + * + * @sa adi_pwr_SetVoltageRange() + */ + +ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable) +{ + ADI_INT_STATUS_ALLOC(); + volatile uint32_t *pReg = NULL; + uint32_t tmp; + + switch(eIrq) + { +#if defined(__ADUCM4x50__) + /*! Interrupt for root clock monitor and Clock Fail */ + case ADI_PWR_ROOT_CLOCK_MON_IEN: + pReg = &pADI_CLKG0_OSC->CTL; + break; +#endif /* __ADUCM4x50__ */ + + /*! Interrupt for LFXTAL clock monitor and Clock Fail */ + case ADI_PWR_LFXTAL_CLOCK_MON_IEN: + pReg = &pADI_CLKG0_OSC->CTL; + break; + + /*! Interrupt when LFXTAL clock becomes stable/unstable */ + case ADI_PWR_LFXTAL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL0; + break; + + /*! Interrupt when HFXTAL clock becomes stable/unstable */ + case ADI_PWR_HFXTAL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL0; + break; + + /*! Interrupt when PLL-LOCK/PLL-UNLOCK */ + case ADI_PWR_PLL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL3; + break; + + default: + break; + } + + ADI_ENTER_CRITICAL_REGION(); + + tmp = *pReg; + + if(bEnable == true) + { + tmp |= (uint32_t)eIrq; + } + else + { + tmp &= ~((uint32_t)eIrq); + } + + /* If we have to write to oscillator control register unlock it */ + if(pReg == &pADI_CLKG0_OSC->CTL) + { + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + } + *pReg = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Program PLL frequency. + * + * @param[in] nDivFactor PLL divider(M). + * @param[in] nMulFactor PLL Multiplier(N) + * @param[in] bDiv2 PLL DIV2 parameter. + * @param[in] bMul2 PLL DIV2 parameter. + * + * @return Status + * - #ADI_PWR_SUCCESS if the PLL has been programmed successfully. + * - #ADI_PWR_OPERATION_NOT_ALLOWED [D] if trying to program SPLL and SPLL drives the system clock. + * - #ADI_PWR_INVALID_CLOCK_ID [D] if the clock identifier does not match either PLL. + * + * @details Program PLL frequency (parameters M, N, DIV2) forSystem PLL(SPLL). + * + * SPLL = input clock * ["(N * (1+ bMul2 )" / "((1+bDiv2)*M)" ] + * where input clock can be HFOSC or HFXTAL. + */ +ADI_PWR_RESULT adi_pwr_SetPll(uint8_t nDivFactor, const uint8_t nMulFactor, const bool bDiv2, const bool bMul2) +{ + uint32_t val, cfg = 0u; + uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* Check if multiplication factor and division factor is more than 6 bits */ + if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* Check if the PLL is multipexed in as root clock source, parameters should not change in that case */ + if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) == + ((uint32_t)((ADI_CLOCK_MUX_ROOT_SPLL - ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX))) + { + return ADI_PWR_OPERATION_NOT_ALLOWED; + } +#endif + + if(nTempDivFactor < MINIMUM_PLL_DIVIDER) + { + nTempDivFactor = MINIMUM_PLL_DIVIDER; + } + if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER) + { + nTempMulFactor = MINIMUM_PLL_MULTIPLIER; + } + + cfg = (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL); + + if(bDiv2 == true) + { + cfg |= (1u <CTL3; + val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL); + val |= cfg; + pADI_CLKG0_CLK->CTL3 = val; + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + * @brief Enable/Disable the power management interrupt. + * + * @param[in] eIrq : Specify which interrupt need to be enable/disabled. + @param[in] bEnable : Specifies to enable/disable the interrupt. + * + * @return Status + * - #ADI_PWR_SUCCESS Enabled the specified interrupt. + * - #ADI_PWR_FAILURE [D] Enabling the battery monitoring interrupt when range is set to safe range (VBAT > 2.75 ). + * + * @note : User should configure the appropriate voltage range before enabling the interrupt for battery voltage range. + * + * @sa adi_pwr_SetVoltageRange() + */ +ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable) +{ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if(((pADI_PMG0->IEN & BITM_PMG_IEN_RANGEBAT) == 0u) || (eIrq != ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN)) + { + return(ADI_PWR_FAILURE); + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if(bEnable == true) + { + pADI_PMG0->IEN |= (uint32_t)eIrq; + } + else + { + pADI_PMG0->IEN &= ~(uint32_t)(eIrq); + } + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + + +/*! + * @brief Enable/disable LFXTAL bypass mode. + * + @param[in] bEnable : Specifies to enable/disable the LFXTAL bypass mode + *\n true: To enable LFXTAL bypass mode. + * \n false: To disable LFXTAL bypass mode. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL bypass mode. + * - #ADI_PWR_FAILURE[D] Failed to Enable/Disable LFXTAL bypass mode. + * + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass(const bool bEnable) +{ + volatile uint32_t nDelay = 0xFFFFFFu; + if(bEnable == true) + { + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Disable the LFXTAL */ + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_EN); + /* Wait till status de-asserted. */ + while(nDelay != 0u) + { + if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Enable the BYPASS mode */ + pADI_CLKG0_OSC->CTL |= (BITM_CLKG_OSC_CTL_LFX_BYP); + /* Wait till status asserted. */ + nDelay = 0xFFFFFFu; + while(nDelay != 0u) + { + if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK)) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + + } + else + { + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Disable the BYPASS mode */ + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_BYP); + /* Wait till status de-asserted. */ + while(nDelay != 0u) + { + if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + } + + return(ADI_PWR_SUCCESS); +} + + +#if defined(__ADUCM4x50__) +/*! + * @brief Enables or disables the LFXTAL Robust mode. + * The Robust mode enables the LFXTAL oscillator to work also when an additional resistive + * load is placed between the crystal pins and GND. This feature is capable of tolerating + * the presence of impurities on the PCB board, where these impurities allow a high-resistance + * leakage path from the crystal pins to ground, which can cause problems to the circuit operation + * + * @param[in] bEnable : Flag which indicates whether to enable or disable LFXTAL Robust mode. + true - Enable Robust mode. + false - Disable Robust mode. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL Robust mode. + * + * @sa adi_pwr_SetLFXTALRobustModeLoad() + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_ROBUST_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_ROBUST_EN); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Enable/Disable the LFXTAL Fail Auto switch. + * Enables/Disable automatic Switching of the LF Mux to LF OSC on LF XTAL Failure. + * + * @param[in] bEnable : Flag which indicates whether to enable/disable LFXTAL Auto switch. + * true - Enable LFXTAL Auto switch. + * false - Disable LFXTAL Auto switch. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL Auto switch mode. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN); + } + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Sets the LFXT Robust Mode Load. + * Selects the amount of loading tolerated when LFXTAL robust mode is enabled. + * + * @param[in] eLoad : Amount of loading tolerance required. + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load tolerance for LFXTAL Robust mode. + * + * @sa adi_pwr_EnableLFXTALRobustMode() + */ +ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( const ADI_PWR_LFXTAL_LOAD eLoad ) +{ + uint32_t tmp; + + tmp = pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFX_ROBUST_LD; + tmp |= ((uint32_t)eLoad) << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD; + + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + pADI_CLKG0_OSC->CTL = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief To enable/disable auto switching of root clock to HFOSC upon detection of Root clock failure. + * This feature is valid only when the ROOT clock monitor is enabled. The root clock monitoring + * can be enabled by using the API #adi_pwr_EnableClockInterrupt. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable Root clock auto switch. + * true - Enable Root clock auto switch. + false - Disable Root clock auto switch. + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load tolerance for LFXTAL Robust mode. + * + * @sa adi_pwr_EnableClockInterrupt() + */ +ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Sets the HF Oscillator divide factor. + * + * Sets the divide factor for the clocks derived from the HF oscillator clock. + * + * @param[in] eDivFactor : HF Clock divide factor to be set. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the clock divide factor for HF Oscillator. + * + * @note When the HF Oscillator auto divide by 1 is set, the divide factor set is automatically + * changed to 1 when coming out of Flexi mode. Application should set it back to the + * required divide after coming out of Flexi mode. + * + * @sa adi_pwr_EnableHFOscAutoDivBy1() + */ +ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( const ADI_PWR_HFOSC_DIV eDivFactor ) +{ + uint32_t tmp; + + tmp = (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL); + tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL); + pADI_CLKG0_CLK->CTL2 = tmp; + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enable or disable the HF oscillator automatic divide by 1 during wakeup from Flexi mode. + * + * This is used to enable/disable the fast wakeup from Flexi power mode. When the fast wakeup + * from Flexi mode is enabled, the frequency undivided 26MHz HF oscillator clock itself will + * be used during the wake up. The undivided HFOSC clock is selected automatically by setting + * the HF oscillator divide factor to 1. This updated divided by 1 clock selection will remain + * same until the new divider value is set. + * + * When disabled the HF Oscillator divide factor will remain unchanged during the wakeup. + * + * @param[in] bEnable : Flag which indicates whether HF oscillator automatic divide by 1 is enabled/disabled. + * 'true' - To enable automatic divide by 1. + * 'false' - To disable automatic divide by 1. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully enable/disabled HF Oscillator automatic divide by 1. + * + * @sa adi_pwr_SetHFOscDivFactor() + */ +ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( const bool bEnable ) +{ + if(bEnable == true) + { + pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN; + } + else + { + pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Set the clock output through the GPIO. + * + * @param[in] eClockOutput : Clock to be output through the GPIO pin. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the GPIO clock output. + */ +ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput( const ADI_CLOCK_OUTPUT_ID eClockOutput ) +{ + uint32_t tmp; + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT); + tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT); + pADI_CLKG0_CLK->CTL0 = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Enable or disable the HPBuck Low Power mode. + * The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode + * and low power modules such as Timer, Beeper only are enabled. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable HPBuck low power mode. + * 'true' - Enable HPBuck low power mode. + * 'false' - Disable HPBuck low power mode. + * @return Status + * - #ADI_PWR_SUCCESS Successfully enabled or disabled the HPBuck low power mode. + */ +ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( const bool bEnable ) +{ + if(bEnable == true) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Set the HP Buck load mode. + * + * HP Buck load mode can be set based on the system load. + * The low load mode can be set when the system is running below 26Mhz. + * The High load mode can be set when the system is running at greater than 26Mhz. + * + * @param[in] eLoadMode : Load mode to be set. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load mode. + */ +ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( const ADI_PWR_HPBUCK_LD_MODE eLoadMode ) +{ + if(eLoadMode == ADI_PWR_HPBUCK_LD_MODE_HIGH) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LD_MODE; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE); + } + + return(ADI_PWR_SUCCESS); +} +#endif /* ADUCM4x50 */ + +/*! + * @brief Enables or disables the HP Buck. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable HPBuck + * 'true' - To enable HPBuck. + * 'false' - To disable HPBuck. + * @return Status + * - #ADI_PWR_SUCCESS Successfully enabled or disabled HPBUCK successfully. + */ +ADI_PWR_RESULT adi_pwr_EnableHPBuck(const bool bEnable) +{ + if(bEnable == true) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCKEN; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCKEN); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Function to retrieve the wakeup from shut down mode status. + * + * @param[in] peStatus : Pointer to #ADI_PWR_WAKEUP_STATUS for returning the wakeup status. + * + * @return Status + * - #ADI_PWR_SUCCESS: Successfully returned the shut down status. + */ +ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS *peStatus) +{ + *peStatus =(ADI_PWR_WAKEUP_STATUS) pADI_PMG0->SHDN_STAT; + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief To Monitor voltage range of battery. + * + * @param[in] eRange : Specify the voltage range for the battery. + * + * @return Status + * - #ADI_PWR_SUCCESS: Successfully programmed battery range. + * @details + * + */ +ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange) +{ + uint32_t tmp; + + tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT); + tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT); + pADI_PMG0->IEN = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! \cond PRIVATE */ + +/* + * Interrupt handler for PLL interrupts. + */ +void PLL_Int_Handler(void) +{ + ISR_PROLOG(); + + /* As the same status word is shared between two interrupts + Crystal_osc_Int_Handler and PLL_Int_Handler + check and clear status bits handled in this handler */ + uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 & + (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK)); + + /* If a callback is registered notify the events */ + if(gpfCallbackFunction != NULL) + { + if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u) + { + /* PLL unlock event */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_UNLOCK,(void *)0); + } + else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u) + { + /* PLL lock event */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_LOCK,(void *)0); + } + else + { + /* Do nothing */ + } + } + + /* Clear the status bits */ + pADI_CLKG0_CLK->STAT0 = nStatus; + + ISR_EPILOG(); +} + +/* + * Interrupt handler for oscillator interrupts. + */ +void Crystal_osc_Int_Handler(void) +{ + ISR_PROLOG(); + + /* As the same status word is shared between two interrupts + Crystal_osc_Int_Handler and PLL_Int_Handler + check and clear status bits handled in this handler */ + uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 & + (BITM_CLKG_CLK_STAT0_HFXTALNOK | + BITM_CLKG_CLK_STAT0_HFXTALOK | + BITM_CLKG_CLK_STAT0_LFXTALOK | + BITM_CLKG_CLK_STAT0_LFXTALNOK)); +#if defined(__ADUCM4x50__) + /* Check if the interrupt was generated due to failure in Root Clock or LFXTAL */ + uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL & (BITM_CLKG_OSC_CTL_LFX_FAIL_STA | + BITM_CLKG_OSC_CTL_ROOT_FAIL_STA | + BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA | + BITM_CLKG_OSC_CTL_LFX_AUTSW_STA )); +#endif /* __ADUCM4x50__ */ + + uint32_t nEvent = 0u; + + + if(gpfCallbackFunction != NULL) + { + /* Is the interrupt caused due to HFXTAL or LFXTAL status */ + if(nClkStatus != 0u) + { + if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK; } + else { /* do nothing */ } + + if(nEvent != 0u) { gpfCallbackFunction( gpPowcbParam, nEvent, (void *)0u); } + + } +#if defined(__ADUCM4x50__) + /* Or is the interrupt caused due to Root Clock or LFXTAL failure status */ + else if(nOscStatus != 0u) + { + /* Did the LFXTAL failed */ + if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u) + { + /* Notifiy LFXTAL failure */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, (void *)0u); + + /* Did the HW auto switched to LFOSC due to LFXTAL failure */ + if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u) + { + /* Notify about the auto switch to LFOSC */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, (void *)0u); + } + } + /* Did the root clock failed */ + else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u) + { + /* Indicate about the root clock failure */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, (void *)0u); + + /* Did the HW auto switched to HFOSC due to root clock failure */ + if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u) + { + /* Notify about auto switch to HFOSC */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, (void *)0u); + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } +#endif /* __ADUCM4x50__ */ + } + + /* Clear the staus bits */ + if(nClkStatus != 0u) + { + pADI_CLKG0_CLK->STAT0 = nClkStatus; + } +#if defined(__ADUCM4x50__) + else if(nOscStatus != 0u) + { + /* Write the oscillator key to clear the status bits */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + /* Clear only status bits */ + pADI_CLKG0_OSC->CTL |= nOscStatus; + } + else + { + /* Do nothing */ + } +#endif /* __ADUCM4x50__ */ + + ISR_EPILOG(); +} + +/* + * Interrupt handler for battery voltage interrupt. + */ +void Battery_Voltage_Int_Handler(void) +{ + ISR_PROLOG(); + uint32_t nStatus = pADI_PMG0->PSM_STAT; + + if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u) + { + if(gpfCallbackFunction != NULL) + { + gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (void *)0); + } + pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR); + } + ISR_EPILOG(); +} + +/* + * Interrupt handler for battery voltage interrupt. + */ +void Vreg_over_Int_Handler(void) +{ + ISR_PROLOG(); + uint32_t nStatus = pADI_PMG0->PSM_STAT; + + if(gpfCallbackFunction != NULL) + { + if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u) + { + gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_OVER_VOLTAGE, NULL); + } + if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u) + { + gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, NULL); + } + } + pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR)); + ISR_EPILOG(); +} + +/*! \endcond */ +/*! + @brief Puts the processor into given low power mode. + + @param[in] PowerMode One of the ADI_PWR_POWER_MODE enum values, defining the specific + low-power modes to use. + + @param[in,out] pnInterruptOccurred + Control parameter selection low-power operation. Either a NULL pointer + for automatic hardware-based sleeping between interrupts, or a pointer + to uint32_t for software looping sleep between interrupts. + + If a pointer to uint32_t is passed in, the integer must be \b 0 on entry, + and will be set to \b 0 on exit. + + When a NULL is passed, it means the application wants the low-power + implementation to use the automatic "sleep-on-exit" hardware sleep + mode in which wakeup interrupts are dispatched and then automatically + put the processor back to sleep on exit. All interrupts execute the + same WFI instruction (no looping) under hardware control, which results + in a faster re-sleep than the software mode. + + When a non-NULL value is passed, it is interpreted as a pointer to a + shared integer application control variable allowing the wake-up + interrupts to control whether/when the control loop should re-sleep the + processor as each interrupt exits. Any interrupt that sets the variable + will cause the sleep loop to exit. Otherwise, exiting interrupts will + cause the core to re-sleep until the variable is set. Each interrupt executes + a different WFI instruction inside a software loop (slower re-sleep). + + @param[in] PriorityMask A right-justified (un shifted) wakeup interrupt priority mask, corresponding + to the programmable interrupt priority encoding scheme defined by the Cortex + NVIC controller. The \a PriorityMask value blocks interrupts with an equal + or lower priority than the specified level, such that only higher-priority + interrupts (less in numerical value) than the priority mask awake the + processor. A zero-valued \a PriorityMask disables interrupt masking. + + @return Status + - #ADI_PWR_SUCCESS If successfully put the processor into low power mode. + - #ADI_PWR_INVALID_PARAM[D] PriorityMask contains unimplemented hardware bits. + + + + Puts the processor into a low-power mode with interrupt-based wakeup(s). Applications specify the low-power + mode, a pointer to an application-defined interrupt variable, and an interrupt priority mask controlling the + interrupt priority level that may awake the processor. + + @par pnInterruptOccurred + When NULL, the processor is automatically put back to sleep as awaking interrupts exit. This mode employs + the hardware "sleep-on-exit" system control register bit: SLEEPONEXIT_BIT in conjunction with the "wait-for- + interrupt" (WFI) instruction to implement a persistent sleep mode. + + When non-Null, a software strategy is used to control sleeping. As awakening interrupts are processed, they + can increment the interrupt controlling variable and thereby cause the sleep mode to be exited. Note that all + interrupts share a common variable and any interrupt that sets the variable will cause the sleep mode to be + exited. + + Use of the \a pnInterruptOccurred parameter provides a mechanism to resolve two potential hibernation trouble + spots: 1) the inherent race between the intended wakeup interrupt and the execution of the Wait-For-Interrupt + instruction (WFI) used to sleep the processor, and 2) unrelated interrupts (of sufficient priority) + that may terminate the wait prematurely. + + In the first case of the race condition, the race is avoided by testing the \a pnInterruptOccurred variable prior + to the WFI within a common critical section. This allows the #adi_pwr_EnterLowPowerMode() implementation + to insure the intended wakeup interrupt has not occurred already and control whether to sleep the processor. + This insures the intended wakeup interrupt has not already occurred prior to the wait, thereby eliminating the + race condition otherwise present. + + In the second case of an unrelated interrupt terminating the sleep prematurely, the problem is solved by + requiring the interrupt handler(s) which is(are) intended to awake the sleeping processor to set the + application-defined \a pnInterruptOccurred variable in their respective interrupt handler(s). This insures only those + interrupts that explicitly set the variable will break the sleeping processor out of the sleep cycle. Other + (incidental) interrupts put the processor back to sleep after the interrupt because the variable would not have been set. + This is why there is a loop around the WFI instruction. + + The \a pnInterruptOccurred variable must be initialized to zero before first use, and this should be done + prior to enabling any interrupt which may set it (otherwise interrupts may be missed). If this variable is + global or static then static initialization to zero or false will be sufficient. + + The variable should only be set, from an interrupt handler, by calling adi_pwr_ExitLowPowerMode() and passing + the variable by reference. The variable should not be assigned to directly, other than for initialization. + + #adi_pwr_EnterLowPowerMode() will always clear the variable again before returning, so it does not + need to be cleared by user code on each use. Explicitly clearing the variable, outside of #adi_pwr_EnterLowPowerMode() + runs the risk of missing interrupts. + + @par PriorityMask + A zero-valued \a PriorityMask disables interrupt masking, leaving all interrupts eligible to awake the + sleeping processor. This means that zero-valued interrupts cannot be masked. A non-zero \a PriorityMask + limits interrupts that may awake the sleeping processor to those with a higher priority level (lower + numerically) than the specified \a PriorityMask value. + + Each "programmable" peripheral interrupt has an associated priority-level register (which defaults to + zero) within the Nested Vectored Interrupt Controller (NVIC). The number of interrupt priority encoding + bits is defined by constant __NVIC_PRIO_BITS and is a fixed silicon attribute configured during chip + design. The interrupt priority-level registers range in width from 3 to 8 bits. + + This processor uses 3-bit priority encoding, allowing priority levels ranging between 0 (the highest, + default programmable priority) and 7 (the lowest). For example, if the \a PriorityMask parameter is + set to 3, only interrupts with assigned priority 0, 1, and 2 may awake the processor. Since default + priority of all programmable interrupts is 0, setting up maskable interrupts requires that they be + demoted in priority (raised numerically) relative to interrupts that are intended to awake the processor. + + @note The number of priority levels is uncorrelated with the actual number of interrupts or their position + in the Interrupt Vector Table (IVT). Interrupt priorities may be programmed individually.\n\n + + @note The priority levels are actually stored in the core as a left-justified value in an 8-bit field. + The #adi_pwr_EnterLowPowerMode() API takes care of aligning the passed \a PriorityMask value to the + core register (BASEPRI).\n\n + + @note The default priority level for all interrupts is zero, which implies it is impossible to mask interrupts + with a default zero-level priority encoding. All interrupt priorities must be managed to create meaningful + interrupt masks for low-power wakeups, as described above.\n\n + + @warning Do not modify the BASEPRI register (used for masking interrupt priority) during interrupts that take + the core out of low-power mode momentarily. The BASEPRI register is saved/restored on low-power mode + entry/exit to honor user priority requests. Interrupt-level changes to BASEPRI will be clobbered on + low-power exit as the saved value is restored.\n\n + + @sa adi_pwr_ExitLowPowerMode +*/ +ADI_PWR_RESULT adi_pwr_EnterLowPowerMode ( const ADI_PWR_POWER_MODE PowerMode, + uint32_t volatile * pnInterruptOccurred, + const uint8_t PriorityMask + ) +{ + uint32_t savedPriority; + uint32_t scrSetBits = 0u; + uint32_t scrClrBits = 0u; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + + /* verify the requested priority mask bits are right-justified and don't exceed __NVIC_PRIO_BITS in width */ + if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u) + { + return ADI_PWR_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* pre-calculate the sleep-on-exit set/clear bits */ + if(NULL == pnInterruptOccurred) { + scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk; + + /* point to private control variable when in hardware (sleep-on-exit) mode */ + pnInterruptOccurred = &gnLowPowerIntOccFlag; + } + + /* pre-calculate the deepsleep and sleep-on-exit set/clear bits */ + switch (PowerMode) { + + case ADI_PWR_MODE_ACTIVE: /* Note: this value is a "reserved" PWRMODE register code. */ + return ADI_PWR_SUCCESS; /* avoids the reserved value "1" being written to PWRMODE. */ + + case ADI_PWR_MODE_FLEXI: /* wfi without deepsleep or sleep-on-exit */ + scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + break; + + case ADI_PWR_MODE_HIBERNATE: /* wfi with deepsleep and sleep-on-exit per pnInterruptOccurred setting */ + scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP; + + break; + + case ADI_PWR_MODE_SHUTDOWN: /* wfi with both deepsleep and sleep-on-exit */ + /* Note: sleep-on-exit causes WFI to never exit and wakeup is only through system reset. */ + scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + break; + + default: + return ADI_PWR_INVALID_POWER_MODE; + + } /* end switch */ + + /* put the power mode and system control mods, as well as the WFI loop inside a critical section */ + ADI_ENTER_CRITICAL_REGION(); + + { /* these lines must be in a success-checking loop if they are not inside critical section */ + /* Uninterruptable unlock sequence */ + pADI_PMG0->PWRKEY = ADI_PMG_KEY; + + /* Clear the previous mode and set new mode */ + pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode ); + } + + /* Update the SCR (sleepdeep and sleep-on-exit bits) */ + SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits); + + /* save/restore current Base Priority Level */ + savedPriority = __get_BASEPRI(); + + /* assert caller's priority threshold (left-justified) */ + __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS)); + + /* if we are in the software looping mode, loop on the user's variable until set */ + while (0u == *pnInterruptOccurred) { + + __DSB(); /* bus sync to insure register writes from interrupt handlers are always complete before WFI */ + + /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */ + + /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt + that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not + dispatched until we get into the WFI. If that interrupt sneaks in prior to our getting to the + WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred. + */ + __WFI(); + + /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched. + This allows *pnInterruptOccurred to be set from any interrupt context. + */ + ADI_EXIT_CRITICAL_REGION(); + /* nop */ + ADI_ENTER_CRITICAL_REGION(); + + } /* end while */ + + /* ...still within critical section... */ + + (*pnInterruptOccurred)--; /* decrement the completion variable on exit */ + + /* Restore previous base priority */ + __set_BASEPRI(savedPriority); + + /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + + __DSB(); /* bus sync before re-enabling interrupts */ + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + * Companion function to #adi_pwr_EnterLowPowerMode() that allows interrupts to \n + * break out of the "FLEXI" mode in which the processor stays in \n + * sleep while peripherals are active. \n + + @param[in,out] pnInterruptOccurred + Control parameter selection low-power operation. Either a NULL pointer \n + for hardware sleep-on-exit feature, or a pointer to uint32_t for software \n + looping sleep between interrupts. + @return Status + - #ADI_PWR_SUCCESS If successfully exited from low power mode. + + * @sa adi_pwr_EnterLowPowerMode + */ +ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile * pnInterruptOccurred) +{ + ADI_INT_STATUS_ALLOC(); + + /* Manage the exit depending on pnInterruptOccurred convention... */ + /* NULL pointer means we are using the hardware sleep-on-exit feature */ + /* non-NULL pointer means we are using a software looping variable top sleep */ + + if (NULL == pnInterruptOccurred) { + + pnInterruptOccurred = &gnLowPowerIntOccFlag; /* point to private control variable in hardware mode */ + + /* clear hardware sleep-on-exit feature */ + ADI_ENTER_CRITICAL_REGION(); + + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + __DSB(); /* bus sync before interrupt exit */ + + ADI_EXIT_CRITICAL_REGION(); + } + + /* set control variable (whether hardware or software based) so WFI exits in SystemEnterLowPowerMode() */ + (*pnInterruptOccurred)++; + return ADI_PWR_SUCCESS; +} + +/* +** EOF +*/ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr_def.h new file mode 100755 index 00000000000..9ba47c90ccb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/pwr/adi_pwr_def.h @@ -0,0 +1,235 @@ +/* + ***************************************************************************** + * @file: adi_pwr_def.h + * @brief: Definitions for the system clock and power management. + *----------------------------------------------------------------------------- + * + * Copyright (c) 2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef ADI_PWR_DEF_H +#define ADI_PWR_DEF_H + + /*Power control register access key */ +#define ADI_PMG_KEY (0x4859u) + + /*Osc control register access key */ +#define ADI_OSC_KEY (0xCB14u) + + /*HCLK/PCLK minimum Divider value */ +#define CLOCK_MIN_DIV_VALUE (0x1u) + + /*HCLK/PCLK maximum Divider value */ +#define CLOCK_MAX_DIV_VALUE (32u) + + /*ADC Clock minimum Divider value */ +#define ACLK_MIN_DIV_VALUE (0x1u) + + /*ADC Clock maximum Divider value */ +#define ACLK_MAX_DIV_VALUE (511u) + +/* Minimum divider for PLL */ +#define MINIMUM_PLL_DIVIDER (0x02u) + +/* Minimum multiplier for PLL */ +#define MINIMUM_PLL_MULTIPLIER (0x08u) + +/* Maximum external clock */ +#define MAXIMUM_EXT_CLOCK (26000000u) + +/* Macro mapping from ADuCM4x50 to ADuCM302x */ +#if defined(__ADUCM302x__) + +#define BITM_CLKG_OSC_CTL_HFOSC_EN BITM_CLKG_OSC_CTL_HFOSCEN +#define BITP_CLKG_OSC_CTL_HFOSC_OK BITP_CLKG_OSC_CTL_HFOSCOK +#define BITM_CLKG_OSC_CTL_HFX_EN BITM_CLKG_OSC_CTL_LFXTALEN +#define BITM_CLKG_CLK_CTL0_PLL_IPSEL BITM_CLKG_CLK_CTL0_SPLLIPSEL +#define BITP_CLKG_CLK_CTL0_PLL_IPSEL BITP_CLKG_CLK_CTL0_SPLLIPSEL +#define BITM_CLKG_OSC_CTL_LFCLK_MUX BITM_CLKG_OSC_CTL_LFCLKMUX +#define BITP_CLKG_OSC_CTL_LFCLK_MUX BITP_CLKG_OSC_CTL_LFCLKMUX +#define BITP_CLKG_OSC_CTL_HFX_EN BITP_CLKG_OSC_CTL_HFXTALEN +#define BITM_CLKG_OSC_CTL_HFX_OK BITM_CLKG_OSC_CTL_HFXTALOK +#define BITP_CLKG_OSC_CTL_LFX_EN BITP_CLKG_OSC_CTL_LFXTALEN +#define BITM_CLKG_OSC_CTL_LFX_EN BITM_CLKG_OSC_CTL_LFXTALEN +#define BITM_CLKG_OSC_CTL_LFX_OK BITM_CLKG_OSC_CTL_LFXTALOK +#define BITP_CLKG_OSC_CTL_HFOSC_EN BITP_CLKG_OSC_CTL_HFOSCEN +#define BITM_CLKG_OSC_CTL_HFOSC_OK BITM_CLKG_OSC_CTL_HFOSCOK +#define BITM_CLKG_OSC_CTL_LFOSC_OK BITM_CLKG_OSC_CTL_LFOSCOK +#define BITM_CLKG_OSC_CTL_LFX_BYP BITM_CLKG_OSC_CTL_LFXTAL_BYPASS + +#endif /* __ADUCM302x__ */ + +#if defined(__ADUCM4x50__) + /* Default osc control register value */ +#define OSCCTRL_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLK_MUX | \ + (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSC_EN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFX_EN | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFX_EN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFX_MON_EN | \ + (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN | \ + (uint32_t) ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN | \ + (uint32_t) ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD | \ + (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE << BITP_CLKG_OSC_CTL_ROOT_MON_EN | \ + (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN ) +#else + + /* Default osc control register value */ +#define OSCCTRL_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLKMUX | \ + (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSCEN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFXTALEN | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFXTALEN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFXTAL_MON_EN ) +#endif /* __ADUCM4x50__ */ + +#if defined(__ADUCM4x50__) + /* Default clock control register-0 value */ +#define CLOCK_CTL0_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT << BITP_CLKG_CLK_CTL0_CLKOUT | \ + (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \ + (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_PLL_IPSEL | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE ) +#else +/* Default clock control register-0 value */ +#define CLOCK_CTL0_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \ + (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \ + (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_SPLLIPSEL | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE ) +#endif + + /* Default clock control register-1 value */ +#define CLOCK_CTL1_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_HCLKDIVCNT | \ + (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_PCLKDIVCNT | \ + (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_ACLKDIVCNT ) + +#if defined(__ADUCM4x50__) +/* Default clock control register-2 value */ +#define CLOCK_CTL2_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1 << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN | \ + (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL ) + +#endif /* __ADUCM4x50__ */ + + /* Default clock control register-3 value */ +#define CLOCK_CTL3_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR << BITP_CLKG_CLK_CTL3_SPLLNSEL | \ + (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2 << BITP_CLKG_CLK_CTL3_SPLLDIV2 | \ + (uint32_t) ADI_PWR_SPLL_ENABLE << BITP_CLKG_CLK_CTL3_SPLLEN | \ + (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL3_SPLLIE | \ + (uint32_t) ADI_PWR_SPLL_DIV_FACTOR << BITP_CLKG_CLK_CTL3_SPLLMSEL | \ + (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2 << BITP_CLKG_CLK_CTL3_SPLLMUL2 ) + +#if defined(__ADUCM4x50__) + /* Default clock control register-5 value */ +#define CLOCK_CTL5_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \ + (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \ + (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \ + (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \ + (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF | \ + (uint32_t) ADI_PWR_TIMER_RGB_ENABLE << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF ) +#else + /* Default clock control register-5 value */ +#define CLOCK_CTL5_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \ + (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \ + (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \ + (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \ + (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF ) +#endif + +/* Default configuration for Power supply monitor Interrupt Enable Register */ +#define PWM_INTERRUPT_CONFIG \ + ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT << BITP_PMG_IEN_VBAT | \ + (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGUNDR | \ + (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGOVR | \ + (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT << BITP_PMG_IEN_IENBAT | \ + (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT << BITP_PMG_IEN_RANGEBAT ) + + /* Default configuration for Power Mode Register */ + #define PWM_PWRMOD_CONFIG \ + ( (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING << BITP_PMG_PWRMOD_MONVBATN ) + +#if defined(__ADUCM4x50__) +/* Default configuration for HP Buck Control register */ +#define PWM_HPBUCK_CONTROL \ + ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN | \ + (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE << BITP_PMG_CTL1_HPBUCK_LD_MODE | \ + (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE ) +#else +/* Default configuration for HP Buck Control register */ +#define PWM_HPBUCK_CONTROL \ + ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN ) +#endif + + /*Selecting HFOSC as input for generating root clock*/ +#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting HFXTAL as input for generating root clock*/ +#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting SPLL as input for generating root clock*/ +#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting GPIO as input for generating root clock*/ +#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* Interrupt handler for the battery voltage interrupt */ +void Battery_Voltage_Int_Handler(void); +/* Interrupt handler for the VREG under/over voltage interrupt */ +void Vreg_over_Int_Handler(void); +/* Interrupt handler for PLL interrupts. */ +void PLL_Int_Handler(void); +/*Interrupt handler for oscillator interrupts.*/ +void Crystal_osc_Int_Handler(void); + +#endif /* ADI_PWR_DEF_H */ + + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng.c new file mode 100755 index 00000000000..c771cca5cd8 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng.c @@ -0,0 +1,796 @@ +/*! + ***************************************************************************** + * @file: adi_rng.c + * @brief: Random Number Generator Driver + *---------------------------------------------------------------------------- + * +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup RNG_Driver RNG Driver + * Random Number Generator Driver + * @{ + */ + + /*! \cond PRIVATE */ + +#include /* for 'NULL' definition */ +#include + +#include +#include +#include "adi_rng_def.h" +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ISR_PROLOG in no-OS case and others. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm143,Pm050 +#endif /* __ICCARM__ */ + +#if defined(__ADUCM4x50__) || defined(__ADUCM302x__) +#define NUM_RNG_DEVICES (1u) +#else +#error "Unsupported processor" +#endif + +/*============== D A T A ===============*/ + +/** + * Information for managing all the RNG devices available + */ +#ifdef __ICCARM__ +#pragma diag_suppress=Pm140 +#endif + +static ADI_RNG_DEV_TYPE gRNG_Device[NUM_RNG_DEVICES] = +{ + {(ADI_RNG_TypeDef*)pADI_RNG0,NULL} /* RNG0 */ +}; +#ifdef __ICCARM__ +#pragma diag_default=Pm140 +#endif + +/* Forward prototypes */ +void RNG_Int_Handler(void); + +/** Check the validity of a handle for debug mode */ +#ifdef ADI_DEBUG +#define ADI_RNG_INVALID_HANDLE(h) (&gRNG_Device[0] != (h)) +#endif + +/*! \endcond */ + +/*! + @brief Opena a Random Number Generator Device + + @param[in] nDeviceNum Device number to be opened. + @param[in] pMemory Pointer to the memory to be used by the driver. + Size of the memory should be at least #ADI_RNG_MEMORY_SIZE bytes. + @param[in] MemorySize Size of the memory passed in pMemory parameter. + @param[out] phDevice Pointer to a location in the calling function memory space to which + the device handle will be written upon successful driver initialization. + + @return Status + - #ADI_RNG_SUCCESS RNG device driver opened successfully. + - #ADI_RNG_INVALID_PARAM [D] The memory passed to the API is either NULL or its size is not sufficient. + - #ADI_RNG_ALREADY_INITIALIZED [D] The RNG is already initialized. + - #ADI_RNG_BAD_DEVICE_NUM [D] The device number is invalid. + + Initialize and allocate a RNG device for other use. The core NVIC RNG interrupt is enabled. This API + must preceed all other RNG API calls and the handle returned must be passed to all other RNG API calls. + + @note The contents of \a ppDevice will be set to NULL upon failure.\n\n + + @note The RNG device driver will clear all pending interrupts and disable all RNG + interrupts during RNG device initialization. + + @sa adi_rng_Close(). +*/ +ADI_RNG_RESULT adi_rng_Open( + uint32_t const nDeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_RNG_HANDLE* const phDevice + ) +{ + ADI_RNG_DEV_TYPE *pDevice; + + /* store a bad handle in case of failure */ + *phDevice = (ADI_RNG_HANDLE) NULL; + +#ifdef ADI_DEBUG + if (nDeviceNum >= NUM_RNG_DEVICES) + { + return ADI_RNG_BAD_DEVICE_NUM; + } + + if ((NULL == pMemory) || ( MemorySize < (uint32_t) ADI_RNG_MEMORY_SIZE)) + { + return ADI_RNG_INVALID_PARAM; + } + assert (ADI_RNG_MEMORY_SIZE == sizeof(ADI_RNG_DEV_DATA_TYPE)); +#endif + + /* local pointer to instance data */ + pDevice = &gRNG_Device[nDeviceNum]; + +#ifdef ADI_DEBUG + if (NULL != pDevice->pData) + { + return ADI_RNG_ALREADY_INITIALIZED; + } +#endif + + /* Set the internal device data */ + pDevice->pData = pMemory; + + /* initialize internal device data */ + pDevice->pData->IRQn = RNG0_EVT_IRQn; + pDevice->pData->CBFunc = NULL; + + /* clear any pending interrupts. Both bits are write 1 to clear */ + pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK; + + /* Set the RNG register based on static configuration */ + pDevice->pRNG->CTL = (uint16_t)RNG0_CFG_ONLY_8_BIT << BITP_RNG_CTL_SINGLE; + pDevice->pRNG->LEN = (RNG0_CFG_LENGTH_RELOAD << BITP_RNG_LEN_RELOAD) + | (RNG0_CFG_LENGTH_PRESCALER << BITP_RNG_LEN_PRESCALE); + + /* The interrupt handler only gets used in the case of callback mode so its + * enabling only happens in the adi_rng_RegisterCallBack API. + */ + NVIC_ClearPendingIRQ(pDevice->pData->IRQn); + + /* store handle at application handle pointer */ + *phDevice = pDevice; + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Uninitializes and deallocates the RNG device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * Uninitialize and release an allocated RNG device for other use. The core NVIC RNG interrupt is disabled. + * + * @sa adi_rng_Open(). + */ +ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ(pDevice->pData->IRQn); + pDevice->pData = NULL; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Enables/Disables the RNG device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] bFlag Flag to specify whether to enable or disable RNG device. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_Enable (ADI_RNG_HANDLE const hDevice, bool const bFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)) { + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { + pDevice->pRNG->CTL |= BITM_RNG_CTL_EN; + } else { + pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_EN); + } + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Enables/Disables Buffering for RNG. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] bFlag Flag to specify whether to enable or disable buffering for RNG device. + * When buffering is enabled, adi_rng_GetRngData returns 32-bit values. + * When buffering is disabled the API returns 8-bit values. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + * @sa adi_rng_GetRngData(). + */ +ADI_RNG_RESULT adi_rng_EnableBuffering (ADI_RNG_HANDLE const hDevice, bool const bFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)) { + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { + pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_SINGLE); + } else { + pDevice->pRNG->CTL |= BITM_RNG_CTL_SINGLE; + } + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Sets the reload and prescale value for the sample counter. + * The Sample Length will be nLenReload*2^nLenPrescaler. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] nLenPrescaler Prescaler value for the sample counter (0-10). + * @param[in] nLenReload Reload value for the sample counter (0-4095) + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_SetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t const nLenPrescaler, + uint16_t const nLenReload + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ( (nLenPrescaler > 10u) + || ((0u == nLenPrescaler) && (0u == nLenReload)) + || (nLenReload > 4095u)) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + /* Set the sample reload and prescaler value */ + pDevice->pRNG->LEN = (uint16_t)((uint16_t)(nLenReload << BITP_RNG_LEN_RELOAD) & BITM_RNG_LEN_RELOAD) + | (uint16_t)((uint16_t)(nLenPrescaler << BITP_RNG_LEN_PRESCALE) & BITM_RNG_LEN_PRESCALE); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieves the current state of RNG data/CRC accumulator register. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pbFlag Pointer to an application-defined boolean variable into which to write the result: + * - true = RNG data is ready to be read. + * - false = RNG data is not ready. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * Retrieve the current state of RNG data/CRC accumulator register. The register holds the final entropy value + * accumulated by RNG and it should to read only when the data is ready. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRngData(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetRdyStatus (ADI_RNG_HANDLE const hDevice, bool* const pbFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pbFlag) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + /* Get the RNG Ready status bit */ + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) != 0u) + { + *pbFlag = true; + } + else + { + *pbFlag = false; + } + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve whether the RNG oscillator output is stuck at a constant value + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pbFlag Pointer to an application-defined boolean variable into which to write the result: + * - true = RNG oscillator is stuck at a constant value. + * - false = RNG oscillator is not stuck at a constant value. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRngData(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetStuckStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (pDevice->pData == NULL) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pbFlag) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + /* Get the stuck status bit */ + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_STUCK) != 0u) + { + *pbFlag = true; + } + else + { + *pbFlag = false; + } + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieve the current value of the RNG data register. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] pRegData Pointer to an application-defined variable into which to write the result. + * Only lower 8-bit is valid if buffering is not enabled + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_PARAM [D] pRegData is a NULL pointer. + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + * + * Retrieve the current value of RNG data register. If the buffering is enabled all 32-bit of value written to + * pRegData is valid else only the lower 8-bit is valid. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRdyStatus(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetRngData (ADI_RNG_HANDLE const hDevice, uint32_t* const pRegData) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pRegData) { + return ADI_RNG_INVALID_PARAM; + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the RNG CRC accumulator value */ + *pRegData = pDevice->pRNG->DATA; + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieve the current RNG Oscillator count. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] pOscCount Pointer to an application-defined variable into which to write the result. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetOscCount (ADI_RNG_HANDLE const hDevice, uint32_t* const pOscCount) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pOscCount) { + return (ADI_RNG_INVALID_PARAM); + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the oscillator count high count */ + *pOscCount = pDevice->pRNG->OSCCNT; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve the current RNG Oscillator difference value for the given index. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] nIndex Index of the difference register. + * @param[out] pOscDiff Pointer to an application-defined variable into which to + * write the oscillator difference value for the given index. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_Rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetOscDiff ( + ADI_RNG_HANDLE const hDevice, + uint32_t const nIndex, + uint8_t* const pOscDiff + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ((NULL == pOscDiff) || (nIndex > 3u)) { + return( ADI_RNG_INVALID_PARAM ); + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the Osc Difference Register */ + *pOscDiff = (uint8_t)pDevice->pRNG->OSCDIFF[nIndex]; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve the current RNG sample length prescale and reload value configured in the device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pLenPrescaler Pointer to an application-defined variable into which the prescaler value is written. + * @param[out] pLenReload Pointer to an application-defined variable into which the reload value for the sample counter is written. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t* const pLenPrescaler, + uint16_t* const pLenReload + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ((NULL == pLenPrescaler) || (NULL == pLenReload)) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + *pLenPrescaler = (pDevice->pRNG->LEN & BITM_RNG_LEN_PRESCALE) >> BITP_RNG_LEN_PRESCALE; + *pLenReload = (pDevice->pRNG->LEN & BITM_RNG_LEN_RELOAD) >> BITP_RNG_LEN_RELOAD; + + return ADI_RNG_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +***************************************** CALLBACKS ****************************************** +***************************************** AND ****************************************** +***************************************** INTERRUPT ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + @brief RNG Application callback registration API. + + @param[in] hDevice Device handle obtained from #adi_rng_Open(). + @param[in] cbFunc Application callback address; the function to call on the interrupt. + @param[in] pCBParam Application handle to be passed in the call back. + + @return Status + - #ADI_RNG_SUCCESS The callback is successfully registered. + - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + + Registers an application-defined callback \a cbFunc function address of type ADI_CALLBACK with the RNG device driver. + Callbacks are made in response to received RNG interrupts. + + The callback to the application is made in context of the originating interrupt (i.e., the RNG driver's + RNG interrupt handler that is registered in the system's interrupt vector table). Extended processing + during the callback (an extension of the RNG's interrupt handler) is discouraged so as to avoid lower-priority + interrupt blocking. Also, any register read-modify-write operations should be protected using the + ADI_ENTER_CRITICAL_REGION()/ADI_EXIT_CRITICAL_REGION() pair to prevent higher-priority interrupts from modifying + said register during the read-modify-write operation. + + @note CALLBACKS: RNG interrupt callbacks are \b disabled by default during RNG device driver + initialization (#adi_rng_Open()). The application uses the #adi_rng_RegisterCallback() + API to request an application-defined callback from the RNG device driver. The RNG device + driver clears the interrupt when the callback exits. + The application callback should avoid extended processing + during callbacks as the callback is executing context of the initiating interrupt and will + block lower-priority interrupts. If extended application-level interrupt processing is + required, the application should schedule it for the main application loop and exit the + callback as soon as possible.\n + + + @sa adi_rng_Open(). +*/ +ADI_RNG_RESULT adi_rng_RegisterCallback ( + ADI_RNG_HANDLE hDevice, + ADI_CALLBACK cbFunc, + void *pCBParam) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + /* save the callback info */ + pDevice->pData->CBFunc = cbFunc; + pDevice->pData->pCBParam = pCBParam; + + if (NULL != cbFunc) { + /* enable RNG interrupts in NVIC */ + NVIC_EnableIRQ(pDevice->pData->IRQn); + } else { + NVIC_DisableIRQ(pDevice->pData->IRQn); + } + + return ADI_RNG_SUCCESS; +} + +/*! \cond PRIVATE */ +/* RNG driver interrupt handler. Overrides weak default handler in startup file */ +void RNG_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_RNG_DEV_TYPE *pDevice = &gRNG_Device[0]; + register uint16_t candidate; + + /* if we have an initialized driver... */ + if (NULL != pDevice->pData) + { + /* if we have a registered callback */ + if (NULL != pDevice->pData->CBFunc) + { + ADI_INT_STATUS_ALLOC(); + + ADI_ENTER_CRITICAL_REGION(); + /* read status register without other interrupts in between */ + candidate = pDevice->pRNG->STAT; + ADI_EXIT_CRITICAL_REGION(); + + /* Only have bits in stat that are necessary */ + candidate = candidate & (BITM_RNG_STAT_STUCK | BITM_RNG_STAT_RNRDY); + + while (0u != candidate) { + uint32_t nEvent; + + if (0u != (candidate & BITM_RNG_STAT_RNRDY)) { + nEvent = ADI_RNG_EVENT_READY; + candidate &= (uint16_t)~BITM_RNG_STAT_RNRDY; + } else if (0u != (candidate & BITM_RNG_STAT_STUCK)) { + nEvent = ADI_RNG_EVENT_STUCK; + candidate &= (uint16_t)~BITM_RNG_STAT_STUCK; + } else { + break; + } + + pDevice->pData->CBFunc ( + pDevice->pData->pCBParam, + nEvent, + NULL + ); + } + + pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK; + } + } + ISR_EPILOG(); +} +/*! \endcond */ + +/* +** EOF +*/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng_def.h new file mode 100755 index 00000000000..462861d976a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rng/adi_rng_def.h @@ -0,0 +1,69 @@ +/*! + ***************************************************************************** + * @file: adi_rng_def.h + * @brief: Random Number Generator Driver private data structures + *---------------------------------------------------------------------------- + * +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_RNG_DEF_H +#define ADI_RNG_DEF_H + + /*! \cond PRIVATE */ + + +/*! RNG device internal instance data structure */ +typedef struct __ADI_RNG_DEV_DATA_TYPE +{ + IRQn_Type IRQn; /*!< RNG interrupt number */ + ADI_CALLBACK CBFunc; /*!< Callback function */ + void *pCBParam; /*!< Callback parameter */ +} ADI_RNG_DEV_DATA_TYPE; + +/*! RNG device internal data structure */ +typedef struct __ADI_RNG_DEV_TYPE +{ + volatile ADI_RNG_TypeDef *pRNG; /*!< MMR address for this RNG */ + ADI_RNG_DEV_DATA_TYPE *pData; /*!< Pointer to instance data */ +} ADI_RNG_DEV_TYPE; + + +/*! \endcond */ +#endif /* ADI_RNG_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc.c new file mode 100755 index 00000000000..3efa64d9115 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc.c @@ -0,0 +1,2673 @@ +/*! + ***************************************************************************** + * @file: adi_rtc.c + * @brief: Real-Time Clock Device Implementations. + * @version: $Revision: 35155 $ + * @date: $Date: 2016-07-26 13:09:22 -0400 (Tue, 26 Jul 2016) $ + *---------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \addtogroup RTC_Driver RTC Driver + * @{ + * @brief Real Time Clock (RTC) Driver + * @details The RTC driver manages all instances of the RTC peripheral. + * @note The application must include drivers/rtc/adi_rtc.h to use this driver + */ + + +/*! \cond PRIVATE */ + +#if defined(__ADUCM302x__) +#define BITP_CLKG_OSC_CTL_LFX_FAIL_STA BITP_CLKG_OSC_CTL_LFX_FAIL_STAT +#endif /* __ADUCM302x__ */ + +#if defined ( __ADSPGCC__ ) +#define UNUSED __attribute__ ((unused)) +#else +#define UNUSED +#endif + +#include /* for 'NULL" definition */ +#include +#include +#include + + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm109 (rule 20.12): the time handling functions of library shall not be used +* Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused +* Needed to implement the functions here. +* +* Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types +* The rule makes an exception for valid expressions. +* +* Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators +* The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused +* +* Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand +* The behaviour as described is correct +* +* Pm031: bitwise operations shall not be performed on signed integer types +* Device drivers often require bit banging on MMRs that are defined as signed + +*/ +#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031 +#endif /* __ICCARM__ */ +/*! \endcond */ + + +#include + + +/*! \cond PRIVATE */ + + +#include "adi_rtc_data.c" + + +#if defined(__ADUCM302x__) +#define BITP_RTC_SSMSK_SS1MSK BITP_RTC_SSMSK_SSMSK +#endif /* __ADUCM302x__ */ + +#if defined(__ADUCM4x50__) + +/* Data structures used to manage the enabling of all RTC interrupts */ +static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u; + +struct xxx +{ + uint16_t *cr; + uint16_t bitPositionl; +} + +Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] = +{ + { &cr0, BITP_RTC_CR0_ALMINTEN }, + { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, + { &cr0, BITP_RTC_CR0_ISOINTEN }, + { &cr0, BITP_RTC_CR0_WPNDERRINTEN }, + { &cr0, BITP_RTC_CR0_WSYNCINTEN }, + { &cr0, BITP_RTC_CR0_WPNDINTEN }, + { &cr1, BITP_RTC_CR1_CNTINTEN }, + { &cr1, BITP_RTC_CR1_PSINTEN }, + { &cr1, BITP_RTC_CR1_TRMINTEN }, + { &cr1, BITP_RTC_CR1_CNTROLLINTEN }, + { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN }, + { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN }, + { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA }, + { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN}, + { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN} + +}; +#elif defined(__ADUCM302x__) + +/* Data structures used to manage the enabling of all RTC interrupts */ +static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u; + +struct xxx +{ + uint16_t *cr; + uint16_t bitPositionl; +} + +Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] = +{ + { &cr0, BITP_RTC_CR0_ALMINTEN }, + { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, + { &cr0, BITP_RTC_CR0_ISOINTEN }, + { &cr0, BITP_RTC_CR0_WPNDERRINTEN }, + { &cr0, BITP_RTC_CR0_WSYNCINTEN }, + { &cr0, BITP_RTC_CR0_WPNDINTEN }, + { &cr1, BITP_RTC_CR1_CNTINTEN }, + { &cr1, BITP_RTC_CR1_PSINTEN }, + { &cr1, BITP_RTC_CR1_TRMINTEN }, + { &cr1, BITP_RTC_CR1_CNTROLLINTEN }, + { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN }, + { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN }, +}; +#else +#error RTC is not ported for this processor +#endif + + +/* Forward prototypes */ +void RTC0_Int_Handler(void); +void RTC1_Int_Handler(void); + + + +#ifdef ADI_DEBUG +static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice) +{ + /* Return code */ + ADI_RTC_RESULT nResult = ADI_RTC_INVALID_HANDLE; + uint32_t i; + for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++) + { + if(aRTCDeviceInfo[i].hDevice == pInDevice) + { + return(ADI_RTC_SUCCESS); + } + } + return (nResult); +} +#endif +/*! \endcond */ + +/*! + @brief RTC Initialization + + * @param[in] DeviceNumber The RTC device instance number to be opened. + * @param[in] pDeviceMemory The pointer to the device memory passed by application. + * @param[in] MemorySize The memory size passed by application. + * @param[out] phDevice The pointer to a location where the handle to the opened RTC device is written. + @return Status + - #ADI_RTC_SUCCESS RTC device driver initialized successfully. + - #ADI_RTC_INVALID_INSTANCE [D] The RTC instance number is invalid. + - #ADI_RTC_FAILURE General RTC initialization failure. + + The RTC controller interrupt enable state is unaltered during driver initialization. + Use the #adi_rtc_EnableInterrupts API to manage interrupting. + + @note The contents of phDevice will be set to NULL upon failure.\n\n + + @note On #ADI_RTC_SUCCESS the RTC device driver is initialized and made ready for use, + though pending interrupts may be latched. During initialization, the content of the + various RTC control, count, alarm and status registers are untouched to preserve prior + RTC initializations and operation. The core NVIC RTC interrupt is enabled.\n\n + + + @note SAFE WRITES: The "safe write" mode is enabled by default and can be changed using the macro + "ADI_RTC_CFG_ENABLE_SAFE_WRITE" defined in adi_rtc_config.h file. + + @sa adi_rtc_Enable(). + @sa adi_rtc_EnableInterrupts(). + @sa adi_rtc_SetCount(). + @sa adi_rtc_Close() +*/ +ADI_RTC_RESULT adi_rtc_Open( + uint32_t DeviceNumber, + void *pDeviceMemory, + uint32_t MemorySize, + ADI_RTC_HANDLE *phDevice + ) +{ + ADI_RTC_DEVICE *pDevice = pDeviceMemory; + + /* store a bad handle in case of failure */ + *phDevice = (ADI_RTC_HANDLE) NULL; + +#ifdef ADI_DEBUG + if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE) + { + return ADI_RTC_INVALID_INSTANCE; + } + assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE)); + if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL) + { + return ADI_RTC_IN_USE; + } + if(MemorySize < ADI_RTC_MEMORY_SIZE) + { + return(ADI_RTC_FAILURE); + } +#endif + + memset(pDeviceMemory,0,MemorySize); + /* initialize device data entries */ + pDevice->pRTCRegs = aRTCDeviceInfo[DeviceNumber].pRTCRegs; + + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + pDevice->pRTCRegs->CR0 = 0u; + pDevice->pRTCRegs->CR1 = 0u; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0) + + pDevice->pRTCRegs->SR0 = ADI_RTC_SR3_IRQ_STATUS_MASK; + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0) + + pDevice->pRTCRegs->CNT0 = 0u; + pDevice->pRTCRegs->CNT1 = 0u; + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCNT0) + + /* local pointer to instance data */ + aRTCDeviceInfo[DeviceNumber].hDevice = pDevice; + pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber]; + + /* Use static configuration to initialize the RTC */ + rtc_init(pDevice,&aRTCConfig[DeviceNumber]); + + /* store handle at application handle pointer */ + *phDevice = pDevice; + pDevice->eIRQn = aRTCDeviceInfo[DeviceNumber].eIRQn; + /* Enable RTC interrupts in NVIC */ + NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn)); + + return ADI_RTC_SUCCESS; /* initialized */ +} + + +/*! + * @brief Uninitialize and deallocate an RTC device. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Uninitialize and release an allocated RTC device for other use. The core NVIC RTC interrupt is disabled. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ( pDevice->eIRQn); + + pDevice->pRTCRegs = NULL; + pDevice->pfCallback = NULL; + pDevice->pCBParam = NULL; + pDevice->cbWatch = 0u; + + pDevice->pDeviceInfo->hDevice = NULL; + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +**************************************** ENABLE APIS ******************************************* +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Enable RTC alarm. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag to enable/disable alarm logic. + * - true : Enable alarm logic. + * - false : Disable alarm logic. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable operation of RTC internal alarm logic. + * + * Alarm events and interrupt notifications are gated by enabling the alarm logic. + * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled + * to have been set. + * + * The alarm is relative to some future alarm value match against the RTC counter. + * + * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_GetCount(). + * @sa adi_rtc_SetAlarm(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC alarm enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_ALMEN; + } + else + { + pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable MOD60 RTC alarm. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag for enable/disable mod60 alarm logic. + * - true : Enable mod60 alarm logic. + * - false : Disable mod60 alarm logic. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable operation of RTC internal MOD60 alarm logic. + * + * Alarm events and interrupt notifications are gated by enabling the alarm logic. + * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled + * to have been set. + * + * The alarm is relative to some future alarm value match against the RTC counter. + * + * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_GetCount(). + * @sa adi_rtc_SetAlarm(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Mod-60 Alarm is present only in RTC-1 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC alarm enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_MOD60ALMEN; + } + else + { + pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable RTC device. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag for enabling/disabling the RTC device. + * - true : Enable RTC device. + * - false : Disable RTC device. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Global enable/disable of the RTC controller. Enables counting of elapsed real time and acts + * as a master enable for the RTC. + * + * @note When enabled, the RTC input clock pre-scaler and trim interval are realigned. + * + * @note The RTC device driver does not modify the device enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableAlarm(). + */ + +ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC device enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN; + } + else + { + pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Manage interrupt enable/disable in the RTC and NVIC controller. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] Interrupts Conveys which interrupts are affected. + * @param[in] bEnable Flag which controls whether to enable or disable RTC interrupt. + * - true : Enable RTC interrupts. + * - false : Disable RTC interrupts. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable RTC interrupt as well as manage global NVIC enable/disable for the RTC. + * Input parameter \a Interrupts is a interrupt ID of type #ADI_RTC_INT_TYPE designating the + * interrupt to be enabled or disabled. The interrupt parameter may be zero, which will then simply + * manage the NVIC RTC enable and leave the individual RTC interrupt enables unchanged. + * Input parameter \a bEnable controls whether to enable or disable the designated set of interrupts. + * + * @note The RTC device driver does not modify the interrupt enables on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + */ +ADI_RTC_RESULT adi_rtc_EnableInterrupts (ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT| + ADI_RTC_COUNT_INT | + ADI_RTC_TRIM_INT | ADI_RTC_COUNT_ROLLOVER_INT | + ADI_RTC_MOD60_ROLLOVER_INT + )) & (uint16_t)Interrupts) != 0u)) + { + return(ADI_RTC_INVALID_PARAM); + } + + assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS); +#endif + + /* TODO - more sync for new registers */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR) + + uint8_t ndx = 0u; + cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u; + +#if defined(__ADUCM4x50__) + cr5ocs = 0u; +#endif /* __ADUCM4x50__ */ + + while( Interrupts ) + { + if( 0u != (Interrupts & 1u) ) + { + uint16_t *cr = Interrupt_Details[ndx].cr; + uint16_t enableBitPosition = Interrupt_Details[ndx].bitPositionl; + *cr = *cr | (1u << enableBitPosition); + } + Interrupts >>= 1; + ndx++; + } + /* set/clear interrupt enable bit(s) in control register */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= cr0; + pDevice->pRTCRegs->CR1 |= cr1; + pDevice->pRTCRegs->CR3SS |= cr3oc; + pDevice->pRTCRegs->CR4SS |= cr4oc; + pDevice->pRTCRegs->CR2IC |= cr2ic; + +#if defined(__ADUCM4x50__) + pDevice->pRTCRegs->CR5SSS |= cr5ocs; +#endif /* __ADUCM4x50__ */ + } + else + { + pDevice->pRTCRegs->CR0 &= ~cr0; + pDevice->pRTCRegs->CR1 &= ~cr1; + pDevice->pRTCRegs->CR3SS &= ~cr3oc; + pDevice->pRTCRegs->CR4SS &= ~cr4oc; + pDevice->pRTCRegs->CR2IC &= ~cr2ic; +#if defined(__ADUCM4x50__) + pDevice->pRTCRegs->CR5SSS &= ~cr5ocs; +#endif /* __ADUCM4x50__ */ + } + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR) + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Enable RTC automatic clock trimming. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable Flag controlling RTC enabling trim. + * - true Enable RTC trimming. + * - false Disable RTC trimming. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable automatic application of trim values to the main RTC clock. Allows application + * of periodic real-time RTC clock adjustments to correct for drift. Trim values are pre-calibrated + * and stored at manufacture. Trim values may be recalibrated by monitoring the RTC clock externally + * and computing/storing new trim values (see #adi_rtc_SetTrim). + * + * @note The trim interval is reset with device enable, #adi_rtc_Enable(). + * + * @note The RTC device driver does not modify the trim enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_GetTrim(). + * @sa adi_rtc_SetTrim(). + */ +ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim enable bit(s) in control register */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN; + } + else + { + pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable input capture for the specified channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInpChannel Specify input compare channel. + * @param[in] bEnable Flag for enabling RTC input capture for specified channel. + * - true Enable input capture. + * - false Disable input capture. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableInputCapture (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel; + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable Flag for enabling overwriting the unread snapshot. + * - true Enable overwrite snapshot. + * - false Disable overwrite of snapshot. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN; + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN; + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set input capture polarity for the specified channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInpChannel Specify which input capture channel. + * @param[in] bEnable Flag for selecting RTC input capture polarity. + * - false channel uses a *high-to-low* transition on its GPIO pin to signal an input capture event + * - true channel uses a *low-to-high* transition on its GPIO pin to signal an input capture event. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nInpChannel = (uint16_t)eInpChannel; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH); + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable output for the specified Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Specify which Sensor Strobe channel. + * @param[in] bEnable Flag for enabling output for specified Sensor Strobe channel. + * - true Enable output. + * - false Disable output. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear Sensor Strobe enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel; + } + else + { + pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable auto reload for given Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel number. + * @param[in] bEnable Flag to enable auto reload for given Sensor Strobe Channel. + * - true Enable auto reload. + * - false Disable auto reload. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear auto reload enable options */ + /* Note that channel 4 does not have this feature */ + if (bEnable) + { + switch( eSSChannel) + { + case ADI_RTC_SS_CHANNEL_1: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN; + break; +#if defined(__ADUCM4x50__) + case ADI_RTC_SS_CHANNEL_2: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN; + break; + case ADI_RTC_SS_CHANNEL_3: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN; + break; +#endif /* __ADUCM4x50__ */ + default: + return ADI_RTC_FAILURE; + } + + } + else + { + switch( eSSChannel) + { + case ADI_RTC_SS_CHANNEL_1: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN; + break; +#if defined(__ADUCM4x50__) + case ADI_RTC_SS_CHANNEL_2: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN; + break; + case ADI_RTC_SS_CHANNEL_3: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN; + break; +#endif /* __ADUCM4x50__ */ + default: + return ADI_RTC_FAILURE; + } + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set auto reload value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe channel for which auto reload to be set. + * @param[in] nValue Auto reload value to be set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * + */ +ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + pDevice->pRTCRegs->SS1 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1) + break; +#if defined(__ADUCM4x50__) + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + pDevice->pRTCRegs->SS2 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2) + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + pDevice->pRTCRegs->SS3 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3) + break; + + case ADI_RTC_SS_CHANNEL_4: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + pDevice->pRTCRegs->SS4 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4) + break; +#endif /* __ADUCM4x50__ */ + + default: + return ADI_RTC_FAILURE; + + } + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable or disable thermometer-code masking for the given Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe channel for which thermometer-code masking to be enabled or disabled. + * @param[in] bEnable Flag to enable or disable masking for the given Sensor Strobe channel. + * - true Enable masking . + * - false Disable masking. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear auto reload enable options */ + if (bEnable) + { + pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel; + } + else + { + pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel; + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief To set channel mask for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel for which the mask to be set. + * @param[in] nMask Channel Mask to be set for Sensor Strobe channel. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_CHANNEL The given channel is invalid. + */ +ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t MaskPos = 0u; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS1MSK; + break; +#if defined(__ADUCM4x50__) + case ADI_RTC_SS_CHANNEL_2: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS2MSK; + break; + + case ADI_RTC_SS_CHANNEL_3: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS3MSK; + break; + + case ADI_RTC_SS_CHANNEL_4: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS4MSK; + break; +#endif /* __ADUCM4x50__ */ + default: + return ADI_RTC_INVALID_CHANNEL; + } + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK) + + pDevice->pRTCRegs->SSMSK = ((uint16_t)nMask & 0xFu) << MaskPos; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK) + + return ADI_RTC_SUCCESS; +} + +/************************************************************************************************* +************************************************************************************************** +****************************************** GET APIS ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Get current RTC alarm value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pAlarm Pointer to application memory where the alarm value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetAlarm(). + */ +ADI_RTC_RESULT adi_rtc_GetAlarm (ADI_RTC_HANDLE hDevice, uint32_t *pAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nAlarm =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u; + nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0; + NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn)); + + *pAlarm = nAlarm; + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC alarm value with fractional part also. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pAlarm Pointer to application memory where the alarm value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetAlarm(). + */ +ADI_RTC_RESULT adi_rtc_GetAlarmEx (ADI_RTC_HANDLE hDevice, float *pAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm,nTemp; + uint16_t nPreScale; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nAlarm = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u; + nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + nTemp = 1lu<pRTCRegs->ALM2 /(float)(nTemp); + + *pAlarm = (float)nAlarm+fFraction; + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC control register value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eRegister Specify which register content need to be returned. + * + * @param[out] pControl Pointer to application memory where the control register value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 16-bit RTC control register value and write it to the address provided by parameter \a pControl. + * + * @sa adi_rtc_Open(). + * @sa adi_rtcSetControl(). + */ +ADI_RTC_RESULT adi_rtc_GetControl (ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister ,uint32_t *pControl) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + switch(eRegister) + { + case ADI_RTC_CONTROL_REGISTER_0: + *pControl = pDevice->pRTCRegs->CR0; + break; + case ADI_RTC_CONTROL_REGISTER_1: + *pControl = pDevice->pRTCRegs->CR1; + break; + default: + return(ADI_RTC_FAILURE); + } + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC count value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pCount Pointer to application memory where the count value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount) +{ + uint32_t nCount; + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + *pCount = nCount; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC count value with fraction. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pfCount Pointer to application memory where the count(with fraction) value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount) +{ + uint32_t nCount,nTemp; + uint16_t nPrescale; + ADI_RTC_DEVICE *pDevice = hDevice; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + nTemp = (1lu<pRTCRegs->CNT2/(float)(nTemp); + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + *pfCount = (float)nCount+ fFraction; + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC count value of all registers. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pnCount Pointer to application memory where the count's 32 MSB are written. + * @param[out] pfCount Pointer to application memory where the count's 16 LSB are written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count integer value and fractional value in the integer format. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount) +{ + uint32_t nCount; + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + *pnCount= nCount; + *pfCount = (uint32_t)pDevice->pRTCRegs->CNT2; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + return ADI_RTC_SUCCESS; +} + + + +/*! + * @brief Get current RTC clock trim value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] peTrim Pointer to #ADI_RTC_TRIM_VALUE where the trim value is to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 16-bit RTC trim value and write it to the address provided by parameter \a pTrim. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_EnableTrim(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_GetWriteSyncStatus(). + * @sa adi_rtc_SetTrim(). + */ +ADI_RTC_RESULT adi_rtc_GetTrim (ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + if(peTrim == NULL) + { + return( ADI_RTC_INVALID_PARAM); + } +#endif + + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM); + + *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE); + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get Sensor Strobe value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel whose value to be read. + * @param[out] pValue Pointer to application memory where the Sensor Strobe value to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + *pValue = pDevice->pRTCRegs->SS1; + break; +#if defined(__ADUCM4x50__) + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + *pValue = pDevice->pRTCRegs->SS2; + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + *pValue = pDevice->pRTCRegs->SS3; + break; + + case ADI_RTC_SS_CHANNEL_4: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + *pValue = pDevice->pRTCRegs->SS4; + break; +#endif /* __ADUCM4x50__ */ + default: + return ADI_RTC_FAILURE; + } + + + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set Sensor Strobe value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel. + * @param[out] nValue Sensor Strobe value to be set for the given Sensor Strobe channel . + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + pDevice->pRTCRegs->SS1 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1) + break; + +#if defined(__ADUCM4x50__) + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + pDevice->pRTCRegs->SS2 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2) + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + pDevice->pRTCRegs->SS3 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3) + break; + + case ADI_RTC_SS_CHANNEL_4: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + pDevice->pRTCRegs->SS4 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4) + break; +#endif /* __ADUCM4x50__ */ + default: + return ADI_RTC_FAILURE; + } + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Get input capture value for specified input channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eChannel Specify which input capture channel. + * @param[out] pValue Pointer to application memory where the input capture value to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * - #ADI_RTC_INVALID_CHANNEL [D] Input channel-0 is not valid for this operation since + * channel-0 can provide precise (47bit) capture value. + * + * + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS; + +#ifdef ADI_DEBUG + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + switch(eChannel) + { + case ADI_RTC_INPUT_CHANNEL_2: + *pValue = pDevice->pRTCRegs->IC2; + break; + case ADI_RTC_INPUT_CHANNEL_3: + *pValue = pDevice->pRTCRegs->IC3; + break; + + case ADI_RTC_INPUT_CHANNEL_4: + *pValue = pDevice->pRTCRegs->IC4; + break; + default: + eResult = ADI_RTC_INVALID_CHANNEL; + break; + } + return(eResult); +} +/*! + * @brief Get snapshot of the value of RTC . + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eChannel Specify input channel from which captured value to be obtained. + * @param[in] pFraction Pointer to application memory where the fractional part of snap shot value to be written. + * @param[out] pValue Pointer to application memory where the snap shot value of RTC to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS; + uint32_t nCount = 0u; +#ifdef ADI_DEBUG + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u; + nCount |= pDevice->pRTCRegs->SNAP0; + *pFraction = pDevice->pRTCRegs->SNAP2; + *pValue = nCount; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + return(eResult); +} + + +/*! + * @brief Get current RTC posted write pending status. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pPendBits Pointer to application memory where the posted write status is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller + * clock is running at a much slower (32kHz) rate than the core processor clock. So each RTC write register has a + * one-deep FIFO to hold write values until the RTC can effect them. This gives rise to the notion of a \a pending + * \a write state: if a write is already pending and another write from the core comes along before the first (pending) + * write has cleared to its destination register, the second write may be lost because the FIFO is full already. + * + * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the configuration switch + * ADI_RTC_CFG_ENABLE_SAFE_WRITE. Enabeling safe writes (on be default) insures write data is never lost by + * detecting and pausing on pending writes prior writing new data. The penalty in using safe writes is the stall + * overhead in execution (which is not incurred if there is nothing pending). Additionally, \a all pending writes + * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all + * pending RTC writes have completed. + * + * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus()) + * status is that the \a pend state is normally clear and is set only while no room remains in a register's write FIFO, + * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent. + * + * Each write error + * source may be configured to interrupt the core by enabling the appropriate + * write error interrupt mask bit in the RTC control register (see the + * #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt handler + * will be dispatched. + * + * @sa adi_rtc_Open(). + * @sa #adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetWriteSyncStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_GetWritePendStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nPendBits; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* get the value */ + nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK; + *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits; + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC posted write synchronization status. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pSyncBits Pointer to application memory where the posted write status is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller + * clock is running at a much slower (32kHz) rate than the core processor clock. So each RTC write register has a + * one-deep FIFO to hold write values until the RTC can effect them. This gives rise to the notion of a \a pending + * \a write state: if a write is already pending and another write from the core comes along before the first (pending) + * write has cleared to its destination register, the second write may be lost because the FIFO is full already. + * + * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the + * #ADI_RTC_CFG_ENABLE_SAFE_WRITE switch. Enabling safe writes (on be default) insures write data is never lost by + * detecting and pausing on pending writes prior writing new data. The penalty in using safe writes is the stall + * overhead in execution (which is not incurred if there is nothing pending). Additionally, \a all pending writes + * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all + * pending RTC writes have completed. + * + * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus()) + * status is that the \a pend state is normally clear is set only while no room remains in a register's write FIFO, + * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent. + * + * Each write error source may be configured to interrupt the core by enabling + * the appropriate write error interrupt mask bit in the RTC control register + * (see the #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt + * handler will be dispatched. + * + * @sa adi_rtc_Open(). + * @sa #adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtcStallOnPendingWrites(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nSyncBits; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0); + + /* get the value */ + nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK; + *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits; + + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +****************************************** SET APIS ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Set a new RTC alarm value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nAlarm New alarm value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Alram Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + pDevice->pRTCRegs->ALM2 = 0u; + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set Prescale. This is power of 2 division factor for the RTC base clock. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nPreScale Prescale value to be set. if "nPreScale" is 5, RTC base clock is + divided by 32. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale ) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nTemp; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Pre scale is invalid for RTC0 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } +#endif + PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR) + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP; + nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP); + pDevice->pRTCRegs->CR1 = nTemp; + ADI_EXIT_CRITICAL_REGION(); + + SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR) + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set the pre-scale. This is power of 2 division factor for the RTC base clock. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nPeriod Periodic, modulo-60 alarm time in pre-scaled RTC time units beyond a modulo-60 boundary. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @note This API helps the CPU to position a periodic (repeating) alarm interrupt from the RTC at any integer number of pre-scaled RTC time units from a modulo-60 boundary (roll-over event) of the value of count. + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod ) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nTemp; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + + /* Mod60 Alarm is valid only in RTC-1 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM; + nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM); + pDevice->pRTCRegs->CR0 = nTemp; + ADI_EXIT_CRITICAL_REGION(); + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set a new RTC alarm value with fractional value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] fAlarm New alarm value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm = (uint32_t)fAlarm,nTemp; + uint16_t nPreScale; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Alarm Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + nTemp = 1lu<pRTCRegs->ALM2 = (uint16_t)(fFraction); + ADI_EXIT_CRITICAL_REGION(); + /* Wait till write to Alarm Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set a new RTC control register value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eRegister Specify which register need to be initialized. + * @param[in] Control New control register value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 16-bit RTC control register with the value provided by \a Control. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetControlRegister(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice,ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + switch(eRegister) + { + case ADI_RTC_CONTROL_REGISTER_0: + pDevice->pRTCRegs->CR0 = (uint16_t)Control; + break; + case ADI_RTC_CONTROL_REGISTER_1: + pDevice->pRTCRegs->CR1 = (uint16_t)Control; + break; + default: + return(ADI_RTC_FAILURE); + } + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; + +} + +/*! + * @brief Registers a Callback function with the RTC device driver. The registered call + * back function will be called when an event is detected. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param [in] pfCallback Function pointer to Callback function. Passing a NULL pointer will + * unregister the call back function. + * + * @param [in] pCBparam Call back function parameter. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_RegisterCallback( + ADI_RTC_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBparam + ) + +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u) + { + } +#endif + /* Store the address of the callback function */ + pDevice->pfCallback = pfCallback; + /* Store the call back parameter */ + pDevice->pCBParam = pCBparam; + + return ADI_RTC_SUCCESS; + +} + +/*! + * @brief Set a new RTC count value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nCount New count value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the main 32-bit RTC counter with the value provided by \a Count. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetCount(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u) + { + + } +#endif + + /* Wait till previously posted write to count Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + pDevice->pRTCRegs->CNT0 = (uint16_t)nCount; + pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16); + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to count Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1)) + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Set an RTC gateway command. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] Command Gateway command value. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 16-bit RTC gateway register with the command provided by \a Command. + * + * The gateway register is used to force the RTC to perform some urgent action. + * + * Currently, only the #ADI_RTC_GATEWAY_FLUSH command is defined, which will cancel all + * RTC register write transactions, both pending and executing. It is intended to truncate + * all core interactions in preparation for an imminent power loss when the RTC power + * isolation barrier will be activated. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* set the command */ + pDevice->pRTCRegs->GWY = Command; + return ADI_RTC_SUCCESS; +} + + + +/*! + * @brief Set a new RTC trim value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInterval Specify the trimming interval and will always in the range of (2^2 to S^17 pre-scaled RTC clock ). + * @param[in] eTrimValue Specify the trimming value. + * @param[in] eOperation Specify the operation(Add or subtract) need to be performed for trimming. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] Input parameter out of range. + * + * The RTC hardware has the ability to automatically trim the clock to compensate for variations + * in oscillator tolerance . Automatic trimming is enabled with the #adi_rtc_EnableTrim() API. + * + * @note Alarms are not affected by automatic trim operations. + * + * @note The trim boundary (interval) alignment is reset when new trim values are written. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableTrim(). + * @sa adi_rtc_GetTrim(). + */ +ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice, ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE eTrimValue, ADI_RTC_TRIM_POLARITY eOperation) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM) + + pDevice->pRTCRegs->TRM = (uint16_t)trm; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM) + + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +************************************ SYNCHRONIZATION API ************************************* +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Force synchronization of all pending writes. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Blocking call to coerce all outstanding posted RTC register writes to fully flush and synchronize. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_GetWriteSyncStatus(). +*/ +ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites (ADI_RTC_HANDLE const hDevice) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + +#endif + + /* forced block until all SYNC bits are set (ignore bSafe) */ + while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK)) + { + + } + + return ADI_RTC_SUCCESS; +} + + +/*! \cond PRIVATE */ + +/* + * @brief Initializes the device using static configuration + * + * @param[in] pDevice Pointer to RTC device . + pConfig Pointer to static configuration device structure. + * +*/ + +static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig) +{ + + /* FIXME - static init is even more now */ + + /* Control register -0 which controls all main stream activity of RTC0 */ + pDevice->pRTCRegs->CR0 = pConfig->CR0; + /* Control register -1 which is granularity of RTC control register */ + pDevice->pRTCRegs->CR1 = pConfig->CR1; + /*CNT0 contains the lower 16 bits of the RTC counter */ + pDevice->pRTCRegs->CNT0 = pConfig->CNT0; + /*CNT1 contains the lower 16 bits of the RTC counter */ + pDevice->pRTCRegs->CNT1 = pConfig->CNT1; + /* ALM0 contains the lower 16 bits of the Alarm register */ + pDevice->pRTCRegs->ALM0 = pConfig->ALM0; + /* ALM1 contains the upper 16 bits of the Alarm register */ + pDevice->pRTCRegs->ALM1 = pConfig->ALM1; + /* ALM1 contains the fractional part of the Alarm register */ + pDevice->pRTCRegs->ALM2 = pConfig->ALM2; + /* Set Input capture/sensor strobe registers only for RTC1 */ + if(pDevice->pRTCRegs == pADI_RTC1) + { + pDevice->pRTCRegs->CR2IC = pConfig->CR2IC; + pDevice->pRTCRegs->CR3SS = pConfig->CR3SS; + pDevice->pRTCRegs->CR4SS = pConfig->CR4SS; + pDevice->pRTCRegs->SSMSK = pConfig->SSMSK; + pDevice->pRTCRegs->SS1 = pConfig->SS1; +#if defined(__ADUCM4x50__) + pDevice->pRTCRegs->CR5SSS = pConfig->CR5SSS; + pDevice->pRTCRegs->CR6SSS = pConfig->CR6SSS; + pDevice->pRTCRegs->CR7SSS = pConfig->CR7SSS; + pDevice->pRTCRegs->GPMUX0 = pConfig->GPMUX0; + pDevice->pRTCRegs->GPMUX1 = pConfig->GPMUX1; +#endif /* __ADUCM4x50__ */ + } +} + + + +/*! @brief RTC device driver interrupt handler. Overrides weakly-bound default interrupt handler in _startup.c. */ +void RTC0_Int_Handler(void) +{ + ISR_PROLOG(); + uint16_t nIntSrc0, nIntSrc2, nIntSrc3; + uint32_t fired = 0u, enables = 0u; + ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice; + + /* determine qualified interrupt source(s) */ + /* need to test each interrupt source and whether it is enabled before notifying */ + /* because each source is latched regardless of whether it is enabled or not :-( */ + + /* CR0 SR0 */ + enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0; + nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0; + if( nIntSrc0 && enables ) + { + if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT)) + { + fired |= ADI_RTC_MOD60ALM_INT; + } + if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT)) + { + fired |= ADI_RTC_ALARM_INT; + } + if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT)) + { + fired |= ADI_RTC_ISO_DONE_INT; + } + if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT)) + { + fired |= ADI_RTC_WRITE_PEND_INT; + } + if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT)) + { + fired |= ADI_RTC_WRITE_SYNC_INT; + } + if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT)) + { + fired |= ADI_RTC_WRITE_PENDERR_INT; + } + } + + /* CR1 SR2 */ + enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1; + nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2; + if( nIntSrc2 && enables ) + { + if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT)) + { + fired |= ADI_RTC_MOD60_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT)) + { + fired |= ADI_RTC_COUNT_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT)) + { + fired |= ADI_RTC_TRIM_INT; + } + if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT)) + { + fired |= ADI_RTC_PSI_INT; + } + if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT)) + { + fired |= ADI_RTC_COUNT_INT; + } + } + + /* CR3OC, CR2IC SR3*/ + enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS; + nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK; + if( nIntSrc3 && enables ) + { +#if defined(__ADUCM4x50__) + if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH4_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH3_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH2_INT; + } +#endif /* __ADUCM4x50__ */ + + if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH1_INT; + } + +#if defined(__ADUCM4x50__) + if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ)) + { + fired |= ADI_RTC_RTCSS4_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ)) + { + fired |= ADI_RTC_RTCSS3_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ)) + { + fired |= ADI_RTC_RTCSS2_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ)) + { + fired |= ADI_RTC_RTCSS1_FE_INT; + } +#endif /* __ADUCM4x50__ */ + } + enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT; + } + if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT; + } + if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT; + } + if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT; + } + } + + + if (pDevice->pfCallback != NULL) { + + /* forward to the user if he is watching this interrupt */ + /* pass the "fired" value as the event. argument param is not used */ + if ( fired) + { + pDevice->pfCallback (pDevice->pCBParam, fired, NULL); + } + } + + /* Write 1 to clear the interrupts */ + pDevice->pRTCRegs->SR0 |= nIntSrc0; + pDevice->pRTCRegs->SR2 |= nIntSrc2; + pDevice->pRTCRegs->SR3 |= nIntSrc3; + ISR_EPILOG(); +} + +/*! @brief RTC device driver interrupt handler. Overrides weakly-bound default interrupt handler in _startup.c. */ +void RTC1_Int_Handler(void) +{ + ISR_PROLOG(); + uint16_t nIntSrc0, nIntSrc2, nIntSrc3; + uint32_t fired = 0u, enables = 0u; + ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice; + + /* determine qualified interrupt source(s) */ + /* need to test each interrupt source and whether it is enabled before notifying */ + /* because each source is latched regardless of whether it is enabled or not :-( */ + + /* CR0 SR0 */ + enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0; + nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0; + if( nIntSrc0 && enables ) + { + if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT)) + { + fired |= ADI_RTC_MOD60ALM_INT; + } + if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT)) + { + fired |= ADI_RTC_ALARM_INT; + } + if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT)) + { + fired |= ADI_RTC_ISO_DONE_INT; + } + if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT)) + { + fired |= ADI_RTC_WRITE_PEND_INT; + } + if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT)) + { + fired |= ADI_RTC_WRITE_SYNC_INT; + } + if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT)) + { + fired |= ADI_RTC_WRITE_PENDERR_INT; + } + } + + /* CR1 SR2 */ + enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1; + nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2; + if( nIntSrc2 && enables ) + { + if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT)) + { + fired |= ADI_RTC_MOD60_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT)) + { + fired |= ADI_RTC_COUNT_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT)) + { + fired |= ADI_RTC_TRIM_INT; + } + if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT)) + { + fired |= ADI_RTC_PSI_INT; + } + if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT)) + { + fired |= ADI_RTC_COUNT_INT; + } + } + + /* CR3OC, CR2IC SR3*/ + enables = pDevice->pRTCRegs->CR3SS & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS; + nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK; + if( nIntSrc3 && enables ) + { +#if defined(__ADUCM4x50__) + if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH4_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH3_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH2_INT; + } +#endif /* __ADUCM4x50__ */ + if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH1_INT; + } +#if defined(__ADUCM4x50__) + if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ)) + { + fired |= ADI_RTC_RTCSS4_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ)) + { + fired |= ADI_RTC_RTCSS3_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ)) + { + fired |= ADI_RTC_RTCSS2_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ)) + { + fired |= ADI_RTC_RTCSS1_FE_INT; + } +#endif /* __ADUCM4x50__ */ + } + enables = pDevice->pRTCRegs->CR2IC & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT; + } + if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT; + } + if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT; + } + if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT; + } + } + + if (pDevice->pfCallback != NULL) { + + /* forward to the user if he is watching this interrupt */ + /* pass the "fired" value as the event. argument param is not used */ + if ( fired) + { + pDevice->pfCallback (pDevice->pCBParam, fired, NULL); + } + } + + /* Write 1 to clear the interrupts */ + pDevice->pRTCRegs->SR0 |= nIntSrc0; + pDevice->pRTCRegs->SR2 |= nIntSrc2; + pDevice->pRTCRegs->SR3 |= nIntSrc3; + + ISR_EPILOG(); +} + +/*! \endcond */ + +/* @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_data.c new file mode 100755 index 00000000000..a4403847156 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_data.c @@ -0,0 +1,202 @@ +/*! + ***************************************************************************** + * @file: adi_rtc_data.c + * @brief: rtc device data file + * @version: $Revision: 34933 $ + * @date: $Date: 2016-06-28 07:11:25 -0400 (Tue, 28 Jun 2016) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \cond PRIVATE */ +#ifndef ADI_RTC_DATA_C_ +#define ADI_RTC_DATA_C_ + +#include +#include +#include "adi_rtc_def.h" + +static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] = +{ + { + (ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL + }, + { + (ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL, + } +}; + + +static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = +{ + { + /* CR0 */ + RTC0_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN | + RTC0_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN | + RTC0_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN | + RTC0_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN | + RTC0_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN | + RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN , + /* CR1 */ + 0, + /* CNT0 */ + RTC0_CFG_COUNT_VALUE_0, + /* CNT1 */ + RTC0_CFG_COUNT_VALUE_1, + /* ALM0 */ + RTC0_CFG_ALARM_VALUE_0, + /* ALM1 */ + RTC0_CFG_ALARM_VALUE_1, + /* ALM2 */ + 0, + /* TRIM */ + RTC0_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN | + RTC0_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | + RTC0_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | + RTC0_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, + 0, /* CR2IC */ + 0, /* CR3SS */ + 0, /* CR4SS */ + 0, /* SSMSK */ + 0, /* SS1 */ + 0, /* CR5SSS */ + 0, /* CR6SSS */ + 0, /* CR7SSS */ + 0, /* GPMUX0 */ + 0 /* GPMUX1 */ + + }, + /* RTC-1 */ + { + /* CR0 */ + RTC1_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN | + RTC1_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN | + RTC1_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN | + RTC1_CFG_ENABLE_MOD60_ALARM << BITP_RTC_CR0_MOD60ALMEN | + RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD << BITP_RTC_CR0_MOD60ALM | + RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT << BITP_RTC_CR0_MOD60ALMINTEN | + RTC1_CFG_ENABLE_ISO_INTERRUPT << BITP_RTC_CR0_ISOINTEN | + RTC1_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN | + RTC1_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN | + RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN , + /* CR1 */ + RTC1_CFG_ENABLE_COUNT_INTERRUPT << BITP_RTC_CR1_CNTINTEN | + RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT << BITP_RTC_CR1_PSINTEN | + RTC1_CFG_ENABLE_TRIM_INTERRUPT << BITP_RTC_CR1_TRMINTEN | + RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTROLLINTEN | + RTC1_CFG_PRESCALE << BITP_RTC_CR1_PRESCALE2EXP | + RTC1_CFG_CNT_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTMOD60ROLLINTEN , + /* CNT0 */ + RTC1_CFG_COUNT_VALUE_0, + /* CNT1 */ + RTC1_CFG_COUNT_VALUE_1, + + /* ALM[123] */ + RTC1_CFG_ALARM_VALUE_0, + RTC1_CFG_ALARM_VALUE_1, + RTC1_CFG_ALARM_VALUE_2, + + /* TRIM */ + RTC1_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN | + RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | + RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | + RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, + + /* CR2IC */ + RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN | + RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN | + RTC1_CFG_IC3_ENABLE << BITP_RTC_CR2IC_IC3EN | + RTC1_CFG_IC4_ENABLE << BITP_RTC_CR2IC_IC4EN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC0IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC2IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC3IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC4IRQEN | + RTC1_CFG_IC0_EDGE_POLARITY << BITP_RTC_CR2IC_IC0LH | + RTC1_CFG_IC2_EDGE_POLARITY << BITP_RTC_CR2IC_IC2LH | + RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH | + RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH | + RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN, + +#if defined(__ADUCM4x50__) + /* CR3SS */ + RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN | + RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN | + RTC1_CFG_SS3_ENABLE << BITP_RTC_CR3SS_SS3EN | + RTC1_CFG_SS4_ENABLE << BITP_RTC_CR3SS_SS4EN | + RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN | + RTC1_CFG_SS2_INT_ENABLE << BITP_RTC_CR3SS_SS2IRQEN | + RTC1_CFG_SS3_INT_ENABLE << BITP_RTC_CR3SS_SS3IRQEN | + RTC1_CFG_SS4_INT_ENABLE << BITP_RTC_CR3SS_SS4IRQEN, + + /* CR4SS */ + RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN | + RTC1_CFG_SS2_MASK_ENABLE << BITP_RTC_CR4SS_SS2MSKEN | + RTC1_CFG_SS3_MASK_ENABLE << BITP_RTC_CR4SS_SS3MSKEN | + RTC1_CFG_SS4_MASK_ENABLE << BITP_RTC_CR4SS_SS4MSKEN | + RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN, +#elif defined(__ADUCM302x__) + /* CR3SS */ + RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN | + RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN | + + /* CR4SS */ + RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN | + RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN, +#else +#error RTC driver not ported to this processor +#endif + /* SSMSK */ + RTC1_CFG_SS1_MASK_VALUE, + + /* SS1 */ + RTC1_CFG_SS1_AUTO_RELOAD_VALUE, + + 0, /* CR5SSS */ /* TODO: Add the following to the static configuration macros */ + 0, /* CR6SSS */ + 0, /* CR7SSS */ + 0x4688, /* GPMUX0 */ + 0x01F5, /* GPMUX1 */ + + } + +}; + +#endif +/*! \endcond */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_def.h new file mode 100755 index 00000000000..a6fca0e37b5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtc/adi_rtc_def.h @@ -0,0 +1,165 @@ +/*! + ***************************************************************************** + * @file: adi_rtc_def.h + * @brief: RTC def file + * @version: $Revision: 33205 $ + * @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ + *----------------------------------------------------------------------------- + * + * Copyright (c) 2010-2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef ADI_RTC_DEF_H__ +#define ADI_RTC_DEF_H__ + +#include + +/*! \cond PRIVATE */ +#define ADI_RTC_NUM_INSTANCE 2u + + + +#define ADI_RTC_INT_ENA_MASK_CR0 0XF804u + +#define ADI_RTC_INT_ENA_MASK_CR1 0X1Fu + +#define ADI_RTC_INT_ENA_MASK_CR2IC 0xF41C +#define ADI_RTC_INT_ENA_MASK_CR3SS 0x1FFE +#define ADI_RTC_INT_ENA_MASK_CR4SS 0x0E0E +#define ADI_RTC_INT_ENA_MASK_CR5SSS 0x0FFF + +#define ADI_RTC_INT_SOURCE_MASK_SR0 0x007Eu +#define ADI_RTC_INT_SOURCE_MASK_SR2 0x001Fu + +#define ADI_RTC_WRITE_STATUS_MASK 0XCF8u +#define ADI_RTC_SR2_IRQ_STATUS_MASK 0X1Fu +#define ADI_RTC_SR3_IRQ_STATUS_MASK 0X1FFFu + + + +#define ADI_RTC_TRIM_MASK (BITM_RTC_TRM_VALUE | BITM_RTC_TRM_ADD|BITM_RTC_TRM_IVL | BITM_RTC_TRM_IVL2EXPMIN ) + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + +#ifdef __ICCARM__ +/* +* Pm154 (rule 19.10): in the definition of a function-like macro, each instance +* of a parameter shall be enclosed in parentheses +* Parameter use without parentheses needed for struct field name in register access macro. +*/ +#pragma diag_suppress=Pm154 +#endif /* __ICCARM__ */ + +#define PEND_BEFORE_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))!=0u)\ + {\ + } + +#define SYNC_AFTER_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))==0u)\ + {\ + } + +#ifdef __ICCARM__ +#pragma diag_default=Pm154 +#endif /* __ICCARM__ */ + +#else + /* pause on pending writes to CR to avoid data loss */ +#define PEND_BEFORE_WRITE(reg,mask) +#define SYNC_AFTER_WRITE(reg,mask) +#endif + +/* + * The following is used for static configuration + */ +typedef struct +{ + uint16_t CR0; /*!< CR0 16 bit control register-0 value */ + uint16_t CR1; /*!< CR1 16 bit control register-1 value */ + uint16_t CNT0; /*!< CNT0 16 bit count register value */ + uint16_t CNT1; /*!< CNT1 16 bit count register value */ + + uint16_t ALM0; /*!< ALM0 16 bit integer part of alarm value */ + uint16_t ALM1; /*!< ALM1 16 bit integer part of alarm value */ + uint16_t ALM2; /*!< ALM2 16 bit integer part of alarm value */ + uint16_t TRIM; /*!< 16 bit trim register value */ + uint16_t CR2IC; /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */ + uint16_t CR3SS; /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */ + uint16_t CR4SS; /*!< CR4SS 16 bit control ( controls Auto reload and mask for sensor strobe ) register-4 value */ + uint16_t SSMSK; /*!< OCMSK Mask register for sensor strobe channel */ + uint16_t SS1; /*!< 16 bit Auto reload value */ + + uint16_t CR5SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t CR6SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t CR7SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t GPMUX0; /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe channel */ + uint16_t GPMUX1; /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe channel */ +}ADI_RTC_CONFIG; + +/* Device information structure */ +typedef struct _ADI_RTC_DEVICE_INFO +{ + volatile ADI_RTC_TypeDef *pRTCRegs; /* Base address of the SPORT registers */ + const IRQn_Type eIRQn; /* IRQn */ + ADI_RTC_HANDLE hDevice; /* RTC handle */ +}ADI_RTC_DEVICE_INFO; + +/*! RTC driver instance data */ +typedef struct _ADI_RTC_DEVICE +{ + volatile ADI_RTC_TypeDef *pRTCRegs; /* Pointer to RTC Memory Mapped Registers */ + + ADI_CALLBACK pfCallback; /* Function pointer for callback function. */ + + void *pCBParam; /* Parameter to callback function. */ + IRQn_Type eIRQn; /* IRQn */ + uint32_t cbWatch; + ADI_RTC_DEVICE_INFO *pDeviceInfo; /* Parameter to callback function. */ + +} ADI_RTC_DEVICE; + + +static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig); + +#ifdef ADI_DEBUG +static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice); +#endif +/*! \endcond */ +#endif /* ADI_RTC_DEF_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map.h new file mode 100755 index 00000000000..7224c14faa4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map.h @@ -0,0 +1,71 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map.h + @brief: RTOS API mapping file. + This is the main RTOS mapping header file which will include other + RTOS mapping files based on the RTOS selection. + + The purpose of RTOS mapping file is for mapping the abstracted + RTOS macros to the RTOS API calls based on the chosen RTOS. + + NOTE: This file is intended to be used by only the drivers. Not at + the application level. + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ +#ifndef ADI_RTOS_MAP_H +#define ADI_RTOS_MAP_H + +#include + +#if (ADI_CFG_RTOS == ADI_CFG_RTOS_MICRIUM_III) + +#include "rtos_map/adi_rtos_map_ucos_iii.h" + +#elif (ADI_CFG_RTOS == ADI_CFG_RTOS_FREERTOS) + +#include "rtos_map/adi_rtos_map_freertos.h" + +#else + +#include "rtos_map/adi_rtos_map_noos.h" + +#endif /* ADI_CFG_RTOS_MICRIUM_III */ + +#endif /* ADI_RTOS_MAP_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_freertos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_freertos.h new file mode 100755 index 00000000000..97cbcaeeb78 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_freertos.h @@ -0,0 +1,144 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_freertos.h + @brief: FreeRTOS RTOS API mapping file. + + This file maps the RTOS macros to FreeRTOS APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_FREERTOS_H +#define ADI_RTOS_MAP_FREERTOS_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include "semphr.h" + +extern BaseType_t xHigherPriorityTaskWoken; + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + StaticQueue_t hSemaphore; + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. FreeRtos does not + require semaphore memory to be passed by application. But memory is required + to store the handle. */ +#define ADI_SEM_SIZE (sizeof(StaticQueue_t)) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ + + /*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + xSemaphoreCreateBinaryStatic(&(DEV)->hSemaphore); \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_DELETE(DEV, error) \ + do { \ + vSemaphoreDelete (&(DEV)->hSemaphore); \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/ +#define SEM_PEND(DEV, error) \ + do { \ + if(xSemaphoreTake (&(DEV)->hSemaphore, portMAX_DELAY) != pdTRUE) \ + return((error)); \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +/* Note that priority inversion is supported */ +#define SEM_POST(DEV) \ + do { \ + /* Assume that a higher priority task can be schedule in */ \ + BaseType_t xHigherPriorityTaskWoken = pdTRUE; \ + xSemaphoreGiveFromISR(&(DEV)->hSemaphore, &xHigherPriorityTaskWoken); \ + } while (0) + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() vPortEnterCritical() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() vPortExitCritical() + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#define ISR_PROLOG() + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() portYIELD() + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER xPortPendSVHandler +#define SYSTICK_HANDLER xPortSysTickHandler +#define SVC_HANDLER vPortSVCHandler + + +#endif /* ADI_RTOS_MAP_FREERTOS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_noos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_noos.h new file mode 100755 index 00000000000..e508f1ccf57 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_noos.h @@ -0,0 +1,180 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_noos.h + @brief: No OS API mapping file. + + This file maps the RTOS macros to No OS APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_NOOS_H +#define ADI_RTOS_MAP_NOOS_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() uint32_t IntStatus = 0u + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() \ +do { \ + IntStatus = __get_PRIMASK(); \ + __disable_irq(); \ +} while (0) + + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() \ +do { \ + __set_PRIMASK(IntStatus); \ +} while (0) + + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. */ +#define ADI_SEM_SIZE (sizeof(uint32_t)) + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) +#define ISR_PROLOG() adi_cyclecount_start(); +#else +#define ISR_PROLOG() +#endif + + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) +#define ISR_EPILOG() adi_cyclecount_stop(); +#else +#define ISR_EPILOG() +#endif + +#if (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR volatile uint32_t nLowPowerExitFlag; + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + (DEV)->nLowPowerExitFlag = 0u + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) do { } while(0) + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + do { \ + ADI_PWR_RESULT eResult; \ + eResult = adi_pwr_EnterLowPowerMode(ADI_PWR_MODE_FLEXI, &(DEV)->nLowPowerExitFlag, 0u); \ + if(eResult != ADI_PWR_SUCCESS) { return ((error)); } \ + } while(0) + + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + adi_pwr_ExitLowPowerMode(&(DEV)->nLowPowerExitFlag); \ + } while(0) + + +#else /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 0 */ + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR volatile uint32_t nSemCount; + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + (DEV)->nSemCount = 0 + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) do { } while(0) + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + while ((DEV)->nSemCount == 0u) {} \ + (DEV)->nSemCount-- + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) { \ + (DEV)->nSemCount++; \ +} + +#endif /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT */ + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER PendSV_Handler +#define SYSTICK_HANDLER SysTick_Handler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_NOOS_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_ucos_iii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_ucos_iii.h new file mode 100755 index 00000000000..e055b7010fb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/rtos_map/adi_rtos_map_ucos_iii.h @@ -0,0 +1,167 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_ucos_iii.h + @brief: uCOS-III RTOS API mapping file. + + This file maps the RTOS macros to uCOS-III APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_UCOS_III_H +#define ADI_RTOS_MAP_UCOS_III_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + OS_SEM Semaphore; + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. uCOS-III requires + semaphore memory to be passed by application. But there is no memory required + to store the handle. For every semaphore related call the same memory pointer + that was used during create will be passed. */ +#define ADI_SEM_SIZE (sizeof(OS_SEM)) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + OS_ERR os_error; \ + OSSemCreate(&((DEV)->Semaphore), name ,0u, &os_error); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_DELETE(DEV, error) \ + do { \ + OS_ERR os_error; \ + OSSemDel( &((DEV)->Semaphore), OS_OPT_DEL_NO_PEND, &os_error ); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/ +#define SEM_PEND(DEV, error) \ + do { \ + OS_ERR os_error; \ + OSSemPend (&((DEV)->Semaphore), 0u, OS_OPT_PEND_BLOCKING , NULL, &os_error); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + OS_ERR os_error; \ + OSSemPost(&((DEV)->Semaphore), OS_OPT_POST_1, &os_error); \ + } while (0) + + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() +*/ +#define ADI_INT_STATUS_ALLOC() CPU_SR_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() CPU_CRITICAL_ENTER() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT() + + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1) +#define ADI_RTOS_UCOS_III_CYCLECOUNT_START adi_cyclecount_start(); +#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP adi_cyclecount_stop(); +#else +#define ADI_RTOS_UCOS_III_CYCLECOUNT_START +#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP +#endif + +#define ISR_PROLOG() \ + do { \ + CPU_SR_ALLOC(); \ + CPU_CRITICAL_ENTER(); \ + OSIntEnter(); \ + CPU_CRITICAL_EXIT(); \ + ADI_RTOS_UCOS_III_CYCLECOUNT_START \ + } while (0); + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() \ + do { \ + ADI_RTOS_UCOS_III_CYCLECOUNT_STOP \ + OSIntExit(); \ + } while (0); \ + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER OS_CPU_PendSVHandler +#define SYSTICK_HANDLER OS_CPU_SysTickHandler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_UCOS_III_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi.c new file mode 100755 index 00000000000..0bb53ac35a5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi.c @@ -0,0 +1,2017 @@ +/*! ***************************************************************************** + * @file: adi_spi.c + * @brief: SPI device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This included file will be containing SPI device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup SPI_Driver SPI Driver + * @{ + * @brief Serial Peripheral Interface (SPI) Driver + * @details The SPI driver manages all instances of the SPI peripheral. + * @note The application must include drivers/spi/adi_spi.h to use this driver. + * @note This driver requires the DMA driver.The application must include the DMA driver sources to avoid link errors. + * @note Also note that the SPI will be configured by default to operate in Master mode. + * @note To configure the driver to operate in slave mode the static configuration file adi_spi_config.h must be modified. + * @note Specifically, the macro ADI_SPIx_MASTER_MODE must be set to '0' to indicate that slave mode functionality is needed. + * @note Since there are three SPI devices there are three macros, ADI_SPI0_MASTER_MODE, ADI_SPI1_MASTER_MODE and ADI_SPI2_MASTER_MODE to control the functionality of each SPI controller. + * @note Each instance of the SPI operates independently from all other instances. + * @note + * @note When operating the SPI at high bit rates the application may need to modify the IRQ interrupt mode. The API adi_spi_SetIrqmode() can be used for this. + * @note At higher bit rates the ISR could mask a TX/RX interrupt. Specifically, it is possible that while servicing a TX/RX event another TX/RX event could occur. It is + * @note possible, therefore, that when the ISR clears the interrupt status it will not only be clearing the current TX event but the next TX/RX event as well. The result + * @note could that a final TX/RX event will not be processed. One way to work around this would be to set IRQMODE such that TX/RX events will occur only after N bytes + * @note are in the FIFO. This will only work for short bursts less than the size of the FIFO. For larger transfer DMA mode, which will not have any of these issues, should be used. + * @note Finally, if interrupt mode is required at hight bit rates note that the SPI ISR has been designed with minimal cycle count as the highest priority. + * @note The ISR could certainly be modified to re-examine the FIFO before existing at the cost of additional cycles. + */ + + /*! \cond PRIVATE */ +#include +/*! \endcond */ + +#include /* for 'NULL" definition */ +#include + +#include +#include +#include +#include +#include +#include "adi_spi_config.h" +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors +* +* Pm151 (rule 17.4): array indexing shall only be applied to objects of array type +* Pm123 (rule 18.5): there shall be no definition of objects in a header file +* +* Pm50: (MISRA C 2004 rule 14.3) a null statement shall only occur on a line by itself, and shall not have any other text on the same line +* Some Macros, such as ISR_PROLOGUE, may not have any expansion resulting in just the terminating ';' +* +*Pm140: (MISRA C 2004 rule 11.3) a cast should not be performed between a pointer type and an integral type +* MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type +* +* Pm031: (MISRA C 2004 rule 12.7) bitwise operations shall not be performed on signed integer types +* MMR macros are beyond the control of the driver. +* +*/ +#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031 + +#endif /* __ICCARM__ */ + +#include "adi_spi_data.c" + +/*! \cond PRIVATE */ + +/* handle checker for debug mode */ +#define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h))) + +/*! \endcond */ + +/* + * Local prototypes + */ +static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD); +static void StartTransaction (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr); +static void TxDmaErrorCallback (void *pCBParam, uint32_t Event, void *pArg); +static void RxDmaErrorCallback (void *pCBParam, uint32_t Event, void *pArg); + +/* ISR forward declarations */ +/*! \cond PRIVATE */ +void SPI0_Int_Handler(void); +void SPI1_Int_Handler(void); +void SPI2_Int_Handler(void); +void DMA_SPI0_TX_Int_Handler(void); +void DMA_SPI0_RX_Int_Handler(void); +void DMA_SPI1_TX_Int_Handler(void); +void DMA_SPI1_RX_Int_Handler(void); +void DMA_SPIH_TX_Int_Handler(void); +void DMA_SPIH_RX_Int_Handler(void); +/*! \endcond */ + +/* + ////////////////////////////////////////////////////////////////////////////// + ////////////////////// API IMPLEMENTATIONS /////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// +*/ + +/*! + * @brief Initialize and allocate an SPI device for use in Master Mode. + * + * @param[in] nDeviceNum Zero-based device index designating which device to initialize. + *\n + * @param [in] pDevMemory Pointer to a buffer of size ADI_SPI_MEMORY_SIZE + *\n required by the driver for the operation of specified SPI device. + * + * @param [in] nMemorySize Size of the buffer to which "pMemory" points. + * + * @param[out] phDevice The caller's device handle pointer for storing the initialized device instance data pointer. + * + * @return Status + * - #ADI_SPI_INVALID_DEVICE_NUM [D] Invalid device index. + * - #ADI_SPI_INVALID_PARAM [D] Invalid parameter. + * - #ADI_SPI_SEMAPHORE_FAILED Semaphore creation failed. + * - #ADI_SPI_DMA_REG_FAILED Failed to register DMA callbacks with common DMA service. + * - #ADI_SPI_IN_USE SPI is already open and in use. + * - #ADI_SPI_SUCCESS Call completed successfully. + * +* @note : No other SPI APIs may be called until the device open function is called. + *\n Initialize an SPI device using internal default configuration settings and allocate the + *\n device for use.The returned device handle is required to be passed to all subsequent + *\n calls to convey which device instance to operate on. + *\n The contents of phDevice will be set to NULL upon failure. Device is opened in Master mode. + *\n + * @sa adi_spi_SetMasterMode() + * @sa adi_spi_Close(). + */ +ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum, + void *pDevMemory, + uint32_t nMemorySize, + ADI_SPI_HANDLE* const phDevice) +{ + +#ifdef ADI_DEBUG + + if (nDeviceNum >= ADI_SPI_NUM_INSTANCES) + { + return ADI_SPI_INVALID_DEVICE_NUM; + } + + if (nMemorySize != sizeof(struct __ADI_SPI_DEV_DATA_TYPE)) + { + return ADI_SPI_INVALID_PARAM; + } + + if( spi_device_info[nDeviceNum].hDevice != NULL ) + { + return ADI_SPI_IN_USE; + } + +#endif + + ADI_SPI_HANDLE hDevice = pDevMemory; + + /* + * Link the two data structures together. + * + * ADI_SPI_DEVICE_INFO <==> ADI_SPI_HANDLE + * + * Clear the ADI_SPI_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bDMA = false) + * + * Other fields, such as callback related fields, are also zeroed + * and therefore properly initialized. + */ + + memset(pDevMemory,0,nMemorySize); + hDevice->pDevInfo = &spi_device_info[nDeviceNum]; + spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory; + + + /* + * Although the ADI_SPI_DEVICE_INFO struct has the address of the SPI registers + * for this instance, copying it to the ADI_SPI_HANDLE struct will minimize + * the runtime footprint and cycle count when accessing the SPI registers + */ + hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs; + + SEM_CREATE(hDevice, "SPI_SEM", ADI_SPI_SEMAPHORE_FAILED); + + /* Static Configuration */ + /* Initialize the device based on the given configuration parameters */ + ADI_SPI_CFG_TYPE const* pSPICfg = &gSPICfg[nDeviceNum]; + hDevice->pSpi->CTL = pSPICfg->SPI_CTL; + hDevice->pSpi->DIV = pSPICfg->SPI_DIV; + + /* write the device data pointer into the caller's handle */ + *phDevice = hDevice; + hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN; + + /* Make sure the DMA controller and its SRAM based descriptors are initialized */ + adi_dma_Init(); + + /* Setup the DMA TX callback */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaTxChannelNumber, TxDmaErrorCallback, (void *) hDevice)) + { + return ADI_SPI_DMA_REG_FAILED; + } + + /* Setup the DMA RX callback */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaRxChannelNumber, RxDmaErrorCallback, (void *) hDevice)) + { + return ADI_SPI_DMA_REG_FAILED; + } + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Uninitialize and deallocate an SPI device. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Uninitialize and release an allocated SPI device,and memory associated with it for other use. + * + * @sa adi_spi_Open(). + */ +ADI_SPI_RESULT adi_spi_Close (ADI_SPI_HANDLE const hDevice) +{ + + ADI_SPI_RESULT result = ADI_SPI_SUCCESS; +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + + /* disable Interrupt */ + NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn); + + + /* destroy semaphore */ + SEM_DELETE((ADI_SPI_HANDLE) hDevice,ADI_SPI_SEMAPHORE_FAILED); + + /* invalidate initialization state */ + hDevice->pDevInfo->hDevice = NULL; + return result; +} + + +/*! + * @brief Register or unregister the callback. + * + * @param [in] hDevice Device handle obtained from adi_spi_Open(). + * @param [in] pfCallback Pointer to the callback function. Can be passed as NULL to unregister the + *\n previously registered callback. + * @param [in] pCBParam Callback parameter which will be passed back to the application when the + *\n callback is called. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + */ +ADI_SPI_RESULT adi_spi_RegisterCallback (ADI_SPI_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + /* Save the application provided callback and callback parameters */ + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the IRQ mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] nMode IRQ mode value to set. +* - true Set continuous transfer mode. +* - false Clear continuous transfer mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * These bits configure when the Tx/Rx interrupts occur in a transfer. + * For DMA Rxtransfer, these bits should be 0. + * Valid values are 0-7 + * Tx interrupt occurs when (nMode+1) byte(s) has been transferred. + * Rx interrupt occurs when (nMode+1) or more bytes have been received into the FIFO. + * + * @note The application will have to carefully manage IRQMODE relative to a transaction's buffer size. + * @note Specifically, the application must ensure that the last byte causes an interrupt else the + * @note transaction will not terminate. As explained in the SPI driver overview, this functionality + * @note is typically needed when operating in interrupt mode with a high SPI bit rate (typically issues + * @note are seen at SPI clock rates of 4MHz or greater). The max clock rate will vary depending on the application. + * @note The max clock rate is a function of the SPI ISR cycle count plus any other delay that might be caused + * @note by other parts of the system. Finally, please note that while sustaining interrupt mode SPI transaction + * @note at high bit rates will work buffers that are the size of the SPI FIFO or less, transactions that are + * @note larger that the size of the FIFO may run into issues associated with masked/lost interrupts. If this + * @note does prove to be an issue for an applicatoon then the SPI ISR could be modified to examine the FIFO + * @note status on a continuous basis in the ISR (as opposed to examining the FIFO status just once at the start + * @note of the ISR). However, adding this functionality to the ISR will increase the ISR cycle count and footprint. + * + */ +ADI_SPI_RESULT adi_spi_SetIrqmode (ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + + if (nMode > ADI_SPI_IRQ_PARAM) { + return ADI_SPI_INVALID_PARAM; + } + +#endif + + uint16_t ien = hDevice->pSpi->IEN; + ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE; + ien = ien | (nMode & BITM_SPI_IEN_IRQMODE); + hDevice->pSpi->IEN = ien; + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the continuous transfer mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage SPI continuous transfer mode. +* - true Set continuous transfer mode. +* - false Clear continuous transfer mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Setting this mode causes the SPI controller to drive the Chip Select signal continuously until the transaction + * is complete. Clearing it causes Chip Select to cycle between bytes. + * + * + */ +ADI_SPI_RESULT adi_spi_SetContinuousMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the internal loopback mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage internal SPI loopback mode. + * - true Set internal loopback mode. + * - false Clear internal loopback mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Set or clear the internal SPI loopback mode. Primarily used for testing. + * + */ +ADI_SPI_RESULT adi_spi_SetLoopback (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set SPI Master-Mode operation. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to select either Master-Mode or Slave-Mode operation. + *\n - true Enable Master-Mode. Default. + *\n - false Enable Slave-Mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Controls SPI Master/Slave mode of operation, set for Master-Mode, clear for Slave-Mode. + * + */ +ADI_SPI_RESULT adi_spi_SetMasterMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { /* hardware default */ + hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER); + } else { + hDevice->pSpi->CNT = 0u; + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN; + hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER); + } + ADI_EXIT_CRITICAL_REGION(); + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the SPI receive FIFO overflow mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage receive FIFO overflow behaviour. + *\n - true Discard old data on receive FIFO overflow. + *\n - false Discard new data on receive FIFO overflow. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Controls what to do with excess incoming data when the receive FIFO becomes full. + * Either the new data or the old data is discarded. Set the receive FIFO overflow mode + * to replace data in the RX register (top of receive FIFO) with the incoming new data. + * Clear it to discard incoming new data and preserve old unread data. + + * + */ +ADI_SPI_RESULT adi_spi_SetReceiveOverflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF; + } + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the SPI transmit FIFO underflow mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage transmit FIFO underflow behaviour. + *\n - true Send zeroes on transmit FIFO underflow. + *\n - false Resend last data on transmit FIFO underflow. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Controls what to transmit when lacking valid data because the transmit FIFO is empty. + *\n Either zeros or the last valid data are transmitted. Set transmit FIFO underflow mode to send zeros. + *\n Clear it to resend the last transmitted data. + * + */ +ADI_SPI_RESULT adi_spi_SetTransmitUnderflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN; + } + + return ADI_SPI_SUCCESS; +} + + + + + + +/*! + * @brief Set the SPI serial clock frequency. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * @param[in] Hertz Target frequency (in Hz) for SPI bitrate. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_INVALID_PARAM Specified frequency is out of range. + * - #ADI_SPI_BAD_SYS_CLOCK Unable to obtain PCLK which is needed to calculate the new bit rate. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Compute and set the internal SPI clock rate divider register to produce + *\n the desired serial clock frequency. Resulting frequency is subject to arithmetic rounding errors. + *\n Use #adi_spi_GetBitrate() to obtain the exact frequency produced, including rounding errors. + * + * @sa adi_spi_GetBitrate(). + */ +ADI_SPI_RESULT adi_spi_SetBitrate (ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz) +{ + uint32_t incoming_clock; + uint16_t Div; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if( adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock) != ADI_PWR_SUCCESS) + { + return ADI_SPI_INVALID_HANDLE; + } + + /* requested rate needs to be 2x or less than incoming clock */ + if ((2U * Hertz) > incoming_clock) + { + return ADI_SPI_BAD_SYS_CLOCK; + } + + /* compute the SPI divider value */ + Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U; /* '>>1' is really a divide by 2 */ + + /* range check that computed divider fits */ + if (Div != (Div & BITM_SPI_DIV_VALUE)) + { + return ADI_SPI_INVALID_PARAM; + } + + /* store it in core */ + hDevice->pSpi->DIV = Div; + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Get the SPI serial clock frequency. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * \n + * @param[out] pnBitrate Pointer to the location where Bitrate need to be written. + * + * @return + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Get the current serial clock frequency. The returned value is exact but + *\n may not exactly match the value set with #adi_spi_SetBitrate() due to + *\n computational round-off errors resulting from fixed register size and + *\n finite-precision arithmetic. + * + * @sa adi_spi_SetBitrate(). + */ +ADI_SPI_RESULT adi_spi_GetBitrate (ADI_SPI_CONST_HANDLE const hDevice, uint32_t* const pnBitrate) +{ + uint32_t incoming_clock; + ADI_PWR_RESULT ePwrResult; + uint32_t Div; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + Div = hDevice->pSpi->DIV; /* assumes this is always a right-justified value */ + + ePwrResult = adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock); + if(ePwrResult != ADI_PWR_SUCCESS) + { + *pnBitrate= 0u; + return(ADI_SPI_FAILURE); + } + *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U; /* '>>1' is divide by 2 */ + return(ADI_SPI_SUCCESS); + +} + +/*! + * @brief Set the clock polarity. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * @param[in] bFlag Flag to manage the idle state of the serial data clock between samples. + *\n - true Clock is idled high. + *\n - false Clock is idled low. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_ERR_NOT_INITIALIZED [D] Device has not been previously configured for use. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Sets the SPI clock polarity control bit (CPOL). Used in conjunction with clock phase (CPHA) to program + *\n the exact timing of serial data capture and transmit. Both clock phase and polarity must be considered in + *\n selecting the data transfer mode best suited to the Master/Slave device pair, typically dependant on the + *\n manufacturer and timing requirements of the external SPI device. + * + *\n Both Master and Slave devices must use the same settings for clock phase and polarity. + * + *\n If the phase of the clock is zero (CPHA=0), receive data are latched on the rising-clock-edge with + *\n CPOL=0 (idle-low) polarity, and on the falling-clock-edge with CPOL=1 (idle high) ploarity. + * + *\n If CPHA=1, the effective clock edges are reversed; CPOL=0 latches receive data on the falling-clock-edge + *\n and CPOL=1 latches receive data on the rising-clock-edge. + * + *\n Data are transmitted on the opposite clock edge as the receive, i.e., receive and transmit are out of phase. + * + * @sa adi_spi_SetClockPhase(). + */ +ADI_SPI_RESULT adi_spi_SetClockPolarity (ADI_SPI_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPOL); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPOL; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the chip select. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] eChipSelect An enum value representing the requested Chip Select. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Sets the desired chip select to use for activating an external slave device. + * + * @note Chip select \a ADI_SPI0_CSn is reserved for SPI device 0 (SPI0) internal chip select line + * dedicated for communications with the UHF device. + * + */ +ADI_SPI_RESULT adi_spi_SetChipSelect (ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + hDevice->ChipSelect = eChipSelect; + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the clock phase. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage the phase of the serial data clock. + *\n - true Sample data on trailing-edge of each serial bit. + *\n - false Sample data on leading-edge of each serial bit. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_ERR_NOT_INITIALIZED [D] Device has not been previously configured for use. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Sets the SPI clock polarity phase bit (CPHA). Used in conjunction with clock polarity (CPOL) to program + *\n the exact timing of serial data capture and transmit. Both clock phase and polarity must be considered in + *\n selecting the data transfer mode best suited to the Master/Slave device pair, typically dependant on the + *\n manufacturer and timing requirements of the external SPI device. + * + *\n Both Master and Slave devices must use the same settings for clock phase and polarity. + * + *\n If the phase of the clock is zero (CPHA=0), receive data are latched on the rising-clock-edge with + *\n CPOL=0 (idle-low) polarity, and on the falling-clock-edge with CPOL=1 (idle high) ploarity. + * + *\n If CPHA=1, the effective clock edges are reversed; CPOL=0 latches receive data on the falling-clock-edge + *\n and CPOL=1 latches receive data on the rising-clock-edge. + * + *\n Data are transmitted on the opposite clock edge as the receive, i.e., receive and transmit are out of phase. + * + * @sa adi_spi_SetClockPolarity(). + */ +ADI_SPI_RESULT adi_spi_SetClockPhase (ADI_SPI_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CPHA); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CPHA; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function + *\n returns only after the data transfer is complete + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct #ADI_SPI_TRANSCEIVER. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_BUFFER_NOT_SUBMITTED [D] Failed to submit the buffer. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n + *\n Request a non-blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n + * @sa adi_spi_MasterSubmitBuffer(). + * @sa ADI_SPI_TRANSCEIVER + */ +ADI_SPI_RESULT adi_spi_MasterReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT eResult; + hDevice->bBlockingMode = true; + eResult = adi_spi_MasterSubmitBuffer(hDevice,pXfr); + hDevice->bBlockingMode = false; + if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u)) + { + eResult = ADI_SPI_HW_ERROR_OCCURRED; + } + return(eResult); +} + +/*! + * @brief Submit data buffers for SPI Master-Mode transaction. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_IN_USE [D] DMA transaction already under way. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Request a blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + * + * + * @sa adi_spi_MasterReadWrite(). + * @sa adi_spi_isBufferAvailable() + * @sa ADI_SPI_TRANSCEIVER + */ + +ADI_SPI_RESULT adi_spi_MasterSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT result = ADI_SPI_SUCCESS; + volatile uint16_t nStatus; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + + if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver)) + { + return ADI_SPI_INVALID_POINTER; + } + + if( (pXfr->bRD_CTL == true) && (pXfr->TransmitterBytes > 16u)) + { + return ADI_SPI_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* Initialize the transaction. 'hDevice' must hold the transaction values as pXfr is owned by the application */ + hDevice->pTxBuffer = pXfr->pTransmitter; + hDevice->pRxBuffer = pXfr->pReceiver; + hDevice->TxRemaining = pXfr->TransmitterBytes; + hDevice->RxRemaining = pXfr->ReceiverBytes; + hDevice->TxIncrement = (uint8_t)pXfr->nTxIncrement; + hDevice->RxIncrement = (uint8_t)pXfr->nRxIncrement; + hDevice->bDmaMode = pXfr->bDMA; + hDevice->bRdCtlMode = pXfr->bRD_CTL; + hDevice->bTransferComplete = false; + hDevice->HWErrors = ADI_SPI_HW_ERROR_NONE; + + + /* + * + * TIM + * If set: initiate transfer with write to SPI_TX register + * If clear: initiate transfer with a read from SPI_RX register + * + * RFLUSH + * Clear this bit to ensure that incoming data is ignored + * + * TFLUSH + * Clear this not to ensure that transmitted data is not a zero (if SPI_CTL.ZEN is set) or last transmitted byte + * + */ + + + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH); + + /* + * If in DMA mode then make sure XFRDONE interrupt is not set. DMA mode will generate three interrupts + * TX DMA + * RX DMA + * XFRDONE + * + * There is a race condition between XFRDONE and DMA interrupts. They are on different clocks. + * + * SPI XfrDone is counted on SPI clock (SCL) edge, which is a fixed timing related to SPI bit protocol. + * But the DMA works upon system clock (HCLK) and it could finish on various timing upon SCL/HCLK ratio. + * And bus bandwidth (e.g., DMA hold off until processor frees up the bus). So SPI RX DMA done interrupt + * could be issued earlier or later than SPI XferDone interrupt. + * + */ + if( hDevice->bDmaMode==true ) { + /* The race condition has been between RX and XFRDONE. If there are no bytes to receive then */ + /* do not clear XFRDONE */ + if( hDevice->RxRemaining != 0u) { + hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE); + } else { + hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE); + } + + } else { + + /* In interrupt mode always enable XFRDONE */ + uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE; + /* Enable underflow on;y if sending bytes */ + if( hDevice->TxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_TXUNDR; + } + /* Enable overflow only if receiving bytes */ + if( hDevice->RxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_RXOVR; + } + + hDevice->pSpi->IEN |= activeInterrupts; + + /* + * In interrupt mode, when there is nothing to receive, need to initiate a transaction + * on an TX write only. Initiating on an RX read will start the transaction, but just for + * a single byte (and we're not sure why this is true) + */ + + if( hDevice->RxRemaining == 0u) { + hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM ); + } + + } + + + /* STAT bits are cleared by writing a '1' to them. Clear any residual status*/ + nStatus = hDevice->pSpi->STAT; + hDevice->pSpi->STAT = nStatus; + + /* Make sure we are in master mode */ + hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN); + + /* Set ChipSelect */ + hDevice->pSpi->CS_CTL = hDevice->ChipSelect; + + StartTransaction(hDevice, pXfr); + + + /* block if required */ + if (hDevice->bBlockingMode == true) + { + SEM_PEND(hDevice,ADI_SPI_PEND_FAILED); + } + + return result; +} + +/*********************************************************************************************************/ +/* */ +/* SPI DRIVER Master Mode transaction start */ +/* */ +/*********************************************************************************************************/ + +static void StartTransaction(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + /* Transaction completion is determined by the number of bytes to be received */ + uint16_t nCount; + + /* Work around SPI anomaly */ + if( (hDevice->bDmaMode == true) && (hDevice->bRdCtlMode == true) && (pXfr->ReceiverBytes == 1)) + { + /* Switch to PIO mode if the transaction is setup for a DMA transfer in RD_CTL mode with an RX count of 1 */ + hDevice->bDmaMode = false; + } + /* Effectively flush the FIFOs before the start of the next transaction */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + + /* Disable any prior notion of DMA */ + hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + + + /* + * If the transaction is DMA based then set up the DMA descriptors for this transaction + */ + + uint16_t dmaFlags = 0u; + + if( hDevice->bDmaMode == true) + { + dmaFlags = BITM_SPI_DMA_EN; + + uint16_t sz = pXfr->TransmitterBytes; + if( sz ) + { + uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber; + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber)); + + /* Disables source address decrement for TX channel */ + pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << TxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << TxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << TxChanNum; + + /* fill in the DMA RAM descriptors */ + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->pTransmitter + (sz - 2U)); + + pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX; + + pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + dmaFlags |= (BITM_SPI_DMA_TXEN); + } + + sz = pXfr->ReceiverBytes; + if( sz ) + { + + uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber; + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber)); + + /* Disables destination address decrement for RX channel */ + pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << RxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << RxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << RxChanNum; + + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX; + + pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->pReceiver + (sz - 2U)); + + pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + dmaFlags |= (BITM_SPI_DMA_RXEN ); + + } + } + + /* + * SPI CNT register + * Non Read Mode: Size of the entire transactions + * Read Mode: Size of the RX transaction + * + * RD_CTL.SZ + * Read Mode: Size of the TX transaction + */ + + hDevice->pSpi->RD_CTL = 0u; + if( hDevice->bRdCtlMode) + { + /* "Half Duplex Mode" */ + + /* The number of bytes to be transmitted */ + uint32_t nBytes = hDevice->TxRemaining - 1U; + + /* Enable RD_CTL and set the TX count for the half-duplex mode of operation */ + hDevice->pSpi->RD_CTL &= (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES << BITP_SPI_RD_CTL_TXBYTES)); + + hDevice->pSpi->RD_CTL |= (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) | + (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN)); + + /* RD_CTL requires continuous mode operation. */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON); + + /* CNT represent the number of bytes to receive */ + hDevice->pSpi->CNT = hDevice->RxRemaining; + + } + else + { + /* Full duplex mode of operation */ + if(hDevice->RxRemaining == 0u) + { + /* There is nothing to receive. Flush the RX FIFO and to ignore all incoming data */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH); + } + else if(hDevice->TxRemaining == 0u) + { + /* If there is nothing to transmit then clear the TX FIFO */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH); + } + else + { + /* Misra compliance: All if/else chains should end with a final else clause */ + } + + /* Set CNT to MAX of RX/TX */ + + nCount = hDevice->RxRemaining > hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining; + hDevice->pSpi->CNT = (uint16_t)nCount; + + } + + + if( hDevice->bDmaMode == false) + { + /* Make sure that the application passed in a TX Buffer */ + if( hDevice->pTxBuffer != NULL) + { + /* interrupt mode: Fill in the FIFO */ + nCount = 0u; + while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u)) + { + /* grab the lead byte */ + hDevice->pSpi->TX = *hDevice->pTxBuffer; + /* modify tx pointer and buffer count prior to interrupt */ + hDevice->pTxBuffer += hDevice->TxIncrement; + /* decrement the byte count */ + hDevice->TxRemaining--; + nCount++; + } + } + + } else { + + hDevice->pSpi->DMA |= dmaFlags; + } + + if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM) + { + uint16_t byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX; + } + + + NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn); + + return; +} + +/*! + * @brief Block until the SPI transaction is complete. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + *\n + * @param[out] pHWErrors Pointer to hardware error return variable. + *\n + * @return Status + * - #ADI_SPI_SUCCESS Call completed successfully. + * - #ADI_SPI_SEMAPHORE_FAILED Semaphore Pend failed + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_spi_MasterSubmitBuffer(). + * @sa adi_spi_SlaveSubmitBuffer(). + */ +ADI_SPI_RESULT adi_spi_GetBuffer( + ADI_SPI_HANDLE const hDevice, + uint32_t * const pHWErrors + ) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + *pHWErrors = ADI_SPI_HW_ERROR_NONE; + return ADI_SPI_INVALID_HANDLE; + } +#endif + + SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED); + *pHWErrors = hDevice->HWErrors; + return(ADI_SPI_SUCCESS); +} + +/*! + * @brief Get the SPI transaction completion status. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + *\n + * @param[out] bComplete Pointer to boolean variable that indicates + *\n - true DMA transmit sequence is complete. + *\n - false DMA transmit sequence is incomplete. + *\n + * @return Status + * - #ADI_SPI_SUCCESS Call completed successfully. + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_spi_MasterSubmitBuffer(). + * @sa adi_spi_SlaveSubmitBuffer(). + */ + +ADI_SPI_RESULT adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice, bool* const bComplete) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + *bComplete = hDevice->bTransferComplete; + return(ADI_SPI_SUCCESS); +} + +/*! + * @brief Submit data buffers for SPI Slave-Mode transaction. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_IN_USE [D] DMA transaction already under way. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Request a non-blocking transmit and receive of multiple data bytes + *\n over the SPI serial channel. Honours current blocking and DMA modes. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n The application must make a call to adi_spi_GetBuffer() to retrieve the buffer + *\n + *\n @note: + * + * @sa adi_spi_MasterReadWrite(). + * @sa adi_spi_EnableDmaMode(). + * @sa adi_spi_isBufferAvailable(). + * @sa adi_spi_GetBuffer(). + */ +ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + volatile uint16_t ADI_UNUSED_ATTRIBUTE byte; + uint32_t nCount = 0u; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver)) + { + return ADI_SPI_INVALID_POINTER; + } + + if ((0u == pXfr->pTransmitter) && (0u == pXfr->pReceiver) ) + { + return ADI_SPI_INVALID_PARAM; + } + /* Return error if the RX buffer is not null and count is equal to zero or vice versa.*/ + if (((pXfr->pReceiver != NULL) && (pXfr->ReceiverBytes == 0u)) || ((pXfr->pReceiver == NULL) && ((pXfr->ReceiverBytes > 0u)))) + { + return ADI_SPI_INVALID_PARAM; + } + + /* Return error if the Tx buffer is not null and count is equal to zero or vice versa.*/ + if (((pXfr->pTransmitter != NULL) && (pXfr->TransmitterBytes == 0u)) || ((pXfr->pTransmitter == NULL) && (pXfr->TransmitterBytes > 0u))) + { + return ADI_SPI_INVALID_PARAM; + } + + /* DMA count register is only 8 bits, so block size is limited to 255 */ + if ((pXfr->bDMA==true) && (pXfr->TransmitterBytes != 0u) &&(((uint32_t)pXfr->pTransmitter&0x1U) !=0u ) ) + { + return ADI_SPI_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* Effectively flush the FIFOs before the start of the next transaction */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + + /* Shut down any DMA enables that are still lingering from a prior transaction */ + hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + + hDevice->bTransferComplete = false; + hDevice->pTxBuffer = pXfr->pTransmitter; + hDevice->pRxBuffer = pXfr->pReceiver; + hDevice->TxRemaining = pXfr->TransmitterBytes; + hDevice->RxRemaining = pXfr->ReceiverBytes; + hDevice->TxIncrement = (uint8_t)pXfr->nTxIncrement; + hDevice->RxIncrement = (uint8_t)pXfr->nRxIncrement; + hDevice->pSpi->CNT = (uint16_t)nCount; + hDevice->bDmaMode = pXfr->bDMA; + hDevice->bRdCtlMode = pXfr->bRD_CTL; + hDevice->HWErrors = ADI_SPI_HW_ERROR_NONE; + + + /* Configure SPI. First step is to clear CTL bits that may have been set previously */ + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON); + if( hDevice->TxRemaining == 0u ) + { + /* This will prevent TX underflow interrupts from occurring */ + hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH; + } + if( hDevice->RxRemaining == 0u ) + { + /* This will prevent data from entering RX. Also prevents overflow interrupts from occurring */ + hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH; + + /* If SPI_CTL.TIM is set, the Tx FIFO status causes the interrupt. */ + if( hDevice->bDmaMode != true) { + hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM; + } + + } + + hDevice->pSpi->CNT = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining; + + uint16_t nDMAFlags = 0u; + + if( hDevice->bDmaMode == true) + { + uint16_t sz = pXfr->TransmitterBytes; + if( sz ) + { + uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber; + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber)); + + /* Disables source address decrement for TX channel */ + pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << TxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << TxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << TxChanNum; + + /* fill in the DMA RAM descriptors */ + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->pTransmitter + (sz - 2U)); + + pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX; + + pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + nDMAFlags |= (BITM_SPI_DMA_TXEN); + } + + sz = pXfr->ReceiverBytes; + if( sz ) + { + + uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber; + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber)); + + /* Disables destination address decrement for RX channel */ + pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << RxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << RxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << RxChanNum; + + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX; + + pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->pReceiver + (sz - 2U)); + + pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + nDMAFlags |= (BITM_SPI_DMA_RXEN ); + + } + } + + /* Make sure XFRDONE is shut down. This IEN has no affect in slave mode */ + hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE; + + if( hDevice->bDmaMode == false) { + /* Make sure we are not in continuous mode from a prior DMA transaction */ + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON; + + + /* interrupt mode: Enable the UNDERFLOW and OVERFLOW interrupts */ + /* XFRDONE is invalid in slave mode */ + uint16_t activeInterrupts = 0u; + /* Enable underflow on;y if sending bytes */ + if( hDevice->TxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_TXUNDR; + } + /* Enable overflow only if receiving bytes */ + if( hDevice->RxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_RXOVR; + } + hDevice->pSpi->IEN |= activeInterrupts; + + /* interrupt mode: Fill in the FIFO and enable the TX by a dummy read. */ + while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u)) + { + /* grab the lead byte */ + hDevice->pSpi->TX = *hDevice->pTxBuffer; + /* modify tx pointer and buffer count prior to interrupt */ + hDevice->pTxBuffer += hDevice->TxIncrement; + /* decrement the byte count */ + hDevice->TxRemaining--; + nCount++; + } + } else { + + /* DMA mode. Enable the controller */ + hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags); + } + + if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM) + { + byte = hDevice->pSpi->RX; + } + NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn); + + if (hDevice->bBlockingMode == true) + { + SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED); + } + + return ADI_SPI_SUCCESS; +} + + + +/*! + * @brief Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function + *\n returns only after the data transfer is complete + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct #ADI_SPI_TRANSCEIVER. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_BUFFER_NOT_SUBMITTED [D] Failed to submit the buffer. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n + *\n Request a non-blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n + * @sa adi_spi_SlaveSubmitBuffer(). + * @sa ADI_SPI_TRANSCEIVER + */ +ADI_SPI_RESULT adi_spi_SlaveReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT eResult; + hDevice->bBlockingMode = true; + eResult = adi_spi_SlaveSubmitBuffer(hDevice,pXfr); + hDevice->bBlockingMode = false; + if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u)) + { + eResult = ADI_SPI_HW_ERROR_OCCURRED; + } + return(eResult); +} + +/* + ***************************************************************************** + * SPI Internal Static Support Functions + *****************************************************************************/ + + + /*! \cond PRIVATE */ + + +/*----------------------------------------------------------------------------- + * + * SPI ISR + * + *----------------------------------------------------------------------------*/ + + + +static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD) +{ + + /* read status register - first thing */ + volatile uint16_t nFifoStatus = pDD->pSpi->FIFO_STAT; + uint16_t nErrorStatus = pDD->pSpi->STAT; + + uint16_t writableBytes; + uint16_t readableBytes; + + + + /* Trap overflow/underflow errors and terminate the current transaction if there is an error. */ + if( BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) { + pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_RX_OVERFLOW; + } else if( BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) { + pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_TX_UNDERFLOW; + } + else + { + + /* calculate number of bytes that can be written to tx fifo */ + writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX); + /* calculate number of bytes to read from rx fifo */ + readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX); + + /* fill tx fifo */ + while ((writableBytes != 0u) && (pDD->TxRemaining != 0u)) + { + pDD->pSpi->TX = *pDD->pTxBuffer; + pDD->pTxBuffer += pDD->TxIncrement; + pDD->TxRemaining--; + writableBytes--; + } + + /* + * Now focus on the RX FIFO but only if we are not in RD_CTL mode OR, if we + * are in RD_CTL mode, TX bytes are all transmitted + */ + + if( (pDD->bRdCtlMode==false) || (pDD->TxRemaining==0u) ) + { + /* empty rx fifo */ + while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u)) + { + + *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX; + pDD->pRxBuffer += pDD->RxIncrement; + pDD->RxRemaining--; + readableBytes--; + } + } + } + + + /* Terminate the transaction and notify the caller + * 1) Master mode: If there are no more bytes to RX or TX and XFRDONE is set + * 2) Slave mode: If there are no more bytes to RX or TX (XFRDONE is invalid in slave mode) + * 3) If there was a HW error + */ + bool terminate = false; + if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u)) + { + if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN )) + { + /* Master mode */ + if( BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE )) + { + /* Master mode XFRDONE */ + terminate = true; + } + } else { + /* Slave mode - we're all done here */ + terminate = true; + } + } + + if( terminate || (pDD->HWErrors != (uint32_t)ADI_SPI_HW_ERROR_NONE)) + { + + /* Clear possible interrupt sources: XFRDONE and underflow and overflow */ + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + + } + + /* All interrupts are cleared by a write of 1 to the status register bits (W1C) */ + pDD->pSpi->STAT = nErrorStatus; + +#if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPI); +#endif + + + +} + + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pCBParam; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR; + break; + default: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != hDevice->pfCallback ){ + hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL); + } + else + { + SEM_POST(hDevice); + } +} + + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pArg; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR; + break; + default: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != hDevice->pfCallback ){ + hDevice->pfCallback(hDevice->pCBParam, hDevice->HWErrors, NULL); + } + else + { + SEM_POST(hDevice); + } +} + + +/*! + * @brief SPI0 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI0 interrupt handler. + */ +void SPI0_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[0].hDevice ); + ISR_EPILOG(); +} + + +/*! + * @brief SPI1 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI1 interrupt handler. + */ +void SPI1_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[1].hDevice); + ISR_EPILOG(); +} + +/*! + * @brief SPI2 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI2 interrupt handler. + */ +void SPI2_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[2].hDevice ); + ISR_EPILOG(); +} + + +/* + ////////////////////////////////////////////////////////////////////////////// + ////////////////////////// DMA-RELATED /////////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// +*/ + + +/* + * SPI DMA interrupt handlers + */ + + +#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==1u) +void DMA_SPI0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +/* Master mode DMA ISR */ +void DMA_SPI0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif +#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==0u) +/* Slave mode DMA ISRs */ +void DMA_SPI0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->TxRemaining = 0u; + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} +void DMA_SPI0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + + + +#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==1u) +/* Master mode DMA ISR */ +void DMA_SPI1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +void DMA_SPI1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif + + +#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==0u) +/* Slave mode DMA ISRs */ +void DMA_SPI1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->TxRemaining = 0u; + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} + + +void DMA_SPI1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + +#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==1u) +/* Master mode DMA ISR */ + +void DMA_SPIH_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +void DMA_SPIH_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif +#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==0u) +/* Master mode DMA ISRs */ + +void DMA_SPIH_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} + +void DMA_SPIH_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + + + +/*! \endcond */ + + +/* @} */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_data.c new file mode 100755 index 00000000000..ecbcb00b62e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_data.c @@ -0,0 +1,163 @@ +/* + ***************************************************************************** + * @file: adi_spi_data.c + * @brief: Data declaration for SPORT Device Driver + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef _ADI_SPI_DATA_C_ +#define _ADI_SPI_DATA_C_ + + /*! \cond PRIVATE */ + +#include +#include "adi_spi_def.h" +#include "adi_spi_config.h" +#include + +/* Stores the information about the specific device */ +static ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]= +{ + { + DMA0_CH4_DONE_IRQn, + SPI0_TX_CHANn, + DMA0_CH5_DONE_IRQn, + SPI0_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI0, + SPI0_EVT_IRQn, + NULL + }, + { + DMA0_CH6_DONE_IRQn, + SPI1_TX_CHANn, + DMA0_CH7_DONE_IRQn, + SPI1_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI1, + SPI1_EVT_IRQn, + NULL + }, + + { + DMA0_CH0_DONE_IRQn, + SPI2_TX_CHANn, + DMA0_CH1_DONE_IRQn, + SPI2_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI2, + SPI2_EVT_IRQn, + NULL + } +}; + +/* SPI Application configuration array */ +static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] = +{ + /* Initialize SPI0 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI0_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI0_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI0_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI0_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI0_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI0_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI0_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI0_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI0_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI0_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI0_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI0_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI0_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI0_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + }, + /* Initialize SPI1 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI1_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI1_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI1_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI1_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI1_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI1_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI1_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI1_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI1_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI1_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI1_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI1_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI1_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI1_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + }, + /* Initialize SPI2 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI2_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI2_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI2_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI2_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI2_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI2_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI2_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI2_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI2_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI2_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI2_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI2_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI2_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI2_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + } +}; + +/*! \endcond */ + +#endif /* _ADI_SPI_DATA_C_ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_def.h new file mode 100755 index 00000000000..4e21f336acf --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/spi/adi_spi_def.h @@ -0,0 +1,154 @@ +/*! + ***************************************************************************** + * @file: adi_spi_def.h + * @brief: SPI Device Driver definition + ***************************************************************************** +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_SPI_DEF_H_ +#define ADI_SPI_DEF_H_ + + + +#include + +#define ADI_SPI_NUM_INSTANCES (3u) +#define ADI_SPI_FIFO_SIZE (8u) +#define ADI_SPI_IRQ_PARAM (7u) + +/* Macro mapping from ADuCM4x50 to ADuCM302x */ +#if defined(__ADUCM302x__) +#define DMA_SPIH_TX_Int_Handler(void) DMA_SPI2_TX_Int_Handler(void) +#define DMA_SPIH_RX_Int_Handler(void) DMA_SPI2_RX_Int_Handler(void) +#endif + + /*! \cond PRIVATE */ + +/* + ***************************************************************************** + * SPI Bitrate Initializer. Sets a default serial clockrate for the SPI channel. + *****************************************************************************/ +/* #define ADI_SPI_BITRATE_INITIALIZER 4000000 // 4MHz default bitrate */ +#define ADI_SPI_BITRATE_INITIALIZER 250000u /* depends on processor */ + +/* + ***************************************************************************** + * SPI0/SPI1 Control Register Initializer. This macro configures default + * settings for the SPI configuration control register when operated in Master-mode. + *****************************************************************************/ +/* SPI master DMA mode control configuration */ +#define ADI_SPI_MASTERCON_INITIALIZER BITM_SPI_CTL_MASEN + +/* + ***************************************************************************** + * SPI0/SPI1 Control Register Initializer. This macro configures default + * settings for the SPI configuration control register when operated in Slave-mode. + *****************************************************************************/ + #define ADI_SPI_SLAVECON_INITIALIZER BITM_SPI_CTL_OEN \ + | BITM_SPI_CTL_ZEN \ + | BITM_SPI_CTL_SPIEN + +/* 16-bit DMA... (two-byte size and increment) */ +#define ADI_DMA_DATA_WIDTH ADI_DMA_WIDTH_2_BYTE /*!< DMA data attribute */ +#define ADI_DMA_DATA_INCREMENT ADI_DMA_INCR_HALFWORD /*!< DMA data attribute */ + + + +/*! + ***************************************************************************** + * SPI Configuration structure. + *****************************************************************************/ +typedef struct ADI_SPI_CONFIG +{ + uint16_t SPI_CTL; /*!< SPI_CTL register configuration. */ + uint16_t SPI_DIV; /*!< SPI_DIV register. */ +} ADI_SPI_CFG_TYPE; + +/*! SPI device information */ + +typedef struct __ADI_SPI_DEVICE_INFO +{ + const uint16_t dmaTxIrqNumber; /* DMA channel ID-Tx */ + const uint16_t dmaTxChannelNumber; /* Tx */ + const uint16_t dmaRxIrqNumber; /* DMA channel ID-Rx */ + const uint16_t dmaRxChannelNumber; /* DMA channel ID-Rx */ + volatile ADI_SPI_TypeDef *pSpiRegs; /* Base address of the SPI registers */ + const IRQn_Type eIRQn; /* IRQn */ + ADI_SPI_HANDLE hDevice; /* SPI handle */ +}ADI_SPI_DEVICE_INFO; + + +/*! \struct ADI_SPI_DEV_DATA_TYPE SPI Device instance data structure */ +typedef struct __ADI_SPI_DEV_DATA_TYPE +{ + + /* device attributes */ + volatile ADI_SPI_TypeDef *pSpi; /*!< track MMR device pointer */ + ADI_SPI_DEVICE_INFO *pDevInfo; + + /* Callback and Callback parameters */ + ADI_CALLBACK pfCallback; /*!< Callback address */ + void * pCBParam; /*!< Callback parameter */ + /* The last recorded SPI event */ + uint32_t HWErrors; /*!< HW transaction status */ + + uint8_t* pTxBuffer; /*!< Transmit Buffer */ + uint8_t* pRxBuffer; /*!< Receive Buffer */ + uint16_t TxRemaining; /*!< Transmit Count */ + uint16_t RxRemaining; /*!< Receive Count */ + uint8_t TxIncrement; /*!< Transmit Increment */ + uint8_t RxIncrement; /*!< Receive Increment */ + + volatile bool bTransferComplete; /*!< Transfer Complete Flag */ + + bool bDmaMode; /*!< DMA mode flag */ + bool bRdCtlMode; /* Use half duplex read control feature */ + bool bBlockingMode; /*!< blocking mode flag */ + ADI_SPI_CHIP_SELECT ChipSelect; /*!< track chip select */ + + SEM_VAR_DECLR +} ADI_SPI_DEV_DATA_TYPE; + + + +/*! \endcond */ + +#endif /* ADI_SPI_DEF_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport.c new file mode 100755 index 00000000000..5c352c2bc50 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport.c @@ -0,0 +1,1771 @@ +/*! **************************************************************************** + * @file: adi_sport.c + * @brief: SPORT (Serial Port) device driver source file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/** @addtogroup SPORT_Driver SPORT Driver + * @{ + */ + +/*! \cond PRIVATE */ + +/*============= I N C L U D E S =============*/ + +#include +#include /* memset declaration */ + +#include +#include +#include +#include +#include "adi_sport_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors + +*/ +#pragma diag_suppress=Pm026,Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm153 +#endif /* __ICCARM__ */ + +/*============== D A T A ===============*/ + +#define SPORT0_A_REGS ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_A) +#define SPORT0_B_REGS ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_B) + +#define SPORT0_A_CFG { 0u, 0u, 0u, 0u, 0u } +#define SPORT0_B_CFG { 0u, 0u, 0u, 0u, 0u } + +#define DXS_FIFO_IS_FULL(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == BITM_SPORT_STAT_A_DXS) +#define DXS_FIFO_IS_EMPTY(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == 0u) + +static ADI_SPORT_DEVICE_INFO gSportDevInfo [ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] = +{ + {/* registers configuration initial state DMA channel DMA IRQ SPORT IRQ handle */ + {SPORT0_A_REGS, SPORT0_A_CFG, ADI_SPORT_STATE_UNINITIALIZED, SPORT0A_CHANn, DMA0_CH2_DONE_IRQn, SPORT_A_EVT_IRQn, NULL}, + {SPORT0_B_REGS, SPORT0_B_CFG, ADI_SPORT_STATE_UNINITIALIZED, SPORT0B_CHANn, DMA0_CH3_DONE_IRQn, SPORT_B_EVT_IRQn, NULL}, + }, +}; + + +static const ADI_SPORT_CONFIG gSportCfg[ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] = +{ + { /* configuration for SPORT 0 */ + /* Configuration for half-SPORT A */ + { /* SPORT_CTL register */ + ((ADI_CFG_SPORT0A_ENABLE_FSMUXSEL) << BITP_SPORT_CTL_A_FSMUXSEL) | + ((ADI_CFG_SPORT0A_ENABLE_CKMUXSEL) << BITP_SPORT_CTL_A_CKMUXSEL) | + ((ADI_CFG_SPORT0A_LSB_FIRST) << BITP_SPORT_CTL_A_LSBF) | + ((ADI_CFG_SPORT0A_SERIAL_WLEN - 1u) << BITP_SPORT_CTL_A_SLEN) | + ((ADI_CFG_SPORT0A_INTERNAL_CLK) << BITP_SPORT_CTL_A_ICLK) | + ((ADI_CFG_SPORT0A_OPERATION_MODE) << BITP_SPORT_CTL_A_OPMODE) | + ((ADI_CFG_SPORT0A_CLOCK_EDGE) << BITP_SPORT_CTL_A_CKRE) | + ((ADI_CFG_SPORT0A_FS_REQUIRED) << BITP_SPORT_CTL_A_FSR) | + ((ADI_CFG_SPORT0A_INTERNAL_FS) << BITP_SPORT_CTL_A_IFS) | + ((ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS) << BITP_SPORT_CTL_A_DIFS) | + ((ADI_CFG_SPORT0A_ACTIVE_LOW_FS) << BITP_SPORT_CTL_A_LFS) | + ((ADI_CFG_SPORT0A_LATE_FS) << BITP_SPORT_CTL_A_LAFS) | + ((ADI_CFG_SPORT0A_ENABLE_PACKING) << BITP_SPORT_CTL_A_PACK) | + ((ADI_CFG_SPORT0A_FS_ERROR_OPERATION) << BITP_SPORT_CTL_A_FSERRMODE) | + ((ADI_CFG_SPORT0A_GATED_CLOCK) << BITP_SPORT_CTL_A_GCLKEN), + + /* SPORT_DIV register */ + ((ADI_CFG_SPORT0A_CLOCK_DIVISOR) << BITP_SPORT_DIV_A_CLKDIV) | + ((ADI_CFG_SPORT0A_FS_DIVISOR) << BITP_SPORT_DIV_A_FSDIV), + + /* SPORT_CONVT register */ + ((ADI_CFG_SPORT0A_CONVT_WIDTH) << BITP_SPORT_CNVT_A_WID) | + ((ADI_CFG_SPORT0A_CONVT_POLARITY) << BITP_SPORT_CNVT_A_POL) | + ((ADI_CFG_SPORT0A_CONVT_FS_DURATION) << BITP_SPORT_CNVT_A_CNVT2FS), + + /* Default DMA data size for SPORT */ + ADI_DMA_WIDTH_4_BYTE, + + /* Default DMA data increment for SPORT */ + ADI_DMA_INCR_4_BYTE + }, + + /* Configuration for half-SPORT B */ + { /* SPORT_CTL register */ + ((ADI_CFG_SPORT0B_LSB_FIRST) << BITP_SPORT_CTL_B_LSBF) | + ((ADI_CFG_SPORT0B_SERIAL_WLEN - 1u) << BITP_SPORT_CTL_B_SLEN) | + ((ADI_CFG_SPORT0B_INTERNAL_CLK) << BITP_SPORT_CTL_B_ICLK) | + ((ADI_CFG_SPORT0B_OPERATION_MODE) << BITP_SPORT_CTL_B_OPMODE) | + ((ADI_CFG_SPORT0B_CLOCK_EDGE) << BITP_SPORT_CTL_B_CKRE) | + ((ADI_CFG_SPORT0B_FS_REQUIRED) << BITP_SPORT_CTL_B_FSR) | + ((ADI_CFG_SPORT0B_INTERNAL_FS) << BITP_SPORT_CTL_B_IFS) | + ((ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS) << BITP_SPORT_CTL_B_DIFS) | + ((ADI_CFG_SPORT0B_ACTIVE_LOW_FS) << BITP_SPORT_CTL_B_LFS) | + ((ADI_CFG_SPORT0B_LATE_FS) << BITP_SPORT_CTL_B_LAFS) | + ((ADI_CFG_SPORT0B_ENABLE_PACKING) << BITP_SPORT_CTL_B_PACK) | + ((ADI_CFG_SPORT0B_FS_ERROR_OPERATION) << BITP_SPORT_CTL_B_FSERRMODE) | + ((ADI_CFG_SPORT0B_GATED_CLOCK) << BITP_SPORT_CTL_B_GCLKEN), + + /* SPORT_DIV register */ + ((ADI_CFG_SPORT0B_CLOCK_DIVISOR) << BITP_SPORT_DIV_B_CLKDIV) | + ((ADI_CFG_SPORT0B_FS_DIVISOR) << BITP_SPORT_DIV_B_FSDIV), + + /* SPORT_CONVT register */ + ((ADI_CFG_SPORT0B_CONVT_WIDTH) << BITP_SPORT_CNVT_B_WID) | + ((ADI_CFG_SPORT0B_CONVT_POLARITY) << BITP_SPORT_CNVT_B_POL) | + ((ADI_CFG_SPORT0B_CONVT_FS_DURATION) << BITP_SPORT_CNVT_B_CNVT2FS), + + /* Default DMA data size for SPORT */ + ADI_DMA_WIDTH_4_BYTE, + + /* Default DMA data increment for SPORT */ + ADI_DMA_INCR_4_BYTE + } + } +}; + +/*! \endcond */ + +/*============= C O D E =============*/ + +extern void SPORT0A_Int_Handler(void); /*!< Interrupt handler for the SPORT0-A */ +extern void SPORT0B_Int_Handler(void); /*!< Interrupt handler for the SPORT0-B */ +extern void DMA_SPORT0A_Int_Handler(void); /*!< DMA handler for the SPORT0-A */ +extern void DMA_SPORT0B_Int_Handler(void); /*!< DMA handler for the SPORT0-B */ + +/*============= L O C A L F U N C T I O N S =============*/ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Initialization function for SPORT device. + * @details Initialization function for SPORT device. This function must be + * called before operating any SPORT device. + * + * @param [in] nDevNum SPORT Device instance to be opened. + * @param [in] eChannel Channel ID of the SPORT device (A or B) + * @param [in] eDirection Direction of the SPORT operation (i.e Rx or Tx) + * @param [in] pMemory Pointer to a 32 bit aligned buffer containing + * ADI_SPORT_MEMORY_SIZE bytes. This buffer is + * required by the SPORT driver for its operations. + * The "ADI_SPORT_MEMORY_SIZE" varies based on the + * configuration. + * @param [in] nMemSize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where a handle to the + * opened SPORT driver can be stored. This handle + * will be used to identity a SPORT device when + * calling SPORT management functions. + * + * @return Status + * - #ADI_SPORT_SUCCESS Successful device initialization. + * - #ADI_SPORT_DEVICE_IN_USE Device already initialized. + * - #ADI_SPORT_FAILED Failed initialize a semaphore for managing device. + * - #ADI_SPORT_INVALID_DEVICE_NUM Invalid SPORT device identifier + * - #ADI_SPORT_INVALID_NULL_POINTER Invalid pointer (callback function or device handle). + * + * @sa adi_sport_Close() + */ +ADI_SPORT_RESULT adi_sport_Open( + const uint32_t nDevNum, + const ADI_SPORT_CHANNEL eChannel, + const ADI_SPORT_DIRECTION eDirection, + void *pMemory, + const uint32_t nMemSize, + ADI_SPORT_HANDLE * const phDevice + ) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + + assert(ADI_SPORT_MEMORY_SIZE == sizeof(ADI_SPORT_DEVICE)); /* validate the memory size macro */ +#ifdef ADI_DEBUG + if (nDevNum >= ADI_SPORT_NUM_INSTANCES) + { + result = ADI_SPORT_INVALID_DEVICE_NUM; /* SPORT identifier must be within [0..ADI_SPORT_NUM_INSTANCES-1] */ + } + else if (phDevice == NULL) + { + result = ADI_SPORT_INVALID_NULL_POINTER; /* the pointer to device handle must be valid */ + } + else if (ADI_SPORT_MEMORY_SIZE != nMemSize) + { + result = ADI_SPORT_FAILED; + } + else if (ADI_SPORT_STATE_UNINITIALIZED != gSportDevInfo[nDevNum][eChannel].eState) + { + result = ADI_SPORT_DEVICE_IN_USE; /* the device instance must not be in use */ + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_DEVICE * pDevice = pMemory; /* Pointer to the SPORT device instance (from supplied memory) */ + ADI_SPORT_DEVICE_INFO * sportInfo = &gSportDevInfo[nDevNum][eChannel]; /* SPORT info for HSPORT A or HSPORT B */ + ADI_SPORT_CONFIG const * sportCfg = &gSportCfg[nDevNum][eChannel]; /* SPORT configuration for HSPORT A or HSPORT B */ + + assert(eChannel < ADI_SPORT_NUM_CHANNELS); + + memset(pMemory, 0, nMemSize); /* clear the device instance data before initializing it */ + + pDevice->pSportInfo = sportInfo; /* Initialize the pointer which provides the device information (HSPORT A or HSPORT B). */ + pDevice->eDirection = eDirection; /* Initialize the direction (BEFORE calling sport_Configure)*/ + pDevice->nHwError = (uint32_t) ADI_SPORT_HW_NO_ERR; + + adi_dma_Init(); /* Set up the DMA Controller. */ + sport_Init(pDevice); /* Initialize the data transmission buffers */ + sport_Configure(pDevice,sportCfg); /* Configure the SPORT */ + + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(sportInfo->eDMAChnlID, sport_DmaErrorCallback, pDevice)) + { + adi_sport_Close(pDevice); + result = ADI_SPORT_DMA_REGISTER_FAILED; + } + + if (ADI_SPORT_SUCCESS == result) + { + ADI_SPORT_DEVICE_INFO * devInfo = &gSportDevInfo[nDevNum][eChannel]; + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + if (ADI_HALF_SPORT_A == eChannel) + { + SEM_CREATE(&pDevice->sportChannel, "SPORT0_A_SEM", ADI_SPORT_FAILED); + }else{ + SEM_CREATE(&pDevice->sportChannel, "SPORT0_B_SEM", ADI_SPORT_FAILED); + } + + /* Change the state of the specified device */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + devInfo->eState = ADI_SPORT_STATE_INITIALIZED; + devInfo->hDevice = pDevice; + ADI_EXIT_CRITICAL_REGION(); + *phDevice = pDevice; /* Return the device handle to the application */ + } + } + + return result; +} + +/** + * @brief Closes the operation of specified SPORT device. + * + * @details Closes the operation of specified SPORT device. + * Device need to be opened again for any further use. + * + * @param [in] hDevice SPORT device handle whose operation is to be closed. + * This handle was obtained when a SPORT device is opened + * successfully. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully closed the specified device. + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * - #ADI_SPORT_FAILED [D] SPORT device internal error. + * + * @note It is user's responsibility to free/reuse the memory supplied + * during the opening of the device. + * + * @sa adi_sport_Open() + */ +ADI_SPORT_RESULT adi_sport_Close(ADI_SPORT_HANDLE const hDevice) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; /* return code */ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS == (result=ValidateHandle(pDevice))) /* Validate the given handle */ +#endif /* ADI_DEBUG */ + { + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; + + /* Free up the device */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + NVIC_DisableIRQ(pSportInfo->eIRQn); /* Disable SPORT event interrupts. */ + NVIC_DisableIRQ(pSportInfo->eDMAn); /* Disable DMA SPORT interrupts. */ + pSportInfo->eState = ADI_SPORT_STATE_UNINITIALIZED; + pSportInfo->hDevice = NULL; /* Free up the device memory. */ + ADI_EXIT_CRITICAL_REGION(); + + SEM_DELETE(&pDevice->sportChannel, ADI_SPORT_FAILED); /* Delete SPORT channel semaphore. */ + + adi_dma_RegisterCallback(pSportInfo->eDMAChnlID, NULL, NULL); /* unregister the callback function in the DMA error handler */ + + pSportInfo->pSportRegs->CTL_A = 0u; + } + return result; +} + +/** + * @brief Submit the buffer for transmitting/receiving the data. This function can + * be used to submit the buffers for both transmitting and receiving. It will + * be returned after successfully submitting the buffer for transmitting data. + * User will be notified if a call back function is registered with an event code + * #ADI_SPORT_EVENT_RX_BUFFER_PROCESSED or #ADI_SPORT_EVENT_TX_BUFFER_PROCESSED" + * depending on the direction in which device is operating. + * + * @param [in] hDevice Device handle to SPORT device is obtained when a SPORT device is opened + * successfully. + * + * @param [in] pBuffer Pointer to buffer from where data need to be transmitted OR to which + * received data need to to be written. + * + * @param [in] nNumBytes Size in bytes of the data to be transmitted/received. + * @param [in] bDMA True if the buffer must be processed through DMA-driven SPORT operations. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Buffer successfully submitted to the specified SPORT. + * - #ADI_SPORT_INVALID_HANDLE Invalid SPORT device handle. + * - #ADI_SPORT_INVALID_PARAMETER Number of bytes is too large for a SPORT transfer or the buffer is mis-aligned + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED All the SPORT buffers are already being used + * + * @sa adi_sport_GetBuffer() + * + */ +ADI_SPORT_RESULT adi_sport_SubmitBuffer(ADI_SPORT_HANDLE const hDevice, + void * const pBuffer, + uint32_t const nNumBytes, + bool const bDMA + ) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* pointer to SPORT device instance */ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; /* return code */ + +#ifdef ADI_DEBUG + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; /* short cut to SPORT configuration */ + + if(ADI_SPORT_SUCCESS != (result=ValidateHandle(hDevice))) /* validate the given handle */ + { + } + else if ( ((2u >= nNumBytes) && ((pDevice->pSportInfo->pSportRegs->CTL_A & BITM_SPORT_CTL_A_OPMODE) != 0u)) + || (0u != (nNumBytes & ~(BITM_SPORT_NUMTRAN_A_VALUE))) /* buffer size limited by SPORT transmission capabilities */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; + } + else +#endif /* ADI_DEBUG */ + /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has finished being processed in "adi_sport_GetBuffer()". + */ + if (NULL != pDevice->sportChannel.pFreeBuffer->pStartAddress) + { + result = ADI_SPORT_BUFFERS_NOT_SUBMITTED; + } + else + { +#ifdef ADI_DEBUG + const uint32_t addr = (uint32_t) pBuffer; + + if (true == bDMA) + { + /** + * Using SPORT configuration data, let's define information such as data + * size in bytes, data number, number of data and bytes in the DMA transfer + * being prepared, last byte position for the DMA transfer + * + * It's important to keep in mind that for buffer that contain too many data + * multiple DMA transfers are needed: it's up to the application to split the + * DMA requests in requests which have an appropriate number of data. + */ + const uint32_t dataSizeInBytes = GetBytesPerSportData(pSportCfg->CTL); + const uint32_t full = nNumBytes / dataSizeInBytes; /* number of full data to transmit/receive */ + const uint32_t partial = nNumBytes % dataSizeInBytes; /* number of partial data to transmit/receive */ + const uint32_t misaligned = addr % dataSizeInBytes; /* number of data to transmit/receive */ + + if ( (full > DMA_TRANSFER_LIMIT) /* number of data to process too large for DMA */ + || (0u != partial) /* buffer size not a multiple of dataSizeInBytes */ + || (0u != misaligned) /* buffer mis-aligned */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; + } + } else { + const uint32_t misAligned = addr % 4u; + const uint32_t invalidNum = nNumBytes % 4u; + + if ( (0u != misAligned) /* mis-aligned buffer */ + || (0u != invalidNum) /* number of bytes not a multiple of 32-bit */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; /* reject the buffer submission */ + } + } + if (ADI_SPORT_SUCCESS == result) +#endif /* ADI_DEBUG */ + { + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + + pSportChnl->pFreeBuffer->pStartAddress = pBuffer; /* Set the start address of the data buffer */ + pSportChnl->pFreeBuffer->nCount = nNumBytes; /* Set the buffer size */ + pSportChnl->pFreeBuffer->nIndex = 0u; /* Initialize the buffer index to zero (1st data in buffer) */ + pSportChnl->pFreeBuffer->bDMA = bDMA; /* Set the DMA boolean value. */ + pSportChnl->pFreeBuffer->bInUse = true; /* this buffer is now being used by the SPORT */ + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the next buffer. "pFreeBuffer" will only be updated + during the process of submitting a buffer or a read/write operation. + */ + pSportChnl->pFreeBuffer = pSportChnl->pFreeBuffer->pNextBuffer; + + /* Set the data transfer mode in case it was #ADI_DT_MODE_NONE. This + will be set back to #ADI_DT_MODE_NONE once this transaction is complete. + Then, if a buffer is not currently active, set up the interrupts for + this transaction. Otherwise if a buffer is currently active, this will + be taken care of in the ISR. + */ + if (pSportChnl->eDataTranferMode == ADI_DT_MODE_NONE) /* if the SPORT is available for a transmission */ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING; + + /* call an appropriate function based on mode in which device is operating */ + if (true == bDMA) /* select a DMA driven or a core driven non-blocking transmission */ + { + result = sport_SubmitBufferDmaMode(pDevice, pSportChnl->pFillBuffer); + } else { + result = sport_SubmitBufferIntMode(pDevice, pSportChnl->pFillBuffer); + } + } + + if(ADI_SPORT_SUCCESS != result) /* if an error occurred...*/ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + } + } + } + + return result; +} + +/* + * @brief Submit a buffer for SPORT Rx or Tx DMA driven transmission. + * + * @param [in] pDevice Pointer to SPORT device. + * + * @param [in] pBuffer Pointer to data transfer buffer information. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS buffer successfully submitted to the DMA associated with the SPORT. + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED Failed to submit the buffer to the DMA associated with the SPORT. + */ +/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, + ADI_DT_BUFF_INFO * pBuff) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + +#ifdef ADI_DEBUG + if ( (pBuff != pDevice->sportChannel.pFillBuffer) /* a submitted buffer should always be the current fill buffer */ + || (true != pBuff->bInUse) /* Processed buffers should already be marked as being used */ + || (0u != pBuff->nIndex) /* processing should start from index 0 */ + ) + { + result = ADI_SPORT_FAILED; + } + else +#endif + { + volatile ADI_SPORT_TypeDef* pSportRegs = pSportInfo->pSportRegs;/* short cut to SPORT registers */ + const uint32_t dmaChnlId = (uint32_t) pSportInfo->eDMAChnlID; /* identifier for the DMA channel to be used */ + const uint32_t dmaChnlBit = (1u << dmaChnlId); /* bit representing the DMA channel to be used */ + + /** + * Using SPORT configuration data, let's define information such as data + * size in bytes, data number, number of data and bytes in the DMA transfer + * being prepared, last byte position for the DMA transfer + * + * It's important to keep in mind that for buffer that contain too many data + * multiple DMA transfers are needed, so a buffer may have had part of its + * content already DMA-transferred: nIndex defines the position of the first + * byte in a buffer that has not been DMA-transferred yet. + */ + const uint32_t dmaIncNone = (uint32_t) ADI_DMA_INCR_NONE; + const uint32_t dmaDcc = (uint32_t) DMA_ENUM_CTL_CYCLE_CTL_BASIC; + const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); + + const uint32_t dataSizeInBytes = (1u << pSportCfg->DMA_WIDTH); /* number of bytes in each data to transmit/receive */ + uint32_t numDmaData = pBuff->nCount / dataSizeInBytes; /* number of DMA data to transmit/receive */ + const uint32_t dmaDataEnd = (pBuff->nCount - dataSizeInBytes); /* position of last <8,16,32>-bit data in the DMA transfer being setup */ + const uint32_t startAddress = (uint32_t) pBuff->pStartAddress; /* address of the first byte in the data buffer */ + const uint32_t numSportData = pBuff->nCount / bytesPerData; /* number of SPORT data to transmit/receive */ + + assert(pBuff->nCount == (numSportData * bytesPerData)); + assert(numSportData <= 0xFFFu); + assert(0u == (pBuff->nCount % dataSizeInBytes)); + assert(numDmaData <= DMA_TRANSFER_LIMIT); + assert((ADI_SPORT_DIR_RX == pDevice->eDirection) || (ADI_SPORT_DIR_TX == pDevice->eDirection)); + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + + pSportRegs->CTL_A = 0u; /* make sure SPORT is disable */ + pADI_DMA0->SRCADDR_CLR = dmaChnlBit; /* Clear source address decrement for TX channel DMA. */ + pADI_DMA0->EN_SET = dmaChnlBit; /* Enable channel DMA. */ + pADI_DMA0->RMSK_CLR = dmaChnlBit; /* Enable SPORT peripheral to generate DMA requests. */ + pADI_DMA0->ALT_CLR = dmaChnlBit; /* Set the primary control data structure as the current DMA descriptor. */ + pADI_DMA0->PRI_SET = dmaChnlBit; + + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + pPrimaryCCD[dmaChnlId].DMASRCEND = (uint32_t) &pSportRegs->RX_A; /* address of the last src data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMADSTEND = startAddress + dmaDataEnd; /* address of the last dst data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMACDC = + (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_DST_INC)) | /* destination address incremented by N bytes */ + (dmaIncNone << ((uint32_t)DMA_BITP_CTL_SRC_INC)); /* source address not incremented */ + } + else /* ADI_SPORT_DIR_TX */ + { + pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd; /* address of the last src data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMADSTEND = (uint32_t) &pSportRegs->TX_A; /* address of the last dst data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMACDC = + (dmaIncNone << ((uint32_t)DMA_BITP_CTL_DST_INC)) | /* destination address not incremented */ + (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_SRC_INC)); /* source address incremented by N byte */ + + /** + * Fix for data transmission when DMA is used with packed data. + */ + if (numDmaData < numSportData) + { + pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd + dataSizeInBytes; /* address of the last src data in the DMA transfer being setup */ + numDmaData++; + } + } + pPrimaryCCD[dmaChnlId].DMACDC |= + (pSportCfg->DMA_WIDTH << ((uint32_t)DMA_BITP_CTL_SRC_SIZE)) | /* source data size in bytes */ + (0u << ((uint32_t) DMA_BITP_CTL_R_POWER)) | + ((numDmaData - 1u) << ((uint32_t)DMA_BITP_CTL_N_MINUS_1)) | /* number of DMA transfers (minus 1) */ + (dmaDcc << ((uint32_t)DMA_BITP_CTL_CYCLE_CTL)); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED; + pSportRegs->NUMTRAN_A = numSportData; + + /* Enable SPORT DMA request interrupt for the SPORT tx channel. */ + NVIC_ClearPendingIRQ(pSportInfo->eIRQn); + NVIC_ClearPendingIRQ(pSportInfo->eDMAn); + + uint32_t ien_a = ((uint32_t)BITM_SPORT_IEN_A_SYSDATERR) | + ((uint32_t)BITM_SPORT_IEN_A_FSERRMSK) | + ((uint32_t)BITM_SPORT_IEN_A_DERRMSK); + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + /* Allow SPORT DMA interrupt handling to mark SPORT Rx as complete */ + NVIC_EnableIRQ(pSportInfo->eDMAn); + } + else + { + /* SPORT DMA Tx is complete when TFI is raised: enable TFI */ + ien_a |= ((uint32_t)BITM_SPORT_IEN_A_TF); + } + + NVIC_EnableIRQ(pSportInfo->eIRQn); + + pSportRegs->IEN_A = ien_a; + pSportRegs->CTL_A = pSportCfg->CTL | + ((uint32_t)BITM_SPORT_CTL_A_SPEN) | + ((uint32_t)BITM_SPORT_CTL_A_DMAEN); + ADI_EXIT_CRITICAL_REGION(); + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** Function prototype for */ +/* + * @brief Submit a buffer for SPORT Rx or Tx core driven transmission. + * + * @details Submit a buffer for SPORT Rx or Tx core driven transmission. + * The buffer must be 32-bit aligned and contain N * 32-bit data. + * + * @param [in] pDevice Pointer to SPORT device. + * + * @param [in] pBuffer Pointer to data transfer buffer information. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully submitted the buffer for data transfer. + * + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED No free descriptor for data transfer. + * + * + */ +static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; +#ifdef ADI_DEBUG + if ( (pBuff != pDevice->sportChannel.pFillBuffer) /* a submitted buffer should always be the current fill buffer */ + || (true != pBuff->bInUse) /* Processed buffers should already be marked as being used */ + || (0u != pBuff->nIndex) /* processing should start from index 0 */ + ) + { + result = ADI_SPORT_FAILED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + volatile ADI_SPORT_TypeDef * pSportRegs = pDevice->pSportInfo->pSportRegs; + uint32_t ctl = pSportCfg->CTL; + uint32_t bytesPerData = GetBytesPerSportData(ctl); + + /** + * Buffer can be too large for being processed in one submission. + * Consequently, if pBuff->nCount requires more than than 12-bit, + * multiple buffer submissions will be required by the application; + * the SPORT driver cannot process large buffers implicitly. + * The number of bytes in submitted buffers must be a multiple of 4 + * because data are processed by the SPORT driver as 32-bit data. + */ + + /* use the SPORT configuration to setup the SPORT registers */ + + pBuff->nCount /= bytesPerData; /* number of data to be transmitted */ + +#ifdef ADI_DEBUG + uint32_t pack = SPORT_GET_PACKEN(pSportCfg->CTL); + assert( ((9u > bytesPerData) && (1u == pack)) || ((17u > bytesPerData) && (2u == pack)) || (0u == pack)); +#endif + assert(pBuff->nCount <= 0xFFFu); + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pSportRegs->CTL_A = 0u; /* make sure SPORT is disable */ + pSportRegs->NUMTRAN_A = pBuff->nCount; + pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED; + + /* Enable SPORT Interrupt. */ + NVIC_ClearPendingIRQ(pDevice->pSportInfo->eIRQn); + NVIC_EnableIRQ(pDevice->pSportInfo->eIRQn); + pSportRegs->IEN_A |= ((uint32_t) ( BITM_SPORT_IEN_A_DATA + | BITM_SPORT_IEN_A_SYSDATERR + | BITM_SPORT_IEN_A_FSERRMSK + | BITM_SPORT_IEN_A_DERRMSK + | BITM_SPORT_IEN_A_TF + ) + ); + pSportRegs->CTL_A = pSportCfg->CTL | ((uint32_t)BITM_SPORT_CTL_A_SPEN); + ADI_EXIT_CRITICAL_REGION(); + } + return result; +} + +/** + * @brief This function returns the address of a processed buffer. This + * is a blocking function: it waits until a buffer has been dealt + * with. This function returns an error if a callback function is + * registered. #adi_sport_IsBufferAvailable can be used as a peek + * function to know whether a buffer is available. + * + * @param [in] hDevice Device handle to SPORT device, obtained when a SPORT + * device is openedsuccessfully. + * + * @param [out] ppBuffer Pointer to a location where the the address of the + * buffer is to be written. Contains the address of an + * "empty" buffer (i.e the content of the buffer is + * transmitted) OR "filled" buffer which contains the + * received data. + * + * @param [out] pHwError Pointer to 32-bit value reporting SPORT/DMA events + * that can occur when processing buffer ppBuffer. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully returned. ppBuffer points + * to the address of the buffer. + * + * - #ADI_SPORT_FAILED Failed to get the buffer since device + * is operating in call back mode. + * ppBuffer points NULL. + * + * - #ADI_SPORT_HW_ERROR SPORT hardware or DMA error detected + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * @sa adi_sport_SubmitBuffer() + * @sa adi_sport_IsBufferAvailable() + * + */ +ADI_SPORT_RESULT adi_sport_GetBuffer(ADI_SPORT_HANDLE const hDevice, + void ** const ppBuffer, + uint32_t * pHwError) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + + *ppBuffer = NULL; +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice))) /* Validate the given handle */ + { + } + else +#endif /* ADI_DEBUG */ + if (NULL != pDevice->pfCallback) + { + result = ADI_SPORT_FAILED; + } else { + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + + SEM_PEND(pSportChnl,ADI_SPORT_FAILED); /* wait for a submitted buffer to be processed */ + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + *pHwError = pDevice->nHwError; + pDevice->nHwError = 0u; + *ppBuffer = pSportChnl->pActiveBuffer->pStartAddress; /* return the buffer start address in *ppBuffer */ + pSportChnl->pActiveBuffer->pStartAddress = NULL; /* clear the free buffer address */ + pSportChnl->pActiveBuffer = pSportChnl->pActiveBuffer->pNextBuffer; + ADI_EXIT_CRITICAL_REGION(); + if (0u != *pHwError) + { + result = ADI_SPORT_HW_ERROR; + } + } + return result; +} + +/** + * @brief Peek function to know whether an empty/filled buffer is available. Call to this + * function is valid only if the call back function is not registered. Call to this + * function results in error if a call back function is registered. + * + * @param [in] hDevice Device handle to SPORT device obtained when a SPORT device is opened + * successfully. + * + * @param [out] pbAvailable Pointer to a boolean variable. Contains "True" if there is an + * empty/filled buffer and a call to #adi_sport_GetBuffer is ensured to be + * successful. Contains "false" if there is no empty buffer. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_SPORT_INVALID_HANDLE Failed to retrieve the status of the buffer availability. + * - #ADI_SPORT_OPERATION_NOT_ALLOWED Function cannot be called (no buffer to be processed or callback function registered). + * - ADI_SPORT_PERIPHERAL_ERROR Hardware error detected + * + * @sa adi_sport_GetBuffer() + * @sa adi_sport_GetBuffer() + * + */ +ADI_SPORT_RESULT adi_sport_IsBufferAvailable(ADI_SPORT_HANDLE const hDevice, + bool * const pbAvailable) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + + *pbAvailable = false; +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice))) /* Validate the given handle */ + { + } + else +#endif /* ADI_DEBUG */ + if (NULL != pDevice->pfCallback) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else + { + ADI_DT_BUFF_INFO * pActiveBuffer = pDevice->sportChannel.pActiveBuffer; + + if (pActiveBuffer->pStartAddress == NULL) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else if (false == pActiveBuffer->bInUse) /* this buffer has been processed by the SPORT */ + { + *pbAvailable = true; + } + else + { + } + } + return result; +} + +/** + * @brief Register and unregister a Callback function with the SPORT device driver. + * A registered call back function will be called, if not NULL, when a buffer + * is processed OR hardware error(s) encountered. + * + * @param [in] hDevice Device handle to SPORT device is obtained when a SPORT device is opened + * successfully. + * + * @param [in] pfCallback Function pointer to Callback function. Passing a NULL pointer will + * unregister the call back function. + * + * @param [in] pCBparam Call back function parameter. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully registered specified callback function. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_RegisterCallback(ADI_SPORT_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void * const pCBparam) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + /* Check if the data flow is already enabled */ + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + /* Not allowed to register a callback if the data flow is enabled. */ + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pDevice->pfCallback = pfCallback; /* Store the address of the callback function */ + pDevice->pCBParam = pCBparam; /* Store the call back parameter */ + ADI_EXIT_CRITICAL_REGION(); + } + return result; +} + +/** + * @brief Sets data format for the specified SPORT device. + * + * @details Sets data type,Big endian (MSB first) OR Little endian (LSB first) and word + * length(in bits) for the specified SPORT device.This function return error if the + * device is already enabled. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nWordLength Specify the word size of the data. Valid range is from + * 4(nWordLength = 3) to 32(nWordLength =31). + * + * @param [in] bLSBFirst Configure the specified SPORT device to operate either LSB + * first or MSB first. + * \n + * \n true : LSB first (Little endian) . + * \n + * \n false : MSB first (Big endian) + * + * @param [in] ePackMode Mode of packging need to configured. Please refer #ADI_SPORT_PACKING_MODE. + * + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured the device to operate in + * specified data format. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_INVALID_WORD_LENGTH [D] Invalid word size. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigData(ADI_SPORT_HANDLE const hDevice, + const uint8_t nWordLength, + const ADI_SPORT_PACKING_MODE ePackMode, + const bool bLSBFirst + ) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) /* Not allowed to change when data flow is enabled */ + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + if (nWordLength > SPORT_WORD_TRANSFER_LENGTH) + { + result = ADI_SPORT_INVALID_WORD_LENGTH; + } + else + { + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + const uint32_t bytesPerData = ((nWordLength < 9u) ? (1u) : ((nWordLength < 17u) ? (2u) : (4u))); + + const uint32_t wordPos = (uint32_t) BITP_SPORT_CTL_A_SLEN; + const uint32_t wordLen = (uint32_t) nWordLength; + const uint32_t ctlSlen = (wordLen - 1u) << wordPos; + const uint32_t packMode = (uint32_t) ePackMode; + const uint32_t ctlSlenBits = (0x1Fu << wordPos); + const uint32_t ctlDataMask = ~(BITM_SPORT_DATA_CONFIG | ctlSlenBits | BITM_SPORT_CTL_A_LSBF); + + uint32_t ctl = pDevice->pSportInfo->sportCfg.CTL; + ctl &= ctlDataMask; /* clear all the fields(i.e Set to "0" ) */ + ctl |= (packMode | ctlSlen); /* assign packing and slen information */ + if (true == bLSBFirst) + { + ctl |= BITM_SPORT_CTL_A_LSBF; /* set the the LSB first field */ + } + pDevice->pSportInfo->sportCfg.CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pDevice->pSportInfo->sportCfg.CTL); + + switch (bytesPerData) + { + case 1u: + if (((uint32_t) ADI_SPORT_8BIT_PACKING) == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE; + + assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode); + } + break; + + case 2u: + if (((uint32_t) ADI_SPORT_16BIT_PACKING) == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE; + + assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode); + } + break; + + default: + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + assert((4u == bytesPerData) || (((uint32_t) ADI_SPORT_NO_PACKING) == packMode)); + break; + } + } + return result; +} + +/** + * @brief Configure the clock for the specified SPORT device. + * + * @details Configure the SPORT device to use the "internal/external " rising/falling clock + * edge,clock edge and for enabling the gated Clock Mode. + * + * @details fspclk = fsclk/(2*( nClockRatio + 1)) + * + * @details fspclk: frequency of SPORT clock + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nClockRatio The value which determines the ratio between System clock and SPORT + * clock as explained above. + * + * + * @param [in] bUseIntlClock Boolean flag to indicate whether to use internal clock or external + * clock for data transmission. By default, device is configured to use + * the external clock. + * \n + * \n true : Device configured to use Internal clock. + * \n + * \n false : Device configured to use external clock.. + * + * @param [in] bRisingEdge Boolean flag to indicate whether to drive data and internal frame + * sync with rising edge OR falling edge of SP clock. + * \n + * \n true : Use falling edge of the clock. + * \n + * \n false : Use rising edge of the clock. + * + * @param [in] bGatedClk Boolean flag to indicate whether to enable/disable gated clock for + * the specified SPORT channel.Ignored in Multi channel mode. Clock will + * be active only when active data is getting transmitted or received + * when this mode is enabled. + * \n true : Enable gated clock mode. + * \n + * \n false : Disable gated clock mode. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured clock for the specified device. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigClock(ADI_SPORT_HANDLE const hDevice, + const uint16_t nClockRatio, + const bool bUseIntlClock, + const bool bRisingEdge, + const bool bGatedClk) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ + +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t clockRatio = (uint32_t) nClockRatio; + + uint32_t ctl = pSportCfg->CTL; + uint32_t dv = pSportCfg->DIV; + + ctl &= ~BITM_SPORT_CLOCK_CONFIG; /* clear all clock configuration fields */ + + dv &= ~BITM_SPORT_DIV_A_CLKDIV; + dv |= (clockRatio & BITM_SPORT_DIV_A_CLKDIV); /* update the clock divisior value */ + + if (true == bUseIntlClock) + { + ctl |= BITM_SPORT_CTL_A_ICLK; /* select the internal clock */ + } + if (true == bRisingEdge) + { + ctl |= BITM_SPORT_CTL_A_CKRE; /* select the rising edge of the clock */ + } + if (true == bGatedClk) + { + ctl |= BITM_SPORT_CTL_A_GCLKEN; /* Enable the Gated clock */ + } + pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv; /* DIV value set */ + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** + * @brief Frame Sync(FS) configuration for the specified SPORT. + * + * @details Configure the SPORT to use internal/external frame sync,level/edge sensitive + * early/late frame sync etc. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nFsDivisor The value which decides the number of SPORT clock cycles between + * each frame count. + * + * @param [in] bFSRequired Boolean flag to indicate whether frame sync required OR not to + * the frame sync for the data transfer. + * \n + * \n true : Device requires a frame sync for its operation. + * \n + * \n false : Device does not requires a frame sync for its operation + * \n + * \n + * + * @param [in] bInternalFS Boolean flag to indicate whether to configure the specified SPORT + * device to use the internal frame sync OR external frame sync as + * below. + * \n + * \n true : Use internal frame sync. + * \n + * \n false : Use external frame sync + * \n + * \n + * + * @param [in] bDataFS Boolean flag to indicate whether to configure the specified SPORT + * device to use the data-independent frame sync OR Serial port uses + * a data-dependent frame sync. Valid only if the specified device is + * in "transmit"(TX)mode . Ignored if the device is opened in + * "receive"(RX) mode. + * \n + * \n true : Use data-independent frame sync. + * \n + * \n false : Use data-dependent frame sync. + * \n + * \n + * + * @param [in] bActiveLowFS Boolean flag to indicate whether to configure the specified SPORT + * device for active low frame sync OR active high frame sync. Call + * to this function will return error if SPORT is configured in I2S + * mode. + * \n + * \n true : Use active low frame sync. + * \n + * \n false : Use active high frame sync. + * \n + * \n + * + * @param [in] bLateFS Boolean flag to indicate whether to use the late frame sync OR + * Early frame sync. + * \n + * \n true : Use late frame sync. + * \n + * \n false : Use Early frame sync. + * \n + * \n + * +* @param [in] bFSErrorOperation Frame Sync Error Operation. This + *\n decides the way the SPORT responds when a frame sync error occurs. + * \n + * \n true : When frame Sync error occurs, discard the receive data. + * \n + * \n false : Flag the Frame Sync error and continue normal operation + * \n + * \n + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured the frame sync requirement. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigFrameSync(ADI_SPORT_HANDLE const hDevice, + const uint16_t nFsDivisor, + const bool bFSRequired, + const bool bInternalFS, + const bool bDataFS, + const bool bActiveLowFS, + const bool bLateFS, + const bool bFSErrorOperation) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + +#ifdef ADI_DEBUG + /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + const uint32_t fsDivisor = (uint32_t) nFsDivisor; + + uint32_t ctl = pSportCfg->CTL; + uint32_t dv = pSportCfg->DIV; + + dv &= ~BITM_SPORT_DIV_A_FSDIV; /* clear all the fields of frame sync */ + dv |= (fsDivisor << BITP_SPORT_DIV_A_FSDIV); + + ctl &= ~BITM_SPORT_FS_CONFIG; /* clear all the fields of frame sync */ + + if ((ADI_SPORT_DIR_RX == pDevice->eDirection) || (true == bDataFS)) + { + ctl |= BITM_SPORT_CTL_A_DIFS; /* Set this bit when SPORT is opened in RX mode */ + } + if (true == bFSRequired) /* "Frame sync required" is reserved when device */ + { /* is operating in I2S and MC mode */ + ctl |= BITM_SPORT_CTL_A_FSR; /* Frame Sync(FS) is required */ + } + if (true == bInternalFS) + { + ctl |= BITM_SPORT_CTL_A_IFS; /* Select the internal Frame Sync(FS)*/ + } + if (true == bActiveLowFS) + { + ctl |= BITM_SPORT_CTL_A_LFS; /* Select the Active High Frame Sync(FS)*/ + } + if (true == bLateFS) + { + ctl |= BITM_SPORT_CTL_A_LAFS; /* Select the Late Frame Sync(FS)*/ + } + if (true == bFSErrorOperation) + { + ctl |= BITM_SPORT_CTL_A_FSERRMODE; /* Select the edge sensitive Frame Sync(FS)*/ + } + pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv; /* DIV value set */ + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** + * @brief Configure the SPORT use the Clocks and Frame Sync of other Half-Sport + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] bUseOtherFS Boolean flag to indicate whether to use own Frame Sync(false) OR to + * use frame sync of other half SPORT (true). + * \n + * \n true : Use frame sync of other half SPORT device. + * \n + * \n false : Use own frame sync. + * + * @param [in] bUseOtherClk Boolean flag to indicate whether to use own clock clock(false) OR to + * use clock of other half SPORT(true). + * \n + * \n true : Use clock of other half SPORT device. + * \n + * \n false : Use own clock. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully enabled the specified SPORT to use the clk + * and FS of other half SPORT. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(ADI_SPORT_HANDLE const hDevice, + const bool bUseOtherFS, + const bool bUseOtherClk) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *)hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if((result = ValidateHandle(pDevice)) != ADI_SPORT_SUCCESS) /* Validate the given handle */ + { + } + else if (pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t ctl = pSportCfg->CTL; + + /* clear the muxing fields of the control register 2 */ + ctl &= (uint32_t)(~(BITM_SPORT_CTL_A_CKMUXSEL | BITM_SPORT_CTL_A_FSMUXSEL)); + if (true == bUseOtherFS) + { + ctl |= BITM_SPORT_CTL_A_FSMUXSEL; /* Use the the frame sync of other half sport*/ + } + if(bUseOtherClk == true) + { + ctl |= BITM_SPORT_CTL_A_CKMUXSEL; /* Use the the clock of other half sport*/ + } + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + + return result; +} +/** + * @brief Configure the SPORT use the Clocks and Frame Sync of other Half-Sport + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nFSDuration Specify the value of the number of clocks which would be programmed corresponding to the + * desired time duration from assertion of CONVT signal to Frame sync signal + * + * @param [in] nWidth Specify the value of the number of serial clocks for which CONVT signal should be active. + + * + * @param [in] bActiveLow Boolean flag to indicate the polarity of the Convt signal. + * \n + * \n true : Active low Polarity. + * \n + * \n false : Active High Polarity. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully enabled the specified SPORT to use the clk + * and FS of other half SPORT. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigTimerMode(ADI_SPORT_HANDLE const hDevice, + const uint8_t nFSDuration, + const uint8_t nWidth, + const bool bActiveLow) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + +#ifdef ADI_DEBUG /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t cnvt = pSportCfg->TIM_CONVT; + + /* clear the muxing fields of the control register 2 */ + cnvt &= (uint32_t)(~(BITM_SPORT_CNVT_A_POL | BITM_SPORT_CNVT_A_WID | BITM_SPORT_CNVT_A_CNVT2FS )); + cnvt |= (((uint32_t) nFSDuration << ((uint32_t) BITP_SPORT_CNVT_A_CNVT2FS)) | ((uint32_t) nWidth)); + if(bActiveLow == true) + { + cnvt |= ((uint32_t) BITM_SPORT_CNVT_A_POL); /* Use the the clock of other half sport*/ + } + pDevice->pSportInfo->pSportRegs->CNVT_A = pSportCfg->TIM_CONVT = cnvt; + } + return result; +} + +/*! \cond PRIVATE */ + +/** + * @brief Create a circular linked list for buffer management. + * + * @details Create a circular linked list for buffer management and + * initialize the free buffer, the fill buffer and he active + * buffer with the first buffer in this circular array. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] NumDesc Number of descriptorS. + * + */ +static inline void sport_Init (ADI_SPORT_DEVICE *pDevice) +{ + uint32_t i; + ADI_DT_CHANNEL *pChannel = &pDevice->sportChannel; + ADI_DT_BUFF_INFO *pBufInfo = &pChannel->BufInfo[0]; /* initialize this variable with the first array element */ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); /* number of bytes in SPORT data (1, 2, or 4) */ + const uint32_t packMode = SPORT_GET_PACKEN(pSportCfg->CTL); /* SPORT data pack mode */ + + /* Initialize the all descriptors. Make it circular. */ + for(i = 0u; i < ADI_DT_BUFNUM; i++) + { + pBufInfo[i].pStartAddress = NULL; + pBufInfo[i].nCount = 0u; + pBufInfo[i].nIndex = 0u; + pBufInfo[i].pNextBuffer = &pBufInfo[(i+1u) % ADI_DT_BUFNUM]; /* link the buffers in a circular way */ + } + pChannel->pFreeBuffer = &pChannel->BufInfo[0u]; /* the first free buffer is the first array element */ + pChannel->pActiveBuffer = &pChannel->BufInfo[0u]; /* the first active buffer is the first array element */ + pChannel->pFillBuffer = &pChannel->BufInfo[0u]; /* the first fill buffer is the first array element */ + + switch (bytesPerData) + { + case 1u: + if (SPORT_BIT_PACK_8 == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE; + + assert(SPORT_BIT_PACK_NONE == packMode); + } + break; + + case 2u: + if (SPORT_BIT_PACK_16 == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE; + + assert(SPORT_BIT_PACK_NONE == packMode); + } + break; + + default: + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + assert((4u == bytesPerData) || (SPORT_BIT_PACK_NONE == packMode)); + break; + } +} + +/* + * @brief Configure the registers with the half-SPORT + * + * @param [in] hDevice Device handle to SPORT device. + * @param [in] sportCfg SPORT configuration to be used. + * + * @return None + */ +static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg) +{ + /* Configure the SPORT device using static configuration parameters. + * pSportInfo is mapped to one of the half-SPORT available; this is the + * half-SPORT configured. (CTL_A, DIV_A, CNVT_A and NUMTRAN_A map either + * to half-SPORT A registers or half-SPORT B registers, depending on + * sportRegs.) + */ + volatile ADI_SPORT_TypeDef * sportRegs = pDevice->pSportInfo->pSportRegs; + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + + /* record the SPORT default configuration */ + memcpy(pSportCfg, sportCfg, sizeof(ADI_SPORT_CONFIG)); + + switch (pDevice->eDirection) /* Set the direction of operation */ + { + case ADI_SPORT_DIR_RX: + pSportCfg->CTL &= ~BITM_SPORT_CTL_A_SPTRAN; + break; + case ADI_SPORT_DIR_TX: + pSportCfg->CTL |= BITM_SPORT_CTL_A_SPTRAN; + break; + default: + assert(0); + break; + } + /* use the SPORT configuration to setup the SPORT registers */ + sportRegs->CTL_A = pSportCfg->CTL; + sportRegs->DIV_A = pSportCfg->DIV; + sportRegs->CNVT_A = pSportCfg->TIM_CONVT; + sportRegs->NUMTRAN_A = 0u; + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); +} + +#ifdef ADI_DEBUG +static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice) +{ + ADI_SPORT_RESULT result = ADI_SPORT_INVALID_HANDLE; + ADI_SPORT_DEVICE * pInDevice = (ADI_SPORT_DEVICE*) hDevice; + ADI_SPORT_DEVICE_INFO *poDeviceInfo = &gSportDevInfo[0][0]; + uint32_t i; + + /* Pointer to SPORT device instance */ + for (i=0u; i<(ADI_SPORT_NUM_INSTANCES << 1u); i++) /* 2 half-devices per SPORT */ + { + if (pInDevice == poDeviceInfo->hDevice) + { + result = ADI_SPORT_SUCCESS; + break; + } + poDeviceInfo++; + } + return result; +} +#endif /* ADI_DEBUG */ + +/* mask for events to be recorded in the driver HW error */ +#define recEvt ((uint32_t) (BITM_SPORT_STAT_A_SYSDATERR | BITM_SPORT_STAT_A_FSERR | BITM_SPORT_STAT_A_DERR)) + +/* bits to be cleared by the ISR */ +#define clrEvt ((recEvt | BITM_SPORT_STAT_A_TFI)) + +static void sport_Terminate(ADI_SPORT_DEVICE * pDevice) +{ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* get SPORT device information */ + volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs; /* access SPORT registers */ + + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + ADI_DT_BUFF_INFO * pBuff = pSportChnl->pFillBuffer; + + pRegs->CTL_A &= ~BITM_SPORT_CTL_A_SPEN; /* disable SPORT */ + pRegs->IEN_A &= ~(BITM_SPORT_IEN_A_TF | BITM_SPORT_IEN_A_DATA); /* disable SPORT interrupts */ + pRegs->NUMTRAN_A = 0u; + +#ifdef ADI_DEBUG + { + /* ============================================= */ + /* Check the number of data transmitted/received */ + /* nIndex is incremented each time a data packed */ + /* or unpacked in received. The size in bytes of */ + /* each data depends on the SPORT configuration. */ + /* In core driven operations, nCount represents */ + /* the number of 32-bit words transmitted. */ + /* In DMA driven operations, nCount represents */ + /* the number of DMA data transmitted */ + /* ============================================= */ + const uint32_t ctl = pRegs->CTL_A; + const uint32_t bytesPerData = GetBytesPerSportData(ctl); + const uint32_t nIndex = pBuff->nIndex * (4u / bytesPerData); + assert((nIndex>=pBuff->nCount)||(true==pBuff->bDMA)); /* buffer must be fully processed */ + } +#endif + + pBuff->bInUse = false; /* mark buffer as ready */ + + NVIC_DisableIRQ(pSportInfo->eIRQn); /* suspend SPORT Interrupt */ + NVIC_DisableIRQ(pSportInfo->eDMAn); /* suspend SPORT DMA interrupt */ + + pDevice->pSportInfo->eState = ADI_SPORT_STATE_PAUSED; + + if(NULL != pDevice->pfCallback) /* Call the callback function if one is registered. */ + { + uint32_t evt = ( (ADI_SPORT_DIR_RX == pDevice->eDirection) + ? ((uint32_t) ADI_SPORT_EVENT_RX_BUFFER_PROCESSED) + : ((uint32_t) ADI_SPORT_EVENT_TX_BUFFER_PROCESSED) + ); + + pDevice->pfCallback(pDevice->pCBParam,evt,pBuff->pStartAddress); + pBuff->pStartAddress = NULL; /* No need to keep the processed buffer address */ + } + else + { + SEM_POST(pSportChnl); /* signal the buffer availability through a semaphore */ + } + pRegs->STAT_A = clrEvt; /* clear status register bits (W1C) */ + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + pBuff = pBuff->pNextBuffer; /* point to the next buffer to process */ + pSportChnl->pFillBuffer = pBuff; /* this is the new pFillBuffer */ + + if ((0u != pBuff->pStartAddress) && (true == pBuff->bInUse)) /* valid buffer not being processed yet */ + { + ADI_SPORT_RESULT result; + + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING; + if (true == pBuff->bDMA) + { + result = sport_SubmitBufferDmaMode(pDevice, pBuff); + } + else + { + result = sport_SubmitBufferIntMode(pDevice, pBuff); + } + + if(ADI_SPORT_SUCCESS != result) /* if an error occurred...*/ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + } + } +} + +/* + * @brief Common SPORT interrupt handler function called by SPORT0 A and SPORT0 B ISRs. + * + * @details Process SPORT0 A and B interrupts, recording HW errors that must be reported, + * reading/writing transmitted data, launching new SPORT transmissions if more + * buffers are to be processed, and deactivating the SPORT device if there are + * no pending requests. (Common fucntion for both core driven and DMA driven + * SPORT operations.) + * + * @param [in] pDevice Sport device pointer related to the calling ISR. + */ +static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice) +{ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* get SPORT device information */ + volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs; /* access SPORT registers */ + const uint32_t sportStatus = pRegs->STAT_A; /* read SPORT status */ + const uint32_t dataRequest = (sportStatus & BITM_SPORT_STAT_A_DATA);/* set if any data to be processed by the SPORT */ + const uint32_t hwEvents = sportStatus & recEvt; /* HW events to be recorded in the driver */ + + + /* This implementation assumes an identity mapping between BITM_SPORT_STAT values + * and their equivalent event in ADI_SPORT_EVENT, e.g. ADI_SPORT_HW_ERR_FS and + * BITM_SPORT_STAT_A_FSERR share the same value. This simplifies event processing + * and reports. */ + assert(((uint32_t) ADI_SPORT_HW_ERR_RX_OVERFLOW) == BITM_SPORT_STAT_A_DERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_TX_UNDERFLOW) == BITM_SPORT_STAT_A_DERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_FS) == BITM_SPORT_STAT_A_FSERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_SYSDATAERR) == BITM_SPORT_STAT_A_SYSDATERR); + + if (0u != hwEvents) /* any event recorded? */ + { + if (NULL != pDevice->pfCallback) /* if a callback has been registered ? */ + { + pDevice->pfCallback(pDevice->pCBParam,hwEvents,NULL); /* then call it */ + } else { + pDevice->nHwError |= hwEvents; /* else set the driver HW error */ + SEM_POST(&pDevice->sportChannel); /* and signal this through a semaphore */ + } + } + + if (0u != dataRequest) /* Tx FIFO is not full or Rx FIFO is not empty */ + { + ADI_DT_BUFF_INFO * pBuff = pDevice->sportChannel.pFillBuffer; + uint32_t * pNextWord = (uint32_t*) pBuff->pStartAddress; + + if ((NULL != pNextWord) && (pBuff->nIndex < pBuff->nCount)) /* This buffer has not been fully processed yet */ + { + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + pNextWord[pBuff->nIndex++] = pRegs->RX_A; /* Read the data received in RX and increment the index */ + while (!DXS_FIFO_IS_EMPTY(pRegs->STAT_A)) /* and if there are more data available in the FIFO */ + { + pNextWord[pBuff->nIndex++] = pRegs->RX_A; /* Read remaining data received in RX and increment the index */ + } + } + else + { + pRegs->TX_A = pNextWord[pBuff->nIndex++]; /* Write the data to be sent into TX and increment the index */ + while ( (pBuff->nIndex < pBuff->nCount) /* and if there are more data to be sent */ + && (!DXS_FIFO_IS_FULL(pRegs->STAT_A)) /* and there is still room in the FIFO */ + ) + { + pRegs->TX_A = pNextWord[pBuff->nIndex++]; /* then write more data to be sent into TX and increment the index */ + } + } + } + } + + /* ========================================================== */ + /* Common to core driven operations and DMA driven operations */ + /* ========================================================== */ + if (0u != (pRegs->STAT_A & BITM_SPORT_STAT_A_TFI)) /* If a SPORT Tx/Rx request has finished */ + { + sport_Terminate(pDevice); + } + +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif +} + +/** Interrupt handler for SPORT0 A */ +void SPORT0A_Int_Handler(void) +{ + ISR_PROLOG(); + sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice); + ISR_EPILOG(); +} + +/** Interrupt handler for SPORT0 B */ +void SPORT0B_Int_Handler(void) +{ + ISR_PROLOG(); + sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice); + ISR_EPILOG(); +} + +void DMA_SPORT0A_Int_Handler(void) +{ + ISR_PROLOG(); + /** + * if SPORT is in Rx mode, then the DMA interrupt is the signal for + * end of transmission: buffer is ready. (In Tx mode, the signal is + * the TFI event and SPORT DMA interrup is not enabled). + */ + sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice); +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif + ISR_EPILOG(); +} + +void DMA_SPORT0B_Int_Handler(void) +{ + ISR_PROLOG(); + /** + * if SPORT is in Rx mode, then the DMA interrupt is the signal for + * end of transmission: buffer is ready. (In Tx mode, the signal is + * the TFI event and SPORT DMA interrup is not enabled). + */ + sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice); +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif + ISR_EPILOG(); +} + +static void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) pCBParam; /* Recover the device handle. */ + ADI_DT_BUFF_INFO * pFillBuffer = pDevice->sportChannel.pFillBuffer; + ADI_DT_BUFF_INFO * pNextBuffer = pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + if (ADI_DMA_EVENT_ERR_BUS == Event) + { + nEvent = (uint32_t) ADI_SPORT_DMA_ERR_BUS; /* SPORT DMA bus error detected */ + } else { + assert(ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR == Event); + nEvent = (uint32_t) ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR; /* SPORT DMA invalid descriptor error detected */ + } + + pDevice->nHwError |= nEvent; + sport_InterruptHandler(pDevice); + + while ( (NULL != pNextBuffer->pStartAddress) + && (true == pNextBuffer->bInUse) + && (true == pNextBuffer->bDMA) + ) /* another buffer is pending for a DMA driven request */ + { + pDevice->nHwError |= nEvent; + pNextBuffer->bInUse = false; + sport_InterruptHandler(pDevice); + pNextBuffer = pNextBuffer->pNextBuffer; + } +} + +static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal) +{ + const uint32_t wlen = SPORT_GET_WLEN(ctlVal); + const uint32_t bytesPerData = ((wlen < 9u) ? (1u) : ((wlen < 17u) ? (2u) : (4u))); + return bytesPerData; +} + +/*! \endcond */ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport_def.h new file mode 100755 index 00000000000..7244562e9ae --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sport/adi_sport_def.h @@ -0,0 +1,193 @@ +/*! ***************************************************************************** + * @file: adi_sport_def.h + * @brief: UART Device Driver definition for processor + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \cond PRIVATE */ +#ifndef ADI_SPORT_DEF_H +#define ADI_SPORT_DEF_H + +#include + +#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) +#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " +#endif + +#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) +#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " +#endif + +#define ADI_SPORT_NUM_INSTANCES (1u) /*!< Number of SPORT devices available */ +#define ADI_SPORT_NUM_CHANNELS (2u) /*!< Number of SPORT channel for each SPORT devcie */ + +#define BITM_SPORT_DATA_CONFIG ( BITM_SPORT_CTL_A_LSBF \ + | BITM_SPORT_CTL_A_PACK) + +#define BITM_SPORT_CLOCK_CONFIG ( BITM_SPORT_CTL_A_ICLK \ + | BITM_SPORT_CTL_A_CKRE \ + | BITM_SPORT_CTL_A_GCLKEN) + +#define BITM_SPORT_FS_CONFIG ( BITM_SPORT_CTL_A_FSR \ + | BITM_SPORT_CTL_A_IFS \ + | BITM_SPORT_CTL_A_DIFS \ + | BITM_SPORT_CTL_A_LFS \ + | BITM_SPORT_CTL_A_LAFS \ + | BITM_SPORT_CTL_A_FSERRMODE) + +#define SPORT_BYTE_TRANSFER_LENGTH (8u) +#define SPORT_HALFWORD_TRANSFER_LENGTH (16u) +#define SPORT_WORD_TRANSFER_LENGTH (32u) + +#define SPORT_GET_WLEN(ctlVal) ((((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_SLEN) >> ((uint32_t) BITP_SPORT_CTL_A_SLEN)) + 1u) +#define SPORT_GET_PACKEN(ctlVal) ((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_PACK) >> ((uint32_t) BITP_SPORT_CTL_A_PACK) + +#define SPORT_CHECK_CFG_CTL(CFG) assert(0u == ((CFG) & (((uint32_t)BITM_SPORT_CTL_A_SPEN) | ((uint32_t)BITM_SPORT_CTL_A_DMAEN)))) + + +#define SPORT_BIT_PACK_NONE (((uint32_t) ADI_SPORT_NO_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) +#define SPORT_BIT_PACK_8 (((uint32_t) ADI_SPORT_8BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) +#define SPORT_BIT_PACK_16 (((uint32_t) ADI_SPORT_16BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) + +/*! + ***************************************************************************** + * \struct ADI_SPORT_STATE + * Enumeration of different SPORT states. + *****************************************************************************/ +typedef enum +{ + ADI_SPORT_STATE_UNINITIALIZED = 0, /*!< SPORT is not yet initialized */ + ADI_SPORT_STATE_INITIALIZED, /*!< SPORT is initialized */ + ADI_SPORT_STATE_DATA_FLOW_ENABLED, /*!< SPORT Tx or Rx data flow is enabled (SPORT peripheral cannot be re-configured) */ + ADI_SPORT_STATE_DATA_FLOW_DISABLED, /*!< SPORT Tx or Rx data flow is disabled (SPORT peripheral can be re-configured) */ + ADI_SPORT_STATE_PAUSED +} ADI_SPORT_STATE; + +/*! + ***************************************************************************** + * \struct ADI_SPORT_CONFIG + * Structure for initializing the static config. + *****************************************************************************/ + +typedef struct _ADI_SPORT_CONFIG +{ + uint32_t CTL; /*!< SPORT_CTL register. */ + uint32_t DIV; /*!< SPORT_DIV register. */ + uint32_t TIM_CONVT; /*!< TIM_CONVT Register. */ + uint32_t DMA_WIDTH; /*!< DMA_WIDTH */ + uint32_t DMA_INC; /*!< DMA_INC */ +} ADI_SPORT_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_SPORT_DEVICE_INFO + * SPORT device information. + *****************************************************************************/ +typedef struct _ADI_SPORT_DEVICE_INFO +{ + volatile ADI_SPORT_TypeDef* pSportRegs; /*!< Base address of the SPORT registers */ + ADI_SPORT_CONFIG sportCfg; /*!< SPORT configuration data */ + ADI_SPORT_STATE eState; /*!< To indicate the state of the device */ + const DMA_CHANn_TypeDef eDMAChnlID; /*!< DMA channel ID */ + const IRQn_Type eDMAn; /*!< DMA channel IRQ identifier */ + const IRQn_Type eIRQn; /*!< SPORT IRQ identifier */ + ADI_SPORT_HANDLE hDevice; /*!< SPORT handle */ +} ADI_SPORT_DEVICE_INFO; + +/****************************************************************************** + * SPORT Device internal API function prototypes + *****************************************************************************/ + +#define NUM_SPORT_BUFFER (2u) + +/** SPORT driver instance data */ +typedef struct _ADI_SPORT_DEVICE +{ + ADI_SPORT_DEVICE_INFO * pSportInfo; /*!< pointer to the structure which stores the information about the SPORT instances.*/ + ADI_SPORT_DIRECTION eDirection; /*!< Direction in which the SPORT is opened */ + ADI_CALLBACK pfCallback; /*!< Function pointer for callback function. */ + void * pCBParam; /*!< Parameter to callback function. */ + ADI_DT_CHANNEL sportChannel; /*!< SPORT channel to manage transmitted data buffers */ + volatile uint32_t nHwError; /*!< variable to store the hardware status */ +} ADI_SPORT_DEVICE; + +/** Initialize a SPORT device */ +static inline void sport_Init (ADI_SPORT_DEVICE * pDevice); + +/** Configure a SPORT device */ +static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg); + +/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff); + +/** Function prototype for submitting a buffer for SPORT Rx or Tx core driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff); + +/** Fucntion prototype for completing a SPORT transmission (Rx or Tx) */ +static void sport_Terminate(ADI_SPORT_DEVICE * pDevice); + +/** Interrupt Handlers */ + +/** SPORT interrupt handler */ +static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice); + +static inline void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); + +static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal); + +/* + * Handle Validation function +*/ +#ifdef ADI_DEBUG +static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice); +#endif /* ADI_DEBUG */ + +#endif /* end of ifndef ADI_SPORT_DEF_H */ +/*! \endcond */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x.h new file mode 100755 index 00000000000..6794f1840ae --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x.h @@ -0,0 +1,4494 @@ +/* ================================================================================ + + Project : ADuCM302x + File : ADuCM302x.h + Description : Register Definitions + + Date : Feb 6, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _DEF_ADUCM302X_H +#define _DEF_ADUCM302X_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + + +#if defined (_MISRA_RULES) +#pragma diag(push) +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros") +#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators") +#endif /* _MISRA_RULES */ + +/* _ADI_MSK_3 might be defined in wrapper includes - otherwise provide a default */ +#if !defined(_ADI_MSK_3) +/* do not add casts to literal constants in assembly code */ +#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__) +/* Use unsuffixed literals for BITM macros */ +#define _ADI_MSK_3( mask, smask, type ) (mask) +#else +/* Use casted suffixed literals for BITM macros */ +#define _ADI_MSK_3( mask, smask, type ) ((type)(smask)) +#endif +#endif + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_ADC__ 1 +#define __ADI_HAS_BEEP__ 1 +#define __ADI_HAS_BUSM__ 1 +#define __ADI_HAS_CLKG_OSC__ 1 +#define __ADI_HAS_CLKG__ 1 +#define __ADI_HAS_CLKG_CLK__ 1 +#define __ADI_HAS_CRC__ 1 +#define __ADI_HAS_CRYPT__ 1 +#define __ADI_HAS_DMA__ 1 +#define __ADI_HAS_XINT__ 1 +#define __ADI_HAS_FLCC__ 1 +#define __ADI_HAS_FLCC_CACHE__ 1 +#define __ADI_HAS_FLCC_DFT__ 1 +#define __ADI_HAS_FLCC_TEST__ 1 +#define __ADI_HAS_GPIO__ 1 +#define __ADI_HAS_TMR__ 1 +#define __ADI_HAS_I2C__ 1 +#define __ADI_HAS_NVIC__ 1 +#define __ADI_HAS_PMG__ 1 +#define __ADI_HAS_PMG_TST__ 1 +#define __ADI_HAS_PTI__ 1 +#define __ADI_HAS_RNG__ 1 +#define __ADI_HAS_RTC__ 1 +#define __ADI_HAS_SPI__ 1 +#define __ADI_HAS_SPORT__ 1 +#define __ADI_HAS_SYS__ 1 +#define __ADI_HAS_UART__ 1 +#define __ADI_HAS_WDT__ 1 + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + TMR0 + ============================================================================================================================ */ +#define REG_TMR0_LOAD 0x40000000 /* TMR0 16-bit Load Value */ +#define REG_TMR0_CURCNT 0x40000004 /* TMR0 16-bit Timer Value */ +#define REG_TMR0_CTL 0x40000008 /* TMR0 Control */ +#define REG_TMR0_CLRINT 0x4000000C /* TMR0 Clear Interrupt */ +#define REG_TMR0_CAPTURE 0x40000010 /* TMR0 Capture */ +#define REG_TMR0_ALOAD 0x40000014 /* TMR0 16-bit Load Value, Asynchronous */ +#define REG_TMR0_ACURCNT 0x40000018 /* TMR0 16-bit Timer Value, Asynchronous */ +#define REG_TMR0_STAT 0x4000001C /* TMR0 Status */ +#define REG_TMR0_PWMCTL 0x40000020 /* TMR0 PWM Control Register */ +#define REG_TMR0_PWMMATCH 0x40000024 /* TMR0 PWM Match Value */ + +/* ============================================================================================================================ + TMR1 + ============================================================================================================================ */ +#define REG_TMR1_LOAD 0x40000400 /* TMR1 16-bit Load Value */ +#define REG_TMR1_CURCNT 0x40000404 /* TMR1 16-bit Timer Value */ +#define REG_TMR1_CTL 0x40000408 /* TMR1 Control */ +#define REG_TMR1_CLRINT 0x4000040C /* TMR1 Clear Interrupt */ +#define REG_TMR1_CAPTURE 0x40000410 /* TMR1 Capture */ +#define REG_TMR1_ALOAD 0x40000414 /* TMR1 16-bit Load Value, Asynchronous */ +#define REG_TMR1_ACURCNT 0x40000418 /* TMR1 16-bit Timer Value, Asynchronous */ +#define REG_TMR1_STAT 0x4000041C /* TMR1 Status */ +#define REG_TMR1_PWMCTL 0x40000420 /* TMR1 PWM Control Register */ +#define REG_TMR1_PWMMATCH 0x40000424 /* TMR1 PWM Match Value */ + +/* ============================================================================================================================ + TMR2 + ============================================================================================================================ */ +#define REG_TMR2_LOAD 0x40000800 /* TMR2 16-bit Load Value */ +#define REG_TMR2_CURCNT 0x40000804 /* TMR2 16-bit Timer Value */ +#define REG_TMR2_CTL 0x40000808 /* TMR2 Control */ +#define REG_TMR2_CLRINT 0x4000080C /* TMR2 Clear Interrupt */ +#define REG_TMR2_CAPTURE 0x40000810 /* TMR2 Capture */ +#define REG_TMR2_ALOAD 0x40000814 /* TMR2 16-bit Load Value, Asynchronous */ +#define REG_TMR2_ACURCNT 0x40000818 /* TMR2 16-bit Timer Value, Asynchronous */ +#define REG_TMR2_STAT 0x4000081C /* TMR2 Status */ +#define REG_TMR2_PWMCTL 0x40000820 /* TMR2 PWM Control Register */ +#define REG_TMR2_PWMMATCH 0x40000824 /* TMR2 PWM Match Value */ + +/* ============================================================================================================================ + TMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_LOAD_VALUE 0 /* Load Value */ +#define BITM_TMR_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CURCNT_VALUE 0 /* Current Count */ +#define BITM_TMR_CURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CTL_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_TMR_CTL_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_TMR_CTL_EVTEN 13 /* Event Select */ +#define BITP_TMR_CTL_EVTRANGE 8 /* Event Select Range */ +#define BITP_TMR_CTL_RLD 7 /* Reload Control */ +#define BITP_TMR_CTL_CLK 5 /* Clock Select */ +#define BITP_TMR_CTL_EN 4 /* Timer Enable */ +#define BITP_TMR_CTL_MODE 3 /* Timer Mode */ +#define BITP_TMR_CTL_UP 2 /* Count up */ +#define BITP_TMR_CTL_PRE 0 /* Prescaler */ +#define BITM_TMR_CTL_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_TMR_CTL_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_TMR_CTL_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_TMR_CTL_EVTRANGE (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ +#define BITM_TMR_CTL_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_TMR_CTL_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_TMR_CTL_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_TMR_CTL_MODE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_TMR_CTL_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_TMR_CTL_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CLRINT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CLRINT_EVTCAPT 1 /* Clear Captured Event Interrupt */ +#define BITP_TMR_CLRINT_TIMEOUT 0 /* Clear Timeout Interrupt */ +#define BITM_TMR_CLRINT_EVTCAPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_TMR_CLRINT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CAPTURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CAPTURE_VALUE 0 /* 16-bit Captured Value */ +#define BITM_TMR_CAPTURE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_ALOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_ALOAD_VALUE 0 /* Load Value, Asynchronous */ +#define BITM_TMR_ALOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_ACURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_ACURCNT_VALUE 0 /* Counter Value */ +#define BITM_TMR_ACURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_STAT_CNTRST 8 /* Counter Reset Occurring */ +#define BITP_TMR_STAT_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_TMR_STAT_BUSY 6 /* Timer Busy */ +#define BITP_TMR_STAT_CAPTURE 1 /* Capture Event Pending */ +#define BITP_TMR_STAT_TIMEOUT 0 /* Timeout Event Occurred */ +#define BITM_TMR_STAT_CNTRST (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_TMR_STAT_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_TMR_STAT_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_TMR_STAT_CAPTURE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_TMR_STAT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_PWMCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_PWMCTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_PWMCTL_MATCH 0 /* PWM Match Enabled */ +#define BITM_TMR_PWMCTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_PWMCTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled */ +#define ENUM_TMR_PWMCTL_IDLE_LOW (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IDLESTATE: PWM idles low */ +#define ENUM_TMR_PWMCTL_IDLE_HIGH (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IDLESTATE: PWM idles high */ +#define ENUM_TMR_PWMCTL_PWM_TOGGLE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MATCH: PWM in toggle mode */ +#define ENUM_TMR_PWMCTL_PWM_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* MATCH: PWM in match mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_PWMMATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_PWMMATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_PWMMATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + + +/* ============================================================================================================================ + Real-Time Clock + ============================================================================================================================ */ + +/* ============================================================================================================================ + RTC0 + ============================================================================================================================ */ +#define REG_RTC0_CR0 0x40001000 /* RTC0 RTC Control 0 */ +#define REG_RTC0_SR0 0x40001004 /* RTC0 RTC Status 0 */ +#define REG_RTC0_SR1 0x40001008 /* RTC0 RTC Status 1 */ +#define REG_RTC0_CNT0 0x4000100C /* RTC0 RTC Count 0 */ +#define REG_RTC0_CNT1 0x40001010 /* RTC0 RTC Count 1 */ +#define REG_RTC0_ALM0 0x40001014 /* RTC0 RTC Alarm 0 */ +#define REG_RTC0_ALM1 0x40001018 /* RTC0 RTC Alarm 1 */ +#define REG_RTC0_TRM 0x4000101C /* RTC0 RTC Trim */ +#define REG_RTC0_GWY 0x40001020 /* RTC0 RTC Gateway */ +#define REG_RTC0_CR1 0x40001028 /* RTC0 RTC Control 1 */ +#define REG_RTC0_SR2 0x4000102C /* RTC0 RTC Status 2 */ +#define REG_RTC0_SNAP0 0x40001030 /* RTC0 RTC Snapshot 0 */ +#define REG_RTC0_SNAP1 0x40001034 /* RTC0 RTC Snapshot 1 */ +#define REG_RTC0_SNAP2 0x40001038 /* RTC0 RTC Snapshot 2 */ +#define REG_RTC0_MOD 0x4000103C /* RTC0 RTC Modulo */ +#define REG_RTC0_CNT2 0x40001040 /* RTC0 RTC Count 2 */ +#define REG_RTC0_ALM2 0x40001044 /* RTC0 RTC Alarm 2 */ +#define REG_RTC0_SR3 0x40001048 /* RTC0 RTC Status 3 */ +#define REG_RTC0_CR2IC 0x4000104C /* RTC0 RTC Control 2 for Configuring Input Capture Channels */ +#define REG_RTC0_CR3SS 0x40001050 /* RTC0 RTC Control 3 for Configuring SensorStrobe Channel */ +#define REG_RTC0_CR4SS 0x40001054 /* RTC0 RTC Control 4 for Configuring SensorStrobe Channel */ +#define REG_RTC0_SSMSK 0x40001058 /* RTC0 RTC Mask for SensorStrobe Channel */ +#define REG_RTC0_SS1ARL 0x4000105C /* RTC0 RTC Auto-Reload for SensorStrobe Channel 1 */ +#define REG_RTC0_IC2 0x40001064 /* RTC0 RTC Input Capture Channel 2 */ +#define REG_RTC0_IC3 0x40001068 /* RTC0 RTC Input Capture Channel 3 */ +#define REG_RTC0_IC4 0x4000106C /* RTC0 RTC Input Capture Channel 4 */ +#define REG_RTC0_SS1 0x40001070 /* RTC0 RTC SensorStrobe Channel 1 */ +#define REG_RTC0_SR4 0x40001080 /* RTC0 RTC Status 4 */ +#define REG_RTC0_SR5 0x40001084 /* RTC0 RTC Status 5 */ +#define REG_RTC0_SR6 0x40001088 /* RTC0 RTC Status 6 */ +#define REG_RTC0_SS1TGT 0x4000108C /* RTC0 RTC SensorStrobe Channel 1 Target */ +#define REG_RTC0_FRZCNT 0x40001090 /* RTC0 RTC Freeze Count */ + +/* ============================================================================================================================ + RTC1 + ============================================================================================================================ */ +#define REG_RTC1_CR0 0x40001400 /* RTC1 RTC Control 0 */ +#define REG_RTC1_SR0 0x40001404 /* RTC1 RTC Status 0 */ +#define REG_RTC1_SR1 0x40001408 /* RTC1 RTC Status 1 */ +#define REG_RTC1_CNT0 0x4000140C /* RTC1 RTC Count 0 */ +#define REG_RTC1_CNT1 0x40001410 /* RTC1 RTC Count 1 */ +#define REG_RTC1_ALM0 0x40001414 /* RTC1 RTC Alarm 0 */ +#define REG_RTC1_ALM1 0x40001418 /* RTC1 RTC Alarm 1 */ +#define REG_RTC1_TRM 0x4000141C /* RTC1 RTC Trim */ +#define REG_RTC1_GWY 0x40001420 /* RTC1 RTC Gateway */ +#define REG_RTC1_CR1 0x40001428 /* RTC1 RTC Control 1 */ +#define REG_RTC1_SR2 0x4000142C /* RTC1 RTC Status 2 */ +#define REG_RTC1_SNAP0 0x40001430 /* RTC1 RTC Snapshot 0 */ +#define REG_RTC1_SNAP1 0x40001434 /* RTC1 RTC Snapshot 1 */ +#define REG_RTC1_SNAP2 0x40001438 /* RTC1 RTC Snapshot 2 */ +#define REG_RTC1_MOD 0x4000143C /* RTC1 RTC Modulo */ +#define REG_RTC1_CNT2 0x40001440 /* RTC1 RTC Count 2 */ +#define REG_RTC1_ALM2 0x40001444 /* RTC1 RTC Alarm 2 */ +#define REG_RTC1_SR3 0x40001448 /* RTC1 RTC Status 3 */ +#define REG_RTC1_CR2IC 0x4000144C /* RTC1 RTC Control 2 for Configuring Input Capture Channels */ +#define REG_RTC1_CR3SS 0x40001450 /* RTC1 RTC Control 3 for Configuring SensorStrobe Channel */ +#define REG_RTC1_CR4SS 0x40001454 /* RTC1 RTC Control 4 for Configuring SensorStrobe Channel */ +#define REG_RTC1_SSMSK 0x40001458 /* RTC1 RTC Mask for SensorStrobe Channel */ +#define REG_RTC1_SS1ARL 0x4000145C /* RTC1 RTC Auto-Reload for SensorStrobe Channel 1 */ +#define REG_RTC1_IC2 0x40001464 /* RTC1 RTC Input Capture Channel 2 */ +#define REG_RTC1_IC3 0x40001468 /* RTC1 RTC Input Capture Channel 3 */ +#define REG_RTC1_IC4 0x4000146C /* RTC1 RTC Input Capture Channel 4 */ +#define REG_RTC1_SS1 0x40001470 /* RTC1 RTC SensorStrobe Channel 1 */ +#define REG_RTC1_SR4 0x40001480 /* RTC1 RTC Status 4 */ +#define REG_RTC1_SR5 0x40001484 /* RTC1 RTC Status 5 */ +#define REG_RTC1_SR6 0x40001488 /* RTC1 RTC Status 6 */ +#define REG_RTC1_SS1TGT 0x4000148C /* RTC1 RTC SensorStrobe Channel 1 Target */ +#define REG_RTC1_FRZCNT 0x40001490 /* RTC1 RTC Freeze Count */ + +/* ============================================================================================================================ + RTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR0_WPNDINTEN 15 /* Enable Write Pending Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_WSYNCINTEN 14 /* Enable Write Synchronization Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_WPNDERRINTEN 13 /* Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ +#define BITP_RTC_CR0_ISOINTEN 12 /* Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ +#define BITP_RTC_CR0_MOD60ALMINTEN 11 /* Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_MOD60ALM 5 /* Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ +#define BITP_RTC_CR0_MOD60ALMEN 4 /* Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ +#define BITP_RTC_CR0_TRMEN 3 /* Enable RTC Digital Trimming */ +#define BITP_RTC_CR0_ALMINTEN 2 /* Enable ALMINT Sourced Alarm Interrupts to the CPU */ +#define BITP_RTC_CR0_ALMEN 1 /* Enable the RTC Alarm (Absolute) Operation */ +#define BITP_RTC_CR0_CNTEN 0 /* Global Enable for the RTC */ +#define BITM_RTC_CR0_WPNDINTEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Write Pending Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_WSYNCINTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Write Synchronization Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_WPNDERRINTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ +#define BITM_RTC_CR0_ISOINTEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ +#define BITM_RTC_CR0_MOD60ALMINTEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_MOD60ALM (_ADI_MSK_3(0x000007E0,0x000007E0U, uint16_t )) /* Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ +#define BITM_RTC_CR0_MOD60ALMEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ +#define BITM_RTC_CR0_TRMEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable RTC Digital Trimming */ +#define BITM_RTC_CR0_ALMINTEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable ALMINT Sourced Alarm Interrupts to the CPU */ +#define BITM_RTC_CR0_ALMEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable the RTC Alarm (Absolute) Operation */ +#define BITM_RTC_CR0_CNTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Global Enable for the RTC */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR0_ISOENB 14 /* Visibility of 32kHz Sourced Registers */ +#define BITP_RTC_SR0_WSYNCTRM 13 /* Synchronisation Status of Posted Writes to TRM */ +#define BITP_RTC_SR0_WSYNCALM1 12 /* Synchronisation Status of Posted Writes to ALM1 */ +#define BITP_RTC_SR0_WSYNCALM0 11 /* Synchronisation Status of Posted Writes to ALM0 */ +#define BITP_RTC_SR0_WSYNCCNT1 10 /* Synchronisation Status of Posted Writes to CNT1 */ +#define BITP_RTC_SR0_WSYNCCNT0 9 /* Synchronisation Status of Posted Writes to CNT0 */ +#define BITP_RTC_SR0_WSYNCSR0 8 /* Synchronisation Status of Posted Writes to SR0 */ +#define BITP_RTC_SR0_WSYNCCR0 7 /* Synchronisation Status of Posted Writes to CR0 */ +#define BITP_RTC_SR0_WPNDINT 6 /* Write Pending Interrupt */ +#define BITP_RTC_SR0_WSYNCINT 5 /* Write Synchronisation Interrupt */ +#define BITP_RTC_SR0_WPNDERRINT 4 /* Write Pending Error Interrupt Source */ +#define BITP_RTC_SR0_ISOINT 3 /* RTC Power-Domain Isolation Interrupt Source */ +#define BITP_RTC_SR0_MOD60ALMINT 2 /* Modulo-60 RTC Alarm Interrupt Source */ +#define BITP_RTC_SR0_ALMINT 1 /* Alarm Interrupt Source */ +#define BITM_RTC_SR0_ISOENB (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Visibility of 32kHz Sourced Registers */ +#define BITM_RTC_SR0_WSYNCTRM (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronisation Status of Posted Writes to TRM */ +#define BITM_RTC_SR0_WSYNCALM1 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronisation Status of Posted Writes to ALM1 */ +#define BITM_RTC_SR0_WSYNCALM0 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Synchronisation Status of Posted Writes to ALM0 */ +#define BITM_RTC_SR0_WSYNCCNT1 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronisation Status of Posted Writes to CNT1 */ +#define BITM_RTC_SR0_WSYNCCNT0 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronisation Status of Posted Writes to CNT0 */ +#define BITM_RTC_SR0_WSYNCSR0 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronisation Status of Posted Writes to SR0 */ +#define BITM_RTC_SR0_WSYNCCR0 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Synchronisation Status of Posted Writes to CR0 */ +#define BITM_RTC_SR0_WPNDINT (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Write Pending Interrupt */ +#define BITM_RTC_SR0_WSYNCINT (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Write Synchronisation Interrupt */ +#define BITM_RTC_SR0_WPNDERRINT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Write Pending Error Interrupt Source */ +#define BITM_RTC_SR0_ISOINT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* RTC Power-Domain Isolation Interrupt Source */ +#define BITM_RTC_SR0_MOD60ALMINT (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Modulo-60 RTC Alarm Interrupt Source */ +#define BITM_RTC_SR0_ALMINT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Alarm Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR1_WPNDTRM 13 /* Pending Status of Posted Writes to TRM */ +#define BITP_RTC_SR1_WPNDALM1 12 /* Pending Status of Posted Writes to ALM1 */ +#define BITP_RTC_SR1_WPNDALM0 11 /* Pending Status of Posted Writes to ALM0 */ +#define BITP_RTC_SR1_WPNDCNT1 10 /* Pending Status of Posted Writes to CNT1 */ +#define BITP_RTC_SR1_WPNDCNT0 9 /* Pending Status of Posted Writes to CNT0 */ +#define BITP_RTC_SR1_WPNDSR0 8 /* Pending Status of Posted Clearances of Interrupt Sources in SR0 */ +#define BITP_RTC_SR1_WPNDCR0 7 /* Pending Status of Posted Writes to CR0 */ +#define BITM_RTC_SR1_WPNDTRM (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to TRM */ +#define BITM_RTC_SR1_WPNDALM1 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to ALM1 */ +#define BITM_RTC_SR1_WPNDALM0 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Pending Status of Posted Writes to ALM0 */ +#define BITM_RTC_SR1_WPNDCNT1 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Writes to CNT1 */ +#define BITM_RTC_SR1_WPNDCNT0 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to CNT0 */ +#define BITM_RTC_SR1_WPNDSR0 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Clearances of Interrupt Sources in SR0 */ +#define BITM_RTC_SR1_WPNDCR0 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Pending Status of Posted Writes to CR0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT0_VALUE 0 /* Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT1_VALUE 0 /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM0_VALUE 0 /* Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ +#define BITM_RTC_ALM0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM1_VALUE 0 /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ +#define BITM_RTC_ALM1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_TRM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_TRM_IVL2EXPMIN 6 /* Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ +#define BITP_RTC_TRM_IVL 4 /* Trim Interval in Prescaled RTC Time Units */ +#define BITP_RTC_TRM_ADD 3 /* Trim Polarity */ +#define BITP_RTC_TRM_VALUE 0 /* Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ +#define BITM_RTC_TRM_IVL2EXPMIN (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t )) /* Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ +#define BITM_RTC_TRM_IVL (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* Trim Interval in Prescaled RTC Time Units */ +#define BITM_RTC_TRM_ADD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Trim Polarity */ +#define BITM_RTC_TRM_VALUE (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GWY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GWY_SWKEY 0 /* Software-keyed Command Issued by the CPU */ +#define BITM_RTC_GWY_SWKEY (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Software-keyed Command Issued by the CPU */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR1_PRESCALE2EXP 5 /* Prescale Power of 2 Division Factor for the RTC Base Clock */ +#define BITP_RTC_CR1_CNTMOD60ROLLINTEN 4 /* Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ +#define BITP_RTC_CR1_CNTROLLINTEN 3 /* Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ +#define BITP_RTC_CR1_TRMINTEN 2 /* Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ +#define BITP_RTC_CR1_PSINTEN 1 /* Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ +#define BITP_RTC_CR1_CNTINTEN 0 /* Enable for the RTC Count Interrupt Source */ +#define BITM_RTC_CR1_PRESCALE2EXP (_ADI_MSK_3(0x000001E0,0x000001E0U, uint16_t )) /* Prescale Power of 2 Division Factor for the RTC Base Clock */ +#define BITM_RTC_CR1_CNTMOD60ROLLINTEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ +#define BITM_RTC_CR1_CNTROLLINTEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ +#define BITM_RTC_CR1_TRMINTEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ +#define BITM_RTC_CR1_PSINTEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ +#define BITM_RTC_CR1_CNTINTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable for the RTC Count Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR2_WSYNCALM2MIR 15 /* Synchronization Status of Posted Writes to ALM2 */ +#define BITP_RTC_SR2_WSYNCCR1MIR 14 /* Synchronization Status of Posted Writes to CR1 */ +#define BITP_RTC_SR2_WPNDALM2MIR 13 /* Pending Status of Posted Writes to ALM2 */ +#define BITP_RTC_SR2_WPNDCR1MIR 12 /* Pending Status of Posted Writes to CR1 */ +#define BITP_RTC_SR2_TRMBDYMIR 7 /* Mirror of MOD:RTCTRMBDY */ +#define BITP_RTC_SR2_CNTMOD60ROLL 6 /* RTC Count Modulo-60 Roll-Over */ +#define BITP_RTC_SR2_CNTROLL 5 /* RTC Count Roll-Over */ +#define BITP_RTC_SR2_CNTMOD60ROLLINT 4 /* RTC Modulo-60 Count Roll-Over Interrupt Source */ +#define BITP_RTC_SR2_CNTROLLINT 3 /* RTC Count Roll-Over Interrupt Source */ +#define BITP_RTC_SR2_TRMINT 2 /* RTC Trim Interrupt Source */ +#define BITP_RTC_SR2_PSINT 1 /* RTC Prescaled, Modulo-1 Boundary Interrupt Source */ +#define BITP_RTC_SR2_CNTINT 0 /* RTC Count Interrupt Source */ +#define BITM_RTC_SR2_WSYNCALM2MIR (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Status of Posted Writes to ALM2 */ +#define BITM_RTC_SR2_WSYNCCR1MIR (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Synchronization Status of Posted Writes to CR1 */ +#define BITM_RTC_SR2_WPNDALM2MIR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to ALM2 */ +#define BITM_RTC_SR2_WPNDCR1MIR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to CR1 */ +#define BITM_RTC_SR2_TRMBDYMIR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Mirror of MOD:RTCTRMBDY */ +#define BITM_RTC_SR2_CNTMOD60ROLL (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* RTC Count Modulo-60 Roll-Over */ +#define BITM_RTC_SR2_CNTROLL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* RTC Count Roll-Over */ +#define BITM_RTC_SR2_CNTMOD60ROLLINT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* RTC Modulo-60 Count Roll-Over Interrupt Source */ +#define BITM_RTC_SR2_CNTROLLINT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* RTC Count Roll-Over Interrupt Source */ +#define BITM_RTC_SR2_TRMINT (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* RTC Trim Interrupt Source */ +#define BITM_RTC_SR2_PSINT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* RTC Prescaled, Modulo-1 Boundary Interrupt Source */ +#define BITM_RTC_SR2_CNTINT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* RTC Count Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP0_VALUE 0 /* Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ +#define BITM_RTC_SNAP0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP1_VALUE 0 /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ +#define BITM_RTC_SNAP1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP2_VALUE 0 /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ +#define BITM_RTC_SNAP2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_MOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_MOD_CNT0_4TOZERO 11 /* Mirror of CNT0[4:0] */ +#define BITP_RTC_MOD_TRMBDY 10 /* Trim Boundary Indicator */ +#define BITP_RTC_MOD_INCR 6 /* Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ +#define BITP_RTC_MOD_CNTMOD60 0 /* Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ +#define BITM_RTC_MOD_CNT0_4TOZERO (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t )) /* Mirror of CNT0[4:0] */ +#define BITM_RTC_MOD_TRMBDY (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Trim Boundary Indicator */ +#define BITM_RTC_MOD_INCR (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t )) /* Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ +#define BITM_RTC_MOD_CNTMOD60 (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT2_VALUE 0 /* Fractional Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Fractional Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM2_VALUE 0 /* Fractional Bits of the Alarm Target Time */ +#define BITM_RTC_ALM2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Fractional Bits of the Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR3_SS1IRQ 9 /* Sticky Interrupt Source for SensorStrobe Channel 1 */ +#define BITP_RTC_SR3_ALMINTMIR 8 /* Read-only Mirror of the ALMINT Interrupt Source in SR0 Register */ +#define BITP_RTC_SR3_IC4IRQ 4 /* Sticky Interrupt Source for the RTC Input Capture Channel 4 */ +#define BITP_RTC_SR3_IC3IRQ 3 /* Sticky Interrupt Source for the RTC Input Capture Channel 3 */ +#define BITP_RTC_SR3_IC2IRQ 2 /* Sticky Interrupt Source for the RTC Input Capture Channel 2 */ +#define BITP_RTC_SR3_IC0IRQ 0 /* Sticky Interrupt Source for the RTC Input Capture Channel 0 */ +#define BITM_RTC_SR3_SS1IRQ (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Sticky Interrupt Source for SensorStrobe Channel 1 */ +#define BITM_RTC_SR3_ALMINTMIR (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Read-only Mirror of the ALMINT Interrupt Source in SR0 Register */ +#define BITM_RTC_SR3_IC4IRQ (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 4 */ +#define BITM_RTC_SR3_IC3IRQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 3 */ +#define BITM_RTC_SR3_IC2IRQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 2 */ +#define BITM_RTC_SR3_IC0IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR2IC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR2IC_ICOWUSEN 15 /* Enable Overwrite of Unread Snapshots for All Input Capture Channels */ +#define BITP_RTC_CR2IC_IC4IRQEN 14 /* Interrupt Enable for the RTC Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3IRQEN 13 /* Interrupt Enable for the RTC Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2IRQEN 12 /* Interrupt Enable for the RTC Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0IRQEN 10 /* Interrupt Enable for the RTC Input Capture Channel 0 */ +#define BITP_RTC_CR2IC_IC4LH 9 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3LH 8 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2LH 7 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0LH 5 /* Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ +#define BITP_RTC_CR2IC_IC4EN 4 /* Enable for the RTC Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3EN 3 /* Enable for the RTC Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2EN 2 /* Enable for the RTC Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0EN 0 /* Enable for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_ICOWUSEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Overwrite of Unread Snapshots for All Input Capture Channels */ +#define BITM_RTC_CR2IC_IC4IRQEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3IRQEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2IRQEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0IRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_IC4LH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3LH (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2LH (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0LH (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_IC4EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the RTC Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3EN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the RTC Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2EN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the RTC Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable for the RTC Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR3SS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR3SS_SS1IRQEN 9 /* Interrupt Enable for SensorStrobe Channel 1 */ +#define BITP_RTC_CR3SS_SS1EN 1 /* Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS1IRQEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Interrupt Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS1EN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR4SS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR4SS_SS1ARLEN 9 /* Enable for Auto-Reloading When SensorStrobe Match Occurs */ +#define BITP_RTC_CR4SS_SS1MSKEN 1 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ +#define BITM_RTC_CR4SS_SS1ARLEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Enable for Auto-Reloading When SensorStrobe Match Occurs */ +#define BITM_RTC_CR4SS_SS1MSKEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ +#define ENUM_RTC_CR4SS_NO_MSK (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1MSKEN: Do not apply a mask to SensorStrobe Channel 1 Register */ +#define ENUM_RTC_CR4SS_THERM_MSK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SS1MSKEN: Apply thermometer decoded mask */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SSMSK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SSMSK_SSMSK 0 /* Thermometer-Encoded Masks for SensorStrobe Channels */ +#define BITM_RTC_SSMSK_SSMSK (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Thermometer-Encoded Masks for SensorStrobe Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1ARL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1ARL_SS1ARL 0 /* Auto-Reload Value When SensorStrobe Match Occurs */ +#define BITM_RTC_SS1ARL_SS1ARL (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Auto-Reload Value When SensorStrobe Match Occurs */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC2_IC2 0 /* RTC Input Capture Channel 2 */ +#define BITM_RTC_IC2_IC2 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC3_IC3 0 /* RTC Input Capture Channel 3 */ +#define BITM_RTC_IC3_IC3 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC4_IC4 0 /* RTC Input Capture Channel 4 */ +#define BITM_RTC_IC4_IC4 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1_SS1 0 /* SensorStrobe Channel 1 */ +#define BITM_RTC_SS1_SS1 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR4_RSYNCIC4 14 /* Synchronization Status of Posted Reads of RTC Input Channel 4 */ +#define BITP_RTC_SR4_RSYNCIC3 13 /* Synchronization Status of Posted Reads of RTC Input Channel 3 */ +#define BITP_RTC_SR4_RSYNCIC2 12 /* Synchronization Status of Posted Reads of RTC Input Channel 2 */ +#define BITP_RTC_SR4_RSYNCIC0 10 /* Synchronization Status of Posted Reads of RTC Input Channel 0 */ +#define BITP_RTC_SR4_WSYNCSS1 6 /* Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITP_RTC_SR4_WSYNCSS1ARL 5 /* Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */ +#define BITP_RTC_SR4_WSYNCSSMSK 4 /* Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR4SS 3 /* Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR3SS 2 /* Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR2IC 1 /* Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITP_RTC_SR4_WSYNCSR3 0 /* Synchronisation Status of Posted Writes to SR3 */ +#define BITM_RTC_SR4_RSYNCIC4 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 4 */ +#define BITM_RTC_SR4_RSYNCIC3 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 3 */ +#define BITM_RTC_SR4_RSYNCIC2 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 2 */ +#define BITM_RTC_SR4_RSYNCIC0 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 0 */ +#define BITM_RTC_SR4_WSYNCSS1 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITM_RTC_SR4_WSYNCSS1ARL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */ +#define BITM_RTC_SR4_WSYNCSSMSK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR4SS (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR3SS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR2IC (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITM_RTC_SR4_WSYNCSR3 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Synchronisation Status of Posted Writes to SR3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR5_RPENDIC4 14 /* Pending Status of Posted Reads of IC4 */ +#define BITP_RTC_SR5_RPENDIC3 13 /* Pending Status of Posted Reads of IC3 */ +#define BITP_RTC_SR5_RPENDIC2 12 /* Pending Status of Posted Reads of IC2 */ +#define BITP_RTC_SR5_RPENDIC0 10 /* Pending Status of Posted Reads of Input Capture Channel 0 */ +#define BITP_RTC_SR5_WPENDSS1 6 /* Pending Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITP_RTC_SR5_WPENDSS1ARL 5 /* Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */ +#define BITP_RTC_SR5_WPENDSSMSK 4 /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR4SS 3 /* Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR3SS 2 /* Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR2IC 1 /* Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITP_RTC_SR5_WPENDSR3 0 /* Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ +#define BITM_RTC_SR5_RPENDIC4 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Pending Status of Posted Reads of IC4 */ +#define BITM_RTC_SR5_RPENDIC3 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Reads of IC3 */ +#define BITM_RTC_SR5_RPENDIC2 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Reads of IC2 */ +#define BITM_RTC_SR5_RPENDIC0 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Reads of Input Capture Channel 0 */ +#define BITM_RTC_SR5_WPENDSS1 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITM_RTC_SR5_WPENDSS1ARL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */ +#define BITM_RTC_SR5_WPENDSSMSK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR4SS (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR3SS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR2IC (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITM_RTC_SR5_WPENDSR3 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR6_FRZCNTPTR 9 /* Pointer for the Triple-Read Sequence of FRZCNT */ +#define BITP_RTC_SR6_IC0SNAP 8 /* Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ +#define BITP_RTC_SR6_IC4UNR 4 /* Sticky Unread Status of the Input Capture Channel 4 */ +#define BITP_RTC_SR6_IC3UNR 3 /* Sticky Unread Status of the Input Capture Channel 3 */ +#define BITP_RTC_SR6_IC2UNR 2 /* Sticky Unread Status of the Input Capture Channel 2 */ +#define BITP_RTC_SR6_IC0UNR 0 /* Sticky Unread Status of the Input Capture Channel 0 */ +#define BITM_RTC_SR6_FRZCNTPTR (_ADI_MSK_3(0x00000600,0x00000600U, uint16_t )) /* Pointer for the Triple-Read Sequence of FRZCNT */ +#define BITM_RTC_SR6_IC0SNAP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ +#define BITM_RTC_SR6_IC4UNR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 4 */ +#define BITM_RTC_SR6_IC3UNR (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 3 */ +#define BITM_RTC_SR6_IC2UNR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 2 */ +#define BITM_RTC_SR6_IC0UNR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1TGT_SS1TGT 0 /* Current Target Value for the SensorStrobe Channel 1 */ +#define BITM_RTC_SS1TGT_SS1TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Target Value for the SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_FRZCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_FRZCNT_FRZCNT 0 /* RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ +#define BITM_RTC_FRZCNT_FRZCNT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ + + +/* ============================================================================================================================ + System Identification and Debug Enable + ============================================================================================================================ */ + +/* ============================================================================================================================ + SYS + ============================================================================================================================ */ +#define REG_SYS_ADIID 0x40002020 /* SYS ADI Identification */ +#define REG_SYS_CHIPID 0x40002024 /* SYS Chip Identifier */ +#define REG_SYS_SWDEN 0x40002040 /* SYS Serial Wire Debug Enable */ + +/* ============================================================================================================================ + SYS Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_ADIID_VALUE 0 /* ADI Cortex Device */ +#define BITM_SYS_ADIID_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* ADI Cortex Device */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_CHIPID_PARTID 4 /* Part Identifier */ +#define BITP_SYS_CHIPID_REV 0 /* Silicon Revision */ +#define BITM_SYS_CHIPID_PARTID (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t )) /* Part Identifier */ +#define BITM_SYS_CHIPID_REV (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Silicon Revision */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_SWDEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_SWDEN_VALUE 0 /* SWD Interface Enable */ +#define BITM_SYS_SWDEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SWD Interface Enable */ + + +/* ============================================================================================================================ + Watchdog Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + WDT0 + ============================================================================================================================ */ +#define REG_WDT0_LOAD 0x40002C00 /* WDT0 Load Value */ +#define REG_WDT0_CCNT 0x40002C04 /* WDT0 Current Count Value */ +#define REG_WDT0_CTL 0x40002C08 /* WDT0 Control */ +#define REG_WDT0_RESTART 0x40002C0C /* WDT0 Clear Interrupt */ +#define REG_WDT0_STAT 0x40002C18 /* WDT0 Status */ + +/* ============================================================================================================================ + WDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_LOAD_VALUE 0 /* Load Value */ +#define BITM_WDT_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_CCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_CCNT_VALUE 0 /* Current Count Value */ +#define BITM_WDT_CCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Count Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_CTL_SPARE 7 /* Unused Spare Bit */ +#define BITP_WDT_CTL_MODE 6 /* Timer Mode */ +#define BITP_WDT_CTL_EN 5 /* Timer Enable */ +#define BITP_WDT_CTL_PRE 2 /* Prescaler */ +#define BITP_WDT_CTL_IRQ 1 /* Timer Interrupt */ +#define BITM_WDT_CTL_SPARE (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Unused Spare Bit */ +#define BITM_WDT_CTL_MODE (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Mode */ +#define BITM_WDT_CTL_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Timer Enable */ +#define BITM_WDT_CTL_PRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Prescaler */ +#define BITM_WDT_CTL_IRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Timer Interrupt */ +#define ENUM_WDT_CTL_FREE_RUN (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MODE: Free running mode */ +#define ENUM_WDT_CTL_PERIODIC (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* MODE: Periodic mode */ +#define ENUM_WDT_CTL_WDT_DIS (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* EN: WDT not enabled */ +#define ENUM_WDT_CTL_WDT_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* EN: WDT enabled */ +#define ENUM_WDT_CTL_DIV1 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* PRE: Source clock/1 */ +#define ENUM_WDT_CTL_DIV16 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* PRE: Source clock/16 */ +#define ENUM_WDT_CTL_DIV256 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* PRE: Source clock/256 (default) */ +#define ENUM_WDT_CTL_RST (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: WDT asserts reset when timed out */ +#define ENUM_WDT_CTL_INT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IRQ: WDT generates interrupt when timed out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_RESTART Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_RESTART_CLRWORD 0 /* Clear Watchdog */ +#define BITM_WDT_RESTART_CLRWORD (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Clear Watchdog */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_STAT_RSTCTL 5 /* Reset Control Register Written and Locked */ +#define BITP_WDT_STAT_LOCKED 4 /* Lock Status Bit */ +#define BITP_WDT_STAT_COUNTING 3 /* Control Register Write Sync in Progress */ +#define BITP_WDT_STAT_LOADING 2 /* Load Register Write Sync in Progress */ +#define BITP_WDT_STAT_CLRIRQ 1 /* Clear Interrupt Register Write Sync in Progress */ +#define BITP_WDT_STAT_IRQ 0 /* WDT Interrupt */ +#define BITM_WDT_STAT_RSTCTL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Reset Control Register Written and Locked */ +#define BITM_WDT_STAT_LOCKED (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Lock Status Bit */ +#define BITM_WDT_STAT_COUNTING (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Control Register Write Sync in Progress */ +#define BITM_WDT_STAT_LOADING (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Load Register Write Sync in Progress */ +#define BITM_WDT_STAT_CLRIRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Interrupt Register Write Sync in Progress */ +#define BITM_WDT_STAT_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* WDT Interrupt */ + + +/* ============================================================================================================================ + I2C Master/Slave + ============================================================================================================================ */ + +/* ============================================================================================================================ + I2C0 + ============================================================================================================================ */ +#define REG_I2C0_MCTL 0x40003000 /* I2C0 Master Control */ +#define REG_I2C0_MSTAT 0x40003004 /* I2C0 Master Status */ +#define REG_I2C0_MRX 0x40003008 /* I2C0 Master Receive Data */ +#define REG_I2C0_MTX 0x4000300C /* I2C0 Master Transmit Data */ +#define REG_I2C0_MRXCNT 0x40003010 /* I2C0 Master Receive Data Count */ +#define REG_I2C0_MCRXCNT 0x40003014 /* I2C0 Master Current Receive Data Count */ +#define REG_I2C0_ADDR1 0x40003018 /* I2C0 Master Address Byte 1 */ +#define REG_I2C0_ADDR2 0x4000301C /* I2C0 Master Address Byte 2 */ +#define REG_I2C0_BYT 0x40003020 /* I2C0 Start Byte */ +#define REG_I2C0_DIV 0x40003024 /* I2C0 Serial Clock Period Divisor */ +#define REG_I2C0_SCTL 0x40003028 /* I2C0 Slave Control */ +#define REG_I2C0_SSTAT 0x4000302C /* I2C0 Slave I2C Status/Error/IRQ */ +#define REG_I2C0_SRX 0x40003030 /* I2C0 Slave Receive */ +#define REG_I2C0_STX 0x40003034 /* I2C0 Slave Transmit */ +#define REG_I2C0_ALT 0x40003038 /* I2C0 Hardware General Call ID */ +#define REG_I2C0_ID0 0x4000303C /* I2C0 First Slave Address Device ID */ +#define REG_I2C0_ID1 0x40003040 /* I2C0 Second Slave Address Device ID */ +#define REG_I2C0_ID2 0x40003044 /* I2C0 Third Slave Address Device ID */ +#define REG_I2C0_ID3 0x40003048 /* I2C0 Fourth Slave Address Device ID */ +#define REG_I2C0_STAT 0x4000304C /* I2C0 Master and Slave FIFO Status */ +#define REG_I2C0_SHCTL 0x40003050 /* I2C0 Shared Control */ +#define REG_I2C0_TCTL 0x40003054 /* I2C0 Timing Control Register */ +#define REG_I2C0_ASTRETCH_SCL 0x40003058 /* I2C0 Automatic Stretch SCL */ + +/* ============================================================================================================================ + I2C Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MCTL_STOPBUSCLR 13 /* Prestop Bus Clear */ +#define BITP_I2C_MCTL_BUSCLR 12 /* Bus-Clear Enable */ +#define BITP_I2C_MCTL_MTXDMA 11 /* Enable Master Tx DMA Request */ +#define BITP_I2C_MCTL_MRXDMA 10 /* Enable Master Rx DMA Request */ +#define BITP_I2C_MCTL_MXMITDEC 9 /* Decrement Master Tx FIFO Status When a Byte Txed */ +#define BITP_I2C_MCTL_IENCMP 8 /* Transaction Completed (or Stop Detected) Interrupt Enable */ +#define BITP_I2C_MCTL_IENACK 7 /* ACK Not Received Interrupt Enable */ +#define BITP_I2C_MCTL_IENALOST 6 /* Arbitration Lost Interrupt Enable */ +#define BITP_I2C_MCTL_IENMTX 5 /* Transmit Request Interrupt Enable */ +#define BITP_I2C_MCTL_IENMRX 4 /* Receive Request Interrupt Enable */ +#define BITP_I2C_MCTL_STRETCHSCL 3 /* Stretch SCL Enable */ +#define BITP_I2C_MCTL_LOOPBACK 2 /* Internal Loopback Enable */ +#define BITP_I2C_MCTL_COMPLETE 1 /* Start Back-off Disable */ +#define BITP_I2C_MCTL_MASEN 0 /* Master Enable */ +#define BITM_I2C_MCTL_STOPBUSCLR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Prestop Bus Clear */ +#define BITM_I2C_MCTL_BUSCLR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Bus-Clear Enable */ +#define BITM_I2C_MCTL_MTXDMA (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Master Tx DMA Request */ +#define BITM_I2C_MCTL_MRXDMA (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Enable Master Rx DMA Request */ +#define BITM_I2C_MCTL_MXMITDEC (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Decrement Master Tx FIFO Status When a Byte Txed */ +#define BITM_I2C_MCTL_IENCMP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Transaction Completed (or Stop Detected) Interrupt Enable */ +#define BITM_I2C_MCTL_IENACK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* ACK Not Received Interrupt Enable */ +#define BITM_I2C_MCTL_IENALOST (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Arbitration Lost Interrupt Enable */ +#define BITM_I2C_MCTL_IENMTX (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Transmit Request Interrupt Enable */ +#define BITM_I2C_MCTL_IENMRX (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Receive Request Interrupt Enable */ +#define BITM_I2C_MCTL_STRETCHSCL (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Stretch SCL Enable */ +#define BITM_I2C_MCTL_LOOPBACK (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Internal Loopback Enable */ +#define BITM_I2C_MCTL_COMPLETE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Start Back-off Disable */ +#define BITM_I2C_MCTL_MASEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Master Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MSTAT_SCLFILT 14 /* State of SCL Line */ +#define BITP_I2C_MSTAT_SDAFILT 13 /* State of SDA Line */ +#define BITP_I2C_MSTAT_MTXUNDR 12 /* Master Transmit Underflow */ +#define BITP_I2C_MSTAT_MSTOP 11 /* STOP Driven by This I2C Master */ +#define BITP_I2C_MSTAT_LINEBUSY 10 /* Line is Busy */ +#define BITP_I2C_MSTAT_MRXOVR 9 /* Master Receive FIFO Overflow */ +#define BITP_I2C_MSTAT_TCOMP 8 /* Transaction Complete or Stop Detected */ +#define BITP_I2C_MSTAT_NACKDATA 7 /* ACK Not Received in Response to Data Write */ +#define BITP_I2C_MSTAT_MBUSY 6 /* Master Busy */ +#define BITP_I2C_MSTAT_ALOST 5 /* Arbitration Lost */ +#define BITP_I2C_MSTAT_NACKADDR 4 /* ACK Not Received in Response to an Address */ +#define BITP_I2C_MSTAT_MRXREQ 3 /* Master Receive Request */ +#define BITP_I2C_MSTAT_MTXREQ 2 /* Master Transmit Request/Clear Master Transmit Interrupt */ +#define BITP_I2C_MSTAT_MTXF 0 /* Master Transmit FIFO Status */ +#define BITM_I2C_MSTAT_SCLFILT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* State of SCL Line */ +#define BITM_I2C_MSTAT_SDAFILT (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* State of SDA Line */ +#define BITM_I2C_MSTAT_MTXUNDR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Master Transmit Underflow */ +#define BITM_I2C_MSTAT_MSTOP (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* STOP Driven by This I2C Master */ +#define BITM_I2C_MSTAT_LINEBUSY (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Line is Busy */ +#define BITM_I2C_MSTAT_MRXOVR (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Master Receive FIFO Overflow */ +#define BITM_I2C_MSTAT_TCOMP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Transaction Complete or Stop Detected */ +#define BITM_I2C_MSTAT_NACKDATA (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* ACK Not Received in Response to Data Write */ +#define BITM_I2C_MSTAT_MBUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Master Busy */ +#define BITM_I2C_MSTAT_ALOST (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Arbitration Lost */ +#define BITM_I2C_MSTAT_NACKADDR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* ACK Not Received in Response to an Address */ +#define BITM_I2C_MSTAT_MRXREQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Master Receive Request */ +#define BITM_I2C_MSTAT_MTXREQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Master Transmit Request/Clear Master Transmit Interrupt */ +#define BITM_I2C_MSTAT_MTXF (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Master Transmit FIFO Status */ +#define ENUM_I2C_MSTAT_FIFO_EMPTY (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MTXF: FIFO Empty. */ +#define ENUM_I2C_MSTAT_FIFO_1BYTE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* MTXF: 1 byte in FIFO. */ +#define ENUM_I2C_MSTAT_FIFO_FULL (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* MTXF: FIFO Full. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MRX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MRX_VALUE 0 /* Master Receive Register */ +#define BITM_I2C_MRX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Master Receive Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MTX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MTX_VALUE 0 /* Master Transmit Register */ +#define BITM_I2C_MTX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Master Transmit Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MRXCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MRXCNT_EXTEND 8 /* Extended Read */ +#define BITP_I2C_MRXCNT_VALUE 0 /* Receive Count */ +#define BITM_I2C_MRXCNT_EXTEND (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Extended Read */ +#define BITM_I2C_MRXCNT_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Receive Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MCRXCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MCRXCNT_VALUE 0 /* Current Receive Count */ +#define BITM_I2C_MCRXCNT_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Current Receive Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ADDR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ADDR1_VALUE 0 /* Address Byte 1 */ +#define BITM_I2C_ADDR1_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Address Byte 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ADDR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ADDR2_VALUE 0 /* Address Byte 2 */ +#define BITM_I2C_ADDR2_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Address Byte 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_BYT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_BYT_SBYTE 0 /* Start Byte */ +#define BITM_I2C_BYT_SBYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Start Byte */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_DIV_HIGH 8 /* Serial Clock High Time */ +#define BITP_I2C_DIV_LOW 0 /* Serial Clock Low Time */ +#define BITM_I2C_DIV_HIGH (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* Serial Clock High Time */ +#define BITM_I2C_DIV_LOW (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Serial Clock Low Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SCTL_STXDMA 14 /* Enable Slave Tx DMA Request */ +#define BITP_I2C_SCTL_SRXDMA 13 /* Enable Slave Rx DMA Request */ +#define BITP_I2C_SCTL_IENREPST 12 /* Repeated Start Interrupt Enable */ +#define BITP_I2C_SCTL_STXDEC 11 /* Decrement Slave Tx FIFO Status When a Byte is Txed */ +#define BITP_I2C_SCTL_IENSTX 10 /* Slave Transmit Request Interrupt Enable */ +#define BITP_I2C_SCTL_IENSRX 9 /* Slave Receive Request Interrupt Enable */ +#define BITP_I2C_SCTL_IENSTOP 8 /* Stop Condition Detected Interrupt Enable */ +#define BITP_I2C_SCTL_NACK 7 /* NACK Next Communication */ +#define BITP_I2C_SCTL_EARLYTXR 5 /* Early Transmit Request Mode */ +#define BITP_I2C_SCTL_GCSBCLR 4 /* General Call Status Bit Clear */ +#define BITP_I2C_SCTL_HGCEN 3 /* Hardware General Call Enable */ +#define BITP_I2C_SCTL_GCEN 2 /* General Call Enable */ +#define BITP_I2C_SCTL_ADR10EN 1 /* Enabled 10-bit Addressing */ +#define BITP_I2C_SCTL_SLVEN 0 /* Slave Enable */ +#define BITM_I2C_SCTL_STXDMA (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Slave Tx DMA Request */ +#define BITM_I2C_SCTL_SRXDMA (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Enable Slave Rx DMA Request */ +#define BITM_I2C_SCTL_IENREPST (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Repeated Start Interrupt Enable */ +#define BITM_I2C_SCTL_STXDEC (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Decrement Slave Tx FIFO Status When a Byte is Txed */ +#define BITM_I2C_SCTL_IENSTX (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Slave Transmit Request Interrupt Enable */ +#define BITM_I2C_SCTL_IENSRX (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave Receive Request Interrupt Enable */ +#define BITM_I2C_SCTL_IENSTOP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Stop Condition Detected Interrupt Enable */ +#define BITM_I2C_SCTL_NACK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* NACK Next Communication */ +#define BITM_I2C_SCTL_EARLYTXR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Early Transmit Request Mode */ +#define BITM_I2C_SCTL_GCSBCLR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* General Call Status Bit Clear */ +#define BITM_I2C_SCTL_HGCEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Hardware General Call Enable */ +#define BITM_I2C_SCTL_GCEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* General Call Enable */ +#define BITM_I2C_SCTL_ADR10EN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enabled 10-bit Addressing */ +#define BITM_I2C_SCTL_SLVEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Slave Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SSTAT_START 14 /* Start and Matching Address */ +#define BITP_I2C_SSTAT_REPSTART 13 /* Repeated Start and Matching Address */ +#define BITP_I2C_SSTAT_IDMAT 11 /* Device ID Matched */ +#define BITP_I2C_SSTAT_STOP 10 /* Stop After Start and Matching Address */ +#define BITP_I2C_SSTAT_GCID 8 /* General ID */ +#define BITP_I2C_SSTAT_GCINT 7 /* General Call Interrupt */ +#define BITP_I2C_SSTAT_SBUSY 6 /* Slave Busy */ +#define BITP_I2C_SSTAT_NOACK 5 /* ACK Not Generated by the Slave */ +#define BITP_I2C_SSTAT_SRXOVR 4 /* Slave Receive FIFO Overflow */ +#define BITP_I2C_SSTAT_SRXREQ 3 /* Slave Receive Request */ +#define BITP_I2C_SSTAT_STXREQ 2 /* Slave Transmit Request/Slave Transmit Interrupt */ +#define BITP_I2C_SSTAT_STXUNDR 1 /* Slave Transmit FIFO Underflow */ +#define BITP_I2C_SSTAT_STXFSEREQ 0 /* Slave Tx FIFO Status or Early Request */ +#define BITM_I2C_SSTAT_START (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Start and Matching Address */ +#define BITM_I2C_SSTAT_REPSTART (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Repeated Start and Matching Address */ +#define BITM_I2C_SSTAT_IDMAT (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t )) /* Device ID Matched */ +#define BITM_I2C_SSTAT_STOP (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Stop After Start and Matching Address */ +#define BITM_I2C_SSTAT_GCID (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* General ID */ +#define BITM_I2C_SSTAT_GCINT (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* General Call Interrupt */ +#define BITM_I2C_SSTAT_SBUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Slave Busy */ +#define BITM_I2C_SSTAT_NOACK (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* ACK Not Generated by the Slave */ +#define BITM_I2C_SSTAT_SRXOVR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Slave Receive FIFO Overflow */ +#define BITM_I2C_SSTAT_SRXREQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Slave Receive Request */ +#define BITM_I2C_SSTAT_STXREQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Slave Transmit Request/Slave Transmit Interrupt */ +#define BITM_I2C_SSTAT_STXUNDR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Slave Transmit FIFO Underflow */ +#define BITM_I2C_SSTAT_STXFSEREQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Slave Tx FIFO Status or Early Request */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SRX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SRX_VALUE 0 /* Slave Receive Register */ +#define BITM_I2C_SRX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Receive Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_STX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_STX_VALUE 0 /* Slave Transmit Register */ +#define BITM_I2C_STX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Transmit Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ALT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ALT_ID 0 /* Slave Alt */ +#define BITM_I2C_ALT_ID (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Alt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID0_VALUE 0 /* Slave Device ID 0 */ +#define BITM_I2C_ID0_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID1_VALUE 0 /* Slave Device ID 1 */ +#define BITM_I2C_ID1_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID2_VALUE 0 /* Slave Device ID 2 */ +#define BITM_I2C_ID2_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID3_VALUE 0 /* Slave Device ID 3 */ +#define BITM_I2C_ID3_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_STAT_MFLUSH 9 /* Flush the Master Transmit FIFO */ +#define BITP_I2C_STAT_SFLUSH 8 /* Flush the Slave Transmit FIFO */ +#define BITP_I2C_STAT_MRXF 6 /* Master Receive FIFO Status */ +#define BITP_I2C_STAT_MTXF 4 /* Master Transmit FIFO Status */ +#define BITP_I2C_STAT_SRXF 2 /* Slave Receive FIFO Status */ +#define BITP_I2C_STAT_STXF 0 /* Slave Transmit FIFO Status */ +#define BITM_I2C_STAT_MFLUSH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Flush the Master Transmit FIFO */ +#define BITM_I2C_STAT_SFLUSH (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Flush the Slave Transmit FIFO */ +#define BITM_I2C_STAT_MRXF (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* Master Receive FIFO Status */ +#define BITM_I2C_STAT_MTXF (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* Master Transmit FIFO Status */ +#define BITM_I2C_STAT_SRXF (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Slave Receive FIFO Status */ +#define BITM_I2C_STAT_STXF (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Slave Transmit FIFO Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SHCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SHCTL_RST 0 /* Reset START STOP Detect Circuit */ +#define BITM_I2C_SHCTL_RST (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Reset START STOP Detect Circuit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_TCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_TCTL_FILTEROFF 8 /* Input Filter Control */ +#define BITP_I2C_TCTL_THDATIN 0 /* Data in Hold Start */ +#define BITM_I2C_TCTL_FILTEROFF (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Input Filter Control */ +#define BITM_I2C_TCTL_THDATIN (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Data in Hold Start */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ASTRETCH_SCL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ASTRETCH_SCL_SLVTMO 9 /* Slave Automatic Stretch Timeout */ +#define BITP_I2C_ASTRETCH_SCL_MSTTMO 8 /* Master Automatic Stretch Timeout */ +#define BITP_I2C_ASTRETCH_SCL_SLV 4 /* Slave Automatic Stretch Mode */ +#define BITP_I2C_ASTRETCH_SCL_MST 0 /* Master Automatic Stretch Mode */ +#define BITM_I2C_ASTRETCH_SCL_SLVTMO (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave Automatic Stretch Timeout */ +#define BITM_I2C_ASTRETCH_SCL_MSTTMO (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Master Automatic Stretch Timeout */ +#define BITM_I2C_ASTRETCH_SCL_SLV (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* Slave Automatic Stretch Mode */ +#define BITM_I2C_ASTRETCH_SCL_MST (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Master Automatic Stretch Mode */ + + +/* ============================================================================================================================ + Serial Peripheral Interface + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPI0 + ============================================================================================================================ */ +#define REG_SPI0_STAT 0x40004000 /* SPI0 Status */ +#define REG_SPI0_RX 0x40004004 /* SPI0 Receive */ +#define REG_SPI0_TX 0x40004008 /* SPI0 Transmit */ +#define REG_SPI0_DIV 0x4000400C /* SPI0 SPI Baud Rate Selection */ +#define REG_SPI0_CTL 0x40004010 /* SPI0 SPI Configuration */ +#define REG_SPI0_IEN 0x40004014 /* SPI0 SPI Interrupts Enable */ +#define REG_SPI0_CNT 0x40004018 /* SPI0 Transfer Byte Count */ +#define REG_SPI0_DMA 0x4000401C /* SPI0 SPI DMA Enable */ +#define REG_SPI0_FIFO_STAT 0x40004020 /* SPI0 FIFO Status */ +#define REG_SPI0_RD_CTL 0x40004024 /* SPI0 Read Control */ +#define REG_SPI0_FLOW_CTL 0x40004028 /* SPI0 Flow Control */ +#define REG_SPI0_WAIT_TMR 0x4000402C /* SPI0 Wait Timer for Flow Control */ +#define REG_SPI0_CS_CTL 0x40004030 /* SPI0 Chip Select Control for Multi-slave Connections */ +#define REG_SPI0_CS_OVERRIDE 0x40004034 /* SPI0 Chip Select Override */ + +/* ============================================================================================================================ + SPI1 + ============================================================================================================================ */ +#define REG_SPI1_STAT 0x40004400 /* SPI1 Status */ +#define REG_SPI1_RX 0x40004404 /* SPI1 Receive */ +#define REG_SPI1_TX 0x40004408 /* SPI1 Transmit */ +#define REG_SPI1_DIV 0x4000440C /* SPI1 SPI Baud Rate Selection */ +#define REG_SPI1_CTL 0x40004410 /* SPI1 SPI Configuration */ +#define REG_SPI1_IEN 0x40004414 /* SPI1 SPI Interrupts Enable */ +#define REG_SPI1_CNT 0x40004418 /* SPI1 Transfer Byte Count */ +#define REG_SPI1_DMA 0x4000441C /* SPI1 SPI DMA Enable */ +#define REG_SPI1_FIFO_STAT 0x40004420 /* SPI1 FIFO Status */ +#define REG_SPI1_RD_CTL 0x40004424 /* SPI1 Read Control */ +#define REG_SPI1_FLOW_CTL 0x40004428 /* SPI1 Flow Control */ +#define REG_SPI1_WAIT_TMR 0x4000442C /* SPI1 Wait Timer for Flow Control */ +#define REG_SPI1_CS_CTL 0x40004430 /* SPI1 Chip Select Control for Multi-slave Connections */ +#define REG_SPI1_CS_OVERRIDE 0x40004434 /* SPI1 Chip Select Override */ + +/* ============================================================================================================================ + SPI2 + ============================================================================================================================ */ +#define REG_SPI2_STAT 0x40024000 /* SPI2 Status */ +#define REG_SPI2_RX 0x40024004 /* SPI2 Receive */ +#define REG_SPI2_TX 0x40024008 /* SPI2 Transmit */ +#define REG_SPI2_DIV 0x4002400C /* SPI2 SPI Baud Rate Selection */ +#define REG_SPI2_CTL 0x40024010 /* SPI2 SPI Configuration */ +#define REG_SPI2_IEN 0x40024014 /* SPI2 SPI Interrupts Enable */ +#define REG_SPI2_CNT 0x40024018 /* SPI2 Transfer Byte Count */ +#define REG_SPI2_DMA 0x4002401C /* SPI2 SPI DMA Enable */ +#define REG_SPI2_FIFO_STAT 0x40024020 /* SPI2 FIFO Status */ +#define REG_SPI2_RD_CTL 0x40024024 /* SPI2 Read Control */ +#define REG_SPI2_FLOW_CTL 0x40024028 /* SPI2 Flow Control */ +#define REG_SPI2_WAIT_TMR 0x4002402C /* SPI2 Wait Timer for Flow Control */ +#define REG_SPI2_CS_CTL 0x40024030 /* SPI2 Chip Select Control for Multi-slave Connections */ +#define REG_SPI2_CS_OVERRIDE 0x40024034 /* SPI2 Chip Select Override */ + +/* ============================================================================================================================ + SPI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_STAT_RDY 15 /* Detected an Edge on Ready Indicator for Flow Control */ +#define BITP_SPI_STAT_CSFALL 14 /* Detected a Falling Edge on CS, in Slave CON Mode */ +#define BITP_SPI_STAT_CSRISE 13 /* Detected a Rising Edge on CS, in Slave CON Mode */ +#define BITP_SPI_STAT_CSERR 12 /* Detected a CS Error Condition in Slave Mode */ +#define BITP_SPI_STAT_CS 11 /* CS Status */ +#define BITP_SPI_STAT_RXOVR 7 /* SPI Rx FIFO Overflow */ +#define BITP_SPI_STAT_RXIRQ 6 /* SPI Rx IRQ */ +#define BITP_SPI_STAT_TXIRQ 5 /* SPI Tx IRQ */ +#define BITP_SPI_STAT_TXUNDR 4 /* SPI Tx FIFO Underflow */ +#define BITP_SPI_STAT_TXDONE 3 /* SPI Tx Done in Read Command Mode */ +#define BITP_SPI_STAT_TXEMPTY 2 /* SPI Tx FIFO Empty Interrupt */ +#define BITP_SPI_STAT_XFRDONE 1 /* SPI Transfer Completion */ +#define BITP_SPI_STAT_IRQ 0 /* SPI Interrupt Status */ +#define BITM_SPI_STAT_RDY (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Detected an Edge on Ready Indicator for Flow Control */ +#define BITM_SPI_STAT_CSFALL (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Detected a Falling Edge on CS, in Slave CON Mode */ +#define BITM_SPI_STAT_CSRISE (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Detected a Rising Edge on CS, in Slave CON Mode */ +#define BITM_SPI_STAT_CSERR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Detected a CS Error Condition in Slave Mode */ +#define BITM_SPI_STAT_CS (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* CS Status */ +#define BITM_SPI_STAT_RXOVR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SPI Rx FIFO Overflow */ +#define BITM_SPI_STAT_RXIRQ (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SPI Rx IRQ */ +#define BITM_SPI_STAT_TXIRQ (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SPI Tx IRQ */ +#define BITM_SPI_STAT_TXUNDR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SPI Tx FIFO Underflow */ +#define BITM_SPI_STAT_TXDONE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SPI Tx Done in Read Command Mode */ +#define BITM_SPI_STAT_TXEMPTY (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* SPI Tx FIFO Empty Interrupt */ +#define BITM_SPI_STAT_XFRDONE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SPI Transfer Completion */ +#define BITM_SPI_STAT_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SPI Interrupt Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_RX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_RX_BYTE2 8 /* 8-bit Receive Buffer, Used Only in DMA Modes */ +#define BITP_SPI_RX_BYTE1 0 /* 8-bit Receive Buffer */ +#define BITM_SPI_RX_BYTE2 (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* 8-bit Receive Buffer, Used Only in DMA Modes */ +#define BITM_SPI_RX_BYTE1 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* 8-bit Receive Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_TX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_TX_BYTE2 8 /* 8-bit Transmit Buffer, Used Only in DMA Modes */ +#define BITP_SPI_TX_BYTE1 0 /* 8-bit Transmit Buffer */ +#define BITM_SPI_TX_BYTE2 (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* 8-bit Transmit Buffer, Used Only in DMA Modes */ +#define BITM_SPI_TX_BYTE1 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* 8-bit Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DIV_VALUE 0 /* SPI Clock Divider */ +#define BITM_SPI_DIV_VALUE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* SPI Clock Divider */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CTL_CSRST 14 /* Reset Mode for CS Error Bit */ +#define BITP_SPI_CTL_TFLUSH 13 /* SPI Tx FIFO Flush Enable */ +#define BITP_SPI_CTL_RFLUSH 12 /* SPI Rx FIFO Flush Enable */ +#define BITP_SPI_CTL_CON 11 /* Continuous Transfer Enable */ +#define BITP_SPI_CTL_LOOPBACK 10 /* Loopback Enable */ +#define BITP_SPI_CTL_OEN 9 /* Slave MISO Output Enable */ +#define BITP_SPI_CTL_RXOF 8 /* Rx Overflow Overwrite Enable */ +#define BITP_SPI_CTL_ZEN 7 /* Transmit Zeros Enable */ +#define BITP_SPI_CTL_TIM 6 /* SPI Transfer and Interrupt Mode */ +#define BITP_SPI_CTL_LSB 5 /* LSB First Transfer Enable */ +#define BITP_SPI_CTL_WOM 4 /* SPI Wired-OR Mode */ +#define BITP_SPI_CTL_CPOL 3 /* Serial Clock Polarity */ +#define BITP_SPI_CTL_CPHA 2 /* Serial Clock Phase Mode */ +#define BITP_SPI_CTL_MASEN 1 /* Master Mode Enable */ +#define BITP_SPI_CTL_SPIEN 0 /* SPI Enable */ +#define BITM_SPI_CTL_CSRST (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Reset Mode for CS Error Bit */ +#define BITM_SPI_CTL_TFLUSH (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SPI Tx FIFO Flush Enable */ +#define BITM_SPI_CTL_RFLUSH (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* SPI Rx FIFO Flush Enable */ +#define BITM_SPI_CTL_CON (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Continuous Transfer Enable */ +#define BITM_SPI_CTL_LOOPBACK (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Loopback Enable */ +#define BITM_SPI_CTL_OEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave MISO Output Enable */ +#define BITM_SPI_CTL_RXOF (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Rx Overflow Overwrite Enable */ +#define BITM_SPI_CTL_ZEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Transmit Zeros Enable */ +#define BITM_SPI_CTL_TIM (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SPI Transfer and Interrupt Mode */ +#define BITM_SPI_CTL_LSB (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* LSB First Transfer Enable */ +#define BITM_SPI_CTL_WOM (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SPI Wired-OR Mode */ +#define BITM_SPI_CTL_CPOL (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Serial Clock Polarity */ +#define BITM_SPI_CTL_CPHA (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Serial Clock Phase Mode */ +#define BITM_SPI_CTL_MASEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Master Mode Enable */ +#define BITM_SPI_CTL_SPIEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SPI Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_IEN_TXEMPTY 14 /* Tx FIFO Empty Interrupt Enable */ +#define BITP_SPI_IEN_XFRDONE 13 /* SPI Transfer Completion Interrupt Enable */ +#define BITP_SPI_IEN_TXDONE 12 /* SPI Transmit Done Interrupt Enable */ +#define BITP_SPI_IEN_RDY 11 /* Ready Signal Edge Interrupt Enable */ +#define BITP_SPI_IEN_RXOVR 10 /* Rx Overflow Interrupt Enable */ +#define BITP_SPI_IEN_TXUNDR 9 /* Tx Underflow Interrupt Enable */ +#define BITP_SPI_IEN_CS 8 /* Enable Interrupt on Every CS Edge in Slave CON Mode */ +#define BITP_SPI_IEN_IRQMODE 0 /* SPI IRQ Mode Bits */ +#define BITM_SPI_IEN_TXEMPTY (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Tx FIFO Empty Interrupt Enable */ +#define BITM_SPI_IEN_XFRDONE (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SPI Transfer Completion Interrupt Enable */ +#define BITM_SPI_IEN_TXDONE (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* SPI Transmit Done Interrupt Enable */ +#define BITM_SPI_IEN_RDY (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Ready Signal Edge Interrupt Enable */ +#define BITM_SPI_IEN_RXOVR (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Rx Overflow Interrupt Enable */ +#define BITM_SPI_IEN_TXUNDR (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Tx Underflow Interrupt Enable */ +#define BITM_SPI_IEN_CS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Enable Interrupt on Every CS Edge in Slave CON Mode */ +#define BITM_SPI_IEN_IRQMODE (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* SPI IRQ Mode Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CNT_FRAMECONT 15 /* Continue Frame */ +#define BITP_SPI_CNT_VALUE 0 /* Transfer Byte Count */ +#define BITM_SPI_CNT_FRAMECONT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Continue Frame */ +#define BITM_SPI_CNT_VALUE (_ADI_MSK_3(0x00003FFF,0x00003FFFU, uint16_t )) /* Transfer Byte Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DMA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DMA_RXEN 2 /* Enable Receive DMA Request */ +#define BITP_SPI_DMA_TXEN 1 /* Enable Transmit DMA Request */ +#define BITP_SPI_DMA_EN 0 /* Enable DMA for Data Transfer */ +#define BITM_SPI_DMA_RXEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Receive DMA Request */ +#define BITM_SPI_DMA_TXEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable Transmit DMA Request */ +#define BITM_SPI_DMA_EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable DMA for Data Transfer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_FIFO_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_FIFO_STAT_RX 8 /* SPI Rx FIFO Dtatus */ +#define BITP_SPI_FIFO_STAT_TX 0 /* SPI Tx FIFO Status */ +#define BITM_SPI_FIFO_STAT_RX (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SPI Rx FIFO Dtatus */ +#define BITM_SPI_FIFO_STAT_TX (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* SPI Tx FIFO Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_RD_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_RD_CTL_THREEPIN 8 /* Three Pin SPI Mode */ +#define BITP_SPI_RD_CTL_TXBYTES 2 /* Transmit Byte Count - 1 (Read Command) */ +#define BITP_SPI_RD_CTL_OVERLAP 1 /* Tx/Rx Overlap Mode */ +#define BITP_SPI_RD_CTL_CMDEN 0 /* Read Command Enable */ +#define BITM_SPI_RD_CTL_THREEPIN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Three Pin SPI Mode */ +#define BITM_SPI_RD_CTL_TXBYTES (_ADI_MSK_3(0x0000003C,0x0000003CU, uint16_t )) /* Transmit Byte Count - 1 (Read Command) */ +#define BITM_SPI_RD_CTL_OVERLAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Tx/Rx Overlap Mode */ +#define BITM_SPI_RD_CTL_CMDEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Read Command Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_FLOW_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_FLOW_CTL_RDBURSTSZ 8 /* Read Data Burst Size - 1 */ +#define BITP_SPI_FLOW_CTL_RDYPOL 4 /* Polarity of RDY/MISO Line */ +#define BITP_SPI_FLOW_CTL_MODE 0 /* Flow Control Mode */ +#define BITM_SPI_FLOW_CTL_RDBURSTSZ (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* Read Data Burst Size - 1 */ +#define BITM_SPI_FLOW_CTL_RDYPOL (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Polarity of RDY/MISO Line */ +#define BITM_SPI_FLOW_CTL_MODE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Flow Control Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_WAIT_TMR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_WAIT_TMR_VALUE 0 /* Wait Timer */ +#define BITM_SPI_WAIT_TMR_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Wait Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CS_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CS_CTL_SEL 0 /* Chip Select Control */ +#define BITM_SPI_CS_CTL_SEL (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Chip Select Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CS_OVERRIDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CS_OVERRIDE_CTL 0 /* CS Override Control */ +#define BITM_SPI_CS_OVERRIDE_CTL (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* CS Override Control */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + UART0 + ============================================================================================================================ */ +#define REG_UART0_RX 0x40005000 /* UART0 Receive Buffer Register */ +#define REG_UART0_TX 0x40005000 /* UART0 Transmit Holding Register */ +#define REG_UART0_IEN 0x40005004 /* UART0 Interrupt Enable */ +#define REG_UART0_IIR 0x40005008 /* UART0 Interrupt ID */ +#define REG_UART0_LCR 0x4000500C /* UART0 Line Control */ +#define REG_UART0_MCR 0x40005010 /* UART0 Modem Control */ +#define REG_UART0_LSR 0x40005014 /* UART0 Line Status */ +#define REG_UART0_MSR 0x40005018 /* UART0 Modem Status */ +#define REG_UART0_SCR 0x4000501C /* UART0 Scratch Buffer */ +#define REG_UART0_FCR 0x40005020 /* UART0 FIFO Control */ +#define REG_UART0_FBR 0x40005024 /* UART0 Fractional Baud Rate */ +#define REG_UART0_DIV 0x40005028 /* UART0 Baud Rate Divider */ +#define REG_UART0_LCR2 0x4000502C /* UART0 Second Line Control */ +#define REG_UART0_CTL 0x40005030 /* UART0 UART Control Register */ +#define REG_UART0_RFC 0x40005034 /* UART0 RX FIFO Byte Count */ +#define REG_UART0_TFC 0x40005038 /* UART0 TX FIFO Byte Count */ +#define REG_UART0_RSC 0x4000503C /* UART0 RS485 Half-duplex Control */ +#define REG_UART0_ACR 0x40005040 /* UART0 Auto Baud Control */ +#define REG_UART0_ASRL 0x40005044 /* UART0 Auto Baud Status (Low) */ +#define REG_UART0_ASRH 0x40005048 /* UART0 Auto Baud Status (High) */ + +/* ============================================================================================================================ + UART Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RX_RBR 0 /* Receive Buffer Register */ +#define BITM_UART_RX_RBR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Receive Buffer Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_TX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_TX_THR 0 /* Transmit Holding Register */ +#define BITM_UART_TX_THR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Transmit Holding Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_IEN_EDMAR 5 /* DMA Requests in Receive Mode */ +#define BITP_UART_IEN_EDMAT 4 /* DMA Requests in Transmit Mode */ +#define BITP_UART_IEN_EDSSI 3 /* Modem Status Interrupt */ +#define BITP_UART_IEN_ELSI 2 /* Rx Status Interrupt */ +#define BITP_UART_IEN_ETBEI 1 /* Transmit Buffer Empty Interrupt */ +#define BITP_UART_IEN_ERBFI 0 /* Receive Buffer Full Interrupt */ +#define BITM_UART_IEN_EDMAR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* DMA Requests in Receive Mode */ +#define BITM_UART_IEN_EDMAT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* DMA Requests in Transmit Mode */ +#define BITM_UART_IEN_EDSSI (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Modem Status Interrupt */ +#define BITM_UART_IEN_ELSI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Rx Status Interrupt */ +#define BITM_UART_IEN_ETBEI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Transmit Buffer Empty Interrupt */ +#define BITM_UART_IEN_ERBFI (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Receive Buffer Full Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_IIR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_IIR_FEND 6 /* FIFO Enabled */ +#define BITP_UART_IIR_STAT 1 /* Interrupt Status */ +#define BITP_UART_IIR_NIRQ 0 /* Interrupt Flag */ +#define BITM_UART_IIR_FEND (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* FIFO Enabled */ +#define BITM_UART_IIR_STAT (_ADI_MSK_3(0x0000000E,0x0000000EU, uint16_t )) /* Interrupt Status */ +#define BITM_UART_IIR_NIRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Flag */ +#define ENUM_UART_IIR_STAT_EDSSI (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* STAT: Modem status interrupt (Read MSR register to clear) */ +#define ENUM_UART_IIR_STAT_ETBEI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* STAT: Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */ +#define ENUM_UART_IIR_STAT_ERBFI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* STAT: Receive buffer full interrupt (Read Rx register to clear) */ +#define ENUM_UART_IIR_STAT_RLSI (_ADI_MSK_3(0x00000006,0x00000006U, uint16_t )) /* STAT: Receive line status interrupt (Read LSR register to clear) */ +#define ENUM_UART_IIR_STAT_RFTOI (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* STAT: Receive FIFO time-out interrupt (Read Rx register to clear) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LCR_BRK 6 /* Set Break */ +#define BITP_UART_LCR_SP 5 /* Stick Parity */ +#define BITP_UART_LCR_EPS 4 /* Parity Select */ +#define BITP_UART_LCR_PEN 3 /* Parity Enable */ +#define BITP_UART_LCR_STOP 2 /* Stop Bit */ +#define BITP_UART_LCR_WLS 0 /* Word Length Select */ +#define BITM_UART_LCR_BRK (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Set Break */ +#define BITM_UART_LCR_SP (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Stick Parity */ +#define BITM_UART_LCR_EPS (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Parity Select */ +#define BITM_UART_LCR_PEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Parity Enable */ +#define BITM_UART_LCR_STOP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Stop Bit */ +#define BITM_UART_LCR_WLS (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Word Length Select */ +#define ENUM_UART_LCR_PAR_NOTFORCED (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SP: Parity will not be forced based on Parity Select and Parity Enable bits. */ +#define ENUM_UART_LCR_PAR_FORCED (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SP: Parity forced based on Parity Select and Parity Enable bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_MCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_MCR_LOOPBACK 4 /* Loopback Mode */ +#define BITP_UART_MCR_OUT2 3 /* Output 2 */ +#define BITP_UART_MCR_OUT1 2 /* Output 1 */ +#define BITP_UART_MCR_RTS 1 /* Request to Send */ +#define BITP_UART_MCR_DTR 0 /* Data Terminal Ready */ +#define BITM_UART_MCR_LOOPBACK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Loopback Mode */ +#define BITM_UART_MCR_OUT2 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Output 2 */ +#define BITM_UART_MCR_OUT1 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Output 1 */ +#define BITM_UART_MCR_RTS (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Request to Send */ +#define BITM_UART_MCR_DTR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Data Terminal Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LSR_FIFOERR 7 /* Rx FIFO Parity Error/Frame Error/Break Indication */ +#define BITP_UART_LSR_TEMT 6 /* Transmit and Shift Register Empty Status */ +#define BITP_UART_LSR_THRE 5 /* Transmit Register Empty */ +#define BITP_UART_LSR_BI 4 /* Break Indicator */ +#define BITP_UART_LSR_FE 3 /* Framing Error */ +#define BITP_UART_LSR_PE 2 /* Parity Error */ +#define BITP_UART_LSR_OE 1 /* Overrun Error */ +#define BITP_UART_LSR_DR 0 /* Data Ready */ +#define BITM_UART_LSR_FIFOERR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Rx FIFO Parity Error/Frame Error/Break Indication */ +#define BITM_UART_LSR_TEMT (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Transmit and Shift Register Empty Status */ +#define BITM_UART_LSR_THRE (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Transmit Register Empty */ +#define BITM_UART_LSR_BI (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Break Indicator */ +#define BITM_UART_LSR_FE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Framing Error */ +#define BITM_UART_LSR_PE (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Parity Error */ +#define BITM_UART_LSR_OE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Overrun Error */ +#define BITM_UART_LSR_DR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Data Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_MSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_MSR_DCD 7 /* Data Carrier Detect */ +#define BITP_UART_MSR_RI 6 /* Ring Indicator */ +#define BITP_UART_MSR_DSR 5 /* Data Set Ready */ +#define BITP_UART_MSR_CTS 4 /* Clear to Send */ +#define BITP_UART_MSR_DDCD 3 /* Delta DCD */ +#define BITP_UART_MSR_TERI 2 /* Trailing Edge RI */ +#define BITP_UART_MSR_DDSR 1 /* Delta DSR */ +#define BITP_UART_MSR_DCTS 0 /* Delta CTS */ +#define BITM_UART_MSR_DCD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Data Carrier Detect */ +#define BITM_UART_MSR_RI (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Ring Indicator */ +#define BITM_UART_MSR_DSR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Data Set Ready */ +#define BITM_UART_MSR_CTS (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Clear to Send */ +#define BITM_UART_MSR_DDCD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Delta DCD */ +#define BITM_UART_MSR_TERI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Trailing Edge RI */ +#define BITM_UART_MSR_DDSR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Delta DSR */ +#define BITM_UART_MSR_DCTS (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Delta CTS */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_SCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_SCR_SCR 0 /* Scratch */ +#define BITM_UART_SCR_SCR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Scratch */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_FCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_FCR_RFTRIG 6 /* Rx FIFO Trigger Level */ +#define BITP_UART_FCR_FDMAMD 3 /* FIFO DMA Mode */ +#define BITP_UART_FCR_TFCLR 2 /* Clear Tx FIFO */ +#define BITP_UART_FCR_RFCLR 1 /* Clear Rx FIFO */ +#define BITP_UART_FCR_FIFOEN 0 /* FIFO Enable as to Work in 16550 Mode */ +#define BITM_UART_FCR_RFTRIG (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* Rx FIFO Trigger Level */ +#define BITM_UART_FCR_FDMAMD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* FIFO DMA Mode */ +#define BITM_UART_FCR_TFCLR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Clear Tx FIFO */ +#define BITM_UART_FCR_RFCLR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Rx FIFO */ +#define BITM_UART_FCR_FIFOEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* FIFO Enable as to Work in 16550 Mode */ +#define ENUM_UART_FCR_MODE0 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* FDMAMD: In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */ +#define ENUM_UART_FCR_MODE1 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* FDMAMD: in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_FBR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_FBR_FBEN 15 /* Fractional Baud Rate Generator Enable */ +#define BITP_UART_FBR_DIVM 11 /* Fractional Baud Rate M Divide Bits 1 to 3 */ +#define BITP_UART_FBR_DIVN 0 /* Fractional Baud Rate N Divide Bits 0 to 2047 */ +#define BITM_UART_FBR_FBEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Fractional Baud Rate Generator Enable */ +#define BITM_UART_FBR_DIVM (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t )) /* Fractional Baud Rate M Divide Bits 1 to 3 */ +#define BITM_UART_FBR_DIVN (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t )) /* Fractional Baud Rate N Divide Bits 0 to 2047 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_DIV_DIV 0 /* Baud Rate Divider */ +#define BITM_UART_DIV_DIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Baud Rate Divider */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LCR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LCR2_OSR 0 /* Over Sample Rate */ +#define BITM_UART_LCR2_OSR (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Over Sample Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_CTL_REV 8 /* UART Revision ID */ +#define BITP_UART_CTL_RXINV 4 /* Invert Receiver Line */ +#define BITP_UART_CTL_FORCECLK 1 /* Force UCLK on */ +#define BITM_UART_CTL_REV (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* UART Revision ID */ +#define BITM_UART_CTL_RXINV (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Invert Receiver Line */ +#define BITM_UART_CTL_FORCECLK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Force UCLK on */ +#define ENUM_UART_CTL_NOTINV_RX (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* RXINV: Don't invert receiver line (idling high). */ +#define ENUM_UART_CTL_INV_RX (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* RXINV: Invert receiver line (idling low). */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RFC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RFC_RFC 0 /* Current Rx FIFO Data Bytes */ +#define BITM_UART_RFC_RFC (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Current Rx FIFO Data Bytes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_TFC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_TFC_TFC 0 /* Current Tx FIFO Data Bytes */ +#define BITM_UART_TFC_TFC (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Current Tx FIFO Data Bytes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RSC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RSC_DISTX 3 /* Hold off Tx When Receiving */ +#define BITP_UART_RSC_DISRX 2 /* Disable Rx When Transmitting */ +#define BITP_UART_RSC_OENSP 1 /* SOUT_EN De-assert Before Full Stop Bit(s) */ +#define BITP_UART_RSC_OENP 0 /* SOUT_EN Polarity */ +#define BITM_UART_RSC_DISTX (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Hold off Tx When Receiving */ +#define BITM_UART_RSC_DISRX (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Disable Rx When Transmitting */ +#define BITM_UART_RSC_OENSP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SOUT_EN De-assert Before Full Stop Bit(s) */ +#define BITM_UART_RSC_OENP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SOUT_EN Polarity */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ACR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ACR_EEC 8 /* Ending Edge Count */ +#define BITP_UART_ACR_SEC 4 /* Starting Edge Count */ +#define BITP_UART_ACR_TOIEN 2 /* Enable Time-out Interrupt */ +#define BITP_UART_ACR_DNIEN 1 /* Enable Done Interrupt */ +#define BITP_UART_ACR_ABE 0 /* Auto Baud Enable */ +#define BITM_UART_ACR_EEC (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* Ending Edge Count */ +#define BITM_UART_ACR_SEC (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* Starting Edge Count */ +#define BITM_UART_ACR_TOIEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Time-out Interrupt */ +#define BITM_UART_ACR_DNIEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable Done Interrupt */ +#define BITM_UART_ACR_ABE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Auto Baud Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ASRL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ASRL_CNT 4 /* Auto Baud Counter Value */ +#define BITP_UART_ASRL_NEETO 3 /* Timed Out Due to No Valid Ending Edge Found */ +#define BITP_UART_ASRL_NSETO 2 /* Timed Out Due to No Valid Start Edge Found */ +#define BITP_UART_ASRL_BRKTO 1 /* Timed Out Due to Long Time Break Condition */ +#define BITP_UART_ASRL_DONE 0 /* Auto Baud Done Successfully */ +#define BITM_UART_ASRL_CNT (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t )) /* Auto Baud Counter Value */ +#define BITM_UART_ASRL_NEETO (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timed Out Due to No Valid Ending Edge Found */ +#define BITM_UART_ASRL_NSETO (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Timed Out Due to No Valid Start Edge Found */ +#define BITM_UART_ASRL_BRKTO (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Timed Out Due to Long Time Break Condition */ +#define BITM_UART_ASRL_DONE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Auto Baud Done Successfully */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ASRH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ASRH_CNT 0 /* Auto Baud Counter Value */ +#define BITM_UART_ASRH_CNT (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Auto Baud Counter Value */ + + +/* ============================================================================================================================ + Beeper Driver + ============================================================================================================================ */ + +/* ============================================================================================================================ + BEEP0 + ============================================================================================================================ */ +#define REG_BEEP0_CFG 0x40005C00 /* BEEP0 Beeper Configuration */ +#define REG_BEEP0_STAT 0x40005C04 /* BEEP0 Beeper Status */ +#define REG_BEEP0_TONEA 0x40005C08 /* BEEP0 Tone A Data */ +#define REG_BEEP0_TONEB 0x40005C0C /* BEEP0 Tone B Data */ + +/* ============================================================================================================================ + BEEP Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_CFG_SEQATENDIRQ 15 /* Sequence End IRQ */ +#define BITP_BEEP_CFG_SEQNEARENDIRQ 14 /* Sequence 1 Cycle from End IRQ */ +#define BITP_BEEP_CFG_BENDIRQ 13 /* Tone B End IRQ */ +#define BITP_BEEP_CFG_BSTARTIRQ 12 /* Tone B Start IRQ */ +#define BITP_BEEP_CFG_AENDIRQ 11 /* Tone A End IRQ */ +#define BITP_BEEP_CFG_ASTARTIRQ 10 /* Tone A Start IRQ */ +#define BITP_BEEP_CFG_EN 8 /* Beeper Enable */ +#define BITP_BEEP_CFG_SEQREPEAT 0 /* Beeper Sequence Repeat Value */ +#define BITM_BEEP_CFG_SEQATENDIRQ (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Sequence End IRQ */ +#define BITM_BEEP_CFG_SEQNEARENDIRQ (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Sequence 1 Cycle from End IRQ */ +#define BITM_BEEP_CFG_BENDIRQ (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Tone B End IRQ */ +#define BITM_BEEP_CFG_BSTARTIRQ (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Tone B Start IRQ */ +#define BITM_BEEP_CFG_AENDIRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Tone A End IRQ */ +#define BITM_BEEP_CFG_ASTARTIRQ (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Tone A Start IRQ */ +#define BITM_BEEP_CFG_EN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Beeper Enable */ +#define BITM_BEEP_CFG_SEQREPEAT (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Beeper Sequence Repeat Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_STAT_SEQENDED 15 /* Sequencer Has Ended */ +#define BITP_BEEP_STAT_SEQNEAREND 14 /* Sequencer Last Tone-pair Has Started */ +#define BITP_BEEP_STAT_BENDED 13 /* Tone B Has Ended */ +#define BITP_BEEP_STAT_BSTARTED 12 /* Tone B Has Started */ +#define BITP_BEEP_STAT_AENDED 11 /* Tone A Has Ended */ +#define BITP_BEEP_STAT_ASTARTED 10 /* Tone A Has Started */ +#define BITP_BEEP_STAT_BUSY 8 /* Beeper is Busy */ +#define BITP_BEEP_STAT_SEQREMAIN 0 /* Remaining Tone-pair Iterations to Play in Sequence Mode */ +#define BITM_BEEP_STAT_SEQENDED (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Sequencer Has Ended */ +#define BITM_BEEP_STAT_SEQNEAREND (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Sequencer Last Tone-pair Has Started */ +#define BITM_BEEP_STAT_BENDED (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Tone B Has Ended */ +#define BITM_BEEP_STAT_BSTARTED (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Tone B Has Started */ +#define BITM_BEEP_STAT_AENDED (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Tone A Has Ended */ +#define BITM_BEEP_STAT_ASTARTED (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Tone A Has Started */ +#define BITM_BEEP_STAT_BUSY (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Beeper is Busy */ +#define BITM_BEEP_STAT_SEQREMAIN (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Remaining Tone-pair Iterations to Play in Sequence Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_TONEA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_TONEA_DIS 15 /* Output Disable */ +#define BITP_BEEP_TONEA_FREQ 8 /* Tone Frequency */ +#define BITP_BEEP_TONEA_DUR 0 /* Tone Duration */ +#define BITM_BEEP_TONEA_DIS (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Disable */ +#define BITM_BEEP_TONEA_FREQ (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t )) /* Tone Frequency */ +#define BITM_BEEP_TONEA_DUR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Tone Duration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_TONEB Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_TONEB_DIS 15 /* Output Disable */ +#define BITP_BEEP_TONEB_FREQ 8 /* Tone Frequency */ +#define BITP_BEEP_TONEB_DUR 0 /* Tone Duration */ +#define BITM_BEEP_TONEB_DIS (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Disable */ +#define BITM_BEEP_TONEB_FREQ (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t )) /* Tone Frequency */ +#define BITM_BEEP_TONEB_DUR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Tone Duration */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + ADC0 + ============================================================================================================================ */ +#define REG_ADC0_CFG 0x40007000 /* ADC0 ADC Configuration */ +#define REG_ADC0_PWRUP 0x40007004 /* ADC0 ADC Power-up Time */ +#define REG_ADC0_CAL_WORD 0x40007008 /* ADC0 Calibration Word */ +#define REG_ADC0_CNV_CFG 0x4000700C /* ADC0 ADC Conversion Configuration */ +#define REG_ADC0_CNV_TIME 0x40007010 /* ADC0 ADC Conversion Time */ +#define REG_ADC0_AVG_CFG 0x40007014 /* ADC0 Averaging Configuration */ +#define REG_ADC0_IRQ_EN 0x40007020 /* ADC0 Interrupt Enable */ +#define REG_ADC0_STAT 0x40007024 /* ADC0 ADC Status */ +#define REG_ADC0_OVF 0x40007028 /* ADC0 Overflow of Output Registers */ +#define REG_ADC0_ALERT 0x4000702C /* ADC0 Alert Indication */ +#define REG_ADC0_CH0_OUT 0x40007030 /* ADC0 Conversion Result Channel 0 */ +#define REG_ADC0_CH1_OUT 0x40007034 /* ADC0 Conversion Result Channel 1 */ +#define REG_ADC0_CH2_OUT 0x40007038 /* ADC0 Conversion Result Channel 2 */ +#define REG_ADC0_CH3_OUT 0x4000703C /* ADC0 Conversion Result Channel 3 */ +#define REG_ADC0_CH4_OUT 0x40007040 /* ADC0 Conversion Result Channel 4 */ +#define REG_ADC0_CH5_OUT 0x40007044 /* ADC0 Conversion Result Channel 5 */ +#define REG_ADC0_CH6_OUT 0x40007048 /* ADC0 Conversion Result Channel 6 */ +#define REG_ADC0_CH7_OUT 0x4000704C /* ADC0 Conversion Result Channel 7 */ +#define REG_ADC0_BAT_OUT 0x40007050 /* ADC0 Battery Monitoring Result */ +#define REG_ADC0_TMP_OUT 0x40007054 /* ADC0 Temperature Result */ +#define REG_ADC0_TMP2_OUT 0x40007058 /* ADC0 Temperature Result 2 */ +#define REG_ADC0_DMA_OUT 0x4000705C /* ADC0 DMA Output Register */ +#define REG_ADC0_LIM0_LO 0x40007060 /* ADC0 Channel 0 Low Limit */ +#define REG_ADC0_LIM0_HI 0x40007064 /* ADC0 Channel 0 High Limit */ +#define REG_ADC0_HYS0 0x40007068 /* ADC0 Channel 0 Hysteresis */ +#define REG_ADC0_LIM1_LO 0x40007070 /* ADC0 Channel 1 Low Limit */ +#define REG_ADC0_LIM1_HI 0x40007074 /* ADC0 Channel 1 High Limit */ +#define REG_ADC0_HYS1 0x40007078 /* ADC0 Channel 1 Hysteresis */ +#define REG_ADC0_LIM2_LO 0x40007080 /* ADC0 Channel 2 Low Limit */ +#define REG_ADC0_LIM2_HI 0x40007084 /* ADC0 Channel 2 High Limit */ +#define REG_ADC0_HYS2 0x40007088 /* ADC0 Channel 2 Hysteresis */ +#define REG_ADC0_LIM3_LO 0x40007090 /* ADC0 Channel 3 Low Limit */ +#define REG_ADC0_LIM3_HI 0x40007094 /* ADC0 Channel 3 High Limit */ +#define REG_ADC0_HYS3 0x40007098 /* ADC0 Channel 3 Hysteresis */ +#define REG_ADC0_CFG1 0x400070C0 /* ADC0 Reference Buffer Low Power Mode */ + +/* ============================================================================================================================ + ADC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CFG_FAST_DISCH 9 /* Fast Switchover of Vref from 2.5 to 1.25 */ +#define BITP_ADC_CFG_TMPEN 8 /* Power up Temperature Sensor */ +#define BITP_ADC_CFG_SINKEN 7 /* Enable Additional Sink Current Capability */ +#define BITP_ADC_CFG_RST 6 /* Reset */ +#define BITP_ADC_CFG_STARTCAL 5 /* Start a New Offset Calibration Cycle */ +#define BITP_ADC_CFG_EN 4 /* Enable ADC Subsystem */ +#define BITP_ADC_CFG_REFBUFEN 2 /* Enable Internal Reference Buffer */ +#define BITP_ADC_CFG_VREFSEL 1 /* Select Vref as 1.25V or 2.5V */ +#define BITP_ADC_CFG_PWRUP 0 /* Powering up the ADC */ +#define BITM_ADC_CFG_FAST_DISCH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Fast Switchover of Vref from 2.5 to 1.25 */ +#define BITM_ADC_CFG_TMPEN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Power up Temperature Sensor */ +#define BITM_ADC_CFG_SINKEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Enable Additional Sink Current Capability */ +#define BITM_ADC_CFG_RST (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Reset */ +#define BITM_ADC_CFG_STARTCAL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Start a New Offset Calibration Cycle */ +#define BITM_ADC_CFG_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable ADC Subsystem */ +#define BITM_ADC_CFG_REFBUFEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Internal Reference Buffer */ +#define BITM_ADC_CFG_VREFSEL (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Select Vref as 1.25V or 2.5V */ +#define BITM_ADC_CFG_PWRUP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Powering up the ADC */ +#define ENUM_ADC_CFG_EXT_REF (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* REFBUFEN: External reference is used */ +#define ENUM_ADC_CFG_BUF_REF (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* REFBUFEN: Reference buffer is enabled */ +#define ENUM_ADC_CFG_V_2P5 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* VREFSEL: Vref = 2.5V */ +#define ENUM_ADC_CFG_V_1P25 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* VREFSEL: Vref = 1.25V */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_PWRUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_PWRUP_WAIT 0 /* Program This with 526/PCLKDIVCNT */ +#define BITM_ADC_PWRUP_WAIT (_ADI_MSK_3(0x000003FF,0x000003FFU, uint16_t )) /* Program This with 526/PCLKDIVCNT */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CAL_WORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CAL_WORD_VALUE 0 /* Offset Calibration Word */ +#define BITM_ADC_CAL_WORD_VALUE (_ADI_MSK_3(0x0000007F,0x0000007FU, uint16_t )) /* Offset Calibration Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CNV_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CNV_CFG_MULTI 15 /* Multiple Conversions */ +#define BITP_ADC_CNV_CFG_SINGLE 14 /* Single Conversion Start */ +#define BITP_ADC_CNV_CFG_DMAEN 13 /* DMA Channel Enable */ +#define BITP_ADC_CNV_CFG_AUTOMODE 12 /* Auto Mode Enable */ +#define BITP_ADC_CNV_CFG_TMP2 10 /* Temperature Measurement 2 */ +#define BITP_ADC_CNV_CFG_TMP 9 /* Temperature Measurement 1 */ +#define BITP_ADC_CNV_CFG_BAT 8 /* Battery Monitoring Enable */ +#define BITP_ADC_CNV_CFG_SEL 0 /* Selection of Channel(s) to Convert */ +#define BITM_ADC_CNV_CFG_MULTI (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Multiple Conversions */ +#define BITM_ADC_CNV_CFG_SINGLE (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Single Conversion Start */ +#define BITM_ADC_CNV_CFG_DMAEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* DMA Channel Enable */ +#define BITM_ADC_CNV_CFG_AUTOMODE (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Auto Mode Enable */ +#define BITM_ADC_CNV_CFG_TMP2 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Temperature Measurement 2 */ +#define BITM_ADC_CNV_CFG_TMP (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Temperature Measurement 1 */ +#define BITM_ADC_CNV_CFG_BAT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Battery Monitoring Enable */ +#define BITM_ADC_CNV_CFG_SEL (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Selection of Channel(s) to Convert */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CNV_TIME Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CNV_TIME_DLY 8 /* Delay Between Two Consecutive Conversions */ +#define BITP_ADC_CNV_TIME_SAMPTIME 0 /* Sampling Time */ +#define BITM_ADC_CNV_TIME_DLY (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* Delay Between Two Consecutive Conversions */ +#define BITM_ADC_CNV_TIME_SAMPTIME (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Sampling Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_AVG_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_AVG_CFG_EN 15 /* Enable Averaging on Channels Enabled in Enable Register */ +#define BITP_ADC_AVG_CFG_OS 14 /* Enable Oversampling */ +#define BITP_ADC_AVG_CFG_FACTOR 0 /* Averaging Factor */ +#define BITM_ADC_AVG_CFG_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Averaging on Channels Enabled in Enable Register */ +#define BITM_ADC_AVG_CFG_OS (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Oversampling */ +#define BITM_ADC_AVG_CFG_FACTOR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Averaging Factor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_IRQ_EN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_IRQ_EN_RDY 13 /* Set to Enable Interrupt When ADC is Ready to Convert */ +#define BITP_ADC_IRQ_EN_ALERT 12 /* Interrupt on Crossing Lower or Higher Limit Enable */ +#define BITP_ADC_IRQ_EN_OVF 11 /* Enable Overflow Interrupt */ +#define BITP_ADC_IRQ_EN_CALDONE 10 /* Enable Interrupt for Calibration Done */ +#define BITP_ADC_IRQ_EN_CNVDONE 0 /* Enable Conversion Done Interrupt */ +#define BITM_ADC_IRQ_EN_RDY (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Set to Enable Interrupt When ADC is Ready to Convert */ +#define BITM_ADC_IRQ_EN_ALERT (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Interrupt on Crossing Lower or Higher Limit Enable */ +#define BITM_ADC_IRQ_EN_OVF (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Overflow Interrupt */ +#define BITM_ADC_IRQ_EN_CALDONE (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Enable Interrupt for Calibration Done */ +#define BITM_ADC_IRQ_EN_CNVDONE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable Conversion Done Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_STAT_RDY 15 /* ADC Ready to Start Converting */ +#define BITP_ADC_STAT_CALDONE 14 /* Calibration Done */ +#define BITP_ADC_STAT_TMP2DONE 10 /* Conversion Done for Temperature Sensing 2 */ +#define BITP_ADC_STAT_TMPDONE 9 /* Conversion Done for Temperature Sensing */ +#define BITP_ADC_STAT_BATDONE 8 /* Conversion Done - Battery Monitoring */ +#define BITP_ADC_STAT_DONE7 7 /* Conversion Done on Channel 7 */ +#define BITP_ADC_STAT_DONE6 6 /* Conversion Done on Channel 6 */ +#define BITP_ADC_STAT_DONE5 5 /* Conversion Done on Channel 5 */ +#define BITP_ADC_STAT_DONE4 4 /* Conversion Done on Channel 4 */ +#define BITP_ADC_STAT_DONE3 3 /* Conversion Done on Channel 3 */ +#define BITP_ADC_STAT_DONE2 2 /* Conversion Done on Channel 2 */ +#define BITP_ADC_STAT_DONE1 1 /* Conversion Done on Channel 1 */ +#define BITP_ADC_STAT_DONE0 0 /* Conversion Done on Channel 0 */ +#define BITM_ADC_STAT_RDY (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* ADC Ready to Start Converting */ +#define BITM_ADC_STAT_CALDONE (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Calibration Done */ +#define BITM_ADC_STAT_TMP2DONE (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Conversion Done for Temperature Sensing 2 */ +#define BITM_ADC_STAT_TMPDONE (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Conversion Done for Temperature Sensing */ +#define BITM_ADC_STAT_BATDONE (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Conversion Done - Battery Monitoring */ +#define BITM_ADC_STAT_DONE7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Conversion Done on Channel 7 */ +#define BITM_ADC_STAT_DONE6 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Conversion Done on Channel 6 */ +#define BITM_ADC_STAT_DONE5 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Conversion Done on Channel 5 */ +#define BITM_ADC_STAT_DONE4 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Conversion Done on Channel 4 */ +#define BITM_ADC_STAT_DONE3 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Conversion Done on Channel 3 */ +#define BITM_ADC_STAT_DONE2 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Conversion Done on Channel 2 */ +#define BITM_ADC_STAT_DONE1 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Conversion Done on Channel 1 */ +#define BITM_ADC_STAT_DONE0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Conversion Done on Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_OVF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_OVF_TMP2 10 /* Overflow in TMP2_OUT */ +#define BITP_ADC_OVF_TMP 9 /* Overflow in TMP_OUT */ +#define BITP_ADC_OVF_BAT 8 /* Overflow in BAT_OUT */ +#define BITP_ADC_OVF_CH7 7 /* Overflow in CH7_OUT */ +#define BITP_ADC_OVF_CH6 6 /* Overflow in CH6_OUT */ +#define BITP_ADC_OVF_CH5 5 /* Overflow in CH5_OUT */ +#define BITP_ADC_OVF_CH4 4 /* Overflow in CH4_OUT */ +#define BITP_ADC_OVF_CH3 3 /* Overflow in CH3_OUT */ +#define BITP_ADC_OVF_CH2 2 /* Overflow in CH2_OUT */ +#define BITP_ADC_OVF_CH1 1 /* Overflow in CH1_OUT */ +#define BITP_ADC_OVF_CH0 0 /* Overflow in CH0_OUT */ +#define BITM_ADC_OVF_TMP2 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Overflow in TMP2_OUT */ +#define BITM_ADC_OVF_TMP (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Overflow in TMP_OUT */ +#define BITM_ADC_OVF_BAT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Overflow in BAT_OUT */ +#define BITM_ADC_OVF_CH7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Overflow in CH7_OUT */ +#define BITM_ADC_OVF_CH6 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Overflow in CH6_OUT */ +#define BITM_ADC_OVF_CH5 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Overflow in CH5_OUT */ +#define BITM_ADC_OVF_CH4 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Overflow in CH4_OUT */ +#define BITM_ADC_OVF_CH3 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Overflow in CH3_OUT */ +#define BITM_ADC_OVF_CH2 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Overflow in CH2_OUT */ +#define BITM_ADC_OVF_CH1 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Overflow in CH1_OUT */ +#define BITM_ADC_OVF_CH0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Overflow in CH0_OUT */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_ALERT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_ALERT_LO3 7 /* Channel 3 Low Alert Status */ +#define BITP_ADC_ALERT_HI3 6 /* Channel 3 High Alert Status */ +#define BITP_ADC_ALERT_LO2 5 /* Channel 2 Low Alert Status */ +#define BITP_ADC_ALERT_HI2 4 /* Channel 2 High Alert Status */ +#define BITP_ADC_ALERT_LO1 3 /* Channel 1 Low Alert Status */ +#define BITP_ADC_ALERT_HI1 2 /* Channel 1 High Alert Status */ +#define BITP_ADC_ALERT_LO0 1 /* Channel 0 Low Alert Status */ +#define BITP_ADC_ALERT_HI0 0 /* Channel 0 High Alert Status */ +#define BITM_ADC_ALERT_LO3 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Channel 3 Low Alert Status */ +#define BITM_ADC_ALERT_HI3 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Channel 3 High Alert Status */ +#define BITM_ADC_ALERT_LO2 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Channel 2 Low Alert Status */ +#define BITM_ADC_ALERT_HI2 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Channel 2 High Alert Status */ +#define BITM_ADC_ALERT_LO1 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Channel 1 Low Alert Status */ +#define BITM_ADC_ALERT_HI1 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Channel 1 High Alert Status */ +#define BITM_ADC_ALERT_LO0 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Channel 0 Low Alert Status */ +#define BITM_ADC_ALERT_HI0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Channel 0 High Alert Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH0_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH0_OUT_RESULT 0 /* Conversion Result of Channel 0 */ +#define BITM_ADC_CH0_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH1_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH1_OUT_RESULT 0 /* Conversion Result of Channel 1 */ +#define BITM_ADC_CH1_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH2_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH2_OUT_RESULT 0 /* Conversion Result of Channel 2 */ +#define BITM_ADC_CH2_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH3_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH3_OUT_RESULT 0 /* Conversion Result of Channel 3 */ +#define BITM_ADC_CH3_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH4_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH4_OUT_RESULT 0 /* Conversion Result of Channel 4 */ +#define BITM_ADC_CH4_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH5_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH5_OUT_RESULT 0 /* Conversion Result of Channel 5 */ +#define BITM_ADC_CH5_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH6_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH6_OUT_RESULT 0 /* Conversion Result of Channel 6 */ +#define BITM_ADC_CH6_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 6 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH7_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH7_OUT_RESULT 0 /* Conversion Result of Channel 7 */ +#define BITM_ADC_CH7_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Channel 7 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_BAT_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_BAT_OUT_RESULT 0 /* Conversion Result of Battery Monitoring */ +#define BITM_ADC_BAT_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Battery Monitoring */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_TMP_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_TMP_OUT_RESULT 0 /* Conversion Result of Temperature Measurement 1 */ +#define BITM_ADC_TMP_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Temperature Measurement 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_TMP2_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_TMP2_OUT_RESULT 0 /* Conversion Result of Temperature Measurement 2 */ +#define BITM_ADC_TMP2_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result of Temperature Measurement 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_DMA_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_DMA_OUT_RESULT 0 /* Conversion Result for DMA */ +#define BITM_ADC_DMA_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion Result for DMA */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM0_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM0_LO_EN 15 /* Enable Low Limit Comparison on Channel 0 */ +#define BITP_ADC_LIM0_LO_VALUE 0 /* Low Limit for Channel 0 */ +#define BITM_ADC_LIM0_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Low Limit Comparison on Channel 0 */ +#define BITM_ADC_LIM0_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low Limit for Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM0_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM0_HI_EN 15 /* Enable High Limit Comparison on Channel 0 */ +#define BITP_ADC_LIM0_HI_VALUE 0 /* High Limit for Channel 0 */ +#define BITM_ADC_LIM0_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable High Limit Comparison on Channel 0 */ +#define BITM_ADC_LIM0_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High Limit for Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS0_EN 15 /* Enable Hysteresis for Comparison on Channel 0 */ +#define BITP_ADC_HYS0_MONCYC 12 /* Number of Conversion Cycles to Monitor Channel 0 */ +#define BITP_ADC_HYS0_VALUE 0 /* Hysteresis Value for Channel 0 */ +#define BITM_ADC_HYS0_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Hysteresis for Comparison on Channel 0 */ +#define BITM_ADC_HYS0_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Number of Conversion Cycles to Monitor Channel 0 */ +#define BITM_ADC_HYS0_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis Value for Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM1_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM1_LO_EN 15 /* Enable Low Limit Comparison on Channel 1 */ +#define BITP_ADC_LIM1_LO_VALUE 0 /* Low Limit for Channel 1 */ +#define BITM_ADC_LIM1_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Low Limit Comparison on Channel 1 */ +#define BITM_ADC_LIM1_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low Limit for Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM1_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM1_HI_EN 15 /* Enable High Limit Comparison on Channel 1 */ +#define BITP_ADC_LIM1_HI_VALUE 0 /* High Limit for Channel 1 */ +#define BITM_ADC_LIM1_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable High Limit Comparison on Channel 1 */ +#define BITM_ADC_LIM1_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High Limit for Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS1_EN 15 /* Enable Hysteresis for Comparison on Channel 1 */ +#define BITP_ADC_HYS1_MONCYC 12 /* Number of Conversion Cycles to Monitor Channel 1 */ +#define BITP_ADC_HYS1_VALUE 0 /* Hysteresis Value for Channel 1 */ +#define BITM_ADC_HYS1_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Hysteresis for Comparison on Channel 1 */ +#define BITM_ADC_HYS1_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Number of Conversion Cycles to Monitor Channel 1 */ +#define BITM_ADC_HYS1_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis Value for Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM2_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM2_LO_EN 15 /* Enable Low Limit Comparison on Channel 2 */ +#define BITP_ADC_LIM2_LO_VALUE 0 /* Low Limit for Channel 2 */ +#define BITM_ADC_LIM2_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Low Limit Comparison on Channel 2 */ +#define BITM_ADC_LIM2_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low Limit for Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM2_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM2_HI_EN 15 /* Enable High Limit Comparison on Channel */ +#define BITP_ADC_LIM2_HI_VALUE 0 /* High Limit for Channel 2 */ +#define BITM_ADC_LIM2_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable High Limit Comparison on Channel */ +#define BITM_ADC_LIM2_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High Limit for Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS2_EN 15 /* Enable Hysteresis for Comparison on Channel 2 */ +#define BITP_ADC_HYS2_MONCYC 12 /* Number of Conversion Cycles to Monitor Channel 2 */ +#define BITP_ADC_HYS2_VALUE 0 /* Hysteresis Value for Channel 2 */ +#define BITM_ADC_HYS2_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Hysteresis for Comparison on Channel 2 */ +#define BITM_ADC_HYS2_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Number of Conversion Cycles to Monitor Channel 2 */ +#define BITM_ADC_HYS2_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis Value for Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM3_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM3_LO_EN 15 /* Enable Low Limit Comparison on Channel 3 */ +#define BITP_ADC_LIM3_LO_VALUE 0 /* Low Limit for Channel 3 */ +#define BITM_ADC_LIM3_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Low Limit Comparison on Channel 3 */ +#define BITM_ADC_LIM3_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low Limit for Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM3_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM3_HI_EN 15 /* Enable High Limit Comparison on Channel 3 */ +#define BITP_ADC_LIM3_HI_VALUE 0 /* High Limit for Channel 3 */ +#define BITM_ADC_LIM3_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable High Limit Comparison on Channel 3 */ +#define BITM_ADC_LIM3_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High Limit for Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS3_EN 15 /* Enable Hysteresis for Comparison on Channel 3 */ +#define BITP_ADC_HYS3_MONCYC 12 /* Number of Conversion Cycles to Monitor Channel 3 */ +#define BITP_ADC_HYS3_VALUE 0 /* Hysteresis Value for Channel 3 */ +#define BITM_ADC_HYS3_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Hysteresis for Comparison on Channel 3 */ +#define BITM_ADC_HYS3_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Number of Conversion Cycles to Monitor Channel 3 */ +#define BITM_ADC_HYS3_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis Value for Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CFG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CFG1_RBUFLP 0 /* Enable Low Power Mode for Reference Buffer */ +#define BITM_ADC_CFG1_RBUFLP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable Low Power Mode for Reference Buffer */ + + +/* ============================================================================================================================ + DMA + ============================================================================================================================ */ + +/* ============================================================================================================================ + DMA0 + ============================================================================================================================ */ +#define REG_DMA0_STAT 0x40010000 /* DMA0 DMA Status */ +#define REG_DMA0_CFG 0x40010004 /* DMA0 DMA Configuration */ +#define REG_DMA0_PDBPTR 0x40010008 /* DMA0 DMA Channel Primary Control Database Pointer */ +#define REG_DMA0_ADBPTR 0x4001000C /* DMA0 DMA Channel Alternate Control Database Pointer */ +#define REG_DMA0_SWREQ 0x40010014 /* DMA0 DMA Channel Software Request */ +#define REG_DMA0_RMSK_SET 0x40010020 /* DMA0 DMA Channel Request Mask Set */ +#define REG_DMA0_RMSK_CLR 0x40010024 /* DMA0 DMA Channel Request Mask Clear */ +#define REG_DMA0_EN_SET 0x40010028 /* DMA0 DMA Channel Enable Set */ +#define REG_DMA0_EN_CLR 0x4001002C /* DMA0 DMA Channel Enable Clear */ +#define REG_DMA0_ALT_SET 0x40010030 /* DMA0 DMA Channel Primary Alternate Set */ +#define REG_DMA0_ALT_CLR 0x40010034 /* DMA0 DMA Channel Primary Alternate Clear */ +#define REG_DMA0_PRI_SET 0x40010038 /* DMA0 DMA Channel Priority Set */ +#define REG_DMA0_PRI_CLR 0x4001003C /* DMA0 DMA Channel Priority Clear */ +#define REG_DMA0_ERRCHNL_CLR 0x40010048 /* DMA0 DMA per Channel Error Clear */ +#define REG_DMA0_ERR_CLR 0x4001004C /* DMA0 DMA Bus Error Clear */ +#define REG_DMA0_INVALIDDESC_CLR 0x40010050 /* DMA0 DMA per Channel Invalid Descriptor Clear */ +#define REG_DMA0_BS_SET 0x40010800 /* DMA0 DMA Channel Bytes Swap Enable Set */ +#define REG_DMA0_BS_CLR 0x40010804 /* DMA0 DMA Channel Bytes Swap Enable Clear */ +#define REG_DMA0_SRCADDR_SET 0x40010810 /* DMA0 DMA Channel Source Address Decrement Enable Set */ +#define REG_DMA0_SRCADDR_CLR 0x40010814 /* DMA0 DMA Channel Source Address Decrement Enable Clear */ +#define REG_DMA0_DSTADDR_SET 0x40010818 /* DMA0 DMA Channel Destination Address Decrement Enable Set */ +#define REG_DMA0_DSTADDR_CLR 0x4001081C /* DMA0 DMA Channel Destination Address Decrement Enable Clear */ +#define REG_DMA0_REVID 0x40010FE0 /* DMA0 DMA Controller Revision ID */ + +/* ============================================================================================================================ + DMA Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_STAT_CHANM1 16 /* Number of Available DMA Channels Minus 1 */ +#define BITP_DMA_STAT_MEN 0 /* Enable Status of the Controller */ +#define BITM_DMA_STAT_CHANM1 (_ADI_MSK_3(0x001F0000,0x001F0000UL, uint32_t )) /* Number of Available DMA Channels Minus 1 */ +#define BITM_DMA_STAT_MEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Status of the Controller */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_CFG_MEN 0 /* Controller Enable */ +#define BITM_DMA_CFG_MEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Controller Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PDBPTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PDBPTR_ADDR 0 /* Pointer to the Base Address of the Primary Data Structure */ +#define BITM_DMA_PDBPTR_ADDR (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Pointer to the Base Address of the Primary Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ADBPTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ADBPTR_ADDR 0 /* Base Address of the Alternate Data Structure */ +#define BITM_DMA_ADBPTR_ADDR (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Base Address of the Alternate Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SWREQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SWREQ_CHAN 0 /* Generate Software Request */ +#define BITM_DMA_SWREQ_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Generate Software Request */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_RMSK_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_RMSK_SET_CHAN 0 /* Mask Requests from DMA Channels */ +#define BITM_DMA_RMSK_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Mask Requests from DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_RMSK_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_RMSK_CLR_CHAN 0 /* Clear Request Mask Set Bits */ +#define BITM_DMA_RMSK_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Clear Request Mask Set Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_EN_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_EN_SET_CHAN 0 /* Enable DMA Channels */ +#define BITM_DMA_EN_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Enable DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_EN_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_EN_CLR_CHAN 0 /* Disable DMA Channels */ +#define BITM_DMA_EN_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Disable DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ALT_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ALT_SET_CHAN 0 /* Control Structure Status / Select Alternate Structure */ +#define BITM_DMA_ALT_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Control Structure Status / Select Alternate Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ALT_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ALT_CLR_CHAN 0 /* Select Primary Data Structure */ +#define BITM_DMA_ALT_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Select Primary Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PRI_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PRI_SET_CHAN 0 /* Configure Channel for High Priority */ +#define BITM_DMA_PRI_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Configure Channel for High Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PRI_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PRI_CLR_CHPRICLR 0 /* Configure Channel for Default Priority Level */ +#define BITM_DMA_PRI_CLR_CHPRICLR (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Configure Channel for Default Priority Level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ERRCHNL_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ERRCHNL_CLR_CHAN 0 /* Per Channel Bus Error Status/Clear */ +#define BITM_DMA_ERRCHNL_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Per Channel Bus Error Status/Clear */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ERR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ERR_CLR_CHAN 0 /* Bus Error Status */ +#define BITM_DMA_ERR_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Bus Error Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_INVALIDDESC_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_INVALIDDESC_CLR_CHAN 0 /* Per Channel Invalid Descriptor Status/Clear */ +#define BITM_DMA_INVALIDDESC_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Per Channel Invalid Descriptor Status/Clear */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_BS_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_BS_SET_CHAN 0 /* Byte Swap Status */ +#define BITM_DMA_BS_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Byte Swap Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_BS_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_BS_CLR_CHAN 0 /* Disable Byte Swap */ +#define BITM_DMA_BS_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Disable Byte Swap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SRCADDR_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SRCADDR_SET_CHAN 0 /* Source Address Decrement Status */ +#define BITM_DMA_SRCADDR_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Source Address Decrement Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SRCADDR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SRCADDR_CLR_CHAN 0 /* Disable Source Address Decrement */ +#define BITM_DMA_SRCADDR_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Disable Source Address Decrement */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_DSTADDR_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_DSTADDR_SET_CHAN 0 /* Destination Address Decrement Status */ +#define BITM_DMA_DSTADDR_SET_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Destination Address Decrement Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_DSTADDR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_DSTADDR_CLR_CHAN 0 /* Disable Destination Address Decrement */ +#define BITM_DMA_DSTADDR_CLR_CHAN (_ADI_MSK_3(0x01FFFFFF,0x01FFFFFFUL, uint32_t )) /* Disable Destination Address Decrement */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_REVID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_REVID_VALUE 0 /* DMA Controller Revision ID */ +#define BITM_DMA_REVID_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* DMA Controller Revision ID */ + + +/* ============================================================================================================================ + Flash Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + FLCC0 + ============================================================================================================================ */ +#define REG_FLCC0_STAT 0x40018000 /* FLCC0 Status */ +#define REG_FLCC0_IEN 0x40018004 /* FLCC0 Interrupt Enable */ +#define REG_FLCC0_CMD 0x40018008 /* FLCC0 Command */ +#define REG_FLCC0_KH_ADDR 0x4001800C /* FLCC0 Write Address */ +#define REG_FLCC0_KH_DATA0 0x40018010 /* FLCC0 Write Lower Data */ +#define REG_FLCC0_KH_DATA1 0x40018014 /* FLCC0 Write Upper Data */ +#define REG_FLCC0_PAGE_ADDR0 0x40018018 /* FLCC0 Lower Page Address */ +#define REG_FLCC0_PAGE_ADDR1 0x4001801C /* FLCC0 Upper Page Address */ +#define REG_FLCC0_KEY 0x40018020 /* FLCC0 Key */ +#define REG_FLCC0_WR_ABORT_ADDR 0x40018024 /* FLCC0 Write Abort Address */ +#define REG_FLCC0_WRPROT 0x40018028 /* FLCC0 Write Protection */ +#define REG_FLCC0_SIGNATURE 0x4001802C /* FLCC0 Signature */ +#define REG_FLCC0_UCFG 0x40018030 /* FLCC0 User Configuration */ +#define REG_FLCC0_TIME_PARAM0 0x40018034 /* FLCC0 Time Parameter 0 */ +#define REG_FLCC0_TIME_PARAM1 0x40018038 /* FLCC0 Time Parameter 1 */ +#define REG_FLCC0_ABORT_EN_LO 0x4001803C /* FLCC0 IRQ Abort Enable (Lower Bits) */ +#define REG_FLCC0_ABORT_EN_HI 0x40018040 /* FLCC0 IRQ Abort Enable (Upper Bits) */ +#define REG_FLCC0_ECC_CFG 0x40018044 /* FLCC0 ECC Configuration */ +#define REG_FLCC0_ECC_ADDR 0x40018048 /* FLCC0 ECC Status (Address) */ +#define REG_FLCC0_POR_SEC 0x40018050 /* FLCC0 Flash Security */ +#define REG_FLCC0_VOL_CFG 0x40018054 /* FLCC0 Volatile Flash Configuration */ + +/* ============================================================================================================================ + FLCC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_STAT_CACHESRAMPERR 29 /* SRAM Parity Errors in Cache Controller */ +#define BITP_FLCC_STAT_ECCDCODE 27 /* DCode AHB Bus Error ECC Status */ +#define BITP_FLCC_STAT_ECCICODE 25 /* ICode AHB Bus Error ECC Status */ +#define BITP_FLCC_STAT_ECCERRCNT 17 /* ECC Correction Counter */ +#define BITP_FLCC_STAT_ECCINFOSIGN 15 /* ECC Status of Flash Initialization */ +#define BITP_FLCC_STAT_INIT 14 /* Flash Controller Initialization in Progress */ +#define BITP_FLCC_STAT_SIGNERR 13 /* Signature Check Failure During Initialization */ +#define BITP_FLCC_STAT_OVERLAP 11 /* Overlapping Command */ +#define BITP_FLCC_STAT_ECCRDERR 9 /* ECC IRQ Cause */ +#define BITP_FLCC_STAT_ECCERRCMD 7 /* ECC Errors Detected During User Issued SIGN Command */ +#define BITP_FLCC_STAT_SLEEPING 6 /* Flash Array is in Low Power (Sleep) Mode */ +#define BITP_FLCC_STAT_CMDFAIL 4 /* Provides Information on Command Failures */ +#define BITP_FLCC_STAT_WRALCOMP 3 /* Write Almost Complete */ +#define BITP_FLCC_STAT_CMDCOMP 2 /* Command Complete */ +#define BITP_FLCC_STAT_WRCLOSE 1 /* WRITE Registers are Closed */ +#define BITP_FLCC_STAT_CMDBUSY 0 /* Command Busy */ +#define BITM_FLCC_STAT_CACHESRAMPERR (_ADI_MSK_3(0x20000000,0x20000000UL, uint32_t )) /* SRAM Parity Errors in Cache Controller */ +#define BITM_FLCC_STAT_ECCDCODE (_ADI_MSK_3(0x18000000,0x18000000UL, uint32_t )) /* DCode AHB Bus Error ECC Status */ +#define BITM_FLCC_STAT_ECCICODE (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t )) /* ICode AHB Bus Error ECC Status */ +#define BITM_FLCC_STAT_ECCERRCNT (_ADI_MSK_3(0x000E0000,0x000E0000UL, uint32_t )) /* ECC Correction Counter */ +#define BITM_FLCC_STAT_ECCINFOSIGN (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t )) /* ECC Status of Flash Initialization */ +#define BITM_FLCC_STAT_INIT (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Flash Controller Initialization in Progress */ +#define BITM_FLCC_STAT_SIGNERR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Signature Check Failure During Initialization */ +#define BITM_FLCC_STAT_OVERLAP (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Overlapping Command */ +#define BITM_FLCC_STAT_ECCRDERR (_ADI_MSK_3(0x00000600,0x00000600UL, uint32_t )) /* ECC IRQ Cause */ +#define BITM_FLCC_STAT_ECCERRCMD (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* ECC Errors Detected During User Issued SIGN Command */ +#define BITM_FLCC_STAT_SLEEPING (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Flash Array is in Low Power (Sleep) Mode */ +#define BITM_FLCC_STAT_CMDFAIL (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Provides Information on Command Failures */ +#define BITM_FLCC_STAT_WRALCOMP (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Write Almost Complete */ +#define BITM_FLCC_STAT_CMDCOMP (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Command Complete */ +#define BITM_FLCC_STAT_WRCLOSE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* WRITE Registers are Closed */ +#define BITM_FLCC_STAT_CMDBUSY (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Command Busy */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_IEN_ECC_ERROR 6 /* Control 2-bit ECC Error Events */ +#define BITP_FLCC_IEN_CMDFAIL 2 /* Command Fail Interrupt Enable */ +#define BITP_FLCC_IEN_WRALCMPLT 1 /* Write Almost Complete Interrupt Enable */ +#define BITP_FLCC_IEN_CMDCMPLT 0 /* Command Complete Interrupt Enable */ +#define BITM_FLCC_IEN_ECC_ERROR (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* Control 2-bit ECC Error Events */ +#define BITM_FLCC_IEN_CMDFAIL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Command Fail Interrupt Enable */ +#define BITM_FLCC_IEN_WRALCMPLT (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Write Almost Complete Interrupt Enable */ +#define BITM_FLCC_IEN_CMDCMPLT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Command Complete Interrupt Enable */ +#define ENUM_FLCC_IEN_NONE_ERR (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ECC_ERROR: Do not generate a response to ECC events */ +#define ENUM_FLCC_IEN_BUS_ERR_ERR (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* ECC_ERROR: Generate Bus Errors in response to ECC events */ +#define ENUM_FLCC_IEN_IRQ_ERR (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* ECC_ERROR: Generate IRQs in response to ECC events */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CMD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CMD_VALUE 0 /* Commands */ +#define BITM_FLCC_CMD_VALUE (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Commands */ +#define ENUM_FLCC_CMD_IDLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VALUE: IDLE */ +#define ENUM_FLCC_CMD_ABORT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* VALUE: ABORT */ +#define ENUM_FLCC_CMD_SLEEP (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* VALUE: Requests flash to enter Sleep mode */ +#define ENUM_FLCC_CMD_SIGN (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* VALUE: SIGN */ +#define ENUM_FLCC_CMD_WRITE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* VALUE: WRITE */ +#define ENUM_FLCC_CMD_BLANK_CHECK (_ADI_MSK_3(0x00000005,0x00000005UL, uint32_t )) /* VALUE: Checks all of User Space; fails if any bits in user space are cleared */ +#define ENUM_FLCC_CMD_ERASEPAGE (_ADI_MSK_3(0x00000006,0x00000006UL, uint32_t )) /* VALUE: ERASEPAGE */ +#define ENUM_FLCC_CMD_MASSERASE (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t )) /* VALUE: MASSERASE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_ADDR_VALUE 3 /* Key Hole Address */ +#define BITM_FLCC_KH_ADDR_VALUE (_ADI_MSK_3(0x0007FFF8,0x0007FFF8UL, uint32_t )) /* Key Hole Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_DATA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_DATA0_VALUE 0 /* Lower 32 Bits of Key Hole Data */ +#define BITM_FLCC_KH_DATA0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Lower 32 Bits of Key Hole Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_DATA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_DATA1_VALUE 0 /* Upper Half of 64-bit Dualword Data to Be Written */ +#define BITM_FLCC_KH_DATA1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Upper Half of 64-bit Dualword Data to Be Written */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_PAGE_ADDR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_PAGE_ADDR0_VALUE 10 /* Lower Address Bits of the Page Address */ +#define BITM_FLCC_PAGE_ADDR0_VALUE (_ADI_MSK_3(0x0007FC00,0x0007FC00UL, uint32_t )) /* Lower Address Bits of the Page Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_PAGE_ADDR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_PAGE_ADDR1_VALUE 10 /* Upper Address Bits of the Page Address */ +#define BITM_FLCC_PAGE_ADDR1_VALUE (_ADI_MSK_3(0x0007FC00,0x0007FC00UL, uint32_t )) /* Upper Address Bits of the Page Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KEY_VALUE 0 /* Key Register */ +#define BITM_FLCC_KEY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key Register */ +#define ENUM_FLCC_KEY_USERKEY (_ADI_MSK_3(0x676C7565,0x676C7565UL, uint32_t )) /* VALUE: USERKEY */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_WR_ABORT_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_WR_ABORT_ADDR_VALUE 0 /* Address Targeted by an Ongoing Write Command */ +#define BITM_FLCC_WR_ABORT_ADDR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Address Targeted by an Ongoing Write Command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_WRPROT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_WRPROT_WORD 0 /* Write Protect */ +#define BITM_FLCC_WRPROT_WORD (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Write Protect */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_SIGNATURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_SIGNATURE_VALUE 0 /* Signature */ +#define BITM_FLCC_SIGNATURE_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Signature */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_UCFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_UCFG_AUTOINCEN 1 /* Auto Address Increment for Key Hole Access */ +#define BITP_FLCC_UCFG_KHDMAEN 0 /* Key Hole DMA Enable */ +#define BITM_FLCC_UCFG_AUTOINCEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Auto Address Increment for Key Hole Access */ +#define BITM_FLCC_UCFG_KHDMAEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Key Hole DMA Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_TIME_PARAM0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_TIME_PARAM0_TNVH1 28 /* NVSTR Hold Time During Mass Erase */ +#define BITP_FLCC_TIME_PARAM0_TERASE 24 /* Erase Time */ +#define BITP_FLCC_TIME_PARAM0_TRCV 20 /* Recovery Time */ +#define BITP_FLCC_TIME_PARAM0_TNVH 16 /* NVSTR Hold Time */ +#define BITP_FLCC_TIME_PARAM0_TPROG 12 /* Program Time */ +#define BITP_FLCC_TIME_PARAM0_TPGS 8 /* NVSTR to Program Setup Time */ +#define BITP_FLCC_TIME_PARAM0_TNVS 4 /* PROG/ERASE to NVSTR Setup Time */ +#define BITP_FLCC_TIME_PARAM0_DIVREFCLK 0 /* Divide Reference Clock (by 2) */ +#define BITM_FLCC_TIME_PARAM0_TNVH1 (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* NVSTR Hold Time During Mass Erase */ +#define BITM_FLCC_TIME_PARAM0_TERASE (_ADI_MSK_3(0x0F000000,0x0F000000UL, uint32_t )) /* Erase Time */ +#define BITM_FLCC_TIME_PARAM0_TRCV (_ADI_MSK_3(0x00F00000,0x00F00000UL, uint32_t )) /* Recovery Time */ +#define BITM_FLCC_TIME_PARAM0_TNVH (_ADI_MSK_3(0x000F0000,0x000F0000UL, uint32_t )) /* NVSTR Hold Time */ +#define BITM_FLCC_TIME_PARAM0_TPROG (_ADI_MSK_3(0x0000F000,0x0000F000UL, uint32_t )) /* Program Time */ +#define BITM_FLCC_TIME_PARAM0_TPGS (_ADI_MSK_3(0x00000F00,0x00000F00UL, uint32_t )) /* NVSTR to Program Setup Time */ +#define BITM_FLCC_TIME_PARAM0_TNVS (_ADI_MSK_3(0x000000F0,0x000000F0UL, uint32_t )) /* PROG/ERASE to NVSTR Setup Time */ +#define BITM_FLCC_TIME_PARAM0_DIVREFCLK (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Divide Reference Clock (by 2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_TIME_PARAM1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_TIME_PARAM1_TWK 0 /* Wakeup Time */ +#define BITM_FLCC_TIME_PARAM1_TWK (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Wakeup Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ABORT_EN_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ABORT_EN_LO_VALUE 0 /* Sys IRQ Abort Enable */ +#define BITM_FLCC_ABORT_EN_LO_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Sys IRQ Abort Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ABORT_EN_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ABORT_EN_HI_VALUE 0 /* Sys IRQ Abort Enable */ +#define BITM_FLCC_ABORT_EN_HI_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Sys IRQ Abort Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ECC_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ECC_CFG_PTR 8 /* ECC Start Page Pointer */ +#define BITP_FLCC_ECC_CFG_INFOEN 1 /* Info Space ECC Enable Bit */ +#define BITP_FLCC_ECC_CFG_EN 0 /* ECC Enable */ +#define BITM_FLCC_ECC_CFG_PTR (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t )) /* ECC Start Page Pointer */ +#define BITM_FLCC_ECC_CFG_INFOEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Info Space ECC Enable Bit */ +#define BITM_FLCC_ECC_CFG_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* ECC Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ECC_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ECC_ADDR_VALUE 0 /* ECC Error Address */ +#define BITM_FLCC_ECC_ADDR_VALUE (_ADI_MSK_3(0x0007FFFF,0x0007FFFFUL, uint32_t )) /* ECC Error Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_POR_SEC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_POR_SEC_SECURE 0 /* Prevent Read/Write Access to User Space (Sticky When Set) */ +#define BITM_FLCC_POR_SEC_SECURE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Prevent Read/Write Access to User Space (Sticky When Set) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_VOL_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_VOL_CFG_INFO_REMAP 0 /* Alias the Info Space to the Base Address of User Space */ +#define BITM_FLCC_VOL_CFG_INFO_REMAP (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Alias the Info Space to the Base Address of User Space */ + + +/* ============================================================================================================================ + Cache Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + FLCC0_CACHE + ============================================================================================================================ */ +#define REG_FLCC0_CACHE_STAT 0x40018058 /* FLCC0_CACHE Cache Status */ +#define REG_FLCC0_CACHE_SETUP 0x4001805C /* FLCC0_CACHE Cache Setup */ +#define REG_FLCC0_CACHE_KEY 0x40018060 /* FLCC0_CACHE Cache Key */ + +/* ============================================================================================================================ + FLCC_CACHE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_STAT_ICEN 0 /* I-Cache Enabled */ +#define BITM_FLCC_CACHE_STAT_ICEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* I-Cache Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_SETUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_SETUP_ICEN 0 /* I-Cache Enable */ +#define BITM_FLCC_CACHE_SETUP_ICEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* I-Cache Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_KEY_VALUE 0 /* Cache Key Register */ +#define BITM_FLCC_CACHE_KEY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Cache Key Register */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + GPIO0 + ============================================================================================================================ */ +#define REG_GPIO0_CFG 0x40020000 /* GPIO0 Port Configuration */ +#define REG_GPIO0_OEN 0x40020004 /* GPIO0 Port Output Enable */ +#define REG_GPIO0_PE 0x40020008 /* GPIO0 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO0_IEN 0x4002000C /* GPIO0 Port Input Path Enable */ +#define REG_GPIO0_IN 0x40020010 /* GPIO0 Port Registered Data Input */ +#define REG_GPIO0_OUT 0x40020014 /* GPIO0 Port Data Output */ +#define REG_GPIO0_SET 0x40020018 /* GPIO0 Port Data Out Set */ +#define REG_GPIO0_CLR 0x4002001C /* GPIO0 Port Data Out Clear */ +#define REG_GPIO0_TGL 0x40020020 /* GPIO0 Port Pin Toggle */ +#define REG_GPIO0_POL 0x40020024 /* GPIO0 Port Interrupt Polarity */ +#define REG_GPIO0_IENA 0x40020028 /* GPIO0 Port Interrupt A Enable */ +#define REG_GPIO0_IENB 0x4002002C /* GPIO0 Port Interrupt B Enable */ +#define REG_GPIO0_INT 0x40020030 /* GPIO0 Port Interrupt Status */ +#define REG_GPIO0_DS 0x40020034 /* GPIO0 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO1 + ============================================================================================================================ */ +#define REG_GPIO1_CFG 0x40020040 /* GPIO1 Port Configuration */ +#define REG_GPIO1_OEN 0x40020044 /* GPIO1 Port Output Enable */ +#define REG_GPIO1_PE 0x40020048 /* GPIO1 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO1_IEN 0x4002004C /* GPIO1 Port Input Path Enable */ +#define REG_GPIO1_IN 0x40020050 /* GPIO1 Port Registered Data Input */ +#define REG_GPIO1_OUT 0x40020054 /* GPIO1 Port Data Output */ +#define REG_GPIO1_SET 0x40020058 /* GPIO1 Port Data Out Set */ +#define REG_GPIO1_CLR 0x4002005C /* GPIO1 Port Data Out Clear */ +#define REG_GPIO1_TGL 0x40020060 /* GPIO1 Port Pin Toggle */ +#define REG_GPIO1_POL 0x40020064 /* GPIO1 Port Interrupt Polarity */ +#define REG_GPIO1_IENA 0x40020068 /* GPIO1 Port Interrupt A Enable */ +#define REG_GPIO1_IENB 0x4002006C /* GPIO1 Port Interrupt B Enable */ +#define REG_GPIO1_INT 0x40020070 /* GPIO1 Port Interrupt Status */ +#define REG_GPIO1_DS 0x40020074 /* GPIO1 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO2 + ============================================================================================================================ */ +#define REG_GPIO2_CFG 0x40020080 /* GPIO2 Port Configuration */ +#define REG_GPIO2_OEN 0x40020084 /* GPIO2 Port Output Enable */ +#define REG_GPIO2_PE 0x40020088 /* GPIO2 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO2_IEN 0x4002008C /* GPIO2 Port Input Path Enable */ +#define REG_GPIO2_IN 0x40020090 /* GPIO2 Port Registered Data Input */ +#define REG_GPIO2_OUT 0x40020094 /* GPIO2 Port Data Output */ +#define REG_GPIO2_SET 0x40020098 /* GPIO2 Port Data Out Set */ +#define REG_GPIO2_CLR 0x4002009C /* GPIO2 Port Data Out Clear */ +#define REG_GPIO2_TGL 0x400200A0 /* GPIO2 Port Pin Toggle */ +#define REG_GPIO2_POL 0x400200A4 /* GPIO2 Port Interrupt Polarity */ +#define REG_GPIO2_IENA 0x400200A8 /* GPIO2 Port Interrupt A Enable */ +#define REG_GPIO2_IENB 0x400200AC /* GPIO2 Port Interrupt B Enable */ +#define REG_GPIO2_INT 0x400200B0 /* GPIO2 Port Interrupt Status */ +#define REG_GPIO2_DS 0x400200B4 /* GPIO2 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_CFG_PIN15 30 /* Pin 15 Configuration Bits */ +#define BITP_GPIO_CFG_PIN14 28 /* Pin 14 Configuration Bits */ +#define BITP_GPIO_CFG_PIN13 26 /* Pin 13 Configuration Bits */ +#define BITP_GPIO_CFG_PIN12 24 /* Pin 12 Configuration Bits */ +#define BITP_GPIO_CFG_PIN11 22 /* Pin 11 Configuration Bits */ +#define BITP_GPIO_CFG_PIN10 20 /* Pin 10 Configuration Bits */ +#define BITP_GPIO_CFG_PIN09 18 /* Pin 9 Configuration Bits */ +#define BITP_GPIO_CFG_PIN08 16 /* Pin 8 Configuration Bits */ +#define BITP_GPIO_CFG_PIN07 14 /* Pin 7 Configuration Bits */ +#define BITP_GPIO_CFG_PIN06 12 /* Pin 6 Configuration Bits */ +#define BITP_GPIO_CFG_PIN05 10 /* Pin 5 Configuration Bits */ +#define BITP_GPIO_CFG_PIN04 8 /* Pin 4 Configuration Bits */ +#define BITP_GPIO_CFG_PIN03 6 /* Pin 3 Configuration Bits */ +#define BITP_GPIO_CFG_PIN02 4 /* Pin 2 Configuration Bits */ +#define BITP_GPIO_CFG_PIN01 2 /* Pin 1 Configuration Bits */ +#define BITP_GPIO_CFG_PIN00 0 /* Pin 0 Configuration Bits */ +#define BITM_GPIO_CFG_PIN15 (_ADI_MSK_3(0xC0000000,0xC0000000UL, uint32_t )) /* Pin 15 Configuration Bits */ +#define BITM_GPIO_CFG_PIN14 (_ADI_MSK_3(0x30000000,0x30000000UL, uint32_t )) /* Pin 14 Configuration Bits */ +#define BITM_GPIO_CFG_PIN13 (_ADI_MSK_3(0x0C000000,0x0C000000UL, uint32_t )) /* Pin 13 Configuration Bits */ +#define BITM_GPIO_CFG_PIN12 (_ADI_MSK_3(0x03000000,0x03000000UL, uint32_t )) /* Pin 12 Configuration Bits */ +#define BITM_GPIO_CFG_PIN11 (_ADI_MSK_3(0x00C00000,0x00C00000UL, uint32_t )) /* Pin 11 Configuration Bits */ +#define BITM_GPIO_CFG_PIN10 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* Pin 10 Configuration Bits */ +#define BITM_GPIO_CFG_PIN09 (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Pin 9 Configuration Bits */ +#define BITM_GPIO_CFG_PIN08 (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* Pin 8 Configuration Bits */ +#define BITM_GPIO_CFG_PIN07 (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t )) /* Pin 7 Configuration Bits */ +#define BITM_GPIO_CFG_PIN06 (_ADI_MSK_3(0x00003000,0x00003000UL, uint32_t )) /* Pin 6 Configuration Bits */ +#define BITM_GPIO_CFG_PIN05 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* Pin 5 Configuration Bits */ +#define BITM_GPIO_CFG_PIN04 (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Pin 4 Configuration Bits */ +#define BITM_GPIO_CFG_PIN03 (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* Pin 3 Configuration Bits */ +#define BITM_GPIO_CFG_PIN02 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Pin 2 Configuration Bits */ +#define BITM_GPIO_CFG_PIN01 (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* Pin 1 Configuration Bits */ +#define BITM_GPIO_CFG_PIN00 (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Pin 0 Configuration Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_OEN_VALUE 0 /* Pin Output Drive Enable */ +#define BITM_GPIO_OEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Pin Output Drive Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_PE_VALUE 0 /* Pin Pull Enable */ +#define BITM_GPIO_PE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Pin Pull Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IEN_VALUE 0 /* Input Path Enable */ +#define BITM_GPIO_IEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Input Path Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IN_VALUE 0 /* Registered Data Input */ +#define BITM_GPIO_IN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Registered Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_OUT_VALUE 0 /* Data Out */ +#define BITM_GPIO_OUT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Data Out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_SET_VALUE 0 /* Set the Output High for the Pin */ +#define BITM_GPIO_SET_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Set the Output High for the Pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_CLR_VALUE 0 /* Set the Output Low for the Port Pin */ +#define BITM_GPIO_CLR_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Set the Output Low for the Port Pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_TGL_VALUE 0 /* Toggle the Output of the Port Pin */ +#define BITM_GPIO_TGL_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Toggle the Output of the Port Pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_POL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_POL_VALUE 0 /* Interrupt polarity */ +#define BITM_GPIO_POL_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt polarity */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IENA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IENA_VALUE 0 /* Interrupt A enable */ +#define BITM_GPIO_IENA_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt A enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IENB Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IENB_VALUE 0 /* Interrupt B enable */ +#define BITM_GPIO_IENB_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt B enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_INT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_INT_VALUE 0 /* Interrupt Status */ +#define BITM_GPIO_INT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_DS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_DS_VALUE 0 /* Drive Strength Select */ +#define BITM_GPIO_DS_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Drive Strength Select */ + + +/* ============================================================================================================================ + Serial Port + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPORT0 + ============================================================================================================================ */ +#define REG_SPORT0_CTL_A 0x40038000 /* SPORT0 Half SPORT 'A' Control */ +#define REG_SPORT0_DIV_A 0x40038004 /* SPORT0 Half SPORT 'A' Divisor */ +#define REG_SPORT0_IEN_A 0x40038008 /* SPORT0 Half SPORT A's Interrupt Enable */ +#define REG_SPORT0_STAT_A 0x4003800C /* SPORT0 Half SPORT A's Status */ +#define REG_SPORT0_NUMTRAN_A 0x40038010 /* SPORT0 Half SPORT A Number of Transfers */ +#define REG_SPORT0_CNVT_A 0x40038014 /* SPORT0 Half SPORT 'A' CNV Width */ +#define REG_SPORT0_TX_A 0x40038020 /* SPORT0 Half SPORT 'A' Tx Buffer */ +#define REG_SPORT0_RX_A 0x40038028 /* SPORT0 Half SPORT 'A' Rx Buffer */ +#define REG_SPORT0_CTL_B 0x40038040 /* SPORT0 Half SPORT 'B' Control */ +#define REG_SPORT0_DIV_B 0x40038044 /* SPORT0 Half SPORT 'B' Divisor */ +#define REG_SPORT0_IEN_B 0x40038048 /* SPORT0 Half SPORT B's Interrupt Enable */ +#define REG_SPORT0_STAT_B 0x4003804C /* SPORT0 Half SPORT B's Status */ +#define REG_SPORT0_NUMTRAN_B 0x40038050 /* SPORT0 Half SPORT B Number of Transfers */ +#define REG_SPORT0_CNVT_B 0x40038054 /* SPORT0 Half SPORT 'B' CNV Width */ +#define REG_SPORT0_TX_B 0x40038060 /* SPORT0 Half SPORT 'B' Tx Buffer */ +#define REG_SPORT0_RX_B 0x40038068 /* SPORT0 Half SPORT 'B' Rx Buffer */ + +/* ============================================================================================================================ + SPORT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CTL_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CTL_A_DMAEN 26 /* DMA Enable */ +#define BITP_SPORT_CTL_A_SPTRAN 25 /* Serial Port Transfer Direction */ +#define BITP_SPORT_CTL_A_GCLKEN 21 /* Gated Clock Enable */ +#define BITP_SPORT_CTL_A_FSERRMODE 20 /* Frame Sync Error Operation */ +#define BITP_SPORT_CTL_A_PACK 18 /* Packing Enable */ +#define BITP_SPORT_CTL_A_LAFS 17 /* Late Frame Sync */ +#define BITP_SPORT_CTL_A_LFS 16 /* Active-Low Frame Sync */ +#define BITP_SPORT_CTL_A_DIFS 15 /* Data-Independent Frame Sync */ +#define BITP_SPORT_CTL_A_IFS 14 /* Internal Frame Sync */ +#define BITP_SPORT_CTL_A_FSR 13 /* Frame Sync Required */ +#define BITP_SPORT_CTL_A_CKRE 12 /* Clock Rising Edge */ +#define BITP_SPORT_CTL_A_OPMODE 11 /* Operation Mode */ +#define BITP_SPORT_CTL_A_ICLK 10 /* Internal Clock */ +#define BITP_SPORT_CTL_A_SLEN 4 /* Serial Word Length */ +#define BITP_SPORT_CTL_A_LSBF 3 /* Least-Significant Bit First */ +#define BITP_SPORT_CTL_A_CKMUXSEL 2 /* Clock Multiplexer Select */ +#define BITP_SPORT_CTL_A_FSMUXSEL 1 /* Frame Sync Multiplexer Select */ +#define BITP_SPORT_CTL_A_SPEN 0 /* Serial Port Enable */ +#define BITM_SPORT_CTL_A_DMAEN (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* DMA Enable */ +#define BITM_SPORT_CTL_A_SPTRAN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Serial Port Transfer Direction */ +#define BITM_SPORT_CTL_A_GCLKEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Gated Clock Enable */ +#define BITM_SPORT_CTL_A_FSERRMODE (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Frame Sync Error Operation */ +#define BITM_SPORT_CTL_A_PACK (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Packing Enable */ +#define BITM_SPORT_CTL_A_LAFS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Late Frame Sync */ +#define BITM_SPORT_CTL_A_LFS (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Active-Low Frame Sync */ +#define BITM_SPORT_CTL_A_DIFS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Data-Independent Frame Sync */ +#define BITM_SPORT_CTL_A_IFS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Internal Frame Sync */ +#define BITM_SPORT_CTL_A_FSR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Frame Sync Required */ +#define BITM_SPORT_CTL_A_CKRE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Clock Rising Edge */ +#define BITM_SPORT_CTL_A_OPMODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Operation Mode */ +#define BITM_SPORT_CTL_A_ICLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Internal Clock */ +#define BITM_SPORT_CTL_A_SLEN (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t )) /* Serial Word Length */ +#define BITM_SPORT_CTL_A_LSBF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Least-Significant Bit First */ +#define BITM_SPORT_CTL_A_CKMUXSEL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Clock Multiplexer Select */ +#define BITM_SPORT_CTL_A_FSMUXSEL (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Frame Sync Multiplexer Select */ +#define BITM_SPORT_CTL_A_SPEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Serial Port Enable */ +#define ENUM_SPORT_CTL_A_CTL_RX (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* SPTRAN: Receive */ +#define ENUM_SPORT_CTL_A_CTL_TX (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* SPTRAN: Transmit */ +#define ENUM_SPORT_CTL_A_CTL_GCLK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* GCLKEN: Disable */ +#define ENUM_SPORT_CTL_A_CTL_GCLK_EN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* GCLKEN: Enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PACK: Disable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_8BIT (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* PACK: 8-bit packing enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_16BIT (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* PACK: 16-bit packing enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_RSV (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* PACK: Reserved */ +#define ENUM_SPORT_CTL_A_CTL_EARLY_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LAFS: Early frame sync */ +#define ENUM_SPORT_CTL_A_CTL_LATE_FS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* LAFS: Late frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_LO (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LFS: Active high frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_HI (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* LFS: Active low frame sync */ +#define ENUM_SPORT_CTL_A_CTL_DATA_DEP_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DIFS: Data-dependent frame sync */ +#define ENUM_SPORT_CTL_A_CTL_DATA_INDP_FS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* DIFS: Data-independent frame sync */ +#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* IFS: External frame sync */ +#define ENUM_SPORT_CTL_A_CTL_INTERNAL_FS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* IFS: Internal frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_NOT_REQ (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* FSR: No frame sync required */ +#define ENUM_SPORT_CTL_A_CTL_FS_REQ (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* FSR: Frame sync required */ +#define ENUM_SPORT_CTL_A_CTL_CLK_FALL_EDGE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CKRE: Clock falling edge */ +#define ENUM_SPORT_CTL_A_CTL_CLK_RISE_EDGE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* CKRE: Clock rising edge */ +#define ENUM_SPORT_CTL_A_CTL_SERIAL (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* OPMODE: DSP standard */ +#define ENUM_SPORT_CTL_A_CTL_TIMER_EN_MODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* OPMODE: Timer_enable mode */ +#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_CLK (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ICLK: External clock */ +#define ENUM_SPORT_CTL_A_CTL_INTERNAL_CLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* ICLK: Internal clock */ +#define ENUM_SPORT_CTL_A_CTL_MSB_FIRST (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LSBF: MSB first sent/received */ +#define ENUM_SPORT_CTL_A_CTL_LSB_FIRST (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* LSBF: LSB first sent/received */ +#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CKMUXSEL: Disable serial clock multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* CKMUXSEL: Enable serial clock multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_FS_MUX_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* FSMUXSEL: Disable frame sync multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_FS_MUX_EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* FSMUXSEL: Enable frame sync multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* SPEN: Disable */ +#define ENUM_SPORT_CTL_A_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* SPEN: Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_DIV_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_DIV_A_FSDIV 16 /* Frame Sync Divisor */ +#define BITP_SPORT_DIV_A_CLKDIV 0 /* Clock Divisor */ +#define BITM_SPORT_DIV_A_FSDIV (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* Frame Sync Divisor */ +#define BITM_SPORT_DIV_A_CLKDIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Clock Divisor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_IEN_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_IEN_A_SYSDATERR 4 /* Data Error for System Writes or Reads */ +#define BITP_SPORT_IEN_A_DATA 3 /* Data Request Interrupt to the Core */ +#define BITP_SPORT_IEN_A_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_A_DERRMSK 1 /* Data Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_A_TF 0 /* Transfer Finish Interrupt Enable */ +#define BITM_SPORT_IEN_A_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Data Error for System Writes or Reads */ +#define BITM_SPORT_IEN_A_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Request Interrupt to the Core */ +#define BITM_SPORT_IEN_A_FSERRMSK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_A_DERRMSK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_A_TF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transfer Finish Interrupt Enable */ +#define ENUM_SPORT_IEN_A_CTL_TXFIN_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TF: Transfer finish Interrupt is disabled */ +#define ENUM_SPORT_IEN_A_CTL_TXFIN_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TF: Transfer Finish Interrupt is Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_STAT_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_STAT_A_DXS 8 /* Data Transfer Buffer Status */ +#define BITP_SPORT_STAT_A_SYSDATERR 4 /* System Data Error Status */ +#define BITP_SPORT_STAT_A_DATA 3 /* Data Buffer Status */ +#define BITP_SPORT_STAT_A_FSERR 2 /* Frame Sync Error Status */ +#define BITP_SPORT_STAT_A_DERR 1 /* Data Error Status */ +#define BITP_SPORT_STAT_A_TFI 0 /* Transmit Finish Interrupt Status */ +#define BITM_SPORT_STAT_A_DXS (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Data Transfer Buffer Status */ +#define BITM_SPORT_STAT_A_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* System Data Error Status */ +#define BITM_SPORT_STAT_A_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Buffer Status */ +#define BITM_SPORT_STAT_A_FSERR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error Status */ +#define BITM_SPORT_STAT_A_DERR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error Status */ +#define BITM_SPORT_STAT_A_TFI (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Status */ +#define ENUM_SPORT_STAT_A_CTL_EMPTY (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DXS: Empty */ +#define ENUM_SPORT_STAT_A_CTL_RSV (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* DXS: Reserved */ +#define ENUM_SPORT_STAT_A_CTL_PART_FULL (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* DXS: Partially full */ +#define ENUM_SPORT_STAT_A_CTL_FULL (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* DXS: Full */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_NUMTRAN_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_NUMTRAN_A_VALUE 0 /* Number of Transfers (Half SPORT A) */ +#define BITM_SPORT_NUMTRAN_A_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* Number of Transfers (Half SPORT A) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CNVT_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CNVT_A_CNVT2FS 16 /* SPT_CNVT to FS Duration: Half SPORT a */ +#define BITP_SPORT_CNVT_A_POL 8 /* Polarity of the SPT_CNVT Signal */ +#define BITP_SPORT_CNVT_A_WID 0 /* SPT_CNVT Signal Width: Half SPORT a */ +#define BITM_SPORT_CNVT_A_CNVT2FS (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* SPT_CNVT to FS Duration: Half SPORT a */ +#define BITM_SPORT_CNVT_A_POL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Polarity of the SPT_CNVT Signal */ +#define BITM_SPORT_CNVT_A_WID (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* SPT_CNVT Signal Width: Half SPORT a */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_TX_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_TX_A_VALUE 0 /* Transmit Buffer */ +#define BITM_SPORT_TX_A_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_RX_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_RX_A_VALUE 0 /* Receive Buffer */ +#define BITM_SPORT_RX_A_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Receive Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CTL_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CTL_B_DMAEN 26 /* DMA Enable */ +#define BITP_SPORT_CTL_B_SPTRAN 25 /* Serial Port Transfer Direction */ +#define BITP_SPORT_CTL_B_GCLKEN 21 /* Gated Clock Enable */ +#define BITP_SPORT_CTL_B_FSERRMODE 20 /* Frame Sync Error Operation */ +#define BITP_SPORT_CTL_B_PACK 18 /* Packing Enable */ +#define BITP_SPORT_CTL_B_LAFS 17 /* Late Frame Sync */ +#define BITP_SPORT_CTL_B_LFS 16 /* Active-Low Frame Sync */ +#define BITP_SPORT_CTL_B_DIFS 15 /* Data-Independent Frame Sync */ +#define BITP_SPORT_CTL_B_IFS 14 /* Internal Frame Sync */ +#define BITP_SPORT_CTL_B_FSR 13 /* Frame Sync Required */ +#define BITP_SPORT_CTL_B_CKRE 12 /* Clock Rising Edge */ +#define BITP_SPORT_CTL_B_OPMODE 11 /* Operation Mode */ +#define BITP_SPORT_CTL_B_ICLK 10 /* Internal Clock */ +#define BITP_SPORT_CTL_B_SLEN 4 /* Serial Word Length */ +#define BITP_SPORT_CTL_B_LSBF 3 /* Least-Significant Bit First */ +#define BITP_SPORT_CTL_B_SPEN 0 /* Serial Port Enable */ +#define BITM_SPORT_CTL_B_DMAEN (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* DMA Enable */ +#define BITM_SPORT_CTL_B_SPTRAN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Serial Port Transfer Direction */ +#define BITM_SPORT_CTL_B_GCLKEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Gated Clock Enable */ +#define BITM_SPORT_CTL_B_FSERRMODE (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Frame Sync Error Operation */ +#define BITM_SPORT_CTL_B_PACK (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Packing Enable */ +#define BITM_SPORT_CTL_B_LAFS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Late Frame Sync */ +#define BITM_SPORT_CTL_B_LFS (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Active-Low Frame Sync */ +#define BITM_SPORT_CTL_B_DIFS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Data-Independent Frame Sync */ +#define BITM_SPORT_CTL_B_IFS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Internal Frame Sync */ +#define BITM_SPORT_CTL_B_FSR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Frame Sync Required */ +#define BITM_SPORT_CTL_B_CKRE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Clock Rising Edge */ +#define BITM_SPORT_CTL_B_OPMODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Operation Mode */ +#define BITM_SPORT_CTL_B_ICLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Internal Clock */ +#define BITM_SPORT_CTL_B_SLEN (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t )) /* Serial Word Length */ +#define BITM_SPORT_CTL_B_LSBF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Least-Significant Bit First */ +#define BITM_SPORT_CTL_B_SPEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Serial Port Enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PACK: Disable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_8BIT (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* PACK: 8-bit packing enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_16BIT (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* PACK: 16-bit packing enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_RSV (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* PACK: Reserved */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_DIV_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_DIV_B_FSDIV 16 /* Frame Sync Divisor */ +#define BITP_SPORT_DIV_B_CLKDIV 0 /* Clock Divisor */ +#define BITM_SPORT_DIV_B_FSDIV (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* Frame Sync Divisor */ +#define BITM_SPORT_DIV_B_CLKDIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Clock Divisor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_IEN_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_IEN_B_SYSDATERR 4 /* Data Error for System Writes or Reads */ +#define BITP_SPORT_IEN_B_DATA 3 /* Data Request Interrupt to the Core */ +#define BITP_SPORT_IEN_B_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_B_DERRMSK 1 /* Data Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_B_TF 0 /* Transmit Finish Interrupt Enable */ +#define BITM_SPORT_IEN_B_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Data Error for System Writes or Reads */ +#define BITM_SPORT_IEN_B_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Request Interrupt to the Core */ +#define BITM_SPORT_IEN_B_FSERRMSK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_B_DERRMSK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_B_TF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Enable */ +#define ENUM_SPORT_IEN_B_CTL_TXFIN_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TF: Transfer Finish Interrupt is disabled */ +#define ENUM_SPORT_IEN_B_CTL_TXFIN_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TF: Transfer Finish Interrupt is Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_STAT_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_STAT_B_DXS 8 /* Data Transfer Buffer Status */ +#define BITP_SPORT_STAT_B_SYSDATERR 4 /* System Data Error Status */ +#define BITP_SPORT_STAT_B_DATA 3 /* Data Buffer Status */ +#define BITP_SPORT_STAT_B_FSERR 2 /* Frame Sync Error Status */ +#define BITP_SPORT_STAT_B_DERR 1 /* Data Error Status */ +#define BITP_SPORT_STAT_B_TFI 0 /* Transmit Finish Interrupt Status */ +#define BITM_SPORT_STAT_B_DXS (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Data Transfer Buffer Status */ +#define BITM_SPORT_STAT_B_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* System Data Error Status */ +#define BITM_SPORT_STAT_B_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Buffer Status */ +#define BITM_SPORT_STAT_B_FSERR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error Status */ +#define BITM_SPORT_STAT_B_DERR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error Status */ +#define BITM_SPORT_STAT_B_TFI (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Status */ +#define ENUM_SPORT_STAT_B_CTL_EMPTY (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DXS: Empty */ +#define ENUM_SPORT_STAT_B_CTL_RSV (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* DXS: Reserved */ +#define ENUM_SPORT_STAT_B_CTL_PART_FULL (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* DXS: Partially full */ +#define ENUM_SPORT_STAT_B_CTL_FULL (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* DXS: Full */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_NUMTRAN_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_NUMTRAN_B_VALUE 0 /* Number of Transfers (Half SPORT A) */ +#define BITM_SPORT_NUMTRAN_B_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* Number of Transfers (Half SPORT A) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CNVT_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CNVT_B_CNVT2FS 16 /* SPT_CNVT to FS Duration: Half SPORT B */ +#define BITP_SPORT_CNVT_B_POL 8 /* Polarity of the SPT_CNVT Signal */ +#define BITP_SPORT_CNVT_B_WID 0 /* SPT_CNVT Signal Width: Half SPORT B */ +#define BITM_SPORT_CNVT_B_CNVT2FS (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* SPT_CNVT to FS Duration: Half SPORT B */ +#define BITM_SPORT_CNVT_B_POL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Polarity of the SPT_CNVT Signal */ +#define BITM_SPORT_CNVT_B_WID (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* SPT_CNVT Signal Width: Half SPORT B */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_TX_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_TX_B_VALUE 0 /* Transmit Buffer */ +#define BITM_SPORT_TX_B_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_RX_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_RX_B_VALUE 0 /* Receive Buffer */ +#define BITM_SPORT_RX_B_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Receive Buffer */ + + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ */ + +/* ============================================================================================================================ + CRC0 + ============================================================================================================================ */ +#define REG_CRC0_CTL 0x40040000 /* CRC0 CRC Control */ +#define REG_CRC0_IPDATA 0x40040004 /* CRC0 Input Data Word */ +#define REG_CRC0_RESULT 0x40040008 /* CRC0 CRC Result */ +#define REG_CRC0_POLY 0x4004000C /* CRC0 Programmable CRC Polynomial */ +#define REG_CRC0_IPBITS0 0x40040010 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS1 0x40040011 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS2 0x40040012 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS3 0x40040013 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS4 0x40040014 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS5 0x40040015 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS6 0x40040016 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS7 0x40040017 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITSn(i) (REG_CRC0_IPBITS0 + ((i) * 1)) +#define REG_CRC0_IPBITSn_COUNT 8 +#define REG_CRC0_IPBYTE 0x40040010 /* CRC0 Input Data Byte */ + +/* ============================================================================================================================ + CRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_CTL_REVID 28 /* Revision ID */ +#define BITP_CRC_CTL_W16SWP 4 /* Word16 Swap */ +#define BITP_CRC_CTL_BYTMIRR 3 /* Byte Mirroring */ +#define BITP_CRC_CTL_BITMIRR 2 /* Bit Mirroring */ +#define BITP_CRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_CRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_CRC_CTL_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Revision ID */ +#define BITM_CRC_CTL_W16SWP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Word16 Swap */ +#define BITM_CRC_CTL_BYTMIRR (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Byte Mirroring */ +#define BITM_CRC_CTL_BITMIRR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bit Mirroring */ +#define BITM_CRC_CTL_LSBFIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSB First Calculation Order */ +#define BITM_CRC_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Peripheral Enable */ +#define ENUM_CRC_CTL_W16SP_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* W16SWP: Word16 Swap disabled */ +#define ENUM_CRC_CTL_W16SP_EN (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* W16SWP: Word16 Swap enabled */ +#define ENUM_CRC_CTL_BYTEMIR_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BYTMIRR: Byte Mirroring is disabled */ +#define ENUM_CRC_CTL_BYTEMIR_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BYTMIRR: Byte Mirroring is enabled */ +#define ENUM_CRC_CTL_BITMIRR_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BITMIRR: Bit Mirroring is disabled */ +#define ENUM_CRC_CTL_BITMIRR_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* BITMIRR: Bit Mirroring is enabled */ +#define ENUM_CRC_CTL_MSB_FIRST (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LSBFIRST: MSB First CRC calculation is done */ +#define ENUM_CRC_CTL_LSB_FIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSBFIRST: LSB First CRC calculation is done */ +#define ENUM_CRC_CTL_CRC_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* EN: CRC peripheral is disabled */ +#define ENUM_CRC_CTL_CRC_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* EN: CRC peripheral is enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPDATA_VALUE 0 /* Data Input */ +#define BITM_CRC_IPDATA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_CRC_RESULT_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_CRC_POLY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPBITS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPBITS_DATA_BITS 0 /* Input Data Bits */ +#define BITM_CRC_IPBITS_DATA_BITS (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte */ +#define BITM_CRC_IPBYTE_DATA_BYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Byte */ + + +/* ============================================================================================================================ + Random Number Generator + ============================================================================================================================ */ + +/* ============================================================================================================================ + RNG0 + ============================================================================================================================ */ +#define REG_RNG0_CTL 0x40040400 /* RNG0 RNG Control Register */ +#define REG_RNG0_LEN 0x40040404 /* RNG0 RNG Sample Length Register */ +#define REG_RNG0_STAT 0x40040408 /* RNG0 RNG Status Register */ +#define REG_RNG0_DATA 0x4004040C /* RNG0 RNG Data Register */ +#define REG_RNG0_OSCCNT 0x40040410 /* RNG0 Oscillator Count */ +#define REG_RNG0_OSCDIFF0 0x40040414 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF1 0x40040415 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF2 0x40040416 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF3 0x40040417 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFFn(i) (REG_RNG0_OSCDIFF0 + ((i) * 1)) +#define REG_RNG0_OSCDIFFn_COUNT 4 + +/* ============================================================================================================================ + RNG Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_CTL_SINGLE 3 /* Generate a Single Number */ +#define BITP_RNG_CTL_EN 0 /* RNG Enable */ +#define BITM_RNG_CTL_SINGLE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Generate a Single Number */ +#define BITM_RNG_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* RNG Enable */ +#define ENUM_RNG_CTL_WORD (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SINGLE: Buffer Word */ +#define ENUM_RNG_CTL_SINGLE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SINGLE: Single Byte */ +#define ENUM_RNG_CTL_DISABLE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* EN: Disable the RNG */ +#define ENUM_RNG_CTL_ENABLE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* EN: Enable the RNG */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_LEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_LEN_PRESCALE 12 /* Prescaler for the Sample Counter */ +#define BITP_RNG_LEN_RELOAD 0 /* Reload Value for the Sample Counter */ +#define BITM_RNG_LEN_PRESCALE (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* Prescaler for the Sample Counter */ +#define BITM_RNG_LEN_RELOAD (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Reload Value for the Sample Counter */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_STAT_STUCK 1 /* Sampled Data Stuck High or Low */ +#define BITP_RNG_STAT_RNRDY 0 /* Random Number Ready */ +#define BITM_RNG_STAT_STUCK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Sampled Data Stuck High or Low */ +#define BITM_RNG_STAT_RNRDY (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Random Number Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_DATA_BUFF 8 /* Buffer for RNG Data */ +#define BITP_RNG_DATA_VALUE 0 /* Value of the CRC Accumulator */ +#define BITM_RNG_DATA_BUFF (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t )) /* Buffer for RNG Data */ +#define BITM_RNG_DATA_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* Value of the CRC Accumulator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_OSCCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_OSCCNT_VALUE 0 /* Oscillator Count */ +#define BITM_RNG_OSCCNT_VALUE (_ADI_MSK_3(0x0FFFFFFF,0x0FFFFFFFUL, uint32_t )) /* Oscillator Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_OSCDIFF[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_OSCDIFF_DELTA 0 /* Oscillator Count Difference */ +#define BITM_RNG_OSCDIFF_DELTA (_ADI_MSK_3(0x000000FF,0x000000FF, int8_t )) /* Oscillator Count Difference */ + + +/* ============================================================================================================================ + Register Map for the Crypto Block + ============================================================================================================================ */ + +/* ============================================================================================================================ + CRYPT0 + ============================================================================================================================ */ +#define REG_CRYPT0_CFG 0x40044000 /* CRYPT0 Configuration Register */ +#define REG_CRYPT0_DATALEN 0x40044004 /* CRYPT0 Payload Data Length */ +#define REG_CRYPT0_PREFIXLEN 0x40044008 /* CRYPT0 Authentication Data Length */ +#define REG_CRYPT0_INTEN 0x4004400C /* CRYPT0 Interrupt Enable Register */ +#define REG_CRYPT0_STAT 0x40044010 /* CRYPT0 Status Register */ +#define REG_CRYPT0_INBUF 0x40044014 /* CRYPT0 Input Buffer */ +#define REG_CRYPT0_OUTBUF 0x40044018 /* CRYPT0 Output Buffer */ +#define REG_CRYPT0_NONCE0 0x4004401C /* CRYPT0 Nonce Bits [31:0] */ +#define REG_CRYPT0_NONCE1 0x40044020 /* CRYPT0 Nonce Bits [63:32] */ +#define REG_CRYPT0_NONCE2 0x40044024 /* CRYPT0 Nonce Bits [95:64] */ +#define REG_CRYPT0_NONCE3 0x40044028 /* CRYPT0 Nonce Bits [127:96] */ +#define REG_CRYPT0_AESKEY0 0x4004402C /* CRYPT0 AES Key Bits [31:0] */ +#define REG_CRYPT0_AESKEY1 0x40044030 /* CRYPT0 AES Key Bits [63:32] */ +#define REG_CRYPT0_AESKEY2 0x40044034 /* CRYPT0 AES Key Bits [95:64] */ +#define REG_CRYPT0_AESKEY3 0x40044038 /* CRYPT0 AES Key Bits [127:96] */ +#define REG_CRYPT0_AESKEY4 0x4004403C /* CRYPT0 AES Key Bits [159:128] */ +#define REG_CRYPT0_AESKEY5 0x40044040 /* CRYPT0 AES Key Bits [191:160] */ +#define REG_CRYPT0_AESKEY6 0x40044044 /* CRYPT0 AES Key Bits [223:192] */ +#define REG_CRYPT0_AESKEY7 0x40044048 /* CRYPT0 AES Key Bits [255:224] */ +#define REG_CRYPT0_CNTRINIT 0x4004404C /* CRYPT0 Counter Initialization Vector */ +#define REG_CRYPT0_SHAH0 0x40044050 /* CRYPT0 SHA Bits [31:0] */ +#define REG_CRYPT0_SHAH1 0x40044054 /* CRYPT0 SHA Bits [63:32] */ +#define REG_CRYPT0_SHAH2 0x40044058 /* CRYPT0 SHA Bits [95:64] */ +#define REG_CRYPT0_SHAH3 0x4004405C /* CRYPT0 SHA Bits [127:96] */ +#define REG_CRYPT0_SHAH4 0x40044060 /* CRYPT0 SHA Bits [159:128] */ +#define REG_CRYPT0_SHAH5 0x40044064 /* CRYPT0 SHA Bits [191:160] */ +#define REG_CRYPT0_SHAH6 0x40044068 /* CRYPT0 SHA Bits [223:192] */ +#define REG_CRYPT0_SHAH7 0x4004406C /* CRYPT0 SHA Bits [255:224] */ +#define REG_CRYPT0_SHA_LAST_WORD 0x40044070 /* CRYPT0 SHA Last Word and Valid Bits Information */ +#define REG_CRYPT0_CCM_NUM_VALID_BYTES 0x40044074 /* CRYPT0 NUM_VALID_BYTES */ + +/* ============================================================================================================================ + CRYPT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CFG_REVID 28 /* Rev ID for Crypto */ +#define BITP_CRYPT_CFG_SHAINIT 26 /* Restarts SHA Computation */ +#define BITP_CRYPT_CFG_SHA256EN 25 /* Enable SHA-256 Operation */ +#define BITP_CRYPT_CFG_CMACEN 20 /* Enable CMAC Mode Operation */ +#define BITP_CRYPT_CFG_CCMEN 19 /* Enable CCM/CCM* Mode Operation */ +#define BITP_CRYPT_CFG_CBCEN 18 /* Enable CBC Mode Operation */ +#define BITP_CRYPT_CFG_CTREN 17 /* Enable CTR Mode Operation */ +#define BITP_CRYPT_CFG_ECBEN 16 /* Enable ECB Mode Operation */ +#define BITP_CRYPT_CFG_AESKEYLEN 8 /* Select Key Length for AES Cipher */ +#define BITP_CRYPT_CFG_AES_BYTESWAP 6 /* Byte Swap 32 Bit AES Input Data */ +#define BITP_CRYPT_CFG_OUTFLUSH 5 /* Output Buffer Flush */ +#define BITP_CRYPT_CFG_INFLUSH 4 /* Input Buffer Flush */ +#define BITP_CRYPT_CFG_OUTDMAEN 3 /* Enable DMA Channel Request for Output Buffer */ +#define BITP_CRYPT_CFG_INDMAEN 2 /* Enable DMA Channel Request for Input Buffer */ +#define BITP_CRYPT_CFG_ENCR 1 /* Encrypt or Decrypt */ +#define BITP_CRYPT_CFG_BLKEN 0 /* Enable Bit for Crypto Block */ +#define BITM_CRYPT_CFG_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Rev ID for Crypto */ +#define BITM_CRYPT_CFG_SHAINIT (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* Restarts SHA Computation */ +#define BITM_CRYPT_CFG_SHA256EN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Enable SHA-256 Operation */ +#define BITM_CRYPT_CFG_CMACEN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Enable CMAC Mode Operation */ +#define BITM_CRYPT_CFG_CCMEN (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* Enable CCM/CCM* Mode Operation */ +#define BITM_CRYPT_CFG_CBCEN (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* Enable CBC Mode Operation */ +#define BITM_CRYPT_CFG_CTREN (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Enable CTR Mode Operation */ +#define BITM_CRYPT_CFG_ECBEN (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Enable ECB Mode Operation */ +#define BITM_CRYPT_CFG_AESKEYLEN (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Select Key Length for AES Cipher */ +#define BITM_CRYPT_CFG_AES_BYTESWAP (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Byte Swap 32 Bit AES Input Data */ +#define BITM_CRYPT_CFG_OUTFLUSH (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Output Buffer Flush */ +#define BITM_CRYPT_CFG_INFLUSH (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Input Buffer Flush */ +#define BITM_CRYPT_CFG_OUTDMAEN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Enable DMA Channel Request for Output Buffer */ +#define BITM_CRYPT_CFG_INDMAEN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable DMA Channel Request for Input Buffer */ +#define BITM_CRYPT_CFG_ENCR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Encrypt or Decrypt */ +#define BITM_CRYPT_CFG_BLKEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Bit for Crypto Block */ +#define ENUM_CRYPT_CFG_AESKEYLEN128 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* AESKEYLEN: Uses 128-bit long key */ +#define ENUM_CRYPT_CFG_AESKEYLEN256 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* AESKEYLEN: Uses 256-bit long key */ +#define ENUM_CRYPT_CFG_DMA_DISABLE_OUTBUF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* OUTDMAEN: Disable DMA Requesting for Output Buffer */ +#define ENUM_CRYPT_CFG_DMA_ENABLE_OUTBUF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* OUTDMAEN: Enable DMA Requesting for Output Buffer */ +#define ENUM_CRYPT_CFG_DMA_DISABLE_INBUF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* INDMAEN: Disable DMA Requesting for Input Buffer */ +#define ENUM_CRYPT_CFG_DMA_ENABLE_INBUF (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* INDMAEN: Enable DMA Requesting for Input Buffer */ +#define ENUM_CRYPT_CFG_ENABLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BLKEN: Enable Crypto Block */ +#define ENUM_CRYPT_CFG_DISABLE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* BLKEN: Disable Crypto Block */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_DATALEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_DATALEN_VALUE 0 /* Length of Payload Data */ +#define BITM_CRYPT_DATALEN_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* Length of Payload Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_PREFIXLEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_PREFIXLEN_VALUE 0 /* Length of Associated Data */ +#define BITM_CRYPT_PREFIXLEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Length of Associated Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_INTEN_SHADONEN 5 /* Enable SHA_Done Interrupt */ +#define BITP_CRYPT_INTEN_INOVREN 2 /* Enable Input Overflow Interrupt */ +#define BITP_CRYPT_INTEN_OUTRDYEN 1 /* Enables the Output Ready Interrupt */ +#define BITP_CRYPT_INTEN_INRDYEN 0 /* Enable Input Ready Interrupt */ +#define BITM_CRYPT_INTEN_SHADONEN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Enable SHA_Done Interrupt */ +#define BITM_CRYPT_INTEN_INOVREN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Input Overflow Interrupt */ +#define BITM_CRYPT_INTEN_OUTRDYEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enables the Output Ready Interrupt */ +#define BITM_CRYPT_INTEN_INRDYEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Input Ready Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_STAT_OUTWORDS 10 /* Number of Words in the Output Buffer */ +#define BITP_CRYPT_STAT_INWORDS 7 /* Number of Words in the Input Buffer */ +#define BITP_CRYPT_STAT_SHABUSY 6 /* SHA Busy. in Computation */ +#define BITP_CRYPT_STAT_SHADONE 5 /* SHA Computation Complete */ +#define BITP_CRYPT_STAT_INOVR 2 /* Overflow in the Input Buffer */ +#define BITP_CRYPT_STAT_OUTRDY 1 /* Output Data Ready */ +#define BITP_CRYPT_STAT_INRDY 0 /* Input Buffer Status */ +#define BITM_CRYPT_STAT_OUTWORDS (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* Number of Words in the Output Buffer */ +#define BITM_CRYPT_STAT_INWORDS (_ADI_MSK_3(0x00000380,0x00000380UL, uint32_t )) /* Number of Words in the Input Buffer */ +#define BITM_CRYPT_STAT_SHABUSY (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* SHA Busy. in Computation */ +#define BITM_CRYPT_STAT_SHADONE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* SHA Computation Complete */ +#define BITM_CRYPT_STAT_INOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Overflow in the Input Buffer */ +#define BITM_CRYPT_STAT_OUTRDY (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Output Data Ready */ +#define BITM_CRYPT_STAT_INRDY (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Input Buffer Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_INBUF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_INBUF_VALUE 0 /* Input Buffer */ +#define BITM_CRYPT_INBUF_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Input Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_OUTBUF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_OUTBUF_VALUE 0 /* Output Buffer */ +#define BITM_CRYPT_OUTBUF_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Output Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE0_VALUE 0 /* Word 0: Nonce Bits [31:0] */ +#define BITM_CRYPT_NONCE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 0: Nonce Bits [31:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE1_VALUE 0 /* Word 1: Nonce Bits [63:32] */ +#define BITM_CRYPT_NONCE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 1: Nonce Bits [63:32] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE2_VALUE 0 /* Word 2: Nonce Bits [95:64] */ +#define BITM_CRYPT_NONCE2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 2: Nonce Bits [95:64] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE3_VALUE 0 /* Word 3: Nonce Bits [127:96] */ +#define BITM_CRYPT_NONCE3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 3: Nonce Bits [127:96] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY0_VALUE 0 /* Key: Bytes [3:0] */ +#define BITM_CRYPT_AESKEY0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [3:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY1_VALUE 0 /* Key: Bytes [7:4] */ +#define BITM_CRYPT_AESKEY1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [7:4] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY2_VALUE 0 /* Key: Bytes [11:8] */ +#define BITM_CRYPT_AESKEY2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [11:8] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY3_VALUE 0 /* Key: Bytes [15:12] */ +#define BITM_CRYPT_AESKEY3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [15:12] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY4_VALUE 0 /* Key: Bytes [19:16] */ +#define BITM_CRYPT_AESKEY4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [19:16] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY5_VALUE 0 /* Key: Bytes [23:20] */ +#define BITM_CRYPT_AESKEY5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [23:20] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY6_VALUE 0 /* Key: Bytes [27:24] */ +#define BITM_CRYPT_AESKEY6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [27:24] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY7_VALUE 0 /* Key: Bytes [31:28] */ +#define BITM_CRYPT_AESKEY7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [31:28] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CNTRINIT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CNTRINIT_VALUE 0 /* Counter Initialization Value */ +#define BITM_CRYPT_CNTRINIT_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* Counter Initialization Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH0_SHAHASH0 0 /* Word 0: SHA Hash */ +#define BITM_CRYPT_SHAH0_SHAHASH0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 0: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH1_SHAHASH1 0 /* Word 1: SHA Hash */ +#define BITM_CRYPT_SHAH1_SHAHASH1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 1: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH2_SHAHASH2 0 /* Word 2: SHA Hash */ +#define BITM_CRYPT_SHAH2_SHAHASH2 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 2: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH3_SHAHASH3 0 /* Word 3: SHA Hash */ +#define BITM_CRYPT_SHAH3_SHAHASH3 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 3: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH4_SHAHASH4 0 /* Word 4: SHA Hash */ +#define BITM_CRYPT_SHAH4_SHAHASH4 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 4: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH5_SHAHASH5 0 /* Word 5: SHA Hash */ +#define BITM_CRYPT_SHAH5_SHAHASH5 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 5: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH6_SHAHASH6 0 /* Word 6: SHA Hash */ +#define BITM_CRYPT_SHAH6_SHAHASH6 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 6: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH7_SHAHASH7 0 /* Word 7: SHA Hash */ +#define BITM_CRYPT_SHAH7_SHAHASH7 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 7: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHA_LAST_WORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID 1 /* Bits Valid in SHA Last Word Input */ +#define BITP_CRYPT_SHA_LAST_WORD_O_LAST_WORD 0 /* Last SHA Input Word */ +#define BITM_CRYPT_SHA_LAST_WORD_O_BITS_VALID (_ADI_MSK_3(0x0000003E,0x0000003EUL, uint32_t )) /* Bits Valid in SHA Last Word Input */ +#define BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Last SHA Input Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CCM_NUM_VALID_BYTES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES 0 /* Number of Valid Bytes in CCM Last Data */ +#define BITM_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Number of Valid Bytes in CCM Last Data */ + + +/* ============================================================================================================================ + Power Management Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + PMG0 + ============================================================================================================================ */ +#define REG_PMG0_IEN 0x4004C000 /* PMG0 Power Supply Monitor Interrupt Enable */ +#define REG_PMG0_PSM_STAT 0x4004C004 /* PMG0 Power Supply Monitor Status */ +#define REG_PMG0_PWRMOD 0x4004C008 /* PMG0 Power Mode Register */ +#define REG_PMG0_PWRKEY 0x4004C00C /* PMG0 Key Protection for PWRMOD and SRAMRET */ +#define REG_PMG0_SHDN_STAT 0x4004C010 /* PMG0 Shutdown Status Register */ +#define REG_PMG0_SRAMRET 0x4004C014 /* PMG0 Control for Retention SRAM in Hibernate Mode */ +#define REG_PMG0_RST_STAT 0x4004C040 /* PMG0 Reset Status */ +#define REG_PMG0_CTL1 0x4004C044 /* PMG0 HP Buck Control */ + +/* ============================================================================================================================ + PMG Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_IEN_IENBAT 10 /* Interrupt Enable for VBAT Range */ +#define BITP_PMG_IEN_RANGEBAT 8 /* Battery Monitor Range */ +#define BITP_PMG_IEN_VREGOVR 2 /* Enable Interrupt When VREG Overvoltage: Above 1.32V */ +#define BITP_PMG_IEN_VREGUNDR 1 /* Enable Interrupt When VREG Undervoltage: Below 1V */ +#define BITP_PMG_IEN_VBAT 0 /* Enable Interrupt for VBAT */ +#define BITM_PMG_IEN_IENBAT (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Interrupt Enable for VBAT Range */ +#define BITM_PMG_IEN_RANGEBAT (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Battery Monitor Range */ +#define BITM_PMG_IEN_VREGOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Interrupt When VREG Overvoltage: Above 1.32V */ +#define BITM_PMG_IEN_VREGUNDR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable Interrupt When VREG Undervoltage: Below 1V */ +#define BITM_PMG_IEN_VBAT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Interrupt for VBAT */ +#define ENUM_PMG_IEN_REGION1 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT > 2.75 V */ +#define ENUM_PMG_IEN_REGION2 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT between 2.75 V - 1.6 V */ +#define ENUM_PMG_IEN_REGION3 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT between 2.3 V - 1.6 V */ +#define ENUM_PMG_IEN_NA (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* RANGEBAT: N/A */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PSM_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PSM_STAT_RORANGE3 15 /* VBAT Range3 (2.3v - 1.6v) */ +#define BITP_PMG_PSM_STAT_RORANGE2 14 /* VBAT Range2 (2.75v - 2.3v) */ +#define BITP_PMG_PSM_STAT_RORANGE1 13 /* VBAT Range1 (> 2.75v) */ +#define BITP_PMG_PSM_STAT_RANGE3 10 /* VBAT Range3 (2.3v - 1.6v) */ +#define BITP_PMG_PSM_STAT_RANGE2 9 /* VBAT Range2 (2.75v - 2.3v) */ +#define BITP_PMG_PSM_STAT_RANGE1 8 /* VBAT Range1 (> 2.75v) */ +#define BITP_PMG_PSM_STAT_WICENACK 7 /* WIC Enable Acknowledge from Cortex */ +#define BITP_PMG_PSM_STAT_VREGOVR 2 /* Status Bit for Alarm Indicating Overvoltage for VREG */ +#define BITP_PMG_PSM_STAT_VREGUNDR 1 /* Status Bit for Alarm Indicating VREG is Below 1V */ +#define BITP_PMG_PSM_STAT_VBATUNDR 0 /* Status Bit Indicating an Alarm That Battery is Below 1.8V */ +#define BITM_PMG_PSM_STAT_RORANGE3 (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* VBAT Range3 (2.3v - 1.6v) */ +#define BITM_PMG_PSM_STAT_RORANGE2 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* VBAT Range2 (2.75v - 2.3v) */ +#define BITM_PMG_PSM_STAT_RORANGE1 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* VBAT Range1 (> 2.75v) */ +#define BITM_PMG_PSM_STAT_RANGE3 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* VBAT Range3 (2.3v - 1.6v) */ +#define BITM_PMG_PSM_STAT_RANGE2 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* VBAT Range2 (2.75v - 2.3v) */ +#define BITM_PMG_PSM_STAT_RANGE1 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* VBAT Range1 (> 2.75v) */ +#define BITM_PMG_PSM_STAT_WICENACK (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* WIC Enable Acknowledge from Cortex */ +#define BITM_PMG_PSM_STAT_VREGOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Status Bit for Alarm Indicating Overvoltage for VREG */ +#define BITM_PMG_PSM_STAT_VREGUNDR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Status Bit for Alarm Indicating VREG is Below 1V */ +#define BITM_PMG_PSM_STAT_VBATUNDR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Status Bit Indicating an Alarm That Battery is Below 1.8V */ +#define ENUM_PMG_PSM_STAT_BATSTAT1 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RORANGE1: VBAT not in the range specified */ +#define ENUM_PMG_PSM_STAT_BATSTAT0 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* RORANGE1: VBAT in the range specified */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PWRMOD_MONVBATN 3 /* Monitor VBAT During Hibernate Mode. Monitors VBAT by Default */ +#define BITP_PMG_PWRMOD_MODE 0 /* Power Mode Bits */ +#define BITM_PMG_PWRMOD_MONVBATN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Monitor VBAT During Hibernate Mode. Monitors VBAT by Default */ +#define BITM_PMG_PWRMOD_MODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Power Mode Bits */ +#define ENUM_PMG_PWRMOD_VBAT_MONEN (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* MONVBATN: VBAT monitor enabled in PMG block. */ +#define ENUM_PMG_PWRMOD_VBAT_MONDIS (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* MONVBATN: VBAT monitor disabled in PMG block. */ +#define ENUM_PMG_PWRMOD_FLEXI (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* MODE: Flexi Mode */ +#define ENUM_PMG_PWRMOD_HIBERNATE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* MODE: Hibernate Mode */ +#define ENUM_PMG_PWRMOD_SHUTDOWN (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* MODE: Shutdown Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PWRKEY_VALUE 0 /* Power Control Key Register */ +#define BITM_PMG_PWRKEY_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Power Control Key Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_SHDN_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_SHDN_STAT_RTC 3 /* Wakeup by Interrupt from RTC */ +#define BITP_PMG_SHDN_STAT_EXTINT2 2 /* Wakeup by Interrupt from External Interrupt 2 */ +#define BITP_PMG_SHDN_STAT_EXTINT1 1 /* Wakeup by Interrupt from External Interrupt 1 */ +#define BITP_PMG_SHDN_STAT_EXTINT0 0 /* Wakeup by Interrupt from External Interrupt 0 */ +#define BITM_PMG_SHDN_STAT_RTC (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Wakeup by Interrupt from RTC */ +#define BITM_PMG_SHDN_STAT_EXTINT2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Wakeup by Interrupt from External Interrupt 2 */ +#define BITM_PMG_SHDN_STAT_EXTINT1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Wakeup by Interrupt from External Interrupt 1 */ +#define BITM_PMG_SHDN_STAT_EXTINT0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Wakeup by Interrupt from External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_SRAMRET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_SRAMRET_BNK2EN 1 /* Enable Retention Bank 2 (16kB) */ +#define BITP_PMG_SRAMRET_BNK1EN 0 /* Enable Retention Bank 1 (8kB) */ +#define BITM_PMG_SRAMRET_BNK2EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable Retention Bank 2 (16kB) */ +#define BITM_PMG_SRAMRET_BNK1EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Retention Bank 1 (8kB) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_RST_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_RST_STAT_PORSRC 4 /* Power-on-Reset Source */ +#define BITP_PMG_RST_STAT_SWRST 3 /* Software Reset */ +#define BITP_PMG_RST_STAT_WDRST 2 /* Watchdog Time-out Reset */ +#define BITP_PMG_RST_STAT_EXTRST 1 /* External Reset */ +#define BITP_PMG_RST_STAT_POR 0 /* Power-on-Reset */ +#define BITM_PMG_RST_STAT_PORSRC (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Power-on-Reset Source */ +#define BITM_PMG_RST_STAT_SWRST (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Software Reset */ +#define BITM_PMG_RST_STAT_WDRST (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Watchdog Time-out Reset */ +#define BITM_PMG_RST_STAT_EXTRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* External Reset */ +#define BITM_PMG_RST_STAT_POR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Power-on-Reset */ +#define ENUM_PMG_RST_STAT_FAILSAFE_HV (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PORSRC: POR triggered because VBAT drops below Fail Safe */ +#define ENUM_PMG_RST_STAT_RST_VBAT (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* PORSRC: POR trigger because VBAT supply (VBAT < 1.7 V) */ +#define ENUM_PMG_RST_STAT_RST_VREG (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* PORSRC: POR triggered because VDD supply (VDD < 1.08 V) */ +#define ENUM_PMG_RST_STAT_FAILSAFE_LV (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* PORSRC: POR triggered because VREG drops below Fail Safe */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_CTL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_CTL1_HPBUCKEN 0 /* Enable HP Buck */ +#define BITM_PMG_CTL1_HPBUCKEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable HP Buck */ + + +/* ============================================================================================================================ + External interrupt configuration + ============================================================================================================================ */ + +/* ============================================================================================================================ + XINT0 + ============================================================================================================================ */ +#define REG_XINT0_CFG0 0x4004C080 /* XINT0 External Interrupt Configuration */ +#define REG_XINT0_EXT_STAT 0x4004C084 /* XINT0 External Wakeup Interrupt Status */ +#define REG_XINT0_CLR 0x4004C090 /* XINT0 External Interrupt Clear */ +#define REG_XINT0_NMICLR 0x4004C094 /* XINT0 Non-Maskable Interrupt Clear */ + +/* ============================================================================================================================ + XINT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_CFG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_CFG0_UART_RX_MDE 21 /* External Interrupt Using UART_RX Wakeup Mode Registers */ +#define BITP_XINT_CFG0_UART_RX_EN 20 /* External Interrupt Enable Bit */ +#define BITP_XINT_CFG0_IRQ3EN 15 /* External Interrupt 3 Enable Bit */ +#define BITP_XINT_CFG0_IRQ3MDE 12 /* External Interrupt 3 Mode Registers */ +#define BITP_XINT_CFG0_IRQ2EN 11 /* External Interrupt 2 Enable Bit */ +#define BITP_XINT_CFG0_IRQ2MDE 8 /* External Interrupt 2 Mode Registers */ +#define BITP_XINT_CFG0_IRQ1EN 7 /* External Interrupt 1 Enable Bit */ +#define BITP_XINT_CFG0_IRQ1MDE 4 /* External Interrupt 1 Mode Registers */ +#define BITP_XINT_CFG0_IRQ0EN 3 /* External Interrupt 0 Enable Bit */ +#define BITP_XINT_CFG0_IRQ0MDE 0 /* External Interrupt 0 Mode Registers */ +#define BITM_XINT_CFG0_UART_RX_MDE (_ADI_MSK_3(0x00E00000,0x00E00000UL, uint32_t )) /* External Interrupt Using UART_RX Wakeup Mode Registers */ +#define BITM_XINT_CFG0_UART_RX_EN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* External Interrupt Enable Bit */ +#define BITM_XINT_CFG0_IRQ3EN (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* External Interrupt 3 Enable Bit */ +#define BITM_XINT_CFG0_IRQ3MDE (_ADI_MSK_3(0x00007000,0x00007000UL, uint32_t )) /* External Interrupt 3 Mode Registers */ +#define BITM_XINT_CFG0_IRQ2EN (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* External Interrupt 2 Enable Bit */ +#define BITM_XINT_CFG0_IRQ2MDE (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t )) /* External Interrupt 2 Mode Registers */ +#define BITM_XINT_CFG0_IRQ1EN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* External Interrupt 1 Enable Bit */ +#define BITM_XINT_CFG0_IRQ1MDE (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t )) /* External Interrupt 1 Mode Registers */ +#define BITM_XINT_CFG0_IRQ0EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* External Interrupt 0 Enable Bit */ +#define BITM_XINT_CFG0_IRQ0MDE (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t )) /* External Interrupt 0 Mode Registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_EXT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_EXT_STAT_STAT_UART_RXWKUP 5 /* Interrupt Status Bit for UART RX Wakeup Interrupt */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT3 3 /* Interrupt Status Bit for External Interrupt 3 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT2 2 /* Interrupt Status Bit for External Interrupt 2 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT1 1 /* Interrupt Status Bit for External Interrupt 1 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT0 0 /* Interrupt Status Bit for External Interrupt 0 */ +#define BITM_XINT_EXT_STAT_STAT_UART_RXWKUP (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Interrupt Status Bit for UART RX Wakeup Interrupt */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Interrupt Status Bit for External Interrupt 3 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Interrupt Status Bit for External Interrupt 2 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Interrupt Status Bit for External Interrupt 1 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Interrupt Status Bit for External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_CLR_UART_RX_CLR 5 /* External Interrupt Clear for UART_RX Wakeup Interrupt */ +#define BITP_XINT_CLR_IRQ3 3 /* External Interrupt 3 */ +#define BITP_XINT_CLR_IRQ2 2 /* External Interrupt 2 */ +#define BITP_XINT_CLR_IRQ1 1 /* External Interrupt 1 */ +#define BITP_XINT_CLR_IRQ0 0 /* External Interrupt 0 */ +#define BITM_XINT_CLR_UART_RX_CLR (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* External Interrupt Clear for UART_RX Wakeup Interrupt */ +#define BITM_XINT_CLR_IRQ3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* External Interrupt 3 */ +#define BITM_XINT_CLR_IRQ2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* External Interrupt 2 */ +#define BITM_XINT_CLR_IRQ1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* External Interrupt 1 */ +#define BITM_XINT_CLR_IRQ0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_NMICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_NMICLR_CLR 0 /* NMI Clear */ +#define BITM_XINT_NMICLR_CLR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* NMI Clear */ + + +/* ============================================================================================================================ + Clocking registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CLKG0_OSC + ============================================================================================================================ */ +#define REG_CLKG0_OSC_KEY 0x4004C10C /* CLKG0_OSC Key Protection for CLKG_OSC_CTL */ +#define REG_CLKG0_OSC_CTL 0x4004C110 /* CLKG0_OSC Oscillator Control */ + +/* ============================================================================================================================ + CLKG_OSC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_OSC_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_OSC_KEY_VALUE 0 /* Oscillator K */ +#define BITM_CLKG_OSC_KEY_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Oscillator K */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_OSC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT 31 /* LFXTAL Not Stable */ +#define BITP_CLKG_OSC_CTL_HFXTALOK 11 /* Status of HFXTAL Oscillator */ +#define BITP_CLKG_OSC_CTL_LFXTALOK 10 /* Status of LFXTAL Oscillator */ +#define BITP_CLKG_OSC_CTL_HFOSCOK 9 /* Status of HFOSC */ +#define BITP_CLKG_OSC_CTL_LFOSCOK 8 /* Status of LFOSC Oscillator */ +#define BITP_CLKG_OSC_CTL_LFXTAL_MON_EN 5 /* LFXTAL Clock Monitor and Clock Fail Interrupt Enable */ +#define BITP_CLKG_OSC_CTL_LFXTAL_BYPASS 4 /* Low Frequency Crystal Oscillator Bypass */ +#define BITP_CLKG_OSC_CTL_HFXTALEN 3 /* High Frequency Crystal Oscillator Enable */ +#define BITP_CLKG_OSC_CTL_LFXTALEN 2 /* Low Frequency Crystal Oscillator Enable */ +#define BITP_CLKG_OSC_CTL_HFOSCEN 1 /* High Frequency Internal Oscillator Enable */ +#define BITP_CLKG_OSC_CTL_LFCLKMUX 0 /* 32kHz Clock Select Mux */ +#define BITM_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* LFXTAL Not Stable */ +#define BITM_CLKG_OSC_CTL_HFXTALOK (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Status of HFXTAL Oscillator */ +#define BITM_CLKG_OSC_CTL_LFXTALOK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Status of LFXTAL Oscillator */ +#define BITM_CLKG_OSC_CTL_HFOSCOK (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Status of HFOSC */ +#define BITM_CLKG_OSC_CTL_LFOSCOK (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Status of LFOSC Oscillator */ +#define BITM_CLKG_OSC_CTL_LFXTAL_MON_EN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LFXTAL Clock Monitor and Clock Fail Interrupt Enable */ +#define BITM_CLKG_OSC_CTL_LFXTAL_BYPASS (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Low Frequency Crystal Oscillator Bypass */ +#define BITM_CLKG_OSC_CTL_HFXTALEN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* High Frequency Crystal Oscillator Enable */ +#define BITM_CLKG_OSC_CTL_LFXTALEN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Low Frequency Crystal Oscillator Enable */ +#define BITM_CLKG_OSC_CTL_HFOSCEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* High Frequency Internal Oscillator Enable */ +#define BITM_CLKG_OSC_CTL_LFCLKMUX (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* 32kHz Clock Select Mux */ +#define ENUM_CLKG_OSC_CTL_LFXTAL_RUNNING (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LFXTAL_MON_FAIL_STAT: LFXTAL is running fine */ +#define ENUM_CLKG_OSC_CTL_LFXTAL_NOTRUNNING (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* LFXTAL_MON_FAIL_STAT: LFXTAL is not running */ + + +/* ============================================================================================================================ + Power Management Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + PMG0_TST + ============================================================================================================================ */ +#define REG_PMG0_TST_SRAM_CTL 0x4004C260 /* PMG0_TST Control for SRAM Parity and Instruction SRAM */ +#define REG_PMG0_TST_SRAM_INITSTAT 0x4004C264 /* PMG0_TST Initialization Status Register */ +#define REG_PMG0_TST_CLR_LATCH_GPIOS 0x4004C268 /* PMG0_TST Clear GPIO After Shutdown Mode */ +#define REG_PMG0_TST_SCRPAD_IMG 0x4004C26C /* PMG0_TST Scratch Pad Image */ +#define REG_PMG0_TST_SCRPAD_3V_RD 0x4004C270 /* PMG0_TST Scratch Pad Saved in Battery Domain */ + +/* ============================================================================================================================ + PMG_TST Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SRAM_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SRAM_CTL_INSTREN 31 /* Enables Instruction SRAM */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK5 21 /* Enable Parity Check SRAM Bank 5 */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK4 20 /* Enable Parity Check SRAM Bank 4 */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK3 19 /* Enable Parity Check SRAM Bank 3 */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK2 18 /* Enable Parity Check SRAM Bank 2 */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK1 17 /* Enable Parity Check SRAM Bank 1 */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK0 16 /* Enable Parity Check SRAM Bank 0 */ +#define BITP_PMG_TST_SRAM_CTL_ABTINIT 15 /* Abort Current Initialization. Self-cleared */ +#define BITP_PMG_TST_SRAM_CTL_AUTOINIT 14 /* Automatic Initialization on Wakeup from Hibernate Mode */ +#define BITP_PMG_TST_SRAM_CTL_STARTINIT 13 /* Write 1 to Trigger Initialization */ +#define BITP_PMG_TST_SRAM_CTL_BNK5EN 5 /* Enable Initialization of SRAM Bank 5 */ +#define BITP_PMG_TST_SRAM_CTL_BNK4EN 4 /* Enable Initialization of SRAM Bank 4 */ +#define BITP_PMG_TST_SRAM_CTL_BNK3EN 3 /* Enable Initialization of SRAM Bank 3 */ +#define BITP_PMG_TST_SRAM_CTL_BNK2EN 2 /* Enable Initialization of SRAM Bank 2 */ +#define BITP_PMG_TST_SRAM_CTL_BNK1EN 1 /* Enable Initialization of SRAM Bank 1 */ +#define BITP_PMG_TST_SRAM_CTL_BNK0EN 0 /* Enable Initialization of SRAM Bank 0 */ +#define BITM_PMG_TST_SRAM_CTL_INSTREN (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Enables Instruction SRAM */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK5 (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Enable Parity Check SRAM Bank 5 */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK4 (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Enable Parity Check SRAM Bank 4 */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK3 (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* Enable Parity Check SRAM Bank 3 */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK2 (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* Enable Parity Check SRAM Bank 2 */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK1 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Enable Parity Check SRAM Bank 1 */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK0 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Enable Parity Check SRAM Bank 0 */ +#define BITM_PMG_TST_SRAM_CTL_ABTINIT (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Abort Current Initialization. Self-cleared */ +#define BITM_PMG_TST_SRAM_CTL_AUTOINIT (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Automatic Initialization on Wakeup from Hibernate Mode */ +#define BITM_PMG_TST_SRAM_CTL_STARTINIT (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Write 1 to Trigger Initialization */ +#define BITM_PMG_TST_SRAM_CTL_BNK5EN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Enable Initialization of SRAM Bank 5 */ +#define BITM_PMG_TST_SRAM_CTL_BNK4EN (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Enable Initialization of SRAM Bank 4 */ +#define BITM_PMG_TST_SRAM_CTL_BNK3EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Enable Initialization of SRAM Bank 3 */ +#define BITM_PMG_TST_SRAM_CTL_BNK2EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Initialization of SRAM Bank 2 */ +#define BITM_PMG_TST_SRAM_CTL_BNK1EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable Initialization of SRAM Bank 1 */ +#define BITM_PMG_TST_SRAM_CTL_BNK0EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Initialization of SRAM Bank 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SRAM_INITSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK5 5 /* Initialization Done of SRAM Bank 5 */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK4 4 /* Initialization Done of SRAM Bank 4 */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK3 3 /* Initialization Done of SRAM Bank 3 */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK2 2 /* Initialization Done of SRAM Bank 2 */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK1 1 /* Initialization Done of SRAM Bank 1 */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK0 0 /* Initialization Done of SRAM Bank 0 */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK5 (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Initialization Done of SRAM Bank 5 */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK4 (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Initialization Done of SRAM Bank 4 */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Initialization Done of SRAM Bank 3 */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Initialization Done of SRAM Bank 2 */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Initialization Done of SRAM Bank 1 */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Initialization Done of SRAM Bank 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_CLR_LATCH_GPIOS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_CLR_LATCH_GPIOS_VALUE 0 /* Clear GPIOs Latches */ +#define BITM_PMG_TST_CLR_LATCH_GPIOS_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Clear GPIOs Latches */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SCRPAD_IMG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SCRPAD_IMG_DATA 0 /* Scratch Image */ +#define BITM_PMG_TST_SCRPAD_IMG_DATA (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Scratch Image */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SCRPAD_3V_RD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SCRPAD_3V_RD_DATA 0 /* Reading the Scratch Pad Stored in Shutdown Mode */ +#define BITM_PMG_TST_SCRPAD_3V_RD_DATA (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Reading the Scratch Pad Stored in Shutdown Mode */ + + +/* ============================================================================================================================ + Clocking registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CLKG0_CLK + ============================================================================================================================ */ +#define REG_CLKG0_CLK_CTL0 0x4004C300 /* CLKG0_CLK Miscellaneous Clock Settings */ +#define REG_CLKG0_CLK_CTL1 0x4004C304 /* CLKG0_CLK Clock Dividers */ +#define REG_CLKG0_CLK_CTL3 0x4004C30C /* CLKG0_CLK System PLL */ +#define REG_CLKG0_CLK_CTL5 0x4004C314 /* CLKG0_CLK User Clock Gating Control */ +#define REG_CLKG0_CLK_STAT0 0x4004C318 /* CLKG0_CLK Clocking Status */ + +/* ============================================================================================================================ + CLKG_CLK Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL0_HFXTALIE 15 /* High Frequency Crystal Interrupt Enable */ +#define BITP_CLKG_CLK_CTL0_LFXTALIE 14 /* Low Frequency Crystal Interrupt Enable */ +#define BITP_CLKG_CLK_CTL0_SPLLIPSEL 11 /* SPLL Source Select Mux */ +#define BITP_CLKG_CLK_CTL0_RCLKMUX 8 /* Flash Reference Clock and HP Buck Source Mux */ +#define BITP_CLKG_CLK_CTL0_CLKMUX 0 /* Clock Mux Select */ +#define BITM_CLKG_CLK_CTL0_HFXTALIE (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* High Frequency Crystal Interrupt Enable */ +#define BITM_CLKG_CLK_CTL0_LFXTALIE (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Low Frequency Crystal Interrupt Enable */ +#define BITM_CLKG_CLK_CTL0_SPLLIPSEL (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* SPLL Source Select Mux */ +#define BITM_CLKG_CLK_CTL0_RCLKMUX (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Flash Reference Clock and HP Buck Source Mux */ +#define BITM_CLKG_CLK_CTL0_CLKMUX (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Clock Mux Select */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL1_ACLKDIVCNT 16 /* ACLK Divide Count */ +#define BITP_CLKG_CLK_CTL1_PCLKDIVCNT 8 /* PCLK Divide Count */ +#define BITP_CLKG_CLK_CTL1_HCLKDIVCNT 0 /* HCLK Divide Count */ +#define BITM_CLKG_CLK_CTL1_ACLKDIVCNT (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* ACLK Divide Count */ +#define BITM_CLKG_CLK_CTL1_PCLKDIVCNT (_ADI_MSK_3(0x00003F00,0x00003F00UL, uint32_t )) /* PCLK Divide Count */ +#define BITM_CLKG_CLK_CTL1_HCLKDIVCNT (_ADI_MSK_3(0x0000003F,0x0000003FUL, uint32_t )) /* HCLK Divide Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL3_SPLLMUL2 16 /* System PLL Multiply by 2 */ +#define BITP_CLKG_CLK_CTL3_SPLLMSEL 11 /* System PLL M Divider */ +#define BITP_CLKG_CLK_CTL3_SPLLIE 10 /* System PLL Interrupt Enable */ +#define BITP_CLKG_CLK_CTL3_SPLLEN 9 /* System PLL Enable */ +#define BITP_CLKG_CLK_CTL3_SPLLDIV2 8 /* System PLL Division by 2 */ +#define BITP_CLKG_CLK_CTL3_SPLLNSEL 0 /* System PLL N Multiplier */ +#define BITM_CLKG_CLK_CTL3_SPLLMUL2 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* System PLL Multiply by 2 */ +#define BITM_CLKG_CLK_CTL3_SPLLMSEL (_ADI_MSK_3(0x00007800,0x00007800UL, uint32_t )) /* System PLL M Divider */ +#define BITM_CLKG_CLK_CTL3_SPLLIE (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* System PLL Interrupt Enable */ +#define BITM_CLKG_CLK_CTL3_SPLLEN (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* System PLL Enable */ +#define BITM_CLKG_CLK_CTL3_SPLLDIV2 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* System PLL Division by 2 */ +#define BITM_CLKG_CLK_CTL3_SPLLNSEL (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t )) /* System PLL N Multiplier */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL5_PERCLKOFF 5 /* Disables All Clocks Connected to All Peripherals */ +#define BITP_CLKG_CLK_CTL5_GPIOCLKOFF 4 /* GPIO Clock Control */ +#define BITP_CLKG_CLK_CTL5_UCLKI2COFF 3 /* I2C Clock User Control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK2OFF 2 /* Timer 2 User Control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK1OFF 1 /* Timer 1 User Control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK0OFF 0 /* Timer 0 User Control */ +#define BITM_CLKG_CLK_CTL5_PERCLKOFF (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Disables All Clocks Connected to All Peripherals */ +#define BITM_CLKG_CLK_CTL5_GPIOCLKOFF (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* GPIO Clock Control */ +#define BITM_CLKG_CLK_CTL5_UCLKI2COFF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* I2C Clock User Control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK2OFF (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Timer 2 User Control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK1OFF (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Timer 1 User Control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK0OFF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Timer 0 User Control */ +#define ENUM_CLKG_CLK_CTL5_PERIPH_CLK_ACT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PERCLKOFF: Clocks to all peripherals are active */ +#define ENUM_CLKG_CLK_CTL5_PERIPH_CLK_OFF (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* PERCLKOFF: Clocks to all peripherals are gated off */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_STAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_STAT0_HFXTALNOK 14 /* HF Crystal Not Stable */ +#define BITP_CLKG_CLK_STAT0_HFXTALOK 13 /* HF Crystal Stable */ +#define BITP_CLKG_CLK_STAT0_HFXTAL 12 /* HF Crystal Status */ +#define BITP_CLKG_CLK_STAT0_LFXTALNOK 10 /* LF Crystal Not Stable */ +#define BITP_CLKG_CLK_STAT0_LFXTALOK 9 /* LF Crystal Stable */ +#define BITP_CLKG_CLK_STAT0_LFXTAL 8 /* LF Crystal Status */ +#define BITP_CLKG_CLK_STAT0_SPLLUNLK 2 /* System PLL Unlock */ +#define BITP_CLKG_CLK_STAT0_SPLLLK 1 /* System PLL Lock */ +#define BITP_CLKG_CLK_STAT0_SPLL 0 /* System PLL Status */ +#define BITM_CLKG_CLK_STAT0_HFXTALNOK (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* HF Crystal Not Stable */ +#define BITM_CLKG_CLK_STAT0_HFXTALOK (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* HF Crystal Stable */ +#define BITM_CLKG_CLK_STAT0_HFXTAL (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* HF Crystal Status */ +#define BITM_CLKG_CLK_STAT0_LFXTALNOK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* LF Crystal Not Stable */ +#define BITM_CLKG_CLK_STAT0_LFXTALOK (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* LF Crystal Stable */ +#define BITM_CLKG_CLK_STAT0_LFXTAL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* LF Crystal Status */ +#define BITM_CLKG_CLK_STAT0_SPLLUNLK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* System PLL Unlock */ +#define BITM_CLKG_CLK_STAT0_SPLLLK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* System PLL Lock */ +#define BITM_CLKG_CLK_STAT0_SPLL (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* System PLL Status */ + + +/* ============================================================================================================================ + Bus matrix + ============================================================================================================================ */ + +/* ============================================================================================================================ + BUSM0 + ============================================================================================================================ */ +#define REG_BUSM0_ARBIT0 0x4004C800 /* BUSM0 Arbitration Priority Configuration for FLASH and SRAM0 */ +#define REG_BUSM0_ARBIT1 0x4004C804 /* BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */ +#define REG_BUSM0_ARBIT2 0x4004C808 /* BUSM0 Arbitration Priority Configuration for APB32 and APB16 */ +#define REG_BUSM0_ARBIT3 0x4004C80C /* BUSM0 Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ + +/* ============================================================================================================================ + BUSM Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT0_SRAM0_DMA0 20 /* SRAM0 priority for DMA0 */ +#define BITP_BUSM_ARBIT0_SRAM0_SBUS 18 /* SRAM0 priority for SBUS */ +#define BITP_BUSM_ARBIT0_SRAM0_DCODE 16 /* SRAM0 priority for Dcode */ +#define BITP_BUSM_ARBIT0_FLSH_DMA0 4 /* Flash priority for DMA0 */ +#define BITP_BUSM_ARBIT0_FLSH_SBUS 2 /* Flash priority for SBUS */ +#define BITP_BUSM_ARBIT0_FLSH_DCODE 0 /* Flash priority for DCODE */ +#define BITM_BUSM_ARBIT0_SRAM0_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* SRAM0 priority for DMA0 */ +#define BITM_BUSM_ARBIT0_SRAM0_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* SRAM0 priority for SBUS */ +#define BITM_BUSM_ARBIT0_SRAM0_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* SRAM0 priority for Dcode */ +#define BITM_BUSM_ARBIT0_FLSH_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Flash priority for DMA0 */ +#define BITM_BUSM_ARBIT0_FLSH_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* Flash priority for SBUS */ +#define BITM_BUSM_ARBIT0_FLSH_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Flash priority for DCODE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT1_SIP_DMA0 20 /* SIP priority for DMA0 */ +#define BITP_BUSM_ARBIT1_SIP_SBUS 18 /* SIP priority for SBUS */ +#define BITP_BUSM_ARBIT1_SIP_DCODE 16 /* SIP priority for DCODE */ +#define BITP_BUSM_ARBIT1_SRAM1_DMA0 4 /* SRAM1 priority for DMA0 */ +#define BITP_BUSM_ARBIT1_SRAM1_SBUS 2 /* SRAM1 priority for SBUS */ +#define BITP_BUSM_ARBIT1_SRAM1_DCODE 0 /* SRAM1 priority for Dcode */ +#define BITM_BUSM_ARBIT1_SIP_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* SIP priority for DMA0 */ +#define BITM_BUSM_ARBIT1_SIP_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* SIP priority for SBUS */ +#define BITM_BUSM_ARBIT1_SIP_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* SIP priority for DCODE */ +#define BITM_BUSM_ARBIT1_SRAM1_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* SRAM1 priority for DMA0 */ +#define BITM_BUSM_ARBIT1_SRAM1_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* SRAM1 priority for SBUS */ +#define BITM_BUSM_ARBIT1_SRAM1_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* SRAM1 priority for Dcode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT2_APB16_DMA0 20 /* APB16 priority for DMA0 */ +#define BITP_BUSM_ARBIT2_APB16_SBUS 18 /* APB16 priority for SBUS */ +#define BITP_BUSM_ARBIT2_APB16_DCODE 16 /* APB16 priority for DCODE */ +#define BITP_BUSM_ARBIT2_APB32_DMA0 4 /* APB32 priority for DMA0 */ +#define BITP_BUSM_ARBIT2_APB32_SBUS 2 /* APB32 priority for SBUS */ +#define BITP_BUSM_ARBIT2_APB32_DCODE 0 /* APB32 priority for DCODE */ +#define BITM_BUSM_ARBIT2_APB16_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* APB16 priority for DMA0 */ +#define BITM_BUSM_ARBIT2_APB16_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* APB16 priority for SBUS */ +#define BITM_BUSM_ARBIT2_APB16_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* APB16 priority for DCODE */ +#define BITM_BUSM_ARBIT2_APB32_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* APB32 priority for DMA0 */ +#define BITM_BUSM_ARBIT2_APB32_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* APB32 priority for SBUS */ +#define BITM_BUSM_ARBIT2_APB32_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* APB32 priority for DCODE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT3_APB16_4DMA_DMA1 17 /* APB16 for dma priority for DMA1 */ +#define BITP_BUSM_ARBIT3_APB16_4DMA_CORE 16 /* APB16 for dma priority for CORE */ +#define BITP_BUSM_ARBIT3_APB16_DMA1 1 /* APB16 priority for DMA1 */ +#define BITP_BUSM_ARBIT3_APB16_CORE 0 /* APB16 priority for CORE */ +#define BITM_BUSM_ARBIT3_APB16_4DMA_DMA1 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* APB16 for dma priority for DMA1 */ +#define BITM_BUSM_ARBIT3_APB16_4DMA_CORE (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* APB16 for dma priority for CORE */ +#define BITM_BUSM_ARBIT3_APB16_DMA1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* APB16 priority for DMA1 */ +#define BITM_BUSM_ARBIT3_APB16_CORE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* APB16 priority for CORE */ + + +/* ============================================================================================================================ + Parallel Test Interface + ============================================================================================================================ */ + +/* ============================================================================================================================ + PTI0 + ============================================================================================================================ */ +#define REG_PTI0_RST_ISR_STARTADDR 0x4004CD00 /* PTI0 Reset ISR Start Address */ +#define REG_PTI0_RST_STACK_PTR 0x4004CD04 /* PTI0 Reset Stack Pointer */ +#define REG_PTI0_CTL 0x4004CD08 /* PTI0 Parallel Test Interface Control Register */ + +/* ============================================================================================================================ + PTI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_RST_ISR_STARTADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_RST_ISR_STARTADDR_VALUE 0 +#define BITM_PTI_RST_ISR_STARTADDR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) + +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_RST_STACK_PTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_RST_STACK_PTR_VALUE 0 +#define BITM_PTI_RST_STACK_PTR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) + +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_CTL_EN 0 +#define BITM_PTI_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) + + +/* ============================================================================================================================ + Cortex-M3 Interrupt Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + NVIC0 + ============================================================================================================================ */ +#define REG_NVIC0_INTNUM 0xE000E004 /* NVIC0 Interrupt Control Type */ +#define REG_NVIC0_STKSTA 0xE000E010 /* NVIC0 Systick Control and Status */ +#define REG_NVIC0_STKLD 0xE000E014 /* NVIC0 Systick Reload Value */ +#define REG_NVIC0_STKVAL 0xE000E018 /* NVIC0 Systick Current Value */ +#define REG_NVIC0_STKCAL 0xE000E01C /* NVIC0 Systick Calibration Value */ +#define REG_NVIC0_INTSETE0 0xE000E100 /* NVIC0 IRQ0..31 Set_Enable */ +#define REG_NVIC0_INTSETE1 0xE000E104 /* NVIC0 IRQ32..63 Set_Enable */ +#define REG_NVIC0_INTCLRE0 0xE000E180 /* NVIC0 IRQ0..31 Clear_Enable */ +#define REG_NVIC0_INTCLRE1 0xE000E184 /* NVIC0 IRQ32..63 Clear_Enable */ +#define REG_NVIC0_INTSETP0 0xE000E200 /* NVIC0 IRQ0..31 Set_Pending */ +#define REG_NVIC0_INTSETP1 0xE000E204 /* NVIC0 IRQ32..63 Set_Pending */ +#define REG_NVIC0_INTCLRP0 0xE000E280 /* NVIC0 IRQ0..31 Clear_Pending */ +#define REG_NVIC0_INTCLRP1 0xE000E284 /* NVIC0 IRQ32..63 Clear_Pending */ +#define REG_NVIC0_INTACT0 0xE000E300 /* NVIC0 IRQ0..31 Active Bit */ +#define REG_NVIC0_INTACT1 0xE000E304 /* NVIC0 IRQ32..63 Active Bit */ +#define REG_NVIC0_INTPRI0 0xE000E400 /* NVIC0 IRQ0..3 Priority */ +#define REG_NVIC0_INTPRI1 0xE000E404 /* NVIC0 IRQ4..7 Priority */ +#define REG_NVIC0_INTPRI2 0xE000E408 /* NVIC0 IRQ8..11 Priority */ +#define REG_NVIC0_INTPRI3 0xE000E40C /* NVIC0 IRQ12..15 Priority */ +#define REG_NVIC0_INTPRI4 0xE000E410 /* NVIC0 IRQ16..19 Priority */ +#define REG_NVIC0_INTPRI5 0xE000E414 /* NVIC0 IRQ20..23 Priority */ +#define REG_NVIC0_INTPRI6 0xE000E418 /* NVIC0 IRQ24..27 Priority */ +#define REG_NVIC0_INTPRI7 0xE000E41C /* NVIC0 IRQ28..31 Priority */ +#define REG_NVIC0_INTPRI8 0xE000E420 /* NVIC0 IRQ32..35 Priority */ +#define REG_NVIC0_INTPRI9 0xE000E424 /* NVIC0 IRQ36..39 Priority */ +#define REG_NVIC0_INTPRI10 0xE000E428 /* NVIC0 IRQ40..43 Priority */ +#define REG_NVIC0_INTCPID 0xE000ED00 /* NVIC0 CPUID Base */ +#define REG_NVIC0_INTSTA 0xE000ED04 /* NVIC0 Interrupt Control State */ +#define REG_NVIC0_INTVEC 0xE000ED08 /* NVIC0 Vector Table Offset */ +#define REG_NVIC0_INTAIRC 0xE000ED0C /* NVIC0 Application Interrupt/Reset Control */ +#define REG_NVIC0_INTCON0 0xE000ED10 /* NVIC0 System Control */ +#define REG_NVIC0_INTCON1 0xE000ED14 /* NVIC0 Configuration Control */ +#define REG_NVIC0_INTSHPRIO0 0xE000ED18 /* NVIC0 System Handlers 4-7 Priority */ +#define REG_NVIC0_INTSHPRIO1 0xE000ED1C /* NVIC0 System Handlers 8-11 Priority */ +#define REG_NVIC0_INTSHPRIO3 0xE000ED20 /* NVIC0 System Handlers 12-15 Priority */ +#define REG_NVIC0_INTSHCSR 0xE000ED24 /* NVIC0 System Handler Control and State */ +#define REG_NVIC0_INTCFSR 0xE000ED28 /* NVIC0 Configurable Fault Status */ +#define REG_NVIC0_INTHFSR 0xE000ED2C /* NVIC0 Hard Fault Status */ +#define REG_NVIC0_INTDFSR 0xE000ED30 /* NVIC0 Debug Fault Status */ +#define REG_NVIC0_INTMMAR 0xE000ED34 /* NVIC0 Mem Manage Address */ +#define REG_NVIC0_INTBFAR 0xE000ED38 /* NVIC0 Bus Fault Address */ +#define REG_NVIC0_INTAFSR 0xE000ED3C /* NVIC0 Auxiliary Fault Status */ +#define REG_NVIC0_INTPFR0 0xE000ED40 /* NVIC0 Processor Feature Register 0 */ +#define REG_NVIC0_INTPFR1 0xE000ED44 /* NVIC0 Processor Feature Register 1 */ +#define REG_NVIC0_INTDFR0 0xE000ED48 /* NVIC0 Debug Feature Register 0 */ +#define REG_NVIC0_INTAFR0 0xE000ED4C /* NVIC0 Auxiliary Feature Register 0 */ +#define REG_NVIC0_INTMMFR0 0xE000ED50 /* NVIC0 Memory Model Feature Register 0 */ +#define REG_NVIC0_INTMMFR1 0xE000ED54 /* NVIC0 Memory Model Feature Register 1 */ +#define REG_NVIC0_INTMMFR2 0xE000ED58 /* NVIC0 Memory Model Feature Register 2 */ +#define REG_NVIC0_INTMMFR3 0xE000ED5C /* NVIC0 Memory Model Feature Register 3 */ +#define REG_NVIC0_INTISAR0 0xE000ED60 /* NVIC0 ISA Feature Register 0 */ +#define REG_NVIC0_INTISAR1 0xE000ED64 /* NVIC0 ISA Feature Register 1 */ +#define REG_NVIC0_INTISAR2 0xE000ED68 /* NVIC0 ISA Feature Register 2 */ +#define REG_NVIC0_INTISAR3 0xE000ED6C /* NVIC0 ISA Feature Register 3 */ +#define REG_NVIC0_INTISAR4 0xE000ED70 /* NVIC0 ISA Feature Register 4 */ +#define REG_NVIC0_INTTRGI 0xE000EF00 /* NVIC0 Software Trigger Interrupt Register */ +#define REG_NVIC0_INTPID4 0xE000EFD0 /* NVIC0 Peripheral Identification Register 4 */ +#define REG_NVIC0_INTPID5 0xE000EFD4 /* NVIC0 Peripheral Identification Register 5 */ +#define REG_NVIC0_INTPID6 0xE000EFD8 /* NVIC0 Peripheral Identification Register 6 */ +#define REG_NVIC0_INTPID7 0xE000EFDC /* NVIC0 Peripheral Identification Register 7 */ +#define REG_NVIC0_INTPID0 0xE000EFE0 /* NVIC0 Peripheral Identification Bits7:0 */ +#define REG_NVIC0_INTPID1 0xE000EFE4 /* NVIC0 Peripheral Identification Bits15:8 */ +#define REG_NVIC0_INTPID2 0xE000EFE8 /* NVIC0 Peripheral Identification Bits16:23 */ +#define REG_NVIC0_INTPID3 0xE000EFEC /* NVIC0 Peripheral Identification Bits24:31 */ +#define REG_NVIC0_INTCID0 0xE000EFF0 /* NVIC0 Component Identification Bits7:0 */ +#define REG_NVIC0_INTCID1 0xE000EFF4 /* NVIC0 Component Identification Bits15:8 */ +#define REG_NVIC0_INTCID2 0xE000EFF8 /* NVIC0 Component Identification Bits16:23 */ +#define REG_NVIC0_INTCID3 0xE000EFFC /* NVIC0 Component Identification Bits24:31 */ + +/* ============================================================================================================================ + NVIC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTNUM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTNUM_VALUE 0 /* Interrupt Control Type */ +#define BITM_NVIC_INTNUM_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Interrupt Control Type */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKSTA_VALUE 0 /* Systick Control and Status */ +#define BITM_NVIC_STKSTA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Control and Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKLD_VALUE 0 /* Systick Reload Value */ +#define BITM_NVIC_STKLD_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Reload Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKVAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKVAL_VALUE 0 /* Systick Current Value */ +#define BITM_NVIC_STKVAL_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Current Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKCAL_VALUE 0 /* Systick Calibration Value */ +#define BITM_NVIC_STKCAL_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Calibration Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETE0_VALUE 0 /* IRQ0..31 Set_Enable */ +#define BITM_NVIC_INTSETE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Set_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETE1_VALUE 0 /* IRQ32..63 Set_Enable */ +#define BITM_NVIC_INTSETE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Set_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRE0_VALUE 0 /* IRQ0..31 Clear_Enable */ +#define BITM_NVIC_INTCLRE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Clear_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRE1_VALUE 0 /* IRQ32..63 Clear_Enable */ +#define BITM_NVIC_INTCLRE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Clear_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETP0_VALUE 0 /* IRQ0..31 Set_Pending */ +#define BITM_NVIC_INTSETP0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Set_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETP1_VALUE 0 /* IRQ32..63 Set_Pending */ +#define BITM_NVIC_INTSETP1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Set_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRP0_VALUE 0 /* IRQ0..31 Clear_Pending */ +#define BITM_NVIC_INTCLRP0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Clear_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRP1_VALUE 0 /* IRQ32..63 Clear_Pending */ +#define BITM_NVIC_INTCLRP1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Clear_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTACT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTACT0_VALUE 0 /* IRQ0..31 Active Bit */ +#define BITM_NVIC_INTACT0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Active Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTACT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTACT1_VALUE 0 /* IRQ32..63 Active Bit */ +#define BITM_NVIC_INTACT1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Active Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI0_VALUE 0 /* IRQ0..3 Priority */ +#define BITM_NVIC_INTPRI0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..3 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI1_VALUE 0 /* IRQ4..7 Priority */ +#define BITM_NVIC_INTPRI1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ4..7 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI2_VALUE 0 /* IRQ8..11 Priority */ +#define BITM_NVIC_INTPRI2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ8..11 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI3_VALUE 0 /* IRQ12..15 Priority */ +#define BITM_NVIC_INTPRI3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ12..15 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI4_VALUE 0 /* IRQ16..19 Priority */ +#define BITM_NVIC_INTPRI4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ16..19 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI5_VALUE 0 /* IRQ20..23 Priority */ +#define BITM_NVIC_INTPRI5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ20..23 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI6_VALUE 0 /* IRQ24..27 Priority */ +#define BITM_NVIC_INTPRI6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ24..27 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI7_VALUE 0 /* IRQ28..31 Priority */ +#define BITM_NVIC_INTPRI7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ28..31 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI8_VALUE 0 /* IRQ32..35 Priority */ +#define BITM_NVIC_INTPRI8_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..35 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI9_VALUE 0 /* IRQ36..39 Priority */ +#define BITM_NVIC_INTPRI9_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ36..39 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI10 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI10_VALUE 0 /* IRQ40..43 Priority */ +#define BITM_NVIC_INTPRI10_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ40..43 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCPID_VALUE 0 /* CPUID Base */ +#define BITM_NVIC_INTCPID_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CPUID Base */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSTA_VALUE 0 /* Interrupt Control State */ +#define BITM_NVIC_INTSTA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Interrupt Control State */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTVEC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTVEC_VALUE 0 /* Vector Table Offset */ +#define BITM_NVIC_INTVEC_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Vector Table Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAIRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAIRC_VALUE 0 /* Application Interrupt/Reset Control */ +#define BITM_NVIC_INTAIRC_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Application Interrupt/Reset Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCON0_SLEEPDEEP 2 /* deep sleep flag for HIBERNATE mode */ +#define BITP_NVIC_INTCON0_SLEEPONEXIT 1 /* Sleeps the core on exit from an ISR */ +#define BITM_NVIC_INTCON0_SLEEPDEEP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* deep sleep flag for HIBERNATE mode */ +#define BITM_NVIC_INTCON0_SLEEPONEXIT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Sleeps the core on exit from an ISR */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCON1_VALUE 0 /* Configuration Control */ +#define BITM_NVIC_INTCON1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Configuration Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO0_VALUE 0 /* System Handlers 4-7 Priority */ +#define BITM_NVIC_INTSHPRIO0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 4-7 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO1_VALUE 0 /* System Handlers 8-11 Priority */ +#define BITM_NVIC_INTSHPRIO1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 8-11 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO3_VALUE 0 /* System Handlers 12-15 Priority */ +#define BITM_NVIC_INTSHPRIO3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 12-15 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHCSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHCSR_VALUE 0 /* System Handler Control and State */ +#define BITM_NVIC_INTSHCSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handler Control and State */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCFSR_VALUE 0 /* Configurable Fault Status */ +#define BITM_NVIC_INTCFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Configurable Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTHFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTHFSR_VALUE 0 /* Hard Fault Status */ +#define BITM_NVIC_INTHFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Hard Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTDFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTDFSR_VALUE 0 /* Debug Fault Status */ +#define BITM_NVIC_INTDFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Debug Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMAR_VALUE 0 /* Mem Manage Address */ +#define BITM_NVIC_INTMMAR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Mem Manage Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTBFAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTBFAR_VALUE 0 /* Bus Fault Address */ +#define BITM_NVIC_INTBFAR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Bus Fault Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAFSR_VALUE 0 /* Auxiliary Fault Status */ +#define BITM_NVIC_INTAFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Auxiliary Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPFR0_VALUE 0 /* Processor Feature Register 0 */ +#define BITM_NVIC_INTPFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Processor Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPFR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPFR1_VALUE 0 /* Processor Feature Register 1 */ +#define BITM_NVIC_INTPFR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Processor Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTDFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTDFR0_VALUE 0 /* Debug Feature Register 0 */ +#define BITM_NVIC_INTDFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Debug Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAFR0_VALUE 0 /* Auxiliary Feature Register 0 */ +#define BITM_NVIC_INTAFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Auxiliary Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR0_VALUE 0 /* Memory Model Feature Register 0 */ +#define BITM_NVIC_INTMMFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR1_VALUE 0 /* Memory Model Feature Register 1 */ +#define BITM_NVIC_INTMMFR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR2_VALUE 0 /* Memory Model Feature Register 2 */ +#define BITM_NVIC_INTMMFR2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR3_VALUE 0 /* Memory Model Feature Register 3 */ +#define BITM_NVIC_INTMMFR3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR0_VALUE 0 /* ISA Feature Register 0 */ +#define BITM_NVIC_INTISAR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR1_VALUE 0 /* ISA Feature Register 1 */ +#define BITM_NVIC_INTISAR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR2_VALUE 0 /* ISA Feature Register 2 */ +#define BITM_NVIC_INTISAR2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR3_VALUE 0 /* ISA Feature Register 3 */ +#define BITM_NVIC_INTISAR3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR4_VALUE 0 /* ISA Feature Register 4 */ +#define BITM_NVIC_INTISAR4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTTRGI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTTRGI_VALUE 0 /* Software Trigger Interrupt Register */ +#define BITM_NVIC_INTTRGI_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Software Trigger Interrupt Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID4_VALUE 0 /* Peripheral Identification Register 4 */ +#define BITM_NVIC_INTPID4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID5_VALUE 0 /* Peripheral Identification Register 5 */ +#define BITM_NVIC_INTPID5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID6_VALUE 0 /* Peripheral Identification Register 6 */ +#define BITM_NVIC_INTPID6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 6 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID7_VALUE 0 /* Peripheral Identification Register 7 */ +#define BITM_NVIC_INTPID7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 7 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID0_VALUE 0 /* Peripheral Identification Bits7:0 */ +#define BITM_NVIC_INTPID0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits7:0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID1_VALUE 0 /* Peripheral Identification Bits15:8 */ +#define BITM_NVIC_INTPID1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits15:8 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID2_VALUE 0 /* Peripheral Identification Bits16:23 */ +#define BITM_NVIC_INTPID2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits16:23 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID3_VALUE 0 /* Peripheral Identification Bits24:31 */ +#define BITM_NVIC_INTPID3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits24:31 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID0_VALUE 0 /* Component Identification Bits7:0 */ +#define BITM_NVIC_INTCID0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits7:0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID1_VALUE 0 /* Component Identification Bits15:8 */ +#define BITM_NVIC_INTCID1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits15:8 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID2_VALUE 0 /* Component Identification Bits16:23 */ +#define BITM_NVIC_INTCID2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits16:23 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID3_VALUE 0 /* Component Identification Bits24:31 */ +#define BITM_NVIC_INTCID3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits24:31 */ + +/* ==================================================================================================== + * Interrupt Definitions + * ==================================================================================================== */ +#define INTR_RESET (-15) /* Cortex-M3 Reset */ +#define INTR_NonMaskableInt (-14) /* Cortex-M3 Non-maskable Interrupt */ +#define INTR_HardFault (-13) /* Cortex-M3 Hardware Fault */ +#define INTR_MemoryManagement (-12) /* Cortex-M3 Memory Management Interrupt */ +#define INTR_BusFault (-11) /* Cortex-M3 Bus Fault */ +#define INTR_UsageFault (-10) /* Cortex-M3 Usage Fault */ +#define INTR_SVCall ( -5) /* Cortex-M3 SVCall Interrupt */ +#define INTR_DebugMonitor ( -4) /* Cortex-M3 Debug Monitor */ +#define INTR_PendSV ( -2) /* Cortex-M3 PendSV Interrupt */ +#define INTR_SysTick ( -1) /* Cortex-M3 SysTick Interrupt */ +#define INTR_RTC1_EVT 0 /* Event */ +#define INTR_XINT_EVT0 1 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT1 2 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT2 3 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT3 4 /* External Wakeup Interrupt n */ +#define INTR_WDT_EXP 5 /* Expiration */ +#define INTR_PMG0_VREG_OVR 6 /* Voltage Regulator (VREG) Overvoltage */ +#define INTR_PMG0_BATT_RANGE 7 /* Battery Voltage (VBAT) Out of Range */ +#define INTR_RTC0_EVT 8 /* Event */ +#define INTR_SYS_GPIO_INTA 9 /* GPIO Interrupt A */ +#define INTR_SYS_GPIO_INTB 10 /* GPIO Interrupt B */ +#define INTR_TMR0_EVT 11 /* Event */ +#define INTR_TMR1_EVT 12 /* Event */ +#define INTR_FLCC_EVT 13 /* Event */ +#define INTR_UART_EVT 14 /* Event */ +#define INTR_SPI0_EVT 15 /* Event */ +#define INTR_SPI2_EVT 16 /* Event */ +#define INTR_I2C_SLV_EVT 17 /* Slave Event */ +#define INTR_I2C_MST_EVT 18 /* Master Event */ +#define INTR_DMA_CHAN_ERR 19 /* Channel Error */ +#define INTR_DMA0_CH0_DONE 20 /* Channel 0 Done */ +#define INTR_DMA0_CH1_DONE 21 /* Channel 1 Done */ +#define INTR_DMA0_CH2_DONE 22 /* Channel 2 Done */ +#define INTR_DMA0_CH3_DONE 23 /* Channel 3 Done */ +#define INTR_DMA0_CH4_DONE 24 /* Channel 4 Done */ +#define INTR_DMA0_CH5_DONE 25 /* Channel 5 Done */ +#define INTR_DMA0_CH6_DONE 26 /* Channel 6 Done */ +#define INTR_DMA0_CH7_DONE 27 /* Channel 7 Done */ +#define INTR_DMA0_CH8_DONE 28 /* Channel 8 Done */ +#define INTR_DMA0_CH9_DONE 29 /* Channel 9 Done */ +#define INTR_DMA0_CH10_DONE 30 /* Channel 10 Done */ +#define INTR_DMA0_CH11_DONE 31 /* Channel 11 Done */ +#define INTR_DMA0_CH12_DONE 32 /* Channel 12 Done */ +#define INTR_DMA0_CH13_DONE 33 /* Channel 13 Done */ +#define INTR_DMA0_CH14_DONE 34 /* Channel 14 Done */ +#define INTR_DMA0_CH15_DONE 35 /* Channel 15 Done */ +#define INTR_SPORT_A_EVT 36 /* Channel A Event */ +#define INTR_SPORT_B_EVT 37 /* Channel B Event */ +#define INTR_CRYPT_EVT 38 /* Event */ +#define INTR_DMA0_CH24_DONE 39 /* Channel 24 Done */ +#define INTR_TMR2_EVT 40 /* Event */ +#define INTR_CLKG_XTAL_OSC_EVT 41 /* Crystal Oscillator Event */ +#define INTR_SPI1_EVT 42 /* Event */ +#define INTR_CLKG_PLL_EVT 43 /* PLL Event */ +#define INTR_RNG0_EVT 44 /* Event */ +#define INTR_BEEP_EVT 45 /* Event */ +#define INTR_ADC0_EVT 46 /* Event */ +#define INTR_DMA0_CH16_DONE 56 /* Channel 16 Done */ +#define INTR_DMA0_CH17_DONE 57 /* Channel 17 Done */ +#define INTR_DMA0_CH18_DONE 58 /* Channel 18 Done */ +#define INTR_DMA0_CH19_DONE 59 /* Channel 19 Done */ +#define INTR_DMA0_CH20_DONE 60 /* Channel 20 Done */ +#define INTR_DMA0_CH21_DONE 61 /* Channel 21 Done */ +#define INTR_DMA0_CH22_DONE 62 /* Channel 22 Done */ +#define INTR_DMA0_CH23_DONE 63 /* Channel 23 Done */ + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + +#endif /* end ifndef _DEF_ADUCM302X_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_cdef.h new file mode 100755 index 00000000000..fea68318596 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_cdef.h @@ -0,0 +1,663 @@ +/* ================================================================================ + + Project : ADuCM302x + File : ADuCM302x_cdef.h + Description : C MMR Pointer Definitions + + Date : Feb 6, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM302X_CDEF_H +#define _ADUCM302X_CDEF_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "ADuCM302x.h" + + +#ifndef __IO +#ifdef __cplusplus +#define __I volatile /* read-only */ +#define __C +#else +#define __I volatile /* read-only */ +#define __C const +#endif +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif +#if defined (_MISRA_RULES) +#pragma diag(push) +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros") +#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators") +#endif /* _MISRA_RULES */ + + +/* ================================================================================= + * General Purpose Timer (TMR0) + * ================================================================================= */ +#define pREG_TMR0_LOAD ((__IO uint16_t *) REG_TMR0_LOAD) /* 16-bit Load Value */ +#define pREG_TMR0_CURCNT ((__I __C uint16_t *) REG_TMR0_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR0_CTL ((__IO uint16_t *) REG_TMR0_CTL) /* Control */ +#define pREG_TMR0_CLRINT ((__O uint16_t *) REG_TMR0_CLRINT) /* Clear Interrupt */ +#define pREG_TMR0_CAPTURE ((__I __C uint16_t *) REG_TMR0_CAPTURE) /* Capture */ +#define pREG_TMR0_ALOAD ((__IO uint16_t *) REG_TMR0_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR0_ACURCNT ((__I __C uint16_t *) REG_TMR0_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR0_STAT ((__I __C uint16_t *) REG_TMR0_STAT) /* Status */ +#define pREG_TMR0_PWMCTL ((__IO uint16_t *) REG_TMR0_PWMCTL) /* PWM Control Register */ +#define pREG_TMR0_PWMMATCH ((__IO uint16_t *) REG_TMR0_PWMMATCH) /* PWM Match Value */ + +/* ================================================================================= + * General Purpose Timer (TMR1) + * ================================================================================= */ +#define pREG_TMR1_LOAD ((__IO uint16_t *) REG_TMR1_LOAD) /* 16-bit Load Value */ +#define pREG_TMR1_CURCNT ((__I __C uint16_t *) REG_TMR1_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR1_CTL ((__IO uint16_t *) REG_TMR1_CTL) /* Control */ +#define pREG_TMR1_CLRINT ((__O uint16_t *) REG_TMR1_CLRINT) /* Clear Interrupt */ +#define pREG_TMR1_CAPTURE ((__I __C uint16_t *) REG_TMR1_CAPTURE) /* Capture */ +#define pREG_TMR1_ALOAD ((__IO uint16_t *) REG_TMR1_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR1_ACURCNT ((__I __C uint16_t *) REG_TMR1_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR1_STAT ((__I __C uint16_t *) REG_TMR1_STAT) /* Status */ +#define pREG_TMR1_PWMCTL ((__IO uint16_t *) REG_TMR1_PWMCTL) /* PWM Control Register */ +#define pREG_TMR1_PWMMATCH ((__IO uint16_t *) REG_TMR1_PWMMATCH) /* PWM Match Value */ + +/* ================================================================================= + * General Purpose Timer (TMR2) + * ================================================================================= */ +#define pREG_TMR2_LOAD ((__IO uint16_t *) REG_TMR2_LOAD) /* 16-bit Load Value */ +#define pREG_TMR2_CURCNT ((__I __C uint16_t *) REG_TMR2_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR2_CTL ((__IO uint16_t *) REG_TMR2_CTL) /* Control */ +#define pREG_TMR2_CLRINT ((__O uint16_t *) REG_TMR2_CLRINT) /* Clear Interrupt */ +#define pREG_TMR2_CAPTURE ((__I __C uint16_t *) REG_TMR2_CAPTURE) /* Capture */ +#define pREG_TMR2_ALOAD ((__IO uint16_t *) REG_TMR2_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR2_ACURCNT ((__I __C uint16_t *) REG_TMR2_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR2_STAT ((__I __C uint16_t *) REG_TMR2_STAT) /* Status */ +#define pREG_TMR2_PWMCTL ((__IO uint16_t *) REG_TMR2_PWMCTL) /* PWM Control Register */ +#define pREG_TMR2_PWMMATCH ((__IO uint16_t *) REG_TMR2_PWMMATCH) /* PWM Match Value */ + +/* ================================================================================= + * Real-Time Clock (RTC0) + * ================================================================================= */ +#define pREG_RTC0_CR0 ((__IO uint16_t *) REG_RTC0_CR0) /* RTC Control 0 */ +#define pREG_RTC0_SR0 ((__IO uint16_t *) REG_RTC0_SR0) /* RTC Status 0 */ +#define pREG_RTC0_SR1 ((__I __C uint16_t *) REG_RTC0_SR1) /* RTC Status 1 */ +#define pREG_RTC0_CNT0 ((__IO uint16_t *) REG_RTC0_CNT0) /* RTC Count 0 */ +#define pREG_RTC0_CNT1 ((__IO uint16_t *) REG_RTC0_CNT1) /* RTC Count 1 */ +#define pREG_RTC0_ALM0 ((__IO uint16_t *) REG_RTC0_ALM0) /* RTC Alarm 0 */ +#define pREG_RTC0_ALM1 ((__IO uint16_t *) REG_RTC0_ALM1) /* RTC Alarm 1 */ +#define pREG_RTC0_TRM ((__IO uint16_t *) REG_RTC0_TRM) /* RTC Trim */ +#define pREG_RTC0_GWY ((__O uint16_t *) REG_RTC0_GWY) /* RTC Gateway */ +#define pREG_RTC0_CR1 ((__IO uint16_t *) REG_RTC0_CR1) /* RTC Control 1 */ +#define pREG_RTC0_SR2 ((__IO uint16_t *) REG_RTC0_SR2) /* RTC Status 2 */ +#define pREG_RTC0_SNAP0 ((__I __C uint16_t *) REG_RTC0_SNAP0) /* RTC Snapshot 0 */ +#define pREG_RTC0_SNAP1 ((__I __C uint16_t *) REG_RTC0_SNAP1) /* RTC Snapshot 1 */ +#define pREG_RTC0_SNAP2 ((__I __C uint16_t *) REG_RTC0_SNAP2) /* RTC Snapshot 2 */ +#define pREG_RTC0_MOD ((__I __C uint16_t *) REG_RTC0_MOD) /* RTC Modulo */ +#define pREG_RTC0_CNT2 ((__I __C uint16_t *) REG_RTC0_CNT2) /* RTC Count 2 */ +#define pREG_RTC0_ALM2 ((__IO uint16_t *) REG_RTC0_ALM2) /* RTC Alarm 2 */ +#define pREG_RTC0_SR3 ((__IO uint16_t *) REG_RTC0_SR3) /* RTC Status 3 */ +#define pREG_RTC0_CR2IC ((__IO uint16_t *) REG_RTC0_CR2IC) /* RTC Control 2 for Configuring Input Capture Channels */ +#define pREG_RTC0_CR3SS ((__IO uint16_t *) REG_RTC0_CR3SS) /* RTC Control 3 for Configuring SensorStrobe Channel */ +#define pREG_RTC0_CR4SS ((__IO uint16_t *) REG_RTC0_CR4SS) /* RTC Control 4 for Configuring SensorStrobe Channel */ +#define pREG_RTC0_SSMSK ((__IO uint16_t *) REG_RTC0_SSMSK) /* RTC Mask for SensorStrobe Channel */ +#define pREG_RTC0_SS1ARL ((__IO uint16_t *) REG_RTC0_SS1ARL) /* RTC Auto-Reload for SensorStrobe Channel 1 */ +#define pREG_RTC0_IC2 ((__I __C uint16_t *) REG_RTC0_IC2) /* RTC Input Capture Channel 2 */ +#define pREG_RTC0_IC3 ((__I __C uint16_t *) REG_RTC0_IC3) /* RTC Input Capture Channel 3 */ +#define pREG_RTC0_IC4 ((__I __C uint16_t *) REG_RTC0_IC4) /* RTC Input Capture Channel 4 */ +#define pREG_RTC0_SS1 ((__IO uint16_t *) REG_RTC0_SS1) /* RTC SensorStrobe Channel 1 */ +#define pREG_RTC0_SR4 ((__I __C uint16_t *) REG_RTC0_SR4) /* RTC Status 4 */ +#define pREG_RTC0_SR5 ((__I __C uint16_t *) REG_RTC0_SR5) /* RTC Status 5 */ +#define pREG_RTC0_SR6 ((__I __C uint16_t *) REG_RTC0_SR6) /* RTC Status 6 */ +#define pREG_RTC0_SS1TGT ((__I __C uint16_t *) REG_RTC0_SS1TGT) /* RTC SensorStrobe Channel 1 Target */ +#define pREG_RTC0_FRZCNT ((__I __C uint16_t *) REG_RTC0_FRZCNT) /* RTC Freeze Count */ + +/* ================================================================================= + * Real-Time Clock (RTC1) + * ================================================================================= */ +#define pREG_RTC1_CR0 ((__IO uint16_t *) REG_RTC1_CR0) /* RTC Control 0 */ +#define pREG_RTC1_SR0 ((__IO uint16_t *) REG_RTC1_SR0) /* RTC Status 0 */ +#define pREG_RTC1_SR1 ((__I __C uint16_t *) REG_RTC1_SR1) /* RTC Status 1 */ +#define pREG_RTC1_CNT0 ((__IO uint16_t *) REG_RTC1_CNT0) /* RTC Count 0 */ +#define pREG_RTC1_CNT1 ((__IO uint16_t *) REG_RTC1_CNT1) /* RTC Count 1 */ +#define pREG_RTC1_ALM0 ((__IO uint16_t *) REG_RTC1_ALM0) /* RTC Alarm 0 */ +#define pREG_RTC1_ALM1 ((__IO uint16_t *) REG_RTC1_ALM1) /* RTC Alarm 1 */ +#define pREG_RTC1_TRM ((__IO uint16_t *) REG_RTC1_TRM) /* RTC Trim */ +#define pREG_RTC1_GWY ((__O uint16_t *) REG_RTC1_GWY) /* RTC Gateway */ +#define pREG_RTC1_CR1 ((__IO uint16_t *) REG_RTC1_CR1) /* RTC Control 1 */ +#define pREG_RTC1_SR2 ((__IO uint16_t *) REG_RTC1_SR2) /* RTC Status 2 */ +#define pREG_RTC1_SNAP0 ((__I __C uint16_t *) REG_RTC1_SNAP0) /* RTC Snapshot 0 */ +#define pREG_RTC1_SNAP1 ((__I __C uint16_t *) REG_RTC1_SNAP1) /* RTC Snapshot 1 */ +#define pREG_RTC1_SNAP2 ((__I __C uint16_t *) REG_RTC1_SNAP2) /* RTC Snapshot 2 */ +#define pREG_RTC1_MOD ((__I __C uint16_t *) REG_RTC1_MOD) /* RTC Modulo */ +#define pREG_RTC1_CNT2 ((__I __C uint16_t *) REG_RTC1_CNT2) /* RTC Count 2 */ +#define pREG_RTC1_ALM2 ((__IO uint16_t *) REG_RTC1_ALM2) /* RTC Alarm 2 */ +#define pREG_RTC1_SR3 ((__IO uint16_t *) REG_RTC1_SR3) /* RTC Status 3 */ +#define pREG_RTC1_CR2IC ((__IO uint16_t *) REG_RTC1_CR2IC) /* RTC Control 2 for Configuring Input Capture Channels */ +#define pREG_RTC1_CR3SS ((__IO uint16_t *) REG_RTC1_CR3SS) /* RTC Control 3 for Configuring SensorStrobe Channel */ +#define pREG_RTC1_CR4SS ((__IO uint16_t *) REG_RTC1_CR4SS) /* RTC Control 4 for Configuring SensorStrobe Channel */ +#define pREG_RTC1_SSMSK ((__IO uint16_t *) REG_RTC1_SSMSK) /* RTC Mask for SensorStrobe Channel */ +#define pREG_RTC1_SS1ARL ((__IO uint16_t *) REG_RTC1_SS1ARL) /* RTC Auto-Reload for SensorStrobe Channel 1 */ +#define pREG_RTC1_IC2 ((__I __C uint16_t *) REG_RTC1_IC2) /* RTC Input Capture Channel 2 */ +#define pREG_RTC1_IC3 ((__I __C uint16_t *) REG_RTC1_IC3) /* RTC Input Capture Channel 3 */ +#define pREG_RTC1_IC4 ((__I __C uint16_t *) REG_RTC1_IC4) /* RTC Input Capture Channel 4 */ +#define pREG_RTC1_SS1 ((__IO uint16_t *) REG_RTC1_SS1) /* RTC SensorStrobe Channel 1 */ +#define pREG_RTC1_SR4 ((__I __C uint16_t *) REG_RTC1_SR4) /* RTC Status 4 */ +#define pREG_RTC1_SR5 ((__I __C uint16_t *) REG_RTC1_SR5) /* RTC Status 5 */ +#define pREG_RTC1_SR6 ((__I __C uint16_t *) REG_RTC1_SR6) /* RTC Status 6 */ +#define pREG_RTC1_SS1TGT ((__I __C uint16_t *) REG_RTC1_SS1TGT) /* RTC SensorStrobe Channel 1 Target */ +#define pREG_RTC1_FRZCNT ((__I __C uint16_t *) REG_RTC1_FRZCNT) /* RTC Freeze Count */ + +/* ================================================================================= + * System Identification and Debug Enable (SYS) + * ================================================================================= */ +#define pREG_SYS_ADIID ((__I __C uint16_t *) REG_SYS_ADIID) /* ADI Identification */ +#define pREG_SYS_CHIPID ((__I __C uint16_t *) REG_SYS_CHIPID) /* Chip Identifier */ +#define pREG_SYS_SWDEN ((__O uint16_t *) REG_SYS_SWDEN) /* Serial Wire Debug Enable */ + +/* ================================================================================= + * Watchdog Timer (WDT0) + * ================================================================================= */ +#define pREG_WDT0_LOAD ((__IO uint16_t *) REG_WDT0_LOAD) /* Load Value */ +#define pREG_WDT0_CCNT ((__I __C uint16_t *) REG_WDT0_CCNT) /* Current Count Value */ +#define pREG_WDT0_CTL ((__IO uint16_t *) REG_WDT0_CTL) /* Control */ +#define pREG_WDT0_RESTART ((__O uint16_t *) REG_WDT0_RESTART) /* Clear Interrupt */ +#define pREG_WDT0_STAT ((__I __C uint16_t *) REG_WDT0_STAT) /* Status */ + +/* ================================================================================= + * I2C Master/Slave (I2C0) + * ================================================================================= */ +#define pREG_I2C0_MCTL ((__IO uint16_t *) REG_I2C0_MCTL) /* Master Control */ +#define pREG_I2C0_MSTAT ((__IO uint16_t *) REG_I2C0_MSTAT) /* Master Status */ +#define pREG_I2C0_MRX ((__I __C uint16_t *) REG_I2C0_MRX) /* Master Receive Data */ +#define pREG_I2C0_MTX ((__IO uint16_t *) REG_I2C0_MTX) /* Master Transmit Data */ +#define pREG_I2C0_MRXCNT ((__IO uint16_t *) REG_I2C0_MRXCNT) /* Master Receive Data Count */ +#define pREG_I2C0_MCRXCNT ((__I __C uint16_t *) REG_I2C0_MCRXCNT) /* Master Current Receive Data Count */ +#define pREG_I2C0_ADDR1 ((__IO uint16_t *) REG_I2C0_ADDR1) /* Master Address Byte 1 */ +#define pREG_I2C0_ADDR2 ((__IO uint16_t *) REG_I2C0_ADDR2) /* Master Address Byte 2 */ +#define pREG_I2C0_BYT ((__IO uint16_t *) REG_I2C0_BYT) /* Start Byte */ +#define pREG_I2C0_DIV ((__IO uint16_t *) REG_I2C0_DIV) /* Serial Clock Period Divisor */ +#define pREG_I2C0_SCTL ((__IO uint16_t *) REG_I2C0_SCTL) /* Slave Control */ +#define pREG_I2C0_SSTAT ((__IO uint16_t *) REG_I2C0_SSTAT) /* Slave I2C Status/Error/IRQ */ +#define pREG_I2C0_SRX ((__I __C uint16_t *) REG_I2C0_SRX) /* Slave Receive */ +#define pREG_I2C0_STX ((__IO uint16_t *) REG_I2C0_STX) /* Slave Transmit */ +#define pREG_I2C0_ALT ((__IO uint16_t *) REG_I2C0_ALT) /* Hardware General Call ID */ +#define pREG_I2C0_ID0 ((__IO uint16_t *) REG_I2C0_ID0) /* First Slave Address Device ID */ +#define pREG_I2C0_ID1 ((__IO uint16_t *) REG_I2C0_ID1) /* Second Slave Address Device ID */ +#define pREG_I2C0_ID2 ((__IO uint16_t *) REG_I2C0_ID2) /* Third Slave Address Device ID */ +#define pREG_I2C0_ID3 ((__IO uint16_t *) REG_I2C0_ID3) /* Fourth Slave Address Device ID */ +#define pREG_I2C0_STAT ((__IO uint16_t *) REG_I2C0_STAT) /* Master and Slave FIFO Status */ +#define pREG_I2C0_SHCTL ((__O uint16_t *) REG_I2C0_SHCTL) /* Shared Control */ +#define pREG_I2C0_TCTL ((__IO uint16_t *) REG_I2C0_TCTL) /* Timing Control Register */ +#define pREG_I2C0_ASTRETCH_SCL ((__IO uint16_t *) REG_I2C0_ASTRETCH_SCL) /* Automatic Stretch SCL */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI0) + * ================================================================================= */ +#define pREG_SPI0_STAT ((__IO uint16_t *) REG_SPI0_STAT) /* Status */ +#define pREG_SPI0_RX ((__I __C uint16_t *) REG_SPI0_RX) /* Receive */ +#define pREG_SPI0_TX ((__O uint16_t *) REG_SPI0_TX) /* Transmit */ +#define pREG_SPI0_DIV ((__IO uint16_t *) REG_SPI0_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI0_CTL ((__IO uint16_t *) REG_SPI0_CTL) /* SPI Configuration */ +#define pREG_SPI0_IEN ((__IO uint16_t *) REG_SPI0_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI0_CNT ((__IO uint16_t *) REG_SPI0_CNT) /* Transfer Byte Count */ +#define pREG_SPI0_DMA ((__IO uint16_t *) REG_SPI0_DMA) /* SPI DMA Enable */ +#define pREG_SPI0_FIFO_STAT ((__I __C uint16_t *) REG_SPI0_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI0_RD_CTL ((__IO uint16_t *) REG_SPI0_RD_CTL) /* Read Control */ +#define pREG_SPI0_FLOW_CTL ((__IO uint16_t *) REG_SPI0_FLOW_CTL) /* Flow Control */ +#define pREG_SPI0_WAIT_TMR ((__IO uint16_t *) REG_SPI0_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI0_CS_CTL ((__IO uint16_t *) REG_SPI0_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI0_CS_OVERRIDE ((__IO uint16_t *) REG_SPI0_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI1) + * ================================================================================= */ +#define pREG_SPI1_STAT ((__IO uint16_t *) REG_SPI1_STAT) /* Status */ +#define pREG_SPI1_RX ((__I __C uint16_t *) REG_SPI1_RX) /* Receive */ +#define pREG_SPI1_TX ((__O uint16_t *) REG_SPI1_TX) /* Transmit */ +#define pREG_SPI1_DIV ((__IO uint16_t *) REG_SPI1_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI1_CTL ((__IO uint16_t *) REG_SPI1_CTL) /* SPI Configuration */ +#define pREG_SPI1_IEN ((__IO uint16_t *) REG_SPI1_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI1_CNT ((__IO uint16_t *) REG_SPI1_CNT) /* Transfer Byte Count */ +#define pREG_SPI1_DMA ((__IO uint16_t *) REG_SPI1_DMA) /* SPI DMA Enable */ +#define pREG_SPI1_FIFO_STAT ((__I __C uint16_t *) REG_SPI1_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI1_RD_CTL ((__IO uint16_t *) REG_SPI1_RD_CTL) /* Read Control */ +#define pREG_SPI1_FLOW_CTL ((__IO uint16_t *) REG_SPI1_FLOW_CTL) /* Flow Control */ +#define pREG_SPI1_WAIT_TMR ((__IO uint16_t *) REG_SPI1_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI1_CS_CTL ((__IO uint16_t *) REG_SPI1_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI1_CS_OVERRIDE ((__IO uint16_t *) REG_SPI1_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI2) + * ================================================================================= */ +#define pREG_SPI2_STAT ((__IO uint16_t *) REG_SPI2_STAT) /* Status */ +#define pREG_SPI2_RX ((__I __C uint16_t *) REG_SPI2_RX) /* Receive */ +#define pREG_SPI2_TX ((__O uint16_t *) REG_SPI2_TX) /* Transmit */ +#define pREG_SPI2_DIV ((__IO uint16_t *) REG_SPI2_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI2_CTL ((__IO uint16_t *) REG_SPI2_CTL) /* SPI Configuration */ +#define pREG_SPI2_IEN ((__IO uint16_t *) REG_SPI2_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI2_CNT ((__IO uint16_t *) REG_SPI2_CNT) /* Transfer Byte Count */ +#define pREG_SPI2_DMA ((__IO uint16_t *) REG_SPI2_DMA) /* SPI DMA Enable */ +#define pREG_SPI2_FIFO_STAT ((__I __C uint16_t *) REG_SPI2_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI2_RD_CTL ((__IO uint16_t *) REG_SPI2_RD_CTL) /* Read Control */ +#define pREG_SPI2_FLOW_CTL ((__IO uint16_t *) REG_SPI2_FLOW_CTL) /* Flow Control */ +#define pREG_SPI2_WAIT_TMR ((__IO uint16_t *) REG_SPI2_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI2_CS_CTL ((__IO uint16_t *) REG_SPI2_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI2_CS_OVERRIDE ((__IO uint16_t *) REG_SPI2_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * (UART0) + * ================================================================================= */ +#define pREG_UART0_TX ((__O uint16_t *) REG_UART0_TX) /* Transmit Holding Register */ +#define pREG_UART0_RX ((__I __C uint16_t *) REG_UART0_RX) /* Receive Buffer Register */ +#define pREG_UART0_IEN ((__IO uint16_t *) REG_UART0_IEN) /* Interrupt Enable */ +#define pREG_UART0_IIR ((__I __C uint16_t *) REG_UART0_IIR) /* Interrupt ID */ +#define pREG_UART0_LCR ((__IO uint16_t *) REG_UART0_LCR) /* Line Control */ +#define pREG_UART0_MCR ((__IO uint16_t *) REG_UART0_MCR) /* Modem Control */ +#define pREG_UART0_LSR ((__I __C uint16_t *) REG_UART0_LSR) /* Line Status */ +#define pREG_UART0_MSR ((__I __C uint16_t *) REG_UART0_MSR) /* Modem Status */ +#define pREG_UART0_SCR ((__IO uint16_t *) REG_UART0_SCR) /* Scratch Buffer */ +#define pREG_UART0_FCR ((__IO uint16_t *) REG_UART0_FCR) /* FIFO Control */ +#define pREG_UART0_FBR ((__IO uint16_t *) REG_UART0_FBR) /* Fractional Baud Rate */ +#define pREG_UART0_DIV ((__IO uint16_t *) REG_UART0_DIV) /* Baud Rate Divider */ +#define pREG_UART0_LCR2 ((__IO uint16_t *) REG_UART0_LCR2) /* Second Line Control */ +#define pREG_UART0_CTL ((__IO uint16_t *) REG_UART0_CTL) /* UART Control Register */ +#define pREG_UART0_RFC ((__I __C uint16_t *) REG_UART0_RFC) /* RX FIFO Byte Count */ +#define pREG_UART0_TFC ((__I __C uint16_t *) REG_UART0_TFC) /* TX FIFO Byte Count */ +#define pREG_UART0_RSC ((__IO uint16_t *) REG_UART0_RSC) /* RS485 Half-duplex Control */ +#define pREG_UART0_ACR ((__IO uint16_t *) REG_UART0_ACR) /* Auto Baud Control */ +#define pREG_UART0_ASRL ((__I __C uint16_t *) REG_UART0_ASRL) /* Auto Baud Status (Low) */ +#define pREG_UART0_ASRH ((__I __C uint16_t *) REG_UART0_ASRH) /* Auto Baud Status (High) */ + +/* ================================================================================= + * Beeper Driver (BEEP0) + * ================================================================================= */ +#define pREG_BEEP0_CFG ((__IO uint16_t *) REG_BEEP0_CFG) /* Beeper Configuration */ +#define pREG_BEEP0_STAT ((__IO uint16_t *) REG_BEEP0_STAT) /* Beeper Status */ +#define pREG_BEEP0_TONEA ((__IO uint16_t *) REG_BEEP0_TONEA) /* Tone A Data */ +#define pREG_BEEP0_TONEB ((__IO uint16_t *) REG_BEEP0_TONEB) /* Tone B Data */ + +/* ================================================================================= + * (ADC0) + * ================================================================================= */ +#define pREG_ADC0_CFG ((__IO uint16_t *) REG_ADC0_CFG) /* ADC Configuration */ +#define pREG_ADC0_PWRUP ((__IO uint16_t *) REG_ADC0_PWRUP) /* ADC Power-up Time */ +#define pREG_ADC0_CAL_WORD ((__IO uint16_t *) REG_ADC0_CAL_WORD) /* Calibration Word */ +#define pREG_ADC0_CNV_CFG ((__IO uint16_t *) REG_ADC0_CNV_CFG) /* ADC Conversion Configuration */ +#define pREG_ADC0_CNV_TIME ((__IO uint16_t *) REG_ADC0_CNV_TIME) /* ADC Conversion Time */ +#define pREG_ADC0_AVG_CFG ((__IO uint16_t *) REG_ADC0_AVG_CFG) /* Averaging Configuration */ +#define pREG_ADC0_IRQ_EN ((__IO uint16_t *) REG_ADC0_IRQ_EN) /* Interrupt Enable */ +#define pREG_ADC0_STAT ((__IO uint16_t *) REG_ADC0_STAT) /* ADC Status */ +#define pREG_ADC0_OVF ((__IO uint16_t *) REG_ADC0_OVF) /* Overflow of Output Registers */ +#define pREG_ADC0_ALERT ((__IO uint16_t *) REG_ADC0_ALERT) /* Alert Indication */ +#define pREG_ADC0_CH0_OUT ((__I __C uint16_t *) REG_ADC0_CH0_OUT) /* Conversion Result Channel 0 */ +#define pREG_ADC0_CH1_OUT ((__I __C uint16_t *) REG_ADC0_CH1_OUT) /* Conversion Result Channel 1 */ +#define pREG_ADC0_CH2_OUT ((__I __C uint16_t *) REG_ADC0_CH2_OUT) /* Conversion Result Channel 2 */ +#define pREG_ADC0_CH3_OUT ((__I __C uint16_t *) REG_ADC0_CH3_OUT) /* Conversion Result Channel 3 */ +#define pREG_ADC0_CH4_OUT ((__I __C uint16_t *) REG_ADC0_CH4_OUT) /* Conversion Result Channel 4 */ +#define pREG_ADC0_CH5_OUT ((__I __C uint16_t *) REG_ADC0_CH5_OUT) /* Conversion Result Channel 5 */ +#define pREG_ADC0_CH6_OUT ((__I __C uint16_t *) REG_ADC0_CH6_OUT) /* Conversion Result Channel 6 */ +#define pREG_ADC0_CH7_OUT ((__I __C uint16_t *) REG_ADC0_CH7_OUT) /* Conversion Result Channel 7 */ +#define pREG_ADC0_BAT_OUT ((__I __C uint16_t *) REG_ADC0_BAT_OUT) /* Battery Monitoring Result */ +#define pREG_ADC0_TMP_OUT ((__I __C uint16_t *) REG_ADC0_TMP_OUT) /* Temperature Result */ +#define pREG_ADC0_TMP2_OUT ((__I __C uint16_t *) REG_ADC0_TMP2_OUT) /* Temperature Result 2 */ +#define pREG_ADC0_DMA_OUT ((__I __C uint16_t *) REG_ADC0_DMA_OUT) /* DMA Output Register */ +#define pREG_ADC0_LIM0_LO ((__IO uint16_t *) REG_ADC0_LIM0_LO) /* Channel 0 Low Limit */ +#define pREG_ADC0_LIM0_HI ((__IO uint16_t *) REG_ADC0_LIM0_HI) /* Channel 0 High Limit */ +#define pREG_ADC0_HYS0 ((__IO uint16_t *) REG_ADC0_HYS0) /* Channel 0 Hysteresis */ +#define pREG_ADC0_LIM1_LO ((__IO uint16_t *) REG_ADC0_LIM1_LO) /* Channel 1 Low Limit */ +#define pREG_ADC0_LIM1_HI ((__IO uint16_t *) REG_ADC0_LIM1_HI) /* Channel 1 High Limit */ +#define pREG_ADC0_HYS1 ((__IO uint16_t *) REG_ADC0_HYS1) /* Channel 1 Hysteresis */ +#define pREG_ADC0_LIM2_LO ((__IO uint16_t *) REG_ADC0_LIM2_LO) /* Channel 2 Low Limit */ +#define pREG_ADC0_LIM2_HI ((__IO uint16_t *) REG_ADC0_LIM2_HI) /* Channel 2 High Limit */ +#define pREG_ADC0_HYS2 ((__IO uint16_t *) REG_ADC0_HYS2) /* Channel 2 Hysteresis */ +#define pREG_ADC0_LIM3_LO ((__IO uint16_t *) REG_ADC0_LIM3_LO) /* Channel 3 Low Limit */ +#define pREG_ADC0_LIM3_HI ((__IO uint16_t *) REG_ADC0_LIM3_HI) /* Channel 3 High Limit */ +#define pREG_ADC0_HYS3 ((__IO uint16_t *) REG_ADC0_HYS3) /* Channel 3 Hysteresis */ +#define pREG_ADC0_CFG1 ((__IO uint16_t *) REG_ADC0_CFG1) /* Reference Buffer Low Power Mode */ + +/* ================================================================================= + * DMA (DMA0) + * ================================================================================= */ +#define pREG_DMA0_STAT ((__I __C uint32_t *) REG_DMA0_STAT) /* DMA Status */ +#define pREG_DMA0_CFG ((__O uint32_t *) REG_DMA0_CFG) /* DMA Configuration */ +#define pREG_DMA0_PDBPTR ((__IO uint32_t *) REG_DMA0_PDBPTR) /* DMA Channel Primary Control Database Pointer */ +#define pREG_DMA0_ADBPTR ((__I __C uint32_t *) REG_DMA0_ADBPTR) /* DMA Channel Alternate Control Database Pointer */ +#define pREG_DMA0_SWREQ ((__O uint32_t *) REG_DMA0_SWREQ) /* DMA Channel Software Request */ +#define pREG_DMA0_RMSK_SET ((__IO uint32_t *) REG_DMA0_RMSK_SET) /* DMA Channel Request Mask Set */ +#define pREG_DMA0_RMSK_CLR ((__O uint32_t *) REG_DMA0_RMSK_CLR) /* DMA Channel Request Mask Clear */ +#define pREG_DMA0_EN_SET ((__IO uint32_t *) REG_DMA0_EN_SET) /* DMA Channel Enable Set */ +#define pREG_DMA0_EN_CLR ((__O uint32_t *) REG_DMA0_EN_CLR) /* DMA Channel Enable Clear */ +#define pREG_DMA0_ALT_SET ((__IO uint32_t *) REG_DMA0_ALT_SET) /* DMA Channel Primary Alternate Set */ +#define pREG_DMA0_ALT_CLR ((__O uint32_t *) REG_DMA0_ALT_CLR) /* DMA Channel Primary Alternate Clear */ +#define pREG_DMA0_PRI_SET ((__O uint32_t *) REG_DMA0_PRI_SET) /* DMA Channel Priority Set */ +#define pREG_DMA0_PRI_CLR ((__O uint32_t *) REG_DMA0_PRI_CLR) /* DMA Channel Priority Clear */ +#define pREG_DMA0_ERRCHNL_CLR ((__IO uint32_t *) REG_DMA0_ERRCHNL_CLR) /* DMA per Channel Error Clear */ +#define pREG_DMA0_ERR_CLR ((__IO uint32_t *) REG_DMA0_ERR_CLR) /* DMA Bus Error Clear */ +#define pREG_DMA0_INVALIDDESC_CLR ((__IO uint32_t *) REG_DMA0_INVALIDDESC_CLR) /* DMA per Channel Invalid Descriptor Clear */ +#define pREG_DMA0_BS_SET ((__IO uint32_t *) REG_DMA0_BS_SET) /* DMA Channel Bytes Swap Enable Set */ +#define pREG_DMA0_BS_CLR ((__O uint32_t *) REG_DMA0_BS_CLR) /* DMA Channel Bytes Swap Enable Clear */ +#define pREG_DMA0_SRCADDR_SET ((__IO uint32_t *) REG_DMA0_SRCADDR_SET) /* DMA Channel Source Address Decrement Enable Set */ +#define pREG_DMA0_SRCADDR_CLR ((__O uint32_t *) REG_DMA0_SRCADDR_CLR) /* DMA Channel Source Address Decrement Enable Clear */ +#define pREG_DMA0_DSTADDR_SET ((__IO uint32_t *) REG_DMA0_DSTADDR_SET) /* DMA Channel Destination Address Decrement Enable Set */ +#define pREG_DMA0_DSTADDR_CLR ((__O uint32_t *) REG_DMA0_DSTADDR_CLR) /* DMA Channel Destination Address Decrement Enable Clear */ +#define pREG_DMA0_REVID ((__I __C uint32_t *) REG_DMA0_REVID) /* DMA Controller Revision ID */ + +/* ================================================================================= + * Flash Controller (FLCC0) + * ================================================================================= */ +#define pREG_FLCC0_STAT ((__IO uint32_t *) REG_FLCC0_STAT) /* Status */ +#define pREG_FLCC0_IEN ((__IO uint32_t *) REG_FLCC0_IEN) /* Interrupt Enable */ +#define pREG_FLCC0_CMD ((__IO uint32_t *) REG_FLCC0_CMD) /* Command */ +#define pREG_FLCC0_KH_ADDR ((__IO uint32_t *) REG_FLCC0_KH_ADDR) /* Write Address */ +#define pREG_FLCC0_KH_DATA0 ((__IO uint32_t *) REG_FLCC0_KH_DATA0) /* Write Lower Data */ +#define pREG_FLCC0_KH_DATA1 ((__IO uint32_t *) REG_FLCC0_KH_DATA1) /* Write Upper Data */ +#define pREG_FLCC0_PAGE_ADDR0 ((__IO uint32_t *) REG_FLCC0_PAGE_ADDR0) /* Lower Page Address */ +#define pREG_FLCC0_PAGE_ADDR1 ((__IO uint32_t *) REG_FLCC0_PAGE_ADDR1) /* Upper Page Address */ +#define pREG_FLCC0_KEY ((__O uint32_t *) REG_FLCC0_KEY) /* Key */ +#define pREG_FLCC0_WR_ABORT_ADDR ((__I __C uint32_t *) REG_FLCC0_WR_ABORT_ADDR) /* Write Abort Address */ +#define pREG_FLCC0_WRPROT ((__IO uint32_t *) REG_FLCC0_WRPROT) /* Write Protection */ +#define pREG_FLCC0_SIGNATURE ((__I __C uint32_t *) REG_FLCC0_SIGNATURE) /* Signature */ +#define pREG_FLCC0_UCFG ((__IO uint32_t *) REG_FLCC0_UCFG) /* User Configuration */ +#define pREG_FLCC0_TIME_PARAM0 ((__IO uint32_t *) REG_FLCC0_TIME_PARAM0) /* Time Parameter 0 */ +#define pREG_FLCC0_TIME_PARAM1 ((__IO uint32_t *) REG_FLCC0_TIME_PARAM1) /* Time Parameter 1 */ +#define pREG_FLCC0_ABORT_EN_LO ((__IO uint32_t *) REG_FLCC0_ABORT_EN_LO) /* IRQ Abort Enable (Lower Bits) */ +#define pREG_FLCC0_ABORT_EN_HI ((__IO uint32_t *) REG_FLCC0_ABORT_EN_HI) /* IRQ Abort Enable (Upper Bits) */ +#define pREG_FLCC0_ECC_CFG ((__IO uint32_t *) REG_FLCC0_ECC_CFG) /* ECC Configuration */ +#define pREG_FLCC0_ECC_ADDR ((__I __C uint32_t *) REG_FLCC0_ECC_ADDR) /* ECC Status (Address) */ +#define pREG_FLCC0_POR_SEC ((__IO uint32_t *) REG_FLCC0_POR_SEC) /* Flash Security */ +#define pREG_FLCC0_VOL_CFG ((__IO uint32_t *) REG_FLCC0_VOL_CFG) /* Volatile Flash Configuration */ + +/* ================================================================================= + * Cache Controller (FLCC0_CACHE) + * ================================================================================= */ +#define pREG_FLCC0_CACHE_STAT ((__I __C uint32_t *) REG_FLCC0_CACHE_STAT) /* Cache Status */ +#define pREG_FLCC0_CACHE_SETUP ((__IO uint32_t *) REG_FLCC0_CACHE_SETUP) /* Cache Setup */ +#define pREG_FLCC0_CACHE_KEY ((__O uint32_t *) REG_FLCC0_CACHE_KEY) /* Cache Key */ + +/* ================================================================================= + * (GPIO0) + * ================================================================================= */ +#define pREG_GPIO0_CFG ((__IO uint32_t *) REG_GPIO0_CFG) /* Port Configuration */ +#define pREG_GPIO0_OEN ((__IO uint16_t *) REG_GPIO0_OEN) /* Port Output Enable */ +#define pREG_GPIO0_PE ((__IO uint16_t *) REG_GPIO0_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO0_IEN ((__IO uint16_t *) REG_GPIO0_IEN) /* Port Input Path Enable */ +#define pREG_GPIO0_IN ((__I __C uint16_t *) REG_GPIO0_IN) /* Port Registered Data Input */ +#define pREG_GPIO0_OUT ((__IO uint16_t *) REG_GPIO0_OUT) /* Port Data Output */ +#define pREG_GPIO0_SET ((__O uint16_t *) REG_GPIO0_SET) /* Port Data Out Set */ +#define pREG_GPIO0_CLR ((__O uint16_t *) REG_GPIO0_CLR) /* Port Data Out Clear */ +#define pREG_GPIO0_TGL ((__O uint16_t *) REG_GPIO0_TGL) /* Port Pin Toggle */ +#define pREG_GPIO0_POL ((__IO uint16_t *) REG_GPIO0_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO0_IENA ((__IO uint16_t *) REG_GPIO0_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO0_IENB ((__IO uint16_t *) REG_GPIO0_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO0_INT ((__IO uint16_t *) REG_GPIO0_INT) /* Port Interrupt Status */ +#define pREG_GPIO0_DS ((__IO uint16_t *) REG_GPIO0_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO1) + * ================================================================================= */ +#define pREG_GPIO1_CFG ((__IO uint32_t *) REG_GPIO1_CFG) /* Port Configuration */ +#define pREG_GPIO1_OEN ((__IO uint16_t *) REG_GPIO1_OEN) /* Port Output Enable */ +#define pREG_GPIO1_PE ((__IO uint16_t *) REG_GPIO1_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO1_IEN ((__IO uint16_t *) REG_GPIO1_IEN) /* Port Input Path Enable */ +#define pREG_GPIO1_IN ((__I __C uint16_t *) REG_GPIO1_IN) /* Port Registered Data Input */ +#define pREG_GPIO1_OUT ((__IO uint16_t *) REG_GPIO1_OUT) /* Port Data Output */ +#define pREG_GPIO1_SET ((__O uint16_t *) REG_GPIO1_SET) /* Port Data Out Set */ +#define pREG_GPIO1_CLR ((__O uint16_t *) REG_GPIO1_CLR) /* Port Data Out Clear */ +#define pREG_GPIO1_TGL ((__O uint16_t *) REG_GPIO1_TGL) /* Port Pin Toggle */ +#define pREG_GPIO1_POL ((__IO uint16_t *) REG_GPIO1_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO1_IENA ((__IO uint16_t *) REG_GPIO1_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO1_IENB ((__IO uint16_t *) REG_GPIO1_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO1_INT ((__IO uint16_t *) REG_GPIO1_INT) /* Port Interrupt Status */ +#define pREG_GPIO1_DS ((__IO uint16_t *) REG_GPIO1_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO2) + * ================================================================================= */ +#define pREG_GPIO2_CFG ((__IO uint32_t *) REG_GPIO2_CFG) /* Port Configuration */ +#define pREG_GPIO2_OEN ((__IO uint16_t *) REG_GPIO2_OEN) /* Port Output Enable */ +#define pREG_GPIO2_PE ((__IO uint16_t *) REG_GPIO2_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO2_IEN ((__IO uint16_t *) REG_GPIO2_IEN) /* Port Input Path Enable */ +#define pREG_GPIO2_IN ((__I __C uint16_t *) REG_GPIO2_IN) /* Port Registered Data Input */ +#define pREG_GPIO2_OUT ((__IO uint16_t *) REG_GPIO2_OUT) /* Port Data Output */ +#define pREG_GPIO2_SET ((__O uint16_t *) REG_GPIO2_SET) /* Port Data Out Set */ +#define pREG_GPIO2_CLR ((__O uint16_t *) REG_GPIO2_CLR) /* Port Data Out Clear */ +#define pREG_GPIO2_TGL ((__O uint16_t *) REG_GPIO2_TGL) /* Port Pin Toggle */ +#define pREG_GPIO2_POL ((__IO uint16_t *) REG_GPIO2_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO2_IENA ((__IO uint16_t *) REG_GPIO2_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO2_IENB ((__IO uint16_t *) REG_GPIO2_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO2_INT ((__IO uint16_t *) REG_GPIO2_INT) /* Port Interrupt Status */ +#define pREG_GPIO2_DS ((__IO uint16_t *) REG_GPIO2_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * Serial Port (SPORT0) + * ================================================================================= */ +#define pREG_SPORT0_CTL_A ((__IO uint32_t *) REG_SPORT0_CTL_A) /* Half SPORT 'A' Control */ +#define pREG_SPORT0_DIV_A ((__IO uint32_t *) REG_SPORT0_DIV_A) /* Half SPORT 'A' Divisor */ +#define pREG_SPORT0_IEN_A ((__IO uint32_t *) REG_SPORT0_IEN_A) /* Half SPORT A's Interrupt Enable */ +#define pREG_SPORT0_STAT_A ((__IO uint32_t *) REG_SPORT0_STAT_A) /* Half SPORT A's Status */ +#define pREG_SPORT0_NUMTRAN_A ((__IO uint32_t *) REG_SPORT0_NUMTRAN_A) /* Half SPORT A Number of Transfers */ +#define pREG_SPORT0_CNVT_A ((__IO uint32_t *) REG_SPORT0_CNVT_A) /* Half SPORT 'A' CNV Width */ +#define pREG_SPORT0_TX_A ((__O uint32_t *) REG_SPORT0_TX_A) /* Half SPORT 'A' Tx Buffer */ +#define pREG_SPORT0_RX_A ((__I __C uint32_t *) REG_SPORT0_RX_A) /* Half SPORT 'A' Rx Buffer */ +#define pREG_SPORT0_CTL_B ((__IO uint32_t *) REG_SPORT0_CTL_B) /* Half SPORT 'B' Control */ +#define pREG_SPORT0_DIV_B ((__IO uint32_t *) REG_SPORT0_DIV_B) /* Half SPORT 'B' Divisor */ +#define pREG_SPORT0_IEN_B ((__IO uint32_t *) REG_SPORT0_IEN_B) /* Half SPORT B's Interrupt Enable */ +#define pREG_SPORT0_STAT_B ((__IO uint32_t *) REG_SPORT0_STAT_B) /* Half SPORT B's Status */ +#define pREG_SPORT0_NUMTRAN_B ((__IO uint32_t *) REG_SPORT0_NUMTRAN_B) /* Half SPORT B Number of Transfers */ +#define pREG_SPORT0_CNVT_B ((__IO uint32_t *) REG_SPORT0_CNVT_B) /* Half SPORT 'B' CNV Width */ +#define pREG_SPORT0_TX_B ((__O uint32_t *) REG_SPORT0_TX_B) /* Half SPORT 'B' Tx Buffer */ +#define pREG_SPORT0_RX_B ((__I __C uint32_t *) REG_SPORT0_RX_B) /* Half SPORT 'B' Rx Buffer */ + +/* ================================================================================= + * CRC Accelerator (CRC0) + * ================================================================================= */ +#define pREG_CRC0_CTL ((__IO uint32_t *) REG_CRC0_CTL) /* CRC Control */ +#define pREG_CRC0_IPDATA ((__O uint32_t *) REG_CRC0_IPDATA) /* Input Data Word */ +#define pREG_CRC0_RESULT ((__IO uint32_t *) REG_CRC0_RESULT) /* CRC Result */ +#define pREG_CRC0_POLY ((__IO uint32_t *) REG_CRC0_POLY) /* Programmable CRC Polynomial */ +#define pREG_CRC0_IPBYTE ((__O uint8_t *) REG_CRC0_IPBYTE) /* Input Data Byte */ +#define pREG_CRC0_IPBITS0 ((__O uint8_t *) REG_CRC0_IPBITS0) /* Input Data Bits */ +#define pREG_CRC0_IPBITS1 ((__O uint8_t *) REG_CRC0_IPBITS1) /* Input Data Bits */ +#define pREG_CRC0_IPBITS2 ((__O uint8_t *) REG_CRC0_IPBITS2) /* Input Data Bits */ +#define pREG_CRC0_IPBITS3 ((__O uint8_t *) REG_CRC0_IPBITS3) /* Input Data Bits */ +#define pREG_CRC0_IPBITS4 ((__O uint8_t *) REG_CRC0_IPBITS4) /* Input Data Bits */ +#define pREG_CRC0_IPBITS5 ((__O uint8_t *) REG_CRC0_IPBITS5) /* Input Data Bits */ +#define pREG_CRC0_IPBITS6 ((__O uint8_t *) REG_CRC0_IPBITS6) /* Input Data Bits */ +#define pREG_CRC0_IPBITS7 ((__O uint8_t *) REG_CRC0_IPBITS7) /* Input Data Bits */ + +/* ================================================================================= + * Random Number Generator (RNG0) + * ================================================================================= */ +#define pREG_RNG0_CTL ((__IO uint16_t *) REG_RNG0_CTL) /* RNG Control Register */ +#define pREG_RNG0_LEN ((__IO uint16_t *) REG_RNG0_LEN) /* RNG Sample Length Register */ +#define pREG_RNG0_STAT ((__IO uint16_t *) REG_RNG0_STAT) /* RNG Status Register */ +#define pREG_RNG0_DATA ((__I __C uint32_t *) REG_RNG0_DATA) /* RNG Data Register */ +#define pREG_RNG0_OSCCNT ((__I __C uint32_t *) REG_RNG0_OSCCNT) /* Oscillator Count */ +#define pREG_RNG0_OSCDIFF0 ((__I __C int8_t *) REG_RNG0_OSCDIFF0) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF1 ((__I __C int8_t *) REG_RNG0_OSCDIFF1) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF2 ((__I __C int8_t *) REG_RNG0_OSCDIFF2) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF3 ((__I __C int8_t *) REG_RNG0_OSCDIFF3) /* Oscillator Difference */ + +/* ================================================================================= + * Register Map for the Crypto Block (CRYPT0) + * ================================================================================= */ +#define pREG_CRYPT0_CFG ((__IO uint32_t *) REG_CRYPT0_CFG) /* Configuration Register */ +#define pREG_CRYPT0_DATALEN ((__IO uint32_t *) REG_CRYPT0_DATALEN) /* Payload Data Length */ +#define pREG_CRYPT0_PREFIXLEN ((__IO uint32_t *) REG_CRYPT0_PREFIXLEN) /* Authentication Data Length */ +#define pREG_CRYPT0_INTEN ((__IO uint32_t *) REG_CRYPT0_INTEN) /* Interrupt Enable Register */ +#define pREG_CRYPT0_STAT ((__IO uint32_t *) REG_CRYPT0_STAT) /* Status Register */ +#define pREG_CRYPT0_INBUF ((__O uint32_t *) REG_CRYPT0_INBUF) /* Input Buffer */ +#define pREG_CRYPT0_OUTBUF ((__I __C uint32_t *) REG_CRYPT0_OUTBUF) /* Output Buffer */ +#define pREG_CRYPT0_NONCE0 ((__IO uint32_t *) REG_CRYPT0_NONCE0) /* Nonce Bits [31:0] */ +#define pREG_CRYPT0_NONCE1 ((__IO uint32_t *) REG_CRYPT0_NONCE1) /* Nonce Bits [63:32] */ +#define pREG_CRYPT0_NONCE2 ((__IO uint32_t *) REG_CRYPT0_NONCE2) /* Nonce Bits [95:64] */ +#define pREG_CRYPT0_NONCE3 ((__IO uint32_t *) REG_CRYPT0_NONCE3) /* Nonce Bits [127:96] */ +#define pREG_CRYPT0_AESKEY0 ((__O uint32_t *) REG_CRYPT0_AESKEY0) /* AES Key Bits [31:0] */ +#define pREG_CRYPT0_AESKEY1 ((__O uint32_t *) REG_CRYPT0_AESKEY1) /* AES Key Bits [63:32] */ +#define pREG_CRYPT0_AESKEY2 ((__O uint32_t *) REG_CRYPT0_AESKEY2) /* AES Key Bits [95:64] */ +#define pREG_CRYPT0_AESKEY3 ((__O uint32_t *) REG_CRYPT0_AESKEY3) /* AES Key Bits [127:96] */ +#define pREG_CRYPT0_AESKEY4 ((__O uint32_t *) REG_CRYPT0_AESKEY4) /* AES Key Bits [159:128] */ +#define pREG_CRYPT0_AESKEY5 ((__O uint32_t *) REG_CRYPT0_AESKEY5) /* AES Key Bits [191:160] */ +#define pREG_CRYPT0_AESKEY6 ((__O uint32_t *) REG_CRYPT0_AESKEY6) /* AES Key Bits [223:192] */ +#define pREG_CRYPT0_AESKEY7 ((__O uint32_t *) REG_CRYPT0_AESKEY7) /* AES Key Bits [255:224] */ +#define pREG_CRYPT0_CNTRINIT ((__IO uint32_t *) REG_CRYPT0_CNTRINIT) /* Counter Initialization Vector */ +#define pREG_CRYPT0_SHAH0 ((__IO uint32_t *) REG_CRYPT0_SHAH0) /* SHA Bits [31:0] */ +#define pREG_CRYPT0_SHAH1 ((__IO uint32_t *) REG_CRYPT0_SHAH1) /* SHA Bits [63:32] */ +#define pREG_CRYPT0_SHAH2 ((__IO uint32_t *) REG_CRYPT0_SHAH2) /* SHA Bits [95:64] */ +#define pREG_CRYPT0_SHAH3 ((__IO uint32_t *) REG_CRYPT0_SHAH3) /* SHA Bits [127:96] */ +#define pREG_CRYPT0_SHAH4 ((__IO uint32_t *) REG_CRYPT0_SHAH4) /* SHA Bits [159:128] */ +#define pREG_CRYPT0_SHAH5 ((__IO uint32_t *) REG_CRYPT0_SHAH5) /* SHA Bits [191:160] */ +#define pREG_CRYPT0_SHAH6 ((__IO uint32_t *) REG_CRYPT0_SHAH6) /* SHA Bits [223:192] */ +#define pREG_CRYPT0_SHAH7 ((__IO uint32_t *) REG_CRYPT0_SHAH7) /* SHA Bits [255:224] */ +#define pREG_CRYPT0_SHA_LAST_WORD ((__IO uint32_t *) REG_CRYPT0_SHA_LAST_WORD) /* SHA Last Word and Valid Bits Information */ +#define pREG_CRYPT0_CCM_NUM_VALID_BYTES ((__IO uint32_t *) REG_CRYPT0_CCM_NUM_VALID_BYTES) /* NUM_VALID_BYTES */ + +/* ================================================================================= + * Power Management (PMG0) + * ================================================================================= */ +#define pREG_PMG0_IEN ((__IO uint32_t *) REG_PMG0_IEN) /* Power Supply Monitor Interrupt Enable */ +#define pREG_PMG0_PSM_STAT ((__IO uint32_t *) REG_PMG0_PSM_STAT) /* Power Supply Monitor Status */ +#define pREG_PMG0_PWRMOD ((__IO uint32_t *) REG_PMG0_PWRMOD) /* Power Mode Register */ +#define pREG_PMG0_PWRKEY ((__O uint32_t *) REG_PMG0_PWRKEY) /* Key Protection for PWRMOD and SRAMRET */ +#define pREG_PMG0_SHDN_STAT ((__I __C uint32_t *) REG_PMG0_SHDN_STAT) /* Shutdown Status Register */ +#define pREG_PMG0_SRAMRET ((__IO uint32_t *) REG_PMG0_SRAMRET) /* Control for Retention SRAM in Hibernate Mode */ +#define pREG_PMG0_RST_STAT ((__IO uint32_t *) REG_PMG0_RST_STAT) /* Reset Status */ +#define pREG_PMG0_CTL1 ((__IO uint32_t *) REG_PMG0_CTL1) /* HP Buck Control */ + +/* ================================================================================= + * External interrupt configuration (XINT0) + * ================================================================================= */ +#define pREG_XINT0_CFG0 ((__IO uint32_t *) REG_XINT0_CFG0) /* External Interrupt Configuration */ +#define pREG_XINT0_EXT_STAT ((__I __C uint32_t *) REG_XINT0_EXT_STAT) /* External Wakeup Interrupt Status */ +#define pREG_XINT0_CLR ((__IO uint32_t *) REG_XINT0_CLR) /* External Interrupt Clear */ +#define pREG_XINT0_NMICLR ((__IO uint32_t *) REG_XINT0_NMICLR) /* Non-Maskable Interrupt Clear */ + +/* ================================================================================= + * Clocking (CLKG0_OSC) + * ================================================================================= */ +#define pREG_CLKG0_OSC_KEY ((__O uint32_t *) REG_CLKG0_OSC_KEY) /* Key Protection for CLKG_OSC_CTL */ +#define pREG_CLKG0_OSC_CTL ((__IO uint32_t *) REG_CLKG0_OSC_CTL) /* Oscillator Control */ + +/* ================================================================================= + * Power Management (PMG0_TST) + * ================================================================================= */ +#define pREG_PMG0_TST_SRAM_CTL ((__IO uint32_t *) REG_PMG0_TST_SRAM_CTL) /* Control for SRAM Parity and Instruction SRAM */ +#define pREG_PMG0_TST_SRAM_INITSTAT ((__IO uint32_t *) REG_PMG0_TST_SRAM_INITSTAT) /* Initialization Status Register */ +#define pREG_PMG0_TST_CLR_LATCH_GPIOS ((__O uint16_t *) REG_PMG0_TST_CLR_LATCH_GPIOS) /* Clear GPIO After Shutdown Mode */ +#define pREG_PMG0_TST_SCRPAD_IMG ((__IO uint32_t *) REG_PMG0_TST_SCRPAD_IMG) /* Scratch Pad Image */ +#define pREG_PMG0_TST_SCRPAD_3V_RD ((__I __C uint32_t *) REG_PMG0_TST_SCRPAD_3V_RD) /* Scratch Pad Saved in Battery Domain */ + +/* ================================================================================= + * Clocking (CLKG0_CLK) + * ================================================================================= */ +#define pREG_CLKG0_CLK_CTL0 ((__IO uint32_t *) REG_CLKG0_CLK_CTL0) /* Miscellaneous Clock Settings */ +#define pREG_CLKG0_CLK_CTL1 ((__IO uint32_t *) REG_CLKG0_CLK_CTL1) /* Clock Dividers */ +#define pREG_CLKG0_CLK_CTL3 ((__IO uint32_t *) REG_CLKG0_CLK_CTL3) /* System PLL */ +#define pREG_CLKG0_CLK_CTL5 ((__IO uint32_t *) REG_CLKG0_CLK_CTL5) /* User Clock Gating Control */ +#define pREG_CLKG0_CLK_STAT0 ((__IO uint32_t *) REG_CLKG0_CLK_STAT0) /* Clocking Status */ + +/* ================================================================================= + * Bus matrix (BUSM0) + * ================================================================================= */ +#define pREG_BUSM0_ARBIT0 ((__IO uint32_t *) REG_BUSM0_ARBIT0) /* Arbitration Priority Configuration for FLASH and SRAM0 */ +#define pREG_BUSM0_ARBIT1 ((__IO uint32_t *) REG_BUSM0_ARBIT1) /* Arbitration Priority Configuration for SRAM1 and SIP */ +#define pREG_BUSM0_ARBIT2 ((__IO uint32_t *) REG_BUSM0_ARBIT2) /* Arbitration Priority Configuration for APB32 and APB16 */ +#define pREG_BUSM0_ARBIT3 ((__IO uint32_t *) REG_BUSM0_ARBIT3) /* Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ + +/* ================================================================================= + * Parallel Test Interface (PTI0) + * ================================================================================= */ +#define pREG_PTI0_RST_ISR_STARTADDR ((__IO uint32_t *) REG_PTI0_RST_ISR_STARTADDR) /* Reset ISR Start Address */ +#define pREG_PTI0_RST_STACK_PTR ((__IO uint32_t *) REG_PTI0_RST_STACK_PTR) /* Reset Stack Pointer */ +#define pREG_PTI0_CTL ((__IO uint32_t *) REG_PTI0_CTL) /* Parallel Test Interface Control Register */ + +/* ================================================================================= + * Cortex-M3 Interrupt Controller (NVIC0) + * ================================================================================= */ +#define pREG_NVIC0_INTNUM ((__IO uint32_t *) REG_NVIC0_INTNUM) /* Interrupt Control Type */ +#define pREG_NVIC0_STKSTA ((__IO uint32_t *) REG_NVIC0_STKSTA) /* Systick Control and Status */ +#define pREG_NVIC0_STKLD ((__IO uint32_t *) REG_NVIC0_STKLD) /* Systick Reload Value */ +#define pREG_NVIC0_STKVAL ((__IO uint32_t *) REG_NVIC0_STKVAL) /* Systick Current Value */ +#define pREG_NVIC0_STKCAL ((__IO uint32_t *) REG_NVIC0_STKCAL) /* Systick Calibration Value */ +#define pREG_NVIC0_INTSETE0 ((__IO uint32_t *) REG_NVIC0_INTSETE0) /* IRQ0..31 Set_Enable */ +#define pREG_NVIC0_INTSETE1 ((__IO uint32_t *) REG_NVIC0_INTSETE1) /* IRQ32..63 Set_Enable */ +#define pREG_NVIC0_INTCLRE0 ((__IO uint32_t *) REG_NVIC0_INTCLRE0) /* IRQ0..31 Clear_Enable */ +#define pREG_NVIC0_INTCLRE1 ((__IO uint32_t *) REG_NVIC0_INTCLRE1) /* IRQ32..63 Clear_Enable */ +#define pREG_NVIC0_INTSETP0 ((__IO uint32_t *) REG_NVIC0_INTSETP0) /* IRQ0..31 Set_Pending */ +#define pREG_NVIC0_INTSETP1 ((__IO uint32_t *) REG_NVIC0_INTSETP1) /* IRQ32..63 Set_Pending */ +#define pREG_NVIC0_INTCLRP0 ((__IO uint32_t *) REG_NVIC0_INTCLRP0) /* IRQ0..31 Clear_Pending */ +#define pREG_NVIC0_INTCLRP1 ((__IO uint32_t *) REG_NVIC0_INTCLRP1) /* IRQ32..63 Clear_Pending */ +#define pREG_NVIC0_INTACT0 ((__IO uint32_t *) REG_NVIC0_INTACT0) /* IRQ0..31 Active Bit */ +#define pREG_NVIC0_INTACT1 ((__IO uint32_t *) REG_NVIC0_INTACT1) /* IRQ32..63 Active Bit */ +#define pREG_NVIC0_INTPRI0 ((__IO uint32_t *) REG_NVIC0_INTPRI0) /* IRQ0..3 Priority */ +#define pREG_NVIC0_INTPRI1 ((__IO uint32_t *) REG_NVIC0_INTPRI1) /* IRQ4..7 Priority */ +#define pREG_NVIC0_INTPRI2 ((__IO uint32_t *) REG_NVIC0_INTPRI2) /* IRQ8..11 Priority */ +#define pREG_NVIC0_INTPRI3 ((__IO uint32_t *) REG_NVIC0_INTPRI3) /* IRQ12..15 Priority */ +#define pREG_NVIC0_INTPRI4 ((__IO uint32_t *) REG_NVIC0_INTPRI4) /* IRQ16..19 Priority */ +#define pREG_NVIC0_INTPRI5 ((__IO uint32_t *) REG_NVIC0_INTPRI5) /* IRQ20..23 Priority */ +#define pREG_NVIC0_INTPRI6 ((__IO uint32_t *) REG_NVIC0_INTPRI6) /* IRQ24..27 Priority */ +#define pREG_NVIC0_INTPRI7 ((__IO uint32_t *) REG_NVIC0_INTPRI7) /* IRQ28..31 Priority */ +#define pREG_NVIC0_INTPRI8 ((__IO uint32_t *) REG_NVIC0_INTPRI8) /* IRQ32..35 Priority */ +#define pREG_NVIC0_INTPRI9 ((__IO uint32_t *) REG_NVIC0_INTPRI9) /* IRQ36..39 Priority */ +#define pREG_NVIC0_INTPRI10 ((__IO uint32_t *) REG_NVIC0_INTPRI10) /* IRQ40..43 Priority */ +#define pREG_NVIC0_INTCPID ((__IO uint32_t *) REG_NVIC0_INTCPID) /* CPUID Base */ +#define pREG_NVIC0_INTSTA ((__IO uint32_t *) REG_NVIC0_INTSTA) /* Interrupt Control State */ +#define pREG_NVIC0_INTVEC ((__IO uint32_t *) REG_NVIC0_INTVEC) /* Vector Table Offset */ +#define pREG_NVIC0_INTAIRC ((__IO uint32_t *) REG_NVIC0_INTAIRC) /* Application Interrupt/Reset Control */ +#define pREG_NVIC0_INTCON0 ((__IO uint16_t *) REG_NVIC0_INTCON0) /* System Control */ +#define pREG_NVIC0_INTCON1 ((__IO uint32_t *) REG_NVIC0_INTCON1) /* Configuration Control */ +#define pREG_NVIC0_INTSHPRIO0 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO0) /* System Handlers 4-7 Priority */ +#define pREG_NVIC0_INTSHPRIO1 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO1) /* System Handlers 8-11 Priority */ +#define pREG_NVIC0_INTSHPRIO3 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO3) /* System Handlers 12-15 Priority */ +#define pREG_NVIC0_INTSHCSR ((__IO uint32_t *) REG_NVIC0_INTSHCSR) /* System Handler Control and State */ +#define pREG_NVIC0_INTCFSR ((__IO uint32_t *) REG_NVIC0_INTCFSR) /* Configurable Fault Status */ +#define pREG_NVIC0_INTHFSR ((__IO uint32_t *) REG_NVIC0_INTHFSR) /* Hard Fault Status */ +#define pREG_NVIC0_INTDFSR ((__IO uint32_t *) REG_NVIC0_INTDFSR) /* Debug Fault Status */ +#define pREG_NVIC0_INTMMAR ((__IO uint32_t *) REG_NVIC0_INTMMAR) /* Mem Manage Address */ +#define pREG_NVIC0_INTBFAR ((__IO uint32_t *) REG_NVIC0_INTBFAR) /* Bus Fault Address */ +#define pREG_NVIC0_INTAFSR ((__IO uint32_t *) REG_NVIC0_INTAFSR) /* Auxiliary Fault Status */ +#define pREG_NVIC0_INTPFR0 ((__IO uint32_t *) REG_NVIC0_INTPFR0) /* Processor Feature Register 0 */ +#define pREG_NVIC0_INTPFR1 ((__IO uint32_t *) REG_NVIC0_INTPFR1) /* Processor Feature Register 1 */ +#define pREG_NVIC0_INTDFR0 ((__IO uint32_t *) REG_NVIC0_INTDFR0) /* Debug Feature Register 0 */ +#define pREG_NVIC0_INTAFR0 ((__IO uint32_t *) REG_NVIC0_INTAFR0) /* Auxiliary Feature Register 0 */ +#define pREG_NVIC0_INTMMFR0 ((__IO uint32_t *) REG_NVIC0_INTMMFR0) /* Memory Model Feature Register 0 */ +#define pREG_NVIC0_INTMMFR1 ((__IO uint32_t *) REG_NVIC0_INTMMFR1) /* Memory Model Feature Register 1 */ +#define pREG_NVIC0_INTMMFR2 ((__IO uint32_t *) REG_NVIC0_INTMMFR2) /* Memory Model Feature Register 2 */ +#define pREG_NVIC0_INTMMFR3 ((__IO uint32_t *) REG_NVIC0_INTMMFR3) /* Memory Model Feature Register 3 */ +#define pREG_NVIC0_INTISAR0 ((__IO uint32_t *) REG_NVIC0_INTISAR0) /* ISA Feature Register 0 */ +#define pREG_NVIC0_INTISAR1 ((__IO uint32_t *) REG_NVIC0_INTISAR1) /* ISA Feature Register 1 */ +#define pREG_NVIC0_INTISAR2 ((__IO uint32_t *) REG_NVIC0_INTISAR2) /* ISA Feature Register 2 */ +#define pREG_NVIC0_INTISAR3 ((__IO uint32_t *) REG_NVIC0_INTISAR3) /* ISA Feature Register 3 */ +#define pREG_NVIC0_INTISAR4 ((__IO uint32_t *) REG_NVIC0_INTISAR4) /* ISA Feature Register 4 */ +#define pREG_NVIC0_INTTRGI ((__IO uint32_t *) REG_NVIC0_INTTRGI) /* Software Trigger Interrupt Register */ +#define pREG_NVIC0_INTPID4 ((__IO uint32_t *) REG_NVIC0_INTPID4) /* Peripheral Identification Register 4 */ +#define pREG_NVIC0_INTPID5 ((__IO uint32_t *) REG_NVIC0_INTPID5) /* Peripheral Identification Register 5 */ +#define pREG_NVIC0_INTPID6 ((__IO uint32_t *) REG_NVIC0_INTPID6) /* Peripheral Identification Register 6 */ +#define pREG_NVIC0_INTPID7 ((__IO uint32_t *) REG_NVIC0_INTPID7) /* Peripheral Identification Register 7 */ +#define pREG_NVIC0_INTPID0 ((__IO uint32_t *) REG_NVIC0_INTPID0) /* Peripheral Identification Bits7:0 */ +#define pREG_NVIC0_INTPID1 ((__IO uint32_t *) REG_NVIC0_INTPID1) /* Peripheral Identification Bits15:8 */ +#define pREG_NVIC0_INTPID2 ((__IO uint32_t *) REG_NVIC0_INTPID2) /* Peripheral Identification Bits16:23 */ +#define pREG_NVIC0_INTPID3 ((__IO uint32_t *) REG_NVIC0_INTPID3) /* Peripheral Identification Bits24:31 */ +#define pREG_NVIC0_INTCID0 ((__IO uint32_t *) REG_NVIC0_INTCID0) /* Component Identification Bits7:0 */ +#define pREG_NVIC0_INTCID1 ((__IO uint32_t *) REG_NVIC0_INTCID1) /* Component Identification Bits15:8 */ +#define pREG_NVIC0_INTCID2 ((__IO uint32_t *) REG_NVIC0_INTCID2) /* Component Identification Bits16:23 */ +#define pREG_NVIC0_INTCID3 ((__IO uint32_t *) REG_NVIC0_INTCID3) /* Component Identification Bits24:31 */ + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#endif + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h new file mode 100755 index 00000000000..b1dca858030 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_device.h @@ -0,0 +1,1217 @@ +/* ================================================================================ + + Project : ADuCM302x + File : ADuCM302x_device.h + Description : C Register Definitions + + Date : Feb 6, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM302X_DEVICE_H +#define _ADUCM302X_DEVICE_H + +/* pickup integer types */ +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "ADuCM302x_typedefs.h" + +#if defined ( __CC_ARM ) +#pragma push +#pragma anon_unions +#endif + + +#ifndef __IO +#ifdef __cplusplus +#define __I volatile /* read-only */ +#define __C +#else +#define __I volatile /* read-only */ +#define __C const +#endif +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif + +#if defined (_MISRA_RULES) +/* + anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. + Use of unions violates MISRA Rule 18.4. + Anonymous unions are required for this implementation. + Re-use of identifiers violates MISRA Rule 5.7. + Field names are repeated for the ADuCM302x register map. +*/ +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions") +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers") +#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope") +#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers") +#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union") +#endif /* _MISRA_RULES */ + +/** @defgroup TMR General Purpose Timer (TMR) Module + * General Purpose Timer + * @{ + */ + +/*! ========================================================================== + * \struct ADI_TMR_TypeDef + * \brief General Purpose Timer + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ +typedef struct _ADI_TMR_TypeDef +{ + __IO uint16_t LOAD; /*!< 16-bit Load Value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CURCNT; /*!< 16-bit Timer Value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t CLRINT; /*!< Clear Interrupt */ + __I __C uint8_t RESERVED3[2]; + __I __C uint16_t CAPTURE; /*!< Capture */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALOAD; /*!< 16-bit Load Value, Asynchronous */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t ACURCNT; /*!< 16-bit Timer Value, Asynchronous */ + __I __C uint8_t RESERVED6[2]; + __I __C uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t PWMCTL; /*!< PWM Control Register */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t PWMMATCH; /*!< PWM Match Value */ +} ADI_TMR_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ */ + +/*!@}*/ + +/** @defgroup RTC Real-Time Clock (RTC) Module + * Real-Time Clock + * @{ + */ + +/*! ========================================================================== + * \struct ADI_RTC_TypeDef + * \brief Real-Time Clock + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ +typedef struct _ADI_RTC_TypeDef +{ + __IO uint16_t CR0; /*!< RTC Control 0 */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t SR0; /*!< RTC Status 0 */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t SR1; /*!< RTC Status 1 */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNT0; /*!< RTC Count 0 */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNT1; /*!< RTC Count 1 */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALM0; /*!< RTC Alarm 0 */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ALM1; /*!< RTC Alarm 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t TRM; /*!< RTC Trim */ + __I __C uint8_t RESERVED7[2]; + __O uint16_t GWY; /*!< RTC Gateway */ + __I __C uint8_t RESERVED8[6]; + __IO uint16_t CR1; /*!< RTC Control 1 */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SR2; /*!< RTC Status 2 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t SNAP0; /*!< RTC Snapshot 0 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SNAP1; /*!< RTC Snapshot 1 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t SNAP2; /*!< RTC Snapshot 2 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t MOD; /*!< RTC Modulo */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CNT2; /*!< RTC Count 2 */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ALM2; /*!< RTC Alarm 2 */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t SR3; /*!< RTC Status 3 */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t CR2IC; /*!< RTC Control 2 for Configuring Input Capture Channels */ + __I __C uint8_t RESERVED18[2]; + __IO uint16_t CR3SS; /*!< RTC Control 3 for Configuring SensorStrobe Channel */ + __I __C uint8_t RESERVED19[2]; + __IO uint16_t CR4SS; /*!< RTC Control 4 for Configuring SensorStrobe Channel */ + __I __C uint8_t RESERVED20[2]; + __IO uint16_t SSMSK; /*!< RTC Mask for SensorStrobe Channel */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t SS1ARL; /*!< RTC Auto-Reload for SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED22[6]; + __I __C uint16_t IC2; /*!< RTC Input Capture Channel 2 */ + __I __C uint8_t RESERVED23[2]; + __I __C uint16_t IC3; /*!< RTC Input Capture Channel 3 */ + __I __C uint8_t RESERVED24[2]; + __I __C uint16_t IC4; /*!< RTC Input Capture Channel 4 */ + __I __C uint8_t RESERVED25[2]; + __IO uint16_t SS1; /*!< RTC SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED26[14]; + __I __C uint16_t SR4; /*!< RTC Status 4 */ + __I __C uint8_t RESERVED27[2]; + __I __C uint16_t SR5; /*!< RTC Status 5 */ + __I __C uint8_t RESERVED28[2]; + __I __C uint16_t SR6; /*!< RTC Status 6 */ + __I __C uint8_t RESERVED29[2]; + __I __C uint16_t SS1TGT; /*!< RTC SensorStrobe Channel 1 Target */ + __I __C uint8_t RESERVED30[2]; + __I __C uint16_t FRZCNT; /*!< RTC Freeze Count */ +} ADI_RTC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SYS System Identification and Debug Enable (SYS) Module + * System Identification and Debug Enable + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SYS_TypeDef + * \brief System Identification and Debug Enable + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ +typedef struct _ADI_SYS_TypeDef +{ + __I __C uint8_t RESERVED0[32]; + __I __C uint16_t ADIID; /*!< ADI Identification */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t CHIPID; /*!< Chip Identifier */ + __I __C uint8_t RESERVED2[26]; + __O uint16_t SWDEN; /*!< Serial Wire Debug Enable */ +} ADI_SYS_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ */ + +/*!@}*/ + +/** @defgroup WDT Watchdog Timer (WDT) Module + * Watchdog Timer + * @{ + */ + +/*! ========================================================================== + * \struct ADI_WDT_TypeDef + * \brief Watchdog Timer + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ +typedef struct _ADI_WDT_TypeDef +{ + __IO uint16_t LOAD; /*!< Load Value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CCNT; /*!< Current Count Value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t RESTART; /*!< Clear Interrupt */ + __I __C uint8_t RESERVED3[10]; + __I __C uint16_t STAT; /*!< Status */ +} ADI_WDT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup I2C I2C Master/Slave (I2C) Module + * I2C Master/Slave + * @{ + */ + +/*! ========================================================================== + * \struct ADI_I2C_TypeDef + * \brief I2C Master/Slave + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ +typedef struct _ADI_I2C_TypeDef +{ + __IO uint16_t MCTL; /*!< Master Control */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t MSTAT; /*!< Master Status */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t MRX; /*!< Master Receive Data */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t MTX; /*!< Master Transmit Data */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t MRXCNT; /*!< Master Receive Data Count */ + __I __C uint8_t RESERVED4[2]; + __I __C uint16_t MCRXCNT; /*!< Master Current Receive Data Count */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ADDR1; /*!< Master Address Byte 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t ADDR2; /*!< Master Address Byte 2 */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t BYT; /*!< Start Byte */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t DIV; /*!< Serial Clock Period Divisor */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SCTL; /*!< Slave Control */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t SSTAT; /*!< Slave I2C Status/Error/IRQ */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SRX; /*!< Slave Receive */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t STX; /*!< Slave Transmit */ + __I __C uint8_t RESERVED13[2]; + __IO uint16_t ALT; /*!< Hardware General Call ID */ + __I __C uint8_t RESERVED14[2]; + __IO uint16_t ID0; /*!< First Slave Address Device ID */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ID1; /*!< Second Slave Address Device ID */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t ID2; /*!< Third Slave Address Device ID */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t ID3; /*!< Fourth Slave Address Device ID */ + __I __C uint8_t RESERVED18[2]; + __IO uint16_t STAT; /*!< Master and Slave FIFO Status */ + __I __C uint8_t RESERVED19[2]; + __O uint16_t SHCTL; /*!< Shared Control */ + __I __C uint8_t RESERVED20[2]; + __IO uint16_t TCTL; /*!< Timing Control Register */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t ASTRETCH_SCL; /*!< Automatic Stretch SCL */ +} ADI_I2C_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SPI Serial Peripheral Interface (SPI) Module + * Serial Peripheral Interface + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SPI_TypeDef + * \brief Serial Peripheral Interface + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ +typedef struct _ADI_SPI_TypeDef +{ + __IO uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t RX; /*!< Receive */ + __I __C uint8_t RESERVED1[2]; + __O uint16_t TX; /*!< Transmit */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t DIV; /*!< SPI Baud Rate Selection */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CTL; /*!< SPI Configuration */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t IEN; /*!< SPI Interrupts Enable */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t CNT; /*!< Transfer Byte Count */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t DMA; /*!< SPI DMA Enable */ + __I __C uint8_t RESERVED7[2]; + __I __C uint16_t FIFO_STAT; /*!< FIFO Status */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t RD_CTL; /*!< Read Control */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t FLOW_CTL; /*!< Flow Control */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t WAIT_TMR; /*!< Wait Timer for Flow Control */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t CS_CTL; /*!< Chip Select Control for Multi-slave Connections */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t CS_OVERRIDE; /*!< Chip Select Override */ + __I __C uint8_t RESERVED13[4]; +} ADI_SPI_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ */ + +/*!@}*/ + +/** @defgroup UART (UART) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_UART_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ +typedef struct _ADI_UART_TypeDef +{ + union { + __I __C uint16_t RX; /*!< Receive Buffer Register */ + __O uint16_t TX; /*!< Transmit Holding Register */ + }; + __I __C uint8_t RESERVED0[2]; + __IO uint16_t IEN; /*!< Interrupt Enable */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t IIR; /*!< Interrupt ID */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t LCR; /*!< Line Control */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t MCR; /*!< Modem Control */ + __I __C uint8_t RESERVED4[2]; + __I __C uint16_t LSR; /*!< Line Status */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t MSR; /*!< Modem Status */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t SCR; /*!< Scratch Buffer */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t FCR; /*!< FIFO Control */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t FBR; /*!< Fractional Baud Rate */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t DIV; /*!< Baud Rate Divider */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t LCR2; /*!< Second Line Control */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t CTL; /*!< UART Control Register */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t RFC; /*!< RX FIFO Byte Count */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t TFC; /*!< TX FIFO Byte Count */ + __I __C uint8_t RESERVED14[2]; + __IO uint16_t RSC; /*!< RS485 Half-duplex Control */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ACR; /*!< Auto Baud Control */ + __I __C uint8_t RESERVED16[2]; + __I __C uint16_t ASRL; /*!< Auto Baud Status (Low) */ + __I __C uint8_t RESERVED17[2]; + __I __C uint16_t ASRH; /*!< Auto Baud Status (High) */ +} ADI_UART_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ */ + +/*!@}*/ + +/** @defgroup BEEP Beeper Driver (BEEP) Module + * Beeper Driver + * @{ + */ + +/*! ========================================================================== + * \struct ADI_BEEP_TypeDef + * \brief Beeper Driver + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ +typedef struct _ADI_BEEP_TypeDef +{ + __IO uint16_t CFG; /*!< Beeper Configuration */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t STAT; /*!< Beeper Status */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t TONEA; /*!< Tone A Data */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t TONEB; /*!< Tone B Data */ +} ADI_BEEP_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ */ + +/*!@}*/ + +/** @defgroup ADC (ADC) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_ADC_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ +typedef struct _ADI_ADC_TypeDef +{ + __IO uint16_t CFG; /*!< ADC Configuration */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t PWRUP; /*!< ADC Power-up Time */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CAL_WORD; /*!< Calibration Word */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNV_CFG; /*!< ADC Conversion Configuration */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNV_TIME; /*!< ADC Conversion Time */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t AVG_CFG; /*!< Averaging Configuration */ + __I __C uint8_t RESERVED5[10]; + __IO uint16_t IRQ_EN; /*!< Interrupt Enable */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t STAT; /*!< ADC Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t OVF; /*!< Overflow of Output Registers */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t ALERT; /*!< Alert Indication */ + __I __C uint8_t RESERVED9[2]; + __I __C uint16_t CH0_OUT; /*!< Conversion Result Channel 0 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t CH1_OUT; /*!< Conversion Result Channel 1 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t CH2_OUT; /*!< Conversion Result Channel 2 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t CH3_OUT; /*!< Conversion Result Channel 3 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t CH4_OUT; /*!< Conversion Result Channel 4 */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CH5_OUT; /*!< Conversion Result Channel 5 */ + __I __C uint8_t RESERVED15[2]; + __I __C uint16_t CH6_OUT; /*!< Conversion Result Channel 6 */ + __I __C uint8_t RESERVED16[2]; + __I __C uint16_t CH7_OUT; /*!< Conversion Result Channel 7 */ + __I __C uint8_t RESERVED17[2]; + __I __C uint16_t BAT_OUT; /*!< Battery Monitoring Result */ + __I __C uint8_t RESERVED18[2]; + __I __C uint16_t TMP_OUT; /*!< Temperature Result */ + __I __C uint8_t RESERVED19[2]; + __I __C uint16_t TMP2_OUT; /*!< Temperature Result 2 */ + __I __C uint8_t RESERVED20[2]; + __I __C uint16_t DMA_OUT; /*!< DMA Output Register */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t LIM0_LO; /*!< Channel 0 Low Limit */ + __I __C uint8_t RESERVED22[2]; + __IO uint16_t LIM0_HI; /*!< Channel 0 High Limit */ + __I __C uint8_t RESERVED23[2]; + __IO uint16_t HYS0; /*!< Channel 0 Hysteresis */ + __I __C uint8_t RESERVED24[6]; + __IO uint16_t LIM1_LO; /*!< Channel 1 Low Limit */ + __I __C uint8_t RESERVED25[2]; + __IO uint16_t LIM1_HI; /*!< Channel 1 High Limit */ + __I __C uint8_t RESERVED26[2]; + __IO uint16_t HYS1; /*!< Channel 1 Hysteresis */ + __I __C uint8_t RESERVED27[6]; + __IO uint16_t LIM2_LO; /*!< Channel 2 Low Limit */ + __I __C uint8_t RESERVED28[2]; + __IO uint16_t LIM2_HI; /*!< Channel 2 High Limit */ + __I __C uint8_t RESERVED29[2]; + __IO uint16_t HYS2; /*!< Channel 2 Hysteresis */ + __I __C uint8_t RESERVED30[6]; + __IO uint16_t LIM3_LO; /*!< Channel 3 Low Limit */ + __I __C uint8_t RESERVED31[2]; + __IO uint16_t LIM3_HI; /*!< Channel 3 High Limit */ + __I __C uint8_t RESERVED32[2]; + __IO uint16_t HYS3; /*!< Channel 3 Hysteresis */ + __I __C uint8_t RESERVED33[38]; + __IO uint16_t CFG1; /*!< Reference Buffer Low Power Mode */ + __I __C uint8_t RESERVED34[576]; +} ADI_ADC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup DMA DMA (DMA) Module + * DMA + * @{ + */ + +/*! ========================================================================== + * \struct ADI_DMA_TypeDef + * \brief DMA + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ +typedef struct _ADI_DMA_TypeDef +{ + __I __C uint32_t STAT; /*!< DMA Status */ + __O uint32_t CFG; /*!< DMA Configuration */ + __IO uint32_t PDBPTR; /*!< DMA Channel Primary Control Database Pointer */ + __I __C uint32_t ADBPTR; /*!< DMA Channel Alternate Control Database Pointer */ + __I __C uint8_t RESERVED0[4]; + __O uint32_t SWREQ; /*!< DMA Channel Software Request */ + __I __C uint8_t RESERVED1[8]; + __IO uint32_t RMSK_SET; /*!< DMA Channel Request Mask Set */ + __O uint32_t RMSK_CLR; /*!< DMA Channel Request Mask Clear */ + __IO uint32_t EN_SET; /*!< DMA Channel Enable Set */ + __O uint32_t EN_CLR; /*!< DMA Channel Enable Clear */ + __IO uint32_t ALT_SET; /*!< DMA Channel Primary Alternate Set */ + __O uint32_t ALT_CLR; /*!< DMA Channel Primary Alternate Clear */ + __O uint32_t PRI_SET; /*!< DMA Channel Priority Set */ + __O uint32_t PRI_CLR; /*!< DMA Channel Priority Clear */ + __I __C uint8_t RESERVED2[8]; + __IO uint32_t ERRCHNL_CLR; /*!< DMA per Channel Error Clear */ + __IO uint32_t ERR_CLR; /*!< DMA Bus Error Clear */ + __IO uint32_t INVALIDDESC_CLR; /*!< DMA per Channel Invalid Descriptor Clear */ + __I __C uint8_t RESERVED3[1964]; + __IO uint32_t BS_SET; /*!< DMA Channel Bytes Swap Enable Set */ + __O uint32_t BS_CLR; /*!< DMA Channel Bytes Swap Enable Clear */ + __I __C uint8_t RESERVED4[8]; + __IO uint32_t SRCADDR_SET; /*!< DMA Channel Source Address Decrement Enable Set */ + __O uint32_t SRCADDR_CLR; /*!< DMA Channel Source Address Decrement Enable Clear */ + __IO uint32_t DSTADDR_SET; /*!< DMA Channel Destination Address Decrement Enable Set */ + __O uint32_t DSTADDR_CLR; /*!< DMA Channel Destination Address Decrement Enable Clear */ + __I __C uint8_t RESERVED5[1984]; + __I __C uint32_t REVID; /*!< DMA Controller Revision ID */ +} ADI_DMA_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ */ + +/*!@}*/ + +/** @defgroup FLCC Flash Controller (FLCC) Module + * Flash Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_FLCC_TypeDef + * \brief Flash Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ +typedef struct _ADI_FLCC_TypeDef +{ + __IO uint32_t STAT; /*!< Status */ + __IO uint32_t IEN; /*!< Interrupt Enable */ + __IO uint32_t CMD; /*!< Command */ + __IO uint32_t KH_ADDR; /*!< Write Address */ + __IO uint32_t KH_DATA0; /*!< Write Lower Data */ + __IO uint32_t KH_DATA1; /*!< Write Upper Data */ + __IO uint32_t PAGE_ADDR0; /*!< Lower Page Address */ + __IO uint32_t PAGE_ADDR1; /*!< Upper Page Address */ + __O uint32_t KEY; /*!< Key */ + __I __C uint32_t WR_ABORT_ADDR; /*!< Write Abort Address */ + __IO uint32_t WRPROT; /*!< Write Protection */ + __I __C uint32_t SIGNATURE; /*!< Signature */ + __IO uint32_t UCFG; /*!< User Configuration */ + __IO uint32_t TIME_PARAM0; /*!< Time Parameter 0 */ + __IO uint32_t TIME_PARAM1; /*!< Time Parameter 1 */ + __IO uint32_t ABORT_EN_LO; /*!< IRQ Abort Enable (Lower Bits) */ + __IO uint32_t ABORT_EN_HI; /*!< IRQ Abort Enable (Upper Bits) */ + __IO uint32_t ECC_CFG; /*!< ECC Configuration */ + __I __C uint32_t ECC_ADDR; /*!< ECC Status (Address) */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t POR_SEC; /*!< Flash Security */ + __IO uint32_t VOL_CFG; /*!< Volatile Flash Configuration */ +} ADI_FLCC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup FLCC_CACHE Cache Controller (FLCC_CACHE) Module + * Cache Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_FLCC_CACHE_TypeDef + * \brief Cache Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ +typedef struct _ADI_FLCC_CACHE_TypeDef +{ + __I __C uint32_t STAT; /*!< Cache Status */ + __IO uint32_t SETUP; /*!< Cache Setup */ + __O uint32_t KEY; /*!< Cache Key */ + __I __C uint8_t RESERVED0[40]; +} ADI_FLCC_CACHE_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ */ + +/*!@}*/ + +/** @defgroup GPIO (GPIO) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_GPIO_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ +typedef struct _ADI_GPIO_TypeDef +{ + __IO uint32_t CFG; /*!< Port Configuration */ + __IO uint16_t OEN; /*!< Port Output Enable */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t PE; /*!< Port Output Pull-up/Pull-down Enable */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t IEN; /*!< Port Input Path Enable */ + __I __C uint8_t RESERVED2[2]; + __I __C uint16_t IN; /*!< Port Registered Data Input */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t OUT; /*!< Port Data Output */ + __I __C uint8_t RESERVED4[2]; + __O uint16_t SET; /*!< Port Data Out Set */ + __I __C uint8_t RESERVED5[2]; + __O uint16_t CLR; /*!< Port Data Out Clear */ + __I __C uint8_t RESERVED6[2]; + __O uint16_t TGL; /*!< Port Pin Toggle */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t POL; /*!< Port Interrupt Polarity */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t IENA; /*!< Port Interrupt A Enable */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t IENB; /*!< Port Interrupt B Enable */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t INT; /*!< Port Interrupt Status */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t DS; /*!< Port Drive Strength Select */ +} ADI_GPIO_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SPORT Serial Port (SPORT) Module + * Serial Port + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SPORT_TypeDef + * \brief Serial Port + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ +typedef struct _ADI_SPORT_TypeDef +{ + __IO uint32_t CTL_A; /*!< Half SPORT 'A' Control */ + __IO uint32_t DIV_A; /*!< Half SPORT 'A' Divisor */ + __IO uint32_t IEN_A; /*!< Half SPORT A's Interrupt Enable */ + __IO uint32_t STAT_A; /*!< Half SPORT A's Status */ + __IO uint32_t NUMTRAN_A; /*!< Half SPORT A Number of Transfers */ + __IO uint32_t CNVT_A; /*!< Half SPORT 'A' CNV Width */ + __I __C uint8_t RESERVED0[8]; + __O uint32_t TX_A; /*!< Half SPORT 'A' Tx Buffer */ + __I __C uint8_t RESERVED1[4]; + __I __C uint32_t RX_A; /*!< Half SPORT 'A' Rx Buffer */ + __I __C uint8_t RESERVED2[20]; + __IO uint32_t CTL_B; /*!< Half SPORT 'B' Control */ + __IO uint32_t DIV_B; /*!< Half SPORT 'B' Divisor */ + __IO uint32_t IEN_B; /*!< Half SPORT B's Interrupt Enable */ + __IO uint32_t STAT_B; /*!< Half SPORT B's Status */ + __IO uint32_t NUMTRAN_B; /*!< Half SPORT B Number of Transfers */ + __IO uint32_t CNVT_B; /*!< Half SPORT 'B' CNV Width */ + __I __C uint8_t RESERVED3[8]; + __O uint32_t TX_B; /*!< Half SPORT 'B' Tx Buffer */ + __I __C uint8_t RESERVED4[4]; + __I __C uint32_t RX_B; /*!< Half SPORT 'B' Rx Buffer */ + __I __C uint8_t RESERVED5[16]; +} ADI_SPORT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CRC CRC Accelerator (CRC) Module + * CRC Accelerator + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CRC_TypeDef + * \brief CRC Accelerator + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ +typedef struct _ADI_CRC_TypeDef +{ + __IO uint32_t CTL; /*!< CRC Control */ + __O uint32_t IPDATA; /*!< Input Data Word */ + __IO uint32_t RESULT; /*!< CRC Result */ + __IO uint32_t POLY; /*!< Programmable CRC Polynomial */ + union { + __O uint8_t IPBITS[8]; /*!< Input Data Bits */ + __O uint8_t IPBYTE; /*!< Input Data Byte */ + }; +} ADI_CRC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup RNG Random Number Generator (RNG) Module + * Random Number Generator + * @{ + */ + +/*! ========================================================================== + * \struct ADI_RNG_TypeDef + * \brief Random Number Generator + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ +typedef struct _ADI_RNG_TypeDef +{ + __IO uint16_t CTL; /*!< RNG Control Register */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t LEN; /*!< RNG Sample Length Register */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t STAT; /*!< RNG Status Register */ + __I __C uint8_t RESERVED2[2]; + __I __C uint32_t DATA; /*!< RNG Data Register */ + __I __C uint32_t OSCCNT; /*!< Oscillator Count */ + __I __C int8_t OSCDIFF[4]; /*!< Oscillator Difference */ +} ADI_RNG_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CRYPT Register Map for the Crypto Block (CRYPT) Module + * Register Map for the Crypto Block + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CRYPT_TypeDef + * \brief Register Map for the Crypto Block + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ +typedef struct _ADI_CRYPT_TypeDef +{ + __IO uint32_t CFG; /*!< Configuration Register */ + __IO uint32_t DATALEN; /*!< Payload Data Length */ + __IO uint32_t PREFIXLEN; /*!< Authentication Data Length */ + __IO uint32_t INTEN; /*!< Interrupt Enable Register */ + __IO uint32_t STAT; /*!< Status Register */ + __O uint32_t INBUF; /*!< Input Buffer */ + __I __C uint32_t OUTBUF; /*!< Output Buffer */ + __IO uint32_t NONCE0; /*!< Nonce Bits [31:0] */ + __IO uint32_t NONCE1; /*!< Nonce Bits [63:32] */ + __IO uint32_t NONCE2; /*!< Nonce Bits [95:64] */ + __IO uint32_t NONCE3; /*!< Nonce Bits [127:96] */ + __O uint32_t AESKEY0; /*!< AES Key Bits [31:0] */ + __O uint32_t AESKEY1; /*!< AES Key Bits [63:32] */ + __O uint32_t AESKEY2; /*!< AES Key Bits [95:64] */ + __O uint32_t AESKEY3; /*!< AES Key Bits [127:96] */ + __O uint32_t AESKEY4; /*!< AES Key Bits [159:128] */ + __O uint32_t AESKEY5; /*!< AES Key Bits [191:160] */ + __O uint32_t AESKEY6; /*!< AES Key Bits [223:192] */ + __O uint32_t AESKEY7; /*!< AES Key Bits [255:224] */ + __IO uint32_t CNTRINIT; /*!< Counter Initialization Vector */ + __IO uint32_t SHAH0; /*!< SHA Bits [31:0] */ + __IO uint32_t SHAH1; /*!< SHA Bits [63:32] */ + __IO uint32_t SHAH2; /*!< SHA Bits [95:64] */ + __IO uint32_t SHAH3; /*!< SHA Bits [127:96] */ + __IO uint32_t SHAH4; /*!< SHA Bits [159:128] */ + __IO uint32_t SHAH5; /*!< SHA Bits [191:160] */ + __IO uint32_t SHAH6; /*!< SHA Bits [223:192] */ + __IO uint32_t SHAH7; /*!< SHA Bits [255:224] */ + __IO uint32_t SHA_LAST_WORD; /*!< SHA Last Word and Valid Bits Information */ + __IO uint32_t CCM_NUM_VALID_BYTES; /*!< NUM_VALID_BYTES */ +} ADI_CRYPT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PMG Power Management (PMG) Module + * Power Management + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PMG_TypeDef + * \brief Power Management + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ +typedef struct _ADI_PMG_TypeDef +{ + __IO uint32_t IEN; /*!< Power Supply Monitor Interrupt Enable */ + __IO uint32_t PSM_STAT; /*!< Power Supply Monitor Status */ + __IO uint32_t PWRMOD; /*!< Power Mode Register */ + __O uint32_t PWRKEY; /*!< Key Protection for PWRMOD and SRAMRET */ + __I __C uint32_t SHDN_STAT; /*!< Shutdown Status Register */ + __IO uint32_t SRAMRET; /*!< Control for Retention SRAM in Hibernate Mode */ + __I __C uint8_t RESERVED0[40]; + __IO uint32_t RST_STAT; /*!< Reset Status */ + __IO uint32_t CTL1; /*!< HP Buck Control */ + __I __C uint8_t RESERVED1[20]; +} ADI_PMG_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ */ + +/*!@}*/ + +/** @defgroup XINT External interrupt configuration (XINT) Module + * External interrupt configuration + * @{ + */ + +/*! ========================================================================== + * \struct ADI_XINT_TypeDef + * \brief External interrupt configuration + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ +typedef struct _ADI_XINT_TypeDef +{ + __IO uint32_t CFG0; /*!< External Interrupt Configuration */ + __I __C uint32_t EXT_STAT; /*!< External Wakeup Interrupt Status */ + __I __C uint8_t RESERVED0[8]; + __IO uint32_t CLR; /*!< External Interrupt Clear */ + __IO uint32_t NMICLR; /*!< Non-Maskable Interrupt Clear */ +} ADI_XINT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CLKG_OSC Clocking (CLKG_OSC) Module + * Clocking + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CLKG_OSC_TypeDef + * \brief Clocking + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ +typedef struct _ADI_CLKG_OSC_TypeDef +{ + __I __C uint8_t RESERVED0[12]; + __O uint32_t KEY; /*!< Key Protection for CLKG_OSC_CTL */ + __IO uint32_t CTL; /*!< Oscillator Control */ + __I __C uint8_t RESERVED1[8]; +} ADI_CLKG_OSC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PMG_TST Power Management (PMG_TST) Module + * Power Management + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PMG_TST_TypeDef + * \brief Power Management + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ +typedef struct _ADI_PMG_TST_TypeDef +{ + __I __C uint8_t RESERVED0[96]; + __IO uint32_t SRAM_CTL; /*!< Control for SRAM Parity and Instruction SRAM */ + __IO uint32_t SRAM_INITSTAT; /*!< Initialization Status Register */ + __O uint16_t CLR_LATCH_GPIOS; /*!< Clear GPIO After Shutdown Mode */ + __I __C uint8_t RESERVED1[2]; + __IO uint32_t SCRPAD_IMG; /*!< Scratch Pad Image */ + __I __C uint32_t SCRPAD_3V_RD; /*!< Scratch Pad Saved in Battery Domain */ +} ADI_PMG_TST_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CLKG_CLK Clocking (CLKG_CLK) Module + * Clocking + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CLKG_CLK_TypeDef + * \brief Clocking + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ +typedef struct _ADI_CLKG_CLK_TypeDef +{ + __IO uint32_t CTL0; /*!< Miscellaneous Clock Settings */ + __IO uint32_t CTL1; /*!< Clock Dividers */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t CTL3; /*!< System PLL */ + __I __C uint8_t RESERVED1[4]; + __IO uint32_t CTL5; /*!< User Clock Gating Control */ + __IO uint32_t STAT0; /*!< Clocking Status */ + __I __C uint8_t RESERVED2[20]; +} ADI_CLKG_CLK_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ */ + +/*!@}*/ + +/** @defgroup BUSM Bus matrix (BUSM) Module + * Bus matrix + * @{ + */ + +/*! ========================================================================== + * \struct ADI_BUSM_TypeDef + * \brief Bus matrix + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ +typedef struct _ADI_BUSM_TypeDef +{ + __IO uint32_t ARBIT0; /*!< Arbitration Priority Configuration for FLASH and SRAM0 */ + __IO uint32_t ARBIT1; /*!< Arbitration Priority Configuration for SRAM1 and SIP */ + __IO uint32_t ARBIT2; /*!< Arbitration Priority Configuration for APB32 and APB16 */ + __IO uint32_t ARBIT3; /*!< Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ + __I __C uint8_t RESERVED0[4]; +} ADI_BUSM_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PTI Parallel Test Interface (PTI) Module + * Parallel Test Interface + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PTI_TypeDef + * \brief Parallel Test Interface + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ +typedef struct _ADI_PTI_TypeDef +{ + __IO uint32_t RST_ISR_STARTADDR; /*!< Reset ISR Start Address */ + __IO uint32_t RST_STACK_PTR; /*!< Reset Stack Pointer */ + __IO uint32_t CTL; /*!< Parallel Test Interface Control Register */ +} ADI_PTI_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ */ + +/*!@}*/ + +/** @defgroup NVIC Cortex-M3 Interrupt Controller (NVIC) Module + * Cortex-M3 Interrupt Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_NVIC_TypeDef + * \brief Cortex-M3 Interrupt Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ +typedef struct _ADI_NVIC_TypeDef +{ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t INTNUM; /*!< Interrupt Control Type */ + __I __C uint8_t RESERVED1[8]; + __IO uint32_t STKSTA; /*!< Systick Control and Status */ + __IO uint32_t STKLD; /*!< Systick Reload Value */ + __IO uint32_t STKVAL; /*!< Systick Current Value */ + __IO uint32_t STKCAL; /*!< Systick Calibration Value */ + __I __C uint8_t RESERVED2[224]; + __IO uint32_t INTSETE0; /*!< IRQ0..31 Set_Enable */ + __IO uint32_t INTSETE1; /*!< IRQ32..63 Set_Enable */ + __I __C uint8_t RESERVED3[120]; + __IO uint32_t INTCLRE0; /*!< IRQ0..31 Clear_Enable */ + __IO uint32_t INTCLRE1; /*!< IRQ32..63 Clear_Enable */ + __I __C uint8_t RESERVED4[120]; + __IO uint32_t INTSETP0; /*!< IRQ0..31 Set_Pending */ + __IO uint32_t INTSETP1; /*!< IRQ32..63 Set_Pending */ + __I __C uint8_t RESERVED5[120]; + __IO uint32_t INTCLRP0; /*!< IRQ0..31 Clear_Pending */ + __IO uint32_t INTCLRP1; /*!< IRQ32..63 Clear_Pending */ + __I __C uint8_t RESERVED6[120]; + __IO uint32_t INTACT0; /*!< IRQ0..31 Active Bit */ + __IO uint32_t INTACT1; /*!< IRQ32..63 Active Bit */ + __I __C uint8_t RESERVED7[248]; + __IO uint32_t INTPRI0; /*!< IRQ0..3 Priority */ + __IO uint32_t INTPRI1; /*!< IRQ4..7 Priority */ + __IO uint32_t INTPRI2; /*!< IRQ8..11 Priority */ + __IO uint32_t INTPRI3; /*!< IRQ12..15 Priority */ + __IO uint32_t INTPRI4; /*!< IRQ16..19 Priority */ + __IO uint32_t INTPRI5; /*!< IRQ20..23 Priority */ + __IO uint32_t INTPRI6; /*!< IRQ24..27 Priority */ + __IO uint32_t INTPRI7; /*!< IRQ28..31 Priority */ + __IO uint32_t INTPRI8; /*!< IRQ32..35 Priority */ + __IO uint32_t INTPRI9; /*!< IRQ36..39 Priority */ + __IO uint32_t INTPRI10; /*!< IRQ40..43 Priority */ + __I __C uint8_t RESERVED8[2260]; + __IO uint32_t INTCPID; /*!< CPUID Base */ + __IO uint32_t INTSTA; /*!< Interrupt Control State */ + __IO uint32_t INTVEC; /*!< Vector Table Offset */ + __IO uint32_t INTAIRC; /*!< Application Interrupt/Reset Control */ + __IO uint16_t INTCON0; /*!< System Control */ + __I __C uint8_t RESERVED9[2]; + __IO uint32_t INTCON1; /*!< Configuration Control */ + __IO uint32_t INTSHPRIO0; /*!< System Handlers 4-7 Priority */ + __IO uint32_t INTSHPRIO1; /*!< System Handlers 8-11 Priority */ + __IO uint32_t INTSHPRIO3; /*!< System Handlers 12-15 Priority */ + __IO uint32_t INTSHCSR; /*!< System Handler Control and State */ + __IO uint32_t INTCFSR; /*!< Configurable Fault Status */ + __IO uint32_t INTHFSR; /*!< Hard Fault Status */ + __IO uint32_t INTDFSR; /*!< Debug Fault Status */ + __IO uint32_t INTMMAR; /*!< Mem Manage Address */ + __IO uint32_t INTBFAR; /*!< Bus Fault Address */ + __IO uint32_t INTAFSR; /*!< Auxiliary Fault Status */ + __IO uint32_t INTPFR0; /*!< Processor Feature Register 0 */ + __IO uint32_t INTPFR1; /*!< Processor Feature Register 1 */ + __IO uint32_t INTDFR0; /*!< Debug Feature Register 0 */ + __IO uint32_t INTAFR0; /*!< Auxiliary Feature Register 0 */ + __IO uint32_t INTMMFR0; /*!< Memory Model Feature Register 0 */ + __IO uint32_t INTMMFR1; /*!< Memory Model Feature Register 1 */ + __IO uint32_t INTMMFR2; /*!< Memory Model Feature Register 2 */ + __IO uint32_t INTMMFR3; /*!< Memory Model Feature Register 3 */ + __IO uint32_t INTISAR0; /*!< ISA Feature Register 0 */ + __IO uint32_t INTISAR1; /*!< ISA Feature Register 1 */ + __IO uint32_t INTISAR2; /*!< ISA Feature Register 2 */ + __IO uint32_t INTISAR3; /*!< ISA Feature Register 3 */ + __IO uint32_t INTISAR4; /*!< ISA Feature Register 4 */ + __I __C uint8_t RESERVED10[396]; + __IO uint32_t INTTRGI; /*!< Software Trigger Interrupt Register */ + __I __C uint8_t RESERVED11[204]; + __IO uint32_t INTPID4; /*!< Peripheral Identification Register 4 */ + __IO uint32_t INTPID5; /*!< Peripheral Identification Register 5 */ + __IO uint32_t INTPID6; /*!< Peripheral Identification Register 6 */ + __IO uint32_t INTPID7; /*!< Peripheral Identification Register 7 */ + __IO uint32_t INTPID0; /*!< Peripheral Identification Bits7:0 */ + __IO uint32_t INTPID1; /*!< Peripheral Identification Bits15:8 */ + __IO uint32_t INTPID2; /*!< Peripheral Identification Bits16:23 */ + __IO uint32_t INTPID3; /*!< Peripheral Identification Bits24:31 */ + __IO uint32_t INTCID0; /*!< Component Identification Bits7:0 */ + __IO uint32_t INTCID1; /*!< Component Identification Bits15:8 */ + __IO uint32_t INTCID2; /*!< Component Identification Bits16:23 */ + __IO uint32_t INTCID3; /*!< Component Identification Bits24:31 */ +} ADI_NVIC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ */ + +/*!@}*/ + +/* ****************************************************************************** + * Peripheral Memory Map Declarations + * *****************************************************************************/ +/*! @defgroup PMEMMAPDEC Peripheral Memory Map Declarations + * \addtogroup PMEMMAPDEC + * @{ */ +#define ADI_TMR0_BASE 0x40000000 /*!< Base address of TMR0 */ +#define ADI_TMR1_BASE 0x40000400 /*!< Base address of TMR1 */ +#define ADI_TMR2_BASE 0x40000800 /*!< Base address of TMR2 */ +#define ADI_RTC0_BASE 0x40001000 /*!< Base address of RTC0 */ +#define ADI_RTC1_BASE 0x40001400 /*!< Base address of RTC1 */ +#define ADI_SYS_BASE 0x40002000 /*!< Base address of SYS */ +#define ADI_WDT0_BASE 0x40002c00 /*!< Base address of WDT0 */ +#define ADI_I2C0_BASE 0x40003000 /*!< Base address of I2C0 */ +#define ADI_SPI0_BASE 0x40004000 /*!< Base address of SPI0 */ +#define ADI_SPI1_BASE 0x40004400 /*!< Base address of SPI1 */ +#define ADI_SPI2_BASE 0x40024000 /*!< Base address of SPI2 */ +#define ADI_UART0_BASE 0x40005000 /*!< Base address of UART0 */ +#define ADI_BEEP0_BASE 0x40005c00 /*!< Base address of BEEP0 */ +#define ADI_ADC0_BASE 0x40007000 /*!< Base address of ADC0 */ +#define ADI_DMA0_BASE 0x40010000 /*!< Base address of DMA0 */ +#define ADI_FLCC0_BASE 0x40018000 /*!< Base address of FLCC0 */ +#define ADI_FLCC0_CACHE_BASE 0x40018058 /*!< Base address of FLCC0_CACHE */ +#define ADI_GPIO0_BASE 0x40020000 /*!< Base address of GPIO0 */ +#define ADI_GPIO1_BASE 0x40020040 /*!< Base address of GPIO1 */ +#define ADI_GPIO2_BASE 0x40020080 /*!< Base address of GPIO2 */ +#define ADI_SPORT0_BASE 0x40038000 /*!< Base address of SPORT0 */ +#define ADI_CRC0_BASE 0x40040000 /*!< Base address of CRC0 */ +#define ADI_RNG0_BASE 0x40040400 /*!< Base address of RNG0 */ +#define ADI_CRYPT0_BASE 0x40044000 /*!< Base address of CRYPT0 */ +#define ADI_PMG0_BASE 0x4004c000 /*!< Base address of PMG0 */ +#define ADI_XINT0_BASE 0x4004c080 /*!< Base address of XINT0 */ +#define ADI_CLKG0_OSC_BASE 0x4004c100 /*!< Base address of CLKG0_OSC */ +#define ADI_PMG0_TST_BASE 0x4004c200 /*!< Base address of PMG0_TST */ +#define ADI_CLKG0_CLK_BASE 0x4004c300 /*!< Base address of CLKG0_CLK */ +#define ADI_BUSM0_BASE 0x4004c800 /*!< Base address of BUSM0 */ +#define ADI_PTI0_BASE 0x4004cd00 /*!< Base address of PTI0 */ +#define ADI_NVIC0_BASE 0xe000e000 /*!< Base address of NVIC0 */ + +/*! @} */ + +/* ****************************************************************************** + * Peripheral Pointer Declarations + * *****************************************************************************/ +/*! @Defgroup Pptrdec Peripheral Pointer Declarations + * \Addtogroup Pptrdec + * @{ */ +#define pADI_TMR0 ((ADI_TMR_TypeDef *) ADI_TMR0_BASE ) /*!< Pointer to General Purpose Timer (TMR0) */ +#define pADI_TMR1 ((ADI_TMR_TypeDef *) ADI_TMR1_BASE ) /*!< Pointer to General Purpose Timer (TMR1) */ +#define pADI_TMR2 ((ADI_TMR_TypeDef *) ADI_TMR2_BASE ) /*!< Pointer to General Purpose Timer (TMR2) */ +#define pADI_RTC0 ((ADI_RTC_TypeDef *) ADI_RTC0_BASE ) /*!< Pointer to Real-Time Clock (RTC0) */ +#define pADI_RTC1 ((ADI_RTC_TypeDef *) ADI_RTC1_BASE ) /*!< Pointer to Real-Time Clock (RTC1) */ +#define pADI_SYS ((ADI_SYS_TypeDef *) ADI_SYS_BASE ) /*!< Pointer to System Identification and Debug Enable (SYS) */ +#define pADI_WDT0 ((ADI_WDT_TypeDef *) ADI_WDT0_BASE ) /*!< Pointer to Watchdog Timer (WDT0) */ +#define pADI_I2C0 ((ADI_I2C_TypeDef *) ADI_I2C0_BASE ) /*!< Pointer to I2C Master/Slave (I2C0) */ +#define pADI_SPI0 ((ADI_SPI_TypeDef *) ADI_SPI0_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI0) */ +#define pADI_SPI1 ((ADI_SPI_TypeDef *) ADI_SPI1_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI1) */ +#define pADI_SPI2 ((ADI_SPI_TypeDef *) ADI_SPI2_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI2) */ +#define pADI_UART0 ((ADI_UART_TypeDef *) ADI_UART0_BASE ) /*!< Pointer to (UART0) */ +#define pADI_BEEP0 ((ADI_BEEP_TypeDef *) ADI_BEEP0_BASE ) /*!< Pointer to Beeper Driver (BEEP0) */ +#define pADI_ADC0 ((ADI_ADC_TypeDef *) ADI_ADC0_BASE ) /*!< Pointer to (ADC0) */ +#define pADI_DMA0 ((ADI_DMA_TypeDef *) ADI_DMA0_BASE ) /*!< Pointer to DMA (DMA0) */ +#define pADI_FLCC0 ((ADI_FLCC_TypeDef *) ADI_FLCC0_BASE ) /*!< Pointer to Flash Controller (FLCC0) */ +#define pADI_FLCC0_CACHE ((ADI_FLCC_CACHE_TypeDef *) ADI_FLCC0_CACHE_BASE) /*!< Pointer to Cache Controller (FLCC0_CACHE) */ +#define pADI_GPIO0 ((ADI_GPIO_TypeDef *) ADI_GPIO0_BASE ) /*!< Pointer to (GPIO0) */ +#define pADI_GPIO1 ((ADI_GPIO_TypeDef *) ADI_GPIO1_BASE ) /*!< Pointer to (GPIO1) */ +#define pADI_GPIO2 ((ADI_GPIO_TypeDef *) ADI_GPIO2_BASE ) /*!< Pointer to (GPIO2) */ +#define pADI_SPORT0 ((ADI_SPORT_TypeDef *) ADI_SPORT0_BASE ) /*!< Pointer to Serial Port (SPORT0) */ +#define pADI_CRC0 ((ADI_CRC_TypeDef *) ADI_CRC0_BASE ) /*!< Pointer to CRC Accelerator (CRC0) */ +#define pADI_RNG0 ((ADI_RNG_TypeDef *) ADI_RNG0_BASE ) /*!< Pointer to Random Number Generator (RNG0) */ +#define pADI_CRYPT0 ((ADI_CRYPT_TypeDef *) ADI_CRYPT0_BASE ) /*!< Pointer to Register Map for the Crypto Block (CRYPT0) */ +#define pADI_PMG0 ((ADI_PMG_TypeDef *) ADI_PMG0_BASE ) /*!< Pointer to Power Management (PMG0) */ +#define pADI_XINT0 ((ADI_XINT_TypeDef *) ADI_XINT0_BASE ) /*!< Pointer to External interrupt configuration (XINT0) */ +#define pADI_CLKG0_OSC ((ADI_CLKG_OSC_TypeDef *) ADI_CLKG0_OSC_BASE ) /*!< Pointer to Clocking (CLKG0_OSC) */ +#define pADI_PMG0_TST ((ADI_PMG_TST_TypeDef *) ADI_PMG0_TST_BASE ) /*!< Pointer to Power Management (PMG0_TST) */ +#define pADI_CLKG0_CLK ((ADI_CLKG_CLK_TypeDef *) ADI_CLKG0_CLK_BASE ) /*!< Pointer to Clocking (CLKG0_CLK) */ +#define pADI_BUSM0 ((ADI_BUSM_TypeDef *) ADI_BUSM0_BASE ) /*!< Pointer to Bus matrix (BUSM0) */ +#define pADI_PTI0 ((ADI_PTI_TypeDef *) ADI_PTI0_BASE ) /*!< Pointer to Parallel Test Interface (PTI0) */ +#define pADI_NVIC0 ((ADI_NVIC_TypeDef *) ADI_NVIC0_BASE ) /*!< Pointer to Cortex-M3 Interrupt Controller (NVIC0) */ + +/*! @} */ + + +/* ========================================================================= + *! \enum IRQn_Type + *! \brief Interrupt Number Assignments + * ========================================================================= */ +#ifndef __ADI_NO_DECL_ENUM_IRQn_Type__ + +typedef enum +{ + RESET_IRQn = -15, /*!< Cortex-M3 Reset */ + NonMaskableInt_IRQn = -14, /*!< Cortex-M3 Non-maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M3 Hardware Fault */ + MemoryManagement_IRQn = -12, /*!< Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M3 Bus Fault */ + UsageFault_IRQn = -10, /*!< Cortex-M3 Usage Fault */ + SVCall_IRQn = -5, /*!< Cortex-M3 SVCall Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M3 Debug Monitor */ + PendSV_IRQn = -2, /*!< Cortex-M3 PendSV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M3 SysTick Interrupt */ + RTC1_EVT_IRQn = 0, /*!< Event */ + XINT_EVT0_IRQn = 1, /*!< External Wakeup Interrupt n */ + XINT_EVT1_IRQn = 2, /*!< External Wakeup Interrupt n */ + XINT_EVT2_IRQn = 3, /*!< External Wakeup Interrupt n */ + XINT_EVT3_IRQn = 4, /*!< External Wakeup Interrupt n */ + WDT_EXP_IRQn = 5, /*!< Expiration */ + PMG0_VREG_OVR_IRQn = 6, /*!< Voltage Regulator (VREG) Overvoltage */ + PMG0_BATT_RANGE_IRQn = 7, /*!< Battery Voltage (VBAT) Out of Range */ + RTC0_EVT_IRQn = 8, /*!< Event */ + SYS_GPIO_INTA_IRQn = 9, /*!< GPIO Interrupt A */ + SYS_GPIO_INTB_IRQn = 10, /*!< GPIO Interrupt B */ + TMR0_EVT_IRQn = 11, /*!< Event */ + TMR1_EVT_IRQn = 12, /*!< Event */ + FLCC_EVT_IRQn = 13, /*!< Event */ + UART_EVT_IRQn = 14, /*!< Event */ + SPI0_EVT_IRQn = 15, /*!< Event */ + SPI2_EVT_IRQn = 16, /*!< Event */ + I2C_SLV_EVT_IRQn = 17, /*!< Slave Event */ + I2C_MST_EVT_IRQn = 18, /*!< Master Event */ + DMA_CHAN_ERR_IRQn = 19, /*!< Channel Error */ + DMA0_CH0_DONE_IRQn = 20, /*!< Channel 0 Done */ + DMA0_CH1_DONE_IRQn = 21, /*!< Channel 1 Done */ + DMA0_CH2_DONE_IRQn = 22, /*!< Channel 2 Done */ + DMA0_CH3_DONE_IRQn = 23, /*!< Channel 3 Done */ + DMA0_CH4_DONE_IRQn = 24, /*!< Channel 4 Done */ + DMA0_CH5_DONE_IRQn = 25, /*!< Channel 5 Done */ + DMA0_CH6_DONE_IRQn = 26, /*!< Channel 6 Done */ + DMA0_CH7_DONE_IRQn = 27, /*!< Channel 7 Done */ + DMA0_CH8_DONE_IRQn = 28, /*!< Channel 8 Done */ + DMA0_CH9_DONE_IRQn = 29, /*!< Channel 9 Done */ + DMA0_CH10_DONE_IRQn = 30, /*!< Channel 10 Done */ + DMA0_CH11_DONE_IRQn = 31, /*!< Channel 11 Done */ + DMA0_CH12_DONE_IRQn = 32, /*!< Channel 12 Done */ + DMA0_CH13_DONE_IRQn = 33, /*!< Channel 13 Done */ + DMA0_CH14_DONE_IRQn = 34, /*!< Channel 14 Done */ + DMA0_CH15_DONE_IRQn = 35, /*!< Channel 15 Done */ + SPORT_A_EVT_IRQn = 36, /*!< Channel A Event */ + SPORT_B_EVT_IRQn = 37, /*!< Channel B Event */ + CRYPT_EVT_IRQn = 38, /*!< Event */ + DMA0_CH24_DONE_IRQn = 39, /*!< Channel 24 Done */ + TMR2_EVT_IRQn = 40, /*!< Event */ + CLKG_XTAL_OSC_EVT_IRQn = 41, /*!< Crystal Oscillator Event */ + SPI1_EVT_IRQn = 42, /*!< Event */ + CLKG_PLL_EVT_IRQn = 43, /*!< PLL Event */ + RNG0_EVT_IRQn = 44, /*!< Event */ + BEEP_EVT_IRQn = 45, /*!< Event */ + ADC0_EVT_IRQn = 46, /*!< Event */ + DMA0_CH16_DONE_IRQn = 56, /*!< Channel 16 Done */ + DMA0_CH17_DONE_IRQn = 57, /*!< Channel 17 Done */ + DMA0_CH18_DONE_IRQn = 58, /*!< Channel 18 Done */ + DMA0_CH19_DONE_IRQn = 59, /*!< Channel 19 Done */ + DMA0_CH20_DONE_IRQn = 60, /*!< Channel 20 Done */ + DMA0_CH21_DONE_IRQn = 61, /*!< Channel 21 Done */ + DMA0_CH22_DONE_IRQn = 62, /*!< Channel 22 Done */ + DMA0_CH23_DONE_IRQn = 63, /*!< Channel 23 Done */ +} IRQn_Type; /* typedef name for fixed interrupt numbers */ +#endif /* !__ADI_NO_DECL_ENUM_IRQn_Type__ */ + + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#if defined (__CC_ARM) +#pragma pop +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h new file mode 100755 index 00000000000..ea2c5d22ac7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/ADuCM302x_typedefs.h @@ -0,0 +1,9564 @@ +/* ================================================================================ + + Project : ADuCM302x + File : ADuCM302x_typedefs.h + Description : C Register Structures + + Date : Feb 6, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM302X_TYPEDEFS_H +#define _ADUCM302X_TYPEDEFS_H + +/* pickup integer types */ +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +#if defined ( __CC_ARM ) +#pragma push +#pragma anon_unions +#endif + + +#if defined (_MISRA_RULES) +/* + anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. + Use of unions violates MISRA Rule 18.4. + Anonymous unions are required for this implementation. + Re-use of identifiers violates MISRA Rule 5.7. + Field names are repeated for the ADuCM302x register map. +*/ +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions") +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers") +#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope") +#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers") +#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union") +#endif /* _MISRA_RULES */ + +/** @defgroup LOAD 16-bit Load Value (LOAD) Register + * 16-bit Load Value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_LOAD_Struct + *! \brief 16-bit Load Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ +typedef struct _ADI_TMR_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CURCNT 16-bit Timer Value (CURCNT) Register + * 16-bit Timer Value (CURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CURCNT_Struct + *! \brief 16-bit Timer Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ +typedef struct _ADI_TMR_CURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current Count */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ +typedef struct _ADI_TMR_CTL_t { + union { + struct { + unsigned int PRE : 2; /**< Prescaler */ + unsigned int UP : 1; /**< Count up */ + unsigned int MODE : 1; /**< Timer Mode */ + unsigned int EN : 1; /**< Timer Enable */ + unsigned int CLK : 2; /**< Clock Select */ + unsigned int RLD : 1; /**< Reload Control */ + unsigned int EVTRANGE : 5; /**< Event Select Range */ + unsigned int EVTEN : 1; /**< Event Select */ + unsigned int RSTEN : 1; /**< Counter and Prescale Reset Enable */ + unsigned int SYNCBYP : 1; /**< Synchronization Bypass */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ */ + +/*@}*/ + +/** @defgroup CLRINT Clear Interrupt (CLRINT) Register + * Clear Interrupt (CLRINT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CLRINT_Struct + *! \brief Clear Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ +typedef struct _ADI_TMR_CLRINT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Clear Timeout Interrupt */ + unsigned int EVTCAPT : 1; /**< Clear Captured Event Interrupt */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_CLRINT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ */ + +/*@}*/ + +/** @defgroup CAPTURE Capture (CAPTURE) Register + * Capture (CAPTURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CAPTURE_Struct + *! \brief Capture Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ +typedef struct _ADI_TMR_CAPTURE_t { + union { + struct { + unsigned int VALUE : 16; /**< 16-bit Captured Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CAPTURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ */ + +/*@}*/ + +/** @defgroup ALOAD 16-bit Load Value, Asynchronous (ALOAD) Register + * 16-bit Load Value, Asynchronous (ALOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_ALOAD_Struct + *! \brief 16-bit Load Value, Asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ +typedef struct _ADI_TMR_ALOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value, Asynchronous */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_ALOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ */ + +/*@}*/ + +/** @defgroup ACURCNT 16-bit Timer Value, Asynchronous (ACURCNT) Register + * 16-bit Timer Value, Asynchronous (ACURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_ACURCNT_Struct + *! \brief 16-bit Timer Value, Asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ +typedef struct _ADI_TMR_ACURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Counter Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_ACURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ +typedef struct _ADI_TMR_STAT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Timeout Event Occurred */ + unsigned int CAPTURE : 1; /**< Capture Event Pending */ + unsigned int reserved2 : 4; + unsigned int BUSY : 1; /**< Timer Busy */ + unsigned int PDOK : 1; /**< Clear Interrupt Register Synchronization */ + unsigned int CNTRST : 1; /**< Counter Reset Occurring */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_TMR_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWMCTL PWM Control Register (PWMCTL) Register + * PWM Control Register (PWMCTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_TMR_PWMCTL_MATCH + *! \brief PWM Match Enabled (MATCH) Enumerations + * ========================================================================= */ +typedef enum +{ + TMR_PWMCTL_PWM_TOGGLE = 0, /**< PWM in toggle mode */ + TMR_PWMCTL_PWM_MATCH = 1 /**< PWM in match mode */ +} ADI_TMR_PWMCTL_MATCH; + + +/* ========================================================================= + *! \enum ADI_TMR_PWMCTL_IDLESTATE + *! \brief PWM Idle State (IDLESTATE) Enumerations + * ========================================================================= */ +typedef enum +{ + TMR_PWMCTL_IDLE_LOW = 0, /**< PWM idles low */ + TMR_PWMCTL_IDLE_HIGH = 1 /**< PWM idles high */ +} ADI_TMR_PWMCTL_IDLESTATE; + + +/* ========================================================================== + *! \struct ADI_TMR_PWMCTL_Struct + *! \brief PWM Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ +typedef struct _ADI_TMR_PWMCTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match Enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_PWMCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ */ + +/*@}*/ + +/** @defgroup PWMMATCH PWM Match Value (PWMMATCH) Register + * PWM Match Value (PWMMATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_PWMMATCH_Struct + *! \brief PWM Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ +typedef struct _ADI_TMR_PWMMATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_PWMMATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ */ + +/*@}*/ + +/** @defgroup CR0 RTC Control 0 (CR0) Register + * RTC Control 0 (CR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR0_Struct + *! \brief RTC Control 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ +typedef struct _ADI_RTC_CR0_t { + union { + struct { + unsigned int CNTEN : 1; /**< Global Enable for the RTC */ + unsigned int ALMEN : 1; /**< Enable the RTC Alarm (Absolute) Operation */ + unsigned int ALMINTEN : 1; /**< Enable ALMINT Sourced Alarm Interrupts to the CPU */ + unsigned int TRMEN : 1; /**< Enable RTC Digital Trimming */ + unsigned int MOD60ALMEN : 1; /**< Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ + unsigned int MOD60ALM : 6; /**< Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ + unsigned int MOD60ALMINTEN : 1; /**< Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ + unsigned int ISOINTEN : 1; /**< Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ + unsigned int WPNDERRINTEN : 1; /**< Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ + unsigned int WSYNCINTEN : 1; /**< Enable Write Synchronization Sourced Interrupts to the CPU */ + unsigned int WPNDINTEN : 1; /**< Enable Write Pending Sourced Interrupts to the CPU */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ */ + +/*@}*/ + +/** @defgroup SR0 RTC Status 0 (SR0) Register + * RTC Status 0 (SR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR0_Struct + *! \brief RTC Status 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ +typedef struct _ADI_RTC_SR0_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int ALMINT : 1; /**< Alarm Interrupt Source */ + unsigned int MOD60ALMINT : 1; /**< Modulo-60 RTC Alarm Interrupt Source */ + unsigned int ISOINT : 1; /**< RTC Power-Domain Isolation Interrupt Source */ + unsigned int WPNDERRINT : 1; /**< Write Pending Error Interrupt Source */ + unsigned int WSYNCINT : 1; /**< Write Synchronisation Interrupt */ + unsigned int WPNDINT : 1; /**< Write Pending Interrupt */ + unsigned int WSYNCCR0 : 1; /**< Synchronisation Status of Posted Writes to CR0 */ + unsigned int WSYNCSR0 : 1; /**< Synchronisation Status of Posted Writes to SR0 */ + unsigned int WSYNCCNT0 : 1; /**< Synchronisation Status of Posted Writes to CNT0 */ + unsigned int WSYNCCNT1 : 1; /**< Synchronisation Status of Posted Writes to CNT1 */ + unsigned int WSYNCALM0 : 1; /**< Synchronisation Status of Posted Writes to ALM0 */ + unsigned int WSYNCALM1 : 1; /**< Synchronisation Status of Posted Writes to ALM1 */ + unsigned int WSYNCTRM : 1; /**< Synchronisation Status of Posted Writes to TRM */ + unsigned int ISOENB : 1; /**< Visibility of 32kHz Sourced Registers */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ */ + +/*@}*/ + +/** @defgroup SR1 RTC Status 1 (SR1) Register + * RTC Status 1 (SR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR1_Struct + *! \brief RTC Status 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ +typedef struct _ADI_RTC_SR1_t { + union { + struct { + unsigned int reserved0 : 7; + unsigned int WPNDCR0 : 1; /**< Pending Status of Posted Writes to CR0 */ + unsigned int WPNDSR0 : 1; /**< Pending Status of Posted Clearances of Interrupt Sources in SR0 */ + unsigned int WPNDCNT0 : 1; /**< Pending Status of Posted Writes to CNT0 */ + unsigned int WPNDCNT1 : 1; /**< Pending Status of Posted Writes to CNT1 */ + unsigned int WPNDALM0 : 1; /**< Pending Status of Posted Writes to ALM0 */ + unsigned int WPNDALM1 : 1; /**< Pending Status of Posted Writes to ALM1 */ + unsigned int WPNDTRM : 1; /**< Pending Status of Posted Writes to TRM */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ */ + +/*@}*/ + +/** @defgroup CNT0 RTC Count 0 (CNT0) Register + * RTC Count 0 (CNT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT0_Struct + *! \brief RTC Count 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ +typedef struct _ADI_RTC_CNT0_t { + union { + struct { + unsigned int VALUE : 16; /**< Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ */ + +/*@}*/ + +/** @defgroup CNT1 RTC Count 1 (CNT1) Register + * RTC Count 1 (CNT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT1_Struct + *! \brief RTC Count 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ +typedef struct _ADI_RTC_CNT1_t { + union { + struct { + unsigned int VALUE : 16; /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ */ + +/*@}*/ + +/** @defgroup ALM0 RTC Alarm 0 (ALM0) Register + * RTC Alarm 0 (ALM0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM0_Struct + *! \brief RTC Alarm 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ +typedef struct _ADI_RTC_ALM0_t { + union { + struct { + unsigned int VALUE : 16; /**< Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ */ + +/*@}*/ + +/** @defgroup ALM1 RTC Alarm 1 (ALM1) Register + * RTC Alarm 1 (ALM1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM1_Struct + *! \brief RTC Alarm 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ +typedef struct _ADI_RTC_ALM1_t { + union { + struct { + unsigned int VALUE : 16; /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ */ + +/*@}*/ + +/** @defgroup TRM RTC Trim (TRM) Register + * RTC Trim (TRM) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_TRM_Struct + *! \brief RTC Trim Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ +typedef struct _ADI_RTC_TRM_t { + union { + struct { + unsigned int VALUE : 3; /**< Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ + unsigned int ADD : 1; /**< Trim Polarity */ + unsigned int IVL : 2; /**< Trim Interval in Prescaled RTC Time Units */ + unsigned int IVL2EXPMIN : 4; /**< Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_RTC_TRM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ */ + +/*@}*/ + +/** @defgroup GWY RTC Gateway (GWY) Register + * RTC Gateway (GWY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GWY_Struct + *! \brief RTC Gateway Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ +typedef struct _ADI_RTC_GWY_t { + union { + struct { + unsigned int SWKEY : 16; /**< Software-keyed Command Issued by the CPU */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_GWY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ */ + +/*@}*/ + +/** @defgroup CR1 RTC Control 1 (CR1) Register + * RTC Control 1 (CR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR1_Struct + *! \brief RTC Control 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ +typedef struct _ADI_RTC_CR1_t { + union { + struct { + unsigned int CNTINTEN : 1; /**< Enable for the RTC Count Interrupt Source */ + unsigned int PSINTEN : 1; /**< Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ + unsigned int TRMINTEN : 1; /**< Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ + unsigned int CNTROLLINTEN : 1; /**< Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ + unsigned int CNTMOD60ROLLINTEN : 1; /**< Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ + unsigned int PRESCALE2EXP : 4; /**< Prescale Power of 2 Division Factor for the RTC Base Clock */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ */ + +/*@}*/ + +/** @defgroup SR2 RTC Status 2 (SR2) Register + * RTC Status 2 (SR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR2_Struct + *! \brief RTC Status 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ +typedef struct _ADI_RTC_SR2_t { + union { + struct { + unsigned int CNTINT : 1; /**< RTC Count Interrupt Source */ + unsigned int PSINT : 1; /**< RTC Prescaled, Modulo-1 Boundary Interrupt Source */ + unsigned int TRMINT : 1; /**< RTC Trim Interrupt Source */ + unsigned int CNTROLLINT : 1; /**< RTC Count Roll-Over Interrupt Source */ + unsigned int CNTMOD60ROLLINT : 1; /**< RTC Modulo-60 Count Roll-Over Interrupt Source */ + unsigned int CNTROLL : 1; /**< RTC Count Roll-Over */ + unsigned int CNTMOD60ROLL : 1; /**< RTC Count Modulo-60 Roll-Over */ + unsigned int TRMBDYMIR : 1; /**< Mirror of MOD:RTCTRMBDY */ + unsigned int reserved8 : 4; + unsigned int WPNDCR1MIR : 1; /**< Pending Status of Posted Writes to CR1 */ + unsigned int WPNDALM2MIR : 1; /**< Pending Status of Posted Writes to ALM2 */ + unsigned int WSYNCCR1MIR : 1; /**< Synchronization Status of Posted Writes to CR1 */ + unsigned int WSYNCALM2MIR : 1; /**< Synchronization Status of Posted Writes to ALM2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ */ + +/*@}*/ + +/** @defgroup SNAP0 RTC Snapshot 0 (SNAP0) Register + * RTC Snapshot 0 (SNAP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP0_Struct + *! \brief RTC Snapshot 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ +typedef struct _ADI_RTC_SNAP0_t { + union { + struct { + unsigned int VALUE : 16; /**< Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ */ + +/*@}*/ + +/** @defgroup SNAP1 RTC Snapshot 1 (SNAP1) Register + * RTC Snapshot 1 (SNAP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP1_Struct + *! \brief RTC Snapshot 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ +typedef struct _ADI_RTC_SNAP1_t { + union { + struct { + unsigned int VALUE : 16; /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ */ + +/*@}*/ + +/** @defgroup SNAP2 RTC Snapshot 2 (SNAP2) Register + * RTC Snapshot 2 (SNAP2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP2_Struct + *! \brief RTC Snapshot 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ +typedef struct _ADI_RTC_SNAP2_t { + union { + struct { + unsigned int VALUE : 15; /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ */ + +/*@}*/ + +/** @defgroup MOD RTC Modulo (MOD) Register + * RTC Modulo (MOD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_MOD_Struct + *! \brief RTC Modulo Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ +typedef struct _ADI_RTC_MOD_t { + union { + struct { + unsigned int CNTMOD60 : 6; /**< Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ + unsigned int INCR : 4; /**< Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ + unsigned int TRMBDY : 1; /**< Trim Boundary Indicator */ + unsigned int CNT0_4TOZERO : 5; /**< Mirror of CNT0[4:0] */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_MOD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ */ + +/*@}*/ + +/** @defgroup CNT2 RTC Count 2 (CNT2) Register + * RTC Count 2 (CNT2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT2_Struct + *! \brief RTC Count 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ +typedef struct _ADI_RTC_CNT2_t { + union { + struct { + unsigned int VALUE : 15; /**< Fractional Bits of the RTC Real-Time Count */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ */ + +/*@}*/ + +/** @defgroup ALM2 RTC Alarm 2 (ALM2) Register + * RTC Alarm 2 (ALM2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM2_Struct + *! \brief RTC Alarm 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ +typedef struct _ADI_RTC_ALM2_t { + union { + struct { + unsigned int VALUE : 15; /**< Fractional Bits of the Alarm Target Time */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ */ + +/*@}*/ + +/** @defgroup SR3 RTC Status 3 (SR3) Register + * RTC Status 3 (SR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR3_Struct + *! \brief RTC Status 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ +typedef struct _ADI_RTC_SR3_t { + union { + struct { + unsigned int IC0IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 2 */ + unsigned int IC3IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 3 */ + unsigned int IC4IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 4 */ + unsigned int reserved5 : 3; + unsigned int ALMINTMIR : 1; /**< Read-only Mirror of the ALMINT Interrupt Source in SR0 Register */ + unsigned int SS1IRQ : 1; /**< Sticky Interrupt Source for SensorStrobe Channel 1 */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ */ + +/*@}*/ + +/** @defgroup CR2IC RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register + * RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR2IC_Struct + *! \brief RTC Control 2 for Configuring Input Capture Channels Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ +typedef struct _ADI_RTC_CR2IC_t { + union { + struct { + unsigned int IC0EN : 1; /**< Enable for the RTC Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2EN : 1; /**< Enable for the RTC Input Capture Channel 2 */ + unsigned int IC3EN : 1; /**< Enable for the RTC Input Capture Channel 3 */ + unsigned int IC4EN : 1; /**< Enable for the RTC Input Capture Channel 4 */ + unsigned int IC0LH : 1; /**< Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ + unsigned int reserved6 : 1; + unsigned int IC2LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ + unsigned int IC3LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ + unsigned int IC4LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ + unsigned int IC0IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 0 */ + unsigned int reserved11 : 1; + unsigned int IC2IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 2 */ + unsigned int IC3IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 3 */ + unsigned int IC4IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 4 */ + unsigned int ICOWUSEN : 1; /**< Enable Overwrite of Unread Snapshots for All Input Capture Channels */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR2IC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ */ + +/*@}*/ + +/** @defgroup CR3SS RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register + * RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR3SS_Struct + *! \brief RTC Control 3 for Configuring SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ +typedef struct _ADI_RTC_CR3SS_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SS1EN : 1; /**< Enable for SensorStrobe Channel 1 */ + unsigned int reserved2 : 7; + unsigned int SS1IRQEN : 1; /**< Interrupt Enable for SensorStrobe Channel 1 */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR3SS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ */ + +/*@}*/ + +/** @defgroup CR4SS RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register + * RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR4SS_SS1MSKEN + *! \brief Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 (SS1MSKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR4SS_NO_MSK = 0, /**< Do not apply a mask to SensorStrobe Channel 1 Register */ + RTC_CR4SS_THERM_MSK = 1 /**< Apply thermometer decoded mask */ +} ADI_RTC_CR4SS_SS1MSKEN; + + +/* ========================================================================== + *! \struct ADI_RTC_CR4SS_Struct + *! \brief RTC Control 4 for Configuring SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ +typedef struct _ADI_RTC_CR4SS_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SS1MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ + unsigned int reserved2 : 7; + unsigned int SS1ARLEN : 1; /**< Enable for Auto-Reloading When SensorStrobe Match Occurs */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR4SS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ */ + +/*@}*/ + +/** @defgroup SSMSK RTC Mask for SensorStrobe Channel (SSMSK) Register + * RTC Mask for SensorStrobe Channel (SSMSK) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SSMSK_Struct + *! \brief RTC Mask for SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ +typedef struct _ADI_RTC_SSMSK_t { + union { + struct { + unsigned int SSMSK : 16; /**< Thermometer-Encoded Masks for SensorStrobe Channels */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SSMSK_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ */ + +/*@}*/ + +/** @defgroup SS1ARL RTC Auto-Reload for SensorStrobe Channel 1 (SS1ARL) Register + * RTC Auto-Reload for SensorStrobe Channel 1 (SS1ARL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1ARL_Struct + *! \brief RTC Auto-Reload for SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1ARL_t__ +typedef struct _ADI_RTC_SS1ARL_t { + union { + struct { + unsigned int SS1ARL : 16; /**< Auto-Reload Value When SensorStrobe Match Occurs */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1ARL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1ARL_t__ */ + +/*@}*/ + +/** @defgroup IC2 RTC Input Capture Channel 2 (IC2) Register + * RTC Input Capture Channel 2 (IC2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC2_Struct + *! \brief RTC Input Capture Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ +typedef struct _ADI_RTC_IC2_t { + union { + struct { + unsigned int IC2 : 16; /**< RTC Input Capture Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ */ + +/*@}*/ + +/** @defgroup IC3 RTC Input Capture Channel 3 (IC3) Register + * RTC Input Capture Channel 3 (IC3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC3_Struct + *! \brief RTC Input Capture Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ +typedef struct _ADI_RTC_IC3_t { + union { + struct { + unsigned int IC3 : 16; /**< RTC Input Capture Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ */ + +/*@}*/ + +/** @defgroup IC4 RTC Input Capture Channel 4 (IC4) Register + * RTC Input Capture Channel 4 (IC4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC4_Struct + *! \brief RTC Input Capture Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ +typedef struct _ADI_RTC_IC4_t { + union { + struct { + unsigned int IC4 : 16; /**< RTC Input Capture Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ */ + +/*@}*/ + +/** @defgroup SS1 RTC SensorStrobe Channel 1 (SS1) Register + * RTC SensorStrobe Channel 1 (SS1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1_Struct + *! \brief RTC SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ +typedef struct _ADI_RTC_SS1_t { + union { + struct { + unsigned int SS1 : 16; /**< SensorStrobe Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ */ + +/*@}*/ + +/** @defgroup SR4 RTC Status 4 (SR4) Register + * RTC Status 4 (SR4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR4_Struct + *! \brief RTC Status 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ +typedef struct _ADI_RTC_SR4_t { + union { + struct { + unsigned int WSYNCSR3 : 1; /**< Synchronisation Status of Posted Writes to SR3 */ + unsigned int WSYNCCR2IC : 1; /**< Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ + unsigned int WSYNCCR3SS : 1; /**< Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR4SS : 1; /**< Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCSSMSK : 1; /**< Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ + unsigned int WSYNCSS1ARL : 1; /**< Synchronization Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */ + unsigned int WSYNCSS1 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ + unsigned int reserved7 : 3; + unsigned int RSYNCIC0 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 0 */ + unsigned int reserved11 : 1; + unsigned int RSYNCIC2 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 2 */ + unsigned int RSYNCIC3 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 3 */ + unsigned int RSYNCIC4 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 4 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ */ + +/*@}*/ + +/** @defgroup SR5 RTC Status 5 (SR5) Register + * RTC Status 5 (SR5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR5_Struct + *! \brief RTC Status 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ +typedef struct _ADI_RTC_SR5_t { + union { + struct { + unsigned int WPENDSR3 : 1; /**< Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ + unsigned int WPENDCR2IC : 1; /**< Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ + unsigned int WPENDCR3SS : 1; /**< Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR4SS : 1; /**< Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDSSMSK : 1; /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ + unsigned int WPENDSS1ARL : 1; /**< Pending Status of Posted Writes to RTC Auto-Reload for SensorStrobe Channel 1 Register */ + unsigned int WPENDSS1 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 1 */ + unsigned int reserved7 : 3; + unsigned int RPENDIC0 : 1; /**< Pending Status of Posted Reads of Input Capture Channel 0 */ + unsigned int reserved11 : 1; + unsigned int RPENDIC2 : 1; /**< Pending Status of Posted Reads of IC2 */ + unsigned int RPENDIC3 : 1; /**< Pending Status of Posted Reads of IC3 */ + unsigned int RPENDIC4 : 1; /**< Pending Status of Posted Reads of IC4 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ */ + +/*@}*/ + +/** @defgroup SR6 RTC Status 6 (SR6) Register + * RTC Status 6 (SR6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR6_Struct + *! \brief RTC Status 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ +typedef struct _ADI_RTC_SR6_t { + union { + struct { + unsigned int IC0UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 2 */ + unsigned int IC3UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 3 */ + unsigned int IC4UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 4 */ + unsigned int reserved5 : 3; + unsigned int IC0SNAP : 1; /**< Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ + unsigned int FRZCNTPTR : 2; /**< Pointer for the Triple-Read Sequence of FRZCNT */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ */ + +/*@}*/ + +/** @defgroup SS1TGT RTC SensorStrobe Channel 1 Target (SS1TGT) Register + * RTC SensorStrobe Channel 1 Target (SS1TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1TGT_Struct + *! \brief RTC SensorStrobe Channel 1 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ +typedef struct _ADI_RTC_SS1TGT_t { + union { + struct { + unsigned int SS1TGT : 16; /**< Current Target Value for the SensorStrobe Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ */ + +/*@}*/ + +/** @defgroup FRZCNT RTC Freeze Count (FRZCNT) Register + * RTC Freeze Count (FRZCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_FRZCNT_Struct + *! \brief RTC Freeze Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ +typedef struct _ADI_RTC_FRZCNT_t { + union { + struct { + unsigned int FRZCNT : 16; /**< RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_FRZCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ */ + +/*@}*/ + +/** @defgroup ADIID ADI Identification (ADIID) Register + * ADI Identification (ADIID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_ADIID_Struct + *! \brief ADI Identification Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ +typedef struct _ADI_SYS_ADIID_t { + union { + struct { + unsigned int VALUE : 16; /**< ADI Cortex Device */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_ADIID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ */ + +/*@}*/ + +/** @defgroup CHIPID Chip Identifier (CHIPID) Register + * Chip Identifier (CHIPID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_CHIPID_Struct + *! \brief Chip Identifier Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ +typedef struct _ADI_SYS_CHIPID_t { + union { + struct { + unsigned int REV : 4; /**< Silicon Revision */ + unsigned int PARTID : 12; /**< Part Identifier */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_CHIPID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ */ + +/*@}*/ + +/** @defgroup SWDEN Serial Wire Debug Enable (SWDEN) Register + * Serial Wire Debug Enable (SWDEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_SWDEN_Struct + *! \brief Serial Wire Debug Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ +typedef struct _ADI_SYS_SWDEN_t { + union { + struct { + unsigned int VALUE : 16; /**< SWD Interface Enable */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_SWDEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ */ + +/*@}*/ + +/** @defgroup LOAD Load Value (LOAD) Register + * Load Value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_LOAD_Struct + *! \brief Load Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ +typedef struct _ADI_WDT_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CCNT Current Count Value (CCNT) Register + * Current Count Value (CCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_CCNT_Struct + *! \brief Current Count Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ +typedef struct _ADI_WDT_CCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current Count Value */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_CCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_WDT_CTL_IRQ + *! \brief Timer Interrupt (IRQ) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_RST = 0, /**< WDT asserts reset when timed out */ + WDT_CTL_INT = 1 /**< WDT generates interrupt when timed out */ +} ADI_WDT_CTL_IRQ; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_PRE + *! \brief Prescaler (PRE) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_DIV1 = 0, /**< Source clock/1 */ + WDT_CTL_DIV16 = 1, /**< Source clock/16 */ + WDT_CTL_DIV256 = 2 /**< Source clock/256 (default) */ +} ADI_WDT_CTL_PRE; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_EN + *! \brief Timer Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_WDT_DIS = 0, /**< WDT not enabled */ + WDT_CTL_WDT_EN = 1 /**< WDT enabled */ +} ADI_WDT_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_MODE + *! \brief Timer Mode (MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_FREE_RUN = 0, /**< Free running mode */ + WDT_CTL_PERIODIC = 1 /**< Periodic mode */ +} ADI_WDT_CTL_MODE; + + +/* ========================================================================== + *! \struct ADI_WDT_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ +typedef struct _ADI_WDT_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int IRQ : 1; /**< Timer Interrupt */ + unsigned int PRE : 2; /**< Prescaler */ + unsigned int reserved4 : 1; + unsigned int EN : 1; /**< Timer Enable */ + unsigned int MODE : 1; /**< Timer Mode */ + unsigned int SPARE : 1; /**< Unused Spare Bit */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_WDT_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ */ + +/*@}*/ + +/** @defgroup RESTART Clear Interrupt (RESTART) Register + * Clear Interrupt (RESTART) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_RESTART_Struct + *! \brief Clear Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ +typedef struct _ADI_WDT_RESTART_t { + union { + struct { + unsigned int CLRWORD : 16; /**< Clear Watchdog */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_RESTART_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ +typedef struct _ADI_WDT_STAT_t { + union { + struct { + unsigned int IRQ : 1; /**< WDT Interrupt */ + unsigned int CLRIRQ : 1; /**< Clear Interrupt Register Write Sync in Progress */ + unsigned int LOADING : 1; /**< Load Register Write Sync in Progress */ + unsigned int COUNTING : 1; /**< Control Register Write Sync in Progress */ + unsigned int LOCKED : 1; /**< Lock Status Bit */ + unsigned int RSTCTL : 1; /**< Reset Control Register Written and Locked */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_WDT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ */ + +/*@}*/ + +/** @defgroup MCTL Master Control (MCTL) Register + * Master Control (MCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MCTL_Struct + *! \brief Master Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ +typedef struct _ADI_I2C_MCTL_t { + union { + struct { + unsigned int MASEN : 1; /**< Master Enable */ + unsigned int COMPLETE : 1; /**< Start Back-off Disable */ + unsigned int LOOPBACK : 1; /**< Internal Loopback Enable */ + unsigned int STRETCHSCL : 1; /**< Stretch SCL Enable */ + unsigned int IENMRX : 1; /**< Receive Request Interrupt Enable */ + unsigned int IENMTX : 1; /**< Transmit Request Interrupt Enable */ + unsigned int IENALOST : 1; /**< Arbitration Lost Interrupt Enable */ + unsigned int IENACK : 1; /**< ACK Not Received Interrupt Enable */ + unsigned int IENCMP : 1; /**< Transaction Completed (or Stop Detected) Interrupt Enable */ + unsigned int MXMITDEC : 1; /**< Decrement Master Tx FIFO Status When a Byte Txed */ + unsigned int MRXDMA : 1; /**< Enable Master Rx DMA Request */ + unsigned int MTXDMA : 1; /**< Enable Master Tx DMA Request */ + unsigned int BUSCLR : 1; /**< Bus-Clear Enable */ + unsigned int STOPBUSCLR : 1; /**< Prestop Bus Clear */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ */ + +/*@}*/ + +/** @defgroup MSTAT Master Status (MSTAT) Register + * Master Status (MSTAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_I2C_MSTAT_MTXF + *! \brief Master Transmit FIFO Status (MTXF) Enumerations + * ========================================================================= */ +typedef enum +{ + I2C_MSTAT_FIFO_EMPTY = 0, /**< FIFO Empty. */ + I2C_MSTAT_FIFO_1BYTE = 2, /**< 1 byte in FIFO. */ + I2C_MSTAT_FIFO_FULL = 3 /**< FIFO Full. */ +} ADI_I2C_MSTAT_MTXF; + + +/* ========================================================================== + *! \struct ADI_I2C_MSTAT_Struct + *! \brief Master Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ +typedef struct _ADI_I2C_MSTAT_t { + union { + struct { + unsigned int MTXF : 2; /**< Master Transmit FIFO Status */ + unsigned int MTXREQ : 1; /**< Master Transmit Request/Clear Master Transmit Interrupt */ + unsigned int MRXREQ : 1; /**< Master Receive Request */ + unsigned int NACKADDR : 1; /**< ACK Not Received in Response to an Address */ + unsigned int ALOST : 1; /**< Arbitration Lost */ + unsigned int MBUSY : 1; /**< Master Busy */ + unsigned int NACKDATA : 1; /**< ACK Not Received in Response to Data Write */ + unsigned int TCOMP : 1; /**< Transaction Complete or Stop Detected */ + unsigned int MRXOVR : 1; /**< Master Receive FIFO Overflow */ + unsigned int LINEBUSY : 1; /**< Line is Busy */ + unsigned int MSTOP : 1; /**< STOP Driven by This I2C Master */ + unsigned int MTXUNDR : 1; /**< Master Transmit Underflow */ + unsigned int SDAFILT : 1; /**< State of SDA Line */ + unsigned int SCLFILT : 1; /**< State of SCL Line */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ */ + +/*@}*/ + +/** @defgroup MRX Master Receive Data (MRX) Register + * Master Receive Data (MRX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MRX_Struct + *! \brief Master Receive Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ +typedef struct _ADI_I2C_MRX_t { + union { + struct { + unsigned int VALUE : 8; /**< Master Receive Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MRX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ */ + +/*@}*/ + +/** @defgroup MTX Master Transmit Data (MTX) Register + * Master Transmit Data (MTX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MTX_Struct + *! \brief Master Transmit Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ +typedef struct _ADI_I2C_MTX_t { + union { + struct { + unsigned int VALUE : 8; /**< Master Transmit Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MTX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ */ + +/*@}*/ + +/** @defgroup MRXCNT Master Receive Data Count (MRXCNT) Register + * Master Receive Data Count (MRXCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MRXCNT_Struct + *! \brief Master Receive Data Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ +typedef struct _ADI_I2C_MRXCNT_t { + union { + struct { + unsigned int VALUE : 8; /**< Receive Count */ + unsigned int EXTEND : 1; /**< Extended Read */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MRXCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ */ + +/*@}*/ + +/** @defgroup MCRXCNT Master Current Receive Data Count (MCRXCNT) Register + * Master Current Receive Data Count (MCRXCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MCRXCNT_Struct + *! \brief Master Current Receive Data Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ +typedef struct _ADI_I2C_MCRXCNT_t { + union { + struct { + unsigned int VALUE : 8; /**< Current Receive Count */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MCRXCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ */ + +/*@}*/ + +/** @defgroup ADDR1 Master Address Byte 1 (ADDR1) Register + * Master Address Byte 1 (ADDR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ADDR1_Struct + *! \brief Master Address Byte 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ +typedef struct _ADI_I2C_ADDR1_t { + union { + struct { + unsigned int VALUE : 8; /**< Address Byte 1 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ADDR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ */ + +/*@}*/ + +/** @defgroup ADDR2 Master Address Byte 2 (ADDR2) Register + * Master Address Byte 2 (ADDR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ADDR2_Struct + *! \brief Master Address Byte 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ +typedef struct _ADI_I2C_ADDR2_t { + union { + struct { + unsigned int VALUE : 8; /**< Address Byte 2 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ADDR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ */ + +/*@}*/ + +/** @defgroup BYT Start Byte (BYT) Register + * Start Byte (BYT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_BYT_Struct + *! \brief Start Byte Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ +typedef struct _ADI_I2C_BYT_t { + union { + struct { + unsigned int SBYTE : 8; /**< Start Byte */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_BYT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ */ + +/*@}*/ + +/** @defgroup DIV Serial Clock Period Divisor (DIV) Register + * Serial Clock Period Divisor (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_DIV_Struct + *! \brief Serial Clock Period Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ +typedef struct _ADI_I2C_DIV_t { + union { + struct { + unsigned int LOW : 8; /**< Serial Clock Low Time */ + unsigned int HIGH : 8; /**< Serial Clock High Time */ + }; + uint16_t VALUE16; + }; +} ADI_I2C_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ */ + +/*@}*/ + +/** @defgroup SCTL Slave Control (SCTL) Register + * Slave Control (SCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SCTL_Struct + *! \brief Slave Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ +typedef struct _ADI_I2C_SCTL_t { + union { + struct { + unsigned int SLVEN : 1; /**< Slave Enable */ + unsigned int ADR10EN : 1; /**< Enabled 10-bit Addressing */ + unsigned int GCEN : 1; /**< General Call Enable */ + unsigned int HGCEN : 1; /**< Hardware General Call Enable */ + unsigned int GCSBCLR : 1; /**< General Call Status Bit Clear */ + unsigned int EARLYTXR : 1; /**< Early Transmit Request Mode */ + unsigned int reserved6 : 1; + unsigned int NACK : 1; /**< NACK Next Communication */ + unsigned int IENSTOP : 1; /**< Stop Condition Detected Interrupt Enable */ + unsigned int IENSRX : 1; /**< Slave Receive Request Interrupt Enable */ + unsigned int IENSTX : 1; /**< Slave Transmit Request Interrupt Enable */ + unsigned int STXDEC : 1; /**< Decrement Slave Tx FIFO Status When a Byte is Txed */ + unsigned int IENREPST : 1; /**< Repeated Start Interrupt Enable */ + unsigned int SRXDMA : 1; /**< Enable Slave Rx DMA Request */ + unsigned int STXDMA : 1; /**< Enable Slave Tx DMA Request */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ */ + +/*@}*/ + +/** @defgroup SSTAT Slave I2C Status/Error/IRQ (SSTAT) Register + * Slave I2C Status/Error/IRQ (SSTAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SSTAT_Struct + *! \brief Slave I2C Status/Error/IRQ Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ +typedef struct _ADI_I2C_SSTAT_t { + union { + struct { + unsigned int STXFSEREQ : 1; /**< Slave Tx FIFO Status or Early Request */ + unsigned int STXUNDR : 1; /**< Slave Transmit FIFO Underflow */ + unsigned int STXREQ : 1; /**< Slave Transmit Request/Slave Transmit Interrupt */ + unsigned int SRXREQ : 1; /**< Slave Receive Request */ + unsigned int SRXOVR : 1; /**< Slave Receive FIFO Overflow */ + unsigned int NOACK : 1; /**< ACK Not Generated by the Slave */ + unsigned int SBUSY : 1; /**< Slave Busy */ + unsigned int GCINT : 1; /**< General Call Interrupt */ + unsigned int GCID : 2; /**< General ID */ + unsigned int STOP : 1; /**< Stop After Start and Matching Address */ + unsigned int IDMAT : 2; /**< Device ID Matched */ + unsigned int REPSTART : 1; /**< Repeated Start and Matching Address */ + unsigned int START : 1; /**< Start and Matching Address */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ */ + +/*@}*/ + +/** @defgroup SRX Slave Receive (SRX) Register + * Slave Receive (SRX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SRX_Struct + *! \brief Slave Receive Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ +typedef struct _ADI_I2C_SRX_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Receive Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SRX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ */ + +/*@}*/ + +/** @defgroup STX Slave Transmit (STX) Register + * Slave Transmit (STX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_STX_Struct + *! \brief Slave Transmit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ +typedef struct _ADI_I2C_STX_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Transmit Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_STX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ */ + +/*@}*/ + +/** @defgroup ALT Hardware General Call ID (ALT) Register + * Hardware General Call ID (ALT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ALT_Struct + *! \brief Hardware General Call ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ +typedef struct _ADI_I2C_ALT_t { + union { + struct { + unsigned int ID : 8; /**< Slave Alt */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ALT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ */ + +/*@}*/ + +/** @defgroup ID0 First Slave Address Device ID (ID0) Register + * First Slave Address Device ID (ID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID0_Struct + *! \brief First Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ +typedef struct _ADI_I2C_ID0_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 0 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ */ + +/*@}*/ + +/** @defgroup ID1 Second Slave Address Device ID (ID1) Register + * Second Slave Address Device ID (ID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID1_Struct + *! \brief Second Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ +typedef struct _ADI_I2C_ID1_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 1 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ */ + +/*@}*/ + +/** @defgroup ID2 Third Slave Address Device ID (ID2) Register + * Third Slave Address Device ID (ID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID2_Struct + *! \brief Third Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ +typedef struct _ADI_I2C_ID2_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 2 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ */ + +/*@}*/ + +/** @defgroup ID3 Fourth Slave Address Device ID (ID3) Register + * Fourth Slave Address Device ID (ID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID3_Struct + *! \brief Fourth Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ +typedef struct _ADI_I2C_ID3_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 3 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ */ + +/*@}*/ + +/** @defgroup STAT Master and Slave FIFO Status (STAT) Register + * Master and Slave FIFO Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_STAT_Struct + *! \brief Master and Slave FIFO Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ +typedef struct _ADI_I2C_STAT_t { + union { + struct { + unsigned int STXF : 2; /**< Slave Transmit FIFO Status */ + unsigned int SRXF : 2; /**< Slave Receive FIFO Status */ + unsigned int MTXF : 2; /**< Master Transmit FIFO Status */ + unsigned int MRXF : 2; /**< Master Receive FIFO Status */ + unsigned int SFLUSH : 1; /**< Flush the Slave Transmit FIFO */ + unsigned int MFLUSH : 1; /**< Flush the Master Transmit FIFO */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_I2C_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ */ + +/*@}*/ + +/** @defgroup SHCTL Shared Control (SHCTL) Register + * Shared Control (SHCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SHCTL_Struct + *! \brief Shared Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ +typedef struct _ADI_I2C_SHCTL_t { + union { + struct { + unsigned int RST : 1; /**< Reset START STOP Detect Circuit */ + unsigned int reserved1 : 15; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SHCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ */ + +/*@}*/ + +/** @defgroup TCTL Timing Control Register (TCTL) Register + * Timing Control Register (TCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_TCTL_Struct + *! \brief Timing Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ +typedef struct _ADI_I2C_TCTL_t { + union { + struct { + unsigned int THDATIN : 5; /**< Data in Hold Start */ + unsigned int reserved5 : 3; + unsigned int FILTEROFF : 1; /**< Input Filter Control */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_I2C_TCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ */ + +/*@}*/ + +/** @defgroup ASTRETCH_SCL Automatic Stretch SCL (ASTRETCH_SCL) Register + * Automatic Stretch SCL (ASTRETCH_SCL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ASTRETCH_SCL_Struct + *! \brief Automatic Stretch SCL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ +typedef struct _ADI_I2C_ASTRETCH_SCL_t { + union { + struct { + unsigned int MST : 4; /**< Master Automatic Stretch Mode */ + unsigned int SLV : 4; /**< Slave Automatic Stretch Mode */ + unsigned int MSTTMO : 1; /**< Master Automatic Stretch Timeout */ + unsigned int SLVTMO : 1; /**< Slave Automatic Stretch Timeout */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ASTRETCH_SCL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ +typedef struct _ADI_SPI_STAT_t { + union { + struct { + unsigned int IRQ : 1; /**< SPI Interrupt Status */ + unsigned int XFRDONE : 1; /**< SPI Transfer Completion */ + unsigned int TXEMPTY : 1; /**< SPI Tx FIFO Empty Interrupt */ + unsigned int TXDONE : 1; /**< SPI Tx Done in Read Command Mode */ + unsigned int TXUNDR : 1; /**< SPI Tx FIFO Underflow */ + unsigned int TXIRQ : 1; /**< SPI Tx IRQ */ + unsigned int RXIRQ : 1; /**< SPI Rx IRQ */ + unsigned int RXOVR : 1; /**< SPI Rx FIFO Overflow */ + unsigned int reserved8 : 3; + unsigned int CS : 1; /**< CS Status */ + unsigned int CSERR : 1; /**< Detected a CS Error Condition in Slave Mode */ + unsigned int CSRISE : 1; /**< Detected a Rising Edge on CS, in Slave CON Mode */ + unsigned int CSFALL : 1; /**< Detected a Falling Edge on CS, in Slave CON Mode */ + unsigned int RDY : 1; /**< Detected an Edge on Ready Indicator for Flow Control */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ */ + +/*@}*/ + +/** @defgroup RX Receive (RX) Register + * Receive (RX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_RX_Struct + *! \brief Receive Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ +typedef struct _ADI_SPI_RX_t { + union { + struct { + unsigned int BYTE1 : 8; /**< 8-bit Receive Buffer */ + unsigned int BYTE2 : 8; /**< 8-bit Receive Buffer, Used Only in DMA Modes */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_RX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ */ + +/*@}*/ + +/** @defgroup TX Transmit (TX) Register + * Transmit (TX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_TX_Struct + *! \brief Transmit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ +typedef struct _ADI_SPI_TX_t { + union { + struct { + unsigned int BYTE1 : 8; /**< 8-bit Transmit Buffer */ + unsigned int BYTE2 : 8; /**< 8-bit Transmit Buffer, Used Only in DMA Modes */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_TX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ */ + +/*@}*/ + +/** @defgroup DIV SPI Baud Rate Selection (DIV) Register + * SPI Baud Rate Selection (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_DIV_Struct + *! \brief SPI Baud Rate Selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ +typedef struct _ADI_SPI_DIV_t { + union { + struct { + unsigned int VALUE : 6; /**< SPI Clock Divider */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_SPI_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ */ + +/*@}*/ + +/** @defgroup CTL SPI Configuration (CTL) Register + * SPI Configuration (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CTL_Struct + *! \brief SPI Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ +typedef struct _ADI_SPI_CTL_t { + union { + struct { + unsigned int SPIEN : 1; /**< SPI Enable */ + unsigned int MASEN : 1; /**< Master Mode Enable */ + unsigned int CPHA : 1; /**< Serial Clock Phase Mode */ + unsigned int CPOL : 1; /**< Serial Clock Polarity */ + unsigned int WOM : 1; /**< SPI Wired-OR Mode */ + unsigned int LSB : 1; /**< LSB First Transfer Enable */ + unsigned int TIM : 1; /**< SPI Transfer and Interrupt Mode */ + unsigned int ZEN : 1; /**< Transmit Zeros Enable */ + unsigned int RXOF : 1; /**< Rx Overflow Overwrite Enable */ + unsigned int OEN : 1; /**< Slave MISO Output Enable */ + unsigned int LOOPBACK : 1; /**< Loopback Enable */ + unsigned int CON : 1; /**< Continuous Transfer Enable */ + unsigned int RFLUSH : 1; /**< SPI Rx FIFO Flush Enable */ + unsigned int TFLUSH : 1; /**< SPI Tx FIFO Flush Enable */ + unsigned int CSRST : 1; /**< Reset Mode for CS Error Bit */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ */ + +/*@}*/ + +/** @defgroup IEN SPI Interrupts Enable (IEN) Register + * SPI Interrupts Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_IEN_Struct + *! \brief SPI Interrupts Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ +typedef struct _ADI_SPI_IEN_t { + union { + struct { + unsigned int IRQMODE : 3; /**< SPI IRQ Mode Bits */ + unsigned int reserved3 : 5; + unsigned int CS : 1; /**< Enable Interrupt on Every CS Edge in Slave CON Mode */ + unsigned int TXUNDR : 1; /**< Tx Underflow Interrupt Enable */ + unsigned int RXOVR : 1; /**< Rx Overflow Interrupt Enable */ + unsigned int RDY : 1; /**< Ready Signal Edge Interrupt Enable */ + unsigned int TXDONE : 1; /**< SPI Transmit Done Interrupt Enable */ + unsigned int XFRDONE : 1; /**< SPI Transfer Completion Interrupt Enable */ + unsigned int TXEMPTY : 1; /**< Tx FIFO Empty Interrupt Enable */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_SPI_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ */ + +/*@}*/ + +/** @defgroup CNT Transfer Byte Count (CNT) Register + * Transfer Byte Count (CNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CNT_Struct + *! \brief Transfer Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ +typedef struct _ADI_SPI_CNT_t { + union { + struct { + unsigned int VALUE : 14; /**< Transfer Byte Count */ + unsigned int reserved14 : 1; + unsigned int FRAMECONT : 1; /**< Continue Frame */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_CNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ */ + +/*@}*/ + +/** @defgroup DMA SPI DMA Enable (DMA) Register + * SPI DMA Enable (DMA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_DMA_Struct + *! \brief SPI DMA Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ +typedef struct _ADI_SPI_DMA_t { + union { + struct { + unsigned int EN : 1; /**< Enable DMA for Data Transfer */ + unsigned int TXEN : 1; /**< Enable Transmit DMA Request */ + unsigned int RXEN : 1; /**< Enable Receive DMA Request */ + unsigned int reserved3 : 13; + }; + uint16_t VALUE16; + }; +} ADI_SPI_DMA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ */ + +/*@}*/ + +/** @defgroup FIFO_STAT FIFO Status (FIFO_STAT) Register + * FIFO Status (FIFO_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_FIFO_STAT_Struct + *! \brief FIFO Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ +typedef struct _ADI_SPI_FIFO_STAT_t { + union { + struct { + unsigned int TX : 4; /**< SPI Tx FIFO Status */ + unsigned int reserved4 : 4; + unsigned int RX : 4; /**< SPI Rx FIFO Dtatus */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_SPI_FIFO_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ */ + +/*@}*/ + +/** @defgroup RD_CTL Read Control (RD_CTL) Register + * Read Control (RD_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_RD_CTL_Struct + *! \brief Read Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ +typedef struct _ADI_SPI_RD_CTL_t { + union { + struct { + unsigned int CMDEN : 1; /**< Read Command Enable */ + unsigned int OVERLAP : 1; /**< Tx/Rx Overlap Mode */ + unsigned int TXBYTES : 4; /**< Transmit Byte Count - 1 (Read Command) */ + unsigned int reserved6 : 2; + unsigned int THREEPIN : 1; /**< Three Pin SPI Mode */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_SPI_RD_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ */ + +/*@}*/ + +/** @defgroup FLOW_CTL Flow Control (FLOW_CTL) Register + * Flow Control (FLOW_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_FLOW_CTL_Struct + *! \brief Flow Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ +typedef struct _ADI_SPI_FLOW_CTL_t { + union { + struct { + unsigned int MODE : 2; /**< Flow Control Mode */ + unsigned int reserved2 : 2; + unsigned int RDYPOL : 1; /**< Polarity of RDY/MISO Line */ + unsigned int reserved5 : 3; + unsigned int RDBURSTSZ : 4; /**< Read Data Burst Size - 1 */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_SPI_FLOW_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ */ + +/*@}*/ + +/** @defgroup WAIT_TMR Wait Timer for Flow Control (WAIT_TMR) Register + * Wait Timer for Flow Control (WAIT_TMR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_WAIT_TMR_Struct + *! \brief Wait Timer for Flow Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ +typedef struct _ADI_SPI_WAIT_TMR_t { + union { + struct { + unsigned int VALUE : 16; /**< Wait Timer */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_WAIT_TMR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ */ + +/*@}*/ + +/** @defgroup CS_CTL Chip Select Control for Multi-slave Connections (CS_CTL) Register + * Chip Select Control for Multi-slave Connections (CS_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CS_CTL_Struct + *! \brief Chip Select Control for Multi-slave Connections Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ +typedef struct _ADI_SPI_CS_CTL_t { + union { + struct { + unsigned int SEL : 4; /**< Chip Select Control */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CS_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ */ + +/*@}*/ + +/** @defgroup CS_OVERRIDE Chip Select Override (CS_OVERRIDE) Register + * Chip Select Override (CS_OVERRIDE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CS_OVERRIDE_Struct + *! \brief Chip Select Override Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ +typedef struct _ADI_SPI_CS_OVERRIDE_t { + union { + struct { + unsigned int CTL : 2; /**< CS Override Control */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CS_OVERRIDE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ */ + +/*@}*/ + +/** @defgroup RX Receive Buffer Register (RX) Register + * Receive Buffer Register (RX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RX_Struct + *! \brief Receive Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ +typedef struct _ADI_UART_RX_t { + union { + struct { + unsigned int RBR : 8; /**< Receive Buffer Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_RX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ */ + +/*@}*/ + +/** @defgroup TX Transmit Holding Register (TX) Register + * Transmit Holding Register (TX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_TX_Struct + *! \brief Transmit Holding Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ +typedef struct _ADI_UART_TX_t { + union { + struct { + unsigned int THR : 8; /**< Transmit Holding Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_TX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ */ + +/*@}*/ + +/** @defgroup IEN Interrupt Enable (IEN) Register + * Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_IEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ +typedef struct _ADI_UART_IEN_t { + union { + struct { + unsigned int ERBFI : 1; /**< Receive Buffer Full Interrupt */ + unsigned int ETBEI : 1; /**< Transmit Buffer Empty Interrupt */ + unsigned int ELSI : 1; /**< Rx Status Interrupt */ + unsigned int EDSSI : 1; /**< Modem Status Interrupt */ + unsigned int EDMAT : 1; /**< DMA Requests in Transmit Mode */ + unsigned int EDMAR : 1; /**< DMA Requests in Receive Mode */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_UART_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ */ + +/*@}*/ + +/** @defgroup IIR Interrupt ID (IIR) Register + * Interrupt ID (IIR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_IIR_STAT + *! \brief Interrupt Status (STAT) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_IIR_STAT_EDSSI = 0, /**< Modem status interrupt (Read MSR register to clear) */ + UART_IIR_STAT_ETBEI = 1, /**< Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */ + UART_IIR_STAT_ERBFI = 2, /**< Receive buffer full interrupt (Read Rx register to clear) */ + UART_IIR_STAT_RLSI = 3, /**< Receive line status interrupt (Read LSR register to clear) */ + UART_IIR_STAT_RFTOI = 6 /**< Receive FIFO time-out interrupt (Read Rx register to clear) */ +} ADI_UART_IIR_STAT; + + +/* ========================================================================== + *! \struct ADI_UART_IIR_Struct + *! \brief Interrupt ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ +typedef struct _ADI_UART_IIR_t { + union { + struct { + unsigned int NIRQ : 1; /**< Interrupt Flag */ + unsigned int STAT : 3; /**< Interrupt Status */ + unsigned int reserved4 : 2; + unsigned int FEND : 2; /**< FIFO Enabled */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_IIR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ */ + +/*@}*/ + +/** @defgroup LCR Line Control (LCR) Register + * Line Control (LCR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_LCR_SP + *! \brief Stick Parity (SP) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_LCR_PAR_NOTFORCED = 0, /**< Parity will not be forced based on Parity Select and Parity Enable bits. */ + UART_LCR_PAR_FORCED = 1 /**< Parity forced based on Parity Select and Parity Enable bits. */ +} ADI_UART_LCR_SP; + + +/* ========================================================================== + *! \struct ADI_UART_LCR_Struct + *! \brief Line Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ +typedef struct _ADI_UART_LCR_t { + union { + struct { + unsigned int WLS : 2; /**< Word Length Select */ + unsigned int STOP : 1; /**< Stop Bit */ + unsigned int PEN : 1; /**< Parity Enable */ + unsigned int EPS : 1; /**< Parity Select */ + unsigned int SP : 1; /**< Stick Parity */ + unsigned int BRK : 1; /**< Set Break */ + unsigned int reserved7 : 9; + }; + uint16_t VALUE16; + }; +} ADI_UART_LCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ */ + +/*@}*/ + +/** @defgroup MCR Modem Control (MCR) Register + * Modem Control (MCR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_MCR_Struct + *! \brief Modem Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ +typedef struct _ADI_UART_MCR_t { + union { + struct { + unsigned int DTR : 1; /**< Data Terminal Ready */ + unsigned int RTS : 1; /**< Request to Send */ + unsigned int OUT1 : 1; /**< Output 1 */ + unsigned int OUT2 : 1; /**< Output 2 */ + unsigned int LOOPBACK : 1; /**< Loopback Mode */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_MCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ */ + +/*@}*/ + +/** @defgroup LSR Line Status (LSR) Register + * Line Status (LSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_LSR_Struct + *! \brief Line Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ +typedef struct _ADI_UART_LSR_t { + union { + struct { + unsigned int DR : 1; /**< Data Ready */ + unsigned int OE : 1; /**< Overrun Error */ + unsigned int PE : 1; /**< Parity Error */ + unsigned int FE : 1; /**< Framing Error */ + unsigned int BI : 1; /**< Break Indicator */ + unsigned int THRE : 1; /**< Transmit Register Empty */ + unsigned int TEMT : 1; /**< Transmit and Shift Register Empty Status */ + unsigned int FIFOERR : 1; /**< Rx FIFO Parity Error/Frame Error/Break Indication */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_LSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ */ + +/*@}*/ + +/** @defgroup MSR Modem Status (MSR) Register + * Modem Status (MSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_MSR_Struct + *! \brief Modem Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ +typedef struct _ADI_UART_MSR_t { + union { + struct { + unsigned int DCTS : 1; /**< Delta CTS */ + unsigned int DDSR : 1; /**< Delta DSR */ + unsigned int TERI : 1; /**< Trailing Edge RI */ + unsigned int DDCD : 1; /**< Delta DCD */ + unsigned int CTS : 1; /**< Clear to Send */ + unsigned int DSR : 1; /**< Data Set Ready */ + unsigned int RI : 1; /**< Ring Indicator */ + unsigned int DCD : 1; /**< Data Carrier Detect */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_MSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ */ + +/*@}*/ + +/** @defgroup SCR Scratch Buffer (SCR) Register + * Scratch Buffer (SCR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_SCR_Struct + *! \brief Scratch Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ +typedef struct _ADI_UART_SCR_t { + union { + struct { + unsigned int SCR : 8; /**< Scratch */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_SCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ */ + +/*@}*/ + +/** @defgroup FCR FIFO Control (FCR) Register + * FIFO Control (FCR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_FCR_FDMAMD + *! \brief FIFO DMA Mode (FDMAMD) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_FCR_MODE0 = 0, /**< In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */ + UART_FCR_MODE1 = 1 /**< in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */ +} ADI_UART_FCR_FDMAMD; + + +/* ========================================================================== + *! \struct ADI_UART_FCR_Struct + *! \brief FIFO Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ +typedef struct _ADI_UART_FCR_t { + union { + struct { + unsigned int FIFOEN : 1; /**< FIFO Enable as to Work in 16550 Mode */ + unsigned int RFCLR : 1; /**< Clear Rx FIFO */ + unsigned int TFCLR : 1; /**< Clear Tx FIFO */ + unsigned int FDMAMD : 1; /**< FIFO DMA Mode */ + unsigned int reserved4 : 2; + unsigned int RFTRIG : 2; /**< Rx FIFO Trigger Level */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_FCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ */ + +/*@}*/ + +/** @defgroup FBR Fractional Baud Rate (FBR) Register + * Fractional Baud Rate (FBR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_FBR_Struct + *! \brief Fractional Baud Rate Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ +typedef struct _ADI_UART_FBR_t { + union { + struct { + unsigned int DIVN : 11; /**< Fractional Baud Rate N Divide Bits 0 to 2047 */ + unsigned int DIVM : 2; /**< Fractional Baud Rate M Divide Bits 1 to 3 */ + unsigned int reserved13 : 2; + unsigned int FBEN : 1; /**< Fractional Baud Rate Generator Enable */ + }; + uint16_t VALUE16; + }; +} ADI_UART_FBR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ */ + +/*@}*/ + +/** @defgroup DIV Baud Rate Divider (DIV) Register + * Baud Rate Divider (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_DIV_Struct + *! \brief Baud Rate Divider Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ +typedef struct _ADI_UART_DIV_t { + union { + struct { + unsigned int DIV : 16; /**< Baud Rate Divider */ + }; + uint16_t VALUE16; + }; +} ADI_UART_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ */ + +/*@}*/ + +/** @defgroup LCR2 Second Line Control (LCR2) Register + * Second Line Control (LCR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_LCR2_Struct + *! \brief Second Line Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ +typedef struct _ADI_UART_LCR2_t { + union { + struct { + unsigned int OSR : 2; /**< Over Sample Rate */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_UART_LCR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ */ + +/*@}*/ + +/** @defgroup CTL UART Control Register (CTL) Register + * UART Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_CTL_RXINV + *! \brief Invert Receiver Line (RXINV) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_CTL_NOTINV_RX = 0, /**< Don't invert receiver line (idling high). */ + UART_CTL_INV_RX = 1 /**< Invert receiver line (idling low). */ +} ADI_UART_CTL_RXINV; + + +/* ========================================================================== + *! \struct ADI_UART_CTL_Struct + *! \brief UART Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ +typedef struct _ADI_UART_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int FORCECLK : 1; /**< Force UCLK on */ + unsigned int reserved2 : 2; + unsigned int RXINV : 1; /**< Invert Receiver Line */ + unsigned int reserved5 : 3; + unsigned int REV : 8; /**< UART Revision ID */ + }; + uint16_t VALUE16; + }; +} ADI_UART_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ */ + +/*@}*/ + +/** @defgroup RFC RX FIFO Byte Count (RFC) Register + * RX FIFO Byte Count (RFC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RFC_Struct + *! \brief RX FIFO Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ +typedef struct _ADI_UART_RFC_t { + union { + struct { + unsigned int RFC : 5; /**< Current Rx FIFO Data Bytes */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_RFC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ */ + +/*@}*/ + +/** @defgroup TFC TX FIFO Byte Count (TFC) Register + * TX FIFO Byte Count (TFC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_TFC_Struct + *! \brief TX FIFO Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ +typedef struct _ADI_UART_TFC_t { + union { + struct { + unsigned int TFC : 5; /**< Current Tx FIFO Data Bytes */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_TFC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ */ + +/*@}*/ + +/** @defgroup RSC RS485 Half-duplex Control (RSC) Register + * RS485 Half-duplex Control (RSC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RSC_Struct + *! \brief RS485 Half-duplex Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ +typedef struct _ADI_UART_RSC_t { + union { + struct { + unsigned int OENP : 1; /**< SOUT_EN Polarity */ + unsigned int OENSP : 1; /**< SOUT_EN De-assert Before Full Stop Bit(s) */ + unsigned int DISRX : 1; /**< Disable Rx When Transmitting */ + unsigned int DISTX : 1; /**< Hold off Tx When Receiving */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_UART_RSC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ */ + +/*@}*/ + +/** @defgroup ACR Auto Baud Control (ACR) Register + * Auto Baud Control (ACR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ACR_Struct + *! \brief Auto Baud Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ +typedef struct _ADI_UART_ACR_t { + union { + struct { + unsigned int ABE : 1; /**< Auto Baud Enable */ + unsigned int DNIEN : 1; /**< Enable Done Interrupt */ + unsigned int TOIEN : 1; /**< Enable Time-out Interrupt */ + unsigned int reserved3 : 1; + unsigned int SEC : 3; /**< Starting Edge Count */ + unsigned int reserved7 : 1; + unsigned int EEC : 4; /**< Ending Edge Count */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_UART_ACR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ */ + +/*@}*/ + +/** @defgroup ASRL Auto Baud Status (Low) (ASRL) Register + * Auto Baud Status (Low) (ASRL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ASRL_Struct + *! \brief Auto Baud Status (Low) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ +typedef struct _ADI_UART_ASRL_t { + union { + struct { + unsigned int DONE : 1; /**< Auto Baud Done Successfully */ + unsigned int BRKTO : 1; /**< Timed Out Due to Long Time Break Condition */ + unsigned int NSETO : 1; /**< Timed Out Due to No Valid Start Edge Found */ + unsigned int NEETO : 1; /**< Timed Out Due to No Valid Ending Edge Found */ + unsigned int CNT : 12; /**< CNT[11:0] Auto Baud Counter Value */ + }; + uint16_t VALUE16; + }; +} ADI_UART_ASRL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ */ + +/*@}*/ + +/** @defgroup ASRH Auto Baud Status (High) (ASRH) Register + * Auto Baud Status (High) (ASRH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ASRH_Struct + *! \brief Auto Baud Status (High) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ +typedef struct _ADI_UART_ASRH_t { + union { + struct { + unsigned int CNT : 8; /**< CNT[19:12] Auto Baud Counter Value */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_ASRH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ */ + +/*@}*/ + +/** @defgroup CFG Beeper Configuration (CFG) Register + * Beeper Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_CFG_Struct + *! \brief Beeper Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ +typedef struct _ADI_BEEP_CFG_t { + union { + struct { + unsigned int SEQREPEAT : 8; /**< Beeper Sequence Repeat Value */ + unsigned int EN : 1; /**< Beeper Enable */ + unsigned int reserved9 : 1; + unsigned int ASTARTIRQ : 1; /**< Tone A Start IRQ */ + unsigned int AENDIRQ : 1; /**< Tone A End IRQ */ + unsigned int BSTARTIRQ : 1; /**< Tone B Start IRQ */ + unsigned int BENDIRQ : 1; /**< Tone B End IRQ */ + unsigned int SEQNEARENDIRQ : 1; /**< Sequence 1 Cycle from End IRQ */ + unsigned int SEQATENDIRQ : 1; /**< Sequence End IRQ */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ */ + +/*@}*/ + +/** @defgroup STAT Beeper Status (STAT) Register + * Beeper Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_STAT_Struct + *! \brief Beeper Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ +typedef struct _ADI_BEEP_STAT_t { + union { + struct { + unsigned int SEQREMAIN : 8; /**< Remaining Tone-pair Iterations to Play in Sequence Mode */ + unsigned int BUSY : 1; /**< Beeper is Busy */ + unsigned int reserved9 : 1; + unsigned int ASTARTED : 1; /**< Tone A Has Started */ + unsigned int AENDED : 1; /**< Tone A Has Ended */ + unsigned int BSTARTED : 1; /**< Tone B Has Started */ + unsigned int BENDED : 1; /**< Tone B Has Ended */ + unsigned int SEQNEAREND : 1; /**< Sequencer Last Tone-pair Has Started */ + unsigned int SEQENDED : 1; /**< Sequencer Has Ended */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ */ + +/*@}*/ + +/** @defgroup TONEA Tone A Data (TONEA) Register + * Tone A Data (TONEA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_TONEA_Struct + *! \brief Tone A Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ +typedef struct _ADI_BEEP_TONEA_t { + union { + struct { + unsigned int DUR : 8; /**< Tone Duration */ + unsigned int FREQ : 7; /**< Tone Frequency */ + unsigned int DIS : 1; /**< Output Disable */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_TONEA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ */ + +/*@}*/ + +/** @defgroup TONEB Tone B Data (TONEB) Register + * Tone B Data (TONEB) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_TONEB_Struct + *! \brief Tone B Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ +typedef struct _ADI_BEEP_TONEB_t { + union { + struct { + unsigned int DUR : 8; /**< Tone Duration */ + unsigned int FREQ : 7; /**< Tone Frequency */ + unsigned int DIS : 1; /**< Output Disable */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_TONEB_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ */ + +/*@}*/ + +/** @defgroup CFG ADC Configuration (CFG) Register + * ADC Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_ADC_CFG_VREFSEL + *! \brief Select Vref as 1.25V or 2.5V (VREFSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + ADC_CFG_V_2P5 = 0, /**< Vref = 2.5V */ + ADC_CFG_V_1P25 = 1 /**< Vref = 1.25V */ +} ADI_ADC_CFG_VREFSEL; + + +/* ========================================================================= + *! \enum ADI_ADC_CFG_REFBUFEN + *! \brief Enable Internal Reference Buffer (REFBUFEN) Enumerations + * ========================================================================= */ +typedef enum +{ + ADC_CFG_EXT_REF = 0, /**< External reference is used */ + ADC_CFG_BUF_REF = 1 /**< Reference buffer is enabled */ +} ADI_ADC_CFG_REFBUFEN; + + +/* ========================================================================== + *! \struct ADI_ADC_CFG_Struct + *! \brief ADC Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ +typedef struct _ADI_ADC_CFG_t { + union { + struct { + unsigned int PWRUP : 1; /**< Powering up the ADC */ + unsigned int VREFSEL : 1; /**< Select Vref as 1.25V or 2.5V */ + unsigned int REFBUFEN : 1; /**< Enable Internal Reference Buffer */ + unsigned int reserved3 : 1; + unsigned int EN : 1; /**< Enable ADC Subsystem */ + unsigned int STARTCAL : 1; /**< Start a New Offset Calibration Cycle */ + unsigned int RST : 1; /**< Reset */ + unsigned int SINKEN : 1; /**< Enable Additional Sink Current Capability */ + unsigned int TMPEN : 1; /**< Power up Temperature Sensor */ + unsigned int FAST_DISCH : 1; /**< Fast Switchover of Vref from 2.5 to 1.25 */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ */ + +/*@}*/ + +/** @defgroup PWRUP ADC Power-up Time (PWRUP) Register + * ADC Power-up Time (PWRUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_PWRUP_Struct + *! \brief ADC Power-up Time Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ +typedef struct _ADI_ADC_PWRUP_t { + union { + struct { + unsigned int WAIT : 10; /**< Program This with 526/PCLKDIVCNT */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_ADC_PWRUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ */ + +/*@}*/ + +/** @defgroup CAL_WORD Calibration Word (CAL_WORD) Register + * Calibration Word (CAL_WORD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CAL_WORD_Struct + *! \brief Calibration Word Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ +typedef struct _ADI_ADC_CAL_WORD_t { + union { + struct { + unsigned int VALUE : 7; /**< Offset Calibration Word */ + unsigned int reserved7 : 9; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CAL_WORD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ */ + +/*@}*/ + +/** @defgroup CNV_CFG ADC Conversion Configuration (CNV_CFG) Register + * ADC Conversion Configuration (CNV_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CNV_CFG_Struct + *! \brief ADC Conversion Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ +typedef struct _ADI_ADC_CNV_CFG_t { + union { + struct { + unsigned int SEL : 8; /**< Selection of Channel(s) to Convert */ + unsigned int BAT : 1; /**< Battery Monitoring Enable */ + unsigned int TMP : 1; /**< Temperature Measurement 1 */ + unsigned int TMP2 : 1; /**< Temperature Measurement 2 */ + unsigned int reserved11 : 1; + unsigned int AUTOMODE : 1; /**< Auto Mode Enable */ + unsigned int DMAEN : 1; /**< DMA Channel Enable */ + unsigned int SINGLE : 1; /**< Single Conversion Start */ + unsigned int MULTI : 1; /**< Multiple Conversions */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CNV_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ */ + +/*@}*/ + +/** @defgroup CNV_TIME ADC Conversion Time (CNV_TIME) Register + * ADC Conversion Time (CNV_TIME) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CNV_TIME_Struct + *! \brief ADC Conversion Time Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ +typedef struct _ADI_ADC_CNV_TIME_t { + union { + struct { + unsigned int SAMPTIME : 8; /**< Sampling Time */ + unsigned int DLY : 8; /**< Delay Between Two Consecutive Conversions */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CNV_TIME_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ */ + +/*@}*/ + +/** @defgroup AVG_CFG Averaging Configuration (AVG_CFG) Register + * Averaging Configuration (AVG_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_AVG_CFG_Struct + *! \brief Averaging Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ +typedef struct _ADI_ADC_AVG_CFG_t { + union { + struct { + unsigned int FACTOR : 8; /**< Averaging Factor */ + unsigned int reserved8 : 6; + unsigned int OS : 1; /**< Enable Oversampling */ + unsigned int EN : 1; /**< Enable Averaging on Channels Enabled in Enable Register */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_AVG_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ */ + +/*@}*/ + +/** @defgroup IRQ_EN Interrupt Enable (IRQ_EN) Register + * Interrupt Enable (IRQ_EN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_IRQ_EN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ +typedef struct _ADI_ADC_IRQ_EN_t { + union { + struct { + unsigned int CNVDONE : 1; /**< Enable Conversion Done Interrupt */ + unsigned int reserved1 : 9; + unsigned int CALDONE : 1; /**< Enable Interrupt for Calibration Done */ + unsigned int OVF : 1; /**< Enable Overflow Interrupt */ + unsigned int ALERT : 1; /**< Interrupt on Crossing Lower or Higher Limit Enable */ + unsigned int RDY : 1; /**< Set to Enable Interrupt When ADC is Ready to Convert */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_ADC_IRQ_EN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ */ + +/*@}*/ + +/** @defgroup STAT ADC Status (STAT) Register + * ADC Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_STAT_Struct + *! \brief ADC Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ +typedef struct _ADI_ADC_STAT_t { + union { + struct { + unsigned int DONE0 : 1; /**< Conversion Done on Channel 0 */ + unsigned int DONE1 : 1; /**< Conversion Done on Channel 1 */ + unsigned int DONE2 : 1; /**< Conversion Done on Channel 2 */ + unsigned int DONE3 : 1; /**< Conversion Done on Channel 3 */ + unsigned int DONE4 : 1; /**< Conversion Done on Channel 4 */ + unsigned int DONE5 : 1; /**< Conversion Done on Channel 5 */ + unsigned int DONE6 : 1; /**< Conversion Done on Channel 6 */ + unsigned int DONE7 : 1; /**< Conversion Done on Channel 7 */ + unsigned int BATDONE : 1; /**< Conversion Done - Battery Monitoring */ + unsigned int TMPDONE : 1; /**< Conversion Done for Temperature Sensing */ + unsigned int TMP2DONE : 1; /**< Conversion Done for Temperature Sensing 2 */ + unsigned int reserved11 : 3; + unsigned int CALDONE : 1; /**< Calibration Done */ + unsigned int RDY : 1; /**< ADC Ready to Start Converting */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ */ + +/*@}*/ + +/** @defgroup OVF Overflow of Output Registers (OVF) Register + * Overflow of Output Registers (OVF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_OVF_Struct + *! \brief Overflow of Output Registers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ +typedef struct _ADI_ADC_OVF_t { + union { + struct { + unsigned int CH0 : 1; /**< Overflow in CH0_OUT */ + unsigned int CH1 : 1; /**< Overflow in CH1_OUT */ + unsigned int CH2 : 1; /**< Overflow in CH2_OUT */ + unsigned int CH3 : 1; /**< Overflow in CH3_OUT */ + unsigned int CH4 : 1; /**< Overflow in CH4_OUT */ + unsigned int CH5 : 1; /**< Overflow in CH5_OUT */ + unsigned int CH6 : 1; /**< Overflow in CH6_OUT */ + unsigned int CH7 : 1; /**< Overflow in CH7_OUT */ + unsigned int BAT : 1; /**< Overflow in BAT_OUT */ + unsigned int TMP : 1; /**< Overflow in TMP_OUT */ + unsigned int TMP2 : 1; /**< Overflow in TMP2_OUT */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_OVF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ */ + +/*@}*/ + +/** @defgroup ALERT Alert Indication (ALERT) Register + * Alert Indication (ALERT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_ALERT_Struct + *! \brief Alert Indication Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ +typedef struct _ADI_ADC_ALERT_t { + union { + struct { + unsigned int HI0 : 1; /**< Channel 0 High Alert Status */ + unsigned int LO0 : 1; /**< Channel 0 Low Alert Status */ + unsigned int HI1 : 1; /**< Channel 1 High Alert Status */ + unsigned int LO1 : 1; /**< Channel 1 Low Alert Status */ + unsigned int HI2 : 1; /**< Channel 2 High Alert Status */ + unsigned int LO2 : 1; /**< Channel 2 Low Alert Status */ + unsigned int HI3 : 1; /**< Channel 3 High Alert Status */ + unsigned int LO3 : 1; /**< Channel 3 Low Alert Status */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_ADC_ALERT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ */ + +/*@}*/ + +/** @defgroup CH0_OUT Conversion Result Channel 0 (CH0_OUT) Register + * Conversion Result Channel 0 (CH0_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH0_OUT_Struct + *! \brief Conversion Result Channel 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ +typedef struct _ADI_ADC_CH0_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH0_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH1_OUT Conversion Result Channel 1 (CH1_OUT) Register + * Conversion Result Channel 1 (CH1_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH1_OUT_Struct + *! \brief Conversion Result Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ +typedef struct _ADI_ADC_CH1_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH1_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH2_OUT Conversion Result Channel 2 (CH2_OUT) Register + * Conversion Result Channel 2 (CH2_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH2_OUT_Struct + *! \brief Conversion Result Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ +typedef struct _ADI_ADC_CH2_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH2_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH3_OUT Conversion Result Channel 3 (CH3_OUT) Register + * Conversion Result Channel 3 (CH3_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH3_OUT_Struct + *! \brief Conversion Result Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ +typedef struct _ADI_ADC_CH3_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH3_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH4_OUT Conversion Result Channel 4 (CH4_OUT) Register + * Conversion Result Channel 4 (CH4_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH4_OUT_Struct + *! \brief Conversion Result Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ +typedef struct _ADI_ADC_CH4_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH4_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH5_OUT Conversion Result Channel 5 (CH5_OUT) Register + * Conversion Result Channel 5 (CH5_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH5_OUT_Struct + *! \brief Conversion Result Channel 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ +typedef struct _ADI_ADC_CH5_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 5 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH5_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH6_OUT Conversion Result Channel 6 (CH6_OUT) Register + * Conversion Result Channel 6 (CH6_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH6_OUT_Struct + *! \brief Conversion Result Channel 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ +typedef struct _ADI_ADC_CH6_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 6 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH6_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH7_OUT Conversion Result Channel 7 (CH7_OUT) Register + * Conversion Result Channel 7 (CH7_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH7_OUT_Struct + *! \brief Conversion Result Channel 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ +typedef struct _ADI_ADC_CH7_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Channel 7 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH7_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ */ + +/*@}*/ + +/** @defgroup BAT_OUT Battery Monitoring Result (BAT_OUT) Register + * Battery Monitoring Result (BAT_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_BAT_OUT_Struct + *! \brief Battery Monitoring Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ +typedef struct _ADI_ADC_BAT_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Battery Monitoring */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_BAT_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ */ + +/*@}*/ + +/** @defgroup TMP_OUT Temperature Result (TMP_OUT) Register + * Temperature Result (TMP_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_TMP_OUT_Struct + *! \brief Temperature Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ +typedef struct _ADI_ADC_TMP_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Temperature Measurement 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_TMP_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ */ + +/*@}*/ + +/** @defgroup TMP2_OUT Temperature Result 2 (TMP2_OUT) Register + * Temperature Result 2 (TMP2_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_TMP2_OUT_Struct + *! \brief Temperature Result 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ +typedef struct _ADI_ADC_TMP2_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result of Temperature Measurement 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_TMP2_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ */ + +/*@}*/ + +/** @defgroup DMA_OUT DMA Output Register (DMA_OUT) Register + * DMA Output Register (DMA_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_DMA_OUT_Struct + *! \brief DMA Output Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ +typedef struct _ADI_ADC_DMA_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion Result for DMA */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_DMA_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ */ + +/*@}*/ + +/** @defgroup LIM0_LO Channel 0 Low Limit (LIM0_LO) Register + * Channel 0 Low Limit (LIM0_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM0_LO_Struct + *! \brief Channel 0 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ +typedef struct _ADI_ADC_LIM0_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low Limit for Channel 0 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable Low Limit Comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM0_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM0_HI Channel 0 High Limit (LIM0_HI) Register + * Channel 0 High Limit (LIM0_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM0_HI_Struct + *! \brief Channel 0 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ +typedef struct _ADI_ADC_LIM0_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High Limit for Channel 0 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable High Limit Comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM0_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS0 Channel 0 Hysteresis (HYS0) Register + * Channel 0 Hysteresis (HYS0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS0_Struct + *! \brief Channel 0 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ +typedef struct _ADI_ADC_HYS0_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis Value for Channel 0 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Number of Conversion Cycles to Monitor Channel 0 */ + unsigned int EN : 1; /**< Enable Hysteresis for Comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ */ + +/*@}*/ + +/** @defgroup LIM1_LO Channel 1 Low Limit (LIM1_LO) Register + * Channel 1 Low Limit (LIM1_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM1_LO_Struct + *! \brief Channel 1 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ +typedef struct _ADI_ADC_LIM1_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low Limit for Channel 1 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable Low Limit Comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM1_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM1_HI Channel 1 High Limit (LIM1_HI) Register + * Channel 1 High Limit (LIM1_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM1_HI_Struct + *! \brief Channel 1 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ +typedef struct _ADI_ADC_LIM1_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High Limit for Channel 1 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable High Limit Comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM1_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS1 Channel 1 Hysteresis (HYS1) Register + * Channel 1 Hysteresis (HYS1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS1_Struct + *! \brief Channel 1 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ +typedef struct _ADI_ADC_HYS1_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis Value for Channel 1 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Number of Conversion Cycles to Monitor Channel 1 */ + unsigned int EN : 1; /**< Enable Hysteresis for Comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ */ + +/*@}*/ + +/** @defgroup LIM2_LO Channel 2 Low Limit (LIM2_LO) Register + * Channel 2 Low Limit (LIM2_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM2_LO_Struct + *! \brief Channel 2 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ +typedef struct _ADI_ADC_LIM2_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low Limit for Channel 2 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable Low Limit Comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM2_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM2_HI Channel 2 High Limit (LIM2_HI) Register + * Channel 2 High Limit (LIM2_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM2_HI_Struct + *! \brief Channel 2 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ +typedef struct _ADI_ADC_LIM2_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High Limit for Channel 2 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable High Limit Comparison on Channel */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM2_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS2 Channel 2 Hysteresis (HYS2) Register + * Channel 2 Hysteresis (HYS2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS2_Struct + *! \brief Channel 2 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ +typedef struct _ADI_ADC_HYS2_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis Value for Channel 2 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Number of Conversion Cycles to Monitor Channel 2 */ + unsigned int EN : 1; /**< Enable Hysteresis for Comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ */ + +/*@}*/ + +/** @defgroup LIM3_LO Channel 3 Low Limit (LIM3_LO) Register + * Channel 3 Low Limit (LIM3_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM3_LO_Struct + *! \brief Channel 3 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ +typedef struct _ADI_ADC_LIM3_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low Limit for Channel 3 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable Low Limit Comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM3_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM3_HI Channel 3 High Limit (LIM3_HI) Register + * Channel 3 High Limit (LIM3_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM3_HI_Struct + *! \brief Channel 3 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ +typedef struct _ADI_ADC_LIM3_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High Limit for Channel 3 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< Enable High Limit Comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM3_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS3 Channel 3 Hysteresis (HYS3) Register + * Channel 3 Hysteresis (HYS3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS3_Struct + *! \brief Channel 3 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ +typedef struct _ADI_ADC_HYS3_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis Value for Channel 3 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Number of Conversion Cycles to Monitor Channel 3 */ + unsigned int EN : 1; /**< Enable Hysteresis for Comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ */ + +/*@}*/ + +/** @defgroup CFG1 Reference Buffer Low Power Mode (CFG1) Register + * Reference Buffer Low Power Mode (CFG1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CFG1_Struct + *! \brief Reference Buffer Low Power Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ +typedef struct _ADI_ADC_CFG1_t { + union { + struct { + unsigned int RBUFLP : 1; /**< Enable Low Power Mode for Reference Buffer */ + unsigned int reserved1 : 15; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CFG1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ */ + +/*@}*/ + +/** @defgroup STAT DMA Status (STAT) Register + * DMA Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_STAT_Struct + *! \brief DMA Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ +typedef struct _ADI_DMA_STAT_t { + union { + struct { + unsigned int MEN : 1; /**< Enable Status of the Controller */ + unsigned int reserved1 : 15; + unsigned int CHANM1 : 5; /**< Number of Available DMA Channels Minus 1 */ + unsigned int reserved21 : 11; + }; + uint32_t VALUE32; + }; +} ADI_DMA_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ */ + +/*@}*/ + +/** @defgroup CFG DMA Configuration (CFG) Register + * DMA Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_CFG_Struct + *! \brief DMA Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ +typedef struct _ADI_DMA_CFG_t { + union { + struct { + unsigned int MEN : 1; /**< Controller Enable */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_DMA_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ */ + +/*@}*/ + +/** @defgroup PDBPTR DMA Channel Primary Control Database Pointer (PDBPTR) Register + * DMA Channel Primary Control Database Pointer (PDBPTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PDBPTR_Struct + *! \brief DMA Channel Primary Control Database Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ +typedef struct _ADI_DMA_PDBPTR_t { + union { + struct { + unsigned int ADDR : 32; /**< Pointer to the Base Address of the Primary Data Structure */ + }; + uint32_t VALUE32; + }; +} ADI_DMA_PDBPTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ */ + +/*@}*/ + +/** @defgroup ADBPTR DMA Channel Alternate Control Database Pointer (ADBPTR) Register + * DMA Channel Alternate Control Database Pointer (ADBPTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ADBPTR_Struct + *! \brief DMA Channel Alternate Control Database Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ +typedef struct _ADI_DMA_ADBPTR_t { + union { + struct { + unsigned int ADDR : 32; /**< Base Address of the Alternate Data Structure */ + }; + uint32_t VALUE32; + }; +} ADI_DMA_ADBPTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ */ + +/*@}*/ + +/** @defgroup SWREQ DMA Channel Software Request (SWREQ) Register + * DMA Channel Software Request (SWREQ) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SWREQ_Struct + *! \brief DMA Channel Software Request Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ +typedef struct _ADI_DMA_SWREQ_t { + union { + struct { + unsigned int CHAN : 25; /**< Generate Software Request */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SWREQ_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ */ + +/*@}*/ + +/** @defgroup RMSK_SET DMA Channel Request Mask Set (RMSK_SET) Register + * DMA Channel Request Mask Set (RMSK_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_RMSK_SET_Struct + *! \brief DMA Channel Request Mask Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ +typedef struct _ADI_DMA_RMSK_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Mask Requests from DMA Channels */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_RMSK_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ */ + +/*@}*/ + +/** @defgroup RMSK_CLR DMA Channel Request Mask Clear (RMSK_CLR) Register + * DMA Channel Request Mask Clear (RMSK_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_RMSK_CLR_Struct + *! \brief DMA Channel Request Mask Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ +typedef struct _ADI_DMA_RMSK_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Clear Request Mask Set Bits */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_RMSK_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ */ + +/*@}*/ + +/** @defgroup EN_SET DMA Channel Enable Set (EN_SET) Register + * DMA Channel Enable Set (EN_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_EN_SET_Struct + *! \brief DMA Channel Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ +typedef struct _ADI_DMA_EN_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Enable DMA Channels */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_EN_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ */ + +/*@}*/ + +/** @defgroup EN_CLR DMA Channel Enable Clear (EN_CLR) Register + * DMA Channel Enable Clear (EN_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_EN_CLR_Struct + *! \brief DMA Channel Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ +typedef struct _ADI_DMA_EN_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Disable DMA Channels */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_EN_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ */ + +/*@}*/ + +/** @defgroup ALT_SET DMA Channel Primary Alternate Set (ALT_SET) Register + * DMA Channel Primary Alternate Set (ALT_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ALT_SET_Struct + *! \brief DMA Channel Primary Alternate Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ +typedef struct _ADI_DMA_ALT_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Control Structure Status / Select Alternate Structure */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ALT_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ */ + +/*@}*/ + +/** @defgroup ALT_CLR DMA Channel Primary Alternate Clear (ALT_CLR) Register + * DMA Channel Primary Alternate Clear (ALT_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ALT_CLR_Struct + *! \brief DMA Channel Primary Alternate Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ +typedef struct _ADI_DMA_ALT_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Select Primary Data Structure */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ALT_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ */ + +/*@}*/ + +/** @defgroup PRI_SET DMA Channel Priority Set (PRI_SET) Register + * DMA Channel Priority Set (PRI_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PRI_SET_Struct + *! \brief DMA Channel Priority Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ +typedef struct _ADI_DMA_PRI_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Configure Channel for High Priority */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_PRI_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ */ + +/*@}*/ + +/** @defgroup PRI_CLR DMA Channel Priority Clear (PRI_CLR) Register + * DMA Channel Priority Clear (PRI_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PRI_CLR_Struct + *! \brief DMA Channel Priority Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ +typedef struct _ADI_DMA_PRI_CLR_t { + union { + struct { + unsigned int CHPRICLR : 25; /**< Configure Channel for Default Priority Level */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_PRI_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ */ + +/*@}*/ + +/** @defgroup ERRCHNL_CLR DMA per Channel Error Clear (ERRCHNL_CLR) Register + * DMA per Channel Error Clear (ERRCHNL_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ERRCHNL_CLR_Struct + *! \brief DMA per Channel Error Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ +typedef struct _ADI_DMA_ERRCHNL_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Per Channel Bus Error Status/Clear */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ERRCHNL_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ */ + +/*@}*/ + +/** @defgroup ERR_CLR DMA Bus Error Clear (ERR_CLR) Register + * DMA Bus Error Clear (ERR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ERR_CLR_Struct + *! \brief DMA Bus Error Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ +typedef struct _ADI_DMA_ERR_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Bus Error Status */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ERR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ */ + +/*@}*/ + +/** @defgroup INVALIDDESC_CLR DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register + * DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_INVALIDDESC_CLR_Struct + *! \brief DMA per Channel Invalid Descriptor Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ +typedef struct _ADI_DMA_INVALIDDESC_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Per Channel Invalid Descriptor Status/Clear */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_INVALIDDESC_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ */ + +/*@}*/ + +/** @defgroup BS_SET DMA Channel Bytes Swap Enable Set (BS_SET) Register + * DMA Channel Bytes Swap Enable Set (BS_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_BS_SET_Struct + *! \brief DMA Channel Bytes Swap Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ +typedef struct _ADI_DMA_BS_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Byte Swap Status */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_BS_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ */ + +/*@}*/ + +/** @defgroup BS_CLR DMA Channel Bytes Swap Enable Clear (BS_CLR) Register + * DMA Channel Bytes Swap Enable Clear (BS_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_BS_CLR_Struct + *! \brief DMA Channel Bytes Swap Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ +typedef struct _ADI_DMA_BS_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Disable Byte Swap */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_BS_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ */ + +/*@}*/ + +/** @defgroup SRCADDR_SET DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register + * DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SRCADDR_SET_Struct + *! \brief DMA Channel Source Address Decrement Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ +typedef struct _ADI_DMA_SRCADDR_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Source Address Decrement Status */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SRCADDR_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ */ + +/*@}*/ + +/** @defgroup SRCADDR_CLR DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register + * DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SRCADDR_CLR_Struct + *! \brief DMA Channel Source Address Decrement Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ +typedef struct _ADI_DMA_SRCADDR_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Disable Source Address Decrement */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SRCADDR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ */ + +/*@}*/ + +/** @defgroup DSTADDR_SET DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register + * DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_DSTADDR_SET_Struct + *! \brief DMA Channel Destination Address Decrement Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ +typedef struct _ADI_DMA_DSTADDR_SET_t { + union { + struct { + unsigned int CHAN : 25; /**< Destination Address Decrement Status */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_DSTADDR_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ */ + +/*@}*/ + +/** @defgroup DSTADDR_CLR DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register + * DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_DSTADDR_CLR_Struct + *! \brief DMA Channel Destination Address Decrement Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ +typedef struct _ADI_DMA_DSTADDR_CLR_t { + union { + struct { + unsigned int CHAN : 25; /**< Disable Destination Address Decrement */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_DMA_DSTADDR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ */ + +/*@}*/ + +/** @defgroup REVID DMA Controller Revision ID (REVID) Register + * DMA Controller Revision ID (REVID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_REVID_Struct + *! \brief DMA Controller Revision ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ +typedef struct _ADI_DMA_REVID_t { + union { + struct { + unsigned int VALUE : 8; /**< DMA Controller Revision ID */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_DMA_REVID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ +typedef struct _ADI_FLCC_STAT_t { + union { + struct { + unsigned int CMDBUSY : 1; /**< Command Busy */ + unsigned int WRCLOSE : 1; /**< WRITE Registers are Closed */ + unsigned int CMDCOMP : 1; /**< Command Complete */ + unsigned int WRALCOMP : 1; /**< Write Almost Complete */ + unsigned int CMDFAIL : 2; /**< Provides Information on Command Failures */ + unsigned int SLEEPING : 1; /**< Flash Array is in Low Power (Sleep) Mode */ + unsigned int ECCERRCMD : 2; /**< ECC Errors Detected During User Issued SIGN Command */ + unsigned int ECCRDERR : 2; /**< ECC IRQ Cause */ + unsigned int OVERLAP : 1; /**< Overlapping Command */ + unsigned int reserved12 : 1; + unsigned int SIGNERR : 1; /**< Signature Check Failure During Initialization */ + unsigned int INIT : 1; /**< Flash Controller Initialization in Progress */ + unsigned int ECCINFOSIGN : 2; /**< ECC Status of Flash Initialization */ + unsigned int ECCERRCNT : 3; /**< ECC Correction Counter */ + unsigned int reserved20 : 5; + unsigned int ECCICODE : 2; /**< ICode AHB Bus Error ECC Status */ + unsigned int ECCDCODE : 2; /**< DCode AHB Bus Error ECC Status */ + unsigned int CACHESRAMPERR : 1; /**< SRAM Parity Errors in Cache Controller */ + unsigned int reserved30 : 2; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ */ + +/*@}*/ + +/** @defgroup IEN Interrupt Enable (IEN) Register + * Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_IEN_ECC_ERROR + *! \brief Control 2-bit ECC Error Events (ECC_ERROR) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_IEN_NONE_ERR = 0, /**< Do not generate a response to ECC events */ + FLCC_IEN_BUS_ERR_ERR = 1, /**< Generate Bus Errors in response to ECC events */ + FLCC_IEN_IRQ_ERR = 2 /**< Generate IRQs in response to ECC events */ +} ADI_FLCC_IEN_ECC_ERROR; + + +/* ========================================================================== + *! \struct ADI_FLCC_IEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ +typedef struct _ADI_FLCC_IEN_t { + union { + struct { + unsigned int CMDCMPLT : 1; /**< Command Complete Interrupt Enable */ + unsigned int WRALCMPLT : 1; /**< Write Almost Complete Interrupt Enable */ + unsigned int CMDFAIL : 1; /**< Command Fail Interrupt Enable */ + unsigned int reserved3 : 3; + unsigned int ECC_ERROR : 2; /**< Control 2-bit ECC Error Events */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ */ + +/*@}*/ + +/** @defgroup CMD Command (CMD) Register + * Command (CMD) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_CMD_VALUE + *! \brief Commands (VALUE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_CMD_IDLE = 0, /**< IDLE */ + FLCC_CMD_ABORT = 1, /**< ABORT */ + FLCC_CMD_SLEEP = 2, /**< Requests flash to enter Sleep mode */ + FLCC_CMD_SIGN = 3, /**< SIGN */ + FLCC_CMD_WRITE = 4, /**< WRITE */ + FLCC_CMD_BLANK_CHECK = 5, /**< Checks all of User Space; fails if any bits in user space are cleared */ + FLCC_CMD_ERASEPAGE = 6, /**< ERASEPAGE */ + FLCC_CMD_MASSERASE = 7 /**< MASSERASE */ +} ADI_FLCC_CMD_VALUE; + + +/* ========================================================================== + *! \struct ADI_FLCC_CMD_Struct + *! \brief Command Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ +typedef struct _ADI_FLCC_CMD_t { + union { + struct { + unsigned int VALUE : 4; /**< Commands */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CMD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ */ + +/*@}*/ + +/** @defgroup KH_ADDR Write Address (KH_ADDR) Register + * Write Address (KH_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_ADDR_Struct + *! \brief Write Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ +typedef struct _ADI_FLCC_KH_ADDR_t { + union { + struct { + unsigned int reserved0 : 3; + unsigned int VALUE : 16; /**< Key Hole Address */ + unsigned int reserved19 : 13; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ */ + +/*@}*/ + +/** @defgroup KH_DATA0 Write Lower Data (KH_DATA0) Register + * Write Lower Data (KH_DATA0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_DATA0_Struct + *! \brief Write Lower Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ +typedef struct _ADI_FLCC_KH_DATA0_t { + union { + struct { + unsigned int VALUE : 32; /**< Lower 32 Bits of Key Hole Data */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_DATA0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ */ + +/*@}*/ + +/** @defgroup KH_DATA1 Write Upper Data (KH_DATA1) Register + * Write Upper Data (KH_DATA1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_DATA1_Struct + *! \brief Write Upper Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ +typedef struct _ADI_FLCC_KH_DATA1_t { + union { + struct { + unsigned int VALUE : 32; /**< Upper Half of 64-bit Dualword Data to Be Written */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_DATA1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ */ + +/*@}*/ + +/** @defgroup PAGE_ADDR0 Lower Page Address (PAGE_ADDR0) Register + * Lower Page Address (PAGE_ADDR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_PAGE_ADDR0_Struct + *! \brief Lower Page Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ +typedef struct _ADI_FLCC_PAGE_ADDR0_t { + union { + struct { + unsigned int reserved0 : 10; + unsigned int VALUE : 9; /**< Lower Address Bits of the Page Address */ + unsigned int reserved19 : 13; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_PAGE_ADDR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ */ + +/*@}*/ + +/** @defgroup PAGE_ADDR1 Upper Page Address (PAGE_ADDR1) Register + * Upper Page Address (PAGE_ADDR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_PAGE_ADDR1_Struct + *! \brief Upper Page Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ +typedef struct _ADI_FLCC_PAGE_ADDR1_t { + union { + struct { + unsigned int reserved0 : 10; + unsigned int VALUE : 9; /**< Upper Address Bits of the Page Address */ + unsigned int reserved19 : 13; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_PAGE_ADDR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ */ + +/*@}*/ + +/** @defgroup KEY Key (KEY) Register + * Key (KEY) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_KEY_VALUE + *! \brief Key Register (VALUE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_KEY_USERKEY = 1735161189 /**< USERKEY */ +} ADI_FLCC_KEY_VALUE; + + +/* ========================================================================== + *! \struct ADI_FLCC_KEY_Struct + *! \brief Key Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ +typedef struct _ADI_FLCC_KEY_t { + union { + struct { + unsigned int VALUE : 32; /**< Key Register */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ */ + +/*@}*/ + +/** @defgroup WR_ABORT_ADDR Write Abort Address (WR_ABORT_ADDR) Register + * Write Abort Address (WR_ABORT_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_WR_ABORT_ADDR_Struct + *! \brief Write Abort Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ +typedef struct _ADI_FLCC_WR_ABORT_ADDR_t { + union { + struct { + unsigned int VALUE : 32; /**< Address Targeted by an Ongoing Write Command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_WR_ABORT_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ */ + +/*@}*/ + +/** @defgroup WRPROT Write Protection (WRPROT) Register + * Write Protection (WRPROT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_WRPROT_Struct + *! \brief Write Protection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ +typedef struct _ADI_FLCC_WRPROT_t { + union { + struct { + unsigned int WORD : 32; /**< Write Protect */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_WRPROT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ */ + +/*@}*/ + +/** @defgroup SIGNATURE Signature (SIGNATURE) Register + * Signature (SIGNATURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_SIGNATURE_Struct + *! \brief Signature Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ +typedef struct _ADI_FLCC_SIGNATURE_t { + union { + struct { + unsigned int VALUE : 32; /**< Signature */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_SIGNATURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ */ + +/*@}*/ + +/** @defgroup UCFG User Configuration (UCFG) Register + * User Configuration (UCFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_UCFG_Struct + *! \brief User Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ +typedef struct _ADI_FLCC_UCFG_t { + union { + struct { + unsigned int KHDMAEN : 1; /**< Key Hole DMA Enable */ + unsigned int AUTOINCEN : 1; /**< Auto Address Increment for Key Hole Access */ + unsigned int reserved2 : 30; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_UCFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ */ + +/*@}*/ + +/** @defgroup TIME_PARAM0 Time Parameter 0 (TIME_PARAM0) Register + * Time Parameter 0 (TIME_PARAM0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_TIME_PARAM0_Struct + *! \brief Time Parameter 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ +typedef struct _ADI_FLCC_TIME_PARAM0_t { + union { + struct { + unsigned int DIVREFCLK : 1; /**< Divide Reference Clock (by 2) */ + unsigned int reserved1 : 3; + unsigned int TNVS : 4; /**< PROG/ERASE to NVSTR Setup Time */ + unsigned int TPGS : 4; /**< NVSTR to Program Setup Time */ + unsigned int TPROG : 4; /**< Program Time */ + unsigned int TNVH : 4; /**< NVSTR Hold Time */ + unsigned int TRCV : 4; /**< Recovery Time */ + unsigned int TERASE : 4; /**< Erase Time */ + unsigned int TNVH1 : 4; /**< NVSTR Hold Time During Mass Erase */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_TIME_PARAM0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ */ + +/*@}*/ + +/** @defgroup TIME_PARAM1 Time Parameter 1 (TIME_PARAM1) Register + * Time Parameter 1 (TIME_PARAM1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_TIME_PARAM1_Struct + *! \brief Time Parameter 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ +typedef struct _ADI_FLCC_TIME_PARAM1_t { + union { + struct { + unsigned int TWK : 4; /**< Wakeup Time */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_TIME_PARAM1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ */ + +/*@}*/ + +/** @defgroup ABORT_EN_LO IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register + * IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ABORT_EN_LO_Struct + *! \brief IRQ Abort Enable (Lower Bits) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ +typedef struct _ADI_FLCC_ABORT_EN_LO_t { + union { + struct { + unsigned int VALUE : 32; /**< VALUE[31:0] Sys IRQ Abort Enable */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ABORT_EN_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ */ + +/*@}*/ + +/** @defgroup ABORT_EN_HI IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register + * IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ABORT_EN_HI_Struct + *! \brief IRQ Abort Enable (Upper Bits) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ +typedef struct _ADI_FLCC_ABORT_EN_HI_t { + union { + struct { + unsigned int VALUE : 32; /**< VALUE[63:32] Sys IRQ Abort Enable */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ABORT_EN_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ */ + +/*@}*/ + +/** @defgroup ECC_CFG ECC Configuration (ECC_CFG) Register + * ECC Configuration (ECC_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ECC_CFG_Struct + *! \brief ECC Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ +typedef struct _ADI_FLCC_ECC_CFG_t { + union { + struct { + unsigned int EN : 1; /**< ECC Enable */ + unsigned int INFOEN : 1; /**< Info Space ECC Enable Bit */ + unsigned int reserved2 : 6; + unsigned int PTR : 24; /**< ECC Start Page Pointer */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ECC_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ */ + +/*@}*/ + +/** @defgroup ECC_ADDR ECC Status (Address) (ECC_ADDR) Register + * ECC Status (Address) (ECC_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ECC_ADDR_Struct + *! \brief ECC Status (Address) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ +typedef struct _ADI_FLCC_ECC_ADDR_t { + union { + struct { + unsigned int VALUE : 19; /**< ECC Error Address */ + unsigned int reserved19 : 13; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ECC_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ */ + +/*@}*/ + +/** @defgroup POR_SEC Flash Security (POR_SEC) Register + * Flash Security (POR_SEC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_POR_SEC_Struct + *! \brief Flash Security Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ +typedef struct _ADI_FLCC_POR_SEC_t { + union { + struct { + unsigned int SECURE : 1; /**< Prevent Read/Write Access to User Space (Sticky When Set) */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_POR_SEC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ */ + +/*@}*/ + +/** @defgroup VOL_CFG Volatile Flash Configuration (VOL_CFG) Register + * Volatile Flash Configuration (VOL_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_VOL_CFG_Struct + *! \brief Volatile Flash Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ +typedef struct _ADI_FLCC_VOL_CFG_t { + union { + struct { + unsigned int INFO_REMAP : 1; /**< Alias the Info Space to the Base Address of User Space */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_VOL_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ */ + +/*@}*/ + +/** @defgroup STAT Cache Status (STAT) Register + * Cache Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_STAT_Struct + *! \brief Cache Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ +typedef struct _ADI_FLCC_CACHE_STAT_t { + union { + struct { + unsigned int ICEN : 1; /**< I-Cache Enabled */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ */ + +/*@}*/ + +/** @defgroup SETUP Cache Setup (SETUP) Register + * Cache Setup (SETUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_SETUP_Struct + *! \brief Cache Setup Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ +typedef struct _ADI_FLCC_CACHE_SETUP_t { + union { + struct { + unsigned int ICEN : 1; /**< I-Cache Enable */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_SETUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ */ + +/*@}*/ + +/** @defgroup KEY Cache Key (KEY) Register + * Cache Key (KEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_KEY_Struct + *! \brief Cache Key Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ +typedef struct _ADI_FLCC_CACHE_KEY_t { + union { + struct { + unsigned int VALUE : 32; /**< Cache Key Register */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ */ + +/*@}*/ + +/** @defgroup CFG Port Configuration (CFG) Register + * Port Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_CFG_Struct + *! \brief Port Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ +typedef struct _ADI_GPIO_CFG_t { + union { + struct { + unsigned int PIN00 : 2; /**< Pin 0 Configuration Bits */ + unsigned int PIN01 : 2; /**< Pin 1 Configuration Bits */ + unsigned int PIN02 : 2; /**< Pin 2 Configuration Bits */ + unsigned int PIN03 : 2; /**< Pin 3 Configuration Bits */ + unsigned int PIN04 : 2; /**< Pin 4 Configuration Bits */ + unsigned int PIN05 : 2; /**< Pin 5 Configuration Bits */ + unsigned int PIN06 : 2; /**< Pin 6 Configuration Bits */ + unsigned int PIN07 : 2; /**< Pin 7 Configuration Bits */ + unsigned int PIN08 : 2; /**< Pin 8 Configuration Bits */ + unsigned int PIN09 : 2; /**< Pin 9 Configuration Bits */ + unsigned int PIN10 : 2; /**< Pin 10 Configuration Bits */ + unsigned int PIN11 : 2; /**< Pin 11 Configuration Bits */ + unsigned int PIN12 : 2; /**< Pin 12 Configuration Bits */ + unsigned int PIN13 : 2; /**< Pin 13 Configuration Bits */ + unsigned int PIN14 : 2; /**< Pin 14 Configuration Bits */ + unsigned int PIN15 : 2; /**< Pin 15 Configuration Bits */ + }; + uint32_t VALUE32; + }; +} ADI_GPIO_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ */ + +/*@}*/ + +/** @defgroup OEN Port Output Enable (OEN) Register + * Port Output Enable (OEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_OEN_Struct + *! \brief Port Output Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ +typedef struct _ADI_GPIO_OEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Pin Output Drive Enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_OEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ */ + +/*@}*/ + +/** @defgroup PE Port Output Pull-up/Pull-down Enable (PE) Register + * Port Output Pull-up/Pull-down Enable (PE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_PE_Struct + *! \brief Port Output Pull-up/Pull-down Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ +typedef struct _ADI_GPIO_PE_t { + union { + struct { + unsigned int VALUE : 16; /**< Pin Pull Enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_PE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ */ + +/*@}*/ + +/** @defgroup IEN Port Input Path Enable (IEN) Register + * Port Input Path Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IEN_Struct + *! \brief Port Input Path Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ +typedef struct _ADI_GPIO_IEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Input Path Enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ */ + +/*@}*/ + +/** @defgroup IN Port Registered Data Input (IN) Register + * Port Registered Data Input (IN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IN_Struct + *! \brief Port Registered Data Input Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ +typedef struct _ADI_GPIO_IN_t { + union { + struct { + unsigned int VALUE : 16; /**< Registered Data Input */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ */ + +/*@}*/ + +/** @defgroup OUT Port Data Output (OUT) Register + * Port Data Output (OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_OUT_Struct + *! \brief Port Data Output Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ +typedef struct _ADI_GPIO_OUT_t { + union { + struct { + unsigned int VALUE : 16; /**< Data Out */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ */ + +/*@}*/ + +/** @defgroup SET Port Data Out Set (SET) Register + * Port Data Out Set (SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_SET_Struct + *! \brief Port Data Out Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ +typedef struct _ADI_GPIO_SET_t { + union { + struct { + unsigned int VALUE : 16; /**< Set the Output High for the Pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ */ + +/*@}*/ + +/** @defgroup CLR Port Data Out Clear (CLR) Register + * Port Data Out Clear (CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_CLR_Struct + *! \brief Port Data Out Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ +typedef struct _ADI_GPIO_CLR_t { + union { + struct { + unsigned int VALUE : 16; /**< Set the Output Low for the Port Pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ */ + +/*@}*/ + +/** @defgroup TGL Port Pin Toggle (TGL) Register + * Port Pin Toggle (TGL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_TGL_Struct + *! \brief Port Pin Toggle Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ +typedef struct _ADI_GPIO_TGL_t { + union { + struct { + unsigned int VALUE : 16; /**< Toggle the Output of the Port Pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_TGL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ */ + +/*@}*/ + +/** @defgroup POL Port Interrupt Polarity (POL) Register + * Port Interrupt Polarity (POL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_POL_Struct + *! \brief Port Interrupt Polarity Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ +typedef struct _ADI_GPIO_POL_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt polarity */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_POL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ */ + +/*@}*/ + +/** @defgroup IENA Port Interrupt A Enable (IENA) Register + * Port Interrupt A Enable (IENA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IENA_Struct + *! \brief Port Interrupt A Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ +typedef struct _ADI_GPIO_IENA_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt A enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IENA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ */ + +/*@}*/ + +/** @defgroup IENB Port Interrupt B Enable (IENB) Register + * Port Interrupt B Enable (IENB) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IENB_Struct + *! \brief Port Interrupt B Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ +typedef struct _ADI_GPIO_IENB_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt B enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IENB_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ */ + +/*@}*/ + +/** @defgroup INT Port Interrupt Status (INT) Register + * Port Interrupt Status (INT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_INT_Struct + *! \brief Port Interrupt Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ +typedef struct _ADI_GPIO_INT_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt Status */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_INT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ */ + +/*@}*/ + +/** @defgroup DS Port Drive Strength Select (DS) Register + * Port Drive Strength Select (DS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_DS_Struct + *! \brief Port Drive Strength Select Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ +typedef struct _ADI_GPIO_DS_t { + union { + struct { + unsigned int VALUE : 16; /**< Drive Strength Select */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_DS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ */ + +/*@}*/ + +/** @defgroup CTL_A Half SPORT 'A' Control (CTL_A) Register + * Half SPORT 'A' Control (CTL_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_SPEN + *! \brief Serial Port Enable (SPEN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_EN = 1 /**< Enable */ +} ADI_SPORT_CTL_A_SPEN; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_FSMUXSEL + *! \brief Frame Sync Multiplexer Select (FSMUXSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_MUX_DIS = 0, /**< Disable frame sync multiplexing */ + SPORT_CTL_A_CTL_FS_MUX_EN = 1 /**< Enable frame sync multiplexing */ +} ADI_SPORT_CTL_A_FSMUXSEL; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_CKMUXSEL + *! \brief Clock Multiplexer Select (CKMUXSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_CLK_MUX_DIS = 0, /**< Disable serial clock multiplexing */ + SPORT_CTL_A_CTL_CLK_MUX_EN = 1 /**< Enable serial clock multiplexing */ +} ADI_SPORT_CTL_A_CKMUXSEL; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LSBF + *! \brief Least-Significant Bit First (LSBF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_MSB_FIRST = 0, /**< MSB first sent/received */ + SPORT_CTL_A_CTL_LSB_FIRST = 1 /**< LSB first sent/received */ +} ADI_SPORT_CTL_A_LSBF; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_ICLK + *! \brief Internal Clock (ICLK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EXTERNAL_CLK = 0, /**< External clock */ + SPORT_CTL_A_CTL_INTERNAL_CLK = 1 /**< Internal clock */ +} ADI_SPORT_CTL_A_ICLK; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_OPMODE + *! \brief Operation Mode (OPMODE) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_SERIAL = 0, /**< DSP standard */ + SPORT_CTL_A_CTL_TIMER_EN_MODE = 1 /**< Timer_enable mode */ +} ADI_SPORT_CTL_A_OPMODE; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_CKRE + *! \brief Clock Rising Edge (CKRE) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_CLK_FALL_EDGE = 0, /**< Clock falling edge */ + SPORT_CTL_A_CTL_CLK_RISE_EDGE = 1 /**< Clock rising edge */ +} ADI_SPORT_CTL_A_CKRE; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_FSR + *! \brief Frame Sync Required (FSR) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_NOT_REQ = 0, /**< No frame sync required */ + SPORT_CTL_A_CTL_FS_REQ = 1 /**< Frame sync required */ +} ADI_SPORT_CTL_A_FSR; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_IFS + *! \brief Internal Frame Sync (IFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EXTERNAL_FS = 0, /**< External frame sync */ + SPORT_CTL_A_CTL_INTERNAL_FS = 1 /**< Internal frame sync */ +} ADI_SPORT_CTL_A_IFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_DIFS + *! \brief Data-Independent Frame Sync (DIFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_DATA_DEP_FS = 0, /**< Data-dependent frame sync */ + SPORT_CTL_A_CTL_DATA_INDP_FS = 1 /**< Data-independent frame sync */ +} ADI_SPORT_CTL_A_DIFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LFS + *! \brief Active-Low Frame Sync (LFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_LO = 0, /**< Active high frame sync */ + SPORT_CTL_A_CTL_FS_HI = 1 /**< Active low frame sync */ +} ADI_SPORT_CTL_A_LFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LAFS + *! \brief Late Frame Sync (LAFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EARLY_FS = 0, /**< Early frame sync */ + SPORT_CTL_A_CTL_LATE_FS = 1 /**< Late frame sync */ +} ADI_SPORT_CTL_A_LAFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_PACK + *! \brief Packing Enable (PACK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_PACK_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_PACK_8BIT = 1, /**< 8-bit packing enable */ + SPORT_CTL_A_CTL_PACK_16BIT = 2, /**< 16-bit packing enable */ + SPORT_CTL_A_CTL_PACK_RSV = 3 /**< Reserved */ +} ADI_SPORT_CTL_A_PACK; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_GCLKEN + *! \brief Gated Clock Enable (GCLKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_GCLK_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_GCLK_EN = 1 /**< Enable */ +} ADI_SPORT_CTL_A_GCLKEN; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_SPTRAN + *! \brief Serial Port Transfer Direction (SPTRAN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_RX = 0, /**< Receive */ + SPORT_CTL_A_CTL_TX = 1 /**< Transmit */ +} ADI_SPORT_CTL_A_SPTRAN; + + +/* ========================================================================== + *! \struct ADI_SPORT_CTL_A_Struct + *! \brief Half SPORT 'A' Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ +typedef struct _ADI_SPORT_CTL_A_t { + union { + struct { + unsigned int SPEN : 1; /**< Serial Port Enable */ + unsigned int FSMUXSEL : 1; /**< Frame Sync Multiplexer Select */ + unsigned int CKMUXSEL : 1; /**< Clock Multiplexer Select */ + unsigned int LSBF : 1; /**< Least-Significant Bit First */ + unsigned int SLEN : 5; /**< Serial Word Length */ + unsigned int reserved9 : 1; + unsigned int ICLK : 1; /**< Internal Clock */ + unsigned int OPMODE : 1; /**< Operation Mode */ + unsigned int CKRE : 1; /**< Clock Rising Edge */ + unsigned int FSR : 1; /**< Frame Sync Required */ + unsigned int IFS : 1; /**< Internal Frame Sync */ + unsigned int DIFS : 1; /**< Data-Independent Frame Sync */ + unsigned int LFS : 1; /**< Active-Low Frame Sync */ + unsigned int LAFS : 1; /**< Late Frame Sync */ + unsigned int PACK : 2; /**< Packing Enable */ + unsigned int FSERRMODE : 1; /**< Frame Sync Error Operation */ + unsigned int GCLKEN : 1; /**< Gated Clock Enable */ + unsigned int reserved22 : 3; + unsigned int SPTRAN : 1; /**< Serial Port Transfer Direction */ + unsigned int DMAEN : 1; /**< DMA Enable */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CTL_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ */ + +/*@}*/ + +/** @defgroup DIV_A Half SPORT 'A' Divisor (DIV_A) Register + * Half SPORT 'A' Divisor (DIV_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_DIV_A_Struct + *! \brief Half SPORT 'A' Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ +typedef struct _ADI_SPORT_DIV_A_t { + union { + struct { + unsigned int CLKDIV : 16; /**< Clock Divisor */ + unsigned int FSDIV : 8; /**< Frame Sync Divisor */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_DIV_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ */ + +/*@}*/ + +/** @defgroup IEN_A Half SPORT A's Interrupt Enable (IEN_A) Register + * Half SPORT A's Interrupt Enable (IEN_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_IEN_A_TF + *! \brief Transfer Finish Interrupt Enable (TF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_IEN_A_CTL_TXFIN_DIS = 0, /**< Transfer finish Interrupt is disabled */ + SPORT_IEN_A_CTL_TXFIN_EN = 1 /**< Transfer Finish Interrupt is Enabled */ +} ADI_SPORT_IEN_A_TF; + + +/* ========================================================================== + *! \struct ADI_SPORT_IEN_A_Struct + *! \brief Half SPORT A's Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ +typedef struct _ADI_SPORT_IEN_A_t { + union { + struct { + unsigned int TF : 1; /**< Transfer Finish Interrupt Enable */ + unsigned int DERRMSK : 1; /**< Data Error (Interrupt) Mask */ + unsigned int FSERRMSK : 1; /**< Frame Sync Error (Interrupt) Mask */ + unsigned int DATA : 1; /**< Data Request Interrupt to the Core */ + unsigned int SYSDATERR : 1; /**< Data Error for System Writes or Reads */ + unsigned int reserved5 : 27; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_IEN_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ */ + +/*@}*/ + +/** @defgroup STAT_A Half SPORT A's Status (STAT_A) Register + * Half SPORT A's Status (STAT_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_STAT_A_DXS + *! \brief Data Transfer Buffer Status (DXS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_STAT_A_CTL_EMPTY = 0, /**< Empty */ + SPORT_STAT_A_CTL_RSV = 1, /**< Reserved */ + SPORT_STAT_A_CTL_PART_FULL = 2, /**< Partially full */ + SPORT_STAT_A_CTL_FULL = 3 /**< Full */ +} ADI_SPORT_STAT_A_DXS; + + +/* ========================================================================== + *! \struct ADI_SPORT_STAT_A_Struct + *! \brief Half SPORT A's Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ +typedef struct _ADI_SPORT_STAT_A_t { + union { + struct { + unsigned int TFI : 1; /**< Transmit Finish Interrupt Status */ + unsigned int DERR : 1; /**< Data Error Status */ + unsigned int FSERR : 1; /**< Frame Sync Error Status */ + unsigned int DATA : 1; /**< Data Buffer Status */ + unsigned int SYSDATERR : 1; /**< System Data Error Status */ + unsigned int reserved5 : 3; + unsigned int DXS : 2; /**< Data Transfer Buffer Status */ + unsigned int reserved10 : 22; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_STAT_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ */ + +/*@}*/ + +/** @defgroup NUMTRAN_A Half SPORT A Number of Transfers (NUMTRAN_A) Register + * Half SPORT A Number of Transfers (NUMTRAN_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_NUMTRAN_A_Struct + *! \brief Half SPORT A Number of Transfers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ +typedef struct _ADI_SPORT_NUMTRAN_A_t { + union { + struct { + unsigned int VALUE : 12; /**< Number of Transfers (Half SPORT A) */ + unsigned int reserved12 : 20; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_NUMTRAN_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ */ + +/*@}*/ + +/** @defgroup CNVT_A Half SPORT 'A' CNV Width (CNVT_A) Register + * Half SPORT 'A' CNV Width (CNVT_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_CNVT_A_Struct + *! \brief Half SPORT 'A' CNV Width Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ +typedef struct _ADI_SPORT_CNVT_A_t { + union { + struct { + unsigned int WID : 4; /**< SPT_CNVT Signal Width: Half SPORT a */ + unsigned int reserved4 : 4; + unsigned int POL : 1; /**< Polarity of the SPT_CNVT Signal */ + unsigned int reserved9 : 7; + unsigned int CNVT2FS : 8; /**< SPT_CNVT to FS Duration: Half SPORT a */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CNVT_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ */ + +/*@}*/ + +/** @defgroup TX_A Half SPORT 'A' Tx Buffer (TX_A) Register + * Half SPORT 'A' Tx Buffer (TX_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_TX_A_Struct + *! \brief Half SPORT 'A' Tx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ +typedef struct _ADI_SPORT_TX_A_t { + union { + struct { + unsigned int VALUE : 32; /**< Transmit Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_TX_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ */ + +/*@}*/ + +/** @defgroup RX_A Half SPORT 'A' Rx Buffer (RX_A) Register + * Half SPORT 'A' Rx Buffer (RX_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_RX_A_Struct + *! \brief Half SPORT 'A' Rx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ +typedef struct _ADI_SPORT_RX_A_t { + union { + struct { + unsigned int VALUE : 32; /**< Receive Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_RX_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ */ + +/*@}*/ + +/** @defgroup CTL_B Half SPORT 'B' Control (CTL_B) Register + * Half SPORT 'B' Control (CTL_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_B_PACK + *! \brief Packing Enable (PACK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_B_CTL_PACK_DIS = 0, /**< Disable */ + SPORT_CTL_B_CTL_PACK_8BIT = 1, /**< 8-bit packing enable */ + SPORT_CTL_B_CTL_PACK_16BIT = 2, /**< 16-bit packing enable */ + SPORT_CTL_B_CTL_PACK_RSV = 3 /**< Reserved */ +} ADI_SPORT_CTL_B_PACK; + + +/* ========================================================================== + *! \struct ADI_SPORT_CTL_B_Struct + *! \brief Half SPORT 'B' Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ +typedef struct _ADI_SPORT_CTL_B_t { + union { + struct { + unsigned int SPEN : 1; /**< Serial Port Enable */ + unsigned int reserved1 : 2; + unsigned int LSBF : 1; /**< Least-Significant Bit First */ + unsigned int SLEN : 5; /**< Serial Word Length */ + unsigned int reserved9 : 1; + unsigned int ICLK : 1; /**< Internal Clock */ + unsigned int OPMODE : 1; /**< Operation Mode */ + unsigned int CKRE : 1; /**< Clock Rising Edge */ + unsigned int FSR : 1; /**< Frame Sync Required */ + unsigned int IFS : 1; /**< Internal Frame Sync */ + unsigned int DIFS : 1; /**< Data-Independent Frame Sync */ + unsigned int LFS : 1; /**< Active-Low Frame Sync */ + unsigned int LAFS : 1; /**< Late Frame Sync */ + unsigned int PACK : 2; /**< Packing Enable */ + unsigned int FSERRMODE : 1; /**< Frame Sync Error Operation */ + unsigned int GCLKEN : 1; /**< Gated Clock Enable */ + unsigned int reserved22 : 3; + unsigned int SPTRAN : 1; /**< Serial Port Transfer Direction */ + unsigned int DMAEN : 1; /**< DMA Enable */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CTL_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ */ + +/*@}*/ + +/** @defgroup DIV_B Half SPORT 'B' Divisor (DIV_B) Register + * Half SPORT 'B' Divisor (DIV_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_DIV_B_Struct + *! \brief Half SPORT 'B' Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ +typedef struct _ADI_SPORT_DIV_B_t { + union { + struct { + unsigned int CLKDIV : 16; /**< Clock Divisor */ + unsigned int FSDIV : 8; /**< Frame Sync Divisor */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_DIV_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ */ + +/*@}*/ + +/** @defgroup IEN_B Half SPORT B's Interrupt Enable (IEN_B) Register + * Half SPORT B's Interrupt Enable (IEN_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_IEN_B_TF + *! \brief Transmit Finish Interrupt Enable (TF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_IEN_B_CTL_TXFIN_DIS = 0, /**< Transfer Finish Interrupt is disabled */ + SPORT_IEN_B_CTL_TXFIN_EN = 1 /**< Transfer Finish Interrupt is Enabled */ +} ADI_SPORT_IEN_B_TF; + + +/* ========================================================================== + *! \struct ADI_SPORT_IEN_B_Struct + *! \brief Half SPORT B's Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ +typedef struct _ADI_SPORT_IEN_B_t { + union { + struct { + unsigned int TF : 1; /**< Transmit Finish Interrupt Enable */ + unsigned int DERRMSK : 1; /**< Data Error (Interrupt) Mask */ + unsigned int FSERRMSK : 1; /**< Frame Sync Error (Interrupt) Mask */ + unsigned int DATA : 1; /**< Data Request Interrupt to the Core */ + unsigned int SYSDATERR : 1; /**< Data Error for System Writes or Reads */ + unsigned int reserved5 : 27; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_IEN_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ */ + +/*@}*/ + +/** @defgroup STAT_B Half SPORT B's Status (STAT_B) Register + * Half SPORT B's Status (STAT_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_STAT_B_DXS + *! \brief Data Transfer Buffer Status (DXS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_STAT_B_CTL_EMPTY = 0, /**< Empty */ + SPORT_STAT_B_CTL_RSV = 1, /**< Reserved */ + SPORT_STAT_B_CTL_PART_FULL = 2, /**< Partially full */ + SPORT_STAT_B_CTL_FULL = 3 /**< Full */ +} ADI_SPORT_STAT_B_DXS; + + +/* ========================================================================== + *! \struct ADI_SPORT_STAT_B_Struct + *! \brief Half SPORT B's Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ +typedef struct _ADI_SPORT_STAT_B_t { + union { + struct { + unsigned int TFI : 1; /**< Transmit Finish Interrupt Status */ + unsigned int DERR : 1; /**< Data Error Status */ + unsigned int FSERR : 1; /**< Frame Sync Error Status */ + unsigned int DATA : 1; /**< Data Buffer Status */ + unsigned int SYSDATERR : 1; /**< System Data Error Status */ + unsigned int reserved5 : 3; + unsigned int DXS : 2; /**< Data Transfer Buffer Status */ + unsigned int reserved10 : 22; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_STAT_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ */ + +/*@}*/ + +/** @defgroup NUMTRAN_B Half SPORT B Number of Transfers (NUMTRAN_B) Register + * Half SPORT B Number of Transfers (NUMTRAN_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_NUMTRAN_B_Struct + *! \brief Half SPORT B Number of Transfers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ +typedef struct _ADI_SPORT_NUMTRAN_B_t { + union { + struct { + unsigned int VALUE : 12; /**< Number of Transfers (Half SPORT A) */ + unsigned int reserved12 : 20; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_NUMTRAN_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ */ + +/*@}*/ + +/** @defgroup CNVT_B Half SPORT 'B' CNV Width (CNVT_B) Register + * Half SPORT 'B' CNV Width (CNVT_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_CNVT_B_Struct + *! \brief Half SPORT 'B' CNV Width Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ +typedef struct _ADI_SPORT_CNVT_B_t { + union { + struct { + unsigned int WID : 4; /**< SPT_CNVT Signal Width: Half SPORT B */ + unsigned int reserved4 : 4; + unsigned int POL : 1; /**< Polarity of the SPT_CNVT Signal */ + unsigned int reserved9 : 7; + unsigned int CNVT2FS : 8; /**< SPT_CNVT to FS Duration: Half SPORT B */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CNVT_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ */ + +/*@}*/ + +/** @defgroup TX_B Half SPORT 'B' Tx Buffer (TX_B) Register + * Half SPORT 'B' Tx Buffer (TX_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_TX_B_Struct + *! \brief Half SPORT 'B' Tx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ +typedef struct _ADI_SPORT_TX_B_t { + union { + struct { + unsigned int VALUE : 32; /**< Transmit Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_TX_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ */ + +/*@}*/ + +/** @defgroup RX_B Half SPORT 'B' Rx Buffer (RX_B) Register + * Half SPORT 'B' Rx Buffer (RX_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_RX_B_Struct + *! \brief Half SPORT 'B' Rx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ +typedef struct _ADI_SPORT_RX_B_t { + union { + struct { + unsigned int VALUE : 32; /**< Receive Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_RX_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ */ + +/*@}*/ + +/** @defgroup CTL CRC Control (CTL) Register + * CRC Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CRC_CTL_EN + *! \brief CRC Peripheral Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_CRC_DIS = 0, /**< CRC peripheral is disabled */ + CRC_CTL_CRC_EN = 1 /**< CRC peripheral is enabled */ +} ADI_CRC_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_LSBFIRST + *! \brief LSB First Calculation Order (LSBFIRST) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_MSB_FIRST = 0, /**< MSB First CRC calculation is done */ + CRC_CTL_LSB_FIRST = 1 /**< LSB First CRC calculation is done */ +} ADI_CRC_CTL_LSBFIRST; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_BITMIRR + *! \brief Bit Mirroring (BITMIRR) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_BITMIRR_DIS = 0, /**< Bit Mirroring is disabled */ + CRC_CTL_BITMIRR_EN = 1 /**< Bit Mirroring is enabled */ +} ADI_CRC_CTL_BITMIRR; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_BYTMIRR + *! \brief Byte Mirroring (BYTMIRR) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_BYTEMIR_DIS = 0, /**< Byte Mirroring is disabled */ + CRC_CTL_BYTEMIR_EN = 1 /**< Byte Mirroring is enabled */ +} ADI_CRC_CTL_BYTMIRR; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_W16SWP + *! \brief Word16 Swap (W16SWP) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_W16SP_DIS = 0, /**< Word16 Swap disabled */ + CRC_CTL_W16SP_EN = 1 /**< Word16 Swap enabled */ +} ADI_CRC_CTL_W16SWP; + + +/* ========================================================================== + *! \struct ADI_CRC_CTL_Struct + *! \brief CRC Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ +typedef struct _ADI_CRC_CTL_t { + union { + struct { + unsigned int EN : 1; /**< CRC Peripheral Enable */ + unsigned int LSBFIRST : 1; /**< LSB First Calculation Order */ + unsigned int BITMIRR : 1; /**< Bit Mirroring */ + unsigned int BYTMIRR : 1; /**< Byte Mirroring */ + unsigned int W16SWP : 1; /**< Word16 Swap */ + unsigned int reserved5 : 23; + unsigned int RevID : 4; /**< Revision ID */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ */ + +/*@}*/ + +/** @defgroup IPDATA Input Data Word (IPDATA) Register + * Input Data Word (IPDATA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPDATA_Struct + *! \brief Input Data Word Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ +typedef struct _ADI_CRC_IPDATA_t { + union { + struct { + unsigned int VALUE : 32; /**< Data Input */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_IPDATA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ */ + +/*@}*/ + +/** @defgroup RESULT CRC Result (RESULT) Register + * CRC Result (RESULT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_RESULT_Struct + *! \brief CRC Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ +typedef struct _ADI_CRC_RESULT_t { + union { + struct { + unsigned int VALUE : 32; /**< CRC Residue */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_RESULT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ */ + +/*@}*/ + +/** @defgroup POLY Programmable CRC Polynomial (POLY) Register + * Programmable CRC Polynomial (POLY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_POLY_Struct + *! \brief Programmable CRC Polynomial Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ +typedef struct _ADI_CRC_POLY_t { + union { + struct { + unsigned int VALUE : 32; /**< CRC Reduction Polynomial */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_POLY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ */ + +/*@}*/ + +/** @defgroup IPBITS Input Data Bits (IPBITS) Register + * Input Data Bits (IPBITS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPBITS_Struct + *! \brief Input Data Bits Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ +typedef struct _ADI_CRC_IPBITS_t { + union { + struct { + unsigned int DATA_BITS : 8; /**< Input Data Bits */ + }; + uint8_t VALUE8; + }; +} ADI_CRC_IPBITS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ */ + +/*@}*/ + +/** @defgroup IPBYTE Input Data Byte (IPBYTE) Register + * Input Data Byte (IPBYTE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPBYTE_Struct + *! \brief Input Data Byte Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ +typedef struct _ADI_CRC_IPBYTE_t { + union { + struct { + unsigned int DATA_BYTE : 8; /**< Input Data Byte */ + }; + uint8_t VALUE8; + }; +} ADI_CRC_IPBYTE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ */ + +/*@}*/ + +/** @defgroup CTL RNG Control Register (CTL) Register + * RNG Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RNG_CTL_EN + *! \brief RNG Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + RNG_CTL_DISABLE = 0, /**< Disable the RNG */ + RNG_CTL_ENABLE = 1 /**< Enable the RNG */ +} ADI_RNG_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_RNG_CTL_SINGLE + *! \brief Generate a Single Number (SINGLE) Enumerations + * ========================================================================= */ +typedef enum +{ + RNG_CTL_WORD = 0, /**< Buffer Word */ + RNG_CTL_SINGLE = 1 /**< Single Byte */ +} ADI_RNG_CTL_SINGLE; + + +/* ========================================================================== + *! \struct ADI_RNG_CTL_Struct + *! \brief RNG Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ +typedef struct _ADI_RNG_CTL_t { + union { + struct { + unsigned int EN : 1; /**< RNG Enable */ + unsigned int reserved1 : 2; + unsigned int SINGLE : 1; /**< Generate a Single Number */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_RNG_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ */ + +/*@}*/ + +/** @defgroup LEN RNG Sample Length Register (LEN) Register + * RNG Sample Length Register (LEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_LEN_Struct + *! \brief RNG Sample Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ +typedef struct _ADI_RNG_LEN_t { + union { + struct { + unsigned int RELOAD : 12; /**< Reload Value for the Sample Counter */ + unsigned int PRESCALE : 4; /**< Prescaler for the Sample Counter */ + }; + uint16_t VALUE16; + }; +} ADI_RNG_LEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ */ + +/*@}*/ + +/** @defgroup STAT RNG Status Register (STAT) Register + * RNG Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_STAT_Struct + *! \brief RNG Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ +typedef struct _ADI_RNG_STAT_t { + union { + struct { + unsigned int RNRDY : 1; /**< Random Number Ready */ + unsigned int STUCK : 1; /**< Sampled Data Stuck High or Low */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_RNG_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ */ + +/*@}*/ + +/** @defgroup DATA RNG Data Register (DATA) Register + * RNG Data Register (DATA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_DATA_Struct + *! \brief RNG Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ +typedef struct _ADI_RNG_DATA_t { + union { + struct { + unsigned int VALUE : 8; /**< Value of the CRC Accumulator */ + unsigned int BUFF : 24; /**< Buffer for RNG Data */ + }; + uint32_t VALUE32; + }; +} ADI_RNG_DATA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ */ + +/*@}*/ + +/** @defgroup OSCCNT Oscillator Count (OSCCNT) Register + * Oscillator Count (OSCCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_OSCCNT_Struct + *! \brief Oscillator Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ +typedef struct _ADI_RNG_OSCCNT_t { + union { + struct { + unsigned int VALUE : 28; /**< Oscillator Count */ + unsigned int reserved28 : 4; + }; + uint32_t VALUE32; + }; +} ADI_RNG_OSCCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ */ + +/*@}*/ + +/** @defgroup OSCDIFF Oscillator Difference (OSCDIFF) Register + * Oscillator Difference (OSCDIFF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_OSCDIFF_Struct + *! \brief Oscillator Difference Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ +typedef struct _ADI_RNG_OSCDIFF_t { + union { + struct { + signed int DELTA : 8; /**< Oscillator Count Difference */ + }; + int8_t VALUE8; + }; +} ADI_RNG_OSCDIFF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ */ + +/*@}*/ + +/** @defgroup CFG Configuration Register (CFG) Register + * Configuration Register (CFG) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_BLKEN + *! \brief Enable Bit for Crypto Block (BLKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_ENABLE = 0, /**< Enable Crypto Block */ + CRYPT_CFG_DISABLE = 1 /**< Disable Crypto Block */ +} ADI_CRYPT_CFG_BLKEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_INDMAEN + *! \brief Enable DMA Channel Request for Input Buffer (INDMAEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_DMA_DISABLE_INBUF = 0, /**< Disable DMA Requesting for Input Buffer */ + CRYPT_CFG_DMA_ENABLE_INBUF = 1 /**< Enable DMA Requesting for Input Buffer */ +} ADI_CRYPT_CFG_INDMAEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_OUTDMAEN + *! \brief Enable DMA Channel Request for Output Buffer (OUTDMAEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_DMA_DISABLE_OUTBUF = 0, /**< Disable DMA Requesting for Output Buffer */ + CRYPT_CFG_DMA_ENABLE_OUTBUF = 1 /**< Enable DMA Requesting for Output Buffer */ +} ADI_CRYPT_CFG_OUTDMAEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_AESKEYLEN + *! \brief Select Key Length for AES Cipher (AESKEYLEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_AESKEYLEN128 = 0, /**< Uses 128-bit long key */ + CRYPT_CFG_AESKEYLEN256 = 2 /**< Uses 256-bit long key */ +} ADI_CRYPT_CFG_AESKEYLEN; + + +/* ========================================================================== + *! \struct ADI_CRYPT_CFG_Struct + *! \brief Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ +typedef struct _ADI_CRYPT_CFG_t { + union { + struct { + unsigned int BLKEN : 1; /**< Enable Bit for Crypto Block */ + unsigned int ENCR : 1; /**< Encrypt or Decrypt */ + unsigned int INDMAEN : 1; /**< Enable DMA Channel Request for Input Buffer */ + unsigned int OUTDMAEN : 1; /**< Enable DMA Channel Request for Output Buffer */ + unsigned int INFLUSH : 1; /**< Input Buffer Flush */ + unsigned int OUTFLUSH : 1; /**< Output Buffer Flush */ + unsigned int AES_BYTESWAP : 1; /**< Byte Swap 32 Bit AES Input Data */ + unsigned int reserved7 : 1; + unsigned int AESKEYLEN : 2; /**< Select Key Length for AES Cipher */ + unsigned int reserved10 : 6; + unsigned int ECBEN : 1; /**< Enable ECB Mode Operation */ + unsigned int CTREN : 1; /**< Enable CTR Mode Operation */ + unsigned int CBCEN : 1; /**< Enable CBC Mode Operation */ + unsigned int CCMEN : 1; /**< Enable CCM/CCM* Mode Operation */ + unsigned int CMACEN : 1; /**< Enable CMAC Mode Operation */ + unsigned int reserved21 : 4; + unsigned int SHA256EN : 1; /**< Enable SHA-256 Operation */ + unsigned int SHAINIT : 1; /**< Restarts SHA Computation */ + unsigned int reserved27 : 1; + unsigned int RevID : 4; /**< Rev ID for Crypto */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ */ + +/*@}*/ + +/** @defgroup DATALEN Payload Data Length (DATALEN) Register + * Payload Data Length (DATALEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_DATALEN_Struct + *! \brief Payload Data Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ +typedef struct _ADI_CRYPT_DATALEN_t { + union { + struct { + unsigned int VALUE : 20; /**< Length of Payload Data */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_DATALEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ */ + +/*@}*/ + +/** @defgroup PREFIXLEN Authentication Data Length (PREFIXLEN) Register + * Authentication Data Length (PREFIXLEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_PREFIXLEN_Struct + *! \brief Authentication Data Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ +typedef struct _ADI_CRYPT_PREFIXLEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Length of Associated Data */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_PREFIXLEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ */ + +/*@}*/ + +/** @defgroup INTEN Interrupt Enable Register (INTEN) Register + * Interrupt Enable Register (INTEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_INTEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ +typedef struct _ADI_CRYPT_INTEN_t { + union { + struct { + unsigned int INRDYEN : 1; /**< Enable Input Ready Interrupt */ + unsigned int OUTRDYEN : 1; /**< Enables the Output Ready Interrupt */ + unsigned int INOVREN : 1; /**< Enable Input Overflow Interrupt */ + unsigned int reserved3 : 2; + unsigned int SHADONEN : 1; /**< Enable SHA_Done Interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_INTEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ */ + +/*@}*/ + +/** @defgroup STAT Status Register (STAT) Register + * Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ +typedef struct _ADI_CRYPT_STAT_t { + union { + struct { + unsigned int INRDY : 1; /**< Input Buffer Status */ + unsigned int OUTRDY : 1; /**< Output Data Ready */ + unsigned int INOVR : 1; /**< Overflow in the Input Buffer */ + unsigned int reserved3 : 2; + unsigned int SHADONE : 1; /**< SHA Computation Complete */ + unsigned int SHABUSY : 1; /**< SHA Busy. in Computation */ + unsigned int INWORDS : 3; /**< Number of Words in the Input Buffer */ + unsigned int OUTWORDS : 3; /**< Number of Words in the Output Buffer */ + unsigned int reserved13 : 19; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ */ + +/*@}*/ + +/** @defgroup INBUF Input Buffer (INBUF) Register + * Input Buffer (INBUF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_INBUF_Struct + *! \brief Input Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ +typedef struct _ADI_CRYPT_INBUF_t { + union { + struct { + unsigned int VALUE : 32; /**< Input Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_INBUF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ */ + +/*@}*/ + +/** @defgroup OUTBUF Output Buffer (OUTBUF) Register + * Output Buffer (OUTBUF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_OUTBUF_Struct + *! \brief Output Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ +typedef struct _ADI_CRYPT_OUTBUF_t { + union { + struct { + unsigned int VALUE : 32; /**< Output Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_OUTBUF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ */ + +/*@}*/ + +/** @defgroup NONCE0 Nonce Bits [31:0] (NONCE0) Register + * Nonce Bits [31:0] (NONCE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE0_Struct + *! \brief Nonce Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ +typedef struct _ADI_CRYPT_NONCE0_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 0: Nonce Bits [31:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ */ + +/*@}*/ + +/** @defgroup NONCE1 Nonce Bits [63:32] (NONCE1) Register + * Nonce Bits [63:32] (NONCE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE1_Struct + *! \brief Nonce Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ +typedef struct _ADI_CRYPT_NONCE1_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 1: Nonce Bits [63:32] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ */ + +/*@}*/ + +/** @defgroup NONCE2 Nonce Bits [95:64] (NONCE2) Register + * Nonce Bits [95:64] (NONCE2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE2_Struct + *! \brief Nonce Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ +typedef struct _ADI_CRYPT_NONCE2_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 2: Nonce Bits [95:64] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ */ + +/*@}*/ + +/** @defgroup NONCE3 Nonce Bits [127:96] (NONCE3) Register + * Nonce Bits [127:96] (NONCE3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE3_Struct + *! \brief Nonce Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ +typedef struct _ADI_CRYPT_NONCE3_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 3: Nonce Bits [127:96] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ */ + +/*@}*/ + +/** @defgroup AESKEY0 AES Key Bits [31:0] (AESKEY0) Register + * AES Key Bits [31:0] (AESKEY0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY0_Struct + *! \brief AES Key Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ +typedef struct _ADI_CRYPT_AESKEY0_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [3:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ */ + +/*@}*/ + +/** @defgroup AESKEY1 AES Key Bits [63:32] (AESKEY1) Register + * AES Key Bits [63:32] (AESKEY1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY1_Struct + *! \brief AES Key Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ +typedef struct _ADI_CRYPT_AESKEY1_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [7:4] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ */ + +/*@}*/ + +/** @defgroup AESKEY2 AES Key Bits [95:64] (AESKEY2) Register + * AES Key Bits [95:64] (AESKEY2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY2_Struct + *! \brief AES Key Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ +typedef struct _ADI_CRYPT_AESKEY2_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [11:8] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ */ + +/*@}*/ + +/** @defgroup AESKEY3 AES Key Bits [127:96] (AESKEY3) Register + * AES Key Bits [127:96] (AESKEY3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY3_Struct + *! \brief AES Key Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ +typedef struct _ADI_CRYPT_AESKEY3_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [15:12] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ */ + +/*@}*/ + +/** @defgroup AESKEY4 AES Key Bits [159:128] (AESKEY4) Register + * AES Key Bits [159:128] (AESKEY4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY4_Struct + *! \brief AES Key Bits [159:128] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ +typedef struct _ADI_CRYPT_AESKEY4_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [19:16] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ */ + +/*@}*/ + +/** @defgroup AESKEY5 AES Key Bits [191:160] (AESKEY5) Register + * AES Key Bits [191:160] (AESKEY5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY5_Struct + *! \brief AES Key Bits [191:160] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ +typedef struct _ADI_CRYPT_AESKEY5_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [23:20] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ */ + +/*@}*/ + +/** @defgroup AESKEY6 AES Key Bits [223:192] (AESKEY6) Register + * AES Key Bits [223:192] (AESKEY6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY6_Struct + *! \brief AES Key Bits [223:192] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ +typedef struct _ADI_CRYPT_AESKEY6_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [27:24] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ */ + +/*@}*/ + +/** @defgroup AESKEY7 AES Key Bits [255:224] (AESKEY7) Register + * AES Key Bits [255:224] (AESKEY7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY7_Struct + *! \brief AES Key Bits [255:224] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ +typedef struct _ADI_CRYPT_AESKEY7_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [31:28] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ */ + +/*@}*/ + +/** @defgroup CNTRINIT Counter Initialization Vector (CNTRINIT) Register + * Counter Initialization Vector (CNTRINIT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_CNTRINIT_Struct + *! \brief Counter Initialization Vector Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ +typedef struct _ADI_CRYPT_CNTRINIT_t { + union { + struct { + unsigned int VALUE : 20; /**< Counter Initialization Value */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CNTRINIT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ */ + +/*@}*/ + +/** @defgroup SHAH0 SHA Bits [31:0] (SHAH0) Register + * SHA Bits [31:0] (SHAH0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH0_Struct + *! \brief SHA Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ +typedef struct _ADI_CRYPT_SHAH0_t { + union { + struct { + unsigned int SHAHASH0 : 32; /**< Word 0: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ */ + +/*@}*/ + +/** @defgroup SHAH1 SHA Bits [63:32] (SHAH1) Register + * SHA Bits [63:32] (SHAH1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH1_Struct + *! \brief SHA Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ +typedef struct _ADI_CRYPT_SHAH1_t { + union { + struct { + unsigned int SHAHASH1 : 32; /**< Word 1: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ */ + +/*@}*/ + +/** @defgroup SHAH2 SHA Bits [95:64] (SHAH2) Register + * SHA Bits [95:64] (SHAH2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH2_Struct + *! \brief SHA Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ +typedef struct _ADI_CRYPT_SHAH2_t { + union { + struct { + unsigned int SHAHASH2 : 32; /**< Word 2: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ */ + +/*@}*/ + +/** @defgroup SHAH3 SHA Bits [127:96] (SHAH3) Register + * SHA Bits [127:96] (SHAH3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH3_Struct + *! \brief SHA Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ +typedef struct _ADI_CRYPT_SHAH3_t { + union { + struct { + unsigned int SHAHASH3 : 32; /**< Word 3: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ */ + +/*@}*/ + +/** @defgroup SHAH4 SHA Bits [159:128] (SHAH4) Register + * SHA Bits [159:128] (SHAH4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH4_Struct + *! \brief SHA Bits [159:128] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ +typedef struct _ADI_CRYPT_SHAH4_t { + union { + struct { + unsigned int SHAHASH4 : 32; /**< Word 4: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ */ + +/*@}*/ + +/** @defgroup SHAH5 SHA Bits [191:160] (SHAH5) Register + * SHA Bits [191:160] (SHAH5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH5_Struct + *! \brief SHA Bits [191:160] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ +typedef struct _ADI_CRYPT_SHAH5_t { + union { + struct { + unsigned int SHAHASH5 : 32; /**< Word 5: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ */ + +/*@}*/ + +/** @defgroup SHAH6 SHA Bits [223:192] (SHAH6) Register + * SHA Bits [223:192] (SHAH6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH6_Struct + *! \brief SHA Bits [223:192] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ +typedef struct _ADI_CRYPT_SHAH6_t { + union { + struct { + unsigned int SHAHASH6 : 32; /**< Word 6: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ */ + +/*@}*/ + +/** @defgroup SHAH7 SHA Bits [255:224] (SHAH7) Register + * SHA Bits [255:224] (SHAH7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH7_Struct + *! \brief SHA Bits [255:224] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ +typedef struct _ADI_CRYPT_SHAH7_t { + union { + struct { + unsigned int SHAHASH7 : 32; /**< Word 7: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ */ + +/*@}*/ + +/** @defgroup SHA_LAST_WORD SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register + * SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHA_LAST_WORD_Struct + *! \brief SHA Last Word and Valid Bits Information Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ +typedef struct _ADI_CRYPT_SHA_LAST_WORD_t { + union { + struct { + unsigned int O_Last_Word : 1; /**< Last SHA Input Word */ + unsigned int O_Bits_Valid : 5; /**< Bits Valid in SHA Last Word Input */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHA_LAST_WORD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ */ + +/*@}*/ + +/** @defgroup CCM_NUM_VALID_BYTES NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register + * NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_CCM_NUM_VALID_BYTES_Struct + *! \brief NUM_VALID_BYTES Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ +typedef struct _ADI_CRYPT_CCM_NUM_VALID_BYTES_t { + union { + struct { + unsigned int NUM_VALID_BYTES : 4; /**< Number of Valid Bytes in CCM Last Data */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CCM_NUM_VALID_BYTES_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ */ + +/*@}*/ + +/** @defgroup IEN Power Supply Monitor Interrupt Enable (IEN) Register + * Power Supply Monitor Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_IEN_RANGEBAT + *! \brief Battery Monitor Range (RANGEBAT) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_IEN_REGION1 = 0, /**< Configure to generate interrupt if VBAT > 2.75 V */ + PMG_IEN_REGION2 = 1, /**< Configure to generate interrupt if VBAT between 2.75 V - 1.6 V */ + PMG_IEN_REGION3 = 2, /**< Configure to generate interrupt if VBAT between 2.3 V - 1.6 V */ + PMG_IEN_NA = 3 /**< N/A */ +} ADI_PMG_IEN_RANGEBAT; + + +/* ========================================================================== + *! \struct ADI_PMG_IEN_Struct + *! \brief Power Supply Monitor Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ +typedef struct _ADI_PMG_IEN_t { + union { + struct { + unsigned int VBAT : 1; /**< Enable Interrupt for VBAT */ + unsigned int VREGUNDR : 1; /**< Enable Interrupt When VREG Undervoltage: Below 1V */ + unsigned int VREGOVR : 1; /**< Enable Interrupt When VREG Overvoltage: Above 1.32V */ + unsigned int reserved3 : 5; + unsigned int RANGEBAT : 2; /**< Battery Monitor Range */ + unsigned int IENBAT : 1; /**< Interrupt Enable for VBAT Range */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_PMG_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ */ + +/*@}*/ + +/** @defgroup PSM_STAT Power Supply Monitor Status (PSM_STAT) Register + * Power Supply Monitor Status (PSM_STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_PSM_STAT_RORANGE1 + *! \brief VBAT Range1 (> 2.75v) (RORANGE1) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PSM_STAT_BATSTAT1 = 0, /**< VBAT not in the range specified */ + PMG_PSM_STAT_BATSTAT0 = 1 /**< VBAT in the range specified */ +} ADI_PMG_PSM_STAT_RORANGE1; + + +/* ========================================================================== + *! \struct ADI_PMG_PSM_STAT_Struct + *! \brief Power Supply Monitor Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ +typedef struct _ADI_PMG_PSM_STAT_t { + union { + struct { + unsigned int VBATUNDR : 1; /**< Status Bit Indicating an Alarm That Battery is Below 1.8V */ + unsigned int VREGUNDR : 1; /**< Status Bit for Alarm Indicating VREG is Below 1V */ + unsigned int VREGOVR : 1; /**< Status Bit for Alarm Indicating Overvoltage for VREG */ + unsigned int reserved3 : 4; + unsigned int WICENACK : 1; /**< WIC Enable Acknowledge from Cortex */ + unsigned int RANGE1 : 1; /**< VBAT Range1 (> 2.75v) */ + unsigned int RANGE2 : 1; /**< VBAT Range2 (2.75v - 2.3v) */ + unsigned int RANGE3 : 1; /**< VBAT Range3 (2.3v - 1.6v) */ + unsigned int reserved11 : 2; + unsigned int RORANGE1 : 1; /**< VBAT Range1 (> 2.75v) */ + unsigned int RORANGE2 : 1; /**< VBAT Range2 (2.75v - 2.3v) */ + unsigned int RORANGE3 : 1; /**< VBAT Range3 (2.3v - 1.6v) */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PSM_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWRMOD Power Mode Register (PWRMOD) Register + * Power Mode Register (PWRMOD) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_PWRMOD_MODE + *! \brief Power Mode Bits (MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PWRMOD_FLEXI = 0, /**< Flexi Mode */ + PMG_PWRMOD_HIBERNATE = 2, /**< Hibernate Mode */ + PMG_PWRMOD_SHUTDOWN = 3 /**< Shutdown Mode */ +} ADI_PMG_PWRMOD_MODE; + + +/* ========================================================================= + *! \enum ADI_PMG_PWRMOD_MONVBATN + *! \brief Monitor VBAT During Hibernate Mode. Monitors VBAT by Default (MONVBATN) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PWRMOD_VBAT_MONEN = 0, /**< VBAT monitor enabled in PMG block. */ + PMG_PWRMOD_VBAT_MONDIS = 1 /**< VBAT monitor disabled in PMG block. */ +} ADI_PMG_PWRMOD_MONVBATN; + + +/* ========================================================================== + *! \struct ADI_PMG_PWRMOD_Struct + *! \brief Power Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ +typedef struct _ADI_PMG_PWRMOD_t { + union { + struct { + unsigned int MODE : 2; /**< Power Mode Bits */ + unsigned int reserved2 : 1; + unsigned int MONVBATN : 1; /**< Monitor VBAT During Hibernate Mode. Monitors VBAT by Default */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PWRMOD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ */ + +/*@}*/ + +/** @defgroup PWRKEY Key Protection for PWRMOD and SRAMRET (PWRKEY) Register + * Key Protection for PWRMOD and SRAMRET (PWRKEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_PWRKEY_Struct + *! \brief Key Protection for PWRMOD and SRAMRET Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ +typedef struct _ADI_PMG_PWRKEY_t { + union { + struct { + unsigned int VALUE : 16; /**< Power Control Key Register */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PWRKEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ */ + +/*@}*/ + +/** @defgroup SHDN_STAT Shutdown Status Register (SHDN_STAT) Register + * Shutdown Status Register (SHDN_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_SHDN_STAT_Struct + *! \brief Shutdown Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ +typedef struct _ADI_PMG_SHDN_STAT_t { + union { + struct { + unsigned int EXTINT0 : 1; /**< Wakeup by Interrupt from External Interrupt 0 */ + unsigned int EXTINT1 : 1; /**< Wakeup by Interrupt from External Interrupt 1 */ + unsigned int EXTINT2 : 1; /**< Wakeup by Interrupt from External Interrupt 2 */ + unsigned int RTC : 1; /**< Wakeup by Interrupt from RTC */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_PMG_SHDN_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ */ + +/*@}*/ + +/** @defgroup SRAMRET Control for Retention SRAM in Hibernate Mode (SRAMRET) Register + * Control for Retention SRAM in Hibernate Mode (SRAMRET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_SRAMRET_Struct + *! \brief Control for Retention SRAM in Hibernate Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ +typedef struct _ADI_PMG_SRAMRET_t { + union { + struct { + unsigned int BNK1EN : 1; /**< Enable Retention Bank 1 (8kB) */ + unsigned int BNK2EN : 1; /**< Enable Retention Bank 2 (16kB) */ + unsigned int reserved2 : 30; + }; + uint32_t VALUE32; + }; +} ADI_PMG_SRAMRET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ */ + +/*@}*/ + +/** @defgroup RST_STAT Reset Status (RST_STAT) Register + * Reset Status (RST_STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_RST_STAT_PORSRC + *! \brief Power-on-Reset Source (PORSRC) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_RST_STAT_FAILSAFE_HV = 0, /**< POR triggered because VBAT drops below Fail Safe */ + PMG_RST_STAT_RST_VBAT = 1, /**< POR trigger because VBAT supply (VBAT < 1.7 V) */ + PMG_RST_STAT_RST_VREG = 2, /**< POR triggered because VDD supply (VDD < 1.08 V) */ + PMG_RST_STAT_FAILSAFE_LV = 3 /**< POR triggered because VREG drops below Fail Safe */ +} ADI_PMG_RST_STAT_PORSRC; + + +/* ========================================================================== + *! \struct ADI_PMG_RST_STAT_Struct + *! \brief Reset Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ +typedef struct _ADI_PMG_RST_STAT_t { + union { + struct { + unsigned int POR : 1; /**< Power-on-Reset */ + unsigned int EXTRST : 1; /**< External Reset */ + unsigned int WDRST : 1; /**< Watchdog Time-out Reset */ + unsigned int SWRST : 1; /**< Software Reset */ + unsigned int PORSRC : 2; /**< Power-on-Reset Source */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_PMG_RST_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ */ + +/*@}*/ + +/** @defgroup CTL1 HP Buck Control (CTL1) Register + * HP Buck Control (CTL1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_CTL1_Struct + *! \brief HP Buck Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ +typedef struct _ADI_PMG_CTL1_t { + union { + struct { + unsigned int HPBUCKEN : 1; /**< Enable HP Buck */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_PMG_CTL1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ */ + +/*@}*/ + +/** @defgroup CFG0 External Interrupt Configuration (CFG0) Register + * External Interrupt Configuration (CFG0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_CFG0_Struct + *! \brief External Interrupt Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ +typedef struct _ADI_XINT_CFG0_t { + union { + struct { + unsigned int IRQ0MDE : 3; /**< External Interrupt 0 Mode Registers */ + unsigned int IRQ0EN : 1; /**< External Interrupt 0 Enable Bit */ + unsigned int IRQ1MDE : 3; /**< External Interrupt 1 Mode Registers */ + unsigned int IRQ1EN : 1; /**< External Interrupt 1 Enable Bit */ + unsigned int IRQ2MDE : 3; /**< External Interrupt 2 Mode Registers */ + unsigned int IRQ2EN : 1; /**< External Interrupt 2 Enable Bit */ + unsigned int IRQ3MDE : 3; /**< External Interrupt 3 Mode Registers */ + unsigned int IRQ3EN : 1; /**< External Interrupt 3 Enable Bit */ + unsigned int reserved16 : 4; + unsigned int UART_RX_EN : 1; /**< External Interrupt Enable Bit */ + unsigned int UART_RX_MDE : 3; /**< External Interrupt Using UART_RX Wakeup Mode Registers */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_XINT_CFG0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ */ + +/*@}*/ + +/** @defgroup EXT_STAT External Wakeup Interrupt Status (EXT_STAT) Register + * External Wakeup Interrupt Status (EXT_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_EXT_STAT_Struct + *! \brief External Wakeup Interrupt Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ +typedef struct _ADI_XINT_EXT_STAT_t { + union { + struct { + unsigned int STAT_EXTINT0 : 1; /**< Interrupt Status Bit for External Interrupt 0 */ + unsigned int STAT_EXTINT1 : 1; /**< Interrupt Status Bit for External Interrupt 1 */ + unsigned int STAT_EXTINT2 : 1; /**< Interrupt Status Bit for External Interrupt 2 */ + unsigned int STAT_EXTINT3 : 1; /**< Interrupt Status Bit for External Interrupt 3 */ + unsigned int reserved4 : 1; + unsigned int STAT_UART_RXWKUP : 1; /**< Interrupt Status Bit for UART RX Wakeup Interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_XINT_EXT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ */ + +/*@}*/ + +/** @defgroup CLR External Interrupt Clear (CLR) Register + * External Interrupt Clear (CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_CLR_Struct + *! \brief External Interrupt Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ +typedef struct _ADI_XINT_CLR_t { + union { + struct { + unsigned int IRQ0 : 1; /**< External Interrupt 0 */ + unsigned int IRQ1 : 1; /**< External Interrupt 1 */ + unsigned int IRQ2 : 1; /**< External Interrupt 2 */ + unsigned int IRQ3 : 1; /**< External Interrupt 3 */ + unsigned int reserved4 : 1; + unsigned int UART_RX_CLR : 1; /**< External Interrupt Clear for UART_RX Wakeup Interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_XINT_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ */ + +/*@}*/ + +/** @defgroup NMICLR Non-Maskable Interrupt Clear (NMICLR) Register + * Non-Maskable Interrupt Clear (NMICLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_NMICLR_Struct + *! \brief Non-Maskable Interrupt Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ +typedef struct _ADI_XINT_NMICLR_t { + union { + struct { + unsigned int CLR : 1; /**< NMI Clear */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_XINT_NMICLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ */ + +/*@}*/ + +/** @defgroup KEY Key Protection for CLKG_OSC_CTL (KEY) Register + * Key Protection for CLKG_OSC_CTL (KEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_OSC_KEY_Struct + *! \brief Key Protection for CLKG_OSC_CTL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ +typedef struct _ADI_CLKG_OSC_KEY_t { + union { + struct { + unsigned int VALUE : 16; /**< Oscillator K */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_OSC_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ */ + +/*@}*/ + +/** @defgroup CTL Oscillator Control (CTL) Register + * Oscillator Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT + *! \brief LFXTAL Not Stable (LFXTAL_MON_FAIL_STAT) Enumerations + * ========================================================================= */ +typedef enum +{ + CLKG_OSC_CTL_LFXTAL_RUNNING = 0, /**< LFXTAL is running fine */ + CLKG_OSC_CTL_LFXTAL_NOTRUNNING = 1 /**< LFXTAL is not running */ +} ADI_CLKG_OSC_CTL_LFXTAL_MON_FAIL_STAT; + + +/* ========================================================================== + *! \struct ADI_CLKG_OSC_CTL_Struct + *! \brief Oscillator Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ +typedef struct _ADI_CLKG_OSC_CTL_t { + union { + struct { + unsigned int LFCLKMUX : 1; /**< 32kHz Clock Select Mux */ + unsigned int HFOSCEN : 1; /**< High Frequency Internal Oscillator Enable */ + unsigned int LFXTALEN : 1; /**< Low Frequency Crystal Oscillator Enable */ + unsigned int HFXTALEN : 1; /**< High Frequency Crystal Oscillator Enable */ + unsigned int LFXTAL_BYPASS : 1; /**< Low Frequency Crystal Oscillator Bypass */ + unsigned int LFXTAL_MON_EN : 1; /**< LFXTAL Clock Monitor and Clock Fail Interrupt Enable */ + unsigned int reserved6 : 2; + unsigned int LFOSCOK : 1; /**< Status of LFOSC Oscillator */ + unsigned int HFOSCOK : 1; /**< Status of HFOSC */ + unsigned int LFXTALOK : 1; /**< Status of LFXTAL Oscillator */ + unsigned int HFXTALOK : 1; /**< Status of HFXTAL Oscillator */ + unsigned int reserved12 : 19; + unsigned int LFXTAL_MON_FAIL_STAT : 1; /**< LFXTAL Not Stable */ + }; + uint32_t VALUE32; + }; +} ADI_CLKG_OSC_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ */ + +/*@}*/ + +/** @defgroup SRAM_CTL Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register + * Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SRAM_CTL_Struct + *! \brief Control for SRAM Parity and Instruction SRAM Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ +typedef struct _ADI_PMG_TST_SRAM_CTL_t { + union { + struct { + unsigned int BNK0EN : 1; /**< Enable Initialization of SRAM Bank 0 */ + unsigned int BNK1EN : 1; /**< Enable Initialization of SRAM Bank 1 */ + unsigned int BNK2EN : 1; /**< Enable Initialization of SRAM Bank 2 */ + unsigned int BNK3EN : 1; /**< Enable Initialization of SRAM Bank 3 */ + unsigned int BNK4EN : 1; /**< Enable Initialization of SRAM Bank 4 */ + unsigned int BNK5EN : 1; /**< Enable Initialization of SRAM Bank 5 */ + unsigned int reserved6 : 7; + unsigned int STARTINIT : 1; /**< Write 1 to Trigger Initialization */ + unsigned int AUTOINIT : 1; /**< Automatic Initialization on Wakeup from Hibernate Mode */ + unsigned int ABTINIT : 1; /**< Abort Current Initialization. Self-cleared */ + unsigned int PENBNK0 : 1; /**< Enable Parity Check SRAM Bank 0 */ + unsigned int PENBNK1 : 1; /**< Enable Parity Check SRAM Bank 1 */ + unsigned int PENBNK2 : 1; /**< Enable Parity Check SRAM Bank 2 */ + unsigned int PENBNK3 : 1; /**< Enable Parity Check SRAM Bank 3 */ + unsigned int PENBNK4 : 1; /**< Enable Parity Check SRAM Bank 4 */ + unsigned int PENBNK5 : 1; /**< Enable Parity Check SRAM Bank 5 */ + unsigned int reserved22 : 9; + unsigned int INSTREN : 1; /**< Enables Instruction SRAM */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SRAM_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ */ + +/*@}*/ + +/** @defgroup SRAM_INITSTAT Initialization Status Register (SRAM_INITSTAT) Register + * Initialization Status Register (SRAM_INITSTAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SRAM_INITSTAT_Struct + *! \brief Initialization Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ +typedef struct _ADI_PMG_TST_SRAM_INITSTAT_t { + union { + struct { + unsigned int BNK0 : 1; /**< Initialization Done of SRAM Bank 0 */ + unsigned int BNK1 : 1; /**< Initialization Done of SRAM Bank 1 */ + unsigned int BNK2 : 1; /**< Initialization Done of SRAM Bank 2 */ + unsigned int BNK3 : 1; /**< Initialization Done of SRAM Bank 3 */ + unsigned int BNK4 : 1; /**< Initialization Done of SRAM Bank 4 */ + unsigned int BNK5 : 1; /**< Initialization Done of SRAM Bank 5 */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SRAM_INITSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ */ + +/*@}*/ + +/** @defgroup CLR_LATCH_GPIOS Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register + * Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_CLR_LATCH_GPIOS_Struct + *! \brief Clear GPIO After Shutdown Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ +typedef struct _ADI_PMG_TST_CLR_LATCH_GPIOS_t { + union { + struct { + unsigned int VALUE : 16; /**< Clear GPIOs Latches */ + }; + uint16_t VALUE16; + }; +} ADI_PMG_TST_CLR_LATCH_GPIOS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ */ + +/*@}*/ + +/** @defgroup SCRPAD_IMG Scratch Pad Image (SCRPAD_IMG) Register + * Scratch Pad Image (SCRPAD_IMG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SCRPAD_IMG_Struct + *! \brief Scratch Pad Image Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ +typedef struct _ADI_PMG_TST_SCRPAD_IMG_t { + union { + struct { + unsigned int DATA : 32; /**< Scratch Image */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SCRPAD_IMG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ */ + +/*@}*/ + +/** @defgroup SCRPAD_3V_RD Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register + * Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SCRPAD_3V_RD_Struct + *! \brief Scratch Pad Saved in Battery Domain Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ +typedef struct _ADI_PMG_TST_SCRPAD_3V_RD_t { + union { + struct { + unsigned int DATA : 32; /**< Reading the Scratch Pad Stored in Shutdown Mode */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SCRPAD_3V_RD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ */ + +/*@}*/ + +/** @defgroup CTL0 Miscellaneous Clock Settings (CTL0) Register + * Miscellaneous Clock Settings (CTL0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL0_Struct + *! \brief Miscellaneous Clock Settings Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ +typedef struct _ADI_CLKG_CLK_CTL0_t { + union { + struct { + unsigned int CLKMUX : 2; /**< Clock Mux Select */ + unsigned int reserved2 : 6; + unsigned int RCLKMUX : 2; /**< Flash Reference Clock and HP Buck Source Mux */ + unsigned int reserved10 : 1; + unsigned int SPLLIPSEL : 1; /**< SPLL Source Select Mux */ + unsigned int reserved12 : 2; + unsigned int LFXTALIE : 1; /**< Low Frequency Crystal Interrupt Enable */ + unsigned int HFXTALIE : 1; /**< High Frequency Crystal Interrupt Enable */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ */ + +/*@}*/ + +/** @defgroup CTL1 Clock Dividers (CTL1) Register + * Clock Dividers (CTL1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL1_Struct + *! \brief Clock Dividers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ +typedef struct _ADI_CLKG_CLK_CTL1_t { + union { + struct { + unsigned int HCLKDIVCNT : 6; /**< HCLK Divide Count */ + unsigned int reserved6 : 2; + unsigned int PCLKDIVCNT : 6; /**< PCLK Divide Count */ + unsigned int reserved14 : 2; + unsigned int ACLKDIVCNT : 8; /**< ACLK Divide Count */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ */ + +/*@}*/ + +/** @defgroup CTL3 System PLL (CTL3) Register + * System PLL (CTL3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL3_Struct + *! \brief System PLL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ +typedef struct _ADI_CLKG_CLK_CTL3_t { + union { + struct { + unsigned int SPLLNSEL : 5; /**< System PLL N Multiplier */ + unsigned int reserved5 : 3; + unsigned int SPLLDIV2 : 1; /**< System PLL Division by 2 */ + unsigned int SPLLEN : 1; /**< System PLL Enable */ + unsigned int SPLLIE : 1; /**< System PLL Interrupt Enable */ + unsigned int SPLLMSEL : 4; /**< System PLL M Divider */ + unsigned int reserved15 : 1; + unsigned int SPLLMUL2 : 1; /**< System PLL Multiply by 2 */ + unsigned int reserved17 : 15; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ */ + +/*@}*/ + +/** @defgroup CTL5 User Clock Gating Control (CTL5) Register + * User Clock Gating Control (CTL5) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CLKG_CLK_CTL5_PERCLKOFF + *! \brief Disables All Clocks Connected to All Peripherals (PERCLKOFF) Enumerations + * ========================================================================= */ +typedef enum +{ + CLKG_CLK_CTL5_PERIPH_CLK_ACT = 0, /**< Clocks to all peripherals are active */ + CLKG_CLK_CTL5_PERIPH_CLK_OFF = 1 /**< Clocks to all peripherals are gated off */ +} ADI_CLKG_CLK_CTL5_PERCLKOFF; + + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL5_Struct + *! \brief User Clock Gating Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ +typedef struct _ADI_CLKG_CLK_CTL5_t { + union { + struct { + unsigned int GPTCLK0OFF : 1; /**< Timer 0 User Control */ + unsigned int GPTCLK1OFF : 1; /**< Timer 1 User Control */ + unsigned int GPTCLK2OFF : 1; /**< Timer 2 User Control */ + unsigned int UCLKI2COFF : 1; /**< I2C Clock User Control */ + unsigned int GPIOCLKOFF : 1; /**< GPIO Clock Control */ + unsigned int PERCLKOFF : 1; /**< Disables All Clocks Connected to All Peripherals */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ */ + +/*@}*/ + +/** @defgroup STAT0 Clocking Status (STAT0) Register + * Clocking Status (STAT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_STAT0_Struct + *! \brief Clocking Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ +typedef struct _ADI_CLKG_CLK_STAT0_t { + union { + struct { + unsigned int SPLL : 1; /**< System PLL Status */ + unsigned int SPLLLK : 1; /**< System PLL Lock */ + unsigned int SPLLUNLK : 1; /**< System PLL Unlock */ + unsigned int reserved3 : 5; + unsigned int LFXTAL : 1; /**< LF Crystal Status */ + unsigned int LFXTALOK : 1; /**< LF Crystal Stable */ + unsigned int LFXTALNOK : 1; /**< LF Crystal Not Stable */ + unsigned int reserved11 : 1; + unsigned int HFXTAL : 1; /**< HF Crystal Status */ + unsigned int HFXTALOK : 1; /**< HF Crystal Stable */ + unsigned int HFXTALNOK : 1; /**< HF Crystal Not Stable */ + unsigned int reserved15 : 17; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_STAT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ */ + +/*@}*/ + +/** @defgroup ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register + * Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT0_Struct + *! \brief Arbitration Priority Configuration for FLASH and SRAM0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ +typedef struct _ADI_BUSM_ARBIT0_t { + union { + struct { + unsigned int FLSH_DCODE : 2; /**< Flash priority for DCODE */ + unsigned int FLSH_SBUS : 2; /**< Flash priority for SBUS */ + unsigned int FLSH_DMA0 : 2; /**< Flash priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int SRAM0_DCODE : 2; /**< SRAM0 priority for Dcode */ + unsigned int SRAM0_SBUS : 2; /**< SRAM0 priority for SBUS */ + unsigned int SRAM0_DMA0 : 2; /**< SRAM0 priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ */ + +/*@}*/ + +/** @defgroup ARBIT1 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register + * Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT1_Struct + *! \brief Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ +typedef struct _ADI_BUSM_ARBIT1_t { + union { + struct { + unsigned int SRAM1_DCODE : 2; /**< SRAM1 priority for Dcode */ + unsigned int SRAM1_SBUS : 2; /**< SRAM1 priority for SBUS */ + unsigned int SRAM1_DMA0 : 2; /**< SRAM1 priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int SIP_DCODE : 2; /**< SIP priority for DCODE */ + unsigned int SIP_SBUS : 2; /**< SIP priority for SBUS */ + unsigned int SIP_DMA0 : 2; /**< SIP priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ */ + +/*@}*/ + +/** @defgroup ARBIT2 Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register + * Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT2_Struct + *! \brief Arbitration Priority Configuration for APB32 and APB16 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ +typedef struct _ADI_BUSM_ARBIT2_t { + union { + struct { + unsigned int APB32_DCODE : 2; /**< APB32 priority for DCODE */ + unsigned int APB32_SBUS : 2; /**< APB32 priority for SBUS */ + unsigned int APB32_DMA0 : 2; /**< APB32 priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int APB16_DCODE : 2; /**< APB16 priority for DCODE */ + unsigned int APB16_SBUS : 2; /**< APB16 priority for SBUS */ + unsigned int APB16_DMA0 : 2; /**< APB16 priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ */ + +/*@}*/ + +/** @defgroup ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register + * Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT3_Struct + *! \brief Arbitration Priority Configuration for APB16 priority for core and for DMA1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ +typedef struct _ADI_BUSM_ARBIT3_t { + union { + struct { + unsigned int APB16_CORE : 1; /**< APB16 priority for CORE */ + unsigned int APB16_DMA1 : 1; /**< APB16 priority for DMA1 */ + unsigned int reserved2 : 14; + unsigned int APB16_4DMA_CORE : 1; /**< APB16 for dma priority for CORE */ + unsigned int APB16_4DMA_DMA1 : 1; /**< APB16 for dma priority for DMA1 */ + unsigned int reserved18 : 14; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ */ + +/*@}*/ + +/** @defgroup RST_ISR_STARTADDR Reset ISR Start Address (RST_ISR_STARTADDR) Register + * Reset ISR Start Address (RST_ISR_STARTADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_RST_ISR_STARTADDR_Struct + *! \brief Reset ISR Start Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ +typedef struct _ADI_PTI_RST_ISR_STARTADDR_t { + union { + struct { + unsigned int VALUE : 32; + }; + uint32_t VALUE32; + }; +} ADI_PTI_RST_ISR_STARTADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ */ + +/*@}*/ + +/** @defgroup RST_STACK_PTR Reset Stack Pointer (RST_STACK_PTR) Register + * Reset Stack Pointer (RST_STACK_PTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_RST_STACK_PTR_Struct + *! \brief Reset Stack Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ +typedef struct _ADI_PTI_RST_STACK_PTR_t { + union { + struct { + unsigned int VALUE : 32; + }; + uint32_t VALUE32; + }; +} ADI_PTI_RST_STACK_PTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ */ + +/*@}*/ + +/** @defgroup CTL Parallel Test Interface Control Register (CTL) Register + * Parallel Test Interface Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_CTL_Struct + *! \brief Parallel Test Interface Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ +typedef struct _ADI_PTI_CTL_t { + union { + struct { + unsigned int EN : 1; + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_PTI_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ */ + +/*@}*/ + +/** @defgroup INTNUM Interrupt Control Type (INTNUM) Register + * Interrupt Control Type (INTNUM) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTNUM_Struct + *! \brief Interrupt Control Type Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ +typedef struct _ADI_NVIC_INTNUM_t { + union { + struct { + unsigned int VALUE : 32; /**< Interrupt Control Type */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTNUM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ */ + +/*@}*/ + +/** @defgroup STKSTA Systick Control and Status (STKSTA) Register + * Systick Control and Status (STKSTA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKSTA_Struct + *! \brief Systick Control and Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ +typedef struct _ADI_NVIC_STKSTA_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Control and Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKSTA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ */ + +/*@}*/ + +/** @defgroup STKLD Systick Reload Value (STKLD) Register + * Systick Reload Value (STKLD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKLD_Struct + *! \brief Systick Reload Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ +typedef struct _ADI_NVIC_STKLD_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Reload Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKLD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ */ + +/*@}*/ + +/** @defgroup STKVAL Systick Current Value (STKVAL) Register + * Systick Current Value (STKVAL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKVAL_Struct + *! \brief Systick Current Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ +typedef struct _ADI_NVIC_STKVAL_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Current Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKVAL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ */ + +/*@}*/ + +/** @defgroup STKCAL Systick Calibration Value (STKCAL) Register + * Systick Calibration Value (STKCAL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKCAL_Struct + *! \brief Systick Calibration Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ +typedef struct _ADI_NVIC_STKCAL_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Calibration Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKCAL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ */ + +/*@}*/ + +/** @defgroup INTSETE0 IRQ0..31 Set_Enable (INTSETE0) Register + * IRQ0..31 Set_Enable (INTSETE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETE0_Struct + *! \brief IRQ0..31 Set_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ +typedef struct _ADI_NVIC_INTSETE0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Set_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ */ + +/*@}*/ + +/** @defgroup INTSETE1 IRQ32..63 Set_Enable (INTSETE1) Register + * IRQ32..63 Set_Enable (INTSETE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETE1_Struct + *! \brief IRQ32..63 Set_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ +typedef struct _ADI_NVIC_INTSETE1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Set_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ */ + +/*@}*/ + +/** @defgroup INTCLRE0 IRQ0..31 Clear_Enable (INTCLRE0) Register + * IRQ0..31 Clear_Enable (INTCLRE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRE0_Struct + *! \brief IRQ0..31 Clear_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ +typedef struct _ADI_NVIC_INTCLRE0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Clear_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ */ + +/*@}*/ + +/** @defgroup INTCLRE1 IRQ32..63 Clear_Enable (INTCLRE1) Register + * IRQ32..63 Clear_Enable (INTCLRE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRE1_Struct + *! \brief IRQ32..63 Clear_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ +typedef struct _ADI_NVIC_INTCLRE1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Clear_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ */ + +/*@}*/ + +/** @defgroup INTSETP0 IRQ0..31 Set_Pending (INTSETP0) Register + * IRQ0..31 Set_Pending (INTSETP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETP0_Struct + *! \brief IRQ0..31 Set_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ +typedef struct _ADI_NVIC_INTSETP0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Set_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ */ + +/*@}*/ + +/** @defgroup INTSETP1 IRQ32..63 Set_Pending (INTSETP1) Register + * IRQ32..63 Set_Pending (INTSETP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETP1_Struct + *! \brief IRQ32..63 Set_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ +typedef struct _ADI_NVIC_INTSETP1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Set_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ */ + +/*@}*/ + +/** @defgroup INTCLRP0 IRQ0..31 Clear_Pending (INTCLRP0) Register + * IRQ0..31 Clear_Pending (INTCLRP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRP0_Struct + *! \brief IRQ0..31 Clear_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ +typedef struct _ADI_NVIC_INTCLRP0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Clear_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ */ + +/*@}*/ + +/** @defgroup INTCLRP1 IRQ32..63 Clear_Pending (INTCLRP1) Register + * IRQ32..63 Clear_Pending (INTCLRP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRP1_Struct + *! \brief IRQ32..63 Clear_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ +typedef struct _ADI_NVIC_INTCLRP1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Clear_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ */ + +/*@}*/ + +/** @defgroup INTACT0 IRQ0..31 Active Bit (INTACT0) Register + * IRQ0..31 Active Bit (INTACT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTACT0_Struct + *! \brief IRQ0..31 Active Bit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ +typedef struct _ADI_NVIC_INTACT0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Active Bit */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTACT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ */ + +/*@}*/ + +/** @defgroup INTACT1 IRQ32..63 Active Bit (INTACT1) Register + * IRQ32..63 Active Bit (INTACT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTACT1_Struct + *! \brief IRQ32..63 Active Bit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ +typedef struct _ADI_NVIC_INTACT1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Active Bit */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTACT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ */ + +/*@}*/ + +/** @defgroup INTPRI0 IRQ0..3 Priority (INTPRI0) Register + * IRQ0..3 Priority (INTPRI0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI0_Struct + *! \brief IRQ0..3 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ +typedef struct _ADI_NVIC_INTPRI0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..3 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ */ + +/*@}*/ + +/** @defgroup INTPRI1 IRQ4..7 Priority (INTPRI1) Register + * IRQ4..7 Priority (INTPRI1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI1_Struct + *! \brief IRQ4..7 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ +typedef struct _ADI_NVIC_INTPRI1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ4..7 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ */ + +/*@}*/ + +/** @defgroup INTPRI2 IRQ8..11 Priority (INTPRI2) Register + * IRQ8..11 Priority (INTPRI2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI2_Struct + *! \brief IRQ8..11 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ +typedef struct _ADI_NVIC_INTPRI2_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ8..11 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ */ + +/*@}*/ + +/** @defgroup INTPRI3 IRQ12..15 Priority (INTPRI3) Register + * IRQ12..15 Priority (INTPRI3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI3_Struct + *! \brief IRQ12..15 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ +typedef struct _ADI_NVIC_INTPRI3_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ12..15 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ */ + +/*@}*/ + +/** @defgroup INTPRI4 IRQ16..19 Priority (INTPRI4) Register + * IRQ16..19 Priority (INTPRI4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI4_Struct + *! \brief IRQ16..19 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ +typedef struct _ADI_NVIC_INTPRI4_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ16..19 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ */ + +/*@}*/ + +/** @defgroup INTPRI5 IRQ20..23 Priority (INTPRI5) Register + * IRQ20..23 Priority (INTPRI5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI5_Struct + *! \brief IRQ20..23 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ +typedef struct _ADI_NVIC_INTPRI5_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ20..23 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ */ + +/*@}*/ + +/** @defgroup INTPRI6 IRQ24..27 Priority (INTPRI6) Register + * IRQ24..27 Priority (INTPRI6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI6_Struct + *! \brief IRQ24..27 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ +typedef struct _ADI_NVIC_INTPRI6_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ24..27 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ */ + +/*@}*/ + +/** @defgroup INTPRI7 IRQ28..31 Priority (INTPRI7) Register + * IRQ28..31 Priority (INTPRI7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI7_Struct + *! \brief IRQ28..31 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ +typedef struct _ADI_NVIC_INTPRI7_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ28..31 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ */ + +/*@}*/ + +/** @defgroup INTPRI8 IRQ32..35 Priority (INTPRI8) Register + * IRQ32..35 Priority (INTPRI8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI8_Struct + *! \brief IRQ32..35 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ +typedef struct _ADI_NVIC_INTPRI8_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..35 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ */ + +/*@}*/ + +/** @defgroup INTPRI9 IRQ36..39 Priority (INTPRI9) Register + * IRQ36..39 Priority (INTPRI9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI9_Struct + *! \brief IRQ36..39 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ +typedef struct _ADI_NVIC_INTPRI9_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ36..39 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ */ + +/*@}*/ + +/** @defgroup INTPRI10 IRQ40..43 Priority (INTPRI10) Register + * IRQ40..43 Priority (INTPRI10) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI10_Struct + *! \brief IRQ40..43 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ +typedef struct _ADI_NVIC_INTPRI10_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ40..43 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI10_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ */ + +/*@}*/ + +/** @defgroup INTCPID CPUID Base (INTCPID) Register + * CPUID Base (INTCPID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCPID_Struct + *! \brief CPUID Base Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ +typedef struct _ADI_NVIC_INTCPID_t { + union { + struct { + unsigned int VALUE : 32; /**< CPUID Base */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCPID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ */ + +/*@}*/ + +/** @defgroup INTSTA Interrupt Control State (INTSTA) Register + * Interrupt Control State (INTSTA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSTA_Struct + *! \brief Interrupt Control State Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ +typedef struct _ADI_NVIC_INTSTA_t { + union { + struct { + unsigned int VALUE : 32; /**< Interrupt Control State */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSTA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ */ + +/*@}*/ + +/** @defgroup INTVEC Vector Table Offset (INTVEC) Register + * Vector Table Offset (INTVEC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTVEC_Struct + *! \brief Vector Table Offset Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ +typedef struct _ADI_NVIC_INTVEC_t { + union { + struct { + unsigned int VALUE : 32; /**< Vector Table Offset */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTVEC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ */ + +/*@}*/ + +/** @defgroup INTAIRC Application Interrupt/Reset Control (INTAIRC) Register + * Application Interrupt/Reset Control (INTAIRC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAIRC_Struct + *! \brief Application Interrupt/Reset Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ +typedef struct _ADI_NVIC_INTAIRC_t { + union { + struct { + unsigned int VALUE : 32; /**< Application Interrupt/Reset Control */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAIRC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ */ + +/*@}*/ + +/** @defgroup INTCON0 System Control (INTCON0) Register + * System Control (INTCON0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCON0_Struct + *! \brief System Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ +typedef struct _ADI_NVIC_INTCON0_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SLEEPONEXIT : 1; /**< Sleeps the core on exit from an ISR */ + unsigned int SLEEPDEEP : 1; /**< deep sleep flag for HIBERNATE mode */ + unsigned int reserved3 : 13; + }; + uint16_t VALUE16; + }; +} ADI_NVIC_INTCON0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ */ + +/*@}*/ + +/** @defgroup INTCON1 Configuration Control (INTCON1) Register + * Configuration Control (INTCON1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCON1_Struct + *! \brief Configuration Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ +typedef struct _ADI_NVIC_INTCON1_t { + union { + struct { + unsigned int VALUE : 32; /**< Configuration Control */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCON1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO0 System Handlers 4-7 Priority (INTSHPRIO0) Register + * System Handlers 4-7 Priority (INTSHPRIO0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO0_Struct + *! \brief System Handlers 4-7 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ +typedef struct _ADI_NVIC_INTSHPRIO0_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 4-7 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO1 System Handlers 8-11 Priority (INTSHPRIO1) Register + * System Handlers 8-11 Priority (INTSHPRIO1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO1_Struct + *! \brief System Handlers 8-11 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ +typedef struct _ADI_NVIC_INTSHPRIO1_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 8-11 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO3 System Handlers 12-15 Priority (INTSHPRIO3) Register + * System Handlers 12-15 Priority (INTSHPRIO3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO3_Struct + *! \brief System Handlers 12-15 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ +typedef struct _ADI_NVIC_INTSHPRIO3_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 12-15 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ */ + +/*@}*/ + +/** @defgroup INTSHCSR System Handler Control and State (INTSHCSR) Register + * System Handler Control and State (INTSHCSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHCSR_Struct + *! \brief System Handler Control and State Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ +typedef struct _ADI_NVIC_INTSHCSR_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handler Control and State */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHCSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ */ + +/*@}*/ + +/** @defgroup INTCFSR Configurable Fault Status (INTCFSR) Register + * Configurable Fault Status (INTCFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCFSR_Struct + *! \brief Configurable Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ +typedef struct _ADI_NVIC_INTCFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Configurable Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ */ + +/*@}*/ + +/** @defgroup INTHFSR Hard Fault Status (INTHFSR) Register + * Hard Fault Status (INTHFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTHFSR_Struct + *! \brief Hard Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ +typedef struct _ADI_NVIC_INTHFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Hard Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTHFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ */ + +/*@}*/ + +/** @defgroup INTDFSR Debug Fault Status (INTDFSR) Register + * Debug Fault Status (INTDFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTDFSR_Struct + *! \brief Debug Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ +typedef struct _ADI_NVIC_INTDFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Debug Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTDFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ */ + +/*@}*/ + +/** @defgroup INTMMAR Mem Manage Address (INTMMAR) Register + * Mem Manage Address (INTMMAR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMAR_Struct + *! \brief Mem Manage Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ +typedef struct _ADI_NVIC_INTMMAR_t { + union { + struct { + unsigned int VALUE : 32; /**< Mem Manage Address */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMAR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ */ + +/*@}*/ + +/** @defgroup INTBFAR Bus Fault Address (INTBFAR) Register + * Bus Fault Address (INTBFAR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTBFAR_Struct + *! \brief Bus Fault Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ +typedef struct _ADI_NVIC_INTBFAR_t { + union { + struct { + unsigned int VALUE : 32; /**< Bus Fault Address */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTBFAR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ */ + +/*@}*/ + +/** @defgroup INTAFSR Auxiliary Fault Status (INTAFSR) Register + * Auxiliary Fault Status (INTAFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAFSR_Struct + *! \brief Auxiliary Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ +typedef struct _ADI_NVIC_INTAFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Auxiliary Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ */ + +/*@}*/ + +/** @defgroup INTPFR0 Processor Feature Register 0 (INTPFR0) Register + * Processor Feature Register 0 (INTPFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPFR0_Struct + *! \brief Processor Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ +typedef struct _ADI_NVIC_INTPFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Processor Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ */ + +/*@}*/ + +/** @defgroup INTPFR1 Processor Feature Register 1 (INTPFR1) Register + * Processor Feature Register 1 (INTPFR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPFR1_Struct + *! \brief Processor Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ +typedef struct _ADI_NVIC_INTPFR1_t { + union { + struct { + unsigned int VALUE : 32; /**< Processor Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPFR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ */ + +/*@}*/ + +/** @defgroup INTDFR0 Debug Feature Register 0 (INTDFR0) Register + * Debug Feature Register 0 (INTDFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTDFR0_Struct + *! \brief Debug Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ +typedef struct _ADI_NVIC_INTDFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Debug Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTDFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ */ + +/*@}*/ + +/** @defgroup INTAFR0 Auxiliary Feature Register 0 (INTAFR0) Register + * Auxiliary Feature Register 0 (INTAFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAFR0_Struct + *! \brief Auxiliary Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ +typedef struct _ADI_NVIC_INTAFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Auxiliary Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR0 Memory Model Feature Register 0 (INTMMFR0) Register + * Memory Model Feature Register 0 (INTMMFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR0_Struct + *! \brief Memory Model Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ +typedef struct _ADI_NVIC_INTMMFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR1 Memory Model Feature Register 1 (INTMMFR1) Register + * Memory Model Feature Register 1 (INTMMFR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR1_Struct + *! \brief Memory Model Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ +typedef struct _ADI_NVIC_INTMMFR1_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR2 Memory Model Feature Register 2 (INTMMFR2) Register + * Memory Model Feature Register 2 (INTMMFR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR2_Struct + *! \brief Memory Model Feature Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ +typedef struct _ADI_NVIC_INTMMFR2_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 2 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR3 Memory Model Feature Register 3 (INTMMFR3) Register + * Memory Model Feature Register 3 (INTMMFR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR3_Struct + *! \brief Memory Model Feature Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ +typedef struct _ADI_NVIC_INTMMFR3_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 3 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ */ + +/*@}*/ + +/** @defgroup INTISAR0 ISA Feature Register 0 (INTISAR0) Register + * ISA Feature Register 0 (INTISAR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR0_Struct + *! \brief ISA Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ +typedef struct _ADI_NVIC_INTISAR0_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ */ + +/*@}*/ + +/** @defgroup INTISAR1 ISA Feature Register 1 (INTISAR1) Register + * ISA Feature Register 1 (INTISAR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR1_Struct + *! \brief ISA Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ +typedef struct _ADI_NVIC_INTISAR1_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ */ + +/*@}*/ + +/** @defgroup INTISAR2 ISA Feature Register 2 (INTISAR2) Register + * ISA Feature Register 2 (INTISAR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR2_Struct + *! \brief ISA Feature Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ +typedef struct _ADI_NVIC_INTISAR2_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 2 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ */ + +/*@}*/ + +/** @defgroup INTISAR3 ISA Feature Register 3 (INTISAR3) Register + * ISA Feature Register 3 (INTISAR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR3_Struct + *! \brief ISA Feature Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ +typedef struct _ADI_NVIC_INTISAR3_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 3 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ */ + +/*@}*/ + +/** @defgroup INTISAR4 ISA Feature Register 4 (INTISAR4) Register + * ISA Feature Register 4 (INTISAR4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR4_Struct + *! \brief ISA Feature Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ +typedef struct _ADI_NVIC_INTISAR4_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 4 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ */ + +/*@}*/ + +/** @defgroup INTTRGI Software Trigger Interrupt Register (INTTRGI) Register + * Software Trigger Interrupt Register (INTTRGI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTTRGI_Struct + *! \brief Software Trigger Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ +typedef struct _ADI_NVIC_INTTRGI_t { + union { + struct { + unsigned int VALUE : 32; /**< Software Trigger Interrupt Register */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTTRGI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ */ + +/*@}*/ + +/** @defgroup INTPID4 Peripheral Identification Register 4 (INTPID4) Register + * Peripheral Identification Register 4 (INTPID4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID4_Struct + *! \brief Peripheral Identification Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ +typedef struct _ADI_NVIC_INTPID4_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 4 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ */ + +/*@}*/ + +/** @defgroup INTPID5 Peripheral Identification Register 5 (INTPID5) Register + * Peripheral Identification Register 5 (INTPID5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID5_Struct + *! \brief Peripheral Identification Register 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ +typedef struct _ADI_NVIC_INTPID5_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 5 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ */ + +/*@}*/ + +/** @defgroup INTPID6 Peripheral Identification Register 6 (INTPID6) Register + * Peripheral Identification Register 6 (INTPID6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID6_Struct + *! \brief Peripheral Identification Register 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ +typedef struct _ADI_NVIC_INTPID6_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 6 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ */ + +/*@}*/ + +/** @defgroup INTPID7 Peripheral Identification Register 7 (INTPID7) Register + * Peripheral Identification Register 7 (INTPID7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID7_Struct + *! \brief Peripheral Identification Register 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ +typedef struct _ADI_NVIC_INTPID7_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 7 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ */ + +/*@}*/ + +/** @defgroup INTPID0 Peripheral Identification Bits7:0 (INTPID0) Register + * Peripheral Identification Bits7:0 (INTPID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID0_Struct + *! \brief Peripheral Identification Bits7:0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ +typedef struct _ADI_NVIC_INTPID0_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits7:0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ */ + +/*@}*/ + +/** @defgroup INTPID1 Peripheral Identification Bits15:8 (INTPID1) Register + * Peripheral Identification Bits15:8 (INTPID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID1_Struct + *! \brief Peripheral Identification Bits15:8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ +typedef struct _ADI_NVIC_INTPID1_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits15:8 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ */ + +/*@}*/ + +/** @defgroup INTPID2 Peripheral Identification Bits16:23 (INTPID2) Register + * Peripheral Identification Bits16:23 (INTPID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID2_Struct + *! \brief Peripheral Identification Bits16:23 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ +typedef struct _ADI_NVIC_INTPID2_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits16:23 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ */ + +/*@}*/ + +/** @defgroup INTPID3 Peripheral Identification Bits24:31 (INTPID3) Register + * Peripheral Identification Bits24:31 (INTPID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID3_Struct + *! \brief Peripheral Identification Bits24:31 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ +typedef struct _ADI_NVIC_INTPID3_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits24:31 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ */ + +/*@}*/ + +/** @defgroup INTCID0 Component Identification Bits7:0 (INTCID0) Register + * Component Identification Bits7:0 (INTCID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID0_Struct + *! \brief Component Identification Bits7:0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ +typedef struct _ADI_NVIC_INTCID0_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits7:0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ */ + +/*@}*/ + +/** @defgroup INTCID1 Component Identification Bits15:8 (INTCID1) Register + * Component Identification Bits15:8 (INTCID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID1_Struct + *! \brief Component Identification Bits15:8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ +typedef struct _ADI_NVIC_INTCID1_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits15:8 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ */ + +/*@}*/ + +/** @defgroup INTCID2 Component Identification Bits16:23 (INTCID2) Register + * Component Identification Bits16:23 (INTCID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID2_Struct + *! \brief Component Identification Bits16:23 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ +typedef struct _ADI_NVIC_INTCID2_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits16:23 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ */ + +/*@}*/ + +/** @defgroup INTCID3 Component Identification Bits24:31 (INTCID3) Register + * Component Identification Bits24:31 (INTCID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID3_Struct + *! \brief Component Identification Bits24:31 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ +typedef struct _ADI_NVIC_INTCID3_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits24:31 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ */ + +/*@}*/ + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#if defined (__CC_ARM) +#pragma pop +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/adi_cio_macros.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/adi_cio_macros.h new file mode 100755 index 00000000000..45f235b44be --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/adi_cio_macros.h @@ -0,0 +1,50 @@ +/* +** adi_cio_macros.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _ADI_CIO_MACROS_H +#define _ADI_CIO_MACROS_H + +/* + * Macro definitions in adi_ADuCM4*50_cdef.h and the struct definitions + * in adi_ADuCM4*50_device.h use macros "__I __C", "__O" and "__IO" to + * represent read-only, write-only and read/write register attributes. + * + * The core_cm4.h include file will define macros __I, __O and __IO as below + * but it does not define __C. + * + * The __C macro is defined to nothing here. The __C macro is intended for + * the proprietary compilers in CCES to avoid MISRA Rule 19.4 errors regarding + * permitted macro expansions. The iccarm.exe MISRA checking does not fault + * the combined "volatile const" __I macro so __C is not required. + * + * Each of the macro defines is guarded by a #ifndef check to allow them + * to be redefined if required. + * + * Workaround for 01-00-0757 / 01-00-0759 + */ + +#ifndef __I + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif +#endif + +#ifndef __O + #define __O volatile /*!< Defines 'write only' permissions */ +#endif + +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +#ifndef __C + #define __C /*nothing*/ +#endif + +#endif /* _ADI_CIO_MACROS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/platform.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/platform.h new file mode 100755 index 00000000000..37dbeae3816 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/sys/platform.h @@ -0,0 +1,60 @@ +/*! + ***************************************************************************** + * @file: platform.h + * @brief: Include appropriate architecture definitions. + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef __ADI_SYS_PLATFORM_H__ +#define __ADI_SYS_PLATFORM_H__ + +/* Include the ADI cdef header for the selected target. */ + +#if defined(__ADUCM4050__) +#include +#elif defined(__ADUCM3027__) +#include +#elif defined(__ADUCM3029__) +#include +#else +#error not configured for this target. +#endif + +#endif /* __ADI_SYS_PLATFORM_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h new file mode 100755 index 00000000000..d36a11ee65b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/system_ADuCM3029.h @@ -0,0 +1,127 @@ +/*! + ***************************************************************************** + * @file: system_ADuCM3029.h + * @brief: CMSIS Cortex-M3 Device Peripheral Access Layer Header File + * for the ADI ADuCxxx Device Series + * @version: $Revision: 36134 $ + * @date: $Date: 2017-01-12 05:13:23 -0500 (Thu, 12 Jan 2017) $ + *----------------------------------------------------------------------------- + * + * Copyright (C) 2009-2013 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + *****************************************************************************/ + + +/*! \addtogroup SYS_Driver System Interfaces + * @{ + * add result types to doxygen + */ + +#ifndef SYSTEM_ADUCM3029_H +#define SYSTEM_ADUCM3029_H + +#include /* for 'NULL' */ +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! \cond PRIVATE */ +#define SUCCESS 0u + +#define FAILURE 1u + +/* System clock constant */ +#define __HFOSC 26000000u + +/* System clock constant (may also be 16000000) */ +#define __HFXTAL 26000000u + +/*System clock constant (same whether internal osc or external xtal) */ +#define __LFCLK 32768u + +/* Selecting HFOSC as input for generating root clock*/ +#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* Selecting HFXTL as input for generating root clock*/ +#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* Selecting SPLL as input for generating root clock*/ +#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* Selecting GPIO as input for generating root clock*/ +#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* + * Security options + */ +typedef struct { + const uint32_t ReadProtectKeyHash[4]; + const uint32_t CrcOfReadProtectKeyHash; + const uint32_t LastCRCPage; + const uint32_t InCircuitWriteProtectCode; + const uint32_t FlashBlockWriteProtect; + +} ADI_ADUCM302X_SECURITY_OPTIONS; + +/*! \endcond */ + +/*! Cache controller key */ +#define CACHE_CONTROLLER_KEY 0xF123F456u +/*! Power key */ +#define PWRKEY_VALUE_KEY 0x4859u + + +/** + * SRAM banks + */ +typedef uint32_t ADI_SRAM_BANK; + +/*! SRAM_BANK_0 */ +#define ADI_SRAM_BANK_0 (1u << 0) +/*! SRAM_BANK_1 */ +#define ADI_SRAM_BANK_1 (1u << 1) +/*! SRAM_BANK_2 */ +#define ADI_SRAM_BANK_2 (1u << 2) +/*! SRAM_BANK_3 */ +#define ADI_SRAM_BANK_3 (1u << 3) +/*! SRAM_BANK_4 */ +#define ADI_SRAM_BANK_4 (1u << 4) +/*! SRAM_BANK_5 */ +#define ADI_SRAM_BANK_5 (1u << 5) +/*! SRAM_BANK_6 */ +#define ADI_SRAM_BANK_6 (1u << 6) +/*! SRAM_BANK_7 */ +#define ADI_SRAM_BANK_7 (1u << 7) + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +void adi_system_EnableCache(bool bEnable); +uint32_t adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable); +void adi_system_EnableISRAM(bool bEnable); +extern uint32_t SystemCoreClock; + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ADUCM3029_H */ + +/**@}*/ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c new file mode 100755 index 00000000000..9e889131ca2 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c @@ -0,0 +1,643 @@ +/*! ***************************************************************************** + * @file adi_tmr.c + * @brief GP and RGB timer device driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used +* Necessary for stdbool. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* Static configuration data file is included. +* +* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type +* This violation appears when deferencing the pointer to the register typedef. No way around this. +* +* Pm141 (Rule 11.4): a cast should not be performed between a pointer to object type and a different pointer to object type +* The pointer casting is necessary to allow the GP and RGB timers to abstracted into one driver. This has been approved by the PO. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm123,Pm140,Pm141,Pm143 +#endif /* __ICCARM__ */ + + +/** @addtogroup TMR_Driver Timer Driver + * @{ + * @brief General Purpose and RGB Timer Driver + * @details The timer driver controls the timer period, event capture, and + * pulse width modulation (PWM) features of the General Purpose (GP) Timers and + * the RGB Timer. + * @note The application must include drivers/tmr/adi_tmr.h to use this driver + */ + +#include +#include +#include +#include + +/* Static configuration data */ +#include "adi_tmr_data.c" + +#if defined(__ADUCM4x50__) +/* In adi_tmr_ConfigPwm, the bit positions for just PWM0 are used for PWM1 and PWM2 to simplify the code. Check here to make sure this is safe. */ +#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM1CTL_IDLESTATE +#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM2CTL_IDLESTATE +#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM1CTL_MATCH +#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM2CTL_MATCH +#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm." +#endif +#endif /*__ADUCM4x50__*/ + +/*! Number of events that can be captured */ +#if defined(__ADUCM302x__) +#define ADI_TMR_NUM_EVENTS (16u) +#elif defined(__ADUCM4x50__) +#define ADI_TMR_NUM_EVENTS (40u) +#else +#error TMR is not ported for this processor +#endif + +/*! \cond PRIVATE */ + +/* Since the RGB typedef is a superset of the GP typedef, treat the GP timers as RGB timers and restrict top register access */ +#if defined(__ADUCM302x__) +static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2}; +#elif defined(__ADUCM4x50__) +static ADI_TMR_RGB_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {(ADI_TMR_RGB_TypeDef *) pADI_TMR0, (ADI_TMR_RGB_TypeDef *) pADI_TMR1, (ADI_TMR_RGB_TypeDef *) pADI_TMR2, pADI_TMR_RGB}; +#else +#error TMR is not ported for this processor +#endif + +/* Interrupt enums */ +#if defined(__ADUCM302x__) +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn}; +#elif defined(__ADUCM4x50__) +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn}; +#else +#error TMR is not ported for this processor +#endif + +/* Private data that the driver needs to retain between function calls */ +static ADI_CALLBACK adi_tmr_callbacks[ADI_TMR_DEVICE_NUM]; +static void * adi_tmr_parameters[ADI_TMR_DEVICE_NUM]; + +static ADI_TMR_RESULT WaitForStatusBit (ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit); +static void CommonIntHandler (ADI_TMR_DEVICE const eDevice); + void GP_Tmr0_Int_Handler(void); + void GP_Tmr1_Int_Handler(void); + void GP_Tmr2_Int_Handler(void); +#if defined(__ADUCM4x50__) + void RGB_Tmr_Int_Handler(void); +#endif + +/*! \endcond */ + + +/********************************************************************************* + API IMPLEMENTATIONS +*********************************************************************************/ + + +/*! + * @brief Initialize GP or RGB Timer + * + * @details Setup callback function, device interrupt, and perform static configuration (if applicable). + * + * @note This function can only be called when the timer is disabled. This function should be called + * before any other functions are called. + * + * @param [in] eDevice : Device number + * + * @param [in] pfCallback : Callback function + * + * @param [in] pCBParam : Callback function parameter + * + * @param [in] bEnableInt : True to enable the device interrupt, false to disable it + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Init(ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Setup the callback function */ + adi_tmr_callbacks [eDevice] = pfCallback; + adi_tmr_parameters[eDevice] = pCBParam; + + /* IF(Enable interrupt) */ + if (bEnableInt == true) { + NVIC_EnableIRQ(adi_tmr_interrupt[eDevice]); + /* ELSE(Disable interrupt) */ + } else { + NVIC_DisableIRQ(adi_tmr_interrupt[eDevice]); + } /* ENDIF */ + + /* Static configuration */ + adi_tmr_registers[eDevice]->CTL = aTimerCtlConfig [eDevice]; + adi_tmr_registers[eDevice]->LOAD = aTimerLoadConfig [eDevice]; + adi_tmr_registers[eDevice]->ALOAD = aTimerALoadConfig [eDevice]; + adi_tmr_registers[eDevice]->PWM0CTL = aTimerPwmCtlConfig [eDevice]; + adi_tmr_registers[eDevice]->PWM0MATCH = aTimerPwmMatchConfig[eDevice]; +#if defined(__ADUCM4x50__) + adi_tmr_registers[eDevice]->EVENTSELECT = aTimerEventConfig [eDevice]; + + /* IF(Initializing the RGB timer, there are 2 other PWM outputs to configure) */ + if (eDevice == ADI_TMR_DEVICE_RGB) { + /* The array is bumped by 1 to get to the 5th entry in the static config array, which contains RGB PWM1 */ + adi_tmr_registers[eDevice]->PWM1CTL = aTimerPwmCtlConfig [eDevice+1u]; + adi_tmr_registers[eDevice]->PWM1MATCH = aTimerPwmMatchConfig[eDevice+1u]; + /* The array is bumped by 2 to get to the 6th entry in the static config array, which contains RGB PWM2 */ + adi_tmr_registers[eDevice]->PWM2CTL = aTimerPwmCtlConfig [eDevice+2u]; + adi_tmr_registers[eDevice]->PWM2MATCH = aTimerPwmMatchConfig[eDevice+2u]; + } /* ENDIF */ +#endif /*__ADUCM4x50__*/ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Configure GP or RGB Timer + * + * @details Configure the basic hardware timer parameters. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] timerConfig : Timer configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_BAD_RELOAD_CONFIGURATION [D] bPeriodic is false and bReloading is true + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG* timerConfig) { + uint16_t nTemp; +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Bad configuration, cannot enable reloading while in free running mode) */ + if ((timerConfig->bPeriodic == false) && (timerConfig->bReloading == true)) { + return ADI_TMR_BAD_RELOAD_CONFIGURATION; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Set the load registers */ + adi_tmr_registers[eDevice]->LOAD = timerConfig->nLoad; + adi_tmr_registers[eDevice]->ALOAD = timerConfig->nAsyncLoad; + + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Read the control register and clear everything aside to the event capture bits, which are the only fields not set in this function */ + nTemp = adi_tmr_registers[eDevice]->CTL; + nTemp &= (uint16_t) (BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN ); + + /* Setup the prescaler and the clock source */ + nTemp |= (uint16_t)(((uint16_t) timerConfig->ePrescaler ) << BITP_TMR_RGB_CTL_PRE); + nTemp |= (uint16_t)(((uint16_t) timerConfig->eClockSource) << BITP_TMR_RGB_CTL_CLK); + + /* IF(Periodic mode) */ + if (timerConfig->bPeriodic == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_MODE); + } /* ENDIF */ + + /* IF(Counting up) */ + if (timerConfig->bCountingUp == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_UP); + } /* ENDIF */ + + /* IF(Reloading is enabled) */ + if (timerConfig->bReloading == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_RLD); + } /* ENDIF */ + + /* IF(Sync bypass is enabled) */ + if (timerConfig->bSyncBypass == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_SYNCBYP); + } /* ENDIF */ + + /* Update the control register with the new configuration */ + adi_tmr_registers[eDevice]->CTL = nTemp; + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Setup GP or RGB Timer Event Capture + * + * @details The timer can be configured to capture the timer value when a specific event occurs. The + * list of events can be found in the hardware reference manual. The callback function specified + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The + * user can then read the captured value by calling #adi_tmr_GetCaptureCount. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] eventConfig : Event configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_BAD_EVENT_ID [D] Event ID was not out of the valid range [0,#ADI_TMR_NUM_EVENTS] + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigEvent(ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG* eventConfig) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Bad event input parameter) */ + if (eventConfig->nEventID >= ADI_TMR_NUM_EVENTS) { + return ADI_TMR_BAD_EVENT_ID; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + +#if defined(__ADUCM4x50__) + /* Set the event number */ + adi_tmr_registers[eDevice]->EVENTSELECT = (uint16_t) eventConfig->nEventID; +#endif + + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Clear the event enable bit and keep the other bits */ + adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~(BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN ); + + /* IF(Turning event capture on) */ + if (eventConfig->bEnable == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EVTEN; + } /* ENDIF */ + + /* IF(Enabling reset on event capture) */ + if (eventConfig->bPrescaleReset == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_RSTEN; + } /* ENDIF */ + +#if defined(__ADUCM302x__) + /* Write the event index */ + adi_tmr_registers[eDevice]->CTL |= (uint16_t) (((uint16_t) eventConfig->nEventID) << BITP_TMR_CTL_EVTRANGE); +#endif + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Setup GP or RGB Timer Pulse Width Modulation + * + * @details The timer can be configured to generate a pulse width modulation output signal. + * The period of this signal is simply determined by the period of timer. The duty + * cycle will be 50% in toggle mode, or can be configured by the user for a different + * value using the match value. The pulse will toggle when the timer count matches + * the match value. The user can also specify the polarity of the signal by choosing + * if the signal idles low or high. GPIO muxing will be required to use the PWM output. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] pwmConfig : PWM configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_BAD_PWM_NUM [D] Invalid eOutput parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigPwm(ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG* pwmConfig) { + uint16_t nControl = 0u; +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#if defined(__ADUCM4x50__) + /* IF(Bad PWM output and device combo OR bad PWM output) */ + if (((eDevice != ADI_TMR_DEVICE_RGB) && (pwmConfig->eOutput != ADI_TMR_PWM_OUTPUT_0)) || (pwmConfig->eOutput >= ADI_TMR_PWM_OUTPUT_NUM)) { + return ADI_TMR_BAD_PWM_NUM; + } /* ENDIF */ +#endif +#endif + /* IF(Idle high is set) */ + if (pwmConfig->bIdleHigh == true) { + nControl = (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_IDLESTATE)); + } /* ENDIF */ + + /* IF(Match mode is enabled) */ + if (pwmConfig->bMatch == true) { + nControl |= (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_MATCH)); + } /* ENDIF */ + + /* IF(PWM output 0) */ + if (pwmConfig->eOutput == ADI_TMR_PWM_OUTPUT_0) { + adi_tmr_registers[eDevice]->PWM0CTL = nControl; + adi_tmr_registers[eDevice]->PWM0MATCH = pwmConfig->nMatchValue; + } +#if defined(__ADUCM4x50__) + /* IF(PWM output 1) */ + else if (pwmConfig->eOutput == ADI_TMR_PWM_OUTPUT_1) { + adi_tmr_registers[eDevice]->PWM1CTL = nControl; + adi_tmr_registers[eDevice]->PWM1MATCH = pwmConfig->nMatchValue; + /* ELSE(PWM output 2) */ + } else { + adi_tmr_registers[eDevice]->PWM2CTL = nControl; + adi_tmr_registers[eDevice]->PWM2MATCH = pwmConfig->nMatchValue; + } /* ENDIF */ +#endif + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Enable or Disable the GP or RGB Timer + * + * @details Start or stop the timer. + * + * @param [in] eDevice : Device number + * + * @param [in] bEnable : True to enable, false to disable + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Enable(ADI_TMR_DEVICE const eDevice, bool bEnable) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ +#endif + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Clear the enable bit and keep the other bits */ + adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~BITM_TMR_RGB_CTL_EN; + + /* IF(Turning the timer on) */ + if (bEnable == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Get GP or RGB Timer Current Count + * + * @details Read the timer. + * + * @param [in] eDevice : Device number + * + * @param [out] pCount : Pointer to the result. + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_NULL_POINTER [D] Invalid pCount parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_GetCurrentCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Null pointer) */ + if (pCount == NULL) { + return ADI_TMR_NULL_POINTER; + } /* ENDIF */ +#endif + *pCount = adi_tmr_registers[eDevice]->CURCNT; + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Get GP or RGB Timer Captured Count + * + * @details Read the captured timer value. This should be called after the callback function + * is called with #ADI_TMR_EVENT_CAPTURE in the Event field. + * + * @param [in] eDevice : Device number + * + * @param [out] pCount : Pointer to the result. + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_NULL_POINTER [D] Invalid pCount parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_GetCaptureCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Null pointer) */ + if (pCount == NULL) { + return ADI_TMR_NULL_POINTER; + } /* ENDIF */ +#endif + *pCount = adi_tmr_registers[eDevice]->CAPTURE; + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Reload GP or RGB Timer + * + * @details Only relevent in peridic mode and when bReloading was set to + * true when configuring the timer. Calling this function will + * reload (i.e. reset) the timer to the LOAD value. + * + * @param [in] eDevice : Device number + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_RELOAD_DISABLED [D] Reloading not enabled for this timer + * - #ADI_TMR_DEVICE_BUSY Reload did not take effect in time + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Reload(ADI_TMR_DEVICE const eDevice) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Reloading has not been enabled) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_RLD) != BITM_TMR_RGB_CTL_RLD) { + return ADI_TMR_RELOAD_DISABLED; + } /* ENDIF */ +#endif + /* Clear the timeout bit to cause a reload to happen */ + adi_tmr_registers[eDevice]->CLRINT = BITM_TMR_RGB_CLRINT_TIMEOUT; + /* IF(The clear interrupt does not take effect in a reasonable amount of time) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_PDOK)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + return ADI_TMR_SUCCESS; +} + + +/********************************************************************************* + PRIVATE FUNCTIONS +*********************************************************************************/ + + /*! \cond PRIVATE */ + +static ADI_TMR_RESULT WaitForStatusBit(ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit) { + /* FOR(Number of arbitrary iterations) */ + for (uint16_t i = 0u; i < 1000u; i++) { + /* IF(Busy bit is low) */ + if ((adi_tmr_registers[(eDevice)]->STAT & nBusyBit) == ((uint16_t) 0u)) { + return ADI_TMR_SUCCESS; + } /* ENDIF */ + } /* ENDFOR */ + return ADI_TMR_DEVICE_BUSY; +} + +static void CommonIntHandler(ADI_TMR_DEVICE const eDevice) { + /* Read status register */ + uint16_t IntStatus = adi_tmr_registers[eDevice]->STAT; + /* IF(Callback function has been set) */ + if(adi_tmr_callbacks[eDevice] != NULL) { + /* IF(Timeout interrupt occurred) */ + if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_TIMEOUT)) != ((uint16_t) 0u)) { + adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_TIMEOUT, NULL); + } /* ENDIF */ + /* IF(Event capture interrupt occurred) */ + if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_CAPTURE)) != ((uint16_t) 0u)) { + adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_CAPTURE, NULL); + } /* ENDIF */ + } /* ENDIF */ + /* Clear pending interrupt */ + adi_tmr_registers[eDevice]->CLRINT = (BITM_TMR_RGB_CLRINT_EVTCAPT | BITM_TMR_RGB_CLRINT_TIMEOUT); +} + +void GP_Tmr0_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP0); + ISR_EPILOG() +} + +void GP_Tmr1_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP1); + ISR_EPILOG() +} + +void GP_Tmr2_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP2); + ISR_EPILOG() +} + +#if defined(__ADUCM4x50__) +void RGB_Tmr_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_RGB); + ISR_EPILOG() +} +#endif +/*! \endcond */ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr_data.c new file mode 100755 index 00000000000..22e656b56cf --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr_data.c @@ -0,0 +1,194 @@ +/*! ***************************************************************************** + * @file adi_tmr_data.c + * @brief GP and RGB timer static configuration data + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_DATA +#define ADI_TMR_DATA + + +#include +#include +#include +#include + +/* Macro mapping from ADuCM4x50 to ADuCM302x */ +#if defined(__ADUCM302x__) +#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN +#define PWM0CTL PWMCTL +#define PWM0MATCH PWMMATCH +#define BITM_TMR_RGB_STAT_BUSY BITM_TMR_STAT_BUSY +#define BITM_TMR_RGB_CTL_EVTEN BITM_TMR_CTL_EVTEN +#define BITM_TMR_RGB_CTL_RSTEN BITM_TMR_CTL_RSTEN +#define BITP_TMR_RGB_CTL_RSTEN BITP_TMR_CTL_RSTEN +#define BITP_TMR_RGB_CTL_EVTEN BITP_TMR_CTL_EVTEN +#define BITP_TMR_RGB_CTL_PRE BITP_TMR_CTL_PRE +#define BITP_TMR_RGB_CTL_CLK BITP_TMR_CTL_CLK +#define BITP_TMR_RGB_CTL_MODE BITP_TMR_CTL_MODE +#define BITP_TMR_RGB_CTL_UP BITP_TMR_CTL_UP +#define BITP_TMR_RGB_CTL_RLD BITP_TMR_CTL_RLD +#define BITP_TMR_RGB_CTL_SYNCBYP BITP_TMR_CTL_SYNCBYP +#define BITP_TMR_RGB_PWM0CTL_IDLESTATE BITP_TMR_PWMCTL_IDLESTATE +#define BITP_TMR_RGB_PWM0CTL_MATCH BITP_TMR_PWMCTL_MATCH +#define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT +#define BITM_TMR_RGB_STAT_PDOK BITM_TMR_STAT_PDOK +#define BITM_TMR_RGB_STAT_TIMEOUT BITM_TMR_STAT_TIMEOUT +#define BITM_TMR_RGB_STAT_CAPTURE BITM_TMR_STAT_CAPTURE +#define BITM_TMR_RGB_CLRINT_EVTCAPT BITM_TMR_CLRINT_EVTCAPT +#define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT +#define BITM_TMR_RGB_CTL_RLD BITM_TMR_CTL_RLD +#endif /*__ADUCM302x__*/ + +/* CTL register static configuration */ +static uint16_t aTimerCtlConfig[] = +{ + (TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR0_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR1_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + +#if defined(__ADUCM4x50__) + (TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), +#endif +}; + +/* LOAD register static configuration */ +static uint16_t aTimerLoadConfig[] = +{ + TMR0_CFG_LOAD_VALUE, + TMR1_CFG_LOAD_VALUE, + TMR2_CFG_LOAD_VALUE, +#if defined(__ADUCM4x50__) + TMR3_CFG_LOAD_VALUE, +#endif +}; + +/* Asynchronous LOAD static configuraton */ +static uint16_t aTimerALoadConfig[] = +{ + TMR0_CFG_ASYNC_LOAD_VALUE, + TMR1_CFG_ASYNC_LOAD_VALUE, + TMR2_CFG_ASYNC_LOAD_VALUE, +#if defined(__ADUCM4x50__) + TMR3_CFG_ASYNC_LOAD_VALUE, +#endif +}; + +/* EVENTSELECT static configuration */ +#if defined(__ADUCM4x50__) +static uint16_t aTimerEventConfig[] = +{ + TMR0_CFG_EVENT_CAPTURE, + TMR1_CFG_EVENT_CAPTURE, + TMR2_CFG_EVENT_CAPTURE, + TMR3_CFG_EVENT_CAPTURE, +}; +#endif + +/* PWM CTL static configuration */ +static uint16_t aTimerPwmCtlConfig[] = +{ + (TMR0_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR0_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR1_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR1_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + +#if defined(__ADUCM4x50__) + (TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) | + (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH), + + (TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) | + (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH), +#endif +}; + +/* PWM MATCH static configuration */ +static uint16_t aTimerPwmMatchConfig[] = { + TMR0_CFG_PWM0_MATCH_VALUE, + TMR1_CFG_PWM0_MATCH_VALUE, + TMR2_CFG_PWM0_MATCH_VALUE, +#if defined(__ADUCM4x50__) + TMR3_CFG_PWM0_MATCH_VALUE, + TMR3_CFG_PWM1_MATCH_VALUE, + TMR3_CFG_PWM2_MATCH_VALUE +#endif +}; + + +#endif /* ADI_TMR_DATA */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c new file mode 100755 index 00000000000..f0dc346bfa1 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c @@ -0,0 +1,2797 @@ +/*! ***************************************************************************** + * @file: adi_uart.c + * @brief: uart device driver implementation + * @details: This file contains the UART device driver functions + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup UART_Driver + * @{ + * @brief UART Driver + * @note The application must include drivers/uart/adi_uart.h to use this + * driver + * @note This driver requires the DMA driver.The application must + * include the DMA driver sources to avoid link errors. + */ + +/*! \cond PRIVATE */ +#include +#include +#include "adi_uart_def.h" +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm50: (MISRA C 2004 rule 14.3): a null statement shall only occur on a line by itself, +* and shall not have any other text on the same line +* Some Macros, such as ISR_PROLOGUE, may not have any expansion +* resulting in just the terminating ';'. +* +* Pm073 (rule 14.7): A function should have a single point of exit. +* Pm143 (rule 14.7): A function should have a single point of exit at the end of the function. +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): Pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm123 (rule 18.5): There shall be no definition of objects in a header file. +* +* Pm140 (rule 11.3): A cast should not be performed between a pointer type and an integral type. +* MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type. +* +* Pm152 (rule 17.4): Array indexing shall only be applied to objects defined as an array type. +* Relying on pointer arithmetic for buffer handling and +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors. +* +* Pm008: Code should not be commented out. + This code was commented out to show what the autobaud equations would look like if there were floating point precision. + Ideally this would be the case but for the sake of footprint size we will leave it at single point precision. +*/ +#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008 +#endif /* __ICCARM__ */ + + + + +/********************************************************** + * UART Data + **********************************************************/ +static ADI_UART_DEVICE_INFO uart_device_info[ ] = +{ + { + UART0_TX_CHANn, /*!< DMA channel number for UART0 Tx. */ + UART0_RX_CHANn, /*!< DMA channel number for UART0 Rx. */ + DMA0_CH8_DONE_IRQn, /*!< DMA channel IRQ for UART0 Tx. */ + DMA0_CH9_DONE_IRQn, /*!< DMA channel IRQ for UART0 Rx. */ + (IRQn_Type)INTR_UART0_EVT, /*!< UART0 interrupt ID. */ + pADI_UART0, /*!< Start address of UART0. */ + NULL /*!< Device Handle for UART0. */ + }, +#if defined (__ADUCM4x50__) + { + UART1_TX_CHANn, /*!< DMA channel number for UART1 Tx. */ + UART1_RX_CHANn, /*!< DMA channel number for UART1 Rx. */ + DMA0_CH25_DONE_IRQn, /*!< DMA channel IRQ for UART1 Tx. */ + DMA0_CH26_DONE_IRQn, /*!< DMA channel IRQ for UART1 Rx. */ + (IRQn_Type)INTR_UART1_EVT, /*!< UART1 interrupt ID. */ + pADI_UART1, /*!< Start address of UART1. */ + NULL /*!< Device Handle for UART1. */ + }, +#endif /* __ADUCM4x50 */ +}; + +static const ADI_UART_CONFIG gUARTCfg[ ] = +{ + { + /* Line control register. */ + ((ADI_UART0_CFG_WORD_LENGTH << BITP_UART_LCR_WLS) | + (ADI_UART0_CFG_STOP_BIT << BITP_UART_LCR_STOP) | + (ADI_UART0_CFG_ENABLE_PARITY << BITP_UART_LCR_PEN) | + (ADI_UART0_CFG_PARITY_SELECTION << BITP_UART_LCR_EPS) | + (ADI_UART0_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)), + + /* Div-C in baudrate divider register. */ + ADI_UART0_CFG_DIVC, + + /* Div-M and Div-N in fractional baudrate Register. */ + (((uint32_t)ADI_UART0_CFG_DIVN << BITP_UART_FBR_DIVN) | + ((uint32_t)ADI_UART0_CFG_DIVM << BITP_UART_FBR_DIVM) | + ((uint32_t)BITM_UART_FBR_FBEN)), + + /* Over sample rate in second line control register. */ + ADI_UART0_CFG_OSR, + + /* FIFO control register. */ + ((ADI_UART0_CFG_ENABLE_FIFO << BITP_UART_FCR_FIFOEN)| + (ADI_UART0_CFG_TRIG_LEVEL << BITP_UART_FCR_RFTRIG)), + + /* Half duplex control register. */ + ((ADI_UART0_CFG_SOUT_POLARITY << BITP_UART_RSC_OENP) | + (ADI_UART0_CFG_DEASSERTION << BITP_UART_RSC_OENSP) | + (ADI_UART0_CFG_DISABLE_RX << BITP_UART_RSC_DISRX) | + (ADI_UART0_CFG_HOLD_TX << BITP_UART_RSC_DISTX)), + + /* Interrupt enable register. */ + ((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) | + (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT << BITP_UART_IEN_ELSI)) + + }, +#if defined (__ADUCM4x50__) + { + /* Line control register. */ + ((ADI_UART1_CFG_WORD_LENGTH << BITP_UART_LCR_WLS) | + (ADI_UART1_CFG_STOP_BIT << BITP_UART_LCR_STOP) | + (ADI_UART1_CFG_ENABLE_PARITY << BITP_UART_LCR_PEN) | + (ADI_UART1_CFG_PARITY_SELECTION << BITP_UART_LCR_EPS) | + (ADI_UART1_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)), + + /* Div-C in Baudrate divider register. */ + ADI_UART1_CFG_DIVC, + + /* Div-M and Div-N in fractional baudrate Register. */ + (((uint32_t)ADI_UART1_CFG_DIVN << BITP_UART_FBR_DIVN) | + ((uint32_t)ADI_UART1_CFG_DIVM << BITP_UART_FBR_DIVM) | + ((uint32_t)BITM_UART_FBR_FBEN)), + + /* Over sample rate in second line control register. */ + ADI_UART1_CFG_OSR, + + /* FIFO control register. */ + ((ADI_UART1_CFG_ENABLE_FIFO << BITP_UART_FCR_FIFOEN)| + (ADI_UART1_CFG_TRIG_LEVEL << BITP_UART_FCR_RFTRIG)), + + /* Half duplex control register. */ + ((ADI_UART1_CFG_SOUT_POLARITY << BITP_UART_RSC_OENP) | + (ADI_UART1_CFG_DEASSERTION << BITP_UART_RSC_OENSP) | + (ADI_UART1_CFG_DISABLE_RX << BITP_UART_RSC_DISRX) | + (ADI_UART1_CFG_HOLD_TX << BITP_UART_RSC_DISTX)), + + /* Interrupt enable register. */ + ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) | + (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT << BITP_UART_IEN_ELSI)) + } +#endif /*__ADUCM4x50*/ +}; + +/*! \endcond */ + +/*! Number of UART devices available on the chip. */ +#define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO)) + +/* Override "weak" default binding in startup.c */ +/*! \cond PRIVATE */ +extern void UART0_Int_Handler(void); +extern void UART1_Int_Handler(void); +extern void DMA_UART0_TX_Int_Handler(void); +extern void DMA_UART0_RX_Int_Handler(void); + +#if defined (__ADUCM4x50__) +extern void DMA_UART1_TX_Int_Handler(void); +extern void DMA_UART1_RX_Int_Handler(void); +#endif + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam; + ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR; + break; + default: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + + if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true)) + { + hDevice->nHwError |= nEvent; + pNextBuff->bInUse = false; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); + + } + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +} + +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam; + ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR; + break; + default: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true)) + { + hDevice->nHwError |= nEvent; + pNextBuff->bInUse = false; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); + + } + + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +} +/*! \endcond */ + +/********************************************************** + * General UART APIs + **********************************************************/ + +/*! + * @brief Initialization function for the UART device. + * @details Opens the specified UART device. This function must be called before operating any UART device. + * + * + * @param [in] nDeviceNum UART device instance to be opened. + * @param [in] eDirection Direction of the UART operation. (i.e Rx or Tx) + * @param [in] pMemory Pointer to a 32 bit aligned buffer the size of #ADI_UART_UNIDIR_MEMORY_SIZE + * or #ADI_UART_BIDIR_MEMORY_SIZE. + * @param [in] nMemSize Size of the buffer to which "pMemory" points. This will vary based on + * direction of operation for this device instance. (i.e Rx and Tx, Rx, Tx) + * + * @param [out] phDevice The caller's device handle pointer for storing the initialized device instance data pointer. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully initialized UART device. + * - #ADI_UART_SEMAPHORE_FAILED Failed to create semaphore. + * - #ADI_UART_INVALID_DEVICE_NUM [D] Device instance is invalid. + * - #ADI_UART_INSUFFICIENT_MEMORY [D] Supplied memory is insufficient for the operation of specified UART device. + * - #ADI_UART_DEVICE_IN_USE [D] Device is already open. + * + * @sa adi_uart_Close() + * + * @note: Memory supplied by the API will be used by the driver for managing the UART device. This memory can be reused once + * device is closed. + * + */ +ADI_UART_RESULT adi_uart_Open( + uint32_t const nDeviceNum, + ADI_UART_DIRECTION const eDirection, + void *pMemory, + uint32_t const nMemSize, + ADI_UART_HANDLE *const phDevice + ) +{ +#ifdef ADI_DEBUG + /* Check if the given device number is within the range of UART + * devices present in the processor. There are two devices present here + * so this can be a 0 or 1 for ADuCM4050 and only 0 for ADuCM302x. + */ + if(nDeviceNum >= ADI_UART_NUM_DEVICES) + { + return(ADI_UART_INVALID_DEVICE_NUM); + } + + /* Verify the device is not already open. */ + if(uart_device_info[nDeviceNum].hDevice != NULL) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure there is enough memory for the device instance to operate in a single direction. */ + if(eDirection != ADI_UART_DIR_BIDIRECTION) + { + if(nMemSize < (uint32_t)ADI_UART_UNIDIR_MEMORY_SIZE) + { + return(ADI_UART_INSUFFICIENT_MEMORY); + } + assert(nMemSize == (sizeof(ADI_UART_DEVICE) + sizeof(ADI_UART_DATA_CHANNEL))); + } + + /* Make sure there is enough memory for the device instance to operate in both directions. */ + else + { + if(nMemSize < (uint32_t)ADI_UART_BIDIR_MEMORY_SIZE) + { + return(ADI_UART_INSUFFICIENT_MEMORY); + } + assert(nMemSize == (sizeof(ADI_UART_DEVICE) + (sizeof(ADI_UART_DATA_CHANNEL)*2u))); + } +#endif /* ADI_DEBUG */ + + /* Initialize the device handle to NULL in case of a failure. */ + *phDevice = NULL; + + /* Link the ADI_UART_HANDLE to the ADI_UART_DEVICE structure. */ + ADI_UART_HANDLE hDevice = pMemory; + + /* Zero the device handle memory so we do not have to explicitely initialize + the structure members to 0. + */ + memset(pMemory, 0, nMemSize); + + + /* Set the device information. */ + hDevice->pUartInfo = &uart_device_info[nDeviceNum]; + + /* Set the base of the UART register address. We do this to minimize + the cycle count when accessing the UART registers. + */ + hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs; + + /* Store the direction that this device will operate in. */ + hDevice->eDirection = eDirection; + + /* Increment the device handle with the size of the UART device structure + so we can set the channel data next without overwriting + the #ADI_UART_DEVICE data. + */ + pMemory = ((uint8_t *)pMemory +(sizeof(ADI_UART_DEVICE))); + + /* Set up the DMA Controller. */ + adi_dma_Init(); + + /* Initialize the TX-channel. */ + if(ADI_UART_DIR_RECEIVE != eDirection) + { + hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory; + + /* Initialize the data transfer mode. */ + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + + /* Initialize Tx buffer pointers. */ + hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0]; + + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + SEM_CREATE(hDevice->pChannelTx, "UART_TX_SEM", ADI_UART_SEMAPHORE_FAILED); + + /* Set submit buffer function pointer. */ + hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer; + + hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1]; + hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0]; + + /*Register DMA Callback. */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaTxChannelNum, TxDmaErrorCallback, (void*)hDevice)) + { + adi_uart_Close(hDevice); + return ADI_UART_ERR_DMA_REGISTER; + } + + /* Increment the device handle the size of #ADI_UART_DATA_CHANNEL + structure in case there is another channel to configure. + */ + pMemory = ((uint8_t *)pMemory + sizeof(ADI_UART_DATA_CHANNEL)); + } + /* Initialize the RX-channel. */ + if(ADI_UART_DIR_TRANSMIT != eDirection) + { + hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory; + + /* Initialize the data transfer mode. */ + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + + /* Initialize Rx buffer pointers. */ + hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + SEM_CREATE(hDevice->pChannelRx, "UART_RX_SEM", ADI_UART_SEMAPHORE_FAILED); + + /* Set submit buffer function pointer. */ + hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer; + + hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1]; + hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0]; + + /*Register DMA Callback. */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaRxChannelNum, RxDmaErrorCallback, (void*)hDevice)) + { + adi_uart_Close(hDevice); + return ADI_UART_ERR_DMA_REGISTER; + } + } + + /* Initialize the device with the static config values.*/ + uart_init(hDevice, nDeviceNum); + + /* Write the device data pointer to the application's handle. */ + *phDevice = hDevice; + + /* Store the device handle. */ + uart_device_info[nDeviceNum].hDevice = hDevice; + + + /* Enable UART Interrupt. */ + NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn); + NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn); + + /* Enable the interrupt for the DMA. */ + NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx); + NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx); + + /* Return SUCCESS */ + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Uninitialize the memory for the specified UART instance. + * + * @param [in] hDevice UART device handle whose operation is to be closed. This handle was obtained when the UART + * device instance was opened successfully. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully closed the UART device instance. + * - #ADI_UART_SEMAPHORE_FAILED Failed to delete the semaphore. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_DEVICE_IN_USE [D] Specified UART device is in the process of a transaction or autobaud has not completed. + * + * @details Closes the operation of specified UART device. Device needs to be opened again for any further use. + * + * @sa adi_uart_Open() + * + * @note: It is the user's responsibility to free/reuse the memory supplied during the opening of the device. + */ +ADI_UART_RESULT adi_uart_Close( + ADI_UART_HANDLE const hDevice + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel, autobaud is not in progress and the + Tx shift register is completely empty. This can be an issue if you submitted a nonblocking transmit + because you will receive interrupt before the hardware has fully finished the transaction. The start + address of the active buffer will remain in use until the buffer has been completely processed. + Therefore if the start address is NULL it means it has not been submitted for a transaction. + */ + if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) || + ((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Disable UART status interrupts. */ + hDevice->pUARTRegs->IEN = 0x00U; + + /* Disable DMA UART interrupts. */ + NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx); + NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx); + + /* Disable UART event interrupt. */ + NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn); + + /* Delete Tx-Channel semaphore. */ + if(hDevice->eDirection != ADI_UART_DIR_RECEIVE) + { + SEM_DELETE(hDevice->pChannelTx, ADI_UART_SEMAPHORE_FAILED); + } + + /* Delete Rx-Channel semaphore. */ + if(hDevice->eDirection != ADI_UART_DIR_TRANSMIT) + { + SEM_DELETE(hDevice->pChannelRx, ADI_UART_SEMAPHORE_FAILED); + } + + /* Free up the device memory. */ + hDevice->pUartInfo->hDevice = NULL; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Submit a "filled" buffer for transmitting data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * This function sets up the apropriate interrupts associated with the transaction and marks + * the buffer as submitted. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to data supplied by the API that is to be transmitted. + * @param [in] nBufSize Size of the buffer to be transmitted(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using the DMA flag. + + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for transmission. + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete + * a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_IsTxBufferAvailable() + * @sa adi_uart_GetTxBuffer() + * @sa adi_uart_SubmitRxBuffer() + * + * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode + * and then right away another using the DMA, this transaction will be denied. + * + */ +ADI_UART_RESULT adi_uart_SubmitTxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA + ) +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure we are transmitting. */ + if(ADI_UART_DIR_RECEIVE == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check the data transfer mode (only allowed in nonblocking mode). */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has finished being processed in "adi_uart_GetBuffer()" or "adi_uart_PendForBuffer()". + */ + if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the start address of the data buffer we are going to submit. */ + hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the buffer size to the size of the data buffer passed down from the API. */ + hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to zero because we will start shifting out + the Tx data from the first position of the buffer. + */ + hDevice->pChannelTx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use so no other transactions can use it until this one is complete. */ + hDevice->pChannelTx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer; + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. Then, if a buffer is not currently active, set up the + interrupts for this transaction. Otherwise if a buffer is currently active, + this will be taken care of in the ISR. + */ + if (hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE) + { + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING; + hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer); + } + + return(ADI_UART_SUCCESS); + } + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_SubmitTxBuffer(). It sets up the Tx channel DMA + or device interrupts for the Tx channel to transmit data. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from where data will be transmitted. + * @param [in] nBufSize Size of the buffer containing the data to be transmitted(in bytes). + * @param [in] bDMA Submit the buffer using the DMA. +*/ +static void uart_submittxbuffer( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ) +{ + /* If this transmission is using DMA... */ + if (pBuffer->bDMA) + { + /* Enable clear source address decrement for TX channel DMA. */ + pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum; + + /* Enable Tx channel DMA. */ + pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Enable UART peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Set the primary control data structure as the current DMA descriptor. */ + pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Fill in the DMA RAM descriptors */ + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u)); + + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND = (uint32_t)&hDevice->pUARTRegs->TX; + + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + ((uint32_t)ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE) | + (0u << DMA_BITP_CTL_R_POWER) | + ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + /* Enable UART DMA request interrupt for the Tx channel. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT); + } + else + /* If this transmission is using UART interrupts.. */ + { + /* Enable buffer empty interrupts. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI); + } +} + +/*! \endcond */ + +/*! + * @brief Submit an empty buffer for receiving the data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * This will set up the Rx channel for notification on incoming data using either the DMA + * or UART interrupts, as well as mark the buffer as submitted. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from that will be filled by the driver when data has been received. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using DMA flag. + + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for receiving data. + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete + * a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_IsRxBufferAvailable() + * @sa adi_uart_GetRxBuffer() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode + * and then right away another using the DMA, this transaction will be denied. +*/ +ADI_UART_RESULT adi_uart_SubmitRxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA + ) +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure the UART device is configured to operate in the receive direction. */ + if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode(only allowed in nonblocking mode). */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. If the start address is not set to NULL, then we + can conclude the buffer has not finished being processed because this gets set in + adi_uart_pend_for_buffer() and adi_uart_get_buffer(). + */ + if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the start address of the buffer you are going to submit. */ + hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the size of the buffer. */ + hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to 0, because as we receive data it will be put into + the buffer starting at the first position. + */ + hDevice->pChannelRx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use. */ + hDevice->pChannelRx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer; + + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. Then, if a buffer is not currently active, set up the + interrupts for this transaction. Otherwise if a buffer is currently active, + this will be taken care of in the ISR. + */ + if (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE) + { + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING; + hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer); + } + + return(ADI_UART_SUCCESS); +} + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_SubmitRxBuffer(). It sets up the DMA + * or device receive interrupts for the Rx channel to receive data. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to the empty receive buffer. + * @param [in] nBufSize Size of the receive buffer(in bytes). + * @param [in] bDMA Submit the buffer using the DMA. +*/ +static void uart_submitrxbuffer( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ) +{ + + + /* If this transaction is using the DMA.. */ + if (pBuffer->bDMA) + { + /* Enable source address decrement for RX DMA channel. */ + pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum; + + /* Enable Rx DMA channel. */ + pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Enable UART peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Set the primary data structure as the current DMA descriptor. */ + pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Fill in the DMA RAM descriptors. */ + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND = (uint32_t)&hDevice->pUARTRegs->RX; + + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u)); + + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC = (uint32_t)(ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC) | + (uint32_t)(ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE) | + (0u << DMA_BITP_CTL_R_POWER) | + ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + /* Enable UART receive DMA requests. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR); + } + /* If this transaction is using UART interrupts.. */ + else + { + /* Enable buffer full interrupt. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI); + } +} + +/*! \endcond */ + +/*! + * @brief Transfer buffer ownership from the device back to the API if the data + * transmit has completed. Otherwise it will block until completion. + * This allows a nonblocking call to become blocking. + * This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] ppBuffer Contains the address of the buffer passed down from the API + * for transmitting data. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully returned buffer to the API. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_BUFFER_NOT_SUBMITTED [D] The buffer has not been submitted to the driver. + * + * @sa adi_uart_IsTxBufferAvailable() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: If the transaction has already completed, this will return immediately rather than block. + */ +ADI_UART_RESULT adi_uart_GetTxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError + ) + +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate that this buffer has actually been submitted. */ + if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL) + { + return(ADI_UART_BUFFER_NOT_SUBMITTED); + } + + /* This function is allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Blocking call to get the submitted buffer */ + return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError)); +} + + + +/*! + * @brief Transfer buffer ownership from the device back to the API if the data + * receive has completed. Otherwise it will block until completion. + * This allows a nonblocking call to become blocking. + * This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] ppBuffer Contains the address of the buffer passed down from the API + * for receiving data. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully returned buffer to the API. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_BUFFER_NOT_SUBMITTED [D] The buffer has not been submitted to the driver. + * + * @sa adi_uart_IsRxBufferAvailable() + * @sa adi_uart_SubmitRxBuffer() + * + * @note: If the transaction has already completed, this will return immediately rather than block. +*/ +ADI_UART_RESULT adi_uart_GetRxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError + ) + +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate that this buffer has actually been submitted. */ + if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL) + { + return(ADI_UART_BUFFER_NOT_SUBMITTED); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Blocking call to get the full Rx Buffer */ + return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError)); +} + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_GetRxBuffer() and adi_uart_GetTxBuffer(). + * It blocks until until the completion of the data transaction. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Pointer to UART channel data structure. + * @param [out] ppBuffer Contains the address of the buffer passed down from the API. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully got buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * +*/ +static ADI_UART_RESULT uart_getbuffer( + ADI_UART_HANDLE hDevice, + ADI_UART_DATA_CHANNEL *pChannel, + void **ppBuffer, + uint32_t *pHwError + ) +{ + /* Set ppBuffer to NULL in case there is an error. */ + *ppBuffer = NULL; + + /* Wait until the peripheral has finished processing the buffer. */ + SEM_PEND(pChannel,ADI_UART_FAILED); + + /* Save the address of the buffer that has just been processed, so it can be + returned back to the API. + */ + *ppBuffer = pChannel->pActiveBuffer->pStartAddress; + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + + /* If there are hardware errors and no callback, then return failure. */ + if(hDevice->nHwError != 0u) + { + /* Save the hardware error detected. This will be passed back to the API. */ + *pHwError = hDevice->nHwError; + + /* Clear any hardware errors detected. */ + hDevice->nHwError = 0u; + + return(ADI_UART_HW_ERROR_DETECTED); + } + else + { + return(ADI_UART_SUCCESS); + } +} + +/*! \endcond */ + + +/*! + * @brief Submit the buffer for transmitting the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * Call to this function will not return until the entire buffer is transmitted. + * Returns error if this function is called when device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * i.e Function "adi_uart_SubmitTxBuffer()" is called and the transfer is not yet complete. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to data supplied by the API that is to be transmitted. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using the DMA flag. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully transmitted the data from the submitted buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete + * a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_INVALID_POINTER [D] The pointer to the buffer being submitted is a NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_Read() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: This function is a blocking function which means that the function returns only after the completion of + * buffer transmission. +*/ +ADI_UART_RESULT adi_uart_Write( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure we are transmitting. */ + if(ADI_UART_DIR_RECEIVE == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode (only allowed in blocking mode). */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this transmit operation. "pFreeBuffer" + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has been processed. + */ + if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. */ + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING; + + /* Set the start address of the data buffer we are going to submit. */ + hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the buffer size to the size of the data buffer passed down from the API. */ + hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to zero because we will start shifting out + the Tx data from the first position of the buffer. + */ + hDevice->pChannelTx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use so no other transactions can use it until this one is complete. */ + hDevice->pChannelTx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer; + + hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer); + + /* Block for the active buffer to complete. */ + return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError)); +} + +/*! + * @brief Submit the buffer for reading the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function will not + * return until the entire buffer is filled up. Returns error if this function is called when + * device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. i.e The function "adi_uart_SubmitRxBuffer()" is called + * when the transfer is not yet complete. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from that will be filled by the driver when data has been received. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using DMA flag. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for receiving data. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete + * a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_Write() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: This function is a blocking function which means that the function returns only after the completion of + * data receive. +*/ +ADI_UART_RESULT adi_uart_Read( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure the UART device is configured to operate in the receive direction. */ + if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode(only allowed in blocking mode).*/ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this receive operation. "pFreeBuffer" + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address gets set to NULL once the buffer + processing has completed. + */ + if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. + */ + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING; + + /* Set the start address of the buffer you are going to submit. */ + hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the size of the buffer. */ + hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to 0, because as we receive data it will be put into + the buffer starting at the first position. + */ + hDevice->pChannelRx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use. */ + hDevice->pChannelRx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA; + + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer; + + hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer); + + /* Block for the active buffer to complete. */ + return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError)); +} + +/*! \cond PRIVATE */ + +/* + * @brief Pends for data transaction to complete. Buffer gets returned to API. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Pointer to UART channel data structure. + * @param [out] pBuffer Address of buffer on which data transfer being carried out. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully got buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * +*/ +static ADI_UART_RESULT uart_PendForBuffer( + ADI_UART_HANDLE const hDevice, + ADI_UART_DATA_CHANNEL *pChannel, + uint32_t *pHwError + ) +{ + + /* Wait until the peripheral has finished processing the buffer. */ + SEM_PEND(pChannel,ADI_UART_FAILED); + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. This will only be updated in places where transactions are completed, + such as uart_PendForBuffer() and uart_GetBuffer(). + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + Only if there are no active buffers. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + + /* If there are hardware errors and no callback, then return failure. */ + if(hDevice->nHwError != 0u) + { + /* Save the hardware error detected. This will be passed back to the API. */ + *pHwError = hDevice->nHwError; + + /* Clear any hardware errors detected. */ + hDevice->nHwError = 0u; + + return(ADI_UART_HW_ERROR_DETECTED); + } + else + { + return(ADI_UART_SUCCESS); + } + +} +/*! \endcond */ + + +/*! + * @brief Peek function to know if an empty buffer is avilable. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbAvailable Pointer to a boolean variable. Contains "true" if there is an empty buffer + * and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains + * "false" if there is no empty buffer. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * + * @sa adi_uart_GetTxBuffer() + * @sa adi_uart_IsRxBufferAvailable + * + */ + +ADI_UART_RESULT adi_uart_IsTxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Initialize to "false" in case of an error. */ + *pbAvailable = false; + + /* Make sure the buffer has not already been processed. This would mean that there are + currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is + called once a transaction has completed. + */ + if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL) + { + /* If the buffer has reached the interrupt handler, "bInUse" will be + updated so we know that the buffer has become available. + */ + if (hDevice->pChannelTx->pActiveBuffer->bInUse == false) + { + *pbAvailable = true; + } + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Peek function to know if a filled buffer is available. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbAvailable Pointer to a boolean variable. Contains "true" if there is an empty buffer + * and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains + * "false" if there is no empty buffer. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * + * @sa adi_uart_GetRxBuffer() + * + */ +ADI_UART_RESULT adi_uart_IsRxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Initialize to "false" in case of an error. */ + *pbAvailable = false; + + /* Make sure the buffer has not already been processed. This would mean that there are + currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is + called once a transaction has completed. + */ + if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL) + { + /* If the buffer has reached the interrupt handler, "bInUse" will be + updated so we know that the buffer has become available. + */ + if (hDevice->pChannelRx->pActiveBuffer->bInUse == false) + { + *pbAvailable = true; + } + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Function to let the API know if all the data had been drained from the Tx shift registers. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbComplete Pointer to a boolean variable. Contains "true" if there is no data left in the + * device to transmit and device can be disabled without data loss. Contains "false" + * if the data transmission is not complete. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of data transmission. + * - #ADI_UART_INVALID_HANDLE [D] Specified handle is invalid. + * + * @note adi_uart_getTxBuffer() or the callback may indicate that a transmit transaction is complete when the + * device is using the DMA. This is because the interrupt will trigger once the transmit holding register is empty. + However, there may still be a some data in the shift register. If the transmit channel needs + * to be closed then the application must poll the transmit channel to see if all data has indeed been transmitted before + * shutting down the channel. Otherwise data will be lost. + * + */ + +ADI_UART_RESULT adi_uart_IsTxComplete( + ADI_UART_HANDLE const hDevice, + bool *const pbComplete + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Initialize to false. */ + *pbComplete = false; + + /* If the register is empty, set the return variable to "true". + This register is empty, when the value becomes a 1. + */ + if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT) + { + *pbComplete = true; + } + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Registering a callback function. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pfCallback Function pointer to callback. Passing a NULL pointer will unregister + * the callback function. + * @param [in] pCBParam Callback function parameter. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully registered callback function. + * - #ADI_UART_DEVICE_IN_USE [D] This operation is not allowed when a data transfer is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * + * +*/ +ADI_UART_RESULT adi_uart_RegisterCallback( + ADI_UART_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void *const pCBParam + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Set the device callback. */ + hDevice->pfCallback = pfCallback; + + /* Set the callback parameter. */ + hDevice->pCBParam = pCBParam; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Configuration of UART data. + * + * @details Sets the configuration parameters for the specified UART device such as wordlength, whether to + * enable/disable the parity, and the number of stop bits. This function returns an error if the + * device has active data or autobaud is in progress. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] eParity Specify the type of parity check for the UART device. + * @param [in] eStopBits Specify the stop-bits for the UART device. + * @param [in] eWordLength Specify the word size of the data for the UART device. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the data configuration. + * - #ADI_UART_DEVICE_IN_USE [D] This operation is not allowed when a data transfer or autobaud is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * +*/ +ADI_UART_RESULT adi_uart_SetConfiguration( + ADI_UART_HANDLE const hDevice, + ADI_UART_PARITY const eParity, + ADI_UART_STOPBITS const eStopBits, + ADI_UART_WORDLEN const eWordLength + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Clear all the fields. */ + uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN)); + + /* Construct the configuration word. */ + nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity)); + + /* Write to the register */ + hDevice->pUARTRegs->LCR = nDataCfg; + + /* Return Success */ + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Set baudrate by configuring the fractional dividors. + * + * @details Baudrate is calculated as per below equation. + * + * Baudrate = (UARTCLK / (nDivM + nDivN/2048)*pow(2,nOSR+2)* nDivC)). + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] nDivC Specify the "nDivC" in the above equation. + * @param [in] nDivM Specify the "nDivM" in the above equation. + * @param [in] nDivN Specify the "nDivN" in the above equation. + * @param [in] nOSR Specify the "nOSR" " in the above equation. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the baudrate for the device. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_DEVICE_IN_USE [D] Device is in use + * - #ADI_UART_INVALID_PARAMETER [D] Input for baud rate values are out of range. + * + * @sa adi_uart_GetBaudRate() + * @sa adi_uart_EnableAutobaud(); + * + * @note It is expected that initialization of the power management + * driver is done before calling this function. + * + */ +ADI_UART_RESULT adi_uart_ConfigBaudRate( + ADI_UART_HANDLE const hDevice, + uint16_t const nDivC, + uint8_t const nDivM, + uint16_t const nDivN, + uint8_t const nOSR + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL))) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Check if the given baudrate is valid */ + if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u)) + { + return ADI_UART_INVALID_PARAMETER; + } + +#endif /* ADI_DEBUG */ + + /* Write back the register contents for baudrate detection in the hardware. */ + hDevice->pUARTRegs->DIV = nDivC; + hDevice->pUARTRegs->FBR = (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <pUARTRegs->LCR2 = nOSR; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Get the baudrate of the UART device instance. This is used in the scenario when a callback has not been initialized. + * This allows the the API to know if autobaud is complete. If this returns a baudrate other than 0, + * it indicates that the autobaud completed, otherwise autobaud is still in progress. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pnBaudRate Pointer to a location where baudrate is to be written. + * @param [out] pAutobaudError Pointer to an integer that will hold the value of any baudrate error(s), that correlates with + * #ADI_UART_AUTOBAUD_ERRORS. This will be 0 if there are no errors. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the baudrate. + * - #ADI_UART_AUTOBAUD_ERROR_DETECTED There has been an autobaud error. The API can get the specific error(s) + * by checking "pAutobaudError". + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_INVALID_POINTER [D] The pointer to baudrate or autobaud error is NULL. + + * +*/ +ADI_UART_RESULT adi_uart_GetBaudRate( + ADI_UART_HANDLE const hDevice, + uint32_t *pnBaudRate, + uint32_t *pAutobaudError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate pointers. */ + if(pnBaudRate == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + +#endif /* ADI_DEBUG */ + + /* If an error occured during autobaud this value will be set to a + non-zero value. The specific error can be found by checking against + #ADI_UART_EVENT. + */ + if(hDevice->nAutobaudError != 0u) + { + /* Save the autobaud error to pass back to the API.*/ + *pAutobaudError = hDevice->nAutobaudError; + + /* Clear the autobaud errors found. */ + hDevice->nAutobaudError = 0u; + + return(ADI_UART_AUTOBAUD_ERROR_DETECTED); + } + + /* Return the baudrate. If this is 0, then autobaud has not completed. */ + *pnBaudRate = hDevice->nBaudRate; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Enable/Disable UART autobaud detection as well as configures the device for autobaud detection. + * + * @details The baud rate is detected using the hardware support. + * After the baud rate is detected the interrupt handler is notified of the completion. + * When a callback is not registered with UART driver, the API adi_uart_GetBaudRate() + * can be used to know if autobaud is complete. Autobaud needs to be disabled in order to + * clear the internal counter and to close the device. + * + * @param [in] hDevice Handle to UART device whose autobaud detection to be enabled/disabled. + * @param [in] bEnable Boolean flag to indicate whether to enable or disable the autobaud. + * @param [in] bAutobaudCallbackMode Use a callback to report autobaud errors or type #ADI_UART_AUTOBAUD_ERRORS. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully enabled/disabled Autobaud detection. + * - #ADI_UART_DEVICE_IN_USE [D] Trying to enable/disable Autobaud when + * dataflow is enabled or autobaud is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * + * @sa adi_uart_GetBaudRate() + * + * @note: For autobaud we assume the key character being used is a carrige return (0xD), so the start edge count is + * hardcoded to the second edge (first edge after start edge) and the last edge count is set to the fouth edge. + * This will give us a total bit count of 8 bits that we will time in order to figure out the baud rate (bits/second). + */ +ADI_UART_RESULT adi_uart_EnableAutobaud( + ADI_UART_HANDLE const hDevice, + bool const bEnable, + bool const bAutobaudCallbackMode + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL))) + { + return(ADI_UART_DEVICE_IN_USE); + } + +#endif /* ADI_DEBUG */ + + if(bEnable) + { + /* Enable Autobaud, timeout interrupt and done interrupt in the autobaud control register. + Set the starting edge trigger to the second edge. Set the ending edge count to + the fourth edge, for the carrige return key character (0xD). + */ + hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u)); + + /* Initialize device baudrate to 0. This will be set once autobaud is complete. */ + hDevice->nBaudRate = 0u; + + /* Change the state to indicate autobaud is in progress. */ + hDevice->bAutobaudInProgress = true; + + /* Set the callback mode for autobaud based on the user input. */ + hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode; + } + else + { + /* Change the state to indicate autobaud is not in progress. */ + hDevice->bAutobaudInProgress = false; + + /* Disable Autobaud, timeout interrupt and done interrupt in the autobaud control register. */ + hDevice->pUARTRegs->ACR |= (uint16_t)(~(uint32_t)BITM_UART_ACR_ABE | ~(uint32_t)BITM_UART_ACR_DNIEN | ~(uint32_t)BITM_UART_ACR_TOIEN); + + /* Initialize device baudrate to 0. */ + hDevice->nBaudRate = 0u; + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Forces the UART to send out a break signal. + * + * @details Sets the UART Tx pin to a logic-low/high (depending upon the + * Tx polarity) asynchronously. The UART keeps transmitting break + * until it is disabled to send the break. + * + * @param [in] hDevice Handle to the UART whose Tx is forced to + * send a break. + * @param [in] bEnable Flag which indicates whether to enable or + * disable transmitting the break. + * + * @return Status + * + * - #ADI_UART_SUCCESS If successfully enabled or disabled sending break. + * - #ADI_UART_INVALID_HANDLE [D] If the given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_ForceTxBreak( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(bEnable == true) + { + /* Set the force break bit. */ + hDevice->pUARTRegs->LCR |= BITM_UART_LCR_BRK; + } + else + { + /* Clear the force break bit. */ + hDevice->pUARTRegs->LCR &= (uint16_t)~(BITM_UART_LCR_BRK); + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Enable/Disable the loopback for the specified UART device. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] bEnable Boolean flag to indicate whether to enable or disable the loopback mode. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully enable/disable the loopback. + * - #ADI_UART_INVALID_HANDLE Invalid UART device handle. + * +*/ +ADI_UART_RESULT adi_uart_EnableLoopBack( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(true == bEnable) + { + /* Enable loopback. */ + hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK); + } + else + { + /* Disable loopback. */ + hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK); + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Sets the RX FIFO trigger level. This will be the amount of data in the FIFO + * that will trigger an interrupt. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] eTriglevel Trigger level to be set in terms of number of bytes. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the trigger level. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_TRIG_LEVEL const eTriglevel + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Clear existing FIFO trigger level. */ + hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG; + + /* Set the FIFO trigger level. */ + hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel; + + return(ADI_UART_SUCCESS); +} +/*! + * @brief Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead + * and maximize system efficiency. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] bEnable Boolean flag to indicate whether to enable or disable FIFO. + * + * @return Status + * - #ADI_UART_SUCCESS If successfully enabled FIFO for UART device. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_EnableFifo( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(bEnable == true) + { + /* Enable TX/RX FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_FIFOEN; + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI); + + hDevice->bRxFifoEn = true; + + } + else + { + /* Disable TX/RX FIFO. */ + hDevice->pUARTRegs->FCR &= (uint16_t)~(BITM_UART_FCR_FIFOEN); + + hDevice->bRxFifoEn = false; + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief To flush the TX FIFO. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed TX Fifo. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushTxFifo( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Flush the Tx FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Flush the RX FIFO. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed RX Fifo. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushRxFifo( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Flush RX FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR; + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Flush the Rx channel and disable interrupts. This will stop any buffers in flight and + * clear out any data that was in the RX holding register as well as the Rx fifo. Once this is done, + * in order to turn back on Rx interrupts, a new transaction will need to be started (adi_uart_Read() + * or adi_uart_SubmitRxBuffer()). + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed the Rx channel. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushRxChannel( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Disable receive interrupts in PIO mode as well as DMA mode. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR); + + /* Clear any data in the Rx Fifo. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR; + + /* Reset the buffers to 0. */ + memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong)); + + hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1]; + hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Reset the buffer pointers. */ + hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Dummy read to flush the RX register. */ + hDevice->pUARTRegs->RX; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Flush the Tx channel and disable interrupts.This will stop any buffers in flight and + * clear out any data that was in the TX holding register. Any data in the TX shift register + * will still finish transmitting. + * + * + * @param [in] hDevice Device handle to UART device obtained when an UART device is opened successfully. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed the Tx channel. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE const hDevice) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Disable transmit interrupts in PIO mode as well as DMA mode. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT); + + /* Clear any data in the Rx Fifo. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR; + + /* Reset the buffers to 0. */ + memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong)); + + hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1]; + hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0]; + + /* Reset the buffer pointers. */ + hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0]; + + return(ADI_UART_SUCCESS); +} + + +/*! \cond PRIVATE */ + +void UART0_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + Common_Uart_Interrupt_Handler(hDevice); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART); +#endif + ISR_EPILOG(); + return; +} + +#if defined (__ADUCM4x50__) + +void UART1_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + Common_Uart_Interrupt_Handler(hDevice); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART); +#endif + ISR_EPILOG(); + return; +} +#endif + +static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice) +{ + switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT ) + { + /* Tx buffer empty interrupt. This means that the data has successfully left the holding register and is + now in transmit shift register or has completed its transfer. + */ + case ENUM_UART_IIR_STAT_ETBEI: + uart_TxDataHandler(hDevice); + break; + + /* Rx buffer FIFO timeout interrupt. This means that we have data in the RX FIFO + but there is not enough data to trigger an interrupt so we will process this data here. + */ + case ENUM_UART_IIR_STAT_RFTOI: + uart_RxDataHandler(hDevice); + break; + + /* Rx buffer full interrupt. This means that the RX buffer has finished receiving data. */ + case ENUM_UART_IIR_STAT_ERBFI: + uart_RxDataHandler(hDevice); + break; + + /* Line status interrupt. */ + case ENUM_UART_IIR_STAT_RLSI: + { + /* Initialze the line status event to 0. */ + uint32_t nEvent = 0u; + + /* Get the interrupts status. */ + uint16_t nStatus = hDevice->pUARTRegs->LSR; + + /* If a break signal is detected.. */ + if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI) + { + /* Dummy read to flush the RX register. We do this because + we do not actaully want to do anything with this data as it + is only a break indicator. */ + hDevice->pUARTRegs->RX; + + /* Set the event to a break interrupt. */ + nEvent = (uint32_t)ADI_UART_BREAK_INTERRUPT; + } + + /* Ignore the framing error if the break is asserted. + We do this because a break can trigger a false framing error. + */ + else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE) + { + /* Set the event to show a framing error has been detected. */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_FRAMING; + } + else + { + /* Do nothing. This is required for MISRA. */ + } + + if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE) + { + /* Set the event to show a parity error has been detected. */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_PARITY; + } + if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE) + { + /* Set the event to show a hardware overrun error has been detected, meaning receive data has + been overwritten. + */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_OVERRUN; + } + + /* If there was an event and autobaud is not in progress, notify the API. */ + if((nEvent != 0u) && (hDevice->bAutobaudInProgress == false)) + { + /* Set the UART device hw error bit field. This will allow us to return the + specific failure to the application once we return from this ISR. + */ + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_HW_ERROR_DETECTED); + } + break; + } + + /* If there was a modem status interrupt. For our purposes, we will only check if this is related to autobaud. */ + case ENUM_UART_IIR_STAT_EDSSI: + { +#if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1) + /* Initialize the autobaud event to 0. */ + uint32_t nEvent = 0u; + + /* Get the autobaud interrupt status but not the counter value. */ + uint16_t nStatus = hDevice->pUARTRegs->ASRL & 0xFu; + + /* Read the autobaud control register to see if autobaud was enabled. */ + uint16_t acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE); + + /* If there is an autobaud event and autobaud is enabled */ + if((nStatus != 0u) && (acr != 0u)) + { + uint32_t nClock; + uint32_t nCount; + + /*Get the clock frequency. */ + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK,&nClock) != ADI_PWR_SUCCESS) + { + nClock = 0u; + } + + /* Get the autobaud counter bits 12-19. */ + nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u; + + /* Get the autobaud counter bits 0-11. */ + nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u; + + /* if the autobaud event was that the autobaud is done.. */ + if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE) + { + /* If the fractional baud generator is enabled, calculate the fractional portional of the baudrate. + It seems that in order to get a correct baudrate reading, we need the fractional divider enabled. + */ + if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u) + { + uint8_t nOSR = 0u; + uint32_t nDivN; + uint32_t nDivNSubtractor = 2048u; + + /* DIVC is always 1, unless the oversample rate is 32. */ + uint16_t nDivC = 1u; + + /* If the oversample rate is 4.. */ + if(nCount < (8u << 3u)) + { + nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor; + } + + /* If the oversample rate is 8.. */ + else if(nCount < (8u << 4u)) + { + nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor; + nOSR = 1u; + } + + /* If the oversample rate is 16.. */ + else if(nCount < (8u << 5u)) + { + nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor; + nOSR = 2u; + } + + /* If the oversample rate is 32.. */ + else + { + nDivC = (uint16_t) (nCount / 32u / 8u); + nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor; + nOSR = 3u; + } + + /* Write back the register contents for baudrate detection in the hardware. */ + adi_uart_ConfigBaudRate(hDevice, nDivC, 1u, (uint16_t)nDivN, nOSR); + + /* For more precise calculations we would use floating point math here. Integer precision will do for now. + This avoids bringing in extra libraries for floating point math. */ + + /* Baudrate = (UARTCLK / (nDivM + nDivN / 2048) * pow(2, nOSR + 2) * nDivC) + nOSR = (1u << (nOSR + 2u)); Seperate this out of the equation for misra compliance + hDevice->nBaudRate = ((float)nClock / (((float)1 + (float)nDivN / (float)2048) * (float)nOSR * (float)nDivC)); + */ + + /* In order to avoid bringing in the extra floating point libraries, we will use the non fractional baudrate for the API. */ + hDevice->nBaudRate = ((nClock * 8u) / nCount); + } + else + { + /* No Fractional divider: Baudrate (bits/second) = (UARTCLK (cycles/second) * counted bits (bits)) / nCount (cycles)*/ + hDevice->nBaudRate = ((nClock * 8u) / nCount); + } + + /* If there is a callback, notify the API that autobaud is complete. + If there is not a callback, the baudrate will be set to a non zero value so the user can call "Get_BaudRate" + to know that autobaud has completed. + */ + if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode == true)) + { + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_COMPLETE, (void*)hDevice->nBaudRate); + } + } + else + { + if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO) + { + /* Autobaud timed out due to break error. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK; + } + if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO) + { + /* Autobaud timed out due to no valid start edge found. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE; + } + if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO) + { + /* Autobaud timed out due to no valid end edge found. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE; + } + /* If there is an event callback.. */ + if((hDevice->pfCallback != NULL) && (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)) + { + /* Notify application of errors through callback. */ + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED, (void*)nEvent); + } + else + { + /* Notify application of errors through autobaud return value. */ + hDevice->nAutobaudError = nEvent; + } + + } + + /* Dummy read to flush the RX register to clear the key character that was sent while configuring autobaud. */ + hDevice->pUARTRegs->RX; + } +#endif + /* Clear auto baud enable and interrupt registers. We disable autobaud here because it is required in order to clear the counter. */ + hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE | + BITM_UART_ACR_DNIEN | + BITM_UART_ACR_TOIEN ); + + hDevice->bAutobaudInProgress = false; + break; + } + default: + break; + } + return; +} + + +/* DMA interrupt handlers */ +void DMA_UART0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX); +#endif + ISR_EPILOG(); +} + +void DMA_UART0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX); +#endif + ISR_EPILOG(); +} + +#if defined(__ADUCM4x50__) + +void DMA_UART1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX); +#endif + ISR_EPILOG(); +} + +void DMA_UART1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX); +#endif + ISR_EPILOG(); +} +#endif/*__ADUCM4x50__*/ +/* + * @brief UART interrupt handler for receiving the data in interrupt mode. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * +*/ +static void uart_RxDataHandler(ADI_UART_HANDLE hDevice) +{ + volatile uint8_t *pNextData; + + /* If there is an active buffer.. */ + if((hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == true)) + { + /* Get the address of the buffer we are filling. */ + pNextData = (uint8_t *)hDevice->pChannelRx->pFillBuffer->pStartAddress; + + /* Read data from the RX holding register into the buffer at the indexed location. */ + pNextData[hDevice->pChannelRx->pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX; + + /* Increment the buffer index so we don't overwrite this data in the buffer. */ + hDevice->pChannelRx->pFillBuffer->nIndex++; + + /* If all of the data has been processed, manage the processed data buffer. Otherwise we will + leave everything as is and continue to receive interrupts for the incoming data, until this + buffer has been filled. + */ + if(hDevice->pChannelRx->pFillBuffer->nIndex == hDevice->pChannelRx->pFillBuffer->nCount) + { + uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_RX_BUFFER_PROCESSED); + } + } + /* If we do not have a buffer submitted.. */ + else + { + /* Ask the API for a buffer so we can process this data before having an overflow. + if there is no callback, the API will not be able to submit a buffer in time. + */ + if (hDevice->pfCallback != NULL) + { + hDevice->pfCallback(hDevice->pCBParam, (uint32_t)ADI_UART_EVENT_NO_RX_BUFFER_EVENT, NULL); + } + + /* This check here is in case in the callback the application submitted a buffer. If they did + not then we need to clear the RX register in order to clear this interrupt. + */ + if((hDevice->pChannelRx->pFillBuffer->pStartAddress == NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == false)) + { + hDevice->pUARTRegs->RX; + } + } + + return; +} + +/* + * @brief UART interrupt handler transmitting the data in interrupt mode. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * +*/ +static void uart_TxDataHandler(ADI_UART_HANDLE hDevice) +{ + volatile uint8_t *pNextData; + + /* If there is an active buffer.. */ + if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse == true)) + { + /* Get the start address of the buffer we are transmitting data from. */ + pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress; + + /* Write data to the TX holding register. This will be shifted out at the baud rate by the shift register. */ + hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex]; + + /* Increment the buffer index. */ + hDevice->pChannelTx->pFillBuffer->nIndex++; + + + /* If all of the characters have been transmitted, manage the data buffer. Otherwise we will leave everything + as is and continue to transmit this data until everything is out of the buffer. */ + if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount) + { + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); + } + } + return; +} + + +/* + * @brief Function for managing the processed buffer. This gets called after the receive buffer has been filled + * and when the transmit buffer has been emptied. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Channel handler for the Tx or Rx. + * @param [in] eEvent Indicate the event ID to be passed to registered callback function, if one has been registered. + * +*/ + +static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice,ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent) +{ + + + /* Now that this transaction has completed, this buffer is no longer in use. */ + pChannel->pFillBuffer->bInUse = false; + + pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer; + + if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + { + /* Disable Tx buffer interrupts. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT); + } + else + { + /* Disable Rx buffer interrupts for the DMA. We do not disable receive buffer full interrupts to allow + the use of the RX FIFO. + */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR); + + if (hDevice->bRxFifoEn != true) + { + /* Disable Rx buffer interrupts for PIO mode if the FIFO is not enabled. + */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI); + } + + } + + /* If there is a callback registered, notify the API that a buffer has been processed. Clean up the buffer. */ + if((hDevice->pfCallback != NULL) && (pChannel->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)) + { + uint32_t nEvent = hDevice->nHwError; + hDevice->nHwError = 0u; + + uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress; + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + if(nEvent != 0u) + { + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_HW_ERROR_DETECTED,(void*)nEvent); + + } + else + { + hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, (void*)pBuffer); + } + + } + else + { + /* Post to the blocking function. If we are in blocking mode, this will allow the buffer to be returned to the API. + If we are in nonblocking mode, this will allow adi_uart_GetBuffer() to return immediately so the API can have + control over the buffer again. + */ + + /* Wait until the last bit is gone before POSTing the SEMAPHORE */ + if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + while( ((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) ||(hDevice->pUARTRegs->TFC != 0)) + { + /*waiting until TFC becomes zero */ + } + + SEM_POST(pChannel); + } + + /* If there is another buffer active. The buffer we want to check is "pFillBuffer" because that is the next one that would + be processed. So if it has been submitted, now would be the time to set up the interrupts based on its requirements. + */ + if(pChannel->pFillBuffer->bInUse == true) + { + pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer); + } +} + + +/* + * @brief Initialize the UART instance to the default values specified in "adi_uart_config.h". + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] nDeviceNum UART device number +*/ + +static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum) +{ + + ADI_UART_CONFIG const* pUARTCfg = &gUARTCfg[nDeviceNum]; + + /* Line Control Register. */ + hDevice->pUARTRegs->LCR = pUARTCfg->LCR; + + /* Div-C in Baudrate divider register. */ + hDevice->pUARTRegs->DIV = pUARTCfg->DIV; + + /* Div-M and Div-N in Fractional Baudrate register. */ + hDevice->pUARTRegs->FBR = pUARTCfg->FBR; + + /* Second line control register. */ + hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2; + + /* FIFO control register. */ + hDevice->pUARTRegs->FCR = pUARTCfg->FCR; + + /* Half Duplex Control Register. */ + hDevice->pUARTRegs->RSC = pUARTCfg->RSC; + + /* Interrupt enable register. */ + hDevice->pUARTRegs->IEN = pUARTCfg->IEN; +} + +#ifdef ADI_DEBUG +/* + * @brief Validate the device handle. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * @return Status + * - #ADI_UART_SUCCESS Specified handle is valid. + * - #ADI_UART_INVALID_HANDLE Specified handle is invalid. + * +*/ + +static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice) +{ + uint32_t i; + + + for(i = 0U; i < ADI_UART_NUM_DEVICES; i++) + { + + if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL)) + { + return(ADI_UART_SUCCESS); + } + } + return(ADI_UART_INVALID_HANDLE); +} +#endif /* ADI_DEBUG */ +/*! \endcond */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart_def.h new file mode 100755 index 00000000000..b7e65321475 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart_def.h @@ -0,0 +1,223 @@ +/*! ***************************************************************************** + * @file: adi_uart_def.h + * @brief: UART Device Driver definition for processor + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \cond PRIVATE */ +#ifndef DEF_UART_DEF_H +#define DEF_UART_DEF_H + +/* Macro mapping from ADuCM4x50 to ADuCM302x */ +#if defined(__ADUCM302x__) + +#define INTR_UART0_EVT INTR_UART_EVT +#define UART0_Int_Handler(void) UART_Int_Handler(void) +#define DMA_UART0_TX_Int_Handler(void) DMA_UART_TX_Int_Handler(void) +#define DMA_UART0_RX_Int_Handler(void) DMA_UART_RX_Int_Handler(void) + +#endif /* __ADUCM302x__ */ + +/*! + ***************************************************************************** + * \struct ADI_UART_BUFF_INFO + * Structure for managing the submitted buffers. + *****************************************************************************/ + +typedef struct UART_BUFF_INFO +{ + void *pStartAddress; /*!< Address of buffer passed down to the UART driver. */ + uint32_t nCount; /*!< Size of buffer in bytes. */ + uint32_t nIndex; /*!< Buffer index. */ + bool bInUse; /*!< Buffer in use flag. */ + bool bDMA; /*!< Transaction is using the DMA flag. */ + struct UART_BUFF_INFO *pNextBuffer; /*!< Pointer to the next buffer in the list. */ + + +}ADI_UART_BUFF_INFO; + + +/*! Function pointer typedef for the function which submit the buffer */ +typedef void (*UART_BUFFER_SUBMIT) (ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ); + + +/*! + ***************************************************************************** + * \struct ADI_UART_DATA_CHANNEL + * Structure to manage the data transfer for a given channel. + * One instance of this structure will be created for managing the + * data transfer in each direction. + *****************************************************************************/ + +typedef struct _ADI_UART_DATA_CHANNEL +{ + ADI_UART_BUFF_INFO PingPong[2]; /*!< Ping Pong Buffers. */ + ADI_UART_BUFF_INFO *pFreeBuffer; /*!< Pointer to free buffer (next buffer to submit). */ + ADI_UART_BUFF_INFO *pFillBuffer; /*!< Pointer to the next buffer to be filled. This is needed for + the case where two buffers are "submitted" before a "get" is + called. */ + ADI_UART_BUFF_INFO *pActiveBuffer; /*!< Pointer to active buffer (next buffer waiting for completion).*/ + ADI_UART_TRANSFER_MODE eDataTranferMode; /*!< Data transfer mode. */ + UART_BUFFER_SUBMIT pfSubmitBuffer; /*!< Pointer to a function used for submitting a buffer. */ + SEM_VAR_DECLR + +}ADI_UART_DATA_CHANNEL; + + +/*! + ***************************************************************************** + * \struct ADI_UART_DEVICE_INFO + * Structure for storing basic device information. + *****************************************************************************/ + +typedef struct _ADI_UART_DEVICE_INFO +{ + DMA_CHANn_TypeDef dmaTxChannelNum; /*!< DMA channel ID-Tx. */ + DMA_CHANn_TypeDef dmaRxChannelNum; /*!< DMA channel ID-Rx. */ + IRQn_Type eDMATx; /*!< DMA channel IRQ-Tx. */ + IRQn_Type eDMARx; /*!< DMA channel IRQ-Rx. */ + IRQn_Type eIRQn; /*!< UART interrupt ID. */ + ADI_UART_TypeDef *pUartRegs; /*!< Base address of the UART registers. */ + ADI_UART_HANDLE hDevice; /*!< Handle for the device instance. */ + +}ADI_UART_DEVICE_INFO; + + +/*! + ***************************************************************************** + * \struct ADI_UART_DEVICE + * Structure for managing the UART device. + *****************************************************************************/ + +typedef struct _ADI_UART_DEVICE +{ + ADI_UART_DIRECTION eDirection; /*!< UART operation direction. */ + ADI_UART_DEVICE_INFO *pUartInfo; /*!< Access to device information about the uart instance. */ + volatile ADI_UART_TypeDef *pUARTRegs; /*!< Access to UART Memory Mapped Registers. */ + ADI_CALLBACK pfCallback; /*!< Callback function. */ + void *pCBParam; /*!< Parameter for callback function. */ + bool bAutobaudInProgress; /*!< Autobaud in progress flag. */ + volatile uint32_t nHwError; /*!< Line status error(s). */ + volatile uint32_t nAutobaudError; /*!< Autobaud error(s). */ + ADI_UART_DATA_CHANNEL *pChannelTx; /*!< Tx channel. */ + ADI_UART_DATA_CHANNEL *pChannelRx; /*!< Rx channel. */ + volatile uint32_t nBaudRate; /*!< Baudrate. */ + bool bAutobaudCallbackMode;/*!< Autobaud detection is using callback mode flag. */ + bool bRxFifoEn; /*!< Rx FIFO enabled. Rx buffer full interrupts will remain enabled. */ + +} ADI_UART_DEVICE; + + +/*! + ***************************************************************************** + * \struct ADI_UART_CONFIG + * Structure for initializing the static config. + *****************************************************************************/ + +typedef struct _ADI_UART_CONFIG +{ + uint16_t LCR; /*!< UART_COMLCR Register. */ + + uint16_t DIV; /*!< UART_COMDIV Register. */ + + uint16_t FBR; /*!< UART_COMFBR Register. */ + + uint16_t LCR2; /*!< UART_COMLCR2 Register.*/ + + uint16_t FCR; /*!< UART_COMFCR Register. */ + + uint16_t RSC; /*!< UART_COMRSC Register. */ + + uint16_t IEN; /*!< UART_COMIEN Register .*/ + +} ADI_UART_CONFIG; + + +/****************************************************************************** + * UART Device internal API function prototypes + *****************************************************************************/ + +/* + * UART device initialization helper function. +*/ +static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum); + + +/* + * Data transfer helper functions. +*/ +static void uart_submittxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer); + +static void uart_submitrxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer); + + +/* + * Data management helper functions. +*/ +static ADI_UART_RESULT uart_getbuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, void **ppBuffer, uint32_t *pHwError); + +static ADI_UART_RESULT uart_PendForBuffer(ADI_UART_HANDLE const hDevice , ADI_UART_DATA_CHANNEL *pChannel, uint32_t *pHwError); + +static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent); + +static void uart_TxDataHandler(ADI_UART_HANDLE hDevice); + +static void uart_RxDataHandler(ADI_UART_HANDLE hDevice); + + +/* + * Interrupt Handler. +*/ +static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice); + + +/* + * Handle Validation function +*/ +#ifdef ADI_DEBUG +static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice); +#endif /* ADI_DEBUG */ + +#endif /* end of ifndef DEF_UART_DEF_H */ +/*! \endcond */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/wdt/adi_wdt.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/wdt/adi_wdt.c new file mode 100755 index 00000000000..b2f34894a25 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/wdt/adi_wdt.c @@ -0,0 +1,225 @@ +/*! ***************************************************************************** + * @file adi_wdt.c + * @brief WDT device driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used +* Necessary for stdbool. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type +* This violation appears when deferencing the pointer to the register typedef. No way around this. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm140,Pm143 +#endif /* __ICCARM__ */ + + +/** @addtogroup WDT_Driver WDT Driver + * @{ + * @brief Watchdog Timer (WDT) Driver + * @details The watchdog timer driver allows the user to enable the timer with + * the static configuration parameters, reset the timer, and read the timer + * count. No interface is provided for setting the timer parameters are + * runtime since the WDT may only be configured once for the program lifetime. + * The timer is disabled by default by the ADuCM4x50 boot kernel. + * @note The application must include drivers/wdt/adi_wdt.h to use this driver + */ + +#include +#include +#include +#include +#include + +/*! \cond PRIVATE */ + +/*! Bus synchronization bits that must go low before writing to the CTL or RESET registers */ +#define ADI_WDT_SYNC_BITS ((0x1u << BITP_WDT_STAT_COUNTING) | (0x1u << BITP_WDT_STAT_LOADING) | (0x1u << BITP_WDT_STAT_CLRIRQ)) + +/*! Value that is written to the reset register to kick the dog */ +#define ADI_WDT_CLR_VALUE (0xCCCCu) + +/*! Store the callback locally if we are using interrupt mode */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) +static ADI_CALLBACK gAppCallback; +#endif + +/*! \endcond */ + +/********************************************************************************* + API IMPLEMENTATIONS +*********************************************************************************/ + + +/*! + * @brief WDT Enable + * + * @details Enables/disables the WDT with the paramters supplied in adi_wdt_config.h + * + * @param [in] bEnable : True to turn WDT on, false to turn it off + * + * @param [in] pfCallback : If interrupt mode is enabled, specify application callback function, + * otherwise simply pass NULL for the argument. + * + * @return ADI_WDT_RESULT + * - #ADI_WDT_FAILURE_LOCKED WDT has already been initialized + * - #ADI_WDT_SUCCESS Function call completed successfully + */ +ADI_WDT_RESULT adi_wdt_Enable(bool const bEnable, ADI_CALLBACK const pfCallback) { + /* IF(Device is enabled, application can't modify it) */ + if ((pADI_WDT0->STAT & ((uint16_t) BITM_WDT_STAT_LOCKED)) != ((uint16_t) 0x0u)) { + return ADI_WDT_FAILURE_LOCKED; + } /* ENDIF */ + + /* Setup interrupts if we are in interrupt mode */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) + gAppCallback = pfCallback; + /* IF(We are enabling the WDT) */ + if (bEnable == true) { + NVIC_EnableIRQ (WDT_EXP_IRQn); + /* ELSE (We are disabling the WDT, this might not be necessary, depends on startup config) */ + } else { + NVIC_DisableIRQ(WDT_EXP_IRQn); + } /* ENDIF */ +#endif + + /* WHILE(Bus sync is underway) */ + while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) { + ; + } /* ENDWHILE */ + + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + + pADI_WDT0->LOAD = ADI_WDT_LOAD_VALUE; + + /* IF(Turning the WDT on) */ + if (bEnable == true) { + pADI_WDT0->CTL = (ADI_WDT_CONTROL_TIMER_MODE << BITP_WDT_CTL_MODE) | + (0x1u << BITP_WDT_CTL_EN ) | + (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) | + (ADI_WDT_CONTROL_TIMEOUT_MODE << BITP_WDT_CTL_IRQ ) | + (ADI_WDT_CONTROL_POWER_MODE << 0u ); + /* ELSE(Turning the WDT off) */ + } else { + pADI_WDT0->CTL = (ADI_WDT_CONTROL_TIMER_MODE << BITP_WDT_CTL_MODE) | + (0x0u << BITP_WDT_CTL_EN ) | + (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) | + (ADI_WDT_CONTROL_TIMEOUT_MODE << BITP_WDT_CTL_IRQ ) | + (ADI_WDT_CONTROL_POWER_MODE << 0u ); + } /* ENDIF */ + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_WDT_SUCCESS; +} + +/*! + * @brief WDT Reset + * + * @details Resets the WDT + * + * @return None + */ +void adi_wdt_Kick(void) { + /* WHILE(Bus sync is underway) */ + while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) { + ; + } /* ENDWHILE */ + + /* Kick the dog! */ + pADI_WDT0->RESTART = ADI_WDT_CLR_VALUE; +} + +/*! + * @brief WDT Read Count + * + * @details Read the current WDT count + * + * @param [out] pCurCount : Pointer to memory to read the count into + * + * @return None + */ +void adi_wdt_GetCount(uint16_t * const pCurCount) { + /* Read the count */ + *pCurCount = pADI_WDT0->CCNT; +} + +/*! \cond PRIVATE */ + +/*! + * @brief WDT0 Interrupt Handler + * + * @details Kicks the dog and calls the user supplied callback function + * + * @return None + * + * @note Do not need to explicitly clear the interrupt status, + * kicking the dog performs this action. + */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) +extern void WDog_Tmr_Int_Handler(void); +void WDog_Tmr_Int_Handler(void) { + ISR_PROLOG() + /* Kick the dog */ + adi_wdt_Kick(); + /* IF(Application supplied a callback) */ + if(gAppCallback != NULL) { + /* Call the callback */ + gAppCallback(NULL, 0x0u, NULL); + } /* ENDIF */ + ISR_EPILOG() +} +#endif /* (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) */ + +/*! \endcond */ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint.c new file mode 100755 index 00000000000..76674dead4c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint.c @@ -0,0 +1,413 @@ +/****************************************************************************** + @file: adi_xint.c + @brief: External Interrupt device driver implementation. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "adi_xint_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* Pm140 (rule 10.3): illegal explicit conversion from underlying MISRA type unsigned int to enum +* The typecast is used for efficiency of the code. +* Pm140 (rule 17.4): array indexing shall only be applied to objects defined as an array +* Array indexing is required on the pointer. The memory for gpCallbackTable is passed from application +*/ +#pragma diag_suppress=Pm073,Pm143,Pm140,Pm136,Pm152 +#endif /* __ICCARM__ */ + +static inline void XIntCommonInterruptHandler (const ADI_XINT_EVENT eEvent); +void Ext_Int0_Handler(void); +void Ext_Int1_Handler(void); +void Ext_Int2_Handler(void); +void Ext_Int3_Handler(void); + + + +/*========== D A T A ==========*/ + +static ADI_XINT_CALLBACK_INFO *gpCallbackTable; + +/*! \endcond */ + +/*! \addtogroup XINT_Driver External Interrupt Driver + * @{ + * @brief External Interrupt (XINT) Driver + * @note The application must include drivers/xint/adi_xint.h to use this driver + */ + +/*! + @brief Initializes the External Interrupt Driver. + + @details This function does the external interrupt driver initialization. This function should be called + before calling any of the XINT driver APIs. + + @param[in] pMemory Pointer to the memory to be used by the driver. + Size of the memory should be at equal to #ADI_XINT_MEMORY_SIZE bytes. + @param[in] MemorySize Size of the memory passed in pMemory parameter. + + @return Status + - ADI_XINT_SUCCESS If successfully initialized XINT driver. + - ADI_XINT_NULL_PARAMETER [D] If the given pointer to the driver memory is pointing to NULL. + - ADI_XINT_INVALID_MEMORY_SIZE [D] If the given memory size is not sufficient to operate the driver. + + @sa adi_xint_UnInit +*/ +ADI_XINT_RESULT adi_xint_Init(void* const pMemory, + uint32_t const MemorySize +) +{ + +#ifdef ADI_DEBUG + /* Verify the given memory pointer */ + if(NULL == pMemory) + { + return ADI_XINT_NULL_PARAMETER; + } + /* Check if the memory size is sufficient to operate the driver */ + if(MemorySize < ADI_XINT_MEMORY_SIZE) + { + return ADI_XINT_INVALID_MEMORY_SIZE; + } + assert(MemorySize == (sizeof(ADI_XINT_CALLBACK_INFO) * ADI_XINT_EVENT_MAX)); +#endif + + /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */ + if (gpCallbackTable == NULL) + { + /* Clear the memory passed by the application */ + memset(pMemory, 0, MemorySize); + + gpCallbackTable = (ADI_XINT_CALLBACK_INFO *)pMemory; + } + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Un-initialize the external interrupt driver. + + @details Terminates the XINT functions, leaving everything unchanged. + + @return Status + - #ADI_XINT_SUCCESS If successfully uninitialized XINT driver. + - #ADI_XINT_NOT_INITIALIZED [D] If XINT driver not yet initialized. + + @sa adi_xint_Init +*/ +ADI_XINT_RESULT adi_xint_UnInit(void) +{ + +#ifdef ADI_DEBUG + /* IF (not initialized) */ + if (NULL == gpCallbackTable) + { + /* return error if not initialized */ + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* Clear the callback pointer */ + gpCallbackTable = NULL; + + return (ADI_XINT_SUCCESS); +} + + + +/*! + @brief Enable an External Interrupt + + @details Enables and sets the triggering mode for the given external interrupt. + Applications may register a callback using the #adi_xint_RegisterCallback + API to get a notification when the interrupt occurs. + + To get the external interrupt working application has to enable the input + (using the GPIO driver API \a adi_gpio_InputEnable) for the corresponding GPIO + pin. Please refer the GPIO chapter pin-muxing section of the Hardware Reference + Manual to see the GPIO pin that is mapped to the required external interrupt. + + @param[in] eEvent Event which needs to be enabled. + @param[in] eMode Interrupt trigger mode for the external interrupt. + + @return Status + - #ADI_XINT_SUCCESS If successfully enabled the external interrupt. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver not yet initialized. + + @sa adi_xint_DisableIRQ + @sa adi_xint_RegisterCallback +*/ +ADI_XINT_RESULT adi_xint_EnableIRQ(const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode) +{ + uint32_t Mask; /* mask to manipulate the register */ + uint32_t Pattern; /* bit pattern that will be written into the register */ + uint32_t CfgReg; /* interrupt config register value */ + IRQn_Type XintIrq; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* create the mask we'll use to clear the relevant bits in the config register */ + Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + /* The Pattern has to be created differently for UART RX wakeup and other events as the + mode and enable bits are flipped in case of UART RX */ + + /* Based on the event figure out the interrupt it is mapped to */ + if(eEvent == ADI_XINT_EVENT_UART_RX) + { + /* create the bit pattern we're going to write into the configuration register */ + Pattern = (BITM_XINT_CFG0_UART_RX_EN | ((uint32_t)eMode << BITP_XINT_CFG0_UART_RX_MDE)); + + XintIrq = XINT_EVT3_IRQn; + } + else + { + /* create the bit pattern we're going to write into the configuration register */ + Pattern = (BITM_XINT_CFG0_IRQ0EN | eMode) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent); + } + + + ADI_ENTER_CRITICAL_REGION(); + + /* read/modify/write the appropriate bits in the register */ + CfgReg = pADI_XINT0->CFG0; + CfgReg &= ~Mask; + CfgReg |= Pattern; + pADI_XINT0->CFG0 = CfgReg; + + ADI_EXIT_CRITICAL_REGION(); + + /* enable the interrupt */ + NVIC_EnableIRQ(XintIrq); + + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Disable an External Interrupt + + @details Disables an external interrupt + + @param[in] eEvent External Interrupt event that should be disabled. + + @return Status + - #ADI_XINT_SUCCESS If successfully disabled the external interrupt. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized. + + @sa adi_xint_EnableIRQ + @sa adi_xint_RegisterCallback +*/ +ADI_XINT_RESULT adi_xint_DisableIRQ(const ADI_XINT_EVENT eEvent) +{ + uint32_t Mask; /* mask to manipulate the register */ + uint32_t CfgReg; /* interrupt config register value */ + IRQn_Type XintIrq; /* External interrupt IRQ the event is mapped to */ + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* Based on the event figure out the interrupt it is mapped to */ + if(eEvent == ADI_XINT_EVENT_UART_RX) + { + XintIrq = XINT_EVT3_IRQn; + } + else + { + XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent); + } + + /* disable the interrupt */ + NVIC_DisableIRQ(XintIrq); + + /* create the mask we'll use to clear the relevant bits in the config register */ + Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + ADI_ENTER_CRITICAL_REGION(); + /* read/modify/write the appropriate bits in the register */ + CfgReg = pADI_XINT0->CFG0; + CfgReg &= ~Mask; + pADI_XINT0->CFG0 = CfgReg; + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Register or unregister an application callback function for external pin interrupts. + + @details Applications may register a callback function that will be called when an + external interrupt occurs. In addition to registering the interrupt, + the application should call the #adi_xint_EnableIRQ API to enable the + external pin interrupt. + + The driver dispatches calls to registered callback functions when the + properly configured pin(s) latches an external interrupt input on the XINT + pin(s). The callback is dispatched with the following parameters, respectively: + + - application-provided callback parameter (\a pCBParam), + - the interrupt ID (#ADI_XINT_EVENT) that initiated the interrupt, + - NULL. + + @param[in] eEvent The interrupt for which the callback is being registered. + @param[in] pfCallback Pointer to the callback function. This can be passed as NULL to + unregister the callback. + @param[in] pCBParam Callback parameter which will be passed back to the application + when the callback is called.. + + @return Status + - #ADI_XINT_SUCCESS If successfully registered the callback. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized. + + @sa adi_xint_EnableIRQ + @sa adi_xint_DisableIRQ +*/ +ADI_XINT_RESULT adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + gpCallbackTable[eEvent].pfCallback = pfCallback; + gpCallbackTable[eEvent].pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + /* return the status */ + return (ADI_XINT_SUCCESS); +} + +/*@}*/ + +/*! \cond PRIVATE */ +/* All of the following is excluded from the doxygen output... */ + +/* Common external interrupt handler */ +static inline void XIntCommonInterruptHandler(const ADI_XINT_EVENT eEvent) +{ + /* Clear the IRQ */ + pADI_XINT0->CLR = (1u << (uint32_t)eEvent); + + /* params list is: application-registered cbParam, Event ID, and NULL */ + if(gpCallbackTable[eEvent].pfCallback != NULL) + { + gpCallbackTable[eEvent].pfCallback (gpCallbackTable[eEvent].pCBParam, (uint32_t) eEvent, NULL); + } +} + +/* strongly-bound interrupt handlers to override the default weak bindings */ +void Ext_Int0_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT0); + ISR_EPILOG() +} + +void Ext_Int1_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT1); + ISR_EPILOG() +} + +void Ext_Int2_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT2); + ISR_EPILOG() + +} + +void Ext_Int3_Handler(void) +{ + ISR_PROLOG() + if((pADI_XINT0->EXT_STAT & BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)==BITM_XINT_EXT_STAT_STAT_UART_RXWKUP) + { + XIntCommonInterruptHandler(ADI_XINT_EVENT_UART_RX); + } + else + { + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT3); + } + ISR_EPILOG() +} + +/*! \endcond */ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint_def.h new file mode 100755 index 00000000000..205602215cd --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/xint/adi_xint_def.h @@ -0,0 +1,61 @@ +/*! + ***************************************************************************** + * @file: adi_xint_def.h + * @brief: External Interrupt Driver definition + ***************************************************************************** +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_XINT_DEF_H +#define ADI_XINT_DEF_H +/*! \cond PRIVATE */ + +/* General macros */ +#define ADI_XINT_CFG_BITS (4u) /*!< number of bits for each external interrupt configuration */ + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_XINT_CALLBACK_INFO +{ + ADI_CALLBACK pfCallback; /*!< Callback function pointer */ + void *pCBParam; /*!< Callback parameter */ +} ADI_XINT_CALLBACK_INFO; + + +/*! \endcond */ +#endif /* ADI_XINT_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h new file mode 100755 index 00000000000..c1cfd6c14ae --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PeripheralNames.h @@ -0,0 +1,136 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = 0, + UART_1 = 1, + UART_2 = 2, + UART_3 = 3, + UART_4 = 4, +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_0 = 0, + I2C_1 = 1, + I2C_2 = 2, +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + // could be 4 or could be 3... not sure what register + // this is for... too much abstraction + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +typedef enum { + ADC0_VIN0 = 0, + ADC0_VIN1 = 1, + ADC0_VIN2 = 2, + ADC0_VIN3 = 3, + ADC0_VIN4 = 4, + ADC0_VIN5 = 5, + ADC0_VIN6 = 6, + ADC0_VIN7 = 7 +} ADCName; + +typedef enum { + DAC_0 = 0 +} DACName; + + +typedef enum { + SPI_0 = 0, + SPI_1 = 1, + SPI_2 = 2, +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h new file mode 100755 index 00000000000..3192608f780 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/PinNames.h @@ -0,0 +1,221 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +/* + The ADuCM4050 is made in two package variants. + + 64 lead LFCSP & 72 ball WLCSP + + There are some differences for Port 2 between the two variants + WLCSP also has Port 3. + + The #define ADUCM4050_LFCSP is used to determine which variant the code + is built for. + + For LFCSP leave the #define in, to build for ADUCM4050_WLCSP remove. +*/ +#define ADUCM4050_LFCSP + +#include "cmsis.h" + +#include "adi_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +//update + +#define GPIO_PORT_SHIFT 12 + + +typedef enum { + P0_00 = (0 << GPIO_PORT_SHIFT | 0 ), + P0_01 = (0 << GPIO_PORT_SHIFT | 1 ), + P0_02 = (0 << GPIO_PORT_SHIFT | 2 ), + P0_03 = (0 << GPIO_PORT_SHIFT | 3 ), + P0_04 = (0 << GPIO_PORT_SHIFT | 4 ), + P0_05 = (0 << GPIO_PORT_SHIFT | 5 ), + P0_06 = (0 << GPIO_PORT_SHIFT | 6 ), + P0_07 = (0 << GPIO_PORT_SHIFT | 7 ), + P0_08 = (0 << GPIO_PORT_SHIFT | 8 ), + P0_09 = (0 << GPIO_PORT_SHIFT | 9 ), + P0_10 = (0 << GPIO_PORT_SHIFT | 10), + P0_11 = (0 << GPIO_PORT_SHIFT | 11), + P0_12 = (0 << GPIO_PORT_SHIFT | 12), + P0_13 = (0 << GPIO_PORT_SHIFT | 13), + P0_14 = (0 << GPIO_PORT_SHIFT | 14), + P0_15 = (0 << GPIO_PORT_SHIFT | 15), + P1_00 = (1 << GPIO_PORT_SHIFT | 0 ), + P1_01 = (1 << GPIO_PORT_SHIFT | 1 ), + P1_02 = (1 << GPIO_PORT_SHIFT | 2 ), + P1_03 = (1 << GPIO_PORT_SHIFT | 3 ), + P1_04 = (1 << GPIO_PORT_SHIFT | 4 ), + P1_05 = (1 << GPIO_PORT_SHIFT | 5 ), + P1_06 = (1 << GPIO_PORT_SHIFT | 6 ), + P1_07 = (1 << GPIO_PORT_SHIFT | 7 ), + P1_08 = (1 << GPIO_PORT_SHIFT | 8 ), + P1_09 = (1 << GPIO_PORT_SHIFT | 9 ), + P1_10 = (1 << GPIO_PORT_SHIFT | 10), + P1_11 = (1 << GPIO_PORT_SHIFT | 11), + P1_12 = (1 << GPIO_PORT_SHIFT | 12), + P1_13 = (1 << GPIO_PORT_SHIFT | 13), + P1_14 = (1 << GPIO_PORT_SHIFT | 14), + P1_15 = (1 << GPIO_PORT_SHIFT | 15), + P2_00 = (2 << GPIO_PORT_SHIFT | 0 ), + P2_01 = (2 << GPIO_PORT_SHIFT | 1 ), + P2_02 = (2 << GPIO_PORT_SHIFT | 2 ), + P2_03 = (2 << GPIO_PORT_SHIFT | 3 ), + P2_04 = (2 << GPIO_PORT_SHIFT | 4 ), + P2_05 = (2 << GPIO_PORT_SHIFT | 5 ), + P2_06 = (2 << GPIO_PORT_SHIFT | 6 ), + P2_07 = (2 << GPIO_PORT_SHIFT | 7 ), + P2_08 = (2 << GPIO_PORT_SHIFT | 8 ), + P2_09 = (2 << GPIO_PORT_SHIFT | 9 ), + P2_10 = (2 << GPIO_PORT_SHIFT | 10), + P2_11 = (2 << GPIO_PORT_SHIFT | 11), + + // USB Pins + USBTX = P0_10, + USBRX = P0_11, + USBTX1 = P1_15, + USBRX1 = P2_00, + + // mbed original LED naming + LED1 = P2_02, + LED2 = P2_10, + LED3 = LED2, + LED4 = LED1, + + //Push buttons + PB0 = P1_00, // BTN1 + PB1 = P0_09, // BTN2 + BOOT = P1_01, + WAKE0 = P0_15, // JP15 to select + WAKE1 = P1_00, // JP8 (BTN1 jumper) to select + WAKE2 = P0_13, // JP4 to select + WAKE3 = P2_01, // JP15 to select + + // SPI Pins + SPI0_SCLK = P0_00, + SPI0_MOSI = P0_01, + SPI0_MISO = P0_02, + SPI0_CS0 = P0_03, + SPI0_CS1 = P1_10, + SPI0_CS2 = P2_08, + SPI0_CS3 = P2_09, + + SPI1_SCLK = P1_06, + SPI1_MOSI = P1_07, + SPI1_MISO = P1_08, + SPI1_CS0 = P1_09, + SPI1_CS1 = P2_11, + SPI1_CS2 = P2_02, + SPI1_CS3 = P1_10, + + SPI2_SCLK = P1_02, + SPI2_MOSI = P1_03, + SPI2_MISO = P1_04, + SPI2_CS0 = P1_05, + SPI2_CS1 = P0_09, + SPI2_CS2 = P2_10, + SPI2_CS3 = P2_07, + + // ADC Pins + ADC_VIN0 = P2_03, + ADC_VIN1 = P2_04, + ADC_VIN2 = P2_05, + ADC_VIN3 = P2_06, + ADC_VIN4 = P2_07, + ADC_VIN5 = P2_08, + ADC_VIN6 = P2_09, + ADC_VIN7 = P2_10, + + // Arduino Headers + D0 = P0_10, // UART0_TXD + D1 = P0_11, // UART0_RXD + D2 = P0_15, // INT_WAKE0 + D3 = P0_13, // EXT_INT_WAKE2 + D4 = P0_09, // EXT_SPI2_CS1 + D5 = P2_01, // INT_WAKE3 or EXT_RTC1_SS1 via JP8 + D6 = P1_11, // GPIO_27 + D7 = P0_12, // GPIO_08 or GPIO_12 via JP7 + + D8 = P1_12, // GPIO_28 + D9 = P1_14, // GPIO_30 + D10 = SPI0_CS2, // P2_08 + D11 = SPI0_MOSI, // P0_01 + D12 = SPI0_MISO, // P0_02 + D13 = SPI0_SCLK, // P0_00 + I2C_SCL = P0_04, // I2C_SCL + I2C_SDA = P0_05, // I2C_SDA + + A0 = P2_03, // ADC0 + A1 = P2_04, // EXT_ADC1 + A2 = P2_05, // EXT_ADC2 + A3 = P2_06, // ADC3 + A4 = P2_07, // SPI2_CS3 + A5 = P2_10, // EXT_GPIO42 + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullNone +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c new file mode 100755 index 00000000000..f88ee01be89 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c @@ -0,0 +1,274 @@ +/*! + ***************************************************************************** + * @file: startup_ADuCM4050.c + * @brief: Interrupt table and default handlers for ADuCM4x50 + * @version: $Revision: $ + * @date: $Date: $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#ifdef __CC_ARM +#include +#include +#endif +#include +#include +#include + +/*---------------------------------------------------------------------------- + Checksum options + *----------------------------------------------------------------------------*/ +#if defined (__CC_ARM) +__attribute__ ((at(0x000001A0u))) +#elif defined(__ICCARM__) +__root +#endif +const uint32_t SECTION_PLACE(blank_checksum[],".checksum") = +{ + BLANKX60,BLANKX600 +}; + + +/*---------------------------------------------------------------------------- + External function Declaration + *----------------------------------------------------------------------------*/ +extern void SramInit(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +WEAK_FUNCTION( NMI_Handler ) +WEAK_FUNCTION( HardFault_Handler ) +WEAK_FUNCTION( MemManage_Handler ) +WEAK_FUNCTION( BusFault_Handler ) +WEAK_FUNCTION( UsageFault_Handler ) +WEAK_FUNCTION( SVC_Handler ) +WEAK_FUNCTION( DebugMon_Handler ) +WEAK_FUNCTION( PendSV_Handler ) +WEAK_FUNCTION( SysTick_Handler ) +WEAK_FUNCTION( RTC1_Int_Handler ) +WEAK_FUNCTION( Ext_Int0_Handler ) +WEAK_FUNCTION( Ext_Int1_Handler ) +WEAK_FUNCTION( Ext_Int2_Handler ) +WEAK_FUNCTION( Ext_Int3_Handler ) +WEAK_FUNCTION( WDog_Tmr_Int_Handler ) +WEAK_FUNCTION( Vreg_over_Int_Handler ) +WEAK_FUNCTION( Battery_Voltage_Int_Handler) +WEAK_FUNCTION( RTC0_Int_Handler ) +WEAK_FUNCTION( GPIO_A_Int_Handler ) +WEAK_FUNCTION( GPIO_B_Int_Handler ) +WEAK_FUNCTION( GP_Tmr0_Int_Handler ) +WEAK_FUNCTION( GP_Tmr1_Int_Handler ) +WEAK_FUNCTION( Flash0_Int_Handler ) +WEAK_FUNCTION( UART0_Int_Handler ) +WEAK_FUNCTION( SPI0_Int_Handler ) +WEAK_FUNCTION( SPI2_Int_Handler ) +WEAK_FUNCTION( I2C0_Slave_Int_Handler ) +WEAK_FUNCTION( I2C0_Master_Int_Handler ) +WEAK_FUNCTION( DMA_Err_Int_Handler ) +WEAK_FUNCTION( DMA_SPIH_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPIH_RX_Int_Handler ) +WEAK_FUNCTION( DMA_SPORT0A_Int_Handler ) +WEAK_FUNCTION( DMA_SPORT0B_Int_Handler ) +WEAK_FUNCTION( DMA_SPI0_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI0_RX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI1_TX_Int_Handler ) +WEAK_FUNCTION( DMA_SPI1_RX_Int_Handler ) +WEAK_FUNCTION( DMA_UART0_TX_Int_Handler ) +WEAK_FUNCTION( DMA_UART0_RX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_STX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_SRX_Int_Handler ) +WEAK_FUNCTION( DMA_I2C0_MX_Int_Handler ) +WEAK_FUNCTION( DMA_AES0_IN_Int_Handler ) +WEAK_FUNCTION( DMA_AES0_OUT_Int_Handler ) +WEAK_FUNCTION( DMA_FLASH0_Int_Handler ) +WEAK_FUNCTION( SPORT0A_Int_Handler ) +WEAK_FUNCTION( SPORT0B_Int_Handler ) +WEAK_FUNCTION( Crypto_Int_Handler ) +WEAK_FUNCTION( DMA_ADC0_Int_Handler ) +WEAK_FUNCTION( GP_Tmr2_Int_Handler ) +WEAK_FUNCTION( Crystal_osc_Int_Handler ) +WEAK_FUNCTION( SPI1_Int_Handler ) +WEAK_FUNCTION( PLL_Int_Handler ) +WEAK_FUNCTION( RNG_Int_Handler ) +WEAK_FUNCTION( Beep_Int_Handler ) +WEAK_FUNCTION( ADC0_Int_Handler ) +WEAK_FUNCTION( DMA_SIP0_Int_Handler ) +WEAK_FUNCTION( DMA_SIP1_Int_Handler ) +WEAK_FUNCTION( DMA_SIP2_Int_Handler ) +WEAK_FUNCTION( DMA_SIP3_Int_Handler ) +WEAK_FUNCTION( DMA_SIP4_Int_Handler ) +WEAK_FUNCTION( DMA_SIP5_Int_Handler ) +WEAK_FUNCTION( DMA_SIP6_Int_Handler ) +WEAK_FUNCTION( DMA_SIP7_Int_Handler ) +WEAK_FUNCTION( UART1_Int_Handler ) +WEAK_FUNCTION( DMA_UART1_TX_Int_Handler ) +WEAK_FUNCTION( DMA_UART1_RX_Int_Handler ) +WEAK_FUNCTION( RGB_Tmr_Int_Handler ) +WEAK_FUNCTION( Root_Clk_Err_Handler ) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +const pFunc SECTION_PLACE(IVT_NAME[104],VECTOR_SECTION) = { + (pFunc) INITIAL_SP, /* Initial Stack Pointer */ + ADUCM4050_VECTORS +}; + +/*---------------------------------------------------------------------------- +* Initialize .bss and .data for GNU +*----------------------------------------------------------------------------*/ +#if defined( __GNUC__) && !defined (__CC_ARM) +void zero_bss(void) +{ + uint32_t *pSrc, *pDest; + uint32_t *pTable __attribute__((unused)); +#ifdef __STARTUP_COPY_MULTIPLE + /* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + pTable = &__copy_table_start__; + + for (; pTable < &__copy_table_end__; pTable = pTable + 3) { + pSrc = (uint32_t*)*(pTable + 0); + pDest = (uint32_t*)*(pTable + 1); + for (; pDest < (uint32_t*)(*(pTable + 1) + *(pTable + 2)) ; ) { + *pDest++ = *pSrc++; + } + } +#else + /* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + pSrc = &__etext; + pDest = &__data_start__; + + for ( ; pDest < &__data_end__ ; ) { + *pDest++ = *pSrc++; + } +#endif /*__STARTUP_COPY_MULTIPLE */ + + /* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE + /* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + pTable = &__zero_table_start__; + + for (; pTable < &__zero_table_end__; pTable = pTable + 2) { + pDest = (uint32_t*)*(pTable + 0); + for (; pDest < (uint32_t*)(*(pTable + 0) + *(pTable + 1)) ; ) { + *pDest++ = 0; + } + } +#elif defined (__STARTUP_CLEAR_BSS) + /* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + pDest = &__bss_start__; + + for ( ; pDest < &__bss_end__ ; ) { + *pDest++ = 0ul; + } +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ +} +#endif + +/*---------------------------------------------------------------------------- +* Function : Reset_Handler (-15) +* Description : Reset event handler +*----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + /* Initialize SRAM configuration. */ + SramInit(); + +#if defined(__GNUC__) && !defined (__CC_ARM) + zero_bss(); +#endif + + /* Setup system. */ + SystemInit(); + + /* Call remaining startup code and then main. */ + RESET_EXCPT_HNDLR(); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +#if defined(__CC_ARM) || defined (__GNUC__) +void Default_Handler(void) +{ + while(1); +} +#endif + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h new file mode 100755 index 00000000000..98da5428c3a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h @@ -0,0 +1,236 @@ +/*! +***************************************************************************** + * @file: startup_ADuCM4050.h + * @brief: CMSIS Cortex-M4 Core Peripheral Access Layer Header File for + * ADI ADuCxxx Device Series + * @version: $Revision: $ + * @date: $Date: $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2017 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/* +WEAK_FUNC(func) + If this is available for a compiler, apply whatever attributes are needed + to a function definition ("func") to flag that the function is a "weak" one. +VECTOR_SECTION + A particular setup may have a requirement that the vector table be placed + in a particular section. This specifies the name of that section +RESET_EXCPT_HNDLR + A particular setup may have a requirement for a different reset handler. + This specifies the name of that handler. +*/ + +#ifndef __STARTUP_H__ +#define __STARTUP_H__ + +#include +#define VECTOR_SECTION ".vectors" +#ifdef __CC_ARM +extern unsigned Image$$ADUCM_HEAP$$Base[]; +extern unsigned Image$$ADUCM_HEAP$$ZI$$Limit[]; +void Default_Handler(void); +#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define IVT_NAME __Vectors +#define RESET_EXCPT_HNDLR __main +#define COMPILER_NAME "ARMCC" +#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#elif defined(__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions: +* +* Pm093 (rule 18.4): use of union - overlapping storage shall not be used. +* Required for interrupt vector table entries. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm093,Pm140 +#define SECTION_PLACE(def,sectionname) def @ sectionname +#define SECTION_NAME(sectionname) def @ sectionname +#define IVT_NAME __vector_table +#define WEAK_FUNC(func) __weak func +#define RESET_EXCPT_HNDLR __iar_program_start +#define COMPILER_NAME "ICCARM" +#define WEAK_FUNCTION(x) WEAK_FUNC ( void x (void)) { while(1){} } +#elif defined(__GNUC__) +extern unsigned __etext; +extern unsigned __data_start__; +extern unsigned __data_end__; +extern unsigned __copy_table_start__; +extern unsigned __copy_table_end__; +extern unsigned __zero_table_start__; +extern unsigned __zero_table_end__; +extern unsigned __bss_start__; +extern unsigned __bss_end__; +extern unsigned __StackTop; +void Default_Handler(void); +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +#ifndef __START +extern void _start(void) __attribute__((noreturn)); /* PreeMain (C library entry point) */ +#define RESET_EXCPT_HNDLR _start +#else +extern int __START(void) __attribute__((noreturn)); /* main entry point */ +#define RESET_EXCPT_HNDLR __START +#endif +#ifndef __STACK_SIZE +#define __STACK_SIZE 0x00000400 +#endif +#if !defined(__HEAP_SIZE) || (__HEAP_SIZE <= 0) +#define __HEAP_SIZE 0x00000C00 +#endif +#define SECTION_NAME(sectionname) __attribute__ ((section(sectionname))) +#define SECTION_PLACE(def,sectionname) def __attribute__ ((section(sectionname))) +#define IVT_NAME __Vectors +#define COMPILER_NAME "GNUC" +#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler"))); +#define __STARTUP_CLEAR_BSS_MULTIPLE +#endif // __GNUC__ +#define LASTCRCPAGE 0 +#define BLANKX4 0xFFFFFFFF +#define BLANKX20 BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4 +#define BLANKX100 BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20,BLANKX20 +#define BLANKX600 BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100,BLANKX100 +#define BLANKX60 BLANKX20,BLANKX20,BLANKX20 +void RESET_EXCPT_HNDLR(void); +void Reset_Handler(void); +/* IVT typedefs. */ +typedef void( *pFunc )( void ); + +#define ADUCM4050_VECTORS \ + /* Configure Initial Stack Pointer, using linker-generated symbols */\ + Reset_Handler, /* -15 */ \ + NMI_Handler, /* -14 */ \ + HardFault_Handler, /* -13 */ \ + MemManage_Handler, /* -12 */ \ + BusFault_Handler, /* -11 */ \ + UsageFault_Handler, /* -10 */ \ + 0, /* -9 */ \ + 0, /* -8 */ \ + 0, /* -7 */ \ + 0, /* -6 */ \ + SVC_Handler, /* -5 */ \ + DebugMon_Handler, /* -4 */ \ + 0, /* -3 */ \ + PendSV_Handler, /* -2 */ \ + SysTick_Handler, /* -1 */ \ + /* External interrupts */ \ + RTC1_Int_Handler, /* 0 */ \ + Ext_Int0_Handler, /* 1 */ \ + Ext_Int1_Handler, /* 2 */ \ + Ext_Int2_Handler, /* 3 */ \ + Ext_Int3_Handler, /* 4 */ \ + WDog_Tmr_Int_Handler, /* 5 */ \ + Vreg_over_Int_Handler, /* 6 */ \ + Battery_Voltage_Int_Handler, /* 7 */ \ + RTC0_Int_Handler, /* 8 */ \ + GPIO_A_Int_Handler, /* 9 */ \ + GPIO_B_Int_Handler, /* 10 */ \ + GP_Tmr0_Int_Handler, /* 11 */ \ + GP_Tmr1_Int_Handler, /* 12 */ \ + Flash0_Int_Handler, /* 13 */ \ + UART0_Int_Handler, /* 14 */ \ + SPI0_Int_Handler, /* 15 */ \ + SPI2_Int_Handler, /* 16 */ \ + I2C0_Slave_Int_Handler, /* 17 */ \ + I2C0_Master_Int_Handler, /* 18 */ \ + DMA_Err_Int_Handler, /* 19 */ \ + DMA_SPIH_TX_Int_Handler, /* 20 */ \ + DMA_SPIH_RX_Int_Handler, /* 21 */ \ + DMA_SPORT0A_Int_Handler, /* 22 */ \ + DMA_SPORT0B_Int_Handler, /* 23 */ \ + DMA_SPI0_TX_Int_Handler, /* 24 */ \ + DMA_SPI0_RX_Int_Handler, /* 25 */ \ + DMA_SPI1_TX_Int_Handler, /* 26 */ \ + DMA_SPI1_RX_Int_Handler, /* 27 */ \ + DMA_UART0_TX_Int_Handler, /* 28 */ \ + DMA_UART0_RX_Int_Handler, /* 29 */ \ + DMA_I2C0_STX_Int_Handler, /* 30 */ \ + DMA_I2C0_SRX_Int_Handler, /* 31 */ \ + DMA_I2C0_MX_Int_Handler, /* 32 */ \ + DMA_AES0_IN_Int_Handler, /* 33 */ \ + DMA_AES0_OUT_Int_Handler, /* 34 */ \ + DMA_FLASH0_Int_Handler, /* 35 */ \ + SPORT0A_Int_Handler, /* 36 */ \ + SPORT0B_Int_Handler, /* 37 */ \ + Crypto_Int_Handler, /* 38 */ \ + DMA_ADC0_Int_Handler, /* 39 */ \ + GP_Tmr2_Int_Handler, /* 40 */ \ + Crystal_osc_Int_Handler, /* 41 */ \ + SPI1_Int_Handler, /* 42 */ \ + PLL_Int_Handler, /* 43 */ \ + RNG_Int_Handler, /* 44 */ \ + Beep_Int_Handler, /* 45 */ \ + ADC0_Int_Handler, /* 46 */ \ + 0, /* 47 */ \ + 0, /* 48 */ \ + 0, /* 49 */ \ + 0, /* 50 */ \ + 0, /* 51 */ \ + 0, /* 52 */ \ + 0, /* 53 */ \ + 0, /* 54 */ \ + 0, /* 55 */ \ + DMA_SIP0_Int_Handler, /* 56 */ \ + DMA_SIP1_Int_Handler, /* 57 */ \ + DMA_SIP2_Int_Handler, /* 58 */ \ + DMA_SIP3_Int_Handler, /* 59 */ \ + DMA_SIP4_Int_Handler, /* 60 */ \ + DMA_SIP5_Int_Handler, /* 61 */ \ + DMA_SIP6_Int_Handler, /* 62 */ \ + DMA_SIP7_Int_Handler, /* 63 */ \ + 0, /* 64 */ \ + 0, /* 65 */ \ + UART1_Int_Handler, /* 66 */ \ + DMA_UART1_TX_Int_Handler, /* 67 */ \ + DMA_UART1_RX_Int_Handler, /* 68 */ \ + RGB_Tmr_Int_Handler, /* 69 */ \ + 0, /* 70 */ \ + Root_Clk_Err_Handler, /* 71 */ \ + 0,0,0,0,0,0,0,0, /* 72 - 79 */ \ + (pFunc)BLANKX4, (pFunc)BLANKX4, /* security_options */ \ + (pFunc)BLANKX4, (pFunc)BLANKX4, \ + (pFunc)0xA79C3203u, (pFunc)LASTCRCPAGE, \ + (pFunc)BLANKX4, (pFunc)BLANKX4 /* 80 - 87 */ + +#endif /* __STARTUP_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c new file mode 100755 index 00000000000..df75af10d2f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c @@ -0,0 +1,322 @@ +/**************************************************************************//** + * @file system_ADuCM4050.c + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Source File for + * Device ADuCM4x50 + * @version V3.10 + * @date 23. November 2012 + * + ******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + + Portions Copyright (c) 2016 - 2017 Analog Devices, Inc. + ---------------------------------------------------------------------------*/ + +#include +#include +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef ADI_DEBUG +/* only needed in debug mode */ +uint32_t lfClock = 0u; /* "lf_clk" coming out of LF mux */ +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +/* Note that these variables will be re-initialized to the value set here by the + LIBC startup code, so if other clock values are required, make sure set them + here. +*/ +uint32_t hfClock = __HFOSC; /* "root_clk" output of HF mux */ +uint32_t gpioClock = 0u; /* external GPIO clock */ +uint32_t SystemCoreClock = __HFOSC; /*!< System Clock Frequency (Core Clock) */ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ + +/*! + * Update the clock. + * + * @param none + * @return none + * + * @brief Updates the variable SystemCoreClock and must be called whenever + * the core clock is changed during program execution. + */ +void SystemCoreClockUpdate(void) +{ + uint32_t val, nDivisor, nMulfactor, div2, mul2; + +#ifdef ADI_DEBUG + /* "lfclock" is only used during debug checks... */ + /* LF clock is always 32k, whether osc or xtal */ + lfClock = __LFCLK; /* for beep, wdt and lcd */ + if (lfClock == 0u) { + while (1) {} + } +#endif + /* Update Core Clock sources */ + /* update the HF clock */ + switch (pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX ) { + + case HFMUX_INTERNAL_OSC_VAL: + hfClock = __HFOSC; + break; + + case HFMUX_EXTERNAL_XTAL_VAL: + hfClock = __HFXTAL; + break; + + case HFMUX_SYSTEM_SPLL_VAL: + /* Calculate System PLL output frequency */ + if ((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_PLL_IPSEL) != 0u) { + /* PLL input from HFXTAL */ + val = __HFXTAL; + } else { + /* PLL input from HFOSC */ + val = __HFOSC; + } + + /* PLL NSEL multiplier */ + nMulfactor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLNSEL) >> BITP_CLKG_CLK_CTL3_SPLLNSEL; + /* PLL MSEL divider */ + nDivisor = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMSEL) >> BITP_CLKG_CLK_CTL3_SPLLMSEL; + + /* PLL NSEL multiplier */ + mul2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLMUL2) >> BITP_CLKG_CLK_CTL3_SPLLMUL2; + /* PLL MSEL divider */ + div2 = (pADI_CLKG0_CLK->CTL3 & BITM_CLKG_CLK_CTL3_SPLLDIV2) >> BITP_CLKG_CLK_CTL3_SPLLDIV2; + + val = ((val << mul2) * nMulfactor / nDivisor) >> div2; + + hfClock = val; + break; + + case HFMUX_GPIO_VAL: + hfClock = gpioClock; + break; + + default: + return; + } /* end switch */ + + SystemCoreClock = hfClock; +} + +/*! + * Configure the SRAM banks + * + * @return none + * + * @brief Setup the SRAM banks. + * Initialize the SRAM configuration and retention. + */ +void SramInit(void) +{ + /* On reset, there is no SRAM retention. Any retention has to be explicitly + * set here. */ + adi_system_EnableRetention(ADI_SRAM_BANK_1 | + ADI_SRAM_BANK_3 | + ADI_SRAM_BANK_4 | + ADI_SRAM_BANK_5 | + ADI_SRAM_BANK_6 | + ADI_SRAM_BANK_7, true); + /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */ + adi_system_EnableISRAM(false); + /* To disable the instruction cache */ + adi_system_EnableCache(false); +} + +/*! + * Initialize the system + * + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the relocate vector table. + */ +void SystemInit (void) +{ + uint32_t IntStatus; + + IntStatus = __get_PRIMASK(); + __disable_irq(); + + /* Set boot ROM IVT. */ + SCB->VTOR = (uint32_t)NVIC_FLASH_VECTOR_ADDRESS; + + /* Set all three (USGFAULTENA, BUSFAULTENA, and MEMFAULTENA) fault enable bits + * in the System Control Block, System Handler Control and State Register + * otherwise these faults are handled as hard faults. + */ + SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk | + SCB_SHCSR_BUSFAULTENA_Msk | + SCB_SHCSR_MEMFAULTENA_Msk ; + +#if (__FPU_PRESENT == 1u) && (__FPU_USED == 1u) + /* the FPU is disabled by default so enable FPU (NEON and VFP) + * set the System Control Block, Coprocessor Access Control Register bits: + * CP10 = grant CP10 coprocessor privileges and user mode access (full access) + * CP11 = grant CP11 coprocessor privileged and user mode access (full access) + * (CP10 and CP11 MUST be the same or "BEHAVIOR IS UNPREDICTABLE") + */ + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 for Full Access */ +#endif + + /* Flush instruction and data pipelines to insure assertion of new settings. */ + __ISB(); + __DSB(); + + adi_pwr_Init(); + adi_pwr_SetClockDivider(ADI_CLOCK_HCLK,1); + adi_pwr_SetClockDivider(ADI_CLOCK_PCLK,1); + + /* Set up the LF clock MUX. Currently LFXTAL is unstable so use the + internal LF Oscillator instead. LFXTAL is still required to be enabled + as it is required by RTC0. This LFXTAL issue is going to be fixed + in the next revision of the silicon. */ + adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFXTAL,true); + adi_pwr_SetLFClockMux(ADI_CLOCK_MUX_LFCLK_LFOSC); + adi_pwr_EnableClockSource(ADI_CLOCK_SOURCE_LFOSC,true); + + __set_PRIMASK(IntStatus); +} + +/*! + * @brief Enables or disables the cache. + * @param bEnable Specify whether to enable/disable cache. + * - true : Enable cache. + * - false: Disable cache. + * @return none + */ +void adi_system_EnableCache(bool bEnable) +{ + pADI_FLCC0_CACHE->KEY = CACHE_CONTROLLER_KEY; + if( bEnable == true ) { + pADI_FLCC0_CACHE->SETUP |= BITM_FLCC_CACHE_SETUP_ICEN; + } else { + pADI_FLCC0_CACHE->SETUP &= ~BITM_FLCC_CACHE_SETUP_ICEN; + } +} + +/*! + * @brief This enables or disables instruction SRAM + * + * @param bEnable Enable/disable the instruction SRAM. + * - true : Enable instruction SRAM. + * - false : Disable instruction SRAM. + * @return none + * @note The appropriate linker file needs to support the configuration. + */ +void adi_system_EnableISRAM(bool bEnable) +{ + + if( bEnable == true ) { + pADI_PMG0_TST->SRAM_CTL |= BITM_PMG_TST_SRAM_CTL_INSTREN; + } else { + pADI_PMG0_TST->SRAM_CTL &= ~BITM_PMG_TST_SRAM_CTL_INSTREN; + } +} + +/*! + * @brief This enables/disable SRAM retention during the hibernation. + * @param eBank: Specify which SRAM banks. Multiple banks can be set + / using a logical OR of the banks. + * @param bEnable Enable/disable the retention for specified SRAM bank. + * - true : Enable retention during hibernation. + * - false: Disable retention during hibernation. + * @return ADI_SYS_SUCCESS Configured successfully. + * @return ADI_SYS_FAILURE Invalid bank, or banks, specified. Any incorrect + * or invalid bank options will result in failure and + * no changes will have been applied. + * @note The appropriate linker file needs to support the configuration. + * BANK 0 is always retained. + * BANKS 1 can be retained individually. + * BANK 2 is never retained. + * BANKS 3 and 4 can only be mutually retained. + * BANKS 5 can be retained individually. + * BANKS 6 and 7 can only be mutually retained. + */ +ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable) +{ + uint32_t retainBits = 0u; + +#ifdef ADI_DEBUG + if((0u != (eBank & ADI_SRAM_BANK_0)) || + (0u != (eBank & ADI_SRAM_BANK_2))) { + /* Banks 0 and 2 are not selectable */ + return ADI_SYS_FAILURE; + } + + /* Are banks 3 or 4 selected? */ + if(0u != (eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4))) { + /* If so, the only valid option is for both to be retained. */ + if((eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) != (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) { + return ADI_SYS_FAILURE; + } + } + + /* Are banks 6 or 7 selected? */ + if(0u != (eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7))) { + /* If so, the only valid option is for both to be retained */ + if((eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) != (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) { + return ADI_SYS_FAILURE; + } + } +#endif + if((eBank & ADI_SRAM_BANK_1) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET1; + } + if((eBank & (ADI_SRAM_BANK_3 | ADI_SRAM_BANK_4)) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET2; + } + if((eBank & ADI_SRAM_BANK_5) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET3; + } + if((eBank & (ADI_SRAM_BANK_6 | ADI_SRAM_BANK_7)) != 0u) { + retainBits |= BITM_PMG_SRAMRET_RET4; + } + + /* Unlock the SRAMRET register using the PWRKEY. + * If there is any chance that this sequence can be interrupted then it + * should be protected by disabling interrupts. A write to any other + * register on the APB bus before writing to PMG_SRAMRET will return the + * protection to the lock state. */ + pADI_PMG0->PWRKEY = PWRKEY_VALUE_KEY; + if(bEnable) { + pADI_PMG0->SRAMRET |= retainBits; + } else { + pADI_PMG0->SRAMRET &= ~(retainBits); + } + + return ADI_SYS_SUCCESS; +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct new file mode 100755 index 00000000000..0f7791ae5ec --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct @@ -0,0 +1,52 @@ +;****************************************************************************** +; File: ADuCM4050.sct +; Scatter loading file for Analog Devices ADuCM4050 processor +; +; Copyright (c) 2011 - 2014 ARM LIMITED +; Copyright (c) 2016 - 2017 Analog Devices, Inc. +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +LR_IROM1 0x00000000 0x0007F000 { + FLASH0 0x00000000 0x00000800 { + *(.vectors, +First) + *(.checksum) + } + + ER_IROM1 AlignExpr(ImageLimit(FLASH0), 16) 0x0007E800 { + ; load address = execution address + *(InRoot$$Sections) + *(+RO) + } + + RW_IRAM1 0x20040000 EMPTY 0 { } + + ADUCM_IRAM2 0x20000200 0x7E00 { *(+RW) } + + ADUCM_IRAM3 0x20048000 0x10000 { *(+ZI) } + + ADUCM_HEAP AlignExpr(ImageLimit(RW_IRAM1), 16) EMPTY + (ImageBase(ADUCM_IRAM3) - 0x2000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { } ; heap +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld new file mode 100755 index 00000000000..2ead54a157c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld @@ -0,0 +1,214 @@ +/* + * Portions Copyright (c) 2016 Analog Devices, Inc. + * + * Based on Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld file in + * ARM.CMSIS.4.5.0.pack. + */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + /* The first 0x800 bytes of flash */ + FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800 + /* The remaining bytes of flash minus 4KB Protected Key Storage */ + FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 512k - 4k - 0x800 + /* SRAM bank 0 */ + DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 32k - 0x200 + /* SRAM bank 3+4+5+6+7 */ + DSRAM_B (rwx) : ORIGIN = 0x20048000, LENGTH = 64k + /* stack must not be in bank 1,2,7 where ISRAM or CACHE + are set at power on */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Custom stack and heap sizes */ +__stack_size__ = 0x2000; +__heap_size__ = 0x6000; + +/* select custom or default sizes for stack and heap */ +STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; +HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0C00; + + +/* Linker script to place sections and symbol values. + * It references the following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines the following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + KEEP(*(.checksum)) + } > FLASH0 + + .security_options : + { + . = ALIGN(4); + KEEP(*(.security_options)) + . = ALIGN(4); + } > FLASH0 + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > DSRAM_A + + .bss : + { + . = ALIGN(16); + __bss2_start__ = .; + *(COMMON) + . = ALIGN(16); + __bss2_end__ = .; + __bss_start__ = .; + *(.bss*) + . = ALIGN(16); + __bss_end__ = .; + } > DSRAM_B + + __StackTop = ORIGIN(DSRAM_B); + __StackLimit = __StackTop - STACK_SIZE; + __HeapLimit = __StackLimit; + __HeapBase = __HeapLimit - HEAP_SIZE; + __end__ = __HeapBase; + PROVIDE(end = __end__); + PROVIDE(__stack = __StackTop); +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf new file mode 100755 index 00000000000..318ad52023c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf @@ -0,0 +1,48 @@ +/****************************************************************************** +* File: ADuCM4050.icf +* ILINK Configuration File for Analog Devices ADuCM4050 processor +* +* Copyright (c) 2011 - 2014 ARM LIMITED +* Copyright (c) 2016 - 2017 Analog Devices, Inc. +* +* All rights reserved. +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* - Neither the name of ARM nor the names of its contributors may be used +* to endorse or promote products derived from this software without +* specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +******************************************************************************/ +define memory mem with size = 4G; +define region ROM_PAGE0_INTVEC = mem:[from 0x00000000 size 0x000001A0]; +define region ROM_PAGE0_CHECKSUM = mem:[from 0x000001A0 size 0x00000660]; +define region ROM_REGION = mem:[from 0x00000800 size 506K]; +define region RAM_bank1_region = mem:[from 0x20040000 size 0x00008000]; +define region RAM_bank2_region = mem:[from 0x20000200 size 0x00007E00] + | mem:[from 0x20048000 size 0x00010000]; +define block CSTACK with alignment = 16, size = 0x2000 { }; +define block HEAP with alignment = 16, size = 0x6000 { }; +do not initialize { section .noinit }; +initialize by copy { rw }; +place at start of ROM_PAGE0_INTVEC { ro section .vectors }; +place in ROM_PAGE0_CHECKSUM { ro section .checksum }; +place in ROM_REGION { ro }; +place at end of RAM_bank1_region { block CSTACK }; +place at start of RAM_bank1_region { block HEAP }; +place in RAM_bank2_region { rw }; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c new file mode 100755 index 00000000000..8257894757b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.c @@ -0,0 +1,138 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +/* + The ADuCM4050 is made in two package variants. + + 64 lead LFCSP & 72 ball WLCSP + + There are some differences for Port 2 between the two variants + WLCSP also has Port 3. + + The #define ADUCM4050_LFCSP is used to determine which variant the code + is built for. + + For LFCSP leave the #define in, to build for ADUCM4050_WLCSP remove. +*/ +#define ADUCM4050_LFCSP + +#include "PeripheralPins.h" + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_10, UART_0, 1}, + {P1_15, UART_1, 2}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_11, UART_0, 1}, + {P2_00, UART_1, 2}, + {NC, NC, 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P0_00, SPI_0, 1}, + {P1_06, SPI_1, 1}, + {P1_02, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P0_01, SPI_0, 1}, + {P1_07, SPI_1, 1}, + {P1_03, SPI_2, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P0_02, SPI_0, 1}, + {P1_08, SPI_1, 1}, + {P1_04, SPI_2, 1}, + {NC, NC, 0} +}; + +#if defined(ADUCM4050_LFCSP) +const PinMap PinMap_SPI_SSEL[] = { + {P0_03, SPI_0, 1}, + {P1_09, SPI_1, 1}, + {P2_10, SPI_2, 1}, + {NC, NC, 0} +}; +#else +const PinMap PinMap_SPI_SSEL[] = { + {P0_03, SPI_0, 1}, + {P1_09, SPI_1, 1}, + {P2_15, SPI_2, 1}, + {NC, NC, 0} +}; +#endif + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_05, I2C_0, 1}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_04, I2C_0, 1}, + {NC, NC, 0} +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P2_03, ADC0_VIN0, 1}, + {P2_04, ADC0_VIN1, 1}, + {P2_05, ADC0_VIN2, 1}, + {P2_06, ADC0_VIN3, 1}, + {P2_07, ADC0_VIN4, 1}, + {P2_08, ADC0_VIN5, 1}, + {P2_09, ADC0_VIN6, 1}, +#ifdef ADUCM4050_LFCSP + {P2_10, ADC0_VIN7, 1}, +#endif + {NC, NC, 0} +}; + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h new file mode 100755 index 00000000000..40ef7f85b12 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/PeripheralPins.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +/************RTC***************/ +extern const PinMap PinMap_RTC[]; + +/************ADC***************/ +extern const PinMap PinMap_ADC[]; + +/************I2C***************/ +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +/************UART***************/ +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; + +/************SPI***************/ +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SSEL[]; + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c new file mode 100755 index 00000000000..baa96a694ef --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -0,0 +1,228 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "adi_adc_def.h" +#include "pinmap.h" +#include "PeripheralPins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* ADC Device number */ +#define ADC_DEV_NUM (0u) + +/* Memory Required for adc driver */ +static uint32_t DeviceMemory[(ADI_ADC_MEMORY_SIZE+3)/4]; +/* Active channel */ +static uint32_t adi_pin2channel(PinName pin); + +/** + * \defgroup hal_analogin Analogin hal functions + * @{ + */ + +/** Initialize the analogin peripheral + * + * Configures the pin used by analogin. + * @param obj The analogin object to initialize + * @param pin The analogin pin name + */ +void analogin_init(analogin_t *obj, PinName pin) +{ + ADI_ADC_HANDLE hDevice; + bool bCalibrationDone = false; + bool bReady = false; + + ADCName peripheral; + uint32_t function, channel; + + peripheral = (ADCName)pinmap_peripheral(pin, &PinMap_ADC[0]); // gives peripheral + MBED_ASSERT(peripheral != (ADCName)NC); + + /* verify read function */ + function = pinmap_function(pin, &PinMap_ADC[0]); + MBED_ASSERT(function == 1); + + /* Configure PORT2_MUX registers */ + pin_function(pin, function); + + /* Configure active channel */ + channel = adi_pin2channel(pin); + MBED_ASSERT(channel != 0xFFFFFFFF); + obj->UserBuffer.nChannels = channel; + + /* Set ACLK to CCLK/16 */ + adi_pwr_SetClockDivider(ADI_CLOCK_ACLK,16); + + /* Set default values for conversion and delay cycles. This sets up a sampling rate of + 16kHz. The sampling frequency is worked out from the following: + + if delay time > 0: + Fs = ACLK / [((14 + sampling time) * oversample factor) + (delay time + 2)] + if delay time = 0: + Fs = ACLK / ((14 + sampling time) * oversample factor) + + The sampling (or acquisition) and delay times are in number of ACLK clock cycles. + */ + obj->DelayCycles = 0; + obj->SampleCycles = 88; + + /* Open the ADC device */ + adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice); + obj->hDevice = hDevice; + + /* Power up ADC */ + adi_adc_PowerUp(hDevice, true); + + /* Set ADC reference */ + adi_adc_SetVrefSource(hDevice, ADI_ADC_VREF_SRC_INT_2_50_V); + + /* Enable ADC sub system */ + adi_adc_EnableADCSubSystem(hDevice, true); + + /* Wait untilthe ADC is ready for sampling */ + while(bReady == false) { + adi_adc_IsReady(hDevice, &bReady); + } + + /* Start calibration */ + adi_adc_StartCalibration(hDevice); + + /* Wait until calibration is done */ + while (!bCalibrationDone) { + adi_adc_IsCalibrationDone(hDevice, &bCalibrationDone); + } + + /* Set the delay time */ + adi_adc_SetDelayTime(hDevice, obj->DelayCycles); + + /* Set the acquisition time. (Application need to change it based on the impedence) */ + adi_adc_SetAcquisitionTime(hDevice, obj->SampleCycles); + +} + +/** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @param obj The analogin object + * @return A floating value representing the current input voltage + */ +float analogin_read(analogin_t *obj) +{ + float fl32 = (float)analogin_read_u16(obj)/(float)4095.0; + + return(fl32); +} + +/** Read the value from analogin pin, represented as an unsigned 16bit value + * + * @param obj The analogin object + * @return An unsigned 16bit value representing the current input voltage + */ +uint16_t analogin_read_u16(analogin_t *obj) +{ + ADI_ADC_HANDLE hDevice = obj->hDevice; + ADI_ADC_BUFFER *pAdcBuffer; + + /* Submit the buffer to the driver */ + adi_adc_SubmitBuffer(hDevice, &obj->UserBuffer); + + /* Enable the ADC */ + adi_adc_Enable(hDevice, true); + + adi_adc_GetBuffer(hDevice, &pAdcBuffer); + MBED_ASSERT(pAdcBuffer == &obj->UserBuffer); + + return( (uint16_t)( ((uint16_t *)pAdcBuffer->pDataBuffer)[(pAdcBuffer->nNumConversionPasses) - 1]) ); +} + +/* Retrieve te active channel correspondoing to the input pin */ +static uint32_t adi_pin2channel(PinName pin) +{ + + uint32_t activech; + + switch(pin) { + case ADC_VIN0: + activech = ADI_ADC_CHANNEL_0; + break; + case ADC_VIN1: + activech = ADI_ADC_CHANNEL_1; + break; + case ADC_VIN2: + activech = ADI_ADC_CHANNEL_2; + break; + case ADC_VIN3: + activech = ADI_ADC_CHANNEL_3; + break; + case ADC_VIN4: + activech = ADI_ADC_CHANNEL_4; + break; + case ADC_VIN5: + activech = ADI_ADC_CHANNEL_5; + break; + case ADC_VIN6: + activech = ADI_ADC_CHANNEL_6; + break; + case ADC_VIN7: + activech = ADI_ADC_CHANNEL_7; + break; + default: + activech = (uint32_t) 0xFFFFFFFF; + break; + } + + return ((uint32_t)activech); +} + + + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif // #if DEVICE_ANALOGIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h new file mode 100755 index 00000000000..b0439b1db09 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H +#define __C +#include "adi_processor.h" +#include "cmsis_nvic.h" +#undef __C +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h new file mode 100755 index 00000000000..3a866a5d726 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h @@ -0,0 +1,78 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include "cmsis.h" + +#define NVIC_USER_IRQ_OFFSET 16 +#define NVIC_USER_IRQ_NUMBER 72 +#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER) + +#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 +#define NVIC_FLASH_VECTOR_ADDRESS 0x0 + +#ifdef __cplusplus +extern "C" { +#endif + +/** Set the ISR for IRQn + * + * Sets an Interrupt Service Routine vector for IRQn; if the feature is available, the vector table is relocated to SRAM + * the first time this function is called + * @param[in] IRQn The Interrupt Request number for which a vector will be registered + * @param[in] vector The ISR vector to register for IRQn + */ +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); + +/** Get the ISR registered for IRQn + * + * Reads the Interrupt Service Routine currently registered for IRQn + * @param[in] IRQn The Interrupt Request number the vector of which will be read + * @return Returns the ISR registered for IRQn + */ +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h new file mode 100755 index 00000000000..0d46738ec1a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/device.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c new file mode 100755 index 00000000000..25afcc193fc --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c @@ -0,0 +1,89 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifdef DEVICE_FLASH +#include "flash_api.h" +#include "flash_data.h" +#include "mbed_critical.h" + +// This file is automagically generated + +// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM + +static unsigned FLASH_ALGO[] = { + 0x20004A4B,0x60111E41,0x6211494A,0x60912107,0x074B6811,0xF011D5FC,0xD0000F30,0x21002001, + 0x47706211,0x2400B510,0xD1082A01,0xF872F000,0x6D09493F,0xD00207C8,0xFFE2F7FF,0x46204604, + 0x493BBD10,0x62082000,0xB5104770,0xF862F000,0x4010E8BD,0x4601E7D4,0x20004A35,0x60131E43, + 0x49346191,0x21066211,0x68116091,0xD5FC074B,0x0F30F011,0x2001D000,0x62112100,0xB57C4770, + 0x4B2C4C2B,0x62232500,0xF04FE03E,0x602333FF,0xD3042908,0x61236813,0x61636853,0xF04FE025, + 0xE9CD33FF,0x29083300,0xE8DFD21A,0x1619F001,0x0A0D1013,0x79910407,0x1006F88D,0xF88D7951, + 0x79111005,0x1004F88D,0xF88D78D1,0x78911003,0x1002F88D,0xF88D7851,0x78111001,0x1000F88D, + 0x1300E9DD,0x61636121,0x60E02108,0x60A32304,0xF0136823,0xD0010F30,0xE0072501,0x075B6823, + 0x3008D5FC,0x32083908,0xD1BE2900,0x62202000,0xBD7C4628,0x21004806,0x4A066041,0x4A066202, + 0x22046342,0x22016382,0x62016542,0x00004770,0x40018000,0x676C7565,0xB8950950,0 +}; + +static const flash_algo_t flash_algo_config = { + .init = 0x00000025, + .uninit = 0x00000043, + .erase_sector = 0x00000057, + .program_page = 0x0000007F, + .static_base = 0x0000013C, + .algo_blob = FLASH_ALGO +}; + +static const sector_info_t sectors_info[] = { + {0x0, 0x800}, +}; + +static const flash_target_config_t flash_target_config = { + .page_size = 0x800, + .flash_start = 0x0, + .flash_size = 0x0007F000, + .sectors = sectors_info, + .sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t) +}; + +void flash_set_target_config(flash_t *obj) +{ + obj->flash_algo = &flash_algo_config; + obj->target_config = &flash_target_config; +} +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c new file mode 100755 index 00000000000..81d4be52cb7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_api.c @@ -0,0 +1,147 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "adi_gpio.h" + + +#define MUX_FUNC_0 0x0 +#define NUM_GPIO_PORTS 4 + +extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +extern uint8_t gpio_initialized; + +static uint16_t gpio_oen[NUM_GPIO_PORTS] = {0}; +static uint16_t gpio_output_val[NUM_GPIO_PORTS] = {0}; + + +/****************************************************************************** + Function definitions + *****************************************************************************/ +uint32_t gpio_set(PinName pin) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_num = pin & 0xFF; + + pin_function(pin, MUX_FUNC_0); + + return (1 << pin_num); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + if (pin == (PinName)NC) { + return; + } + + // Initialize the GPIO driver. This function + // initializes the GPIO driver only once globally. + if (!gpio_initialized) { + adi_gpio_Init(gpioMemory, ADI_GPIO_MEMORY_SIZE); + } + + pin_function(pin, MUX_FUNC_0); +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + uint32_t pin = obj->pin; + + pin_mode((PinName)pin, mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + + if (direction == PIN_OUTPUT) { + adi_gpio_OutputEnable((ADI_GPIO_PORT)port, 1 << pin_num, true); + // save the input/output configuration + gpio_oen[port] |= (1 << pin_num); + } else { + adi_gpio_InputEnable((ADI_GPIO_PORT)port, 1 << pin_num, true); + // save the input/output configuration + gpio_oen[port] &= (~(1 << pin_num)); + } +} + +void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + + if (value & 1) { + adi_gpio_SetHigh((ADI_GPIO_PORT)port, (1 << pin_num)); + + // save the output port value + gpio_output_val[port] |= ((value & 1) << pin_num); + } else { + adi_gpio_SetLow((ADI_GPIO_PORT)port, (1 << pin_num)); + + // save the output port value + gpio_output_val[port] &= (~(1 << pin_num)); + } +} + + +int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t port = obj->pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pin & 0xFF; + uint16_t Data; + + // check whether the pin is configured as input or output + if ((gpio_oen[port] >> pin_num) & 1) { + Data = gpio_output_val[port] & (1 << pin_num); + } else { + // otherwise call GetData + adi_gpio_GetData((ADI_GPIO_PORT)port, (1 << pin_num), &Data); + } + + return ((((uint32_t)Data) >> pin_num) & 1); +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c new file mode 100755 index 00000000000..5e0d99ad8b0 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_dev_mem.c @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include + +// ADI GPIO device driver state memory. Only one state memory is required globally. +uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; + +// Flag to indicate whether the GPIO driver has been initialized +uint8_t gpio_initialized = 0; diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c new file mode 100755 index 00000000000..3cf237218bd --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_irq_api.c @@ -0,0 +1,326 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "gpio_irq_api.h" +#include "adi_gpio.h" +#include "adi_gpio_def.h" + +#ifdef DEVICE_INTERRUPTIN + +#define MAX_GPIO_LINES 16 +#define MAX_GPIO_PORTS ADI_GPIO_NUM_PORTS + +typedef struct { + unsigned int id; + gpio_irq_event event; + uint8_t int_enable; +} gpio_chan_info_t; + +extern uint8_t gpioMemory[ADI_GPIO_MEMORY_SIZE]; +extern uint8_t gpio_initialized; +static gpio_chan_info_t channel_ids[MAX_GPIO_PORTS][MAX_GPIO_LINES]; +static gpio_irq_handler irq_handler = NULL; + + +/** Local interrupt callback routine. + */ +static void gpio_irq_callback(void *pCBParam, uint32_t Event, void *pArg) +{ + uint16_t pin = *(ADI_GPIO_DATA*)pArg; + int index = 0; + + // determine the index of the pin that caused the interrupt + while (pin) { + if (pin & 0x01) { + // call the user ISR. The argument Event is the port number of the GPIO line. + if (irq_handler != NULL) + irq_handler((uint32_t)channel_ids[Event][index].id, channel_ids[Event][index].event); + } + index++; + pin >>= 1; + } +} + + +/** Function to get the IENA and IENB register values. + * Added here based on code from ADuCM302x + */ +static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPins(const ADI_GPIO_PORT Port, const IRQn_Type eIrq, + const ADI_GPIO_DATA Pins, uint16_t* const pValue) +{ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2, pADI_GPIO3}; + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + uint16_t Value = 0u; + + pPort = pReg[Port]; + + switch (eIrq) { + case SYS_GPIO_INTA_IRQn: + Value = pPort->IENA; + break; + case SYS_GPIO_INTB_IRQn: + Value = pPort->IENB; + break; + default: + break; /* This shall never reach */ + } + + *pValue = (Value & Pins); + return (ADI_GPIO_SUCCESS); +} + + +/** Function to get the interrupt polarity register content. + * Added here based on code from ADuCM302x + */ +static ADI_GPIO_RESULT adi_gpio_GetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, + uint16_t* const pValue) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS] = {pADI_GPIO0, pADI_GPIO1, pADI_GPIO2, pADI_GPIO3}; + + pPort = pReg[Port]; + + *pValue = (pPort->POL & Pins); + + return (ADI_GPIO_SUCCESS); +} + + +/** Function to clear the relevant interrupt enable bits in both the IENA and IENB registers + * for the given GPIO pin. + */ +static void disable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number) +{ + uint16_t int_reg_val; + + // Read the current content of the IENA register + adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, 1 << pin_number, &int_reg_val); + + // clear the bit for the pin + int_reg_val &= ~(1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTA_IRQn, int_reg_val); + + // Do the same to IENB + adi_gpio_GetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, 1 << pin_number, &int_reg_val); + + // clear the bit for the pin + int_reg_val &= ~(1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, SYS_GPIO_INTB_IRQn, int_reg_val); +} + + +/** Function to set the relevant interrupt enable bits in either the IENA and IENB registers + * for the given GPIO pin. + */ +static void enable_pin_interrupt(ADI_GPIO_PORT port, uint32_t pin_number, IRQn_Type eIrq) +{ + uint16_t int_reg_val; + + // Read the current interrupt enable register content + adi_gpio_GetGroupInterruptPins(port, eIrq, 1 << pin_number, &int_reg_val); + + // set the bit for the pin + int_reg_val |= (1 << pin_number); + + // write the interrupt register + adi_gpio_SetGroupInterruptPins(port, eIrq, int_reg_val); +} + + +/** Initialize the GPIO IRQ pin + * + * @param obj The GPIO object to initialize + * @param pin The GPIO pin name + * @param handler The handler to be attached to GPIO IRQ + * @param id The object ID (id != 0, 0 is reserved) + * @return -1 if pin is NC, 0 otherwise + */ +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + uint32_t port = pin >> GPIO_PORT_SHIFT; + uint32_t pin_num = pin & 0xFF; + + // check for valid pin and ID + if ((pin == NC) || (id == 0)) { + return -1; + } + + // make sure gpio driver has been initialized + if (!gpio_initialized) { + adi_gpio_Init(gpioMemory,ADI_GPIO_MEMORY_SIZE); + gpio_initialized = 1; + } + + // save the handler + if (handler) { + irq_handler = handler; + } + + // disable the interrupt for the given pin + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + + // set the port pin as input + adi_gpio_InputEnable(port, 1 << pin_num, true); + + // save the ID for future reference + channel_ids[port][pin_num].id = id; + channel_ids[port][pin_num].event = IRQ_NONE; + channel_ids[port][pin_num].int_enable = 0; + obj->id = id; + obj->pinname = pin; + + return 0; +} + +/** Release the GPIO IRQ PIN + * + * @param obj The gpio object + */ +void gpio_irq_free(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + // disable interrupt for the given pin + gpio_irq_disable(obj); + + // clear the status table + channel_ids[port][pin_num].id = 0; + channel_ids[port][pin_num].event = IRQ_NONE; + channel_ids[port][pin_num].int_enable = 0; +} + +/** Enable/disable pin IRQ event + * + * @param obj The GPIO object + * @param event The GPIO IRQ event + * @param enable The enable flag + */ +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint16_t int_polarity_reg; + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (event == IRQ_NONE) { + return; + } + + // read the current polarity register + adi_gpio_GetGroupInterruptPolarity((ADI_GPIO_PORT)port, 1 << pin_num, &int_polarity_reg); + + if (event == IRQ_RISE) { + int_polarity_reg |= (1 << pin_num); + } else { + int_polarity_reg &= ~(1 << pin_num); + } + + // set the polarity register + adi_gpio_SetGroupInterruptPolarity((ADI_GPIO_PORT)port, int_polarity_reg); + + channel_ids[port][pin_num].event = event; + + // enable interrupt for this pin if enable flag is set + if (enable) { + gpio_irq_enable(obj); + } else { + gpio_irq_disable(obj); + } +} + +/** Enable GPIO IRQ + * + * This is target dependent, as it might enable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_enable(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (channel_ids[port][pin_num].event == IRQ_NONE) { + return; + } + + // Group all RISE interrupts in INTA and FALL interrupts in INTB + if (channel_ids[port][pin_num].event == IRQ_RISE) { + // set the callback routine + adi_gpio_RegisterCallback(SYS_GPIO_INTA_IRQn, gpio_irq_callback, obj); + enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTA_IRQn); + } else if (channel_ids[port][pin_num].event == IRQ_FALL) { + // set the callback routine + adi_gpio_RegisterCallback(SYS_GPIO_INTB_IRQn, gpio_irq_callback, obj); + enable_pin_interrupt((ADI_GPIO_PORT)port, pin_num, SYS_GPIO_INTB_IRQn); + } + + channel_ids[port][pin_num].int_enable = 1; +} + +/** Disable GPIO IRQ + * + * This is target dependent, as it might disable the entire port or just a pin + * @param obj The GPIO object + */ +void gpio_irq_disable(gpio_irq_t *obj) +{ + uint32_t port = obj->pinname >> GPIO_PORT_SHIFT; + uint32_t pin_num = obj->pinname & 0xFF; + + if (channel_ids[port][pin_num].event == IRQ_NONE) { + return; + } + + // Group all RISE interrupts in INTA and FALL interrupts in INTB + if (channel_ids[port][pin_num].event == IRQ_RISE) { + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + } + else if (channel_ids[port][pin_num].event == IRQ_FALL) { + disable_pin_interrupt((ADI_GPIO_PORT)port, pin_num); + } + + channel_ids[port][pin_num].int_enable = 0; +} + +#endif // #ifdef DEVICE_INTERRUPTIN diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h new file mode 100755 index 00000000000..8d59616b7f7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/gpio_object.h @@ -0,0 +1,61 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; +} gpio_t; + +static inline int gpio_is_connected(const gpio_t *obj) +{ + return obj->pin != (PinName)NC; +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c new file mode 100755 index 00000000000..f25d80c9105 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/i2c_api.c @@ -0,0 +1,220 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "drivers/i2c/adi_i2c.h" + + + +#if defined(BUILD_I2C_MI_DYNAMIC) +#if defined(ADI_DEBUG) +#warning "BUILD_I2C_MI_DYNAMIC is defined. Memory allocation for I2C will be dynamic" +int adi_i2c_memtype = 0; +#endif +#else +static uint8_t i2c_Mem[ADI_I2C_MEMORY_SIZE]; +static ADI_I2C_HANDLE i2c_Handle; +#if defined(ADI_DEBUG) +#warning "BUILD_I2C_MI_DYNAMIC is NOT defined. Memory allocation for I2C will be static" +int adi_i2c_memtype = 1; +#endif +#endif + + + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + ADI_I2C_HANDLE *pI2C_Handle; + uint8_t *I2C_Mem; + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + uint32_t I2C_DevNum = I2C_0; /* ADuCM4050 only has 1 I2C port */ + + +#if defined(BUILD_I2C_MI_DYNAMIC) + I2C_DevNum = I2C_0; + pI2C_Handle = &obj->I2C_Handle; + obj->pI2C_Handle = pI2C_Handle; + I2C_Mem = obj->I2C_Mem; +#else + I2C_DevNum = I2C_0; + pI2C_Handle = &i2c_Handle; + obj->pI2C_Handle = pI2C_Handle; + I2C_Mem = &i2c_Mem[0]; +#endif + + + obj->instance = pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->instance != NC); + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + SystemCoreClockUpdate(); + I2C_Return = adi_i2c_Open(I2C_DevNum, I2C_Mem, ADI_I2C_MEMORY_SIZE, pI2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } + I2C_Return = adi_i2c_Reset(*pI2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_start(i2c_t *obj) +{ + /* The Hardware does not support this feature. */ + return -1; +} + + +int i2c_stop(i2c_t *obj) +{ + /* The Hardware does not support this feature. */ + return -1; +} + + +void i2c_frequency(i2c_t *obj, int hz) +{ + ADI_I2C_HANDLE I2C_Handle; + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetBitRate(I2C_Handle, (uint32_t) hz); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + ADI_I2C_RESULT I2C_Return; + ADI_I2C_TRANSACTION I2C_inst; + uint8_t I2C_PrologueData = 0x00; + uint32_t I2C_Errors; /* HW Error result */ + ADI_I2C_HANDLE I2C_Handle; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF)); + I2C_inst.pPrologue = &I2C_PrologueData; + I2C_inst.nPrologueSize = 0; + I2C_inst.pData = (uint8_t*) data; + I2C_inst.nDataSize = length; + I2C_inst.bReadNotWrite = true; + I2C_inst.bRepeatStart = stop; + I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return -1; + } else { + return length; + } +} + + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + ADI_I2C_RESULT I2C_Return = ADI_I2C_SUCCESS; + ADI_I2C_TRANSACTION I2C_inst; + uint8_t I2C_PrologueData = 0x00; + uint32_t I2C_Errors; /* HW Error result */ + ADI_I2C_HANDLE I2C_Handle; + + + I2C_Handle = *obj->pI2C_Handle; + I2C_Return = adi_i2c_SetSlaveAddress(I2C_Handle, (address & 0x0000FFFF)); + I2C_inst.pPrologue = &I2C_PrologueData; + I2C_inst.nPrologueSize = 0; + I2C_inst.pData = (uint8_t*) data; + I2C_inst.nDataSize = length; + I2C_inst.bReadNotWrite = false; + I2C_inst.bRepeatStart = stop; + I2C_Return = adi_i2c_ReadWrite(I2C_Handle, &I2C_inst, &I2C_Errors); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return -1; + } else { + return length; + } +} + + +void i2c_reset(i2c_t *obj) +{ + ADI_I2C_RESULT I2C_Return; + ADI_I2C_HANDLE I2C_Handle = *obj->pI2C_Handle; + + I2C_Return = adi_i2c_Reset(I2C_Handle); + if (I2C_Return) { + obj->error = I2C_EVENT_ERROR; + return; + } +} + + +int i2c_byte_read(i2c_t *obj, int last) +{ + /* The Hardware does not support this feature. */ + return -1; +} + + +int i2c_byte_write(i2c_t *obj, int data) +{ + /* The Hardware does not support this feature. */ + return -1; +} + +#endif // #if DEVICE_I2C diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h new file mode 100755 index 00000000000..495faf8c671 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/objects.h @@ -0,0 +1,112 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" +#include "adi_rng.h" + +#include "adi_i2c.h" +#include "adi_spi.h" +#include "adi_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + unsigned int id; + PinName pinname; +}; + +struct sleep_s { + int temp; +}; + +struct serial_s { + int index; +}; + +struct trng_s { + ADI_RNG_HANDLE RNGhDevice; +}; + +#define BUILD_I2C_MI_DYNAMIC +struct i2c_s { + uint32_t instance; + uint32_t error; + ADI_I2C_HANDLE *pI2C_Handle; +#if defined(BUILD_I2C_MI_DYNAMIC) + ADI_I2C_HANDLE I2C_Handle; + uint8_t I2C_Mem[ADI_I2C_MEMORY_SIZE]; +#endif +}; + +#define BUILD_SPI_MI_DYNAMIC +struct spi_s { + uint32_t instance; + uint32_t error; + ADI_SPI_HANDLE *pSPI_Handle; +#if defined(BUILD_SPI_MI_DYNAMIC) + ADI_SPI_HANDLE SPI_Handle; + uint8_t SPI_Mem[ADI_SPI_MEMORY_SIZE]; +#endif +}; + +#include "gpio_object.h" + +struct analogin_s { + ADI_ADC_HANDLE hDevice; + ADI_ADC_BUFFER UserBuffer; + uint8_t DelayCycles; + uint8_t SampleCycles; +}; + + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c new file mode 100755 index 00000000000..bb061e0ba4a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/pinmap.c @@ -0,0 +1,103 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" + +#include "PinNames.h" +#include "adi_gpio.h" + +void pin_function(PinName pin, int function) +{ + // pin is composed of port and pin + // function is the function number (the mux selection number shifted by the pin value + // and written to pin mux register, each pin mux takes 2 bits hence multiplying by 2) + + MBED_ASSERT(pin != (PinName)NC); + + uint8_t port = pin >> GPIO_PORT_SHIFT; + uint32_t cfg_reg, mask; + volatile uint32_t *pGPIO_CFG; + + switch (port) { + case 0: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO0_CFG; + break; + case 1: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO1_CFG; + break; + case 2: + pGPIO_CFG = (volatile uint32_t *)REG_GPIO2_CFG; + break; + + default: + return; + } + + cfg_reg = *pGPIO_CFG; + // clear the corresponding 2 bit field first before writing the function + // bits + mask = ~(3 << (pin * 2)); + cfg_reg = cfg_reg & mask | (function << (pin*2)); + *pGPIO_CFG = cfg_reg; +} + +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + + uint8_t port = pin >> GPIO_PORT_SHIFT; + uint32_t pin_reg_value = 2 ^ (0xFF & pin); + + switch (mode) { + case PullNone: + adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA) pin_reg_value,false); + break; + + case PullDown: + case PullUp: + adi_gpio_PullUpEnable((ADI_GPIO_PORT)port, (ADI_GPIO_DATA) pin_reg_value,true); + break; + + default: + break; + } +} diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c new file mode 100755 index 00000000000..8b650705fc6 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/rtc_api.c @@ -0,0 +1,94 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "adi_rtc.h" +#include "adi_pwr.h" + +#define RTC_DEVICE_NUM 0 +static uint8_t aRtcDevMem0[ADI_RTC_MEMORY_SIZE]; +static ADI_RTC_HANDLE hDevice0 = NULL; + + +void rtc_init(void) +{ + /* initialize driver */ + adi_rtc_Open(RTC_DEVICE_NUM,aRtcDevMem0,ADI_RTC_MEMORY_SIZE,&hDevice0); + + adi_rtc_Enable(hDevice0, true); +} + +void rtc_free(void) +{ + adi_rtc_Close(hDevice0); +} + +/* + * Little check routine to see if the RTC has been enabled + * 0 = Disabled, 1 = Enabled + */ +int rtc_isenabled(void) +{ + uint32_t ControlReg; + + adi_rtc_GetControl (hDevice0, ADI_RTC_CONTROL_REGISTER_0,&ControlReg); + + return((int) (ControlReg & BITM_RTC_CR0_CNTEN)); +} + +time_t rtc_read(void) +{ + time_t currentCount; + + adi_rtc_GetCount(hDevice0, (uint32_t *)(¤tCount)); + + return(currentCount); +} + +void rtc_write(time_t t) +{ + adi_rtc_SetCount (hDevice0, t); +} + +#endif // #if DEVICE_RTC + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c new file mode 100755 index 00000000000..fabe28d035e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/serial_api.c @@ -0,0 +1,251 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "serial_api.h" + +#if DEVICE_SERIAL + +// math.h required for floating point operations for baud rate calculation +#include +#include "mbed_assert.h" + +#include + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "drivers/uart/adi_uart.h" +#define ADI_UART_MEMORY_SIZE (ADI_UART_BIDIR_MEMORY_SIZE) +#define ADI_UART_NUM_DEVICES 2 + +static ADI_UART_HANDLE hDevice[ADI_UART_NUM_DEVICES]; +static uint32_t UartDeviceMem[ADI_UART_NUM_DEVICES][(ADI_UART_MEMORY_SIZE + 3)/4]; +static uint32_t serial_irq_ids[ADI_UART_NUM_DEVICES] = {0}; +static uart_irq_handler irq_handler = NULL; +int stdio_uart_inited = 0; +serial_t stdio_uart; +static int rxbuffer[2]; +static int txbuffer[2]; + +static void uart_callback(void *pCBParam, uint32_t Event, void *pArg) +{ + MBED_ASSERT(irq_handler); + serial_t *obj = pCBParam; + if (Event == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + irq_handler(serial_irq_ids[obj->index], TxIrq); + else if (Event == ADI_UART_EVENT_RX_BUFFER_PROCESSED) + irq_handler(serial_irq_ids[obj->index], RxIrq); +} + + +void serial_free(serial_t *obj) +{ + adi_uart_Close(hDevice[obj->index]); +} + +void serial_baud(serial_t *obj, int baudrate) +{ + uint32_t uartdivc,uartdivm,uartdivn,uartosr; + + // figures based on PCLK of 26MHz + switch (baudrate) { + case 9600: + uartdivc= 28; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + case 19200: + uartdivc= 14; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + case 38400: + uartdivc= 07; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + case 57600: + uartdivc= 14; + uartdivm= 1; + uartdivn= 15; + uartosr= 3; + break; + case 115200: + uartdivc= 03; + uartdivm= 2; + uartdivn= 719; + uartosr= 3; + break; + case 230400: + uartdivc= 03; + uartdivm= 1; + uartdivn= 359; + uartosr= 3; + break; + default: // default of 9600kbps + uartdivc= 28; + uartdivm= 3; + uartdivn= 46; + uartosr= 3; + break; + } + + adi_uart_ConfigBaudRate(hDevice[obj->index],uartdivc,uartdivm,uartdivn,uartosr); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + ADI_UART_PARITY convertedparity = ADI_UART_NO_PARITY; + ADI_UART_STOPBITS convertedstopbits = ADI_UART_ONE_STOPBIT; + + if (stop_bits) { + convertedstopbits = ADI_UART_ONE_AND_HALF_TWO_STOPBITS; + } + + if (parity == ParityOdd) { + convertedparity = ADI_UART_ODD_PARITY; + } else if (parity == ParityEven) { + convertedparity = ADI_UART_EVEN_PARITY; + } else if (parity == ParityForced1) { + convertedparity = ADI_UART_ODD_PARITY_STICKY; + } else if (parity == ParityForced0) { + convertedparity = ADI_UART_EVEN_PARITY_STICKY; + } + + adi_uart_SetConfiguration(hDevice[obj->index], convertedparity, convertedstopbits, + (ADI_UART_WORDLEN)(data_bits - 5)); +} + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + obj->index = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->index != NC); + adi_uart_Open(obj->index,ADI_UART_DIR_BIDIRECTION,UartDeviceMem[obj->index],ADI_UART_MEMORY_SIZE,&hDevice[obj->index]); + serial_baud(obj, 9600); + serial_format(obj, 8, ParityNone, 1); + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + if (tx != NC) { + pin_mode(tx, PullUp); + } + if (rx != NC) { + pin_mode(rx, PullUp); + } + if (obj->index == STDIO_UART) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +int serial_readable(serial_t *obj) +{ + bool bAvailable = false; + adi_uart_IsRxBufferAvailable(hDevice[obj->index], &bAvailable); + return bAvailable; +} + +int serial_getc(serial_t *obj) +{ + int c; + void *pBuff; + uint32_t pHwError; + adi_uart_SubmitRxBuffer(hDevice[obj->index], &rxbuffer[obj->index], 1, 1); + adi_uart_GetRxBuffer(hDevice[obj->index], &pBuff, &pHwError); + c = (unsigned) rxbuffer[obj->index]; + return (c); +} + +int serial_writable(serial_t *obj) +{ + bool bAvailable = false; + adi_uart_IsTxBufferAvailable(hDevice[obj->index], &bAvailable); + return bAvailable; +} + +void serial_putc(serial_t *obj, int c) +{ + void *pBuff; + uint32_t pHwError; + txbuffer[obj->index]= (char) c; + adi_uart_SubmitTxBuffer(hDevice[obj->index],&txbuffer[obj->index], 1, 1); + adi_uart_GetTxBuffer(hDevice[obj->index], &pBuff, &pHwError); + return; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + MBED_ASSERT(obj); + + adi_uart_RegisterCallback(hDevice[obj->index], &uart_callback, obj); + if (enable) { + } else { + } +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + adi_uart_ForceTxBreak(hDevice[obj->index], true); +} + +void serial_break_clear(serial_t *obj) +{ + adi_uart_ForceTxBreak(hDevice[obj->index], false); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + + MBED_ASSERT(obj); + + irq_handler = handler; + serial_irq_ids[obj->index] = id; +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c new file mode 100755 index 00000000000..b6ea83f1ed4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.c @@ -0,0 +1,256 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include "sleep_api.h" + +#ifdef DEVICE_SLEEP + +#include "adi_pwr.h" +#include "adi_pwr_def.h" +#include "adi_rtos_map.h" +#include "adi_ADuCM4050_device.h" +#include "sleep.h" + +/** + * Function to put processor into sleep (FLEXI mode only). + */ +static void go_into_WFI(const ADI_PWR_POWER_MODE PowerMode) +{ + uint32_t savedPriority; + uint16_t savedWDT; + uint16_t ActiveWDT; + uint32_t scrSetBits = 0u; + uint32_t scrClrBits = 0u; + uint32_t IntStatus = 0u; + + /* pre-calculate the sleep-on-exit set/clear bits */ + scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk; + + /* wfi without deepsleep or sleep-on-exit */ + scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + + ADI_ENTER_CRITICAL_REGION(); + + { /* these lines must be in a success-checking loop if they are not inside critical section */ + /* Uninterruptable unlock sequence */ + pADI_PMG0->PWRKEY = ADI_PMG_KEY; + + /* Clear the previous mode and set new mode */ + pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode ); + } + + /* Update the SCR (sleepdeep and sleep-on-exit bits) */ + SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits); + + /* save/restore current Base Priority Level */ + savedPriority = __get_BASEPRI(); + + /* assert caller's priority threshold (left-justified), currently set to 0, i.e. disable interrupt masking */ + __set_BASEPRI(0); + + /* save/restore WDT control register (which is not retained during hibernation) */ + savedWDT = pADI_WDT0->CTL; + + /* optimization: compute local WDT enable flag once (outside the loop) */ + ActiveWDT = ((savedWDT & BITM_WDT_CTL_EN) >> BITP_WDT_CTL_EN); + + /* SAR-51938: insure WDT is fully synchronized or looping on interrupts + in hibernate mode may lock out the sync bits. + + In hibernate mode (during which the WDT registers are not retained), + the WDT registers will have been reset to default values after each + interrupt exit and we require a WDT clock domain sync. + + We also need to insure a clock domain sync before (re)entering the WFI + in case an interrupt did a watchdog kick. + + Optimization: only incur WDT sync overhead (~100us) if the WDT is enabled. + */ + if (ActiveWDT > 0u) { + while ((pADI_WDT0->STAT & (uint32_t)(BITM_WDT_STAT_COUNTING | BITM_WDT_STAT_LOADING | BITM_WDT_STAT_CLRIRQ)) != 0u) { + ; + } + } + + __DSB(); /* bus sync to insure register writes from interrupt handlers are always complete before WFI */ + + /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */ + + /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt + that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not + dispatched until we get into the WFI. If that interrupt sneaks in prior to our getting to the + WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred. + */ + __WFI(); + + /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched. + This allows *pnInterruptOccurred to be set from any interrupt context. + */ + ADI_EXIT_CRITICAL_REGION(); + /* nop */ + ADI_ENTER_CRITICAL_REGION(); + + /* ...still within critical section... */ + + /* Restore previous base priority */ + __set_BASEPRI(savedPriority); + + /* conditionally, restore WDT control register. + avoid unnecessary WDT writes which will invoke a sync problem + described above as SAR-51938: going into hibernation with pending, + unsynchronized WDT writes may lock out the sync bits. + + Note: it takes over 1000us to sync WDT writes between the 26MHz and + 32kHz clock domains, so this write may actually impact the NEXT + low-power entry. + */ + if (ActiveWDT > 0u) { + pADI_WDT0->CTL = savedWDT; + } + + /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + + __DSB(); /* bus sync before re-enabling interrupts */ + + ADI_EXIT_CRITICAL_REGION(); +} + + +/** + * Function to enable/disable clock gating for the available clocks. + * PCLK overrides all the other clocks. + */ +void set_clock_gating(peripheral_clk_t eClk, int enable) +{ + uint32_t flag; + + switch (eClk) { + case PCLK: + flag = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF; + break; + case GPT0_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF; + break; + case GPT1_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF; + break; + case GPT2_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF; + break; + case I2C_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF; + break; + case GPIO_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF; + break; + case TIMER_RGB_CLOCK: + flag = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF; + break; + default: + return; + } + + // if enable, set the bit otherwise clear the bit + if (enable) { + pADI_CLKG0_CLK->CTL5 |= flag; + } else { + pADI_CLKG0_CLK->CTL5 &= (~flag); + } +} + + + +/** Send the microcontroller to sleep + * + * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the + * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates + * dynamic power used by the processor, memory systems and buses. The processor, peripheral and + * memory state are maintained, and the peripherals continue to work and can generate interrupts. + * + * The processor can be woken up by any internal peripheral interrupt or external pin interrupt. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + * + * This mode puts the processor into FLEXI mode however the peripheral clocks are not gated + * hence they are still active. + */ +void hal_sleep(void) +{ + // set to go into the FLEXI mode where the processor is asleep and all peripherals are + // still active + go_into_WFI(ADI_PWR_MODE_FLEXI); +} + + +/** Send the microcontroller to deep sleep + * + * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode + * has the same sleep features as sleep plus it powers down peripherals and clocks. All state + * is still maintained. + * + * The processor can only be woken up by an external interrupt on a pin or a watchdog timer. + * + * @note + * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored. + * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be + * able to access the LocalFileSystem + * + * This mode puts the processor into FLEXI mode and all the peripheral clocks are clock gated + * hence they are inactive until interrupts are generated in which case the processor is awaken + * from sleep. + */ +void hal_deepsleep(void) +{ + // set clock gating to all the peripheral clocks + set_clock_gating(PCLK, 1); + + // set to go into the FLEXI mode with peripheral clocks gated. + go_into_WFI(ADI_PWR_MODE_FLEXI); + + // when exiting, clear all peripheral clock gating bits. This is done to enable clocks that aren't + // automatically re-enabled out of sleep such as the GPIO clock. + pADI_CLKG0_CLK->CTL5 = 0; +} + +#endif // #ifdef DEVICE_SLEEP diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h new file mode 100755 index 00000000000..5ba806dbee5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/sleep.h @@ -0,0 +1,69 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#ifndef __SLEEP__H__ +#define __SLEEP__H__ + + +/* Enumeration to specify peripheral clock types: + General purpose timer clocks 0-2, + I2C clock, + GPIO clock, + RGB timer clock. + Peripheral clock (PCLK) controls all the peripheral clocks, including + all the clocks mentioned previously +*/ +typedef enum { + GPT0_CLOCK = 0, + GPT1_CLOCK, + GPT2_CLOCK, + I2C_CLOCK, + GPIO_CLOCK, + TIMER_RGB_CLOCK, + PCLK +} peripheral_clk_t; + + +/* Function to enable/disable clock gating for the available clocks. + PCLK overrides all the other clocks. +*/ +void set_clock_gating(peripheral_clk_t eClk, int enable); + +#endif // #ifndef __SLEEP_H__ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c new file mode 100755 index 00000000000..a52406889b9 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -0,0 +1,341 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include "mbed_assert.h" + +#include + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include "drivers/spi/adi_spi.h" + + + +#if defined(BUILD_SPI_MI_DYNAMIC) +#if defined(ADI_DEBUG) +#warning "BUILD_SPI_MI_DYNAMIC is defined. Memory allocation for SPI will be dynamic" +int adi_spi_memtype = 0; +#endif +#else +ADI_SPI_HANDLE spi_Handle0; +uint8_t spi_Mem0[ADI_SPI_MEMORY_SIZE]; +ADI_SPI_HANDLE spi_Handle1; +uint8_t spi_Mem1[ADI_SPI_MEMORY_SIZE]; +ADI_SPI_HANDLE spi_Handle2; +uint8_t spi_Mem2[ADI_SPI_MEMORY_SIZE]; +#if defined(ADI_DEBUG) +#warning "BUILD_SPI_MI_DYNAMIC is NOT defined. Memory allocation for SPI will be static" +int adi_spi_memtype = 1; +#endif +#endif + + + +/** Initialize the SPI peripheral + * + * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral + * @param[out] obj The SPI object to initialize + * @param[in] mosi The pin to use for MOSI + * @param[in] miso The pin to use for MISO + * @param[in] sclk The pin to use for SCLK + * @param[in] ssel The pin to use for SSEL + */ +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // determine the SPI to use + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + ADI_SPI_HANDLE *pSPI_Handle; + uint8_t *SPI_Mem; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + uint32_t nDeviceNum = 0; + ADI_SPI_CHIP_SELECT spi_cs = ADI_SPI_CS_NONE; + + +#if defined(BUILD_SPI_MI_DYNAMIC) + if (mosi == SPI0_MOSI) { + nDeviceNum = SPI_0; + } else if (mosi == SPI1_MOSI) { + nDeviceNum = SPI_1; + } else if (mosi == SPI2_MOSI) { + nDeviceNum = SPI_2; + } + pSPI_Handle = &obj->SPI_Handle; + obj->pSPI_Handle = pSPI_Handle; + SPI_Mem = obj->SPI_Mem; +#else + if (mosi == SPI0_MOSI) { + nDeviceNum = SPI_0; + pSPI_Handle = &spi_Handle0; + SPI_Mem = &spi_Mem0[0]; + } else if (mosi == SPI1_MOSI) { + nDeviceNum = SPI_1; + pSPI_Handle = &spi_Handle1; + SPI_Mem = &spi_Mem1[0]; + } else if (mosi == SPI2_MOSI) { + nDeviceNum = SPI_2; + pSPI_Handle = &spi_Handle2; + SPI_Mem = &spi_Mem2[0]; + } + obj->pSPI_Handle = pSPI_Handle; +#endif + + + obj->instance = pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->instance != NC); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } + + SystemCoreClockUpdate(); + SPI_Return = adi_spi_Open(nDeviceNum, SPI_Mem, ADI_SPI_MEMORY_SIZE, pSPI_Handle); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + + if (ssel != NC) { + if ( (ssel == SPI0_CS0) || (ssel == SPI1_CS0) || (ssel == SPI2_CS0)) { + spi_cs = ADI_SPI_CS0; + } else if ( (ssel == SPI0_CS1) || (ssel == SPI1_CS1) || (ssel == SPI2_CS1)) { + spi_cs = ADI_SPI_CS1; + } else if ( (ssel == SPI0_CS2) || (ssel == SPI1_CS2) || (ssel == SPI2_CS2)) { + spi_cs = ADI_SPI_CS2; + } else if ( (ssel == SPI0_CS3) || (ssel == SPI1_CS3) || (ssel == SPI2_CS3)) { + spi_cs = ADI_SPI_CS3; + } + + SPI_Return = adi_spi_SetChipSelect(*pSPI_Handle, spi_cs); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } + } +} + + +/** Release a SPI object + * + * TODO: spi_free is currently unimplemented + * This will require reference counting at the C++ level to be safe + * + * Return the pins owned by the SPI object to their reset state + * Disable the SPI peripheral + * Disable the SPI clock + * @param[in] obj The SPI object to deinitialize + */ +void spi_free(spi_t *obj) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_Close(SPI_Handle); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Configure the SPI format + * + * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode. + * The default bit order is MSB. + * @param[in,out] obj The SPI object to configure + * @param[in] bits The number of bits per frame + * @param[in] mode The SPI mode (clock polarity, phase, and shift direction) + * @param[in] slave Zero for master mode or non-zero for slave mode + * + ** Configure the data transmission format + * + * @param bits Number of bits per SPI frame (4 - 16) + * @param mode Clock polarity and phase mode (0 - 3) + * + * @code + * mode | POL PHA + * -----+-------- + * 0 | 0 0 + * 1 | 0 1 + * 2 | 1 0 + * 3 | 1 1 + * @endcode + + bool phase; + true : trailing-edge + false : leading-edge + + bool polarity; + true : CPOL=1 (idle high) polarity + false : CPOL=0 (idle-low) polarity + */ +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + bool master; + + master = !((bool_t)slave); + SPI_Handle = *obj->pSPI_Handle; + + SPI_Return = adi_spi_SetMasterMode(SPI_Handle, master); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Set the SPI baud rate + * + * Actual frequency may differ from the desired frequency due to available dividers and bus clock + * Configures the SPI peripheral's baud rate + * @param[in,out] obj The SPI object to configure + * @param[in] hz The baud rate in Hz + */ +void spi_frequency(spi_t *obj, int hz) +{ + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_SetBitrate(SPI_Handle, (uint32_t) hz); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return; + } +} + + +/** Write a byte out in master mode and receive a value + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] value The value to send + * @return Returns the value received during send + */ +int spi_master_write(spi_t *obj, int value) +{ + ADI_SPI_TRANSCEIVER transceive; + uint8_t TxBuf; + uint8_t RxBuf; + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + TxBuf = (uint8_t)value; + + transceive.pReceiver = &RxBuf; + transceive.ReceiverBytes = 1; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = &TxBuf; /* initialize data attributes */ + transceive.TransmitterBytes = 1; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ + + transceive.bDMA = false; + transceive.bRD_CTL = false; + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return 1; + } + + return((int)RxBuf); +} + + +/** Write a block out in master mode and receive a value + * + * The total number of bytes sent and recieved will be the maximum of + * tx_length and rx_length. The bytes written will be padded with the + * value 0xff. + * + * @param[in] obj The SPI peripheral to use for sending + * @param[in] tx_buffer Pointer to the byte-array of data to write to the device + * @param[in] tx_length Number of bytes to write, may be zero + * @param[in] rx_buffer Pointer to the byte-array of data to read from the device + * @param[in] rx_length Number of bytes to read, may be zero + * @param[in] write_fill Default data transmitted while performing a read + * @returns + * The number of bytes written and read from the device. This is + * maximum of tx_length and rx_length. + */ +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + ADI_SPI_TRANSCEIVER transceive; + ADI_SPI_HANDLE SPI_Handle; + ADI_SPI_RESULT SPI_Return = ADI_SPI_SUCCESS; + + transceive.pReceiver = (uint8_t*)rx_buffer; + transceive.ReceiverBytes = rx_length; /* link transceive data size to the remaining count */ + transceive.nRxIncrement = 1; /* auto increment buffer */ + transceive.pTransmitter = (uint8_t*)tx_buffer; /* initialize data attributes */ + transceive.TransmitterBytes = tx_length; /* link transceive data size to the remaining count */ + transceive.nTxIncrement = 1; /* auto increment buffer */ + + transceive.bDMA = false; + transceive.bRD_CTL = false; + SPI_Handle = *obj->pSPI_Handle; + SPI_Return = adi_spi_MasterReadWrite(SPI_Handle, &transceive); + if (SPI_Return) { + obj->error = SPI_EVENT_ERROR; + return -1; + } + else { + return((int)tx_length); + } +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c new file mode 100755 index 00000000000..cfab85645d5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/trng_api.c @@ -0,0 +1,135 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#if defined(DEVICE_TRNG) + +#include +#include +#include +#include "adi_rng_def.h" +#include "cmsis.h" +#include "trng_api.h" + +// Sampling counter values +// Prescaler: 0 - 10 +// LenReload: 0 - 4095 +#define TRNG_CNT_VAL 4095 +#define TRNG_PRESCALER 2 + +/* Data buffers for Random numbers */ +static uint32_t RngDevMem[(ADI_RNG_MEMORY_SIZE + 3)/4]; + +void trng_init(trng_t *obj) +{ + ADI_RNG_HANDLE RNGhDevice; + + // Open the device + adi_rng_Open(0,RngDevMem,sizeof(RngDevMem),&RNGhDevice); + + // Set sample length for the H/W RN accumulator + adi_rng_SetSampleLen(RNGhDevice, TRNG_PRESCALER, TRNG_CNT_VAL); + + // Disable buffering - single byte generation only + adi_rng_EnableBuffering(RNGhDevice, false); + + // Enable the TRNG + adi_rng_Enable(RNGhDevice, true); + + // Save device handle + obj->RNGhDevice = RNGhDevice; +} + +void trng_free(trng_t *obj) +{ + ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; + + adi_rng_Enable(RNGhDevice, false); + adi_rng_Close(RNGhDevice); +} + +int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) +{ + ADI_RNG_HANDLE RNGhDevice = obj->RNGhDevice; + bool bRNGRdy, bStuck; + uint32_t i; + volatile uint32_t nRandomNum; + ADI_RNG_RESULT result; + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)RNGhDevice; + + for (i = 0; i < length; i++) { + // Loop until the device has data to be read + do { + result = adi_rng_GetRdyStatus(RNGhDevice, &bRNGRdy); + if (result != ADI_RNG_SUCCESS) { + return -1; + } + } while (!bRNGRdy); + + // Check the STUCK bit to make sure the oscillator output isn't stuck + result = adi_rng_GetStuckStatus(RNGhDevice, &bStuck); + + // If the stuck bit is set, this means there may be a problem with RNG hardware, + // exit with an error + if ( (result != ADI_RNG_SUCCESS) || ((result == ADI_RNG_SUCCESS) && (bStuck)) ) { + // Clear the STUCK bit by writing a 1 to it + pDevice->pRNG->STAT |= BITM_RNG_STAT_STUCK; + return -1; + } + + // Read the RNG + result = adi_rng_GetRngData(RNGhDevice, (uint32_t*)(&nRandomNum)); + + if (result != ADI_RNG_SUCCESS) { + return -1; + } + + // Save the output + output[i] = (uint8_t)(nRandomNum & 0xFF); + } + + *output_length = length; + + // Clear nRandomNum on the stack before exiting + nRandomNum = 0; + + return 0; +} + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c new file mode 100755 index 00000000000..29c53a47169 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c @@ -0,0 +1,346 @@ +/******************************************************************************* + * Copyright (c) 2010-2017 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- + * INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF + * CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + +#include +#include +#include +#include +#include + +#ifndef BITM_TMR_RGB_CTL_EN +#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN +#endif + +typedef uint32_t timestamp_t; + +// defined in mbed_us_ticker_api.c which calls the ticker_irq_handler() routine +// defined in mbed_ticker_api.c +void us_ticker_irq_handler(void); + +static int us_ticker_inited = 0; + +static ADI_TMR_CONFIG tmrConfig, tmr2Config; + +static volatile uint32_t Upper_count = 0, largecnt = 0; + +static ADI_TMR_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {pADI_TMR0, pADI_TMR1, pADI_TMR2}; + +#if defined(__ADUCM302x__) +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn}; +#elif defined(__ADUCM4x50__) +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn}; +#else +#error TMR is not ported for this processor +#endif + + +/*---------------------------------------------------------------------------* + Local functions + *---------------------------------------------------------------------------*/ +static void GP1CallbackFunction(void *pCBParam, uint32_t Event, void * pArg) +{ + Upper_count++; +} + + +static uint32_t get_current_time(void) +{ + uint16_t tmrcnt0, tmrcnt1; + uint32_t totaltmr0, totaltmr1; + uint32_t uc1, tmrpend0, tmrpend1; + + do { + volatile uint32_t *ucptr = &Upper_count; + + /* + * Carefully coded to prevent race conditions. Do not make changes unless you understand all the + * implications. + * + * Note this function can be called with interrupts globally disabled or enabled. It has been coded to work in both cases. + * + * TMR0 and TMR1 both run from the same synchronous clock. TMR0 runs at 26MHz and TMR1 runs at 26/256MHz. + * TMR1 generates an interrupt every time it overflows its 16 bit counter. TMR0 runs faster and provides + * the lowest 8 bits of the current time count. When TMR0 and TMR1 are combined, they provide 24 bits of + * timer precision. i.e. (TMR0.CURCNT & 0xff) + (TMR1.CURCNT << 8) + * + * There are several race conditions protected against: + * 1. TMR0 and TMR1 are both read at the same time, however, on rare occasions, one will have incremented before the other. + * Therefore we read both timer counters, and check if the middle 8 bits match, if they don't then read the counts again + * until they do. This ensures that one or the other counters are stable with respect to each other. + * + * 2. TMR1.CURCNT and Upper_count racing. Prevent this by disabling the TMR1 interrupt, which stops Upper_count increment interrupt (GP1CallbackFunction). + * Then check pending bit of TMR1 to see if we missed Upper_count interrupt, and add it manually later. + * + * 3. Race between the TMR1 pend, and the TMR1.CURCNT read. Even with TMR1 interrupt disabled, the pend bit + * may be set while TMR1.CURCNT is being read. We don't know if the pend bit matches the TMR1 state. + * To prevent this, the pending bit is read twice, and we see if it matches; if it doesn't, loop around again. + * + * Note the TMR1 interrupt is enabled on each iteration of the loop to flush out any pending TMR1 interrupt, + * thereby clearing any TMR1 pend's. This have no effect if this routine is called with interrupts globally disabled. + */ + + NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // Prevent Upper_count increment + tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); + // Check if there is a pending interrupt for timer 1 + + __DMB(); // memory barrier: read GP0 before GP1 + + tmrcnt0 = adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CURCNT; // to minimize skew, read both timers manually + + __DMB(); // memory barrier: read GP0 before GP1 + + tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT; // read both timers manually + + totaltmr0 = tmrcnt0; // expand to u32 bits + totaltmr1 = tmrcnt1; // expand to u32 bits + + tmrcnt0 &= 0xff00u; + tmrcnt1 <<= 8; + + __DMB(); + + uc1 = *ucptr; // Read Upper_count + + tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); + // Check for a pending interrupt again. Only leave loop if they match + + NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]); // enable interrupt on every loop to allow TMR1 interrupt to run + } while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1)); + + totaltmr1 <<= 8; // Timer1 runs 256x slower + totaltmr1 += totaltmr0 & 0xffu; // Use last 8 bits of Timer0 as it runs faster + // totaltmr1 now contain 24 bits of significance + + if (tmrpend0) { // If an interrupt is pending, then increment local copy of upper count + uc1++; + } + + uint64_t Uc = totaltmr1; // expand out to 64 bits unsigned + Uc += ((uint64_t) uc1) << 24; // Add on the upper count to get the full precision count + + // Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs + + Uc *= 1290555u; // Divide total(1/26) << 25 + Uc >>= 25; // shift back. Fixed point avoid use of floating point divide. + // Compiler does this inline using shifts and adds. + + return Uc; +} + + +static void calc_event_counts(uint32_t timestamp) +{ + uint32_t calc_time, blocks, offset; + uint64_t aa; + + calc_time = get_current_time(); + offset = timestamp - calc_time; // offset in useconds + + if (offset > 0xf0000000u) // if offset is a really big number, assume that timer has already expired (i.e. negative) + offset = 0u; + + if (offset > 10u) { // it takes 10us to user timer routine after interrupt. Offset timer to account for that. + offset -= 10u; + } else + offset = 0u; + + aa = (uint64_t) offset; + aa *= 26u; // convert from 1MHz to 26MHz clock. todo scale for other clock freqs + + blocks = aa >> 7; + blocks++; // round + + largecnt = blocks>>1; // communicate to event_timer() routine +} + +static void event_timer() +{ + if (largecnt) { + uint32_t cnt = largecnt; + + if (cnt > 65535u) { + cnt = 0u; + } else + cnt = 65536u - cnt; + + tmr2Config.nLoad = cnt; + tmr2Config.nAsyncLoad = cnt; + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config); + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true); + } else { + us_ticker_irq_handler(); + } +} + + +/* + * Interrupt routine for timer 2 + * + * largecnt counts how many timer ticks should be counted to reach timer event. + * Each interrupt happens every 65536 timer ticks, unless there are less than 65536 ticks to count. + * In that case do the remaining timers ticks. + * + * largecnt is a global that is used to communicate between event_timer and the interrupt routine + * On entry, largecnt will be any value larger than 0. + */ +static void GP2CallbackFunction(void *pCBParam, uint32_t Event, void * pArg) +{ + if (largecnt >= 65536u) { + largecnt -= 65536u; + } else + largecnt = 0; + + if (largecnt < 65536u) { + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false); + event_timer(); + } +} + + +/*---------------------------------------------------------------------------* + us_ticker HAL APIs + *---------------------------------------------------------------------------*/ +void us_ticker_init(void) +{ + if (us_ticker_inited) { + return; + } + + us_ticker_inited = 1; + + /*--------------------- GP TIMER INITIALIZATION --------------------------*/ + + /* Set up GP0 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP0, NULL, NULL, false); + + /* Set up GP1 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP1, GP1CallbackFunction, NULL, true); + + /* Set up GP1 callback function */ + adi_tmr_Init(ADI_TMR_DEVICE_GP2, GP2CallbackFunction, NULL, true); + + /* Configure GP0 to run at 26MHz */ + tmrConfig.bCountingUp = true; + tmrConfig.bPeriodic = true; + tmrConfig.ePrescaler = ADI_TMR_PRESCALER_1; // TMR0 at 26MHz + tmrConfig.eClockSource = ADI_TMR_CLOCK_PCLK; // TMR source is PCLK (most examples use HFOSC) + tmrConfig.nLoad = 0; + tmrConfig.nAsyncLoad = 0; + tmrConfig.bReloading = false; + tmrConfig.bSyncBypass = true; // Allow x1 prescale: requires PCLK as a clk + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP0, tmrConfig); + + /* Configure GP1 to have a period 256 times longer than GP0 */ + tmrConfig.nLoad = 0; + tmrConfig.nAsyncLoad = 0; + tmrConfig.ePrescaler = ADI_TMR_PRESCALER_256; // TMR1 = 26MHz/256 + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP1, tmrConfig); + + /* Configure GP2 for doing event counts */ + tmr2Config.bCountingUp = true; + tmr2Config.bPeriodic = true; + tmr2Config.ePrescaler = ADI_TMR_PRESCALER_256; // TMR2 at 26MHz/256 + tmr2Config.eClockSource = ADI_TMR_CLOCK_PCLK; // TMR source is PCLK (most examples use HFOSC) + tmr2Config.nLoad = 0; + tmr2Config.nAsyncLoad = 0; + tmr2Config.bReloading = false; + tmr2Config.bSyncBypass = true; // Allow x1 prescale + adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config); + + + /*------------------------- GP TIMER ENABLE ------------------------------*/ + + /* Manually enable both timers to get them started at the same time + * + */ + adi_tmr_registers[ADI_TMR_DEVICE_GP0]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; + adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; +} + +uint32_t us_ticker_read() +{ + uint32_t curr_time; + + if (!us_ticker_inited) { + us_ticker_init(); + } + + curr_time = get_current_time(); + + return curr_time; +} + +void us_ticker_disable_interrupt(void) +{ + adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false); +} + +void us_ticker_clear_interrupt(void) +{ + NVIC_ClearPendingIRQ(TMR2_EVT_IRQn); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + + /* timestamp is when interrupt should fire. + * + * This MUST not be called if another timer event is currently enabled. + * + */ + calc_event_counts(timestamp); // use timestamp to calculate largecnt to control number of timer interrupts + event_timer(); // uses largecnt to initiate timer interrupts +} + +/** Set pending interrupt that should be fired right away. + * + * The ticker should be initialized prior calling this function. + * + * This MUST not be called if another timer event is currently enabled. + */ +void us_ticker_fire_interrupt(void) +{ + NVIC_SetPendingIRQ(TMR2_EVT_IRQn); +} + + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h new file mode 100755 index 00000000000..39158f2f9cf --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050.h @@ -0,0 +1,26 @@ +/* +** ADuCM4050.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef ADUCM4050_H +#define ADUCM4050_H + +#include +#include + +#define __CM4_REV 0x0001U /*!< CM4 Core Revision r0p1 */ +#define __MPU_PRESENT 1u /*!< MPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1u /*!< FPU present */ +#endif +#define __NVIC_PRIO_BITS 3u /*!< Number of Bits for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< 1 if different SysTick Config is used */ + +#include + +#include "system_ADuCM4050.h" + +#endif /* ADUCM4050_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h new file mode 100755 index 00000000000..8b6f35d28cf --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_cdef.h @@ -0,0 +1,18 @@ +/* +** ADuCM4050_cdef.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_CDEF_H +#define _WRAP_ADUCM4050_CDEF_H + +#include + +#include + +#include +#include + +#endif /* _WRAP_ADUCM4050_CDEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h new file mode 100755 index 00000000000..222e865aa41 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_def.h @@ -0,0 +1,34 @@ +/* +** ADuCM4050_def.h +** +** Copyright (C) 2016-2017 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_DEF_H +#define _WRAP_ADUCM4050_DEF_H + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Some comments are wrongly identified as code. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * The YODA-generated headers rely on more. The IAR compiler supports that. + */ +_Pragma("diag_suppress=Pm008,Pm009") +#endif /* __ICCARM__ */ + +#ifdef __IASMARM__ +/* Define masks to plain numeric literal for IAR assembler. */ +#define _ADI_MSK_3( mask, smask, type ) (mask) +#endif /* __IASMARM__ */ + +#include + +#ifdef __ICCARM__ +_Pragma("diag_default=Pm008,Pm009") +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM4050_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h new file mode 100755 index 00000000000..28b096bfc03 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_device.h @@ -0,0 +1,29 @@ +/* +** ADuCM4050_device.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_DEVICE_H +#define _WRAP_ADUCM4050_DEVICE_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm093 (rule 18.4): use of union - overlapping storage shall not be used. + * Unions are required by sys/adi_ADuCM4050_device.h. + */ +_Pragma("diag_suppress=Pm093") +#endif /* __ICCARM__ */ + +#include + +#ifdef __ICCARM__ +_Pragma("diag_default=Pm093") +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM4050_DEVICE_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h new file mode 100755 index 00000000000..6354190e978 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/ADuCM4050_typedefs.h @@ -0,0 +1,31 @@ +/* +** ADuCM4050_typedefs.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _WRAP_ADUCM4050_TYPEDEFS_H +#define _WRAP_ADUCM4050_TYPEDEFS_H + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions: + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Some comments are wrongly identified as code. + * + * Pm093 (rule 18.4): use of union - overlapping storage shall not be used. + * Unions are required by sys/adi_ADuCM4050_typedefs.h. + */ +_Pragma("diag_suppress=Pm008,Pm093") +#endif /* __ICCARM__ */ + +#include + +#ifdef __ICCARM__ +_Pragma("diag_default=Pm008,Pm093") +#endif /* __ICCARM__ */ + +#endif /* _WRAP_ADUCM4050_TYPEDEFS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c new file mode 100755 index 00000000000..ea473df8ded --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc.c @@ -0,0 +1,2371 @@ +/*! ***************************************************************************** + * @file: adi_adc.c + * @brief: ADC device driver global file. + * @details: This file contain the ADC device driver implementation. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/** @addtogroup ADC_Driver ADC Driver + * @{ + * @brief ADC Driver + * @details The ADC driver manages all instances of the ADC peripheral. + * @note - The application must include drivers/adc/adi_adc.h to use this driver. + * @note - This driver also requires the DMA driver. The application must include + the DMA driver sources to avoid link errors. + */ + +#ifndef ADI_ADC_C +/*! \cond PRIVATE */ +#define ADI_ADC_C + +/*============= I N C L U D E S =============*/ + + +/* Header file with definitions specific to ADC driver implementation */ + +/*============= A D C I M P L E M E N T A T I O N S O U R C E F I L E S =============*/ +#include +#include +#include +#include +#include +#include +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors + +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm152 +#endif /* __ICCARM__ */ + +#include "adi_adc_def.h" +#include "adi_adc_data.c" + +/*============== D E F I N E S ===============*/ +#ifdef ADI_DEBUG +#define ADI_ADC_INVALID_HANDLE(h) (AdcDevInfo[0].hDevice != (h)) +#endif + +/* Specify the maximum acquisition time, based on the width of the SAMPTIME field. */ +#define ADI_MAX_ACQUISITION_TIME (((uint32_t)BITM_ADC_CNV_TIME_SAMPTIME << BITP_ADC_CNV_TIME_SAMPTIME) + 1u) + +/* The 12bit maximum sample value */ +#define ADI_ADC_SAMPLE_MAX ((uint16_t)(4095u)) + +/*============= C O D E =============*/ + +/*============= D E B U G F U N C T I O N P R O T O T Y P E S =============*/ + +/* Override "weak" default binding in startup_*.c */ +/*! \cond PRIVATE */ +extern void ADC0_Int_Handler(void); +extern void DMA_ADC0_Int_Handler (void); + +/*! \endcond */ + +/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */ +/*============= L O C A L F U N C T I O N S P R O T O T Y P E S =============*/ +static uint16_t ReadOutReg(uint32_t nChannelNum); + +/* ADC management functions, based on transfer method */ +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 +static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); +#else +static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); +#endif + +/* Channel helper functions */ +static uint32_t GetNumChannels(uint32_t nChannels); +static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel); + +/* Buffer management functions */ +static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice); +static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice); +static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels); + +/* Internal configuration functions */ +static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable); +static void StaticConfiguration(ADI_ADC_DEVICE *pDevice); + +/*! \endcond */ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Opens an ADC device instance. + * + * @param [in] nDeviceNum Device number to open + * @param [in] pMemory Pointer to a #ADI_ADC_MEMORY_SIZE sized buffer to manage the device + * instance. + * @param [in] nMemorySize Size of the buffer to which "pMemory" points + * @param [out] phDevice Pointer to a location where ADC device handle is to be written. + * + * @return Status + * - #ADI_ADC_SUCCESS Call completed successfully + * - #ADI_ADC_INVALID_DEVICE_NUM [D] Invalid Device Number + * - #ADI_ADC_INSUFFICIENT_MEMORY [D] Memory passed is not sufficient + * - #ADI_ADC_IN_USE [D] ADC driver was already opened + */ +ADI_ADC_RESULT adi_adc_Open ( + uint32_t nDeviceNum, + void *pMemory, + uint32_t nMemorySize, + ADI_ADC_HANDLE *phDevice) +{ + ADI_INT_STATUS_ALLOC(); + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)pMemory; + +#ifdef ADI_DEBUG + if (nDeviceNum > (sizeof (AdcDevInfo)/sizeof(AdcDevInfo[0]))) + { + return ADI_ADC_INVALID_DEVICE_NUM; + } + + if (nMemorySize < ADI_ADC_MEMORY_SIZE) + { + return ADI_ADC_INSUFFICIENT_MEMORY; + } + + if (AdcDevInfo[nDeviceNum].hDevice != NULL) + { + return ADI_ADC_IN_USE; + } + + assert (ADI_ADC_MEMORY_SIZE >= sizeof (ADI_ADC_DEVICE)); +#endif /* ADI_DEBUG */ + + memset (pMemory, 0, nMemorySize); + + ADI_ENTER_CRITICAL_REGION(); + AdcDevInfo[nDeviceNum].hDevice = (ADI_ADC_HANDLE)pDevice; + pDevice->pReg = AdcDevInfo[nDeviceNum].pReg; + ADI_EXIT_CRITICAL_REGION(); + + /* Reset the ADC */ + pDevice->pReg->CFG = BITM_ADC_CFG_RST; + + /* Enable the IRQs */ + NVIC_ClearPendingIRQ(ADC0_EVT_IRQn); + NVIC_EnableIRQ(ADC0_EVT_IRQn); + + /* Initialize the registers to known value */ + pDevice->pReg->IRQ_EN = BITM_ADC_IRQ_EN_RDY | BITM_ADC_IRQ_EN_ALERT | BITM_ADC_IRQ_EN_OVF | BITM_ADC_IRQ_EN_CALDONE | BITM_ADC_IRQ_EN_CNVDONE; + + /* Do the static configuration */ + StaticConfiguration(pDevice); + + /* Create a semaphore for buffer management */ + SEM_CREATE(pDevice, "ADC Sem", ADI_ADC_ERR_RTOS); + + /* Set the default FIFO Manage function */ +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 + pDevice->pfManageFifo = DmaFIFOManage; + /* Make sure the DMA controller and its SRAM based descriptors are initialized */ + adi_dma_Init(); +#else + pDevice->pfManageFifo = InterruptFIFOManage; +#endif + + /* Return the device handle back to the application */ + *phDevice = AdcDevInfo[nDeviceNum].hDevice; + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Close the given device instance + * + * @param [in] hDevice Handle to the device instance + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully closed the device + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle based to the function + */ +ADI_ADC_RESULT adi_adc_Close (ADI_ADC_HANDLE hDevice) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + ADI_ADC_RESULT eResult; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + /* Power down the device */ + if ((eResult = adi_adc_PowerUp (hDevice, false)) != ADI_ADC_SUCCESS) { + return eResult; + } + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 + /* Close the DMA if configured */ + NVIC_DisableIRQ(DMA0_CH24_DONE_IRQn); +#endif /* ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 */ + + /* Disable the ADC interrupt */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + /* Destroy the semaphore */ + SEM_DELETE(pDevice, ADI_ADC_ERR_RTOS); + + /* Finally, zero the device */ + AdcDevInfo[0].hDevice = (NULL); + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Power up ADC + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bPowerUp 'true' to power up and 'false' to power down the ADC. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully closed the device + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain PCLK which is needed to calculate + * powerup values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nClock = 0u; + uint16_t nCount = 0u; + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bPowerUp == true) + { + if (IS_NOT_IN_ANY_STATE(ADC_STATUS_POWERED_UP)) + { + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* We need the cycles equivelent of 20us entered here, based on the PCLK + * clock. nClock is the frequency of the PCLK, 50000 is the equivalent frequency of 20us + * e.g. 26,000,000Hz, 0.00002s produces 520 cycles.*/ + nCount = (uint16_t)(nClock / 50000u); + + /* Powering up ADC */ + pDevice->pReg->CFG |= BITM_ADC_CFG_PWRUP; + + /* Set ADC_PWRUP.WAIT bits for the new count */ + pDevice->pReg->PWRUP = (uint16_t)(((uint32_t)nCount << BITP_ADC_PWRUP_WAIT) & BITM_ADC_PWRUP_WAIT); + + SET_STATE(ADC_STATUS_POWERED_UP); + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + } + } + else + { + if (IS_IN_STATE(ADC_STATUS_POWERED_UP)) + { + /* If the ADC system is up then disable the ADC subsystem */ + if ( IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN) ) + { + eResult = adi_adc_EnableADCSubSystem (hDevice, false); + if (eResult != ADI_ADC_SUCCESS) + { + return eResult; + } + } + + /* Powering down ADC */ + pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_PWRUP)); + CLR_STATE(ADC_STATUS_POWERED_UP); + } + } + + return eResult; +} + + +/** + * @brief Registering a callback function + * + * @param [in] hDevice Handle to the device instance + * @param [in] pfCallback Function pointer to callback function. Passing a NULL pointer will + * unregister the call back function. + * @param [in] pCBParam Call back function parameter + * + * @details This function registers a call back function. Registered function will be called when + * the given computation is over. It will also be called when the digital comparitor is being + * used and a limit has been broken. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully registerd the callback + * - #ADI_ADC_INVALID_SEQUENCE [D] Callback cannot be registered when ADC is enabled for sampling. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_RegisterCallback ( + ADI_ADC_HANDLE hDevice, + ADI_CALLBACK pfCallback, + void *pCBParam) +{ + ADI_INT_STATUS_ALLOC(); + + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + +#endif /* ADI_DEBUG */ + + ADI_ENTER_CRITICAL_REGION(); + pDevice->pfCallback = pfCallback; + pDevice->pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Enable/Disables the ADC Subsystem + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to Disable` + * + * @details Enables/Disables the ADC Subsystem. The ADC subsystem need to be enabled before using the ADC + * for sampling the signal. The driver should check whether the ADC is ready by calling adi_adc_IsReady + * API before continuing. If internal reference buffer is used as voltage reference then application + * has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled the ADC subsystem + * - #ADI_ADC_INVALID_SEQUENCE [D] Can only be called if the ADC is powered up, + * and cannot be disabled when sampling or using + * the camparator. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + */ +ADI_ADC_RESULT adi_adc_EnableADCSubSystem ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_POWERED_UP)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (bEnable == true) { + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + } else { + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= BITM_ADC_CFG_EN; + SET_STATE(ADC_STATUS_SUB_SYSTEM_EN); + } + else + { + pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_EN); + CLR_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_SUB_SYSTEM_READY); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Returns whether the ADC Subsystem is ready + * + * @param [in] hDevice Handle to the device instance + * + +* @param [in] pbReady Pointer to a bool variable. The variable will be set to 'true' if the ADC is ready else 'false' + * + * @details Returns whether the ADC is ready for sampling. This API should be called after enabling the ADC sub-system using + * adi_adc_EnableADCSubSystem API. If internal reference buffer is used as voltage reference then application + * has to wait at least 3.5ms after enabling irrespective of whether adi_adc_IsReady returns ready or not. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the ready status + * - #ADI_ADC_INVALID_SEQUENCE [D] Cannot be called if the subsystem is not enabled. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the function + * - #ADI_ADC_NULL_POINTER [D] pbReady is NULL + */ + +ADI_ADC_RESULT adi_adc_IsReady ( + ADI_ADC_HANDLE hDevice, + bool *pbReady +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (pbReady == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_READY)) + { + *pbReady = true; + } + else + { + *pbReady = false; + } + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the Voltage Reference source + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eVrefSrc Voltage Reference source to be used + * + * @details The API can be used to select the voltage reference to be used by the ADC. This option need to be + * set before enabling the ADC subsystem. + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully set the Vref source + * - #ADI_ADC_INVALID_PARAMETER Vref source enum passed is invalid. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle based to the function. + * - #ADI_ADC_INVALID_SEQUENCE [D] VREF cannot be changed once the ADC subsystem is enabled. + */ + +ADI_ADC_RESULT adi_adc_SetVrefSource ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_VREF_SRC eVrefSrc) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + pDevice->pReg->CFG &= (uint16_t)(~(BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL | BITM_ADC_CFG_VREFVBAT)); + + switch (eVrefSrc) + { + case ADI_ADC_VREF_SRC_INT_1_25_V: + pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL; + break; + + case ADI_ADC_VREF_SRC_INT_2_50_V: + pDevice->pReg->CFG |= BITM_ADC_CFG_REFBUFEN; + break; + + case ADI_ADC_VREF_SRC_VBAT: + pDevice->pReg->CFG |= BITM_ADC_CFG_VREFVBAT; + break; + + case ADI_ADC_VREF_SRC_EXT: + break; + + default: + eResult = ADI_ADC_INVALID_PARAMETER; + break; + } + + return eResult; +} + + +/** + * @brief Enable/Disable Current Sink + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to Disable current sink + * + * @details If the volatage reference is required to sink current then this option need to be enabled. + * The ADC subsystem has the capability to sink upto 50uA at Vref of 1.25V and 100uA at Vref of 2.5V + + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled sink + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + */ + +ADI_ADC_RESULT adi_adc_SinkEnable ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= BITM_ADC_CFG_SINKEN; + } + else + { + pDevice->pReg->CFG &= (uint16_t)~(BITM_ADC_CFG_SINKEN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Start the ADC calibration + * + * @param [in] hDevice Handle to the device instance + * + * @details The call to this function initiate calibration of the ADC. The user is recommended to do calibration of the ADC after + * enabling the ADC subsystem. The status of the calibration can be checked using adi_adc_IsCalibrationDone API. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully initiated calibration of ADC + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Sampling cannot be enabled if the ADC is enabled. + */ +ADI_ADC_RESULT adi_adc_StartCalibration(ADI_ADC_HANDLE hDevice) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + /* Calibration cannot be done when ADC is processing the buffers */ + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + +#endif /* ADI_DEBUG */ + + /* Clear the calibration done state */ + CLR_STATE(ADC_STATUS_CALIBRATION_DONE); + + /* Clear ADC_STAT.CALDONE */ + pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE; + + /* Set the state as calibration enabled. This state will be cleared when we get the + calibration done interrupt. */ + SET_STATE (ADC_STATUS_CALIBRATION_EN); + + /* Start ADC calibration */ + pDevice->pReg->CFG |= BITM_ADC_CFG_STARTCAL; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Returns the status of the calibration which was initiated. + * + * @param [in] hDevice Handle to the device instance + * + * @param [out] pbCalibrationDone Pointer to the location to which the status of calibration is written. + * 'true' if the calibration started by call to is done else 'false' + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the status of ADC calibration. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pbCalibrationDone is NULL + */ + +ADI_ADC_RESULT adi_adc_IsCalibrationDone ( + ADI_ADC_HANDLE hDevice, + bool *pbCalibrationDone) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (pbCalibrationDone == NULL) + { + return ADI_ADC_NULL_POINTER; + } +#endif /* ADI_DEBUG */ + + /* The driver will check whether the driver is set to calibration done state. This state will + * be set in the driver when the calibration done interrupt is received by the driver + */ + if (IS_IN_STATE(ADC_STATUS_CALIBRATION_DONE)) + { + *pbCalibrationDone = true; + } + else + { + *pbCalibrationDone = false; + } + + return ADI_ADC_SUCCESS; +} + + + +/** + * @brief Set the acquisition time of ADC in ADC clock cycles + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nAcqTimeInAClkCycles Acquisition time in ADC clock cycles. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the acquisition time of ADC + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Acquisition time cannot be set when the ADC is enabled for sampling + * - #ADI_ADC_INVALID_PARAMETER [D] nAcqTimeInAClkCycles is not in the valid range + */ +ADI_ADC_RESULT adi_adc_SetAcquisitionTime ( + ADI_ADC_HANDLE hDevice, + uint32_t nAcqTimeInAClkCycles + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + /* A valid range is 1u to the width of the SAMPTIME field + 1. */ + if ((nAcqTimeInAClkCycles == 0u) || (nAcqTimeInAClkCycles > (ADI_MAX_ACQUISITION_TIME))) + { + return ADI_ADC_INVALID_PARAMETER; + } + +#endif /* ADI_DEBUG */ + + /* Acquisition phase is (ADC_CNV_TIME.SAMPTIME + 1) ACLK cycles */ + nCnvTime = pDevice->pReg->CNV_TIME; + nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_SAMPTIME); + nCnvTime |= (uint16_t)((nAcqTimeInAClkCycles - ((uint32_t)1u)) << BITP_ADC_CNV_TIME_SAMPTIME); + pDevice->pReg->CNV_TIME = nCnvTime; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the delay time of ADC in ADC cycles for multi iteration mode. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nDelayInAClkCycles Delay time in ADC clock cycles. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set delay time + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] nDelayInAClkCycles is not in the valid range + */ +ADI_ADC_RESULT adi_adc_SetDelayTime ( + ADI_ADC_HANDLE hDevice, + uint32_t nDelayInAClkCycles) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (nDelayInAClkCycles > (BITM_ADC_CNV_TIME_DLY >> BITP_ADC_CNV_TIME_DLY)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nCnvTime = pDevice->pReg->CNV_TIME; + nCnvTime &= (uint16_t)(~BITM_ADC_CNV_TIME_DLY); + nCnvTime |= (uint16_t)(nDelayInAClkCycles << BITP_ADC_CNV_TIME_DLY); + pDevice->pReg->CNV_TIME = nCnvTime; + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Set the resolution of ADC. he default resolution of ADC is 12-bit and the ADC increases the resolution + * by oversampling. Averaging will be disabled when the resolution is more than 12-bits. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eResolution Enum of ADC resolution + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the resolution of the ADC. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_SEQUENCE [D] Resolution cannot be changed when the ADC is enabled for sampling + * - #ADI_ADC_INVALID_STATE [D] Resolution cannot be changed from 12-bit if averaging is enabled + * - #ADI_ADC_INVALID_PARAMETER eResolution parameter passed is invalid. + */ +ADI_ADC_RESULT adi_adc_SetResolution ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_RESOLUTION eResolution) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nFactor; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN) && (eResolution != ADI_ADC_RESOLUTION_12_BIT)) + { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + switch (eResolution) + { + case ADI_ADC_RESOLUTION_12_BIT: + pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_OS); + if (IS_NOT_IN_STATE(ADC_STATUS_AVGERAGING_EN)) { + pDevice->pReg->AVG_CFG = 0u; + } + CLR_STATE(ADC_STATUS_OVERSAMPLING_EN); + break; + + case ADI_ADC_RESOLUTION_13_BIT: + case ADI_ADC_RESOLUTION_14_BIT: + case ADI_ADC_RESOLUTION_15_BIT: + case ADI_ADC_RESOLUTION_16_BIT: + /* factor = 0x02 for 13-bit + 0x08 for 14-bit + 0x20 for 15-bit + 0x80 for 16-bit */ + nFactor = (uint16_t)1u << (((uint16_t)eResolution * 2u) - ((uint16_t)1u)); + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN + | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR); + SET_STATE(ADC_STATUS_OVERSAMPLING_EN); + + break; + + default: + return ADI_ADC_INVALID_PARAMETER; + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Enable Averaging for all ADC channels. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nAveragingSamples Specifies the number of samples used for averaging. The valid value is between 1-256, in the steps of power of 2. 1 is for disabling averaging. + * The averaging require that the resolution of ADC is 12-bit. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled averaging. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Averaging cannot be enabled if the resolution is above 12bits + * - #ADI_ADC_INVALID_PARAMETER [D] nAveragingSamples parameter passed is invalid. + */ +ADI_ADC_RESULT adi_adc_EnableAveraging ( + ADI_ADC_HANDLE hDevice, + uint16_t nAveragingSamples + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nFactor; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if ((nAveragingSamples == 0u) || (nAveragingSamples > 256u) + /* Or nAveragingSamples is not a power of 2 */ + || ((nAveragingSamples & (nAveragingSamples - 1u)) != 0u)) + { + return ADI_ADC_INVALID_PARAMETER; + } + if (IS_IN_STATE(ADC_STATUS_OVERSAMPLING_EN)) + { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + /* Disable averaging */ + if (nAveragingSamples == 1u) + { + pDevice->pReg->AVG_CFG &= (uint16_t)(~BITM_ADC_AVG_CFG_EN); + CLR_STATE(ADC_STATUS_AVGERAGING_EN); + } + else + { + nFactor = nAveragingSamples >> 1; + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_EN | (uint16_t)(nFactor << BITP_ADC_AVG_CFG_FACTOR); + SET_STATE(ADC_STATUS_AVGERAGING_EN); + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure low limit for an ADC channel when it is used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the low limit of the digital comparator + * + * @param [in] nLowLimit The low limit of the digital comparator. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured set the low limit. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetLowLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nLowLimit + ) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nLowLimit > (BITM_ADC_LIM0_LO_VALUE >> BITP_ADC_LIM0_LO_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_LO_VALUE)) | + (uint16_t)(nLowLimit << BITP_ADC_LIM0_LO_VALUE); + + /* Now enable this channel comparitor - unused until the comparitor is enabled */ + pDevice->ComparitorLo |= (1u << nChannelNum); + } + else { + pDevice->ComparitorLo &= ~(1u << nChannelNum); + } + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure high limit for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the high limit of the digital comparator + * + * @param [in] nHighLimit The high limit of the digital comparator. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully set the high limit + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetHighLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHighLimit) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nHighLimit > (BITM_ADC_LIM0_HI_VALUE >> BITP_ADC_LIM0_HI_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + /* Set the given high value - only relevant if the limit is enabled. */ + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_LIM0_HI_VALUE)) + | (uint16_t)(nHighLimit << BITP_ADC_LIM0_HI_VALUE); + + /* Now enable this channel comparitor - unused until the comparitor is enabled */ + pDevice->ComparitorHi |= (1u << nChannelNum); + } + else { + pDevice->ComparitorHi &= ~(1u << nChannelNum); + } + } + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure hysteresis for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] bEnable Enable or disable the hysteresis of the digital comparator + * + * @param [in] nHysteresis The hysteresis to be used. If bEnable is false, this paramter is omitted. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured the comparator + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetHysteresis ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHysteresis) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3 + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nHysteresis > (BITM_ADC_HYS0_VALUE >> BITP_ADC_HYS0_VALUE)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + if (bEnable == true) { + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_VALUE)) + | (uint16_t)(nHysteresis << BITP_ADC_HYS0_VALUE); + + /* Now enable this channel hysteresis - unused until the comparitor is enabled */ + pDevice->ComparitorHys |= (1u << nChannelNum); + } + else { + pDevice->ComparitorHys &= ~(1u << nChannelNum); + } + } + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] eChannel The ADC channel for which to configure the comparator + * + * @param [in] nNumMonitorCycles Number of Monitor cycles before giving interrupt + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully configured the comparator + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Parameters passed is not valid. + */ +ADI_ADC_RESULT adi_adc_SetNumMonitorCycles( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + uint32_t nNumMonitorCycles) +{ + #ifdef ADI_DEBUG + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#endif /* ADI_DEBUG */ + + static volatile uint16_t* pRegister[4] = { + pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3 + }; + int32_t nChannelNum = 0; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nNumMonitorCycles > (BITM_ADC_HYS0_MONCYC >> BITP_ADC_HYS0_MONCYC)) || (nChannelNum < 0) || (nChannelNum > 3)) + { + return ADI_ADC_INVALID_PARAMETER; + } +#endif /* ADI_DEBUG */ + + nChannelNum = nGetChannelNumber(eChannel); + + if((nChannelNum >= 0) && (nChannelNum <= 3)) { + *pRegister[nChannelNum] = (uint16_t)(*pRegister[nChannelNum] & (uint16_t)(~BITM_ADC_HYS0_MONCYC)) + | (uint16_t)(nNumMonitorCycles << BITP_ADC_HYS0_MONCYC); + } + return ADI_ADC_SUCCESS; +} + + + +/** + * @brief Enable/Disable digital comparator for the given channel(s) + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnableComparator 'true' to Enable and 'false' to disable + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled digital comparator for the given channels + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Digital comparator cannot be enabled if sampling resolution is more than 12-bit or + * averaging is enabled. Comparator for a given channel cannot be enbaled if none of the limits + * are enabled for the given channel. + * - #ADI_ADC_INVALID_SEQUENCE [D] Comparator cannot be enabled when ADC is enabled for sampling. + * - #ADI_ADC_INVALID_OPERATION [D] Comparator require callback to be registered. + */ +ADI_ADC_RESULT adi_adc_EnableDigitalComparator ( + ADI_ADC_HANDLE hDevice, + bool bEnableComparator +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_AVGERAGING_EN | ADC_STATUS_OVERSAMPLING_EN)) + { + return ADI_ADC_INVALID_STATE; + } + + if (pDevice->pfCallback == NULL) { + return ADI_ADC_INVALID_OPERATION; + } + + if (bEnableComparator == true) { + if((pDevice->ComparitorHi | pDevice->ComparitorLo) == 0u) { + return ADI_ADC_INVALID_STATE; + } + } +#endif /* ADI_DEBUG */ + + EnableComparator(pDevice, bEnableComparator); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Submit the ADC buffer for processing to the ADC Module + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pBuffer Pointer to the #ADI_ADC_BUFFER structure which contains details + * of the buffers required by the driver. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully submitted the buffer + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pBuffer is NULL + * - #ADI_ADC_INVALID_BUFFER [D] Buffer parameters are invalid. + * + * @note The driver will take ownership of the ADI_ADC_BUFFER structure passed to the driver. + * The application has to make sure the structure is not used and it's scope is valid till + * the structure is returned back to the application. + */ +ADI_ADC_RESULT adi_adc_SubmitBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER* pBuffer +) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nNumChannels = 0u; + + ADC_INT_BUFFER* pIntBuffer; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pBuffer == NULL) { + return ADI_ADC_NULL_POINTER; + } + if ((pBuffer->nChannels == 0u) || (pBuffer->pDataBuffer == NULL) || (pBuffer->nNumConversionPasses == 0u)) + { + return ADI_ADC_INVALID_BUFFER; + } +#endif /* ADI_DEBUG */ + + nNumChannels = GetNumChannels(pBuffer->nChannels); + + pIntBuffer = &pDevice->s_Buffer; + + pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN; + pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK; + if (pBuffer->nNumConversionPasses == 1u) + { + pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN; + } + pIntBuffer->pUserBuffer = pBuffer; + pIntBuffer->pCurDataBuffer = pBuffer->pDataBuffer; + pIntBuffer->nNumSamplesRemaining = nNumChannels * pBuffer->nNumConversionPasses; + pIntBuffer->nChannels = pBuffer->nChannels; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT); + + return ADI_ADC_SUCCESS; +} + +/** + * @brief Get a processed buffer from the ADC Driver. This function is a blocking call and will only return + * once it has the buffer or if any error occurred. If a callback is registered then any call to this + * function will fail. + * + * @param [in] hDevice Handle to the device instance. + * @param [out] ppBuffer Pointer to a pointer to ADI_ADC_BUFFER structure. The returned pointer + * to ADI_ADC_BUFFER is written here. + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the buffer + * - #ADI_ADC_INVALID_STATE adi_adc_GetBuffer cannot be called when no buffer is given to the driver for processing. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_OPERATION [D] adi_adc_GetBuffer cannot be used when callback is registered. + * - #ADI_ADC_NULL_POINTER [D] ppBuffer is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] adi_adc_GetBuffer cannot be used if non-blocking is not enabled. + * + */ +ADI_ADC_RESULT adi_adc_GetBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER **ppBuffer) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (ppBuffer == NULL) { + return ADI_ADC_NULL_POINTER; + } + if (pDevice->pfCallback != NULL) { + return ADI_ADC_INVALID_OPERATION; + } + if (IS_NOT_IN_STATE(ADC_STATUS_NON_BLOCKING_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if (pDevice->s_Buffer.pUserBuffer == NULL) { + return ADI_ADC_INVALID_STATE; + } + + /* Wait for read completion */ + SEM_PEND(pDevice, ADI_ADC_ERR_RTOS); + + if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) { + eADCresult = ADI_ADC_BUFFER_OVERFLOW; + } + *ppBuffer = pDevice->s_Buffer.pUserBuffer; + pDevice->s_Buffer.pUserBuffer = NULL; + CLR_STATE(ADC_STATUS_NON_BLOCKING_EN); + + return eADCresult; +} + +/** + * @brief Enable/Disable ADC for sampling + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] bEnable 'true' to Enable and 'false' to disable + * + * @details + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully Enabled or disabled ADC for sampling + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_STATE [D] Non-blocking cannot be enabled if comparator is enabled or any blocking API is in progress. + */ +ADI_ADC_RESULT adi_adc_Enable ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) { + /* Set the driver to be in non-blocking mode */ + SET_STATE(ADC_STATUS_NON_BLOCKING_EN); + + /* Enable the IRQs */ + NVIC_EnableIRQ(ADC0_EVT_IRQn); + + /* Try to submit possible number of buffers */ + InitBufferProcessing(pDevice); + } else { + /* Disble the IRQs */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + /* Abort any transaction if present */ + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ABORT); + + CLR_STATE(ADC_STATUS_NON_BLOCKING_EN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief This function return whether a filled buffer is available to be returned to the user. + * If this function return true, then a call to adi_adc_GetBuffer will not block + * + * @param [in] hDevice Handle to the device instance. + * @param [out] pbIsBufferAvailable Pointer to a bool variable to which the availability of buffer will be written. + * The variable will be set to 'true' if buffer is available else 'false' + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully returned the status of the buffer availability + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pbIsBufferAvailable is valid + * - #ADI_ADC_INVALID_OPERATION [D] adi_adc_IsBufferAvailable cannot be used when callback is registered. + * + */ +ADI_ADC_RESULT adi_adc_IsBufferAvailable ( + ADI_ADC_HANDLE hDevice, + bool *pbIsBufferAvailable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pbIsBufferAvailable == NULL) + { + return ADI_ADC_NULL_POINTER; + } + if (pDevice->pfCallback != NULL) { + return ADI_ADC_INVALID_OPERATION; + } +#endif /* ADI_DEBUG */ + + if(IS_IN_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) + { + *pbIsBufferAvailable = false; + } + else + { + *pbIsBufferAvailable = true; + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Sample the given channels for the given number of conversion passes and put it into the given buffer. This function only return after + * the channels are sampled the given number of conversion times or if any error occurs. + * + * @param [in] hDevice Handle to the device instance + * + * @param [in] nChannels Channels to sample. Should be an ORed value of ADI_ADC_CHANNEL types. + * + * @param [in] nNumConversionPasses Number of conversion passes. In one conversion pass, the ADC will sample all the given channel(s) once. + * + * @param [in] pBuffer Pointer to the buffer to which the sampled data is put. + * + * @param [in] nBuffLength Length of the buffer. The length of the buffer should be at least + * 2*(Num of Channels)*nNumConversionPasses bytes. + * + * @details Sample all the given channels for the given number of conversion passes and put the samples values into the given buffers. + * The channels will be sampled starting from the lower number. This function only return after + * the channels are sampled the given number of conversion times or if any error occurs. + * + * @return Status + * - #ADI_ADC_SUCCESS Succesfully Enabled or disabled ADC for sampling + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_INVALID_PARAMETER [D] Some parameter passed to the function is not valid + * - #ADI_ADC_INVALID_SEQUENCE [D] adi_adc_ReadChannels cannot be called if camparator is enabled or if + * Non-blocking is enabled or if another blocking API is in progress. + */ + +ADI_ADC_RESULT adi_adc_ReadChannels ( + ADI_ADC_HANDLE hDevice, + uint32_t nChannels, + uint32_t nNumConversionPasses, + void *pBuffer, + uint32_t nBuffLength) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint32_t nNumChannels = 0u; + ADI_ADC_RESULT eADCresult = ADI_ADC_SUCCESS; + + ADC_INT_BUFFER* pIntBuffer; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if ((nChannels == 0u) || (nNumConversionPasses == 0u) || (pBuffer == NULL)) + { + return ADI_ADC_INVALID_PARAMETER; + } + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + nNumChannels = GetNumChannels(nChannels); + + if (nBuffLength < ((nNumChannels * sizeof(uint16_t)) * nNumConversionPasses)) + { + return ADI_ADC_INSUFFICIENT_MEMORY; + } + + /* Clear ADC status */ + pDevice->pReg->STAT = 0xFFFFu; + + /* Set the driver to be in blocking mode */ + SET_STATE(ADC_STATUS_BLOCKING_EN); + + /* Get the buffer */ + pIntBuffer = &pDevice->s_Buffer; + + pIntBuffer->nConfig = ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN; + if (nNumConversionPasses == 1u) { + pIntBuffer->nConfig |= ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN; + } + + pIntBuffer->nStatus = ADC_BUFFER_STATUS_OK; + pIntBuffer->pUserBuffer = NULL; + pIntBuffer->pCurDataBuffer = pBuffer; + pIntBuffer->nNumSamplesRemaining = nNumChannels * nNumConversionPasses; + pIntBuffer->nChannels = nChannels; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INIT); + + InitBufferProcessing(pDevice); + + /* Wait for read completion */ + SEM_PEND(pDevice, ADI_ADC_ERR_RTOS); + + if ((uint16_t)(pDevice->s_Buffer.nStatus & ADC_BUFFER_STATUS_OVERFLOW) != 0u) { + eADCresult = ADI_ADC_BUFFER_OVERFLOW; + } + + /* Driver is no longer in blocking mode */ + CLR_STATE(ADC_STATUS_BLOCKING_EN); + + /* Enable the IRQs */ + NVIC_DisableIRQ(ADC0_EVT_IRQn); + + return eADCresult; +} + + +/** + * @brief Returns the battery voltage. + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] nRefVoltage Reference voltage in fixed point(16.16) format. + * + * @param [out] pnBatVoltage Pointer to a variable to which the voltage of the battery will be written. + * The battery voltage will be in fixed point (16.16) format. + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the battery voltage. + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain CLK which is needed to calculate + * voltage conversion timing values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pnBatVoltage is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] ADC sub system should be up and ADC should be free for getting the battery voltage. + */ +ADI_ADC_RESULT adi_adc_GetBatteryVoltage ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + uint32_t *pnBatVoltage) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nConvTimeBackup; + uint16_t nAvgCfgBackup; + uint32_t nAdcValue = 0u; + uint32_t nClock = 0u; + uint32_t nACLKDIVCNT; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pnBatVoltage == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN |ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif /* ADI_DEBUG */ + + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* Take the backup of registers that need to be changed */ + nConvTimeBackup = pDevice->pReg->CNV_TIME; + nAvgCfgBackup = pDevice->pReg->AVG_CFG; + + /* Set the required value in the registers. */ + nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + + /* Calculate the number of cycles required for conversion. + * The conversion time required is 500ns = 2000000Hz + */ + nClock = nClock/nACLKDIVCNT; /* nClock = ACLK frequency Hz */ + pDevice->pReg->CNV_TIME = (uint16_t)((nClock/2000000u) + ((uint16_t)1u)); + pDevice->pReg->AVG_CFG = 0u; + + /* Clear the battery done status */ + pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE; + + /* Clear the battery done state */ + CLR_STATE(ADC_STATUS_BATTERY_DONE); + + /* Set the registers */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_BAT); + + /* Wait for the Battery done status */ + while (IS_NOT_IN_STATE(ADC_STATUS_BATTERY_DONE)) { ; } + + /* Clear the conversion register */ + pDevice->pReg->CNV_CFG = 0u; + + /* Restore the changed registers */ + pDevice->pReg->CNV_TIME = nConvTimeBackup; + pDevice->pReg->AVG_CFG = nAvgCfgBackup; + + /* Calculate the battery voltage */ + + /* From HRM: converting ADC result to battery voltage, following calculations should be done: + * VBAT = 4 * (adc_out) * Vref / (2^12 - 1) */ + nAdcValue = pDevice->pReg->BAT_OUT; + *pnBatVoltage = (4u * nAdcValue * nRefVoltage) / ADI_ADC_SAMPLE_MAX; + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + + return eResult; +} +/** + * @brief Enable or disable the temperature sensor + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] bEnable 'true' to enable and 'false' to disable the temperature sensor + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully enabled/disabled the temperature sensor + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + */ +ADI_ADC_RESULT adi_adc_EnableTemperatureSensor ( + ADI_ADC_HANDLE hDevice, + bool bEnable) +{ + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } +#endif /* ADI_DEBUG */ + + if (bEnable == true) + { + pDevice->pReg->CFG |= (uint16_t)BITM_ADC_CFG_TMPEN; + SET_STATE(ADC_STATUS_TEMP_SENSOR_EN); + } + else + { + pDevice->pReg->CFG &= (uint16_t)(~BITM_ADC_CFG_TMPEN); + CLR_STATE(ADC_STATUS_TEMP_SENSOR_EN); + } + + return ADI_ADC_SUCCESS; +} + + +/** + * @brief Return the temperature in fixed point format in degree Celcius. + * + * @param [in] hDevice Handle to the device instance. + * + * @param [in] nRefVoltage Reference voltage in fixed point(16.16) format. + * + * @param [out] pnTemperature Pointer to a variable to which the ADC die temperature (in degree Celsius) will be written. + * The temperature will be in fixed point (16.16) format. + * + * + * @return Status + * - #ADI_ADC_SUCCESS Successfully retrieved the die temperature + * - #ADI_ADC_BAD_SYS_CLOCK Unable to obtain CLK which is needed to calculate + * temperature conversion timing values. + * - #ADI_ADC_INVALID_DEVICE_HANDLE [D] Invalid device handle passed to the API + * - #ADI_ADC_NULL_POINTER [D] pnBatVoltage is NULL + * - #ADI_ADC_INVALID_SEQUENCE [D] ADC sub system should be up and ADC should be free for getting the battery voltage. The Temperator + * sensor also need to be enabled. + * - #ADI_ADC_INVALID_STATE [D] Temperature sensor require an aquisition time of 65us and that cannot be set with the current + * ACLK since only ACLK of 255 can be stored to the sampling register. Decrease the ACLK clock to + * rectify this. + */ +ADI_ADC_RESULT adi_adc_GetTemperature ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + int32_t* pnTemperature + ) +{ + ADI_ADC_RESULT eResult = ADI_ADC_SUCCESS; + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *)hDevice; + uint16_t nConvTimeBackup; + uint16_t nAvgCfgBackup; + uint32_t nAdcTmpValue = 0u; + uint32_t nAdcTmp2Value = 0u; + uint32_t nClock = 0u; + uint32_t nACLKDIVCNT; + uint32_t nCnvTime; + +#ifdef ADI_DEBUG + if (pDevice == NULL) + { + return ADI_ADC_INVALID_DEVICE_HANDLE; + } + if (pnTemperature == NULL) + { + return ADI_ADC_NULL_POINTER; + } + + if (IS_NOT_IN_STATE(ADC_STATUS_SUB_SYSTEM_EN | ADC_STATUS_TEMP_SENSOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } + + if (IS_IN_ANY_STATE(ADC_STATUS_NON_BLOCKING_EN | ADC_STATUS_BLOCKING_EN | ADC_STATUS_COMPARATOR_EN)) + { + return ADI_ADC_INVALID_SEQUENCE; + } +#endif + + + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &nClock) == ADI_PWR_SUCCESS) + { + /* Calculate the conversion time */ + nACLKDIVCNT = (*pREG_CLKG0_CLK_CTL1 & BITM_CLKG_CLK_CTL1_ACLKDIVCNT) >> BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + nCnvTime = ((nClock / nACLKDIVCNT) / (uint16_t)15385u) + 1u; /* 65us acquisition time required = 15385Hz sample */ + + #ifdef ADI_DEBUG + if (nCnvTime >= 256u) { + return ADI_ADC_INVALID_STATE; + } + #endif + /* Take the backup of registers that need to be changed */ + nConvTimeBackup = pDevice->pReg->CNV_TIME; + nAvgCfgBackup = pDevice->pReg->AVG_CFG; + + /* Set the required value in the registers. */ + + pDevice->pReg->CNV_TIME = (uint16_t)((nCnvTime << BITP_ADC_CNV_TIME_SAMPTIME) & BITM_ADC_CNV_TIME_SAMPTIME); + pDevice->pReg->AVG_CFG = 0u; + + /* Clear the temperature done status */ + pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE | BITM_ADC_STAT_TMP2DONE; + + /* Clear the temperature done state */ + CLR_STATE(ADC_STATUS_TMP_DONE | ADC_STATUS_TMP2_DONE); + + /* Sample Tmp register */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP); + while (IS_NOT_IN_STATE(ADC_STATUS_TMP_DONE)) { ; } + nAdcTmpValue = pDevice->pReg->TMP_OUT; + pDevice->pReg->CNV_CFG = 0u; + + + /* Sample Tmp2 register */ + pDevice->pReg->CNV_CFG = (BITM_ADC_CNV_CFG_SINGLE | BITM_ADC_CNV_CFG_TMP2); + while (IS_NOT_IN_STATE(ADC_STATUS_TMP2_DONE)) { ; } + pDevice->pReg->CNV_CFG = 0u; + nAdcTmp2Value = pDevice->pReg->TMP2_OUT; + + /* Restore the changed registers */ + pDevice->pReg->CNV_TIME = nConvTimeBackup; + pDevice->pReg->AVG_CFG = nAvgCfgBackup; + + /* Calculate the temperature voltage. + * From the HRM: Temperature can be calculated as: + * + * T(^0 C)= code1/(code2+RG*code1)*Rvirtualreference/(ideal_sensitivity )-273.15 + * + * Some of these values are constants, and some have been read from registers. + * The above formula, when populated with variables and constants, would look like this: + * T(^0 C)= (nAdcTmpValue/(nAdcTmp2Value + nTempRG * nAdcTmpValue)) * (1.2256/1.2411e-3)) -273.15 + */ + { + uint32_t nRVirRefByIdealSensitivity = 2070960834u; /* 1.2256/1.2411e-3 in 11.21 format */ + + uint32_t nTempRG = 19380u; /* 1.1829 in 2.14 format */ + uint32_t nTmp2 = ((nAdcTmp2Value << 14u) + (nTempRG * nAdcTmpValue)); /* in 14.14 format */ + + uint32_t nOffsetPart = (335544320u/nRefVoltage); /* (1.25 in 4.28 format / ReferenceVoltage(16.16)) = Result in format *.12 */ + uint32_t nOffset = (161u * nOffsetPart); /* 12.12 format */ + + uint32_t nTmp3 = ((nAdcTmpValue << 12) - nOffset) << 8u; /* Format 12.20 */ + uint32_t nRatio = (nTmp3/(nTmp2 >> 10u)); /* nTmp2 resolution reduced by 10 to 14.4 and the result resolution is 0.16 */ + uint32_t nTemp = (nRatio * (nRVirRefByIdealSensitivity >> 16u)) >> 5u; /* Temperature in degree kelvin in 16.16 format */ + + int32_t iTemp = (int32_t)nTemp - ((int32_t)17901158); /* Subtract 273.15 (in 16.16) to get the temperature in degree celcius */ + *pnTemperature = iTemp; + } + } + else + { + eResult = ADI_ADC_BAD_SYS_CLOCK; + } + + return eResult; +} + + +/*! \cond PRIVATE */ + +/*========== S T A T I C F U N C T I O N S ==========*/ +/* Read the output register for the given channel number */ +static uint16_t ReadOutReg(uint32_t nChannelNum) +{ + const volatile uint16_t* pOutRegister = pREG_ADC0_CH0_OUT; + pOutRegister += nChannelNum*2u; + return *pOutRegister; +} + +/* Init buffer processing */ +static bool InitBufferProcessing(ADI_ADC_DEVICE *pDevice) +{ + uint32_t nCnvReg = ((uint32_t)(pDevice->pReg->CNV_CFG) & BITM_ADC_CNV_CFG_DMAEN); + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if (IS_NOT_IN_ANY_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS)) + { + /* Clear conversion done flags */ + pDevice->pReg->STAT = 0xFFFFu; + + /* Clear the overflow and alert register */ + pDevice->pReg->OVF = 0xFFFFu; + } + + /* Calculate the conversion register value for the given configuration */ + nCnvReg |= pIntBuffer->nChannels; + if ((uint16_t)(pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN) != 0u) { + nCnvReg |= BITM_ADC_CNV_CFG_AUTOMODE; + } + if ((pIntBuffer->nConfig & ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN) != 0u) { + nCnvReg |= BITM_ADC_CNV_CFG_SINGLE; + } else { + nCnvReg |= BITM_ADC_CNV_CFG_MULTI; + } + + SET_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + pDevice->pReg->CNV_CFG |= (uint16_t)nCnvReg; + + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_ENABLED); + + return true; +} + + +#if ADI_ADC_ENABLE_MULTI_ACQUIRE == 1 +/* DMA Callback Handler */ +void DMA_ADC0_Int_Handler (void) +{ + ISR_PROLOG(); + ADI_ADC_DEVICE *pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice; + + DmaFIFOManage(pDevice, ADC_FIFO_MODE_DMA_BUFFER_PROCESS); + + ISR_EPILOG(); +} + +static ADI_ADC_RESULT DmaFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode) +{ + uint16_t nCount = 0u; + uint16_t chanNum = ADC0_CHANn; + uint16_t IRQ_Backup; + + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if(pDevice->s_Buffer.pCurDataBuffer == NULL) { + /* If there is nothing active... */ + if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) { + /* ...it's something leftover, so cleanup. */ + uint16_t nStat = pDevice->pReg->STAT & 0x00FFu; + FlushFifo(pDevice, (uint32_t)nStat); + pDevice->pReg->STAT = nStat; + } + } + else { + switch (eFifoMode) + { + case ADC_FIFO_MODE_INIT: + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ(DMA0_CH24_DONE_IRQn); + + pADI_DMA0->SRCADDR_CLR = 1U << chanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << chanNum; + + /* Enables peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << chanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << chanNum; /* Should be default */ + + /* Setup the DMA registers */ + nCount = (uint16_t)pIntBuffer->nNumSamplesRemaining; + + /* Point to the end of the DMA source */ + pPrimaryCCD[chanNum].DMASRCEND = (uint32_t)(&(pDevice->pReg->DMA_OUT)); + + /* Point to the end of the DMA write-to destination */ + pPrimaryCCD[chanNum].DMADSTEND = (uint32_t)((void*)pIntBuffer->pCurDataBuffer) + ((nCount * 2u) - 1u); + + /* Configure the DMA itself */ + pPrimaryCCD[chanNum].DMACDC = ((ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | /* Increment destination address */ + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | /* Don't increment the source address */ + ((uint32_t)ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | /* 16bit transfers */ + ((nCount - (uint32_t)1U)<< DMA_BITP_CTL_N_MINUS_1) | /* Data size? */ + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) | /* Basic only */ + ((uint32_t)ADI_DMA_RPOWER_1 << DMA_BITP_CTL_R_POWER)); /* Arbitration */ + + /* Enable DMA */ + pDevice->pReg->CNV_CFG |= BITM_ADC_CNV_CFG_DMAEN; + break; + + case ADC_FIFO_MODE_ENABLED: + break; + + case ADC_FIFO_MODE_INTERRUPT_PROCESS: + /* Clear the status registers */ + pDevice->pReg->STAT = (pDevice->pReg->STAT & 0x00FFu); + break; + + case ADC_FIFO_MODE_INTERRUPT_OVERFLOW: + pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW; + break; + + case ADC_FIFO_MODE_DMA_BUFFER_PROCESS: + pIntBuffer->nNumSamplesRemaining = 0u; + ManageFifoCompletion(pDevice); + break; + + case ADC_FIFO_MODE_ABORT: + + /* Take backup of IRQ */ + IRQ_Backup = pDevice->pReg->IRQ_EN; + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + + /* Disable the DMA channel */ + pADI_DMA0->EN_CLR = 1U << chanNum; + + /* Clear the status bits */ + pDevice->pReg->STAT = pDevice->pReg->STAT; + + /* Clear the sampling in progress state */ + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + /* Read and flush all the buffers */ + FlushFifo(pDevice, 0x00FFu); + + /* Restore the IRQ */ + pDevice->pReg->IRQ_EN = IRQ_Backup; + + break; + + default: + break; + } + } + + return ADI_ADC_SUCCESS; +} +#else /* else ADI_ADC_ENABLE_MULTI_ACQUIRE == 0 */ + +static ADI_ADC_RESULT InterruptFIFOManage (ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode) +{ + ADC_INT_BUFFER* pIntBuffer = &pDevice->s_Buffer; + + if(pDevice->s_Buffer.pCurDataBuffer == NULL) { + if (eFifoMode == ADC_FIFO_MODE_INTERRUPT_PROCESS) { + uint16_t nStat = pDevice->pReg->STAT & 0x00FFu; + FlushFifo(pDevice, (uint32_t)nStat); + pDevice->pReg->STAT = nStat; + } + return ADI_ADC_SUCCESS; + } + + switch (eFifoMode) + { + case ADC_FIFO_MODE_INIT: + { + /* Enable the conversion done and overflow interrupt */ + pDevice->ActData.nCurChannel = 0u; + } + break; + + case ADC_FIFO_MODE_ENABLED: + break; + + case ADC_FIFO_MODE_INTERRUPT_PROCESS: + { + while (pIntBuffer->nNumSamplesRemaining > 0u) { + uint32_t nConvStatus = ((uint32_t)pDevice->pReg->STAT & (uint32_t)0x00FFu); + if ((nConvStatus & 0x00FFu) == 0u) + { + break; + } + + uint32_t nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel); + while ((nCurChannelBitM & nConvStatus) == 0u) { + pDevice->ActData.nCurChannel++; + if (pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) { + pDevice->ActData.nCurChannel = 0u; + } + nCurChannelBitM = ((uint32_t)1u << pDevice->ActData.nCurChannel); + } + + assert ((pIntBuffer->nChannels & ((uint32_t)1u << pDevice->ActData.nCurChannel)) != 0u); + + *pIntBuffer->pCurDataBuffer = ReadOutReg( pDevice->ActData.nCurChannel); + pIntBuffer->pCurDataBuffer++; + + + pDevice->pReg->STAT = (uint16_t)nCurChannelBitM; + pIntBuffer->nNumSamplesRemaining -= 1u; + + pDevice->ActData.nCurChannel += 1u; + if ( pDevice->ActData.nCurChannel >= NUM_ADC_CHANNELS) { + pDevice->ActData.nCurChannel = 0u; + } + } + + if (pIntBuffer->nNumSamplesRemaining == 0u) { + ManageFifoCompletion(pDevice); + } + } + break; + + case ADC_FIFO_MODE_INTERRUPT_OVERFLOW: + { + pIntBuffer->nStatus |= ADC_BUFFER_STATUS_OVERFLOW; + } + break; + + case ADC_FIFO_MODE_ABORT: + { + uint16_t IRQ_Backup; + + /* Take backup of IRQ */ + IRQ_Backup = pDevice->pReg->IRQ_EN; + + /* Disable the IRQ */ + pDevice->pReg->IRQ_EN = 0u; + + /* Clear the conversion cfg register to stop any transaction */ + pDevice->pReg->CNV_CFG = 0u; + + /* Clear the status bits */ + pDevice->pReg->STAT = pDevice->pReg->STAT; + + /* Clear the sampling in progress state */ + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + /* Read and flush all the buffers */ + FlushFifo(pDevice, 0x00FFu); + + /* Restore the IRQ */ + pDevice->pReg->IRQ_EN = IRQ_Backup; + } + break; + + default: + break; + } + + return ADI_ADC_SUCCESS; +} +#endif + +static void FlushFifo(ADI_ADC_DEVICE *pDevice, uint32_t nChannels) +{ + uint32_t x; + for (x = 0u; x < 8u; x++) { + if ((nChannels & ((uint32_t)1u << x)) != 0u) { + ReadOutReg(x); + } + } +} + + +/* Called when a transfer is complete */ +static void ManageFifoCompletion(ADI_ADC_DEVICE *pDevice) +{ + /* Clear the conversion configuration */ + pDevice->pReg->CNV_CFG = 0u; + CLR_STATE(ADC_STATUS_SAMPLING_IN_PROGRESS); + + SEM_POST(pDevice); +} + + +/* Internal function to extract the number of channels + * in a 32bit word. */ +static uint32_t GetNumChannels(uint32_t nChannels) +{ + uint32_t n = nChannels & 0x000000FFu; + + n = (n & 0x00000055u) + ((n >> 1u) & 0x00000055u); + n = (n & 0x00000033u) + ((n >> 2u) & 0x00000033u); + n = (n + (n >> 4u)) & (0x0000000Fu); + + return n; +} + +/* Returns the channel number based on the ADI_ADC_CHANNEL type. + * i.e. ADI_ADC_CHANNEL1 returns 1. */ +static int32_t nGetChannelNumber(ADI_ADC_CHANNEL eChannel) +{ + int32_t retVal = 0; + uint32_t nChannel = (uint32_t)eChannel & 0x000000FFu; + + if ((nChannel & (nChannel - (uint32_t)1u)) != 0u) { + return -1; + } + if ((nChannel & 0x000000AAu) != 0u) { retVal += 1; } + if ((nChannel & 0x000000CCu) != 0u) { retVal += 2; } + if ((nChannel & 0x000000F0u) != 0u) { retVal += 4; } + + return retVal; +} + +/* Internal function to set static configuration options. */ +static void StaticConfiguration(ADI_ADC_DEVICE *pDevice) +{ + uint16_t nCfgReg = 0u; + + /* Configure the resolution */ +#if ADI_ADC_CFG_RESOLUTION == 12 + pDevice->pReg->AVG_CFG = 0u; +#else + +#if ADI_ADC_CFG_RESOLUTION == 13 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0002u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 14 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0008u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 15 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0020u << BITP_ADC_AVG_CFG_FACTOR); +#elif ADI_ADC_CFG_RESOLUTION == 16 + pDevice->pReg->AVG_CFG = BITM_ADC_AVG_CFG_OS | BITM_ADC_AVG_CFG_EN | (0x0080u << BITP_ADC_AVG_CFG_FACTOR); +#else +#error "Invalid Resolution" +#endif + + SET_STATE(ADC_STATUS_OVERSAMPLING_EN); +#endif + + /* Configure the VREF */ +#if ADI_ADC_CFG_VREF == 0 /* 1.25V Internal Reference*/ + nCfgReg |= BITM_ADC_CFG_REFBUFEN | BITM_ADC_CFG_VREFSEL; +#elif ADI_ADC_CFG_VREF == 1 /* 2.5V Internal Reference */ + nCfgReg |= BITM_ADC_CFG_REFBUFEN; +#elif ADI_ADC_CFG_VREF == 2 /* Battery Voltage */ + nCfgReg |= BITM_ADC_CFG_VREFVBAT; +#endif + + pDevice->pReg->CFG = nCfgReg; + +#if ADI_ADC_ENABLE_STATIC_COMPARATOR == 1 + /* High limit registers */ +#if ADI_ADC_COMPARATOR_AIN0_HI_EN == 1 + pDevice->pReg->LIM0_HI = ADI_ADC_COMPARATOR_AIN0_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_HI_EN == 1 + pDevice->pReg->LIM1_HI = ADI_ADC_COMPARATOR_AIN1_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_HI_EN == 1 + pDevice->pReg->LIM2_HI = ADI_ADC_COMPARATOR_AIN2_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_HI_EN == 1 + pDevice->pReg->LIM3_HI = ADI_ADC_COMPARATOR_AIN3_HI_VAL; + pDevice->ComparitorHi |= ADI_ADC_CHANNEL_3; +#endif + /* Low limit registers */ +#if ADI_ADC_COMPARATOR_AIN0_LO_EN == 1 + pDevice->pReg->LIM0_LO = (uint16_t)ADI_ADC_COMPARATOR_AIN0_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_LO_EN == 1 + pDevice->pReg->LIM1_LO = ADI_ADC_COMPARATOR_AIN1_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_LO_EN == 1 + pDevice->pReg->LIM2_LO = ADI_ADC_COMPARATOR_AIN2_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_LO_EN == 1 + pDevice->pReg->LIM3_LO = ADI_ADC_COMPARATOR_AIN3_LO_VAL; + pDevice->ComparitorLo |= ADI_ADC_CHANNEL_3; +#endif + + /* Hysteresis registers */ +#if ADI_ADC_COMPARATOR_AIN0_HYS_EN == 1 + pDevice->pReg->HYS0 = (uint16_t)(ADI_ADC_COMPARATOR_AIN0_HYS_VAL | (ADI_ADC_COMPARATOR_AIN0_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_0; +#endif +#if ADI_ADC_COMPARATOR_AIN1_HYS_EN == 1 + pDevice->pReg->HYS1 = (ADI_ADC_COMPARATOR_AIN1_HYS_VAL | (ADI_ADC_COMPARATOR_AIN1_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_1; +#endif +#if ADI_ADC_COMPARATOR_AIN2_HYS_EN == 1 + pDevice->pReg->HYS2 = (ADI_ADC_COMPARATOR_AIN2_HYS_VAL | (ADI_ADC_COMPARATOR_AIN2_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_2; +#endif +#if ADI_ADC_COMPARATOR_AIN3_HYS_EN == 1 + pDevice->pReg->HYS3 = (ADI_ADC_COMPARATOR_AIN3_HYS_VAL | (ADI_ADC_COMPARATOR_AIN3_HYS_CYC << BITP_ADC_HYS0_MONCYC)); + pDevice->ComparitorHys |= ADI_ADC_CHANNEL_3; +#endif +#endif + +} + +/* Internal function to enable the comparitor for previously-configured channels + * Does not set the limits, only enables. +*/ +static void EnableComparator(ADI_ADC_DEVICE *pDevice, bool bEnable) +{ + uint32_t x; + uint16_t nCnvCfg = 0u; + volatile uint16_t* pLO_Register[4] = {pREG_ADC0_LIM0_LO, pREG_ADC0_LIM1_LO, pREG_ADC0_LIM2_LO, pREG_ADC0_LIM3_LO}; + volatile uint16_t* pHI_Register[4] = {pREG_ADC0_LIM0_HI, pREG_ADC0_LIM1_HI, pREG_ADC0_LIM2_HI, pREG_ADC0_LIM3_HI}; + volatile uint16_t* pHYS_Register[4] = {pREG_ADC0_HYS0, pREG_ADC0_HYS1, pREG_ADC0_HYS2, pREG_ADC0_HYS3}; + + if (bEnable == true) + { + /* Loop round all the channels enabling each part if required. */ + for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) { + if((pDevice->ComparitorHi & (1u << x)) > 0u) { + *pHI_Register[x] |= BITM_ADC_LIM0_HI_EN; + } + if((pDevice->ComparitorLo & (1u << x)) > 0u) { + *pLO_Register[x] |= BITM_ADC_LIM0_LO_EN; + } + if((pDevice->ComparitorHys & (1u << x)) > 0u) { + *pHYS_Register[x] |= BITM_ADC_HYS0_EN; + } + } + nCnvCfg = (uint16_t)((uint16_t)pDevice->ComparitorHi | (uint16_t)pDevice->ComparitorLo); + + pDevice->pReg->IRQ_EN &= (uint16_t)(~BITM_ADC_IRQ_EN_CNVDONE); + pDevice->pReg->CNV_CFG = (uint16_t)nCnvCfg | (uint16_t)(BITM_ADC_CNV_CFG_MULTI | BITM_ADC_CNV_CFG_AUTOMODE); + SET_STATE(ADC_STATUS_COMPARATOR_EN); + } + else { + /* Loop round disabling all. */ + for (x = 0u; x < NUM_ADC_COMPARATOR_CHANNELS; x++) { + *pHI_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_HI_EN)); + *pLO_Register[x] &= (uint16_t)(~(BITM_ADC_LIM0_LO_EN)); + *pHYS_Register[x] &= (uint16_t)(~(BITM_ADC_HYS0_EN)); + } + pDevice->pReg->CNV_CFG = 0u; + pDevice->pReg->STAT = pDevice->pReg->STAT & 0x00FFu; + CLR_STATE(ADC_STATUS_COMPARATOR_EN); + pDevice->pReg->IRQ_EN |= BITM_ADC_IRQ_EN_CNVDONE; + } +} + + +/* In Handler handles the following cases: + * ADI_ADC_EVENT_ADC_READY + * ADI_ADC_EVENT_CALIBRATION_DONE + * ADC_STATUS_BATTERY_DONE + * ADC_STATUS_TMP_DONE + * ADC_STATUS_TMP2_DONE + * ADI_ADC_EVENT_HIGH_LIMIT_CROSSED + * ADI_ADC_EVENT_LOW_LIMIT_CROSSED +*/ +void ADC0_Int_Handler(void) +{ + ADI_ADC_DEVICE *pDevice; + ISR_PROLOG(); + + pDevice = (ADI_ADC_DEVICE *) AdcDevInfo[0].hDevice; + + if ((pDevice->pReg->STAT & 0x00FFu) != 0u) { + if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) { + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_PROCESS); + } else { + pDevice->pReg->STAT = pDevice->pReg->STAT & (0x00FFu); + } + } + if ((uint16_t)(pDevice->pReg->STAT & 0xFF00u) != 0u) { + if ((pDevice->pReg->STAT & BITM_ADC_STAT_RDY) != 0u) { + SET_STATE(ADC_STATUS_SUB_SYSTEM_READY); + pDevice->pReg->STAT = BITM_ADC_STAT_RDY; + if (pDevice->pfCallback != NULL) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_ADC_READY, NULL); + } + } + if ((pDevice->pReg->STAT & BITM_ADC_STAT_CALDONE) != 0u) { + SET_STATE(ADC_STATUS_CALIBRATION_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_CALDONE; + if (pDevice->pfCallback != NULL) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_CALIBRATION_DONE, NULL); + } + } + if ((pDevice->pReg->STAT & BITM_ADC_STAT_BATDONE) != 0u) { + SET_STATE(ADC_STATUS_BATTERY_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_BATDONE; + } + + if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMPDONE) != 0u) { + SET_STATE(ADC_STATUS_TMP_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_TMPDONE; + } + + if ((pDevice->pReg->STAT & BITM_ADC_STAT_TMP2DONE) != 0u) { + SET_STATE(ADC_STATUS_TMP2_DONE); + pDevice->pReg->STAT = BITM_ADC_STAT_TMP2DONE; + } + } + if (pDevice->pReg->OVF) { + uint16_t nOvrFlowValue = pDevice->pReg->OVF; + if (IS_NOT_IN_STATE(ADC_STATUS_COMPARATOR_EN)) { + pDevice->pfManageFifo(pDevice, ADC_FIFO_MODE_INTERRUPT_OVERFLOW); + } + pDevice->pReg->OVF = nOvrFlowValue; + } + if (pDevice->pReg->ALERT) { + uint32_t nAlertValue = pDevice->pReg->ALERT; + uint32_t channel; + if (IS_IN_STATE(ADC_STATUS_COMPARATOR_EN) && (pDevice->pfCallback != NULL)) { + for (channel = 0u; channel < (NUM_ADC_COMPARATOR_CHANNELS); channel++) { + /* Alert bit positions: hi limits are 0b01, + * lo limit alerts are 0b10. + */ + if((nAlertValue & (1u << (2u * channel))) > 0u) { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, (void*)channel); + } + if((nAlertValue & (1u << ((2u * channel) + ((uint32_t)1u)))) > 0u) + { + pDevice->pfCallback(pDevice->pCBParam, ADI_ADC_EVENT_LOW_LIMIT_CROSSED, (void*)channel); + } + } + } + pDevice->pReg->ALERT = (uint16_t)nAlertValue; + } + ISR_EPILOG(); +} + + +/*! \endcond */ + +#endif /* ADI_ADC_C */ + +/*****/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c new file mode 100755 index 00000000000..169378ea0fd --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c @@ -0,0 +1,20 @@ +#ifndef ADI_ADC_DATA_C +#define ADI_ADC_DATA_C + +#include +#include +#include +#include "adi_adc_def.h" + +/*! \cond PRIVATE */ + +static ADI_ADC_INFO AdcDevInfo[] = { + { + NULL, + (ADI_ADC_TypeDef*)REG_ADC0_CFG + } +}; + +/*! \endcond */ + +#endif /* ADI_ADC_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h new file mode 100755 index 00000000000..6568f6f277e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_def.h @@ -0,0 +1,120 @@ +/*! \cond PRIVATE */ + +#ifndef ADI_ADC_DEF +#define ADI_ADC_DEF + +#include +#include + +#if defined(__ECC__) +#define ALIGN +#define ALIGN4 _Pragma("align(4)") +#elif defined(__ICCARM__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#elif defined (__GNUC__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#endif + + +#define IS_IN_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X)) +#define IS_NOT_IN_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u) +#define IS_IN_ALL_STATES(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == (uint32_t)(X)) +#define IS_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) != 0u) +#define IS_NOT_IN_ANY_STATE(X) ((pDevice->nDriverStatus & (uint32_t)(X)) == 0u) + +#define SET_STATE(X) (pDevice->nDriverStatus |= (uint32_t)(X)) +#define CLR_STATE(X) (pDevice->nDriverStatus &= ~((uint32_t)(X))) + +#define NUM_ADC_CHANNELS (8u) +#define NUM_ADC_COMPARATOR_CHANNELS (4u) + +/* To keep state for the driver for error checking */ +typedef enum __ADC_STATUS { + ADC_STATUS_POWERED_UP = (1u << 0), + ADC_STATUS_SUB_SYSTEM_EN = (1u << 1), + ADC_STATUS_SUB_SYSTEM_READY = (1u << 2), + + ADC_STATUS_NON_BLOCKING_EN = (1u << 3), + ADC_STATUS_BLOCKING_EN = (1u << 4), + ADC_STATUS_COMPARATOR_EN = (1u << 5), + + ADC_STATUS_SAMPLING_IN_PROGRESS = (1u << 6), + ADC_STATUS_CALIBRATION_EN = (1u << 7), + ADC_STATUS_CALIBRATION_DONE = (1u << 8), + + ADC_STATUS_BATTERY_DONE = (1u << 9), + + ADC_STATUS_OVERSAMPLING_EN = (1u << 10), + ADC_STATUS_AVGERAGING_EN = (1u << 11), + + ADC_STATUS_TEMP_SENSOR_EN = (1u << 12), + + ADC_STATUS_TMP_DONE = (1u << 13), + ADC_STATUS_TMP2_DONE = (1u << 14), +} ADC_STATUS; + +typedef enum __ADC_FIFO_MODE { + ADC_FIFO_MODE_INIT, + ADC_FIFO_MODE_ENABLED, + ADC_FIFO_MODE_INTERRUPT_PROCESS, + ADC_FIFO_MODE_INTERRUPT_OVERFLOW, + ADC_FIFO_MODE_DMA_BUFFER_PROCESS, + ADC_FIFO_MODE_DMA_INVALID_DESC, + ADC_FIFO_MODE_ABORT +} ADC_FIFO_MODE; + +typedef enum __ADC_BUFFER_CONFIG { + ADC_BUFFER_CONFIG_BUFFER_SINGLE_CONV_EN = ((uint32_t)1u << 1u), + ADC_BUFFER_CONFIG_BUFFER_AUTO_MODE_EN = ((uint32_t)1u << 0u), +} ADC_BUFFER_CONFIG; + + +typedef enum __ADC_BUFFER_STATUS { + ADC_BUFFER_STATUS_OK = ((uint32_t)1u << 0u), + ADC_BUFFER_STATUS_OVERFLOW = ((uint32_t)1u << 1u) +} ADC_BUFFER_STATUS; + +typedef struct __ADC_INT_BUFFER { + uint16_t nConfig; + uint16_t nStatus; + ADI_ADC_BUFFER *pUserBuffer; + uint16_t* pCurDataBuffer; + uint32_t nNumSamplesRemaining; + uint32_t nChannels; +} ADC_INT_BUFFER; + +typedef struct __ADC_ACTIVE_DATA { + uint32_t nCurChannel; +} ADC_ACTIVE_DATA; + +typedef ADI_ADC_RESULT (*ADC_MANAGE_FIFO_FUNC)(struct __ADI_ADC_DEVICE *pDevice, ADC_FIFO_MODE eFifoMode); + +typedef struct __ADI_ADC_DEVICE +{ + volatile uint32_t nDriverStatus; + ADI_ADC_TypeDef *pReg; + void* pCBParam; + ADI_CALLBACK pfCallback; + + ADC_ACTIVE_DATA ActData; + ADC_MANAGE_FIFO_FUNC pfManageFifo; + + ADC_INT_BUFFER s_Buffer; + uint8_t ComparitorHi; + uint8_t ComparitorLo; + uint8_t ComparitorHys; + + SEM_VAR_DECLR +} ADI_ADC_DEVICE; + +typedef struct __ADI_ADC_INFO +{ + ADI_ADC_HANDLE hDevice; + ADI_ADC_TypeDef* pReg; +} ADI_ADC_INFO; + +#endif /* ADI_ADC_DEF */ + +/*! \endcond */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h new file mode 100755 index 00000000000..fd2e04f282b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_callback.h @@ -0,0 +1,60 @@ +/*! + ***************************************************************************** + @file: adi_callback.h + @brief: callback APIs. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#ifndef ADI_CALLBACK_H +#define ADI_CALLBACK_H + +#include + +/** + * @brief Device Drivers Callback function definition + */ +typedef void (* ADI_CALLBACK) ( /*!< Callback function pointer */ + void *pCBParam, /*!< Client supplied callback param */ + uint32_t Event, /*!< Event ID specific to the Driver/Service */ + void *pArg); /*!< Pointer to the event specific argument */ + +#endif /* ADI_CALLBACK_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h new file mode 100755 index 00000000000..a2b5807a628 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_cyclecount.h @@ -0,0 +1,137 @@ +/* + ******************************************************************************* + * @brief: Framework to preform cycle count measurements + * + * @details this is a framework for monitoring the cycle counts + * for ISRs and APIs. The framework uses systick. + +******************************************************************************* + + Copyright(c) 2016 Analog Devices, Inc. All Rights Reserved. + + This software is proprietary and confidential. By using this software you agree + to the terms of the associated Analog Devices License Agreement. + + ******************************************************************************/ + +#ifndef ADI_CYCLECOUNT_H +#define ADI_CYCLECOUNT_H + +#include +#include +#include + + + /** @addtogroup cyclecount_logging Cycle Counting Framework + * @{ + */ + +/*! + * 64-bit integer to record cycle counts. + * Since UINT32_MAX = 4,294,967,296 cycles + * at 26 MHz this would allow us to record for 165 seconds + * before the system would wrap around. + * By moving to a 64-bit integer we can record for 11,248 years. + */ +typedef uint64_t adi_cyclecount_t; + + +/*! + * The systick timer is a 24-bit count down timer + * The initial value can, therefore, be up to 0xFFFFFF + * The larger the value the fewer interrupts that will be taken + * and the less impact cycle counting will have on the system + */ +#define ADI_CYCLECOUNT_SYSTICKS (0xFFFFFFu) + +/*! + * Cycle counting nesting is supported via a cycle counting stack. The initial + * value of the stack index is one less than the starting stack + * index (0) + */ +#define ADI_CYCLECOUNT_INITIAL_STACK_INDEX (-1) + +/*! + * Cycle Count API function return values. + */ +typedef enum { + + ADI_CYCLECOUNT_SUCCESS, /*!< API completed successfully */ + ADI_CYCLECOUNT_ADD_ENTITY_FAILURE, /*!< There is not enough space in the cycle counting entity array. Consider increasing the size via the #ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS static configuration macro */ + ADI_CYCLECOUNT_INVALID_ID, /*!< The API/ISR ID is invalid. */ + ADI_CYCLECOUNT_FAILURE /*!< API did not complete successfully. */ +} ADI_CYCLECOUNT_RESULT; + + +/*! + * List of cycle counting IDs for the ISRs and APIs that can record cycle counts. + * Items enumerated here must be aligned with adi_cyclecounting_identifiers + * + * Note that the ID numbering starts at 1. ID==0 is not used. + * Note that the application can extend this list via static configuration (see adi_cycle_counting_config.h) and + * via the adi_cyclecount_addEntity() API. + */ +#define ADI_CYCLECOUNT_ISR_EXT_3 1u /*!< Cycle count ID for EXT3 Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_UART 2u /*!< Cycle count ID for UART Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_DMA_UART_TX 3u /*!< Cycle count ID for UART DMA TX Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_DMA_UART_RX 4u /*!< Cycle count ID for UART DMA RX Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_TMR_COMMON 5u /*!< Cycle count ID for Timer Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_RTC 6u /*!< Cycle count ID for RTC Interrupt Handler.*/ +#define ADI_CYCLECOUNT_ISR_SPI 7u /*!< Cycle count ID for SPI Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_CRC 8u /*!< Cycle count ID for CRC Interrupt Handler. */ +#define ADI_CYCLECOUNT_ISR_SPORT 9u /*!< Cycle count ID for SPORT Interrupt Handler. */ +#define ADI_CYCLECOUNT_ID_COUNT 10u /*!< Number of cycle count ISRs and APIs. Must be one greater than the last ID. */ + + +/*! + * The following are tracked when cycle counting + * Maximum number of cycle counts + * Minimum number of cycle counts + * Average number of cycle counts + */ +typedef struct +{ + adi_cyclecount_t max_cycles_adjusted; /*!< Tracks the adjusted max cycle count */ + adi_cyclecount_t min_cycles_adjusted; /*!< Tracks the adjusted min cycle count */ + adi_cyclecount_t average_cycles_adjusted; /*!< Tracks the adjusted average cycle count */ + + adi_cyclecount_t max_cycles_unadjusted; /*!< Tracks the unadjusted max cycle count */ + adi_cyclecount_t min_cycles_unadjusted; /*!< Tracks the unadjusted min cycle count */ + adi_cyclecount_t average_cycles_unadjusted; /*!< Tracks the unadjusted average cycle count */ + + uint32_t sample_count; /*!< Number of cycle count samples recorded, used to compute the average */ + +} ADI_CYCLECOUNT_LOG; + +/*! + * Cycle counting has to be enabled in the cycle counting configuration file + * If enabled then cycle counting related macros map to the cycle counting APIs. + * If not enabled, then the macros maps to a NOP + */ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) + + #define ADI_CYCLECOUNT_INITIALIZE() adi_cyclecount_init() /*!< Initialize the cycle counting data structures */ + #define ADI_CYCLECOUNT_STORE(id) adi_cyclecount_store(id) /*!< Record the number of cycles for the specified ISR or API */ + #define ADI_CYCLECOUNT_REPORT() adi_cyclecount_report() /*!< Generate a cycle counting report */ + +#else + + #define ADI_CYCLECOUNT_INITIALIZE() do{}while(0) /*!< Initialize the cycle counting data structures */ + #define ADI_CYCLECOUNT_STORE(id) do{}while(0) /*!< Record the number of cycles for the specified ISR or API */ + #define ADI_CYCLECOUNT_REPORT() do{}while(0) /*!< Generate a cycle counting report */ +#endif + + +/* Forward API declarations */ +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_start(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_stop(void); +extern adi_cyclecount_t adi_cyclecount_get(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_store(uint32_t id); +extern void adi_cyclecount_init(void); +extern void adi_cyclecount_report(void); +extern ADI_CYCLECOUNT_RESULT adi_cyclecount_addEntity(const char *EntityName, uint32_t *pid); + +/**@}*/ + +#endif /* ADI_CYCLECOUNT_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h new file mode 100755 index 00000000000..3032a13ac10 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_processor.h @@ -0,0 +1,67 @@ +/*! + ***************************************************************************** + * @file: adi_processor.h + * @brief: Include appropriate CMSIS device header. + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ADI_PROCESSOR_H__ +#define __ADI_PROCESSOR_H__ + +/* Default to ADuCM4050 if no processor macro is defined. */ + +#if !defined(__ADUCM4050__) + #define __ADUCM4050__ +#endif + +/* Define a family macro */ + +#if !defined(__ADUCM4x50__) + #define __ADUCM4x50__ +#endif + +/* Include CMSIS device header for selected target processor. */ + +#if defined(__ADUCM4050__) +#include +#endif + +#endif /* __ADI_PROCESSOR_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h new file mode 100755 index 00000000000..ca221b8360a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_types.h @@ -0,0 +1,18 @@ +#ifndef __ADI_TYPES_H__ +#define __ADI_TYPES_H__ + +/* obtain integer types ... */ +#include + +/* obtain boolean types ... */ +#include + +/* define required types that are not provided by stdint.h or stdbool.h ... */ +typedef bool bool_t; +typedef char char_t; +typedef float float32_t; +#if !defined(__NO_FLOAT64) +typedef long double float64_t; +#endif + +#endif /* __ADI_TYPES_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h new file mode 100755 index 00000000000..6dd08f49bb7 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adi_version.h @@ -0,0 +1,63 @@ +/*! + ***************************************************************************** + * @file: adi_version.h + * @brief: Version macros for ADI ADuCMxxx Device Series + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + + THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __ADI_VERSION_H__ +#define __ADI_VERSION_H__ + +/* use a 32-bit versioning scheme that supports numerical compares */ +#define ADI_VERSION_MAJOR 1u /* must be <= 255 */ +#define ADI_VERSION_MINOR 0u /* must be <= 255 */ +#define ADI_VERSION_BUILD 0u /* must be <= 255 */ +#define ADI_VERSION_PATCH 0u /* must be <= 255 */ + +#define ADI_CONSTRUCT_VERSION(a,b,c,d) (((a) << 24u) | ((b) << 16u) | ((c) << 8u) | (d)) + +/* known versions */ +#define ADI_VERSION_1_0_0_0 ADI_CONSTRUCT_VERSION(1u,0u,0u,0u) + +/* test current version against known predefines (see SystemInit() example in system.c) */ +#define ADI_VERSION_CURRENT ADI_CONSTRUCT_VERSION(ADI_VERSION_MAJOR, ADI_VERSION_MINOR, ADI_VERSION_BUILD, ADI_VERSION_PATCH) + +#endif /* __ADI_VERSION_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c new file mode 100755 index 00000000000..0d0054c432e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep.c @@ -0,0 +1,751 @@ +/*! ***************************************************************************** + * @file: adi_beep.c + * @brief: BEEP device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This included file will be containing BEEP device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#include + +#include +#include + +#include +#include +#include "adi_beep_def.h" + +/** @addtogroup BEEP_Driver BEEP Driver + * @{ + * @brief Beeper Driver + * @note The application must include drivers/beep/adi_beep.h to use this driver. + */ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit. +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function. +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Required for MMR addresses and callback parameters. +* +* Pm031: (MISRA C 2004 rule 12.7) bitwise operations shall not be performed on signed integer types +* Required for MMR manipulations. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Required for adi_beep_PlaySequence() to access the user-supplied array of notes. +* +* Pm141: (MISRA C 2004 rule 11.4) a cast should not be performed between a pointer to object type and a +* different pointer to object type, this casts from type. +* Required to store a an array of varying size in a device structure. +* +* Required for adi_beep_PlaySequence() to access the user-supplied array of notes. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm140,Pm031,Pm152,Pm141 +#endif /* __ICCARM__ */ + +/*========== D A T A ==========*/ +static ADI_BEEP_DRIVER adi_beep_Device[1]; + +/*! \cond PRIVATE */ +/* Handler for the BEEP interrupt */ +void Beep_Int_Handler(void); + +/* debug handle checker */ +#ifdef ADI_DEBUG +#define ADI_BEEP_INVALID_HANDLE(h) (&adi_beep_Device[0] != (h)) +#endif + +/* definition for the BEEP IRQ - there is only ever one instance of the + * BEEP driver, so reducing space by using a #define rather than including + * it in the device structure. */ +#define BEEP_IRQ (BEEP_EVT_IRQn) + +#if ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE == 0 +/* A single note is requested. Only enable the AEND int. */ +#define INTERRUPT_ON_SEQEND (0) +#define INTERRUPT_ON_AEND (1) +#else +/* A two-tone sequence is requested. Only enable the SEQEND int. */ +#define INTERRUPT_ON_SEQEND (1) +#define INTERRUPT_ON_AEND (0) +#endif + +/*! \endcond */ + +static const ADI_BEEP_STATIC_INIT gBeeperStaticConfigData[ADI_BEEP_MAX_DEVID] = { + /* single instance of Beeper device */ + { + /* configuration register */ + ( (INTERRUPT_ON_SEQEND << BITP_BEEP_CFG_SEQATENDIRQ) + | (INTERRUPT_ON_AEND << BITP_BEEP_CFG_AENDIRQ) + | (ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE << BITP_BEEP_CFG_SEQREPEAT) + ), + + /* Status register (interrupt clears) */ + (ADI_BEEP_ALL_INTERRUPTS), + + /* ToneA control register */ + ( ((uint32_t)ADI_BEEP_TONEA_DISABLE << BITP_BEEP_TONEA_DIS) + | ((uint32_t)ADI_BEEP_TONEA_FREQUENCY << BITP_BEEP_TONEA_FREQ) + | ((uint32_t)ADI_BEEP_TONEA_DURATION << BITP_BEEP_TONEA_DUR) + ), + + /* ToneB control register */ + ( ((uint32_t)ADI_BEEP_TONEB_DISABLE << BITP_BEEP_TONEB_DIS) + | ((uint32_t)ADI_BEEP_TONEB_FREQUENCY << BITP_BEEP_TONEB_FREQ) + | ((uint32_t)ADI_BEEP_TONEB_DURATION << BITP_BEEP_TONEB_DUR) + ) + } +}; + +/*! \endcond */ + + +/*! + * @brief BEEP Initialization + * + * @param[in] DeviceNum Integer specifying the ID of Beeper to use. + * @param[in] pMemory Pointer to the memory to be used by the driver. + * Size of the memory should be at least #ADI_BEEP_MEMORY_SIZE bytes. + * @param[in] MemorySize Size of the memory passed in pMemory parameter. + * @param[out] phDevice Pointer to a location that the device data pointer + * will be written upon successful initialization. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: BEEP device driver initialized successfully. + * - #ADI_BEEP_SEMAPHORE_FAILED The BEEP sempahore could not be created. + * - #ADI_BEEP_ALREADY_INITIALIZED [D] The BEEP is already initialized. + * - #ADI_BEEP_NULL_PTR [D] Null pointer. + * - #ADI_BEEP_BAD_DEV_ID [D] The device number is invalid. + * + * Initialize the BEEP device for use. The core NVIC BEEP interrupt is enabled. This API + * must preceed all other beeper API calls and the handle returned must be passed to all other beeper API + * calls. + * + * + * @note The contents of \a phDevice will be set to NULL upon failure.\n\n + * + * @note The BEEP device driver will clear all pending interrupts and disable all beeper + * interrupts during beeper device initialization. + * + * @note CALLBACKS: If a callback is registered, it will be called on + * completion of the note or sequence. The "Event" parameter will + * contain which event occurred, either ADI_BEEP_INTERRUPT_SEQUENCE_END + * or ADI_BEEP_INTERRUPT_NOTE_END. + * + * @warning This API will put the beeper in preconfigured mode as defined in + * adi_beep_config.h file. + * Refer adi_beep_config.h file to see which all features can be preconfigured. + * + * @sa adi_beep_Close(). + */ +ADI_BEEP_RESULT adi_beep_Open(ADI_BEEP_DEV_ID const DeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_BEEP_HANDLE* const phDevice) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_DEV_DATA *pData; + /* store a bad handle in case of failure */ + *phDevice = (ADI_BEEP_HANDLE) NULL; + +#ifdef ADI_DEBUG + if (DeviceNum >= ADI_BEEP_MAX_DEVID) + { + return ADI_BEEP_BAD_DEV_ID; + } + + if (pMemory == NULL) + { + return ADI_BEEP_NULL_PTR; + } + + assert (MemorySize >= sizeof(ADI_BEEP_DRIVER)); +#endif + + /* local pointer to instance data */ + pDevice = &adi_beep_Device[DeviceNum]; + pDevice->pReg = pADI_BEEP0; + pDevice->pData = (ADI_BEEP_DEV_DATA*)pMemory; + pData = pDevice->pData; + +#ifdef ADI_DEBUG + if (ADI_BEEP_STATE_UNINITIALIZED != adi_beep_Device[DeviceNum].pData->state) + { + return ADI_BEEP_ALREADY_INITIALIZED; + } +#endif + + pData->cbFunc = NULL; + pData->cbParam = NULL; + SEM_CREATE(pDevice->pData, "BEEP_SEM", ADI_BEEP_SEMAPHORE_FAILED); + + /* set statically configured initialization data */ + ADI_BEEP_STATIC_INIT const* pInitData = &gBeeperStaticConfigData[DeviceNum]; + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + + pReg->CFG = pInitData->BEEP_CFG; + pReg->STAT = pInitData->BEEP_STAT; + pReg->TONEA = pInitData->BEEP_TONEA; + pReg->TONEB = pInitData->BEEP_TONEB; + + /* enable beeper interrupts in NVIC */ + NVIC_EnableIRQ(BEEP_IRQ); + + /* mark driver initialized */ + pData->state = ADI_BEEP_STATE_INITIALIZED; + + /* store handle at application handle pointer */ + *phDevice = (ADI_BEEP_HANDLE)pDevice; + + return ADI_BEEP_SUCCESS; /* initialized */ +} + + +/*! + * @brief Uninitialize and deallocate a BEEP device. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Uninitialize and release an allocated BEEP device for other use. The core NVIC BEEP interrupt is disabled. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Close(ADI_BEEP_HANDLE const hDevice) +{ + + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_DEV_DATA *pData; + ADI_BEEP_TypeDef *pReg; + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pData = pDevice->pData; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) + { + return ADI_BEEP_BAD_DEV_HANDLE; + } + if (ADI_BEEP_STATE_UNINITIALIZED == pData->state) + { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ(BEEP_IRQ); + + pData->state = ADI_BEEP_STATE_UNINITIALIZED; + pData->cbFunc = NULL; + pReg->CFG = 0u; + pReg->STAT = 0u; + pReg->TONEA = 0u; + pReg->TONEB = 0u; + SEM_DELETE(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED); + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Register a callback for the beeper driver. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] pfCallback The application supplied callback which will be called to notify device + * related events. + * @param[in] pCBParam The application supplied callback parameter which can be passed back in + * the callback function. + * + * @return Status + * - #ADI_BEEP_SUCCESS Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_beep_Open(). + * + * Registers a callback for the beeper interrupts. When an interrupt occurs, the + * driver will handle any required interaction with the hardware and then call + * the registered callback. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_RegisterCallback(ADI_BEEP_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void* const pCBParam) +{ + ADI_BEEP_DRIVER *pDevice = (ADI_BEEP_DRIVER*)hDevice; + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + /* Assign the callback within a critical region. */ + ADI_ENTER_CRITICAL_REGION(); + pDevice->pData->cbFunc = pfCallback; + pDevice->pData->cbParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + + +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 +/*! + * @brief Play a beeper tone sequence. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] aSequence The sequence of notes to be played by the beeper. + * @param[in] count The number of notes in the sequence, must be a multiple + * of two, and a maximum size of 254 notes. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_INVALID_COUNT Sequence count must be multiples of two. + * - #ADI_BEEP_NULL_PTR [D] Null pointer. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the A/B tone pair to play a sequence of notes. The sequnce can be + * stopped by calling adi_beep_Enable(..., false). The beeper will be enabled + * and disabled internally by the driver. This code, and supporting data, can + * be removed by setting ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 0 in the + * adi_beep_config.h configuration file. + * + * @sa adi_beep_Open(). + * @sa adi_beep_Enable() + */ +ADI_BEEP_RESULT adi_beep_PlaySequence(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE aSequence[], + uint8_t count) +{ + ADI_BEEP_DRIVER *pDevice = (ADI_BEEP_DRIVER*)hDevice; + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + uint16_t nSeqCnt = 0u; + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } + + if (NULL == aSequence) { + return ADI_BEEP_NULL_PTR; + } + + /* The sequence count must be a multiple of two, be greater than 1 + * and must be a maximum of (127 * 2) notes in length. The hardware supports a + * sequence of up to 127, and there are two notes associated with that. */ + if (((127u * 2u) < count) || + ((count % 2u) != 0u) || + (count < 2u)) { + return ADI_BEEP_INVALID_COUNT; + } +#endif + + /* Two notes are loaded at a time, and the sequence count refers to + * the number of times that both tone registers should be played. */ + nSeqCnt = ((uint16_t)count) >> 1u; + + ADI_ENTER_CRITICAL_REGION(); + + /* make a hole, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ | BITM_BEEP_CFG_EN); + + pReg->TONEA = ( (uint16_t)((uint16_t)aSequence[0].frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)aSequence[0].duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)aSequence[1].frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)aSequence[1].duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | + BITM_BEEP_CFG_BSTARTIRQ | + BITM_BEEP_CFG_SEQATENDIRQ | + (uint16_t)((uint16_t)(nSeqCnt) << BITP_BEEP_CFG_SEQREPEAT)); + + pDevice->pData->pSeqArray = (ADI_BEEP_NOTE(*)[])aSequence; + pDevice->pData->nSeqMax = count; + pDevice->pData->nSeqIndex = 2u; + + /* We're now playing, but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} +#endif + +/*! + * @brief Play a single note/beep. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] note The note to play. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the A tone to play a single note. + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_PlayNote(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE note) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + /* Clear any previous sequence setup, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_EN); + + /* Set Tone A */ + pReg->TONEA = ( (uint16_t)((uint16_t)note.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)note.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_AENDIRQ); + + /* We're now playing but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + + +/*! + * @brief Play a a repeating two-tone beep. Similar to an alarm. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] noteA The note to play first. + * @param[in] noteB The note to play second. + * @param[in] count The number of times to repeat the two-note signal, + * maximum of 127. + * + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * Programs the beeper to play a repeating two-tone signal. + * The count argument refers to the number of iterations of both notes, not + * just a single note. + * + * @sa adi_beep_Open(). + * @sa adi_beep_PlayNote(). + * @sa adi_beep_PlayNSequence(). + */ +ADI_BEEP_RESULT adi_beep_PlayTwoTone(ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE noteA, + ADI_BEEP_NOTE noteB, + uint8_t count) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + /* make a hole, and disable the beeper */ + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_SEQREPEAT | BITM_BEEP_CFG_AENDIRQ |BITM_BEEP_CFG_EN); + + pReg->TONEA = ( (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + |(uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + /* program new sequence count, while preserving everything else */ + pReg->CFG |= (BITM_BEEP_CFG_EN | BITM_BEEP_CFG_SEQATENDIRQ |(uint16_t)((uint16_t)count << BITP_BEEP_CFG_SEQREPEAT)); + + /* We're now playing but not blocked */ + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Enable or disable the beeper. Other APIs will automatically enable the beeper if required, + * so this function is best used in the following situations: + * - when only using static configuration, i.e. start playing the notes + * set up in static adi_beep_config.h. + * - Otherwise, this can be used to stop the beeper during playback, + * when started from any other API. + * + * @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * @param[in] bFlag true to enable the device, false to stop playback. + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Enable(ADI_BEEP_HANDLE const hDevice, bool const bFlag) +{ + ADI_BEEP_DRIVER *pDevice; + ADI_BEEP_TypeDef *pReg; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + pReg = pDevice->pReg; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + if (bFlag == true) { + /* All the registers should already be set - just enable the beep */ + pReg->CFG |= BITM_BEEP_CFG_EN; + pDevice->pData->state |= (ADI_BEEP_STATE_PLAYING); + } + else { + pReg->CFG &= (uint16_t)~(BITM_BEEP_CFG_EN); + pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING); + } + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_BEEP_SUCCESS; +} + +/*! + * @brief Wait for the current playback to finish. This is a blocking call, + * that will not return until the current playback (if any) has finished. + * If there is no current playback, it will return immediately. + * +* @param[in] hDevice Device handle obtained from #adi_beep_Open(). + * + * @return Status + * - #ADI_BEEP_SUCCESS Success: Call completed successfully. + * - #ADI_BEEP_FAILURE Error: Semaphore failure. + * - #ADI_BEEP_BAD_DEV_HANDLE [D] Error: Invalid device handle parameter. + * - #ADI_BEEP_NOT_INITIALIZED [D] Error: Device has not been initialized for use, see #adi_beep_Open(). + * + * @sa adi_beep_Open(). + */ +ADI_BEEP_RESULT adi_beep_Wait(ADI_BEEP_HANDLE const hDevice) +{ + ADI_BEEP_DRIVER *pDevice; + bool wait = false; + ADI_INT_STATUS_ALLOC(); + + pDevice = (ADI_BEEP_DRIVER*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_BEEP_INVALID_HANDLE(hDevice)) { + return ADI_BEEP_BAD_DEV_HANDLE; + } + + if (ADI_BEEP_STATE_UNINITIALIZED == pDevice->pData->state) { + return ADI_BEEP_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + + if((pDevice->pData->state | ADI_BEEP_STATE_PLAYING) > 0u) { + /* We are going to pend on the semaphore, no matter what. */ + pDevice->pData->state |= ADI_BEEP_STATE_BLOCKED; + wait = true; + } + + ADI_EXIT_CRITICAL_REGION(); + + if(wait == true) { + /* Wait for the completion interrupt to post */ + SEM_PEND(pDevice->pData, ADI_BEEP_SEMAPHORE_FAILED); + } + + return ADI_BEEP_SUCCESS; +} + +/*! \cond PRIVATE */ + +/*! @brief BEEP device driver interrupt handler. Overrides weakly-bound + * default interrupt handler in the startup file. */ +void Beep_Int_Handler(void) +{ + ISR_PROLOG(); +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + ADI_BEEP_DEV_DATA *pData; + ADI_BEEP_NOTE noteA, noteB; +#endif + ADI_BEEP_DRIVER *pDevice = &adi_beep_Device[ADI_BEEP_DEVID_0]; /* so far, there is only one BEEP, so this is safe */ + ADI_BEEP_TypeDef *pReg = pDevice->pReg; + uint16_t fired = ADI_BEEP_ALL_INTERRUPTS; + register uint16_t candidate; + + /* Make sure our driver is up and running. */ + if (ADI_BEEP_STATE_UNINITIALIZED != pDevice->pData->state) { + + /* read both status and mask registers */ + candidate = pReg->CFG & ADI_BEEP_ALL_INTERRUPTS; /* Take the fired interrupts */ + fired = candidate; /* ...and a copy. */ + candidate = candidate & pReg->STAT; /* ...and remove the unused set interrupt bits */ + + /* From this driver's perspective, there are only two states + * to watch for - finished playing, or continuing the playing sequence. + * Finished will be handled here. */ + if((candidate & (BITM_BEEP_CFG_SEQATENDIRQ | BITM_BEEP_CFG_AENDIRQ)) > 0u) { + + /* If we are blocked, unblock by posting the semaphore */ + if((pDevice->pData->state | ADI_BEEP_STATE_BLOCKED) > 0u) { + SEM_POST(pDevice->pData); + } + + /* Reset the device playing status. */ + pDevice->pData->state &= ~(ADI_BEEP_STATE_PLAYING | ADI_BEEP_STATE_BLOCKED); + + /* ...and disable the device. */ + pReg->CFG &= (uint16_t)(~(BITM_BEEP_CFG_EN)); + + /* forward the interrupt to the user if they are watching it and it has fired */ + /* pass the interrupt as the event. */ + if (pDevice->pData->cbFunc != NULL) { + pDevice->pData->cbFunc (pDevice->pData->cbParam, (uint32_t)candidate, NULL); + } + } + + #if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + /* The second state is if we are playing a longer sequence, so this + * interrupt may be to move the sequence along. */ + if ((BITM_BEEP_CFG_BSTARTIRQ & candidate) != 0u) { + + /* Get a local copy of data, to shorten the following code. */ + pData = pDevice->pData; + + /* If there's still data to play */ + if(pData->nSeqIndex < pData->nSeqMax) { + /* Move the sequence along.*/ + noteA = (*pData->pSeqArray)[pData->nSeqIndex]; + pData->nSeqIndex++; + noteB = (*pData->pSeqArray)[pData->nSeqIndex]; + pData->nSeqIndex++; + + /* Any values written will not impact the current tones, + * they will take effect after the current tone is completed */ + pReg->TONEA = ( (uint16_t)((uint16_t)noteA.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + | (uint16_t)((uint16_t)noteA.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + + pReg->TONEB = ( (uint16_t)((uint16_t)noteB.frequency << ADI_BEEP_TONE_FREQ_BITPOS) + | (uint16_t)((uint16_t)noteB.duration << ADI_BEEP_TONE_DUR_BITPOS) ); + } + } +#endif + } + + /* clear the watched interrupt(s) that fired */ + pReg->STAT |= (uint16_t)(fired & ADI_BEEP_ALL_INTERRUPTS); /* only write allowed interrupt bits */ + ISR_EPILOG(); +} +/*! \endcond */ + +/*@}*/ + + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h new file mode 100755 index 00000000000..22e0b3a949c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/beep/adi_beep_def.h @@ -0,0 +1,128 @@ +/*! + ***************************************************************************** + * @file: adi_beep_def.h + * @brief: BEEP Device Driver definition + *----------------------------------------------------------------------------- + * + * Copyright (c) 2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef _ADI_BEEP_DEF_H_ +#define _ADI_BEEP_DEF_H_ + +/*! \cond PRIVATE */ +#include + +/*! + ***************************************************************************** + * An interrupt mask covering all Beeper interrupts. + *****************************************************************************/ +#define ADI_BEEP_ALL_INTERRUPTS ( BITM_BEEP_CFG_SEQATENDIRQ \ + | BITM_BEEP_CFG_SEQNEARENDIRQ \ + | BITM_BEEP_CFG_BENDIRQ \ + | BITM_BEEP_CFG_BSTARTIRQ \ + | BITM_BEEP_CFG_AENDIRQ \ + | BITM_BEEP_CFG_ASTARTIRQ) + +#define ADI_BEEP_TONE_DISABLE (BITM_BEEP_TONEA_DIS) /*!< Beeper tone disable bit */ + +#define ADI_BEEP_TONE_FREQ_BITPOS (BITP_BEEP_TONEA_FREQ) /*!< Beeper tone frequency bitfield position */ +#define ADI_BEEP_TONE_DUR_BITPOS (BITP_BEEP_TONEA_DUR) /*!< Beeper tone duration bitfield position */ + +#define ADI_BEEP_TONE_FREQ_MASK (BITM_BEEP_TONEA_FREQ) /*!< Beeper tone frequency bitfield mask */ +#define ADI_BEEP_TONE_DUR_MASK (BITM_BEEP_TONEA_DUR) /*!< Beeper tone duration bitfield mask */ + +/*! + ***************************************************************************** + * ADI_BEEP_STATE + * + * BEEP driver state. Used for internal tracking of the BEEP device initialization + * progress during the adi_beep_Open(). Also used to insure the BEEP device has been + * properly initialized as a prerequisite to using the balance of the BEEP API. + * + *****************************************************************************/ +typedef uint8_t ADI_BEEP_STATE; +#define ADI_BEEP_STATE_UNINITIALIZED 0u /*!< BEEP is not initialized. */ +#define ADI_BEEP_STATE_INITIALIZED (1u << 1u) /*!< BEEP is initialized. */ +#define ADI_BEEP_STATE_PLAYING (1u << 2u) /*!< BEEP is currently playing. */ +#define ADI_BEEP_STATE_BLOCKED (1u << 3u) /*!< BEEP has blocked, waiting completion. */ + +/*! + * \struct ADI_BEEP_DEV_DATA + * Beeper device internal instance data structure. + */ +typedef struct _ADI_BEEP_DEV_DATA +{ + volatile ADI_BEEP_STATE state; /*!< Device state */ + ADI_CALLBACK cbFunc; /*!< Callback function */ + void *cbParam; /*!< Callback parameter */ +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 + ADI_BEEP_NOTE (*pSeqArray)[]; /*!< Pointer to a user-allocated array of notes. */ + volatile uint8_t nSeqIndex; /*!< Index for incrementing sequence */ + uint8_t nSeqMax; /*!< Size of the sequence */ +#endif + SEM_VAR_DECLR +} ADI_BEEP_DEV_DATA; + + +/*! \struct ADI_BEEP_DRIVER_STRUCT + * BEEP Device Structure + */ +typedef struct _ADI_BEEP_DRIVER_STRUCT +{ + ADI_BEEP_TypeDef *pReg; /*!< Pointer to register base */ + ADI_BEEP_DEV_DATA *pData; /*!< Pointer to device data structure */ +} ADI_BEEP_DRIVER_STRUCT; + +/*! \struct ADI_BEEP_STATIC_INIT + * conditionally create static initialization data based on adi_beep_config.h settings + */ +typedef struct { + uint16_t BEEP_CFG; /*!< Beeper configuration register */ + uint16_t BEEP_STAT; /*!< Beeper status register */ + uint16_t BEEP_TONEA; /*!< Beeper ToneA register */ + uint16_t BEEP_TONEB; /*!< Beeper ToneB register */ +} ADI_BEEP_STATIC_INIT; + +/* alias for the actual device structure */ +typedef ADI_BEEP_DRIVER_STRUCT ADI_BEEP_DRIVER; + +/*! \endcond */ + +#endif /* _ADI_BEEP_DEF_H_ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h new file mode 100755 index 00000000000..e35f0bd8c2a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/common.h @@ -0,0 +1,127 @@ +/*! + ***************************************************************************** + * @file: common.h + * @brief: Common include file for all example + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************/ + + +#ifndef COMMON_H +#define COMMON_H + +#ifdef __ICCARM__ +/* +* Pm106 (rule 20.9): the input/output library shall not be used in + production code +* The purpose of this header is to provide I/O facilities based on stdio. +*/ +#pragma diag_suppress=Pm106 +#endif /* __ICCARM__ */ + +#include +#include +#include +#include +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): The basic types of char, int, short, long, float shall not be used. +* Pm064 (rule 16.1): functions with variable number of arguments shall not be used. +*/ +#pragma diag_suppress=Pm011,Pm064 +#endif /* __ICCARM__ */ + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Enable REDIRECT_OUTPUT_TO_UART to send the output to UART terminal. */ +/* #define REDIRECT_OUTPUT_TO_UART */ + +extern char aDebugString[150]; + +#ifdef __ICCARM__ +/* +* Pm154 (rule 19.10): in the definition of a function-like macro, each instance +* of a parameter shall be enclosed in parentheses +* The __VA_ARGS__ macro cannot be enclosed in parentheses. +*/ +#pragma diag_suppress=Pm154 +#endif /* __ICCARM__ */ + +#define DEBUG_MESSAGE(...) \ + do { \ + sprintf(aDebugString,__VA_ARGS__); \ + common_Perf(aDebugString); \ + } while(0) + +#ifdef __ICCARM__ +#pragma diag_default=Pm154 +#endif /* __ICCARM__ */ + +#define DEBUG_RESULT(s,result,expected_value) \ + do { \ + if ((result) != (expected_value)) { \ + sprintf(aDebugString,"%s %d", __FILE__,__LINE__); \ + common_Fail(aDebugString); \ + sprintf(aDebugString,"%s Error Code: 0x%08X\n\rFailed\n\r",(s),(result)); \ + common_Perf(aDebugString); \ + exit(0); \ + } \ + } while (0) + +/******************************************************************************** +* API function prototypes +*********************************************************************************/ +void common_Init(void); +void common_Pass(void); +void common_Fail(char *FailureReason); +void common_Perf(char *InfoString); + +#ifdef __cplusplus +} +#endif + +#endif /* COMMON_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h new file mode 100755 index 00000000000..733f75771c6 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_adc_config.h @@ -0,0 +1,342 @@ +/*! + ***************************************************************************** + @file: adi_adc_config.h + @brief: Configuration options for ADC driver. + This is specific to the ADC driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_ADC_CONFIG_H +#define ADI_ADC_CONFIG_H +#include +/** @defgroup ADC_Driver_Cfg Static Configuration + * @ingroup ADC_Driver + */ + +/** @addtogroup ADC_Driver_Cfg Static Configuration +* @{ +*/ + +/************* ADC Driver configurations ***************/ + + +/*! Configure the default ADC configuration. Oversampling support must be enabled for resolution >12-bits.\n + Valid values are 12 to 16 +*/ +#define ADI_ADC_CFG_RESOLUTION (12) + +/*! Configure the default Vref\n + 3 - External Reference + 2 - Battery Voltage + 1 - 2.5V Internal Reference\n + 0 - 1.25V Internal Reference\n + +*/ +#define ADI_ADC_CFG_VREF (1) + +/*! Enable/Disable MULTI acquisitions of ADC data. + When enabled, DMA will be used for ADC readings which is + the preferred transfer method for multiple transactions. + Otherwise all will be interrupt driven. \n + 1 - Enable MULTI (DMA) acquisitions \n + 0 - Disable MULTI (use Interrupt) acquisitions \n +*/ +#define ADI_ADC_ENABLE_MULTI_ACQUIRE (1) + +/*! Enable/Disable HI/LO Digital Comparator limits \n + 1 - Enable HI/LO Digital Comparator limits\n + 0 - Disable HI/LO Digital Comparator limits\n +*/ +#define ADI_ADC_ENABLE_STATIC_COMPARATOR (1) + +/*! Enable/Disable Channel0 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HI_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel0 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_LO_EN (1) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel0 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_EN (1) /* 0 or 1 */ + +/*! Set the Channel0 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel0 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN0_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN0_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel1 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel1 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel1 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel1 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel1 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN1_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN1_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel2 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel2 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel2 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel2 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel2 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN2_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN2_HYS_CYC (0) /* 3 bits, 0 to 7 */ + +/*! Enable/Disable Channel3 limit comparator \n + 1 - Enable HI Digital Comparator limit\n + 0 - Disable HI Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HI_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator value \n + Sets the HI limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HI_EN is set to 1. \n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HI_VAL (4095) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel3 limit comparator \n + 1 - Enable LO Digital Comparator limit\n + 0 - Disable LO Digital Comparator limit\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_LO_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator value. \n + Sets the LO limit value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_LO_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_LO_VAL (0) /* Range: 0 to 4095 */ + +/*! Enable/Disable Channel3 hysteresis and monitor cycles \n + 1 - Enable hysteresis and monitor cycles\n + 0 - Disable hysteresis and monitor cycles\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_EN (0) /* 0 or 1 */ + +/*! Set the Channel3 limit comparator hysteresis value. \n + Sets the hysteresis value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_VAL (0) /* 9 bits, 0 to 511 */ + +/*! Set the Channel3 limit comparator hysteresis monitor value. \n + Sets the monitor value for the channel, only \n + relevant if ADI_ADC_COMPARATOR_AIN3_HYS_EN is set to 1.\n +*/ +#define ADI_ADC_COMPARATOR_AIN3_HYS_CYC (0) /* 3 bits, 0 to 7 */ + + +/************** Macro validation *****************************/ + +#if (ADI_ADC_CFG_RESOLUTION < 12) || (ADI_ADC_CFG_RESOLUTION > 16) +#error "ADI_ADC_CFG_RESOLUTION is invalid" +#endif + +#if (ADI_ADC_CFG_VREF < 0) || (ADI_ADC_CFG_VREF > 3) +#error "ADI_ADC_CFG_VREF is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN0_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN0_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN1_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN2_HI_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HI_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HI_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN0_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN1_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN2_LO_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_LO_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_LO_VAL > (4095)) +#error "ADI_ADC_COMPARATOR_AIN3_HI_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN0_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN1_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN2_HYS_VAL is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HYS_VAL < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_VAL > (511)) +#error "ADI_ADC_COMPARATOR_AIN3_HYS_VAL is invalid" +#endif + + +#if (ADI_ADC_COMPARATOR_AIN0_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN0_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN0_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN1_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN1_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN1_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN2_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN2_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN2_HYS_CYC is invalid" +#endif + +#if (ADI_ADC_COMPARATOR_AIN3_HYS_CYC < (0)) || (ADI_ADC_COMPARATOR_AIN3_HYS_CYC > (7)) +#error "ADI_ADC_COMPARATOR_AIN3_HYS_CYC is invalid" +#endif + + + + +/*! @} */ + +#endif /* ADI_ADC_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h new file mode 100755 index 00000000000..a78814b0c72 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_beep_config.h @@ -0,0 +1,164 @@ +/*! + ***************************************************************************** + @file: adi_beep_config.h + @brief: Configuration options for BEEP driver. + This is specific to the BEEP driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_BEEP_CONFIG_H +#define ADI_BEEP_CONFIG_H +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * IAR compiler supports longer identifiers. + */ +#pragma diag_suppress=Pm009 +#endif /* __ICCARM__ */ + +/** @addtogroup BEEP_Driver_Config Static Configuration + * @ingroup BEEP_Driver + * @{ + */ + +/************* BEEP Driver configurations ***************/ +/*! Enable the inclusion of adi_beep_PlaySequence(). This \n + API requires more data in the device structures to manage \n + the longer playing sequences, along with extra code in \n + the interrupt handler. \n + 0 - adi_beep_PlaySequence() omitted.\n + 1 - adi_beep_PlaySequence() is included. */ +#define ADI_BEEP_INCLUDE_PLAY_SEQUENCE 1 + +/************* BEEP controller static configurations ***************/ + +/*! Configure beeper disable.\n + 0 - Beeper enabled.\n + 1 - Beeper disabled. */ +#define ADI_BEEP_CFG_BEEPER_DISABLE 0 + +/*! Configure beeper sequence, when using static configuration. \n + 0 - Single note (Tone A only).\n + 1-255 - Sequence mode repeat count (Tone A then B sequentially). */ +#define ADI_BEEP_CFG_SEQUENCE_REPEAT_VALUE 5 + + +/* TONEA CONTROL REGISTER */ + +/*! Initial ToneA Disable.\n + 0 - ToneA Enabled.\n + 1 - ToneA Disabled. */ +#define ADI_BEEP_TONEA_DISABLE 0 + +/*! Initial ToneA Frequency.\n + 0-3 - Rest Tone (no oscillation).\n + 4-127 - Oscillate at 32kHz/freq Hz. */ +#define ADI_BEEP_TONEA_FREQUENCY 20 + +/*! Initial ToneA Duration.\n + 0-254 - Play for 4ms*duration.\n + 255 - Play for infinite duration. */ +#define ADI_BEEP_TONEA_DURATION 2 + + + +/* TONEB CONTROL REGISTER */ + +/*! Initial ToneB Disable.\n + 0 - ToneB Enabled.\n + 1 - ToneB Disabled. */ +#define ADI_BEEP_TONEB_DISABLE 0 + +/*! Initial ToneB Frequency. \n + 0-3 - Rest Tone (no oscillation).\n + 4-127 - Oscillate at 32kHz/freq Hz. */ +#define ADI_BEEP_TONEB_FREQUENCY 50 + +/*! Initial ToneB Duration.\n + 0-254 - Play for 4ms*duration.\n + 255 - Play for infinite duration. */ +#define ADI_BEEP_TONEB_DURATION 2 + + + +#ifdef __ICCARM__ +/* +* Pm085 (rule 19.11): identifiers in pre-processor directives should be defined before use +* The macros in the the following #if directives are defined to enum constants by default. +*/ +#pragma diag_suppress=Pm085 +#endif /* __ICCARM__ */ + +#if (ADI_BEEP_TONEA_DISABLE > 1) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEA_FREQUENCY > 127 ) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEA_DURATION > 255 ) +#error "Invalid configuration" +#endif + +#if (ADI_BEEP_TONEB_DISABLE > 1) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEB_FREQUENCY > 127 ) +#error "Invalid configuration" +#endif + +#if ( ADI_BEEP_TONEB_DURATION > 255 ) +#error "Invalid configuration" +#endif + +#ifdef __ICCARM__ +#pragma diag_default=Pm009,Pm085 +#endif /* __ICCARM__ */ + +/*! @} */ + +#endif /* ADI_BEEP_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h new file mode 100755 index 00000000000..19737e3a883 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crc_config.h @@ -0,0 +1,100 @@ +/*! + ***************************************************************************** + @file: adi_crc_config.h + @brief: Configuration options for CRC driver. + This is specific to the CRC driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_CONFIG_H +#define ADI_CRC_CONFIG_H + +#include + +/** @defgroup CRC_Driver_Cfg Static Configuration + * @ingroup CRC_Driver + */ + +/** @addtogroup CRC_Driver_Cfg Static Configuration +* @{ +*/ + +/************* CRC Driver configurations ***************/ +/*! + Enable DMA support in the driver code.\n + 1 - To have the DMA support code in the driver.\n + 0 - To eliminate the DMA support. Operates in core mode.\n +*/ +#define ADI_CRC_CFG_ENABLE_DMA_SUPPORT 0 + +/*! + Enable Byte mirroring option\n + 1 - To enable byte mirroring \n + 0 - To disable the byte mirroring. +*/ +#define ADI_CFG_CRC_ENABLE_BYTE_MIRRORING 0 +/*! + Enable Bit mirroring option\n + 1 - To enable bit mirroring \n + 0 - To disable the bit mirroring. +*/ +#define ADI_CFG_CRC_ENABLE_BIT_MIRRORING 0 + +/*! + To specify the seed value for CRC computation +*/ + +#define ADI_CFG_CRC_SEED_VALUE (0xFFFFFFFFu) + +/*! + To specify the polynomial to be used for CRC computation +*/ +#define ADI_CFG_CRC_POLYNOMIAL (0x04C11DB7u) + +/*! + To specify the Software DMA channel to be used for the CRC computation + 0 -> DMA channel SIP0, ..., 7 -> DMA channel SIP7 +*/ +#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7 + +#endif /* ADI_CRC_CONFIG_H */ +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h new file mode 100755 index 00000000000..d67f6ab81c1 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_crypto_config.h @@ -0,0 +1,138 @@ +/*! + ***************************************************************************** + @file: adi_crypto_config.h + @brief: Configuration options for Crypto driver. + This is specific to the Crypto driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2014-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef __ADI_CRYPTO_CONFIG_H__ +#define __ADI_CRYPTO_CONFIG_H__ +#include + +/** @addtogroup Crypto_Driver_Config Static Configuration + * @ingroup Crypto_Driver + * @{ + */ + +/************* Crypto Driver configurations ***************/ + +/*! Enable/Disable ECB Support\n + 1 - Enable ECB Support\n + 0 - Disable ECB Support\n +*/ +#define ADI_CRYPTO_ENABLE_ECB_SUPPORT (1) + +/*! Enable/Disable CTR Support\n + 1 - Enable CTR Support\n + 0 - Disable CTR Support\n +*/ +#define ADI_CRYPTO_ENABLE_CTR_SUPPORT (1) + +/*! Enable/Disable CBC Support\n + 1 - Enable CBC Support\n + 0 - Disable CBC Support\n +*/ +#define ADI_CRYPTO_ENABLE_CBC_SUPPORT (1) + +/*! Enable/Disable CCM Support\n + 1 - Enable CCM Support\n + 0 - Disable CCM Support\n +*/ +#define ADI_CRYPTO_ENABLE_CCM_SUPPORT (1) + +/*! Enable/Disable CMAC Support\n + 1 - Enable CMAC Support\n + 0 - Disable CMAC Support\n +*/ +#define ADI_CRYPTO_ENABLE_CMAC_SUPPORT (1) + +/*! Enable/Disable HMAC Support\n + 1 - Enable HMAC Support\n + 0 - Disable HMAC Support\n +*/ +#define ADI_CRYPTO_ENABLE_HMAC_SUPPORT (1) + +/*! Enable/Disable SHA Support\n + 1 - Enable SHA Support\n + 0 - Disable SHA Support\n +*/ +#define ADI_CRYPTO_ENABLE_SHA_SUPPORT (1) + + +/*! Enable/Disable DMA Support\n + 1 - Enable DMA Support\n + 0 - Disable DMA Support +*/ +#define ADI_CRYPTO_ENABLE_DMA_SUPPORT (1) + +/*! Enable/Disable DMA Transfer by default\n + 1 - Enable DMA \n + 0 - Disable DMA +*/ +#define ADI_CRYPTO_ENABLE_DMA (1) + +/*! SHA output format\n + 1 - Big-Endian \n + 0 - Little-Endian +*/ +#define ADI_CRYPTO_SHA_OUTPUT_FORMAT (1) + + + +/************** Macro validation *****************************/ + +#if ((ADI_CRYPTO_ENABLE_DMA_SUPPORT != 0) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT != 1)) +#error "ADI_CRYPTO_ENABLE_DMA_SUPPORT is invalid" +#endif + +#if ((ADI_CRYPTO_ENABLE_DMA != 0) && (ADI_CRYPTO_ENABLE_DMA != 1)) +#error "ADI_CRYPTO_ENABLE_DMA is invalid" +#endif + +#if ((ADI_CRYPTO_ENABLE_DMA == 1) && (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 0)) +#error "DMA cannot be enabled if DMA support is disabled" +#endif + +/*! @} */ + +#endif /* __ADI_CRYPTO_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h new file mode 100755 index 00000000000..4b83c46fd7b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_cycle_counting_config.h @@ -0,0 +1,105 @@ +/*! ***************************************************************************** + * @file adi_cycle_counting_config.h + * @brief Cycle Counting Framework configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_CYCLE_COUNTING_CONFIG_H +#define ADI_CYCLE_COUNTING_CONFIG_H + +/** @addtogroup CYCLE_COUNTING_Config Static Configuration + * @ingroup cyclecount_logging + * @{ + */ + + +/************* Cycle Counting Configuration ***************/ + +/*! Global enable. This must be enabled for any other functionality to work\n + 0u disabled + 1u enabled +*/ +#define ADI_CYCLECOUNT_ENABLED (0u) + +/*! SPI Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of SPI ISR cycle counting. + 1 - Enables the recording of SPI ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_SPI_ISR_ENABLED (0u) + + +/*! CRC Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of CRC ISR cycle counting. + 1 - Enables the recording of CRC ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_CRC_ISR_ENABLED (0u) + + +/*! SPORT Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of SPORT ISR cycle counting. + 1 - Enables the recording of SPORT ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_SPORT_ISR_ENABLED (0u) + +/*! UART Interrupt Mode ISR Cycle Counting Enabled\n + 0 - Disables the recording of UART ISR cycle counting. + 1 - Enables the recording of UART ISR cycle counting. +*/ +#define ADI_CYCLECOUNT_UART_ISR_ENABLED (0u) + + +/*! A user application may desire/require cycle counting in an application defined API + or ISR. Set this macro to the number of required. +*/ +#define ADI_CYCLECOUNT_NUMBER_USER_DEFINED_APIS (0u) + +/*! + * Cycle count 'stack' nesting depth. Adjust as needed. + * This should map to the maximum number of nested interrupts an application might experience. + */ +#define ADI_CYCLECOUNT_STACK_SIZE 10 + +/** + * @} + */ + +#endif /* ADI_CYCLE_COUNTING_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h new file mode 100755 index 00000000000..5eb4e5a779f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_flash_config.h @@ -0,0 +1,299 @@ +/*! + ***************************************************************************** + @file: adi_flash_config.h + @brief: Configuration options for flash driver. + This is specific to the flash driver and will be included by the driver. + It is not required for the application to include this header file. + @version: $Revision: 33205 $ + @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FLASH_CONFIG_H +#define ADI_FLASH_CONFIG_H +#include + +/** @addtogroup Flash_Driver_Config Static Configuration + * @ingroup Flash_Driver + * @{ + */ + + +/****SETTINGS THAT LIVE IN FEE INTERRUPT ENABLE (IEN) REGISTER****/ + + +/*! + * Configure a response to the 2-bit ECC ERROR events (in IEN). + * - 0 Do not generate a response to ECC Error Events. + * - 1 Generate Bus Errors in response to ECC Error Events. + * - 2 Generate IRQs in response to ECC Error Events. + */ +#define ADI_FEE_CFG_ECC_ERROR_RESPONSE (1u) +/*! + * Configure a response to the 1-bit ECC CORRECTION events (in IEN). + * - 0 Do not generate a response to ECC correction Events. + * - 1 Generate Bus Errors in response to ECC correction Events. + * - 2 Generate IRQs in response to ECC correction Events. + */ +#define ADI_FEE_CFG_ECC_CORRECTION_RESPONSE (2u) + + + +/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 0 (TIME_PARAM0) REGISTER****/ + + +/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */ +/*! + * Configure flash non-volatile mass erase hold time.\n + * Upper 4-bits of 11-bit value.\n + * (Lower bits are hard-coded to 0x14.)\n + * Hardware default value is 0xb. + */ +#define ADI_FEE_CFG_PARAM0_TNVH1 (0xbu) + +/*! + * Configure flash erase time.\n + * Upper 4-bits of 19-bit value.\n + * (Lower bits are hard-coded to 0x7370.)\n + * Hardware default value is 0x8. + */ +#define ADI_FEE_CFG_PARAM0_TERASE (0x8u) + +/*! + * Configure flash recovery time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x2.)\n + * Hardware default value is 0x9. + */ +#define ADI_FEE_CFG_PARAM0_TRCV (0x9u) + +/*! + * Configure flash non-volatile hold time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x1.)\n + * Hardware default value is 0x5. + */ +#define ADI_FEE_CFG_PARAM0_TNVH (0x5u) + +/*! + * Configure flash program time.\n + * Upper 4-bits of 10-bit value.\n + * (Lower bits are hard-coded to 0x7.)\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM0_TPROG (0x0u) + +/*! + * Configure flash NVSTR-to-program setup time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x2.)\n + * Hardware default value is 0x9. + */ +#define ADI_FEE_CFG_PARAM0_TPGS (0x9u) + +/*! + * Configure flash program/erase-to-NVSTR setup time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0x1.)\n + * Hardware default value is 0x5. + */ +#define ADI_FEE_CFG_PARAM0_TNVS (0x5u) + +/*! + * Configure flash reference clock divide-by-2 setting.\n + * All timing parameters are referenced to this parameter. + * - 0 Reference clock is not divided. + * - 1 Reference clock is divided by 2.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM0_CLKDIV (0x0u) + + + +/****SETTINGS THAT LIVE IN FEE TIME PARAMETER 1 (TIME_PARAM1) REGISTER****/ + + +/* It is recommended to NOT MODIFY flash timing parameters without keen insight and caution */ +/*! + * Configure flash read access wait states.\n + * Number of 3-bit read access wait states to use.\n + * Maximum allowed value is 0x4.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_PARAM1_WAITESTATES (0x0u) + +/*! + * Configure flash sleep mode wake-up time.\n + * Upper 4-bits of 8-bit value.\n + * (Lower bits are hard-coded to 0xb.)\n + * Hardware default value is 0x4. + */ +#define ADI_FEE_CFG_PARAM1_TWK (0x4u) + + + +/****SETTINGS THAT LIVE IN FEE SYSTEM ABOUT ENABLE (ABOUT_EN_XX) REGISTERS****/ + + +/*! + * Configure lower (0-31) flash system interrupt abort enables.\n + * Allows system interrupts to abort an ongoing flash command.\n + * Only 64 system interrupts are supported.\n + * Lower interrupts (0-31) are encoded in ADI_FEE_CFG_ABORT_EN_LO, + * - 0 Corresponding interrupt is prevented from aborting flash command. + * - 1 Corresponding interrupt is allowed to abort flash command.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_ABORT_EN_LO (0x0u) + +/*! + * Configure upper (32-63) flash system interrupt abort enables.\n + * Allows system interrupts to abort an ongoing flash command.\n + * Only 64 system interrupts are supported.\n + * Upper interrupts (32-63) are encoded in ADI_FEE_CFG_ABORT_EN_HI. + * - 0 Corresponding interrupt is prevented from aborting flash command. + * - 1 Corresponding interrupt is allowed to abort flash command.\n + * Hardware default value is 0x0. + */ +#define ADI_FEE_CFG_ABORT_EN_HI (0x0u) + + + +/****SETTINGS THAT LIVE IN ECC CONFIG REGISTER (ECC_CFG) REGISTER****/ + + +/*! + * ECC Start Page Pointer (in ECC_CFG). + */ +#define ADI_FEE_CFG_ECC_START_PAGE (0u) + +/*! + * Enable/Disable ECC for info space (in ECC_CFG). + * - 1 Enable Info Space. + * - 0 Disable Info Space. + */ +#define ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE (0u) + +/*! + * Enable/Disable ECC (in ECC_CFG). + * - 1 Enable ECC. + * - 0 Disable ECC. + */ +#define ADI_FEE_CFG_ENABLE_ECC (0u) + + + +/************* Flash Driver Configuration Settings Checkers ***************/ + + + +/* IEN CHECKS */ +#if ((ADI_FEE_CFG_ECC_ERROR_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_ERROR_RESPONSE > 2u)) +#error "ADI_FEE_CFG_ECC_ERROR_RESPONSE should be in the range 0-2." +#endif +#if ((ADI_FEE_CFG_ECC_CORRECTION_RESPONSE < 0u) || (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE > 2u)) +#error "ADI_FEE_CFG_ECC_CORRECTION_RESPONSE should be in the range 0-2." +#endif + + + +/* PARAM0 CHECKS */ +#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TERASE < 0u) || (ADI_FEE_CFG_PARAM0_TERASE > 15u)) +#error "ADI_FEE_CFG_PARAM0_TERASE should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TRCV < 0u) || (ADI_FEE_CFG_PARAM0_TRCV > 15u)) +#error "ADI_FEE_CFG_PARAM0_TRCV should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TNVH1 < 0u) || (ADI_FEE_CFG_PARAM0_TNVH1 > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVH1 should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TPROG < 0u) || (ADI_FEE_CFG_PARAM0_TPROG > 15u)) +#error "ADI_FEE_CFG_PARAM0_TPROG should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TPGS < 0u) || (ADI_FEE_CFG_PARAM0_TPGS > 15u)) +#error "ADI_FEE_CFG_PARAM0_TPGS should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_TNVS < 0u) || (ADI_FEE_CFG_PARAM0_TNVS > 15u)) +#error "ADI_FEE_CFG_PARAM0_TNVS should be in the range 0-15." +#endif +#if ((ADI_FEE_CFG_PARAM0_CLKDIV < 0u) || (ADI_FEE_CFG_PARAM0_CLKDIV > 1u)) +#error "ADI_FEE_CFG_PARAM0_CLKDIV should be in the range 0-1." +#endif + + + +/* PARAM1 CHECKS */ +#if ((ADI_FEE_CFG_PARAM1_WAITESTATES < 0u) || (ADI_FEE_CFG_PARAM1_WAITESTATES > 4u)) +#error "ADI_FEE_CFG_PARAM1_WAITESTATES should be in the range 0-4." +#endif +#if ((ADI_FEE_CFG_PARAM1_TWK < 0u) || (ADI_FEE_CFG_PARAM1_TWK > 15u)) +#error "ADI_FEE_CFG_PARAM1_TWK should be in the range 0-15." +#endif + + + +/* ABORT_EN_XX CHECKS */ +#if ((ADI_FEE_CFG_ABORT_EN_LO < 0u) || (ADI_FEE_CFG_ABORT_EN_LO > 0XFFFFu)) +#error "ADI_FEE_CFG_ABORT_EN_LO should be in 32-bit range." +#endif +#if ((ADI_FEE_CFG_ABORT_EN_HI < 0u) || (ADI_FEE_CFG_ABORT_EN_HI > 0XFFFFu)) +#error "ADI_FEE_CFG_ABORT_EN_HI should be in 32-bit range." +#endif + + + +/* ECC_CFG CHECKS */ +#if (((ADI_FEE_CFG_ECC_START_PAGE >> 8u) << 8) != ADI_FEE_CFG_ECC_START_PAGE) +#error "ADI_FEE_CFG_ECC_START_PAGE has invalid bits set in lower 8-bits." +#endif +#if ((ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 0u) && (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE != 1u)) +#error "ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE should be 1 or 0." +#endif +#if ((ADI_FEE_CFG_ENABLE_ECC != 0u) && (ADI_FEE_CFG_ENABLE_ECC != 1u)) +#error "ADI_FEE_CFG_ENABLE_ECC should be 1 or 0." +#endif + +/*! @} */ + +#endif /* ADI_FLASH_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h new file mode 100755 index 00000000000..6d205577a3b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_global_config.h @@ -0,0 +1,131 @@ +/*! + ***************************************************************************** + @file: adi_global_config.h + @brief: Configuration options for all the drivers. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_GLOBAL_CONFIG_H +#define ADI_GLOBAL_CONFIG_H + +/** @addtogroup GLOBAL_Driver_Config Global Static Configuration + * @brief Configuration options for all the drivers. + * @{ + */ + +/*! @name RTOS used + * In order to be used in a multi-threaded application, the device drivers + * may require the use of some RTOS-specific signals like semaphores or actions + * may be required when entering/exiting an interrupt. By specifying the RTOS + * that the application uses, the drivers can map their requirements to the + * specific RTOS, without requiring an OS abstraction layer. + * @note This macros do not add the RTOS sources to the application, users need + * to set up the source and include paths in their application themselves + * @note If the RTOS specified is not in the list of supported RTOS the build + * mechanism fails + */ +/**@{*/ + +/*! @hideinitializer Indicates that no RTOS is used (bare-metal applications) */ +#define ADI_CFG_RTOS_NO_OS (1) +/*! @hideinitializer Indicates that Micrium uCOS-III is used */ +#define ADI_CFG_RTOS_MICRIUM_III (2) +/*! @hideinitializer Indicates that Micrium FreeRTOS is used */ +#define ADI_CFG_RTOS_FREERTOS (3) + +/*! Configure the RTOS required across the project. + It can be configured to one of the following macros: + - #ADI_CFG_RTOS_NO_OS + - #ADI_CFG_RTOS_MICRIUM_III + - #ADI_CFG_RTOS_FREERTOS + */ +#define ADI_CFG_RTOS ADI_CFG_RTOS_NO_OS + +/**@}*/ + +/*! @name Low power mode support + All applications may have to block when a buffer is being processed. In the + case of an RTOS application, when a task is blocked waiting for a buffer, a + different task can run. If no tasks are available then the idle task runs. + In many RTOS the idle task can be configured so it perform actions like + entering low power modes. + + In the case of a bare-metal (no RTOS) application, since there are no other + tasks to be run, the driver can enter low power modes itself when it blocks. + */ + +/*! Configures the drivers to enter low power mode (Flexi mode) + when waiting for a buffer to be processed. This macro is applicable + only when the drivers are operating in the bare metal mode (No RTOS). + + The possible values it can be configured to are: + + - 1 : Low power mode support required. + - 0 : Low power mode support not required. +*/ +#define ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT (1) +/**@}*/ + + + +/* +** Verify the macro configuration +*/ +#if ((ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_MICRIUM_III) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_FREERTOS)) +#error "ADI_CFG_RTOS macro wrongly configured" +#endif /* ADI_CFG_RTOS verification */ + +#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 0) && \ + (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT != 1)) +#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT macro is wrongly configured" +#endif + +#if ((ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) && \ + (ADI_CFG_RTOS != ADI_CFG_RTOS_NO_OS)) +#error "ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT cannot be set to 1 in multi-threaded applications" +#endif +/** + * @} + */ + +#endif /* ADI_GLOBAL_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h new file mode 100755 index 00000000000..0f6bbca875a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_i2c_config.h @@ -0,0 +1,226 @@ +/*! + ***************************************************************************** + @file: adi_i2c_config.h + @brief: Configuration options for I2C driver. + This is specific to the I2C driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_I2C_CONFIG_H +#define ADI_I2C_CONFIG_H +#include + +/** @addtogroup I2C_Driver_Config Static Configuration + * @ingroup I2C_Driver + * @{ + */ + +/************* I2C Driver configurations ***************/ + +/*! Master control register TX FIFO decrement control bit.\n + 1 - Decrement master TX FIFO status when a byte has been fully serialized.\n + 0 - Decrement master TX FIFO status when a byte is unloaded from the TX FIFO, + but not yet serialized on the bus. */ +#define ADI_I2C_CFG_MCTL_MXMITDEC (0) + +/*! Master control register STOP condition interrupt enable.\n + 1 - Enable completion interrupt when a STOP condition is detected.\n + 0 - Disable completion interrupt when a STOP condition is detected. */ +#define ADI_I2C_CFG_MCTL_IENCMP (1) + +/*! Master control register NACK (NotACKnowledge) interrupt enable.\n + 1 - Enable NACK interrupt when an acknowledge is not received.\n + 0 - Disable NACK interrupt when an acknowledge is not received. */ +#define ADI_I2C_CFG_MCTL_IENACK (1) + +/*! Master control register ALOST (Arbitration LOST) interrupt enable.\n + 1 - Enable ALOST interrupt when bus arbitration is lost.\n + 0 - Disable ALOST interrupt when bus arbitration is lost. */ +#define ADI_I2C_CFG_MCTL_IENALOST (1) + +/*! Master control register clock stretch enable.\n + 1 - Enable clock stretch by slave device.\n + 0 - Disable clock stretch by slave device. */ +#define ADI_I2C_CFG_MCTL_STRETCHSCL (0) + +/*! Master control register internal loopback enable.\n + 1 - Enable internal looping of SCL and SDA outputs onto their corresponding inputs.\n + 0 - Disable internal looping of SCL and SDA outputs onto their corresponding inputs. */ +#define ADI_I2C_CFG_MCTL_LOOPBACK (0) + +/*! Master control register start condition back-off disable.\n + 1 - Enables controller to compete for bus ownership even if another device is driving a START condition.\n + 0 - Disables controller to compete for bus ownership even if another device is driving a START condition. */ +#define ADI_I2C_CFG_MCTL_COMPLETE (0) + +/*! Master control register device enable.\n + 1 - Enable controller as a Master device.\n + 0 - Disables controller as a Master device. */ +#define ADI_I2C_CFG_MCTL_MASEN (0) + +/*! + * Standard Clock divider Clock-HI settings. + * Assuming a 26 MHz core clock, the following settings + * will be useful: \n + * - For STANDARD (100 kHz) rate, use: HI= 25, LO= 31. \n + * - For FAST (400 kHz) rate, use: HI=123, LO=129. \n + * \n + * @note The clock high setting varies with pull-up loading, + * board layout, slew-rate, etc., so exact settings are somewhat + * empirical. The clock high counter does not start until + * a logic high transition is sensed on the clock line, so + * variability in this logic transaction will alter the + * effective clock rate. This results from the internal + * clock-stretch hardware feature supporting a slave slow device + * that may hold off the master by holding the clock line low. + * + * @sa ADI_I2C_CFG_DIV_LOW + */ +#define ADI_I2C_CFG_DIV_HIGH (25) + +/*! Standard Clock divider Clock-LO setting + * + * @sa ADI_I2C_CFG_DIV_HIGH + */ +#define ADI_I2C_CFG_DIV_LOW (31) + +/*! Shared control reset START/STOP detect circuit.\n + 1 - Reset the SCL and SDA synchronizers, START/STOP detect logic, and LINEBUSY detect logic.\n + 0 - Do nothing. */ +#define ADI_I2C_CFG_SHCTL_RST (0) + +/*! Timing control filter disable.\n + 1 - Disable digital input clock filter.\n + 0 - Enable digital input clock filter (1 PCLK). */ +#define ADI_I2C_CFG_TCTL_FILTEROFF (0) + +/*! Timing control data input hold time requirement to recognize START/STOP condition (5-bit max).\n + Value - Minimum data input hold time count in units of PCLK period. (Value = Thd/PCLK-period) */ +#define ADI_I2C_CFG_TCTL_THDATIN (1) + +/*! Master automatic stretch mode duration (4-bit), e.g., (in binary):\n + - 0b0000 - No SCL clock stretching.\n + - 0b0001 - Timeout after hold SCL LOW 2^1 = 2 bit-times.\n + - 0b0010 - Timeout after hold SCL LOW 2^2 = 4 bit-times.\n + - ...\n + - 0b1110 - Timeout after hold SCL LOW 2^14 = 16,384 bit-times.\n + - 0b1111 - Hold SCL LOW with no timeout.\n +\n + Where "bit-time" is computed by CLKDIV values and incoming UCLK (see HRM). */ +#define ADI_I2C_CFG_ASTRETCH_MST (0) + +/*! Unformatted, 7-bit max width I2C "7-bit Addressing" slave device address value (unshifted and excluding R/W direction bit).\n + For example, the value:\n + 0x50 - Is the "raw" (unencoded) slave address for the "Aardvark Activity Board" ATMEL AT24C02 I2C slave EEPROM device.\n + It is encoded (upshifted by one and ORed with R/W direction bit) on the I2C bus as:\n + - 0xA0 for write operations, or\n + - 0xA1 for read operations */ +#define ADI_I2C_CFG_SLAVE_ADDRESS (0x50) + + +/***********************************\ +|* Check for overflowing values... *| +\***********************************/ + +#if (ADI_I2C_CFG_MCTL_MXMITDEC >> 1) +#error "Decrement TX FIFO status config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENCMP >> 1) +#error "Transaction complete (STOP) interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENACK >> 1) +#error "NACK interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_IENALOST >> 1) +#error "ALOST interrupt enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_STRETCHSCL >> 1) +#error "Clock stretch enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_LOOPBACK >> 1) +#error "Loopback enable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_COMPLETE >> 1) +#error "Start back-off disable config value too wide" +#endif + +#if (ADI_I2C_CFG_MCTL_MASEN >> 1) +#error "Master device enable config value too wide" +#endif + +#if (ADI_I2C_CFG_DIV_HIGH >> 8) +#error "Clock HIGH time config value too wide" +#endif + +#if (ADI_I2C_CFG_DIV_LOW >> 8) +#error "Clock LOW time config value too wide" +#endif + +#if (ADI_I2C_CFG_SHCTL_RST >> 1) +#error "Shared control reset config value too wide" +#endif + +#if (ADI_I2C_CFG_TCTL_FILTEROFF >> 1) +#error "Timing control filter-off config value too wide" +#endif + +#if (ADI_I2C_CFG_TCTL_THDATIN >> 5) +#error "Timing control filter-off config value too wide" +#endif + +#if (ADI_I2C_CFG_ASTRETCH_MST >> 4) +#error "Master clock stretch config value too wide" +#endif + +#if (ADI_I2C_CFG_SLAVE_ADDRESS >> 7) +#error "Slave address config value too wide" +#endif + +/*! @} */ + +#endif /* ADI_I2C_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h new file mode 100755 index 00000000000..11207b99478 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_pwr_config.h @@ -0,0 +1,638 @@ +/* + ***************************************************************************** + @file: adi_pwr_config.h + @brief: Configuration options for PWR driver. + This is specific to the PWR driver and will be included by the source file. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_PWR_CONFIG_H +#define ADI_PWR_CONFIG_H +#include +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. +* +* Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. +* The YODA-generated headers rely on more. The IAR compiler supports that. +*/ +#pragma diag_suppress=Pm009 +#endif /* __ICCARM__ */ + +/** @addtogroup PWR_Driver_Config Static Configuration + * @ingroup Power_Driver + * @{ + */ + +/*! Enable the code to support input clock through the GPIO pin + 0 - No support for input clock through the GPIO pin. + 1 - Support for input clock through the GPIO pin. + +*/ +#define ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO 0 + +/*------------------------------------------------------------------------------- + Set of MACROs for configuring the clock +--------------------------------------------------------------------------------*/ +/* Oscillator Control Register */ + +/*! + 32 KHz clock select mux. This clock connects to beeper, RTC.\n + 0 - Internal 32 KHz oscillator is selected.\n + 1 - External 32 KHz crystal is selected.. +*/ +#define ADI_PWR_LF_CLOCK_MUX 0 + + +/*! + High frequency internal oscillator enable\n + 0 - The HFOSC oscillator is disabled and placed in a low power state\n + 1 - The HFOSC oscillator is enabled. +*/ +#define ADI_PWR_HFOSC_CLOCK_ENABLE 1 + +/*! + Low frequency external oscillator enable and placed in a low power state\n + 0 - The LFXTAL oscillator is disabled\n + 1 - The LFXTAL oscillator is enabled. +*/ +#define ADI_PWR_LFXTAL_CLOCK_ENABLE 0 + +/*! + High frequency external oscillator enable\n + 0 - The HFXTAL oscillator is disabled and placed in a low power state\n + 1 - The HFXTAL oscillator is enabled. +*/ +#define ADI_PWR_HFXTAL_CLOCK_ENABLE 0 + +/*! + Low frequency external clock fail interrupt enable \n + 0 - The LFXTAL clock monitor and clock fail interrupt disabled \n + 1 - The LFXTAL clock monitor and clock fail interrupt enabled. +*/ +#define ADI_PWR_LFXTAL_CLOCK_MON_ENABLE 0 + +/*! + Automatic switching of the LF Mux to LF Oscillator on LFXTAL failure. \n + 0 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure \n + 1 - Disables Automatic switching of LF Mux to LF Oscillator on LFXTAL failure. +*/ +#define ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE 0 + +/*! + Low frequency crystal Robust mode enable. The Robust mode enables the LFXTAL oscillator to work also when an + additional resistive load is placed between the crystal pins and GND. \n + 0 - Selects Normal mode \n + 1 - Selects Robust mode +*/ +#define ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE 0 + +/*! + Low frequency crystal Robust mode load select. The amount of loading tolerated when robust mode is enabled. \n + 0 - No Trim, and big resistive loads not tolerated. \n + 1 - 20 Mohm load mode, greater than 20 Mohm load allowed. \n + 2 - 10 Mohm load mode, greater than 10 Mohm load allowed. \n + 3 - 5 Mohm load mode, 5 Mohm load allowed on both IO pins. +*/ +#define ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT 0 + + +/*! + Root clock monitor and Clock Fail interrupt enable. + 0 - Disable Root Clock Monitor and Clock Fail interrupt. + 1 - Enable Root Clock Monitor and Clock Fail interrupt. +*/ +#define ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE 0 + + +/*! + Enable Auto switch to High Frequency Oscillator (HFOSC) when Root Clock Fails. + 0 - Disable Automatic switching of the Root Clock. + 1 - Enable Automatic switching of the Root Clock. +*/ +#define ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE 0 + + +/********** Miscellaneous clock setting register CTL0 *************/ + +/*! + Selecting the input clock for Root Clock mux. Determines which single shared clock source + is used by the PCLK, and HCLK dividers. \n + 0 - HFOSC High frequency internal oscillator \n + 1 - HFXTAL High frequency external oscillator\n + 2 - SPLL Output of System PLL is selected\n + 3 - External GPIO port is selected +*/ +#define ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX 0 + +/*! + GPIO clock out select. Selects the clock to be routed to the GPIO clock out pin. \n + 0 - Root Clock (ROOT_CLK)\n + 1 - Low Frequency Clock (LF_CLK) \n + 2 - ADC Clock (ACLK) \n + 3 - HCLK_BUS \n + 4 - HCLK_CORE \n + 5 - Peripheral Clock (PCLK) + 6 - Reference Clock for Flash controller timer (RCLK)\n + 7 - Mux of HFOSC, HFXTAL clock (RHP_CLK)\n + 8 - GP Timer 0 clock (GPT0_CLK)\n + 9 - GP Timer 1 clock (GPT1_CLK)\n + 10 - Peripherals operating at HCLK (HCLK_P)\n + 11 - PLL Clock out (PCLK)\n + 12 - RTC0 Clock \n + 13 - HP Buck Clock (HPBUCK_CLK)\n + 14 - HP Buck Non overlap clock\n + 15 - RTC1 generated clock +*/ +#define ADI_PWR_GPIO_CLOCK_OUT_SELECT 0 + +/*! + Flash reference clock and HPBUCK clock source mux. \n + 0 - sourcing from HFOSC (High frequency internal oscillator) \n + 2 - sourcing from external HFXTAL( High frequency external oscillator 26M Hz )\n + 3 - sourcing from external HFXTAL( High frequency external oscillator 16M Hz ) + +*/ +#define ADI_PWR_INPUT_TO_RCLK_MUX 0 + +/*! + Selecting the input clock for the system PLL clock. \n + 0 - sourcing from HFOSC (High frequency internal oscillator) \n + 1 - sourcing from HFXTAL(High frequency external oscillator) \n + 2 - GPIO Input clock. \n + 3 - GPIO Input clock. +*/ +#define ADI_PWR_INPUT_TO_SPLL_MUX 0 + +/*! + External Low frequency crystal interrupt enable.\n + 0 - Disable the interrupt for LF clock \n + 1 - Enable the interrupt for LF clock +*/ +#define ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE 0 + +/*! + External Hight frequency crystal interrupt enable.\n + 0 - Disable the interrupt for HFXTAL clock \n + 1 - Enable the interrupt for HFXTAL clock +*/ +#define ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE 0 + + + +/********** Clock divider register CTL1 ***************/ + +/*! + HCLK divide count.Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/HCLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_HCLK_DIVIDE_COUNT 4 + +/*! + PCLK divide count.Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/PCLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_PCLK_DIVIDE_COUNT 4 + +/*! + ACLK divide count.Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/ACLKDIVCNT. + 0 - 63 is valid range. +*/ +#define ADI_PWR_ACLK_DIVIDE_COUNT 16 + + +/************* HF Oscillator divide clock select register CTL2 ***********/ + +/*! + HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode. + + When enabled enabled (Set to 1), the frequency undivided 26MHz HF oscillator clock itself will be used during the wake up. + The undivided HFOSC clock is selected automatically by clearing the HFOSCDIVCLKSEL register content to 0, which selects the HFOSC/1 clock.This updated divided by 1 clock selection will remain same until the new divider value is written to this register. + + When disabled (Set to 0), this fast wake up feature will be disabled and the HFOSCDIVCLKSEL register will remain unchanged + during the wakeup. + + 0 - Auto select HFOSC/1 clock during wakeup from Flexi mode is disable. + 1 - Auto select HFOSC/1 clock during wakeup from Flexi mode is enabled. +*/ +#define ADI_PWR_HFOSC_AUTO_DIV_BY_1 0 + +/*! + HF Oscillator divide select. + 0 - HFOSC/1. \n + 1 - HFOSC/2. \n + 2 - HFOSC/4. \n + 3 - HFOSC/8. \n + 4 - HFOSC/16. \n + 5 - HFOSC/32. +*/ +#define ADI_PWR_HFOSC_DIVIDE_SELECT 0 + + + +/****** System PLL Register CTL3 *****/ +/*! + System PLL N multiplier(SPLL_NSEL). Sets the N value used to obtain the multiplication + factor N/M of the PLL. + 8 - 31 is valid range. +*/ +#define ADI_PWR_SPLL_MUL_FACTOR 26 + +/*! + System PLL division by 2. Controls if an optional divide by two is placed on the PLL output.\n + 0 - The System PLL is not divided. Its output frequency equals that selected by the N/M ratio \n + 1 - The System PLL is divided by two. Its output frequency equals that selected by the N/M ratio + with an additional divide by 2 +*/ +#define ADI_PWR_SPLL_ENABLE_DIV2 0 + +/*! + System PLL enable. Controls if the PLL should be enabled or placed in its low power state. \n + 0 - The system PLL is disabled and is in its power down state\n + 1 - The system PLL is enabled. +*/ +#define ADI_PWR_SPLL_ENABLE 0 + +/*! + System PLL interrupt enable.Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt generated.\n + 0 - Disable the SPLL interrupt generation\n + 1 - Enable the SPLL interrupt generation +*/ +#define ADI_PWR_SPLL_INTERRUPT_ENABLE 0 + +/*! + System PLL M Divider(SPLL_MSEL). Sets the M value used to obtain the multiplication + factor N/M of the PLL. + 2 - 15 is valid range. +*/ +#define ADI_PWR_SPLL_DIV_FACTOR 13 + +/*! + system PLL multiply by 2. This bit is used to configure if the VCO clock frequency should be multiplied by 2 or 1.\n + 0 - The System PLL is multiplied by 1.\n + 1 - The System PLL is multiplied by 2. +*/ +#define ADI_PWR_SPLL_ENABLE_MUL2 0 + + +/********** User Clock Gating Control CTL5 ********************/ + +/*! + This can be used to enable/disable clock to GPT0. \n + 0 - Disable the clock to GPT0\n + 1 - Enable the clock to GPT0 +*/ +#define ADI_PWR_GPT0_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to GPT1. \n + 0 - Disable the clock to GPT1\n + 1 - Enable the clock to GPT1 +*/ +#define ADI_PWR_GPT1_CLOCK_ENABLE 1 +/*! + This can be used to enable/disable clock to GPT2. \n + 0 - Disable the clock to GPT2\n + 1 - Enable the clock to GPT2 +*/ +#define ADI_PWR_GPT2_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to I2C. \n + 0 - Disable the clock to I2C\n + 1 - Enable the clock to I2C +*/ +#define ADI_PWR_I2C_CLOCK_ENABLE 1 + +/*! + This can be used to enable/disable clock to GPIO. \n + 0 - Disable the clock to GPIO\n + 1 - Enable the clock to GPIO +*/ +#define ADI_PWR_GPIO_CLOCK_ENABLE 1 + + +/*! + This can be used to enable/disable all clocks connected to peripherals. \n + 0 - Disable the Clock supply to peripherals\n + 1 - Enable the Clock supply to peripherals +*/ +#define ADI_PWR_PCLK_ENABLE 0 + + +/*! + This can be used to enable/disable clocks to Timer RGB. \n + 0 - Disable the Clock supply to Timer RGB \n + 1 - Enable the Clock supply to Timer RGB +*/ +#define ADI_PWR_TIMER_RGB_ENABLE 1 + +/*------------------------------------------------------------------------------- + Set of macros for configuring the power management module +--------------------------------------------------------------------------------*/ + +/********* Interrupt enable register IEN ********/ + +/*! + Enabling the interrupt if the Battery voltage falls below 1.8V.\n + 0 - Disable Battery voltage interrupt \n + 1 - Enable Battery voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VBAT_INTERRUPT 0 + +/*! + Enabling the interrupt for under VREG voltage (i.e less than 1V).\n + 0 - Disable VREG under voltage interrupt \n + 1 - Enable VREG under voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT 0 + +/*! + Enabling the interrupt for over VREG voltage (i.e above than 1.32V).\n + 0 - Disable VREG over voltage interrupt \n + 1 - Enable VREG over voltage interrupt. +*/ +#define ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT 0 + +/*! + Enabling the interrupt for Battery range.\n + 0 - Disable battery voltage range interrupt \n + 1 - Enable battery voltage range interrupt +*/ +#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT 0 + +/*! + Battery voltage range for generating the interrupt.\n + 0 - Configure to generate interrupt if VBAT > 2.75V \n + 1 - Configure to generate interrupt if VBAT is between 2.75 and 1.6V \n + 2 - Configure to generate interrupt if VBAT is between 2.3V and 1.6V +*/ +#define ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT 0 + +/********* HP Buck control register CTL1 ********/ +/*! + Enable or disable HP Buck.\n + 0 - Disable HP Buck. + 1 - Enable HP Buck. +*/ +#define ADI_PWR_HP_BUCK_ENABLE 0 + +/*! + HP Buck Load mode.\n + 0 - HP Buck low load mode. Can be set when the system is running at + less than 26 Mhz. \n + 1 - HP Buck High load mode. Can be set when the system is running at + more than 26 Mh. +*/ +#define ADI_PWR_HP_BUCK_LOAD_MODE 0 + +/*! + HP Buck low power mode.\n + The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode + and low power modules such as Timer, Beeper only are enabled + + 0 - HPBUCK Low power mode is disabled. \n + 1 - HPBUCK Low power mode is enabled. +*/ +#define ADI_PWR_HP_BUCK_LOW_POWER_MODE 0 + + +/********* Power mode register ********/ + +/*! + Enable or disable monitoring battery voltage (VBAT) during HIBERNATE Mode. \n + 0 - Battery voltage monitoring is enabled. + 1 - Battery voltage monitoring is disabled. + + By default battery voltage monitoring during hibernate is enabled. +*/ +#define ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING 0 + + +/******************************************************************************* + M A C R O V A L I D A T I O N +*******************************************************************************/ + +#if ( ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO > 1 ) +#error "Invalid configuration set for ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO" +#endif + +#if ( ADI_PWR_LF_CLOCK_MUX > 1 ) +#error "Invalid configuration set for ADI_PWR_LF_CLOCK_MUX" +#endif + +#if ( ADI_PWR_HFOSC_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_HFXTAL_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_MON_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_MON_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE" +#endif + +#if ( ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT > 3 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT" +#endif + +#if ( ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE" +#endif + +#if ( ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE" +#endif + +#if ( ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX" +#endif + +#if ( ADI_PWR_GPIO_CLOCK_OUT_SELECT > 15 ) +#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_OUT_SELECT" +#endif + +#if ( ADI_PWR_INPUT_TO_RCLK_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_RCLK_MUX" +#endif + +#if ( ADI_PWR_INPUT_TO_SPLL_MUX > 3 ) +#error "Invalid configuration set for ADI_PWR_INPUT_TO_SPLL_MUX" +#endif + +#if ( ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_HCLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_HCLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_PCLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_PCLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_ACLK_DIVIDE_COUNT > 63 ) +#error "Invalid configuration set for ADI_PWR_ACLK_DIVIDE_COUNT" +#endif + +#if ( ADI_PWR_HFOSC_AUTO_DIV_BY_1 > 1 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_AUTO_DIV_BY_1" +#endif + +#if ( ADI_PWR_HFOSC_DIVIDE_SELECT > 5 ) +#error "Invalid configuration set for ADI_PWR_HFOSC_DIVIDE_SELECT" +#endif + +#if ( ADI_PWR_SPLL_MUL_FACTOR < 8 || ADI_PWR_SPLL_MUL_FACTOR > 31 ) +#error "Invalid configuration set for ADI_PWR_SPLL_MUL_FACTOR" +#endif + +#if ( ADI_PWR_SPLL_ENABLE_DIV2 > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_DIV2" +#endif + +#if ( ADI_PWR_SPLL_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE" +#endif + +#if ( ADI_PWR_SPLL_INTERRUPT_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_INTERRUPT_ENABLE" +#endif + +#if ( ADI_PWR_SPLL_DIV_FACTOR < 2 || ADI_PWR_SPLL_DIV_FACTOR > 15 ) +#error "Invalid configuration set for ADI_PWR_SPLL_DIV_FACTOR" +#endif + +#if ( ADI_PWR_SPLL_ENABLE_MUL2 > 1 ) +#error "Invalid configuration set for ADI_PWR_SPLL_ENABLE_MUL2" +#endif + +#if ( ADI_PWR_GPT0_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT0_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPT1_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT1_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPT2_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPT2_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_I2C_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_I2C_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_GPIO_CLOCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_GPIO_CLOCK_ENABLE" +#endif + +#if ( ADI_PWR_PCLK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_PCLK_ENABLE" +#endif + +#if ( ADI_PWR_TIMER_RGB_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_TIMER_RGB_ENABLE" +#endif + +#if ( ADI_PWR_ENABLE_VBAT_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VBAT_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT" +#endif + +#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT" +#endif + +#if ( ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT > 2 ) +#error "Invalid configuration set for ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT" +#endif + +#if ( ADI_PWR_HP_BUCK_ENABLE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_ENABLE" +#endif + +#if ( ADI_PWR_HP_BUCK_LOAD_MODE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOAD_MODE" +#endif + +#if ( ADI_PWR_HP_BUCK_LOW_POWER_MODE > 1 ) +#error "Invalid configuration set for ADI_PWR_HP_BUCK_LOW_POWER_MODE" +#endif + +#if ( ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING > 1 ) +#error "Invalid configuration set for ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING" +#endif + + + +/*! @} */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm009 +#endif /* __ICCARM__ */ + +#endif /* ADI_PWR_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h new file mode 100755 index 00000000000..76afe147cfb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rng_config.h @@ -0,0 +1,106 @@ +/*! + ***************************************************************************** + @file: adi_rng_config.h + @brief: Configuration options for RNG driver. + This is specific to the RNG driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_RNG_CONFIG_H__ +#define ADI_RNG_CONFIG_H__ +#include +/** @defgroup RNG_Driver_Cfg RNG Driver Configuration + * @ingroup RNG_Driver + + */ + +/*! \addtogroup RNG_Driver_Cfg RNG Driver Configuration + * @{ + */ + +/************* RNG Driver configurations ***************/ + +/************* RNG controller configurations ***************/ + +/*! RNG Control Register, bit 3\n + Enable only 8-bit generation\n + 0 - Generate 32-bit random number\n + 1 - Generate only 8-bit random number +*/ +#define RNG0_CFG_ONLY_8_BIT 1 + +/*! RNG Sample Length Register, bits [11:0]\n + The register defines the number of samples to accumulate in the + CRC register when generating a random number.\n + + Bits [11:0] contains the reload value of the sample counter + + */ +#define RNG0_CFG_LENGTH_RELOAD 256u + +/*! RNG Sample Length Register, bits [15:12]\n + The register defines the number of samples to accumulate in the + CRC register when generating a random number. The number of values + accumulated in the counter reload value is scaled by 2^prescaler.\n + + Bits [15:12] contains the prescaler for the sample counter + + */ +#define RNG0_CFG_LENGTH_PRESCALER 0u + +/************** Macro validation *****************************/ + +#if ( RNG0_CFG_ONLY_8_BIT > 1 ) +#error "Invalid configuration" +#endif + +#if ( RNG0_CFG_LENGTH_RELOAD > 4095u ) +#error "Invalid value for reload" +#endif + +#if ( RNG0_CFG_LENGTH_PRESCALER > 10u ) +#error "Invalid value for prescaler" +#endif + +/*! @} */ + +#endif /* __ADI_RNG_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h new file mode 100755 index 00000000000..ef97a3b0a48 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_rtc_config.h @@ -0,0 +1,397 @@ +/*! + ***************************************************************************** + @file: adi_rtc_config.h + @brief: Configuration options for Real Time Clock device driver. + This is specific to the RTC driver and will be included by the driver. + It is not required for the application to include this header file. + @version: $Revision: 33005 $ + @date: $Date: 2015-12-12 10:43:13 -0500 (Sat, 12 Dec 2015) $ + ----------------------------------------------------------------------------- + +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_RTC_CONFIG_H__ +#define ADI_RTC_CONFIG_H__ +#include + +/** @addtogroup RTC_Driver_Config Static Configuration + * @ingroup RTC_Driver + * @{ + */ + +/*! + * The safe write mode insures any pending writes that have not yet synchronized between the faster core clock + * domain and the internal RTC 32kHz clock domain are reconciled before multiple writes to the same RTC register + * are allowed +*/ + +#define ADI_RTC_CFG_ENABLE_SAFE_WRITE 1 + + +/** @addtogroup RTC_Driver_Config_RTC0 RTC0 Static Configuration + * @ingroup RTC_Driver_Config + * @{ + */ + +/* +=================================================================== + ------------------------RTC-0 CONFIGURATION MACRO----------------- +=================================================================== +*/ +/*! Enable the Alarm */ +#define RTC0_CFG_ENABLE_ALARM 0 + +/*! Enable the Alarm interrupt*/ +#define RTC0_CFG_ENABLE_ALARM_INTERRUPT 0 + +/*! Enable the Trim */ +#define RTC0_CFG_ENABLE_TRIM 0 + +/*! Enable the PENDERROR interrupt*/ +#define RTC0_CFG_ENABLE_PENDERROR_INTERRUPT 0 + +/*! Enable the write sync interrupt*/ +#define RTC0_CFG_ENABLE_WSYNC_INTERRUPT 0 + +/*! Enable the pend write interrupt*/ +#define RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT 0 + +/*! Initial the count Value*/ +#define RTC0_CFG_COUNT_VALUE 0 + +/*! Initial the count Value-0*/ +#define RTC0_CFG_COUNT_VALUE_0 0 + +/*! Initial the count Value-1*/ +#define RTC0_CFG_COUNT_VALUE_1 0 + +/*! Alarm-0 Value*/ +#define RTC0_CFG_ALARM_VALUE_0 0 + +/*! Alarm-1 Value*/ +#define RTC0_CFG_ALARM_VALUE_1 0 + +/*! Trim interval*/ +#define RTC0_CFG_TRIM_INTERVAL 0 + +/*! Trim interval with power of 2*/ +#define RTC0_CFG_POW2_TRIM_INTERVAL 0 + +/*! Trim operation to be performed for RTC0*/ +#define RTC0_CFG_TRIM_OPERATION 0 + +/*! Trim Value for RTC-0*/ +#define RTC0_CFG_TRIM_VALUE 0 + +/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 3. + * Enables sampling of Sensor Strobe GPIO inputs around rising edge of Sensor Strobe Channel 3 pulse. + * + * 0 No sampling of input around rising edge. + * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. + * 10 Input sampled at rising edge of Sensor Strobe. + * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. + */ +#define RTC0_SS3_SMPONRE 0 + +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 3. + * Enables sampling of Sensor Strobe GPIO inputs around falling edge of Sensor Strobe Channel 3 pulse. + * + * 0 No sampling of input around rising edge. + * 1 Input sampled one clock cycle before rising edge of Sensor Strobe. + * 10 Input sampled at rising edge of Sensor Strobe. + * 11 Input sampled one clock cycle after rising edge of Sensor Strobe. + */ +#define RTC0_SS3_SMPONFE 0 +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 2. */ +#define RTC0_SS2_SMPONFE 0 +/*! GPIO Sample around Rising Edge of Sensor Strobe Channel 1. */ +#define RTC0_SS1_SMPONRE 0 +/*! GPIO Sample around Falling Edge of Sensor Strobe Channel 1. */ +#define RTC0_SS1_SMPONFE 0 + + +/*! Sensor Strobe's GP Input Sampling Mux + * SS 2 GPIO Pin 1 + * + * GPMUX0/1.SSxGPINySEL 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 + * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] + */ +#define RTC0_SS2_GPIN1SEL 0x4 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ +#define RTC0_SS2_GPIN0SEL 0x3 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ +#define RTC0_SS1_GPIN2SEL 0x2 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ +#define RTC0_SS1_GPIN1SEL 0x1 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ +#define RTC0_SS1_GPIN0SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ +#define RTC0_SS3_GPIN2SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ +#define RTC0_SS3_GPIN1SEL 0x7 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ +#define RTC0_SS3_GPIN0SEL 0x6 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ +#define RTC0_SS2_GPIN2SEL 0x5 + +/*! Differential output option for Sensor Strobe channel 3. + * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out + * for this channel is available in corresponding GPIO. + * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. + */ +#define RTC0_SS3_DIFFOUT 0 +/*! Differential output option for Sensor Strobe channel 1. + * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out + * for this channel is available in corresponding GPIO. + * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. + */ +#define RTC0_SS1_DIFFOUT 0 + + + +/*! @} */ + +/* +=================================================================== + ------------------------RTC-1 CONFIGURATION MACRO----------------- +=================================================================== +*/ + +/** @addtogroup RTC_Driver_Config_RTC1 RTC1 Static Configuration + * @ingroup RTC_Driver_Config + * @{ + */ + + + +/*! Enable the Alarm */ +#define RTC1_CFG_ENABLE_ALARM 0 + +/*! Enable the Alarm interrupt*/ +#define RTC1_CFG_ENABLE_ALARM_INTERRUPT 0 + +/*! Enable the Trim */ +#define RTC1_CFG_ENABLE_TRIM 0 + +/*! Enable the mod-60 Alarm */ +#define RTC1_CFG_ENABLE_MOD60_ALARM 0 + +/*! Enable the mod-60 Alarm period*/ +#define RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD 0 + +/*! Enable the Alarm interrupt*/ +#define RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT 0 + +/*! Enable the ISOINT interrupt*/ +#define RTC1_CFG_ENABLE_ISO_INTERRUPT 0 + +/*! Enable the PENDERROR interrupt*/ +#define RTC1_CFG_ENABLE_PENDERROR_INTERRUPT 0 + +/*! Enable the write sync interrupt*/ +#define RTC1_CFG_ENABLE_WSYNC_INTERRUPT 0 + +/*! Enable the pend write interrupt*/ +#define RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT 0 + +/*! Enable the RTC count interrupt*/ +#define RTC1_CFG_ENABLE_COUNT_INTERRUPT 0 + +/*! Enable the prescaled modulo-1 interrupt*/ +#define RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT 0 + +/*! Enable the Trim interrupt*/ +#define RTC1_CFG_ENABLE_TRIM_INTERRUPT 0 + +/*! Enable the Mod60 roll over interrupt*/ +#define RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT 0 + +/*! Prescale value for the RTC1*/ +#define RTC1_CFG_PRESCALE 0 + +/*! Enable the counter roll over interrupt*/ +#define RTC1_CFG_CNT_ROLLLOVER_INTERRUPT 0 + +/*! Initial the count Value-0*/ +#define RTC1_CFG_COUNT_VALUE_0 0 + +/*! Initial the count Value-1*/ +#define RTC1_CFG_COUNT_VALUE_1 0 + +/*! Alarm Value-0*/ +#define RTC1_CFG_ALARM_VALUE_0 0 + +/*! Alarm Value-1*/ +#define RTC1_CFG_ALARM_VALUE_1 0 + +/*! Alarm Value-2*/ +#define RTC1_CFG_ALARM_VALUE_2 0 + +/*! Trim interval*/ +#define RTC1_CFG_TRIM_INTERVAL 0 + +/*! Trim interval with power of 2*/ +#define RTC1_CFG_POW2_TRIM_INTERVAL 0 + +/*! Trim operation to be performed for RTC1*/ +#define RTC1_CFG_TRIM_OPERATION 0 + +/*! Trim Value for RTC-1*/ +#define RTC1_CFG_TRIM_VALUE 0 + +/*! Enable the input capture channel-0*/ +#define RTC1_CFG_IC0_ENABLE 0 + +/*! Enable the input capture channel-2*/ +#define RTC1_CFG_IC2_ENABLE 0 + +/*! Enable the input capture channel-3*/ +#define RTC1_CFG_IC3_ENABLE 0 + +/*! Enable the input capture channel-4*/ +#define RTC1_CFG_IC4_ENABLE 0 + +/*! Enable the Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_ENABLE 0 +/*! Enable the Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_ENABLE 0 +/*! Enable the Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_ENABLE 0 +/*! Enable the Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_ENABLE 0 + +/*! Enable the interrupt for input capture channel-0*/ +#define RTC1_CFG_IC0_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-2*/ +#define RTC1_CFG_IC2_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-3*/ +#define RTC1_CFG_IC3_INT_ENABLE 0 + +/*! Enable the interrupt for input capture channel-4*/ +#define RTC1_CFG_IC4_INT_ENABLE 0 + +/*! Enable the over write input capture channels*/ +#define RTC1_CFG_IC_OVER_WRITE_ENABLE 0 + +/*! Polarity for input capture channel-0*/ +#define RTC1_CFG_IC0_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-2*/ +#define RTC1_CFG_IC2_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-3*/ +#define RTC1_CFG_IC3_EDGE_POLARITY 0 + +/*! Polarity for input capture channel-4*/ +#define RTC1_CFG_IC4_EDGE_POLARITY 0 + +/*! Enable the interrupt for Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_INT_ENABLE 0 +/*! Enable the interrupt for Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_INT_ENABLE 0 + +/*! Enable the masking for Sensor Strobe channel-1*/ +#define RTC1_CFG_SS1_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-2*/ +#define RTC1_CFG_SS2_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-3*/ +#define RTC1_CFG_SS3_MASK_ENABLE 0 +/*! Enable the masking for Sensor Strobe channel-4*/ +#define RTC1_CFG_SS4_MASK_ENABLE 0 + +/*! Enable the auto-reloading for Sensor Strobe channel-0*/ +#define RTC1_CFG_SS1_AUTO_RELOADING_ENABLE 0 + +/*! Mask for Sensor Strobe channel-0 */ +#define RTC1_CFG_SS1_MASK_VALUE 0 + + +/*! Auto reload value for Sensor Strobe channel-0 */ +#define RTC1_CFG_SS1_AUTO_RELOAD_VALUE 32768/2 + + +/*! Sensor Strobe GP Input Sampling Mux + * SS2 GPIO Pin 1 + * + * GPMUX0/1.SSxGPINySEL 3’b000 3’b001 3’b010 3’b011 3’b100 3’b101 3’b110 3’b111 + * RTCSSxGPIny p0[12] p2[0] p0[9] p0[8] p1[13] p1[2] p2[7] p2[9] + */ +#define RTC1_SS2_GPIN1SEL 0x4 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 0*/ +#define RTC1_SS2_GPIN0SEL 0x3 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 2*/ +#define RTC1_SS1_GPIN2SEL 0x2 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 1*/ +#define RTC1_SS1_GPIN1SEL 0x1 +/*! Sensor Strobe's GP Input Sampling Mux SS 1 GPIO Pin 0*/ +#define RTC1_SS1_GPIN0SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 2*/ +#define RTC1_SS3_GPIN2SEL 0x0 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 1*/ +#define RTC1_SS3_GPIN1SEL 0x7 +/*! Sensor Strobe's GP Input Sampling Mux SS 3 GPIO Pin 0*/ +#define RTC1_SS3_GPIN0SEL 0x6 +/*! Sensor Strobe's GP Input Sampling Mux SS 2 GPIO Pin 2*/ +#define RTC1_SS2_GPIN2SEL 0x5 + +/*! Differential output option for Sensor Strobe channel 3. + * Sensor Strobe channel3 is used as differential signal, actual RTC_SS3 out + * for this channel is available in corresponding GPIO. + * RTC_SS4 of Sensor Strobe channel 4 is used to provided inverted signal of RTC_SS3. + */ +#define RTC1_SS3_DIFFOUT 0 +/*! Differential output option for Sensor Strobe channel 1. + * Sensor Strobe channel 1 is used as differential signal, actual RTC_SS1 out + * for this channel is available in corresponding GPIO. + * RTC_SS1 of Sensor Strobe channel 2 is used to provided inverted signal of RTC_SS1. + */ +#define RTC1_SS1_DIFFOUT 0 + + +/*! @} */ + +/*! @} */ +#endif /* ADI_RTC_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h new file mode 100755 index 00000000000..e2a8ccd572b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h @@ -0,0 +1,592 @@ +/*! + ***************************************************************************** + @file: adi_spi_config.h + @brief: Configuration options for SPI driver. + This is specific to the SPI driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_SPI_CONFIG_H__ +#define ADI_SPI_CONFIG_H__ +#include +/** @addtogroup SPI_Driver_Config Static Configuration + * @ingroup SPI_Driver + * @{ + */ + + +/*! Set this macro to the system clock frequency in hertz*/ +#define ADI_CFG_SYSTEM_CLOCK_HZ (26000000u) + +/************* SPI controller configurations ***************/ + +/* There are three SPI instances SPI0, SPI1 and SPI2 */ +/* Each SPI has its own configuration macros */ + + +/*----------------------------------------------------------*/ +/* -------------------- SPI0 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration + * @ingroup SPI_Driver_Config + * @{ + */ + + /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI0_MASTER_MODE (1u) + + +/*! Set this macro to the SPI0 bit rate in hertz */ +#define ADI_SPI0_CFG_BIT_RATE (2000000u) + +/*! SPI0 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI0_CFG_ENABLE (0u) + +/*! SPI0 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI0_CFG_CLK_PHASE (0u) + + + + + +/*! SPI0 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI0_CFG_CLK_POLARITY (0u) + + +/*! SPI0 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI0_CFG_WIRED_OR (0u) + + +/*! SPI0 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI0_CFG_LSB_MSB (0u) + + +/*! SPI0 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI0_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI0_CFG_TX_UNDERFLOW (0u) + + +/*! SPI0 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI0_CFG_RX_OVERFLOW (0u) + + +/*! SPI0 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI0_CFG_MISO_ENABLE (0u) + + +/*! SPI0 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI0_CFG_LOOPBACK (0u) + +/*! SPI0 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI0_CFG_CONTINUOUS (0u) + +/*! SPI0 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI0_CFG_RX_FLUSH (0u) + + +/*! SPI0 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI0_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI0 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI0_CFG_CSERR_RESET (0u) + + +/*! SPI0 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI0_CFG_CLK_DIV (0u) + + +/*! SPI0 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI0_CFG_HFM (0u) + + +/*! SPI0 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI0_CFG_CS_ERR (0u) + + +/*! SPI0 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI0_CFG_CS_IRQ (0u) + + +/*! @} */ + +/*----------------------------------------------------------*/ +/* -------------------- SPI1 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration + * @ingroup SPI_Driver_Config + * @{ + */ + + /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI1_MASTER_MODE (1u) + +/*! Set this macro to the SPI1 bit rate in hertz */ +#define ADI_SPI1_CFG_BIT_RATE (2000000u) + +/*! SPI1 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI1_CFG_ENABLE (0u) + +/*! SPI1 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI1_CFG_CLK_PHASE (0u) + + + + + +/*! SPI1 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI1_CFG_CLK_POLARITY (0u) + + +/*! SPI1 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI1_CFG_WIRED_OR (0u) + + +/*! SPI1 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI1_CFG_LSB_MSB (0u) + + +/*! SPI1 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI1_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI1_CFG_TX_UNDERFLOW (0u) + + +/*! SPI1 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI1_CFG_RX_OVERFLOW (0u) + + +/*! SPI1 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI1_CFG_MISO_ENABLE (0u) + + +/*! SPI1 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI1_CFG_LOOPBACK (0u) + +/*! SPI1 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI1_CFG_CONTINUOUS (0u) + +/*! SPI1 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI1_CFG_RX_FLUSH (0u) + + +/*! SPI1 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI1_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI1 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI1_CFG_CSERR_RESET (0u) + + +/*! SPI1 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI1_CFG_CLK_DIV (0u) + + +/*! SPI1 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI1_CFG_HFM (0u) + + +/*! SPI1 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI1_CFG_CS_ERR (0u) + + +/*! SPI1 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI1_CFG_CS_IRQ + +/*! @} */ + +/*----------------------------------------------------------*/ +/* -------------------- SPI2 -------------------------------*/ +/*----------------------------------------------------------*/ + +/** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration + * @ingroup SP2_Driver_Config + * @{ + */ + +/*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */ +#define ADI_SPI2_MASTER_MODE (1u) + +/*! Set this macro to the SPI2 bit rate in hertz */ +#define ADI_SPI2_CFG_BIT_RATE (2000000u) + +/*! SPI2 enable\n + SPI configuration register: Bit[0]\n + 1 - Enable SPI\n + 0 - Disable SPI */ +#define ADI_SPI2_CFG_ENABLE (0u) + +/*! SPI2 clock phase mode\n + SPI configuration register: Bit[2]\n + 1 - Serial clock pulses at the beginning of each serial bit transfer.\n + 0 - Serial clock pulses at the end of each serial bit transfer. */ +#define ADI_SPI2_CFG_CLK_PHASE (0u) + + + + + +/*! SPI2 clock polarity\n + SPI configuration register: Bit[3]\n + 1 - Serial clock idles high.\n + 0 - Serial clock idles low. */ +#define ADI_SPI2_CFG_CLK_POLARITY (0u) + + +/*! SPI2 wired OR mode\n + SPI configuration register: Bit[4]\n + 1 - Enables open circuit output enable.\n + 0 - Normal output levels. */ +#define ADI_SPI2_CFG_WIRED_OR (0u) + + +/*! SPI2 LSB/MSB\n + SPI configuration register: Bit[5]\n + 1 - MSB transmitted first.\n + 0 - LSB transmitted first. */ +#define ADI_SPI2_CFG_LSB_MSB (0u) + + +/*! SPI2 transfer initiate\n + SPI configuration register: Bit[6]\n + 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n + 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/ +#define ADI_SPI2_CFG_TRANSFER_INITIATE (0u) + + +/*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n + SPI configuration register: Bit[7]\n + 1 - Tx FIFO sends zeros upon underflow.\n + 0 - Tx FIFO repeats last bit upon underflow. */ +#define ADI_SPI2_CFG_TX_UNDERFLOW (0u) + + +/*! SPI2 Rx FIFO overflows with received data or data is discarded\n + SPI configuration register: Bit[8]\n + 1 - Rx FIFO receives data upon overflow.\n + 0 - Rx FIFO discards received data upon overflow. */ +#define ADI_SPI2_CFG_RX_OVERFLOW (0u) + + +/*! SPI2 slave mode MISO enable\n + SPI configuration register: Bit[9]\n + 1 - MISO operates as normal in slave mode.\n + 0 - MISO is disabled in slave mode. */ +#define ADI_SPI2_CFG_MISO_ENABLE (0u) + + +/*! SPI2 internal loopback enable\n + SPI configuration register: Bit[10]\n + 1 - MISO and MOSI is loopbacked internally.\n + 0 - MISO and MOSI operates normally. */ +#define ADI_SPI2_CFG_LOOPBACK (0u) + +/*! SPI2 transfer and interrupt mode\n + SPI configuration register: Bit[11]\n + 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n + 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/ +#define ADI_SPI2_CFG_CONTINUOUS (0u) + +/*! SPI2 Rx FIFO flush enable\n + SPI configuration register: Bit[12]\n + 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n + 0 - Rx FIFO flush is disabled. */ +#define ADI_SPI2_CFG_RX_FLUSH (0u) + + +/*! SPI2 Tx FIFO flush enable\n + SPI configuration register: Bit[13]\n + 1 - Tx FIFO is flushed.\n + 0 - Tx FIFO flush is disabled. */ +#define ADI_SPI2_CFG_TX_FLUSH (0u) + + +/*! Reset Mode for CSERR. \n + SPI2 configuration register: Bit[14]\n + 0 - To continue from where it stopped. SPI can receive the remaining bits + when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n + 1 - To enable resetting the bit counter and reset if there is a + CS error condition and the Cortex is expected to clear the SPI_EN bit. +*/ +#define ADI_SPI2_CFG_CSERR_RESET (0u) + + +/*! SPI2 clock divide\n + SPI baud rate selection register: Bit[0:5]\n + Value between 0-63 that is used to divide the UCLK to generate + the SPI serial clock. */ +#define ADI_SPI2_CFG_CLK_DIV (0u) + + +/*! SPI2 high frequency mode\n + SPI baud rate selection register: Bit[6]\n + 1 - High frequency mode enabled.\n + 0 - High frequency mode disabled. */ +#define ADI_SPI2_CFG_HFM (0u) + + +/*! SPI2 reset mode for CSERR\n + SPI baud rate selection register: Bit[7]\n + 1 - clear bit counter on CS error.\n + 0 - do not clear bit counter on CS error. */ +#define ADI_SPI2_CFG_CS_ERR (0u) + + +/*! SPI2 CS interrupt\n + SPI baud rate selection register: Bit[8]\n + 1 - In continuous mode, generate interrupt on CS.\n + 0 - In continuous mode, do not generate interrupt on CS. */ +#define ADI_SPI2_CFG_CS_IRQ + +/*! @} */ + +/************** Macro validation *****************************/ + +#if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ + ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \ + ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_ENABLE > 1u ) || \ + ( ADI_SPI1_CFG_ENABLE > 1u ) || \ + ( ADI_SPI2_CFG_ENABLE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \ + ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \ + ( ADI_SPI2_CFG_CLK_PHASE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \ + ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \ + ( ADI_SPI2_CFG_CLK_POLARITY > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \ + ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \ + ( ADI_SPI2_CFG_WIRED_OR > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \ + ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \ + ( ADI_SPI2_CFG_LSB_MSB > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \ + ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \ + ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \ + ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \ + ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \ + ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \ + ( ADI_SPI2_CFG_RX_OVERFLOW > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \ + ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \ + ( ADI_SPI2_CFG_MISO_ENABLE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \ + ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \ + ( ADI_SPI2_CFG_LOOPBACK > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \ + ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \ + ( ADI_SPI2_CFG_CONTINUOUS > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \ + ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \ + ( ADI_SPI2_CFG_RX_FLUSH > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \ + ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \ + ( ADI_SPI2_CFG_TX_FLUSH > 1u ) +#error "Invalid configuration" +#endif + + +/*! @} */ + +#endif /* ADI_SPI_CONFIG_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h new file mode 100755 index 00000000000..db0fdb6636a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_sport_config.h @@ -0,0 +1,355 @@ +/*! **************************************************************************** + * @file adi_sport_config.h + * @brief Configuration options for SPORT driver. + * @details This is specific to the SPORT driver and will be included by the + * driver. It is not required for the application to include this + * header file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_SPORT_CONFIG_H +#define ADI_SPORT_CONFIG_H +#include + +/** @addtogroup SPORT_Driver_Config Static Configuration + * @ingroup SPORT_Driver + * @{ + */ + +/************* SPORT Driver configurations FOR SPORT-0-A ***************/ +/*! + Frame Sync Multiplexer Select.\n + 0 - Disable frame sync multiplexing\n + 1 - Enable frame sync multiplexing. +*/ +#define ADI_CFG_SPORT0A_ENABLE_FSMUXSEL (0u) + +/*! + Clock Multiplexer Select.\n + 0 - Disable serial clock multiplexing\n + 1 - Enable serial clock multiplexing. +*/ +#define ADI_CFG_SPORT0A_ENABLE_CKMUXSEL (1u) + +/*! + Least-Significant Bit First.\n + 0 - MSB first sent/received.\n + 1 - LSB first sent/received. +*/ +#define ADI_CFG_SPORT0A_LSB_FIRST (0u) + + +/*! + Serial Word Length in bits.\n + 1 - 32 - SPORT word length +*/ +#define ADI_CFG_SPORT0A_SERIAL_WLEN (32u) + + +/*! + Internal Clock.\n + 0 - External clock.\n + 1 - Internal clock. +*/ +#define ADI_CFG_SPORT0A_INTERNAL_CLK (1u) + +/*! + Operation Mode\n + 0 - DSP standard.\n + 1 - Timer_enable mode. +*/ +#define ADI_CFG_SPORT0A_OPERATION_MODE (0u) + + +/*! + Clock Rising Edge\n + 0 - Clock falling edge\n + 1 - Clock rising edge. +*/ +#define ADI_CFG_SPORT0A_CLOCK_EDGE (0u) + +/*! + Frame Sync Required\n + 0 - No frame sync required \n + 1 - Frame sync required. +*/ +#define ADI_CFG_SPORT0A_FS_REQUIRED (1u) + +/*! + Internal Frame Sync\n + 0 - External frame sync\n + 1 - Internal frame sync +*/ +#define ADI_CFG_SPORT0A_INTERNAL_FS (0u) + + +/*! + Data-Independent Frame Sync\n + 0 - Data-dependent frame sync\n + 1 - Data-independent frame +*/ +#define ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS (0u) + +/*! + Active-Low Frame Sync\n + 0 - Active high frame sync\n + 1 - Active low frame sync +*/ +#define ADI_CFG_SPORT0A_ACTIVE_LOW_FS (0u) + +/*! + Late Frame Sync\n + 0 - Early frame sync\n + 1 - Late frame sync +*/ +#define ADI_CFG_SPORT0A_LATE_FS (0u) + +/*! + Enable Packing \n + 0 - Disable\n + 1 - 8-bit packing enable\n + 2 - 16-bit packing enable +*/ +#define ADI_CFG_SPORT0A_ENABLE_PACKING (0u) + +/*! + Frame Sync Error Operation + 0 - Flag the Frame Sync error\n + 1 - When frame Sync error occurs, discard the receive data +*/ +#define ADI_CFG_SPORT0A_FS_ERROR_OPERATION (1u) + +/*! + Enabling Gated Clock\n + 0 - Disable Gated Clock\n + 1 - Enable Gated Clock +*/ +#define ADI_CFG_SPORT0A_GATED_CLOCK (0u) + +/*! + Serial Clock divisor.\n + 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial + clock (ACLK) from the processor system clock (PCLK). +*/ +#define ADI_CFG_SPORT0A_CLOCK_DIVISOR (2u) + +/*! + Frame Sync Divisor.\n + 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock + cycles that the half SPORT counts before generating a frame sync pulse. +*/ +#define ADI_CFG_SPORT0A_FS_DIVISOR (0x40u) + + +/*! + CONVT to FS duration.\n + 0 - 128 - Specify the value of the number of clocks which would be programmed + corresponding to the desired time duration from assertion of CONVT + signal to Frame sync signal +*/ +#define ADI_CFG_SPORT0A_CONVT_FS_DURATION (1u) + +/*! + Polarity of the Convt signal.\n + 0 - Active High Polarity\n + 1 - Active low Polarity +*/ +#define ADI_CFG_SPORT0A_CONVT_POLARITY (0u) + +/*! + CONVT signal width.\n + 0 - 15 - Specify the value of the number of serial clocks for which CONVT + signal should be active + +*/ +#define ADI_CFG_SPORT0A_CONVT_WIDTH (1u) + +#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) +#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " +#endif + +/************* SPORT Driver configurations FOR SPORT-0-B ***************/ +/*! + Least-Significant Bit First.\n + 0 - MSB first sent/received.\n + 1 - LSB first sent/received. +*/ +#define ADI_CFG_SPORT0B_LSB_FIRST (0u) + + +/*! + Serial Word Length in bits.\n + 1 - 32 - SPORT word length +*/ +#define ADI_CFG_SPORT0B_SERIAL_WLEN (32u) + + +/*! + Internal Clock.\n + 0 - External clock.\n + 1 - Internal clock. +*/ +#define ADI_CFG_SPORT0B_INTERNAL_CLK (1u) + +/*! + Operation Mode\n + 0 - DSP standard.\n + 1 - Timer_enable mode. +*/ +#define ADI_CFG_SPORT0B_OPERATION_MODE (0u) + + +/*! + Clock Rising Edge\n + 0 - Clock falling edge\n + 1 - Clock rising edge. +*/ +#define ADI_CFG_SPORT0B_CLOCK_EDGE (0u) + +/*! + Frame Sync Required\n + 0 - No frame sync required \n + 1 - Frame sync required. +*/ +#define ADI_CFG_SPORT0B_FS_REQUIRED (1u) + +/*! + Internal Frame Sync\n + 0 - External frame sync\n + 1 - Internal frame sync +*/ +#define ADI_CFG_SPORT0B_INTERNAL_FS (1u) + + +/*! + Data-Independent Frame Sync\n + 0 - Data-dependent frame sync\n + 1 - Data-independent frame +*/ +#define ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS (0u) + +/*! + Active-Low Frame Sync\n + 0 - Active high frame sync\n + 1 - Active low frame sync +*/ +#define ADI_CFG_SPORT0B_ACTIVE_LOW_FS (0u) + +/*! + Late Frame Sync\n + 0 - Early frame sync\n + 1 - Late frame sync +*/ +#define ADI_CFG_SPORT0B_LATE_FS (0u) + +/*! + Enable Packing \n + 0 - Disable\n + 1 - 8-bit packing enable\n + 2 - 16-bit packing enable\n +*/ +#define ADI_CFG_SPORT0B_ENABLE_PACKING (0u) + +/*! + Frame Sync Error Operation\n + 0 - Flag the Frame Sync error\n + 1 - When frame Sync error occurs, discard the receive data +*/ +#define ADI_CFG_SPORT0B_FS_ERROR_OPERATION (1u) + +/*! + Enabling Gated Clock\n + 0 - Disable Gated Clock\n + 1 - Enable Gated Clock +*/ +#define ADI_CFG_SPORT0B_GATED_CLOCK (0u) + +/*! + Serial Clock divisor.\n + 0 - 65535 - Serial Clock Divisor which SPORT device use to calculate the serial + clock (ACLK) from the processor system clock (PCLK). +*/ +#define ADI_CFG_SPORT0B_CLOCK_DIVISOR (2u) + +/*! + Frame Sync Divisor.\n + 0 - 128 - Frame Sync Divisor which select the number of transmit or receive clock + cycles that the half SPORT counts before generating a frame sync pulse. +*/ +#define ADI_CFG_SPORT0B_FS_DIVISOR (0x40u) + + +/*! + CONVT to FS duration.\n + 0 - 128 - Specify the value of the number of clocks which would be programmed + corresponding to the desired time duration from assertion of CONVT + signal to Frame sync signal +*/ +#define ADI_CFG_SPORT0B_CONVT_FS_DURATION (1u) + +/*! + Polarity of the Convt signal.\n + 0 - Active High Polarity\n + 1 - Active low Polarity +*/ +#define ADI_CFG_SPORT0B_CONVT_POLARITY (0u) + +/*! + CONVT signal width.\n + 0-15 - Specify the value of the number of serial clocks for which CONVT + signal should be active + +*/ +#define ADI_CFG_SPORT0B_CONVT_WIDTH (1u) + +#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) +#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " +#endif + +/*! @} */ + +#endif /* ADI_SPORT_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h new file mode 100755 index 00000000000..8d6ee10347f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_tmr_config.h @@ -0,0 +1,902 @@ +/*! ***************************************************************************** + * @file adi_tmr_config.h + * @brief GP and RGB timer device driver configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_CONFIG_H +#define ADI_TMR_CONFIG_H + + +#include + + +/** @addtogroup TMR_Driver_Config Static Configuration + * @ingroup TMR_Driver + * @{ + */ + + +/*! Static configuration allows all 3 GP timers and the RGB timer to be configured + with the parameters in this file by simply calling #adi_tmr_Init. The user can + then call any of the configuration API's to override the static configuration, + or simply call #adi_tmr_Enable to start the timer. Since all of these parameters + must be stored in arrays for abstraction, using static configuration will increase the + data footprint. If the user doesn't call any of the runtime configuration API's, the + linker will throw them out and the code footprint will be reduced significantly. Using + static configuration also reduces cycle count and simplifies the user application. + Static configuration should be used if the timers need to be configured once and do not + need to be changed during the system lifetime. + + 0 - Disable static confiscation support. User must call #adi_tmr_ConfigTimer and other + configuration API's after calling #adi_tmr_Init and prior to calling #adi_tmr_Enable + in order to set up the timer. + + 1 - Enable static configuration support. The timer registers will be set based on the + settings in this file when #adi_tmr_Init is called. +*/ +#define ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT (0u) + + +/************************************************************* + GP Timer 0 Configuration + *************************************************************/ + + /** @addtogroup GPTimer0_Driver_Config GP Timer 0 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR0_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR0_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR0_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR0_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR0_CFG_LOAD_VALUE (0x8F9Cu) + +/*! Timer asynchrounous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR0_CFG_ASYNC_LOAD_VALUE (0x8F9Cu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR0_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR0_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + GP Timer 0 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR0_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR0_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR0_CFG_EVENT_CAPTURE (27u) + +/************************************************************* + GP Timer 0 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This vlaue can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR0_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR0_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR0_CFG_PWM0_MATCH_VALUE (0x0E5Cu) + +/*! @} */ + + +/************************************************************* + GP Timer 1 Configuration + *************************************************************/ + + /** @addtogroup GPTimer1_Driver_Config GP Timer 1 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR1_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR1_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR1_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR1_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR1_CFG_LOAD_VALUE (0x23E7u) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR1_CFG_ASYNC_LOAD_VALUE (0x23E7u) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR1_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR1_CFG_ENABLE_SYNC_BYPASS (0u) + + +/************************************************************* + GP Timer 1 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR1_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR1_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR1_CFG_EVENT_CAPTURE (28u) + +/************************************************************* + GP Timer 1 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR1_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR1_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR1_CFG_PWM0_MATCH_VALUE (0x08F9u) + +/*! @} */ + +/************************************************************* + GP Timer 2 Configuration + *************************************************************/ + + /** @addtogroup GPTimer2_Driver_Config GP Timer 2 Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR2_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR2_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR2_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR2_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR2_CFG_LOAD_VALUE (0x0E5Cu) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing Asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR2_CFG_ASYNC_LOAD_VALUE (0x0E5Cu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR2_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR2_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + GP Timer 2 Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR2_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR2_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR2_CFG_EVENT_CAPTURE (27u) + +/************************************************************* + GP Timer 2 PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR2_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR2_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR2_CFG_PWM0_MATCH_VALUE (0x02DFu) + +/*! @} */ + + +/************************************************************* + RGB Timer Configuration + *************************************************************/ + +/** @addtogroup RGBTimer_Driver_Config RGB Timer Static Configuration + * @ingroup TMR_Driver_Config + * @{ + */ + + +/*! Count up or down. Used to control whether the timer increments (counts up) + or decrements (counts down) the Up/Down counter, it can be set to\n + 0 - Timer is set to count down.\n + 1 - Timer is set to count up. +*/ +#define TMR3_CFG_COUNT_UP (0u) + +/*! Timer mode. Used to control whether the timer runs in periodic or + free running mode, it can be set to\n + 0 - Timer is in free running mode.\n + 1 - Timer is in periodic mode. +*/ +#define TMR3_CFG_MODE (1u) + +/*! Prescale factor. Controls the prescaler division factor + to the timer's selected clock. It can be set to\n + + 0 - source_clock/[1 or 4]\n + 1 - source_clock/16\n + 2 - source_clock/64\n + 3 - source_clock/256 +*/ +#define TMR3_CFG_PRESCALE_FACTOR (0u) + +/*! Timer clock source. Used to select a timer clock from the four + available clock sources, it can be set to\n + 0 - Select PCLK\n + 1 - Select HFOSC\n + 2 - Select LFOSC\n + 3 - Select LFXTAL +*/ +#define TMR3_CFG_CLOCK_SOURCE (0u) + +/*! Timer load value. The Up/Down counter is periodically loaded with this + value if periodic mode is selected. LOAD writes during Up/Down counter timeout events + are delayed until the event has passed. It can be set to any value from 0 to 65535. + +*/ +#define TMR3_CFG_LOAD_VALUE (0x47CEu) + +/*! Timer asynchronous load value. The Up/Down counter is periodically loaded with + this value if periodic mode is selected. Writing asynchronous Load value takes + advantage of having the timer run on PCLK by bypassing clock synchronization + logic otherwise required. It can be set to any value from 0 to 65535. + +*/ +#define TMR3_CFG_ASYNC_LOAD_VALUE (0x47CEu) + +/*! Reload control. This allows the user to select whether the Up/Down counter should be + reset only on a timeout event or also when interrupt is cleared. It can be set to\n + 0 - Up/down counter is only reset on a time out event.\n + 1 - Resets the up/down counter when the interrupt is cleared. +*/ +#define TMR3_CFG_ENABLE_RELOADING (0u) + +/*! Enable or disable Synchronization bypass\n + 0 - Disable Synchronization bypass.\n + 1 - Enable Synchronization bypass. +*/ +#define TMR3_CFG_ENABLE_SYNC_BYPASS (0u) + +/************************************************************* + RGB Timer Event Configuration + *************************************************************/ + +/*! Enable or disable event capture. It can be set to\n + 0 - Disable event capturing.\n + 1 - Enable event capturing. +*/ +#define TMR3_CFG_ENABLE_EVENT_CAPTURE (1u) + +/*! Enable or disable prescale reset\n + 0 - Disable rescale reset.\n + 1 - Enable rescale reset. +*/ +#define TMR3_CFG_ENABLE_PRESCALE_RESET (0u) + +/*! Event to be captured. One of the selected 40 events associated + with a general purpose time can be captured. It can be set to + a value of 0 - 39. Please refer hardware reference manual to know + which events can be captured by a particular GP timer. +*/ +#define TMR3_CFG_EVENT_CAPTURE (28u) + +/************************************************************* + RGB Timer PWM0 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM0_MATCH_MODE (1u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM0_IDLE_STATE (1u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM0_MATCH_VALUE (0x23E7u) + +/************************************************************* + RGB Timer PWM1 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM1_MATCH_MODE (0u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM1_IDLE_STATE (0u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM1_MATCH_VALUE (0u) + +/************************************************************* + RGB Timer PWM2 Configuration + *************************************************************/ + +/*! Timer PWM Enable Match. This will control PWM operation mode of the timer. + Toggle mode provides a 50% duty cycle and match mode provides a configurable + duty cycle by using the match value. This value can be set to\n + 0 - PWM in toggle mode.\n + 1 - PWM in match mode. +*/ +#define TMR3_CFG_ENABLE_PWM2_MATCH_MODE (0u) + + +/*! Timer PWM Idle state. This will control PWM idle state. It can be set to\n + 0 - PWM idles low.\n + 1 - PWM idles high. +*/ +#define TMR3_CFG_PWM2_IDLE_STATE (0u) + + +/*! PWM Match value. The value is used when the PWM is operating in match mode. + The PWM output is asserted when the Up/Down counter is equal to this match value. + PWM output is deasserted again when a timeout event occurs. + If the match value is never reached, or occurs simultaneous to a timeout event, + the PWM output remains idle. It can be any value from 0 to 65535. +*/ +#define TMR3_CFG_PWM2_MATCH_VALUE (0u) + +/*! @} */ + +/************************************************************* + GP Timer 0 Macro Validation +**************************************************************/ + +#if TMR0_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR0_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + GP Timer 1 Macro Validation +**************************************************************/ + +#if TMR1_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR1_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + GP Timer 2 Macro Validation +**************************************************************/ + +#if TMR2_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR2_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/************************************************************* + RGB Timer Macro Validation +**************************************************************/ + +#if TMR3_CFG_COUNT_UP > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PRESCALE_FACTOR > 3u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_CLOCK_SOURCE > 3u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ASYNC_LOAD_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_RELOADING > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_SYNC_BYPASS > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PRESCALE_RESET > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_EVENT_CAPTURE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_EVENT_CAPTURE > 39u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM0_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM0_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM0_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM1_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM1_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM1_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +#if TMR3_CFG_ENABLE_PWM2_MATCH_MODE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM2_IDLE_STATE > 1u +#error "Invalid configuration" +#endif + +#if TMR3_CFG_PWM2_MATCH_VALUE > 0xFFFFu +#error "Invalid configuration" +#endif + +/*! @} */ + + +#endif /* ADI_TMR_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h new file mode 100755 index 00000000000..1cf72a4b91a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_uart_config.h @@ -0,0 +1,496 @@ +/*! + ***************************************************************************** + @file: adi_uart_config.h + @brief: Configuration options for UART driver. + This is specific to the UART driver and will be included by the driver. + It is not required for the application to include this header file. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_UART_CONFIG_H +#define ADI_UART_CONFIG_H + +/** @addtogroup UART_Driver_Config Static Configuration + * @ingroup UART_Driver + * @{ + */ + + +#include + +/************** Common UART Driver configurations ************** */ +/*! + Enable the autobaud detection. \n + Range: 0 to 1. +*/ +#define ADI_UART_CFG_ENABLE_AUTOBAUD 1 + + +/** @addtogroup UART0_Driver_Config UART0 Static Configuration + * @ingroup UART_Driver_Config + * @{ + */ + +/************** UART Driver configurations FOR UART 0 ************** */ +/*! + Word length Select. \n + 0 - 5 Bits word length. \n + 1 - 6 Bits word length. \n + 2 - 7 Bits word length. \n + 3 - 8 Bits word length. +*/ +#define ADI_UART0_CFG_WORD_LENGTH 3 + + +/*! + Stop bit selection. \n + 0 - Send 1 stop bit regardless of the word length. \n + 1 - Send a number of stop bits based on the word length. \n + WORD-LENGTH 5 Bits => 1.5 Stop Bits. \n + WORD-LENGTH (6/7/8) Bits => 2 Stop Bits. +*/ +#define ADI_UART0_CFG_STOP_BIT 1 + + +/*! + Parity Enable. Used to control the parity bit. \n + 0 - Parity will not be transmitted or checked. \n + 1 - Parity will be transmitted and checked. +*/ +#define ADI_UART0_CFG_ENABLE_PARITY 0 + + +/*! + Parity Select. This bit only has meaning if parity is enabled. \n + 0 - Odd parity will be transmitted and checked. \n + 1 - Even parity will be transmitted and checked. +*/ +#define ADI_UART0_CFG_PARITY_SELECTION 0 + + +/*! + Stick Parity. Used to force parity to defined values. \n + 0 - Parity will not be forced. \n + 1 - Set parity based on the following bit settings: \n + EPS = 1 and PEN = 1, parity will be forced to 0. \n + EPS = 0 and PEN = 1, parity will be forced to 1. \n + EPS = 1/0 and PEN = 0, no parity will be transmitted. +*/ +#define ADI_UART0_CFG_ENABLE_STICKY_PARITY 0 + + +/* + Table 21-2: Baud Rate Examples Based on 26 MHz PCLK + Baud Rate OSR COMDIV DIVM DIVN + 9600 3 24 3 1078 + 19200 3 12 3 1078 + 38400 3 8 2 1321 + 57600 3 4 3 1078 + 115200 3 4 1 1563 + 230400 3 2 1 1563 + 460800 3 1 1 1563 + 921,600 2 1 1 1563 + 1,000,000 2 1 1 1280 + 1,500,000 2 1 1 171 + +These are calculated with the UarDivCalculator tool. +*/ + +/*! + Fractional baud rate N divide value. \n + Range: 0 to 2047. +*/ +#define ADI_UART0_CFG_DIVN 1078 + + +/*! + Fractional baud rate M divide value. \n + Range: 1 to 3. +*/ +#define ADI_UART0_CFG_DIVM 3 + + +/*! + Fractional baud rate C divide value. \n + Range: 1 to 65535. +*/ +#define ADI_UART0_CFG_DIVC 24 + + +/*! + Over Sample Rate value. \n + Range: 0 to 3. \n + 0 - Over sample by 4. \n + 1 - Over sample by 8. \n + 2 - Over sample by 16. \n + 3 - Over sample by 32. + +*/ +#define ADI_UART0_CFG_OSR 3 + + +/*! + Enable Internal FIFO. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_FIFO 1 + + +/*! + TRIG Level for UART device. \n + Range: 0 to 3. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. \n + 2 - 8 bytes to trig RX interrupt. \n + 3 - 14 bytes to trig RX interrupt. +*/ +#define ADI_UART0_CFG_TRIG_LEVEL 0 + + +/*! + Hold TX while RX is active. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_HOLD_TX 0 + + +/*! + Disable RX when TX is active. \n + Range: 0 to 1. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. +*/ +#define ADI_UART0_CFG_DISABLE_RX 0 + + +/*! + Configure the SOUT de-assertion earlier than full stop bit(s). \n + Range: 0 to 1. \n + 0 - SOUT_EN de-assert same time as full stop bit(s). \n + 1 - SOUT_EN de-assert half-bit earlier than full stop bit(s). +*/ +#define ADI_UART0_CFG_DEASSERTION 0 + + +/*! + Set the SOUT polarity low. \n + Range: 0 to 1. \n + 0 - Active high. \n + 1 - Active low. +*/ +#define ADI_UART0_CFG_SOUT_POLARITY 0 + +/*! + Enable the RX status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT 1 + + +/*! + Enable the Modem status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT 0 + +/*! @} */ + + +/*************** UART Driver configurations FOR UART 1 **************/ + +/** @addtogroup UART1_Driver_Config UART1 Static Configuration + * @ingroup UART_Driver_Config + * @{ + */ + +/*! + Word length Select. \n + 0 - 5 Bits word length. \n + 1 - 6 Bits word length. \n + 2 - 7 Bits word length. \n + 3 - 8 Bits word length. +*/ +#define ADI_UART1_CFG_WORD_LENGTH 3 + + +/*! + Stop bit selection.\n + 0 - Send 1 stop bit regardless of the word length. \n + 1 - Send a number of stop bits based on the word length. \n + WORD-LENGTH 5 Bits => 1.5 Stop Bits. \n + WORD-LENGTH (6/7/8) Bits => 2 Stop Bits. +*/ +#define ADI_UART1_CFG_STOP_BIT 1 + + +/*! + Parity Enable. Used to control the parity bit. \n + 0 - Parity will not be transmitted or checked. \n + 1 - Parity will be transmitted and checked. +*/ +#define ADI_UART1_CFG_ENABLE_PARITY 0 + + +/*! + Parity Select. This bit only has meaning if parity is enabled. \n + 0 - Odd parity will be transmitted and checked. \n + 1 - Even parity will be transmitted and checked. +*/ +#define ADI_UART1_CFG_PARITY_SELECTION 0 + + +/*! + Stick Parity. Used to force parity to defined values. \n + 0 - Parity will not be forced. \n + 1 - Set parity based on the following bit settings: \n + EPS = 1 and PEN = 1, parity will be forced to 0. \n + EPS = 0 and PEN = 1, parity will be forced to 1. \n + EPS = 1/0 and PEN = 0, no parity will be transmitted. +*/ +#define ADI_UART1_CFG_ENABLE_STICKY_PARITY 0 + + +/* + Table 21-2: Baud Rate Examples Based on 26 MHz PCLK + Baud Rate OSR COMDIV DIVM DIVN + 9600 3 24 3 1078 + 19200 3 12 3 1078 + 38400 3 8 2 1321 + 57600 3 4 3 1078 + 115200 3 4 1 1563 + 230400 3 2 1 1563 + 460800 3 1 1 1563 + 921,600 2 1 1 1563 + 1,000,000 2 1 1 1280 + 1,500,000 2 1 1 171 + +These are calculated with the UarDivCalculator tool. +*/ + +/*! + Fractional baud rate N divide value. \n + Range: 0 to 2047. +*/ +#define ADI_UART1_CFG_DIVN 1563 + + +/*! + Fractional baud rate M divide value. \n + Range: 1 to 3. +*/ +#define ADI_UART1_CFG_DIVM 1 + + +/*! + Fractional baud rate C divide value. \n + Range: 1 to 65535. +*/ +#define ADI_UART1_CFG_DIVC 1 + + +/*! + Over Sample Rate value. \n + Range: 0 to 3. \n + 0 - Over sample by 4. \n + 1 - Over sample by 8. \n + 2 - Over sample by 16. \n + 3 - Over sample by 32. + +*/ +#define ADI_UART1_CFG_OSR 3 + + +/*! + Enable Internal FIFO. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_FIFO 1 + + +/*! + TRIG Level for UART device. \n + Range: 0 to 3. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. \n + 2 - 8 bytes to trig RX interrupt. \n + 3 - 14 bytes to trig RX interrupt. +*/ +#define ADI_UART1_CFG_TRIG_LEVEL 0 + + +/*! + Hold TX while RX is active. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_HOLD_TX 0 + + +/*! + Disable RX when TX is active. \n + Range: 0 to 1. \n + 0 - 1 byte to trig RX interrupt. \n + 1 - 4 bytes to trig RX interrupt. +*/ +#define ADI_UART1_CFG_DISABLE_RX 0 + + +/*! + Configure the SOUT de-assertion earlier than full stop bit(s). \n + Range: 0 to 1. \n + 0 - SOUT_EN de-assert same time as full stop bit(s). \n + 1 - SOUT_EN de-assert half-bit earlier than full stop bit(s). +*/ +#define ADI_UART1_CFG_DEASSERTION 0 + + +/*! + Set the SOUT polarity low. \n + Range: 0 to 1. \n + 0 - Active high. \n + 1 - Active low. +*/ +#define ADI_UART1_CFG_SOUT_POLARITY 0 + +/*! + Enable the RX status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT 1 + + +/*! + Enable the Modem status interrupt. \n + Range: 0 to 1. +*/ +#define ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT 0 +/*! @} */ + +/*! @} */ + + +/*************** UART Driver Debug Checks ************** */ + +/* Check word length */ +#if (((ADI_UART0_CFG_WORD_LENGTH < 0) || (ADI_UART0_CFG_WORD_LENGTH > 3)) || ((ADI_UART1_CFG_WORD_LENGTH < 0) || (ADI_UART1_CFG_WORD_LENGTH > 3))) +#error "Word length needs to be between 0 and 3" +#endif + +/* Check stop bit */ +#if (((ADI_UART0_CFG_STOP_BIT < 0) || (ADI_UART0_CFG_STOP_BIT > 1)) || ((ADI_UART1_CFG_STOP_BIT < 0) || (ADI_UART1_CFG_STOP_BIT > 1))) +#error "Stop bit selection needs to be 0 or 1" +#endif + +/* Check parity enable */ +#if (((ADI_UART0_CFG_ENABLE_PARITY < 0) || (ADI_UART0_CFG_ENABLE_PARITY > 1)) || ((ADI_UART1_CFG_ENABLE_PARITY < 0) || (ADI_UART1_CFG_ENABLE_PARITY > 1))) +#error "Parity Enable bit needs to be 0 or 1" +#endif + +/* Check parity select */ +#if (((ADI_UART0_CFG_PARITY_SELECTION < 0) || (ADI_UART0_CFG_PARITY_SELECTION > 1)) || ((ADI_UART1_CFG_PARITY_SELECTION < 0) || (ADI_UART1_CFG_PARITY_SELECTION > 1))) +#error "Parity bit selection needs to be 0 or 1" +#endif + +/* Check enable sticky parity */ +#if (((ADI_UART0_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART0_CFG_ENABLE_STICKY_PARITY > 1)) || ((ADI_UART1_CFG_ENABLE_STICKY_PARITY < 0) || (ADI_UART1_CFG_ENABLE_STICKY_PARITY > 1))) +#error "Sticky parity enable needs to be 0 or 1" +#endif + +/* Check fractional baudrate N divider value */ +#if (((ADI_UART0_CFG_DIVN < 0) || (ADI_UART0_CFG_DIVN > 2047)) || ((ADI_UART1_CFG_DIVN < 0) || (ADI_UART1_CFG_DIVN > 2047))) +#error "Fractional baudrate N divider value needs to be between 0 and 2047" +#endif + +/* Check fractional baudrate M divider value */ +#if (((ADI_UART0_CFG_DIVM < 1) || (ADI_UART0_CFG_DIVM > 3)) || ((ADI_UART1_CFG_DIVM < 1) || (ADI_UART1_CFG_DIVM > 3))) +#error "Fractional baudrate M divider value needs to be between 1 and 3" +#endif + +/* Check fractional baudrate C divider value */ +#if (((ADI_UART0_CFG_DIVC < 1) || (ADI_UART0_CFG_DIVC > 65535)) || ((ADI_UART1_CFG_DIVC < 1) || (ADI_UART1_CFG_DIVC > 65535))) +#error "Fractional baudrate C divider value needs to be between 1 and 65535" +#endif + +/* Check over same rate value */ +#if (((ADI_UART0_CFG_OSR < 0) || (ADI_UART0_CFG_OSR > 3)) || ((ADI_UART1_CFG_OSR < 0) || (ADI_UART1_CFG_OSR > 3))) +#error "over sample rate value needs to be between 0 and 3" +#endif + +/* Check enable internal FIFO */ +#if (((ADI_UART0_CFG_ENABLE_FIFO < 0) || (ADI_UART0_CFG_ENABLE_FIFO > 1)) || ((ADI_UART1_CFG_ENABLE_FIFO < 0) || (ADI_UART1_CFG_ENABLE_FIFO > 1))) +#error "Enable internal FIFO needs to be 0 or 1" +#endif + +/* Check UART trig level */ +#if (((ADI_UART0_CFG_TRIG_LEVEL < 0) || (ADI_UART0_CFG_TRIG_LEVEL > 3)) || ((ADI_UART1_CFG_TRIG_LEVEL < 0) || (ADI_UART1_CFG_TRIG_LEVEL > 3))) +#error "Trig level for the UART device needs to be 0 or 1" +#endif + +/* Check value for holding tx while rx is active */ +#if (((ADI_UART0_CFG_HOLD_TX < 0) || (ADI_UART0_CFG_HOLD_TX > 1)) || ((ADI_UART1_CFG_HOLD_TX < 0) || (ADI_UART1_CFG_HOLD_TX > 1))) +#error "Value for holding Tx while Rx is active needs to be 0 or 1" +#endif + +/* Check value de-assertion */ +#if (((ADI_UART0_CFG_DEASSERTION < 0) || (ADI_UART0_CFG_DEASSERTION > 1)) || ((ADI_UART1_CFG_DEASSERTION < 0) || (ADI_UART1_CFG_DEASSERTION > 1))) +#error "Value for de-assertion needs to be 0 or 1" +#endif + +/* Check value for SOUT polarity */ +#if (((ADI_UART0_CFG_SOUT_POLARITY < 0) || (ADI_UART0_CFG_SOUT_POLARITY > 1)) || ((ADI_UART1_CFG_SOUT_POLARITY < 0) || (ADI_UART1_CFG_SOUT_POLARITY > 1))) +#error "Value for SOUT polarity needs to be 0 or 1" +#endif + +/* Check value to enable autobaud detection */ +#if ((ADI_UART_CFG_ENABLE_AUTOBAUD < 0) || (ADI_UART_CFG_ENABLE_AUTOBAUD > 1)) +#error "Value for autobaud enable needs to be 0 or 1" +#endif + +/* Check value to enable Rx status interrupt */ +#if (((ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT > 1)) || ((ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT > 1))) +#error "Value to enable Rx status interrupt needs to be 0 or 1" +#endif + +/* Check value to enable modem status interrupt */ +#if (((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1)) || ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT < 0) || (ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT > 1))) +#error "Value to enable modem status interrupt needs to be 0 or 1" +#endif + +#endif /* ADI_UART_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h new file mode 100755 index 00000000000..25e47a78509 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_wdt_config.h @@ -0,0 +1,119 @@ +/*! ***************************************************************************** + * @file adi_wdt_config.h + * @brief WDT device driver configuration + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_WDT_CONFIG_H +#define ADI_WDT_CONFIG_H + + +/** @addtogroup WDT_Driver_Config Static Configuration + * @ingroup WDT_Driver + * @{ + */ + + +/************* WDT Static Configuration ***************/ + +/*! WDT Timer Reload Value\n + Value used to reload the WDT count register after count expires.\n + 0-65535 - WDT reload value (default is 0x0100). +*/ +#define ADI_WDT_LOAD_VALUE (0x1000u) + +/*! WDT Timer Mode\n + Selects WDT operating mode.\n + 0 - WDT operates in free-running mode.\n + 1 - WDT operates in periodic mode (default). +*/ +#define ADI_WDT_CONTROL_TIMER_MODE (1u) + +/*! WDT Clock Prescaler\n + Controls WDT clock prescale.\n + 0 - WDT operates at (source clock)/1.\n + 1 - WDT operates at (source clock)/16.\n + 2 - WDT operates at (source clock)/256 (default).\n +*/ +#define ADI_WDT_CONTROL_CLOCK_PRESCALER (2u) + +/*! WDT Timeout Mode\n + Controls WDT timeout behaviour.\n + 0 - WDT issues RESET on timeout (default).\n + 1 - WDT issues INTERRUPT on timeout. +*/ +#define ADI_WDT_CONTROL_TIMEOUT_MODE (0u) + +/*! WDT Power Mode Disable\n + Controls WDT countdown in hibernate or halted mode.\n + 0 - WDT continues to count down when core is halted or in hibernate.\n + 1 - WDT pauses count down when core is halted or in hibernate (default).\n +*/ +#define ADI_WDT_CONTROL_POWER_MODE (1u) + +/************** Macro Validation *****************************/ + +#if ( ADI_WDT_LOAD_VALUE > 65535u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_TIMER_MODE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_CLOCK_PRESCALER > 2u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_TIMEOUT_MODE > 1u ) +#error "Invalid configuration" +#endif + +#if ( ADI_WDT_CONTROL_POWER_MODE > 1u ) +#error "Invalid configuration" +#endif + +/** + * @} + */ + +#endif /* ADI_WDT_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c new file mode 100755 index 00000000000..4ea2233205c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc.c @@ -0,0 +1,1279 @@ +/*! **************************************************************************** + * @file: adi_crc.c + * @brief: CRC device driver global file. + * @details: This file contain the CRC device driver impelementation. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#include +#include + + +/** @addtogroup CRC_Driver CRC Device Driver + * @{ + +@brief Cyclic Redundancy Check (CRC) peripheral driver +@details + +The CRC peripheral is used to perform the Cyclic Redundancy Check (CRC) of the +block of data that is presented to the peripheral. The peripheral provides a +means to periodically verify the integrity of the system memory and it is based +on a CRC32 engine that computes the signature of 32-bit data presented to the +hardware engine. CRC operations can be core driven or DMA driven depending on +static configuration. + + - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to 0 defines a core driven CRC driver + - #ADI_CRC_CFG_ENABLE_DMA_SUPPORT set to a non 0 value defines a DMA driven + CRC driver + +Core driven CRC operations + +The adi_crc_Compute function executes core driven CRC operations to calculate the +CRC on the buffer input with the CRC parameters set in the driver. In this mode, +data in the submitted buffer is transmitted to the CRC directly by the core. + +Memory DMA driver CRC operations + +The adi_crc_Compute function executes DMA driven CRC operations to calculate the +CRC on the buffer input with the CRC parameters set in the driver. In this mode, +data in the submitted buffer is transmitted to the CRC through DMA transfers. + +The software DMA channel reserved for the CRC driver is defined by a macro, +ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID, which can take a value between 0 and 7. +If this macro is not defined, e.g. in a configuration file, then its value +is defaulted to 7: in this case, DMA channel SIP7 is used by the CRC driver +and DMA_SIP7_Int_Handler becomes the interrupt used by the DMA when a transfer +to the CRC is complete. + +Computing CRC + +The CRC engine performs a 32-bit CRC operation on the incoming data stream. + +Sequence of function calls for Computing CRC :\n + - #adi_crc_Open() to open CRC device and get a valid CRC handle. + - #adi_crc_SetPolynomialVal() to set the polynomial value to be used in CRC operations. + - #adi_crc_SetBitMirroring() to enable/disable bit mirroring + - #adi_crc_SetByteMirroring() to enable/disable byte mirroring + - #adi_crc_SetLSBFirst() to indicate if data is Big or Little Endian. + - #adi_crc_IsCrcInProgress() to poll the current status of CRC operation or + wait for callback event. + - #adi_crc_GetFinalCrcVal() to get the CRC value of the data stream if its + CRC value is unknown. (Note that #adi_crc_GetFinalCrcVal resets the CRC + seed to the #ADI_CFG_CRC_SEED_VALUE default value.) + + Note that using statically configured parameters such as + #ADI_CFG_CRC_ENABLE_BYTE_MIRRORING, #ADI_CFG_CRC_ENABLE_BIT_MIRRORING, + #ADI_CFG_CRC_POLYNOMIAL and #ADI_CFG_CRC_SEED_VALUE, functions + #adi_crc_SetBitMirroring, #adi_crc_SetByteMirroring, #adi_crc_SetPolynomialVal + and #adi_crc_SetBitMirroring don't need to be called explicitly in your + application: the parameters will be assigned when opening the driver. + + @note - The application must include drivers/crc/adi_crc.h to use this driver. + @note - This driver also requires the DMA driver. The application must include + the DMA driver sources to avoid link errors. + */ + +/*! \cond PRIVATE */ +/*============= I N C L U D E S =============*/ + +#include +#include +#include "adi_crc_def.h" + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Casts from pointer to uint32_t needed to determine pointer alignment. +*/ +#pragma diag_suppress=Pm123,Pm088,Pm152,Pm140 +#endif /* __ICCARM__ */ + +/*============== D E F I N E S ===============*/ + +/* CRC Peripheral specific information */ +#define ADI_CRC_NUM_DEVICES (1u) + +/*! \endcond */ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0) + +/** + * If a DMA channel has not been configured for the CRC driver, +* then a default software DMA channel is assigned: SIP7. + */ + +#ifndef ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID +#define ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID 7 +#pragma message("ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID implicitly defaulted to 7!") +#endif + +/** + * The following macros define + * - the Software DMA channel identifier to be used in CRC DMA driven operations + * - the ISR used by the CRC, which depends on the Software DMA channel + * selected to drive the CRC in DMA driven CRC operations. + * - the interrupt identifier mapped to the software DMA channel; selected for + * the CRC operations + */ +#if (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 0) +#define ADI_CFG_CRC_DMA_CHANNEL SIP0_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP0_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH16_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 1) +#define ADI_CFG_CRC_DMA_CHANNEL SIP1_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP1_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH17_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 2) +#define ADI_CFG_CRC_DMA_CHANNEL SIP2_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP2_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH18_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 3) +#define ADI_CFG_CRC_DMA_CHANNEL SIP3_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP3_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH19_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 4) +#define ADI_CFG_CRC_DMA_CHANNEL SIP4_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP4_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH20_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 5) +#define ADI_CFG_CRC_DMA_CHANNEL SIP5_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP5_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH21_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 6) +#define ADI_CFG_CRC_DMA_CHANNEL SIP6_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP6_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH22_DONE_IRQn +#elif (ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID == 7) +#define ADI_CFG_CRC_DMA_CHANNEL SIP7_CHANn +#define ADI_DMA_CRC_ISR DMA_SIP7_Int_Handler +#define ADI_CRC_IRQ_ID DMA0_CH23_DONE_IRQn +#else +#error "Invalid Software DMA channel identifier ADI_CFG_CRC_SOFTWARE_DMA_CHANNEL_ID: it must be between 0 and 7" +#endif + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/*! \cond PRIVATE */ + +/** Check the validity of a CRC device identifier */ +#define ADI_CRC_VALID_DEVICE_ID(DEVNUM) ((DEVNUM)<(ADI_CRC_NUM_DEVICES)) + +/** Check that a CRC driver is in idle state */ +#define ADI_CRC_DEVICE_IS_IDLE(DEV) (((DEV)->eCrcOpStatus == ADI_CRC_OP_IDLE) ? true : false) + +/*============== D A T A ===============*/ + +/** + * Information for managing all the CRC devices available + */ +static ADI_CRC_INFO crc_device_info[ADI_CRC_NUM_DEVICES] = +{ + { pADI_CRC0, NULL } /* CRC 0 */ +}; + +/*============== M O R E D E F I N E S ===============*/ + +/** Check the validity of a CRC handle for debug mode */ +#define ADI_CRC_INVALID_HANDLE(h) ((NULL == (h)) || (crc_device_info[0].hDevice != (h))) + +/** Condition used to indicate if a CRC driver is already in use */ +#define ADI_CRC_DEVICE_IN_USE(DEVNUM) ((NULL) != crc_device_info[(DEVNUM)].hDevice) + +#ifdef ADI_DEBUG +#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_INVALID_HANDLE(HDL)) ? (NULL) : ((ADI_CRC_DEVICE*) (HDL))) +#else +#define HDL_TO_DEVICE_PTR(HDL) ((ADI_CRC_DEVICE*) (HDL)) +#endif + +/*============= C O D E =============*/ + +#if (ADI_CRC_NUM_DEVICES!=1u) +#error "!!! Current CRC driver implementation can deal with a unique CRC instance !!!" +#endif + +/*============= L O C A L F U N C T I O N S =============*/ + +/* Prototypes for static functions (required by MISRA-C:2004 Rule 8.1) */ + +static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice); + +static void crc_ResetRegisters (ADI_CRC_DEVICE *pDevice); + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + +/* Functions specific to core driven CRC operations */ + +static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation (ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits); + +#else + +/* Functions specific to DMA driven CRC operations */ + +static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation(ADI_CRC_DEVICE *pDevice, void *pCrcBuf, uint32_t NumBytes, uint32_t NumBits); +static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits); +static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg); +void ADI_DMA_CRC_ISR(void); + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + +/** + * @brief return a pointer to the CRC device information mapped to the CRC + * device identified by a handle + * + * @param [in] hDevice CRC device handle + * + * @return pointer to CRC device information identified by hDevice + * (NULL if the CRC device handle is invalid) + */ +static ADI_CRC_INFO *crc_DeviceInfo(ADI_CRC_HANDLE hDevice) +{ + ADI_CRC_INFO *pCrcInfo = (ADI_CRC_INVALID_HANDLE(hDevice)) + ? NULL + : (&(crc_device_info[0])); + return pCrcInfo; +} + + +/** + * @brief Reset CRC registers to default values + * + * @details Reset CRC registers to default values as defined in configuration. + * + * @param [in] pDevice Pointer to CRC device + * + * @return None + */ +static void crc_ResetRegisters(ADI_CRC_DEVICE *pDevice) +{ + /* Cast the values to be assigned to the targetted types */ + const uint32_t byte_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BYTE_MIRRORING; + const uint32_t byte_mirroring_pos = (uint32_t) BITP_CRC_CTL_BYTMIRR; + const uint32_t bit_mirroring_val = (uint32_t) ADI_CFG_CRC_ENABLE_BIT_MIRRORING; + const uint32_t bit_mirroring_pos = (uint32_t) BITP_CRC_CTL_BITMIRR; + const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE; + const uint32_t polynomial = (uint32_t) ADI_CFG_CRC_POLYNOMIAL; + + /* Set byte mirroring and bit mirroring in CTL register as configured */ + pDevice->pReg->CTL = ( (byte_mirroring_val << byte_mirroring_pos) + | (bit_mirroring_val << bit_mirroring_pos) + ); + pDevice->pReg->RESULT = seed_value; + pDevice->pReg->POLY = polynomial; +} + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + +/* + * @brief Starts core driven CRC operation. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pCrcBuf Address of data buffer. + * @param [in] NumBytes Number of bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - ADI_CRC_SUCCESS: Successfully set expected CRC result. + */ +static ADI_CRC_RESULT crc_ExecuteCoreDrivenOperation( + ADI_CRC_DEVICE *pDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + uint8_t *pData = (uint8_t *)pCrcBuf; /* initialize the pointer to data to the start of the data buffer */ + uint32_t lsbFirst = pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST; + + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /*! enable CRC peripheral */ + + if (((uint32_t)pData & 0x3u) != 0u) /* If the buffer is not 4-byte aligned */ + { + /* feed the CRC byte per byte as long as there are data in the input buffer AND + * the data left in the buffer are not 4-byte aligned */ + while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u)) + { + pDevice->pReg->IPBYTE = *pData; /* feed the CRC with the first byte in the buffer */ + pData++; /* get the next byte to feed into CRC */ + NumBytes--; /* decrease the number of bytes to be processed */ + } + } + + /* data left in the input buffer are now 4-byte aligned */ + + while (NumBytes >= 4u) /* if the number of bytes left is greater than 4 bytes */ + { /* feed CRC peripheral with 4-byte data */ + uint32_t nData; /* 32-bit variable to be used to feed the CRC peripheral */ + + /* + * Here we assume memory is little endian. We need change the following + * code if we produce a Cortex-M processor with big endian memory. + */ + if (lsbFirst != 0u) + { + nData = pData[3]; + nData = (nData << 8) | pData[2]; + nData = (nData << 8) | pData[1]; + nData = (nData << 8) | pData[0]; + } + else + { + nData = pData[0]; + nData = (nData << 8) | pData[1]; + nData = (nData << 8) | pData[2]; + nData = (nData << 8) | pData[3]; + } + pDevice->pReg->IPDATA = nData; /* feed the CRC peripheral with 32-bit data input */ + pData += 4; /* move the data pointer in the data buffer */ + NumBytes -= 4u; /* decrease the number of data to be processed */ + } + + while (NumBytes > 0u) /* if the number of data left in the input buffer is smaller than 4 */ + { + pDevice->pReg->IPBYTE = *pData; /* feed the CRC peripheral with the remaining bytes */ + pData++; /* move the pointer to the next byte in input data buffer */ + NumBytes--; /* decrease the number of data to be fed into the CRC peripheral */ + } + + if (NumBits > 0u) /* if the last byte is a partial byte containing less than 8 bits */ + { + pDevice->pReg->IPBITS[NumBits] = *pData;/* feed the CRC peripheral with the remaining bits (use IPBITS[N] to feed N bits) */ + } + + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); /* All the data have been fed into the CRC peripheral : disable it */ + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC back in idle state */ + return result; +} + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/** + * @brief Send a Memory DMA request to the CRC, which triggers a DMA driven + * CRC operation. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pCrcBuf Address of data buffer. + * @param [in] NumBytes Number of whole bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set expected CRC result. + * - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC + */ +static ADI_CRC_RESULT crc_ExecuteDmaDrivenOperation( + ADI_CRC_DEVICE *pDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + uint8_t *pData = (uint8_t *)pCrcBuf; + bool bUseDma = false; /* assume core driven CRC by default */ + +#ifdef ADI_DEBUG + if (!ADI_CRC_VALID_DMA_CHANNEL(ADI_CFG_CRC_DMA_CHANNEL)) + { + /* Report error as Memory DMA not open */ + result = ADI_CRC_INVALID_DMA_CHANNEL; + } + else +#endif /* ADI_DEBUG */ + { + /* If LSBFIRST, it's easy. */ + if ((pDevice->pReg->CTL & BITM_CRC_CTL_LSBFIRST) != 0u) + { + /* If the buffer is not 4-byte aligned */ + if (((uint32_t)pData & 0x3u) != 0u) + { + /* process the first bytes until a 4-byte aligned data location is reached */ + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /* enable CRC */ + while ((NumBytes > 0u) && (((uint32_t)pData & 0x3u) != 0u)) + { + pDevice->pReg->IPBYTE = *pData; /* feed byte into CRC */ + pData++; /* get to the next byte */ + NumBytes--; /* decrease the number of bytes still to be processed */ + } + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); /* disable CRC */ + } + + /* 4-byte aligned data transfer */ + if (NumBytes >= 4u) + { + /* there are enough data for kicking off a DMA driven CRC operation */ + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + const uint32_t numData = NumBytes / 4u; /* number of 4-byte data to be transferred */ + const uint32_t src = (uint32_t) pData; /* DMA source address */ + const uint32_t dst = (uint32_t) &pDevice->pReg->IPDATA; /* destination is CRC IPDATA 32-bit register */ + const uint32_t numTransData = ( (numData > DMA_TRANSFER_LIMIT) + ? DMA_TRANSFER_LIMIT + : numData + ); + const uint32_t numTransBytes = (numTransData << 2u); + const uint32_t lastDataPos = (numTransBytes - 4u); /* position of last 32-bit data to be transferred in current DMA request */ + + pDevice->pReg->CTL |= ((uint32_t) BITM_CRC_CTL_EN); /* enable CRC (leave other bits unmodified) */ + + pADI_DMA0->EN_SET = channelBit; /* Enable the channel */ + pADI_DMA0->ALT_CLR = channelBit; /* Set the primary as the current DMA descriptor */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* Ensure decrement for source is cleared */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* Ensure decrement for destination is cleared */ + + pPrimaryCCD[channelId].DMADSTEND = dst; /* destination is CRC IPDATA 32-bit register */ + pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos; /* source end address */ + + pPrimaryCCD[channelId].DMACDC = + ( (((uint32_t) ADI_DMA_INCR_NONE) << ((uint32_t) DMA_BITP_CTL_DST_INC)) /* destination address not incremented */ + | (((uint32_t) ADI_DMA_INCR_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_INC)) /* source address incremented by 4 bytes */ + | (((uint32_t) ADI_DMA_WIDTH_4_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 4-byte */ + | ((numTransData - 1u) << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */ + | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL) /* DMA Auto Request transmission */ + ); + pDevice->pRemainingData = (void*)(src + numTransBytes); /* remaining data start address */ + pDevice->RemainingBytes = NumBytes - numTransBytes; /* remaining bytes that cannot be processed in this DMA batch */ + pDevice->RemainingBits = NumBits; /* remaining bits if last byte is a partial byte */ + bUseDma = true; /* there are enough data to run 4-byte DMA transfers to CRC */ + } + } + /* + * If ! LSBFIRST, we need the DMA controller support byte swap for fixed destination address. + * But we don't have such luck, although it supports byte swap for fixed source address. + * So we have to set DMA size to one byte, which is slower. + * + * Another option is using mirroring feature of CRC unit, which would be more complicated. + */ + else + { + if (NumBytes > 0u) + { + /** + * There are enough data for kicking off a DMA driven CRC operation. + * DMA transfers are limited to 1024 bytes : if the buffer is larger + * than 1024 then generate repeated DMA request through the CRC DMA + * interrupt handler, i.e. the interrupt handler used by the software + * DMA channel driving the CRC operations. + */ + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + const uint32_t src = (uint32_t) pData; /* DMA source address */ + const uint32_t dst = (uint32_t) &pDevice->pReg->IPBYTE; /* destination is CRC IPBYTE 8-bit register */ + const uint32_t numTransData = ( (NumBytes > DMA_TRANSFER_LIMIT) + ? DMA_TRANSFER_LIMIT + : NumBytes + ); + const uint32_t lastDataPos = (numTransData - 1u); /* position of last data to be transferred in buffer */ + + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); /* enable CRC (leave other bits unmodified) */ + + pADI_DMA0->EN_SET = channelBit; /* Enable the channel */ + pADI_DMA0->ALT_CLR = channelBit; /* Set the primary as the current DMA descriptor */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* Ensure decrement for source is cleared */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* Ensure decrement for destination is cleared */ + + pPrimaryCCD[channelId].DMADSTEND = dst; /* destination is CRC IPBYTE 8-bit register */ + pPrimaryCCD[channelId].DMASRCEND = src + lastDataPos; /* source end address */ + pPrimaryCCD[channelId].DMACDC = + ( (((uint32_t) ADI_DMA_INCR_NONE) << ((uint32_t) DMA_BITP_CTL_DST_INC)) /* destination address not incremented */ + | (((uint32_t) ADI_DMA_INCR_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_INC)) /* source address incremented by 1 byte */ + | (((uint32_t) ADI_DMA_WIDTH_1_BYTE) << ((uint32_t) DMA_BITP_CTL_SRC_SIZE)) /* source data size is 1-byte */ + | ((numTransData - 1u) << ((uint32_t) DMA_BITP_CTL_N_MINUS_1))/* number of DMA transfers (minus 1) */ + | (DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ << DMA_BITP_CTL_CYCLE_CTL) /* DMA Auto Request transmission */ + ); + pDevice->pRemainingData = (void*) (src + numTransData); /* remaining data start address */ + pDevice->RemainingBytes = NumBytes - numTransData; /* remaining bytes */ + pDevice->RemainingBits = NumBits; /* remaining bits if last byte is a partial byte */ + bUseDma = true; /* there are enough data to run 4-byte DMA transfers to CRC */ + } + } + + /* if we are in a position to use the DMA to transfer data to the CRC */ + if (bUseDma== true) + { + const uint32_t channelId = (uint32_t) ADI_CFG_CRC_DMA_CHANNEL; + const uint32_t channelBit = 1ul << channelId; /* get a value with the bit set at position identified by channelId */ + pADI_DMA0->SWREQ = channelBit; /* Issue a software DMA request */ + } + else + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_EN); + crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits); + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_EN); + if(pDevice->pfCallback != NULL) + { + pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, pData); + } + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC calculation completed */ + } + } + return result; +} + +/** + * @brief Completes a DMA driven CRC operation by dealing with remaining + * data, usually when the number of bytes left is smaller than 4. + * + * @param [in] pDevice Pointer to CRC device + * @param [in] pData Address of data buffer. + * @param [in] NumBytes Number of whole bytes in data buffer. + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + */ +static void crc_CalculateCrcForRemaining(ADI_CRC_DEVICE *pDevice, uint8_t *pData, uint32_t NumBytes, uint32_t NumBits) +{ + /* process the remaining bytes */ + while (NumBytes > 0u) + { + pDevice->pReg->IPBYTE = *pData; + pData++; + NumBytes--; + } + + /* process the remaining bits in the last byte if the number of bits is smaller than 8 */ + if (NumBits > 0u) + { + pDevice->pReg->IPBITS[NumBits] = *pData; + } +} + +/** + * @brief Callback function used by the DMA when a DMA error occurs + * + * @details Callback function used by the DMA when a DMA error must be reported + * to the CRC driver because it affects the DMA channel driving the CRC. + */ +static void CRC_Callback_For_DMA_Err_Int_Handler(void *pcbparam, uint32_t nEvent, void *pArg) +{ + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(pcbparam); + + if (NULL != pDevice) + { + /* DMA error detected */ + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* mark the CRC peripheral as IDLE */ + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_EN)); /* disable CRC peripheral */ + } +} + +/** + * @brief interrupt handler used by the software DMA channel driving the CRC + * + * @details interrupt handler used by the software DMA channel driving the CRC + * ADI_DMA_CRC_ISR is a macro with the final interrupt handler name + * being DMA_SIP0_Int_Handler, ..., DMA_SIP7_Int_Handler, depending + * on the software DMA channel driving the CRC. + */ +void ADI_DMA_CRC_ISR(void) +{ + ISR_PROLOG(); + + if (ADI_CRC_DEVICE_IN_USE(0)) + { + ADI_CRC_DEVICE * pDevice = HDL_TO_DEVICE_PTR(crc_device_info[0].hDevice); + if (NULL != pDevice) + { + uint8_t *pData = (uint8_t *)(pDevice->pRemainingData); + uint32_t NumBytes = pDevice->RemainingBytes; + uint32_t NumBits = pDevice->RemainingBits; + bool finishing = (NumBytes < 4u); + + if (!finishing) + { + /* there's enough data left for another DMA transfer */ + ADI_CRC_RESULT result = pDevice->pfSubmitBuffer(pDevice, pData, NumBytes, NumBits); + if (ADI_CRC_SUCCESS != result) + { + /* buffer submission failed: complete the task through core driven operations */ + finishing = true; + } + } + + if (finishing) + { + /* There are a very few bytes/bits left to be processed or + * a DMA transfer request could not be sent */ + crc_CalculateCrcForRemaining(pDevice, pData, NumBytes, NumBits); + + /* if a callback function is registered with the interrupt handler + * associated with the software DMA channel driving the CRC */ + if(pDevice->pfCallback != NULL) + { + pDevice->pfCallback(pDevice->pCBParam, (uint32_t) ADI_CRC_EVENT_BUFFER_PROCESSED, NULL); + } + pDevice->eCrcOpStatus = ADI_CRC_OP_IDLE; /* CRC back in idle state */ + + } + } + } + +#if defined(ADI_CYCLECOUNT_CRC_ISR_ENABLED) && (ADI_CYCLECOUNT_CRC_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_CRC); +#endif + + ISR_EPILOG(); +} + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/*! \endcond */ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Opens a CRC device instance. + * + * @param [in] DeviceNum Number identifying the CRC Device to open. + * @param [in] pMemory Pointer to a #ADI_CRC_MEMORY_SIZE. + * sized buffer to manage the device instance. + * @param [in] MemorySize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where CRC device handle to be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully opened a CRC device. + * - #ADI_CRC_BAD_DEVICE_NUMBER [D]: Supplied CRC Device ID is invalid. + * - #ADI_CRC_IN_USE [D]: Supplied CRC Device ID is already in use. + * - #ADI_CRC_INSUFFICIENT_MEMORY [D]: Supplied memory is not sufficient to handle a CRC device instance. + * - #ADI_CRC_FAILURE [D]: callback registration failed for CRC function used by DMA Error Interrupt Handler. + * + * @note For the device memory should be of size #ADI_CRC_MEMORY_SIZE. + * + */ +ADI_CRC_RESULT adi_crc_Open( + uint32_t DeviceNum, + void *pMemory, + uint32_t MemorySize, + ADI_CRC_HANDLE *phDevice) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = (ADI_CRC_DEVICE*) pMemory;/* memory block to be used to manage a CRC driver instance */ + +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (!ADI_CRC_VALID_DEVICE_ID(DeviceNum)) /* IF (This is not a valid CRC device number) */ + { + result = ADI_CRC_BAD_DEVICE_NUMBER; /* Report failure as bad device number */ + } + else if (ADI_CRC_DEVICE_IN_USE(DeviceNum)) /* IF (The device is in use) */ + { + result = ADI_CRC_IN_USE; /* return CRC Device in use error */ + } + else if ( (MemorySize < ADI_CRC_MEMORY_SIZE) /* IF (Supplied memory size is insufficient) */ + || (ADI_CRC_MEMORY_SIZE < sizeof(ADI_CRC_DEVICE)) + ) + { + result = ADI_CRC_INSUFFICIENT_MEMORY; /* Report failure as insufficient memory */ + } + else +#endif /* ADI_DEBUG */ + { + /* check that ADI_CRC_MEMORY_SIZE is accurately defined */ + assert(ADI_CRC_MEMORY_SIZE == sizeof(ADI_CRC_DEVICE)); + + memset(pMemory, 0, MemorySize); /* Clear the given memory */ + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); /* Entering critical region, disable interrupts */ + + /* Save the supplied device memory address */ + crc_device_info[DeviceNum].hDevice = (ADI_CRC_HANDLE)pDevice; + pDevice->pReg = crc_device_info[DeviceNum].pReg; + + ADI_EXIT_CRITICAL_REGION(); /* Re-enable interrupts */ + + crc_ResetRegisters(pDevice); /* Reset CRC registers */ + *phDevice = crc_device_info[DeviceNum].hDevice; /* Pass a valid handle to this CRC device */ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + + pDevice->pfSubmitBuffer = &crc_ExecuteCoreDrivenOperation; + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + pDevice->pfSubmitBuffer = &crc_ExecuteDmaDrivenOperation; + adi_dma_Init(); + + /* Register CRC DMA callback */ +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice)) + { + result = ADI_CRC_FAILURE; + } +#else + adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,CRC_Callback_For_DMA_Err_Int_Handler,pDevice); +#endif + NVIC_EnableIRQ(ADI_CRC_IRQ_ID); /* Enable the interrupt for the DMA channel used by CRC */ +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + } + return result; +} + +/** + * @brief Closes CRC device instance opened for use. + * + * @param [in] hDevice Handle to CRC Device instance to close. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully closed CRC device. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FAILURE [D]: callback un-registration failed for CRC function used by DMA Error Interrupt Handler. + */ +ADI_CRC_RESULT adi_crc_Close(ADI_CRC_HANDLE const hDevice) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_INFO *pCrcInfo = crc_DeviceInfo(hDevice); /* get CRC info pointer from CRC handle */ +#ifdef ADI_DEBUG + if (NULL == pCrcInfo) + { + result = ADI_CRC_BAD_HANDLE; /* invalid CRC handle being used */ + } + else +#endif + { +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT != 0) + NVIC_DisableIRQ(ADI_CRC_IRQ_ID); /* Disable the interrupt for the DMA channel used by CRC. */ + /* Register CRC DMA callback */ +#ifdef ADI_DEBUG /* IF (Debug information enabled) */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL)) + { + result = ADI_CRC_FAILURE; + } +#else + adi_dma_RegisterCallback(ADI_CFG_CRC_DMA_CHANNEL,NULL,NULL); +#endif +#endif + pCrcInfo->hDevice = NULL; /* Mark CRC driver as closed */ + } + return result; +} +/*! + * @brief Set the bit mirroring. This function should be called only when device is idle, + * i.e. when no data are being processd by the CRC. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable bit mirroring. + * true : To Enable bit mirroring. + * false : To Disable bit mirroring. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D] :Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * @sa adi_crc_SetByteMirroring(). + * @sa adi_crc_SetWordSwap(). + */ +ADI_CRC_RESULT adi_crc_SetBitMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* Function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_BITMIRR); /* enable bit mirroring */ + } + else + { + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BITMIRR)); /* disable bit mirroring */ + } + return result; +} +/*! + * @brief Set the byte mirroring. This function should be called only when device is disabled. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable byte mirroring. + * true : To Enable byte mirroring. + * false : To Disable byte mirroring. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_EnableBitMirroring(). + * @sa adi_crc_EnableWordSwap(). + */ +ADI_CRC_RESULT adi_crc_SetByteMirroring(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* Function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_BYTMIRR); /* enable byte mirroring */ + } + else + { + pDevice->pReg->CTL &= (uint32_t)(~(BITM_CRC_CTL_BYTMIRR)); /* disable byte mirroring */ + } + return result; +} + +/*! + * @brief Enable the LSB first. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag which indicate whether LSB first OR MSB first for CRC calculation. + * true : For LSB First CRC calculation + * false : For MSB First CRC calculation + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_EnableBitmirroring(). + * @sa adi_crc_EnableWordSwap(). + */ + +ADI_CRC_RESULT adi_crc_SetLSBFirst(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); /* get CRC device pointer from CRC handle */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= (BITM_CRC_CTL_LSBFIRST); /* enable LSB first (MSB first disable) */ + } + else + { + pDevice->pReg->CTL &= ~(BITM_CRC_CTL_LSBFIRST); /* disable LSB first (MSB first enable) */ + } + return result; +} +/*! + * @brief To enable/disable the word Swap. This function should be called only when device is disabled. + * + * @param[in] hDevice Device handle obtained from adi_crc_Open(). + * @param[in] bEnable Boolean flag to enable/disable word swap. + * true : To Enable word swap. + * false : To Disable word swap. + * + * @return Status + * - #ADI_CRC_SUCCESS: Call completed successfully. + * - #ADI_CRC_BAD_HANDLE [D]: Invalid device handle parameter. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: CRC is executing a request, its parameters cannot be altered. + * + * + * @sa adi_crc_SetBitMirroring(). + * @sa adi_crc_SetByteMirroring(). + */ +ADI_CRC_RESULT adi_crc_EnableWordSwap(ADI_CRC_HANDLE const hDevice, const bool bEnable) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif + if(bEnable == true) + { + pDevice->pReg->CTL |= BITM_CRC_CTL_W16SWP; /* enable word swap */ + } + else + { + pDevice->pReg->CTL &= ~BITM_CRC_CTL_W16SWP; /* disable word swap */ + } + + return result; +} +/** + * @brief Sets the initial seed value for the CRC operation that is about to take place. + * + * @param [in] hDevice Handle to CRC device instance to work on. + * @param [in] CrcSeedVal Initial seed value for the CRC operation that is about to take place. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set CRC seed value. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_PERMITTED [D] : Function not permitted when CRC operation is in progress. + * + */ +ADI_CRC_RESULT adi_crc_SetCrcSeedVal( + ADI_CRC_HANDLE const hDevice, + uint32_t CrcSeedVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->pReg->RESULT = CrcSeedVal; /* Load the CRC seed value */ + } + return result; +} + +/** + * @brief Sets the 32-bit polynomial for CRC operations. + * + * @param [in] hDevice Handle to CRC device instance to work on. + * @param [in] PolynomialVal 32-bit CRC polynomial to use for CRC operation. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set polynomial value. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress. + * + */ +ADI_CRC_RESULT adi_crc_SetPolynomialVal( + ADI_CRC_HANDLE const hDevice, + uint32_t PolynomialVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->pReg->POLY = PolynomialVal; /* Load Polynomial value */ + } + return result; +} + +/** + * @brief Submits data buffer for CRC computation + * + * @details This API can be used to submit data buffer for CRC computation. + * If NumBits is in [0..7] then the number of bytes to be processed + * is NumBytes plus one partial byte containing NumBits bits. + * If DMA mode of operation is selected, buffer is processed using + * the specified DMA channel. + * + * @param [in] hDevice Handle of CRC device + * @param [in] pCrcBuf Address of CRC data buffer + * @param [in] NumBytes Number of whole bytes in CRC data buffer + * @param [in] NumBits Number of bits, 0 to 7, in the last partial byte + * in CRC data buffer + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully submitted data buffer. + * - #ADI_CRC_INVALID_PARAMETER [D]: one of the parameter used is invalid. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + * - #ADI_CRC_FN_NOT_SUPPORTED [D]: Function not supported by this CRC revision. + * - #ADI_CRC_FN_NOT_PERMITTED [D]: Function not permitted when CRC operation is in progress. + * - #ADI_CRC_INVALID_DMA_CHANNEL: DMA channel cannot be used with CRC (from crc_DmaDrivenOperation) + */ +ADI_CRC_RESULT adi_crc_Compute( + ADI_CRC_HANDLE const hDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); +#ifdef ADI_DEBUG + if (NumBits >= 8u) + { + result = ADI_CRC_INVALID_PARAMETER; + } + else if (NULL == pDevice) + { + result = ADI_CRC_BAD_HANDLE; + } + else if (((pDevice->pReg->CTL & BITM_CRC_CTL_REVID) == 0u) && (NumBits != 0u)) + { + result = ADI_CRC_FN_NOT_SUPPORTED; /* Partial byte needs CRC unit revision 1 or up */ + } + else + if (!ADI_CRC_DEVICE_IS_IDLE(pDevice)) /* IF (CRC in progress) */ + { + result = ADI_CRC_FN_NOT_PERMITTED; /* function not permitted when CRC operation is in progress */ + } + else +#endif /* ADI_DEBUG */ + { + pDevice->eCrcOpStatus = ADI_CRC_OP_IN_PROGRESS; /* mark the CRC as in progress */ + result = pDevice->pfSubmitBuffer(pDevice, pCrcBuf, NumBytes, NumBits); + + /* CRC returns in IDLE mode when it has processed all its data, not after submitting a request */ + } + return result; +} + +/** + * @brief Gets the current CRC peripheral status. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [in] pbCrcInProgress Pointer to location to store the current status of CRC peripheral. + * 'true' when CRC peripheral is in currently performing a CRC operation. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully set expected CRC result. + * - #ADI_CRC_BAD_HANDLE [D}: Supplied CRC handle is invalid. + * + * @note This function is valid only when device is operating in DMA mode. + * + */ +ADI_CRC_RESULT adi_crc_IsCrcInProgress( + ADI_CRC_HANDLE const hDevice, + bool *pbCrcInProgress) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + + if ((pDevice)->eCrcOpStatus == ADI_CRC_OP_IN_PROGRESS) + { + *pbCrcInProgress = true; + + } + else + { + *pbCrcInProgress = false; + + } + } + return result; +} + +/** + * @brief Gets the final CRC result computed for a data stream + * + * @details This API gets the final CRC result computed for a data stream + * and clears the current and final CRC results register. + * The CRC Current result register holds the current or + * intermediate CRC result. Whenever a CRC operation is initiated, + * the CRC peripheral takes the CRC Current register value as + * initial seed for CRC computation. This API clears both results + * register to start a fresh CRC computation. + * Use the adi_crc_GetCurrentCrcVal() API to get an intermediate + * CRC result without clearing the results register. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [out] pFinalCrcVal Pointer to location where the final CRC result of + * a data stream to be processed will be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully read final CRC result. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_GetFinalCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pFinalCrcVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + const uint32_t seed_value = (uint32_t) ADI_CFG_CRC_SEED_VALUE; + *pFinalCrcVal = pDevice->pReg->RESULT; /* Get the final CRC result */ + pDevice->pReg->RESULT = seed_value; + } + return result; +} + +/** + * @brief Gets the current/intermediate CRC result computed for a data stream. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [out] pCurrentCrcVal Pointer to location where the intermediate CRC result of + * a data stream to be processed will be written. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully read current CRC result. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_GetCurrentCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pCurrentCrcVal) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + *pCurrentCrcVal = pDevice->pReg->RESULT; /* Get the current CRC result */ + } + + return result; +} + +/** + * @brief Registers or unregisters a callback with the CRC device + * + * @details It is not required to register a callback for the operation of the + * driver. Data compare or DMA error will be notified via the + * adi_crc_IsCrcInProgress() API. But if an application requires the + * errors/events to be notified immediately it can register a callback + * with the driver which will be called to notify errors/events. + * + * When a callback is registered the API adi_crc_IsCrcInProgress() + * will not return error. + * + * @param [in] hDevice Handle to CRC device instance to work on + * @param [in] pfCallback Pointer to application callback function. The callback function + * has the prototype + * void callback(void *pCBParam, uint32_t nEvent, void *pArg) + * To unregister a callback pass the the pointer to the callback + * function as NULL. + * @param [in] pCBParam Callback parameter which will be returned back to the + * application when the callback function is called. + * + * @return Status + * - #ADI_CRC_SUCCESS: Successfully registered callback. + * - #ADI_CRC_BAD_HANDLE [D]: Supplied CRC handle is invalid. + */ +ADI_CRC_RESULT adi_crc_RegisterCallback( + ADI_CRC_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void *const pCBParam) +{ + ADI_CRC_RESULT result = ADI_CRC_SUCCESS; + ADI_CRC_DEVICE *pDevice = HDL_TO_DEVICE_PTR(hDevice); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); /* Entering critical region, disable interrupts */ + +#ifdef ADI_DEBUG + if (NULL == pDevice) /* IF (CRC device handle is invalid) */ + { + result = ADI_CRC_BAD_HANDLE; + } + else +#endif /* ADI_DEBUG */ + { + /* Update CRC Callback information */ + pDevice->pfCallback = pfCallback; + pDevice->pCBParam = pCBParam; + } + + ADI_EXIT_CRITICAL_REGION(); /* Re-enable interrupts */ + + return result; +} + + +/*****/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h new file mode 100755 index 00000000000..1558146d56f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crc/adi_crc_def.h @@ -0,0 +1,92 @@ +/*! ***************************************************************************** + * @file: adi_crc_def.h + * @brief: Private header file for for CRC driver. + * @details + * This is a private header file for the CRC driver, + * which contains the API declarations, data and + * constant definitions used in driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_DEF_H +#define ADI_CRC_DEF_H + +/* CRC Driver includes */ +#include + +/*! \cond PRIVATE */ + +typedef struct __ADI_CRC_DEVICE ADI_CRC_DEVICE; +typedef ADI_CRC_RESULT (*CRC_BUFFER_SUBMIT) (ADI_CRC_DEVICE *pDevice, void *pBuffer, uint32_t NumBytes, uint32_t NumBits); + +/* Enumeration of CRC operation status */ +typedef enum +{ + ADI_CRC_OP_IDLE = 0u, /* CRC idle */ + ADI_CRC_OP_IN_PROGRESS = 0x01u, /* CRC operation in progress */ +} ADI_CRC_OP_STATUS; + + +#pragma pack() + +/* Structure to handle CRC Peripheral instance */ +struct __ADI_CRC_DEVICE +{ + volatile ADI_CRC_TypeDef *pReg; + CRC_BUFFER_SUBMIT pfSubmitBuffer; /* Function for submitting CRC data buffer for calculation */ + ADI_CALLBACK pfCallback; /* Client supplied callback function */ + void *pCBParam; /* Client supplied callback parameter */ + void *pRemainingData; /* Pointer to the buffer containing remaining bytes */ + uint32_t RemainingBytes; /* Remaining bytes */ + uint32_t RemainingBits; /* Remaining bits */ + ADI_CRC_OP_STATUS eCrcOpStatus; /* Current status of the CRC Operation */ +}; + +/* Structure to hold CRC device specific information */ +typedef struct +{ + volatile ADI_CRC_TypeDef *pReg; /* CRC peripheral Registers */ + ADI_CRC_HANDLE hDevice; /* CRC device handle */ +} ADI_CRC_INFO; + +/*! \endcond */ + +#endif /* ADI_CRC_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c new file mode 100755 index 00000000000..e9405571657 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto.c @@ -0,0 +1,1577 @@ +/*! ***************************************************************************** + * @file: adi_crypto.c + * @brief: CRYPTO device driver source file. + * @details: This is the Crypto driver implementation file. + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup Crypto_Driver Crypto Driver + * @{ + * + * @brief Crypto Driver + * + * @details + * + * The Crypto controller provides hardware acceleration of various AES cryptographic + * cipher modes, including: ECB, CBC, CTR, CMAC, CCM, and SGA-256. The Crypto block + * works most efficiently in DMA mode due to the large about of data I/O which would + * otherwise incur a lot of PIO-mode interrupt traffic to manually pump data. + * + * Crypto Driver Static Configuration + * + * A number of Crypto cipher modes are able to be configured statically, such that + * if particular mode(s) are not required, the resulting driver footprint can be reduced + * internally by blocking out chunks of code that are not needed. + * + * @note - The application must include drivers/crypto/adi_crypto.h to use this driver. + * @note - This driver optionally uses the DMA driver if DMA is selected and active. + * In this case, the application must include the DMA driver sources to resolve + * DMA symbols. + */ + + +/*======== I N C L U D E ========*/ + +/*! \cond PRIVATE */ +#include +#include +#include + +/* main crypto include file */ +#include + +/* private crypto defines */ +#include "adi_crypto_def.h" + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* dma interface */ +#include +#endif + + +/*======== D E F I N E S ========*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Pm152 (rule 17.4): array indexing shall only be applied to objects defined as an array type +*/ +#pragma diag_suppress=Pm123,Pm140,Pm050,Pm088,Pm073,Pm143,Pm152 +#endif /* __ICCARM__ */ + +/* Utility Macros */ +#define CLR_BITS(REG,BITS) ((REG) &= ~(BITS)) +#define SET_BITS(REG,BITS) ((REG) |= (BITS)) +#define IS_ANY_BIT_SET(REG,BITS) (((REG) & (BITS)) != 0u) + + +/* Number of crypto device for the given processor */ +#define NUM_DEVICES (1u) + +/* Compiler-specific mapping of assebbly-level byte-swap instruction + IAR is "__REV", and we think Keil is "__rev", but lets see how that + goes when it is undefined for Keil. +*/ +#if defined ( __ICCARM__ ) +#define __ADI_BYTE_SWAP(X) __REV(X) +#elif defined (__GNUC__) +#define __ADI_BYTE_SWAP(X) __builtin_bswap32(X) +#elif defined (__CC_ARM) +#define __ADI_BYTE_SWAP(X) __rev(X) +#else +#error "This toolchain is not supported" +#endif + + +/*======== L O C A L F U N C D E C L ========*/ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void dmaCallback (void *pCBParam, uint32_t Event, void *pArg); +#endif + +#ifdef ADI_DEBUG +/* Validatation routines */ +static ADI_CRYPTO_RESULT ValidateHandle (ADI_CRYPTO_HANDLE const hDevice); +static ADI_CRYPTO_RESULT ValidateUserBuffer (ADI_CRYPTO_TRANSACTION * const pBuffer); +#endif + +/* Generate a uint32_t value from a pointer to a uint8_t buffer */ +static uint32_t u32FromU8p (uint8_t * const pData); + +/* Initialize the internal device handle object (user memory) */ +static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice); + +/* Initiate the computation for a buffer */ +static void StartCompute (ADI_CRYPTO_HANDLE const hDevice); + +/* Stop the device */ +static void StopCompute (ADI_CRYPTO_HANDLE const hDevice); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void programDMA (ADI_CRYPTO_HANDLE const hDevice); +#endif + +/* PIO mode write input data */ +static void writePioInputData (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status); + +/* PIO mode read output data */ +static void readPioOutputData (ADI_CRYPTO_HANDLE const hDevice, uint32_t const status); + +/* Flush the input and output buffers */ +static void FlushInputOutputRegisters (ADI_CRYPTO_HANDLE const hDevice); + + +/* pre-defined Crypto interrupt handler prototypes, as linked in IVT */ +void Crypto_Int_Handler(void); +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +void DMA_AES0_IN_Int_Handler (void); +void DMA_AES0_OUT_Int_Handler (void); +#endif + + +/*======== D A T A ========*/ +/* Internal device structure */ + +static CRYPTO_INFO CryptoDevInfo[] = { + {pADI_CRYPT0, /* physical device controller pointer */ + NULL, /* hDevice */ +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + DMA0_CH13_DONE_IRQn, /* DMA input interrupt number */ + DMA0_CH14_DONE_IRQn, /* DMA output interrupt number */ + AES0_IN_CHANn, /* DMA input channel */ + AES0_OUT_CHANn, /* DMA output channel */ + ADI_CRYPTO_SUCCESS, /* DMA error state */ +#endif + } +}; + +/*! \endcond */ + +/*======== C O D E ========*/ + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + +/* Internal Crypto registered DMA Callback for receiving DMA + fault notifications from the shared DMA error handler */ +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) +{ + /* recover device handle */ + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + + /* recover failing channel number */ + uint32_t failingChannel = (uint32_t)pCBParam; + + /* save the DMA error */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_INVALID_DESCR; + break; + default: + hDevice->dmaErrorCode = ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR; + break; + } + + /* transfer is toast... post semaphore to unblock any waiters */ + SEM_POST(hDevice); + + /* call user's callback */ + if (0u != hDevice->pfCallback) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaErrorCode, (void*)failingChannel); + } + + /* game over... */ + StopCompute(hDevice); +} +#endif + + +#ifdef ADI_DEBUG +/* Validate the given handle */ +static ADI_CRYPTO_RESULT ValidateHandle(ADI_CRYPTO_HANDLE const hDevice) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_ERR_BAD_DEV_HANDLE; + uint32_t x; + + for (x = 0u; x < NUM_DEVICES; x++) { + if (CryptoDevInfo[x].hDevice == hDevice) { + result = ADI_CRYPTO_SUCCESS; + break; + } + } + + return result; +} +#endif + + +#ifdef ADI_DEBUG +static ADI_CRYPTO_RESULT ValidateUserBuffer(ADI_CRYPTO_TRANSACTION * const pBuffer) +{ + + /* null pointer and zero count checks */ + if ( + (pBuffer->pInputData == NULL) + || (pBuffer->numInputBytes == 0u) + || (pBuffer->pOutputData == NULL) + || (pBuffer->numOutputBytes == 0u) + || ( + (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_LITTLE_ENDIAN) + && (pBuffer->eAesByteSwap != ADI_CRYPTO_AES_BIG_ENDIAN)) + ) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + + /* check buffer pointers for 32-bit alignment */ + if ( (0u != (3u & (uint32_t)pBuffer->pAuthData)) || (0u != (3u & (uint32_t)pBuffer->pInputData)) || (0u != (3u & (uint32_t)pBuffer->pOutputData)) ) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* check buffer sizes for max DMA size */ + if ((MAX_CRYPTO_DMA_BYTES < pBuffer->numAuthBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numInputBytes) || (MAX_CRYPTO_DMA_BYTES < pBuffer->numOutputBytes)) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } +#endif + +#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_SHA) + { + /* SHA output digest is 256-bit and hence the output buffer size should be at least 32 bytes */ + if (pBuffer->numOutputBytes < SHA_OUTPUT_SIZE_IN_BYTES) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + +#if ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CMAC) { + /* CMAC output is always a 128-bit block */ + if (pBuffer->numOutputBytes < CRYPTO_INPUT_SIZE_IN_BYTES) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + if ( + (pBuffer->pKey == NULL) + || ( (pBuffer->eAesKeyLen != ADI_CRYPTO_AES_KEY_LEN_128_BIT) + && (pBuffer->eAesKeyLen != ADI_CRYPTO_AES_KEY_LEN_256_BIT)) + || ( (pBuffer->eCodingMode != ADI_CRYPTO_ENCODE) + && (pBuffer->eCodingMode != ADI_CRYPTO_DECODE))) + { + return ADI_CRYPTO_ERR_BAD_CONFIG; + } + +#if ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CTR) + { + if ((pBuffer->CounterInit & (0xFFF00000u)) != 0u) { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } +#endif + +#if ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_CCM) + { + if ( ((pBuffer->CounterInit & (0xFFFF0000u)) != 0u) + || ( (pBuffer->pAuthData != NULL) + && ( + (pBuffer->numAuthBytes == 0u) + || (pBuffer->numValidBytes == 0u) + || (pBuffer->numValidBytes > CRYPTO_INPUT_SIZE_IN_BYTES) + || (pBuffer->numOutputBytes < (pBuffer->numInputBytes + CRYPTO_INPUT_SIZE_IN_BYTES)) + ) + ) + ) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + else +#endif + { + if (pBuffer->numOutputBytes < pBuffer->numInputBytes) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } + } + } + } + +/* FIXME: Issue http://labrea.ad.analog.com/browse/MSKEW-299 describes missing support + for HMAC mode, so reject HMAC submits until support for this mode is implimented. + ***REMOVE THIS BLOCK WHEN HMAC SUPPORT IS ADDED*** +*/ +#if ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1 + if (pBuffer->eCipherMode == ADI_CRYPTO_MODE_HMAC) + { + return ADI_CRYPTO_ERR_BAD_BUFFER; + } +#endif + + return ADI_CRYPTO_SUCCESS; +} +#endif + + +/** + * @brief Opens a Crypto device instance. + * + * @param [in] nDeviceNum Device number to open. + * @param [in] pMemory Pointer to a #ADI_CRYPTO_MEMORY_SIZE sized buffer to manage the device + * instance. + * @param [in] nMemorySize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where the Crypto device handle is to be written. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Call completed successfully. + * - #ADI_CRYPTO_ERR_BAD_DEVICE_NUM [D] Error: The device number is invalid. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: A parameter is invalid. + * - #ADI_CRYPTO_ERR_INSUFFICIENT_MEM [D] Error: The memory passed to the device is insufficient. + * - #ADI_CRYPTO_ERR_ALREADY_INITIALIZED [D] Error: The device is already opened. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Unable to create semaphore. + * - #ADI_CRYPTO_ERR_DMA_REGISTER Error: Unable to register DMA error callback function. + * + * @sa adi_crypto_Close(). + */ +ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice) +{ + ADI_CRYPTO_HANDLE hDevice = NULL; + +#ifdef ADI_DEBUG + if (nDeviceNum >= NUM_DEVICES) { + return ADI_CRYPTO_ERR_BAD_DEVICE_NUM; + } + + if ((pMemory == NULL) || (phDevice == NULL)) { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + + if (nMemorySize < ADI_CRYPTO_MEMORY_SIZE) { + return ADI_CRYPTO_ERR_INSUFFICIENT_MEM; + } + + if (CryptoDevInfo[nDeviceNum].hDevice != NULL) { + return ADI_CRYPTO_ERR_ALREADY_INITIALIZED; + } + + /* reality checks */ + assert (ADI_CRYPTO_MEMORY_SIZE == sizeof(ADI_CRYPTO_DEV_DATA_TYPE)); + assert (sizeof(ADI_CRYPTO_TRANSACTION) == sizeof(CRYPTO_COMPUTE)); + +#endif /* ADI_DEBUG */ + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* point local device handle to the user memory */ + hDevice = (ADI_CRYPTO_HANDLE)pMemory; + + /* link CRYPTO controller register set */ + hDevice->pDev = CryptoDevInfo[nDeviceNum].pDev; + + /* link device info */ + hDevice->pDevInfo = CryptoDevInfo; + + /* cross-link device handle into device info */ + CryptoDevInfo[nDeviceNum].hDevice = hDevice; + + /* Initialize the driver internals */ + InitializeDevData(hDevice); + + /* create the semaphore */ + SEM_CREATE(hDevice, "crypto_sem", ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* initialize DMA core */ + adi_dma_Init(); + + /* register DMA error callback for INPUT channel */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaInputChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize crypto driver and fail */ + adi_crypto_Close(hDevice); + return ADI_CRYPTO_ERR_DMA_REGISTER; + } + /* register DMA error callback for OUTPUT channel */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaOutputChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize crypto driver and fail */ + adi_crypto_Close(hDevice); + return ADI_CRYPTO_ERR_DMA_REGISTER; + } +#endif + + /* Give the handle back to the application */ + *phDevice = hDevice; + + /* Return success */ + return ADI_CRYPTO_SUCCESS; +} + +/** + * @brief Close the given device instance. + * + * @param [in] hDevice Handle to the device instance. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully closed the device. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Unable to delete semaphore. + * + * @sa adi_crypto_Open(). + */ +ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice) +{ + uint32_t x; + ADI_CRYPTO_RESULT result; + +#ifdef ADI_DEBUG + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } +#endif /* ADI_DEBUG */ + + /* IF (The device is enabled) */ + if (hDevice->bDeviceEnabled) { + result = adi_crypto_Enable(hDevice, false); + if (result != ADI_CRYPTO_SUCCESS) { + return result; + } + } + + /* Destroy the semaphore */ + SEM_DELETE(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + + /* Close the device */ + for (x=0u; x < NUM_DEVICES; x++) { + if (CryptoDevInfo[x].hDevice == hDevice) { + CryptoDevInfo[x].hDevice = NULL; + break; + } + } + + return ADI_CRYPTO_SUCCESS; +} + + +/** + * @brief Register a user callback function. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pfCallback Function pointer to user callback function. Passing a NULL pointer will + * unregister the callback function. + * @param [in] pCBParam Callback function parameter. + * + * @details This function registers a user callback function. The registered function will be called when + * the given computation is over. Registering an active user callback function implies use of the + * (non-blocking) CALLBACK mode during which any subsequent calls to the (blocking-mode) + * #adi_crypto_GetBuffer() API will be rejected. + * + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully registerd the callback. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + */ + ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam) +{ +#ifdef ADI_DEBUG + ADI_CRYPTO_RESULT result; + + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } +#endif /* ADI_DEBUG */ + + /* store user's callback values (critical section) */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + return ADI_CRYPTO_SUCCESS; +} + + +/** + * @brief Submit a Crypto transaction buffer for processing. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pBuffer Pointer to the #ADI_CRYPTO_TRANSACTION structure which contains details + * of the cipher-dependent buffer elements required by the driver. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully submitted the buffer. + * - #ADI_CRYPTO_ERR_COMPUTE_ACTIVE Error: Buffer already submitted. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_BAD_BUFFER [D] Error: The buffer passed to the device is invalid or unsupported. + * + * The buffer submitted is queued for eventual CRYPTO processing. A single buffer may be submitted + * prior to initiating CRYPTO buffer processing. Buffer processing is initiated with the + * #adi_crypto_Enable() call. As buffer processing is completed, the buffer (and result info) + * is retrieved with the #adi_crypto_GetBuffer() API or through the user callback notification. + * + * @note The driver takes ownership of the ADI_CRYPTO_TRANSACTION structure passed to the driver. + * The application must insure the structure is not used and its scope is valid untill + * the structure is returned back to the application. + * + * @warning The #ADI_CRYPTO_TRANSACTION buffer is a common superset of all possible cipher mode parameters. + * As such, not all parameters pertain to each cipher mode. It is recommended users clear unused + * parameters prior to configuration for the particular cipher mode. The example provided + * illustrates this with a call to: "memset(&Buffer, 0, sizeof(ADI_CRYPTO_TRANSACTION));" + * before configuring and then submitting each transaction. + * + * @sa adi_crypto_Enable(). + * @sa adi_crypto_GetBuffer(). + * @sa adi_crypto_IsBufferAvailable(). + */ + ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + + /* reject if we already have a user buffer */ + if (NULL != hDevice->pUserBuffer) { + /* computation already active */ + return ADI_CRYPTO_ERR_COMPUTE_ACTIVE; + } + +#ifdef ADI_DEBUG + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } + + /* validate user Buffer */ + if (ADI_CRYPTO_SUCCESS != (result = ValidateUserBuffer(pBuffer))) { + return result; + } +#endif + + /* store user buffer pointer to return later */ + hDevice->pUserBuffer = pBuffer; + + /* initialize internal compute state from user buffer */ + memcpy(&hDevice->Computation, pBuffer, sizeof(ADI_CRYPTO_TRANSACTION)); + + /* don't initiate transaction until we get adi_crypto_Enable() */ + + /* reset dma error code */ + hDevice->dmaErrorCode = ADI_CRYPTO_SUCCESS; + + return result; +} + + +/** + * @brief Get the submitted transaction buffer back from the driver. + * + * @param [in] hDevice Handle to the device instance. + * @param [out] ppBuffer Pointer to a location to which the address of the buffer structure is written. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully got a buffer. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: Pointer to the buffer is NULL. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_DMA_BUS_FAULT Error: DMA bus fault was reported. + * - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR Error: Invalid DMA descriptor was reported. + * - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR Error: An unexpected DMA error was reported. + * - #ADI_CRYPTO_ERR_SEMAPHORE_FAILED Error: Semaphore pend request failed. + * - #ADI_CRYPTO_ERR_INVALID_STATE Error: Invalid call when using callback mode. + * + * This is a blocking call and will await transaction completion (if not already). + * This function should not be called if a callback function is registered. + * + * @sa adi_crypto_SubmitBuffer(). + * @sa adi_crypto_IsBufferAvailable(). + */ +ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + + if (ppBuffer == NULL) { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } +#endif /* ADI_DEBUG */ + + if (NULL != hDevice->pfCallback) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } + + /* pend on completion (even if already complete) */ + SEM_PEND(hDevice, ADI_CRYPTO_ERR_SEMAPHORE_FAILED); + + /* give back the user's buffer */ + *ppBuffer = hDevice->pUserBuffer; + + /* clear internal user buffer pointer */ + hDevice->pUserBuffer = NULL; + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + + return result; +} + + +/** + * @brief Peek function to know whether a submitted transaction is complete. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] pbAvailable Pointer to a Boolean variable. Set to "true" if there is a completed + * buffer and a call to adi_crypto_GetBuffer is ensured to be successful. + * Set to "false" if there is no completed buffer. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully peeked for a buffer. + * - #ADI_CRYPTO_ERR_INVALID_PARAM [D] Error: The pointer passed is NULL. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_DMA_BUS_FAULT Error: DMA bus fault was reported. + * - #ADI_CRYPTO_ERR_DMA_INVALID_DESCR Error: Invalid DMA descriptor was reported. + * - #ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR Error: An unexpected DMA error was reported. + * + * @sa adi_crypto_SubmitBuffer(). + * @sa adi_crypto_GetBuffer(). + */ +ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + if (pbAvailable == NULL) + { + return ADI_CRYPTO_ERR_INVALID_PARAM; + } + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } +#endif /* ADI_DEBUG */ + + /* let the respective PIO/DMA interrupts drive completion... just return that state here */ + *pbAvailable = hDevice->bCompletion; + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + + return result; +} + + +/** + * @brief Enable/Disable the device. Enabling the device causes the submitted buffer to be processed. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] bEnable 'true' to enable and 'false' to disable the device. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully enabled/disabled the device. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_INVALID_STATE [D] Error: Calling enable when device is already enabled or + * disable when the device is already disabled. + * + */ +ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable) +{ + ADI_CRYPTO_RESULT result = ADI_CRYPTO_SUCCESS; + +#ifdef ADI_DEBUG + + if (ADI_CRYPTO_SUCCESS != (result = ValidateHandle(hDevice))) { + return result; + } + if (bEnable == hDevice->bDeviceEnabled) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (true == bEnable) { + + /* device enable */ + + /* Enable the IRQs */ + NVIC_EnableIRQ(CRYPT_EVT_IRQn); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* Enable the DMA interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); +#endif + + /* Mark the device as enabled */ + hDevice->bDeviceEnabled = true; + + /* Start processing buffer */ + StartCompute(hDevice); + + } else { + + /* device disable */ + + /* Disable the IRQs */ + NVIC_DisableIRQ(CRYPT_EVT_IRQn); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* Enable the DMA interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); +#endif + + /* Stop the device */ + StopCompute(hDevice); + + /* if we had a DMA error, return that instead of success */ + if (ADI_CRYPTO_SUCCESS != hDevice->dmaErrorCode) { + result = hDevice->dmaErrorCode; + } + } + + /* Return success */ + return result; +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/** + * @brief Dynamically Enable/Disable DMA mode for the device. + * + * @param [in] hDevice Handle to the device instance. + * @param [in] bEnable 'true' will enable DMA and 'false' disables the DMA. + * + * @return Status + * - #ADI_CRYPTO_SUCCESS Successfully enabled/disabled the DMA. + * - #ADI_CRYPTO_ERR_BAD_DEV_HANDLE [D] Error: Handle Passed is invalid. + * - #ADI_CRYPTO_ERR_INVALID_STATE [D] Error: DMA cannot be enabled or disabled when the device is already enabled. + * + * Manage use of DMA mode dynamically. Presupposes DMA support has been enabled statically + * in the static configuration files via the ADI_CRYPTO_ENABLE_DMA_SUPPORT macro. + * + * @note In addition to requiring that DMA support is enabled (see ADI_CRYPTO_ENABLE_DMA_SUPPORT static + * configuration macro) for #adi_crypto_EnableDmaMode() to be available, use of DMA mode may + * also be statically configured (see ADI_CRYPTO_ENABLE_DMA). Both these macros may be set statically + * to both enable DMA support and to activate the DMA mode in a fully static manner, without need of + * calling adi_crypto_EnableDmaMode() at all (in which case, this function may be eliminated by the linker). + */ +ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable) +{ +#ifdef ADI_DEBUG + ADI_CRYPTO_RESULT result; + + if ((result = ValidateHandle(hDevice)) != ADI_CRYPTO_SUCCESS) { + return result; + } + if (hDevice->bDeviceEnabled) { + return ADI_CRYPTO_ERR_INVALID_STATE; + } +#endif /* ADI_DEBUG */ + + if (bEnable) + { + /* Enable DMA and map data pump handler */ + hDevice->bDmaEnabled = true; + + /* Enable the DMA interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + } + else + { + /* Disable DMA and map data pump handler */ + hDevice->bDmaEnabled = false; + + /* Disable the DMA interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + } + + /* Return success */ + return ADI_CRYPTO_SUCCESS; +} +#endif + + + +/*! \cond PRIVATE */ + +/*======== L O C A L F U N C T I O N D E F I N I T I O N S ========*/ + +/* Generate a u32 from a pointer to u8 buffer */ +static uint32_t u32FromU8p(uint8_t * const pData) +{ + int32_t x = 0; + uint32_t nValue = pData[3]; + + for (x = 2; x >= 0; x--) { + nValue = (nValue << 8u) | pData[x]; + } + return nValue; +} + + +/* Initialize the device structure */ +static void InitializeDevData (ADI_CRYPTO_HANDLE const hDevice) +{ + /* Clear the device structure */ + memset(hDevice, 0, sizeof(ADI_CRYPTO_HANDLE)); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + #if (ADI_CRYPTO_ENABLE_DMA == 1) + hDevice->bDmaEnabled = true; + NVIC_EnableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + #else + hDevice->bDmaEnabled = false; + NVIC_DisableIRQ(hDevice->pDevInfo->dmaInputIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaOutputIrqNum); + #endif +#else + /* no DMA support */ + hDevice->bDmaEnabled = false; +#endif +} + + +/* initiate buffer processing (called from crypto enable) */ +static void StartCompute(ADI_CRYPTO_HANDLE const hDevice) +{ + /* clear completion flag */ + hDevice->bCompletion = false; + + /* Get pointer to the compute buffer */ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + + /* Clear any pending interrupts (all are R/W1C) */ + hDevice->pDev->STAT = hDevice->pDev->STAT; + + /* reset crypto config register */ + hDevice->pDev->CFG = 0u; + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + /* reset SHA hardware machine state */ + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_SHAINIT); + } +#endif + + /* program main config register settings */ + SET_BITS(hDevice->pDev->CFG, + ( (uint32_t)pCompute->eCipherMode /* cipher mode */ + | (uint32_t)pCompute->eKeyByteSwap /* KEY endianness */ + | (uint32_t)pCompute->eShaByteSwap /* SHA endianness */ + | (uint32_t)pCompute->eAesByteSwap /* AES endianness */ + | (uint32_t)pCompute->eAesKeyLen /* AES key length */ + | (uint32_t)pCompute->eCodingMode /* encode mode */ + ) + ); + +#if (CRYPTO_SUPPORT_KEY_REQUIRED) + if (NULL != pCompute->pKey) { + + /* program user key */ + uint32_t volatile *pKeyReg = &hDevice->pDev->AESKEY0; + uint8_t *pUserKey = pCompute->pKey; + uint32_t numKeyWords; + + /* set key length register */ + SET_BITS(hDevice->pDev->CFG, (uint32_t)pCompute->eAesKeyLen); + + /* Set the number of keywords to write to the 32-bit keyword registers */ + switch (pCompute->eAesKeyLen) { + case ADI_CRYPTO_AES_KEY_LEN_128_BIT: + numKeyWords = 4u; + break; + case ADI_CRYPTO_AES_KEY_LEN_256_BIT: + numKeyWords = 8u; + break; + default: + numKeyWords = 0u; /* hardware only supports only 128-bit and 256-bit key length (no 192-bit) */ + break; + } + + /* load the key (key registers have write-no-read attribute) */ + for (uint32_t count = 0u; count < numKeyWords; count++) { + *pKeyReg = u32FromU8p(pUserKey); + pKeyReg++; + pUserKey += sizeof(uint32_t); + } + } +#endif /* (CRYPTO_SUPPORT_KEY_REQUIRED) */ + +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CMAC == pCompute->eCipherMode) { + /* program CMAC-specific registers */ + /* DATALEN in CMAC mode is number of 128 bit pages (or 16, 8 byte pages) */ + hDevice->pDev->DATALEN = pCompute->numInputBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + } +#endif /* (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) { + /* program CMM-specific registers */ + hDevice->pDev->PREFIXLEN = pCompute->numAuthBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + hDevice->pDev->DATALEN = pCompute->numInputBytesRemaining / CRYPTO_INPUT_SIZE_IN_BYTES; + hDevice->pDev->CCM_NUM_VALID_BYTES = pCompute->numValidBytes; + } +#endif /* (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + + if ( (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CCM == pCompute->eCipherMode) || (ADI_CRYPTO_MODE_CTR == pCompute->eCipherMode) ) + { + /* program NONCE/IV for CBC, CCM and CTR modes */ + assert (NULL != pCompute->pNonceIV); + + /* Configure Counter Init and NONCE values */ + hDevice->pDev->CNTRINIT = pCompute->CounterInit; + + hDevice->pDev->NONCE0 = u32FromU8p(&pCompute->pNonceIV[0]); + hDevice->pDev->NONCE1 = u32FromU8p(&pCompute->pNonceIV[4]); + hDevice->pDev->NONCE2 = u32FromU8p(&pCompute->pNonceIV[8]); + + hDevice->pDev->NONCE3 = ((uint32_t)pCompute->pNonceIV[12] << 0u) | ((uint32_t)pCompute->pNonceIV[13] << 8u); + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + if (ADI_CRYPTO_MODE_CBC == pCompute->eCipherMode) { + + /* additionally, CBC mode requires remaining IV data */ + hDevice->pDev->NONCE3 |= ( ((uint32_t)pCompute->pNonceIV[14] << 16u) | ((uint32_t)pCompute->pNonceIV[15] << 24u) ); + } +#endif /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) */ + } +#endif /* (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + + /* onle enable DMA for non-SHA mode or SHA mode with > 4 bytes of input... */ + if ( ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode)) + || ((true == hDevice->bDmaEnabled) && (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) && (4u < pCompute->numInputBytesRemaining)) ) + { + + /* DMA startup... */ + programDMA(hDevice); + + /* mode-specific DMA interrupt enables */ + switch (pCompute->eCipherMode) { + case ADI_CRYPTO_MODE_HMAC: + /* enable HMAC done and overrun interrupts (via PIO handler) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_INOVREN)); + break; + case ADI_CRYPTO_MODE_SHA: + /* enable SHA done and overrun interrupts */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN)); + SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN)); + break; + default: + /* enable DMA I/O interrupts */ + SET_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_OUTDMAEN | BITM_CRYPT_CFG_INDMAEN)); + break; + } + + /* crypto hardware enable */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + } else +#endif + { + /* mode-specific PIO interrupt enables */ + switch (pCompute->eCipherMode) { + case ADI_CRYPTO_MODE_HMAC: + /* HMAC done interrupts via PIO handler (do NOT use INRDY in HMAC mode) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_HMACDONEEN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INOVREN)); + break; + case ADI_CRYPTO_MODE_SHA: + /* SHA done interrupts via PIO handler (do NOT use INRDY in SHA mode) */ + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_SHADONEN | BITM_CRYPT_INTEN_INOVREN)); + break; + default: + SET_BITS(hDevice->pDev->INTEN, (BITM_CRYPT_INTEN_INOVREN | BITM_CRYPT_INTEN_OUTRDYEN | BITM_CRYPT_INTEN_INRDYEN)); + break; + } + + /* crypto hardware enable */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + /* manual write of 1st input data batch... (interrupt-driven hereafter...) */ + writePioInputData(hDevice, hDevice->pDev->STAT); + } +} + + +/* halt computation */ +static void StopCompute (ADI_CRYPTO_HANDLE const hDevice) +{ + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + /* disable Crypto DMA */ + CLR_BITS(hDevice->pDev->CFG, (BITM_CRYPT_CFG_INDMAEN | BITM_CRYPT_CFG_OUTDMAEN)); +#endif + + /* clear all interrupt enables */ + hDevice->pDev->INTEN = 0u; + + /* Flush the buffers */ + FlushInputOutputRegisters(hDevice); + + /* device disable */ + CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_BLKEN); + + /* Mark the device as disabled */ + hDevice->bDeviceEnabled = false; +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +static void programDMA(ADI_CRYPTO_HANDLE const hDevice) +{ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + ADI_DCC_TypeDef* pCCD; /* pointer to DMA Control Data Descriptor */ + uint32_t channelBit; + uint32_t num32BitWords; + + /* start with INPUT channel */ + channelBit = 1u << hDevice->pDevInfo->dmaInputChanNum; + + /* disable various stuff */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* disable src endpointer decrement mode */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* disable dst endpointer decrement mode */ + pADI_DMA0->EN_SET = channelBit; /* channel enable */ + pADI_DMA0->RMSK_CLR = channelBit; /* allow Crypto to request DMA service */ + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + /* program input descriptor(s) */ + if (0u != pCompute->pNextAuthInput) { + + /* schedule authentication data into primary descriptor (USING ping-pong mode) */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate PRIMARY descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to primary INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextAuthInput + sizeof(uint32_t) * (pCompute->numAuthBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numAuthBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_PING_PONG << DMA_BITP_CTL_CYCLE_CTL) ); + + + /* schedule input data into alternate descriptor (in basic mode) */ + pADI_DMA0->PRI_CLR = channelBit; /* activate ALTERNATE descriptor */ + pCCD = pAlternateCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to alternate INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + } else +#endif /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + { + + /* no authentication data, just schedule input data into primary descriptor (in basic mode) */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate PRIMARY descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaInputChanNum; /* point to primary INPUT descriptor */ + + /* setup the endpoints (point to input register & last 4 bytes of input array) */ +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Stop SHA-mode input writes one short of last 32-bit word so the DMA input interrupt + can manually call PIO write function to handle SHA end flag and last write manually. */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * (pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 2u); + num32BitWords = (pCompute->numInputBytesRemaining - (pCompute->numInputBytesRemaining % sizeof(uint32_t))) / sizeof(uint32_t) - 1u; /* count - 1 */ + } + else +#endif + { + /* stop at last write end */ + pCCD->DMASRCEND = (uint32_t)pCompute->pNextInput + sizeof(uint32_t) * ( pCompute->numInputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + num32BitWords = pCompute->numInputBytesRemaining / sizeof(uint32_t); /* count */ + } + + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->INBUF; + + /* program DMA Control Data Config register */ + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + } + +/* don't program output DMA in SHA mode... */ +#if CRYPTO_SUPPORT_MODE_ANY_NON_SHA + + if (ADI_CRYPTO_MODE_SHA != pCompute->eCipherMode) { + + /* switch to OUTPUT channel */ + channelBit = 1u << hDevice->pDevInfo->dmaOutputChanNum; + + /* disable various stuff */ + pADI_DMA0->SRCADDR_CLR = channelBit; /* disable src endpointer decrement mode */ + pADI_DMA0->DSTADDR_CLR = channelBit; /* disable dst endpointer decrement mode */ + pADI_DMA0->EN_SET = channelBit; /* channel enable */ + pADI_DMA0->RMSK_CLR = channelBit; /* allow Crypto to request DMA service */ + + pADI_DMA0->ALT_CLR = channelBit; /* activate primary descriptor */ + pCCD = pPrimaryCCD + hDevice->pDevInfo->dmaOutputChanNum; /* point to crypto OUTPUT descriptor */ + + + /* setup the endpoints (point to output register & last 4 bytes of output array) */ + pCCD->DMASRCEND = (uint32_t)&hDevice->pDev->OUTBUF; + pCCD->DMADSTEND = (uint32_t)pCompute->pNextOutput + sizeof(uint32_t) * (pCompute->numOutputBytesRemaining / FIFO_WIDTH_IN_BYTES - 1u); + + /* program DMA Control Data Config register */ + num32BitWords = pCompute->numOutputBytesRemaining / sizeof(uint32_t); + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_4 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((num32BitWords - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + } /* end non-SHA mode */ + +#endif /* CRYPTO_SUPPORT_MODE_ANY_NON_SHA */ +} +#endif /* #if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) */ + + +static void writePioInputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status) +{ + CRYPTO_COMPUTE* pCompute = &hDevice->Computation; + uint32_t numWritable = FIFO_DEPTH - ((status & BITM_CRYPT_STAT_INWORDS) >> BITP_CRYPT_STAT_INWORDS); + +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + /* always send authentication data before input payload is sent */ + if (0u != pCompute->numAuthBytesRemaining) { + + /* fill input FIFO with 32-bit authentication data */ + while ((0u != numWritable) && (0u != pCompute->numAuthBytesRemaining)) { + hDevice->pDev->INBUF = *pCompute->pNextAuthInput; + pCompute->pNextAuthInput++; + pCompute->numAuthBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numWritable--; + } + } else +#endif /* #if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) */ + { + /* no authentication data, process payload input data */ + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Drive up to a full "chunk" of SHA input message data. + Chunk size is limited to 512-bits (64-bytes) by AES + hardware compute block. + */ + + if (pCompute->numInputBytesRemaining >= SHA_CHUNK_MAX_BYTES) + { + /* This is the simple case, load up an entire chunk and let it go */ + for (uint8_t i = 0u; i < SHA_CHUNK_MAX_WORDS; i++) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + } + + pCompute->numShaBitsRemaining -= SHA_CHUNK_MAX_BITS; + pCompute->numInputBytesRemaining -= SHA_CHUNK_MAX_BYTES; + } + else + { + /* The final case, we load up any bytes less than a full chunk and trigger the last word */ + while (FIFO_WIDTH_IN_BITS <= pCompute->numShaBitsRemaining) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + pCompute->numShaBitsRemaining -= FIFO_WIDTH_IN_BITS; + } + + hDevice->pDev->SHA_LAST_WORD = (pCompute->numShaBitsRemaining << BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID) | BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD; + + /* Last write is dummy or not, depending on remaining bit count */ + if (0u == pCompute->numShaBitsRemaining) { + /* dummy write */ + hDevice->pDev->INBUF = 0u; + } else { + /* partial data (last remaining message data word) */ + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + } + + pCompute->numShaBitsRemaining = 0u; + pCompute->numInputBytesRemaining = 0u; + + /* Use output bytes as a way of confirming that we are really done (can't use input bytes/bits) */ + pCompute->numOutputBytesRemaining -= SHA_OUTPUT_SIZE_IN_BYTES; + } + } /* end of SHA mode */ + else +#endif + { + /* full input FIFO with normal payload write (non-SHA) */ + while ((0u != numWritable) && (0u != pCompute->numInputBytesRemaining)) { + hDevice->pDev->INBUF = *pCompute->pNextInput; + pCompute->pNextInput++; + pCompute->numInputBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numWritable--; + } + } + } +} + + +static void readPioOutputData(ADI_CRYPTO_HANDLE const hDevice, uint32_t const status) +{ + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + uint32_t numReadable; + +#if ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1 + /* Copy the SHA output if enabled */ + if (pCompute->eCipherMode == ADI_CRYPTO_MODE_SHA) + { + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_SHADONE)) { + + /* Get 1 SHADONE per block + 1 SHADONE when we trigger the last word */ + if (0u == pCompute->numOutputBytesRemaining) { +#if ADI_CRYPTO_SHA_OUTPUT_FORMAT == 0 /* Little Endian */ + pCompute->pNextOutput[0] = hDevice->pDev->SHAH7; + pCompute->pNextOutput[1] = hDevice->pDev->SHAH6; + pCompute->pNextOutput[2] = hDevice->pDev->SHAH5; + pCompute->pNextOutput[3] = hDevice->pDev->SHAH4; + pCompute->pNextOutput[4] = hDevice->pDev->SHAH3; + pCompute->pNextOutput[5] = hDevice->pDev->SHAH2; + pCompute->pNextOutput[6] = hDevice->pDev->SHAH1; + pCompute->pNextOutput[7] = hDevice->pDev->SHAH0; +#else + pCompute->pNextOutput[0] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH0); + pCompute->pNextOutput[1] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH1); + pCompute->pNextOutput[2] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH2); + pCompute->pNextOutput[3] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH3); + pCompute->pNextOutput[4] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH4); + pCompute->pNextOutput[5] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH5); + pCompute->pNextOutput[6] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH6); + pCompute->pNextOutput[7] = __ADI_BYTE_SWAP(hDevice->pDev->SHAH7); +#endif + } + } + } + else +#endif + { + /* read any ready non-SHA output from output FIFO */ + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_OUTRDY)) { + numReadable = ((status & BITM_CRYPT_STAT_OUTWORDS) >> BITP_CRYPT_STAT_OUTWORDS); + while ((0u != numReadable) && (0u != pCompute->numOutputBytesRemaining)) { + *pCompute->pNextOutput = hDevice->pDev->OUTBUF; + pCompute->pNextOutput++; + pCompute->numOutputBytesRemaining -= FIFO_WIDTH_IN_BYTES; + numReadable--; + } + } + } + + /* if output count has gone to zero, set completion flag */ + if (0u == pCompute->numOutputBytesRemaining) { + hDevice->bCompletion = true; + } +} + + +/* Flush the Crypto input and output buffers */ +static void FlushInputOutputRegisters(ADI_CRYPTO_HANDLE const hDevice) +{ + /* Set and clear the flush bits to flush the input and output buffers */ + SET_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH); + CLR_BITS(hDevice->pDev->CFG, BITM_CRYPT_CFG_INFLUSH | BITM_CRYPT_CFG_OUTFLUSH); +} + + +/*================ INTERRUPT HANDELING ==================*/ + +/* native PIO-mode (non-DMA) interrupt handler */ +void Crypto_Int_Handler(void) +{ + ISR_PROLOG(); + + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + uint32_t status = hDevice->pDev->STAT; + uint32_t event; + + /* clear status */ + hDevice->pDev->STAT = status; + + /* check for overflow */ + if (IS_ANY_BIT_SET(status, BITM_CRYPT_STAT_INOVR)) { + + /* call user's callback */ + if (0u != hDevice->pfCallback) { + hDevice->pfCallback(hDevice->pCBParam, ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, (void *)status); + } + + /* stop */ + StopCompute(hDevice); + + /* post the semaphore */ + SEM_POST(hDevice); + + return; + } + + /* pull outputs (updates completion flag) */ + readPioOutputData(hDevice, status); + + if (false == hDevice->bCompletion) { + + /* push more inputs, but not in SHA DMA mode (except for when its perfectly aligned block) */ + if ((pCompute->eCipherMode != ADI_CRYPTO_MODE_SHA) || (hDevice->bDmaEnabled == false) || (pCompute->numInputBytesRemaining == 0u)) + { + writePioInputData(hDevice, status); + } + + } else { + + /* we're done */ + + /* dispatch to user callback if we have one */ + if (0u != hDevice->pfCallback) { + + /* check for overflow first */ + if (0u != (BITM_CRYPT_STAT_INOVR & status)) { + event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW; + } else { + /* completion message depends on mode */ + switch (hDevice->Computation.eCipherMode) { +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CBC: event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + case ADI_CRYPTO_MODE_CCM: event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + case ADI_CRYPTO_MODE_CTR: event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) + case ADI_CRYPTO_MODE_ECB: event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + case ADI_CRYPTO_MODE_SHA: event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE; break; +#endif + default: event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN; break; + } + } + + /* call user's callback and give back buffer pointer */ + hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer); + + /* clear private copy of user buffer pointer */ + /* (this is done in GetBuffer in non-Callback mode) */ + hDevice->pUserBuffer = NULL; + } + + /* disable interrupts */ + hDevice->pDev->INTEN = 0u; + + /* post the semaphore */ + SEM_POST(hDevice); + } + + ISR_EPILOG(); +} + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* native DMA input interrupt handler */ +void DMA_AES0_IN_Int_Handler (void) +{ + ISR_PROLOG(); + + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + CRYPTO_COMPUTE *pCompute = &hDevice->Computation; + +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + if (ADI_CRYPTO_MODE_SHA == pCompute->eCipherMode) { + + /* Update the compute structure to reflect the "post DMA" state of the transaction */ + uint32_t numTotalBytes = pCompute->numInputBytesRemaining; + uint32_t num32BitWords = (numTotalBytes - (numTotalBytes % sizeof(uint32_t))) / sizeof(uint32_t) - 1u; + pCompute->numInputBytesRemaining -= num32BitWords*4u; + pCompute->numShaBitsRemaining -= num32BitWords*32u; + pCompute->pNextInput += num32BitWords; + + if ((numTotalBytes % SHA_CHUNK_MAX_BYTES) == 0u) + { + /* For perfect block sizes, need to write the last word WITHOUT triggering SHA_LAST_WORD */ + hDevice->pDev->INBUF = *pCompute->pNextInput; + + pCompute->numInputBytesRemaining = 0u; + pCompute->numShaBitsRemaining = 0u; + } + else + { + /* Go ahead and write the remaining word, and its okay to trigger SHA_LAST_WORD */ + writePioInputData(hDevice, hDevice->pDev->STAT); + } + } +#endif + + /* defer post to output interrupt... */ + + ISR_EPILOG(); +} +#endif + + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +/* native DMA output interrupt handler */ +void DMA_AES0_OUT_Int_Handler (void) +{ + ISR_PROLOG(); + ADI_CRYPTO_HANDLE hDevice = CryptoDevInfo[0].hDevice; + uint32_t status = hDevice->pDev->STAT; + uint32_t event; + + /* by the time we get here, everything should be complete */ + + /* dispatch to user callback if we have one */ + if (0u != hDevice->pfCallback) { + + /* check for overflow first */ + if (0u != (BITM_CRYPT_STAT_INOVR & status)) { + event = ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW; + } else { + /* completion message depends on mode */ + switch (hDevice->Computation.eCipherMode) { +#if (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CBC: event = ADI_CRYPTO_EVENT_STATUS_CBC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) + case ADI_CRYPTO_MODE_CCM: event = ADI_CRYPTO_EVENT_STATUS_CCM_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_CMAC: event = ADI_CRYPTO_EVENT_STATUS_CMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) + case ADI_CRYPTO_MODE_CTR: event = ADI_CRYPTO_EVENT_STATUS_CTR_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) + case ADI_CRYPTO_MODE_ECB: event = ADI_CRYPTO_EVENT_STATUS_ECB_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_HMAC_SUPPORT == 1) + case ADI_CRYPTO_MODE_HMAC: event = ADI_CRYPTO_EVENT_STATUS_HMAC_DONE; break; +#endif +#if (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) + case ADI_CRYPTO_MODE_SHA: event = ADI_CRYPTO_EVENT_STATUS_SHA_DONE; break; +#endif + default: event = ADI_CRYPTO_EVENT_STATUS_UNKNOWN; break; + } + } + + /* call user's callback and give back buffer pointer */ + hDevice->pfCallback(hDevice->pCBParam, event, (void*)hDevice->pUserBuffer); + + /* clear private copy of user buffer pointer */ + /* this is done in GetBuffer in non-Callback mode */ + hDevice->pUserBuffer = NULL; + } + + /* mark completion */ + hDevice->bCompletion = true; + + /* clear status */ + hDevice->pDev->STAT = status; + + /* post the semaphore */ + SEM_POST(hDevice); + + ISR_EPILOG(); +} +#endif + +/*! \endcond */ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h new file mode 100755 index 00000000000..b9e82e14b36 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/crypto/adi_crypto_def.h @@ -0,0 +1,209 @@ +/*! + ***************************************************************************** + @file: adi_crypto_def.h + @brief: Crypto Device Driver definitions for ADuCM4x50 processor + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_CRYPTO_DEF_H +#define ADI_CRYPTO_DEF_H + +/*! \cond PRIVATE */ + +#include +#include + +/* pick up compiler-specific alignment directives */ +#include +#define ALIGN4 ALIGNED_PRAGMA(4) + +/* Support Check MACROS */ +#define CRYPTO_SUPPORT_KEY_REQUIRED ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_CCM_ONLY ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CTR_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CBC_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + && (ADI_CRYPTO_ENABLE_CMAC_SUPPORT != 1) \ + && (ADI_CRYPTO_ENABLE_SHA_SUPPORT != 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_ANY_NON_CCM ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_SHA_SUPPORT == 1) \ + ) + +#define CRYPTO_SUPPORT_MODE_ANY_NON_SHA ( \ + (ADI_CRYPTO_ENABLE_ECB_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CTR_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CBC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CMAC_SUPPORT == 1) \ + || (ADI_CRYPTO_ENABLE_CCM_SUPPORT == 1) \ + ) + +/* define local MIN/MAX macros, if not already... */ +#ifndef MIN +#define MIN(a,b) (((a)<(b))?(a):(b)) +#endif +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* various size macros */ +#define MAX_CRYPTO_DMA_BYTES (DMA_TRANSFER_LIMIT * sizeof(uint32_t)) + +/* SHA hardware max chunk size attributes */ +#define SHA_CHUNK_MAX_BYTES (64u) +#define SHA_CHUNK_MAX_BITS (SHA_CHUNK_MAX_BYTES * 8U) +#define SHA_CHUNK_MAX_WORDS (16u) + +#define FIFO_WIDTH_IN_BITS (32u) +#define FIFO_WIDTH_IN_BYTES (FIFO_WIDTH_IN_BITS/8u) +#define FIFO_DEPTH (4u) + +#define CRYPTO_INPUT_SIZE_IN_BITS (128u) +#define CRYPTO_INPUT_SIZE_IN_BYTES (CRYPTO_INPUT_SIZE_IN_BITS/8u) + +#define SHA_OUTPUT_SIZE_IN_BITS (256u) +#define SHA_OUTPUT_SIZE_IN_BYTES (SHA_OUTPUT_SIZE_IN_BITS/8u) + + +/* MAKE SURE THIS STRUCT REMAINS *******PERFECTLY ALIGNED******* WITH USER + ADI_CRYPTO_TRANSACTION BECAUSE WE USE BCOPY TO INITIALIZE EACH NEW SUBMIT! + + Internal compute structure reflecting mostly, user ADI_CRYPTO_TRANSACTION, + except for moving data pointers and remaining counts. Contents initialized + directly from from ADI_CRYPTO_TRANSACTION during buffer submit. +*/ +typedef struct _CRYPTO_COMPUTE { + ADI_CRYPTO_CIPHER_MODE eCipherMode; /*!< Cipher mode to use */ + ADI_CRYPTO_CODING_MODE eCodingMode; /*!< Coding Mode (Encryption or Decryption) */ + + ADI_CRYPTO_KEY_BYTE_SWAP eKeyByteSwap; /*!< KEY endianness */ + ADI_CRYPTO_SHA_BYTE_SWAP eShaByteSwap; /*!< SHA endianness */ + ADI_CRYPTO_AES_BYTE_SWAP eAesByteSwap; /*!< AES endianness */ + + uint8_t *pKey; /*!< Pointer to the key data pre-formatted as a byte array, according to eAesKeyLen. */ + ADI_CRYPTO_AES_KEY_LEN eAesKeyLen; /*!< The length of the key */ + + uint32_t *pNextAuthInput; /* CCM mode: pointer to user prefix buffer */ + uint32_t numAuthBytesRemaining; /* Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */ + + uint32_t *pNextInput; /* Pointer to next user 32-bit input location */ + uint32_t numInputBytesRemaining; /* Number of input bytes remaining */ + + uint32_t *pNextOutput; /* Pointer to next user 32-bit output location */ + uint32_t numOutputBytesRemaining; /* Number of output bytes remaining */ + + uint8_t *pNonceIV; /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode: + CTR mode = 108-bit NONCE + CCM mode = 112-bit NONCE + CBC mode = 128-bit IV (Initialization Vector) + NONCE and IV assume little endian format, for example: CTR NONCE packing is: + NONCE[0] -> 7:0 + NONCE[1] -> 15:8 + ... + NONCE[13] -> 103:96 + NONCE[14](Bits 3:0) -> 107:104 */ + uint32_t CounterInit; /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */ + uint32_t numValidBytes; /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */ + uint32_t numShaBitsRemaining; /*!< SHA mode: Number of bits remaining in the SHA payload, which may be odd-sized */ +} CRYPTO_COMPUTE; + + +/* Crypto device attributes */ +typedef struct _CRYPTO_INFO { + ADI_CRYPT_TypeDef *pDev; /* Pointer to physical Crypto controller */ + ADI_CRYPTO_HANDLE hDevice; /* Device Handle */ +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) + IRQn_Type dmaInputIrqNum; + IRQn_Type dmaOutputIrqNum; + DMA_CHANn_TypeDef dmaInputChanNum; + DMA_CHANn_TypeDef dmaOutputChanNum; + volatile ADI_CRYPTO_RESULT dmaError; /* DMA error collector. */ +#endif +} CRYPTO_INFO; + + +#ifdef __ICCARM__ +/* +* Pm123 (RULE 8.5) there shall be no definition of objects or functions in a header file. +* Exception is to allow the Crypto device data type and instance to be declared simultaniously. +*/ +#pragma diag_suppress=Pm123 +#endif /* __ICCARM__ */ + +/* Crypto driver internal data */ +struct __ADI_CRYPTO_DEV_DATA_TYPE { + bool bDeviceEnabled; /* Boolean flag to signify whether the device is enable/disabled */ + bool bDmaEnabled; /* Boolean flag to signify whether the DMA is enable/disabled */ + bool bCompletion; /* Boolean flag to signify whether a transaction is complete */ + + ADI_CRYPT_TypeDef *pDev; /* Pointer to physical Crypto controller */ + + CRYPTO_INFO *pDevInfo; /* access to device info */ + + CRYPTO_COMPUTE Computation; /* Active computation structure */ + + ADI_CRYPTO_TRANSACTION *pUserBuffer; /* saved user buffer pointer from submit */ + ADI_CALLBACK pfCallback; /* User defined callback function */ + void *pCBParam; /* User defined callback param */ + ADI_CRYPTO_RESULT dmaErrorCode; /* saved DMA error code to return via user API */ + + + SEM_VAR_DECLR /* Blocking object abstraction: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos, etc. */ +} ADI_CRYPTO_DEV_DATA_TYPE; + +#ifdef __ICCARM__ +#pragma diag_default=Pm123 +#endif /* __ICCARM__ */ + +/*! \endcond */ + +#endif /* ADI_CRYPTO_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c new file mode 100755 index 00000000000..7ced9f04492 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/dma/adi_dma.c @@ -0,0 +1,346 @@ +/*! ***************************************************************************** + * @file: adi_dma.c + * @brief: DMA manager global file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + + +/*! \addtogroup DMA_Driver DMA Driver + * uDMA Device Driver. + * @{ + */ + +/*============= I N C L U D E S =============*/ +#include +#include +#include +#include +#include + +/*! \cond PRIVATE */ + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): he basic types of char, int, short, long, float, and double should not be used +* Need to use bool. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm011,Pm140 +#endif /* __ICCARM__ */ + +/*============= D E F I N E S =============*/ + +/* CCD array allocation macros */ +#define CCD_ALIGN (0x400) /* Memory alignment required for CCD array */ +#define CCD_SIZE (32u) /* Configure CCD allocation as an integral power of two, + i.e., 24 channels is allocated as 32 */ + +/*============= R E G I S T E R D E F I N E S =============*/ + + + + +/*============= T Y P E D E F I N E S =============*/ + +/*! DMA Channel callback information structure */ +typedef struct _DMA_CHANNEL { + ADI_CALLBACK pfCallback; /*!< Pointer to the callback func */ + void* pCBParam; /*!< Application Callback param */ +} DMA_CHANNEL_CALLBACK_INFO; + +/*! \struct ADI_DMA_DEV_DATA + * DMA Device instance data structure + * + * CallbackInfo[NUM_DMA_CHANNELSn] + * The semantics of indexes used to access CallbackInfo elements is defined by the semantics + * of the bits in registers DMA_ERRCHNL_CLR and DMA_INVALIDDESC_CLR. The position of these + * bits define the channel nodes of the peripheral they map to, e.g. bit N maps to channel + * node N. + */ +typedef struct { + bool Initialized; /*!< track initialization state. See function adi_dma_Init) */ + DMA_CHANNEL_CALLBACK_INFO CallbackInfo[NUM_DMA_CHANNELSn]; + uint32_t ChannelsInUse; /*!< bits 0 to 26 record active channels */ +} ADI_DMA_DEV_DATA; + + +/*============= D A T A =============*/ + +/* DMA descriptor arrays must be contiguous */ +/* AND impose strict alignment requirements */ +/* Each compiler has different alignment directives */ + +/* ALIGNED: DMA channel control data array declaration */ +ADI_ALIGNED_PRAGMA(CCD_ALIGN) +static ADI_DCC_TypeDef gChannelControlDataArray[CCD_SIZE * 2u] ADI_ALIGNED_ATTRIBUTE(CCD_ALIGN) + +#ifdef ADI_DMA_DESCRIPTORS_IN_VOLATILE_MEMORY + /* conditional placement of DMA descriptor table to volatile memory */ + @ "volatile_ram"; +#else + /* default placement to non-volatile memory (no override) */ + ; +#endif + + +/* pointer to the primary CCD array */ +ADI_DCC_TypeDef* const pPrimaryCCD = &gChannelControlDataArray[0]; + +/* pointer to the alternate CCD array */ +ADI_DCC_TypeDef* const pAlternateCCD = &gChannelControlDataArray[CCD_SIZE]; + + +/*! DMA Device Driver Data instance + * 32 Channel Handles initialized to {0, 0}, i.e. call-back function pointer + * set to NULL and call-back function parameters set to NULL + */ +static ADI_DMA_DEV_DATA DMA_DevData = { + + false, /*!< DMA device data not initialized. (See adi_dma_Init) */ + {{0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, {0,0}, + {0,0}, {0,0}, {0,0}}, + 0ul /*!< channels-in-use bitfield */ +}; + +/*! pointer to the DMA Device Driver Data instance */ +static ADI_DMA_DEV_DATA* const pDMA_DevData = &DMA_DevData; + +/*============= Local function declarations =============*/ + +/*========== DMA HANDLERS ==========*/ + +/*! DMA Error Handler */ +void DMA_Err_Int_Handler(void); + +/*========== U T I L I T Y M A C R O S ==========*/ + +/*! \endcond*/ +/*============= A P I I M P L E M E N T A T I O N S =============*/ + +/*! + * @brief Initialize the DMA peripheral + * + * @return none + * + * The application must call this API once + * + */ +void adi_dma_Init(void) +{ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + + if( false == pDMA_DevData->Initialized ) + { + pDMA_DevData->Initialized = true; + + /* Enable the DMA Controller */ + pADI_DMA0->CFG |= BITM_DMA_CFG_MEN; + + /* Set descriptor memory base pointer on DMA controller */ + pADI_DMA0->PDBPTR = (uint32_t)pPrimaryCCD; + + /* Enable the DMA Error Interrupt */ + NVIC_EnableIRQ(DMA_CHAN_ERR_IRQn); + + /* Reset per-channel, bitmapped control registers (W1C) */ + const uint32_t w1r_value = (uint32_t) ((1 << NUM_DMA_CHANNELSn) - 1); + pADI_DMA0->RMSK_SET = w1r_value; + pADI_DMA0->EN_CLR = w1r_value; + pADI_DMA0->ALT_CLR = w1r_value; + pADI_DMA0->PRI_CLR = w1r_value; + pADI_DMA0->ERRCHNL_CLR = w1r_value; + pADI_DMA0->ERR_CLR = w1r_value; + pADI_DMA0->INVALIDDESC_CLR = w1r_value; + } + + ADI_EXIT_CRITICAL_REGION(); +} + +/** + * @brief Register a call-back function for a DMA channel. + * + * @param [in] eChannelID The ID of the DMA channel being assigned a call-back function. + * @param [in] pfCallback Pointer to the application callback function. + * @param [in] pCBParam Application callback parameter. + * + * @details The function registers a call-back function for the DMA channel node + * identified by eChannelID and stores the extra parameters this call-back function + * may require. A NULL callback function pointer means "DMA channel unused". + * + * @return Status + * - #ADI_DMA_SUCCESS Successfully registered a call-back function for the given DMA channel node. + * - #ADI_DMA_ERR_NOT_INITIALIZED [D] adi_dma_Init must be called prior registering a call-back function. + * - #ADI_DMA_ERR_INVALID_PARAMETER [D] Some parameter(s) passed to the function is invalid. + */ +ADI_DMA_RESULT adi_dma_RegisterCallback ( + DMA_CHANn_TypeDef const eChannelID, + ADI_CALLBACK const pfCallback, + void* const pCBParam + ) +{ + ADI_DMA_RESULT result = ADI_DMA_SUCCESS; + +#ifdef ADI_DEBUG + /* DMA must be initialized first */ + if (false == pDMA_DevData->Initialized) { + result = ADI_DMA_ERR_NOT_INITIALIZED; + }else{ + const size_t numChannelId = sizeof(pDMA_DevData->CallbackInfo) / sizeof(DMA_CHANNEL_CALLBACK_INFO); + if (numChannelId <= eChannelID) /*!< pDMA_DevData->CallbackInfo definition is invalid */ + { + result = ADI_DMA_ERR_INVALID_PARAMETER; + } + } + if (ADI_DMA_SUCCESS == result) /* if no errors previously detected */ +#endif + { + /* eChannelID cannot be out of range by definition (we use DMA_CHANn_TypeDef) */ + DMA_CHANNEL_CALLBACK_INFO * pChannel = &pDMA_DevData->CallbackInfo[eChannelID]; + + /* Set the callback parameters */ + pChannel->pfCallback = pfCallback; /* assign the pointer to a callback function */ + pChannel->pCBParam = pCBParam; /* store the parameters to be used with the callback function */ + + const uint32_t nChannelBit = (1u << eChannelID); + if (NULL != pfCallback) { + pDMA_DevData->ChannelsInUse |= nChannelBit; /* set the bit to mark the channel as "being used" */ + }else{ + pDMA_DevData->ChannelsInUse &= (~nChannelBit); /* clear the bit to mark the channel as "not being used" */ + } + } + return result; +} + +/*! \cond PRIVATE */ + + +#if defined(__ICCARM__) + +/* ARM Cortex-M3/M4, IAR compiler (CMSIS standard) */ +#define ADI_CLZ(X) __CLZ(X) + +#elif defined(__GNUC__) + +/* ARM Cortex-M3/M4, GNU-ARM compiler */ +#define ADI_CLZ(X) __builtin_clz(X) + +#elif defined(__CC_ARM) + +/* ARM Cortex-M3/M4, Keil compiler */ +#define ADI_CLZ(X) __clz(X) + +#else + +#error "Macro ADI_CLZ undefined!!!" + +#endif + +/*! DMA Error Handler + * + * The DMA Error handler looks at the channels in use which are flagged in register ERRCHNL_CLR + * or INVALIDDESC_CLR and calls the associated call-back functions, if defined. If a call-back + * function is undefined (NULL pointer) then it means the associated driver ignores these errors. + * + * Then, all the bits set in ERRCHNL_CLR and INVALIDDESC_CLR at the time the handler is called + * are cleared. + */ +void DMA_Err_Int_Handler(void) +{ + ISR_PROLOG() + + const uint32_t nErrClr = pADI_DMA0->ERR_CLR; /* get all the bits set in ERR_CLR */ + const uint32_t nErrChnClr = pADI_DMA0->ERRCHNL_CLR; /* get all the bits set in ERRCHNL_CLR */ + const uint32_t nInvdDescClr = pADI_DMA0->INVALIDDESC_CLR; /* get all the bits set in INVALIDDESC_CLR */ + + /* if there are invalid channel descriptors or channel errors amongts the channels in use */ + uint32_t functionsToBeCalled = pDMA_DevData->ChannelsInUse & (nErrChnClr | nInvdDescClr); + + if (functionsToBeCalled > 0u) + { + const uint32_t numBits = sizeof(uint32_t) << 3; /* maximum number of bits to be considered */ + uint32_t nlz; /* number of leading zeroes in functionsToBeCalled */ + + /* For all the bits set in functionsToBeCalled, starting from the MSB */ + for (nlz = (uint32_t) ADI_CLZ(functionsToBeCalled); nlz < numBits; nlz = (uint32_t) ADI_CLZ(functionsToBeCalled)) + { + const uint32_t bitSet = numBits - nlz - 1u; /* bit position in functionsToBeCalled */ + const uint32_t selected_bit = ((uint32_t)1u << bitSet); + DMA_CHANNEL_CALLBACK_INFO* pChannel = &pDMA_DevData->CallbackInfo[bitSet]; + + /* if there's a callback function to be called */ + if (NULL != pChannel->pfCallback) + { + /* define the nature of the error: DMA bus error or else invalid descriptor */ + uint32_t nEvent = ((nErrChnClr & selected_bit) != 0u) + ? (uint32_t)ADI_DMA_EVENT_ERR_BUS + : (uint32_t)ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR; + + /* report the error to the peripheral through the callback function */ + pChannel->pfCallback (pChannel->pCBParam, nEvent, NULL ); + } + + functionsToBeCalled &= ~selected_bit; /* clear bit in functionsToBeCalled */ + } + } + + /* Clear the errors processed in the loop above */ + pADI_DMA0->ERRCHNL_CLR = nErrChnClr; /* W1C: clear only all the bits set in nErrChnClr */ + pADI_DMA0->INVALIDDESC_CLR = nInvdDescClr; /* W1C: clear only all the bits set in nInvdDescClr */ + pADI_DMA0->ERR_CLR = nErrClr; /* W1C: clear only all the bits set in nErrClr */ + + ISR_EPILOG() +} + +/*! \endcond*/ + +/**@}*/ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h new file mode 100755 index 00000000000..1794f4ab2c4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/adc/adi_adc.h @@ -0,0 +1,346 @@ +/*! ***************************************************************************** + * @file adi_adc.h + * @brief Main include file for ADC Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_ADC_H +#define ADI_ADC_H + +#include +#include +#include +#include /* for ADI_SEM_SIZE */ + +/** @addtogroup ADC_Driver ADC Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/*! Amount of memory(In bytes) required by the ADC device driver for managing the operation + * of a ADC controller. The memory is passed to the driver when the driver is opended. + * The memory is completely owned by the driver till the the driver is closed. + * + */ +#define ADI_ADC_MEMORY_SIZE (48u + ADI_SEM_SIZE) /*!< Memory Size of the buffer required by the ADC driver */ + + +/*! + * \enum ADI_ADC_RESULT + * ADC API return codes + */ +typedef enum { + ADI_ADC_SUCCESS = 0, /*!< No Error, API suceeded */ + ADI_ADC_INVALID_DEVICE_NUM, /*!< Invalid device number passed */ + ADI_ADC_INVALID_DEVICE_HANDLE, /*!< Invalid device handle passed */ + ADI_ADC_INVALID_STATE, /*!< Invalid State */ + ADI_ADC_INSUFFICIENT_MEMORY, /*!< Insufficient memory passed to the driver */ + ADI_ADC_IN_USE, /*!< ADC is alreaady in use */ + ADI_ADC_INVALID_PARAMETER, /*!< Invalid parameter passed to the driver */ + ADI_ADC_NULL_POINTER, /*!< Null pointer passed when expecting a valid pointer */ + ADI_ADC_FAILURE, /*!< General ADC Failure */ + ADI_ADC_INVALID_SEQUENCE, /*!< Invalid sequence of API calls */ + ADI_ADC_ERR_RTOS, /*!< RTOS error occurred */ + ADI_ADC_INVALID_OPERATION, /*!< API call is an invalid operation */ + ADI_ADC_INVALID_BUFFER, /*!< Buffer passed to the application is invalid */ + ADI_ADC_BUFFER_OVERFLOW, /*!< Buffer overflow occurred */ + ADI_ADC_DMA_ERROR, /*!< DMA Error occurred */ + ADI_ADC_BAD_SYS_CLOCK, /*!< Could not retrieve core clock value. */ +} ADI_ADC_RESULT; + +/*! + * \enum ADI_ADC_VREF_SRC + * Voltage Reference source selection. + */ +typedef enum { + ADI_ADC_VREF_SRC_INT_1_25_V, /*!< 1.25V Internal Voltage Reference */ + ADI_ADC_VREF_SRC_INT_2_50_V, /*!< 2.50V Internal Voltage Reference */ + ADI_ADC_VREF_SRC_EXT, /*!< External Voltage Reference */ + ADI_ADC_VREF_SRC_VBAT, /*!< Battery Voltage as Voltage Reference source */ +} ADI_ADC_VREF_SRC; + +/*! + * \enum ADI_ADC_RESOLUTION + * Resolution of the ADC. + */ +typedef enum { + ADI_ADC_RESOLUTION_12_BIT, /*!< 12-bit ADC Resolution */ + ADI_ADC_RESOLUTION_13_BIT, /*!< 13-bit ADC Resolution */ + ADI_ADC_RESOLUTION_14_BIT, /*!< 14-bit ADC Resolution */ + ADI_ADC_RESOLUTION_15_BIT, /*!< 15-bit ADC Resolution */ + ADI_ADC_RESOLUTION_16_BIT /*!< 16-bit ADC Resolution */ +} ADI_ADC_RESOLUTION; + +/*! + * \typedef ADI_ADC_CHANNEL + * Typedef for ADC Channels + */ +typedef uint32_t ADI_ADC_CHANNEL; + +/*! + * defines for ADC Channels + */ +#define ADI_ADC_CHANNEL_0 (1u << 0u) /*!< ADC Channel 0 */ +#define ADI_ADC_CHANNEL_1 (1u << 1u) /*!< ADC Channel 1 */ +#define ADI_ADC_CHANNEL_2 (1u << 2u) /*!< ADC Channel 2 */ +#define ADI_ADC_CHANNEL_3 (1u << 3u) /*!< ADC Channel 3 */ +#define ADI_ADC_CHANNEL_4 (1u << 4u) /*!< ADC Channel 4 */ +#define ADI_ADC_CHANNEL_5 (1u << 5u) /*!< ADC Channel 5 */ +#define ADI_ADC_CHANNEL_6 (1u << 6u) /*!< ADC Channel 6 */ +#define ADI_ADC_CHANNEL_7 (1u << 7u) /*!< ADC Channel 7 */ + +/*! + * \enum ADI_ADC_EVENT + * Callback events from the ADC driver. + */ +typedef enum { + ADI_ADC_EVENT_CALIBRATION_DONE, /*!< Calibration done event. arg to the callback function will be NULL. */ + ADI_ADC_EVENT_ADC_READY, /*!< ADC Ready event. arg to the callback function will be null */ + ADI_ADC_EVENT_OVERFLOW, /*!< Overflow event occurred. The channel(#ADI_ADC_CHANNEL) for which the overflow occurred will be passed as arg to the callback function. */ + ADI_ADC_EVENT_HIGH_LIMIT_CROSSED, /*!< High Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */ + ADI_ADC_EVENT_LOW_LIMIT_CROSSED, /*!< Low Limit crossed event. The channel(#ADI_ADC_CHANNEL) for which the limit is crossed will be passed as arg to the callback function. */ +} ADI_ADC_EVENT; + +/*! Structure which hold the details of the buffer and sampling details */ +typedef struct __ADI_ADC_BUFFER { + uint32_t nChannels; /*!< Channels to sample. Should be an ORed value of #ADI_ADC_CHANNEL enum */ + void* pDataBuffer; /*!< Pointer to the Buffer to read the sample value into. If single channel(say Channel 0) is selected + then the format of buffer will be .... but if + multiple channels (say Channel 1 and Channel2) are selected then the format of buffer will be + .... + \n The pBuffer should be 2 byte aligned. + \n + \n If N is the number of channels selected then in single iteration mode the number of samples + written to in the buffer will be N and for multiple iteration, the driver will try to fill the whole + buffer with data and it is preferred that the nBuffSize be able to accommodate a multiple of N samples. + */ + uint32_t nNumConversionPasses; /*!< Num of conversion passes */ + uint32_t nBuffSize; /*!< Size of the buffer supplied */ +} ADI_ADC_BUFFER; + +/* Type def for the ADC Handle. */ +typedef struct __ADI_ADC_DEVICE* ADI_ADC_HANDLE; /*!< ADC Device Handler */ + + +/*============= A P I F U N C T I O N S P R O T O T Y P E S =============*/ + +/* Opens an ADC device instance. */ +ADI_ADC_RESULT adi_adc_Open ( + uint32_t nDeviceNum, + void* pMemory, + uint32_t nMemorySize, + ADI_ADC_HANDLE* phDevice +); + +/* Close the given device instance */ +ADI_ADC_RESULT adi_adc_Close(ADI_ADC_HANDLE hDevice); + +/* Power up or power down the ADC */ +ADI_ADC_RESULT adi_adc_PowerUp (ADI_ADC_HANDLE hDevice, bool bPowerUp); + +/* Register the callback */ +ADI_ADC_RESULT adi_adc_RegisterCallback( + ADI_ADC_HANDLE hDevice, + ADI_CALLBACK pfCallback, + void *pCBParam +); + +/* Enables/Disables the ADC Subsystem */ + ADI_ADC_RESULT adi_adc_EnableADCSubSystem ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Returns whether the ADC subsytem is ready */ +ADI_ADC_RESULT adi_adc_IsReady ( + ADI_ADC_HANDLE hDevice, + bool *pbReady +); + +/* Set the voltage reference source */ +ADI_ADC_RESULT adi_adc_SetVrefSource ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_VREF_SRC eVrefSrc +); + +/* Enable/Disable current sink */ +ADI_ADC_RESULT adi_adc_SinkEnable ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Start the ADC Calibration */ +ADI_ADC_RESULT adi_adc_StartCalibration ( + ADI_ADC_HANDLE hDevice +); + + ADI_ADC_RESULT adi_adc_IsCalibrationDone ( + ADI_ADC_HANDLE hDevice, + bool* pbCalibrationDone + ); + + +/* Set the acquisition time of ADC in ADC clock cycles */ +ADI_ADC_RESULT adi_adc_SetAcquisitionTime( + ADI_ADC_HANDLE hDevice, + uint32_t nAcqTimeInAClkCycles +); + +/* Set the delay time of ADC in ADC cycles for multi iteration mode */ +ADI_ADC_RESULT adi_adc_SetDelayTime( + ADI_ADC_HANDLE hDevice, + uint32_t nDelayInAClkCycles +); + +/* set the resolution of ADC. The default resolution of ADC is 12-bit and the ADC increases the resolution by oversampling */ +ADI_ADC_RESULT adi_adc_SetResolution ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_RESOLUTION eResolution +); + +/* Enable Averaging for all ADC channels */ +ADI_ADC_RESULT adi_adc_EnableAveraging ( + ADI_ADC_HANDLE hDevice, + uint16_t nAveragingSamples +); + +/* Configure low limit for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetLowLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nLowLimit +); + +/* Configure high limit for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetHighLimit ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHighLimit +); + + +/* Configure hysteresis for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetHysteresis( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + bool bEnable, + uint16_t nHysteresis +); + +/* Configure number of monitor cycles for an ADC channel when it's used as a digital comparator. */ +ADI_ADC_RESULT adi_adc_SetNumMonitorCycles( + ADI_ADC_HANDLE hDevice, + ADI_ADC_CHANNEL eChannel, + uint32_t nNumMonitorCycles +); + +/* Enable/Disable digital comparator for the given channel(s) */ +ADI_ADC_RESULT adi_adc_EnableDigitalComparator ( + ADI_ADC_HANDLE hDevice, + bool bEnableComparator +); + +/* Submit buffer for sampling */ +ADI_ADC_RESULT adi_adc_SubmitBuffer ( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER* pBuffer +); + +/* Get a completed buffer from the driver */ +ADI_ADC_RESULT adi_adc_GetBuffer( + ADI_ADC_HANDLE hDevice, + ADI_ADC_BUFFER** ppBuffer +); + +/* Enable/Disable buffer processing */ +ADI_ADC_RESULT adi_adc_Enable ( + ADI_ADC_HANDLE hDevice, + bool bEnable +); + +/* Check whether a completed buffer is available in the driver */ +ADI_ADC_RESULT adi_adc_IsBufferAvailable( + ADI_ADC_HANDLE hDevice, + bool* pbIsBufferAvailable +); + +/* Read the given channels. This will only return once the given amount of samples are collected */ +ADI_ADC_RESULT adi_adc_ReadChannels ( + ADI_ADC_HANDLE hDevice, + uint32_t nChannels, + uint32_t nNumConversionPasses, + void* pBuffer, + uint32_t nBuffLength +); + +/* Get Battery Voltage */ +ADI_ADC_RESULT adi_adc_GetBatteryVoltage ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + uint32_t* pnBatVoltage +); + +/* Enable/Disable Temperature Sensor */ +ADI_ADC_RESULT adi_adc_EnableTemperatureSensor ( + ADI_ADC_HANDLE hDevice, + bool bEnable + ); + +/* Get the Temperature Value */ +ADI_ADC_RESULT adi_adc_GetTemperature ( + ADI_ADC_HANDLE hDevice, + uint32_t nRefVoltage, + int32_t* pnTemperature + ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + + +#endif /* ADI_ADC_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h new file mode 100755 index 00000000000..6fa441895ec --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/beep/adi_beep.h @@ -0,0 +1,277 @@ +/*! ***************************************************************************** + * @file adi_beep.h + * @brief Main include file for BEEP device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/** @addtogroup BEEP_Driver BEEP Driver +* @{ +*/ +#ifndef ADI_BEEP_H +#define ADI_BEEP_H + +#include "adi_processor.h" + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! Amount of memory(In bytes) required by the Beep device driver for managing the operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#if ADI_BEEP_INCLUDE_PLAY_SEQUENCE == 1 +/*! @hideinitializer Indicates the size of the BEEP memory to be used */ +#define ADI_BEEP_MEMORY_SIZE (20u + ADI_SEM_SIZE) +#else +/*! @hideinitializer Indicates the size of the BEEP memory to be used */ +#define ADI_BEEP_MEMORY_SIZE (12u + ADI_SEM_SIZE) +#endif + +/*! + * \enum ADI_BEEP_RESULT + * Beeper API return codes + */ +typedef enum +{ + ADI_BEEP_SUCCESS = 0, /*!< No Error, API suceeded */ + + ADI_BEEP_FAILURE, /*!< An unknown error was detected */ + ADI_BEEP_ALREADY_INITIALIZED, /*!< BEEP is already initialized */ + ADI_BEEP_BAD_DEV_HANDLE, /*!< Invalid device handle passed */ + ADI_BEEP_BAD_DEV_ID, /*!< Asking to initialize an unknown device num */ + ADI_BEEP_NOT_INITIALIZED, /*!< BEEP not yet initialized */ + ADI_BEEP_PARAM_OUT_OF_RANGE, /*!< Parameter is out of range. */ + ADI_BEEP_INVALID_COUNT, /*!< Invalid count for supplied beep sequence */ + ADI_BEEP_NULL_PTR, /*!< Null pointer supplied. */ + ADI_BEEP_SEMAPHORE_FAILED, /*!< BEEP semaphore failure. */ +} ADI_BEEP_RESULT; + + +/*! + * \enum ADI_BEEP_DEV_ID + * @brief Beeper Device IDs. + * @details List of all Beeper Device IDs for the current part + */ +typedef enum +{ + ADI_BEEP_DEVID_0 = 0, /*!< BEEP Timer Device 0 */ + ADI_BEEP_MAX_DEVID /*!< max number of BEEP devices */ +} ADI_BEEP_DEV_ID; + +/*! + * \enum ADI_BEEP_INTERRUPT + * @brief Beeper Interrupt Bits. + * @details List of all Beeper interrupt (enables and status) bits. + */ +typedef enum +{ + ADI_BEEP_INTERRUPT_SEQUENCE_END = BITM_BEEP_CFG_SEQATENDIRQ, /*!< Beeper sequence has finished */ + ADI_BEEP_INTERRUPT_NOTE_END = BITM_BEEP_CFG_AENDIRQ, /*!< Beeper note has finished */ +} ADI_BEEP_INTERRUPT; + + +#define LFCLK_FREQ 32768.0f /*!< Beeper main clock frequency. */ +#define FREQUENCY_ENCODE(x) (uint8_t)(LFCLK_FREQ/(x) + 0.5f) /*!< Beeper tone frequency encoder macro */ + +/*! + * \enum ADI_BEEP_NOTE_FREQUENCY + * @brief Beeper tone frequency list. + * @details List of possible Beeper tone frequencies. + */ +typedef enum { + /* Constants are pre-computed note frequencies (Hz). */ + /* See http://www.phy.mtu.edu/~suits/notefreqs.html. */ + /* Encodings are clock divider values for that note. */ + /* Flats are the same as the lower sharp, so only sharps are listed. */ + /* Even though octaves are simple frequency doublings/halvings */ + /* of adjuacient octaves, we pre-compute each constant (as opposed */ + /* to halving/doubling the encodings between octaves) to */ + /* minimize repeated doubling/halving errors across all octaves. */ + /* !!!ALL ENCODINGS MUST BE IN THE RANGE 4-127!!! */ + + ADI_BEEP_FREQ_REST = (0), /*!< silence */ + + ADI_BEEP_FREQ_C4 = FREQUENCY_ENCODE(261.63f), /*!< Middle C (lowest representable frequency @ 32KHz) */ + ADI_BEEP_FREQ_Cs4 = FREQUENCY_ENCODE(277.18f), + ADI_BEEP_FREQ_D4 = FREQUENCY_ENCODE(293.66f), + ADI_BEEP_FREQ_Ds4 = FREQUENCY_ENCODE(311.13f), + ADI_BEEP_FREQ_E4 = FREQUENCY_ENCODE(329.63f), + ADI_BEEP_FREQ_F4 = FREQUENCY_ENCODE(349.23f), + ADI_BEEP_FREQ_Fs4 = FREQUENCY_ENCODE(369.99f), + ADI_BEEP_FREQ_G4 = FREQUENCY_ENCODE(392.00f), + ADI_BEEP_FREQ_Gs4 = FREQUENCY_ENCODE(415.30f), + ADI_BEEP_FREQ_A4 = FREQUENCY_ENCODE(440.00f), + ADI_BEEP_FREQ_As4 = FREQUENCY_ENCODE(466.16f), + ADI_BEEP_FREQ_B4 = FREQUENCY_ENCODE(493.88f), + + ADI_BEEP_FREQ_C5 = FREQUENCY_ENCODE(523.25f), + ADI_BEEP_FREQ_Cs5 = FREQUENCY_ENCODE(554.37f), + ADI_BEEP_FREQ_D5 = FREQUENCY_ENCODE(587.33f), + ADI_BEEP_FREQ_Ds5 = FREQUENCY_ENCODE(622.25f), + ADI_BEEP_FREQ_E5 = FREQUENCY_ENCODE(659.26f), + ADI_BEEP_FREQ_F5 = FREQUENCY_ENCODE(698.46f), + ADI_BEEP_FREQ_Fs5 = FREQUENCY_ENCODE(739.99f), + ADI_BEEP_FREQ_G5 = FREQUENCY_ENCODE(783.99f), + ADI_BEEP_FREQ_Gs5 = FREQUENCY_ENCODE(830.61f), + ADI_BEEP_FREQ_A5 = FREQUENCY_ENCODE(880.00f), + ADI_BEEP_FREQ_As5 = FREQUENCY_ENCODE(932.33f), + ADI_BEEP_FREQ_B5 = FREQUENCY_ENCODE(987.77f), + + ADI_BEEP_FREQ_C6 = FREQUENCY_ENCODE(1046.50f), + ADI_BEEP_FREQ_Cs6 = FREQUENCY_ENCODE(1108.73f), + ADI_BEEP_FREQ_D6 = FREQUENCY_ENCODE(1174.66f), + ADI_BEEP_FREQ_Ds6 = FREQUENCY_ENCODE(1244.51f), + ADI_BEEP_FREQ_E6 = FREQUENCY_ENCODE(1318.51f), + ADI_BEEP_FREQ_F6 = FREQUENCY_ENCODE(1396.91f), + ADI_BEEP_FREQ_Fs6 = FREQUENCY_ENCODE(1479.98f), + ADI_BEEP_FREQ_G6 = FREQUENCY_ENCODE(1567.98f), + ADI_BEEP_FREQ_Gs6 = FREQUENCY_ENCODE(1661.22f), + ADI_BEEP_FREQ_A6 = FREQUENCY_ENCODE(1760.00f), + ADI_BEEP_FREQ_As6 = FREQUENCY_ENCODE(1864.66f), + ADI_BEEP_FREQ_B6 = FREQUENCY_ENCODE(1975.53f), + + ADI_BEEP_FREQ_C7 = FREQUENCY_ENCODE(2093.00f), + ADI_BEEP_FREQ_Cs7 = FREQUENCY_ENCODE(2217.46f), + ADI_BEEP_FREQ_D7 = FREQUENCY_ENCODE(2349.32f), + ADI_BEEP_FREQ_Ds7 = FREQUENCY_ENCODE(2489.02f), + ADI_BEEP_FREQ_E7 = FREQUENCY_ENCODE(2637.02f), + ADI_BEEP_FREQ_F7 = FREQUENCY_ENCODE(2793.83f), + ADI_BEEP_FREQ_Fs7 = FREQUENCY_ENCODE(2959.96f), + ADI_BEEP_FREQ_G7 = FREQUENCY_ENCODE(3135.96f), + ADI_BEEP_FREQ_Gs7 = FREQUENCY_ENCODE(3322.44f), + ADI_BEEP_FREQ_A7 = FREQUENCY_ENCODE(3520.00f), + ADI_BEEP_FREQ_As7 = FREQUENCY_ENCODE(3729.31f), + ADI_BEEP_FREQ_B7 = FREQUENCY_ENCODE(3951.07f), + + ADI_BEEP_FREQ_C8 = FREQUENCY_ENCODE(4186.01f), + ADI_BEEP_FREQ_Cs8 = FREQUENCY_ENCODE(4434.92f), + ADI_BEEP_FREQ_D8 = FREQUENCY_ENCODE(4698.64f), + ADI_BEEP_FREQ_Ds8 = FREQUENCY_ENCODE(4978.03f), + ADI_BEEP_FREQ_E8 = FREQUENCY_ENCODE(5274.04f), + ADI_BEEP_FREQ_F8 = FREQUENCY_ENCODE(5587.65f), + ADI_BEEP_FREQ_Fs8 = FREQUENCY_ENCODE(5919.91f), + ADI_BEEP_FREQ_G8 = FREQUENCY_ENCODE(6271.93f), +} ADI_BEEP_NOTE_FREQUENCY; + +#define ADI_BEEP_DUR_ZERO (0) /*!< Beeper zero tone duration value */ +#define ADI_BEEP_DUR_MIN (1) /*!< Beeper minimum tone duration value */ +#define ADI_BEEP_DUR_MAX (254) /*!< Beeper maximum tone duration value */ +#define ADI_BEEP_DUR_INFINITE (255) /*!< Beeper infinite tone duration value */ + +/*! A device handle used in all API functions to identify the BEEP device. */ +typedef void * ADI_BEEP_HANDLE; + +#define DURATION_ENCODE(x) (uint8_t)((float)ADI_BEEP_DUR_MAX/(float)(x) + 0.5f) /*!< Beeper tone duration encoder macro */ + +/*! + * \enum ADI_BEEP_NOTE_DURATION + * @brief Beeper tone duration list. + * @details List of possible Beeper tone durations. + */ +typedef enum { + ADI_BEEP_DUR_0 = ADI_BEEP_DUR_ZERO, /*!< stop */ + ADI_BEEP_DUR_32_32 = DURATION_ENCODE(1), /*!< whole note (1.016 seconds) */ + ADI_BEEP_DUR_16_32 = DURATION_ENCODE(2), /*!< half note */ + ADI_BEEP_DUR_12_32 = DURATION_ENCODE(8/3), /*!< three eights note */ + ADI_BEEP_DUR_8_32 = DURATION_ENCODE(4), /*!< one quarter note */ + ADI_BEEP_DUR_6_32 = DURATION_ENCODE(16/3), /*!< three sixteenth note */ + ADI_BEEP_DUR_4_32 = DURATION_ENCODE(8), /*!< one eighth note */ + ADI_BEEP_DUR_2_32 = DURATION_ENCODE(16), /*!< one sixteenth note */ + ADI_BEEP_DUR_1_32 = DURATION_ENCODE(32), /*!< one thirty-secondth note */ + ADI_BEEP_DUR_N = ADI_BEEP_DUR_INFINITE, /*!< continuous play */ +} ADI_BEEP_NOTE_DURATION; + +/*! + * \struct ADI_BEEP_NOTE + * @brief Beeper note structure. + * @details Describes a note in terms of frequency and duration. + */ +typedef struct { + ADI_BEEP_NOTE_FREQUENCY frequency; /*!< Frequency of the note */ + ADI_BEEP_NOTE_DURATION duration; /*!< Duration of the note */ +} ADI_BEEP_NOTE; + + +/*================ E X T E R N A L S ==================*/ + +/* + * Beeper API + */ + +ADI_BEEP_RESULT adi_beep_Open (ADI_BEEP_DEV_ID const DeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_BEEP_HANDLE* const phDevice); + +ADI_BEEP_RESULT adi_beep_RegisterCallback (ADI_BEEP_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void* const pCBParam); + +ADI_BEEP_RESULT adi_beep_PlayNote (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE note); + +ADI_BEEP_RESULT adi_beep_PlayTwoTone (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE noteA, + ADI_BEEP_NOTE noteB, + uint8_t count); + +ADI_BEEP_RESULT adi_beep_PlaySequence (ADI_BEEP_HANDLE const hDevice, + ADI_BEEP_NOTE aSequence[], + uint8_t count); + +ADI_BEEP_RESULT adi_beep_Enable (ADI_BEEP_HANDLE const hDevice, + bool const bFlag); + +ADI_BEEP_RESULT adi_beep_Wait (ADI_BEEP_HANDLE const hDevice); + +ADI_BEEP_RESULT adi_beep_Close (ADI_BEEP_HANDLE const hDevice); + +#ifdef __cplusplus +} +#endif + + +#endif /* ADI_BEEP_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h new file mode 100755 index 00000000000..9fddbc60858 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crc/adi_crc.h @@ -0,0 +1,236 @@ +/*! ***************************************************************************** + * @file adi_crc.h + * @brief CRC (Cyclic Redundancy Check) Device driver global include file + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_CRC_H +#define ADI_CRC_H + +/** @addtogroup CRC_Driver CRC Device Driver + * @{ + */ + +#include + +/*============= I N C L U D E S =============*/ +#include +/* Memory size check */ +#include + +/* DMA Manager includes */ +#include + +/* Include the config file for CRC */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/*============== D E F I N E S ===============*/ + +#if (ADI_CRC_CFG_ENABLE_DMA_SUPPORT == 0) + + +/** + * The size of types may vary between building tools (int, char, enumerator, etc.). + * This impacts the memory size required by a CRC driver. + * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent. + */ +#if defined(__ICCARM__) +/** + * The amount of application supplied memory required to operate a core driven CRC device + * using a CRC driver built in IAR environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#else +/** + * The amount of application supplied memory required to operate a core driven CRC device + * using a CRC driver built in a generic built environment. + * Note: Create a new macro definition for your targetted development environment + * if this generic value was not appropriate in your development environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#endif + + +#else /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + + +/** + * The size of types may vary between building tools (int, char, enumerator, etc.). + * This impacts the memory size required by a CRC driver. + * Consequently, ADI_CRC_MEMORY_SIZE is environment dependent. + */ +#if defined(__ICCARM__) +/** + * The amount of application supplied memory required to operate a DMA driven CRC device + * using a CRC driver built in IAR environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#else +/** + * The amount of application supplied memory required to operate a DMA driven CRC device + * using a CRC driver built in a generic built environment. + * Note: Create a new macro definition for your targetted development environment + * if this generic value was not appropriate in your development environment. + */ +#define ADI_CRC_MEMORY_SIZE (32u) +#endif + +/** Check that a DMA channel can be used with CRC */ +#define ADI_CRC_VALID_DMA_CHANNEL(DMA_CHANNEL_ID) ((SIP0_CHANn<=(DMA_CHANNEL_ID)) && ((DMA_CHANNEL_ID)<=SIP7_CHANn)) + +/** + * CRC events used in CRC callback functions to report + * - the completion of a DMA driven CRC request + * - errors detected when executing a DMA driven CRC request + */ +typedef enum __ADI_CRC_EVENT +{ + /*! DMA driven CRC peripheral has completed processing a request */ + ADI_CRC_EVENT_BUFFER_PROCESSED = ADI_DMA_EVENT_BUFFER_PROCESSED, + + /*! DMA driven CRC peripheral has encountered a problem when processing a request */ + ADI_CRC_EVENT_ERROR +} ADI_CRC_EVENT; + +#endif /* ADI_CRC_CFG_ENABLE_DMA_SUPPORT */ + +/** + * A device handle used in all API functions to identify a CRC device. + * This handle is obtained when opening a CRC driver using adi_crc_Open. + * It stops being valid after closing the CRC driver using adi_crc_Close. + */ +typedef struct __ADI_CRC_DEVICE* ADI_CRC_HANDLE; + +/** + * CRC driver return codes + */ +typedef enum +{ + ADI_CRC_SUCCESS = 0, /*!< 0x00 - Generic success */ + ADI_CRC_FAILURE, /*!< 0x01 - Generic failure */ + ADI_CRC_IN_USE, /*!< 0x02 - Supplied CRC device number is already open and in use */ + ADI_CRC_INSUFFICIENT_MEMORY, /*!< 0x03 - Supplied memory is insufficient to operate the CRC device */ + ADI_CRC_FN_NOT_SUPPORTED, /*!< 0x04 - Function not supported */ + ADI_CRC_FN_NOT_PERMITTED, /*!< 0x05 - Function not permitted at current stage */ + ADI_CRC_BAD_HANDLE, /*!< 0x06 - Bad CRC device handle (can be caused by a CRC device not opened)*/ + ADI_CRC_BAD_DEVICE_NUMBER, /*!< 0x07 - There is no CRC device identified by this number */ + ADI_CRC_INVALID_DMA_CHANNEL, /*!< 0x08 - Invalid DMA channel assigned to a CRC driver */ + ADI_CRC_INVALID_PARAMETER, /*!< 0x09 - Invalid parameter used in a CRC function */ +} ADI_CRC_RESULT; + +/*======= P U B L I C P R O T O T Y P E S ========*/ +/* (globally-scoped functions) */ + +/* Opens a CRC device instance */ +ADI_CRC_RESULT adi_crc_Open( + uint32_t DeviceNum, + void *pMemory, + uint32_t MemorySize, + ADI_CRC_HANDLE *phDevice); + +/* Closes a CRC device instance */ +ADI_CRC_RESULT adi_crc_Close( + ADI_CRC_HANDLE const hDevice); + +/* Registers or unregisters a callback, used by the CRC interrupt handler or with DMA driven operations, with the CRC device */ +ADI_CRC_RESULT adi_crc_RegisterCallback( + ADI_CRC_HANDLE const hDevice, + ADI_CALLBACK pfCallback, + void *const pCBParam); + +/* Sets the 32-bit polynomial for CRC operations */ +ADI_CRC_RESULT adi_crc_SetPolynomialVal( + ADI_CRC_HANDLE const hDevice, + uint32_t PolynomialVal); + +/* Submits data buffer for CRC operation */ +ADI_CRC_RESULT adi_crc_Compute( + ADI_CRC_HANDLE const hDevice, + void *pCrcBuf, + uint32_t NumBytes, + uint32_t NumBits); + +/* Gets the current CRC peripheral status */ +ADI_CRC_RESULT adi_crc_IsCrcInProgress( + ADI_CRC_HANDLE const hDevice, + bool *pbCrcInProgress); + +/* Gets the final CRC result computed for a data stream */ +ADI_CRC_RESULT adi_crc_GetFinalCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pFinalCrcVal); + +/* Gets the current/intermediate CRC result computed for a data stream */ +ADI_CRC_RESULT adi_crc_GetCurrentCrcVal( + ADI_CRC_HANDLE const hDevice, + uint32_t *pCurrentCrcVal); + +ADI_CRC_RESULT adi_crc_SetBitMirroring( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_SetByteMirroring( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_EnableWordSwap( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +ADI_CRC_RESULT adi_crc_SetCrcSeedVal( + ADI_CRC_HANDLE const hDevice, + uint32_t CrcSeedVal); + +ADI_CRC_RESULT adi_crc_SetLSBFirst( + ADI_CRC_HANDLE const hDevice, + const bool bEnable); + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* ADI_CRC_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h new file mode 100755 index 00000000000..54971c2217a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/crypto/adi_crypto.h @@ -0,0 +1,235 @@ +/*! ***************************************************************************** + * @file adi_crypto.h + * @brief Main include file for CRYPTO Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +/** @addtogroup Crypto_Driver Crypto Driver +* @{ +*/ + +#ifndef ADI_CRYPTO_H +#define ADI_CRYPTO_H + + /*! \cond PRIVATE */ +#include +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_CRYPTO_RESULT + * Crypto API return codes + */ +typedef enum +{ + ADI_CRYPTO_SUCCESS = 0, /*!< No Error, API suceeded. */ + ADI_CRYPTO_ERR_ALREADY_INITIALIZED, /*!< Crypto is already initialized. */ + ADI_CRYPTO_ERR_BAD_BUFFER, /*!< Invalid buffer parameters. */ + ADI_CRYPTO_ERR_BAD_CONFIG, /*!< Invalid device config parameters passed. */ + ADI_CRYPTO_ERR_BAD_DEVICE_NUM, /*!< Invalid device instance number. */ + ADI_CRYPTO_ERR_BAD_DEV_HANDLE, /*!< Invalid device handle passed. */ + ADI_CRYPTO_ERR_COMPUTE_ACTIVE, /*!< Computation underway. */ + ADI_CRYPTO_ERR_DMA_BUS_FAULT, /*!< Runtime DMA bus fault detected. */ + ADI_CRYPTO_ERR_DMA_INVALID_DESCR, /*!< Runtime DMA invalid descriptor detected. */ + ADI_CRYPTO_ERR_DMA_REGISTER, /*!< Error registering DMA error callback function. */ + ADI_CRYPTO_ERR_DMA_UNKNOWN_ERROR, /*!< Unknown runtime DMA error detected. */ + ADI_CRYPTO_ERR_INSUFFICIENT_MEM, /*!< Insufficient memory passed to the driver. */ + ADI_CRYPTO_ERR_INVALID_PARAM, /*!< Invalid function parameter. */ + ADI_CRYPTO_ERR_INVALID_STATE, /*!< Operation failed since the device is in an invalid state. */ + ADI_CRYPTO_ERR_SEMAPHORE_FAILED, /*!< Failure in semaphore functions. */ +} ADI_CRYPTO_RESULT; + +/*! + * \enum ADI_CRYPTO_EVENT + * Crypto callback events + */ +typedef enum +{ + /* successful buffer completion events */ + ADI_CRYPTO_EVENT_STATUS_CBC_DONE, /*!< CBC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CCM_DONE, /*!< CCM operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CMAC_DONE, /*!< CMAC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_CTR_DONE, /*!< CTR operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_ECB_DONE, /*!< ECB operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_HMAC_DONE, /*!< HMAC operation is complete. */ + ADI_CRYPTO_EVENT_STATUS_SHA_DONE, /*!< SHA operation is complete. */ + + /* other events */ + ADI_CRYPTO_EVENT_DMA_BUS_ERROR, /*!< DMA bus error encountered. */ + ADI_CRYPTO_EVENT_DMA_DESCRIPTOR_ERROR, /*!< DMA descriptor error encountered. */ + ADI_CRYPTO_EVENT_DMA_UNKNOWN_ERROR, /*!< DMA unknown error encountered. */ + ADI_CRYPTO_EVENT_STATUS_INPUT_OVERFLOW, /*!< Input overflow error encountered. */ + ADI_CRYPTO_EVENT_STATUS_UNKNOWN, /*!< Unknown error encountered. */ +} ADI_CRYPTO_EVENT; + +/*! The amount of application supplied memory used by the CRYPTO driver to store internal state. */ +#define ADI_CRYPTO_MEMORY_SIZE (88u + ADI_SEM_SIZE) + +/*! A device handle used in all API functions to identify the flash device. */ +typedef struct __ADI_CRYPTO_DEV_DATA_TYPE* ADI_CRYPTO_HANDLE; + +/*! Number of bytes to allocate for SHA256 hash outputs */ +#define ADI_CRYPTO_SHA_HASH_BYTES (256u/8u) + +/*! Computation mode(Encryption/Decryption) for given buffers */ +typedef enum +{ + ADI_CRYPTO_DECODE = (0u << BITP_CRYPT_CFG_ENCR), /*!< Encoding mode is decryption. */ + ADI_CRYPTO_ENCODE = (1u << BITP_CRYPT_CFG_ENCR), /*!< Encoding mode is encryption. */ +} ADI_CRYPTO_CODING_MODE; + +/*! Enum for the AES KEY Length */ +typedef enum +{ + ADI_CRYPTO_AES_KEY_LEN_128_BIT = (0u << BITP_CRYPT_CFG_AESKEYLEN), /*!< KEY length is 128 bits. */ + ADI_CRYPTO_AES_KEY_LEN_256_BIT = (2u << BITP_CRYPT_CFG_AESKEYLEN), /*!< KEY length is 256 bits. */ +} ADI_CRYPTO_AES_KEY_LEN; + +/*! Enable byte swapping for KEY writes */ +typedef enum +{ + ADI_CRYPTO_KEY_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_KEY_BYTESWAP), /*!< Do not apply KEY write byte swaps. */ + ADI_CRYPTO_KEY_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_KEY_BYTESWAP), /*!< Apply KEY write byte swaps. */ +} ADI_CRYPTO_KEY_BYTE_SWAP; + +/*! Byte-swap the SHA Input Data */ +typedef enum +{ + ADI_CRYPTO_SHA_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_SHA_BYTESWAP), /*!< Do not apply SHA data write byte swaps. */ + ADI_CRYPTO_SHA_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_SHA_BYTESWAP), /*!< Apply SHA data write byte swaps. */ +} ADI_CRYPTO_SHA_BYTE_SWAP; + +/*! Byte-swap the AES Input Data */ +typedef enum +{ + ADI_CRYPTO_AES_LITTLE_ENDIAN = (0u << BITP_CRYPT_CFG_AES_BYTESWAP), /*!< Do not apply AES data write byte swaps. */ + ADI_CRYPTO_AES_BIG_ENDIAN = (1u << BITP_CRYPT_CFG_AES_BYTESWAP), /*!< Apply AES data write byte swaps. */ +} ADI_CRYPTO_AES_BYTE_SWAP; + +/*! + * \enum ADI_CRYPTO_CIPHER_MODE + * Enum for the cipher modes. + */ +typedef enum { + ADI_CRYPTO_MODE_CBC = BITM_CRYPT_CFG_CBCEN, /*!< Select CBC cipher mode. */ + ADI_CRYPTO_MODE_CCM = BITM_CRYPT_CFG_CCMEN, /*!< Select CCM cipher mode. */ + ADI_CRYPTO_MODE_CMAC = BITM_CRYPT_CFG_CMACEN, /*!< Select CMAC cipher mode. */ + ADI_CRYPTO_MODE_CTR = BITM_CRYPT_CFG_CTREN, /*!< Select CTR cipher mode. */ + ADI_CRYPTO_MODE_ECB = BITM_CRYPT_CFG_ECBEN, /*!< Select ECB cipher mode. */ + ADI_CRYPTO_MODE_HMAC = BITM_CRYPT_CFG_HMACEN, /*!< Select HMAC cipher mode. */ + ADI_CRYPTO_MODE_SHA = BITM_CRYPT_CFG_SHA256EN, /*!< Select SHA cipher mode. */ +} ADI_CRYPTO_CIPHER_MODE; + +/*! superset user Crypto transaction structure (different elements used for different modes) */ +typedef struct +{ + ADI_CRYPTO_CIPHER_MODE eCipherMode; /*!< Cipher mode to use */ + ADI_CRYPTO_CODING_MODE eCodingMode; /*!< Coding Mode (Encryption or Decryption) */ + + ADI_CRYPTO_KEY_BYTE_SWAP eKeyByteSwap; /*!< KEY endianness */ + ADI_CRYPTO_SHA_BYTE_SWAP eShaByteSwap; /*!< SHA endianness */ + ADI_CRYPTO_AES_BYTE_SWAP eAesByteSwap; /*!< AES endianness */ + + uint8_t *pKey; /*!< Pointer to the KEY data: pre-formatted as a byte array, according to eAesKeyLen. */ + ADI_CRYPTO_AES_KEY_LEN eAesKeyLen; /*!< The length of the AES KEY */ + + uint32_t *pAuthData; /*!< CCM mode: pointer to user prefix buffer */ + uint32_t numAuthBytes; /*!< Length of the prefix buffer in bytes (should be a multiple of 16 bytes) */ + + uint32_t *pInputData; /*!< Pointer to user input data buffer */ + uint32_t numInputBytes; /*!< Length of the data buffer in bytes (should be a multiple of 16bytes) */ + + uint32_t *pOutputData; /*!< Pointer to user output buffer */ + uint32_t numOutputBytes; /*!< Length of the output buffer in bytes (should be a multiple of 16bytes) */ + + uint8_t *pNonceIV; /*!< Pointer to user 16-byte array containing one of three values, depending on cipher mode:\n + - CTR mode = 108-bit NONCE\n + - CCM mode = 112-bit NONCE\n + - CBC mode = 128-bit IV (Initialization Vector)\n\n + NONCE and IV assume little endian format, for example: CTR NONCE packing is:\n + - NONCE[0] -> 7:0\n + - NONCE[1] -> 15:8\n + - ...\n + - NONCE[13] -> 103:96\n + - NONCE[14](Bits 3:0) -> 107:104\n + */ + uint32_t CounterInit; /*!< CTR/CCM mode: Counter Initialization Value (CTR=20-bit, CCM=16-bit) */ + uint32_t numValidBytes; /*!< CCM mode: Number of valid bytes in the last (padding) block (1-16) */ + uint32_t numShaBits; /*!< SHA mode: Number of bits in the SHA payload, which may be odd-sized */ +} ADI_CRYPTO_TRANSACTION; + + +/*================ PUBLIC API ==================*/ + + +ADI_CRYPTO_RESULT adi_crypto_Open (uint32_t const nDeviceNum, void * const pMemory, uint32_t const nMemorySize, ADI_CRYPTO_HANDLE * const phDevice); +ADI_CRYPTO_RESULT adi_crypto_Close (ADI_CRYPTO_HANDLE const hDevice); +ADI_CRYPTO_RESULT adi_crypto_RegisterCallback (ADI_CRYPTO_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void * const pCBParam); +ADI_CRYPTO_RESULT adi_crypto_Enable (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); + +ADI_CRYPTO_RESULT adi_crypto_SubmitBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION * const pBuffer); +ADI_CRYPTO_RESULT adi_crypto_GetBuffer (ADI_CRYPTO_HANDLE const hDevice, ADI_CRYPTO_TRANSACTION ** const ppBuffer); +ADI_CRYPTO_RESULT adi_crypto_IsBufferAvailable (ADI_CRYPTO_HANDLE const hDevice, bool * const pbAvailable); + +#if (ADI_CRYPTO_ENABLE_DMA_SUPPORT == 1) +ADI_CRYPTO_RESULT adi_crypto_EnableDmaMode (ADI_CRYPTO_HANDLE const hDevice, bool const bEnable); +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h new file mode 100755 index 00000000000..63c3bb2cf9c --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/dma/adi_dma.h @@ -0,0 +1,274 @@ +/*! + ***************************************************************************** + * @file: adi_dma.h + * @brief: DMA Device Definitions for ADuCxxx + *----------------------------------------------------------------------------- + * +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ADI_DMA_MODE_PING_PONG +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \addtogroup DMA_Driver DMA Driver + * @{ + * @brief DMA Driver + * @details This driver is intended to be used only by the device drivers and not by the application. + * @note The device drivers must include drivers/dma/adi_dma.h to use this driver + */ + +#ifndef ADI_DMA__H__ +#define ADI_DMA__H__ + +#include + + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*============= D E F I N E S =============*/ +/*! Amount of memory(In bytes) required by the DMA manager for managing the operation + * This memory is completely owned by the driver till the end of the operation. + */ + +/*============= D A T A T Y P E S =============*/ + + +/*! + * Dma Data Increments + */ +typedef enum +{ + ADI_DMA_INCR_1_BYTE = 0x00u, /*!< Byte increment */ + ADI_DMA_INCR_2_BYTE = 0x01u, /*!< Half word increment */ + ADI_DMA_INCR_4_BYTE = 0x02u, /*!< Word increment */ + ADI_DMA_INCR_NONE = 0x03u, /*!< No increment */ + + ADI_DMA_DECR_1_BYTE = 0x10u, /*!< Byte decrement */ + ADI_DMA_DECR_2_BYTE = 0x11u, /*!< Half word decrement */ + ADI_DMA_DECR_4_BYTE = 0x12u /*!< Word decrement */ + +} ADI_DMA_INCR_TYPE; + +/*! + * DMA Callback Events + */ +typedef enum +{ + ADI_DMA_EVENT_BUFFER_PROCESSED, /*!< Buffer processed event */ + ADI_DMA_EVENT_ERR_BUS, /*!< Bus Error Occurred Event */ + ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR /*!< Invalid Descriptor Event */ +} ADI_DMA_EVENT; + + +/*! + * Dma Data Widths + */ +typedef enum +{ + ADI_DMA_WIDTH_1_BYTE = 0x0, /*!< 8-bit */ + ADI_DMA_WIDTH_2_BYTE = 0x1, /*!< 16-bit */ + ADI_DMA_WIDTH_4_BYTE = 0x2 /*!< 32-bit */ +} ADI_DMA_WIDTH_TYPE; + + +/*! + * Dma Rearbitration Intervals (chunk size between bus arbitrations) + */ +typedef enum +{ + ADI_DMA_RPOWER_1 = 0, /*!< Rearbitrate after 1 transfer */ + ADI_DMA_RPOWER_2, /*!< Rearbitrate after 2 transfers */ + ADI_DMA_RPOWER_4, /*!< Rearbitrate after 4 transfers */ + ADI_DMA_RPOWER_8, /*!< Rearbitrate after 8 transfers */ + ADI_DMA_RPOWER_16, /*!< Rearbitrate after 16 transfers */ + ADI_DMA_RPOWER_32, /*!< Rearbitrate after 32 transfers */ + ADI_DMA_RPOWER_64, /*!< Rearbitrate after 64 transfers */ + ADI_DMA_RPOWER_128, /*!< Rearbitrate after 128 transfers */ + ADI_DMA_RPOWER_256, /*!< Rearbitrate after 256 transfers */ + ADI_DMA_RPOWER_512, /*!< Rearbitrate after 512 transfers */ + ADI_DMA_RPOWER_1024 /*!< Rearbitrate after 1024 transfers */ +} ADI_DMA_RPOWER; + + +/*! + * Dma Transfer Modes + */ +typedef enum +{ + ADI_DMA_MODE_BASIC, /*!< Basic mode */ + ADI_DMA_MODE_AUTO, /*!< Auto request mode */ + ADI_DMA_MODE_PING_PONG, /*!< Ping pong mode */ + ADI_DMA_MODE_MSG, /*!< Memory Scatter gather mode (not valid as no Memory DMA support) */ + ADI_DMA_MODE_PSG /*!< Peripheral Scatter mode */ +} ADI_DMA_MODE; + + +/*! + * Dma Channel Priority Settings (only HIGH or DEFAULT priority supported) + */ +typedef enum +{ + ADI_DMA_PRIORITY_DEFAULT = 0, /*!< Use DEFAULT channel priority */ + ADI_DMA_PRIORITY_HIGH /*!< Elevate channel to HIGH priority */ +} ADI_DMA_PRIORITY; + + +/*! + * Result Event Type + */ +typedef enum { + ADI_DMA_SUCCESS, /*!< Successfully Completed */ + ADI_DMA_ERR_NOT_INITIALIZED, /*!< DMA not initialized */ + ADI_DMA_ERR_INVALID_PARAMETER, /*!< Input parameter to the function is invalid */ +} ADI_DMA_RESULT; + +/*! \cond PRIVATE*/ +/*! + * \enum DMA_CHANn_TypeDef + * DMA Channel Assignments + */ +typedef enum +{ + SPI2_TX_CHANn = 0, /*!< SPI2 Transmit DMA channel */ + SPI2_RX_CHANn = 1, /*!< SPI2 Receive DMA channel */ + SPORT0A_CHANn = 2, /*!< SPORT0-A DMA channel */ + SPORT0B_CHANn = 3, /*!< SPORT0-B DMA channel */ + SPI0_TX_CHANn = 4, /*!< SPI0 Transmit DMA channel */ + SPI0_RX_CHANn = 5, /*!< SPI0 Receive DMA channel */ + SPI1_TX_CHANn = 6, /*!< SPI1 Transmit DMA channel */ + SPI1_RX_CHANn = 7, /*!< SPI1 Receive DMA channel */ + UART0_TX_CHANn = 8, /*!< UART0 Transmit DMA channel */ + UART0_RX_CHANn = 9, /*!< UART0 Receive DMA channel */ + I2CS_TX_CHANn = 10, /*!< I2C Slave Transmit DMA channel */ + I2CS_RX_CHANn = 11, /*!< I2C Slave Receive DMA channel */ + I2CM_CHANn = 12, /*!< I2C Master DMA channel */ + AES0_IN_CHANn = 13, /*!< AES0-IN DMA channel */ + AES0_OUT_CHANn = 14, /*!< AES0-OUT DMA channel */ + FLASH_CHANn = 15, /*!< FLASH DMA channel */ + SIP0_CHANn = 16, /*!< SIP-0 DMA channel */ + SIP1_CHANn = 17, /*!< SIP-1 DMA channel */ + SIP2_CHANn = 18, /*!< SIP-2 DMA channel */ + SIP3_CHANn = 19, /*!< SIP-3 DMA channel */ + SIP4_CHANn = 20, /*!< SIP-4 DMA channel */ + SIP5_CHANn = 21, /*!< SIP-5 DMA channel */ + SIP6_CHANn = 22, /*!< SIP-6 DMA channel */ + SIP7_CHANn = 23, /*!< SIP-7 DMA channel */ + ADC0_CHANn = 24, /*!< ADC0 DMA channel */ + UART1_TX_CHANn = 25, /*!< UART1 Transmit DMA channel */ + UART1_RX_CHANn = 26, /*!< UART1 Receive DMA channel */ + NUM_DMA_CHANNELSn = 27 /*!< Total Number of DMA channels */ +} DMA_CHANn_TypeDef; /** typedef name for fixed DMA channel assignments */ +/*! \endcond */ + +/*! + * \struct ADI_DCC_TypeDef + * DMA Channel Control MMR Access Template + */ +typedef struct +{ + __IO uint32_t DMASRCEND; /*!< Source End Pointer */ + __IO uint32_t DMADSTEND; /*!< Destination End Pointer */ + __IO uint32_t DMACDC; /*!< Channel Data Configuration */ + uint32_t RESERVED; /*!< Address gap filler */ +} ADI_DCC_TypeDef; + + +/*! \cond PRIVATE */ +/* Bit Position for DMA Descriptor Control */ +#define DMA_BITP_CTL_DST_INC (30u) +#define DMA_BITP_CTL_SRC_INC (26u) +#define DMA_BITP_CTL_SRC_SIZE (24u) +#define DMA_BITP_CTL_R_POWER (14u) +#define DMA_BITP_CTL_N_MINUS_1 (4u) +#define DMA_BITP_CTL_CYCLE_CTL (0u) + +/* Bit Mask for DMA Descriptor Control */ +#define DMA_BITM_CTL_DST_INC ((0x00000003u) << DMA_BITP_CTL_DST_INC) +#define DMA_BITM_CTL_SRC_INC ((0x00000003u) << DMA_BITP_CTL_SRC_INC) +#define DMA_BITM_CTL_SRC_SIZE ((0x00000003u) << DMA_BITP_CTL_SRC_SIZE) +#define DMA_BITM_CTL_R_POWER ((0x0000000Fu) << DMA_BITP_CTL_R_POWER) +#define DMA_BITM_CTL_N_MINUS_1 ((0x000003FFu) << DMA_BITP_CTL_N_MINUS_1) +#define DMA_BITM_CTL_CYCLE_CTL ((0x00000007u) << DMA_BITP_CTL_CYCLE_CTL) + +/* Enum for the DMA Descriptor Cycle Control */ +#define DMA_ENUM_CTL_CYCLE_CTL_INVALID (0u) +#define DMA_ENUM_CTL_CYCLE_CTL_BASIC (1u) +#define DMA_ENUM_CTL_CYCLE_CTL_AUTO_REQ (2u) +#define DMA_ENUM_CTL_CYCLE_CTL_PING_PONG (3u) +#define DMA_ENUM_CTL_CYCLE_CTL_MSG_PRI (4u) +#define DMA_ENUM_CTL_CYCLE_CTL_MSG_ALT (5u) +#define DMA_ENUM_CTL_CYCLE_CTL_PSG_PRI (6u) +#define DMA_ENUM_CTL_CYCLE_CTL_PSG_ALT (7u) + + +#define DMA_BITM_INCR_TYPE_DECR (0x10u) + +#define DMA_BITM_OCTL_SRC_DECR (0x01u) +#define DMA_BITM_OCTL_DST_DECR (0x02u) + +#define DMA_BITM_OCTL_SRC_INCR (0x04u) +#define DMA_BITM_OCTL_DST_INCR (0x08u) + +#define DMA_TRANSFER_LIMIT (1024u) /*!< Maximum number of transfers handled by the DMA in one request */ + +/* pointer to the primary CCD array */ +extern ADI_DCC_TypeDef* const pPrimaryCCD; +/* pointer to the alternate CCD array */ +extern ADI_DCC_TypeDef* const pAlternateCCD; +/*! \endcond */ +/*========== DMA API DECLARATIONS ==========*/ + +extern void adi_dma_Init(void); + +extern ADI_DMA_RESULT adi_dma_RegisterCallback ( + DMA_CHANn_TypeDef const eChannelID, + ADI_CALLBACK const pfCallback, + void* const pCBParam + ); + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/**@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h new file mode 100755 index 00000000000..c72524e3e4d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/flash/adi_flash.h @@ -0,0 +1,185 @@ +/*! + ***************************************************************************** + @file: adi_flash.h + @brief: Flash device driver definitions + @date: $Date: 2016-07-05 00:49:46 -0400 (Tue, 05 Jul 2016) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! @addtogroup Flash_Driver Flash Driver + * @{ + */ + +#ifndef ADI_FLASH_H +#define ADI_FLASH_H + + /*! \cond PRIVATE */ +#include +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_FEE_RESULT + * Flash Controller return codes. + */ + typedef enum { + ADI_FEE_SUCCESS = 0, /*!< The function completed successfully. */ + ADI_FEE_ERR_ALIGNMENT, /*!< The flash write source data pointer is misaligned. */ + ADI_FEE_ERR_ALREADY_INITIALIZED, /*!< The flash device driver is already initialized. */ + ADI_FEE_ERR_BAD_DEVICE_NUM, /*!< Device number passed is invalid. */ + ADI_FEE_ERR_BUFFER_ERR, /*!< An error occurred while processing a write buffer. */ + ADI_FEE_ERR_DEVICE_BUSY, /*!< The device is busy. */ + ADI_FEE_ERR_DMA_BUS_FAULT, /*!< Runtime DMA bus fault detected. */ + ADI_FEE_ERR_DMA_INVALID_DESCR, /*!< Runtime DMA invalid descriptor detected. */ + ADI_FEE_ERR_DMA_REGISTER, /*!< Error registering DMA error callback function. */ + ADI_FEE_ERR_DMA_UNKNOWN_ERROR, /*!< Unknown runtime DMA error detected. */ + ADI_FEE_ERR_HW_ERROR_DETECTED, /*!< An FEE hardware error occurred (pHwErrors param). */ + ADI_FEE_ERR_INSUFFICIENT_MEM, /*!< The memory passed is undersized. */ + ADI_FEE_ERR_INVALID_HANDLE, /*!< Device Handle is invalid. */ + ADI_FEE_ERR_INVALID_PARAM, /*!< A function parameter is invalid. */ + ADI_FEE_ERR_NO_DATA_TO_TRANSFER, /*!< No transfer data detected. */ + ADI_FEE_ERR_TRANSFER_IN_PROGRESS, /*!< Operation already in progress. */ + ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY, /*!< Unmatched read/write vs. submit/get API call. */ + ADI_FEE_ERR_SEMAPHORE_FAILED, /*!< An semaphore operation failed. */ + } ADI_FEE_RESULT; + + +/*! A device handle used in all API functions to identify the flash device. */ +typedef struct __ADI_FEE_DEV_DATA_TYPE* ADI_FEE_HANDLE; + + +/*! Applications use the "ADI_FEE_MEMORY_SIZE" macro to allocate + required flash driver memory. This memory (and size) are passed + to the flash driver during the "adi_fee_Open()" driver initialization + call. This memory is used to store internal flash driver state. +*/ +#define ADI_FEE_MEMORY_SIZE (44u + ADI_SEM_SIZE) + + +/*! + * \enum ADI_FEE_CALLBACK_EVENT + * Enum for the callback events. + */ +typedef enum { + ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, /*!< Buffer processed successfully event. */ + ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, /*!< Device error(s) detected during command. */ +} ADI_FEE_CALLBACK_EVENT; + +/*! + * \enum ADI_FEE_ECC_EVENT_TYPE + * Enum for the Error-Correction-Code event type. + */ +typedef enum { + ADI_FEE_ECC_EVENT_TYPE_ERROR, /*!< ECC Error Event. */ + ADI_FEE_ECC_EVENT_TYPE_CORRECT /*!< ECC correction event. */ +} ADI_FEE_ECC_EVENT_TYPE; + +/*! + * \enum ADI_FEE_ECC_RESPONSE + * Error-Correction-Code configuration codes. + */ +typedef enum { + ADI_FEE_ECC_RESPONSE_NONE = 0x0, /*!< No Response. */ + ADI_FEE_ECC_RESPONSE_BUS_ERROR = 0x1, /*!< Generate a Bus Error. */ + ADI_FEE_ECC_RESPONSE_IRQ = 0x2 /*!< Generate an IRQ. */ +} ADI_FEE_ECC_RESPONSE; + + +/*! + * \struct ADI_FEE_TRANSACTION + * Flash write data transaction block. + */ +typedef struct { + uint32_t *pWriteAddr; /*!< Pointer to flash-space (destination) write location. */ + uint32_t *pWriteData; /*!< Pointer to user-space (source) write Data. */ + uint32_t nSize; /*!< Write data size (in bytes). */ + bool bUseDma; /*!< DMA flag controlling use of DMA or not. */ +} ADI_FEE_TRANSACTION; + + +/*================ E X T E R N A L S ==================*/ +/* Flash Controller API */ + +ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice); +ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice); +ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam); + +ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors); + +ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction); + +ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState); +ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors); + +ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum); +ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum); + +ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors); +ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum); + +ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep); +ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice); +ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress); + +ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable); +ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable); +ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse); +ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress); +ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections); + +#ifdef __cplusplus +} +#endif + +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h new file mode 100755 index 00000000000..89ab88d841e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_data_transfer.h @@ -0,0 +1,127 @@ +/*! **************************************************************************** + * @file adi_data_transfer.h + * @brief General data transfer types for drivers + * @details General data transfer types for drivers + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_DATA_TRANSFER_H +#define ADI_DATA_TRANSFER_H + +/*============= I N C L U D E S =============*/ + +#include /* defines types such as uint32_t*/ +#include /* needed for SEM_VAR_DECLR declaration */ + +/*! \cond PRIVATE */ +/** @addtogroup Data_Transfer Common Data Transfer Structures +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*============== D E F I N E S ===============*/ + +#define ADI_DT_BUFNUM (2u) /*!< Number of buffers available for data transfers in each communication channel */ + +/*! + ******************************************************************************* + * \struct ADI_DT_BUFF_INFO + * Structure for managing buffers submitted to drivers. + ******************************************************************************/ +struct _ADI_DT_BUFF_INFO; + +/*! + ******************************************************************************* + * Structure for managing buffers submitted to drivers. + ******************************************************************************/ +typedef struct _ADI_DT_BUFF_INFO +{ + void * pStartAddress; /*!< Address of buffer passed down a driver. */ + uint32_t nCount; /*!< Size of buffer in bytes. */ + uint32_t nIndex; /*!< Position of first byte to be transmitted. */ + bool bInUse; /*!< Buffer in use flag. */ + bool bDMA; /*!< Transaction is using the DMA flag. */ + struct _ADI_DT_BUFF_INFO * pNextBuffer; /*!< Pointer to the next buffer in the list. */ +} ADI_DT_BUFF_INFO; + +/*! + ******************************************************************************* + * Enumeration of different data transfer modes supported by drivers. + ******************************************************************************/ +typedef enum _ADI_DT_MODE +{ + ADI_DT_MODE_NONE, /*!< Mode of data transfer is not selected. */ + ADI_DT_MODE_BLOCKING, /*!< Only calls to adi_xxx_Read or adi_xxx_Write are allowed for transferring data. */ + ADI_DT_MODE_NONBLOCKING /*!< Only calls to adi_xxx_SubmitBuffer are allowed for transferring data. */ +} ADI_DT_MODE; + +typedef void * ADI_DEVICE_HANDLE; /*!< Generic device handle */ + +/*! + ******************************************************************************* + * Structure for managing pool of buffers submitted to drivers. + ******************************************************************************/ +typedef struct +{ + ADI_DT_BUFF_INFO BufInfo[ADI_DT_BUFNUM]; /*!< Ping Pong Buffers. */ + ADI_DT_BUFF_INFO * pFreeBuffer; /*!< Pointer to free buffer. (Next buffer to submit). */ + ADI_DT_BUFF_INFO * pFillBuffer; /*!< Pointer to the next buffer to be filled. (Needed for the case + where many buffers are "submitted" before a "get" is called.) */ + ADI_DT_BUFF_INFO * pActiveBuffer; /*!< Pointer to active buffer. (Next buffer waiting for completion.)*/ + ADI_DT_MODE eDataTranferMode; /*!< Data transfer mode (blocking or non-blockig). */ + + SEM_VAR_DECLR +} ADI_DT_CHANNEL; + + +/*============= P U B L I C F U N C T I O N S =============*/ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*! \endcond */ + +#endif /* ADI_DATA_TRANSFER_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h new file mode 100755 index 00000000000..0540cea56ed --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/general/adi_drivers_general.h @@ -0,0 +1,98 @@ +/*! + ***************************************************************************** + * @file: adi_drivers_general.h + * @brief: Macros and types used in multiple drivers + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#ifndef ADI_DRIVERS_GENERAL__H +#define ADI_DRIVERS_GENERAL__H + + +/* Macros related to alignment in the different toolchains supported */ + +/* + * These macros are designed to be used as follows: + * ADI_ALIGNED_PRAGMA() + * ADI_ALIGNED_ATTRIBUTE() + */ + +#if defined ( __ICCARM__ ) +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm120 (rule 19.10): In the definition of a function-like macro each parameter +* shall be enclosed in parenthesis. +* This is not possible in attributes and pragmas +* Pm154 (rule 19.13): The # and ## preprocessor operators shall not be used. +* We need to do this to abstract the macros for the +* different toolchains +*/ +#pragma diag_suppress=Pm120,Pm154 +#endif + +#define PRAGMA(x) _Pragma(#x) +#define ATTRIBUTE(x) __attribute__((x)) + +#if defined (__GNUC__) + /* Gcc uses attributes */ + #define ADI_ALIGNED_PRAGMA(num) + #define ADI_ALIGNED_ATTRIBUTE(num) ATTRIBUTE(aligned(num)) + #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) +#elif defined ( __ICCARM__ ) + /* IAR uses a pragma */ + #define ADI_ALIGNED_ATTRIBUTE(num) + #define ADI_ALIGNED_PRAGMA(num) PRAGMA(data_alignment=num) + #define ADI_UNUSED_ATTRIBUTE +#elif defined (__CC_ARM) + /* Keil uses a decorator which is placed in the same position as pragmas */ + #define ADI_ALIGNED_ATTRIBUTE(num) + #define ADI_ALIGNED_PRAGMA(num) __align(##num) + #define ADI_UNUSED_ATTRIBUTE ATTRIBUTE(unused) +#else +#error "Toolchain not supported" +#endif + + +#if defined ( __ICCARM__ ) +#pragma diag_default=Pm120,Pm154 +#endif +#endif /* ADI_DRIVERS_GENERAL__H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h new file mode 100755 index 00000000000..ad0673a2b50 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/gpio/adi_gpio.h @@ -0,0 +1,174 @@ +/* + ***************************************************************************** + @file: adi_gpio.h + @brief: GPIO definitions and API + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_GPIO_H +#define ADI_GPIO_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm008 (rule 2.4): sections of code should not be 'commented out'. + * Allow code example in doxygen comment. + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm008,Pm011 +#endif /* __ICCARM__ */ + +/*! \addtogroup GPIO_Driver GPIO Driver + * @{ + */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm008 +#endif /* __ICCARM__ */ + +/* C++ linkage */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! Amount of memory(in bytes) required by the GPIO device driver for its operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_GPIO_MEMORY_SIZE (16u) + +/* typedefs for 16-bit Ports */ +typedef uint16_t ADI_GPIO_DATA; /*!< pin data reg type */ + + +/*! GPIO API function return codes */ +typedef enum +{ + ADI_GPIO_SUCCESS = 0, /*!< No error detected. */ + ADI_GPIO_FAILURE, /*!< The API call failed. */ + ADI_GPIO_ALREADY_INITIALIZED, /*!< GPIO device has already been initialized. */ + ADI_GPIO_NOT_INITIALIZED, /*!< GPIO device has not yet been initialized. */ + ADI_GPIO_NULL_PARAMETER, /*!< The given pointer is pointing to NULL. */ + ADI_GPIO_INVALID_MEMORY_SIZE, /*!< The given memory is not sufficient to operate the driver. */ + ADI_GPIO_INVALID_PINS, /*!< Invalid pin combination. */ + ADI_GPIO_INVALID_INTERRUPT, /*!< Invalid interrupt number. */ + ADI_GPIO_INVALID_TRIGGER, /*!< Invalid trigger condition. */ +} ADI_GPIO_RESULT; + + +/*! GPIO trigger condition enumerations */ +typedef enum { + ADI_GPIO_IRQ_RISING_EDGE =(0x0), /*!< Trigger an interrupt on a rising edge. */ + ADI_GPIO_IRQ_FALLING_EDGE =(0x1), /*!< Trigger an interrupt on a falling edge. */ + ADI_GPIO_IRQ_EITHER_EDGE =(0x2), /*!< Trigger an interrupt on either edge. */ + ADI_GPIO_IRQ_HIGH_LEVEL =(0x3), /*!< Trigger an interrupt on a high level. */ + ADI_GPIO_IRQ_LOW_LEVEL =(0x4) /*!< Trigger an interrupt on a low level. */ +} ADI_GPIO_IRQ_TRIGGER_CONDITION; + +/*! GPIO IRQ enumeration */ +typedef enum { + ADI_GPIO_INTA_IRQ = SYS_GPIO_INTA_IRQn, /*!< GPIO Group Interrupt A. */ + ADI_GPIO_INTB_IRQ = SYS_GPIO_INTB_IRQn, /*!< GPIO Group Interrupt B. */ +} ADI_GPIO_IRQ; + + +/*! GPIO port enumerations */ +typedef enum { + ADI_GPIO_PORT0, /*!< Port 0 */ + ADI_GPIO_PORT1, /*!< Port 1 */ + ADI_GPIO_PORT2, /*!< Port 2 */ + ADI_GPIO_PORT3, /*!< Port 3 */ + ADI_GPIO_NUM_PORTS /*!< maximum number of ports */ +} ADI_GPIO_PORT; + +/* 16-bit port pin defs */ +#define ADI_GPIO_PIN_0 ((ADI_GPIO_DATA)(0x0001)) /*!< Pin 0 */ +#define ADI_GPIO_PIN_1 ((ADI_GPIO_DATA)(0x0002)) /*!< Pin 1 */ +#define ADI_GPIO_PIN_2 ((ADI_GPIO_DATA)(0x0004)) /*!< Pin 2 */ +#define ADI_GPIO_PIN_3 ((ADI_GPIO_DATA)(0x0008)) /*!< Pin 3 */ +#define ADI_GPIO_PIN_4 ((ADI_GPIO_DATA)(0x0010)) /*!< Pin 4 */ +#define ADI_GPIO_PIN_5 ((ADI_GPIO_DATA)(0x0020)) /*!< Pin 5 */ +#define ADI_GPIO_PIN_6 ((ADI_GPIO_DATA)(0x0040)) /*!< Pin 6 */ +#define ADI_GPIO_PIN_7 ((ADI_GPIO_DATA)(0x0080)) /*!< Pin 7 */ +#define ADI_GPIO_PIN_8 ((ADI_GPIO_DATA)(0x0100)) /*!< Pin 8 */ +#define ADI_GPIO_PIN_9 ((ADI_GPIO_DATA)(0x0200)) /*!< Pin 9 */ +#define ADI_GPIO_PIN_10 ((ADI_GPIO_DATA)(0x0400)) /*!< Pin 10 */ +#define ADI_GPIO_PIN_11 ((ADI_GPIO_DATA)(0x0800)) /*!< Pin 11 */ +#define ADI_GPIO_PIN_12 ((ADI_GPIO_DATA)(0x1000)) /*!< Pin 12 */ +#define ADI_GPIO_PIN_13 ((ADI_GPIO_DATA)(0x2000)) /*!< Pin 13 */ +#define ADI_GPIO_PIN_14 ((ADI_GPIO_DATA)(0x4000)) /*!< Pin 14 */ +#define ADI_GPIO_PIN_15 ((ADI_GPIO_DATA)(0x8000)) /*!< Pin 15 */ + +/* GPIO port pins availability mask */ +#define ADI_GPIO_PORT0_PIN_AVL (0xFFFFu) /*!< Port 0 pin mask (16 pins)*/ +#define ADI_GPIO_PORT1_PIN_AVL (0xFFFFu) /*!< Port 1 pin mask (16 pins)*/ +#define ADI_GPIO_PORT2_PIN_AVL (0xFFFFu) /*!< Port 2 pin mask (16 pins)*/ +#define ADI_GPIO_PORT3_PIN_AVL (0x000Fu) /*!< Port 2 pin mask (4 pins) */ + + +/* GPIO API functions */ +ADI_GPIO_RESULT adi_gpio_Init (void* const pMemory, uint32_t const MemorySize); +ADI_GPIO_RESULT adi_gpio_UnInit (void); +ADI_GPIO_RESULT adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam ); +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins (const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_OutputEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_InputEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_PullUpEnable (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag); +ADI_GPIO_RESULT adi_gpio_SetHigh (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetLow (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_Toggle (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_SetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); +ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue); + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_GPIO_V1_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h new file mode 100755 index 00000000000..edd398f3f9b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/i2c/adi_i2c.h @@ -0,0 +1,243 @@ +/*! + ***************************************************************************** + @file: adi_i2c.h + @brief: I2C device driver definitions + @details This is the primary header file for the I2C driver, which contains the + API declarations, data and constant definitions used in the APIs. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_I2C_H +#define ADI_I2C_H + + /*! \cond PRIVATE */ +#include +#include /* for ADI_SEM_SIZE */ +/*! \endcond */ + + +/** @addtogroup I2C_Driver I2C Driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +*/ +#pragma diag_suppress=Pm011 + +#endif + +/*! + ***************************************************************************** + * \enum ADI_I2C_RESULT + * + * I2C Device Error Codes. #ADI_I2C_SUCCESS is always zero + * The return value of all I2C APIs returning #ADI_I2C_RESULT + * should always be tested at the application level for success or failure. + * Specific I2C bus error conditions are returned as elements of + * #ADI_I2C_RESULT. + * + *****************************************************************************/ +typedef enum +{ + ADI_I2C_SUCCESS = 0, /*!< The API call succeeded. */ + ADI_I2C_BAD_BITRATE, /*!< The bit rate is invalid. */ + ADI_I2C_BAD_DEVICE_HANDLE, /*!< The device handle is invalid. */ + ADI_I2C_BAD_DEVICE_NUMBER, /*!< The device number is invalid. */ + ADI_I2C_BAD_SYS_CLOCK, /*!< Unable to obtain system clock rate. */ + ADI_I2C_DEVICE_IN_USE, /*!< The device is in use. */ + ADI_I2C_DEVICE_NOT_OPEN, /*!< The device is not open. */ + ADI_I2C_FAILURE, /*!< Generic API failure code. */ + ADI_I2C_HW_ERROR_DETECTED, /*!< An I2C hardware error occurred. See #ADI_I2C_HW_ERRORS. */ + ADI_I2C_INSUFFICIENT_MEMORY, /*!< The application supplied memory size is insufficient. */ + ADI_I2C_INVALID_PARAMETER, /*!< An invalid parameter is passed to the function. */ + ADI_I2C_INVALID_SLAVE_ADDRESS, /*!< The application supplied slave address is too wide. */ + ADI_I2C_INVALID_SUBMIT_API, /*!< Unmatched read/write vs. submit/get API call. */ + ADI_I2C_SEMAPHORE_FAILED /*!< Semaphore operation failed. */ + +} ADI_I2C_RESULT; + + +/*! + ***************************************************************************** + * \enum ADI_I2C_HW_ERRORS + * + * I2C Device Hardware Error Codes. Contains one or more hardware (I2C protocol) + * errors. Use this enum to decode hardware errors when the main #ADI_I2C_RESULT + * return result value is #ADI_I2C_HW_ERROR_DETECTED. + * + *****************************************************************************/ +typedef enum +{ + ADI_I2C_HW_ERROR_NONE = 0, /*!< No hardware error. */ + ADI_I2C_HW_ERROR_NACK_ADDR = 0x0001, /*!< A no-acknowledgement occurred for the address. */ + ADI_I2C_HW_ERROR_NACK_DATA = 0x0002, /*!< A no-acknowledgement occurred for the data. */ + ADI_I2C_HW_ERROR_ARBITRATION_LOST = 0x0004, /*!< I2C bus arbitration was Lost. */ + ADI_I2C_HW_ERROR_UNEXPECTED_ERROR = 0x0008, /*!< An unexpected error occurred. */ + +} ADI_I2C_HW_ERRORS; + + +/*! A device handle used in all API functions to identify the I2C device. */ +typedef struct __ADI_I2C_DEV_DATA_TYPE* ADI_I2C_HANDLE; + +/*! Use macro "ADI_I2C_MEMORY_SIZE" to know how much memory to + provide the i2c driver during the "adi_i2c_Open()" driver + initialization call. This memory is used to store internal + driver state data. Use map file to verify. +*/ +#define ADI_I2C_MEMORY_SIZE (44u + ADI_SEM_SIZE) + + +/*! + * \struct ADI_I2C_TRANSACTION + ***************************************************************************** + * I2C Device Command/Data Transaction Structure. This is the called-provided + * data structure used by the blocking #adi_i2c_ReadWrite() and non-blocking + * #adi_i2c_SubmitBuffer() calls to describe the caller's transaction parameters, + * consisting of prologue data and size (the addressing phase), transmit/receive + * data pointer and size (the data phase), and various transaction control parameters. + * + * Each transaction may optionally be prefaced with a prologue block, which may + * describe a read/write memory/register address, a slave-specific command, or + * some other slave-specific protocol that may precede the actual read/write + * data. Set the prologue size to zero if no prologue is desired. + * + * Each call to #adi_i2c_ReadWrite or #adi_i2c_SubmitBuffer() must populate the + * following fields of the ADI_I2C_TRANSACTION block: + * + * @par pPrologue + * Byte pointer to an application-supplied prologue byte array. If the value is + * zero, prologue data is ignored. + * + * @par nPrologueSize + * The number of prologue bytes to be transmitted ahead of the data phase. If the + * value is zero, prologue data is ignored. + * + * @par pData + * Byte pointer to the application-supplied data byte array. This buffer is + * either the source or destination address of the data being transmitted or + * received, respectively. + * + * @par nDataSize + * The number of data bytes to be transmitted or received during the data phase. + * If the value is zero, the data phase is ignored. + * + * @par bReadNotWrite + * Direction control for data phase. If "true", data phase is a read (from + * the slave), if "false", data phase is a write (to the slave). Pertains only + * to the data phase. Any prologue data (addressing/command phase) is always + * transmitted (written to the slave) prior to the data phase. + * + * @par bRepeatStart + * Controls suppression of a Stop Condition between the addressing phase and the + * data phase of an I2C transaction. After the prologue (if present), a + * unidirectional data stream (I2C is a half-duplex protocol) is either + * transmitted or received (depending on the transfer direction). Frequently, a + * Repeat-Start Condition (in reality, just the absence of a Stop Condition + * following the prologue/addressing phase) is required between the addressing + * phase (prologue) and the data phase of a transaction to meet slave device + * protocol requirements. The Repeat-Start requirement can be driven by the + * slave device communications protocol, or simply to just prevent any other + * I2C master from rearbitrating the bus between the prologue (addressing) and + * data phases of a so-called "COMBINED FORMAT" (write-followed-by-read). + * When bRepeatStart is set "true", the usual Stop Condition between the addressing + * phase and the data phase is suppressed and the I2C bus controller issues a + * second Start Condition (Repeat-Start) for the data phase. Without + * Repeat-Start (bRepeatStart "false"), the addressing phase ends with a normal + * Stop Condition ahead of the data phase. Repeat-Start conditions are used + * when "turning the bus around" as in writing a read address (for example), + * immediately followed by a data stream from that read address... without + * releasing bus arbitration. + * + *****************************************************************************/ +typedef struct { + uint8_t *pPrologue; /*!< Prologue pointer. */ + uint16_t nPrologueSize; /*!< Prologue byte count. */ + uint8_t *pData; /*!< Data pointer. */ + uint16_t nDataSize; /*!< Data byte count. */ + bool bReadNotWrite; /*!< Read/write flag. */ + bool bRepeatStart; /*!< Repeat start flag. */ +} ADI_I2C_TRANSACTION; + + +/*! Maximum supported bitrate is "FAST" mode (400 kHz). */ +#define ADI_I2C_MAX_RATE (400000u) + +/*************************************************************** + * Eliminable user API that may be optimized out by the linker * + ***************************************************************/ +ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice); +ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice); + +/* blocking calls... */ +ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors); + +/* non-blocking calls... */ +ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction); +ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState); +ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors); + +/* other (blocking) calls... */ +ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice); +ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32); +ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress); +ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors); + + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_I2C_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h new file mode 100755 index 00000000000..1bb8f41467f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/pwr/adi_pwr.h @@ -0,0 +1,689 @@ +/* + ***************************************************************************** + * @file: adi_pwr.h + * @brief: System clock and power management driver. + *----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +/*! \addtogroup Power_Driver Power Driver + * @{ + */ + +#ifndef ADI_PWR_H +#define ADI_PWR_H + +#include +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm009 (rule 5.1): identifiers shall not rely on significance of more than 31 characters. + * IAR compiler supports longer identifiers. + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm009,Pm011 +#endif /* __ICCARM__ */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*! Enumeration of clock sources for various peripherals. */ +typedef enum { + /*! Source for all peripherals SPI, SPORT, SIP, CRC, AES, SIP interface, I2C, UART, optionally for timers. */ + ADI_CLOCK_PCLK, + /*! Source for Core,Bus etc. */ + ADI_CLOCK_HCLK, + /*! Source for the ADC. */ + ADI_CLOCK_ACLK + +} ADI_CLOCK_ID; + +/*! Enumeration of input clock sources */ +typedef enum { + /*! Clock ID for 16 MHz or 26 MHz external crystal oscillator called HFXTAL. */ + ADI_CLOCK_SOURCE_HFXTAL, + /*! Clock ID 32 kHz external crystal oscillator called LFXTAL. */ + ADI_CLOCK_SOURCE_LFXTAL, + /*! Clock ID for 26 MHz internal oscillator called HFOSC. */ + ADI_CLOCK_SOURCE_HFOSC, + /*! Clock ID 32 kHz a 32 kHz internal oscillator called LFXTAL. */ + ADI_CLOCK_SOURCE_LFOSC, + /*! Clock ID for output clock for System PLL. */ + ADI_CLOCK_SOURCE_SPLL, + /*! Clock ID for external clock from GPIO. */ + ADI_CLOCK_SOURCE_GPIO +} ADI_CLOCK_SOURCE_ID; + + +/*! + * Enumeration of clock sources for each clock multiplexer. + * The processor has the following clock multiplexers. + * - SPLL Mux (System PLL). + * - Reference clock Mux. + * - Root Clock Mux. + */ +typedef enum { + + /*! Input clock for system PLL mux is HFOSC. */ + ADI_CLOCK_MUX_SPLL_HFOSC, + /*! Input clock for system PLL mux is HFXTAL. */ + ADI_CLOCK_MUX_SPLL_HFXTAL, + /*! Input clock for system PLL mux is provided through GPIO. */ + ADI_CLOCK_MUX_SPLL_GPIO, + + /*! Input clock for low frequency clock mux is LFOSC. */ + ADI_CLOCK_MUX_LFCLK_LFOSC, + /*! Input clock for low frequency clock mux is LFXTAL. */ + ADI_CLOCK_MUX_LFCLK_LFXTAL, + + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is HFOSC. */ + ADI_CLOCK_MUX_REF_HFOSC_CLK, + /*! Reserved. */ + ADI_CLOCK_MUX_REF_RESERVED, + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is 26 MHz HFXTAL. */ + ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK, + /*! Input clock to the multiplexer which provides reference clock for Flash + and HPBUCK clock is 16 MHz HFXTAL. */ + ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK, + + /*! Input clock to root multiplexer is HFOSC. */ + ADI_CLOCK_MUX_ROOT_HFOSC, + /*! Input clock to root multiplexer is HFXTAL. */ + ADI_CLOCK_MUX_ROOT_HFXTAL, + /*! Input clock to root multiplexer is SPLL. */ + ADI_CLOCK_MUX_ROOT_SPLL, + /*! Input clock to root multiplexer is from GPIO. */ + ADI_CLOCK_MUX_ROOT_GPIO + +} ADI_CLOCK_MUX_ID; + + +/*! + * Enumeration of clock source status. + */ +typedef enum { + /*! Specified clock source is disabled. */ + ADI_CLOCK_SOURCE_DISABLED = 0, + /*! Specified clock source is not stable. */ + ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE, + /*! Specified clock source is enabled and stable. */ + ADI_CLOCK_SOURCE_ENABLED_STABLE, + /*! Invalid clock ID. */ + ADI_CLOCK_SOURCE_ID_NOT_VALID + +} ADI_CLOCK_SOURCE_STATUS; + +/*! Clock output options through GPIO pin. + The GPIO clock output pin can be driven through one of these clocks. +*/ +typedef enum +{ + /*! Root Clock (ROOT_CLK). */ + ADI_CLOCK_OUTPUT_ROOT_CLK, + + /*! Low Frequency Clock (LF_CLK). */ + ADI_CLOCK_OUTPUT_LF_CLK, + + /*! ADC Clock (ACLK). */ + ADI_CLOCK_OUTPUT_ACLK, + + /*! HCLK_BUS. */ + ADI_CLOCK_OUTPUT_HCLK_BUS, + + /*! HCLK_CORE. */ + ADI_CLOCK_OUTPUT_HCLK_CORE, + + /*! Peripheral Clock (PCLK). */ + ADI_CLOCK_OUTPUT_PCLK, + + /*! Reference Clock for Flash controller timer (RCLK). */ + ADI_CLOCK_OUTPUT_RCLK, + + /*! Mux of HFOSC, HFXTAL clock (RHP_CLK). */ + ADI_CLOCK_OUTPUT_RHP_CLK, + + /*! GP Timer 0 clock (GPT0_CLK). */ + ADI_CLOCK_OUTPUT_GPT0_CLK, + + /*! GP Timer 1 clock (GPT1_CLK). */ + ADI_CLOCK_OUTPUT_GPT1_CLK, + + /*! Peripherals operating at HCLK (HCLK_P). */ + ADI_CLOCK_OUTPUT_HCLK_PERIPHERAL, + + /*! PLL Clock out. */ + ADI_CLOCK_OUTPUT_PLL_OUTPUT, + + /*! RTC0 Clock. */ + ADI_CLOCK_OUTPUT_RTC0_CLK, + + /*! HP Buck Clock (HPBUCK_CLK). */ + ADI_CLOCK_OUTPUT_HPBUCK_CLK, + + /*! HP Buck Non overlap clock. */ + ADI_CLOCK_OUTPUT_HPBUCK_NO_OVERLAP_CLK, + + /*! RTC1 generated clock. */ + ADI_CLOCK_OUTPUT_RTC1_CLK + +}ADI_CLOCK_OUTPUT_ID; + + +/*! Enumeration of clock gates using which the clocks can be gated. */ +typedef enum { + /*! Clock Gate for the GP Timer-0. */ + ADI_CLOCK_GATE_GPT0_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK0OFF, + /*! Clock Gate for the GP Timer-1. */ + ADI_CLOCK_GATE_GPT1_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK1OFF, + /*! Clock Gate for the GP Timer-2. */ + ADI_CLOCK_GATE_GPT2_CLK = 1 << BITP_CLKG_CLK_CTL5_GPTCLK2OFF, + /*! Clock Gate for the I2C. */ + ADI_CLOCK_GATE_I2C_CLK = 1 << BITP_CLKG_CLK_CTL5_UCLKI2COFF, + /*! Clock Gate for the GPIO. */ + ADI_CLOCK_GATE_GPIO_CLK = 1 << BITP_CLKG_CLK_CTL5_GPIOCLKOFF, + /*! Clock Gate for the PCLK. */ + ADI_CLOCK_GATE_PCLK = 1 << BITP_CLKG_CLK_CTL5_PERCLKOFF, + /*! Clock Gate for the RGB Timer. */ + ADI_CLOCK_GATE_TMR_RGB_CLK = 1 << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF + +} ADI_CLOCK_GATE; + +/*! + * Enumeration of HF oscillator clock divide factor. + */ +typedef enum +{ + /*! Divide by 1. */ + ADI_PWR_HFOSC_DIV_BY_1, + /*! Divide by 2. */ + ADI_PWR_HFOSC_DIV_BY_2, + /*! Divide by 4. */ + ADI_PWR_HFOSC_DIV_BY_4, + /*! Divide by 8. */ + ADI_PWR_HFOSC_DIV_BY_8, + /*! Divide by 16. */ + ADI_PWR_HFOSC_DIV_BY_16, + /*! Divide by 32. */ + ADI_PWR_HFOSC_DIV_BY_32 + +} ADI_PWR_HFOSC_DIV; + + /*! + ***************************************************************************** + * Power driver API return codes + *****************************************************************************/ +typedef enum +{ + /*! No error detected. */ + ADI_PWR_SUCCESS = 0, + /*! Generic unknown error occurred. */ + ADI_PWR_FAILURE, + /*! If the given pointer is pointing to NULL. */ + ADI_PWR_NULL_POINTER, + /*! Requested divide value is out of range. */ + ADI_PWR_INVALID_CLOCK_DIVIDER, + /*! Invalid ADI_CLOCK_ID specified. */ + ADI_PWR_INVALID_CLOCK_ID, + /*! PDIV:HDIV ratio must be integral. */ + ADI_PWR_INVALID_CLOCK_RATIO, + /*! Invalid low-power mode requested. */ + ADI_PWR_INVALID_POWER_MODE, + /*! Invalid clock speed. */ + ADI_PWR_INVALID_CLOCK_SPEED, + /*! Specified operation is not allowed. */ + ADI_PWR_OPERATION_NOT_ALLOWED, + /*! Parameter is out of range. */ + ADI_PWR_INVALID_PARAM, + /*! System not initialized, call the API SystemInit. */ + ADI_PWR_SYSTEM_NOT_INITIALIZED + +} ADI_PWR_RESULT; + +/*! + * Enumeration of the power modes supported by the processor. + */ +typedef enum +{ + /*! Core Sleep power-down mode. */ + ADI_PWR_MODE_FLEXI = 0 << BITP_PMG_PWRMOD_MODE, + /*! Fully Active. (piggy-back on bitmode value "1", normally reserved) */ + ADI_PWR_MODE_ACTIVE = 1 << BITP_PMG_PWRMOD_MODE, + /*! Full Hibernate power-down mode. */ + ADI_PWR_MODE_HIBERNATE = 2 << BITP_PMG_PWRMOD_MODE, + /*! System Sleep power-down mode. */ + ADI_PWR_MODE_SHUTDOWN = 3 << BITP_PMG_PWRMOD_MODE + +} ADI_PWR_POWER_MODE; + + +/*! + * Enumeration of power management interrupts. + */ +typedef enum +{ + /*! Interrupt when battery voltage drops below 1.8V.*/ + ADI_PWR_LOW_BATTERY_VOLTAGE_IEN = 1 << BITP_PMG_IEN_VBAT, + /*! Interrupt when VREG under-voltage: below 1V. */ + ADI_PWR_UNDER_VOLATAGE_IEN = 1 << BITP_PMG_IEN_VREGUNDR, + /*! Interrupt when VREG over-voltage: over- 1.32V. */ + ADI_PWR_OVER_VOLATAGE_IEN = 1 << BITP_PMG_IEN_VREGOVR, + /*! Interrupt when battery voltage falls to the specified range.Please see #adi_pwr_SetVoltageRange.*/ + ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN = 1 << BITP_PMG_IEN_IENBAT + +} ADI_PWR_PMG_IRQ; + + +/*! + * Enumeration of system clock module interrupts. + */ +typedef enum +{ + /*! Interrupt for root clock monitor and Clock Fail. */ + ADI_PWR_ROOT_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_ROOT_MON_EN, + /*! Interrupt for LFXTAL clock monitor and Clock Fail. */ + ADI_PWR_LFXTAL_CLOCK_MON_IEN = 1 << BITP_CLKG_OSC_CTL_LFX_MON_EN, + /*! Interrupt when LFXTAL clock becomes stable/unstable. */ + ADI_PWR_LFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_LFXTALIE, + /*! Interrupt when HFXTAL clock becomes stable/unstable. */ + ADI_PWR_HFXTAL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL0_HFXTALIE, + /*! Interrupt when PLL-LOCK/PLL-UNLOCK. */ + ADI_PWR_PLL_STATUS_IEN = 1 << BITP_CLKG_CLK_CTL3_SPLLIE + +} ADI_PWR_CLOCK_IRQ; + +/** + * Enumeration of the power driver events notified through the callback. + */ +typedef enum +{ + /*! Event for indicating Over voltage VREG > 1.32v. */ + ADI_PWR_EVENT_VREG_OVER_VOLTAGE, + /*! Event for indicating under voltage VREG < 1V. */ + ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, + + /*! Event for indicating battery voltage below 1.8V. */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_LOW, + /*! Event for indicating battery voltage in specified range-1.VBAT range1 (> 2.75v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_1, + /*! Event for indicating battery voltage in specified range-2.VBAT range2 (2.75v - 2.3v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_2, + /*! Event for indicating battery voltage in specified range-3.VBAT range3 (2.3v - 1.6v). */ + ADI_PWR_EVENT_BATTERY_VOLTAGE_RANGE_3, + + /*! Event to indicate that LFXTAL failed and hardware automatically switched to LFOSC. */ + ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, + /*! Event to indicate the LFXTAL clock is not stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, + /*! Event to indicate the Root clock is not stable. */ + ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, + /*! Event to indicate the Root clock failed and hardware automatically switched to HFOSC. */ + ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, + + /*! Event to indicate HF crystal stable. */ + ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK, + /*! Event to indicate HF crystal is not stable. */ + ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK, + /*! Event to indicate LF crystal is stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK, + /*! Event to indicate LF crystal is not stable. */ + ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK, + /*! Event for indicating PLL is locked. */ + + ADI_PWR_EVENT_PLLC_LOCK, + /*! Event for indicating PLL is unlocked. */ + ADI_PWR_EVENT_PLLC_UNLOCK + +} ADI_PWR_EVENT; + + +/*! + * Enumeration of processor wake up status. +*/ +typedef enum +{ + /*! Interrupt from External Interrupt 0. */ + ADI_PWR_INT_EXT0, + /*! Interrupt from External Interrupt 1. */ + ADI_PWR_INT_EXT1, + /*! Interrupt from External Interrupt 2. */ + ADI_PWR_INT_EXT2, + /*! Interrupt from RTC. */ + ADI_PWR_INT_RTC + +} ADI_PWR_WAKEUP_STATUS; + +/*! + * Enumeration of the battery voltage ranges for voltage monitoring interrupt generation. +*/ +typedef enum +{ + /*! Voltage range is in safe region. */ + ADI_PWR_BAT_VOLTAGE_RANGE_SAFE, + /*! Battery voltage is in the range of 2.2 to 2.75 V. */ + ADI_PWR_VOLTAGE_RANGE_2_2_TO_2_75, + /*! Battery voltage is in the range of 1.6 to 2.2 V. */ + ADI_PWR_VOLTAGE_RANGE_1_6_TO_2_2 +} ADI_PWR_VOLTAGE_RANGE; + +/*! + * Enumeration of LFXTAL Robust Mode Load select. The amount of loading tolerated when + * LFXTAL robust mode is selected, that is when LFXTAL robust mode is enabled. + */ +typedef enum +{ + /*! No Trim, and big resistive loads not tolerated. */ + ADI_PWR_LFXTAL_LOAD_NONE, + /*! 20 MOHM Load mode, greater than 20 MOHM load allowed. */ + ADI_PWR_LFXTAL_LOAD_20MOHM, + /*! 10 MOHM Load mode, greater than 10 MOHM load allowed. */ + ADI_PWR_LFXTAL_LOAD_10MOHM, + /*! 5 MOHM load resistance allowed on both IO pins, the user can scale the current + down if the load is expected to be smaller than 5 MOHM. */ + ADI_PWR_LFXTAL_LOAD_5MOHM + +}ADI_PWR_LFXTAL_LOAD; + +/*! +* Enumeration of HP Buck load modes. The modes can be used to choose the loading capability +* of the HPBUCK. The low load mode and high load mode are based on the loading in the system. +*/ +typedef enum +{ + /*! HPBUCK Low load mode. This mode can be set if the maximum system clock(HCLK) frequency + is 26 MHz. */ + ADI_PWR_HPBUCK_LD_MODE_LOW, + + /*! HPBUCK High load mode. This mode can be set if the system clock(HCLK) frequency is greater + than 26 MHz. */ + ADI_PWR_HPBUCK_LD_MODE_HIGH + +}ADI_PWR_HPBUCK_LD_MODE; + +/* Related clock APIs */ + +/* + * Initialize the dynamic power management service + */ +ADI_PWR_RESULT adi_pwr_Init(void); + +/* + * ================================================================= + * Clock Management related APIs + * ================================================================= +*/ + +/* + * Update the internal clock variable based on current configuration + */ +ADI_PWR_RESULT adi_pwr_UpdateCoreClock(void); + +/* + * Set the external clock frequency. + */ +ADI_PWR_RESULT adi_pwr_SetExtClkFreq( + const uint32_t ExtClkFreq + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetRootClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetPLLClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * To Configure the root clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetLFClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + + +/* + * To Enable/Disable the LFXTAL robust mode. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( + const bool bEnable + ); + +/* + * To configure the LFXTAL robust mode load. + */ +ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( + const ADI_PWR_LFXTAL_LOAD eLoad + ); + +/* + * To Enable/Disable the LFXTAL Fail Auto switch. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( + const bool bEnable + ); + +/* + * To enable/disable auto switching of root clock to HFOSC upon detection + * of Root clock failure. + */ +ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( + const bool bEnable + ); + +/* + * To set the HF Oscillator divide factor + */ +ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( + const ADI_PWR_HFOSC_DIV eDivFactor + ); + +/* + * To set the HF oscillator automatic divide by 1 during wakeup from Flexi mode + */ +ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( + const bool bEnable + ); + +/* + * To Configure the reference clock muxing + */ +ADI_PWR_RESULT adi_pwr_SetRefClockMux( + const ADI_CLOCK_MUX_ID eClockID + ); + +/* + * Get external clock frequency. + */ +ADI_PWR_RESULT adi_pwr_GetExtClkFreq( + uint32_t *pExtClock + ); + +/* + * Get current clock frequency. This API can be used to know PCLK, HCLK. + */ +ADI_PWR_RESULT adi_pwr_GetClockFrequency( + const ADI_CLOCK_ID eClockId, + uint32_t *pClock + ); +/* + * To enable/disable the specific clock. + */ +ADI_PWR_RESULT adi_pwr_EnableClock( + const ADI_CLOCK_GATE eClockGate, + const bool bEnable + ); + +/* + * To enable/disable the specific clock source. + */ +ADI_PWR_RESULT adi_pwr_EnableClockSource( + const ADI_CLOCK_SOURCE_ID eClockSource, + const bool bEnable + ); +/* + * To set the specific clock divider. +*/ +ADI_PWR_RESULT adi_pwr_SetClockDivider( + const ADI_CLOCK_ID eClockId, + const uint16_t nDiv + ); +/* + * To Get the clock status. +*/ +ADI_PWR_RESULT adi_pwr_GetClockStatus( + const ADI_CLOCK_SOURCE_ID eClockSource, + ADI_CLOCK_SOURCE_STATUS *peStatus + ); +/* + * To configure the PLL to generate the SPLL +*/ +ADI_PWR_RESULT adi_pwr_SetPll( + uint8_t nDivFactor, + const uint8_t nMulFactor, + const bool bDiv2, + const bool bMul2 + ); + +/* To enable the interrupt for clock monitoring LFXTAL/HFXTAL/PLL.*/ +ADI_PWR_RESULT adi_pwr_EnableClockInterrupt( + const ADI_PWR_CLOCK_IRQ eIrq, + const bool bEnable + ); + +/* Enabling the LFXTAL bypass mode */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass( + const bool bEnable + ); + + +/* Set the clock output through the GPIO */ +ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput( + const ADI_CLOCK_OUTPUT_ID eClockOutput + ); + +/* + * ================================================================= + * Power Management related APIs + * ================================================================= +*/ +/* To enable the interrupt for voltage monitoring.*/ +ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt( + const ADI_PWR_PMG_IRQ eIrq, + const bool bEnable + ); + +/* + * To know which is interrupt caused the processor to wake up from SHUTDOWN mode. + */ +ADI_PWR_RESULT adi_pwr_GetWakeUpStatus( + ADI_PWR_WAKEUP_STATUS *peStatus + ); + +/* + * To select the voltage range of the battery for monitoring. +*/ +ADI_PWR_RESULT adi_pwr_SetVoltageRange( + const ADI_PWR_VOLTAGE_RANGE eRange + ); + +/* + * For entering the low power mode. +*/ +ADI_PWR_RESULT adi_pwr_EnterLowPowerMode( + const ADI_PWR_POWER_MODE PowerMode, + uint32_t volatile * pnInterruptOccurred, + const uint8_t PriorityMask + ); + +/* + * For exiting the low power mode. +*/ +ADI_PWR_RESULT adi_pwr_ExitLowPowerMode( + uint32_t volatile * pnInterruptOccurred + ); + +/* To enable the HPBUCK */ +ADI_PWR_RESULT adi_pwr_EnableHPBuck( + const bool bEnable + ); + + +/* To enable the HPBUCK Low Power mode */ +ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( + const bool bEnable + ); + +/* To enable the HPBUCK Load mode */ +ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( + const ADI_PWR_HPBUCK_LD_MODE eLoadMode + ); + +/* + * For registering the call back function . +*/ +ADI_PWR_RESULT adi_pwr_RegisterCallback( + const ADI_CALLBACK pfCallback, + void *pcbParam + ); + +#ifdef __cplusplus +} +#endif + +#endif /* ADI_PWR_H */ + + +/*@}*/ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h new file mode 100755 index 00000000000..f5101ef6901 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rng/adi_rng.h @@ -0,0 +1,204 @@ +/*! + ***************************************************************************** + @file adi_rng.h + @brief Random Number Generator Driver + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup RNG_Driver RNG Driver + * Random Number Generator Driver + * @{ + */ + +#ifndef ADI_RNG_H +#define ADI_RNG_H + +#include +#include + +#ifndef __ADUCM4x50__ +#error "Unsupported processor" +#endif + +#include + +#ifdef __ICCARM__ +/* IAR MISRA C 2004 error suppressions. + * + * Pm011 (rule 6.3): The basic types of char, int, long, float cannot be used. + * bool is used in the APIs as it is not affending the rule. Disabling this as IAR treats it as an error. + */ +#pragma diag_suppress=Pm011 +#endif /* __ICCARM__ */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! + * \enum ADI_RNG_RESULT + * Random Number Generator API return codes + */ +typedef enum +{ + ADI_RNG_SUCCESS = 0, /*!< No Error, API suceeded */ + ADI_RNG_UNKNOWN_ERROR, /*!< Unknown error detected */ + ADI_RNG_ALREADY_INITIALIZED, /*!< RNG is already initialized */ + ADI_RNG_INVALID_PARAM, /*!< Invalid function parameter */ + ADI_RNG_BAD_DEV_HANDLE, /*!< Invalid device handle passed */ + ADI_RNG_BAD_DEVICE_NUM, /*!< Invalid device instance */ + ADI_RNG_NOT_INITIALIZED, /*!< RNG not yet initialized */ + ADI_RNG_INVALID_STATE /*!< Device is in an invalid state */ +} ADI_RNG_RESULT; + +/*! + * \enum ADI_RNG_EVENT + * Random Number Generator callback events + */ +typedef enum +{ + ADI_RNG_EVENT_READY, /*!< Random number ready event */ + ADI_RNG_EVENT_STUCK /*!< The ring oscillator got stuck event */ +} ADI_RNG_EVENT; + + +/*! The amount of application supplied memory required by the RNG driver */ +#define ADI_RNG_MEMORY_SIZE (12u) + + +/*! RNG Device handle typedef */ +typedef void* ADI_RNG_HANDLE; + +/*================ E X T E R N A L S ==================*/ + +/* + * RNG API + */ + +/* Open a random number generator device */ +extern ADI_RNG_RESULT adi_rng_Open( + uint32_t const nDeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_RNG_HANDLE* const phDevice + ); + +/* Close the RNG Device */ +extern ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice); + +/* Enable/Disable the device */ +extern ADI_RNG_RESULT adi_rng_Enable ( + ADI_RNG_HANDLE const hDevice, + bool const bFlag + ); +/* Enable/Disable buffering */ +extern ADI_RNG_RESULT adi_rng_EnableBuffering ( + ADI_RNG_HANDLE const hDevice, + bool const bFlag + ); + +/* Set the sample length */ +extern ADI_RNG_RESULT adi_rng_SetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t const nLenPrescaler, + uint16_t const nLenReload + ); + +/* Get whether the random number is ready */ +extern ADI_RNG_RESULT adi_rng_GetRdyStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ); + +/* Get whether the ring oscillator output is stuck or not */ +extern ADI_RNG_RESULT adi_rng_GetStuckStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ); + +/* Get the random number */ +extern ADI_RNG_RESULT adi_rng_GetRngData ( + ADI_RNG_HANDLE const hDevice, + uint32_t* const pRegData + ); + +/* Get the oscillator count */ +extern ADI_RNG_RESULT adi_rng_GetOscCount ( + ADI_RNG_HANDLE const hDevice, + uint32_t* const pOscCount + ); + +/* Get the oscillator count difference value */ +extern ADI_RNG_RESULT adi_rng_GetOscDiff ( + ADI_RNG_HANDLE const hDevice, + uint32_t const nIndex, + uint8_t* const pOscDiff + ); + +/* Register a callback */ +extern ADI_RNG_RESULT adi_rng_RegisterCallback ( + ADI_RNG_HANDLE hDevice, + ADI_CALLBACK cbFunc, + void *pCBParam + ); + +/* Retrieve the current RNG sample length prescale and reload value configured in the device. */ +extern ADI_RNG_RESULT adi_rng_GetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t* const pLenPrescaler, + uint16_t* const pLenReload + ); + +#ifdef __cplusplus +} +#endif + +#ifdef __ICCARM__ +#pragma diag_default=Pm011 +#endif /* __ICCARM__ */ +#endif /* include guard */ + +/* +** EOF +*/ + +/*@}*/ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h new file mode 100755 index 00000000000..739bc47dc0b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/rtc/adi_rtc.h @@ -0,0 +1,521 @@ +/*! + ***************************************************************************** + @file adi_rtc.h + @brief Primary include file for Real Time Clock Services. + @version $Revision: 29004 $ + @date $Date: 2014-12-06 10:37:26 -0500 (Sat, 06 Dec 2014) $ + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_RTC_H__ +#define ADI_RTC_H__ +#include "adi_processor.h" + +#include +#include +#include + +/*! \addtogroup RTC_Driver RTC Driver + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + + +/*! Amount of memory(In bytes) required by the RTC device driver for managing the operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_RTC_MEMORY_SIZE (24u) + +/*! Emergency flush command to gatweay register */ +#define ADI_RTC_GATEWAY_FLUSH 0xa2c5 + +/*! A device handle used in all API functions to identify the RTC device. */ +typedef void* ADI_RTC_HANDLE; + +/*! Interrupt bit position-1*/ +#define ADI_RTC_INTERRUPT_OFFSET 16 + +/*! Interrupt bit position-2*/ +#define ADI_RTC_INTERRUPT_OFFSET_IO_CAPTURE 21 + +/*! + * RTC API return codes + */ +typedef enum +{ + /*! No Error, API succeeded */ + ADI_RTC_SUCCESS, + /*! Generic failure */ + ADI_RTC_FAILURE, + /*! RTC is in failsafe mode and not reliable */ + ADI_RTC_CLOCK_FAILSAFE, + /*! RTC is already initialized */ + ADI_RTC_IN_USE, + /*! Invalid device handle passed */ + ADI_RTC_INVALID_HANDLE, + /*! Asking to initialize an unknown instance */ + ADI_RTC_INVALID_INSTANCE, + /*! Parameter is out of range */ + ADI_RTC_INVALID_OPTION, + /*! Specified operation not allowed */ + ADI_RTC_OPERATION_NOT_ALLOWED, + /*! One of the parameters is invalid */ + ADI_RTC_INVALID_PARAM, + /*! Input/SensorStrobe channel is invalid for the specified operation */ + ADI_RTC_INVALID_CHANNEL + +} ADI_RTC_RESULT; + + +/*! + * RTC Interrupt Enable Bits. + */ + + +typedef uint32_t ADI_RTC_INT_TYPE; + +#define ADI_RTC_ALARM_INT 0x00000001u /*!< Alarm interrupt enable bit */ +#define ADI_RTC_MOD60ALM_INT 0x00000002u /*!< modulo 60 Alarm interrupt enable */ +#define ADI_RTC_ISO_DONE_INT 0x00000004u /*!< Power isolation done interrupt enable */ +#define ADI_RTC_WRITE_PENDERR_INT 0x00000008u /*!< Write pend error interrupt enable */ +#define ADI_RTC_WRITE_SYNC_INT 0x00000010u /*!< Write sync interrupt enable */ +#define ADI_RTC_WRITE_PEND_INT 0x00000020u /*!< Write pend interrupt enable */ +#define ADI_RTC_COUNT_INT 0x00000040u /*!< RTC count interrupt source enable */ +#define ADI_RTC_PSI_INT 0x00000080u /*!< Precaled Module 1 interrupt */ +#define ADI_RTC_TRIM_INT 0x00000100u /*!< Enable for the RTC trim interrupt source */ +#define ADI_RTC_COUNT_ROLLOVER_INT 0x00000200u /*!< Enable for the RTC count roll-over interrupt source */ +#define ADI_RTC_MOD60_ROLLOVER_INT 0x00000400u /*!< Enable for the RTC modulo-60 count roll-over interrupt source */ +#define ADI_RTC_SENSOR_STROBE_CH1_INT 0x00000800u /*!< Enable interrupt for sensor strobe channel -1*/ +#define ADI_RTC_SENSOR_STROBE_CH2_INT 0x00001000u /*!< Enable interrupt for sensor strobe channel -2*/ +#define ADI_RTC_SENSOR_STROBE_CH3_INT 0x00002000u /*!< Enable interrupt for sensor strobe channel -3*/ +#define ADI_RTC_SENSOR_STROBE_CH4_INT 0x00004000u /*!< Enable interrupt for sensor strobe channel -4*/ +#define ADI_RTC_INPUT_CAPTURE_CH0_INT 0x00008000u /*!< Enable interrupt for input capture channel -0*/ +#define ADI_RTC_INPUT_CAPTURE_CH2_INT 0x00010000u /*!< Enable interrupt for input capture channel -2*/ +#define ADI_RTC_INPUT_CAPTURE_CH3_INT 0x00020000u /*!< Enable interrupt for input capture channel -3*/ +#define ADI_RTC_INPUT_CAPTURE_CH4_INT 0x00040000u /*!< Enable interrupt for input capture channel -4*/ +#define ADI_RTC_LFXTL_FAILURE_INT 0x00080000u /*!< Interrupt for LFXTL failure. LFXTL failure interrupt is mapped to RTC1 interrupt.*/ +#define ADI_RTC_RTCSS4_FE_INT 0x00100000u /*!< Enable interrupt for Sensor Strobe channel 3*/ +#define ADI_RTC_RTCSS3_FE_INT 0x00200000u /*!< Enable interrupt for Sensor Strobe channel 3*/ +#define ADI_RTC_RTCSS2_FE_INT 0x00400000u /*!< Enable interrupt for Sensor Strobe channel 2*/ +#define ADI_RTC_RTCSS1_FE_INT 0x00800000u /*!< Enable interrupt for Sensor Strobe channel 2*/ +#define ADI_RTC_RTCSS4MSKEN 0x01000000u /*!< Enable interrupt for Sensor Strobe channel 4 Mask */ +#define ADI_RTC_RTCSS3MSKEN 0x02000000u /*!< Enable interrupt for Sensor Strobe channel 3 Mask */ +#define ADI_RTC_RTCSS2MSKEN 0x04000000u /*!< Enable interrupt for Sensor Strobe channel 2 Mask */ +#define ADI_RTC_RTCSS1MSKEN 0x08000000u /*!< Enable interrupt for Sensor Strobe channel 1 Mask */ +#define ADI_RTC_CR5OCS_SS3SMPMTCHIRQEN 0x10000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 3 */ +#define ADI_RTC_CR5OCS_SS2SMPMTCHIRQEN 0x20000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 2 */ +#define ADI_RTC_CR5OCS_SS1SMPMTCHIRQEN 0x40000000u /*!< Sample activity Interrupt enable for RTC Sensor Strobe Channel 1. */ + + +#define ADI_RTC_NUM_INTERRUPTS 31 /*!< Number of RTC interrupts. */ + + +/*! + * RTC Posted Write Status Bits. + */ +typedef enum +{ + /*! Posted write control register-0 status bit */ + ADI_RTC_WRITE_STATUS_CONTROL0 = 1 << BITP_RTC_SR0_WSYNCCR0, + /*! Posted write status0 register status bit */ + ADI_RTC_WRITE_STATUS_STATUS0 = 1 << BITP_RTC_SR0_WSYNCSR0, + /*! Posted write count0 register status bit */ + ADI_RTC_WRITE_STATUS_COUNT0 = 1 << BITP_RTC_SR0_WSYNCCNT0, + /*! Posted write count1 register status bit */ + ADI_RTC_WRITE_STATUS_COUNT1 = 1 << BITP_RTC_SR0_WSYNCCNT1, + /*! Posted write alarm0 register status bit */ + ADI_RTC_WRITE_STATUS_ALARM0 = 1 << BITP_RTC_SR0_WSYNCALM0, + /*! Posted write alarm1 register status bit */ + ADI_RTC_WRITE_STATUS_ALARM1 = 1 << BITP_RTC_SR0_WSYNCALM1, + /*! Posted write trim register status bit */ + ADI_RTC_WRITE_STATUS_TRIM = 1 << BITP_RTC_SR0_WSYNCTRM +} ADI_RTC_WRITE_STATUS; + + +/*! + * RTC Trim intervals. + */ +typedef enum +{ + /*! Trim interval is 2^2 seconds */ + ADI_RTC_TRIM_INTERVAL_2 = (2 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^3 seconds */ + ADI_RTC_TRIM_INTERVAL_3 = (3 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^4 seconds */ + ADI_RTC_TRIM_INTERVAL_4 = (4 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^5 seconds */ + ADI_RTC_TRIM_INTERVAL_5 = (5 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^6 seconds */ + ADI_RTC_TRIM_INTERVAL_6 = (6 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^7 seconds */ + ADI_RTC_TRIM_INTERVAL_7 = (7 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^8 seconds */ + ADI_RTC_TRIM_INTERVAL_8 = (8 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^9 seconds */ + ADI_RTC_TRIM_INTERVAL_9 = (9 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^10 seconds */ + ADI_RTC_TRIM_INTERVAL_10 = (10 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^11 seconds */ + ADI_RTC_TRIM_INTERVAL_11 = (11 << BITP_RTC_TRM_IVL2EXPMIN | 0x1 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^12 seconds */ + ADI_RTC_TRIM_INTERVAL_12 = (12 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^13 seconds */ + ADI_RTC_TRIM_INTERVAL_13 = (13 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^14 seconds */ + ADI_RTC_TRIM_INTERVAL_14 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x0 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^15 seconds */ + ADI_RTC_TRIM_INTERVAL_15 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x1 << BITP_RTC_TRM_IVL), + /*! Trim interval is 2^16 seconds */ + ADI_RTC_TRIM_INTERVAL_16 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x2 << BITP_RTC_TRM_IVL ), + /*! Trim interval is 2^17 seconds */ + ADI_RTC_TRIM_INTERVAL_17 = (14 << BITP_RTC_TRM_IVL2EXPMIN | 0x3 << BITP_RTC_TRM_IVL) + +} ADI_RTC_TRIM_INTERVAL; + +/*! + * RTC input capture channels. + */ +typedef enum +{ + /*! Input capture channel-0 */ + ADI_RTC_INPUT_CHANNEL_0 = 1 << BITP_RTC_CR2IC_IC0EN, + /*! Input capture channel-2 */ + ADI_RTC_INPUT_CHANNEL_2 = 1 << BITP_RTC_CR2IC_IC2EN, + /*! Input capture channel-3 */ + ADI_RTC_INPUT_CHANNEL_3 = 1 << BITP_RTC_CR2IC_IC3EN, + /*! Input capture channel-4 */ + ADI_RTC_INPUT_CHANNEL_4 = 1 << BITP_RTC_CR2IC_IC4EN + +}ADI_RTC_INPUT_CHANNEL; + +/*! + * RTC Sensor Strobe channels. + */ +typedef enum +{ + /*! Sensor Strobe channel-1 */ + ADI_RTC_SS_CHANNEL_1 = 1 << BITP_RTC_CR3SS_SS1EN, + /*! Sensor Strobe channel-2 */ + ADI_RTC_SS_CHANNEL_2 = 1 << BITP_RTC_CR3SS_SS2EN, + /*! Sensor Strobe channel-3 */ + ADI_RTC_SS_CHANNEL_3 = 1 << BITP_RTC_CR3SS_SS3EN, + /*! Sensor Strobe channel-4 */ + ADI_RTC_SS_CHANNEL_4 = 1 << BITP_RTC_CR3SS_SS4EN, + +}ADI_RTC_SS_CHANNEL; + +/*! + * RTC Trim polarity. + */ +typedef enum +{ + /*! Trim value is added every trim interval */ + ADI_RTC_TRIM_ADD = (1 << BITP_RTC_TRM_ADD), + /*! Trim value is subtracted every trim interval */ + ADI_RTC_TRIM_SUB = (0 << BITP_RTC_TRM_ADD), +} ADI_RTC_TRIM_POLARITY; + +/*! + * RTC Trim values. + */ +typedef enum +{ + /*! Trim value is +/- 0 */ + ADI_RTC_TRIM_0 = (0 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 1 */ + ADI_RTC_TRIM_1 = (1 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 2 */ + ADI_RTC_TRIM_2 = (2 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 3 */ + ADI_RTC_TRIM_3 = (3 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 4 */ + ADI_RTC_TRIM_4 = (4 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 5 */ + ADI_RTC_TRIM_5 = (5 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 6 */ + ADI_RTC_TRIM_6 = (6 << BITP_RTC_TRM_VALUE), + /*! Trim value is +/- 7 */ + ADI_RTC_TRIM_7 = (7 << BITP_RTC_TRM_VALUE) +} ADI_RTC_TRIM_VALUE; + +/*! + * RTC control register set. + */ +typedef enum +{ + /*! Specify the RTC-Control register-0 */ + ADI_RTC_CONTROL_REGISTER_0, + /*! Specify the RTC-Control register-1 */ + ADI_RTC_CONTROL_REGISTER_1 +} ADI_RTC_CONTROL_REGISTER; + +/*================ E X T E R N A L S ==================*/ + +/* + */ + +/*************************************/ +/* RTC API */ +/*************************************/ +ADI_RTC_RESULT adi_rtc_Open( + uint32_t DeviceNumber, + void *pDeviceMemory, + uint32_t MemorySize, + ADI_RTC_HANDLE *phDevice + ); + +ADI_RTC_RESULT adi_rtc_Close( + ADI_RTC_HANDLE const hDevice + ); + +/*************************************/ +/* Enable APIs for RTC Device */ +/*************************************/ + +ADI_RTC_RESULT adi_rtc_EnableAlarm( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableMod60Alarm( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_Enable( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableInterrupts( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INT_TYPE Interrupts, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableTrim( + ADI_RTC_HANDLE const hDevice, + bool bEnable + ); + +ADI_RTC_RESULT adi_rtc_EnableAutoReload( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableInputCapture ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eInpChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot ( + ADI_RTC_HANDLE const hDevice, + bool bEnable); + +/*************************************/ +/* Set APIs for RTC Device */ +/*************************************/ + + +ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod( + ADI_RTC_HANDLE const hDevice, + uint8_t nPeriod + ); + +ADI_RTC_RESULT adi_rtc_SetAlarm( + ADI_RTC_HANDLE const hDevice, + uint32_t nAlarm + ); + +ADI_RTC_RESULT adi_rtc_SetAlarmEx( + ADI_RTC_HANDLE const hDevice, + float fAlarm + ); + + +ADI_RTC_RESULT adi_rtc_SetControlRegister( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_CONTROL_REGISTER eRegister, + uint32_t Control + ); + +ADI_RTC_RESULT adi_rtc_SetCount( + ADI_RTC_HANDLE const hDevice, + uint32_t nCount + ); + +ADI_RTC_RESULT adi_rtc_SetGateway( + ADI_RTC_HANDLE const hDevice, + uint16_t Command + ); + + +ADI_RTC_RESULT adi_rtc_SetPreScale( + ADI_RTC_HANDLE const hDevice, + uint8_t nPreScale + ); + +ADI_RTC_RESULT adi_rtc_SetTrim( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_TRIM_INTERVAL eInterval, + ADI_RTC_TRIM_VALUE eTrimValue, + ADI_RTC_TRIM_POLARITY eOperation + ); + +ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint8_t nMask); + +ADI_RTC_RESULT adi_rtc_SetAutoReloadValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t nValue); + +ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity ( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eInpChannel, + bool bEnable); + +ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t nValue); + +/*************************************/ +/* Get APIs for RTC Device */ +/*************************************/ + +ADI_RTC_RESULT adi_rtc_GetAlarm ( + ADI_RTC_HANDLE hDevice, + uint32_t *pAlarm + ); + +ADI_RTC_RESULT adi_rtc_GetAlarmEx ( + ADI_RTC_HANDLE hDevice, + float *pAlarm); + +ADI_RTC_RESULT adi_rtc_GetControl ( + ADI_RTC_HANDLE hDevice, + ADI_RTC_CONTROL_REGISTER eRegister , + uint32_t *pControl); + +ADI_RTC_RESULT adi_rtc_GetTrim( + ADI_RTC_HANDLE hDevice, + ADI_RTC_TRIM_VALUE *peTrim + ); + +ADI_RTC_RESULT adi_rtc_GetCount( + ADI_RTC_HANDLE const hDevice, + uint32_t *pCount + ); + +ADI_RTC_RESULT adi_rtc_GetCountEx( + ADI_RTC_HANDLE const hDevice, + float *pfCount + ); + +ADI_RTC_RESULT adi_rtc_GetSnapShot( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eChannel, + uint32_t *pValue, + uint16_t *pFraction); + +ADI_RTC_RESULT adi_rtc_GetInputCaptureValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_INPUT_CHANNEL eChannel, + uint16_t *pValue); + +ADI_RTC_RESULT adi_rtc_GetWritePendStatus( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_WRITE_STATUS *pPendBits + ); + +ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_WRITE_STATUS *pSyncBits + ); + +ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue( + ADI_RTC_HANDLE const hDevice, + ADI_RTC_SS_CHANNEL eSSChannel, + uint16_t *pValue); + +ADI_RTC_RESULT adi_rtc_GetCountRegs( + ADI_RTC_HANDLE const hDevice, + uint32_t *pnCount, + uint32_t *pfCount); +/************************************************/ +/* RTC APIs for managing interrupt/sync */ +/***********************************************/ + +ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites( + ADI_RTC_HANDLE const hDevice + ); + +ADI_RTC_RESULT adi_rtc_RegisterCallback( + ADI_RTC_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBparam + ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_RTC_H__ */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h new file mode 100755 index 00000000000..f3aa1118c2a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/spi/adi_spi.h @@ -0,0 +1,386 @@ +/*! ***************************************************************************** + * @file adi_spi.h + * @brief Main include file for SPI Device driver definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here.ADI_SEM_SIZE + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_SPI_H__ +#define ADI_SPI_H__ + +#include +#include +#include + +/** @addtogroup SPI_Driver SPI Driver + * @{ + */ + + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*! Amount of memory(In bytes) required by the SPI device driver for managing the operation + * of a SPI controller. The memory is passed to the driver when the driver is opened. + * The memory is completely owned by the driver till the the driver is closed. + * + */ + +#define ADI_SPI_MEMORY_SIZE (40u + ADI_SEM_SIZE) + + +/*! + ***************************************************************************** + * \enum ADI_SPI_RESULT + * + * SPI Device Error Codes. #ADI_SPI_SUCCESS is always zero + * The return value of all SPI APIs returning #ADI_SPI_RESULT + * should always be tested at the application level for success or failure. + * + *****************************************************************************/ +typedef enum +{ + /*! Generic success. */ + ADI_SPI_SUCCESS, + /*! Generic Failure. */ + ADI_SPI_FAILURE, + /*! SPI device is already initialized. */ + ADI_SPI_IN_USE, + /*! Invalid device handle. */ + ADI_SPI_INVALID_HANDLE, + /*! Invalid device ID. */ + ADI_SPI_INVALID_DEVICE_NUM, + /*! DMA configuration failure. */ + ADI_SPI_DMA_ERROR , + /*! NULL data pointer not allowed. */ + ADI_SPI_INVALID_POINTER, + /*! Parameter is out of range. */ + ADI_SPI_INVALID_PARAM, + /*! Unsupported mode of operation. */ + ADI_SPI_UNSUPPORTED_MODE, + /*! Semaphore in error . */ + ADI_SPI_SEMAPHORE_FAILED, + /*! Invalid operation */ + ADI_SPI_INVALID_OPERATION, + /*! Buffer Not submitted */ + ADI_SPI_BUFFER_NOT_SUBMITTED, + /*! Could not obtain the system clock */ + ADI_SPI_BAD_SYS_CLOCK, + /*! Blocking PEND failed */ + ADI_SPI_PEND_FAILED, + /*! DMA callback register failed */ + ADI_SPI_DMA_REG_FAILED, + /*! Hardware error occurred */ + ADI_SPI_HW_ERROR_OCCURRED +} ADI_SPI_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_SPI_HW_ERRORS + * + * Enumeration of events notified in the application provided callback. + * More than one event can be recorded at a time so the enumerator symbols + * have to be assigned values of 2^N + *****************************************************************************/ +typedef enum +{ + /*!< The given buffer is processed. Application can use this event to submit + the next buffer to be transmitted. */ + ADI_SPI_HW_ERROR_NONE = 0u, + /*! Tx-underflow interrupt enable */ + ADI_SPI_HW_ERROR_TX_UNDERFLOW = 1u, + /*! Rx-overflow interrupt enable */ + ADI_SPI_HW_ERROR_RX_OVERFLOW = 2u, + /*! Rx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT = 4u, + /*! Tx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT = 8u, + /*! Rx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR = 16u, + /*! Tx DMA channel bus fault detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR = 32u, + /*! Rx DMA channel unkown error detected */ + ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR = 64u, + /*! Tx DMA channel unkown error detected */ + ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR = 128u + +} ADI_SPI_HW_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_SPI_CHIP_SELECT + * + * SPI Device Chip Select Enumeration. Allows designation of an external + * SPI slave device chip select pin to be driven by the SPI controller. + * Multiple external slave SPI devices may be present on a shared SPI bus, + * and the chip select pin allows each of them to be assigned dedicated selects. + * Use the #adi_spi_SetChipSelect() API to configure the active chip select. + * Note that SPI0 is an internal channel dedicated to the UHF controller and + * hence, has a dedicated SPI0 chip select pin that is not available externally. + * + *****************************************************************************/ +typedef enum +{ + /*! No Slave Chip Select for SPI. */ + ADI_SPI_CS_NONE = 0, + /*! CS0 Slave Chip Select for SPI. */ + ADI_SPI_CS0 = 1, + /*! CS1 Slave Chip Select for SPI. */ + ADI_SPI_CS1 = 2, + /*! CS2 Slave Chip Select for SPI. */ + ADI_SPI_CS2 = 4, + /*! CS3 Slave Chip Select for SPI. */ + ADI_SPI_CS3 = 8 +} ADI_SPI_CHIP_SELECT; + + +/*! SPI Device instance private data handle typedef. */ +typedef struct __ADI_SPI_DEV_DATA_TYPE* ADI_SPI_HANDLE; +/*! SPI Device instance private data handle typedef. 'const' version */ +typedef const struct __ADI_SPI_DEV_DATA_TYPE* ADI_SPI_CONST_HANDLE; + + +/*! + * \struct ADI_SPI_TRANSCEIVER + ***************************************************************************** + * SPI Device Command/Data Transceiver Structure. Data structure used by + * the #adi_spi_MasterReadWrite(),#adi_spi_MasterSubmitBuffer() + * API to convey all parameters, consisting of + * prologue, transmit and receive data and size, and buffer increment flags. + * DMA and Half-Duplex operation are also specified in this structure as T/F. + * + * Each call to #adi_spi_MasterReadWrite or #adi_spi_MasterSubmitBuffer() must populate the following fields of the + * ADI_SPI_TRANSCEIVER block: + * + * @par TransmitterBytes + * The number of bytes to be transmitted. If the value is zero, data will not be transmitted from the + * buffer pointed by pTransmitter. + * + * @par ReceiverBytes + * The number of bytes to be received. If the value is zero, data will not be stored in the + * buffer pointed by pReceiver. + * + * @par pTransmitter + * Pointer to the application-defined transmit data buffer. This is the data sent out + * over the SPI transmit wire (MOSI for Master-mode, MISO for Slave-mode) during the SPI transaction. + * For SPI DMA mode (which is 16-bit based), the transmit buffer must be 16-bit aligned. + * + * @par pReceiver + * Pointer to the application-defined receive data buffer. This is where the receive data + * will be stored from the SPI receive wire (MISO for Master-mode, MOSI for Slave-mode) + * during the SPI transaction. + * For SPI DMA mode (which is 16-bit based), the receive buffer must be 16-bit aligned. + * + * @par bTxIncrement + * Increment to be done for the transmit buffer after every transaction . The transmit data buffer + * pointer is advanced as each byte is sent. If it is set to zero, the transmit data pointer is stationary. + * A stationary buffer pointer is useful for sending the same data to an external device or if + * the source data is from a fixed memory address. + * + * @par bRxIncrement + * Increment to be done for the receive buffer. The transmit data buffer + * pointer is advanced as each byte is sent. If it is value is set to zero, the receive + * data pointer is stationary. A stationary buffer pointer is useful for monitoring commands + * from an external device or if the receive data is going to a fixed memory address. + * + * @par bDMA + * Indicate whether the transaction is to use DMA (true) or not (false). If using DMA SPI + * transactions are limited to 2048 bytes. If more than 2048 bytes are needed then the application + * must use multiple transactions (DMA ping pong mode is not supported in the driver). + * For SPI DMA mode (which is 16-bit based), TransmitterBytes/ReceiverBytes is rounded up to an + * even number by the SPI driver before submitting to DMA. + * Please align the buffer to 16 bit word boundary since the data transfer is 16bit. + * + * + * @par bRD_CTL + * Indicate whether the transaction should enable RD_CTL (true) or not (false). + * RD_CTL effectively provides half-duplex operation as outlined in the HRM. + + *****************************************************************************/ +typedef struct +{ + /*! Pointer to transmit data. */ + uint8_t* pTransmitter; + /*! Pointer to receive data. */ + uint8_t* pReceiver; + /*! Data size for TX(bytes). */ + uint16_t TransmitterBytes; + /*! Data size for RX(bytes). */ + uint16_t ReceiverBytes; + /*! Transmit pointer increment flag. */ + uint8_t nTxIncrement; + /*! Receive pointer increment flag. */ + uint8_t nRxIncrement; + /*! DMA mode operation */ + bool bDMA; + /*! RD_CTL, half-duplex, operation */ + bool bRD_CTL; + +} ADI_SPI_TRANSCEIVER; + + + +/****************************************************************************** + * SPI Device External API function prototypes + *****************************************************************************/ + +/* Device Initialization and Uninitialization Interfaces */ +ADI_SPI_RESULT adi_spi_Open( + uint32_t nDeviceNum, + void *pDevMemory, + uint32_t nMemorySize, + ADI_SPI_HANDLE* const phDevice + ); + +ADI_SPI_RESULT adi_spi_Close( + ADI_SPI_HANDLE const hDevice + ); + +/****************************************************************** + * Eliminatable functions that may be optimized out by the linker * + *****************************************************************/ + +ADI_SPI_RESULT adi_spi_MasterReadWrite( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + + +ADI_SPI_RESULT adi_spi_SetMasterMode( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +/* Slave Mode APIs */ +ADI_SPI_RESULT adi_spi_SlaveReadWrite( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + +/* Command/Data transceiver API */ +ADI_SPI_RESULT adi_spi_MasterSubmitBuffer( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* const pXfr + ); + +ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_TRANSCEIVER* + const pXfr + ); + +ADI_SPI_RESULT adi_spi_RegisterCallback ( + ADI_SPI_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBParam + ); + + +/* Turn a non-blocking call into a blocking call. Wait for the transaction to complete */ +ADI_SPI_RESULT adi_spi_GetBuffer( + ADI_SPI_HANDLE const hDevice, + uint32_t * const pHWErrors + ); + +/* Query function for the data transfer completion */ +ADI_SPI_RESULT adi_spi_isBufferAvailable( + ADI_SPI_CONST_HANDLE const hDevice, + bool* const bComplete + ); + + + +ADI_SPI_RESULT adi_spi_SetContinuousMode( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + + +ADI_SPI_RESULT adi_spi_SetLoopback( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetIrqmode ( + ADI_SPI_CONST_HANDLE const hDevice, + const uint8_t nMode); + +ADI_SPI_RESULT adi_spi_SetReceiveOverflow( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +ADI_SPI_RESULT adi_spi_SetTransmitUnderflow( + ADI_SPI_CONST_HANDLE const hDevice, + const bool bFlag + ); + +/* Mode Configuration Interface */ +ADI_SPI_RESULT adi_spi_SetBitrate( + ADI_SPI_CONST_HANDLE const hDevice, + const uint32_t Hertz + ); +ADI_SPI_RESULT adi_spi_SetChipSelect( + ADI_SPI_HANDLE const hDevice, + const ADI_SPI_CHIP_SELECT eChipSelect + ); + +ADI_SPI_RESULT adi_spi_GetBitrate( + ADI_SPI_CONST_HANDLE const hDevice, + uint32_t* const pnBitrate + ); + + +#ifdef __cplusplus +} +#endif + + +/**@}*/ + + +#endif /* ADI_SPI_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h new file mode 100755 index 00000000000..aaf32f2cb0a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/sport/adi_sport.h @@ -0,0 +1,236 @@ +/*! **************************************************************************** + * @file adi_sport.h + * @brief SPORT (Serial Port) Device driver definitions + * @details Header File for the SPORT driver API functions and definitions + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ +#ifndef ADI_SPORT_H +#define ADI_SPORT_H + +/*============= I N C L U D E S =============*/ + +#include +#include +#include +#include + +/** @addtogroup SPORT_Driver SPORT Driver +* @{ +*/ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*============== D E F I N E S ===============*/ + +/** + * Amount of memory (bytes) required by the SPORT device driver for managing + * the operation in interrupt mode. This memory is completely owned by the + * driver till the end of the operation. + */ +#define ADI_SPORT_MEMORY_SIZE (76u + ADI_SEM_SIZE) + +typedef void* ADI_SPORT_HANDLE; /*!< Handle to the SPORT Device */ + +/** + * Enumeration of different channels of the SPORT + */ +typedef enum +{ + ADI_HALF_SPORT_A = 0, /*!< First half SPORT */ + ADI_HALF_SPORT_B = 1 /*!< Second half SPORT */ +} ADI_SPORT_CHANNEL; + +/** + * Enumeration for the direction of operation. + */ +typedef enum +{ + ADI_SPORT_DIR_RX, /*!< Sport in Rx mode */ + ADI_SPORT_DIR_TX /*!< Sport in Tx mode */ +} ADI_SPORT_DIRECTION; + +/** + * Enumeration for enabling packing. + */ +typedef enum +{ + ADI_SPORT_NO_PACKING = 0, /*!< No Packing */ + ADI_SPORT_8BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_8BIT, /*!< 8-bit packing */ + ADI_SPORT_16BIT_PACKING = ENUM_SPORT_CTL_A_CTL_PACK_16BIT /*!< 16-Bit packing */ +} ADI_SPORT_PACKING_MODE; + +/** + * Enumeration for Hardware Error encountered by the SPORT device. + */ + typedef enum +{ + ADI_SPORT_HW_NO_ERR = 0x00, /*!< No Hardware error */ + ADI_SPORT_HW_ERR_RX_OVERFLOW = 0x02, /*!< Data overflow for Rx (same value as Tx underflow) */ + ADI_SPORT_HW_ERR_TX_UNDERFLOW = 0x02, /*!< Data underflow for Tx (same value as Rx overflow) */ + ADI_SPORT_HW_ERR_FS = 0x04, /*!< Frame sync error */ + ADI_SPORT_HW_ERR_SYSDATAERR = 0x10, /*!< System Data Error */ + + ADI_SPORT_EVENT_RX_BUFFER_PROCESSED = 0x20, /*!< Processed the submitted RX buffer */ + ADI_SPORT_EVENT_TX_BUFFER_PROCESSED = 0x40, /*!< Processed the submitted TX buffer */ + + ADI_SPORT_DMA_ERR_BUS = 0x100, /*!< SPORT DMA bus error detected */ + ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR = 0x200 /*!< SPORT DMA invalid descriptor error detected */ +}ADI_SPORT_EVENT; + + +/** + * Enumeration for result code returned from the SPORT device driver functions. + */ +typedef enum +{ + ADI_SPORT_SUCCESS, /*!< Success */ + ADI_SPORT_FAILED, /*!< Generic Failure to indicate a call to SPORT driver function returned unsuccessful */ + ADI_SPORT_INVALID_DEVICE_NUM , /*!< Invalid device number */ + ADI_SPORT_INVALID_NULL_POINTER, /*!< Specified pointer is invalid */ + ADI_SPORT_INVALID_HANDLE, /*!< The given handle is invalid */ + ADI_SPORT_INVALID_PARAMETER, /*!< Specified parameter is not valid */ + ADI_SPORT_DMA_REGISTER_FAILED, /*!< Registering DMA error handler failed */ + ADI_SPORT_DEVICE_IN_USE, /*!< The specified SPORT channel is already open and in use */ + ADI_SPORT_INVALID_CONFIGURATION, /*!< The SPORT configuration is invalid */ + ADI_SPORT_BUFFERS_NOT_SUBMITTED, /*!< Buffer submission failed */ + ADI_SPORT_INVALID_WORD_LENGTH, /*!< Invalid word size */ + ADI_SPORT_OPERATION_NOT_ALLOWED, /*!< Specified operation is not allowed when SPORT is transmitting/receiving data */ + ADI_SPORT_HW_ERROR /*!< SPORT hardware or DMA reports an error */ +} ADI_SPORT_RESULT; + +/*============= P U B L I C F U N C T I O N S =============*/ + +/* Opens a SPORT device */ +ADI_SPORT_RESULT adi_sport_Open( + const uint32_t nDevNum, + const ADI_SPORT_CHANNEL eChannel, + const ADI_SPORT_DIRECTION eDirection, + void *pMemory, + const uint32_t nMemSize, + ADI_SPORT_HANDLE * const phDevice + ); + +/* Closes a SPORT device */ +ADI_SPORT_RESULT adi_sport_Close( + ADI_SPORT_HANDLE const hDevice + ); + +/* Submits a buffer to the driver */ +ADI_SPORT_RESULT adi_sport_SubmitBuffer( + ADI_SPORT_HANDLE const hDevice, + void * const pBuffer, + uint32_t const nNumBytes, + bool const bDMA + ); + +/* Get the processed buffer from the driver */ +ADI_SPORT_RESULT adi_sport_GetBuffer( + ADI_SPORT_HANDLE const hDevice, + void ** const ppBuffer, + uint32_t * pHwError + ); + +/* Peek function to know whether an processed buffer is avilable */ +ADI_SPORT_RESULT adi_sport_IsBufferAvailable( + ADI_SPORT_HANDLE const hDevice, + bool * const pbAvailable + ); + +/* To register the callback function */ +ADI_SPORT_RESULT adi_sport_RegisterCallback( + ADI_SPORT_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void * const pCBparam + ); + +/* Configure the data */ +ADI_SPORT_RESULT adi_sport_ConfigData( + ADI_SPORT_HANDLE const hDevice, + const uint8_t nWordLength, + const ADI_SPORT_PACKING_MODE ePackMode, + const bool bLSBFirst + ); + +/* Configure the clock */ +ADI_SPORT_RESULT adi_sport_ConfigClock( + ADI_SPORT_HANDLE const hDevice, + const uint16_t nClockRatio, + const bool bUseIntlClock, + const bool bRisingEdge, + const bool bGatedClk + ); + +/* Configure the frame sync */ +ADI_SPORT_RESULT adi_sport_ConfigFrameSync( + ADI_SPORT_HANDLE const hDevice, + const uint16_t nFsDivisor, + const bool bFSRequired, + const bool bInternalFS, + const bool bDataFS, + const bool bActiveLowFS, + const bool bLateFS, + const bool bFSErrorOperation + ); + +/* To mux the half-SPORT; this makes the device to use FS and Clock from other half-SPORT */ +ADI_SPORT_RESULT adi_sport_MultiplexSportSignal( + ADI_SPORT_HANDLE const hDevice, + const bool bUseOtherFS, + const bool bUseOtherClk + ); + +/* To configure the SPORT in timer mode */ +ADI_SPORT_RESULT adi_sport_ConfigTimerMode( + ADI_SPORT_HANDLE const hDevice, + const uint8_t nFSDuration, + const uint8_t nWidth, + const bool bActiveLow + ); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ADI_SPORT_H */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h new file mode 100755 index 00000000000..9331593a126 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/tmr/adi_tmr.h @@ -0,0 +1,253 @@ +/*! ***************************************************************************** + * @file adi_tmr.h + * @brief GP and RGB timer device driver public header file + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_H +#define ADI_TMR_H + + +#include +#include +#include + + +/** @addtogroup TMR_Driver Timer Driver + * @{ + */ + + +/*! + ***************************************************************************** + * \enum ADI_TMR_RESULT + * Enumeration for result code returned from the timer device driver functions. + * The return value of all timer APIs returning #ADI_TMR_RESULT should always + * be tested at the application level for success or failure. + *****************************************************************************/ +typedef enum { + /*! Successful operation */ + ADI_TMR_SUCCESS, + /*! Bad device number supplied by user */ + ADI_TMR_BAD_DEVICE_NUM, + /*! Bad PWM output number supplied by user to #adi_tmr_ConfigPwm */ + ADI_TMR_BAD_PWM_NUM, + /*! Bad event number supplied by user to #adi_tmr_ConfigEvent */ + ADI_TMR_BAD_EVENT_ID, + /*! Bad timer configuration, reloading and free running are mutually exclusive options */ + ADI_TMR_BAD_RELOAD_CONFIGURATION, + /*! Setup or enable function called while the timer is running */ + ADI_TMR_OPERATION_NOT_ALLOWED, + /*! Timeout while waiting for busy bit to clear before writing control register */ + ADI_TMR_DEVICE_BUSY, + /*! User attempts to reload the timer when reloading has not been enabled */ + ADI_TMR_RELOAD_DISABLED, + /*! User attempts to read the current or captured count with a NULL pointer */ + ADI_TMR_NULL_POINTER +} ADI_TMR_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_TMR_DEVICE + * Enumeration for the hardware peripheral being used during the API call + *****************************************************************************/ +typedef enum { + /*! General purpose timer 0 */ + ADI_TMR_DEVICE_GP0 = 0u, + /*! General purpose timer 1 */ + ADI_TMR_DEVICE_GP1 = 1u, + /*! General purpose timer 2 */ + ADI_TMR_DEVICE_GP2 = 2u, + /*! RGB timer */ + ADI_TMR_DEVICE_RGB = 3u, + /*! Total number of devices (private) */ + ADI_TMR_DEVICE_NUM = 4u, +} ADI_TMR_DEVICE; + +/*! + ***************************************************************************** + * \enum ADI_TMR_EVENT + * Enumeration of events notified in the application provided callback. + *****************************************************************************/ +typedef enum { + /*! Timeout event occurred */ + ADI_TMR_EVENT_TIMEOUT = 0x01, + /*! Event capture event occurred */ + ADI_TMR_EVENT_CAPTURE = 0x02, +} ADI_TMR_EVENT; + +/*! + ***************************************************************************** + * \enum ADI_TMR_PRESCALER + * Prescale options when configuring the timer + *****************************************************************************/ +typedef enum { + /*! Count every 1 source clock periods */ + ADI_TMR_PRESCALER_1 = 0u, + /*! Count every 16 source clock periods */ + ADI_TMR_PRESCALER_16 = 1u, + /*! Count every 64 source clock periods */ + ADI_TMR_PRESCALER_64 = 2u, + /*! Count every 256 source clock periods */ + ADI_TMR_PRESCALER_256 = 3u, +} ADI_TMR_PRESCALER; + +/*! + ***************************************************************************** + * \enum ADI_TMR_CLOCK_SOURCE + * Source clock options when configuring the timer + *****************************************************************************/ +typedef enum { + /*! Use periphreal clock (PCLK) */ + ADI_TMR_CLOCK_PCLK = 0u, + /*! Use internal high frequency clock (HFOSC) */ + ADI_TMR_CLOCK_HFOSC = 1u, + /*! Use internal low frequency clock (LFOSC) */ + ADI_TMR_CLOCK_LFOSC = 2u, + /*! Use external low frequency clock (LFXTAL) */ + ADI_TMR_CLOCK_LFXTAL = 3u, +} ADI_TMR_CLOCK_SOURCE; + +/*! + ***************************************************************************** + * \enum ADI_TMR_PWM_OUTPUT + * RGB PWM outputs, used to specify which PWM output to configure. For the GP + * timers only #ADI_TMR_PWM_OUTPUT_0 is allowed. The RGB timer has all three + * outputs. + *****************************************************************************/ +typedef enum { + /*! PWM output 0 */ + ADI_TMR_PWM_OUTPUT_0 = 0u, + /*! PWM output 1 */ + ADI_TMR_PWM_OUTPUT_1 = 1u, + /*! PWM output 2 */ + ADI_TMR_PWM_OUTPUT_2 = 2u, + /*! Total number of outputs (private) */ + ADI_TMR_PWM_OUTPUT_NUM = 3u, +} ADI_TMR_PWM_OUTPUT; + +/*! + ***************************************************************************** + * \struct ADI_TMR_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigTimer when + * configuring the GP or RGB timer + *****************************************************************************/ +typedef struct { + /*! True to count up, false to count down */ + bool bCountingUp; + /*! True for periodic (specific load value), false for free running (0xFFFF) */ + bool bPeriodic; + /*! Prescaler */ + ADI_TMR_PRESCALER ePrescaler; + /*! Clock source */ + ADI_TMR_CLOCK_SOURCE eClockSource; + /*! Load value (only relent in periodic mode) */ + uint16_t nLoad; + /*! Asynchronous load value (only relevant in periodic mode, and when PCLK is used) */ + uint16_t nAsyncLoad; + /*! True to enable reloading, false to disable it (only relevant in periodic mode) */ + bool bReloading; + /*! True to enable sync bypass, false to disable it */ + bool bSyncBypass; +} ADI_TMR_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_TMR_EVENT_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigEvent when + * configuring event capture + *****************************************************************************/ +typedef struct { + /*! True to enable event capture, false to disable it */ + bool bEnable; + /*! True to reset the counter and prescaler when the selected event occurs, false to let it continue */ + bool bPrescaleReset; + /*! Event identifier, see hardware reference manual for details */ + uint8_t nEventID; +} ADI_TMR_EVENT_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_TMR_PWM_CONFIG + * Configuration structure to fill and pass to #adi_tmr_ConfigPwm when + * configuring pulse width modulation output + *****************************************************************************/ +typedef struct { + /*! PWM output */ + ADI_TMR_PWM_OUTPUT eOutput; + /*! True if match mode (configurable duty cycle), false if toggle mode (50% duty cycle) */ + bool bMatch; + /*! True for PWM idle high, false for PWM idle low */ + bool bIdleHigh; + /*! Match value, only applicable if in match mode */ + uint16_t nMatchValue; +} ADI_TMR_PWM_CONFIG; + +/****************************************************************************** + * PUBLIC API + * 1.) Eliminate functions that may be optimized out by the linker + * 2.) Ordered by designed function call sequence + *****************************************************************************/ + +/* Initialize timer driver */ +ADI_TMR_RESULT adi_tmr_Init (ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt); + +/* Configuration interface functions */ +ADI_TMR_RESULT adi_tmr_ConfigTimer (ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG timerConfig); +ADI_TMR_RESULT adi_tmr_ConfigEvent (ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG eventConfig); +ADI_TMR_RESULT adi_tmr_ConfigPwm (ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG pwmConfig ); + +/* Timer start and stop */ +ADI_TMR_RESULT adi_tmr_Enable (ADI_TMR_DEVICE const eDevice, bool bEnable); + +/* Read functions */ +ADI_TMR_RESULT adi_tmr_GetCurrentCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount); +ADI_TMR_RESULT adi_tmr_GetCaptureCount (ADI_TMR_DEVICE const eDevice, uint16_t *pCount); + +/* Reload function */ +ADI_TMR_RESULT adi_tmr_Reload (ADI_TMR_DEVICE const eDevice); + + +/*! @} */ + + +#endif /* ADI_TMR_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h new file mode 100755 index 00000000000..abb0bf3109a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/uart/adi_uart.h @@ -0,0 +1,498 @@ +/*! ***************************************************************************** + * @file adi_uart.h + * @brief UART device driver global include file. + * @details This a global file which includes a specific file based on the processor family. + * This included file will be containing UART device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_UART_H +#define ADI_UART_H + +/** @addtogroup UART_Driver UART Driver +* @{ +*/ + +/*! \cond PRIVATE */ + +/*============= I N C L U D E S =============*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! \endcond */ + +/*! Amount of memory(bytes) required by the UART device driver for operating unidirectionally(Either RX or TX). + * This memory is completely owned by the driver until the end of the operation. + */ +#define ADI_UART_UNIDIR_MEMORY_SIZE (48u + (60u + ADI_SEM_SIZE)) + +/*! Amount of memory(bytes) required by the UART device driver for operating bidirectionally(Both RX and TX). + * This memory is completely owned by the driver until the end of the operation. + */ +#define ADI_UART_BIDIR_MEMORY_SIZE (48u + (60u + ADI_SEM_SIZE)*2u) + +/*! + * Handle for managing the UART device typedef. + */ +typedef struct _ADI_UART_DEVICE* ADI_UART_HANDLE; + +/*! + * Handle for managing the UART device typedef 'const' version. + */ +typedef const struct _ADI_UART_DEVICE* ADI_UART_CONST_HANDLE; + +/*! + ***************************************************************************** + * \enum ADI_UART_DIRECTION + * Enumeration for the UART direction. + *****************************************************************************/ +typedef enum +{ + ADI_UART_DIR_TRANSMIT, /*!< UART is only transmitting. */ + + ADI_UART_DIR_RECEIVE, /*!< UART is only receiving. */ + + ADI_UART_DIR_BIDIRECTION /*!< UART in bidirectional. */ + +} ADI_UART_DIRECTION; + + +/*! + ***************************************************************************** + * \enum ADI_UART_EVENT + * Enumeration of events notified in the application provided callback. + *****************************************************************************/ + typedef enum +{ + ADI_UART_EVENT_RX_BUFFER_PROCESSED, /*!< Rx buffer is processed. */ + + ADI_UART_EVENT_TX_BUFFER_PROCESSED, /*!< Tx buffer is processed. */ + + ADI_UART_EVENT_NO_RX_BUFFER_EVENT, /*!< No Rx buffer but data is in FIFO. */ + + ADI_UART_EVENT_AUTOBAUD_COMPLETE, /*!< Autobaud is complete. */ + + ADI_UART_EVENT_HW_ERROR_DETECTED, /*!< Hardware error detected. */ + + ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED /*!< Autobaud error detected. */ + +}ADI_UART_EVENT; + + +/*! + ***************************************************************************** + * \enum ADI_UART_RESULT + * Enumeration for result code returned from the UART device driver functions. + * The return value of all UART APIs returning #ADI_UART_RESULT + * should always be tested at the application level for success or failure. + *****************************************************************************/ + typedef enum +{ + + ADI_UART_SUCCESS, /*!< Generic success. */ + + ADI_UART_FAILED, /*!< Generic failure. */ + + ADI_UART_SEMAPHORE_FAILED, /*!< Semaphore error. */ + + ADI_UART_INVALID_HANDLE, /*!< Invalid device handle. */ + + ADI_UART_DEVICE_IN_USE, /*!< UART device in use. */ + + ADI_UART_INVALID_DEVICE_NUM, /*!< Invalid device number. */ + + ADI_UART_INVALID_POINTER, /*!< NULL data pointer is not allowed. */ + + ADI_UART_INSUFFICIENT_MEMORY, /*!< Insufficent memory. */ + + ADI_UART_INVALID_DIR, /*!< Invalid UART direction. */ + + ADI_UART_OPERATION_NOT_ALLOWED, /*!< Invalid operation. */ + + ADI_UART_INVALID_PARAMETER, /*!< Invalid parameter. */ + + ADI_UART_BUFFER_NOT_SUBMITTED, /*!< Buffer not submitted. */ + + ADI_UART_INVALID_DATA_TRANSFER_MODE, /*!< Invalid transfer mode. + Adi_uart_Read()/adi_uart_Write() is used in nonblocking mode + or adi_uart_SubmitRxBuffer()/adi_uart_SubmitTxBuffer() + is used in blocking mode. */ + + ADI_UART_HW_ERROR_DETECTED, /*!< Hardware error detected. */ + + ADI_UART_AUTOBAUD_ERROR_DETECTED, /*!< Autobaud error detected. */ + + ADI_UART_ERR_DMA_REGISTER, /*!< Error while registering the DMA callback. */ + + ADI_UART_INVALID_DATA_SIZE /*!< Invalid transfer size. Must be less than 1025 bytes */ + +} ADI_UART_RESULT; + +/*! + ***************************************************************************** + * \enum ADI_UART_HW_ERRORS + * Enumeration for UART hardware errors. If hardware error(s) occur in + * either callback or interrupt mode, they are mapped to #ADI_UART_HW_ERRORS. + * Interpretation of the break condition is application specific. + *****************************************************************************/ +typedef enum +{ + ADI_UART_NO_HW_ERROR = 0x00, /*!< No hardware error. */ + + ADI_UART_HW_ERR_FRAMING = 0x10, /*!< Rx framing error. */ + + ADI_UART_HW_ERR_PARITY = 0x20, /*!< Rx parity error. */ + + ADI_UART_HW_ERR_OVERRUN = 0x40, /*!< Receive overrun. */ + + ADI_UART_BREAK_INTERRUPT = 0x80, /*!< Break condition. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT = 0x100, /*!< Rx DMA channel bus fault detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT = 0x200, /*!< Tx DMA channel bus fault detected. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR = 0x400, /*!< Rx DMA channel invalid descriptor detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR = 0x800, /*!< Tx DMA channel invalid descriptor detected. */ + + ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR = 0x1000, /*!< Rx DMA channel unknown error detected. */ + + ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR = 0x2000, /*!< Tx DMA channel unknown error detected. */ + +}ADI_UART_HW_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_UART_AUTOBAUD_ERRORS + * Enumeration for UART autobaud errors. If autobaud related error(s) occur + * they are mapped to #ADI_UART_AUTOBAUD_ERRORS. + *****************************************************************************/ +typedef enum +{ + ADI_UART_AUTOBAUD_NO_ERROR = 0x000, /*!< No autobaud error. */ + + ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE = 0x100, /*!< Timeout due to no valid start edge found during autobaud. */ + + ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK = 0x200, /*!< Timeout due to break condition detected during autobaud. */ + + ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE = 0x400 /*!< Timeout due to no valid end edge found during autobaud. */ + +}ADI_UART_AUTOBAUD_ERRORS; + +/*! + ***************************************************************************** + * \enum ADI_UART_TRIG_LEVEL + * Enumeration for the FIFO trigger level. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_RX_FIFO_TRIG_LEVEL_1BYTE = 0 << BITP_UART_FCR_RFTRIG, /*!< 1-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_4BYTE = 1 << BITP_UART_FCR_RFTRIG, /*!< 4-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_8BYTE = 2 << BITP_UART_FCR_RFTRIG, /*!< 8-byte to trigger RX interrupt. */ + + ADI_UART_RX_FIFO_TRIG_LEVEL_14BYTE = 3 << BITP_UART_FCR_RFTRIG /*!< 14-byte to trigger RX interrupt. */ + +}ADI_UART_TRIG_LEVEL; + +/*! + ***************************************************************************** + * \enum ADI_UART_WORDLEN + * Enumeration for data width. + *****************************************************************************/ +typedef enum +{ + ADI_UART_WORDLEN_5BITS, /*!< 5 bits wide. */ + + ADI_UART_WORDLEN_6BITS, /*!< 6 bits wide. */ + + ADI_UART_WORDLEN_7BITS, /*!< 7 bits wide. */ + + ADI_UART_WORDLEN_8BITS /*!< 8 bits wide. */ + +} ADI_UART_WORDLEN; + +/*! + ***************************************************************************** + * \enum ADI_UART_PARITY + * Enumeration for parity check. + *****************************************************************************/ +typedef enum +{ + ADI_UART_NO_PARITY = 0x0, /*!< No parity. */ + + ADI_UART_ODD_PARITY = 0x8, /*!< Odd parity. */ + + ADI_UART_EVEN_PARITY = 0x18, /*!< Even Parity. */ + + ADI_UART_ODD_PARITY_STICKY = 0x28, /*!< Sticky odd parity. */ + + ADI_UART_EVEN_PARITY_STICKY = 0x38 /*!< Sticky even parity. */ + +} ADI_UART_PARITY; + +/*! + ***************************************************************************** + * \enum ADI_UART_STOPBITS + * Enumeration for the number of stop bits. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_ONE_STOPBIT = 0x00, /*! One stop bit regardless of the word length */ + + ADI_UART_ONE_AND_HALF_TWO_STOPBITS = 0x04 /*! Number of stop bits based on word length. 1.5 stop bits + for word length of 5 bits and 2 for rest( 6,7,8 bit word length) */ + +} ADI_UART_STOPBITS; + +/*! + ***************************************************************************** + * \enum ADI_UART_TRANSFER_MODE + * Enumeration for data transfer mode. + *****************************************************************************/ +typedef enum +{ + + ADI_UART_DATA_TRANSFER_MODE_NONE, /*! Mode of data transfer is not selected. */ + + ADI_UART_DATA_TRANSFER_MODE_BLOCKING, /*! Blocking mode. Only calls to adi_uart_Read or adi_uart_write + are allowed for sending or receiving data. */ + + ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING /*! Non-Blocking mode. Only calls to adi_uart_SubmitRxBuffer or + adi_uart_SubmitTxBuffer are allowed for sending or receiving data. */ + +} ADI_UART_TRANSFER_MODE; + + +/****************************************************************************** + * UART Device external API function prototypes + *****************************************************************************/ + +/* + * Device initialization and uninitialization interfaces. +*/ +ADI_UART_RESULT adi_uart_Open( + uint32_t const nDeviceNum, + ADI_UART_DIRECTION const eDirection, + void *pMemory, + uint32_t const nMemSize, + ADI_UART_HANDLE *const phDevice +); + +ADI_UART_RESULT adi_uart_Close( + ADI_UART_HANDLE const hDevice +); + + +/****************************************************************************** + * Eliminatable functions that may be optimized out by the linker + *****************************************************************************/ + +/* + * Non-blocking mode functions. +*/ + +ADI_UART_RESULT adi_uart_SubmitTxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA +); + +ADI_UART_RESULT adi_uart_SubmitRxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA +); + +ADI_UART_RESULT adi_uart_GetTxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError +); + +ADI_UART_RESULT adi_uart_GetRxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError +); +ADI_UART_RESULT adi_uart_IsTxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable +); + +ADI_UART_RESULT adi_uart_IsRxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable +); + +/* + * Blocking mode functions. +*/ + +ADI_UART_RESULT adi_uart_Write( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError +); + +ADI_UART_RESULT adi_uart_Read( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError +); + + +/* + * Configuration interface functions. +*/ + +ADI_UART_RESULT adi_uart_EnableLoopBack( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_EnableAutobaud( + ADI_UART_HANDLE const hDevice, + bool const bEnable, + bool const bAutobaudCallbackMode +); + +ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_TRIG_LEVEL const eTriglevel +); + +ADI_UART_RESULT adi_uart_EnableFifo( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_GetBaudRate( + ADI_UART_HANDLE const hDevice, + uint32_t *pnBaudRate, + uint32_t *pAutobaudError +); + +ADI_UART_RESULT adi_uart_ForceTxBreak( + ADI_UART_HANDLE const hDevice, + bool const bEnable +); + +ADI_UART_RESULT adi_uart_SetConfiguration( + ADI_UART_HANDLE const hDevice, + ADI_UART_PARITY const eParity, + ADI_UART_STOPBITS const eStopBits, + ADI_UART_WORDLEN const eWordLength +); + +ADI_UART_RESULT adi_uart_ConfigBaudRate( + ADI_UART_HANDLE const hDevice, + uint16_t const nDivC, + uint8_t const nDivM, + uint16_t const nDivN, + uint8_t const nOSR +); + +/* + * Channel data control functions. +*/ + +ADI_UART_RESULT adi_uart_FlushTxFifo( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_FlushRxFifo( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_FlushRxChannel( + ADI_UART_CONST_HANDLE const hDevice +); + + +ADI_UART_RESULT adi_uart_FlushTxChannel( + ADI_UART_CONST_HANDLE const hDevice +); + +ADI_UART_RESULT adi_uart_IsTxComplete( + ADI_UART_HANDLE const hDevice, + bool *const pbComplete +); + +/* + * Callback functions. +*/ + +ADI_UART_RESULT adi_uart_RegisterCallback( + ADI_UART_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void *const pCBParam +); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/*@}*/ + +#endif /* ADI_UART_H */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h new file mode 100755 index 00000000000..834afee018d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/wdt/adi_wdt.h @@ -0,0 +1,77 @@ +/*! ***************************************************************************** + * @file adi_wdt.h + * @brief WDT device driver public header + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_WDT_H +#define ADI_WDT_H + +#include + +/** @addtogroup WDT_Driver WDT Driver + * @{ + */ + +/*! \enum ADI_WDT_RESULT Watchdog Device Error Codes. */ +typedef enum +{ + /*! Generic success. */ + ADI_WDT_SUCCESS, + /*! Timer is locked. */ + ADI_WDT_FAILURE_LOCKED +} ADI_WDT_RESULT; + + +/****************************************************************************** + * PUBLIC API + * 1.) Eliminatable functions that may be optimized out by the linker + * 2.) Ordered by designed function call sequence + *****************************************************************************/ + +ADI_WDT_RESULT adi_wdt_Enable (bool const bEnable, ADI_CALLBACK const pfCallback); +void adi_wdt_Kick (void); +void adi_wdt_GetCount(uint16_t * const pCurCount); + + +/*! @} */ + +#endif /* ADI_WDT_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h new file mode 100755 index 00000000000..ba76911f640 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/drivers/xint/adi_xint.h @@ -0,0 +1,120 @@ +/* + ***************************************************************************** + @file: adi_xint.h + @brief: External interrupt driver definitions and API + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_XINT_H +#define ADI_XINT_H + +/*! \addtogroup XINT_Driver External Interrupt Driver + * @{ + */ + +#ifdef __ICCARM__ +#pragma diag_default=Pm008 +#endif /* __ICCARM__ */ + +#include +#include + +#if !defined(__ADUCM4x50__) +#error "Unknown processor family" +#endif + +/* C++ linkage */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/*! Amount of memory(in bytes) required by the External Interrupt device driver for its operation. + * This memory is completely owned by the driver till the end of the operation. + */ +#define ADI_XINT_MEMORY_SIZE (48u) + +/*! External Interrupt Driver API function return codes */ +typedef enum +{ + ADI_XINT_SUCCESS = 0, /*!< API successfully returned. */ + ADI_XINT_FAILURE, /*!< The API call failed. */ + ADI_XINT_ALREADY_INITIALIZED, /*!< External interrupt driver has already been initialized. */ + ADI_XINT_NOT_INITIALIZED, /*!< External interrupt driver has not yet been initialized. */ + ADI_XINT_NULL_PARAMETER, /*!< The given pointer is pointing to NULL. */ + ADI_XINT_INVALID_MEMORY_SIZE, /*!< The given memory is not sufficient to operate the driver. */ + ADI_XINT_INVALID_INTERRUPT /*!< Invalid interrupt number. */ +} ADI_XINT_RESULT; + + +/*! External interrupt trigger condition enumerations */ +typedef enum { + ADI_XINT_IRQ_RISING_EDGE = 0x0, /*!< Trigger an interrupt when a rising edge is detected. */ + ADI_XINT_IRQ_FALLING_EDGE = 0x1, /*!< Trigger an interrupt when on a falling edge is detected. */ + ADI_XINT_IRQ_EITHER_EDGE = 0x2, /*!< Trigger an interrupt on either falling or rising edge is detected. */ + ADI_XINT_IRQ_HIGH_LEVEL = 0x3, /*!< Trigger an interrupt on a logic level high is detected. */ + ADI_XINT_IRQ_LOW_LEVEL = 0x4 /*!< Trigger an interrupt on a logic level low is detected. */ +} ADI_XINT_IRQ_MODE; + +/*! External interrupts. */ +typedef enum { + ADI_XINT_EVENT_INT0 = 0x0, /*!< Event for external interrupt-0 */ + ADI_XINT_EVENT_INT1 = 0x1, /*!< Event for external interrupt-1 */ + ADI_XINT_EVENT_INT2 = 0x2, /*!< Event for external interrupt-2 */ + ADI_XINT_EVENT_INT3 = 0x3, /*!< Event for external interrupt-3 */ + ADI_XINT_EVENT_RESERVED = 0x4, /*!< Event is reserved. */ + ADI_XINT_EVENT_UART_RX = 0x5, /*!< Event for UART Rx activity */ + ADI_XINT_EVENT_MAX = 0x6 /*!< Number of external interrupt events */ +} ADI_XINT_EVENT; + + +/* External Interrupt API functions */ +ADI_XINT_RESULT adi_xint_Init (void* const pMemory, uint32_t const MemorySize); +ADI_XINT_RESULT adi_xint_UnInit (void); +ADI_XINT_RESULT adi_xint_EnableIRQ (const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode); +ADI_XINT_RESULT adi_xint_DisableIRQ (const ADI_XINT_EVENT eEvent); +ADI_XINT_RESULT adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam ); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* ADI_XINT_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c new file mode 100755 index 00000000000..66bc3cf1f69 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash.c @@ -0,0 +1,1812 @@ +/*! + ***************************************************************************** + @file: adi_flash.c + @brief: Flash Device Driver Implementation + @date: $Date: 2016-06-30 08:06:37 -0400 (Thu, 30 Jun 2016) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup Flash_Driver Flash Driver + * @{ + * + * @brief Flash (FEE) Driver + * + * @details + * + * The flash controller provides access to the embedded flash memory. The embedded + * flash has a 72-bit wide data bus providing for two 32-bit words of data and + * one corresponding 8-bit ECC byte per access. + * + * Flash Driver Hardware Errors + * + * Many of the Flash Controller APIs can result in hardware errors. Each such API has a + * a hardware error parameter (pHwErrors), which is a pointer to an application-defined + * variable into which the failing API will store the failing hardware error status.\n + * + * APIs failing with hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED + * return code.\n + * + * Hardware error details may be decoded according to the flash controller status register + * ("STAT") bit-map, documented in the Hardware Reference Manual (HRM). Flash hardware + * errors are separate and distinct from DMA errors, which have separate and distinct + * return codes (#ADI_FEE_ERR_DMA_BUS_FAULT, #ADI_FEE_ERR_DMA_INVALID_DESCR, and + * #ADI_FEE_ERR_DMA_UNKNOWN_ERROR). + * + * Flash Driver Static Configuration + * + * A number of flash driver APIs manage configurations that very likely do not require + * dynamic (run-time) management. Such cases are documented with the respective APIs. + * In all such cases, the user is encouraged to consider using the static configuration + * equivalents (provided in the adi_flash_config.h file) in lieu of the dynamic APIs. + * In so doing, linker elimination may reduce the resulting code image footprint + * (provided the API is not called). + * + * @note - The application must include drivers/flash/adi_flash.h to use this driver. + * @note - This driver also requires the DMA driver. The application must include + * the DMA driver sources to avoid link errors. + */ + +/*======== I N C L U D E ========*/ + + /*! \cond PRIVATE */ +#include +#include +#include /* for "memset" */ +/*! \endcond */ + +#include + +/*============= M I S R A =============*/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* Required for MMR accesses, determining pointer alignment, and a callback argument. +* +* Pm026 (rule 12.4): the right hand operand of an && or || operator shall not contain side effects +* Side effects being mis-reported due to added volatile storage class. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm050,Pm088,Pm140,Pm026 +#endif /* __ICCARM__ */ + +/* pull in internal data structures */ +#include "adi_flash_data.c" + +/*======== D E F I N E S ========*/ + +/*! \cond PRIVATE */ + +#ifdef ADI_DEBUG +#define ASSERT(X) assert(X) +#else +#define ASSERT(X) +#endif + +/* internal utility macros */ +#define CLR_BITS(REG, BITS) ((REG) &= ~(BITS)) +#define SET_BITS(REG, BITS) ((REG) |= (BITS)) + +#ifdef ADI_DEBUG +/* Validate Device Handle */ +static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice); +static bool IsDeviceHandle (ADI_FEE_HANDLE const hDevice) +{ + if ( (fee_device_info[0].hDevice == (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL) ) { + return true; + } else { + return false; + } +} +#endif + +/* Wait for specified flash status to be clear */ +static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status); +static void BusyWait (ADI_FEE_HANDLE const hDevice, uint32_t const status) +{ + while ((hDevice->pDev->STAT & status) != 0u) {} +} + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler */ +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg); +static void dmaCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* recover the device handle */ + ADI_FEE_HANDLE hDevice = (ADI_FEE_HANDLE)pCBParam; + + /* save the DMA error */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->dmaError = ADI_FEE_ERR_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->dmaError = ADI_FEE_ERR_DMA_INVALID_DESCR; + break; + default: + hDevice->dmaError = ADI_FEE_ERR_DMA_UNKNOWN_ERROR; + break; + } + + /* transfer is toast... post and callback any waiters */ + + SEM_POST(hDevice); + + if (0u != hDevice->pfCallback) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, (void*)NULL); + } +} + +/*! \endcond */ + + +/*======== C O D E ========*/ +/* + * API Implementation + */ + + +/** + * @brief Open the flash controller. + * + * @param [in] nDeviceNum The zero-based device instance number of flash controller to be opened. + * @param [in] pMemory Application supplied memory space for use by the driver. + * @param [in] nMemorySize Size of the application supplied memory (in bytes). + * @param [in,out] phDevice The caller's device handle pointer for storing the initialized + * device instance data pointer. + * + * @return Status + * - #ADI_FEE_SUCCESS The device is opened successfully. + * - #ADI_FEE_ERR_BAD_DEVICE_NUM [D] The device number passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Some pointer(s) passed to the function is NULL. + * - #ADI_FEE_ERR_ALREADY_INITIALIZED [D] The device is already initialized and hence cannot be opened. + * - #ADI_FEE_ERR_INSUFFICIENT_MEM [D] The memory passed to the driver is insufficient. + * - #ADI_FEE_ERR_DMA_REGISTER The required DMA common error handler registration failed. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore create operation failed. + * + * Initialize an instance of the flash device driver using default user configuration settings + * (from adi_flash_config.h) and allocate the device for use. + * + * No other flash APIs may be called until the device open function is called. The returned + * device handle is required to be passed to all subsequent flash API calls to identify the + * physical device instance in use. The user device handle (pointed to by phDevice) is set + * to NULL on failure. + * + * @note Currently, only a singular flash physical device instance (device ID "0") exists. + * + * @sa adi_fee_Close(). + */ +ADI_FEE_RESULT adi_fee_Open (uint32_t const nDeviceNum, void* const pMemory, uint32_t const nMemorySize, ADI_FEE_HANDLE* const phDevice) +{ + ADI_FEE_HANDLE hDevice = NULL; /* initially */ + +#ifdef ADI_DEBUG + if (nDeviceNum >= ADI_FEE_NUM_INSTANCES) { + return ADI_FEE_ERR_BAD_DEVICE_NUM; + } + + /* verify device is not already open */ + if (fee_device_info[nDeviceNum].hDevice != NULL) { + return ADI_FEE_ERR_ALREADY_INITIALIZED; + } + + if ((pMemory == NULL) || (phDevice == NULL)) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (nMemorySize < ADI_FEE_MEMORY_SIZE) { + return ADI_FEE_ERR_INSUFFICIENT_MEM; + } + + assert (ADI_FEE_MEMORY_SIZE == sizeof(ADI_FEE_DEV_DATA_TYPE)); +#endif + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* Link user memory (handle) into ADI_FEE_DEVICE_INFO data structure. + * + * ADI_FEE_DEVICE_INFO <==> ADI_FEE_HANDLE + */ + fee_device_info[nDeviceNum].hDevice = (ADI_FEE_DEV_DATA_TYPE *)pMemory; + + /* Clear the ADI_FEE_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bUseDma = false) + */ + memset(pMemory, 0, nMemorySize); + + /* initialize local device handle and link up device info for this device instance */ + hDevice = (ADI_FEE_HANDLE)pMemory; + hDevice->pDevInfo = &fee_device_info[nDeviceNum]; + + /* Although the ADI_FEE_DEVICE_INFO struct has the physical device pointer + * for this instance, copying it to the ADI_FEE_HANDLE struct (in user memory) + * will minimize the runtime footprint and cycle count when accessing the FEE + * registers. + */ + hDevice->pDev = fee_device_info[nDeviceNum].pDev; + + /* store a pointer to user's static configuration settings for this device instance */ + hDevice->pDevInfo->pConfig = (ADI_FEE_CONFIG*)&gConfigInfo[nDeviceNum]; + + /* create the semaphore */ + SEM_CREATE(hDevice, "fee_sem", ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* grant keyed access */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + + /* apply the static initializers */ + hDevice->pDev->IEN = hDevice->pDevInfo->pConfig->eccIrqEnables; + hDevice->pDev->TIME_PARAM0 = hDevice->pDevInfo->pConfig->param0; + hDevice->pDev->TIME_PARAM1 = hDevice->pDevInfo->pConfig->param1; + hDevice->pDev->ABORT_EN_LO = hDevice->pDevInfo->pConfig->abortEnableLo; + hDevice->pDev->ABORT_EN_HI = hDevice->pDevInfo->pConfig->abortEnableHi; + hDevice->pDev->ECC_CFG = hDevice->pDevInfo->pConfig->eccConfig; + + /* clear auto-increment and dma enable bits */ + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + + /* close keyed access */ + hDevice->pDev->KEY = 0u; + + /* store device handle into user handle */ + *phDevice = (ADI_FEE_HANDLE)hDevice; + + /* initialize DMA service */ + adi_dma_Init(); + + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pDevInfo->dmaChanNum, dmaCallback, (void*)hDevice)) { + /* uninitialize flash driver and fail */ + adi_fee_Close(hDevice); + return ADI_FEE_ERR_DMA_REGISTER; + } + + /* NVIC enables */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIrqNum); + NVIC_EnableIRQ(hDevice->pDevInfo->dmaIrqNum); + + /* return success */ + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Close the flash controller. + * + * @param [in] hDevice The handle to the flash controller device + * + * @return Status + * - #ADI_FEE_SUCCESS The device is closed successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore delete operation failed. + * + * Uninitialize and release an allocated flash device, and memory associated with it + * for other use. + * + * @note The user memory is released from use by the flash driver, but is not freed. + * + * @sa adi_fee_Open(). + */ +ADI_FEE_RESULT adi_fee_Close (ADI_FEE_HANDLE const hDevice) +{ + uint32_t dev; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + + /* Destroy the semaphore */ + SEM_DELETE(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* Remove the device handle from the list of possible device instances */ + for (dev = 0u; dev < ADI_FEE_NUM_INSTANCES; dev++) + { + if (fee_device_info[dev].hDevice == hDevice) + { + fee_device_info[dev].hDevice = NULL; + break; + } + } + + /* NVIC disables */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIrqNum); + NVIC_DisableIRQ(hDevice->pDevInfo->dmaIrqNum); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Register an application-defined callback function. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pfCallback A pointer to an application-supplied calllback function + * which is called to notify the application of device-related + * events. A value of NULL disables driver callbacks. + * @param [in] pCBParam An application-supplied callback parameter which will be passed + * back to the callback function. + * + * @return Status + * - #ADI_FEE_SUCCESS The callback is registered successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress and + * the callback registration is ignored. + * + * Links the user-provided callback function into the #adi_fee_SubmitBuffer() API such that + * rather than polling for buffer completion (with #adi_fee_IsBufferAvailable()) and eventually + * reacquiring the buffer (with #adi_fee_GetBuffer()), the user can simply register a callback + * function that will be called upon buffer completion with no further action needed.\n + * + * Error conditions are also passed to the callback, including DMA errors if DMA is active. Make sure + * to always check the event value passed to the callback, just as the various API return codes should + * always be checked.\n + * + * However, callbacks are always made in context of an interrupt, so applications are strongly encouraged + * to exit the callback as quickly as possible so normal interrupt processing is disrupted as little as + * possible. This is also an argument for not using callbacks at at all. + * + * @note When using callbacks to reacquire buffers, DO NOT use the #adi_fee_GetBuffer() API. The two + * methods are mutually exclusive. + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_IsBufferAvailable(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_RegisterCallback (ADI_FEE_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void* const pCBParam) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* Set the callback function and param in the device */ + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Erase the given range of (2kB) page(s) within the flash user space memory. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nPageNumStart Start page number. + * @param [in] nPageNumEnd End page number. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The page(s) is(are) cleared successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] The page(s) number(s) is(are) incorrect. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Erases entire page(s). Callers are expected to save/restore any partial page data prior + * to erasure, as needed. Translate literal flash addresses into flash start and end page + * numbers with #adi_fee_GetPageNumber(). + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_GetPageNumber(). + * @sa adi_fee_MassErase(). + */ +ADI_FEE_RESULT adi_fee_PageErase (ADI_FEE_HANDLE const hDevice, uint32_t const nPageNumStart, uint32_t const nPageNumEnd, uint32_t* const pHwErrors) + +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + + uint32_t page; + +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + uint32_t nRelAddrStart = (nPageNumStart << FEE_PAGE_SHIFT); + uint32_t nRelAddrStop = (nPageNumEnd << FEE_PAGE_SHIFT); + + if ( (nPageNumStart > nPageNumEnd) + || (nRelAddrStart >= FEE_FLASH_SIZE) + || (nRelAddrStop >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif /* defined (ADI_DEBUG) */ + + for (page = nPageNumStart; page <= nPageNumEnd; page++) + { + /* Wait until not busy */ + BusyWait(hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Set the page address */ + hDevice->pDev->PAGE_ADDR0 = (page << FEE_PAGE_SHIFT); + + /* Issue a page erase command */ + result = SendCommand (hDevice, ENUM_FLCC_CMD_ERASEPAGE); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + if (result != ADI_FEE_SUCCESS) { + break; + } + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Erase the entire flash user space memory. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The flash is cleared successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * @note Do not call mass erase on or from code that is running from flash. Doing so will leave + * an indeterminate machine state. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_PageErase(). + */ +ADI_FEE_RESULT adi_fee_MassErase (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* Call the mass erase command */ + result = SendCommand (hDevice, ENUM_FLCC_CMD_MASSERASE); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Perform a blocking flash data write operation. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pTransaction Pointer to a user-defined control block describing the data to be transferred, containing: + * - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash. + * - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory. + * - nSize; Number of bytes to write (must be an integral multiple of 8). + * - bUseDma; Flag controlling use of DMA to perform the write. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_ALIGNMENT [D] The flash write source data pointer is misaligned. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Buffer size is not a multiple of 8-bytes (or too large for DMA). + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DEVICE_BUSY The flash controller is busy. + * - #ADI_FEE_ERR_DMA_BUS_FAULT A runtime DMA bus fault was detected. + * - #ADI_FEE_ERR_DMA_INVALID_DESCR A runtime DMA invalid descriptor was detected. + * - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR An unknown runtime DMA error was detected. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER Transfer ran out of write data unexpectedly. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Perform a blocking flash data write operation. This API does not return until the write operation is completed. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). Flash hardware errors are separate + * and distinct from DMA errors, which have separate and distinct return codes, as described above. + */ +ADI_FEE_RESULT adi_fee_Write (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* check address is 64-bit aligned and data pointer is 32-bit aligned */ + if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) ) + { + return ADI_FEE_ERR_ALIGNMENT; + } + + /* make sure size is a multiple of 8 */ + if ((pTransaction->nSize & 0x7u) != 0u) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (true == pTransaction->bUseDma) { + /* check for max DMA units (32-bit chunks, i.e., 4 bytes at a whack) */ + if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) { + return ADI_FEE_ERR_INVALID_PARAM; + } + } +#endif + + /* reset submit/get safeguard flag */ + hDevice->bSubmitCalled = false; + + /* Fill in the transfer params */ + hDevice->pNextWriteAddress = pTransaction->pWriteAddr; + hDevice->pNextReadAddress = pTransaction->pWriteData; + hDevice->nRemainingBytes = pTransaction->nSize; + hDevice->bUseDma = pTransaction->bUseDma; + + /* Initiate a transfer */ + result = InitiateTransfer (hDevice); + + /* Wait for the completed transfer */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* issue any flash DMA error status codes... */ + if (0u != hDevice->dmaError) { + return hDevice->dmaError; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + /* Check for errors in buffer write */ + if (hDevice->nRemainingBytes != 0u) { + return ADI_FEE_ERR_BUFFER_ERR; + } + + return result; +} + + +/** + * @brief Submit a non-blocking flash data write operation for background processing. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] pTransaction Pointer to a user-defined control block describing the data to be transferred, containing: + * - pWriteAddr; Pointer to a 64-bit-aligned destination address in flash. + * - pWriteData; Pointer to a 32-bit-aligned source data buffer in user memory. + * - nSize; Number of bytes to write (must be an integral multiple of 8). + * - bUseDma; Flag controlling use of DMA to perform the write. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_ALIGNMENT [D] The flash write source data pointer is misaligned. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Buffer size is not a multiple of 8-bytes (or too large for DMA). + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DEVICE_BUSY The flash controller is busy. + * - #ADI_FEE_ERR_NO_DATA_TO_TRANSFER Transfer ran out of write data unexpectedly. + * + * Submit a flash data write transaction. This is a non-blocking function which returns immediately. + * The application may either: poll for transaction completion through the non-blocking #adi_fee_IsBufferAvailable() + * API, and/or await transaction completion through the blocking mode #adi_fee_GetBuffer() API. If an application + * callback has been registered, the application is advised of completion status through the callback. + * + * @note If using callback mode, DO NOT USE the #adi_fee_GetBuffer() API, which are mutually exclusive protocols. + * + * @sa adi_fee_IsBufferAvailable(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_SubmitBuffer (ADI_FEE_HANDLE const hDevice, ADI_FEE_TRANSACTION* const pTransaction) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* check address is 64-bit aligned and data pointer is 32-bit aligned */ + if ( (((uint32_t)pTransaction->pWriteAddr & 0x7u) != 0u) || ((((uint32_t)pTransaction->pWriteData) & 0x3u) != 0u) ) + { + return ADI_FEE_ERR_ALIGNMENT; + } + + /* make sure size is a multiple of 8 */ + if ((pTransaction->nSize & 0x7u) != 0u) { + return ADI_FEE_ERR_INVALID_PARAM; + } + + if (true == pTransaction->bUseDma) { + /* check for max DMA units (32-bit channel width means 4 bytes at a whack) */ + if (DMA_TRANSFER_LIMIT < (pTransaction->nSize / sizeof(uint32_t))) { + return ADI_FEE_ERR_INVALID_PARAM; + } + } +#endif + + /* set submit/get safeguard flag */ + hDevice->bSubmitCalled = true; + + /* Fill in the transfer params */ + hDevice->pNextWriteAddress = pTransaction->pWriteAddr; + hDevice->pNextReadAddress = pTransaction->pWriteData; + hDevice->nRemainingBytes = pTransaction->nSize; + hDevice->bUseDma = pTransaction->bUseDma; + + /* initiate a transfer */ + result = InitiateTransfer (hDevice); + + /* no pend here... just return */ + + return result; +} + + +/** + * @brief Non-blocking check if a write transaction complete. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pbCompletionState True if transfer is complete, false if not. + * + * @return Status + * - #ADI_FEE_SUCCESS The status of buffer is returned successfully. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Pointer passed is NULL. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY No matching buffer submit call found. + * + * Check if a non-blocking write transaction that was submitted via adi_fee_SubmitBuffer() is complete. + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_GetBuffer(). + */ +ADI_FEE_RESULT adi_fee_IsBufferAvailable (ADI_FEE_HANDLE const hDevice, bool* const pbCompletionState) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pbCompletionState == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY; + } + + if (true == hDevice->bTransferInProgress) { + *pbCompletionState = false; + } else { + *pbCompletionState = true; + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Blocking mode call to await transaction completion. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The buffer is successfully written to the flash. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_BUFFER_ERR Error occurred in processing the buffer. + * - #ADI_FEE_ERR_DMA_BUS_FAULT A runtime DMA bus fault was detected. + * - #ADI_FEE_ERR_DMA_INVALID_DESCR A runtime DMA invalid descriptor was detected. + * - #ADI_FEE_ERR_DMA_UNKNOWN_ERROR An unknown runtime DMA error was detected. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * - #ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY No matching buffer submit call found. + * + * This function blocks until a previously-submitted flash write operation has completed. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_SubmitBuffer(). + * @sa adi_fee_IsBufferAvailable(). + */ +ADI_FEE_RESULT adi_fee_GetBuffer (ADI_FEE_HANDLE const hDevice, uint32_t* const pHwErrors) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_FEE_ERR_UNMATCHED_SUBMIT_QUERY; + } + + /* Pend for the semaphore */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* issue any flash DMA error status codes... */ + if (0u != hDevice->dmaError) { + return hDevice->dmaError; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + /* Check for errors in buffer write or transfer still in progress */ + if ((0u != hDevice->nRemainingBytes) || (true == hDevice->bTransferInProgress)) { + return ADI_FEE_ERR_BUFFER_ERR; + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the (2kB) page number within which a flash address resides. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nAddress The flash address for which the page number is required. + * @param [in,out] pnPageNum Pointer to a variable into which the page number corresponding + * to the provided flash address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The page number is returned successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameter(s) are invalid. + * + * Translates a literal flash address into a page number for use with various page-based flash operations. + * + * @sa adi_fee_PageErase(). + * @sa adi_fee_VerifySignature(). + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_GetBlockNumber(). + * + */ +ADI_FEE_RESULT adi_fee_GetPageNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnPageNum) +{ +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if ( (pnPageNum == NULL) + || (nAddress >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the page number for the given flash address */ + *pnPageNum = (nAddress >> FEE_PAGE_SHIFT); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the (16kB) block number within which a flash address resides. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nAddress The flash address for which the block number is required. + * @param [in,out] pnBlockNum Pointer to a variable into which the block number corresponding + * to the provided flash address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The block number is returned successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameter(s) are invalid. + * + * Translates a literal flash address into a block number for use with setting flash write protection on a block. + * + * @sa adi_fee_WriteProtectBlock(). + * @sa adi_fee_GetPageNumber(). + */ +ADI_FEE_RESULT adi_fee_GetBlockNumber (ADI_FEE_HANDLE const hDevice, uint32_t const nAddress, uint32_t* const pnBlockNum) +{ +#ifdef ADI_DEBUG + + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if ( (pnBlockNum == NULL) + || (nAddress >= FEE_FLASH_SIZE)) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the block number */ + *pnBlockNum = (nAddress >> FEE_BLOCK_SHIFT); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Generate the CRC signature for a range of flash data page(s). This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nStartPage The lower page number of the signature range. + * @param [in] nEndPage The upper page number of the signature range. + * @param [in,out] pSigResult Pointer to a variable into which the computed signature is stored. + * @param [in,out] pHwErrors Pointer to user location into which any flash hardware errors are reported. + * + * @return Status + * - #ADI_FEE_SUCCESS The signature is verified successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] The page(s) number(s) is(are) incorrect. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] A flash write operation is in progress. + * - #ADI_FEE_ERR_HW_ERROR_DETECTED An internal flash controller hardware error was detected. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Compute and return a CRC over a range of contiguous whole flash memory pages(s). The computed CRC + * signature may subsequently be written into the most-significant word of the region over which the + * signature was calculated. This is done in context of enabling bootloader enforcement of CRC signature + * verification during system startup. See HRM for signature storage programming requirements and + * bootloader operation. + * + * @note Flash hardware errors are flagged with the #ADI_FEE_ERR_HW_ERROR_DETECTED return code. + * Flash hardware error details are written to the location pointed to by the pHwErrors parameter. + * Hardware error details may be decoded according to the flash controller status register ("STAT") + * bit-map, documented in the Hardware Reference Manual (HRM). + * + * @sa adi_fee_GetPageNumber(). + */ +ADI_FEE_RESULT adi_fee_VerifySignature (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, uint32_t const nEndPage, uint32_t* const pSigResult, uint32_t* const pHwErrors) + +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if ( (pSigResult == NULL) + || (nStartPage > nEndPage) + || (nStartPage >= FEE_MAX_NUM_PAGES) + || (nEndPage >= FEE_MAX_NUM_PAGES) + ) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Wait until not busy */ + BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Set the lower and upper page */ + hDevice->pDev->PAGE_ADDR0 = nStartPage << FEE_PAGE_SHIFT; + hDevice->pDev->PAGE_ADDR1 = nEndPage << FEE_PAGE_SHIFT; + + /* Do a SIGN command */ + result = SendCommand(hDevice, ENUM_FLCC_CMD_SIGN); + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + /* Return the signature to the application */ + if (ADI_FEE_SUCCESS == result) { + *pSigResult = hDevice->pDev->SIGNATURE; + } else { + *pSigResult = 0u; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->feeError; + if (0u != hDevice->feeError) { + /* return the HW error return code */ + return ADI_FEE_ERR_HW_ERROR_DETECTED; + } + + return result; +} + + +/** + * @brief Set write protection on an (16kB) block. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nBlockNum The block number. + * + * @return Status + * - #ADI_FEE_SUCCESS The block is write protected successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Block number is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Assert memory write-protection for specified block. Note that only entire blocks are protectable, + * with each block spanning 8 pages. + * + * @note Blocks may only be write-protected during user run-time code. Unprotecting is only + * possible with a power-on-reset or a mass erase; write-protection is not otherwise clearable. + * + * @warning Flash-based code that write-protects blocks will cause the write-protection (and data at + * time of write-protect assertion) to apparently not clear... even after a mass erase or power-on-reset. + * This apparently "stuck" write-protection results from the flash-based write-protect code running + * after reset (as usual), but still prior to the debugger halting the target through the debug + * interrupt. The debugger target halt occurs WELL AFTER the flash code has already run, thereby + * relocking the block and making it appear the write-protection was never reset. This can be difficult + * Catch-22 situation to recover from, requiring repeated hardware resets and reflashing new code that + * does not assert the write-protection. + * + * @sa adi_fee_GetBlockNumber(). + */ +ADI_FEE_RESULT adi_fee_WriteProtectBlock (ADI_FEE_HANDLE const hDevice, uint32_t const nBlockNum) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if (nBlockNum > FEE_MAX_NUM_BLOCKS) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Set the write protection (by clearing the bit) for the given block */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->WRPROT, 1u << nBlockNum); + hDevice->pDev->KEY = 0u; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Sleep or awake the flash controller. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] bSleep 'true' to enable to sleep the flash device + * and 'false' to wake up the device. + * + * @return Status + * - #ADI_FEE_SUCCESS The flash controller is moved to sleep/wake + * up sate successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * Places the flash controller into a low-power sleep mode - see details in Hardware Reference Manual (HRM). + * Default wakeup time is approximately 5us, and is configurable with static configuration parameter + * ADI_FEE_CFG_PARAM1_TWK in adi_flash_config.h file. + */ +ADI_FEE_RESULT adi_fee_Sleep (ADI_FEE_HANDLE const hDevice, bool const bSleep) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* TODO: Check that IDLE can take the controller + * out of sleep + */ + + if (true == bSleep) { + result = SendCommand (hDevice, ENUM_FLCC_CMD_SLEEP); + } else { + result = SendCommand (hDevice, ENUM_FLCC_CMD_IDLE); + } + + /* block on command */ + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + return result; +} + + +/** + * @brief Forcefully ABORT an ongoing flash operation. This is a blocking call. + * + * @param [in] hDevice The handle to the flash controller device. + * + * @return Statuus + * - #ADI_FEE_SUCCESS The command is successfully aborted. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid + * - #ADI_FEE_ERR_SEMAPHORE_FAILED The semaphore pend operation failed. + * + * @warning Use this command sparingly and as a last resort to satisfy critical + * time-sensitive events. Aborting any flash command results in prematurely ending the + * current flash access and may result in corrupted flash data. + * + * @sa adi_fee_GetAbortAddr(). + */ +ADI_FEE_RESULT adi_fee_Abort (ADI_FEE_HANDLE const hDevice) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } +#endif + /* Issue the command (abort is keyed) directly */ + /* (avoid SendCommand() here, as it does a busy wait, which may not clear if we're in a recovery mode) */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + hDevice->pDev->CMD = ENUM_FLCC_CMD_ABORT; + hDevice->pDev->KEY = 0u; + + SEM_PEND(hDevice, ADI_FEE_ERR_SEMAPHORE_FAILED); + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the address of recently aborted write command. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnAddress Pointer to which the address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The abort address is retrieved successfully + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid + * - #ADI_FEE_ERR_INVALID_PARAM [D] Pointer passed is NULL + * + * Users may use this result to determine the flash location(s) affected by a write abort command. + * Subsequent flash commands invalidate the write abort address register. + * + * + * @sa adi_fee_Abort(). + */ +ADI_FEE_RESULT adi_fee_GetAbortAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnAddress == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Write the address of the last write abort to the pointer + * supplied by the application + */ + *pnAddress = hDevice->pDev->WR_ABORT_ADDR; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Configure ECC start page and enablement. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] nStartPage The start page for which ECC will be performed. + * @param [in] bInfoECCEnable Info space ECC enable: + * - 'true' to enable info space ECC, or + * - 'false' to disable info space ECC. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC was configured successfully + * - #ADI_FEE_ERR_INVALID_PARAM [D] Start page is invalid + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @warning This API leaves user space ECC disabled. Use #adi_fee_EnableECC() to manage ECC enable/disable. + * + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_ConfigECC (ADI_FEE_HANDLE const hDevice, uint32_t const nStartPage, bool const bInfoECCEnable) +{ + uint32_t nRelAddress = nStartPage << FEE_PAGE_SHIFT; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + if (nStartPage >= FEE_MAX_NUM_PAGES) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Clear the ECC config bits */ + CLR_BITS (hDevice->pDev->ECC_CFG, (BITM_FLCC_ECC_CFG_PTR | BITM_FLCC_ECC_CFG_INFOEN)); + + /* Set the start page address in the ECC Cfg register */ + hDevice->pDev->ECC_CFG |= (nRelAddress & BITM_FLCC_ECC_CFG_PTR); + + /* enable ECC on info space... if requested */ + if (true == bInfoECCEnable) { + SET_BITS (hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_INFOEN); + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Enable/Disable user space ECC for the device. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] bEnable User space ECC enable: + * - 'true' to enable user space ECC, or + * - 'false' to disable user space ECC. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC is enabled/disabled successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Manage enablement of user space ECC function. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_EnableECC (ADI_FEE_HANDLE const hDevice, bool const bEnable) +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } +#endif + + /* manage flash ECC enable */ + if (true == bEnable) { + SET_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN); + } else { + CLR_BITS(hDevice->pDev->ECC_CFG, BITM_FLCC_ECC_CFG_EN); + } + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Confifure ECC event response. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in] eEvent ECC event - Either error or correction event. + * @param [in] eResponse The response to the eEvent - One of none, bus error, or interrupt. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC events are configured successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * - #ADI_FEE_ERR_TRANSFER_IN_PROGRESS [D] Another transfer is already in progress. + * + * Configures two major aspects of ECC event response: + * - On ECC (2-bit) Error events, generate one of: no response, bus error, or flash interrupt. + * - On ECC (1-bit) Correction events, generate one of: no response, bus error, or flash interrupt. + * + * @note The settings this API manages are very likely not needed to be modified dynamically (at run-time). + * If so, consider using the static configuration equivalents (see adi_flash_config.h) in lieu of + * this API... which will reduce the resulting code image footprint through linker elimination. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_GetECCErrAddr(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_ConfigECCEvents (ADI_FEE_HANDLE const hDevice, ADI_FEE_ECC_EVENT_TYPE const eEvent, ADI_FEE_ECC_RESPONSE const eResponse) + +{ + uint32_t nBitMask; + int32_t nBitPos; + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + /* reject while a transfer is in progress */ + if (true == hDevice->bTransferInProgress) { + return ADI_FEE_ERR_TRANSFER_IN_PROGRESS; + } + + /* Check the function parameters */ + if ( ( (eEvent != ADI_FEE_ECC_EVENT_TYPE_ERROR) + && (eEvent != ADI_FEE_ECC_EVENT_TYPE_CORRECT)) + + || ( (eResponse != ADI_FEE_ECC_RESPONSE_NONE) + && (eResponse != ADI_FEE_ECC_RESPONSE_BUS_ERROR) + && (eResponse != ADI_FEE_ECC_RESPONSE_IRQ)) + ) + { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Select the correct bit mask and bit pos for the event type */ + if (eEvent == ADI_FEE_ECC_EVENT_TYPE_ERROR) { + nBitMask = BITM_FLCC_IEN_ECC_ERROR; + nBitPos = BITP_FLCC_IEN_ECC_ERROR; + } else { + nBitMask = BITM_FLCC_IEN_ECC_CORRECT; + nBitPos = BITP_FLCC_IEN_ECC_CORRECT; + } + + /* clear the bits */ + CLR_BITS (hDevice->pDev->IEN, nBitMask); + + /* set the response */ + SET_BITS (hDevice->pDev->IEN, ((uint32_t)eResponse) << nBitPos); + + return ADI_FEE_SUCCESS; +} + + +/** + * `@brief Get the address for which the ECC event is detected. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnAddress Pointer to which the address is written. + * + * @return Status + * - #ADI_FEE_SUCCESS The ECC error address is retrieved successfully. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * + * Returns the address of the first ECC error or correction event to generate an + * interrupt since the last time ECC status bits were cleared (or since reset). + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCCorrections(). + */ +ADI_FEE_RESULT adi_fee_GetECCErrAddr (ADI_FEE_HANDLE const hDevice, uint32_t* const pnAddress) + +{ +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnAddress == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Write the address of the last ECC error/correction */ + *pnAddress = hDevice->pDev->ECC_ADDR; + + return ADI_FEE_SUCCESS; +} + + +/** + * @brief Get the number of 1-bit error corrections. + * + * @param [in] hDevice The handle to the flash controller device. + * @param [in,out] pnNumCorrections Pointer to which the number of corrections are written. + * + * @return Status + * - #ADI_FEE_SUCCESS The number of ECC corrections are successfully retrieved. + * - #ADI_FEE_ERR_INVALID_HANDLE [D] The device handle passed is invalid. + * - #ADI_FEE_ERR_INVALID_PARAM [D] Parameters are invalid. + * + * See HRM for details on how current ECC configuration affects this reporting. + * + * @sa adi_fee_ConfigECC(). + * @sa adi_fee_EnableECC(). + * @sa adi_fee_ConfigECCEvents(). + * @sa adi_fee_GetECCErrAddr(). + */ +ADI_FEE_RESULT adi_fee_GetECCCorrections (ADI_FEE_HANDLE const hDevice, uint32_t* const pnNumCorrections) +{ + +#ifdef ADI_DEBUG + if (true != IsDeviceHandle(hDevice)) { + return ADI_FEE_ERR_INVALID_HANDLE; + } + + if (pnNumCorrections == NULL) { + return ADI_FEE_ERR_INVALID_PARAM; + } +#endif + + /* Get the number of ECC Error corrections */ + *pnNumCorrections = (hDevice->pDev->STAT & BITM_FLCC_STAT_ECCERRCNT) >> BITP_FLCC_STAT_ECCERRCNT; + + return ADI_FEE_SUCCESS; +} + + +/*======== L O C A L F U N C T I O N D E F I N I T I O N S ========*/ + + +/* Send a command to the flash controller... bot don't block on it... + */ +static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd) +{ + /* Wait for the flash to be free */ + BusyWait (hDevice, (BITM_FLCC_STAT_CMDBUSY | BITM_FLCC_STAT_WRCLOSE)); + + /* Clear the command completion status bit + * by acknowledging it + */ + hDevice->pDev->STAT = BITM_FLCC_STAT_CMDCOMP; + + /* Enable command-complete and command-fail interrupt */ + SET_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* Issue the command (most commands are keyed) */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + hDevice->pDev->CMD = cmd; + hDevice->pDev->KEY = 0u; + + return ADI_FEE_SUCCESS; +} + + +static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice) +{ + + /* use PIO interrupt mode in non-burst-mode (burst-mode only spans 256-bytes). + Initiate the 1st write here, then let the interrupt handler feed + the remaining data as we process "almost-complete" interrupts. + */ + + /* write the 1st 64-bits of data */ + if (0u != hDevice->nRemainingBytes) { + + /* enable command interrupts */ + SET_BITS (hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* set initial write address*/ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + hDevice->pNextWriteAddress += 2; + + /* set key-hole data registers */ + hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->nRemainingBytes -= sizeof(uint64_t); + + /* write the command register which launches the burst write */ + hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE; + + } else { + return ADI_FEE_ERR_NO_DATA_TO_TRANSFER; + } + + return ADI_FEE_SUCCESS; +} + + +/* DMA Transfer to FIFO */ +static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice) +{ + ADI_DCC_TypeDef* pCCD = pPrimaryCCD; /* pointer to primary DMA descriptor array */ + + if (0u != hDevice->nRemainingBytes) { + + /* local channel number */ + uint16_t chan = hDevice->pDevInfo->dmaChanNum; + + /* disable endpointer decrement modes */ + pADI_DMA0->SRCADDR_CLR = 1u << chan; + pADI_DMA0->DSTADDR_CLR = 1u << chan; + + /* enable the channel */ + pADI_DMA0->EN_SET = 1u << chan; + + /* allow flash to request DMA service */ + pADI_DMA0->RMSK_CLR = 1u << chan; + + /* activate primary descriptor */ + pADI_DMA0->ALT_CLR = 1u << chan; + + /* Note: DMA width is 32-bit for the flash controller, but flash writes require + 64-bit writes at a whack. Set DMA R_Power (bus rearbitration rate) to two so + we get two uninterrupted 32-bit DMA writes to the flash with each DMA transfer. + */ + + /* set DMA source endpoint */ + pCCD += chan; /* offset descriptor pointer to flash channel */ + pCCD->DMASRCEND = (uint32_t)hDevice->pNextReadAddress + hDevice->nRemainingBytes - sizeof(uint32_t); + + /* set DMA destination endpoint (no increment) */ + pCCD->DMADSTEND = (uint32_t)&hDevice->pDev->KH_DATA1; + + /* set the initial write address */ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + + /* set the DMA Control Data Configuration register */ + pCCD->DMACDC = + ( ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) + | ((uint32_t)ADI_DMA_INCR_4_BYTE << DMA_BITP_CTL_SRC_INC) + | ((uint32_t)ADI_DMA_WIDTH_4_BYTE << DMA_BITP_CTL_SRC_SIZE) + | ((uint32_t)ADI_DMA_RPOWER_2 << DMA_BITP_CTL_R_POWER) + | (uint32_t)((hDevice->nRemainingBytes/sizeof(uint32_t) - 1u) << DMA_BITP_CTL_N_MINUS_1) + | ((uint32_t)DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL) ); + + /* set auto-increment and DMA enable bits, launching transder */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + SET_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + } else { + return ADI_FEE_ERR_NO_DATA_TO_TRANSFER; + } + + return ADI_FEE_SUCCESS; +} + + +/* Initiate transfer */ +static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice) +{ + ADI_FEE_RESULT result = ADI_FEE_SUCCESS; + + /* If a transfer is in progress or if the pending buffers are empty + * the return as there is nothing to be done now + */ + if (true == hDevice->bTransferInProgress) + { + return ADI_FEE_ERR_DEVICE_BUSY; + } + + /* Wait for the flash to not be busy */ + BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY); + + /* clear internal errors */ + hDevice->feeError = 0u; + hDevice->dmaError = ADI_FEE_SUCCESS; + + /* Set the bool variable to signify that a transfer is in progress */ + hDevice->bTransferInProgress = true; + + /* clear any command interrupt enables */ + CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* clear any dangeling command-related status */ + hDevice->pDev->STAT = BITM_FLCC_STAT_WRALCOMP | BITM_FLCC_STAT_CMDCOMP | BITM_FLCC_STAT_CMDFAIL; + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* Call the corresponding Transfer functions */ + if (true == hDevice->bUseDma) { + result = InitiateDmaTransfer(hDevice); + } else { + result = InitiatePioTransfer(hDevice); + } + + return result; +} + + +/* hide the interrupt handlers from DoxyGen */ +/*! \cond PRIVATE */ + +/* Flash PIO interrupt handler */ +void Flash0_Int_Handler(void) +{ + ISR_PROLOG(); + + /* post flag */ + bool bPost = false; + bool bError = false; + + /* recover the driver handle */ + ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice; + +#ifdef ADI_DEBUG + /* Return if the device is not opened - spurious interrupts */ + if (hDevice == NULL) { + return; + } +#endif + + /* update status cache and clear it right away on the controller */ + hDevice->FlashStatusCopy = hDevice->pDev->STAT; + hDevice->pDev->STAT = hDevice->FlashStatusCopy; + + /* check for flash device errors */ + hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy); + if (0u != hDevice->feeError) { + bError = true; + } + + /* if no errors */ + if (false == bError) { + + if (0u != (BITM_FLCC_STAT_WRALCOMP & hDevice->FlashStatusCopy)) { + + /* write-almost-complete */ + + /* if more data to write... */ + if (0u != hDevice->nRemainingBytes) { + + /* set next write the address */ + hDevice->pDev->KH_ADDR = (uint32_t)hDevice->pNextWriteAddress; + hDevice->pNextWriteAddress += 2; + + /* set next key-hole data */ + hDevice->pDev->KH_DATA0 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->pDev->KH_DATA1 = *hDevice->pNextReadAddress; + hDevice->pNextReadAddress++; + hDevice->nRemainingBytes -= sizeof(uint64_t); + + /* initiate next write */ + hDevice->pDev->CMD = ENUM_FLCC_CMD_WRITE; + + } else { + + /* no more data to write... + wait for current write-almost-complete status to transition to not busy */ + BusyWait (hDevice, BITM_FLCC_STAT_CMDBUSY); + + /* set post flag */ + bPost = true; + } + + } else if (0u != (BITM_FLCC_STAT_CMDCOMP & hDevice->FlashStatusCopy)) { + + /* command-complete */ + + /* this path is for blocking-mode commands (erase, verify, abort, etc.) */ + + /* set post flag */ + bPost = true; + + } else { + /* no other interrupt types expected */ + } + } else { + /* error(s) detected... set the post flag */ + bPost = true; + } + + /* singular post */ + if (true == bPost) { + + /* clear the command interrupt enables */ + CLR_BITS(hDevice->pDev->IEN, (BITM_FLCC_IEN_WRALCMPLT | BITM_FLCC_IEN_CMDCMPLT | BITM_FLCC_IEN_CMDFAIL)); + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* mark transfer complete */ + hDevice->bTransferInProgress = false; + + /* dispatch callback (if we have one...) */ + if (0u != hDevice->pfCallback) { + if (false == bError) { + /* no error, pass success flag to callback */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL); + } else { + /* error condition, pass error flag and error status to callback */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError); + } + } + + /* post the semaphore */ + SEM_POST(hDevice); + } + + ISR_EPILOG(); +} + + +/* Flash DMA interrupt handler */ +void DMA_FLASH0_Int_Handler (void) +{ + /* rtos prologue */ + ISR_PROLOG() + ; + + /* recover the driver handle */ + ADI_FEE_HANDLE hDevice = fee_device_info[0].hDevice; + + /* update status cache and clear it right away on the controller */ + hDevice->FlashStatusCopy = hDevice->pDev->STAT; + hDevice->pDev->STAT = hDevice->FlashStatusCopy; + + /* capture any hw error status */ + hDevice->feeError = (ADI_FEE_STATUS_ERROR_MASK & hDevice->FlashStatusCopy); + + /* clear auto-increment and dma enable bits */ + hDevice->pDev->KEY = ENUM_FLCC_KEY_USERKEY; + CLR_BITS (hDevice->pDev->UCFG, (BITM_FLCC_UCFG_AUTOINCEN | BITM_FLCC_UCFG_KHDMAEN)); + hDevice->pDev->KEY = 0u; + + /* clear the remaining count, as it should all have gone in one swoop */ + hDevice->nRemainingBytes = 0u; + + /* mark transfer complete */ + hDevice->bTransferInProgress = false; + + /* dispatch callback (if we have one...) */ + if (0u != hDevice->pfCallback) { + + /* no errors, notify success */ + if ((0u == hDevice->feeError) && (0u == hDevice->dmaError)) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_BUFFER_PROCESSED, (void*)NULL); + + /* flash hardware error */ + } else if (0u == hDevice->feeError) { + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)ADI_FEE_CALLBACK_EVENT_DEVICE_ERROR, (void*)hDevice->feeError); + + /* flash dma error */ + } else if (0u == hDevice->dmaError) { + /* DMA error */ + hDevice->pfCallback (hDevice->pCBParam, (uint32_t)hDevice->dmaError, NULL); + } else { + /* no other cases... */ + } + } + + /* post the semaphore */ + SEM_POST(hDevice); + + ISR_EPILOG(); +} + +/*! \endcond */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c new file mode 100755 index 00000000000..d5b6027573f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c @@ -0,0 +1,116 @@ +/* + ***************************************************************************** + * @file: adi_flash_data.c + * @brief: Data declaration for Flash Device Driver + * @date: $Date$ + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be consciously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FEE_DATA_C +#define ADI_FEE_DATA_C + + /*! \cond PRIVATE */ + +#include +#include "adi_flash_def.h" +#include "adi_flash_config.h" + +/* Stores the information about the specific device */ +static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] = +{ + /* only one flash instance at this time */ + { pADI_FLCC0, /* Flash controller pointer */ + FLCC_EVT_IRQn, /* Flash PIO interrupt number */ + DMA0_CH15_DONE_IRQn, /* Flash DMA interrupt number */ + FLASH_CHANn, /* Flash DMA channel (15) number */ + NULL, /* Flash static config info */ + NULL /* Flash driver handle */ + }, +}; + + +/* build Flash Application configuration array */ +static ADI_FEE_CONFIG gConfigInfo[ADI_FEE_NUM_INSTANCES] = +{ + /* the one-and-only (so far) instance data for FEE0... */ + { + /* ECC interrupt enable settings (IEN register) */ + ( (ADI_FEE_CFG_ECC_ERROR_RESPONSE << BITP_FLCC_IEN_ECC_ERROR) + | (ADI_FEE_CFG_ECC_CORRECTION_RESPONSE << BITP_FLCC_IEN_ECC_CORRECT) + ), + + /* timing parameter settings (TIME_PARAM0 register) */ + ( (ADI_FEE_CFG_PARAM0_TNVH1 << BITP_FLCC_TIME_PARAM0_TNVH1) + | (ADI_FEE_CFG_PARAM0_TERASE << BITP_FLCC_TIME_PARAM0_TERASE) + | (ADI_FEE_CFG_PARAM0_TRCV << BITP_FLCC_TIME_PARAM0_TRCV) + | (ADI_FEE_CFG_PARAM0_TNVH << BITP_FLCC_TIME_PARAM0_TNVH) + | (ADI_FEE_CFG_PARAM0_TPROG << BITP_FLCC_TIME_PARAM0_TPROG) + | (ADI_FEE_CFG_PARAM0_TPGS << BITP_FLCC_TIME_PARAM0_TPGS) + | (ADI_FEE_CFG_PARAM0_TNVS << BITP_FLCC_TIME_PARAM0_TNVS) + | (ADI_FEE_CFG_PARAM0_CLKDIV << BITP_FLCC_TIME_PARAM0_DIVREFCLK) + ), + + /* more timing parameter settings (TIME_PARAM1 register) */ + ( (ADI_FEE_CFG_PARAM1_WAITESTATES << BITP_FLCC_TIME_PARAM1_WAITSTATES) + | (ADI_FEE_CFG_PARAM1_TWK << BITP_FLCC_TIME_PARAM1_TWK) + ), + + /* system interrupt abort enables (ABORT_EN_XX registers) */ + (ADI_FEE_CFG_ABORT_EN_LO), + (ADI_FEE_CFG_ABORT_EN_HI), + + /* ECC configuration register settings (ECC_CFG register) */ + (((ADI_FEE_CFG_ECC_START_PAGE << FEE_PAGE_SHIFT) & BITM_FLCC_ECC_CFG_PTR) +#if (ADI_FEE_CFG_ENABLE_ECC_FOR_INFO_SPACE == 1u) + | (BITM_FLCC_ECC_CFG_INFOEN) +#endif +#if (ADI_FEE_CFG_ENABLE_ECC == 1u) + | (BITM_FLCC_ECC_CFG_EN) +#endif + ) + } /* end device 0 settings */ +}; + +/*! \endcond */ + + +#endif /* ADI_FEE_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h new file mode 100755 index 00000000000..c14be74be09 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_def.h @@ -0,0 +1,181 @@ +/*! + ***************************************************************************** + @file: adi_flash_def.h + @brief: Internal Flash device driver definitions and macros + @date: $Date: 2014-11-28 01:48:03 -0500 (Fri, 28 Nov 2014) $ + ----------------------------------------------------------------------------- +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_FLASH_DEF_H +#define ADI_FLASH_DEF_H + +/*! \cond PRIVATE */ + +#include +#include + +#include + +/* fixed number of flash controllers */ +#define ADI_FEE_NUM_INSTANCES (1u) + +/* STATUS register error mask */ +#define ADI_FEE_STATUS_ERROR_MASK ( BITM_FLCC_STAT_ACCESS_MODE \ + | BITM_FLCC_STAT_CACHESRAMPERR \ + | BITM_FLCC_STAT_ECCDCODE \ + | BITM_FLCC_STAT_ECCINFOSIGN \ + | BITM_FLCC_STAT_SIGNERR \ + | BITM_FLCC_STAT_OVERLAP \ + | BITM_FLCC_STAT_ECCRDERR \ + | BITM_FLCC_STAT_ECCERRCMD \ + | BITM_FLCC_STAT_SLEEPING \ + | BITM_FLCC_STAT_CMDFAIL) + + +#if defined(__ECC__) +#define ALIGN +#define ALIGN4 _Pragma("align(4)") +#elif defined(__ICCARM__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#elif defined (__GNUC__) +#define ALIGN _Pragma("pack()") +#define ALIGN4 _Pragma("pack(4)") +#endif + +/* Flash Size and Page/Block macros: + 512kB total user space, broken up as + 256-pages, 2kB/page + 32-blocks, 16kB/block + 8 pages/block +*/ +#define FEE_FLASH_SIZE (0x80000u) /* 512kB total */ +#define FEE_PAGE_SHIFT (11u) /* 2kB page size */ +#define FEE_BLOCK_SHIFT (14u) /* 16kB block size */ +#define FEE_MAX_NUM_PAGES (FEE_FLASH_SIZE >> FEE_PAGE_SHIFT) /* max number of pages (256) */ +#define FEE_MAX_NUM_BLOCKS (FEE_FLASH_SIZE >> FEE_BLOCK_SHIFT) /* max number of blocks (32) */ + +#if (ADI_FEE_CFG_ECC_START_PAGE >= FEE_MAX_NUM_PAGES) +#error "ADI_FEE_CFG_ECC_START_PAGE range is invalid" +#endif + + +/* INTERNAL DRIVER STATIC FUNCTION PROTOTYPES */ + +/* Send a command to the flash controller, but does no pend on it... */ +static ADI_FEE_RESULT SendCommand (ADI_FEE_HANDLE const hDevice, uint32_t const cmd); + +/* generic transfer initiator... dispatches to InitiatePioTransfer() or InitiateDmaTransfer() */ +static ADI_FEE_RESULT InitiateTransfer (ADI_FEE_HANDLE const hDevice); + +/* PIO initiator */ +static ADI_FEE_RESULT InitiatePioTransfer (ADI_FEE_HANDLE const hDevice); + +/* DMA initiator */ +static ADI_FEE_RESULT InitiateDmaTransfer (ADI_FEE_HANDLE const hDevice); + +/* interrupt handlers */ +void Flash0_Int_Handler(void); +void DMA_FLASH0_Int_Handler (void); + +/* INTERNAL DRIVER DATATYPES */ + +/* + ***************************************************************************** + * FEE Configuration structure. + *****************************************************************************/ +typedef struct __ADI_FEE_CONFIG { + uint32_t eccIrqEnables; /* ECC interrupt enables. */ + uint32_t param0; /* TIME_PARAM0 register. */ + uint32_t param1; /* TIME_PARAM1 register. */ + uint32_t abortEnableLo; /* Lower interrupt abort enables (IRQs 0-31). */ + uint32_t abortEnableHi; /* Upper interrupt abort enables (IRQs 32-63.) */ + uint32_t eccConfig; /* ECC_CFG register. */ +} ADI_FEE_CONFIG; + + +/* Flash physical device instance data */ +typedef struct __ADI_FEE_DEVICE_INFO { + + ADI_FLCC_TypeDef *pDev; /* Pointer to the physical controller. */ + IRQn_Type pioIrqNum; /* The flash controller PIO interrupt number. */ + IRQn_Type dmaIrqNum; /* The flash controller DMA interrupt number. */ + DMA_CHANn_TypeDef dmaChanNum; /* The flash controller DMA channel number. */ + ADI_FEE_CONFIG *pConfig; /* Pointer to user config info. */ + ADI_FEE_HANDLE hDevice; /* Pointer the device memory (supplied by the application). */ + +} ADI_FEE_DEVICE_INFO; + + +/* Flash driver instance data structure */ +typedef struct __ADI_FEE_DEV_DATA_TYPE { + + /* make sure to synchronize ANY size changes with ADI_FLASH_MEMORY_SIZE macro in adi_flash.h */ + + /* NOTE: "volatile" storage class on all interrupt-modified valuables */ + + /* device attributes */ + ADI_FLCC_TypeDef *pDev; /* Pointer top physical flash controller. */ + ADI_FEE_DEVICE_INFO *pDevInfo; /* Pointer to hardware device attributes. */ + + /* callback info */ + ADI_CALLBACK pfCallback; /* Registered callback function address. */ + void *pCBParam; /* Registered callback user parameter. */ + + /* internal driver state variables */ + bool bUseDma; /* DMA control flag (from user). */ + bool bSubmitCalled; /* Flag to identify if a buffer was "submitted". */ + volatile uint32_t FlashStatusCopy; /* Clop of latest flash status register. */ + volatile uint32_t feeError; /* Flash error collector. */ + volatile ADI_FEE_RESULT dmaError; /* DMA error collector. */ + volatile bool bTransferInProgress; /* Flag indicating if a transfer is in progress. */ + + /* data info */ + volatile uint32_t *pNextWriteAddress; /* Pointer to next write data in flash space. */ + volatile uint32_t *pNextReadAddress; /* Pointer to next read data in user buffer. */ + volatile uint32_t nRemainingBytes; /* Number of remaining bytes still to transfer. */ + + SEM_VAR_DECLR /* Blocking object: "Semaphore" for rtos, "bLowPowerExitFlag" for non-rtos. */ + +} ADI_FEE_DEV_DATA_TYPE; + +/*! \endcond */ + +#endif /* ADI_FLASH_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c new file mode 100755 index 00000000000..3725f72ead5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio.c @@ -0,0 +1,975 @@ +/* + ***************************************************************************** + @file: adi_gpio.c + @brief: GPIO device driver implementation. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "adi_gpio_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm123,Pm073,Pm143,Pm140 +#endif /* __ICCARM__ */ + +/* Debug function declarations */ +#ifdef ADI_DEBUG +static bool ArePinsValid (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins); /*!< tests for pins validity */ +#endif /* ADI_DEBUG */ + + +static void CommonInterruptHandler (const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq); +void GPIO_A_Int_Handler(void); +void GPIO_B_Int_Handler(void); + +/*========== D A T A ==========*/ +static ADI_GPIO_DRIVER adi_gpio_Device = +{ + { + pADI_GPIO0, /* port 0 base address */ + pADI_GPIO1, /* port 1 base address */ + pADI_GPIO2, /* port 2 base address */ + pADI_GPIO3, /* port 3 base address */ + }, + + NULL +}; +/*! \endcond */ + +/*! \addtogroup GPIO_Driver GPIO Driver + * @{ + + @brief GPIO port and pin identifiers + @note The application must include drivers/gpio/adi_gpio.h to use this driver + @details The documented macros can be passed to the following functions: + - adi_gpio_OutputEnable() + - adi_gpio_PullUpEnable() + - adi_gpio_SetHigh() + - adi_gpio_SetLow() + - adi_gpio_Toggle() + - adi_gpio_SetData() + - adi_gpio_GetData() + + To control a single GPIO, these macros can be passed to the functions one + at a time. For example, to set the GPIO on port 2, pin 4 to a logical high + level, the following is used: + + 
+      adi_gpio_SetHigh(ADI_GPIO_PORT2, ADI_GPIO_PIN_4)
+
+ + Multiple GPIOs, so long as they reside on the same port, can be controlled + simultaneously. These macros can be OR-ed together and passed to the + functions. For example, to set the GPIOs on port 2, pins 3, 4 and 7 to + a logical low level, the following is used: + + 
+      adi_gpio_SetLow(ADI_GPIO_PORT2, ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7)
+
+ + For the sensing, or adi_gpio_Getxxx, functions, the passed pValue parameter is written with + a packed value containing the status of the requested GPIO pins on the given port. + + If information is required for a single pin, return value can be directly used + For example to see if pin 4 on port 2 has the pull up enabled, the following is used: + adi_gpio_GetData(ADI_GPIO_PORT2, ADI_GPIO_PIN_4, &pValue) + pValue will contain the required information. + + If information is required for multiple pins, following method is required: + 
+        adi_gpio_GetData(ADI_GPIO_PORT2, (ADI_GPIO_PIN_3 | ADI_GPIO_PIN_4 | ADI_GPIO_PIN_7), &pValue)
+
+ To test if pin 4 on port 2 has pull up enabled, the following is used: + 
+        if   (pValue & ADI_GPIO_PIN_4) {
+                    the pull up is enabled for pin 4 on port 2
+        } else {
+                    the pull up is disabled for pin 4 on port 2
+        }
+
+ + */ + +/*! + @brief Initializes the GPIO functions. + + @details This function initializes the GPIO driver. This function should be called before calling any of the GPIO + driver APIs. + + @param[in] pMemory Pointer to the memory required for the driver to operate. + The size of the memory should be at least #ADI_GPIO_MEMORY_SIZE bytes. + + @param[in] MemorySize Size of the memory (in bytes) passed in pMemory parameter. + + @return Status + - ADI_GPIO_SUCCESS If successfully initialized the GPIO driver. + - ADI_GPIO_NULL_PARAMETER [D] If the given pointer to the driver memory is pointing to NULL. + - ADI_GPIO_INVALID_MEMORY_SIZE [D] If the given memory size is not sufficient to operate the driver. + + @note This function clears memory reserved for managing the callback function when it is called + for the first time. It is expected from user to call "adi_gpio_UnInit" function when the GPIO service is no longer required. + + @sa adi_gpio_UnInit +*/ +ADI_GPIO_RESULT adi_gpio_Init( + void* const pMemory, + uint32_t const MemorySize +) +{ + +#ifdef ADI_DEBUG + /* Verify the given memory pointer */ + if(NULL == pMemory) + { + return ADI_GPIO_NULL_PARAMETER; + } + /* Check if the memory size is sufficient to operate the driver */ + if(MemorySize < ADI_GPIO_MEMORY_SIZE) + { + return ADI_GPIO_INVALID_MEMORY_SIZE; + } + assert(ADI_GPIO_MEMORY_SIZE == sizeof(ADI_GPIO_DEV_DATA)); +#endif + + /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */ + if (NULL == adi_gpio_Device.pData) + { + uint32_t i; + + adi_gpio_Device.pData = (ADI_GPIO_DEV_DATA*)pMemory; + + /* Initialize the callback table */ + for (i = 0u; i < ADI_GPIO_NUM_INTERRUPTS; i++) + { + adi_gpio_Device.pData->CallbackTable[i].pfCallback = NULL; + adi_gpio_Device.pData->CallbackTable[i].pCBParam = NULL; + } + + /* Enable the group interrupts */ + NVIC_EnableIRQ(SYS_GPIO_INTA_IRQn); + NVIC_EnableIRQ(SYS_GPIO_INTB_IRQn); + } + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Un-initialize the GPIO driver. + + @details Terminates the GPIO functions, leaving everything unchanged. + + @return Status + - #ADI_GPIO_SUCCESS if successfully uninitialized + - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized + + @sa adi_gpio_Init +*/ +ADI_GPIO_RESULT adi_gpio_UnInit(void) +{ + +#ifdef ADI_DEBUG + /* IF (not initialized) */ + if (NULL == adi_gpio_Device.pData) + { + /* return error if not initialized */ + return (ADI_GPIO_NOT_INITIALIZED); + } +#endif + + /* Clear the data pointer */ + adi_gpio_Device.pData = NULL; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Group the pins for the given group interrupt. + + @details Group the given pins for the Group A/B interrupt. + Applications can register/unregister a callback using the #adi_gpio_RegisterCallback API + to get a notification when the group interrupt occurs. + + @param[in] Port GPIO port number to be operated on. + @param[in] eIrq Interrupt (Group A/B) to which the pin(s) are to be grouped. + @param[in] Pins The GPIO pins which needs to be grouped. + Pin bits that are set enable the interrupt for the group A/B. + Pin bits that are clear disable the interrupt for the group A/B. + @return Status + - #ADI_GPIO_SUCCESS If successfully grouped the given pins. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver is not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] The given pins are invalid. + + @sa adi_gpio_RegisterCallback + @sa adi_gpio_SetGroupInterruptPolarity +*/ +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPins(const ADI_GPIO_PORT Port, const ADI_GPIO_IRQ eIrq, const ADI_GPIO_DATA Pins) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + switch (eIrq) + { + case SYS_GPIO_INTA_IRQn: + pPort->IENA = Pins; + break; + case SYS_GPIO_INTB_IRQn: + pPort->IENB = Pins; + break; + default: + break; /* This shall never reach */ + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Set the interrupt polarity for the given pins. + + @details Sets the interrupt polarity for the given pins for the given port. + When the corresponding bit is set an interrupt is generated when the pin transitions from low-to-high. When the corresponding bit is cleared an interrupt is generated when the pin transitions from high-to-low. + + @param[in] Port GPIO port number to be operated on. + @param[in] Pins Pins whose polarity to be set. + + @return Status + - #ADI_GPIO_SUCCESS If successfully set the polarity. + - #ADI_GPIO_NOT_INITIALIZED [D] If not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_RegisterCallback + @sa adi_gpio_SetGroupInterruptPins +*/ +ADI_GPIO_RESULT adi_gpio_SetGroupInterruptPolarity(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + pPort->POL = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Output Drivers for GPIO Pin(s) + + @details Enables/disables the output drivers for the given GPIO pin(s) on + the given port. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[in] bFlag Boolean value describing the action to be taken + - true enables the output driver + - false disables the output driver + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_OutputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + /* enable output */ + pPort->OEN |= Pins; + } else + { + /* disable output */ + pPort->OEN &= (uint16_t)~Pins; + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Input Drivers for GPIO Pin(s) + + @details Enables/disables the input drivers for the given GPIO pin(s) on + the given port. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @param[in] bFlag Boolean value describing the action to be taken + - true enables the input driver + - false disables the input driver + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_InputEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + /* enable input */ + pPort->IEN |= Pins; + } else + { + /* disable input */ + pPort->IEN &= (uint16_t)~Pins; + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Enables/Disables the Pull-Up for GPIO Pin(s) + + @details Enables/disables the internal pull-up for the given GPIO pin(s) on + the given port. API simply enables/disables whatever the hard-wired + pulls (up/down) are. + + @param[in] Port The GPIO port to be configured. + @param[in] Pins One or more GPIO pins to be configured. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[in] bFlag Boolean value describing the action to be taken + - true enables the pull-up + - false disables the pull-up + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. +*/ +ADI_GPIO_RESULT adi_gpio_PullUpEnable(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, const bool bFlag) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + ADI_ENTER_CRITICAL_REGION(); + if (bFlag) + { + pPort->PE |= Pins; + } else + { + pPort->PE &= (uint16_t)(~Pins); + } + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_GPIO_SUCCESS); +} + +/*! + + @brief Sets the Given GPIO pin(s) to a Logical High Level + + @details Sets the given GPIO pin(s) on the given port to a logical high + level. + + @param[in] Port GPIO port whose pins need to be set to logical high level. + @param[in] Pins One or more GPIO pins to be set to logical high. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetHigh(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the given GPIOs high */ + pPort->SET = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Sets the Given GPIO pin(s) to a Logical Low Level + + @details Sets the given GPIO pin(s) on the given port to a logical low + level. + + @param[in] Port The GPIO port whose pins need to be set to logical low level. + @param[in] Pins One or more GPIO pins to be whose logic level to be set. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_Toggle, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetLow(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the given GPIOs low */ + pPort->CLR = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Toggles the Logical Level of the Given GPIO pin(s) + + @details Toggles the logical level of the given GPIO pin(s) on the given port. + If a given GPIO pin is at a logical low level, this function will + change the level to a logical high value. If a given GPIO pin is + at a logical high level, this function will change the level to a + logical low value. + + @param[in] Port The GPIO port whose pins to be toggled. + @param[in] Pins The GPIO pins whose logic level to be toggled. GPIO + pins can be passed one at a time or in combination. To + configure a single GPIO pin, a single GPIO value is + passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + + @return Status + - #ADI_GPIO_SUCCESS If successfully configured. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_SetData, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_Toggle(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* toggle the given GPIOs */ + pPort->TGL = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + + @brief Sets the logic level of all GPIO pins on the given port to + a given logic level. + + @details Sets the logic level of all the GPIO pins on the given port to the + given value. + + @param[in] Port The GPIO port whose pins logic level to be set. + @param[in] Pins The GPIO pins whose logic level to be set high. All other + GPIO pins on the port will be set to a logical low level. + For example, to set pins 0 and 1 to a logical high level and + all other pins to a logical low level, this parameter should + be passed as #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_1. + + @return Status + - #ADI_GPIO_SUCCESS If successfully set the given data. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_GetData +*/ +ADI_GPIO_RESULT adi_gpio_SetData(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* set the GPIOs as directed */ + pPort->OUT = Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Gets/Senses the input level of all GPIO Pins on the given port. + + @details Gets the level of all GPIO input pins on the given port. + + @param[in] Port The GPIO port whose input level to be sensed. + @param[in] Pins The GPIO pins to be sensed. To sense a single GPIO pin, a single + GPIO value is passed for this parameter. For example, #ADI_GPIO_PIN_4. + Alternatively, multiple GPIO pins can be configured + simultaneously by OR-ing together GPIO pin values and + passing the resulting value for this parameter. For + example, #ADI_GPIO_PIN_0 | #ADI_GPIO_PIN_5 | #ADI_GPIO_PIN_6. + @param[out] pValue The passed pValue parameter is written with a packed value containing + the status of all the requested GPIO pins on the given port. + + To get the status of a single GPIO pin, return value can be directly used. + For example to see if pin 4 on port 2 is a logical high level, the following is used: + 
+        adi_gpio_GetData(#ADI_GPIO_PORT2, #ADI_GPIO_PIN_4, &pValue)
+
+ pValue will contain the required information. + + If information is required for multiple pins, following method is required: + 
+        adi_gpio_GetData(#ADI_GPIO_PORT2, (#ADI_GPIO_PIN_3 | #ADI_GPIO_PIN_4 | #ADI_GPIO_PIN_7), &pValue)
+
+ + To test if pin 4 on port 2 is a logical high level, the following is used: + 
+        if  (pValue & ADI_GPIO_PIN_4) {
+            pin 4 on port 2 is a logical high value
+        } else {
+            pin 4 on port 2 is a logical low value
+        }
+
+ + @return Status + - #ADI_GPIO_SUCCESS If successfully sensed the input pins. + - #ADI_GPIO_NOT_INITIALIZED [D] If GPIO driver not yet initialized. + - #ADI_GPIO_INVALID_PINS [D] If the given pins are invalid. + + @sa adi_gpio_SetHigh, adi_gpio_SetLow, adi_gpio_Toggle, adi_gpio_SetData +*/ +ADI_GPIO_RESULT adi_gpio_GetData (const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins, uint16_t* const pValue) +{ + + ADI_GPIO_TypeDef *pPort; /* pointer to port registers */ + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } + + /* validate the pins */ + if (!ArePinsValid(Port, Pins)) + { + return (ADI_GPIO_INVALID_PINS); + } +#endif + + pPort = adi_gpio_Device.pReg[Port]; + + /* return the status of the GPIOs */ + *pValue = (pPort->IN) & Pins; + + return (ADI_GPIO_SUCCESS); +} + + +/*! + @brief Register or unregister an application callback function for group (A/B) interrupts. + + @details Applications may register a callback function that will be called when a + GPIO group (A/B) interrupt occurs. + + The driver dispatches calls to registered callback functions when the + properly configured pin(s) latches an external interrupt input on the GPIO + pin(s). The callback is dispatched with the following parameters, respectively: + - application-provided callback parameter (\a pCBParam), + - The GPIO Port, + - The GPIO Pins. + + @param[in] eIrq The interrupt for which the callback is being registered. + @param[in] pfCallback Pointer to the callback function. This can be passed as NULL to + unregister the callback. + @param[in] pCBParam Callback parameter which will be passed back to the application + when the callback is called.. + + @return Status + - #ADI_GPIO_SUCCESS if successfully registered the callback. + - #ADI_GPIO_NOT_INITIALIZED [D] if not yet initialized + - #ADI_GPIO_INVALID_INTERRUPT [D] if interrupt ID is invalid + + @sa adi_gpio_SetGroupInterruptPolarity +*/ +ADI_GPIO_RESULT adi_gpio_RegisterCallback (const ADI_GPIO_IRQ eIrq, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ + uint16_t index = 0u; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == adi_gpio_Device.pData) + { + return (ADI_GPIO_NOT_INITIALIZED); + } +#endif + + index = (uint16_t)eIrq - (uint16_t)SYS_GPIO_INTA_IRQn + ADI_GPIO_IRQ_GROUPA_INDEX; + + ADI_ENTER_CRITICAL_REGION(); + + adi_gpio_Device.pData->CallbackTable[index].pfCallback = pfCallback; + adi_gpio_Device.pData->CallbackTable[index].pCBParam = pCBParam; + + ADI_EXIT_CRITICAL_REGION(); + + /* return the status */ + return (ADI_GPIO_SUCCESS); +} + + + +/*@}*/ + +/*! \cond PRIVATE */ +/* All of the following is excluded from the doxygen output... */ + +/* Common group (A/B) interrupt handler */ +static void CommonInterruptHandler(const ADI_GPIO_IRQ_INDEX index, const IRQn_Type eIrq) +{ + ADI_GPIO_PORT Port; + ADI_GPIO_TypeDef *pPort; + ADI_GPIO_DATA Pins; + ADI_GPIO_DATA nIntEnabledPins; + + ADI_GPIO_CALLBACK_INFO *pCallbackInfo = &adi_gpio_Device.pData->CallbackTable[index]; + + /* Loop over all the ports. */ + for(Port=ADI_GPIO_PORT0; PortIENA; + } + else /* Is the interrupt is for GROUP B */ + { + nIntEnabledPins = pPort->IENB; + } + + /* Clear only required interrupts */ + Pins = ((pPort->INT) & nIntEnabledPins); + pPort->INT = Pins; + + /* params list is: application-registered cbParam, Port number, and interrupt status */ + if((pCallbackInfo->pfCallback != NULL) && (Pins != 0u)) + { + pCallbackInfo->pfCallback (pCallbackInfo->pCBParam, (uint32_t)Port, &Pins); + } + } +} + +/* Interrupt A handler */ +void GPIO_A_Int_Handler(void) +{ + ISR_PROLOG() + CommonInterruptHandler(ADI_GPIO_IRQ_GROUPA_INDEX, SYS_GPIO_INTA_IRQn); + ISR_EPILOG() +} + +/* Interrupt B handler */ +void GPIO_B_Int_Handler (void) +{ + ISR_PROLOG() + CommonInterruptHandler(ADI_GPIO_IRQ_GROUPB_INDEX, SYS_GPIO_INTB_IRQn); + ISR_EPILOG() +} + +#ifdef ADI_DEBUG + + +/*! + @brief Tests a Pins Parameter for Validity + + @details A debug function that checks a Pins parameter for validity + + @param[in] Pins Logical OR-ing of one or more ADI_GPIO_PIN_x values + + @return Status + - true the Pins value contains valid data + - false the Pins value contains invalid data +*/ +static bool ArePinsValid(const ADI_GPIO_PORT Port, const ADI_GPIO_DATA Pins) +{ + uint32_t PinValid = 0u; + + /* test for a valid pin */ + switch (Port) + { + case ADI_GPIO_PORT0: + PinValid = ~ADI_GPIO_PORT0_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT1: + PinValid = ~ADI_GPIO_PORT1_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT2: + PinValid = ~ADI_GPIO_PORT2_PIN_AVL & Pins; + break; + + case ADI_GPIO_PORT3: + PinValid = ~ADI_GPIO_PORT3_PIN_AVL & Pins; + break; + + default: + break; + } + + if (PinValid == 0u) + { + return true; + } + else + { + return false; + } +} +#endif /* ADI_DEBUG */ + +/*! \endcond */ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h new file mode 100755 index 00000000000..90282625df8 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/gpio/adi_gpio_def.h @@ -0,0 +1,94 @@ +/*! + ***************************************************************************** + * @file: adi_gpio_def.h + * @brief: GPIO Device Driver definition + ***************************************************************************** +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_GPIO_DEF_H +#define ADI_GPIO_DEF_H +/*! \cond PRIVATE */ + + +/*! local enum for callback table indexing */ +typedef enum +{ + /* Group interrupts */ + ADI_GPIO_IRQ_GROUPA_INDEX = (0x0), /*!< GroupA interrupt index. */ + ADI_GPIO_IRQ_GROUPB_INDEX = (0x1), /*!< GroupB interrupt index. */ + + ADI_GPIO_NUM_INTERRUPTS = (0x2), /*!< Number of GPIO interrupts */ + +} ADI_GPIO_IRQ_INDEX; + + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_GPIO_CALLBACK_INFO +{ + ADI_CALLBACK pfCallback; /*!< Callback function pointer */ + void *pCBParam; /*!< Callback parameter */ +} ADI_GPIO_CALLBACK_INFO; + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_GPIO_DEV_DATA +{ + ADI_GPIO_CALLBACK_INFO CallbackTable[ADI_GPIO_NUM_INTERRUPTS]; /*!< Callback Info for External interrupts */ +} ADI_GPIO_DEV_DATA; + +/*! \struct ADI_GPIO_DEVICE + + GPIO instance data + + This structure contains the "state" information for the + instance of the device. For GPIO there is only one + of these objects. +*/ +typedef struct _ADI_GPIO_DRIVER_STRUCT +{ + ADI_GPIO_TypeDef *pReg[ADI_GPIO_NUM_PORTS]; /*!< GPIO Ports Register base */ + ADI_GPIO_DEV_DATA *pData; /*!< Pointer to device data */ +} ADI_GPIO_DRIVER_STRUCT; + + +/* alias for the actual device structure */ +typedef ADI_GPIO_DRIVER_STRUCT ADI_GPIO_DRIVER; + +/*! \endcond */ +#endif /* ADI_GPIO_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c new file mode 100755 index 00000000000..cb8dba8001b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c.c @@ -0,0 +1,1169 @@ +/*! ***************************************************************************** + * @file: adi_i2c.c + * @brief: I2C device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This file contains the I2C device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup I2C_Driver I2C Driver + * @{ + * @brief Inter-Integrated Circuit (I2C) Driver + * @details The I2C Master device driver manages the on-chip I2C hardware to + * control the external two-wire I2C Bus interface, allowing communication with + * multiple I2C slave devices through the I2C slave device addressing scheme. + * @note The application must include drivers/i2c/adi_i2c.h to use this driver + */ + + /*! \cond PRIVATE */ +#include +#include +#include /* for "memset" */ +/*! \endcond */ + +#include +#include + + /*! \cond PRIVATE */ + +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* It is used in the _data.h file which isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ + +#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm088,Pm140 +#endif /* __ICCARM__ */ + +/* pull in internal data structures */ +#include "adi_i2c_data.c" + + +/* handy type-safe zero */ +uint16_t uZero16 = 0u; + +/* central busy checker */ +#define I2C_BUSY (uZero16 != ((hDevice->pDev->MSTAT) & (uint16_t)(BITM_I2C_MSTAT_MBUSY | BITM_I2C_MSTAT_LINEBUSY))) + +/*! + * Read/write bit. + */ + #define READ_NOT_WRITE (1u) + +/* Override "weak" default binding in startup.c */ +/*! \cond PRIVATE */ +extern void I2C0_Master_Int_Handler(void); +/*! \endcond */ + +#if defined(ADI_DEBUG) +/* + * Verifies a pointer to a driver points to one of the driver + * struct's internal to this file. + */ +static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice); +static bool IsDeviceHandle(ADI_I2C_HANDLE const hDevice) +{ + if ((i2c_device_info[0].hDevice != (hDevice)) && ((hDevice)->pDevInfo->hDevice != NULL)) { + return true; + } else { + return false; + } +} +#endif + + +/*! \endcond */ + + +/**********************************************************************************\ +|**********************************USER INTERFACE**********************************| +\**********************************************************************************/ + + +/*! + * @brief Initialize and allocate an I2C device for use in Master Mode. + * + * @param[in] DeviceNum Zero-based device index designating the I2C device to initialize. + * + * @param [in] pMemory Pointer to a 32-bit aligned buffer of size ADI_I2C_MEMORY_SIZE + * required by the driver for the operation of specified I2C device. + * + * @param [in] MemorySize Size of the buffer to which "pMemory" points. + * + * @param[out] phDevice The caller's device handle pointer for storing the initialized + * device instance data pointer. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_NUMBER [D] Invalid device index. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is already opened. + * - #ADI_I2C_INSUFFICIENT_MEMORY [D] Device memory is not sufficient. + * + * Initialize an I2C device using default user configuration settings (from adi_i2c_config.h) + * and allocate the device for use. Device is opened in Master mode only. + * + * No other I2C APIs may be called until the device open function is called. The returned + * device handle is required to be passed to all subsequent I2C API calls to identify the + * physical device instance to use. The user device handle (pointed to by phDevice) is set + * to NULL on failure. + * + * @note Currently, only a singular I2C physical device instance (device ID "0") exists. + * + * @sa adi_spi_Close(). + */ +ADI_I2C_RESULT adi_i2c_Open (uint32_t const DeviceNum, void* const pMemory, uint32_t const MemorySize, ADI_I2C_HANDLE* const phDevice) { + + /* make a device handle out of the user memory */ + ADI_I2C_HANDLE hDevice = (ADI_I2C_HANDLE)pMemory; + +#if defined(ADI_DEBUG) + /* check requested device number */ + if (DeviceNum >= (uint32_t)ADI_I2C_NUM_INSTANCES) { + return ADI_I2C_BAD_DEVICE_NUMBER; + } + + /* verify device is not already open */ + if (i2c_device_info[DeviceNum].hDevice != NULL) { + return ADI_I2C_DEVICE_IN_USE; + } + + /* verify memory size macro value */ + assert(ADI_I2C_MEMORY_SIZE == sizeof(ADI_I2C_DEV_DATA_TYPE)); + + /* verify user-provided memory meets requirement */ + if ((NULL == pMemory) || (MemorySize < (uint32_t)ADI_I2C_MEMORY_SIZE)) { + return ADI_I2C_INSUFFICIENT_MEMORY; + } +#endif + + /* store a bad handle in case of failure */ + *phDevice = NULL; + + /* + * Link user memory (handle) to ADI_I2C_DEVICE_INFO data structure. + * + * ADI_I2C_DEVICE_INFO <==> ADI_I2C_HANDLE + * + * Clear the ADI_I2C_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bRepearStart = false) + */ + i2c_device_info[DeviceNum].hDevice = (ADI_I2C_DEV_DATA_TYPE *)pMemory; + memset(pMemory, 0, MemorySize); + + /* also link device handle within __ADI_I2C_DEV_DATA_TYPE data structure */ + hDevice->pDevInfo = &i2c_device_info[DeviceNum]; + /* + * Although the ADI_I2C_DEVICE_INFO struct has the physical device pointer + * for this instance, copying it to the ADI_I2C_HANDLE struct (in user memory) + * will minimize the runtime footprint and cycle count when accessing the I2C + * registers. + */ + hDevice->pDev = i2c_device_info[DeviceNum].pDev; + + /* store a pointer to user's static configuration settings */ + hDevice->pDevInfo->pConfig = (ADI_I2C_CONFIG*)&gConfigInfo[DeviceNum]; + + /* create the semaphore */ + SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice); + + /* store device handle into user handle */ + *phDevice = (ADI_I2C_HANDLE)hDevice; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Uninitialize and deallocate an I2C device. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * + * Uninitialize and release an allocated I2C device, and memory associated with it + * for other use. + * + * @note The user memory is released from use by the I2C driver, but is not freed. + * + * @sa adi_spi_Open(). + */ +ADI_I2C_RESULT adi_i2c_Close (ADI_I2C_HANDLE const hDevice) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* destroy semaphore */ + SEM_DELETE(hDevice,ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + ADI_I2C_RESULT ignore ADI_UNUSED_ATTRIBUTE = i2cReset(hDevice); + + /* stub handle */ + hDevice->pDevInfo->hDevice = NULL; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Blocking I2C Master-Mode data read/write API. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pTransaction Pointer to I2C transaction data struct. + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] An I2C transaction is already underway. + * - #ADI_I2C_INVALID_PARAMETER [D] Invalid data pointer or count is detected. + * - #ADI_I2C_HW_ERROR_DETECTED A hardware error occurred, check \a pHwErrors. + * + * Request a blocking I2C data transfer (read or write, not both as I2C is unidirectional bus) + * with or without preceding prologue transmitted. Control is not returned to the calling + * application until the transfer is complete. Buffer allocations are made by the calling code + * (the application). + * + * The optional prologue (if present) and MANDATORY transaction data pointers are used to read or + * write data over the I2C serial bus according to the prologue and data pointers and corresponding + * size information contained in the \a pTransaction parameter block. The most recently set slave + * target address (set statically with user configuration settings contained in adi_i2c_config.h file + * or set dynamically (at run-time) via the #adi_i2c_SetSlaveAddress() API) is used to address the + * specific destination slave device on the I2C bus. + * + * If present, the prologue (typically, an addressing phase conveying a memory/register address or + * slave device command) is transmitted prior to the data read or write phase, with or without + * an intervening I2C STOP condition. The prologue data is entirely slave device dependent. + * + * In the case of a prologue followed by a data read operation, the I2C bus direction must be + * reversed following the prologue transmit. In this case, The usual I2C STOP condition following + * the prologue (if present) transmit may be suppressed by setting the \a bRepeatStart transaction + * parameter "true". In this case, a second (repeat) START condition is "transmitted" between the + * addressing phase (prologue transmit) and the data phase of the read sequence... \a without an + * intervening STOP condition. This is commonly referred to as the "combined format" in which the + * I2C bus direction is reversed halfway through the transaction without releasing control of the + * I2C bus arbitration. The REPEAT-START condition is a common I2C bus protocol required by many + * I2C slave devices. + * + * In the case of a prologue followed by a data write operation, there is no need to turn the bus + * around and so the \a bRepeatStart parameter is ignored. + * + * @note Application must check the return code to verify if any I2C Bus errors occurred. Hardware + * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and + * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are + * indicated in the value set to user variable pointed to by \a pHwErrors. + * + * @sa adi_i2c_SetSlaveAddress(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + * @sa ADI_I2C_HW_ERRORS. + */ +ADI_I2C_RESULT adi_i2c_ReadWrite (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction, uint32_t* const pHwErrors) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } + /* NULL transaction data pointer or zero transaction data count */ + if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) { + return ADI_I2C_INVALID_PARAMETER; + } +#endif + + /* reset submit/get safeguard flag */ + hDevice->bSubmitCalled = false; + + /* submit/commence the transaction */ + submitTransaction(hDevice, pTransaction); + + /* block on internal transaction completion/error semaphore */ + if (ADI_I2C_SUCCESS == hDevice->result) { + + SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED); + + /* completion interrupt comes as FIFO unloads, but serialization may not be complete yet... */ + /* must also wait for hardware busy status to clear before giving back control */ + /* i.e., allow any transmit serialization to complete after last FIFO unload */ + while (I2C_BUSY) { + ; + } + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->hwErrors; + if (0u != hDevice->hwErrors) { + /* set the HW error return code */ + hDevice->result = ADI_I2C_HW_ERROR_DETECTED; + } + + /* return transaction result code */ + return hDevice->result; +} + + +/*! + * @brief Non-Blocking I2C Master-Mode data read or data write API. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pTransaction Pointer to I2C transaction data struct. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] An I2C transaction is already underway. + * - #ADI_I2C_INVALID_PARAMETER [D] Invalid data pointer or count is detected. + * + * Request a non-blocking I2C data transfer (read or write) with or without preceding prologue + * transmitted. Control is returned to the calling application immediately, allowing the application + * process other tasks. The transaction result code is retrieved by #adi_i2c_GetBuffer(). + * + * The application may optionally poll the I2C driver via the #adi_i2c_IsBufferAvailable() API while + * the transaction is underway to determine if and when the submitted transaction is complete. + * Eventually, the application \a MUST call the \a MANDATORY #adi_i2c_GetBuffer() API to obtain the + * transaction result and complete the transaction. Buffer allocations are made by the calling + * code (the application). + * + * The #adi_i2c_GetBuffer() API may be called at any time, even if the transaction is incomplete; + * the #adi_i2c_GetBuffer() call will simply block in incomplete transactions until the + * transaction does complete... at which point #adi_i2c_GetBuffer() returns control with + * the transaction result code. Submitting background transactions is useful if the application has + * housekeeping chores to perform when the I2C transaction is started, but later the application + * decides to just block until the transaction is complete. + * + * The prologue and data buffers are handled as they are in the blocking #adi_i2c_ReadWrite() call, + * it's just that the #adi_i2c_SubmitBuffer() API does not block on the data phase. + * + * @note The non-blocking #adi_i2c_SubmitBuffer() call \a REQUIRES a matching #adi_i2c_GetBuffer() call + * to obtain the final transaction result code and to inform the driver that the application wants to + * regain ownership of the buffers. The application should be prepared to wait for this ownership + * until the current transaction completes. The matching #adi_i2c_GetBuffer() call is required even if + * the transaction may have already completed. The #adi_i2c_GetBuffer() call allows the driver to block + * on completion or error events and then synchronize its internal blocking object. The intermediate + * #adi_i2c_IsBufferAvailable() API is optional.\n\n + * + * @note The #adi_i2c_SubmitBuffer() API is singular, i.e., only a single transaction may be submitted + * at a time. Simultaneous submits (e.g., ping-pong mode) are not supported by the I2C driver. + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SetSlaveAddress(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + */ +ADI_I2C_RESULT adi_i2c_SubmitBuffer (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } + /* NULL transaction data pointer or zero transaction data count */ + if ((NULL == pTransaction->pData) || (0u == pTransaction->nDataSize)) { + return ADI_I2C_INVALID_PARAMETER; + } +#endif + + /* set submit/get safeguard flag */ + hDevice->bSubmitCalled = true; + + /* submit/commence the transaction */ + submitTransaction(hDevice, pTransaction); + + /* no blocking on submit... just return the submit result */ + return hDevice->result; +} + + +/*! + * @brief Query if a non-blocking I2C transfer is complete. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[out] pbCompletionState Pointer to Boolean into which the I2C bus state is written. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_INVALID_SUBMIT_API No matching submit call. + * + * Sets the application-provided Boolean variable pointed to by pbCompletionState either: + * - true, when the non-blocking transactions is complete, or + * - false, while the non-blocking transactions is still underway. + * + * This API is used in conjunction with a non-blocking #adi_i2c_SubmitBuffer() transfer to + * determine when the transaction is complete. Typically, non-blocking calls are used when the + * calling application has other work to do while I2C controller serializes data over the I2C bus, + * which is an interrupt-driven process. The transaction is submitted as a non-blocking call and + * the submitting API returns immediately, allowing the calling application to perform its other tasks. + * The I2C driver services the interrupts to transfer data while the application performs its + * other tasks. + * + * Non-blocking calls can be polled with this API for completion, or if the application has completed + * its other tasks and wants to just wait on the I2C completion without further polling, it may call + * the associated #adi_i2c_GetBuffer() API to convert the currently unblocked transaction to + * a blocking one. + * + * @note This API is inappropriate in context of blocking calls to #adi_i2c_ReadWrite(). + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_GetBuffer(). + * @sa ADI_I2C_TRANSACTION. + */ +ADI_I2C_RESULT adi_i2c_IsBufferAvailable (ADI_I2C_HANDLE const hDevice, bool* const pbCompletionState) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_I2C_INVALID_SUBMIT_API; + } + + /* return true when bus goes quiet */ + if (I2C_BUSY) { + *pbCompletionState = false; + } else { + *pbCompletionState = true; + } + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Request ownership of a submitted buffer. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_INVALID_SUBMIT_API No matching submit call. + * - #ADI_I2C_HW_ERROR_DETECTED A hardware error occurred, check \a pHwErrors. + * + * This is a potentially blocking MANDATORY call that the application MUST use to reclaim + * ownership of any "submitted" transaction (submitted via a previous #adi_i2c_SubmitBuffer() + * call) and obtain the transaction success/failure result code. This API blocks until the + * transaction is complete and returns the transaction result code. If the transaction is + * already complete, the blocking is trivial and control is returned immediately. + * + * Non-blocking calls can also be (optionally) polled with the non-blocking + * #adi_i2c_IsBufferAvailable() API to see if and when the transaction is complete. + * + * The #adi_i2c_GetBuffer() call is a MANDATORY compliment to #adi_i2c_SubmitBuffer() and + * allows the I2C driver to synchronize its internal blocking object. + * + * @note Application must check the return code to verify if any I2C Bus errors occurred. Hardware + * errors (I2C Protocol errors) are indicated with the #ADI_I2C_HW_ERROR_DETECTED return code, and + * the set of hardware errors (enum #ADI_I2C_HW_ERRORS) that occurred (there may be multiple) are + * indicated in the value set to user variable pointed to by \a pHwErrors. + * + * @sa adi_i2c_ReadWrite(). + * @sa adi_i2c_SubmitBuffer(). + * @sa adi_i2c_IsBufferAvailable(). + * @sa ADI_I2C_TRANSACTION. + * @sa ADI_I2C_HW_ERRORS. + */ +ADI_I2C_RESULT adi_i2c_GetBuffer (ADI_I2C_HANDLE const hDevice, uint32_t* const pHwErrors) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* fail if not a submit-based transaction */ + if (false == hDevice->bSubmitCalled) { + return ADI_I2C_INVALID_SUBMIT_API; + } + + /* block until complete or error interrupt sets the semaphore */ + SEM_PEND(hDevice, ADI_I2C_SEMAPHORE_FAILED); + + /* delay until bus goes quiet */ + while (I2C_BUSY) { + ; + } + + /* copy out any hardware errors... */ + *pHwErrors = hDevice->hwErrors; + if (0u != hDevice->hwErrors) { + /* set the HW error return code */ + hDevice->result = ADI_I2C_HW_ERROR_DETECTED; + } + + /* return transaction result code */ + return hDevice->result; +} + +/*! + * @brief Reset an I2C device and driver instance. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * + * Reset the I2C physical controller and device driver internals. + */ +ADI_I2C_RESULT adi_i2c_Reset (ADI_I2C_HANDLE const hDevice) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } +#endif + + /* destroy/recreate the semaphore to force a clear state */ + SEM_DELETE(hDevice, ADI_I2C_SEMAPHORE_FAILED) + ; + SEM_CREATE(hDevice, "i2c_sem", ADI_I2C_SEMAPHORE_FAILED) + ; + + /* reset the driver and HW state */ + return i2cReset(hDevice); +} + + +/*! + * @brief Set the I2C serial bus speed. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] requestedBitRate32 Requested I2C bus clock rate (in Hz). + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * - #ADI_I2C_BAD_SYS_CLOCK Failure to obtain the current PCLK rate. + * - #ADI_I2C_BAD_BITRATE Requested clock speed exceeds operational specification. + * + * Sets the I2C bus clock speed to the requested user parameter, \a requestedBitRate. + * + * @note Any I2C Bus clock rate may be requested up to and including the "FAST" mode I2C clock + * rate (400 kHz), including the "STANDARD" mode (100 kHz). Faster clock rates beyond "FAST" + * mode (e.g., "FAST+" or "HIGH-SPEED" modes) are not supported by the hardware. Slower clock + * rates below approximately 55 kHz (assuming a 26 MHz system clock) are physically unrealizable + * due to the fixed 8-bit field-width of the 8-bit I2C clock rate divide register.\n\n + * + * @note Default clock rate may be specified statically in the default user configuration file, + * "adi_i2c_config.h". + */ +ADI_I2C_RESULT adi_i2c_SetBitRate (ADI_I2C_HANDLE const hDevice, uint32_t const requestedBitRate32) { + + uint32_t clockFrequency32, halfClock32; + uint16_t halfClock16; + uint16_t highTime16, lowTime16; + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* get input clockrate from power service */ + if (ADI_PWR_SUCCESS != adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &clockFrequency32)) { + return ADI_I2C_BAD_SYS_CLOCK; + } + + /* block requests above max rated 400kHz operation */ + if (ADI_I2C_MAX_RATE < requestedBitRate32) { + return ADI_I2C_BAD_BITRATE; + } + + /* compute half-cycle period in 32-bits (">>1" is divide by 2) */ + halfClock32 = (clockFrequency32 / requestedBitRate32) >> 1; /* HRM equation */ + + /* downcast to 16-bit to match destination field */ + halfClock16 = (uint16_t)(halfClock32 & 0x0000ffffu); + + /* check for lost precision in conversion */ + if (halfClock32 != halfClock16) { + return ADI_I2C_BAD_BITRATE; + } + + /* adjust high and low durations per HRM */ + highTime16 = halfClock16 - 7u; /* empirical: varies with board layout, pullups, etc */ + lowTime16 = halfClock16 - 1u; + + /* shift values into their clock rate divider register positions */ + highTime16 <<= BITP_I2C_DIV_HIGH; + lowTime16 <<= BITP_I2C_DIV_LOW; + + /* check for divider overflows beyond designated (8-bit) field masks */ + if ( (uZero16 != ((uint16_t)highTime16 & (uint16_t)(~(BITM_I2C_DIV_HIGH)))) + || + (uZero16 != ((uint16_t)lowTime16 & (uint16_t)(~(BITM_I2C_DIV_LOW)))) + ) { + return ADI_I2C_BAD_BITRATE; + } + + /* program new values */ + hDevice->pDev->DIV = highTime16 | lowTime16; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Set the I2C serial bus slave address. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] SlaveAddress New 7-bit address for targeting a slave device. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * - #ADI_I2C_INVALID_SLAVE_ADDRESS Slave address exceeds the 7-bit limit. + * + * Sets the 7-bit (unformatted) slave address for which all subsequent I2C bus traffic is directed. + * Read/write address formatting is performed by the driver, depending on bus direction. + * + * @note This driver does not support the I2C 10-bit extended addressing scheme.\n\n + * + * @note Default slave address may be specified statically in the default user configuration file, + * "adi_i2c_config.h". + */ +ADI_I2C_RESULT adi_i2c_SetSlaveAddress (ADI_I2C_HANDLE const hDevice, uint16_t const SlaveAddress) { + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* verify no slave address bits fall outside the 7-bit addressing model (10-bit addressing not supported) */ + if (uZero16 != (SlaveAddress & (uint16_t)(~(BITM_I2C_ADDR1_VALUE >> 1)))) { + return ADI_I2C_INVALID_SLAVE_ADDRESS; + } + + /* save new address */ + hDevice->i2cDeviceAddress = SlaveAddress; + + return ADI_I2C_SUCCESS; +} + + +/*! + * @brief Transmit a General Call command to all slave devices on the I2C bus. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pData Pointer to data buffer to transmit. + * @param[in] nDataSize Size of data buffer to transmit. + * @param[out] pHwErrors Pointer to hardware error return variable. + * + * @return Status + * - #ADI_I2C_SUCCESS Call completed successfully. + * - #ADI_I2C_BAD_DEVICE_HANDLE [D] Invalid device handle parameter. + * - #ADI_I2C_DEVICE_IN_USE [D] Device is busy. + * + * Broadcasts the given command buffer across the I2C bus to reserved General Call (GC) + * address (address zero). All, some, or none of the slave devices on the I2C bus will + * respond, depending on their capabilities. All responding slave devices will process + * the GC command according to their capabilities. + * + * The GC command is a blocking transaction. + * + * The application is responsible for formatting the GC command into the data buffer + * according to various Philips Semiconductor (now, NXP) documents, such as the 2014 + * Revision 6 document: "UM10204 I2C-Bus Specification and User Manual" + * (see www.nxp.com/documents/user_manual/UM10204.pdf). + * + * No prologue precedes the GC command data; the GC command data is transmitted verbatim. + * + * @note The currently active slave address is saved and restored when transmitting GC + * commands to the reserved GC address (address zero). + * + */ +ADI_I2C_RESULT adi_i2c_IssueGeneralCall (ADI_I2C_HANDLE const hDevice, uint8_t* const pData, uint8_t const nDataSize, uint32_t* const pHwErrors) { + + ADI_I2C_RESULT result; + ADI_I2C_TRANSACTION xfr; + +#ifdef ADI_DEBUG + if (IsDeviceHandle(hDevice)) { + return ADI_I2C_BAD_DEVICE_HANDLE; + } + if (I2C_BUSY) { + return ADI_I2C_DEVICE_IN_USE; + } +#endif + + /* force general call reserved target address of zero */ + uint16_t savedSlaveAddress = hDevice->i2cDeviceAddress; + hDevice->i2cDeviceAddress = 0u; + + /* setup the transfer */ + xfr.pPrologue = NULL; + xfr.nPrologueSize = 0u; + xfr.pData = pData; + xfr.nDataSize = nDataSize; + xfr.bReadNotWrite = false; + xfr.bRepeatStart = false; + + /* dispatch as a blocking transmit call */ + result = adi_i2c_ReadWrite(hDevice, &xfr, pHwErrors); + + /* always restore saved slave address */ + hDevice->i2cDeviceAddress = savedSlaveAddress; + + if (ADI_I2C_SUCCESS != result) { + return result; /* read/write failure... */ + } else { + return hDevice->result; /* actual result */ + } +} + + + /*! \cond PRIVATE */ + + +/**********************************************************************************\ +|*****************************static helper functions******************************| +\**********************************************************************************/ + +static void submitTransaction(ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction) { + + /* reset internal return code */ + hDevice->result = ADI_I2C_SUCCESS; + + /* reset hardware error code */ + hDevice->hwErrors = ADI_I2C_HW_ERROR_NONE; + + /* wait for HW to be ready */ + while (I2C_BUSY) { + ; + } + + /* save common user parameters */ + hDevice->pNextPrologueByte = pTransaction->pPrologue; + hDevice->remainingPrologueCount = pTransaction->nPrologueSize; + hDevice->bRepeatStart = pTransaction->bRepeatStart; + + /* encode (mask and upshift) the slave address, leaving room for the r/w control bit (LSB) */ + hDevice->i2cEncodedDeviceAddress = (hDevice->i2cDeviceAddress & (BITM_I2C_ADDR1_VALUE >> 1)) << 1; + + /* dispatch */ + if (pTransaction->bReadNotWrite) { + + /* setup read parameters */ + hDevice->pNextReadByte = pTransaction->pData; + hDevice->remainingReadCount = pTransaction->nDataSize; + hDevice->pNextWriteByte = NULL; + hDevice->remainingWriteCount = 0u; + + /* set read bit */ + hDevice->i2cEncodedDeviceAddress |= READ_NOT_WRITE; + + /* commence receive */ + commenceReceive(hDevice); + + } else { + + /* setup write parameters */ + hDevice->pNextReadByte = NULL; + hDevice->remainingReadCount = 0u; + hDevice->pNextWriteByte = pTransaction->pData; + hDevice->remainingWriteCount = pTransaction->nDataSize; + + /* clear read bit */ + hDevice->i2cEncodedDeviceAddress &= (~READ_NOT_WRITE); + + /* commence transmit */ + commenceTransmit(hDevice); + } +} + + +static void commenceTransmit(ADI_I2C_HANDLE const hDevice) { + + /* transmit is always pure transmit, whether we have a prologue or not... */ + + /* enable PIO interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn); + + /* enable i2c for PIO-based transmit interrupts */ + hDevice->pDev->MCTL |= (BITM_I2C_MCTL_IENMTX | BITM_I2C_MCTL_MASEN); + + /* how many bytes are available in the transmit FIFO (2-deep) */ + uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF); + + /* prime transmit FIFO with any prologue data */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* flesh out any remaining FIFO space with transmit data */ + while ((0u < writableBytes) && (hDevice->remainingWriteCount)) { + hDevice->pDev->MTX = *hDevice->pNextWriteByte; + hDevice->pNextWriteByte++; + hDevice->remainingWriteCount--; + writableBytes--; + } + + /* launch the transmit */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; +} + + +/* initiate receive addressing phase */ +static void commenceReceive(ADI_I2C_HANDLE const hDevice) { + + /* receive can be either pure receive (no prologue), + or a transmit (of prologue) followed by a receive */ + + /* enable PIO interrupts */ + NVIC_EnableIRQ(hDevice->pDevInfo->pioIRQn); + + /* enable i2c for PIO-based receive interrupts */ + hDevice->pDev->MCTL |= (uint16_t)(BITM_I2C_MCTL_IENMRX | BITM_I2C_MCTL_MASEN); + + /* program HW receive count */ + if (hDevice->remainingReadCount > BITM_I2C_MRXCNT_EXTEND) { + hDevice->pDev->MRXCNT = BITM_I2C_MRXCNT_EXTEND; + hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND; + } else { + hDevice->pDev->MRXCNT = hDevice->remainingReadCount - 1u; + hDevice->remainingReadCount = 0u; + } + + /* if we have prologue (the dreaded "COMBINED FORMAT"), transmit the prologue prior to data receive... */ + if (hDevice->remainingPrologueCount) { + + /* -OR- in transmit interrupt enable if we have prologue data to send */ + hDevice->pDev->MCTL |= BITM_I2C_MCTL_IENMTX; + + /* how many bytes are available in the transmit FIFO (should be 2) */ + uint16_t writableBytes = 2u - (hDevice->pDev->MSTAT & (uint16_t)BITM_I2C_MSTAT_MTXF); + + /* prime transmit FIFO with any prologue data (memory address or command) first */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* initiate prologue transmit with read bit cleared (for prologue write) */ + /* (read sequence is initiated by transmit handler, *after* prologue is transmitted...) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress & (uint16_t)(~READ_NOT_WRITE); + + } else { + + /* no prologue... initiate pure receive (read bit already set) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + } +} + + +/* reset the I2C HW */ +static ADI_I2C_RESULT i2cReset(ADI_I2C_HANDLE const hDevice) { + + volatile uint16_t temp; + /* disable interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn); + + /* reset any pending interrupts and TX FIFO (W1C) */ + temp = hDevice->pDev->MSTAT; + hDevice->pDev->MSTAT = temp; + + /* discard any rogue RX FIFO data */ + while (uZero16 != (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF)) { + volatile uint16_t delme ADI_UNUSED_ATTRIBUTE = hDevice->pDev->MTX; + } + + /* reset i2c control register */ + hDevice->pDev->MCTL = 0u; + + /* reset repeat start logic */ + hDevice->pDev->SHCTL = 1u; + + /* (re)assert controller defaults from user config values */ + hDevice->pDev->MCTL = hDevice->pDevInfo->pConfig->MasterControlRegister; + hDevice->pDev->DIV = hDevice->pDevInfo->pConfig->ClockDividerRegister; + hDevice->pDev->SHCTL = hDevice->pDevInfo->pConfig->SharedControlRegister; + hDevice->pDev->TCTL = hDevice->pDevInfo->pConfig->TimingControlRegister; + hDevice->pDev->ASTRETCH_SCL = hDevice->pDevInfo->pConfig->ClockStretchRegister; + hDevice->i2cDeviceAddress = hDevice->pDevInfo->pConfig->TargetSlaveAddress; + + return ADI_I2C_SUCCESS; +} + + +/**********************************************************************************\ +|********************************interrupt handlers********************************| +\**********************************************************************************/ + + +/* transmit interrupt handler */ +static void transmitHandler(ADI_I2C_HANDLE const hDevice) { + + /* how much room in transmit FIFO? */ + /* DO ***NOT*** USE MSTAT:MTXF... FALSELY INDICATES MOSTLY FULL FIFO! */ + uint16_t writableBytes = 2u - ((hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MTXF) >> BITP_I2C_STAT_MTXF); + + /* for extended prologues, continue pushing prologue data out */ + while ((0u < writableBytes) && (hDevice->remainingPrologueCount)) { + hDevice->pDev->MTX = *hDevice->pNextPrologueByte; + hDevice->pNextPrologueByte++; + hDevice->remainingPrologueCount--; + writableBytes--; + } + + /* once the prologue is done... */ + if (0u == hDevice->remainingPrologueCount) { + + /* if we have a completed prologue associated with a read sequence... */ + if (0u < hDevice->remainingReadCount) { + + /* initiate the read (subsequently driven by receive interrupt handler) */ + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + + } else { + + /* normal transmit interrupt: just push transmit data */ + while ((0u < writableBytes) && (hDevice->remainingWriteCount)) { + hDevice->pDev->MTX = *hDevice->pNextWriteByte; + hDevice->pNextWriteByte++; + hDevice->remainingWriteCount--; + writableBytes--; + } + } + } + + /* clear TX interrupt as we complete transmit writes */ + if (0u == hDevice->remainingWriteCount) { + hDevice->pDev->MSTAT = BITM_I2C_MSTAT_MTXREQ; + } +} + + +/* receive interrupt handler */ +static void receiveHandler(ADI_I2C_HANDLE const hDevice) { + + /* note: we never need to deal with prologue data here... it will already be transmitted... */ + + /* how many bytes in receive FIFO? */ + uint16_t readableBytes = (hDevice->pDev->STAT & (uint16_t)BITM_I2C_STAT_MRXF) >> BITP_I2C_STAT_MRXF; + + /* pull bytes from fifo */ + while (0u < readableBytes) { + + readableBytes--; + + /* pull one byte */ + *hDevice->pNextReadByte = (uint8_t)hDevice->pDev->MRX; + hDevice->pNextReadByte++; + + if ((0u == hDevice->pDev->MCRXCNT) && (hDevice->remainingReadCount)) { + + /* if HW read counter goes to zero with remaining data to read, reprogram read count */ + if (hDevice->remainingReadCount > BITM_I2C_MRXCNT_EXTEND) { + /* use extended count flag for large remaining counts... */ + hDevice->pDev->MRXCNT = BITM_I2C_MRXCNT_EXTEND; + hDevice->remainingReadCount -= BITM_I2C_MRXCNT_EXTEND; + } else { + /* new count fits... no need for extended count */ + hDevice->pDev->MRXCNT = hDevice->remainingReadCount - 1u; + hDevice->remainingReadCount = 0u; + } + } + } +} + +/* completion interrupt handler */ +static void completeHandler(ADI_I2C_HANDLE const hDevice) { + + /* block on busy until all transmit data has both left + the fifo AND has been fully serialized to the bus. */ + while (I2C_BUSY) { + ; + } + + /* disable interrupts */ + NVIC_DisableIRQ(hDevice->pDevInfo->pioIRQn); + + /* reset controller to default user config state */ + hDevice->pDev->MCTL = (uint16_t)gConfigInfo->MasterControlRegister; +} + + +/* error interrupt handler */ +static void errorHandler(ADI_I2C_HANDLE const hDevice) { + + /* accumulate I2C bus errors */ + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKADDR)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_ADDR; + } + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_NACKDATA)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_NACK_DATA; + } + + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_ALOST)) { + hDevice->hwErrors |= ADI_I2C_HW_ERROR_ARBITRATION_LOST; + } + + /* if no other errors exist, note we had an unexpected error */ + if (hDevice->hwErrors == ADI_I2C_HW_ERROR_NONE) { + hDevice->hwErrors = ADI_I2C_HW_ERROR_UNEXPECTED_ERROR; + } +} + + +/**********************************************************************************\ +|*****************************I2C INTERRUPT HANDLER********************************| +\**********************************************************************************/ + + +/* PIO mode I2C interrupt handler */ +void I2C0_Master_Int_Handler(void) { + + bool bPost = false; + + /* rtos prologue */ + ISR_PROLOG() + ; + + /* recover device handle */ + ADI_I2C_HANDLE const hDevice = (ADI_I2C_HANDLE)i2c_device_info[0].hDevice; + + /* save destructive status read... */ + hDevice->hwStatus = hDevice->pDev->MSTAT; + + /* if RepeatStart request is pending, rewrite address register ASAP (and only once) to block stop bit */ + if (hDevice->bRepeatStart) { + hDevice->pDev->ADDR1 = hDevice->i2cEncodedDeviceAddress; + hDevice->bRepeatStart = false; /* just do it once on 1st interrupt */ + } + + /* forward TX interrupts to TX handler */ + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MTXREQ)) { + transmitHandler(hDevice); + } + + /* forward RX interrupts to RX handler */ + if (uZero16 != (hDevice->hwStatus & (uint16_t)BITM_I2C_MSTAT_MRXREQ)) { + receiveHandler(hDevice); + } + + /* dispatch any errors */ + if (uZero16 != (hDevice->hwStatus & ADI_I2C_STATUS_ERROR_MASK)) { + errorHandler(hDevice); + + /* post on bus error */ + bPost = true; + } + + /* transmit complete */ + if (uZero16 != (hDevice->hwStatus & BITM_I2C_MSTAT_TCOMP)) { + completeHandler(hDevice); + + /* post on completion */ + bPost = true; + } + + /* just post once */ + if (true == bPost) { + SEM_POST(hDevice); + } + + /* rtos epilogue */ + ISR_EPILOG() + ; +} + +/*! \endcond */ + + +/* @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c new file mode 100755 index 00000000000..6d7a63801c8 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c @@ -0,0 +1,120 @@ +/* + ***************************************************************************** + * @file: adi_i2c_data.c + * @brief: Data declaration for I2C Device Driver + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be coni2ccuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef ADI_I2C_DATA_C +#define ADI_I2C_DATA_C + + /*! \cond PRIVATE */ + +#include +#include "adi_i2c_def.h" +#include "adi_i2c_config.h" + +/* Stores the information about the specific device */ +static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] = +{ + /* fixed instance data for the singular I2C0 controller */ + { + I2C_MST_EVT_IRQn, /* pio interrupt number */ + (ADI_I2C_TypeDef *)pADI_I2C0, /* i2c controller pointer */ + NULL, /* pointer to user config data */ + NULL /* i2c device handle (user mem) */ + }, + + /* no other i2c instances at this time */ +}; + +/* build I2C Application configuration array */ +static ADI_I2C_CONFIG gConfigInfo[ADI_I2C_NUM_INSTANCES] = +{ + /* the one-and-only (so far) instance data for I2C, I2C0... */ + { + /**** I2C_MCTL Master Control register *** */ + ( + /* note: Master IENMTX and IENMRX (transmit and receive interrupts) are managed dynamically */ + ( ADI_I2C_CFG_MCTL_MXMITDEC << BITP_I2C_MCTL_MXMITDEC ) | + ( ADI_I2C_CFG_MCTL_IENCMP << BITP_I2C_MCTL_IENCMP ) | + ( ADI_I2C_CFG_MCTL_IENACK << BITP_I2C_MCTL_IENACK ) | + ( ADI_I2C_CFG_MCTL_IENALOST << BITP_I2C_MCTL_IENALOST ) | + ( ADI_I2C_CFG_MCTL_STRETCHSCL << BITP_I2C_MCTL_STRETCHSCL ) | + ( ADI_I2C_CFG_MCTL_LOOPBACK << BITP_I2C_MCTL_LOOPBACK ) | + ( ADI_I2C_CFG_MCTL_COMPLETE << BITP_I2C_MCTL_COMPLETE ) | + ( ADI_I2C_CFG_MCTL_MASEN << BITP_I2C_MCTL_MASEN ) + ), + + /**** I2C_DIV Clock Divider register *** */ + ( + ( ADI_I2C_CFG_DIV_HIGH << BITP_I2C_DIV_HIGH ) | + ( ADI_I2C_CFG_DIV_LOW << BITP_I2C_DIV_LOW ) + ), + + /**** I2C_SHCTL Shared Control register *** */ + ( + ( ADI_I2C_CFG_SHCTL_RST << BITP_I2C_TCTL_FILTEROFF ) + ), + + /**** I2C_TCTL Timing control register *** */ + ( + ( ADI_I2C_CFG_TCTL_FILTEROFF << BITP_I2C_SHCTL_RST ) | + ( ADI_I2C_CFG_TCTL_THDATIN << BITP_I2C_TCTL_THDATIN ) + ), + + /**** I2C_ASTRETCH Master Clock Stretch register *** */ + ( + ( ADI_I2C_CFG_ASTRETCH_MST << BITP_I2C_ASTRETCH_SCL_MST ) + ), + + /**** Target Slave configuration value (not a register) *** */ + ( + ( ADI_I2C_CFG_SLAVE_ADDRESS ) + ), + } +}; + +/*! \endcond */ + + +#endif /* ADI_I2C_DATA_C */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h new file mode 100755 index 00000000000..03ba0b5bf92 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_def.h @@ -0,0 +1,129 @@ +/*! + ***************************************************************************** + @file: adi_i2c_def.h + @brief: Internal I2C device driver definitions and macros + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ +#ifndef ADI_I2C_DEF_H +#define ADI_I2C_DEF_H + +/*! \cond PRIVATE */ + +#include + +#define ADI_I2C_NUM_INSTANCES (1u) +#define ADI_I2C_STATUS_ERROR_MASK ( (1u << BITP_I2C_MSTAT_NACKADDR) \ + | (1u << BITP_I2C_MSTAT_NACKDATA) \ + | (1u << BITP_I2C_MSTAT_ALOST) ) + +/* Internal Actions */ +static void submitTransaction (ADI_I2C_HANDLE const hDevice, ADI_I2C_TRANSACTION* const pTransaction); +static void commenceTransmit (ADI_I2C_HANDLE const hDevice); +static void commenceReceive (ADI_I2C_HANDLE const hDevice); +static ADI_I2C_RESULT i2cReset (ADI_I2C_HANDLE const hDevice); + +/* interrupt event handlers */ +static void transmitHandler (ADI_I2C_HANDLE const hDevice); +static void receiveHandler (ADI_I2C_HANDLE const hDevice); +static void completeHandler (ADI_I2C_HANDLE const hDevice); +static void errorHandler (ADI_I2C_HANDLE const hDevice); + + +/* + ***************************************************************************** + * I2C Configuration structure. + *****************************************************************************/ +typedef struct __ADI_I2C_CONFIG { + uint16_t MasterControlRegister; /* I2C_MCTL register configuration. */ + uint16_t ClockDividerRegister; /* I2C_DIV register. */ + uint16_t SharedControlRegister; /* I2C_DIV register. */ + uint16_t TimingControlRegister; /* I2C_TCTL register. */ + uint16_t ClockStretchRegister; /* I2C_ASTRETCH register. */ + uint16_t TargetSlaveAddress; /* slave address value (not a register). */ +} ADI_I2C_CONFIG; + + +/* I2C physical device instance data */ +typedef struct __ADI_I2C_DEVICE_INFO { + IRQn_Type pioIRQn; /* PIO interrupt number */ + ADI_I2C_TypeDef *pDev; /* pointer to i2c controller */ + ADI_I2C_CONFIG *pConfig; /* pointer to user config info */ + ADI_I2C_HANDLE hDevice; /* I2C handle or NULL if uninitialized */ +} ADI_I2C_DEVICE_INFO; + +/* I2C driver instance data structure */ +typedef struct __ADI_I2C_DEV_DATA_TYPE { + + /* make sure to synchronize ANY size changes with ADI_I2C_MEMORY_SIZE macro in adi_i2c.h */ + + /* device attributes */ + ADI_I2C_TypeDef *pDev; + ADI_I2C_DEVICE_INFO *pDevInfo; + + + /* driver state */ + uint16_t hwStatus; + bool bRepeatStart; + uint16_t i2cDeviceAddress; + uint16_t i2cEncodedDeviceAddress; /* encoded as 7-bit device address + r/w LSB */ + bool bSubmitCalled; + + /* prologue data */ + volatile uint8_t *pNextPrologueByte; + volatile uint16_t remainingPrologueCount; + + /* write data */ + volatile uint8_t *pNextWriteByte; + volatile uint16_t remainingWriteCount; + + /* read data */ + volatile uint8_t *pNextReadByte; + volatile uint16_t remainingReadCount; + + ADI_I2C_RESULT result; /* collector for return status */ + ADI_I2C_HW_ERRORS hwErrors; /* collector for error status */ + + SEM_VAR_DECLR /* blocking object: "Semaphore" for rtos, "nLowPowerExitFlag" for non-rtos */ + +} ADI_I2C_DEV_DATA_TYPE; + +/*! \endcond */ + +#endif /* end of ifndef ADI_I2C_DEF_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c new file mode 100755 index 00000000000..a91c53e02ce --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr.c @@ -0,0 +1,1904 @@ +/* + ***************************************************************************** + * @file: adi_pwr.c + * @brief: Power Management driver implementation. + *----------------------------------------------------------------------------- + * +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \addtogroup Power_Driver Power Driver + * @{ + * @brief Power Management Driver + * @note The application must include drivers/pwr/adi_pwr.h to use this driver + * @note The API #adi_pwr_EnableClockSource requires the GPIO driver if + * #ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO is set to 1. In that case the + * application must include the GPIO driver sources to avoid link errors. + */ + + +#include /* for 'NULL' */ +#include +#include "adi_pwr_def.h" +#include +#include +#include +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* Pm057 (rule 15.2): Every non-empty case clause in a switch statement shall be terminated with a break statement. +* In some cases we have return statement instead of break. It is not valid to both return and break in MISRA 2012. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm050,Pm140,Pm143,Pm057 +#endif /* __ICCARM__ */ + +/*! \cond PRIVATE */ + +/*---------------------------------------------------------------------------- + Internal Clock Variables. The external ones are defined in system.c + *---------------------------------------------------------------------------*/ +#ifdef ADI_DEBUG +/* not needed unless its debug mode */ +extern uint32_t lfClock; /* "lf_clk" coming out of LF mux */ +#endif + +extern uint32_t hfClock; /* "root_clk" output of HF mux */ +extern uint32_t gpioClock; /* external GPIO clock */ + +static ADI_CALLBACK gpfCallbackFunction; +static void *gpPowcbParam = NULL; +static uint32_t gnLowPowerIntOccFlag = 0u; + +/*! \endcond */ + +/*---------------------------------------------------------------------------- + Clock functions + *---------------------------------------------------------------------------*/ +/** + * Initialize the clock configuration register with the default values. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully initialized the power service. + */ +ADI_PWR_RESULT adi_pwr_Init (void) +{ + /* Enable internal HF oscillators */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + pADI_CLKG0_OSC->CTL = OSCCTRL_CONFIG_VALUE; + + gpfCallbackFunction = NULL; + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + /* Switch on the internal HF oscillator */ + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_HFOSC_EN; + + /* wait for HF OSC to stabilize */ + while ((pADI_CLKG0_OSC->CTL & (1U << BITP_CLKG_OSC_CTL_HFOSC_OK)) == 0u) + { + } + + /* Switch over to the internal HF oscillator */ + pADI_CLKG0_CLK->CTL0 &= ~(BITM_CLKG_CLK_CTL0_CLKMUX); + + /* complete remaining reset sequence */ + pADI_CLKG0_CLK->CTL0 = CLOCK_CTL0_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL1 = CLOCK_CTL1_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL2 = CLOCK_CTL2_CONFIG_VALUE; + pADI_CLKG0_CLK->CTL3 = CLOCK_CTL3_CONFIG_VALUE; + /* No CLK CTL4 */ + pADI_CLKG0_CLK->CTL5 = CLOCK_CTL5_CONFIG_VALUE; + + /* + * Configure the power management registers + */ + pADI_PMG0->IEN = PWM_INTERRUPT_CONFIG; + pADI_PMG0->PWRMOD = PWM_PWRMOD_CONFIG; + pADI_PMG0->CTL1 = PWM_HPBUCK_CONTROL; + + /* disable external HF crystal oscillator */ + /* (don't disable LF crystal or the RTC will lose time */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + pADI_CLKG0_OSC->CTL &= ~BITM_CLKG_OSC_CTL_HFX_EN; + + NVIC_EnableIRQ(PMG0_VREG_OVR_IRQn); + NVIC_EnableIRQ(PMG0_BATT_RANGE_IRQn); + + NVIC_EnableIRQ(CLKG_XTAL_OSC_EVT_IRQn); + NVIC_EnableIRQ(CLKG_PLL_EVT_IRQn); + + /* compute new internal clocks based on the newly reset controller */ + SystemCoreClockUpdate(); + + return(ADI_PWR_SUCCESS); +} + + +/** + * @brief Updates the internal SystemCoreClock variable with current core + * Clock retrieved from cpu registers. + * + * @return Status + * - #ADI_PWR_SUCCESS : Updated core system core clock variables. + * + * Updates the internal SystemCoreClock variable with current core + * Clock retrieved from cpu registers. + * + * @sa adi_pwr_GetClockFrequency () + */ +ADI_PWR_RESULT adi_pwr_UpdateCoreClock (void) +{ + SystemCoreClockUpdate(); + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Registers or unregister the callback function. + * + * @details Application can register or unregister the callback function which + * will be called to notify the events from the driver. + * + * @param[in] pfCallback : Callback function pointer. + * @param[in] pcbParam : Callback parameter. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully installed the callback function. + * - #ADI_PWR_NULL_POINTER [D] : Failed to install the callback function since the call back function pointer is NULL. + */ +ADI_PWR_RESULT adi_pwr_RegisterCallback( + const ADI_CALLBACK pfCallback, + void *pcbParam + ) +{ + +#ifdef ADI_DEBUG + if(pfCallback == NULL) + { + return(ADI_PWR_NULL_POINTER); + } +#endif + + gpfCallbackFunction = pfCallback; + gpPowcbParam = pcbParam; + + return ADI_PWR_SUCCESS; +} + +/** + * @brief Sets the system external clock frequency + * + * @param[in] ExtClkFreq: External clock frequency in Hz + + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the external clock as source. + * - #ADI_PWR_INVALID_CLOCK_SPEED [D]: Specified clock is out of range. + * + * @sa adi_pwr_GetClockFrequency () + */ +ADI_PWR_RESULT adi_pwr_SetExtClkFreq (const uint32_t ExtClkFreq) +{ +#ifdef ADI_DEBUG + if(ExtClkFreq > MAXIMUM_EXT_CLOCK) + { + return(ADI_PWR_INVALID_CLOCK_SPEED); + } +#endif + gpioClock = ExtClkFreq; + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the input clock source for PLL multiplexer. + * + * @param[in] eClockID: Clock source to the System PLL multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the PLL multiplexer clock source. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetPLLClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* Validate the given clock ID */ + switch (eClockID) + { + case ADI_CLOCK_MUX_SPLL_HFOSC: + case ADI_CLOCK_MUX_SPLL_HFXTAL: + case ADI_CLOCK_MUX_SPLL_GPIO: + break; + /* Any other clock ID is not valid since we are configuring the SPLL clock multiplexer. + * Only valid input clock to the multiplexer is HFOSC, HFXTAL, GPIO */ + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_PLL_IPSEL); + tmp |= (( (uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_SPLL_HFOSC) << BITP_CLKG_CLK_CTL0_PLL_IPSEL); + pADI_CLKG0_CLK->CTL0 = tmp; + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the input clock for low frequency clock multiplexer. + * + * @param[in] eClockID: Clock source to the low frequency clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully LF clock multiplexer clock source. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetRootClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetLFClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + + case ADI_CLOCK_MUX_LFCLK_LFOSC: + case ADI_CLOCK_MUX_LFCLK_LFXTAL: + break; + /* Any other clock ID is not valid since we are configuring the Low frequency clock multiplexer. + * Only valid input clock to the multiplexer is LFOSC, LFXTAL */ + + default: + return(ADI_PWR_INVALID_CLOCK_ID); + + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + tmp = (pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFCLK_MUX); + tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_LFCLK_LFOSC) << BITP_CLKG_OSC_CTL_LFCLK_MUX); + pADI_CLKG0_OSC->CTL = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets clock source for the Reference clock multiplexer. + * + * @param[in] eClockID: Clock source to the reference clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the source for reference clock multiplexer. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + * @sa adi_pwr_SetRootClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ + +ADI_PWR_RESULT adi_pwr_SetRefClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + + case ADI_CLOCK_MUX_REF_HFOSC_CLK: + case ADI_CLOCK_MUX_REF_HFXTAL_26MHZ_CLK: + case ADI_CLOCK_MUX_REF_HFXTAL_16MHZ_CLK: + break; + /* Any other clock ID is not valid since we are configuring the out clock multiplexer.*/ + + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_RCLKMUX); + tmp |=(((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_REF_HFOSC_CLK) << BITP_CLKG_CLK_CTL0_RCLKMUX); + pADI_CLKG0_CLK->CTL0 = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + +/** + * @brief Sets the source for the root clock multiplexer. + * + * @param[in] eClockID: Clock source to the root clock multiplexer. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully set the source for root clock multiplexer. + * - #ADI_PWR_INVALID_CLOCK_ID [D] : Specified clock ID is invalid. + * + * @sa adi_pwr_SetLFClockMux() + * @sa adi_pwr_SetPLLClockMux() + */ +ADI_PWR_RESULT adi_pwr_SetRootClockMux(const ADI_CLOCK_MUX_ID eClockID) +{ + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + switch (eClockID) + { + case ADI_CLOCK_MUX_ROOT_HFOSC: + case ADI_CLOCK_MUX_ROOT_HFXTAL: + case ADI_CLOCK_MUX_ROOT_SPLL: + case ADI_CLOCK_MUX_ROOT_GPIO: + break; + /* Any other clock ID is not valid since we are configuring the root clock multiplexer. + * Only valid input clock to the multiplexer is HFOSC, HFXTAL, SPLL, GPIO */ + default: + return(ADI_PWR_INVALID_CLOCK_ID); + } +#endif /* ADI_DEBUG */ + + /* update the mux setting inside a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKMUX); + tmp |= (((uint32_t)eClockID - (uint32_t)ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX); + pADI_CLKG0_CLK->CTL0 = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + +/** + * @brief Gets the system external clock frequency. + * Gets the clock frequency of the source connected to the external GPIO clock input source. + * + * @param [in] pExtClock : Pointer to write the external clock frequency. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully returning the external clock frequency. + * - #ADI_PWR_NULL_POINTER [D] : If the given pointer is pointing to NULL. + * - #ADI_PWR_FAILURE [D] : The system is not initialized yet. Call SystemInit before calling this API. + */ +ADI_PWR_RESULT adi_pwr_GetExtClkFreq (uint32_t *pExtClock) +{ +#ifdef ADI_DEBUG + /* Trap here if the app fails to set the external clock frequency. */ + if (0u == gpioClock) + { + return (ADI_PWR_FAILURE); + } + + if(pExtClock == NULL) + { + return (ADI_PWR_NULL_POINTER); + } +#endif + *pExtClock = gpioClock; + return ADI_PWR_SUCCESS; +} + + +/*! + * @brief Get the frequency of the given clock. + * Obtain individual peripheral clock frequencies + * + * @param[in] eClockId : Clock identifier + * @param[out] pClock : Pointer to a location to store the clock frequency. + * + * @return Status + * - #ADI_PWR_SUCCESS : Successfully returned the queried clock. + * - #ADI_PWR_SYSTEM_NOT_INITIALIZED [D] : The system is not initialized yet. Call SystemInit before calling this API. + * + * @sa adi_PWR_SetClockDivide + * @sa SystemSetClockDivider +*/ +ADI_PWR_RESULT adi_pwr_GetClockFrequency (const ADI_CLOCK_ID eClockId, uint32_t *pClock ) +{ + uint32_t src, nDiv; + +#ifdef ADI_DEBUG + /* trap here if the app fails to call SystemInit(). */ + if ((0u == hfClock) || (0u == lfClock)) + { + return ADI_PWR_SYSTEM_NOT_INITIALIZED; + } +#endif + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); + src = hfClock; + + switch (eClockId) { + + /* HCLOCK domain */ + case ADI_CLOCK_HCLK: + nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + break; + + /* PCLOCK domain */ + case ADI_CLOCK_PCLK: + nDiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + break; + + default: + return ADI_PWR_INVALID_CLOCK_ID; + } /* end switch */ + + if(nDiv == 0u) + { + nDiv = 1u; + } + + *pClock = (src/nDiv); + + return ADI_PWR_SUCCESS; +} + + +/*! + @brief Enable/disable individual peripheral clocks. + + @param[in] eClockGate Clock identifier + @param[in] bEnable Flag to indicate whether to enable/disable individual clock. + true - to enable individual clock. + false - to disable individual clock. + + @return Status + - #ADI_PWR_SUCCESS if we have successfully enabled or disabled the clock. + + @details Manage individual peripheral clock gates to enable or disable the clocks to the peripheral. +*/ +ADI_PWR_RESULT adi_pwr_EnableClock (const ADI_CLOCK_GATE eClockGate, const bool bEnable) +{ + uint32_t mask; + ADI_INT_STATUS_ALLOC(); + + mask = (uint16_t)eClockGate; + /* update the Clock Gate register in a critical region */ + ADI_ENTER_CRITICAL_REGION(); + + /* NOTE NEGATIVE LOGIC!!! */ + if (bEnable == true) { + + /* clear disable bit */ + pADI_CLKG0_CLK->CTL5 &= ~mask; + } else { + /* set disable bit */ + pADI_CLKG0_CLK->CTL5 |= mask; + } + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + @brief Sets the clock divide factor for an individual clock group. + + @param[in] eClockId Clock domain identifier. + @param[in] nDiv Clock divide value to be set (right-justified uint16_t). + + @return Status + - #ADI_PWR_SUCCESS if successfully set the given clock divide factor. + - #ADI_PWR_INVALID_CLOCK_DIVIDER [D] if the divider is out of range. + - #ADI_PWR_INVALID_CLOCK_ID [D] if the given clock is invalid. + - #ADI_PWR_INVALID_CLOCK_RATIO [D] if the given clock ratio invalid. + + @details Manage individual peripheral clock dividers. + + @sa SystemGetClockFrequency +*/ +ADI_PWR_RESULT adi_pwr_SetClockDivider (const ADI_CLOCK_ID eClockId, const uint16_t nDiv) +{ + uint32_t mask; + uint32_t value; + uint32_t tmp; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + uint32_t hdiv, pdiv; +#endif /*ADI_DEBUG*/ + + switch (eClockId) + { + case ADI_CLOCK_HCLK: +#ifdef ADI_DEBUG + /* Verify the divide factor is within the range */ + if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify PCLK freq is <= requested HCLK */ + pdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_PCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + hdiv = nDiv; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + + mask = BITM_CLKG_CLK_CTL1_HCLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + break; + + case ADI_CLOCK_PCLK: +#ifdef ADI_DEBUG + + /* Verify the divide factor is within the range */ + if ((nDiv > CLOCK_MAX_DIV_VALUE) || (nDiv < CLOCK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify requested PCLK freq is <= HCLK */ + pdiv = nDiv; + hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + mask = BITM_CLKG_CLK_CTL1_PCLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_PCLKDIVCNT; + break; + + case ADI_CLOCK_ACLK: +#ifdef ADI_DEBUG + /* Verify the divide factor is within the range */ + if ((nDiv > ACLK_MAX_DIV_VALUE) || (nDiv < ACLK_MIN_DIV_VALUE)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* verify requested ACLK freq is <= HCLK */ + pdiv = nDiv; + hdiv = (pADI_CLKG0_CLK->CTL1 & BITM_CLKG_CLK_CTL1_HCLKDIVCNT) >> BITP_CLKG_CLK_CTL1_HCLKDIVCNT; + if (hdiv > pdiv) { + return ADI_PWR_INVALID_CLOCK_SPEED; + } + + /* verify new PDIV:HDIV ratio will be integral */ + if ((pdiv % hdiv) != 0u) + { + return ADI_PWR_INVALID_CLOCK_RATIO; + } +#endif /*ADI_DEBUG*/ + + mask = BITM_CLKG_CLK_CTL1_ACLKDIVCNT; + value = (uint32_t)nDiv << BITP_CLKG_CLK_CTL1_ACLKDIVCNT; + break; + + + default: + return ADI_PWR_INVALID_CLOCK_ID; + } /* end switch */ + + /* critical region */ + ADI_ENTER_CRITICAL_REGION(); + + /* read-modify-write without any interrupts */ + /* change in a tmp variable and write entire new value all at once */ + tmp = pADI_CLKG0_CLK->CTL1; + tmp &= ~mask; /* blank the field */ + tmp |= value; /* set the new value */ + pADI_CLKG0_CLK->CTL1 = tmp; /* write the new value */ + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + /* refresh internal clock variables */ + SystemCoreClockUpdate(); + + return ADI_PWR_SUCCESS; +} + +/*! + * @brief To Enable/disable clock sources. + * + * @param[in] eClockSource : Clock source identifier. + * @param[in] bEnable : Enable (true) or disable (false) the clock source. + * + * @return Status + * - #ADI_PWR_SUCCESS if the clock source powers up successfully. + * - #ADI_PWR_INVALID_PARAM if the clock source is not valid. + * + * @details Enables or disables clock sources without additional checks, by writing a "1" or "0" to the enable bit. + * + */ +ADI_PWR_RESULT adi_pwr_EnableClockSource (const ADI_CLOCK_SOURCE_ID eClockSource, const bool bEnable) +{ + uint32_t val = 0u; + volatile uint32_t *pReg = NULL; + uint32_t nMask = 0u; + ADI_INT_STATUS_ALLOC(); + + /* This switch statement does not handle every value in the ADI_CLOCK_SOURCE_ID enumeration + * which results on a gcc warning. This is done intentionally: + * ADI_CLOCK_SOURCE_LFOSC is not checked because it is enabled always and it cannot be disabled + * ADI_CLOCK_SOURCE_GPIO is only checked if a specific configuration macro is defined + */ + switch(eClockSource) + { + case ADI_CLOCK_SOURCE_HFXTAL: + val = (1u << BITP_CLKG_OSC_CTL_HFX_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_HFX_OK; + break; + + case ADI_CLOCK_SOURCE_LFXTAL: + val = (1u << BITP_CLKG_OSC_CTL_LFX_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_LFX_OK; + break; + + case ADI_CLOCK_SOURCE_HFOSC: + val = (1u << BITP_CLKG_OSC_CTL_HFOSC_EN); + pReg = &pADI_CLKG0_OSC->CTL; + nMask = BITM_CLKG_OSC_CTL_HFOSC_OK; + break; + + case ADI_CLOCK_SOURCE_SPLL: + val = (1u << BITP_CLKG_CLK_CTL3_SPLLEN); + pReg = &pADI_CLKG0_CLK->CTL3; + nMask = BITM_CLKG_CLK_CTL3_SPLLEN; + break; + +#if (ADI_PWR_CFG_ENABLE_CLOCK_SOURCE_GPIO == 1) + case ADI_CLOCK_SOURCE_GPIO: + if(adi_gpio_PullUpEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,false) != ADI_GPIO_SUCCESS) + { + return(ADI_PWR_FAILURE); + } + if(adi_gpio_InputEnable(ADI_GPIO_PORT1,ADI_GPIO_PIN_10,true) != ADI_GPIO_SUCCESS) + { + return ADI_PWR_SUCCESS; + } + break; +#endif + + default: + return(ADI_PWR_INVALID_PARAM); + + } /* end switch */ + + ADI_ENTER_CRITICAL_REGION(); + + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + if (bEnable == true) + { + *pReg |= val; + } + else + { + *pReg &= ~val; + } + + ADI_EXIT_CRITICAL_REGION(); + + if((nMask !=0u) && (bEnable == true)) + { + while(0u== (pADI_CLKG0_OSC->CTL & nMask)){} + } + + return (ADI_PWR_SUCCESS); +} + + +/*! + * @brief Return the status of a clock source. + * + * @param[in] eClockSource : Clock source identifier. + * @param[out] peStatus : Pointer to variable of type #ADI_CLOCK_SOURCE_STATUS for storing clock source status. + * + * @return Status + * - #ADI_PWR_SUCCESS if the clock source is disabled. + * - #ADI_PWR_NULL_POINTER [D] if the given pointer is pointing to NULL. + + * @details Return the status of a clock source. + * + */ +ADI_PWR_RESULT adi_pwr_GetClockStatus (const ADI_CLOCK_SOURCE_ID eClockSource, ADI_CLOCK_SOURCE_STATUS *peStatus) +{ + uint32_t val = pADI_CLKG0_OSC->CTL; + +#ifdef ADI_DEBUG + if(peStatus == NULL) + { + return ADI_PWR_NULL_POINTER; + } +#endif /* ADI_DEBUG */ + + *peStatus = ADI_CLOCK_SOURCE_DISABLED; + + switch(eClockSource) + { + case ADI_CLOCK_SOURCE_HFOSC: + if ((val & BITM_CLKG_OSC_CTL_HFOSC_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_HFOSC_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_HFXTAL: + if ((val & BITM_CLKG_OSC_CTL_HFX_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_HFX_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_LFXTAL: + if ((val & BITM_CLKG_OSC_CTL_LFX_EN) != 0u) + { + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_LFX_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + } + break; + + case ADI_CLOCK_SOURCE_LFOSC: + /* Clock source enabled, now check for stable */ + if ((val & BITM_CLKG_OSC_CTL_LFOSC_OK) != 0u) + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_STABLE; + } + else + { + *peStatus = ADI_CLOCK_SOURCE_ENABLED_NOT_STABLE; + } + break; + + /* Since the clock through GPIO is supplied externally we cannot get + the clock status for GPIO */ + case ADI_CLOCK_SOURCE_GPIO: + default: + *peStatus = ADI_CLOCK_SOURCE_ID_NOT_VALID; + break; + + } /* end switch */ + + return ADI_PWR_SUCCESS; +} + +/*! + * @brief Enable/Disable the clock interrupt to monitor status of LFXTAL, HFXTAL and PLL. + * + * @param[in] eIrq : Specify which interrupt need to be enable/disabled. + @param[in] bEnable : Specifies to enable/disable the specified interrupt. + * + * @return Status + * - #ADI_PWR_SUCCESS Enabled the specified interrupt. + * + * @sa adi_pwr_SetVoltageRange() + */ + +ADI_PWR_RESULT adi_pwr_EnableClockInterrupt(const ADI_PWR_CLOCK_IRQ eIrq, const bool bEnable) +{ + ADI_INT_STATUS_ALLOC(); + volatile uint32_t *pReg = NULL; + uint32_t tmp; + + switch(eIrq) + { + /*! Interrupt for root clock monitor and Clock Fail */ + case ADI_PWR_ROOT_CLOCK_MON_IEN: + pReg = &pADI_CLKG0_OSC->CTL; + break; + + /*! Interrupt for LFXTAL clock monitor and Clock Fail */ + case ADI_PWR_LFXTAL_CLOCK_MON_IEN: + pReg = &pADI_CLKG0_OSC->CTL; + break; + + /*! Interrupt when LFXTAL clock becomes stable/unstable */ + case ADI_PWR_LFXTAL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL0; + break; + + /*! Interrupt when HFXTAL clock becomes stable/unstable */ + case ADI_PWR_HFXTAL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL0; + break; + + /*! Interrupt when PLL-LOCK/PLL-UNLOCK */ + case ADI_PWR_PLL_STATUS_IEN: + pReg = &pADI_CLKG0_CLK->CTL3; + break; + + default: + break; + } + + ADI_ENTER_CRITICAL_REGION(); + + tmp = *pReg; + + if(bEnable == true) + { + tmp |= (uint32_t)eIrq; + } + else + { + tmp &= ~((uint32_t)eIrq); + } + + /* If we have to write to oscillator control register unlock it */ + if(pReg == &pADI_CLKG0_OSC->CTL) + { + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + } + *pReg = tmp; + + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Program PLL frequency. + * + * @param[in] nDivFactor PLL divider(M). + * @param[in] nMulFactor PLL Multiplier(N) + * @param[in] bDiv2 PLL DIV2 parameter. + * @param[in] bMul2 PLL DIV2 parameter. + * + * @return Status + * - #ADI_PWR_SUCCESS if the PLL has been programmed successfully. + * - #ADI_PWR_OPERATION_NOT_ALLOWED [D] if trying to program SPLL and SPLL drives the system clock. + * - #ADI_PWR_INVALID_CLOCK_ID [D] if the clock identifier does not match either PLL. + * + * @details Program PLL frequency (parameters M, N, DIV2) forSystem PLL(SPLL). + * + * SPLL = input clock * ["(N * (1+ bMul2 )" / "((1+bDiv2)*M)" ] + * where input clock can be HFOSC or HFXTAL. + */ +ADI_PWR_RESULT adi_pwr_SetPll(uint8_t nDivFactor, const uint8_t nMulFactor, const bool bDiv2, const bool bMul2) +{ + uint32_t val, cfg = 0u; + uint8_t nTempDivFactor = nDivFactor, nTempMulFactor = nMulFactor; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* Check if multiplication factor and division factor is more than 6 bits */ + if (((nMulFactor & ~0x3Fu) != 0u) || ((nDivFactor & ~0x3Fu) != 0u)) + { + return ADI_PWR_INVALID_CLOCK_DIVIDER; + } + + /* Check if the PLL is multipexed in as root clock source, parameters should not change in that case */ + if((pADI_CLKG0_CLK->CTL0 & BITM_CLKG_CLK_CTL0_CLKMUX) == + ((uint32_t)((ADI_CLOCK_MUX_ROOT_SPLL - ADI_CLOCK_MUX_ROOT_HFOSC) << BITP_CLKG_CLK_CTL0_CLKMUX))) + { + return ADI_PWR_OPERATION_NOT_ALLOWED; + } +#endif + + if(nTempDivFactor < MINIMUM_PLL_DIVIDER) + { + nTempDivFactor = MINIMUM_PLL_DIVIDER; + } + if(nTempMulFactor < MINIMUM_PLL_MULTIPLIER) + { + nTempMulFactor = MINIMUM_PLL_MULTIPLIER; + } + + cfg = (((uint32_t)nTempDivFactor) << BITP_CLKG_CLK_CTL3_SPLLMSEL)|( ((uint32_t) nTempMulFactor) << BITP_CLKG_CLK_CTL3_SPLLNSEL); + + if(bDiv2 == true) + { + cfg |= (1u <CTL3; + val &= ~( BITM_CLKG_CLK_CTL3_SPLLMUL2 | BITM_CLKG_CLK_CTL3_SPLLMSEL | BITM_CLKG_CLK_CTL3_SPLLDIV2 | BITM_CLKG_CLK_CTL3_SPLLNSEL); + val |= cfg; + pADI_CLKG0_CLK->CTL3 = val; + + /* end critical region */ + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + * @brief Enable/Disable the power management interrupt. + * + * @param[in] eIrq : Specify which interrupt need to be enable/disabled. + @param[in] bEnable : Specifies to enable/disable the interrupt. + * + * @return Status + * - #ADI_PWR_SUCCESS Enabled the specified interrupt. + * - #ADI_PWR_FAILURE [D] Enabling the battery monitoring interrupt when range is set to safe range (VBAT > 2.75 ). + * + * @note : User should configure the appropriate voltage range before enabling the interrupt for battery voltage range. + * + * @sa adi_pwr_SetVoltageRange() + */ +ADI_PWR_RESULT adi_pwr_EnablePMGInterrupt(const ADI_PWR_PMG_IRQ eIrq, const bool bEnable) +{ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if(((pADI_PMG0->IEN & BITM_PMG_IEN_RANGEBAT) == 0u) || (eIrq != ADI_PWR_BATTERY_VOLTAGE_RANGE_IEN)) + { + return(ADI_PWR_FAILURE); + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if(bEnable == true) + { + pADI_PMG0->IEN |= (uint32_t)eIrq; + } + else + { + pADI_PMG0->IEN &= ~(uint32_t)(eIrq); + } + ADI_EXIT_CRITICAL_REGION(); + + return(ADI_PWR_SUCCESS); +} + + + +/*! + * @brief Enable/disable LFXTAL bypass mode. + * + @param[in] bEnable : Specifies to enable/disable the LFXTAL bypass mode + *\n true: To enable LFXTAL bypass mode. + * \n false: To disable LFXTAL bypass mode. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL bypass mode. + * - #ADI_PWR_FAILURE[D] Failed to Enable/Disable LFXTAL bypass mode. + * + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALBypass(const bool bEnable) +{ + volatile uint32_t nDelay = 0xFFFFFFu; + if(bEnable == true) + { + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Disable the LFXTAL */ + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_EN); + /* Wait till status de-asserted. */ + while(nDelay != 0u) + { + if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Enable the BYPASS mode */ + pADI_CLKG0_OSC->CTL |= (BITM_CLKG_OSC_CTL_LFX_BYP); + /* Wait till status asserted. */ + nDelay = 0xFFFFFFu; + while(nDelay != 0u) + { + if(((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK)== BITM_CLKG_OSC_CTL_LFX_OK)) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + + } + else + { + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + /* Disable the BYPASS mode */ + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_BYP); + /* Wait till status de-asserted. */ + while(nDelay != 0u) + { + if((pADI_CLKG0_OSC->CTL & BITM_CLKG_OSC_CTL_LFX_OK) == 0u) + { + break; + } + nDelay--; + } +#ifdef ADI_DEBUG + if(nDelay == 0u) + { + return(ADI_PWR_FAILURE); + } +#endif + } + + return(ADI_PWR_SUCCESS); +} + + + +/*! + * @brief Enables or disables the LFXTAL Robust mode. + * The Robust mode enables the LFXTAL oscillator to work also when an additional resistive + * load is placed between the crystal pins and GND. This feature is capable of tolerating + * the presence of impurities on the PCB board, where these impurities allow a high-resistance + * leakage path from the crystal pins to ground, which can cause problems to the circuit operation + * + * @param[in] bEnable : Flag which indicates whether to enable or disable LFXTAL Robust mode. + true - Enable Robust mode. + false - Disable Robust mode. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL Robust mode. + * + * @sa adi_pwr_SetLFXTALRobustModeLoad() + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALRobustMode( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_ROBUST_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_ROBUST_EN); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Enable/Disable the LFXTAL Fail Auto switch. + * Enables/Disable automatic Switching of the LF Mux to LF OSC on LF XTAL Failure. + * + * @param[in] bEnable : Flag which indicates whether to enable/disable LFXTAL Auto switch. + * true - Enable LFXTAL Auto switch. + * false - Disable LFXTAL Auto switch. + * @return Status + * - #ADI_PWR_SUCCESS Enabled/Disabled LFXTAL Auto switch mode. + */ +ADI_PWR_RESULT adi_pwr_EnableLFXTALFailAutoSwitch( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_LFX_AUTSW_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_LFX_AUTSW_EN); + } + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Sets the LFXT Robust Mode Load. + * Selects the amount of loading tolerated when LFXTAL robust mode is enabled. + * + * @param[in] eLoad : Amount of loading tolerance required. + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load tolerance for LFXTAL Robust mode. + * + * @sa adi_pwr_EnableLFXTALRobustMode() + */ +ADI_PWR_RESULT adi_pwr_SetLFXTALRobustModeLoad( const ADI_PWR_LFXTAL_LOAD eLoad ) +{ + uint32_t tmp; + + tmp = pADI_CLKG0_OSC->CTL & ~BITM_CLKG_OSC_CTL_LFX_ROBUST_LD; + tmp |= ((uint32_t)eLoad) << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD; + + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + pADI_CLKG0_OSC->CTL = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief To enable/disable auto switching of root clock to HFOSC upon detection of Root clock failure. + * This feature is valid only when the ROOT clock monitor is enabled. The root clock monitoring + * can be enabled by using the API #adi_pwr_EnableClockInterrupt. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable Root clock auto switch. + * true - Enable Root clock auto switch. + false - Disable Root clock auto switch. + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load tolerance for LFXTAL Robust mode. + * + * @sa adi_pwr_EnableClockInterrupt() + */ +ADI_PWR_RESULT adi_pwr_EnableRootClockFailAutoSwitch( const bool bEnable ) +{ + /* Write the oscillator key */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + if(bEnable == true) + { + pADI_CLKG0_OSC->CTL |= BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN; + } + else + { + pADI_CLKG0_OSC->CTL &= ~(BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Sets the HF Oscillator divide factor. + * + * Sets the divide factor for the clocks derived from the HF oscillator clock. + * + * @param[in] eDivFactor : HF Clock divide factor to be set. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the clock divide factor for HF Oscillator. + * + * @note When the HF Oscillator auto divide by 1 is set, the divide factor set is automatically + * changed to 1 when coming out of Flexi mode. Application should set it back to the + * required divide after coming out of Flexi mode. + * + * @sa adi_pwr_EnableHFOscAutoDivBy1() + */ +ADI_PWR_RESULT adi_pwr_SetHFOscDivFactor( const ADI_PWR_HFOSC_DIV eDivFactor ) +{ + uint32_t tmp; + + tmp = (pADI_CLKG0_CLK->CTL2 & ~BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL); + tmp |= ((uint32_t) eDivFactor << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL); + pADI_CLKG0_CLK->CTL2 = tmp; + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enable or disable the HF oscillator automatic divide by 1 during wakeup from Flexi mode. + * + * This is used to enable/disable the fast wakeup from Flexi power mode. When the fast wakeup + * from Flexi mode is enabled, the frequency undivided 26MHz HF oscillator clock itself will + * be used during the wake up. The undivided HFOSC clock is selected automatically by setting + * the HF oscillator divide factor to 1. This updated divided by 1 clock selection will remain + * same until the new divider value is set. + * + * When disabled the HF Oscillator divide factor will remain unchanged during the wakeup. + * + * @param[in] bEnable : Flag which indicates whether HF oscillator automatic divide by 1 is enabled/disabled. + * 'true' - To enable automatic divide by 1. + * 'false' - To disable automatic divide by 1. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully enable/disabled HF Oscillator automatic divide by 1. + * + * @sa adi_pwr_SetHFOscDivFactor() + */ +ADI_PWR_RESULT adi_pwr_EnableHFOscAutoDivBy1( const bool bEnable ) +{ + if(bEnable == true) + { + pADI_CLKG0_CLK->CTL2 |= BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN; + } + else + { + pADI_CLKG0_CLK->CTL2 &= ~(BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Set the clock output through the GPIO. + * + * @param[in] eClockOutput : Clock to be output through the GPIO pin. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the GPIO clock output. + */ +ADI_PWR_RESULT adi_pwr_SetGPIOClockOutput( const ADI_CLOCK_OUTPUT_ID eClockOutput ) +{ + uint32_t tmp; + + tmp = (pADI_CLKG0_CLK->CTL0 & ~BITM_CLKG_CLK_CTL0_CLKOUT); + tmp |= ((uint32_t)eClockOutput << BITP_CLKG_CLK_CTL0_CLKOUT); + pADI_CLKG0_CLK->CTL0 = tmp; + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enables or disables the HP Buck. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable HPBuck + * 'true' - To enable HPBuck. + * 'false' - To disable HPBuck. + * @return Status + * - #ADI_PWR_SUCCESS Successfully enabled or disabled HPBUCK successfully. + */ +ADI_PWR_RESULT adi_pwr_EnableHPBuck(const bool bEnable) +{ + if(bEnable == true) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCKEN; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCKEN); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Enable or disable the HPBuck Low Power mode. + * The HPBUCK Low Power mode can be selected, when the Chip is in Flexi Power mode + * and low power modules such as Timer, Beeper only are enabled. + * + * @param[in] bEnable : Flag which indicates whether to enable or disable HPBuck low power mode. + * 'true' - Enable HPBuck low power mode. + * 'false' - Disable HPBuck low power mode. + * @return Status + * - #ADI_PWR_SUCCESS Successfully enabled or disabled the HPBuck low power mode. + */ +ADI_PWR_RESULT adi_pwr_EnableHPBuckLowPowerMode( const bool bEnable ) +{ + if(bEnable == true) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE); + } + + return(ADI_PWR_SUCCESS); +} + +/*! + * @brief Set the HP Buck load mode. + * + * HP Buck load mode can be set based on the system load. + * The low load mode can be set when the system is running below 26Mhz. + * The High load mode can be set when the system is running at greater than 26Mhz. + * + * @param[in] eLoadMode : Load mode to be set. + * + * @return Status + * - #ADI_PWR_SUCCESS Successfully set the load mode. + */ +ADI_PWR_RESULT adi_pwr_SetHPBuckLoadMode( const ADI_PWR_HPBUCK_LD_MODE eLoadMode ) +{ + if(eLoadMode == ADI_PWR_HPBUCK_LD_MODE_HIGH) + { + pADI_PMG0->CTL1 |= BITM_PMG_CTL1_HPBUCK_LD_MODE; + } + else + { + pADI_PMG0->CTL1 &= ~(BITM_PMG_CTL1_HPBUCK_LD_MODE); + } + + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief Function to retrieve the wakeup from shut down mode status. + * + * @param[in] peStatus : Pointer to #ADI_PWR_WAKEUP_STATUS for returning the wakeup status. + * + * @return Status + * - #ADI_PWR_SUCCESS: Successfully returned the shut down status. + */ +ADI_PWR_RESULT adi_pwr_GetWakeUpStatus(ADI_PWR_WAKEUP_STATUS *peStatus) +{ + *peStatus =(ADI_PWR_WAKEUP_STATUS) pADI_PMG0->SHDN_STAT; + return(ADI_PWR_SUCCESS); +} + + +/*! + * @brief To Monitor voltage range of battery. + * + * @param[in] eRange : Specify the voltage range for the battery. + * + * @return Status + * - #ADI_PWR_SUCCESS: Successfully programmed battery range. + * @details + * + */ +ADI_PWR_RESULT adi_pwr_SetVoltageRange(const ADI_PWR_VOLTAGE_RANGE eRange) +{ + uint32_t tmp; + + tmp = (pADI_PMG0->IEN & ~BITM_PMG_IEN_RANGEBAT); + tmp |= ((uint32_t)eRange << BITP_PMG_IEN_RANGEBAT); + pADI_PMG0->IEN = tmp; + + return(ADI_PWR_SUCCESS); +} + +/*! \cond PRIVATE */ + +/* + * Interrupt handler for PLL interrupts. + */ +void PLL_Int_Handler(void) +{ + ISR_PROLOG(); + + /* As the same status word is shared between two interrupts + Crystal_osc_Int_Handler and PLL_Int_Handler + check and clear status bits handled in this handler */ + uint32_t nStatus = (pADI_CLKG0_CLK->STAT0 & + (BITM_CLKG_CLK_STAT0_SPLLUNLK | BITM_CLKG_CLK_STAT0_SPLLLK)); + + /* If a callback is registered notify the events */ + if(gpfCallbackFunction != NULL) + { + if((nStatus & BITM_CLKG_CLK_STAT0_SPLLUNLK ) != 0u) + { + /* PLL unlock event */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_UNLOCK,(void *)0); + } + else if((nStatus & BITM_CLKG_CLK_STAT0_SPLLLK) != 0u) + { + /* PLL lock event */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_PLLC_LOCK,(void *)0); + } + else + { + /* Do nothing */ + } + } + + /* Clear the status bits */ + pADI_CLKG0_CLK->STAT0 = nStatus; + + ISR_EPILOG(); +} + +/* + * Interrupt handler for oscillator interrupts. + */ +void Crystal_osc_Int_Handler(void) +{ + ISR_PROLOG(); + + /* As the same status word is shared between two interrupts + Crystal_osc_Int_Handler and PLL_Int_Handler + check and clear status bits handled in this handler */ + uint32_t nClkStatus = (pADI_CLKG0_CLK->STAT0 & + (BITM_CLKG_CLK_STAT0_HFXTALNOK | + BITM_CLKG_CLK_STAT0_HFXTALOK | + BITM_CLKG_CLK_STAT0_LFXTALOK | + BITM_CLKG_CLK_STAT0_LFXTALNOK)); + + /* Check if the interrupt was generated due to failure in Root Clock or LFXTAL */ + uint32_t nOscStatus = (pADI_CLKG0_OSC->CTL & (BITM_CLKG_OSC_CTL_LFX_FAIL_STA | + BITM_CLKG_OSC_CTL_ROOT_FAIL_STA | + BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA | + BITM_CLKG_OSC_CTL_LFX_AUTSW_STA )); + + uint32_t nEvent = 0u; + + + if(gpfCallbackFunction != NULL) + { + /* Is the interrupt caused due to HFXTAL or LFXTAL status */ + if(nClkStatus != 0u) + { + if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_NO_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_HFXTALOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_HFXTAL_CLOCK_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_OK; } + else if ((nClkStatus & BITM_CLKG_CLK_STAT0_LFXTALNOK) != 0u) { nEvent |= ADI_PWR_EVENT_OSC_LFXTAL_CLOCK_NO_OK; } + else { /* do nothing */ } + + if(nEvent != 0u) { gpfCallbackFunction( gpPowcbParam, nEvent, (void *)0u); } + + } + /* Or is the interrupt caused due to Root Clock or LFXTAL failure status */ + else if(nOscStatus != 0u) + { + /* Did the LFXTAL failed */ + if( (nOscStatus & BITM_CLKG_OSC_CTL_LFX_FAIL_STA) != 0u) + { + /* Notifiy LFXTAL failure */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_MON_FAIL, (void *)0u); + + /* Did the HW auto switched to LFOSC due to LFXTAL failure */ + if((nOscStatus & BITM_CLKG_OSC_CTL_LFX_AUTSW_STA) != 0u) + { + /* Notify about the auto switch to LFOSC */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_LFXTAL_AUTO_SWITCH, (void *)0u); + } + } + /* Did the root clock failed */ + else if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_FAIL_STA) != 0u) + { + /* Indicate about the root clock failure */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_MON_FAIL, (void *)0u); + + /* Did the HW auto switched to HFOSC due to root clock failure */ + if((nOscStatus & BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA) != 0u) + { + /* Notify about auto switch to HFOSC */ + gpfCallbackFunction( gpPowcbParam, ADI_PWR_EVENT_OSC_ROOT_CLOCK_FAIL_AUTO_SWITCH, (void *)0u); + } + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + + /* Clear the staus bits */ + if(nClkStatus != 0u) + { + pADI_CLKG0_CLK->STAT0 = nClkStatus; + } + else if(nOscStatus != 0u) + { + /* Write the oscillator key to clear the status bits */ + pADI_CLKG0_OSC->KEY = ADI_OSC_KEY; + + /* Clear only status bits */ + pADI_CLKG0_OSC->CTL |= nOscStatus; + } + else + { + /* Do nothing */ + } + + ISR_EPILOG(); +} + +/* + * Interrupt handler for battery voltage interrupt. + */ +void Battery_Voltage_Int_Handler(void) +{ + ISR_PROLOG(); + uint32_t nStatus = pADI_PMG0->PSM_STAT; + + if ((nStatus & BITM_PMG_PSM_STAT_VBATUNDR) != 0u) + { + if(gpfCallbackFunction != NULL) + { + gpfCallbackFunction( gpPowcbParam, (uint32_t)nStatus, (void *)0); + } + pADI_PMG0->PSM_STAT |= (BITM_PMG_PSM_STAT_VBATUNDR); + } + ISR_EPILOG(); +} + +/* + * Interrupt handler for battery voltage interrupt. + */ +void Vreg_over_Int_Handler(void) +{ + ISR_PROLOG(); + uint32_t nStatus = pADI_PMG0->PSM_STAT; + + if(gpfCallbackFunction != NULL) + { + if ((nStatus & BITM_PMG_PSM_STAT_VREGOVR) != 0u) + { + gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_OVER_VOLTAGE, NULL); + } + if ((nStatus & BITM_PMG_PSM_STAT_VREGUNDR) != 0u) + { + gpfCallbackFunction(gpPowcbParam, (uint32_t)ADI_PWR_EVENT_VREG_UNDER_VOLTAGE, NULL); + } + } + pADI_PMG0->PSM_STAT |= (nStatus &(BITM_PMG_PSM_STAT_VREGOVR | BITM_PMG_PSM_STAT_VREGUNDR)); + ISR_EPILOG(); +} + +/*! \endcond */ +/*! + @brief Puts the processor into given low power mode. + + @param[in] PowerMode One of the ADI_PWR_POWER_MODE enum values, defining the specific + low-power modes to use. + + @param[in,out] pnInterruptOccurred + Control parameter selection low-power operation. Either a NULL pointer + for automatic hardware-based sleeping between interrupts, or a pointer + to uint32_t for software looping sleep between interrupts. + + If a pointer to uint32_t is passed in, the integer must be \b 0 on entry, + and will be set to \b 0 on exit. + + When a NULL is passed, it means the application wants the low-power + implementation to use the automatic "sleep-on-exit" hardware sleep + mode in which wakeup interrupts are dispatched and then automatically + put the processor back to sleep on exit. All interrupts execute the + same WFI instruction (no looping) under hardware control, which results + in a faster re-sleep than the software mode. + + When a non-NULL value is passed, it is interpreted as a pointer to a + shared integer application control variable allowing the wake-up + interrupts to control whether/when the control loop should re-sleep the + processor as each interrupt exits. Any interrupt that sets the variable + will cause the sleep loop to exit. Otherwise, exiting interrupts will + cause the core to re-sleep until the variable is set. Each interrupt executes + a different WFI instruction inside a software loop (slower re-sleep). + + @param[in] PriorityMask A right-justified (un shifted) wakeup interrupt priority mask, corresponding + to the programmable interrupt priority encoding scheme defined by the Cortex + NVIC controller. The \a PriorityMask value blocks interrupts with an equal + or lower priority than the specified level, such that only higher-priority + interrupts (less in numerical value) than the priority mask awake the + processor. A zero-valued \a PriorityMask disables interrupt masking. + + @return Status + - #ADI_PWR_SUCCESS If successfully put the processor into low power mode. + - #ADI_PWR_INVALID_PARAM[D] PriorityMask contains unimplemented hardware bits. + + + + Puts the processor into a low-power mode with interrupt-based wakeup(s). Applications specify the low-power + mode, a pointer to an application-defined interrupt variable, and an interrupt priority mask controlling the + interrupt priority level that may awake the processor. + + @par pnInterruptOccurred + When NULL, the processor is automatically put back to sleep as awaking interrupts exit. This mode employs + the hardware "sleep-on-exit" system control register bit: SLEEPONEXIT_BIT in conjunction with the "wait-for- + interrupt" (WFI) instruction to implement a persistent sleep mode. + + When non-Null, a software strategy is used to control sleeping. As awakening interrupts are processed, they + can increment the interrupt controlling variable and thereby cause the sleep mode to be exited. Note that all + interrupts share a common variable and any interrupt that sets the variable will cause the sleep mode to be + exited. + + Use of the \a pnInterruptOccurred parameter provides a mechanism to resolve two potential hibernation trouble + spots: 1) the inherent race between the intended wakeup interrupt and the execution of the Wait-For-Interrupt + instruction (WFI) used to sleep the processor, and 2) unrelated interrupts (of sufficient priority) + that may terminate the wait prematurely. + + In the first case of the race condition, the race is avoided by testing the \a pnInterruptOccurred variable prior + to the WFI within a common critical section. This allows the #adi_pwr_EnterLowPowerMode() implementation + to insure the intended wakeup interrupt has not occurred already and control whether to sleep the processor. + This insures the intended wakeup interrupt has not already occurred prior to the wait, thereby eliminating the + race condition otherwise present. + + In the second case of an unrelated interrupt terminating the sleep prematurely, the problem is solved by + requiring the interrupt handler(s) which is(are) intended to awake the sleeping processor to set the + application-defined \a pnInterruptOccurred variable in their respective interrupt handler(s). This insures only those + interrupts that explicitly set the variable will break the sleeping processor out of the sleep cycle. Other + (incidental) interrupts put the processor back to sleep after the interrupt because the variable would not have been set. + This is why there is a loop around the WFI instruction. + + The \a pnInterruptOccurred variable must be initialized to zero before first use, and this should be done + prior to enabling any interrupt which may set it (otherwise interrupts may be missed). If this variable is + global or static then static initialization to zero or false will be sufficient. + + The variable should only be set, from an interrupt handler, by calling adi_pwr_ExitLowPowerMode() and passing + the variable by reference. The variable should not be assigned to directly, other than for initialization. + + #adi_pwr_EnterLowPowerMode() will always clear the variable again before returning, so it does not + need to be cleared by user code on each use. Explicitly clearing the variable, outside of #adi_pwr_EnterLowPowerMode() + runs the risk of missing interrupts. + + @par PriorityMask + A zero-valued \a PriorityMask disables interrupt masking, leaving all interrupts eligible to awake the + sleeping processor. This means that zero-valued interrupts cannot be masked. A non-zero \a PriorityMask + limits interrupts that may awake the sleeping processor to those with a higher priority level (lower + numerically) than the specified \a PriorityMask value. + + Each "programmable" peripheral interrupt has an associated priority-level register (which defaults to + zero) within the Nested Vectored Interrupt Controller (NVIC). The number of interrupt priority encoding + bits is defined by constant __NVIC_PRIO_BITS and is a fixed silicon attribute configured during chip + design. The interrupt priority-level registers range in width from 3 to 8 bits. + + This processor uses 3-bit priority encoding, allowing priority levels ranging between 0 (the highest, + default programmable priority) and 7 (the lowest). For example, if the \a PriorityMask parameter is + set to 3, only interrupts with assigned priority 0, 1, and 2 may awake the processor. Since default + priority of all programmable interrupts is 0, setting up maskable interrupts requires that they be + demoted in priority (raised numerically) relative to interrupts that are intended to awake the processor. + + @note The number of priority levels is uncorrelated with the actual number of interrupts or their position + in the Interrupt Vector Table (IVT). Interrupt priorities may be programmed individually.\n\n + + @note The priority levels are actually stored in the core as a left-justified value in an 8-bit field. + The #adi_pwr_EnterLowPowerMode() API takes care of aligning the passed \a PriorityMask value to the + core register (BASEPRI).\n\n + + @note The default priority level for all interrupts is zero, which implies it is impossible to mask interrupts + with a default zero-level priority encoding. All interrupt priorities must be managed to create meaningful + interrupt masks for low-power wakeups, as described above.\n\n + + @warning Do not modify the BASEPRI register (used for masking interrupt priority) during interrupts that take + the core out of low-power mode momentarily. The BASEPRI register is saved/restored on low-power mode + entry/exit to honor user priority requests. Interrupt-level changes to BASEPRI will be clobbered on + low-power exit as the saved value is restored.\n\n + + @sa adi_pwr_ExitLowPowerMode +*/ +ADI_PWR_RESULT adi_pwr_EnterLowPowerMode ( const ADI_PWR_POWER_MODE PowerMode, + uint32_t volatile * pnInterruptOccurred, + const uint8_t PriorityMask + ) +{ + uint32_t savedPriority; + uint32_t scrSetBits = 0u; + uint32_t scrClrBits = 0u; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + + /* verify the requested priority mask bits are right-justified and don't exceed __NVIC_PRIO_BITS in width */ + if ((PriorityMask & ~((1u << __NVIC_PRIO_BITS) - 1u)) != 0u) + { + return ADI_PWR_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* pre-calculate the sleep-on-exit set/clear bits */ + if(NULL == pnInterruptOccurred) { + scrSetBits |= SCB_SCR_SLEEPONEXIT_Msk; + + /* point to private control variable when in hardware (sleep-on-exit) mode */ + pnInterruptOccurred = &gnLowPowerIntOccFlag; + } + + /* pre-calculate the deepsleep and sleep-on-exit set/clear bits */ + switch (PowerMode) { + + case ADI_PWR_MODE_ACTIVE: /* Note: this value is a "reserved" PWRMODE register code. */ + return ADI_PWR_SUCCESS; /* avoids the reserved value "1" being written to PWRMODE. */ + + case ADI_PWR_MODE_FLEXI: /* wfi without deepsleep or sleep-on-exit */ + scrClrBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + break; + + case ADI_PWR_MODE_HIBERNATE: /* wfi with deepsleep and sleep-on-exit per pnInterruptOccurred setting */ + scrSetBits |= BITM_NVIC_INTCON0_SLEEPDEEP; + + break; + + case ADI_PWR_MODE_SHUTDOWN: /* wfi with both deepsleep and sleep-on-exit */ + /* Note: sleep-on-exit causes WFI to never exit and wakeup is only through system reset. */ + scrSetBits |= (uint32_t)(BITM_NVIC_INTCON0_SLEEPDEEP | BITM_NVIC_INTCON0_SLEEPONEXIT); + break; + + default: + return ADI_PWR_INVALID_POWER_MODE; + + } /* end switch */ + + /* put the power mode and system control mods, as well as the WFI loop inside a critical section */ + ADI_ENTER_CRITICAL_REGION(); + + { /* these lines must be in a success-checking loop if they are not inside critical section */ + /* Uninterruptable unlock sequence */ + pADI_PMG0->PWRKEY = ADI_PMG_KEY; + + /* Clear the previous mode and set new mode */ + pADI_PMG0->PWRMOD = (uint32_t) ( ( pADI_PMG0->PWRMOD & (uint32_t) (~BITM_PMG_PWRMOD_MODE) ) | PowerMode ); + } + + /* Update the SCR (sleepdeep and sleep-on-exit bits) */ + SCB->SCR = ((SCB->SCR | scrSetBits) & ~scrClrBits); + + /* save/restore current Base Priority Level */ + savedPriority = __get_BASEPRI(); + + /* assert caller's priority threshold (left-justified) */ + __set_BASEPRI((uint32_t)PriorityMask << (8u -__NVIC_PRIO_BITS)); + + /* if we are in the software looping mode, loop on the user's variable until set */ + while (0u == *pnInterruptOccurred) { + + __DSB(); /* bus sync to insure register writes from interrupt handlers are always complete before WFI */ + + /* NOTE: aggressive compiler optimizations can muck up critical timing here, so reduce if hangs are present */ + + /* The WFI loop MUST reside in a critical section because we need to insure that the interrupt + that is planned to take us out of WFI (via a call to adi_pwr_ExitLowPowerMode()) is not + dispatched until we get into the WFI. If that interrupt sneaks in prior to our getting to the + WFI, then we may end up waiting (potentially forever) for an interrupt that has already occurred. + */ + __WFI(); + + /* Recycle the critical section so that other (non-wakeup) interrupts are dispatched. + This allows *pnInterruptOccurred to be set from any interrupt context. + */ + ADI_EXIT_CRITICAL_REGION(); + /* nop */ + ADI_ENTER_CRITICAL_REGION(); + + } /* end while */ + + /* ...still within critical section... */ + + (*pnInterruptOccurred)--; /* decrement the completion variable on exit */ + + /* Restore previous base priority */ + __set_BASEPRI(savedPriority); + + /* clear sleep-on-exit bit to avoid sleeping on exception return to thread level */ + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + + __DSB(); /* bus sync before re-enabling interrupts */ + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_PWR_SUCCESS; +} + + +/*! + * Companion function to #adi_pwr_EnterLowPowerMode() that allows interrupts to \n + * break out of the "FLEXI" mode in which the processor stays in \n + * sleep while peripherals are active. \n + + @param[in,out] pnInterruptOccurred + Control parameter selection low-power operation. Either a NULL pointer \n + for hardware sleep-on-exit feature, or a pointer to uint32_t for software \n + looping sleep between interrupts. + @return Status + - #ADI_PWR_SUCCESS If successfully exited from low power mode. + + * @sa adi_pwr_EnterLowPowerMode + */ +ADI_PWR_RESULT adi_pwr_ExitLowPowerMode(uint32_t volatile * pnInterruptOccurred) +{ + ADI_INT_STATUS_ALLOC(); + + /* Manage the exit depending on pnInterruptOccurred convention... */ + /* NULL pointer means we are using the hardware sleep-on-exit feature */ + /* non-NULL pointer means we are using a software looping variable top sleep */ + + if (NULL == pnInterruptOccurred) { + + pnInterruptOccurred = &gnLowPowerIntOccFlag; /* point to private control variable in hardware mode */ + + /* clear hardware sleep-on-exit feature */ + ADI_ENTER_CRITICAL_REGION(); + + SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; + __DSB(); /* bus sync before interrupt exit */ + + ADI_EXIT_CRITICAL_REGION(); + } + + /* set control variable (whether hardware or software based) so WFI exits in SystemEnterLowPowerMode() */ + (*pnInterruptOccurred)++; + return ADI_PWR_SUCCESS; +} + +/* +** EOF +*/ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h new file mode 100755 index 00000000000..c5f372ed340 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/pwr/adi_pwr_def.h @@ -0,0 +1,172 @@ +/* + ***************************************************************************** + * @file: adi_pwr_def.h + * @brief: Definitions for the system clock and power management. + *----------------------------------------------------------------------------- + * + * Copyright (c) 2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef ADI_PWR_DEF_H +#define ADI_PWR_DEF_H + + /*Power control register access key */ +#define ADI_PMG_KEY (0x4859u) + + /*Osc control register access key */ +#define ADI_OSC_KEY (0xCB14u) + + /*HCLK/PCLK minimum Divider value */ +#define CLOCK_MIN_DIV_VALUE (0x1u) + + /*HCLK/PCLK maximum Divider value */ +#define CLOCK_MAX_DIV_VALUE (32u) + + /*ADC Clock minimum Divider value */ +#define ACLK_MIN_DIV_VALUE (0x1u) + + /*ADC Clock maximum Divider value */ +#define ACLK_MAX_DIV_VALUE (511u) + +/* Minimum divider for PLL */ +#define MINIMUM_PLL_DIVIDER (0x02u) + +/* Minimum multiplier for PLL */ +#define MINIMUM_PLL_MULTIPLIER (0x08u) + +/* Maximum external clock */ +#define MAXIMUM_EXT_CLOCK (26000000u) + + /* Default osc control register value */ +#define OSCCTRL_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_LF_CLOCK_MUX << BITP_CLKG_OSC_CTL_LFCLK_MUX | \ + (uint32_t) ADI_PWR_HFOSC_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFOSC_EN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_LFX_EN | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_ENABLE << BITP_CLKG_OSC_CTL_HFX_EN | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_MON_ENABLE << BITP_CLKG_OSC_CTL_LFX_MON_EN | \ + (uint32_t) ADI_PWR_LFXTAL_FAIL_AUTO_SWITCH_ENABLE << BITP_CLKG_OSC_CTL_LFX_AUTSW_EN | \ + (uint32_t) ADI_PWR_LFXTAL_ROBUST_MODE_ENABLE << BITP_CLKG_OSC_CTL_LFX_ROBUST_EN | \ + (uint32_t) ADI_PWR_LFXTAL_ROBUST_LOAD_SELECT << BITP_CLKG_OSC_CTL_LFX_ROBUST_LD | \ + (uint32_t) ADI_PWR_ROOT_CLOCK_MON_INT_ENABLE << BITP_CLKG_OSC_CTL_ROOT_MON_EN | \ + (uint32_t) ADI_PWR_ROOT_CLOCK_FAIL_AUTOSWITCH_ENABLE << BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN ) + + /* Default clock control register-0 value */ +#define CLOCK_CTL0_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_INPUT_TO_ROOT_CLOCK_MUX << BITP_CLKG_CLK_CTL0_CLKMUX | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_OUT_SELECT << BITP_CLKG_CLK_CTL0_CLKOUT | \ + (uint32_t) ADI_PWR_INPUT_TO_RCLK_MUX << BITP_CLKG_CLK_CTL0_RCLKMUX | \ + (uint32_t) ADI_PWR_INPUT_TO_SPLL_MUX << BITP_CLKG_CLK_CTL0_PLL_IPSEL | \ + (uint32_t) ADI_PWR_LFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_LFXTALIE | \ + (uint32_t) ADI_PWR_HFXTAL_CLOCK_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL0_HFXTALIE ) + + /* Default clock control register-1 value */ +#define CLOCK_CTL1_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_HCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_HCLKDIVCNT | \ + (uint32_t) ADI_PWR_PCLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_PCLKDIVCNT | \ + (uint32_t) ADI_PWR_ACLK_DIVIDE_COUNT << BITP_CLKG_CLK_CTL1_ACLKDIVCNT ) + +/* Default clock control register-2 value */ +#define CLOCK_CTL2_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_HFOSC_AUTO_DIV_BY_1 << BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN | \ + (uint32_t) ADI_PWR_HFOSC_DIVIDE_SELECT << BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL ) + + /* Default clock control register-3 value */ +#define CLOCK_CTL3_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_SPLL_MUL_FACTOR << BITP_CLKG_CLK_CTL3_SPLLNSEL | \ + (uint32_t) ADI_PWR_SPLL_ENABLE_DIV2 << BITP_CLKG_CLK_CTL3_SPLLDIV2 | \ + (uint32_t) ADI_PWR_SPLL_ENABLE << BITP_CLKG_CLK_CTL3_SPLLEN | \ + (uint32_t) ADI_PWR_SPLL_INTERRUPT_ENABLE << BITP_CLKG_CLK_CTL3_SPLLIE | \ + (uint32_t) ADI_PWR_SPLL_DIV_FACTOR << BITP_CLKG_CLK_CTL3_SPLLMSEL | \ + (uint32_t) ADI_PWR_SPLL_ENABLE_MUL2 << BITP_CLKG_CLK_CTL3_SPLLMUL2 ) + + /* Default clock control register-5 value */ +#define CLOCK_CTL5_CONFIG_VALUE \ + ( (uint32_t) ADI_PWR_GPT0_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK0OFF | \ + (uint32_t) ADI_PWR_GPT1_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK1OFF | \ + (uint32_t) ADI_PWR_GPT2_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPTCLK2OFF | \ + (uint32_t) ADI_PWR_I2C_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_UCLKI2COFF | \ + (uint32_t) ADI_PWR_GPIO_CLOCK_ENABLE << BITP_CLKG_CLK_CTL5_GPIOCLKOFF | \ + (uint32_t) ADI_PWR_PCLK_ENABLE << BITP_CLKG_CLK_CTL5_PERCLKOFF | \ + (uint32_t) ADI_PWR_TIMER_RGB_ENABLE << BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF ) + +/* Default configuration for Power supply monitor Interrupt Enable Register */ +#define PWM_INTERRUPT_CONFIG \ + ( (uint32_t) ADI_PWR_ENABLE_VBAT_INTERRUPT << BITP_PMG_IEN_VBAT | \ + (uint32_t) ADI_PWR_ENABLE_VREG_UNDER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGUNDR | \ + (uint32_t) ADI_PWR_ENABLE_VREG_OVER_VOLTAGE_INTERRUPT << BITP_PMG_IEN_VREGOVR | \ + (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_RANGE_INTERRUPT << BITP_PMG_IEN_IENBAT | \ + (uint32_t) ADI_PWR_BATTERY_VOLTAGE_RANGE_FOR_INTERRUPT << BITP_PMG_IEN_RANGEBAT ) + + /* Default configuration for Power Mode Register */ + #define PWM_PWRMOD_CONFIG \ + ( (uint32_t) ADI_PWR_ENABLE_BATTERY_VOLTAGE_MONITORING << BITP_PMG_PWRMOD_MONVBATN ) + +/* Default configuration for HP Buck Control register */ +#define PWM_HPBUCK_CONTROL \ + ( (uint32_t) ADI_PWR_HP_BUCK_ENABLE << BITP_PMG_CTL1_HPBUCKEN | \ + (uint32_t) ADI_PWR_HP_BUCK_LOAD_MODE << BITP_PMG_CTL1_HPBUCK_LD_MODE | \ + (uint32_t) ADI_PWR_HP_BUCK_LOW_POWER_MODE << BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE ) + + /*Selecting HFOSC as input for generating root clock*/ +#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting HFXTAL as input for generating root clock*/ +#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting SPLL as input for generating root clock*/ +#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting GPIO as input for generating root clock*/ +#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/* Interrupt handler for the battery voltage interrupt */ +void Battery_Voltage_Int_Handler(void); +/* Interrupt handler for the VREG under/over voltage interrupt */ +void Vreg_over_Int_Handler(void); +/* Interrupt handler for PLL interrupts. */ +void PLL_Int_Handler(void); +/*Interrupt handler for oscillator interrupts.*/ +void Crystal_osc_Int_Handler(void); + +#endif /* ADI_PWR_DEF_H */ + + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h new file mode 100755 index 00000000000..a9f0e37275a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/retarget_uart_config.h @@ -0,0 +1,27 @@ +/* +** I/O redirection support over UART, via SSL/DD. +** Copyright (C) 2017 Analog Devices, Inc. All Rights Reserved. +** +** This file is intended for use with the ARM:Compiler:IO:*:User +** components, which set up redirection of stdout and stderr. +*/ + +#ifndef RETARGET_UART_CONFIG_H +#define RETARGET_UART_CONFIG_H + +// --- <<< Use Configuration Wizard in Context Menu >>> --- + +// UART Configuration for STDOUT and STDERR + +// Configure Pinmuxing for UART. +// Enable pinmux configuration for UART on first output. +#define ADI_UART_SETUP_PINMUX 1 + +// Raise Breakpoint on exit() +// Cause a breakpoint event in exit() rather than looping forever. +#define ADI_UART_EXIT_BREAKPOINT 1 + + +// + +#endif /* RETARGET_UART_CONFIG_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c new file mode 100755 index 00000000000..75eb73a6cbd --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng.c @@ -0,0 +1,796 @@ +/*! + ***************************************************************************** + * @file: adi_rng.c + * @brief: Random Number Generator Driver + *---------------------------------------------------------------------------- + * +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/*! \addtogroup RNG_Driver RNG Driver + * Random Number Generator Driver + * @{ + */ + + /*! \cond PRIVATE */ + +#include /* for 'NULL' definition */ +#include + +#include +#include +#include "adi_rng_def.h" +#include + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ISR_PROLOG in no-OS case and others. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm143,Pm050 +#endif /* __ICCARM__ */ + +#ifdef __ADUCM4x50__ +#define NUM_RNG_DEVICES (1u) +#else +#error "Unsupported processor" +#endif + +/*============== D A T A ===============*/ + +/** + * Information for managing all the RNG devices available + */ +#ifdef __ICCARM__ +#pragma diag_suppress=Pm140 +#endif + +static ADI_RNG_DEV_TYPE gRNG_Device[NUM_RNG_DEVICES] = +{ + {(ADI_RNG_TypeDef*)pADI_RNG0,NULL} /* RNG0 */ +}; +#ifdef __ICCARM__ +#pragma diag_default=Pm140 +#endif + +/* Forward prototypes */ +void RNG_Int_Handler(void); + +/** Check the validity of a handle for debug mode */ +#ifdef ADI_DEBUG +#define ADI_RNG_INVALID_HANDLE(h) (&gRNG_Device[0] != (h)) +#endif + +/*! \endcond */ + +/*! + @brief Opena a Random Number Generator Device + + @param[in] nDeviceNum Device number to be opened. + @param[in] pMemory Pointer to the memory to be used by the driver. + Size of the memory should be at least #ADI_RNG_MEMORY_SIZE bytes. + @param[in] MemorySize Size of the memory passed in pMemory parameter. + @param[out] phDevice Pointer to a location in the calling function memory space to which + the device handle will be written upon successful driver initialization. + + @return Status + - #ADI_RNG_SUCCESS RNG device driver opened successfully. + - #ADI_RNG_INVALID_PARAM [D] The memory passed to the API is either NULL or its size is not sufficient. + - #ADI_RNG_ALREADY_INITIALIZED [D] The RNG is already initialized. + - #ADI_RNG_BAD_DEVICE_NUM [D] The device number is invalid. + + Initialize and allocate a RNG device for other use. The core NVIC RNG interrupt is enabled. This API + must preceed all other RNG API calls and the handle returned must be passed to all other RNG API calls. + + @note The contents of \a ppDevice will be set to NULL upon failure.\n\n + + @note The RNG device driver will clear all pending interrupts and disable all RNG + interrupts during RNG device initialization. + + @sa adi_rng_Close(). +*/ +ADI_RNG_RESULT adi_rng_Open( + uint32_t const nDeviceNum, + void* const pMemory, + uint32_t const MemorySize, + ADI_RNG_HANDLE* const phDevice + ) +{ + ADI_RNG_DEV_TYPE *pDevice; + + /* store a bad handle in case of failure */ + *phDevice = (ADI_RNG_HANDLE) NULL; + +#ifdef ADI_DEBUG + if (nDeviceNum >= NUM_RNG_DEVICES) + { + return ADI_RNG_BAD_DEVICE_NUM; + } + + if ((NULL == pMemory) || ( MemorySize < (uint32_t) ADI_RNG_MEMORY_SIZE)) + { + return ADI_RNG_INVALID_PARAM; + } + assert (ADI_RNG_MEMORY_SIZE == sizeof(ADI_RNG_DEV_DATA_TYPE)); +#endif + + /* local pointer to instance data */ + pDevice = &gRNG_Device[nDeviceNum]; + +#ifdef ADI_DEBUG + if (NULL != pDevice->pData) + { + return ADI_RNG_ALREADY_INITIALIZED; + } +#endif + + /* Set the internal device data */ + pDevice->pData = pMemory; + + /* initialize internal device data */ + pDevice->pData->IRQn = RNG0_EVT_IRQn; + pDevice->pData->CBFunc = NULL; + + /* clear any pending interrupts. Both bits are write 1 to clear */ + pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK; + + /* Set the RNG register based on static configuration */ + pDevice->pRNG->CTL = (uint16_t)RNG0_CFG_ONLY_8_BIT << BITP_RNG_CTL_SINGLE; + pDevice->pRNG->LEN = (RNG0_CFG_LENGTH_RELOAD << BITP_RNG_LEN_RELOAD) + | (RNG0_CFG_LENGTH_PRESCALER << BITP_RNG_LEN_PRESCALE); + + /* The interrupt handler only gets used in the case of callback mode so its + * enabling only happens in the adi_rng_RegisterCallBack API. + */ + NVIC_ClearPendingIRQ(pDevice->pData->IRQn); + + /* store handle at application handle pointer */ + *phDevice = pDevice; + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Uninitializes and deallocates the RNG device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * Uninitialize and release an allocated RNG device for other use. The core NVIC RNG interrupt is disabled. + * + * @sa adi_rng_Open(). + */ +ADI_RNG_RESULT adi_rng_Close(ADI_RNG_HANDLE hDevice) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ(pDevice->pData->IRQn); + pDevice->pData = NULL; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Enables/Disables the RNG device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] bFlag Flag to specify whether to enable or disable RNG device. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_Enable (ADI_RNG_HANDLE const hDevice, bool const bFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)) { + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { + pDevice->pRNG->CTL |= BITM_RNG_CTL_EN; + } else { + pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_EN); + } + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Enables/Disables Buffering for RNG. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] bFlag Flag to specify whether to enable or disable buffering for RNG device. + * When buffering is enabled, adi_rng_GetRngData returns 32-bit values. + * When buffering is disabled the API returns 8-bit values. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + * @sa adi_rng_GetRngData(). + */ +ADI_RNG_RESULT adi_rng_EnableBuffering (ADI_RNG_HANDLE const hDevice, bool const bFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)) { + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { + pDevice->pRNG->CTL &= (uint16_t)~(BITM_RNG_CTL_SINGLE); + } else { + pDevice->pRNG->CTL |= BITM_RNG_CTL_SINGLE; + } + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Sets the reload and prescale value for the sample counter. + * The Sample Length will be nLenReload*2^nLenPrescaler. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] nLenPrescaler Prescaler value for the sample counter (0-10). + * @param[in] nLenReload Reload value for the sample counter (0-4095) + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_SetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t const nLenPrescaler, + uint16_t const nLenReload + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ( (nLenPrescaler > 10u) + || ((0u == nLenPrescaler) && (0u == nLenReload)) + || (nLenReload > 4095u)) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + /* Set the sample reload and prescaler value */ + pDevice->pRNG->LEN = (uint16_t)((uint16_t)(nLenReload << BITP_RNG_LEN_RELOAD) & BITM_RNG_LEN_RELOAD) + | (uint16_t)((uint16_t)(nLenPrescaler << BITP_RNG_LEN_PRESCALE) & BITM_RNG_LEN_PRESCALE); + ADI_EXIT_CRITICAL_REGION(); + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieves the current state of RNG data/CRC accumulator register. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pbFlag Pointer to an application-defined boolean variable into which to write the result: + * - true = RNG data is ready to be read. + * - false = RNG data is not ready. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * Retrieve the current state of RNG data/CRC accumulator register. The register holds the final entropy value + * accumulated by RNG and it should to read only when the data is ready. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRngData(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetRdyStatus (ADI_RNG_HANDLE const hDevice, bool* const pbFlag) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pbFlag) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + /* Get the RNG Ready status bit */ + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) != 0u) + { + *pbFlag = true; + } + else + { + *pbFlag = false; + } + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve whether the RNG oscillator output is stuck at a constant value + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pbFlag Pointer to an application-defined boolean variable into which to write the result: + * - true = RNG oscillator is stuck at a constant value. + * - false = RNG oscillator is not stuck at a constant value. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRngData(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetStuckStatus ( + ADI_RNG_HANDLE const hDevice, + bool* const pbFlag + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (pDevice->pData == NULL) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pbFlag) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + /* Get the stuck status bit */ + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_STUCK) != 0u) + { + *pbFlag = true; + } + else + { + *pbFlag = false; + } + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieve the current value of the RNG data register. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] pRegData Pointer to an application-defined variable into which to write the result. + * Only lower 8-bit is valid if buffering is not enabled + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_PARAM [D] pRegData is a NULL pointer. + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + * + * Retrieve the current value of RNG data register. If the buffering is enabled all 32-bit of value written to + * pRegData is valid else only the lower 8-bit is valid. + * + * @sa adi_rng_Open(). + * @sa adi_rng_GetRdyStatus(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetRngData (ADI_RNG_HANDLE const hDevice, uint32_t* const pRegData) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pRegData) { + return ADI_RNG_INVALID_PARAM; + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the RNG CRC accumulator value */ + *pRegData = pDevice->pRNG->DATA; + + return ADI_RNG_SUCCESS; +} + + +/*! + * @brief Retrieve the current RNG Oscillator count. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] pOscCount Pointer to an application-defined variable into which to write the result. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetOscCount (ADI_RNG_HANDLE const hDevice, uint32_t* const pOscCount) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if (NULL == pOscCount) { + return (ADI_RNG_INVALID_PARAM); + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the oscillator count high count */ + *pOscCount = pDevice->pRNG->OSCCNT; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve the current RNG Oscillator difference value for the given index. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[in] nIndex Index of the difference register. + * @param[out] pOscDiff Pointer to an application-defined variable into which to + * write the oscillator difference value for the given index. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + * - #ADI_RNG_INVALID_STATE[D] Random number ready status is not set + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * @sa adi_rng_Open(). + * @sa adi_Rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetOscDiff ( + ADI_RNG_HANDLE const hDevice, + uint32_t const nIndex, + uint8_t* const pOscDiff + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ((NULL == pOscDiff) || (nIndex > 3u)) { + return( ADI_RNG_INVALID_PARAM ); + } + + if ((pDevice->pRNG->STAT & BITM_RNG_STAT_RNRDY) == 0u) { + return ADI_RNG_INVALID_STATE; + } +#endif + + /* Get the Osc Difference Register */ + *pOscDiff = (uint8_t)pDevice->pRNG->OSCDIFF[nIndex]; + + return ADI_RNG_SUCCESS; +} + +/*! + * @brief Retrieve the current RNG sample length prescale and reload value configured in the device. + * + * @param[in] hDevice Device handle obtained from adi_rng_Open(). + * @param[out] pLenPrescaler Pointer to an application-defined variable into which the prescaler value is written. + * @param[out] pLenReload Pointer to an application-defined variable into which the reload value for the sample counter is written. + * + * @return Status + * - #ADI_RNG_SUCCESS Call completed successfully. + * - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + * - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + - #ADI_RNG_INVALID_PARAM [D] Argument is incorrect. + * + * + * @sa adi_rng_Open(). + * @sa adi_rng_RegisterCallback(). + */ +ADI_RNG_RESULT adi_rng_GetSampleLen ( + ADI_RNG_HANDLE const hDevice, + uint16_t* const pLenPrescaler, + uint16_t* const pLenReload + ) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } + + if ((NULL == pLenPrescaler) || (NULL == pLenReload)) { + return ADI_RNG_INVALID_PARAM; + } +#endif + + *pLenPrescaler = (pDevice->pRNG->LEN & BITM_RNG_LEN_PRESCALE) >> BITP_RNG_LEN_PRESCALE; + *pLenReload = (pDevice->pRNG->LEN & BITM_RNG_LEN_RELOAD) >> BITP_RNG_LEN_RELOAD; + + return ADI_RNG_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +***************************************** CALLBACKS ****************************************** +***************************************** AND ****************************************** +***************************************** INTERRUPT ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + @brief RNG Application callback registration API. + + @param[in] hDevice Device handle obtained from #adi_rng_Open(). + @param[in] cbFunc Application callback address; the function to call on the interrupt. + @param[in] pCBParam Application handle to be passed in the call back. + + @return Status + - #ADI_RNG_SUCCESS The callback is successfully registered. + - #ADI_RNG_BAD_DEV_HANDLE [D] Invalid device handle parameter. + - #ADI_RNG_NOT_INITIALIZED [D] Device has not been initialized for use, see #adi_rng_Open(). + + Registers an application-defined callback \a cbFunc function address of type ADI_CALLBACK with the RNG device driver. + Callbacks are made in response to received RNG interrupts. + + The callback to the application is made in context of the originating interrupt (i.e., the RNG driver's + RNG interrupt handler that is registered in the system's interrupt vector table). Extended processing + during the callback (an extension of the RNG's interrupt handler) is discouraged so as to avoid lower-priority + interrupt blocking. Also, any register read-modify-write operations should be protected using the + ADI_ENTER_CRITICAL_REGION()/ADI_EXIT_CRITICAL_REGION() pair to prevent higher-priority interrupts from modifying + said register during the read-modify-write operation. + + @note CALLBACKS: RNG interrupt callbacks are \b disabled by default during RNG device driver + initialization (#adi_rng_Open()). The application uses the #adi_rng_RegisterCallback() + API to request an application-defined callback from the RNG device driver. The RNG device + driver clears the interrupt when the callback exits. + The application callback should avoid extended processing + during callbacks as the callback is executing context of the initiating interrupt and will + block lower-priority interrupts. If extended application-level interrupt processing is + required, the application should schedule it for the main application loop and exit the + callback as soon as possible.\n + + + @sa adi_rng_Open(). +*/ +ADI_RNG_RESULT adi_rng_RegisterCallback ( + ADI_RNG_HANDLE hDevice, + ADI_CALLBACK cbFunc, + void *pCBParam) +{ + ADI_RNG_DEV_TYPE *pDevice = (ADI_RNG_DEV_TYPE*)hDevice; + +#ifdef ADI_DEBUG + if (ADI_RNG_INVALID_HANDLE(pDevice)){ + return ADI_RNG_BAD_DEV_HANDLE; + } + + if (NULL == pDevice->pData) { + return ADI_RNG_NOT_INITIALIZED; + } +#endif + + /* save the callback info */ + pDevice->pData->CBFunc = cbFunc; + pDevice->pData->pCBParam = pCBParam; + + if (NULL != cbFunc) { + /* enable RNG interrupts in NVIC */ + NVIC_EnableIRQ(pDevice->pData->IRQn); + } else { + NVIC_DisableIRQ(pDevice->pData->IRQn); + } + + return ADI_RNG_SUCCESS; +} + +/*! \cond PRIVATE */ +/* RNG driver interrupt handler. Overrides weak default handler in startup file */ +void RNG_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_RNG_DEV_TYPE *pDevice = &gRNG_Device[0]; + register uint16_t candidate; + + /* if we have an initialized driver... */ + if (NULL != pDevice->pData) + { + /* if we have a registered callback */ + if (NULL != pDevice->pData->CBFunc) + { + ADI_INT_STATUS_ALLOC(); + + ADI_ENTER_CRITICAL_REGION(); + /* read status register without other interrupts in between */ + candidate = pDevice->pRNG->STAT; + ADI_EXIT_CRITICAL_REGION(); + + /* Only have bits in stat that are necessary */ + candidate = candidate & (BITM_RNG_STAT_STUCK | BITM_RNG_STAT_RNRDY); + + while (0u != candidate) { + uint32_t nEvent; + + if (0u != (candidate & BITM_RNG_STAT_RNRDY)) { + nEvent = ADI_RNG_EVENT_READY; + candidate &= (uint16_t)~BITM_RNG_STAT_RNRDY; + } else if (0u != (candidate & BITM_RNG_STAT_STUCK)) { + nEvent = ADI_RNG_EVENT_STUCK; + candidate &= (uint16_t)~BITM_RNG_STAT_STUCK; + } else { + break; + } + + pDevice->pData->CBFunc ( + pDevice->pData->pCBParam, + nEvent, + NULL + ); + } + + pDevice->pRNG->STAT = BITM_RNG_STAT_RNRDY | BITM_RNG_STAT_STUCK; + } + } + ISR_EPILOG(); +} +/*! \endcond */ + +/* +** EOF +*/ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h new file mode 100755 index 00000000000..462861d976a --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rng/adi_rng_def.h @@ -0,0 +1,69 @@ +/*! + ***************************************************************************** + * @file: adi_rng_def.h + * @brief: Random Number Generator Driver private data structures + *---------------------------------------------------------------------------- + * +Copyright (c) 2012-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_RNG_DEF_H +#define ADI_RNG_DEF_H + + /*! \cond PRIVATE */ + + +/*! RNG device internal instance data structure */ +typedef struct __ADI_RNG_DEV_DATA_TYPE +{ + IRQn_Type IRQn; /*!< RNG interrupt number */ + ADI_CALLBACK CBFunc; /*!< Callback function */ + void *pCBParam; /*!< Callback parameter */ +} ADI_RNG_DEV_DATA_TYPE; + +/*! RNG device internal data structure */ +typedef struct __ADI_RNG_DEV_TYPE +{ + volatile ADI_RNG_TypeDef *pRNG; /*!< MMR address for this RNG */ + ADI_RNG_DEV_DATA_TYPE *pData; /*!< Pointer to instance data */ +} ADI_RNG_DEV_TYPE; + + +/*! \endcond */ +#endif /* ADI_RNG_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c new file mode 100755 index 00000000000..f4b91d4adbb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc.c @@ -0,0 +1,2608 @@ +/*! + ***************************************************************************** + * @file: adi_rtc.c + * @brief: Real-Time Clock Device Implementations. + * @version: $Revision: 35155 $ + * @date: $Date: 2016-07-26 13:09:22 -0400 (Tue, 26 Jul 2016) $ + *---------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \addtogroup RTC_Driver RTC Driver + * @{ + * @brief Real Time Clock (RTC) Driver + * @details The RTC driver manages all instances of the RTC peripheral. + * @note The application must include drivers/rtc/adi_rtc.h to use this driver + */ + + +/*! \cond PRIVATE */ + + +#if defined ( __ADSPGCC__ ) +#define UNUSED __attribute__ ((unused)) +#else +#define UNUSED +#endif + +#include /* for 'NULL" definition */ +#include +#include +#include + + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm109 (rule 20.12): the time handling functions of library shall not be used +* Pm150 (rule 20.2): the names of standard library macros, objects and function shall not be reused +* Needed to implement the functions here. +* +* Pm129 (rule 12.7): bitwise operations shall not be performed on signed integer types +* The rule makes an exception for valid expressions. +* +* Pm029: this bitwise operation is in a boolean context - logical operators should not be confused with bitwise operators +* The rule is suppressed as the bitwise and logical operators are being used correctly and are not being confused +* +* Pm126: if the bitwise operators ~ and << are applied to an operand of underlying type 'unsigned char' or 'unsigned short', the result shall be immediately cast to the underlying type of the operand +* The behaviour as described is correct +* +* Pm031: bitwise operations shall not be performed on signed integer types +* Device drivers often require bit banging on MMRs that are defined as signed + +*/ +#pragma diag_suppress=Pm011,Pm123,Pm073,Pm143,Pm050,Pm109,Pm150,Pm140,Pm129,Pm029,Pm126,Pm031 +#endif /* __ICCARM__ */ +/*! \endcond */ + + +#include + + +/*! \cond PRIVATE */ + + +#include "adi_rtc_data.c" + + + + +/* Forward prototypes */ +void RTC0_Int_Handler(void); +void RTC1_Int_Handler(void); + + + +#ifdef ADI_DEBUG +static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice) +{ + /* Return code */ + ADI_RTC_RESULT nResult = ADI_RTC_INVALID_HANDLE; + uint32_t i; + for(i = 0u; i < ADI_RTC_NUM_INSTANCE; i++) + { + if(aRTCDeviceInfo[i].hDevice == pInDevice) + { + return(ADI_RTC_SUCCESS); + } + } + return (nResult); +} +#endif +/*! \endcond */ + +/*! + @brief RTC Initialization + + * @param[in] DeviceNumber The RTC device instance number to be opened. + * @param[in] pDeviceMemory The pointer to the device memory passed by application. + * @param[in] MemorySize The memory size passed by application. + * @param[out] phDevice The pointer to a location where the handle to the opened RTC device is written. + @return Status + - #ADI_RTC_SUCCESS RTC device driver initialized successfully. + - #ADI_RTC_INVALID_INSTANCE [D] The RTC instance number is invalid. + - #ADI_RTC_FAILURE General RTC initialization failure. + + The RTC controller interrupt enable state is unaltered during driver initialization. + Use the #adi_rtc_EnableInterrupts API to manage interrupting. + + @note The contents of phDevice will be set to NULL upon failure.\n\n + + @note On #ADI_RTC_SUCCESS the RTC device driver is initialized and made ready for use, + though pending interrupts may be latched. During initialization, the content of the + various RTC control, count, alarm and status registers are untouched to preserve prior + RTC initializations and operation. The core NVIC RTC interrupt is enabled.\n\n + + + @note SAFE WRITES: The "safe write" mode is enabled by default and can be changed using the macro + "ADI_RTC_CFG_ENABLE_SAFE_WRITE" defined in adi_rtc_config.h file. + + @sa adi_rtc_Enable(). + @sa adi_rtc_EnableInterrupts(). + @sa adi_rtc_SetCount(). + @sa adi_rtc_Close() +*/ +ADI_RTC_RESULT adi_rtc_Open( + uint32_t DeviceNumber, + void *pDeviceMemory, + uint32_t MemorySize, + ADI_RTC_HANDLE *phDevice + ) +{ + ADI_RTC_DEVICE *pDevice = pDeviceMemory; + + /* store a bad handle in case of failure */ + *phDevice = (ADI_RTC_HANDLE) NULL; + +#ifdef ADI_DEBUG + if ( DeviceNumber >= ADI_RTC_NUM_INSTANCE) + { + return ADI_RTC_INVALID_INSTANCE; + } + assert(ADI_RTC_MEMORY_SIZE == sizeof(ADI_RTC_DEVICE)); + if (aRTCDeviceInfo[DeviceNumber].hDevice != NULL) + { + return ADI_RTC_IN_USE; + } + if(MemorySize < ADI_RTC_MEMORY_SIZE) + { + return(ADI_RTC_FAILURE); + } +#endif + + memset(pDeviceMemory,0,MemorySize); + /* initialize device data entries */ + pDevice->pRTCRegs = aRTCDeviceInfo[DeviceNumber].pRTCRegs; + + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + pDevice->pRTCRegs->CR0 = 0u; + pDevice->pRTCRegs->CR1 = 0u; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0) + + pDevice->pRTCRegs->SR0 = ADI_RTC_SR3_IRQ_STATUS_MASK; + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCSR0) + + pDevice->pRTCRegs->CNT0 = 0u; + pDevice->pRTCRegs->CNT1 = 0u; + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCNT0) + + /* local pointer to instance data */ + aRTCDeviceInfo[DeviceNumber].hDevice = pDevice; + pDevice->pDeviceInfo = &aRTCDeviceInfo[DeviceNumber]; + + /* Use static configuration to initialize the RTC */ + rtc_init(pDevice,&aRTCConfig[DeviceNumber]); + + /* store handle at application handle pointer */ + *phDevice = pDevice; + pDevice->eIRQn = aRTCDeviceInfo[DeviceNumber].eIRQn; + /* Enable RTC interrupts in NVIC */ + NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn)); + + return ADI_RTC_SUCCESS; /* initialized */ +} + + +/*! + * @brief Uninitialize and deallocate an RTC device. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Uninitialize and release an allocated RTC device for other use. The core NVIC RTC interrupt is disabled. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_Close(ADI_RTC_HANDLE const hDevice) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* uninitialize */ + NVIC_DisableIRQ( pDevice->eIRQn); + + pDevice->pRTCRegs = NULL; + pDevice->pfCallback = NULL; + pDevice->pCBParam = NULL; + pDevice->cbWatch = 0u; + + pDevice->pDeviceInfo->hDevice = NULL; + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +**************************************** ENABLE APIS ******************************************* +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Enable RTC alarm. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag to enable/disable alarm logic. + * - true : Enable alarm logic. + * - false : Disable alarm logic. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable operation of RTC internal alarm logic. + * + * Alarm events and interrupt notifications are gated by enabling the alarm logic. + * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled + * to have been set. + * + * The alarm is relative to some future alarm value match against the RTC counter. + * + * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_GetCount(). + * @sa adi_rtc_SetAlarm(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_EnableAlarm(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC alarm enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_ALMEN; + } + else + { + pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_ALMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable MOD60 RTC alarm. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag for enable/disable mod60 alarm logic. + * - true : Enable mod60 alarm logic. + * - false : Disable mod60 alarm logic. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable operation of RTC internal MOD60 alarm logic. + * + * Alarm events and interrupt notifications are gated by enabling the alarm logic. + * RTC alarm interrupts require both RTC device and RTC alarm interrupt to be enabled + * to have been set. + * + * The alarm is relative to some future alarm value match against the RTC counter. + * + * @note The RTC device driver does not modify the alarm enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_GetCount(). + * @sa adi_rtc_SetAlarm(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_EnableMod60Alarm(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Mod-60 Alarm is present only in RTC-1 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC alarm enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_MOD60ALMEN; + } + else + { + pDevice->pRTCRegs->CR0 &= (uint16_t)(~BITM_RTC_CR0_MOD60ALMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable RTC device. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable boolean Flag for enabling/disabling the RTC device. + * - true : Enable RTC device. + * - false : Disable RTC device. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Global enable/disable of the RTC controller. Enables counting of elapsed real time and acts + * as a master enable for the RTC. + * + * @note When enabled, the RTC input clock pre-scaler and trim interval are realigned. + * + * @note The RTC device driver does not modify the device enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableAlarm(). + */ + +ADI_RTC_RESULT adi_rtc_Enable(ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear RTC device enable */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_CNTEN; + } + else + { + pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_CNTEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} + + +/* Data structures used to manage the enabling of all RTC interrupts */ +static uint16_t cr0 = 0u, cr1 = 0u, cr3oc = 0u, cr4oc = 0u, cr2ic = 0u, cr5ocs = 0u; + +static struct xxx +{ + uint16_t *cr; + uint16_t bitPositionl; +} +Interrupt_Details[ADI_RTC_NUM_INTERRUPTS] = +{ + { &cr0, BITP_RTC_CR0_ALMINTEN }, + { &cr0, BITP_RTC_CR0_MOD60ALMINTEN }, + { &cr0, BITP_RTC_CR0_ISOINTEN }, + { &cr0, BITP_RTC_CR0_WPNDERRINTEN }, + { &cr0, BITP_RTC_CR0_WSYNCINTEN }, + { &cr0, BITP_RTC_CR0_WPNDINTEN }, + { &cr1, BITP_RTC_CR1_CNTINTEN }, + { &cr1, BITP_RTC_CR1_PSINTEN }, + { &cr1, BITP_RTC_CR1_TRMINTEN }, + { &cr1, BITP_RTC_CR1_CNTROLLINTEN }, + { &cr1, BITP_RTC_CR1_CNTMOD60ROLLINTEN }, + { &cr3oc, BITP_RTC_CR3SS_SS1IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS2IRQEN }, + { &cr3oc, BITP_RTC_CR3SS_SS4IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC0IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC2IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC3IRQEN }, + { &cr2ic, BITP_RTC_CR2IC_IC4IRQEN }, + { &cr2ic, BITP_CLKG_OSC_CTL_LFX_FAIL_STA }, + { &cr3oc, BITM_RTC_CR3SS_SS4FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS3FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS2FEIRQEN}, + { &cr3oc, BITM_RTC_CR3SS_SS1FEIRQEN}, + { &cr4oc, BITP_RTC_CR4SS_SS4MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS3MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS2MSKEN}, + { &cr4oc, BITP_RTC_CR4SS_SS1MSKEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN}, + { &cr5ocs, BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN} + +}; + + +/*! + * @brief Manage interrupt enable/disable in the RTC and NVIC controller. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] Interrupts Conveys which interrupts are affected. + * @param[in] bEnable Flag which controls whether to enable or disable RTC interrupt. + * - true : Enable RTC interrupts. + * - false : Disable RTC interrupts. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable RTC interrupt as well as manage global NVIC enable/disable for the RTC. + * Input parameter \a Interrupts is a interrupt ID of type #ADI_RTC_INT_TYPE designating the + * interrupt to be enabled or disabled. The interrupt parameter may be zero, which will then simply + * manage the NVIC RTC enable and leave the individual RTC interrupt enables unchanged. + * Input parameter \a bEnable controls whether to enable or disable the designated set of interrupts. + * + * @note The RTC device driver does not modify the interrupt enables on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + */ +ADI_RTC_RESULT adi_rtc_EnableInterrupts (ADI_RTC_HANDLE const hDevice, ADI_RTC_INT_TYPE Interrupts, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + if( (pDevice->pRTCRegs == pADI_RTC0) &&(((uint16_t)((ADI_RTC_MOD60ALM_INT | ADI_RTC_ISO_DONE_INT| + ADI_RTC_COUNT_INT | + ADI_RTC_TRIM_INT | ADI_RTC_COUNT_ROLLOVER_INT | + ADI_RTC_MOD60_ROLLOVER_INT + )) & (uint16_t)Interrupts) != 0u)) + { + return(ADI_RTC_INVALID_PARAM); + } + + assert(sizeof(Interrupt_Details)/sizeof(Interrupt_Details[0]) == ADI_RTC_NUM_INTERRUPTS); +#endif + + /* TODO - more sync for new registers */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR) + + uint8_t ndx = 0u; + cr0 = 0u; cr1 = 0u; cr3oc = 0u; cr4oc = 0u; cr2ic = 0u; cr5ocs = 0u; + + while( Interrupts ) + { + if( 0u != (Interrupts & 1u) ) + { + uint16_t *cr = Interrupt_Details[ndx].cr; + uint16_t enableBitPosition = Interrupt_Details[ndx].bitPositionl; + *cr = *cr | (1u << enableBitPosition); + } + Interrupts >>= 1; + ndx++; + } + /* set/clear interrupt enable bit(s) in control register */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= cr0; + pDevice->pRTCRegs->CR1 |= cr1; + pDevice->pRTCRegs->CR3SS |= cr3oc; + pDevice->pRTCRegs->CR4SS |= cr4oc; + pDevice->pRTCRegs->CR2IC |= cr2ic; + pDevice->pRTCRegs->CR5SSS |= cr5ocs; + + } + else + { + pDevice->pRTCRegs->CR0 &= ~cr0; + pDevice->pRTCRegs->CR1 &= ~cr1; + pDevice->pRTCRegs->CR3SS &= ~cr3oc; + pDevice->pRTCRegs->CR4SS &= ~cr4oc; + pDevice->pRTCRegs->CR2IC &= ~cr2ic; + pDevice->pRTCRegs->CR5SSS &= ~cr5ocs; + } + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR) + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Enable RTC automatic clock trimming. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable Flag controlling RTC enabling trim. + * - true Enable RTC trimming. + * - false Disable RTC trimming. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Enable/disable automatic application of trim values to the main RTC clock. Allows application + * of periodic real-time RTC clock adjustments to correct for drift. Trim values are pre-calibrated + * and stored at manufacture. Trim values may be recalibrated by monitoring the RTC clock externally + * and computing/storing new trim values (see #adi_rtc_SetTrim). + * + * @note The trim interval is reset with device enable, #adi_rtc_Enable(). + * + * @note The RTC device driver does not modify the trim enable on the hardware except through use of this API. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_GetTrim(). + * @sa adi_rtc_SetTrim(). + */ +ADI_RTC_RESULT adi_rtc_EnableTrim (ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim enable bit(s) in control register */ + if (bEnable) + { + pDevice->pRTCRegs->CR0 |= BITM_RTC_CR0_TRMEN; + } + else + { + pDevice->pRTCRegs->CR0 &=(uint16_t)(~BITM_RTC_CR0_TRMEN); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable input capture for the specified channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInpChannel Specify input compare channel. + * @param[in] bEnable Flag for enabling RTC input capture for specified channel. + * - true Enable input capture. + * - false Disable input capture. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableInputCapture (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |=(uint16_t)eInpChannel; + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)(~(uint16_t)eInpChannel); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] bEnable Flag for enabling overwriting the unread snapshot. + * - true Enable overwrite snapshot. + * - false Disable overwrite of snapshot. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableOverwriteSnapshot (ADI_RTC_HANDLE const hDevice, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |= BITM_RTC_CR2IC_ICOWUSEN; + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)~BITM_RTC_CR2IC_ICOWUSEN; + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set input capture polarity for the specified channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInpChannel Specify which input capture channel. + * @param[in] bEnable Flag for selecting RTC input capture polarity. + * - false channel uses a *high-to-low* transition on its GPIO pin to signal an input capture event + * - true channel uses a *low-to-high* transition on its GPIO pin to signal an input capture event. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_SetInputCapturePolarity (ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eInpChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nInpChannel = (uint16_t)eInpChannel; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR2IC) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear trim input capture enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR2IC |= (uint16_t)(nInpChannel << BITP_RTC_CR2IC_IC0LH); + } + else + { + pDevice->pRTCRegs->CR2IC &= (uint16_t)~(nInpChannel << BITP_RTC_CR2IC_IC0LH); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR2IC) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable output for the specified Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Specify which Sensor Strobe channel. + * @param[in] bEnable Flag for enabling output for specified Sensor Strobe channel. + * - true Enable output. + * - false Disable output. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeOutput (ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR3SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear Sensor Strobe enable for specified channel*/ + if (bEnable) + { + pDevice->pRTCRegs->CR3SS |=(uint16_t)eSSChannel; + } + else + { + pDevice->pRTCRegs->CR3SS &= (uint16_t)(~(uint16_t)eSSChannel); + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR3SS) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Enable auto reload for given Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel number. + * @param[in] bEnable Flag to enable auto reload for given Sensor Strobe Channel. + * - true Enable auto reload. + * - false Disable auto reload. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableAutoReload(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDCR4SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear auto reload enable options */ + /* Note that channel 4 does not have this feature */ + if (bEnable) + { + switch( eSSChannel) + { + case ADI_RTC_SS_CHANNEL_1: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS1ARLEN; + break; + case ADI_RTC_SS_CHANNEL_2: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS2ARLEN; + break; + case ADI_RTC_SS_CHANNEL_3: + pDevice->pRTCRegs->CR4SS |= BITM_RTC_CR4SS_SS3ARLEN; + break; + default: + return ADI_RTC_FAILURE; + } + + } + else + { + switch( eSSChannel) + { + case ADI_RTC_SS_CHANNEL_1: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS1ARLEN; + break; + case ADI_RTC_SS_CHANNEL_2: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS2ARLEN; + break; + case ADI_RTC_SS_CHANNEL_3: + pDevice->pRTCRegs->CR4SS &= (uint16_t)~BITM_RTC_CR4SS_SS3ARLEN; + break; + default: + return ADI_RTC_FAILURE; + } + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set auto reload value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe channel for which auto reload to be set. + * @param[in] nValue Auto reload value to be set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * + */ +ADI_RTC_RESULT adi_rtc_SetAutoReloadValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + pDevice->pRTCRegs->SS1 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1) + break; + + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + pDevice->pRTCRegs->SS2 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2) + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + pDevice->pRTCRegs->SS3 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3) + break; + + case ADI_RTC_SS_CHANNEL_4: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + pDevice->pRTCRegs->SS4 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4) + break; + + default: + return ADI_RTC_FAILURE; + + } + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Enable or disable thermometer-code masking for the given Sensor Strobe Channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe channel for which thermometer-code masking to be enabled or disabled. + * @param[in] bEnable Flag to enable or disable masking for the given Sensor Strobe channel. + * - true Enable masking . + * - false Disable masking. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + */ +ADI_RTC_RESULT adi_rtc_EnableSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, bool bEnable) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDCR4SS) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* set/clear auto reload enable options */ + if (bEnable) + { + pDevice->pRTCRegs->CR4SS |= (uint16_t)eSSChannel; + } + else + { + pDevice->pRTCRegs->CR4SS &= (uint16_t)~(uint16_t)eSSChannel; + } + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCCR4SS) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief To set channel mask for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel for which the mask to be set. + * @param[in] nMask Channel Mask to be set for Sensor Strobe channel. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_CHANNEL The given channel is invalid. + */ +ADI_RTC_RESULT adi_rtc_SetSensorStrobeChannelMask(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint8_t nMask) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t MaskPos = 0u; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS1MSK; + break; + + case ADI_RTC_SS_CHANNEL_2: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS2MSK; + break; + + case ADI_RTC_SS_CHANNEL_3: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS3MSK; + break; + + case ADI_RTC_SS_CHANNEL_4: + MaskPos = (uint16_t)BITP_RTC_SSMSK_SS4MSK; + break; + + default: + return ADI_RTC_INVALID_CHANNEL; + } + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5, BITM_RTC_SR5_WPENDSSMSK) + + pDevice->pRTCRegs->SSMSK = ((uint16_t)nMask & 0xFu) << MaskPos; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4, BITM_RTC_SR4_WSYNCSSMSK) + + return ADI_RTC_SUCCESS; +} + +/************************************************************************************************* +************************************************************************************************** +****************************************** GET APIS ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Get current RTC alarm value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pAlarm Pointer to application memory where the alarm value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetAlarm(). + */ +ADI_RTC_RESULT adi_rtc_GetAlarm (ADI_RTC_HANDLE hDevice, uint32_t *pAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nAlarm =(uint32_t) pDevice->pRTCRegs->ALM1 << 16u; + nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0; + NVIC_EnableIRQ((IRQn_Type)(pDevice->eIRQn)); + + *pAlarm = nAlarm; + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC alarm value with fractional part also. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pAlarm Pointer to application memory where the alarm value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 32-bit RTC alarm value and write it to the address provided by parameter \a pAlarm. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetAlarm(). + */ +ADI_RTC_RESULT adi_rtc_GetAlarmEx (ADI_RTC_HANDLE hDevice, float *pAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm,nTemp; + uint16_t nPreScale; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nAlarm = (uint32_t)pDevice->pRTCRegs->ALM1 << 16u; + nAlarm |= (uint32_t)pDevice->pRTCRegs->ALM0; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + nTemp = 1lu<pRTCRegs->ALM2 /(float)(nTemp); + + *pAlarm = (float)nAlarm+fFraction; + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC control register value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eRegister Specify which register content need to be returned. + * + * @param[out] pControl Pointer to application memory where the control register value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the currently programmed 16-bit RTC control register value and write it to the address provided by parameter \a pControl. + * + * @sa adi_rtc_Open(). + * @sa adi_rtcSetControl(). + */ +ADI_RTC_RESULT adi_rtc_GetControl (ADI_RTC_HANDLE hDevice, ADI_RTC_CONTROL_REGISTER eRegister ,uint32_t *pControl) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + switch(eRegister) + { + case ADI_RTC_CONTROL_REGISTER_0: + *pControl = pDevice->pRTCRegs->CR0; + break; + case ADI_RTC_CONTROL_REGISTER_1: + *pControl = pDevice->pRTCRegs->CR1; + break; + default: + return(ADI_RTC_FAILURE); + } + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC count value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pCount Pointer to application memory where the count value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCount(ADI_RTC_HANDLE const hDevice, uint32_t *pCount) +{ + uint32_t nCount; + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + *pCount = nCount; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC count value with fraction. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pfCount Pointer to application memory where the count(with fraction) value is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count value and write it to the address provided by parameter \a pCount. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCountEx(ADI_RTC_HANDLE const hDevice, float *pfCount) +{ + uint32_t nCount,nTemp; + uint16_t nPrescale; + ADI_RTC_DEVICE *pDevice = hDevice; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + nPrescale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + nTemp = (1lu<pRTCRegs->CNT2/(float)(nTemp); + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + *pfCount = (float)nCount+ fFraction; + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get current RTC count value of all registers. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pnCount Pointer to application memory where the count's 32 MSB are written. + * @param[out] pfCount Pointer to application memory where the count's 16 LSB are written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 32-bit RTC count integer value and fractional value in the integer format. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetCountRegs(ADI_RTC_HANDLE const hDevice, uint32_t *pnCount, uint32_t *pfCount) +{ + uint32_t nCount; + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->CNT1 << 16u; + nCount |= pDevice->pRTCRegs->CNT0; + *pnCount= nCount; + *pfCount = (uint32_t)pDevice->pRTCRegs->CNT2; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + return ADI_RTC_SUCCESS; +} + + + +/*! + * @brief Get current RTC clock trim value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] peTrim Pointer to #ADI_RTC_TRIM_VALUE where the trim value is to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * Read the current 16-bit RTC trim value and write it to the address provided by parameter \a pTrim. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableInterrupts(). + * @sa adi_rtc_EnableTrim(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_GetWriteSyncStatus(). + * @sa adi_rtc_SetTrim(). + */ +ADI_RTC_RESULT adi_rtc_GetTrim (ADI_RTC_HANDLE hDevice, ADI_RTC_TRIM_VALUE *peTrim) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + if(peTrim == NULL) + { + return( ADI_RTC_INVALID_PARAM); + } +#endif + + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM); + + *peTrim =(ADI_RTC_TRIM_VALUE)(pDevice->pRTCRegs->TRM & BITM_RTC_TRM_VALUE); + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Get Sensor Strobe value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel whose value to be read. + * @param[out] pValue Pointer to application memory where the Sensor Strobe value to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t *pValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + *pValue = pDevice->pRTCRegs->SS1; + break; + + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + *pValue = pDevice->pRTCRegs->SS2; + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + *pValue = pDevice->pRTCRegs->SS3; + break; + + case ADI_RTC_SS_CHANNEL_4: + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + *pValue = pDevice->pRTCRegs->SS4; + break; + + default: + return ADI_RTC_FAILURE; + } + + + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set Sensor Strobe value for the given Sensor Strobe channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eSSChannel Sensor Strobe Channel. + * @param[out] nValue Sensor Strobe value to be set for the given Sensor Strobe channel . + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_SetSensorStrobeValue(ADI_RTC_HANDLE const hDevice, ADI_RTC_SS_CHANNEL eSSChannel, uint16_t nValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + switch( eSSChannel ) + { + case ADI_RTC_SS_CHANNEL_1: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS1) + pDevice->pRTCRegs->SS1 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS1) + break; + + case ADI_RTC_SS_CHANNEL_2: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS2) + pDevice->pRTCRegs->SS2 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS2) + break; + + case ADI_RTC_SS_CHANNEL_3: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS3) + pDevice->pRTCRegs->SS3 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS3) + break; + + case ADI_RTC_SS_CHANNEL_4: + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR5,BITM_RTC_SR5_WPENDSS4) + pDevice->pRTCRegs->SS4 = nValue; + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR4,BITM_RTC_SR4_WSYNCSS4) + break; + + default: + return ADI_RTC_FAILURE; + } + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Get input capture value for specified input channel. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eChannel Specify which input capture channel. + * @param[out] pValue Pointer to application memory where the input capture value to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * - #ADI_RTC_INVALID_CHANNEL [D] Input channel-0 is not valid for this operation since + * channel-0 can provide precise (47bit) capture value. + * + * + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetInputCaptureValue(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint16_t *pValue) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS; + +#ifdef ADI_DEBUG + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + switch(eChannel) + { + case ADI_RTC_INPUT_CHANNEL_2: + *pValue = pDevice->pRTCRegs->IC2; + break; + case ADI_RTC_INPUT_CHANNEL_3: + *pValue = pDevice->pRTCRegs->IC3; + break; + + case ADI_RTC_INPUT_CHANNEL_4: + *pValue = pDevice->pRTCRegs->IC4; + break; + default: + eResult = ADI_RTC_INVALID_CHANNEL; + break; + } + return(eResult); +} +/*! + * @brief Get snapshot of the value of RTC . + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eChannel Specify input channel from which captured value to be obtained. + * @param[in] pFraction Pointer to application memory where the fractional part of snap shot value to be written. + * @param[out] pValue Pointer to application memory where the snap shot value of RTC to be written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_Enable(). + * @sa adi_rtc_SetCount(). + */ +ADI_RTC_RESULT adi_rtc_GetSnapShot(ADI_RTC_HANDLE const hDevice,ADI_RTC_INPUT_CHANNEL eChannel, uint32_t *pValue, uint16_t *pFraction) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + ADI_RTC_RESULT eResult= ADI_RTC_SUCCESS; + uint32_t nCount = 0u; +#ifdef ADI_DEBUG + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* disable interrupts during paired read */ + NVIC_DisableIRQ(pDevice->eIRQn); + nCount = (uint32_t)pDevice->pRTCRegs->SNAP1 << 16u; + nCount |= pDevice->pRTCRegs->SNAP0; + *pFraction = pDevice->pRTCRegs->SNAP2; + *pValue = nCount; + NVIC_EnableIRQ((IRQn_Type)pDevice->eIRQn); + return(eResult); +} + + +/*! + * @brief Get current RTC posted write pending status. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pPendBits Pointer to application memory where the posted write status is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller + * clock is running at a much slower (32kHz) rate than the core processor clock. So each RTC write register has a + * one-deep FIFO to hold write values until the RTC can effect them. This gives rise to the notion of a \a pending + * \a write state: if a write is already pending and another write from the core comes along before the first (pending) + * write has cleared to its destination register, the second write may be lost because the FIFO is full already. + * + * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the configuration switch + * ADI_RTC_CFG_ENABLE_SAFE_WRITE. Enabeling safe writes (on be default) insures write data is never lost by + * detecting and pausing on pending writes prior writing new data. The penalty in using safe writes is the stall + * overhead in execution (which is not incurred if there is nothing pending). Additionally, \a all pending writes + * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all + * pending RTC writes have completed. + * + * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus()) + * status is that the \a pend state is normally clear and is set only while no room remains in a register's write FIFO, + * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent. + * + * Each write error + * source may be configured to interrupt the core by enabling the appropriate + * write error interrupt mask bit in the RTC control register (see the + * #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt handler + * will be dispatched. + * + * @sa adi_rtc_Open(). + * @sa #adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetWriteSyncStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_GetWritePendStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pPendBits) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nPendBits; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* get the value */ + nPendBits = pDevice->pRTCRegs->SR1 & ADI_RTC_WRITE_STATUS_MASK; + *pPendBits = (ADI_RTC_WRITE_STATUS)nPendBits; + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Get current RTC posted write synchronization status. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[out] pSyncBits Pointer to application memory where the posted write status is written. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] NULL pointer for input parameter. + * + * + * \b Pending \b Writes: Register writes to internal RTC registers take time to complete because the RTC controller + * clock is running at a much slower (32kHz) rate than the core processor clock. So each RTC write register has a + * one-deep FIFO to hold write values until the RTC can effect them. This gives rise to the notion of a \a pending + * \a write state: if a write is already pending and another write from the core comes along before the first (pending) + * write has cleared to its destination register, the second write may be lost because the FIFO is full already. + * + * To avoid data loss, the user may tell the RTC device driver to enforce safe writes with the + * #ADI_RTC_CFG_ENABLE_SAFE_WRITE switch. Enabling safe writes (on be default) insures write data is never lost by + * detecting and pausing on pending writes prior writing new data. The penalty in using safe writes is the stall + * overhead in execution (which is not incurred if there is nothing pending). Additionally, \a all pending writes + * may also be synchronized manually with the #adi_rtc_SynchronizeAllWrites() API, which will pause until all + * pending RTC writes have completed. + * + * The distinction between "pend" status (#adi_rtc_GetWritePendStatus()) and "sync" (#adi_rtc_GetWriteSyncStatus()) + * status is that the \a pend state is normally clear is set only while no room remains in a register's write FIFO, + * whereas \a sync state is normally set and is clear only while the effects of the write are not yet apparent. + * + * Each write error source may be configured to interrupt the core by enabling + * the appropriate write error interrupt mask bit in the RTC control register + * (see the #adi_rtc_EnableInterrupts() API), at which time, the RTC interrupt + * handler will be dispatched. + * + * @sa adi_rtc_Open(). + * @sa #adi_rtc_EnableInterrupts(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtcStallOnPendingWrites(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_GetWriteSyncStatus (ADI_RTC_HANDLE const hDevice, ADI_RTC_WRITE_STATUS *pSyncBits) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nSyncBits; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to couunt Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDSR0); + + /* get the value */ + nSyncBits = pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK; + *pSyncBits = (ADI_RTC_WRITE_STATUS)nSyncBits; + + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +****************************************** SET APIS ****************************************** +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Set a new RTC alarm value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nAlarm New alarm value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetAlarm (ADI_RTC_HANDLE const hDevice, uint32_t nAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + + /* Wait till previously posted write to Alram Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + pDevice->pRTCRegs->ALM2 = 0u; + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set Prescale. This is power of 2 division factor for the RTC base clock. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nPreScale Prescale value to be set. if "nPreScale" is 5, RTC base clock is + divided by 32. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetPreScale(ADI_RTC_HANDLE const hDevice, uint8_t nPreScale ) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nTemp; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Pre scale is invalid for RTC0 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } +#endif + PEND_BEFORE_WRITE(SR2,BITM_RTC_SR2_WPNDCR1MIR) + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + nTemp = pDevice->pRTCRegs->CR1 & (uint16_t)~BITM_RTC_CR1_PRESCALE2EXP; + nTemp |= (uint16_t)((uint16_t)nPreScale << BITP_RTC_CR1_PRESCALE2EXP); + pDevice->pRTCRegs->CR1 = nTemp; + ADI_EXIT_CRITICAL_REGION(); + + SYNC_AFTER_WRITE(SR2,BITM_RTC_SR2_WSYNCCR1MIR) + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set the pre-scale. This is power of 2 division factor for the RTC base clock. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nPeriod Periodic, modulo-60 alarm time in pre-scaled RTC time units beyond a modulo-60 boundary. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @note This API helps the CPU to position a periodic (repeating) alarm interrupt from the RTC at any integer number of pre-scaled RTC time units from a modulo-60 boundary (roll-over event) of the value of count. + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetMod60AlarmPeriod(ADI_RTC_HANDLE const hDevice, uint8_t nPeriod ) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint16_t nTemp; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + + /* Mod60 Alarm is valid only in RTC-1 */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + nTemp = pDevice->pRTCRegs->CR0 & BITM_RTC_CR0_MOD60ALM; + nTemp |= (uint16_t)((uint16_t)nPeriod << BITP_RTC_CR0_MOD60ALM); + pDevice->pRTCRegs->CR0 = nTemp; + ADI_EXIT_CRITICAL_REGION(); + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; +} +/*! + * @brief Set a new RTC alarm value with fractional value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] fAlarm New alarm value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 32-bit RTC alarm comparator with the value provided by \a Alarm. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetAlarm(). + * @sa adi_rtc_EnableAlarm(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetAlarmEx(ADI_RTC_HANDLE const hDevice, float fAlarm) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t nAlarm = (uint32_t)fAlarm,nTemp; + uint16_t nPreScale; + float fFraction; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + /* Only 1Hz clocking is supported in RTC-0.So no fractional Alarm. */ + if(pDevice->pRTCRegs == pADI_RTC0) + { + return(ADI_RTC_OPERATION_NOT_ALLOWED); + } + +#endif + + /* Wait till previously posted write to Alarm Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDALM0|BITM_RTC_SR1_WPNDALM1)) + nPreScale = (pDevice->pRTCRegs->CR1&BITM_RTC_CR1_PRESCALE2EXP)>>BITP_RTC_CR1_PRESCALE2EXP; + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + /* format is Alarm1(16-32) Alarm0(0-16).Alarm2(fraction)*/ + pDevice->pRTCRegs->ALM0 = (uint16_t)nAlarm; + pDevice->pRTCRegs->ALM1 = (uint16_t)(nAlarm >> 16); + nTemp = 1lu<pRTCRegs->ALM2 = (uint16_t)(fFraction); + ADI_EXIT_CRITICAL_REGION(); + /* Wait till write to Alarm Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCALM0|BITM_RTC_SR0_WSYNCALM1)) + + return ADI_RTC_SUCCESS; +} + +/*! + * @brief Set a new RTC control register value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eRegister Specify which register need to be initialized. + * @param[in] Control New control register value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 16-bit RTC control register with the value provided by \a Control. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetControlRegister(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetControlRegister(ADI_RTC_HANDLE const hDevice,ADI_RTC_CONTROL_REGISTER eRegister, uint32_t Control) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDCR0) + + switch(eRegister) + { + case ADI_RTC_CONTROL_REGISTER_0: + pDevice->pRTCRegs->CR0 = (uint16_t)Control; + break; + case ADI_RTC_CONTROL_REGISTER_1: + pDevice->pRTCRegs->CR1 = (uint16_t)Control; + break; + default: + return(ADI_RTC_FAILURE); + } + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCCR0) + + return ADI_RTC_SUCCESS; + +} + +/*! + * @brief Registers a Callback function with the RTC device driver. The registered call + * back function will be called when an event is detected. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param [in] pfCallback Function pointer to Callback function. Passing a NULL pointer will + * unregister the call back function. + * + * @param [in] pCBparam Call back function parameter. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_RegisterCallback( + ADI_RTC_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void *const pCBparam + ) + +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + while((pDevice->pRTCRegs->SR1 & (uint32_t)ADI_RTC_WRITE_STATUS_CONTROL0)!=0u) + { + } +#endif + /* Store the address of the callback function */ + pDevice->pfCallback = pfCallback; + /* Store the call back parameter */ + pDevice->pCBParam = pCBparam; + + return ADI_RTC_SUCCESS; + +} + +/*! + * @brief Set a new RTC count value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] nCount New count value to set. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the main 32-bit RTC counter with the value provided by \a Count. + * + * Honours the safe write mode if set. Otherwise, it is the application's responsibility to + * synchronize any multiple writes to the same register. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_SetCount(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_SynchronizeAllWrites(). + */ +ADI_RTC_RESULT adi_rtc_SetCount (ADI_RTC_HANDLE const hDevice, uint32_t nCount) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + while((pDevice->pRTCRegs->SR1 & (uint32_t)(ADI_RTC_WRITE_STATUS_COUNT0 | ADI_RTC_WRITE_STATUS_COUNT1)) !=0u) + { + + } +#endif + + /* Wait till previously posted write to count Register to complete */ + PEND_BEFORE_WRITE(SR1,(BITM_RTC_SR1_WPNDCNT0|BITM_RTC_SR1_WPNDCNT1)) + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + /* RTC hardware insures paired write, so no need to disable interrupts */ + pDevice->pRTCRegs->CNT0 = (uint16_t)nCount; + pDevice->pRTCRegs->CNT1 = (uint16_t)(nCount >> 16); + ADI_EXIT_CRITICAL_REGION(); + + /* Wait till write to count Register to take effect */ + SYNC_AFTER_WRITE(SR0,(BITM_RTC_SR0_WSYNCCNT0|BITM_RTC_SR0_WSYNCCNT1)) + + return ADI_RTC_SUCCESS; +} + + +/*! + * @brief Set an RTC gateway command. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] Command Gateway command value. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Writes the 16-bit RTC gateway register with the command provided by \a Command. + * + * The gateway register is used to force the RTC to perform some urgent action. + * + * Currently, only the #ADI_RTC_GATEWAY_FLUSH command is defined, which will cancel all + * RTC register write transactions, both pending and executing. It is intended to truncate + * all core interactions in preparation for an imminent power loss when the RTC power + * isolation barrier will be activated. + * + * @sa adi_rtc_Open(). + */ +ADI_RTC_RESULT adi_rtc_SetGateway(ADI_RTC_HANDLE const hDevice, uint16_t Command) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } +#endif + /* set the command */ + pDevice->pRTCRegs->GWY = Command; + return ADI_RTC_SUCCESS; +} + + + +/*! + * @brief Set a new RTC trim value. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * @param[in] eInterval Specify the trimming interval and will always in the range of (2^2 to S^17 pre-scaled RTC clock ). + * @param[in] eTrimValue Specify the trimming value. + * @param[in] eOperation Specify the operation(Add or subtract) need to be performed for trimming. + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_RTC_INVALID_PARAM [D] Input parameter out of range. + * + * The RTC hardware has the ability to automatically trim the clock to compensate for variations + * in oscillator tolerance . Automatic trimming is enabled with the #adi_rtc_EnableTrim() API. + * + * @note Alarms are not affected by automatic trim operations. + * + * @note The trim boundary (interval) alignment is reset when new trim values are written. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_EnableTrim(). + * @sa adi_rtc_GetTrim(). + */ +ADI_RTC_RESULT adi_rtc_SetTrim(ADI_RTC_HANDLE const hDevice, ADI_RTC_TRIM_INTERVAL eInterval, ADI_RTC_TRIM_VALUE eTrimValue, ADI_RTC_TRIM_POLARITY eOperation) +{ + ADI_RTC_DEVICE *pDevice = hDevice; + uint32_t trm = (uint32_t)eInterval | (uint32_t)eTrimValue | (uint32_t)eOperation; + +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + +#endif + + /* Wait till previously posted write to Control Register to complete */ + PEND_BEFORE_WRITE(SR1,BITM_RTC_SR1_WPNDTRM) + + pDevice->pRTCRegs->TRM = (uint16_t)trm; + + /* Wait till write to Control Register to take effect */ + SYNC_AFTER_WRITE(SR0,BITM_RTC_SR0_WSYNCTRM) + + return ADI_RTC_SUCCESS; +} + + +/************************************************************************************************* +************************************************************************************************** +************************************ SYNCHRONIZATION API ************************************* +************************************************************************************************** +*************************************************************************************************/ + + +/*! + * @brief Force synchronization of all pending writes. + * + * @param[in] hDevice Device handle obtained from adi_rtc_Open(). + * + * @return Status + * - #ADI_RTC_SUCCESS Call completed successfully. + * - #ADI_RTC_INVALID_HANDLE [D] Invalid device handle parameter. + * + * Blocking call to coerce all outstanding posted RTC register writes to fully flush and synchronize. + * + * @sa adi_rtc_Open(). + * @sa adi_rtc_GetWritePendStatus(). + * @sa adi_rtc_GetWriteSyncStatus(). +*/ +ADI_RTC_RESULT adi_rtc_SynchronizeAllWrites (ADI_RTC_HANDLE const hDevice) +{ + ADI_RTC_DEVICE *pDevice = hDevice; +#ifdef ADI_DEBUG + ADI_RTC_RESULT eResult; + if((eResult = ValidateHandle(pDevice)) != ADI_RTC_SUCCESS) + { + return eResult; + } + +#endif + + /* forced block until all SYNC bits are set (ignore bSafe) */ + while (ADI_RTC_WRITE_STATUS_MASK != (pDevice->pRTCRegs->SR0 & ADI_RTC_WRITE_STATUS_MASK)) + { + + } + + return ADI_RTC_SUCCESS; +} + + +/*! \cond PRIVATE */ + +/* + * @brief Initializes the device using static configuration + * + * @param[in] pDevice Pointer to RTC device . + pConfig Pointer to static configuration device structure. + * +*/ + +static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig) +{ + + /* FIXME - static init is even more now */ + + /* Control register -0 which controls all main stream activity of RTC0 */ + pDevice->pRTCRegs->CR0 = pConfig->CR0; + /* Control register -1 which is granularity of RTC control register */ + pDevice->pRTCRegs->CR1 = pConfig->CR1; + /*CNT0 contains the lower 16 bits of the RTC counter */ + pDevice->pRTCRegs->CNT0 = pConfig->CNT0; + /*CNT1 contains the lower 16 bits of the RTC counter */ + pDevice->pRTCRegs->CNT1 = pConfig->CNT1; + /* ALM0 contains the lower 16 bits of the Alarm register */ + pDevice->pRTCRegs->ALM0 = pConfig->ALM0; + /* ALM1 contains the upper 16 bits of the Alarm register */ + pDevice->pRTCRegs->ALM1 = pConfig->ALM1; + /* ALM1 contains the fractional part of the Alarm register */ + pDevice->pRTCRegs->ALM2 = pConfig->ALM2; + /* Set Input capture/sensor strobe registers only for RTC1 */ + if(pDevice->pRTCRegs == pADI_RTC1) + { + pDevice->pRTCRegs->CR2IC = pConfig->CR2IC; + pDevice->pRTCRegs->CR3SS = pConfig->CR3SS; + pDevice->pRTCRegs->CR4SS = pConfig->CR4SS; + pDevice->pRTCRegs->SSMSK = pConfig->SSMSK; + pDevice->pRTCRegs->SS1 = pConfig->SS1; + pDevice->pRTCRegs->CR5SSS = pConfig->CR5SSS; + pDevice->pRTCRegs->CR6SSS = pConfig->CR6SSS; + pDevice->pRTCRegs->CR7SSS = pConfig->CR7SSS; + pDevice->pRTCRegs->GPMUX0 = pConfig->GPMUX0; + pDevice->pRTCRegs->GPMUX1 = pConfig->GPMUX1; + } +} + + + +/*! @brief RTC device driver interrupt handler. Overrides weakly-bound default interrupt handler in _startup.c. */ +void RTC0_Int_Handler(void) +{ + ISR_PROLOG(); + uint16_t nIntSrc0, nIntSrc2, nIntSrc3; + uint32_t fired = 0u, enables = 0u; + ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[0].hDevice; + + /* determine qualified interrupt source(s) */ + /* need to test each interrupt source and whether it is enabled before notifying */ + /* because each source is latched regardless of whether it is enabled or not :-( */ + + /* CR0 SR0 */ + enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0; + nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0; + if( nIntSrc0 && enables ) + { + if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT)) + { + fired |= ADI_RTC_MOD60ALM_INT; + } + if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT)) + { + fired |= ADI_RTC_ALARM_INT; + } + if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT)) + { + fired |= ADI_RTC_ISO_DONE_INT; + } + if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT)) + { + fired |= ADI_RTC_WRITE_PEND_INT; + } + if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT)) + { + fired |= ADI_RTC_WRITE_SYNC_INT; + } + if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT)) + { + fired |= ADI_RTC_WRITE_PENDERR_INT; + } + } + + /* CR1 SR2 */ + enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1; + nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2; + if( nIntSrc2 && enables ) + { + if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT)) + { + fired |= ADI_RTC_MOD60_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT)) + { + fired |= ADI_RTC_COUNT_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT)) + { + fired |= ADI_RTC_TRIM_INT; + } + if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT)) + { + fired |= ADI_RTC_PSI_INT; + } + if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT)) + { + fired |= ADI_RTC_COUNT_INT; + } + } + + /* CR3OC, CR2IC SR3*/ + enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR3SS; + nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH4_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH3_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH2_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH1_INT; + } + + if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ)) + { + fired |= ADI_RTC_RTCSS4_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ)) + { + fired |= ADI_RTC_RTCSS3_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ)) + { + fired |= ADI_RTC_RTCSS2_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ)) + { + fired |= ADI_RTC_RTCSS1_FE_INT; + } + } + enables = pDevice->pRTCRegs->CR3SS & (uint16_t)ADI_RTC_INT_ENA_MASK_CR2IC; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT; + } + if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT; + } + if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT; + } + if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT; + } + } + + + if (pDevice->pfCallback != NULL) { + + /* forward to the user if he is watching this interrupt */ + /* pass the "fired" value as the event. argument param is not used */ + if ( fired) + { + pDevice->pfCallback (pDevice->pCBParam, fired, NULL); + } + } + + /* Write 1 to clear the interrupts */ + pDevice->pRTCRegs->SR0 |= nIntSrc0; + pDevice->pRTCRegs->SR2 |= nIntSrc2; + pDevice->pRTCRegs->SR3 |= nIntSrc3; + ISR_EPILOG(); +} + +/*! @brief RTC device driver interrupt handler. Overrides weakly-bound default interrupt handler in _startup.c. */ +void RTC1_Int_Handler(void) +{ + ISR_PROLOG(); + uint16_t nIntSrc0, nIntSrc2, nIntSrc3; + uint32_t fired = 0u, enables = 0u; + ADI_RTC_DEVICE *pDevice = aRTCDeviceInfo[1].hDevice; + + /* determine qualified interrupt source(s) */ + /* need to test each interrupt source and whether it is enabled before notifying */ + /* because each source is latched regardless of whether it is enabled or not :-( */ + + /* CR0 SR0 */ + enables = (uint32_t)pDevice->pRTCRegs->CR0 & ADI_RTC_INT_ENA_MASK_CR0; + nIntSrc0 = pDevice->pRTCRegs->SR0 & ADI_RTC_INT_SOURCE_MASK_SR0; + if( nIntSrc0 && enables ) + { + if( (enables & BITM_RTC_CR0_MOD60ALMEN) && (nIntSrc0 & BITM_RTC_SR0_MOD60ALMINT)) + { + fired |= ADI_RTC_MOD60ALM_INT; + } + if( (enables & BITM_RTC_CR0_ALMINTEN) && (nIntSrc0 & BITM_RTC_SR0_ALMINT)) + { + fired |= ADI_RTC_ALARM_INT; + } + if( (enables & BITM_RTC_CR0_ISOINTEN) && (nIntSrc0 & BITM_RTC_SR0_ISOINT)) + { + fired |= ADI_RTC_ISO_DONE_INT; + } + if( (enables & BITM_RTC_CR0_WPNDINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDINT)) + { + fired |= ADI_RTC_WRITE_PEND_INT; + } + if( (enables & BITM_RTC_CR0_WSYNCINTEN) && (nIntSrc0 & BITM_RTC_SR0_WSYNCINT)) + { + fired |= ADI_RTC_WRITE_SYNC_INT; + } + if( (enables & BITM_RTC_CR0_WPNDERRINTEN) && (nIntSrc0 & BITM_RTC_SR0_WPNDERRINT)) + { + fired |= ADI_RTC_WRITE_PENDERR_INT; + } + } + + /* CR1 SR2 */ + enables = (uint32_t)pDevice->pRTCRegs->CR1 & ADI_RTC_INT_ENA_MASK_CR1; + nIntSrc2 = pDevice->pRTCRegs->SR2 & ADI_RTC_INT_SOURCE_MASK_SR2; + if( nIntSrc2 && enables ) + { + if( (enables & BITM_RTC_CR1_CNTMOD60ROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTMOD60ROLLINT)) + { + fired |= ADI_RTC_MOD60_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_CNTROLLINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTROLLINT)) + { + fired |= ADI_RTC_COUNT_ROLLOVER_INT; + } + if( (enables & BITM_RTC_CR1_TRMINTEN) && (nIntSrc2 & BITM_RTC_SR2_TRMINT)) + { + fired |= ADI_RTC_TRIM_INT; + } + if( (enables & BITM_RTC_CR1_PSINTEN) && (nIntSrc2 & BITM_RTC_SR2_PSINT)) + { + fired |= ADI_RTC_PSI_INT; + } + if( (enables & BITM_RTC_CR1_CNTINTEN) && (nIntSrc2 & BITM_RTC_SR2_CNTINT)) + { + fired |= ADI_RTC_COUNT_INT; + } + } + + /* CR3OC, CR2IC SR3*/ + enables = pDevice->pRTCRegs->CR3SS & (uint32_t)ADI_RTC_INT_ENA_MASK_CR3SS; + nIntSrc3 = pDevice->pRTCRegs->SR3 & ADI_RTC_SR3_IRQ_STATUS_MASK; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR3SS_SS4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH4_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH3_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH2_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1IRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1IRQ)) + { + fired |= ADI_RTC_SENSOR_STROBE_CH1_INT; + } + + if( (enables & BITM_RTC_CR3SS_SS4FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS4FEIRQ)) + { + fired |= ADI_RTC_RTCSS4_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS3FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS2FEIRQ)) + { + fired |= ADI_RTC_RTCSS3_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS2FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS3FEIRQ)) + { + fired |= ADI_RTC_RTCSS2_FE_INT; + } + if( (enables & BITM_RTC_CR3SS_SS1FEIRQEN) && (nIntSrc3 & BITM_RTC_SR3_SS1FEIRQ)) + { + fired |= ADI_RTC_RTCSS1_FE_INT; + } + } + enables = pDevice->pRTCRegs->CR2IC & (uint32_t)ADI_RTC_INT_ENA_MASK_CR2IC; + if( nIntSrc3 && enables ) + { + if( (enables & BITM_RTC_CR2IC_IC4IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC4IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH4_INT; + } + if( (enables & BITM_RTC_CR2IC_IC3IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC3IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH3_INT; + } + if( (enables & BITM_RTC_CR2IC_IC2IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC2IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH2_INT; + } + if( (enables & BITM_RTC_CR2IC_IC0IRQEN) && (nIntSrc3 & BITM_RTC_SR3_IC0IRQ)) + { + fired |= ADI_RTC_INPUT_CAPTURE_CH0_INT; + } + } + + if (pDevice->pfCallback != NULL) { + + /* forward to the user if he is watching this interrupt */ + /* pass the "fired" value as the event. argument param is not used */ + if ( fired) + { + pDevice->pfCallback (pDevice->pCBParam, fired, NULL); + } + } + + /* Write 1 to clear the interrupts */ + pDevice->pRTCRegs->SR0 |= nIntSrc0; + pDevice->pRTCRegs->SR2 |= nIntSrc2; + pDevice->pRTCRegs->SR3 |= nIntSrc3; + + ISR_EPILOG(); +} + +/*! \endcond */ + +/* @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c new file mode 100755 index 00000000000..624b8d30309 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c @@ -0,0 +1,192 @@ +/*! + ***************************************************************************** + * @file: adi_rtc_data.c + * @brief: rtc device data file + * @version: $Revision: 34933 $ + * @date: $Date: 2016-06-28 07:11:25 -0400 (Tue, 28 Jun 2016) $ + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/*! \cond PRIVATE */ +#ifndef ADI_RTC_DATA_C_ +#define ADI_RTC_DATA_C_ + +#include +#include +#include "adi_rtc_def.h" + + +static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] = +{ + { + (ADI_RTC_TypeDef *)pADI_RTC0,RTC0_EVT_IRQn, NULL + }, + { + (ADI_RTC_TypeDef *)pADI_RTC1,RTC1_EVT_IRQn,NULL, + } +}; + + +static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] = +{ + { + /* CR0 */ + RTC0_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN | + RTC0_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN | + RTC0_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN | + RTC0_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN | + RTC0_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN | + RTC0_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN , + /* CR1 */ + 0, + /* CNT0 */ + RTC0_CFG_COUNT_VALUE_0, + /* CNT1 */ + RTC0_CFG_COUNT_VALUE_1, + /* ALM0 */ + RTC0_CFG_ALARM_VALUE_0, + /* ALM1 */ + RTC0_CFG_ALARM_VALUE_1, + /* ALM2 */ + 0, + /* TRIM */ + RTC0_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN | + RTC0_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | + RTC0_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | + RTC0_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, + 0, /* CR2IC */ + 0, /* CR3SS */ + 0, /* CR4SS */ + 0, /* SSMSK */ + 0, /* SS1 */ + 0, /* CR5SSS */ + 0, /* CR6SSS */ + 0, /* CR7SSS */ + 0, /* GPMUX0 */ + 0 /* GPMUX1 */ + + }, + /* RTC-1 */ + { + /* CR0 */ + RTC1_CFG_ENABLE_ALARM << BITP_RTC_CR0_ALMEN | + RTC1_CFG_ENABLE_ALARM_INTERRUPT << BITP_RTC_CR0_ALMINTEN | + RTC1_CFG_ENABLE_TRIM << BITP_RTC_CR0_TRMEN | + RTC1_CFG_ENABLE_MOD60_ALARM << BITP_RTC_CR0_MOD60ALMEN | + RTC1_CFG_ENABLE_MOD60_ALARM_PERIOD << BITP_RTC_CR0_MOD60ALM | + RTC1_CFG_ENABLE_MOD60_ALARM_INTERRUPT << BITP_RTC_CR0_MOD60ALMINTEN | + RTC1_CFG_ENABLE_ISO_INTERRUPT << BITP_RTC_CR0_ISOINTEN | + RTC1_CFG_ENABLE_PENDERROR_INTERRUPT << BITP_RTC_CR0_WPNDERRINTEN | + RTC1_CFG_ENABLE_WSYNC_INTERRUPT << BITP_RTC_CR0_WSYNCINTEN | + RTC1_CFG_ENABLE_WRITEPEND_INTERRUPT << BITP_RTC_CR0_WPNDINTEN , + /* CR1 */ + RTC1_CFG_ENABLE_COUNT_INTERRUPT << BITP_RTC_CR1_CNTINTEN | + RTC1_CFG_ENABLE_MOD1_COUNT_INTERRUPT << BITP_RTC_CR1_PSINTEN | + RTC1_CFG_ENABLE_TRIM_INTERRUPT << BITP_RTC_CR1_TRMINTEN | + RTC1_CFG_CNT_MOD60_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTROLLINTEN | + RTC1_CFG_PRESCALE << BITP_RTC_CR1_PRESCALE2EXP | + RTC1_CFG_CNT_ROLLLOVER_INTERRUPT << BITP_RTC_CR1_CNTMOD60ROLLINTEN , + /* CNT0 */ + RTC1_CFG_COUNT_VALUE_0, + /* CNT1 */ + RTC1_CFG_COUNT_VALUE_1, + + /* ALM[123] */ + RTC1_CFG_ALARM_VALUE_0, + RTC1_CFG_ALARM_VALUE_1, + RTC1_CFG_ALARM_VALUE_2, + + /* TRIM */ + RTC1_CFG_POW2_TRIM_INTERVAL << BITP_RTC_TRM_IVL2EXPMIN | + RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL | + RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD | + RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE, + + /* CR2IC */ + RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN | + RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN | + RTC1_CFG_IC3_ENABLE << BITP_RTC_CR2IC_IC3EN | + RTC1_CFG_IC4_ENABLE << BITP_RTC_CR2IC_IC4EN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC0IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC2IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC3IRQEN | + RTC1_CFG_IC0_INT_ENABLE << BITP_RTC_CR2IC_IC4IRQEN | + RTC1_CFG_IC0_EDGE_POLARITY << BITP_RTC_CR2IC_IC0LH | + RTC1_CFG_IC2_EDGE_POLARITY << BITP_RTC_CR2IC_IC2LH | + RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH | + RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH | + RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN, + + /* CR3SS */ + RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN | + RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN | + RTC1_CFG_SS3_ENABLE << BITP_RTC_CR3SS_SS3EN | + RTC1_CFG_SS4_ENABLE << BITP_RTC_CR3SS_SS4EN | + RTC1_CFG_SS1_INT_ENABLE << BITP_RTC_CR3SS_SS1IRQEN | + RTC1_CFG_SS2_INT_ENABLE << BITP_RTC_CR3SS_SS2IRQEN | + RTC1_CFG_SS3_INT_ENABLE << BITP_RTC_CR3SS_SS3IRQEN | + RTC1_CFG_SS4_INT_ENABLE << BITP_RTC_CR3SS_SS4IRQEN, + + /* CR4SS */ + RTC1_CFG_SS1_MASK_ENABLE << BITP_RTC_CR4SS_SS1MSKEN | + RTC1_CFG_SS2_MASK_ENABLE << BITP_RTC_CR4SS_SS2MSKEN | + RTC1_CFG_SS3_MASK_ENABLE << BITP_RTC_CR4SS_SS3MSKEN | + RTC1_CFG_SS4_MASK_ENABLE << BITP_RTC_CR4SS_SS4MSKEN | + RTC1_CFG_SS1_AUTO_RELOADING_ENABLE << BITP_RTC_CR4SS_SS1ARLEN, + + /* SSMSK */ + RTC1_CFG_SS1_MASK_VALUE, + + /* SS1 */ + RTC1_CFG_SS1_AUTO_RELOAD_VALUE, + + 0, /* CR5SSS */ /* TODO: Add the following to the static configuration macros */ + 0, /* CR6SSS */ + 0, /* CR7SSS */ + 0x4688, /* GPMUX0 */ + 0x01F5, /* GPMUX1 */ + + } + +}; + +#endif +/*! \endcond */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h new file mode 100755 index 00000000000..a6fca0e37b5 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h @@ -0,0 +1,165 @@ +/*! + ***************************************************************************** + * @file: adi_rtc_def.h + * @brief: RTC def file + * @version: $Revision: 33205 $ + * @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $ + *----------------------------------------------------------------------------- + * + * Copyright (c) 2010-2016 Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * - Modified versions of the software must be conspicuously marked as such. + * - This software is licensed solely and exclusively for use with processors + * manufactured by or for Analog Devices, Inc. + * - This software may not be combined or merged with other code in any manner + * that would cause the software to become subject to terms and conditions + * which differ from those listed here. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights of one + * or more patent holders. This license does not release you from the + * requirement that you obtain separate licenses from these patent holders + * to use this software. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL + * PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef ADI_RTC_DEF_H__ +#define ADI_RTC_DEF_H__ + +#include + +/*! \cond PRIVATE */ +#define ADI_RTC_NUM_INSTANCE 2u + + + +#define ADI_RTC_INT_ENA_MASK_CR0 0XF804u + +#define ADI_RTC_INT_ENA_MASK_CR1 0X1Fu + +#define ADI_RTC_INT_ENA_MASK_CR2IC 0xF41C +#define ADI_RTC_INT_ENA_MASK_CR3SS 0x1FFE +#define ADI_RTC_INT_ENA_MASK_CR4SS 0x0E0E +#define ADI_RTC_INT_ENA_MASK_CR5SSS 0x0FFF + +#define ADI_RTC_INT_SOURCE_MASK_SR0 0x007Eu +#define ADI_RTC_INT_SOURCE_MASK_SR2 0x001Fu + +#define ADI_RTC_WRITE_STATUS_MASK 0XCF8u +#define ADI_RTC_SR2_IRQ_STATUS_MASK 0X1Fu +#define ADI_RTC_SR3_IRQ_STATUS_MASK 0X1FFFu + + + +#define ADI_RTC_TRIM_MASK (BITM_RTC_TRM_VALUE | BITM_RTC_TRM_ADD|BITM_RTC_TRM_IVL | BITM_RTC_TRM_IVL2EXPMIN ) + +#if (ADI_RTC_CFG_ENABLE_SAFE_WRITE == 1) + /* pause on pending writes to CR to avoid data loss */ + +#ifdef __ICCARM__ +/* +* Pm154 (rule 19.10): in the definition of a function-like macro, each instance +* of a parameter shall be enclosed in parentheses +* Parameter use without parentheses needed for struct field name in register access macro. +*/ +#pragma diag_suppress=Pm154 +#endif /* __ICCARM__ */ + +#define PEND_BEFORE_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))!=0u)\ + {\ + } + +#define SYNC_AFTER_WRITE(reg,mask) while((pDevice->pRTCRegs->reg&(mask))==0u)\ + {\ + } + +#ifdef __ICCARM__ +#pragma diag_default=Pm154 +#endif /* __ICCARM__ */ + +#else + /* pause on pending writes to CR to avoid data loss */ +#define PEND_BEFORE_WRITE(reg,mask) +#define SYNC_AFTER_WRITE(reg,mask) +#endif + +/* + * The following is used for static configuration + */ +typedef struct +{ + uint16_t CR0; /*!< CR0 16 bit control register-0 value */ + uint16_t CR1; /*!< CR1 16 bit control register-1 value */ + uint16_t CNT0; /*!< CNT0 16 bit count register value */ + uint16_t CNT1; /*!< CNT1 16 bit count register value */ + + uint16_t ALM0; /*!< ALM0 16 bit integer part of alarm value */ + uint16_t ALM1; /*!< ALM1 16 bit integer part of alarm value */ + uint16_t ALM2; /*!< ALM2 16 bit integer part of alarm value */ + uint16_t TRIM; /*!< 16 bit trim register value */ + uint16_t CR2IC; /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */ + uint16_t CR3SS; /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */ + uint16_t CR4SS; /*!< CR4SS 16 bit control ( controls Auto reload and mask for sensor strobe ) register-4 value */ + uint16_t SSMSK; /*!< OCMSK Mask register for sensor strobe channel */ + uint16_t SS1; /*!< 16 bit Auto reload value */ + + uint16_t CR5SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t CR6SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t CR7SSS; /*!< Configure Sensor Strobe Channel GPIO Sampling Register */ + uint16_t GPMUX0; /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe channel */ + uint16_t GPMUX1; /*!< Control register for selecting a GPIO (pin) as data to be sampled by a Sensor Strobe channel */ +}ADI_RTC_CONFIG; + +/* Device information structure */ +typedef struct _ADI_RTC_DEVICE_INFO +{ + volatile ADI_RTC_TypeDef *pRTCRegs; /* Base address of the SPORT registers */ + const IRQn_Type eIRQn; /* IRQn */ + ADI_RTC_HANDLE hDevice; /* RTC handle */ +}ADI_RTC_DEVICE_INFO; + +/*! RTC driver instance data */ +typedef struct _ADI_RTC_DEVICE +{ + volatile ADI_RTC_TypeDef *pRTCRegs; /* Pointer to RTC Memory Mapped Registers */ + + ADI_CALLBACK pfCallback; /* Function pointer for callback function. */ + + void *pCBParam; /* Parameter to callback function. */ + IRQn_Type eIRQn; /* IRQn */ + uint32_t cbWatch; + ADI_RTC_DEVICE_INFO *pDeviceInfo; /* Parameter to callback function. */ + +} ADI_RTC_DEVICE; + + +static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig); + +#ifdef ADI_DEBUG +static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice); +#endif +/*! \endcond */ +#endif /* ADI_RTC_DEF_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h new file mode 100755 index 00000000000..7224c14faa4 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map.h @@ -0,0 +1,71 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map.h + @brief: RTOS API mapping file. + This is the main RTOS mapping header file which will include other + RTOS mapping files based on the RTOS selection. + + The purpose of RTOS mapping file is for mapping the abstracted + RTOS macros to the RTOS API calls based on the chosen RTOS. + + NOTE: This file is intended to be used by only the drivers. Not at + the application level. + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ +#ifndef ADI_RTOS_MAP_H +#define ADI_RTOS_MAP_H + +#include + +#if (ADI_CFG_RTOS == ADI_CFG_RTOS_MICRIUM_III) + +#include "rtos_map/adi_rtos_map_ucos_iii.h" + +#elif (ADI_CFG_RTOS == ADI_CFG_RTOS_FREERTOS) + +#include "rtos_map/adi_rtos_map_freertos.h" + +#else + +#include "rtos_map/adi_rtos_map_noos.h" + +#endif /* ADI_CFG_RTOS_MICRIUM_III */ + +#endif /* ADI_RTOS_MAP_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h new file mode 100755 index 00000000000..97cbcaeeb78 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_freertos.h @@ -0,0 +1,144 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_freertos.h + @brief: FreeRTOS RTOS API mapping file. + + This file maps the RTOS macros to FreeRTOS APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_FREERTOS_H +#define ADI_RTOS_MAP_FREERTOS_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include "semphr.h" + +extern BaseType_t xHigherPriorityTaskWoken; + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + StaticQueue_t hSemaphore; + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. FreeRtos does not + require semaphore memory to be passed by application. But memory is required + to store the handle. */ +#define ADI_SEM_SIZE (sizeof(StaticQueue_t)) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ + + /*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + xSemaphoreCreateBinaryStatic(&(DEV)->hSemaphore); \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_DELETE(DEV, error) \ + do { \ + vSemaphoreDelete (&(DEV)->hSemaphore); \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/ +#define SEM_PEND(DEV, error) \ + do { \ + if(xSemaphoreTake (&(DEV)->hSemaphore, portMAX_DELAY) != pdTRUE) \ + return((error)); \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +/* Note that priority inversion is supported */ +#define SEM_POST(DEV) \ + do { \ + /* Assume that a higher priority task can be schedule in */ \ + BaseType_t xHigherPriorityTaskWoken = pdTRUE; \ + xSemaphoreGiveFromISR(&(DEV)->hSemaphore, &xHigherPriorityTaskWoken); \ + } while (0) + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() vPortEnterCritical() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() vPortExitCritical() + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#define ISR_PROLOG() + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() portYIELD() + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER xPortPendSVHandler +#define SYSTICK_HANDLER xPortSysTickHandler +#define SVC_HANDLER vPortSVCHandler + + +#endif /* ADI_RTOS_MAP_FREERTOS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h new file mode 100755 index 00000000000..e508f1ccf57 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_noos.h @@ -0,0 +1,180 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_noos.h + @brief: No OS API mapping file. + + This file maps the RTOS macros to No OS APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_NOOS_H +#define ADI_RTOS_MAP_NOOS_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() uint32_t IntStatus = 0u + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() \ +do { \ + IntStatus = __get_PRIMASK(); \ + __disable_irq(); \ +} while (0) + + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() \ +do { \ + __set_PRIMASK(IntStatus); \ +} while (0) + + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. */ +#define ADI_SEM_SIZE (sizeof(uint32_t)) + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) +#define ISR_PROLOG() adi_cyclecount_start(); +#else +#define ISR_PROLOG() +#endif + + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1u) +#define ISR_EPILOG() adi_cyclecount_stop(); +#else +#define ISR_EPILOG() +#endif + +#if (ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 1) + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR volatile uint32_t nLowPowerExitFlag; + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + (DEV)->nLowPowerExitFlag = 0u + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) do { } while(0) + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + do { \ + ADI_PWR_RESULT eResult; \ + eResult = adi_pwr_EnterLowPowerMode(ADI_PWR_MODE_FLEXI, &(DEV)->nLowPowerExitFlag, 0u); \ + if(eResult != ADI_PWR_SUCCESS) { return ((error)); } \ + } while(0) + + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + adi_pwr_ExitLowPowerMode(&(DEV)->nLowPowerExitFlag); \ + } while(0) + + +#else /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT == 0 */ + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR volatile uint32_t nSemCount; + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + (DEV)->nSemCount = 0 + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) do { } while(0) + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + while ((DEV)->nSemCount == 0u) {} \ + (DEV)->nSemCount-- + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) { \ + (DEV)->nSemCount++; \ +} + +#endif /* ADI_CFG_ENTER_LOW_PWR_MODE_SUPPORT */ + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER PendSV_Handler +#define SYSTICK_HANDLER SysTick_Handler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_NOOS_H */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h new file mode 100755 index 00000000000..20ee60f610f --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_ii.h @@ -0,0 +1,149 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_ucos_ii.h + @brief: uCOS-III RTOS API mapping file. + + This file maps the RTOS macros to uCOS-II APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_UCOS_II_H +#define ADI_RTOS_MAP_UCOS_II_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + OS_EVENT *hSemaphore; + +/*! Memory size required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. In case of uCOS-II + there is no requirement to provide the memory to create the semaphore, but + memory is required to store the handle */ +#define ADI_SEM_SIZE sizeof(OS_EVENT) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + ((DEV)->hSemaphore) = OSSemCreate(0u); \ + if((DEV)->hSemaphore == NULL) {return((error));} \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle */ +#define SEM_DELETE(DEV, error) \ + do { \ + INT8U os_error; \ + OSSemDel( (DEV)->hSemaphore, OS_DEL_NO_PEND, &os_error ); \ + if(os_error != OS_ERR_NONE) {return((error));} \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_PEND(DEV, error) \ + do { \ + INT8U os_error; \ + OSSemPend ((DEV)->hSemaphore, 0u, &os_error); \ + if(os_error != OS_ERR_NONE) {return((error));} \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + OSSemPost((DEV)->hSemaphore ); \ + } while (0) + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() + */ +#define ADI_INT_STATUS_ALLOC() CPU_SR_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() CPU_CRITICAL_ENTER() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT() + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#define ISR_PROLOG() \ + do { \ + CPU_SR_ALLOC(); \ + CPU_CRITICAL_ENTER(); \ + OSIntEnter(); \ + CPU_CRITICAL_EXIT(); \ + } while (0); + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() OSIntExit(); + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER OS_CPU_PendSVHandler +#define SYSTICK_HANDLER OS_CPU_SysTickHandler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_UCOS_II_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h new file mode 100755 index 00000000000..e055b7010fb --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtos_map/adi_rtos_map_ucos_iii.h @@ -0,0 +1,167 @@ +/*! + ***************************************************************************** + @file: adi_rtos_map_ucos_iii.h + @brief: uCOS-III RTOS API mapping file. + + This file maps the RTOS macros to uCOS-III APIs + + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. +*****************************************************************************/ + +#ifndef ADI_RTOS_MAP_UCOS_III_H +#define ADI_RTOS_MAP_UCOS_III_H + +/* If building a c file */ +#if defined(__STDC__) + +#include +#include +#include +#include + +/*! Macro that declares the semaphore type that the drivers use. + The macro should be used within the device data structure. + It should not be used to declare the semaphore as a global variable. */ +#define SEM_VAR_DECLR \ + OS_SEM Semaphore; + +/*! Memory required for semaphore in terms bytes. This size is used to compute + the total memory required for the operation of the driver. uCOS-III requires + semaphore memory to be passed by application. But there is no memory required + to store the handle. For every semaphore related call the same memory pointer + that was used during create will be passed. */ +#define ADI_SEM_SIZE (sizeof(OS_SEM)) + +/*! Macro that creates a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_CREATE(DEV, name, error) \ + do { \ + OS_ERR os_error; \ + OSSemCreate(&((DEV)->Semaphore), name ,0u, &os_error); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + +/*! Macro that deletes a semaphore and returns the error specified in case of failure. DEV is the handle to the device driver structure that contains the semaphore/semaphore handle. */ +#define SEM_DELETE(DEV, error) \ + do { \ + OS_ERR os_error; \ + OSSemDel( &((DEV)->Semaphore), OS_OPT_DEL_NO_PEND, &os_error ); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + + +/*! Macro that blocks indefinitely on a semaphore and returns error in case of failure. DEV is the handle to the device driver structure that contains the semaphore handle.*/ +#define SEM_PEND(DEV, error) \ + do { \ + OS_ERR os_error; \ + OSSemPend (&((DEV)->Semaphore), 0u, OS_OPT_PEND_BLOCKING , NULL, &os_error); \ + if(OS_ERR_NONE != os_error) {return((error));} \ + } while (0) + +/*! Macro that posts a semaphore. DEV is the handle to the device driver structure that contains the semaphore handle. */ +#define SEM_POST(DEV) \ + do { \ + OS_ERR os_error; \ + OSSemPost(&((DEV)->Semaphore), OS_OPT_POST_1, &os_error); \ + } while (0) + + +/*! Defines a local variable where interrupt status register value is stored. + This macro should be used within a function in which critical section + macros ADI_ENTER_CRITICAL_REGION and ADI_EXIT_CRITICAL_REGION are + used. + + @sa ADI_ENTER_CRITICAL_REGION() + @sa ADI_EXIT_CRITICAL_REGION() +*/ +#define ADI_INT_STATUS_ALLOC() CPU_SR_ALLOC() + +/*! Macro to enter critical section. To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_ENTER_CRITICAL_REGION() CPU_CRITICAL_ENTER() + +/*! Macro to exit critical section.To use this macro, the + interrupt status variable should be defined (ADI_INT_STATUS_ALLOC) + in the same scope. + + @sa ADI_INT_STATUS_ALLOC() +*/ +#define ADI_EXIT_CRITICAL_REGION() CPU_CRITICAL_EXIT() + + +/*! Code that uCOS requires to be run in the beginning of an interrupt handler. + @sa ISR_EPILOG() +*/ +#if defined(ADI_CYCLECOUNT_ENABLED) && (ADI_CYCLECOUNT_ENABLED == 1) +#define ADI_RTOS_UCOS_III_CYCLECOUNT_START adi_cyclecount_start(); +#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP adi_cyclecount_stop(); +#else +#define ADI_RTOS_UCOS_III_CYCLECOUNT_START +#define ADI_RTOS_UCOS_III_CYCLECOUNT_STOP +#endif + +#define ISR_PROLOG() \ + do { \ + CPU_SR_ALLOC(); \ + CPU_CRITICAL_ENTER(); \ + OSIntEnter(); \ + CPU_CRITICAL_EXIT(); \ + ADI_RTOS_UCOS_III_CYCLECOUNT_START \ + } while (0); + +/*! Code that uCOS requires to be run in the end of an interrupt handler. + @sa ISR_PROLOG() +*/ +#define ISR_EPILOG() \ + do { \ + ADI_RTOS_UCOS_III_CYCLECOUNT_STOP \ + OSIntExit(); \ + } while (0); \ + +#endif /* __STDC__ */ + +#define PENDSV_HANDLER OS_CPU_PendSVHandler +#define SYSTICK_HANDLER OS_CPU_SysTickHandler +#define SVC_HANDLER SVC_Handler + + +#endif /* ADI_RTOS_MAP_UCOS_III_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c new file mode 100755 index 00000000000..7c8c0e30229 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi.c @@ -0,0 +1,1892 @@ +/*! ***************************************************************************** + * @file: adi_spi.c + * @brief: SPI device driver global file. + * @details: This a global file which includes a specific file based on the processor family. + * This included file will be containing SPI device driver functions. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup SPI_Driver SPI Driver + * @{ + * @brief Serial Peripheral Interface (SPI) Driver + * @details The SPI driver manages all instances of the SPI peripheral. + * @note The application must include drivers/spi/adi_spi.h to use this driver. + * @note This driver requires the DMA driver.The application must include the DMA driver sources to avoid link errors. + * @note Also note that the SPI will be configured by default to operate in Master mode. + * @note To configure the driver to operate in slave mode the static configuration file adi_spi_config.h must be modified. + * @note Specifically, the macro ADI_SPIx_MASTER_MODE must be set to '0' to indicate that slave mode functionality is needed. + * @note Since there are three SPI devices there are three macros, ADI_SPI0_MASTER_MODE, ADI_SPI1_MASTER_MODE and ADI_SPI2_MASTER_MODE to control the functionality of each SPI controller. + * @note Each instance of the SPI operates independently from all other instances. + * @note + * @note When operating the SPI at high bit rates the application may need to modify the IRQ interrupt mode. The API adi_spi_SetIrqmode() can be used for this. + * @note At higher bit rates the ISR could mask a TX/RX interrupt. Specifically, it is possible that while servicing a TX/RX event another TX/RX event could occur. It is + * @note possible, therefore, that when the ISR clears the interrupt status it will not only be clearing the current TX event but the next TX/RX event as well. The result + * @note could that a final TX/RX event will not be processed. One way to work around this would be to set IRQMODE such that TX/RX events will occur only after N bytes + * @note are in the FIFO. This will only work for short bursts less than the size of the FIFO. For larger transfer DMA mode, which will not have any of these issues, should be used. + * @note Finally, if interrupt mode is required at hight bit rates note that the SPI ISR has been designed with minimal cycle count as the highest priority. + * @note The ISR could certainly be modified to re-examine the FIFO before existing at the cost of additional cycles. + */ + + /*! \cond PRIVATE */ +#include +/*! \endcond */ + +#include /* for 'NULL" definition */ +#include + +#include +#include +#include +#include +#include +#include "adi_spi_config.h" +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors +* +* Pm151 (rule 17.4): array indexing shall only be applied to objects of array type +* Pm123 (rule 18.5): there shall be no definition of objects in a header file +* +* Pm50: (MISRA C 2004 rule 14.3) a null statement shall only occur on a line by itself, and shall not have any other text on the same line +* Some Macros, such as ISR_PROLOGUE, may not have any expansion resulting in just the terminating ';' +* +*Pm140: (MISRA C 2004 rule 11.3) a cast should not be performed between a pointer type and an integral type +* MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type +* +* Pm031: (MISRA C 2004 rule 12.7) bitwise operations shall not be performed on signed integer types +* MMR macros are beyond the control of the driver. +* +*/ +#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm143,Pm152,Pm140,Pm031 + +#endif /* __ICCARM__ */ + +#include "adi_spi_data.c" + +/*! \cond PRIVATE */ + +/* handle checker for debug mode */ +#define ADI_SPI_VALIDATE_HANDLE(h) ((spi_device_info[0].hDevice != (h)) && (spi_device_info[1].hDevice != (h)) && (spi_device_info[2].hDevice != (h))) + +/*! \endcond */ + +/* + * Local prototypes + */ +static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD); +static void StartTransaction (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr); +static void TxDmaErrorCallback (void *pCBParam, uint32_t Event, void *pArg); +static void RxDmaErrorCallback (void *pCBParam, uint32_t Event, void *pArg); + +/* ISR forward declarations */ +/*! \cond PRIVATE */ +void SPI0_Int_Handler(void); +void SPI1_Int_Handler(void); +void SPI2_Int_Handler(void); +void DMA_SPI0_TX_Int_Handler(void); +void DMA_SPI0_RX_Int_Handler(void); +void DMA_SPI1_TX_Int_Handler(void); +void DMA_SPI1_RX_Int_Handler(void); +void DMA_SPIH_TX_Int_Handler(void); +void DMA_SPIH_RX_Int_Handler(void); +/*! \endcond */ + +/* + ////////////////////////////////////////////////////////////////////////////// + ////////////////////// API IMPLEMENTATIONS /////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// +*/ + +/*! + * @brief Initialize and allocate an SPI device for use in Master Mode. + * + * @param[in] nDeviceNum Zero-based device index designating which device to initialize. + *\n + * @param [in] pDevMemory Pointer to a buffer of size ADI_SPI_MEMORY_SIZE + *\n required by the driver for the operation of specified SPI device. + * + * @param [in] nMemorySize Size of the buffer to which "pMemory" points. + * + * @param[out] phDevice The caller's device handle pointer for storing the initialized device instance data pointer. + * + * @return Status + * - #ADI_SPI_INVALID_DEVICE_NUM [D] Invalid device index. + * - #ADI_SPI_INVALID_PARAM [D] Invalid parameter. + * - #ADI_SPI_SEMAPHORE_FAILED Semaphore creation failed. + * - #ADI_SPI_DMA_REG_FAILED Failed to register DMA callbacks with common DMA service. + * - #ADI_SPI_IN_USE SPI is already open and in use. + * - #ADI_SPI_SUCCESS Call completed successfully. + * +* @note : No other SPI APIs may be called until the device open function is called. + *\n Initialize an SPI device using internal default configuration settings and allocate the + *\n device for use.The returned device handle is required to be passed to all subsequent + *\n calls to convey which device instance to operate on. + *\n The contents of phDevice will be set to NULL upon failure. Device is opened in Master mode. + *\n + * @sa adi_spi_SetMasterMode() + * @sa adi_spi_Close(). + */ +ADI_SPI_RESULT adi_spi_Open(uint32_t nDeviceNum, + void *pDevMemory, + uint32_t nMemorySize, + ADI_SPI_HANDLE* const phDevice) +{ + +#ifdef ADI_DEBUG + + if (nDeviceNum >= ADI_SPI_NUM_INSTANCES) + { + return ADI_SPI_INVALID_DEVICE_NUM; + } + + if (nMemorySize != sizeof(struct __ADI_SPI_DEV_DATA_TYPE)) + { + return ADI_SPI_INVALID_PARAM; + } + + if( spi_device_info[nDeviceNum].hDevice != NULL ) + { + return ADI_SPI_IN_USE; + } + +#endif + + ADI_SPI_HANDLE hDevice = pDevMemory; + + /* + * Link the two data structures together. + * + * ADI_SPI_DEVICE_INFO <==> ADI_SPI_HANDLE + * + * Clear the ADI_SPI_HANDLE memory. This also sets all bool + * structure members to false so we do not need to waste cycles + * setting these explicitly (e.g. hDevice->bDMA = false) + * + * Other fields, such as callback related fields, are also zeroed + * and therefore properly initialized. + */ + + spi_device_info[nDeviceNum].hDevice = (ADI_SPI_DEV_DATA_TYPE *)pDevMemory; + memset(pDevMemory,0,nMemorySize); + hDevice->pDevInfo = &spi_device_info[nDeviceNum]; + + + /* + * Although the ADI_SPI_DEVICE_INFO struct has the address of the SPI registers + * for this instance, copying it to the ADI_SPI_HANDLE struct will minimize + * the runtime footprint and cycle count when accessing the SPI registers + */ + hDevice->pSpi = spi_device_info[nDeviceNum].pSpiRegs; + + SEM_CREATE(hDevice, "SPI_SEM", ADI_SPI_SEMAPHORE_FAILED); + + /* Static Configuration */ + /* Initialize the device based on the given configuration parameters */ + ADI_SPI_CFG_TYPE const* pSPICfg = &gSPICfg[nDeviceNum]; + hDevice->pSpi->CTL = pSPICfg->SPI_CTL; + hDevice->pSpi->DIV = pSPICfg->SPI_DIV; + + /* write the device data pointer into the caller's handle */ + *phDevice = hDevice; + hDevice->pSpi->CTL |= BITM_SPI_CTL_SPIEN; + + /* Make sure the DMA controller and its SRAM based descriptors are initialized */ + adi_dma_Init(); + + /* Setup the DMA TX callback */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaTxChannelNumber, TxDmaErrorCallback, (void *) hDevice)) + { + return ADI_SPI_DMA_REG_FAILED; + } + + /* Setup the DMA RX callback */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback((DMA_CHANn_TypeDef) hDevice->pDevInfo->dmaRxChannelNumber, RxDmaErrorCallback, (void *) hDevice)) + { + return ADI_SPI_DMA_REG_FAILED; + } + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Uninitialize and deallocate an SPI device. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Uninitialize and release an allocated SPI device,and memory associated with it for other use. + * + * @sa adi_spi_Open(). + */ +ADI_SPI_RESULT adi_spi_Close (ADI_SPI_HANDLE const hDevice) +{ + + ADI_SPI_RESULT result = ADI_SPI_SUCCESS; +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + + /* disable Interrupt */ + NVIC_DisableIRQ(hDevice->pDevInfo->eIRQn); + + + /* destroy semaphore */ + SEM_DELETE((ADI_SPI_HANDLE) hDevice,ADI_SPI_SEMAPHORE_FAILED); + + /* invalidate initialization state */ + hDevice->pDevInfo->hDevice = NULL; + return result; +} + + +/*! + * @brief Register or unregister the callback. + * + * @param [in] hDevice Device handle obtained from adi_spi_Open(). + * @param [in] pfCallback Pointer to the callback function. Can be passed as NULL to unregister the + *\n previously registered callback. + * @param [in] pCBParam Callback parameter which will be passed back to the application when the + *\n callback is called. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + */ +ADI_SPI_RESULT adi_spi_RegisterCallback (ADI_SPI_HANDLE const hDevice, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + /* Save the application provided callback and callback parameters */ + hDevice->pfCallback = pfCallback; + hDevice->pCBParam = pCBParam; + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the IRQ mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] nMode IRQ mode value to set. +* - true Set continuous transfer mode. +* - false Clear continuous transfer mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * These bits configure when the Tx/Rx interrupts occur in a transfer. + * For DMA Rxtransfer, these bits should be 0. + * Value values are 0-7 + * Tx interrupt occurs when (nMode+1) byte(s) has been transferred. + * Rx interrupt occurs when (nMode+1) or more bytes have been received into the FIFO. + * + * @note The application will have to carefully manage IRQMODE relative to a transaction's buffer size. + * @note Specifically, the application must ensure that the last byte causes an interrupt else the + * @note transaction will not terminate. As explained in the SPI driver overview, this functionality + * @note is typically needed when operating in interrupt mode with a high SPI bit rate (typically issues + * @note are seen at SPI clock rates of 4MHz or greater). The max clock rate will vary depending on the application. + * @note The max clock rate is a function of the SPI ISR cycle count plus any other delay that might be caused + * @note by other parts of the system. Finally, please note that while sustaining interrupt mode SPI transaction + * @note at high bit rates will work buffers that are the size of the SPI FIFO or less, transactions that are + * @note larger that the size of the FIFO may run into issues associated with masked/lost interrupts. If this + * @note does prove to be an issue for an applicatoon then the SPI ISR could be modified to examine the FIFO + * @note status on a continuous basis in the ISR (as opposed to examining the FIFO status just once at the start + * @note of the ISR). However, adding this functionality to the ISR will increase the ISR cycle count and footprint. + * + */ +ADI_SPI_RESULT adi_spi_SetIrqmode (ADI_SPI_CONST_HANDLE const hDevice, const uint8_t nMode) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + uint16_t ien = hDevice->pSpi->IEN; + ien = ien & (uint16_t)~BITM_SPI_IEN_IRQMODE; + ien = ien | (nMode & BITM_SPI_IEN_IRQMODE); + hDevice->pSpi->IEN = ien; + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the continuous transfer mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage SPI continuous transfer mode. +* - true Set continuous transfer mode. +* - false Clear continuous transfer mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Setting this mode causes the SPI controller to drive the Chip Select signal continuously until the transaction + * is complete. Clearing it causes Chip Select to cycle between bytes. + * + * + */ +ADI_SPI_RESULT adi_spi_SetContinuousMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set the internal loopback mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage internal SPI loopback mode. + * - true Set internal loopback mode. + * - false Clear internal loopback mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Set or clear the internal SPI loopback mode. Primarily used for testing. + * + */ +ADI_SPI_RESULT adi_spi_SetLoopback (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_LOOPBACK); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_LOOPBACK; + } + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Set SPI Master-Mode operation. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to select either Master-Mode or Slave-Mode operation. + *\n - true Enable Master-Mode. Default. + *\n - false Enable Slave-Mode. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Controls SPI Master/Slave mode of operation, set for Master-Mode, clear for Slave-Mode. + * + */ +ADI_SPI_RESULT adi_spi_SetMasterMode (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + if (true == bFlag) { /* hardware default */ + hDevice->pSpi->CTL |= (ADI_SPI_MASTERCON_INITIALIZER); + } else { + hDevice->pSpi->CNT = 0u; + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_MASEN; + hDevice->pSpi->CTL |= (ADI_SPI_SLAVECON_INITIALIZER); + } + ADI_EXIT_CRITICAL_REGION(); + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the SPI receive FIFO overflow mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage receive FIFO overflow behaviour. + *\n - true Discard old data on receive FIFO overflow. + *\n - false Discard new data on receive FIFO overflow. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Controls what to do with excess incoming data when the receive FIFO becomes full. + * Either the new data or the old data is discarded. Set the receive FIFO overflow mode + * to replace data in the RX register (top of receive FIFO) with the incoming new data. + * Clear it to discard incoming new data and preserve old unread data. + + * + */ +ADI_SPI_RESULT adi_spi_SetReceiveOverflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RXOF); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_RXOF; + } + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Set the SPI transmit FIFO underflow mode. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] bFlag Flag to manage transmit FIFO underflow behaviour. + *\n - true Send zeroes on transmit FIFO underflow. + *\n - false Resend last data on transmit FIFO underflow. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Controls what to transmit when lacking valid data because the transmit FIFO is empty. + *\n Either zeros or the last valid data are transmitted. Set transmit FIFO underflow mode to send zeros. + *\n Clear it to resend the last transmitted data. + * + */ +ADI_SPI_RESULT adi_spi_SetTransmitUnderflow (ADI_SPI_CONST_HANDLE const hDevice, const bool bFlag) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if (true == bFlag) { + hDevice->pSpi->CTL |= (BITM_SPI_CTL_ZEN); + } else { + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_ZEN; + } + + return ADI_SPI_SUCCESS; +} + + + + + + +/*! + * @brief Set the SPI serial clock frequency. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * @param[in] Hertz Target frequency (in Hz) for SPI bitrate. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_INVALID_PARAM Specified frequency is out of range. + * - #ADI_SPI_BAD_SYS_CLOCK Unable to obtain PCLK which is needed to calculate the new bit rate. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Compute and set the internal SPI clock rate divider register to produce + *\n the desired serial clock frequency. Resulting frequency is subject to arithmetic rounding errors. + *\n Use #adi_spi_GetBitrate() to obtain the exact frequency produced, including rounding errors. + * + * @sa adi_spi_GetBitrate(). + */ +ADI_SPI_RESULT adi_spi_SetBitrate (ADI_SPI_CONST_HANDLE const hDevice, const uint32_t Hertz) +{ + uint32_t incoming_clock; + uint16_t Div; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + if( adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock) != ADI_PWR_SUCCESS) + { + return ADI_SPI_INVALID_HANDLE; + } + + /* requested rate needs to be 2x or less than incoming clock */ + if ((2U * Hertz) > incoming_clock) + { + return ADI_SPI_BAD_SYS_CLOCK; + } + + /* compute the SPI divider value */ + Div = (uint16_t) ((incoming_clock / Hertz) >> 1U) - 1U; /* '>>1' is really a divide by 2 */ + + /* range check that computed divider fits */ + if (Div != (Div & BITM_SPI_DIV_VALUE)) + { + return ADI_SPI_INVALID_PARAM; + } + + /* store it in core */ + hDevice->pSpi->DIV = Div; + + return ADI_SPI_SUCCESS; +} + + +/*! + * @brief Get the SPI serial clock frequency. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open() + * \n + * @param[out] pnBitrate Pointer to the location where Bitrate need to be written. + * + * @return + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Get the current serial clock frequency. The returned value is exact but + *\n may not exactly match the value set with #adi_spi_SetBitrate() due to + *\n computational round-off errors resulting from fixed register size and + *\n finite-precision arithmetic. + * + * @sa adi_spi_SetBitrate(). + */ +ADI_SPI_RESULT adi_spi_GetBitrate (ADI_SPI_CONST_HANDLE const hDevice, uint32_t* const pnBitrate) +{ + uint32_t incoming_clock; + ADI_PWR_RESULT ePwrResult; + uint32_t Div; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + Div = hDevice->pSpi->DIV; /* assumes this is always a right-justified value */ + + ePwrResult = adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK, &incoming_clock); + if(ePwrResult != ADI_PWR_SUCCESS) + { + *pnBitrate= 0u; + return(ADI_SPI_FAILURE); + } + *pnBitrate= (incoming_clock / (Div + 1U)) >> 1U; /* '>>1' is divide by 2 */ + return(ADI_SPI_SUCCESS); + +} + + +/*! + * @brief Set the chip select. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] eChipSelect An enum value representing the requested Chip Select. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_SUCCESS Call completed successfully. + * + * Sets the desired chip select to use for activating an external slave device. + * + * @note Chip select \a ADI_SPI0_CSn is reserved for SPI device 0 (SPI0) internal chip select line + * dedicated for communications with the UHF device. + * + */ +ADI_SPI_RESULT adi_spi_SetChipSelect (ADI_SPI_HANDLE const hDevice, const ADI_SPI_CHIP_SELECT eChipSelect) +{ + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + hDevice->ChipSelect = eChipSelect; + + return ADI_SPI_SUCCESS; +} + +/*! + * @brief Submit data buffers for SPI Master-Mode transaction in "Blocking mode".This function + *\n returns only after the data transfer is complete + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct #ADI_SPI_TRANSCEIVER. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_BUFFER_NOT_SUBMITTED [D] Failed to submit the buffer. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n + *\n Request a non-blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n + * @sa adi_spi_MasterSubmitBuffer(). + * @sa ADI_SPI_TRANSCEIVER + */ +ADI_SPI_RESULT adi_spi_MasterReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT eResult; + hDevice->bBlockingMode = true; + eResult = adi_spi_MasterSubmitBuffer(hDevice,pXfr); + hDevice->bBlockingMode = false; + if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u)) + { + eResult = ADI_SPI_HW_ERROR_OCCURRED; + } + return(eResult); +} + +/*! + * @brief Submit data buffers for SPI Master-Mode transaction. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_IN_USE [D] DMA transaction already under way. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Request a blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + * + * + * @sa adi_spi_MasterReadWrite(). + * @sa adi_spi_isBufferAvailable() + * @sa ADI_SPI_TRANSCEIVER + */ + +ADI_SPI_RESULT adi_spi_MasterSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT result = ADI_SPI_SUCCESS; + volatile uint16_t nStatus; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + + if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver)) + { + return ADI_SPI_INVALID_POINTER; + } + + if( (pXfr->bRD_CTL == true) && (pXfr->TransmitterBytes > 16u)) + { + return ADI_SPI_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* Initialize the transaction. 'hDevice' must hold the transaction values as pXfr is owned by the application */ + hDevice->pTxBuffer = pXfr->pTransmitter; + hDevice->pRxBuffer = pXfr->pReceiver; + hDevice->TxRemaining = pXfr->TransmitterBytes; + hDevice->RxRemaining = pXfr->ReceiverBytes; + hDevice->TxIncrement = (uint8_t)pXfr->nTxIncrement; + hDevice->RxIncrement = (uint8_t)pXfr->nRxIncrement; + hDevice->bDmaMode = pXfr->bDMA; + hDevice->bRdCtlMode = pXfr->bRD_CTL; + hDevice->bTransferComplete = false; + hDevice->HWErrors = ADI_SPI_HW_ERROR_NONE; + + + /* + * + * TIM + * If set: initiate transfer with write to SPI_TX register + * If clear: initiate transfer with a read from SPI_RX register + * + * RFLUSH + * Clear this bit to ensure that incoming data is ignored + * + * TFLUSH + * Clear this not to ensure that transmitted data is not a zero (if SPI_CTL.ZEN is set) or last transmitted byte + * + */ + + + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH); + + /* + * If in DMA mode then make sure XFRDONE interrupt is not set. DMA mode will generate three interrupts + * TX DMA + * RX DMA + * XFRDONE + * + * There is a race condition between XFRDONE and DMA interrupts. They are on different clocks. + * + * SPI XfrDone is counted on SPI clock (SCL) edge, which is a fixed timing related to SPI bit protocol. + * But the DMA works upon system clock (HCLK) and it could finish on various timing upon SCL/HCLK ratio. + * And bus bandwidth (e.g., DMA hold off until processor frees up the bus). So SPI RX DMA done interrupt + * could be issued earlier or later than SPI XferDone interrupt. + * + */ + if( hDevice->bDmaMode==true ) { + /* The race condition has been between RX and XFRDONE. If there are no bytes to receive then */ + /* do not clear XFRDONE */ + if( hDevice->RxRemaining != 0u) { + hDevice->pSpi->IEN &= (uint16_t)~(BITM_SPI_IEN_XFRDONE); + } else { + hDevice->pSpi->IEN |= (BITM_SPI_IEN_XFRDONE); + } + + } else { + + /* In interrupt mode always enable XFRDONE */ + uint16_t activeInterrupts = BITM_SPI_IEN_XFRDONE; + /* Enable underflow on;y if sending bytes */ + if( hDevice->TxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_TXUNDR; + } + /* Enable overflow only if receiving bytes */ + if( hDevice->RxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_RXOVR; + } + + hDevice->pSpi->IEN |= activeInterrupts; + + /* + * In interrupt mode, when there is nothing to receive, need to initiate a transaction + * on an TX write only. Initiating on an RX read will start the transaction, but just for + * a single byte (and we're not sure why this is true) + */ + + if( hDevice->RxRemaining == 0u) { + hDevice->pSpi->CTL |= ( BITM_SPI_CTL_TIM ); + } + + } + + + /* STAT bits are cleared by writing a '1' to them. Clear any residual status*/ + nStatus = hDevice->pSpi->STAT; + hDevice->pSpi->STAT = nStatus; + + /* Make sure we are in master mode */ + hDevice->pSpi->CTL |= ( BITM_SPI_CTL_MASEN); + + /* Set ChipSelect */ + hDevice->pSpi->CS_CTL = hDevice->ChipSelect; + + StartTransaction(hDevice, pXfr); + + + /* block if required */ + if (hDevice->bBlockingMode == true) + { + SEM_PEND(hDevice,ADI_SPI_PEND_FAILED); + } + + return result; +} + +/*********************************************************************************************************/ +/* */ +/* SPI DRIVER Master Mode transaction start */ +/* */ +/*********************************************************************************************************/ + +static void StartTransaction(ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + /* Transaction completion is determined by the number of bytes to be received */ + uint16_t nCount; + + /* Effectively flush the FIFOs before the start of the next transaction */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + + /* Disable any prior notion of DMA */ + hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + + + /* + * If the transaction is DMA based then set up the DMA descriptors for this transaction + */ + + uint16_t dmaFlags = 0u; + + if( hDevice->bDmaMode == true) + { + dmaFlags = BITM_SPI_DMA_EN; + + uint16_t sz = pXfr->TransmitterBytes; + if( sz ) + { + uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber; + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber)); + + /* Disables source address decrement for TX channel */ + pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << TxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << TxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << TxChanNum; + + /* fill in the DMA RAM descriptors */ + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->pTransmitter + (sz - 2U)); + + pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX; + + pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + dmaFlags |= (BITM_SPI_DMA_TXEN); + } + + sz = pXfr->ReceiverBytes; + if( sz ) + { + + uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber; + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber)); + + /* Disables destination address decrement for RX channel */ + pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << RxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << RxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << RxChanNum; + + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX; + + pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->pReceiver + (sz - 2U)); + + pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + dmaFlags |= (BITM_SPI_DMA_RXEN ); + + } + } + + /* + * SPI CNT register + * Non Read Mode: Size of the entire transactions + * Read Mode: Size of the RX transaction + * + * RD_CTL.SZ + * Read Mode: Size of the TX transaction + */ + + hDevice->pSpi->RD_CTL = 0u; + if( hDevice->bRdCtlMode) + { + /* "Half Duplex Mode" */ + + /* The number of bytes to be transmitted */ + uint32_t nBytes = hDevice->TxRemaining - 1U; + + /* Enable RD_CTL and set the TX count for the half-duplex mode of operation */ + hDevice->pSpi->RD_CTL &= (uint16_t)~((uint16_t)(BITM_SPI_RD_CTL_TXBYTES << BITP_SPI_RD_CTL_TXBYTES)); + + hDevice->pSpi->RD_CTL |= (uint16_t)( (uint16_t)(nBytes << BITP_SPI_RD_CTL_TXBYTES) | + (uint16_t)(1 << BITP_SPI_RD_CTL_CMDEN)); + + /* RD_CTL requires continuous mode operation. */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_CON); + + /* CNT represent the number of bytes to receive */ + hDevice->pSpi->CNT = hDevice->RxRemaining; + + } + else + { + /* Full duplex mode of operation */ + if(hDevice->RxRemaining == 0u) + { + /* There is nothing to receive. Flush the RX FIFO and to ignore all incoming data */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH); + } + else if(hDevice->TxRemaining == 0u) + { + /* If there is nothing to transmit then clear the TX FIFO */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_TFLUSH); + } + else + { + /* Misra compliance: All if/else chains should end with a final else clause */ + } + + /* Set CNT to MAX of RX/TX */ + + nCount = hDevice->RxRemaining > hDevice->TxRemaining ? hDevice->RxRemaining : hDevice->TxRemaining; + hDevice->pSpi->CNT = (uint16_t)nCount; + + } + + + if( hDevice->bDmaMode == false) + { + /* Make sure that the application passed in a TX Buffer */ + if( hDevice->pTxBuffer != NULL) + { + /* interrupt mode: Fill in the FIFO */ + nCount = 0u; + while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u)) + { + /* grab the lead byte */ + hDevice->pSpi->TX = *hDevice->pTxBuffer; + /* modify tx pointer and buffer count prior to interrupt */ + hDevice->pTxBuffer += hDevice->TxIncrement; + /* decrement the byte count */ + hDevice->TxRemaining--; + nCount++; + } + } + + } else { + + hDevice->pSpi->DMA |= dmaFlags; + } + + if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM) + { + uint16_t byte ADI_UNUSED_ATTRIBUTE = hDevice->pSpi->RX; + } + + + NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn); + + return; +} + +/*! + * @brief Block until the SPI transaction is complete. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + *\n + * @param[out] pHWErrors Pointer to hardware error return variable. + *\n + * @return Status + * - #ADI_SPI_SUCCESS Call completed successfully. + * - #ADI_SPI_SEMAPHORE_FAILED Semaphore Pend failed + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_spi_MasterSubmitBuffer(). + * @sa adi_spi_SlaveSubmitBuffer(). + */ +ADI_SPI_RESULT adi_spi_GetBuffer( + ADI_SPI_HANDLE const hDevice, + uint32_t * const pHWErrors + ) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + *pHWErrors = ADI_SPI_HW_ERROR_NONE; + return ADI_SPI_INVALID_HANDLE; + } +#endif + + SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED); + *pHWErrors = hDevice->HWErrors; + return(ADI_SPI_SUCCESS); +} + +/*! + * @brief Get the SPI transaction completion status. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + *\n + * @param[out] bComplete Pointer to boolean variable that indicates + *\n - true DMA transmit sequence is complete. + *\n - false DMA transmit sequence is incomplete. + *\n + * @return Status + * - #ADI_SPI_SUCCESS Call completed successfully. + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * + * @sa adi_spi_MasterSubmitBuffer(). + * @sa adi_spi_SlaveSubmitBuffer(). + */ + +ADI_SPI_RESULT adi_spi_isBufferAvailable(ADI_SPI_CONST_HANDLE const hDevice, bool* const bComplete) +{ +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } +#endif + + *bComplete = hDevice->bTransferComplete; + return(ADI_SPI_SUCCESS); +} + +/*! + * @brief Submit data buffers for SPI Slave-Mode transaction. + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_IN_USE [D] DMA transaction already under way. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n Request a non-blocking transmit and receive of multiple data bytes + *\n over the SPI serial channel. Honours current blocking and DMA modes. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n The application must make a call to adi_spi_GetBuffer() to retrieve the buffer + *\n + *\n @note: + * + * @sa adi_spi_MasterReadWrite(). + * @sa adi_spi_EnableDmaMode(). + * @sa adi_spi_isBufferAvailable(). + * @sa adi_spi_GetBuffer(). + */ +ADI_SPI_RESULT adi_spi_SlaveSubmitBuffer (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + volatile uint16_t ADI_UNUSED_ATTRIBUTE byte; + uint32_t nCount = 0u; + +#ifdef ADI_DEBUG + if (ADI_SPI_VALIDATE_HANDLE(hDevice)) + { + return ADI_SPI_INVALID_HANDLE; + } + if ((NULL == pXfr->pTransmitter) && (NULL == pXfr->pReceiver)) + { + return ADI_SPI_INVALID_POINTER; + } + + if ((0u == pXfr->pTransmitter) && (0u == pXfr->pReceiver) ) + { + return ADI_SPI_INVALID_PARAM; + } + /* Return error if the RX buffer is not null and count is equal to zero or vice versa.*/ + if (((pXfr->pReceiver != NULL) && (pXfr->ReceiverBytes == 0u)) || ((pXfr->pReceiver == NULL) && ((pXfr->ReceiverBytes > 0u)))) + { + return ADI_SPI_INVALID_PARAM; + } + + /* Return error if the Tx buffer is not null and count is equal to zero or vice versa.*/ + if (((pXfr->pTransmitter != NULL) && (pXfr->TransmitterBytes == 0u)) || ((pXfr->pTransmitter == NULL) && (pXfr->TransmitterBytes > 0u))) + { + return ADI_SPI_INVALID_PARAM; + } + + /* DMA count register is only 8 bits, so block size is limited to 255 */ + if ((pXfr->bDMA==true) && (pXfr->TransmitterBytes != 0u) &&(((uint32_t)pXfr->pTransmitter&0x1U) !=0u ) ) + { + return ADI_SPI_INVALID_PARAM; + } + +#endif /* ADI_DEBUG */ + + /* Effectively flush the FIFOs before the start of the next transaction */ + hDevice->pSpi->CTL |= (BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_RFLUSH|BITM_SPI_CTL_TFLUSH); + + /* Shut down any DMA enables that are still lingering from a prior transaction */ + hDevice->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + + hDevice->bTransferComplete = false; + hDevice->pTxBuffer = pXfr->pTransmitter; + hDevice->pRxBuffer = pXfr->pReceiver; + hDevice->TxRemaining = pXfr->TransmitterBytes; + hDevice->RxRemaining = pXfr->ReceiverBytes; + hDevice->TxIncrement = (uint8_t)pXfr->nTxIncrement; + hDevice->RxIncrement = (uint8_t)pXfr->nRxIncrement; + hDevice->pSpi->CNT = (uint16_t)nCount; + hDevice->bDmaMode = pXfr->bDMA; + hDevice->bRdCtlMode = pXfr->bRD_CTL; + hDevice->HWErrors = ADI_SPI_HW_ERROR_NONE; + + + /* Configure SPI. First step is to clear CTL bits that may have been set previously */ + hDevice->pSpi->CTL &= (uint16_t)~(BITM_SPI_CTL_TIM | BITM_SPI_CTL_RFLUSH | BITM_SPI_CTL_TFLUSH | BITM_SPI_CTL_CON); + if( hDevice->TxRemaining == 0u ) + { + /* This will prevent TX underflow interrupts from occurring */ + hDevice->pSpi->CTL |= BITM_SPI_CTL_TFLUSH; + } + if( hDevice->RxRemaining == 0u ) + { + /* This will prevent data from entering RX. Also prevents overflow interrupts from occurring */ + hDevice->pSpi->CTL |= BITM_SPI_CTL_RFLUSH; + + /* If SPI_CTL.TIM is set, the Tx FIFO status causes the interrupt. */ + if( hDevice->bDmaMode != true) { + hDevice->pSpi->CTL |= BITM_SPI_CTL_TIM; + } + + } + + hDevice->pSpi->CNT = (uint16_t) hDevice->TxRemaining > hDevice->RxRemaining ? hDevice->TxRemaining : hDevice->RxRemaining; + + uint16_t nDMAFlags = 0u; + + if( hDevice->bDmaMode == true) + { + uint16_t sz = pXfr->TransmitterBytes; + if( sz ) + { + uint16_t TxChanNum = hDevice->pDevInfo->dmaTxChannelNumber; + + /* Enable the interrupt for the given DMA */ + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaTxIrqNumber)); + + /* Disables source address decrement for TX channel */ + pADI_DMA0->SRCADDR_CLR = 1U << TxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << TxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << TxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << TxChanNum; + + /* fill in the DMA RAM descriptors */ + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[TxChanNum].DMASRCEND = (uint32_t)(pXfr->pTransmitter + (sz - 2U)); + + pPrimaryCCD[TxChanNum].DMADSTEND = (uint32_t)&hDevice->pSpi->TX; + + pPrimaryCCD[TxChanNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U)<< DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + nDMAFlags |= (BITM_SPI_DMA_TXEN); + } + + sz = pXfr->ReceiverBytes; + if( sz ) + { + + uint16_t RxChanNum = hDevice->pDevInfo->dmaRxChannelNumber; + NVIC_EnableIRQ((IRQn_Type)(hDevice->pDevInfo->dmaRxIrqNumber)); + + /* Disables destination address decrement for RX channel */ + pADI_DMA0->DSTADDR_CLR = 1U << RxChanNum; + + /* Enable the channel */ + pADI_DMA0->EN_SET = 1U << RxChanNum; + + /* Enables SPI peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1U << RxChanNum; + + /* Set the primary as the current DMA descriptor */ + pADI_DMA0->ALT_CLR = 1U << RxChanNum; + + if( (sz & 1U) != 0u ) + { + /* DMA is performed on 16-bit data. Make sure the DMA engine is properly aligned to even counts */ + /* The SPI_CNT register will hold the "real" transfer count */ + sz++; + } + + pPrimaryCCD[RxChanNum].DMASRCEND = (uint32_t)&hDevice->pSpi->RX; + + pPrimaryCCD[RxChanNum].DMADSTEND = (uint32_t)(pXfr->pReceiver + (sz - 2U)); + + pPrimaryCCD[RxChanNum].DMACDC = (ADI_DMA_INCR_2_BYTE << DMA_BITP_CTL_DST_INC) | + (ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_2_BYTE << DMA_BITP_CTL_SRC_SIZE) | + ((sz/2U -1U) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + + nDMAFlags |= (BITM_SPI_DMA_RXEN ); + + } + } + + /* Make sure XFRDONE is shut down. This IEN has no affect in slave mode */ + hDevice->pSpi->IEN &= (uint16_t)~BITM_SPI_IEN_XFRDONE; + + if( hDevice->bDmaMode == false) { + /* Make sure we are not in continuous mode from a prior DMA transaction */ + hDevice->pSpi->CTL &= (uint16_t)~BITM_SPI_CTL_CON; + + + /* interrupt mode: Enable the UNDERFLOW and OVERFLOW interrupts */ + /* XFRDONE is invalid in slave mode */ + uint16_t activeInterrupts = 0u; + /* Enable underflow on;y if sending bytes */ + if( hDevice->TxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_TXUNDR; + } + /* Enable overflow only if receiving bytes */ + if( hDevice->RxRemaining ) { + activeInterrupts |= BITM_SPI_IEN_RXOVR; + } + hDevice->pSpi->IEN |= activeInterrupts; + + /* interrupt mode: Fill in the FIFO and enable the TX by a dummy read. */ + while((nCount < ADI_SPI_FIFO_SIZE) && (hDevice->TxRemaining != 0u)) + { + /* grab the lead byte */ + hDevice->pSpi->TX = *hDevice->pTxBuffer; + /* modify tx pointer and buffer count prior to interrupt */ + hDevice->pTxBuffer += hDevice->TxIncrement; + /* decrement the byte count */ + hDevice->TxRemaining--; + nCount++; + } + } else { + + /* DMA mode. Enable the controller */ + hDevice->pSpi->DMA |= (uint16_t)(BITM_SPI_DMA_EN | nDMAFlags); + } + + if((hDevice->pSpi->CTL & BITM_SPI_CTL_TIM) != BITM_SPI_CTL_TIM) + { + byte = hDevice->pSpi->RX; + } + NVIC_EnableIRQ(hDevice->pDevInfo->eIRQn); + + if (hDevice->bBlockingMode == true) + { + SEM_PEND(hDevice,ADI_SPI_SEMAPHORE_FAILED); + } + + return ADI_SPI_SUCCESS; +} + + + +/*! + * @brief Submit data buffers for SPI Slave-Mode transaction in "Blocking mode".This function + *\n returns only after the data transfer is complete + * + * @param[in] hDevice Device handle obtained from adi_spi_Open(). + * @param[in] pXfr Pointer to transfer data struct #ADI_SPI_TRANSCEIVER. + * + * @return Status + * - #ADI_SPI_INVALID_HANDLE [D] Invalid device handle parameter. + * - #ADI_SPI_BUFFER_NOT_SUBMITTED [D] Failed to submit the buffer. + * - #ADI_SPI_INVALID_POINTER [D] Invalid data pointer detected (NULL). + * - #ADI_SPI_INVALID_PARAM [D] Invalid size parameter detected (0). + * - #ADI_SPI_SUCCESS Call completed successfully. + * + *\n + *\n Request a non-blocking mode transmit and receive of multiple data bytes + *\n over the SPI serial channel. + *\n Buffer allocations are made by the calling code (the application). + *\n + *\n The transmit buffer is sent and the receive buffer is written according + *\n to the size and increment information contained by the \a pXft transfer + *\n data structure parameter. + *\n + *\n + * @sa adi_spi_SlaveSubmitBuffer(). + * @sa ADI_SPI_TRANSCEIVER + */ +ADI_SPI_RESULT adi_spi_SlaveReadWrite (ADI_SPI_HANDLE const hDevice, const ADI_SPI_TRANSCEIVER* const pXfr) +{ + ADI_SPI_RESULT eResult; + hDevice->bBlockingMode = true; + eResult = adi_spi_SlaveSubmitBuffer(hDevice,pXfr); + hDevice->bBlockingMode = false; + if( (eResult == ADI_SPI_SUCCESS) && (hDevice->HWErrors != 0u)) + { + eResult = ADI_SPI_HW_ERROR_OCCURRED; + } + return(eResult); +} + +/* + ***************************************************************************** + * SPI Internal Static Support Functions + *****************************************************************************/ + + + /*! \cond PRIVATE */ + + +/*----------------------------------------------------------------------------- + * + * SPI ISR + * + *----------------------------------------------------------------------------*/ + + + +static void common_SPI_Int_Handler (ADI_SPI_DEV_DATA_TYPE* pDD) +{ + + /* read status register - first thing */ + volatile uint16_t nFifoStatus = pDD->pSpi->FIFO_STAT; + uint16_t nErrorStatus = pDD->pSpi->STAT; + + uint16_t writableBytes; + uint16_t readableBytes; + + + + /* Trap overflow/underflow errors and terminate the current transaction if there is an error. */ + if( BITM_SPI_STAT_RXOVR == (BITM_SPI_STAT_RXOVR & nErrorStatus)) { + pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_RX_OVERFLOW; + } else if( BITM_SPI_STAT_TXUNDR == (BITM_SPI_STAT_TXUNDR & nErrorStatus)) { + pDD->HWErrors |= (uint32_t)ADI_SPI_HW_ERROR_TX_UNDERFLOW; + } + else + { + + /* calculate number of bytes that can be written to tx fifo */ + writableBytes = ADI_SPI_FIFO_SIZE - ((BITM_SPI_FIFO_STAT_TX & nFifoStatus) >> BITP_SPI_FIFO_STAT_TX); + /* calculate number of bytes to read from rx fifo */ + readableBytes = ((BITM_SPI_FIFO_STAT_RX & nFifoStatus) >> BITP_SPI_FIFO_STAT_RX); + + /* fill tx fifo */ + while ((writableBytes != 0u) && (pDD->TxRemaining != 0u)) + { + pDD->pSpi->TX = *pDD->pTxBuffer; + pDD->pTxBuffer += pDD->TxIncrement; + pDD->TxRemaining--; + writableBytes--; + } + + /* + * Now focus on the RX FIFO but only if we are not in RD_CTL mode OR, if we + * are in RD_CTL mode, TX bytes are all transmitted + */ + + if( (pDD->bRdCtlMode==false) || (pDD->TxRemaining==0u) ) + { + /* empty rx fifo */ + while ((readableBytes != 0u) &&(pDD->RxRemaining != 0u)) + { + + *pDD->pRxBuffer = (uint8_t) pDD->pSpi->RX; + pDD->pRxBuffer += pDD->RxIncrement; + pDD->RxRemaining--; + readableBytes--; + } + } + } + + + /* Terminate the transaction and notify the caller + * 1) Master mode: If there are no more bytes to RX or TX and XFRDONE is set + * 2) Slave mode: If there are no more bytes to RX or TX (XFRDONE is invalid in slave mode) + * 3) If there was a HW error + */ + bool terminate = false; + if( (pDD->RxRemaining == 0u) && (pDD->TxRemaining == 0u)) + { + if( BITM_SPI_CTL_MASEN == (pDD->pSpi->CTL & BITM_SPI_CTL_MASEN )) + { + /* Master mode */ + if( BITM_SPI_STAT_XFRDONE == (pDD->pSpi->STAT & BITM_SPI_STAT_XFRDONE )) + { + /* Master mode XFRDONE */ + terminate = true; + } + } else { + /* Slave mode - we're all done here */ + terminate = true; + } + } + + if( terminate || (pDD->HWErrors != (uint32_t)ADI_SPI_HW_ERROR_NONE)) + { + + /* Clear possible interrupt sources: XFRDONE and underflow and overflow */ + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + + } + + /* All interrupts are cleared by a write of 1 to the status register bits (W1C) */ + pDD->pSpi->STAT = nErrorStatus; + +#if defined(ADI_CYCLECOUNT_SPI_ISR_ENABLED) && (ADI_CYCLECOUNT_SPI_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPI); +#endif + + + +} + + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pCBParam; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_INVALID_DESCR; + break; + default: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_RX_CHAN_DMA_UNKNOWN_ERROR; + break; + } +} + + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_SPI_HANDLE hDevice = (ADI_SPI_HANDLE) pArg; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_INVALID_DESCR; + break; + default: + hDevice->HWErrors |= ADI_SPI_HW_ERROR_TX_CHAN_DMA_UNKNOWN_ERROR; + break; + } +} + + +/*! + * @brief SPI0 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI0 interrupt handler. + */ +void SPI0_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[0].hDevice ); + ISR_EPILOG(); +} + + +/*! + * @brief SPI1 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI1 interrupt handler. + */ +void SPI1_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[1].hDevice); + ISR_EPILOG(); +} + +/*! + * @brief SPI2 Interrupt Handler. + * + * @return void. + * + * Overrides default SPI2 interrupt handler. + */ +void SPI2_Int_Handler(void) { + ISR_PROLOG(); + common_SPI_Int_Handler(spi_device_info[2].hDevice ); + ISR_EPILOG(); +} + + +/* + ////////////////////////////////////////////////////////////////////////////// + ////////////////////////// DMA-RELATED /////////////////////////////////// + ////////////////////////////////////////////////////////////////////////////// +*/ + + +/* + * SPI DMA interrupt handlers + */ + + +#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==1u) +void DMA_SPI0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +/* Master mode DMA ISR */ +void DMA_SPI0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif +#if defined(ADI_SPI0_MASTER_MODE) && (ADI_SPI0_MASTER_MODE==0u) +/* Slave mode DMA ISRs */ +void DMA_SPI0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->TxRemaining = 0u; + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} +void DMA_SPI0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[0].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + + + +#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==1u) +/* Master mode DMA ISR */ +void DMA_SPI1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +void DMA_SPI1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif + + +#if defined(ADI_SPI1_MASTER_MODE) && (ADI_SPI1_MASTER_MODE==0u) +/* Slave mode DMA ISRs */ +void DMA_SPI1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->TxRemaining = 0u; + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} + + +void DMA_SPI1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[1].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + +#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==1u) +/* Master mode DMA ISR */ + +void DMA_SPIH_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); +} + +void DMA_SPIH_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + /* Master mode: Now allow the XFRDONE interrupt to occur. It's the SPI ISR that really ends the transaction */ + /* The slave mode is not affected by this setting */ + pDD->pSpi->IEN |= BITM_SPI_IEN_XFRDONE; + ISR_EPILOG(); +} +#endif +#if defined(ADI_SPI2_MASTER_MODE) && (ADI_SPI2_MASTER_MODE==0u) +/* Master mode DMA ISRs */ + +void DMA_SPIH_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->TxRemaining = 0u; + ISR_EPILOG(); + if( pDD->RxRemaining == 0) + { + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + } + ISR_EPILOG(); +} + +void DMA_SPIH_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_SPI_HANDLE pDD = spi_device_info[2].hDevice; + pDD->RxRemaining = 0u; + /* Disable DMA */ + pDD->pSpi->DMA &= (uint16_t)~(BITM_SPI_DMA_EN | BITM_SPI_DMA_RXEN | BITM_SPI_DMA_TXEN); + pDD->pSpi->IEN &= ~(BITM_SPI_IEN_XFRDONE|BITM_SPI_IEN_RXOVR|BITM_SPI_IEN_TXUNDR); + pDD->bTransferComplete = true; + NVIC_DisableIRQ(pDD->pDevInfo->eIRQn); + + /* If a callback is registered notify the buffer processed event to the application */ + if(NULL != pDD->pfCallback ){ + pDD->pfCallback(pDD->pCBParam, pDD->HWErrors, NULL); + } + else + { + SEM_POST(pDD); + } + ISR_EPILOG(); +} +#endif + + + + +/*! \endcond */ + + +/* @} */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c new file mode 100755 index 00000000000..ecbcb00b62e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c @@ -0,0 +1,163 @@ +/* + ***************************************************************************** + * @file: adi_spi_data.c + * @brief: Data declaration for SPORT Device Driver + ***************************************************************************** + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifndef _ADI_SPI_DATA_C_ +#define _ADI_SPI_DATA_C_ + + /*! \cond PRIVATE */ + +#include +#include "adi_spi_def.h" +#include "adi_spi_config.h" +#include + +/* Stores the information about the specific device */ +static ADI_SPI_DEVICE_INFO spi_device_info [ADI_SPI_NUM_INSTANCES]= +{ + { + DMA0_CH4_DONE_IRQn, + SPI0_TX_CHANn, + DMA0_CH5_DONE_IRQn, + SPI0_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI0, + SPI0_EVT_IRQn, + NULL + }, + { + DMA0_CH6_DONE_IRQn, + SPI1_TX_CHANn, + DMA0_CH7_DONE_IRQn, + SPI1_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI1, + SPI1_EVT_IRQn, + NULL + }, + + { + DMA0_CH0_DONE_IRQn, + SPI2_TX_CHANn, + DMA0_CH1_DONE_IRQn, + SPI2_RX_CHANn, + (volatile ADI_SPI_TypeDef *)pADI_SPI2, + SPI2_EVT_IRQn, + NULL + } +}; + +/* SPI Application configuration array */ +static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] = +{ + /* Initialize SPI0 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI0_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI0_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI0_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI0_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI0_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI0_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI0_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI0_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI0_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI0_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI0_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI0_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI0_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI0_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + }, + /* Initialize SPI1 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI1_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI1_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI1_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI1_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI1_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI1_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI1_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI1_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI1_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI1_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI1_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI1_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI1_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI1_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + }, + /* Initialize SPI2 Instance configuration. */ + { + /**** SPI_CFG register configuration *** */ + (( ADI_SPI2_CFG_ENABLE << BITP_SPI_CTL_SPIEN ) | + ( ADI_SPI2_CFG_CLK_PHASE << BITP_SPI_CTL_CPHA ) | + ( ADI_SPI2_CFG_CLK_POLARITY << BITP_SPI_CTL_CPOL ) | + ( ADI_SPI2_CFG_WIRED_OR << BITP_SPI_CTL_WOM ) | + ( ADI_SPI2_CFG_LSB_MSB << BITP_SPI_CTL_LSB ) | + ( ADI_SPI2_CFG_TRANSFER_INITIATE << BITP_SPI_CTL_TIM ) | + ( ADI_SPI2_CFG_TX_UNDERFLOW << BITP_SPI_CTL_ZEN ) | + ( ADI_SPI2_CFG_RX_OVERFLOW << BITP_SPI_CTL_RXOF ) | + ( ADI_SPI2_CFG_MISO_ENABLE << BITP_SPI_CTL_OEN ) | + ( ADI_SPI2_CFG_LOOPBACK << BITP_SPI_CTL_LOOPBACK ) | + ( ADI_SPI2_CFG_CONTINUOUS << BITP_SPI_CTL_CON ) | + ( ADI_SPI2_CFG_RX_FLUSH << BITP_SPI_CTL_RFLUSH ) | + ( ADI_SPI2_CFG_TX_FLUSH << BITP_SPI_CTL_TFLUSH ) | + ( ADI_SPI2_CFG_CSERR_RESET << BITP_SPI_CTL_CSRST )), + + /**** SPI_DIV buad rate selection register *** */ + (((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\ + << BITP_SPI_DIV_VALUE ) + } +}; + +/*! \endcond */ + +#endif /* _ADI_SPI_DATA_C_ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h new file mode 100755 index 00000000000..8cbbf1b8d7e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_def.h @@ -0,0 +1,148 @@ +/*! + ***************************************************************************** + * @file: adi_spi_def.h + * @brief: SPI Device Driver definition + ***************************************************************************** +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_SPI_DEF_H_ +#define ADI_SPI_DEF_H_ + + + +#include + +#define ADI_SPI_NUM_INSTANCES (3u) +#define ADI_SPI_FIFO_SIZE (8u) + + + /*! \cond PRIVATE */ + +/* + ***************************************************************************** + * SPI Bitrate Initializer. Sets a default serial clockrate for the SPI channel. + *****************************************************************************/ +/* #define ADI_SPI_BITRATE_INITIALIZER 4000000 // 4MHz default bitrate */ +#define ADI_SPI_BITRATE_INITIALIZER 250000u /* depends on processor */ + +/* + ***************************************************************************** + * SPI0/SPI1 Control Register Initializer. This macro configures default + * settings for the SPI configuration control register when operated in Master-mode. + *****************************************************************************/ +/* SPI master DMA mode control configuration */ +#define ADI_SPI_MASTERCON_INITIALIZER BITM_SPI_CTL_MASEN + +/* + ***************************************************************************** + * SPI0/SPI1 Control Register Initializer. This macro configures default + * settings for the SPI configuration control register when operated in Slave-mode. + *****************************************************************************/ + #define ADI_SPI_SLAVECON_INITIALIZER BITM_SPI_CTL_OEN \ + | BITM_SPI_CTL_ZEN \ + | BITM_SPI_CTL_SPIEN + +/* 16-bit DMA... (two-byte size and increment) */ +#define ADI_DMA_DATA_WIDTH ADI_DMA_WIDTH_2_BYTE /*!< DMA data attribute */ +#define ADI_DMA_DATA_INCREMENT ADI_DMA_INCR_HALFWORD /*!< DMA data attribute */ + + + +/*! + ***************************************************************************** + * SPI Configuration structure. + *****************************************************************************/ +typedef struct ADI_SPI_CONFIG +{ + uint16_t SPI_CTL; /*!< SPI_CTL register configuration. */ + uint16_t SPI_DIV; /*!< SPI_DIV register. */ +} ADI_SPI_CFG_TYPE; + +/*! SPI device information */ + +typedef struct __ADI_SPI_DEVICE_INFO +{ + const uint16_t dmaTxIrqNumber; /* DMA channel ID-Tx */ + const uint16_t dmaTxChannelNumber; /* Tx */ + const uint16_t dmaRxIrqNumber; /* DMA channel ID-Rx */ + const uint16_t dmaRxChannelNumber; /* DMA channel ID-Rx */ + volatile ADI_SPI_TypeDef *pSpiRegs; /* Base address of the SPI registers */ + const IRQn_Type eIRQn; /* IRQn */ + ADI_SPI_HANDLE hDevice; /* SPI handle */ +}ADI_SPI_DEVICE_INFO; + + +/*! \struct ADI_SPI_DEV_DATA_TYPE SPI Device instance data structure */ +typedef struct __ADI_SPI_DEV_DATA_TYPE +{ + + /* device attributes */ + volatile ADI_SPI_TypeDef *pSpi; /*!< track MMR device pointer */ + ADI_SPI_DEVICE_INFO *pDevInfo; + + /* Callback and Callback parameters */ + ADI_CALLBACK pfCallback; /*!< Callback address */ + void * pCBParam; /*!< Callback parameter */ + /* The last recorded SPI event */ + uint32_t HWErrors; /*!< HW transaction status */ + + uint8_t* pTxBuffer; /*!< Transmit Buffer */ + uint8_t* pRxBuffer; /*!< Receive Buffer */ + uint16_t TxRemaining; /*!< Transmit Count */ + uint16_t RxRemaining; /*!< Receive Count */ + uint8_t TxIncrement; /*!< Transmit Increment */ + uint8_t RxIncrement; /*!< Receive Increment */ + + volatile bool bTransferComplete; /*!< Transfer Complete Flag */ + + bool bDmaMode; /*!< DMA mode flag */ + bool bRdCtlMode; /* Use half duplex read control feature */ + bool bBlockingMode; /*!< blocking mode flag */ + ADI_SPI_CHIP_SELECT ChipSelect; /*!< track chip select */ + + SEM_VAR_DECLR +} ADI_SPI_DEV_DATA_TYPE; + + + +/*! \endcond */ + +#endif /* ADI_SPI_DEF_H__ */ + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c new file mode 100755 index 00000000000..5c352c2bc50 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport.c @@ -0,0 +1,1771 @@ +/*! **************************************************************************** + * @file: adi_sport.c + * @brief: SPORT (Serial Port) device driver source file. + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*******************************************************************************/ + +/** @addtogroup SPORT_Driver SPORT Driver + * @{ + */ + +/*! \cond PRIVATE */ + +/*============= I N C L U D E S =============*/ + +#include +#include /* memset declaration */ + +#include +#include +#include +#include +#include "adi_sport_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* This isn't a header as such. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm050 (rule 14.2): a null statement shall only occur on a line by itself +* Needed for null expansion of ADI_INSTALL_HANDLER and others. +* +* Pm088 (rule 17.4): pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* +* Pm152: (MISRA C 2004 rule 17.4) array indexing shall only be applied to objects defined as an array type +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors + +*/ +#pragma diag_suppress=Pm026,Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm153 +#endif /* __ICCARM__ */ + +/*============== D A T A ===============*/ + +#define SPORT0_A_REGS ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_A) +#define SPORT0_B_REGS ((volatile ADI_SPORT_TypeDef*)REG_SPORT0_CTL_B) + +#define SPORT0_A_CFG { 0u, 0u, 0u, 0u, 0u } +#define SPORT0_B_CFG { 0u, 0u, 0u, 0u, 0u } + +#define DXS_FIFO_IS_FULL(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == BITM_SPORT_STAT_A_DXS) +#define DXS_FIFO_IS_EMPTY(STAT) (((STAT) & BITM_SPORT_STAT_A_DXS) == 0u) + +static ADI_SPORT_DEVICE_INFO gSportDevInfo [ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] = +{ + {/* registers configuration initial state DMA channel DMA IRQ SPORT IRQ handle */ + {SPORT0_A_REGS, SPORT0_A_CFG, ADI_SPORT_STATE_UNINITIALIZED, SPORT0A_CHANn, DMA0_CH2_DONE_IRQn, SPORT_A_EVT_IRQn, NULL}, + {SPORT0_B_REGS, SPORT0_B_CFG, ADI_SPORT_STATE_UNINITIALIZED, SPORT0B_CHANn, DMA0_CH3_DONE_IRQn, SPORT_B_EVT_IRQn, NULL}, + }, +}; + + +static const ADI_SPORT_CONFIG gSportCfg[ADI_SPORT_NUM_INSTANCES][ADI_SPORT_NUM_CHANNELS] = +{ + { /* configuration for SPORT 0 */ + /* Configuration for half-SPORT A */ + { /* SPORT_CTL register */ + ((ADI_CFG_SPORT0A_ENABLE_FSMUXSEL) << BITP_SPORT_CTL_A_FSMUXSEL) | + ((ADI_CFG_SPORT0A_ENABLE_CKMUXSEL) << BITP_SPORT_CTL_A_CKMUXSEL) | + ((ADI_CFG_SPORT0A_LSB_FIRST) << BITP_SPORT_CTL_A_LSBF) | + ((ADI_CFG_SPORT0A_SERIAL_WLEN - 1u) << BITP_SPORT_CTL_A_SLEN) | + ((ADI_CFG_SPORT0A_INTERNAL_CLK) << BITP_SPORT_CTL_A_ICLK) | + ((ADI_CFG_SPORT0A_OPERATION_MODE) << BITP_SPORT_CTL_A_OPMODE) | + ((ADI_CFG_SPORT0A_CLOCK_EDGE) << BITP_SPORT_CTL_A_CKRE) | + ((ADI_CFG_SPORT0A_FS_REQUIRED) << BITP_SPORT_CTL_A_FSR) | + ((ADI_CFG_SPORT0A_INTERNAL_FS) << BITP_SPORT_CTL_A_IFS) | + ((ADI_CFG_SPORT0A_DATA_INDEPENDENT_FS) << BITP_SPORT_CTL_A_DIFS) | + ((ADI_CFG_SPORT0A_ACTIVE_LOW_FS) << BITP_SPORT_CTL_A_LFS) | + ((ADI_CFG_SPORT0A_LATE_FS) << BITP_SPORT_CTL_A_LAFS) | + ((ADI_CFG_SPORT0A_ENABLE_PACKING) << BITP_SPORT_CTL_A_PACK) | + ((ADI_CFG_SPORT0A_FS_ERROR_OPERATION) << BITP_SPORT_CTL_A_FSERRMODE) | + ((ADI_CFG_SPORT0A_GATED_CLOCK) << BITP_SPORT_CTL_A_GCLKEN), + + /* SPORT_DIV register */ + ((ADI_CFG_SPORT0A_CLOCK_DIVISOR) << BITP_SPORT_DIV_A_CLKDIV) | + ((ADI_CFG_SPORT0A_FS_DIVISOR) << BITP_SPORT_DIV_A_FSDIV), + + /* SPORT_CONVT register */ + ((ADI_CFG_SPORT0A_CONVT_WIDTH) << BITP_SPORT_CNVT_A_WID) | + ((ADI_CFG_SPORT0A_CONVT_POLARITY) << BITP_SPORT_CNVT_A_POL) | + ((ADI_CFG_SPORT0A_CONVT_FS_DURATION) << BITP_SPORT_CNVT_A_CNVT2FS), + + /* Default DMA data size for SPORT */ + ADI_DMA_WIDTH_4_BYTE, + + /* Default DMA data increment for SPORT */ + ADI_DMA_INCR_4_BYTE + }, + + /* Configuration for half-SPORT B */ + { /* SPORT_CTL register */ + ((ADI_CFG_SPORT0B_LSB_FIRST) << BITP_SPORT_CTL_B_LSBF) | + ((ADI_CFG_SPORT0B_SERIAL_WLEN - 1u) << BITP_SPORT_CTL_B_SLEN) | + ((ADI_CFG_SPORT0B_INTERNAL_CLK) << BITP_SPORT_CTL_B_ICLK) | + ((ADI_CFG_SPORT0B_OPERATION_MODE) << BITP_SPORT_CTL_B_OPMODE) | + ((ADI_CFG_SPORT0B_CLOCK_EDGE) << BITP_SPORT_CTL_B_CKRE) | + ((ADI_CFG_SPORT0B_FS_REQUIRED) << BITP_SPORT_CTL_B_FSR) | + ((ADI_CFG_SPORT0B_INTERNAL_FS) << BITP_SPORT_CTL_B_IFS) | + ((ADI_CFG_SPORT0B_DATA_INDEPENDENT_FS) << BITP_SPORT_CTL_B_DIFS) | + ((ADI_CFG_SPORT0B_ACTIVE_LOW_FS) << BITP_SPORT_CTL_B_LFS) | + ((ADI_CFG_SPORT0B_LATE_FS) << BITP_SPORT_CTL_B_LAFS) | + ((ADI_CFG_SPORT0B_ENABLE_PACKING) << BITP_SPORT_CTL_B_PACK) | + ((ADI_CFG_SPORT0B_FS_ERROR_OPERATION) << BITP_SPORT_CTL_B_FSERRMODE) | + ((ADI_CFG_SPORT0B_GATED_CLOCK) << BITP_SPORT_CTL_B_GCLKEN), + + /* SPORT_DIV register */ + ((ADI_CFG_SPORT0B_CLOCK_DIVISOR) << BITP_SPORT_DIV_B_CLKDIV) | + ((ADI_CFG_SPORT0B_FS_DIVISOR) << BITP_SPORT_DIV_B_FSDIV), + + /* SPORT_CONVT register */ + ((ADI_CFG_SPORT0B_CONVT_WIDTH) << BITP_SPORT_CNVT_B_WID) | + ((ADI_CFG_SPORT0B_CONVT_POLARITY) << BITP_SPORT_CNVT_B_POL) | + ((ADI_CFG_SPORT0B_CONVT_FS_DURATION) << BITP_SPORT_CNVT_B_CNVT2FS), + + /* Default DMA data size for SPORT */ + ADI_DMA_WIDTH_4_BYTE, + + /* Default DMA data increment for SPORT */ + ADI_DMA_INCR_4_BYTE + } + } +}; + +/*! \endcond */ + +/*============= C O D E =============*/ + +extern void SPORT0A_Int_Handler(void); /*!< Interrupt handler for the SPORT0-A */ +extern void SPORT0B_Int_Handler(void); /*!< Interrupt handler for the SPORT0-B */ +extern void DMA_SPORT0A_Int_Handler(void); /*!< DMA handler for the SPORT0-A */ +extern void DMA_SPORT0B_Int_Handler(void); /*!< DMA handler for the SPORT0-B */ + +/*============= L O C A L F U N C T I O N S =============*/ + +/*============= P U B L I C F U N C T I O N S =============*/ + +/** + * @brief Initialization function for SPORT device. + * @details Initialization function for SPORT device. This function must be + * called before operating any SPORT device. + * + * @param [in] nDevNum SPORT Device instance to be opened. + * @param [in] eChannel Channel ID of the SPORT device (A or B) + * @param [in] eDirection Direction of the SPORT operation (i.e Rx or Tx) + * @param [in] pMemory Pointer to a 32 bit aligned buffer containing + * ADI_SPORT_MEMORY_SIZE bytes. This buffer is + * required by the SPORT driver for its operations. + * The "ADI_SPORT_MEMORY_SIZE" varies based on the + * configuration. + * @param [in] nMemSize Size of the buffer to which "pMemory" points. + * @param [out] phDevice Pointer to a location where a handle to the + * opened SPORT driver can be stored. This handle + * will be used to identity a SPORT device when + * calling SPORT management functions. + * + * @return Status + * - #ADI_SPORT_SUCCESS Successful device initialization. + * - #ADI_SPORT_DEVICE_IN_USE Device already initialized. + * - #ADI_SPORT_FAILED Failed initialize a semaphore for managing device. + * - #ADI_SPORT_INVALID_DEVICE_NUM Invalid SPORT device identifier + * - #ADI_SPORT_INVALID_NULL_POINTER Invalid pointer (callback function or device handle). + * + * @sa adi_sport_Close() + */ +ADI_SPORT_RESULT adi_sport_Open( + const uint32_t nDevNum, + const ADI_SPORT_CHANNEL eChannel, + const ADI_SPORT_DIRECTION eDirection, + void *pMemory, + const uint32_t nMemSize, + ADI_SPORT_HANDLE * const phDevice + ) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + + assert(ADI_SPORT_MEMORY_SIZE == sizeof(ADI_SPORT_DEVICE)); /* validate the memory size macro */ +#ifdef ADI_DEBUG + if (nDevNum >= ADI_SPORT_NUM_INSTANCES) + { + result = ADI_SPORT_INVALID_DEVICE_NUM; /* SPORT identifier must be within [0..ADI_SPORT_NUM_INSTANCES-1] */ + } + else if (phDevice == NULL) + { + result = ADI_SPORT_INVALID_NULL_POINTER; /* the pointer to device handle must be valid */ + } + else if (ADI_SPORT_MEMORY_SIZE != nMemSize) + { + result = ADI_SPORT_FAILED; + } + else if (ADI_SPORT_STATE_UNINITIALIZED != gSportDevInfo[nDevNum][eChannel].eState) + { + result = ADI_SPORT_DEVICE_IN_USE; /* the device instance must not be in use */ + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_DEVICE * pDevice = pMemory; /* Pointer to the SPORT device instance (from supplied memory) */ + ADI_SPORT_DEVICE_INFO * sportInfo = &gSportDevInfo[nDevNum][eChannel]; /* SPORT info for HSPORT A or HSPORT B */ + ADI_SPORT_CONFIG const * sportCfg = &gSportCfg[nDevNum][eChannel]; /* SPORT configuration for HSPORT A or HSPORT B */ + + assert(eChannel < ADI_SPORT_NUM_CHANNELS); + + memset(pMemory, 0, nMemSize); /* clear the device instance data before initializing it */ + + pDevice->pSportInfo = sportInfo; /* Initialize the pointer which provides the device information (HSPORT A or HSPORT B). */ + pDevice->eDirection = eDirection; /* Initialize the direction (BEFORE calling sport_Configure)*/ + pDevice->nHwError = (uint32_t) ADI_SPORT_HW_NO_ERR; + + adi_dma_Init(); /* Set up the DMA Controller. */ + sport_Init(pDevice); /* Initialize the data transmission buffers */ + sport_Configure(pDevice,sportCfg); /* Configure the SPORT */ + + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(sportInfo->eDMAChnlID, sport_DmaErrorCallback, pDevice)) + { + adi_sport_Close(pDevice); + result = ADI_SPORT_DMA_REGISTER_FAILED; + } + + if (ADI_SPORT_SUCCESS == result) + { + ADI_SPORT_DEVICE_INFO * devInfo = &gSportDevInfo[nDevNum][eChannel]; + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + if (ADI_HALF_SPORT_A == eChannel) + { + SEM_CREATE(&pDevice->sportChannel, "SPORT0_A_SEM", ADI_SPORT_FAILED); + }else{ + SEM_CREATE(&pDevice->sportChannel, "SPORT0_B_SEM", ADI_SPORT_FAILED); + } + + /* Change the state of the specified device */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + devInfo->eState = ADI_SPORT_STATE_INITIALIZED; + devInfo->hDevice = pDevice; + ADI_EXIT_CRITICAL_REGION(); + *phDevice = pDevice; /* Return the device handle to the application */ + } + } + + return result; +} + +/** + * @brief Closes the operation of specified SPORT device. + * + * @details Closes the operation of specified SPORT device. + * Device need to be opened again for any further use. + * + * @param [in] hDevice SPORT device handle whose operation is to be closed. + * This handle was obtained when a SPORT device is opened + * successfully. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully closed the specified device. + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * - #ADI_SPORT_FAILED [D] SPORT device internal error. + * + * @note It is user's responsibility to free/reuse the memory supplied + * during the opening of the device. + * + * @sa adi_sport_Open() + */ +ADI_SPORT_RESULT adi_sport_Close(ADI_SPORT_HANDLE const hDevice) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; /* return code */ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS == (result=ValidateHandle(pDevice))) /* Validate the given handle */ +#endif /* ADI_DEBUG */ + { + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; + + /* Free up the device */ + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + NVIC_DisableIRQ(pSportInfo->eIRQn); /* Disable SPORT event interrupts. */ + NVIC_DisableIRQ(pSportInfo->eDMAn); /* Disable DMA SPORT interrupts. */ + pSportInfo->eState = ADI_SPORT_STATE_UNINITIALIZED; + pSportInfo->hDevice = NULL; /* Free up the device memory. */ + ADI_EXIT_CRITICAL_REGION(); + + SEM_DELETE(&pDevice->sportChannel, ADI_SPORT_FAILED); /* Delete SPORT channel semaphore. */ + + adi_dma_RegisterCallback(pSportInfo->eDMAChnlID, NULL, NULL); /* unregister the callback function in the DMA error handler */ + + pSportInfo->pSportRegs->CTL_A = 0u; + } + return result; +} + +/** + * @brief Submit the buffer for transmitting/receiving the data. This function can + * be used to submit the buffers for both transmitting and receiving. It will + * be returned after successfully submitting the buffer for transmitting data. + * User will be notified if a call back function is registered with an event code + * #ADI_SPORT_EVENT_RX_BUFFER_PROCESSED or #ADI_SPORT_EVENT_TX_BUFFER_PROCESSED" + * depending on the direction in which device is operating. + * + * @param [in] hDevice Device handle to SPORT device is obtained when a SPORT device is opened + * successfully. + * + * @param [in] pBuffer Pointer to buffer from where data need to be transmitted OR to which + * received data need to to be written. + * + * @param [in] nNumBytes Size in bytes of the data to be transmitted/received. + * @param [in] bDMA True if the buffer must be processed through DMA-driven SPORT operations. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Buffer successfully submitted to the specified SPORT. + * - #ADI_SPORT_INVALID_HANDLE Invalid SPORT device handle. + * - #ADI_SPORT_INVALID_PARAMETER Number of bytes is too large for a SPORT transfer or the buffer is mis-aligned + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED All the SPORT buffers are already being used + * + * @sa adi_sport_GetBuffer() + * + */ +ADI_SPORT_RESULT adi_sport_SubmitBuffer(ADI_SPORT_HANDLE const hDevice, + void * const pBuffer, + uint32_t const nNumBytes, + bool const bDMA + ) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* pointer to SPORT device instance */ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; /* return code */ + +#ifdef ADI_DEBUG + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; /* short cut to SPORT configuration */ + + if(ADI_SPORT_SUCCESS != (result=ValidateHandle(hDevice))) /* validate the given handle */ + { + } + else if ( ((2u >= nNumBytes) && ((pDevice->pSportInfo->pSportRegs->CTL_A & BITM_SPORT_CTL_A_OPMODE) != 0u)) + || (0u != (nNumBytes & ~(BITM_SPORT_NUMTRAN_A_VALUE))) /* buffer size limited by SPORT transmission capabilities */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; + } + else +#endif /* ADI_DEBUG */ + /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has finished being processed in "adi_sport_GetBuffer()". + */ + if (NULL != pDevice->sportChannel.pFreeBuffer->pStartAddress) + { + result = ADI_SPORT_BUFFERS_NOT_SUBMITTED; + } + else + { +#ifdef ADI_DEBUG + const uint32_t addr = (uint32_t) pBuffer; + + if (true == bDMA) + { + /** + * Using SPORT configuration data, let's define information such as data + * size in bytes, data number, number of data and bytes in the DMA transfer + * being prepared, last byte position for the DMA transfer + * + * It's important to keep in mind that for buffer that contain too many data + * multiple DMA transfers are needed: it's up to the application to split the + * DMA requests in requests which have an appropriate number of data. + */ + const uint32_t dataSizeInBytes = GetBytesPerSportData(pSportCfg->CTL); + const uint32_t full = nNumBytes / dataSizeInBytes; /* number of full data to transmit/receive */ + const uint32_t partial = nNumBytes % dataSizeInBytes; /* number of partial data to transmit/receive */ + const uint32_t misaligned = addr % dataSizeInBytes; /* number of data to transmit/receive */ + + if ( (full > DMA_TRANSFER_LIMIT) /* number of data to process too large for DMA */ + || (0u != partial) /* buffer size not a multiple of dataSizeInBytes */ + || (0u != misaligned) /* buffer mis-aligned */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; + } + } else { + const uint32_t misAligned = addr % 4u; + const uint32_t invalidNum = nNumBytes % 4u; + + if ( (0u != misAligned) /* mis-aligned buffer */ + || (0u != invalidNum) /* number of bytes not a multiple of 32-bit */ + ) + { + result = ADI_SPORT_INVALID_PARAMETER; /* reject the buffer submission */ + } + } + if (ADI_SPORT_SUCCESS == result) +#endif /* ADI_DEBUG */ + { + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + + pSportChnl->pFreeBuffer->pStartAddress = pBuffer; /* Set the start address of the data buffer */ + pSportChnl->pFreeBuffer->nCount = nNumBytes; /* Set the buffer size */ + pSportChnl->pFreeBuffer->nIndex = 0u; /* Initialize the buffer index to zero (1st data in buffer) */ + pSportChnl->pFreeBuffer->bDMA = bDMA; /* Set the DMA boolean value. */ + pSportChnl->pFreeBuffer->bInUse = true; /* this buffer is now being used by the SPORT */ + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the next buffer. "pFreeBuffer" will only be updated + during the process of submitting a buffer or a read/write operation. + */ + pSportChnl->pFreeBuffer = pSportChnl->pFreeBuffer->pNextBuffer; + + /* Set the data transfer mode in case it was #ADI_DT_MODE_NONE. This + will be set back to #ADI_DT_MODE_NONE once this transaction is complete. + Then, if a buffer is not currently active, set up the interrupts for + this transaction. Otherwise if a buffer is currently active, this will + be taken care of in the ISR. + */ + if (pSportChnl->eDataTranferMode == ADI_DT_MODE_NONE) /* if the SPORT is available for a transmission */ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING; + + /* call an appropriate function based on mode in which device is operating */ + if (true == bDMA) /* select a DMA driven or a core driven non-blocking transmission */ + { + result = sport_SubmitBufferDmaMode(pDevice, pSportChnl->pFillBuffer); + } else { + result = sport_SubmitBufferIntMode(pDevice, pSportChnl->pFillBuffer); + } + } + + if(ADI_SPORT_SUCCESS != result) /* if an error occurred...*/ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + } + } + } + + return result; +} + +/* + * @brief Submit a buffer for SPORT Rx or Tx DMA driven transmission. + * + * @param [in] pDevice Pointer to SPORT device. + * + * @param [in] pBuffer Pointer to data transfer buffer information. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS buffer successfully submitted to the DMA associated with the SPORT. + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED Failed to submit the buffer to the DMA associated with the SPORT. + */ +/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, + ADI_DT_BUFF_INFO * pBuff) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + +#ifdef ADI_DEBUG + if ( (pBuff != pDevice->sportChannel.pFillBuffer) /* a submitted buffer should always be the current fill buffer */ + || (true != pBuff->bInUse) /* Processed buffers should already be marked as being used */ + || (0u != pBuff->nIndex) /* processing should start from index 0 */ + ) + { + result = ADI_SPORT_FAILED; + } + else +#endif + { + volatile ADI_SPORT_TypeDef* pSportRegs = pSportInfo->pSportRegs;/* short cut to SPORT registers */ + const uint32_t dmaChnlId = (uint32_t) pSportInfo->eDMAChnlID; /* identifier for the DMA channel to be used */ + const uint32_t dmaChnlBit = (1u << dmaChnlId); /* bit representing the DMA channel to be used */ + + /** + * Using SPORT configuration data, let's define information such as data + * size in bytes, data number, number of data and bytes in the DMA transfer + * being prepared, last byte position for the DMA transfer + * + * It's important to keep in mind that for buffer that contain too many data + * multiple DMA transfers are needed, so a buffer may have had part of its + * content already DMA-transferred: nIndex defines the position of the first + * byte in a buffer that has not been DMA-transferred yet. + */ + const uint32_t dmaIncNone = (uint32_t) ADI_DMA_INCR_NONE; + const uint32_t dmaDcc = (uint32_t) DMA_ENUM_CTL_CYCLE_CTL_BASIC; + const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); + + const uint32_t dataSizeInBytes = (1u << pSportCfg->DMA_WIDTH); /* number of bytes in each data to transmit/receive */ + uint32_t numDmaData = pBuff->nCount / dataSizeInBytes; /* number of DMA data to transmit/receive */ + const uint32_t dmaDataEnd = (pBuff->nCount - dataSizeInBytes); /* position of last <8,16,32>-bit data in the DMA transfer being setup */ + const uint32_t startAddress = (uint32_t) pBuff->pStartAddress; /* address of the first byte in the data buffer */ + const uint32_t numSportData = pBuff->nCount / bytesPerData; /* number of SPORT data to transmit/receive */ + + assert(pBuff->nCount == (numSportData * bytesPerData)); + assert(numSportData <= 0xFFFu); + assert(0u == (pBuff->nCount % dataSizeInBytes)); + assert(numDmaData <= DMA_TRANSFER_LIMIT); + assert((ADI_SPORT_DIR_RX == pDevice->eDirection) || (ADI_SPORT_DIR_TX == pDevice->eDirection)); + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + + pSportRegs->CTL_A = 0u; /* make sure SPORT is disable */ + pADI_DMA0->SRCADDR_CLR = dmaChnlBit; /* Clear source address decrement for TX channel DMA. */ + pADI_DMA0->EN_SET = dmaChnlBit; /* Enable channel DMA. */ + pADI_DMA0->RMSK_CLR = dmaChnlBit; /* Enable SPORT peripheral to generate DMA requests. */ + pADI_DMA0->ALT_CLR = dmaChnlBit; /* Set the primary control data structure as the current DMA descriptor. */ + pADI_DMA0->PRI_SET = dmaChnlBit; + + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + pPrimaryCCD[dmaChnlId].DMASRCEND = (uint32_t) &pSportRegs->RX_A; /* address of the last src data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMADSTEND = startAddress + dmaDataEnd; /* address of the last dst data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMACDC = + (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_DST_INC)) | /* destination address incremented by N bytes */ + (dmaIncNone << ((uint32_t)DMA_BITP_CTL_SRC_INC)); /* source address not incremented */ + } + else /* ADI_SPORT_DIR_TX */ + { + pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd; /* address of the last src data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMADSTEND = (uint32_t) &pSportRegs->TX_A; /* address of the last dst data in the DMA transfer being setup */ + pPrimaryCCD[dmaChnlId].DMACDC = + (dmaIncNone << ((uint32_t)DMA_BITP_CTL_DST_INC)) | /* destination address not incremented */ + (pSportCfg->DMA_INC << ((uint32_t)DMA_BITP_CTL_SRC_INC)); /* source address incremented by N byte */ + + /** + * Fix for data transmission when DMA is used with packed data. + */ + if (numDmaData < numSportData) + { + pPrimaryCCD[dmaChnlId].DMASRCEND = startAddress + dmaDataEnd + dataSizeInBytes; /* address of the last src data in the DMA transfer being setup */ + numDmaData++; + } + } + pPrimaryCCD[dmaChnlId].DMACDC |= + (pSportCfg->DMA_WIDTH << ((uint32_t)DMA_BITP_CTL_SRC_SIZE)) | /* source data size in bytes */ + (0u << ((uint32_t) DMA_BITP_CTL_R_POWER)) | + ((numDmaData - 1u) << ((uint32_t)DMA_BITP_CTL_N_MINUS_1)) | /* number of DMA transfers (minus 1) */ + (dmaDcc << ((uint32_t)DMA_BITP_CTL_CYCLE_CTL)); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED; + pSportRegs->NUMTRAN_A = numSportData; + + /* Enable SPORT DMA request interrupt for the SPORT tx channel. */ + NVIC_ClearPendingIRQ(pSportInfo->eIRQn); + NVIC_ClearPendingIRQ(pSportInfo->eDMAn); + + uint32_t ien_a = ((uint32_t)BITM_SPORT_IEN_A_SYSDATERR) | + ((uint32_t)BITM_SPORT_IEN_A_FSERRMSK) | + ((uint32_t)BITM_SPORT_IEN_A_DERRMSK); + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + /* Allow SPORT DMA interrupt handling to mark SPORT Rx as complete */ + NVIC_EnableIRQ(pSportInfo->eDMAn); + } + else + { + /* SPORT DMA Tx is complete when TFI is raised: enable TFI */ + ien_a |= ((uint32_t)BITM_SPORT_IEN_A_TF); + } + + NVIC_EnableIRQ(pSportInfo->eIRQn); + + pSportRegs->IEN_A = ien_a; + pSportRegs->CTL_A = pSportCfg->CTL | + ((uint32_t)BITM_SPORT_CTL_A_SPEN) | + ((uint32_t)BITM_SPORT_CTL_A_DMAEN); + ADI_EXIT_CRITICAL_REGION(); + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** Function prototype for */ +/* + * @brief Submit a buffer for SPORT Rx or Tx core driven transmission. + * + * @details Submit a buffer for SPORT Rx or Tx core driven transmission. + * The buffer must be 32-bit aligned and contain N * 32-bit data. + * + * @param [in] pDevice Pointer to SPORT device. + * + * @param [in] pBuffer Pointer to data transfer buffer information. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully submitted the buffer for data transfer. + * + * - #ADI_SPORT_BUFFERS_NOT_SUBMITTED No free descriptor for data transfer. + * + * + */ +static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; +#ifdef ADI_DEBUG + if ( (pBuff != pDevice->sportChannel.pFillBuffer) /* a submitted buffer should always be the current fill buffer */ + || (true != pBuff->bInUse) /* Processed buffers should already be marked as being used */ + || (0u != pBuff->nIndex) /* processing should start from index 0 */ + ) + { + result = ADI_SPORT_FAILED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + volatile ADI_SPORT_TypeDef * pSportRegs = pDevice->pSportInfo->pSportRegs; + uint32_t ctl = pSportCfg->CTL; + uint32_t bytesPerData = GetBytesPerSportData(ctl); + + /** + * Buffer can be too large for being processed in one submission. + * Consequently, if pBuff->nCount requires more than than 12-bit, + * multiple buffer submissions will be required by the application; + * the SPORT driver cannot process large buffers implicitly. + * The number of bytes in submitted buffers must be a multiple of 4 + * because data are processed by the SPORT driver as 32-bit data. + */ + + /* use the SPORT configuration to setup the SPORT registers */ + + pBuff->nCount /= bytesPerData; /* number of data to be transmitted */ + +#ifdef ADI_DEBUG + uint32_t pack = SPORT_GET_PACKEN(pSportCfg->CTL); + assert( ((9u > bytesPerData) && (1u == pack)) || ((17u > bytesPerData) && (2u == pack)) || (0u == pack)); +#endif + assert(pBuff->nCount <= 0xFFFu); + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pSportRegs->CTL_A = 0u; /* make sure SPORT is disable */ + pSportRegs->NUMTRAN_A = pBuff->nCount; + pDevice->pSportInfo->eState = ADI_SPORT_STATE_DATA_FLOW_ENABLED; + + /* Enable SPORT Interrupt. */ + NVIC_ClearPendingIRQ(pDevice->pSportInfo->eIRQn); + NVIC_EnableIRQ(pDevice->pSportInfo->eIRQn); + pSportRegs->IEN_A |= ((uint32_t) ( BITM_SPORT_IEN_A_DATA + | BITM_SPORT_IEN_A_SYSDATERR + | BITM_SPORT_IEN_A_FSERRMSK + | BITM_SPORT_IEN_A_DERRMSK + | BITM_SPORT_IEN_A_TF + ) + ); + pSportRegs->CTL_A = pSportCfg->CTL | ((uint32_t)BITM_SPORT_CTL_A_SPEN); + ADI_EXIT_CRITICAL_REGION(); + } + return result; +} + +/** + * @brief This function returns the address of a processed buffer. This + * is a blocking function: it waits until a buffer has been dealt + * with. This function returns an error if a callback function is + * registered. #adi_sport_IsBufferAvailable can be used as a peek + * function to know whether a buffer is available. + * + * @param [in] hDevice Device handle to SPORT device, obtained when a SPORT + * device is openedsuccessfully. + * + * @param [out] ppBuffer Pointer to a location where the the address of the + * buffer is to be written. Contains the address of an + * "empty" buffer (i.e the content of the buffer is + * transmitted) OR "filled" buffer which contains the + * received data. + * + * @param [out] pHwError Pointer to 32-bit value reporting SPORT/DMA events + * that can occur when processing buffer ppBuffer. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully returned. ppBuffer points + * to the address of the buffer. + * + * - #ADI_SPORT_FAILED Failed to get the buffer since device + * is operating in call back mode. + * ppBuffer points NULL. + * + * - #ADI_SPORT_HW_ERROR SPORT hardware or DMA error detected + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * @sa adi_sport_SubmitBuffer() + * @sa adi_sport_IsBufferAvailable() + * + */ +ADI_SPORT_RESULT adi_sport_GetBuffer(ADI_SPORT_HANDLE const hDevice, + void ** const ppBuffer, + uint32_t * pHwError) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + + *ppBuffer = NULL; +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice))) /* Validate the given handle */ + { + } + else +#endif /* ADI_DEBUG */ + if (NULL != pDevice->pfCallback) + { + result = ADI_SPORT_FAILED; + } else { + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + + SEM_PEND(pSportChnl,ADI_SPORT_FAILED); /* wait for a submitted buffer to be processed */ + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + *pHwError = pDevice->nHwError; + pDevice->nHwError = 0u; + *ppBuffer = pSportChnl->pActiveBuffer->pStartAddress; /* return the buffer start address in *ppBuffer */ + pSportChnl->pActiveBuffer->pStartAddress = NULL; /* clear the free buffer address */ + pSportChnl->pActiveBuffer = pSportChnl->pActiveBuffer->pNextBuffer; + ADI_EXIT_CRITICAL_REGION(); + if (0u != *pHwError) + { + result = ADI_SPORT_HW_ERROR; + } + } + return result; +} + +/** + * @brief Peek function to know whether an empty/filled buffer is available. Call to this + * function is valid only if the call back function is not registered. Call to this + * function results in error if a call back function is registered. + * + * @param [in] hDevice Device handle to SPORT device obtained when a SPORT device is opened + * successfully. + * + * @param [out] pbAvailable Pointer to a boolean variable. Contains "True" if there is an + * empty/filled buffer and a call to #adi_sport_GetBuffer is ensured to be + * successful. Contains "false" if there is no empty buffer. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_SPORT_INVALID_HANDLE Failed to retrieve the status of the buffer availability. + * - #ADI_SPORT_OPERATION_NOT_ALLOWED Function cannot be called (no buffer to be processed or callback function registered). + * - ADI_SPORT_PERIPHERAL_ERROR Hardware error detected + * + * @sa adi_sport_GetBuffer() + * @sa adi_sport_GetBuffer() + * + */ +ADI_SPORT_RESULT adi_sport_IsBufferAvailable(ADI_SPORT_HANDLE const hDevice, + bool * const pbAvailable) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + + *pbAvailable = false; +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result=ValidateHandle(pDevice))) /* Validate the given handle */ + { + } + else +#endif /* ADI_DEBUG */ + if (NULL != pDevice->pfCallback) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else + { + ADI_DT_BUFF_INFO * pActiveBuffer = pDevice->sportChannel.pActiveBuffer; + + if (pActiveBuffer->pStartAddress == NULL) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else if (false == pActiveBuffer->bInUse) /* this buffer has been processed by the SPORT */ + { + *pbAvailable = true; + } + else + { + } + } + return result; +} + +/** + * @brief Register and unregister a Callback function with the SPORT device driver. + * A registered call back function will be called, if not NULL, when a buffer + * is processed OR hardware error(s) encountered. + * + * @param [in] hDevice Device handle to SPORT device is obtained when a SPORT device is opened + * successfully. + * + * @param [in] pfCallback Function pointer to Callback function. Passing a NULL pointer will + * unregister the call back function. + * + * @param [in] pCBparam Call back function parameter. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully registered specified callback function. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_RegisterCallback(ADI_SPORT_HANDLE const hDevice, + ADI_CALLBACK const pfCallback, + void * const pCBparam) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + /* Check if the data flow is already enabled */ + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + /* Not allowed to register a callback if the data flow is enabled. */ + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + pDevice->pfCallback = pfCallback; /* Store the address of the callback function */ + pDevice->pCBParam = pCBparam; /* Store the call back parameter */ + ADI_EXIT_CRITICAL_REGION(); + } + return result; +} + +/** + * @brief Sets data format for the specified SPORT device. + * + * @details Sets data type,Big endian (MSB first) OR Little endian (LSB first) and word + * length(in bits) for the specified SPORT device.This function return error if the + * device is already enabled. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nWordLength Specify the word size of the data. Valid range is from + * 4(nWordLength = 3) to 32(nWordLength =31). + * + * @param [in] bLSBFirst Configure the specified SPORT device to operate either LSB + * first or MSB first. + * \n + * \n true : LSB first (Little endian) . + * \n + * \n false : MSB first (Big endian) + * + * @param [in] ePackMode Mode of packging need to configured. Please refer #ADI_SPORT_PACKING_MODE. + * + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured the device to operate in + * specified data format. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_INVALID_WORD_LENGTH [D] Invalid word size. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigData(ADI_SPORT_HANDLE const hDevice, + const uint8_t nWordLength, + const ADI_SPORT_PACKING_MODE ePackMode, + const bool bLSBFirst + ) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) /* Not allowed to change when data flow is enabled */ + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + if (nWordLength > SPORT_WORD_TRANSFER_LENGTH) + { + result = ADI_SPORT_INVALID_WORD_LENGTH; + } + else + { + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + const uint32_t bytesPerData = ((nWordLength < 9u) ? (1u) : ((nWordLength < 17u) ? (2u) : (4u))); + + const uint32_t wordPos = (uint32_t) BITP_SPORT_CTL_A_SLEN; + const uint32_t wordLen = (uint32_t) nWordLength; + const uint32_t ctlSlen = (wordLen - 1u) << wordPos; + const uint32_t packMode = (uint32_t) ePackMode; + const uint32_t ctlSlenBits = (0x1Fu << wordPos); + const uint32_t ctlDataMask = ~(BITM_SPORT_DATA_CONFIG | ctlSlenBits | BITM_SPORT_CTL_A_LSBF); + + uint32_t ctl = pDevice->pSportInfo->sportCfg.CTL; + ctl &= ctlDataMask; /* clear all the fields(i.e Set to "0" ) */ + ctl |= (packMode | ctlSlen); /* assign packing and slen information */ + if (true == bLSBFirst) + { + ctl |= BITM_SPORT_CTL_A_LSBF; /* set the the LSB first field */ + } + pDevice->pSportInfo->sportCfg.CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pDevice->pSportInfo->sportCfg.CTL); + + switch (bytesPerData) + { + case 1u: + if (((uint32_t) ADI_SPORT_8BIT_PACKING) == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE; + + assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode); + } + break; + + case 2u: + if (((uint32_t) ADI_SPORT_16BIT_PACKING) == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE; + + assert(((uint32_t) ADI_SPORT_NO_PACKING) == packMode); + } + break; + + default: + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + assert((4u == bytesPerData) || (((uint32_t) ADI_SPORT_NO_PACKING) == packMode)); + break; + } + } + return result; +} + +/** + * @brief Configure the clock for the specified SPORT device. + * + * @details Configure the SPORT device to use the "internal/external " rising/falling clock + * edge,clock edge and for enabling the gated Clock Mode. + * + * @details fspclk = fsclk/(2*( nClockRatio + 1)) + * + * @details fspclk: frequency of SPORT clock + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nClockRatio The value which determines the ratio between System clock and SPORT + * clock as explained above. + * + * + * @param [in] bUseIntlClock Boolean flag to indicate whether to use internal clock or external + * clock for data transmission. By default, device is configured to use + * the external clock. + * \n + * \n true : Device configured to use Internal clock. + * \n + * \n false : Device configured to use external clock.. + * + * @param [in] bRisingEdge Boolean flag to indicate whether to drive data and internal frame + * sync with rising edge OR falling edge of SP clock. + * \n + * \n true : Use falling edge of the clock. + * \n + * \n false : Use rising edge of the clock. + * + * @param [in] bGatedClk Boolean flag to indicate whether to enable/disable gated clock for + * the specified SPORT channel.Ignored in Multi channel mode. Clock will + * be active only when active data is getting transmitted or received + * when this mode is enabled. + * \n true : Enable gated clock mode. + * \n + * \n false : Disable gated clock mode. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured clock for the specified device. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigClock(ADI_SPORT_HANDLE const hDevice, + const uint16_t nClockRatio, + const bool bUseIntlClock, + const bool bRisingEdge, + const bool bGatedClk) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ + +#ifdef ADI_DEBUG + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t clockRatio = (uint32_t) nClockRatio; + + uint32_t ctl = pSportCfg->CTL; + uint32_t dv = pSportCfg->DIV; + + ctl &= ~BITM_SPORT_CLOCK_CONFIG; /* clear all clock configuration fields */ + + dv &= ~BITM_SPORT_DIV_A_CLKDIV; + dv |= (clockRatio & BITM_SPORT_DIV_A_CLKDIV); /* update the clock divisior value */ + + if (true == bUseIntlClock) + { + ctl |= BITM_SPORT_CTL_A_ICLK; /* select the internal clock */ + } + if (true == bRisingEdge) + { + ctl |= BITM_SPORT_CTL_A_CKRE; /* select the rising edge of the clock */ + } + if (true == bGatedClk) + { + ctl |= BITM_SPORT_CTL_A_GCLKEN; /* Enable the Gated clock */ + } + pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv; /* DIV value set */ + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** + * @brief Frame Sync(FS) configuration for the specified SPORT. + * + * @details Configure the SPORT to use internal/external frame sync,level/edge sensitive + * early/late frame sync etc. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nFsDivisor The value which decides the number of SPORT clock cycles between + * each frame count. + * + * @param [in] bFSRequired Boolean flag to indicate whether frame sync required OR not to + * the frame sync for the data transfer. + * \n + * \n true : Device requires a frame sync for its operation. + * \n + * \n false : Device does not requires a frame sync for its operation + * \n + * \n + * + * @param [in] bInternalFS Boolean flag to indicate whether to configure the specified SPORT + * device to use the internal frame sync OR external frame sync as + * below. + * \n + * \n true : Use internal frame sync. + * \n + * \n false : Use external frame sync + * \n + * \n + * + * @param [in] bDataFS Boolean flag to indicate whether to configure the specified SPORT + * device to use the data-independent frame sync OR Serial port uses + * a data-dependent frame sync. Valid only if the specified device is + * in "transmit"(TX)mode . Ignored if the device is opened in + * "receive"(RX) mode. + * \n + * \n true : Use data-independent frame sync. + * \n + * \n false : Use data-dependent frame sync. + * \n + * \n + * + * @param [in] bActiveLowFS Boolean flag to indicate whether to configure the specified SPORT + * device for active low frame sync OR active high frame sync. Call + * to this function will return error if SPORT is configured in I2S + * mode. + * \n + * \n true : Use active low frame sync. + * \n + * \n false : Use active high frame sync. + * \n + * \n + * + * @param [in] bLateFS Boolean flag to indicate whether to use the late frame sync OR + * Early frame sync. + * \n + * \n true : Use late frame sync. + * \n + * \n false : Use Early frame sync. + * \n + * \n + * +* @param [in] bFSErrorOperation Frame Sync Error Operation. This + *\n decides the way the SPORT responds when a frame sync error occurs. + * \n + * \n true : When frame Sync error occurs, discard the receive data. + * \n + * \n false : Flag the Frame Sync error and continue normal operation + * \n + * \n + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully configured the frame sync requirement. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigFrameSync(ADI_SPORT_HANDLE const hDevice, + const uint16_t nFsDivisor, + const bool bFSRequired, + const bool bInternalFS, + const bool bDataFS, + const bool bActiveLowFS, + const bool bLateFS, + const bool bFSErrorOperation) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *) hDevice; /* Pointer to SPORT device instance */ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + +#ifdef ADI_DEBUG + /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if(pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + const uint32_t fsDivisor = (uint32_t) nFsDivisor; + + uint32_t ctl = pSportCfg->CTL; + uint32_t dv = pSportCfg->DIV; + + dv &= ~BITM_SPORT_DIV_A_FSDIV; /* clear all the fields of frame sync */ + dv |= (fsDivisor << BITP_SPORT_DIV_A_FSDIV); + + ctl &= ~BITM_SPORT_FS_CONFIG; /* clear all the fields of frame sync */ + + if ((ADI_SPORT_DIR_RX == pDevice->eDirection) || (true == bDataFS)) + { + ctl |= BITM_SPORT_CTL_A_DIFS; /* Set this bit when SPORT is opened in RX mode */ + } + if (true == bFSRequired) /* "Frame sync required" is reserved when device */ + { /* is operating in I2S and MC mode */ + ctl |= BITM_SPORT_CTL_A_FSR; /* Frame Sync(FS) is required */ + } + if (true == bInternalFS) + { + ctl |= BITM_SPORT_CTL_A_IFS; /* Select the internal Frame Sync(FS)*/ + } + if (true == bActiveLowFS) + { + ctl |= BITM_SPORT_CTL_A_LFS; /* Select the Active High Frame Sync(FS)*/ + } + if (true == bLateFS) + { + ctl |= BITM_SPORT_CTL_A_LAFS; /* Select the Late Frame Sync(FS)*/ + } + if (true == bFSErrorOperation) + { + ctl |= BITM_SPORT_CTL_A_FSERRMODE; /* Select the edge sensitive Frame Sync(FS)*/ + } + pDevice->pSportInfo->pSportRegs->DIV_A = pSportCfg->DIV = dv; /* DIV value set */ + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + return result; +} + +/** + * @brief Configure the SPORT use the Clocks and Frame Sync of other Half-Sport + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] bUseOtherFS Boolean flag to indicate whether to use own Frame Sync(false) OR to + * use frame sync of other half SPORT (true). + * \n + * \n true : Use frame sync of other half SPORT device. + * \n + * \n false : Use own frame sync. + * + * @param [in] bUseOtherClk Boolean flag to indicate whether to use own clock clock(false) OR to + * use clock of other half SPORT(true). + * \n + * \n true : Use clock of other half SPORT device. + * \n + * \n false : Use own clock. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully enabled the specified SPORT to use the clk + * and FS of other half SPORT. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_MultiplexSportSignal(ADI_SPORT_HANDLE const hDevice, + const bool bUseOtherFS, + const bool bUseOtherClk) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE *)hDevice; /* Pointer to SPORT device instance */ +#ifdef ADI_DEBUG + if((result = ValidateHandle(pDevice)) != ADI_SPORT_SUCCESS) /* Validate the given handle */ + { + } + else if (pDevice->pSportInfo->eState == ADI_SPORT_STATE_DATA_FLOW_ENABLED) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t ctl = pSportCfg->CTL; + + /* clear the muxing fields of the control register 2 */ + ctl &= (uint32_t)(~(BITM_SPORT_CTL_A_CKMUXSEL | BITM_SPORT_CTL_A_FSMUXSEL)); + if (true == bUseOtherFS) + { + ctl |= BITM_SPORT_CTL_A_FSMUXSEL; /* Use the the frame sync of other half sport*/ + } + if(bUseOtherClk == true) + { + ctl |= BITM_SPORT_CTL_A_CKMUXSEL; /* Use the the clock of other half sport*/ + } + pSportCfg->CTL = ctl; /* CTL value set - CTL_A is assigned when submitting a buffer */ + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); + } + + return result; +} +/** + * @brief Configure the SPORT use the Clocks and Frame Sync of other Half-Sport + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] nFSDuration Specify the value of the number of clocks which would be programmed corresponding to the + * desired time duration from assertion of CONVT signal to Frame sync signal + * + * @param [in] nWidth Specify the value of the number of serial clocks for which CONVT signal should be active. + + * + * @param [in] bActiveLow Boolean flag to indicate the polarity of the Convt signal. + * \n + * \n true : Active low Polarity. + * \n + * \n false : Active High Polarity. + * + * @return Status + * + * - #ADI_SPORT_SUCCESS Successfully enabled the specified SPORT to use the clk + * and FS of other half SPORT. + * + * - #ADI_SPORT_INVALID_HANDLE [D] Invalid SPORT device handle. + * + * - #ADI_SPORT_OPERATION_NOT_ALLOWED [D] Operation is not allowed when data flow is enabled. + * + */ +ADI_SPORT_RESULT adi_sport_ConfigTimerMode(ADI_SPORT_HANDLE const hDevice, + const uint8_t nFSDuration, + const uint8_t nWidth, + const bool bActiveLow) +{ + ADI_SPORT_RESULT result = ADI_SPORT_SUCCESS; + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) hDevice; /* Pointer to SPORT device instance */ + +#ifdef ADI_DEBUG /* Validate the given handle */ + if (ADI_SPORT_SUCCESS != (result = ValidateHandle(pDevice))) + { + } + else if (ADI_SPORT_STATE_DATA_FLOW_ENABLED == pDevice->pSportInfo->eState) + { + result = ADI_SPORT_OPERATION_NOT_ALLOWED; + } + else +#endif /* ADI_DEBUG */ + { + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + uint32_t cnvt = pSportCfg->TIM_CONVT; + + /* clear the muxing fields of the control register 2 */ + cnvt &= (uint32_t)(~(BITM_SPORT_CNVT_A_POL | BITM_SPORT_CNVT_A_WID | BITM_SPORT_CNVT_A_CNVT2FS )); + cnvt |= (((uint32_t) nFSDuration << ((uint32_t) BITP_SPORT_CNVT_A_CNVT2FS)) | ((uint32_t) nWidth)); + if(bActiveLow == true) + { + cnvt |= ((uint32_t) BITM_SPORT_CNVT_A_POL); /* Use the the clock of other half sport*/ + } + pDevice->pSportInfo->pSportRegs->CNVT_A = pSportCfg->TIM_CONVT = cnvt; + } + return result; +} + +/*! \cond PRIVATE */ + +/** + * @brief Create a circular linked list for buffer management. + * + * @details Create a circular linked list for buffer management and + * initialize the free buffer, the fill buffer and he active + * buffer with the first buffer in this circular array. + * + * @param [in] hDevice Device handle to SPORT device. + * + * @param [in] NumDesc Number of descriptorS. + * + */ +static inline void sport_Init (ADI_SPORT_DEVICE *pDevice) +{ + uint32_t i; + ADI_DT_CHANNEL *pChannel = &pDevice->sportChannel; + ADI_DT_BUFF_INFO *pBufInfo = &pChannel->BufInfo[0]; /* initialize this variable with the first array element */ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* short cut to SPORT information */ + ADI_SPORT_CONFIG * pSportCfg = &pSportInfo->sportCfg; /* short cut to SPORT configuration */ + const uint32_t bytesPerData = GetBytesPerSportData(pSportCfg->CTL); /* number of bytes in SPORT data (1, 2, or 4) */ + const uint32_t packMode = SPORT_GET_PACKEN(pSportCfg->CTL); /* SPORT data pack mode */ + + /* Initialize the all descriptors. Make it circular. */ + for(i = 0u; i < ADI_DT_BUFNUM; i++) + { + pBufInfo[i].pStartAddress = NULL; + pBufInfo[i].nCount = 0u; + pBufInfo[i].nIndex = 0u; + pBufInfo[i].pNextBuffer = &pBufInfo[(i+1u) % ADI_DT_BUFNUM]; /* link the buffers in a circular way */ + } + pChannel->pFreeBuffer = &pChannel->BufInfo[0u]; /* the first free buffer is the first array element */ + pChannel->pActiveBuffer = &pChannel->BufInfo[0u]; /* the first active buffer is the first array element */ + pChannel->pFillBuffer = &pChannel->BufInfo[0u]; /* the first fill buffer is the first array element */ + + switch (bytesPerData) + { + case 1u: + if (SPORT_BIT_PACK_8 == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_1_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_1_BYTE; + + assert(SPORT_BIT_PACK_NONE == packMode); + } + break; + + case 2u: + if (SPORT_BIT_PACK_16 == packMode) + { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + } else { + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_2_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_2_BYTE; + + assert(SPORT_BIT_PACK_NONE == packMode); + } + break; + + default: + pSportCfg->DMA_WIDTH = ADI_DMA_WIDTH_4_BYTE; + pSportCfg->DMA_INC = ADI_DMA_INCR_4_BYTE; + assert((4u == bytesPerData) || (SPORT_BIT_PACK_NONE == packMode)); + break; + } +} + +/* + * @brief Configure the registers with the half-SPORT + * + * @param [in] hDevice Device handle to SPORT device. + * @param [in] sportCfg SPORT configuration to be used. + * + * @return None + */ +static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg) +{ + /* Configure the SPORT device using static configuration parameters. + * pSportInfo is mapped to one of the half-SPORT available; this is the + * half-SPORT configured. (CTL_A, DIV_A, CNVT_A and NUMTRAN_A map either + * to half-SPORT A registers or half-SPORT B registers, depending on + * sportRegs.) + */ + volatile ADI_SPORT_TypeDef * sportRegs = pDevice->pSportInfo->pSportRegs; + ADI_SPORT_CONFIG * pSportCfg = &pDevice->pSportInfo->sportCfg; + + /* record the SPORT default configuration */ + memcpy(pSportCfg, sportCfg, sizeof(ADI_SPORT_CONFIG)); + + switch (pDevice->eDirection) /* Set the direction of operation */ + { + case ADI_SPORT_DIR_RX: + pSportCfg->CTL &= ~BITM_SPORT_CTL_A_SPTRAN; + break; + case ADI_SPORT_DIR_TX: + pSportCfg->CTL |= BITM_SPORT_CTL_A_SPTRAN; + break; + default: + assert(0); + break; + } + /* use the SPORT configuration to setup the SPORT registers */ + sportRegs->CTL_A = pSportCfg->CTL; + sportRegs->DIV_A = pSportCfg->DIV; + sportRegs->CNVT_A = pSportCfg->TIM_CONVT; + sportRegs->NUMTRAN_A = 0u; + + SPORT_CHECK_CFG_CTL(pSportCfg->CTL); +} + +#ifdef ADI_DEBUG +static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice) +{ + ADI_SPORT_RESULT result = ADI_SPORT_INVALID_HANDLE; + ADI_SPORT_DEVICE * pInDevice = (ADI_SPORT_DEVICE*) hDevice; + ADI_SPORT_DEVICE_INFO *poDeviceInfo = &gSportDevInfo[0][0]; + uint32_t i; + + /* Pointer to SPORT device instance */ + for (i=0u; i<(ADI_SPORT_NUM_INSTANCES << 1u); i++) /* 2 half-devices per SPORT */ + { + if (pInDevice == poDeviceInfo->hDevice) + { + result = ADI_SPORT_SUCCESS; + break; + } + poDeviceInfo++; + } + return result; +} +#endif /* ADI_DEBUG */ + +/* mask for events to be recorded in the driver HW error */ +#define recEvt ((uint32_t) (BITM_SPORT_STAT_A_SYSDATERR | BITM_SPORT_STAT_A_FSERR | BITM_SPORT_STAT_A_DERR)) + +/* bits to be cleared by the ISR */ +#define clrEvt ((recEvt | BITM_SPORT_STAT_A_TFI)) + +static void sport_Terminate(ADI_SPORT_DEVICE * pDevice) +{ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* get SPORT device information */ + volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs; /* access SPORT registers */ + + ADI_DT_CHANNEL * pSportChnl = &pDevice->sportChannel; + ADI_DT_BUFF_INFO * pBuff = pSportChnl->pFillBuffer; + + pRegs->CTL_A &= ~BITM_SPORT_CTL_A_SPEN; /* disable SPORT */ + pRegs->IEN_A &= ~(BITM_SPORT_IEN_A_TF | BITM_SPORT_IEN_A_DATA); /* disable SPORT interrupts */ + pRegs->NUMTRAN_A = 0u; + +#ifdef ADI_DEBUG + { + /* ============================================= */ + /* Check the number of data transmitted/received */ + /* nIndex is incremented each time a data packed */ + /* or unpacked in received. The size in bytes of */ + /* each data depends on the SPORT configuration. */ + /* In core driven operations, nCount represents */ + /* the number of 32-bit words transmitted. */ + /* In DMA driven operations, nCount represents */ + /* the number of DMA data transmitted */ + /* ============================================= */ + const uint32_t ctl = pRegs->CTL_A; + const uint32_t bytesPerData = GetBytesPerSportData(ctl); + const uint32_t nIndex = pBuff->nIndex * (4u / bytesPerData); + assert((nIndex>=pBuff->nCount)||(true==pBuff->bDMA)); /* buffer must be fully processed */ + } +#endif + + pBuff->bInUse = false; /* mark buffer as ready */ + + NVIC_DisableIRQ(pSportInfo->eIRQn); /* suspend SPORT Interrupt */ + NVIC_DisableIRQ(pSportInfo->eDMAn); /* suspend SPORT DMA interrupt */ + + pDevice->pSportInfo->eState = ADI_SPORT_STATE_PAUSED; + + if(NULL != pDevice->pfCallback) /* Call the callback function if one is registered. */ + { + uint32_t evt = ( (ADI_SPORT_DIR_RX == pDevice->eDirection) + ? ((uint32_t) ADI_SPORT_EVENT_RX_BUFFER_PROCESSED) + : ((uint32_t) ADI_SPORT_EVENT_TX_BUFFER_PROCESSED) + ); + + pDevice->pfCallback(pDevice->pCBParam,evt,pBuff->pStartAddress); + pBuff->pStartAddress = NULL; /* No need to keep the processed buffer address */ + } + else + { + SEM_POST(pSportChnl); /* signal the buffer availability through a semaphore */ + } + pRegs->STAT_A = clrEvt; /* clear status register bits (W1C) */ + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + pBuff = pBuff->pNextBuffer; /* point to the next buffer to process */ + pSportChnl->pFillBuffer = pBuff; /* this is the new pFillBuffer */ + + if ((0u != pBuff->pStartAddress) && (true == pBuff->bInUse)) /* valid buffer not being processed yet */ + { + ADI_SPORT_RESULT result; + + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONBLOCKING; + if (true == pBuff->bDMA) + { + result = sport_SubmitBufferDmaMode(pDevice, pBuff); + } + else + { + result = sport_SubmitBufferIntMode(pDevice, pBuff); + } + + if(ADI_SPORT_SUCCESS != result) /* if an error occurred...*/ + { + pSportChnl->eDataTranferMode = ADI_DT_MODE_NONE; /* SPORT is available */ + } + } +} + +/* + * @brief Common SPORT interrupt handler function called by SPORT0 A and SPORT0 B ISRs. + * + * @details Process SPORT0 A and B interrupts, recording HW errors that must be reported, + * reading/writing transmitted data, launching new SPORT transmissions if more + * buffers are to be processed, and deactivating the SPORT device if there are + * no pending requests. (Common fucntion for both core driven and DMA driven + * SPORT operations.) + * + * @param [in] pDevice Sport device pointer related to the calling ISR. + */ +static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice) +{ + ADI_SPORT_DEVICE_INFO * pSportInfo = pDevice->pSportInfo; /* get SPORT device information */ + volatile ADI_SPORT_TypeDef * pRegs = pSportInfo->pSportRegs; /* access SPORT registers */ + const uint32_t sportStatus = pRegs->STAT_A; /* read SPORT status */ + const uint32_t dataRequest = (sportStatus & BITM_SPORT_STAT_A_DATA);/* set if any data to be processed by the SPORT */ + const uint32_t hwEvents = sportStatus & recEvt; /* HW events to be recorded in the driver */ + + + /* This implementation assumes an identity mapping between BITM_SPORT_STAT values + * and their equivalent event in ADI_SPORT_EVENT, e.g. ADI_SPORT_HW_ERR_FS and + * BITM_SPORT_STAT_A_FSERR share the same value. This simplifies event processing + * and reports. */ + assert(((uint32_t) ADI_SPORT_HW_ERR_RX_OVERFLOW) == BITM_SPORT_STAT_A_DERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_TX_UNDERFLOW) == BITM_SPORT_STAT_A_DERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_FS) == BITM_SPORT_STAT_A_FSERR); + assert(((uint32_t) ADI_SPORT_HW_ERR_SYSDATAERR) == BITM_SPORT_STAT_A_SYSDATERR); + + if (0u != hwEvents) /* any event recorded? */ + { + if (NULL != pDevice->pfCallback) /* if a callback has been registered ? */ + { + pDevice->pfCallback(pDevice->pCBParam,hwEvents,NULL); /* then call it */ + } else { + pDevice->nHwError |= hwEvents; /* else set the driver HW error */ + SEM_POST(&pDevice->sportChannel); /* and signal this through a semaphore */ + } + } + + if (0u != dataRequest) /* Tx FIFO is not full or Rx FIFO is not empty */ + { + ADI_DT_BUFF_INFO * pBuff = pDevice->sportChannel.pFillBuffer; + uint32_t * pNextWord = (uint32_t*) pBuff->pStartAddress; + + if ((NULL != pNextWord) && (pBuff->nIndex < pBuff->nCount)) /* This buffer has not been fully processed yet */ + { + if (ADI_SPORT_DIR_RX == pDevice->eDirection) + { + pNextWord[pBuff->nIndex++] = pRegs->RX_A; /* Read the data received in RX and increment the index */ + while (!DXS_FIFO_IS_EMPTY(pRegs->STAT_A)) /* and if there are more data available in the FIFO */ + { + pNextWord[pBuff->nIndex++] = pRegs->RX_A; /* Read remaining data received in RX and increment the index */ + } + } + else + { + pRegs->TX_A = pNextWord[pBuff->nIndex++]; /* Write the data to be sent into TX and increment the index */ + while ( (pBuff->nIndex < pBuff->nCount) /* and if there are more data to be sent */ + && (!DXS_FIFO_IS_FULL(pRegs->STAT_A)) /* and there is still room in the FIFO */ + ) + { + pRegs->TX_A = pNextWord[pBuff->nIndex++]; /* then write more data to be sent into TX and increment the index */ + } + } + } + } + + /* ========================================================== */ + /* Common to core driven operations and DMA driven operations */ + /* ========================================================== */ + if (0u != (pRegs->STAT_A & BITM_SPORT_STAT_A_TFI)) /* If a SPORT Tx/Rx request has finished */ + { + sport_Terminate(pDevice); + } + +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif +} + +/** Interrupt handler for SPORT0 A */ +void SPORT0A_Int_Handler(void) +{ + ISR_PROLOG(); + sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice); + ISR_EPILOG(); +} + +/** Interrupt handler for SPORT0 B */ +void SPORT0B_Int_Handler(void) +{ + ISR_PROLOG(); + sport_InterruptHandler(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice); + ISR_EPILOG(); +} + +void DMA_SPORT0A_Int_Handler(void) +{ + ISR_PROLOG(); + /** + * if SPORT is in Rx mode, then the DMA interrupt is the signal for + * end of transmission: buffer is ready. (In Tx mode, the signal is + * the TFI event and SPORT DMA interrup is not enabled). + */ + sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_A].hDevice); +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif + ISR_EPILOG(); +} + +void DMA_SPORT0B_Int_Handler(void) +{ + ISR_PROLOG(); + /** + * if SPORT is in Rx mode, then the DMA interrupt is the signal for + * end of transmission: buffer is ready. (In Tx mode, the signal is + * the TFI event and SPORT DMA interrup is not enabled). + */ + sport_Terminate(gSportDevInfo[0][ADI_HALF_SPORT_B].hDevice); +#if defined(ADI_CYCLECOUNT_SPORT_ISR_ENABLED) && (ADI_CYCLECOUNT_SPORT_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_SPORT); +#endif + ISR_EPILOG(); +} + +static void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) +{ + ADI_SPORT_DEVICE * pDevice = (ADI_SPORT_DEVICE*) pCBParam; /* Recover the device handle. */ + ADI_DT_BUFF_INFO * pFillBuffer = pDevice->sportChannel.pFillBuffer; + ADI_DT_BUFF_INFO * pNextBuffer = pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + if (ADI_DMA_EVENT_ERR_BUS == Event) + { + nEvent = (uint32_t) ADI_SPORT_DMA_ERR_BUS; /* SPORT DMA bus error detected */ + } else { + assert(ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR == Event); + nEvent = (uint32_t) ADI_SPORT_DMA_ERR_INVALID_DESCRIPTOR; /* SPORT DMA invalid descriptor error detected */ + } + + pDevice->nHwError |= nEvent; + sport_InterruptHandler(pDevice); + + while ( (NULL != pNextBuffer->pStartAddress) + && (true == pNextBuffer->bInUse) + && (true == pNextBuffer->bDMA) + ) /* another buffer is pending for a DMA driven request */ + { + pDevice->nHwError |= nEvent; + pNextBuffer->bInUse = false; + sport_InterruptHandler(pDevice); + pNextBuffer = pNextBuffer->pNextBuffer; + } +} + +static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal) +{ + const uint32_t wlen = SPORT_GET_WLEN(ctlVal); + const uint32_t bytesPerData = ((wlen < 9u) ? (1u) : ((wlen < 17u) ? (2u) : (4u))); + return bytesPerData; +} + +/*! \endcond */ + +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h new file mode 100755 index 00000000000..7244562e9ae --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sport/adi_sport_def.h @@ -0,0 +1,193 @@ +/*! ***************************************************************************** + * @file: adi_sport_def.h + * @brief: UART Device Driver definition for processor + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \cond PRIVATE */ +#ifndef ADI_SPORT_DEF_H +#define ADI_SPORT_DEF_H + +#include + +#if defined(ADI_CFG_SPORT0A_SERIAL_WLEN) +#if (ADI_CFG_SPORT0A_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0A_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0A_SERIAL_WLEN undefined!!! " +#endif + +#if defined(ADI_CFG_SPORT0B_SERIAL_WLEN) +#if (ADI_CFG_SPORT0B_SERIAL_WLEN <= 3u) || (ADI_CFG_SPORT0B_SERIAL_WLEN > 32u) +#error "Invalid word length : it must be between 4 and 32" +#endif +#else +#error "ADI_CFG_SPORT0B_SERIAL_WLEN undefined!!! " +#endif + +#define ADI_SPORT_NUM_INSTANCES (1u) /*!< Number of SPORT devices available */ +#define ADI_SPORT_NUM_CHANNELS (2u) /*!< Number of SPORT channel for each SPORT devcie */ + +#define BITM_SPORT_DATA_CONFIG ( BITM_SPORT_CTL_A_LSBF \ + | BITM_SPORT_CTL_A_PACK) + +#define BITM_SPORT_CLOCK_CONFIG ( BITM_SPORT_CTL_A_ICLK \ + | BITM_SPORT_CTL_A_CKRE \ + | BITM_SPORT_CTL_A_GCLKEN) + +#define BITM_SPORT_FS_CONFIG ( BITM_SPORT_CTL_A_FSR \ + | BITM_SPORT_CTL_A_IFS \ + | BITM_SPORT_CTL_A_DIFS \ + | BITM_SPORT_CTL_A_LFS \ + | BITM_SPORT_CTL_A_LAFS \ + | BITM_SPORT_CTL_A_FSERRMODE) + +#define SPORT_BYTE_TRANSFER_LENGTH (8u) +#define SPORT_HALFWORD_TRANSFER_LENGTH (16u) +#define SPORT_WORD_TRANSFER_LENGTH (32u) + +#define SPORT_GET_WLEN(ctlVal) ((((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_SLEN) >> ((uint32_t) BITP_SPORT_CTL_A_SLEN)) + 1u) +#define SPORT_GET_PACKEN(ctlVal) ((ctlVal) & (uint32_t) BITM_SPORT_CTL_A_PACK) >> ((uint32_t) BITP_SPORT_CTL_A_PACK) + +#define SPORT_CHECK_CFG_CTL(CFG) assert(0u == ((CFG) & (((uint32_t)BITM_SPORT_CTL_A_SPEN) | ((uint32_t)BITM_SPORT_CTL_A_DMAEN)))) + + +#define SPORT_BIT_PACK_NONE (((uint32_t) ADI_SPORT_NO_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) +#define SPORT_BIT_PACK_8 (((uint32_t) ADI_SPORT_8BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) +#define SPORT_BIT_PACK_16 (((uint32_t) ADI_SPORT_16BIT_PACKING) >> ((uint32_t) BITP_SPORT_CTL_A_PACK)) + +/*! + ***************************************************************************** + * \struct ADI_SPORT_STATE + * Enumeration of different SPORT states. + *****************************************************************************/ +typedef enum +{ + ADI_SPORT_STATE_UNINITIALIZED = 0, /*!< SPORT is not yet initialized */ + ADI_SPORT_STATE_INITIALIZED, /*!< SPORT is initialized */ + ADI_SPORT_STATE_DATA_FLOW_ENABLED, /*!< SPORT Tx or Rx data flow is enabled (SPORT peripheral cannot be re-configured) */ + ADI_SPORT_STATE_DATA_FLOW_DISABLED, /*!< SPORT Tx or Rx data flow is disabled (SPORT peripheral can be re-configured) */ + ADI_SPORT_STATE_PAUSED +} ADI_SPORT_STATE; + +/*! + ***************************************************************************** + * \struct ADI_SPORT_CONFIG + * Structure for initializing the static config. + *****************************************************************************/ + +typedef struct _ADI_SPORT_CONFIG +{ + uint32_t CTL; /*!< SPORT_CTL register. */ + uint32_t DIV; /*!< SPORT_DIV register. */ + uint32_t TIM_CONVT; /*!< TIM_CONVT Register. */ + uint32_t DMA_WIDTH; /*!< DMA_WIDTH */ + uint32_t DMA_INC; /*!< DMA_INC */ +} ADI_SPORT_CONFIG; + +/*! + ***************************************************************************** + * \struct ADI_SPORT_DEVICE_INFO + * SPORT device information. + *****************************************************************************/ +typedef struct _ADI_SPORT_DEVICE_INFO +{ + volatile ADI_SPORT_TypeDef* pSportRegs; /*!< Base address of the SPORT registers */ + ADI_SPORT_CONFIG sportCfg; /*!< SPORT configuration data */ + ADI_SPORT_STATE eState; /*!< To indicate the state of the device */ + const DMA_CHANn_TypeDef eDMAChnlID; /*!< DMA channel ID */ + const IRQn_Type eDMAn; /*!< DMA channel IRQ identifier */ + const IRQn_Type eIRQn; /*!< SPORT IRQ identifier */ + ADI_SPORT_HANDLE hDevice; /*!< SPORT handle */ +} ADI_SPORT_DEVICE_INFO; + +/****************************************************************************** + * SPORT Device internal API function prototypes + *****************************************************************************/ + +#define NUM_SPORT_BUFFER (2u) + +/** SPORT driver instance data */ +typedef struct _ADI_SPORT_DEVICE +{ + ADI_SPORT_DEVICE_INFO * pSportInfo; /*!< pointer to the structure which stores the information about the SPORT instances.*/ + ADI_SPORT_DIRECTION eDirection; /*!< Direction in which the SPORT is opened */ + ADI_CALLBACK pfCallback; /*!< Function pointer for callback function. */ + void * pCBParam; /*!< Parameter to callback function. */ + ADI_DT_CHANNEL sportChannel; /*!< SPORT channel to manage transmitted data buffers */ + volatile uint32_t nHwError; /*!< variable to store the hardware status */ +} ADI_SPORT_DEVICE; + +/** Initialize a SPORT device */ +static inline void sport_Init (ADI_SPORT_DEVICE * pDevice); + +/** Configure a SPORT device */ +static inline void sport_Configure (ADI_SPORT_DEVICE *pDevice, ADI_SPORT_CONFIG const * sportCfg); + +/** Function prototype for submitting a buffer for SPORT Rx or Tx DMA driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferDmaMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff); + +/** Function prototype for submitting a buffer for SPORT Rx or Tx core driven transmission */ +static ADI_SPORT_RESULT sport_SubmitBufferIntMode(ADI_SPORT_DEVICE * pDevice, ADI_DT_BUFF_INFO * pBuff); + +/** Fucntion prototype for completing a SPORT transmission (Rx or Tx) */ +static void sport_Terminate(ADI_SPORT_DEVICE * pDevice); + +/** Interrupt Handlers */ + +/** SPORT interrupt handler */ +static void sport_InterruptHandler(ADI_SPORT_DEVICE * pDevice); + +static inline void sport_DmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); + +static inline uint32_t GetBytesPerSportData(const uint32_t ctlVal); + +/* + * Handle Validation function +*/ +#ifdef ADI_DEBUG +static ADI_SPORT_RESULT ValidateHandle(ADI_SPORT_HANDLE const hDevice); +#endif /* ADI_DEBUG */ + +#endif /* end of ifndef ADI_SPORT_DEF_H */ +/*! \endcond */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h new file mode 100755 index 00000000000..d2a7a908a41 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050.h @@ -0,0 +1,5339 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050.h + Description : Register Definitions + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _DEF_ADUCM4050_H +#define _DEF_ADUCM4050_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + + +#if defined (_MISRA_RULES) +#pragma diag(push) +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros") +#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators") +#endif /* _MISRA_RULES */ + +/* _ADI_MSK_3 might be defined in wrapper includes - otherwise provide a default */ +#if !defined(_ADI_MSK_3) +/* do not add casts to literal constants in assembly code */ +#if defined(_LANGUAGE_ASM) || defined(__ASSEMBLER__) +/* Use unsuffixed literals for BITM macros */ +#define _ADI_MSK_3( mask, smask, type ) (mask) +#else +/* Use casted suffixed literals for BITM macros */ +#define _ADI_MSK_3( mask, smask, type ) ((type)(smask)) +#endif +#endif + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_ADC__ 1 +#define __ADI_HAS_BEEP__ 1 +#define __ADI_HAS_BUSM__ 1 +#define __ADI_HAS_CLKG_OSC__ 1 +#define __ADI_HAS_CLKG__ 1 +#define __ADI_HAS_CLKG_CLK__ 1 +#define __ADI_HAS_CRC__ 1 +#define __ADI_HAS_CRYPT__ 1 +#define __ADI_HAS_DMA__ 1 +#define __ADI_HAS_XINT__ 1 +#define __ADI_HAS_FLCC__ 1 +#define __ADI_HAS_FLCC_CACHE__ 1 +#define __ADI_HAS_FLCC_DFT__ 1 +#define __ADI_HAS_FLCC_TEST__ 1 +#define __ADI_HAS_GPIO__ 1 +#define __ADI_HAS_TMR__ 1 +#define __ADI_HAS_I2C__ 1 +#define __ADI_HAS_NVIC__ 1 +#define __ADI_HAS_PMG__ 1 +#define __ADI_HAS_PMG_TST__ 1 +#define __ADI_HAS_PTI__ 1 +#define __ADI_HAS_RNG__ 1 +#define __ADI_HAS_RTC__ 1 +#define __ADI_HAS_SPI__ 1 +#define __ADI_HAS_SPORT__ 1 +#define __ADI_HAS_SYS__ 1 +#define __ADI_HAS_TMR_RGB__ 1 +#define __ADI_HAS_UART__ 1 +#define __ADI_HAS_WDT__ 1 + +/* ============================================================================================================================ + General Purpose Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + TMR0 + ============================================================================================================================ */ +#define REG_TMR0_LOAD 0x40000000 /* TMR0 16-bit Load Value */ +#define REG_TMR0_CURCNT 0x40000004 /* TMR0 16-bit Timer Value */ +#define REG_TMR0_CTL 0x40000008 /* TMR0 Control */ +#define REG_TMR0_CLRINT 0x4000000C /* TMR0 Clear Interrupt */ +#define REG_TMR0_CAPTURE 0x40000010 /* TMR0 Capture */ +#define REG_TMR0_ALOAD 0x40000014 /* TMR0 16-bit Load Value, Asynchronous */ +#define REG_TMR0_ACURCNT 0x40000018 /* TMR0 16-bit Timer Value, Asynchronous */ +#define REG_TMR0_STAT 0x4000001C /* TMR0 Status */ +#define REG_TMR0_PWMCTL 0x40000020 /* TMR0 PWM Control Register */ +#define REG_TMR0_PWMMATCH 0x40000024 /* TMR0 PWM Match Value */ +#define REG_TMR0_EVENTSELECT 0x40000028 /* TMR0 Timer Event Selection Register */ + +/* ============================================================================================================================ + TMR1 + ============================================================================================================================ */ +#define REG_TMR1_LOAD 0x40000400 /* TMR1 16-bit Load Value */ +#define REG_TMR1_CURCNT 0x40000404 /* TMR1 16-bit Timer Value */ +#define REG_TMR1_CTL 0x40000408 /* TMR1 Control */ +#define REG_TMR1_CLRINT 0x4000040C /* TMR1 Clear Interrupt */ +#define REG_TMR1_CAPTURE 0x40000410 /* TMR1 Capture */ +#define REG_TMR1_ALOAD 0x40000414 /* TMR1 16-bit Load Value, Asynchronous */ +#define REG_TMR1_ACURCNT 0x40000418 /* TMR1 16-bit Timer Value, Asynchronous */ +#define REG_TMR1_STAT 0x4000041C /* TMR1 Status */ +#define REG_TMR1_PWMCTL 0x40000420 /* TMR1 PWM Control Register */ +#define REG_TMR1_PWMMATCH 0x40000424 /* TMR1 PWM Match Value */ +#define REG_TMR1_EVENTSELECT 0x40000428 /* TMR1 Timer Event Selection Register */ + +/* ============================================================================================================================ + TMR2 + ============================================================================================================================ */ +#define REG_TMR2_LOAD 0x40000800 /* TMR2 16-bit Load Value */ +#define REG_TMR2_CURCNT 0x40000804 /* TMR2 16-bit Timer Value */ +#define REG_TMR2_CTL 0x40000808 /* TMR2 Control */ +#define REG_TMR2_CLRINT 0x4000080C /* TMR2 Clear Interrupt */ +#define REG_TMR2_CAPTURE 0x40000810 /* TMR2 Capture */ +#define REG_TMR2_ALOAD 0x40000814 /* TMR2 16-bit Load Value, Asynchronous */ +#define REG_TMR2_ACURCNT 0x40000818 /* TMR2 16-bit Timer Value, Asynchronous */ +#define REG_TMR2_STAT 0x4000081C /* TMR2 Status */ +#define REG_TMR2_PWMCTL 0x40000820 /* TMR2 PWM Control Register */ +#define REG_TMR2_PWMMATCH 0x40000824 /* TMR2 PWM Match Value */ +#define REG_TMR2_EVENTSELECT 0x40000828 /* TMR2 Timer Event Selection Register */ + +/* ============================================================================================================================ + TMR Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_LOAD_VALUE 0 /* Load Value */ +#define BITM_TMR_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CURCNT_VALUE 0 /* Current Count */ +#define BITM_TMR_CURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CTL_SYNCBYP 15 /* Synchronization Bypass */ +#define BITP_TMR_CTL_RSTEN 14 /* Counter and Prescale Reset Enable */ +#define BITP_TMR_CTL_EVTEN 13 /* Event Select */ +#define BITP_TMR_CTL_RLD 7 /* Reload Control */ +#define BITP_TMR_CTL_CLK 5 /* Clock Select */ +#define BITP_TMR_CTL_EN 4 /* Timer Enable */ +#define BITP_TMR_CTL_MODE 3 /* Timer Mode */ +#define BITP_TMR_CTL_UP 2 /* Count up */ +#define BITP_TMR_CTL_PRE 0 /* Prescaler */ +#define BITM_TMR_CTL_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ +#define BITM_TMR_CTL_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ +#define BITM_TMR_CTL_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ +#define BITM_TMR_CTL_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ +#define BITM_TMR_CTL_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ +#define BITM_TMR_CTL_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ +#define BITM_TMR_CTL_MODE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ +#define BITM_TMR_CTL_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_TMR_CTL_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CLRINT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CLRINT_EVTCAPT 1 /* Clear Captured Event Interrupt */ +#define BITP_TMR_CLRINT_TIMEOUT 0 /* Clear Timeout Interrupt */ +#define BITM_TMR_CLRINT_EVTCAPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ +#define BITM_TMR_CLRINT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_CAPTURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_CAPTURE_VALUE 0 /* 16-bit Captured Value */ +#define BITM_TMR_CAPTURE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* 16-bit Captured Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_ALOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_ALOAD_VALUE 0 /* Load Value, Asynchronous */ +#define BITM_TMR_ALOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value, Asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_ACURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_ACURCNT_VALUE 0 /* Counter Value */ +#define BITM_TMR_ACURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Counter Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_STAT_CNTRST 8 /* Counter Reset Occurring */ +#define BITP_TMR_STAT_PDOK 7 /* Clear Interrupt Register Synchronization */ +#define BITP_TMR_STAT_BUSY 6 /* Timer Busy */ +#define BITP_TMR_STAT_CAPTURE 1 /* Capture Event Pending */ +#define BITP_TMR_STAT_TIMEOUT 0 /* Timeout Event Occurred */ +#define BITM_TMR_STAT_CNTRST (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ +#define BITM_TMR_STAT_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ +#define BITM_TMR_STAT_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_TMR_STAT_CAPTURE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ +#define BITM_TMR_STAT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_PWMCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_PWMCTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_PWMCTL_MATCH 0 /* PWM Match Enabled */ +#define BITM_TMR_PWMCTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_PWMCTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled */ +#define ENUM_TMR_PWMCTL_IDLE_LOW (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IDLESTATE: PWM idles low */ +#define ENUM_TMR_PWMCTL_IDLE_HIGH (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IDLESTATE: PWM idles high */ +#define ENUM_TMR_PWMCTL_PWM_TOGGLE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MATCH: PWM in toggle mode */ +#define ENUM_TMR_PWMCTL_PWM_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* MATCH: PWM in match mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_PWMMATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_PWMMATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_PWMMATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_EVENTSELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_EVENTSELECT_EVTRANGE 0 /* Event Select Range */ +#define BITM_TMR_EVENTSELECT_EVTRANGE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Event Select Range */ + + +/* ============================================================================================================================ + Timer_RGB with 3 PWM outputs + ============================================================================================================================ */ + +/* ============================================================================================================================ + TMR_RGB + ============================================================================================================================ */ +#define REG_TMR_RGB_LOAD 0x40000C00 /* TMR_RGB 16-bit load value */ +#define REG_TMR_RGB_CURCNT 0x40000C04 /* TMR_RGB 16-bit timer value */ +#define REG_TMR_RGB_CTL 0x40000C08 /* TMR_RGB Control */ +#define REG_TMR_RGB_CLRINT 0x40000C0C /* TMR_RGB Clear interrupt */ +#define REG_TMR_RGB_CAPTURE 0x40000C10 /* TMR_RGB Capture */ +#define REG_TMR_RGB_ALOAD 0x40000C14 /* TMR_RGB 16-bit load value, asynchronous */ +#define REG_TMR_RGB_ACURCNT 0x40000C18 /* TMR_RGB 16-bit timer value, asynchronous */ +#define REG_TMR_RGB_STAT 0x40000C1C /* TMR_RGB Status */ +#define REG_TMR_RGB_PWM0CTL 0x40000C20 /* TMR_RGB PWM0 Control Register */ +#define REG_TMR_RGB_PWM0MATCH 0x40000C24 /* TMR_RGB PWM0 Match Value */ +#define REG_TMR_RGB_EVENTSELECT 0x40000C28 /* TMR_RGB Timer Event selection Register */ +#define REG_TMR_RGB_PWM1CTL 0x40000C2C /* TMR_RGB PWM1 Control Register */ +#define REG_TMR_RGB_PWM1MATCH 0x40000C30 /* TMR_RGB PWM1 Match Value */ +#define REG_TMR_RGB_PWM2CTL 0x40000C34 /* TMR_RGB PWM2 Control Register */ +#define REG_TMR_RGB_PWM2MATCH 0x40000C38 /* TMR_RGB PWM2 Match Value */ + +/* ============================================================================================================================ + TMR_RGB Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_LOAD_VALUE 0 /* Load value */ +#define BITM_TMR_RGB_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CURCNT_VALUE 0 /* Current count */ +#define BITM_TMR_RGB_CURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CTL_SYNCBYP 15 /* Synchronization bypass */ +#define BITP_TMR_RGB_CTL_RSTEN 14 /* Counter and prescale reset enable */ +#define BITP_TMR_RGB_CTL_EVTEN 13 /* Event select */ +#define BITP_TMR_RGB_CTL_RLD 7 /* Reload control */ +#define BITP_TMR_RGB_CTL_CLK 5 /* Clock select */ +#define BITP_TMR_RGB_CTL_EN 4 /* Timer enable */ +#define BITP_TMR_RGB_CTL_MODE 3 /* Timer mode */ +#define BITP_TMR_RGB_CTL_UP 2 /* Count up */ +#define BITP_TMR_RGB_CTL_PRE 0 /* Prescaler */ +#define BITM_TMR_RGB_CTL_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization bypass */ +#define BITM_TMR_RGB_CTL_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and prescale reset enable */ +#define BITM_TMR_RGB_CTL_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event select */ +#define BITM_TMR_RGB_CTL_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload control */ +#define BITM_TMR_RGB_CTL_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock select */ +#define BITM_TMR_RGB_CTL_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer enable */ +#define BITM_TMR_RGB_CTL_MODE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer mode */ +#define BITM_TMR_RGB_CTL_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ +#define BITM_TMR_RGB_CTL_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CLRINT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CLRINT_EVTCAPT 1 /* Clear captured event interrupt */ +#define BITP_TMR_RGB_CLRINT_TIMEOUT 0 /* Clear timeout interrupt */ +#define BITM_TMR_RGB_CLRINT_EVTCAPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear captured event interrupt */ +#define BITM_TMR_RGB_CLRINT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear timeout interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_CAPTURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_CAPTURE_VALUE 0 /* 16-bit captured value */ +#define BITM_TMR_RGB_CAPTURE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* 16-bit captured value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_ALOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_ALOAD_VALUE 0 /* Load value, asynchronous */ +#define BITM_TMR_RGB_ALOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load value, asynchronous */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_ACURCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_ACURCNT_VALUE 0 /* Counter value */ +#define BITM_TMR_RGB_ACURCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Counter value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_STAT_CNTRST 8 /* Counter reset occurring */ +#define BITP_TMR_RGB_STAT_PDOK 7 /* Clear Interrupt Register synchronization */ +#define BITP_TMR_RGB_STAT_BUSY 6 /* Timer Busy */ +#define BITP_TMR_RGB_STAT_CAPTURE 1 /* Capture event pending */ +#define BITP_TMR_RGB_STAT_TIMEOUT 0 /* Timeout event occurred */ +#define BITM_TMR_RGB_STAT_CNTRST (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter reset occurring */ +#define BITM_TMR_RGB_STAT_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register synchronization */ +#define BITM_TMR_RGB_STAT_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ +#define BITM_TMR_RGB_STAT_CAPTURE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture event pending */ +#define BITM_TMR_RGB_STAT_TIMEOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout event occurred */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM0CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM0CTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_RGB_PWM0CTL_MATCH 0 /* PWM Match enabled */ +#define BITM_TMR_RGB_PWM0CTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_RGB_PWM0CTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM0MATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM0MATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_RGB_PWM0MATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_EVENTSELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_EVENTSELECT_EVTRANGE 0 /* Event select range */ +#define BITM_TMR_RGB_EVENTSELECT_EVTRANGE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Event select range */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM1CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM1CTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_RGB_PWM1CTL_MATCH 0 /* PWM Match enabled */ +#define BITM_TMR_RGB_PWM1CTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_RGB_PWM1CTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM1MATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM1MATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_RGB_PWM1MATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM2CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM2CTL_IDLESTATE 1 /* PWM Idle State */ +#define BITP_TMR_RGB_PWM2CTL_MATCH 0 /* PWM Match enabled */ +#define BITM_TMR_RGB_PWM2CTL_IDLESTATE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ +#define BITM_TMR_RGB_PWM2CTL_MATCH (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + TMR_RGB_PWM2MATCH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TMR_RGB_PWM2MATCH_VALUE 0 /* PWM Match Value */ +#define BITM_TMR_RGB_PWM2MATCH_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* PWM Match Value */ + + +/* ============================================================================================================================ + Real-Time Clock + ============================================================================================================================ */ + +/* ============================================================================================================================ + RTC0 + ============================================================================================================================ */ +#define REG_RTC0_CR0 0x40001000 /* RTC0 RTC Control 0 */ +#define REG_RTC0_SR0 0x40001004 /* RTC0 RTC Status 0 */ +#define REG_RTC0_SR1 0x40001008 /* RTC0 RTC Status 1 */ +#define REG_RTC0_CNT0 0x4000100C /* RTC0 RTC Count 0 */ +#define REG_RTC0_CNT1 0x40001010 /* RTC0 RTC Count 1 */ +#define REG_RTC0_ALM0 0x40001014 /* RTC0 RTC Alarm 0 */ +#define REG_RTC0_ALM1 0x40001018 /* RTC0 RTC Alarm 1 */ +#define REG_RTC0_TRM 0x4000101C /* RTC0 RTC Trim */ +#define REG_RTC0_GWY 0x40001020 /* RTC0 RTC Gateway */ +#define REG_RTC0_CR1 0x40001028 /* RTC0 RTC Control 1 */ +#define REG_RTC0_SR2 0x4000102C /* RTC0 RTC Status 2 */ +#define REG_RTC0_SNAP0 0x40001030 /* RTC0 RTC Snapshot 0 */ +#define REG_RTC0_SNAP1 0x40001034 /* RTC0 RTC Snapshot 1 */ +#define REG_RTC0_SNAP2 0x40001038 /* RTC0 RTC Snapshot 2 */ +#define REG_RTC0_MOD 0x4000103C /* RTC0 RTC Modulo */ +#define REG_RTC0_CNT2 0x40001040 /* RTC0 RTC Count 2 */ +#define REG_RTC0_ALM2 0x40001044 /* RTC0 RTC Alarm 2 */ +#define REG_RTC0_SR3 0x40001048 /* RTC0 RTC Status 3 */ +#define REG_RTC0_CR2IC 0x4000104C /* RTC0 RTC Control 2 for Configuring Input Capture Channels */ +#define REG_RTC0_CR3SS 0x40001050 /* RTC0 RTC Control 3 for Configuring SensorStrobe Channel */ +#define REG_RTC0_CR4SS 0x40001054 /* RTC0 RTC Control 4 for Configuring SensorStrobe Channel */ +#define REG_RTC0_SSMSK 0x40001058 /* RTC0 RTC Mask for SensorStrobe Channel */ +#define REG_RTC0_IC2 0x40001064 /* RTC0 RTC Input Capture Channel 2 */ +#define REG_RTC0_IC3 0x40001068 /* RTC0 RTC Input Capture Channel 3 */ +#define REG_RTC0_IC4 0x4000106C /* RTC0 RTC Input Capture Channel 4 */ +#define REG_RTC0_SS1 0x40001070 /* RTC0 RTC SensorStrobe Channel 1 */ +#define REG_RTC0_SS2 0x40001074 /* RTC0 RTC SensorStrobe Channel 2 */ +#define REG_RTC0_SS3 0x40001078 /* RTC0 RTC SensorStrobe Channel 3 */ +#define REG_RTC0_SS4 0x4000107C /* RTC0 RTC SensorStrobe Channel 4 */ +#define REG_RTC0_SR4 0x40001080 /* RTC0 RTC Status 4 */ +#define REG_RTC0_SR5 0x40001084 /* RTC0 RTC Status 5 */ +#define REG_RTC0_SR6 0x40001088 /* RTC0 RTC Status 6 */ +#define REG_RTC0_SS1TGT 0x4000108C /* RTC0 RTC SensorStrobe Channel 1 Target */ +#define REG_RTC0_FRZCNT 0x40001090 /* RTC0 RTC Freeze Count */ +#define REG_RTC0_SS2TGT 0x40001094 /* RTC0 RTC SensorStrobe Channel 2 Target */ +#define REG_RTC0_SS3TGT 0x40001098 /* RTC0 RTC SensorStrobe Channel 3 Target */ +#define REG_RTC0_SS1LOWDUR 0x400010A0 /* RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define REG_RTC0_SS2LOWDUR 0x400010A4 /* RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define REG_RTC0_SS3LOWDUR 0x400010A8 /* RTC0 RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define REG_RTC0_SS1HIGHDUR 0x400010B0 /* RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define REG_RTC0_SS2HIGHDUR 0x400010B4 /* RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define REG_RTC0_SS3HIGHDUR 0x400010B8 /* RTC0 RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define REG_RTC0_SSMSKOT 0x400010C0 /* RTC0 RTC Masks for SensorStrobe Channels on Time Control */ +#define REG_RTC0_CR5SSS 0x400010C4 /* RTC0 RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define REG_RTC0_CR6SSS 0x400010C8 /* RTC0 RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define REG_RTC0_CR7SSS 0x400010CC /* RTC0 RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define REG_RTC0_SR7 0x400010D0 /* RTC0 RTC Status 7 */ +#define REG_RTC0_SR8 0x400010D4 /* RTC0 RTC Status 8 */ +#define REG_RTC0_SR9 0x400010D8 /* RTC0 RTC Status 9 */ +#define REG_RTC0_GPMUX0 0x400010E0 /* RTC0 RTC GPIO Pin Mux Control Register 0 */ +#define REG_RTC0_GPMUX1 0x400010E4 /* RTC0 RTC GPIO Pin Mux Control Register 1 */ + +/* ============================================================================================================================ + RTC1 + ============================================================================================================================ */ +#define REG_RTC1_CR0 0x40001400 /* RTC1 RTC Control 0 */ +#define REG_RTC1_SR0 0x40001404 /* RTC1 RTC Status 0 */ +#define REG_RTC1_SR1 0x40001408 /* RTC1 RTC Status 1 */ +#define REG_RTC1_CNT0 0x4000140C /* RTC1 RTC Count 0 */ +#define REG_RTC1_CNT1 0x40001410 /* RTC1 RTC Count 1 */ +#define REG_RTC1_ALM0 0x40001414 /* RTC1 RTC Alarm 0 */ +#define REG_RTC1_ALM1 0x40001418 /* RTC1 RTC Alarm 1 */ +#define REG_RTC1_TRM 0x4000141C /* RTC1 RTC Trim */ +#define REG_RTC1_GWY 0x40001420 /* RTC1 RTC Gateway */ +#define REG_RTC1_CR1 0x40001428 /* RTC1 RTC Control 1 */ +#define REG_RTC1_SR2 0x4000142C /* RTC1 RTC Status 2 */ +#define REG_RTC1_SNAP0 0x40001430 /* RTC1 RTC Snapshot 0 */ +#define REG_RTC1_SNAP1 0x40001434 /* RTC1 RTC Snapshot 1 */ +#define REG_RTC1_SNAP2 0x40001438 /* RTC1 RTC Snapshot 2 */ +#define REG_RTC1_MOD 0x4000143C /* RTC1 RTC Modulo */ +#define REG_RTC1_CNT2 0x40001440 /* RTC1 RTC Count 2 */ +#define REG_RTC1_ALM2 0x40001444 /* RTC1 RTC Alarm 2 */ +#define REG_RTC1_SR3 0x40001448 /* RTC1 RTC Status 3 */ +#define REG_RTC1_CR2IC 0x4000144C /* RTC1 RTC Control 2 for Configuring Input Capture Channels */ +#define REG_RTC1_CR3SS 0x40001450 /* RTC1 RTC Control 3 for Configuring SensorStrobe Channel */ +#define REG_RTC1_CR4SS 0x40001454 /* RTC1 RTC Control 4 for Configuring SensorStrobe Channel */ +#define REG_RTC1_SSMSK 0x40001458 /* RTC1 RTC Mask for SensorStrobe Channel */ +#define REG_RTC1_IC2 0x40001464 /* RTC1 RTC Input Capture Channel 2 */ +#define REG_RTC1_IC3 0x40001468 /* RTC1 RTC Input Capture Channel 3 */ +#define REG_RTC1_IC4 0x4000146C /* RTC1 RTC Input Capture Channel 4 */ +#define REG_RTC1_SS1 0x40001470 /* RTC1 RTC SensorStrobe Channel 1 */ +#define REG_RTC1_SS2 0x40001474 /* RTC1 RTC SensorStrobe Channel 2 */ +#define REG_RTC1_SS3 0x40001478 /* RTC1 RTC SensorStrobe Channel 3 */ +#define REG_RTC1_SS4 0x4000147C /* RTC1 RTC SensorStrobe Channel 4 */ +#define REG_RTC1_SR4 0x40001480 /* RTC1 RTC Status 4 */ +#define REG_RTC1_SR5 0x40001484 /* RTC1 RTC Status 5 */ +#define REG_RTC1_SR6 0x40001488 /* RTC1 RTC Status 6 */ +#define REG_RTC1_SS1TGT 0x4000148C /* RTC1 RTC SensorStrobe Channel 1 Target */ +#define REG_RTC1_FRZCNT 0x40001490 /* RTC1 RTC Freeze Count */ +#define REG_RTC1_SS2TGT 0x40001494 /* RTC1 RTC SensorStrobe Channel 2 Target */ +#define REG_RTC1_SS3TGT 0x40001498 /* RTC1 RTC SensorStrobe Channel 3 Target */ +#define REG_RTC1_SS1LOWDUR 0x400014A0 /* RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define REG_RTC1_SS2LOWDUR 0x400014A4 /* RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define REG_RTC1_SS3LOWDUR 0x400014A8 /* RTC1 RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define REG_RTC1_SS1HIGHDUR 0x400014B0 /* RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define REG_RTC1_SS2HIGHDUR 0x400014B4 /* RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define REG_RTC1_SS3HIGHDUR 0x400014B8 /* RTC1 RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define REG_RTC1_SSMSKOT 0x400014C0 /* RTC1 RTC Masks for SensorStrobe Channels on Time Control */ +#define REG_RTC1_CR5SSS 0x400014C4 /* RTC1 RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define REG_RTC1_CR6SSS 0x400014C8 /* RTC1 RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define REG_RTC1_CR7SSS 0x400014CC /* RTC1 RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define REG_RTC1_SR7 0x400014D0 /* RTC1 RTC Status 7 */ +#define REG_RTC1_SR8 0x400014D4 /* RTC1 RTC Status 8 */ +#define REG_RTC1_SR9 0x400014D8 /* RTC1 RTC Status 9 */ +#define REG_RTC1_GPMUX0 0x400014E0 /* RTC1 RTC GPIO Pin Mux Control Register 0 */ +#define REG_RTC1_GPMUX1 0x400014E4 /* RTC1 RTC GPIO Pin Mux Control Register 1 */ + +/* ============================================================================================================================ + RTC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR0_WPNDINTEN 15 /* Enable Write Pending Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_WSYNCINTEN 14 /* Enable Write Synchronization Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_WPNDERRINTEN 13 /* Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ +#define BITP_RTC_CR0_ISOINTEN 12 /* Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ +#define BITP_RTC_CR0_MOD60ALMINTEN 11 /* Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ +#define BITP_RTC_CR0_MOD60ALM 5 /* Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ +#define BITP_RTC_CR0_MOD60ALMEN 4 /* Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ +#define BITP_RTC_CR0_TRMEN 3 /* Enable RTC Digital Trimming */ +#define BITP_RTC_CR0_ALMINTEN 2 /* Enable ALMINT Sourced Alarm Interrupts to the CPU */ +#define BITP_RTC_CR0_ALMEN 1 /* Enable the RTC Alarm (Absolute) Operation */ +#define BITP_RTC_CR0_CNTEN 0 /* Global Enable for the RTC */ +#define BITM_RTC_CR0_WPNDINTEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Write Pending Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_WSYNCINTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Write Synchronization Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_WPNDERRINTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ +#define BITM_RTC_CR0_ISOINTEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ +#define BITM_RTC_CR0_MOD60ALMINTEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ +#define BITM_RTC_CR0_MOD60ALM (_ADI_MSK_3(0x000007E0,0x000007E0U, uint16_t )) /* Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ +#define BITM_RTC_CR0_MOD60ALMEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ +#define BITM_RTC_CR0_TRMEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable RTC Digital Trimming */ +#define BITM_RTC_CR0_ALMINTEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable ALMINT Sourced Alarm Interrupts to the CPU */ +#define BITM_RTC_CR0_ALMEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable the RTC Alarm (Absolute) Operation */ +#define BITM_RTC_CR0_CNTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Global Enable for the RTC */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR0_ISOENB 14 /* Visibility of 32kHz Sourced Registers */ +#define BITP_RTC_SR0_WSYNCTRM 13 /* Synchronisation Status of Posted Writes to TRM */ +#define BITP_RTC_SR0_WSYNCALM1 12 /* Synchronisation Status of Posted Writes to ALM1 */ +#define BITP_RTC_SR0_WSYNCALM0 11 /* Synchronisation Status of Posted Writes to ALM0 */ +#define BITP_RTC_SR0_WSYNCCNT1 10 /* Synchronisation Status of Posted Writes to CNT1 */ +#define BITP_RTC_SR0_WSYNCCNT0 9 /* Synchronisation Status of Posted Writes to CNT0 */ +#define BITP_RTC_SR0_WSYNCSR0 8 /* Synchronisation Status of Posted Writes to SR0 */ +#define BITP_RTC_SR0_WSYNCCR0 7 /* Synchronisation Status of Posted Writes to CR0 */ +#define BITP_RTC_SR0_WPNDINT 6 /* Write Pending Interrupt */ +#define BITP_RTC_SR0_WSYNCINT 5 /* Write Synchronisation Interrupt */ +#define BITP_RTC_SR0_WPNDERRINT 4 /* Write Pending Error Interrupt Source */ +#define BITP_RTC_SR0_ISOINT 3 /* RTC Power-Domain Isolation Interrupt Source */ +#define BITP_RTC_SR0_MOD60ALMINT 2 /* Modulo-60 RTC Alarm Interrupt Source */ +#define BITP_RTC_SR0_ALMINT 1 /* Alarm Interrupt Source */ +#define BITM_RTC_SR0_ISOENB (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Visibility of 32kHz Sourced Registers */ +#define BITM_RTC_SR0_WSYNCTRM (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronisation Status of Posted Writes to TRM */ +#define BITM_RTC_SR0_WSYNCALM1 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronisation Status of Posted Writes to ALM1 */ +#define BITM_RTC_SR0_WSYNCALM0 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Synchronisation Status of Posted Writes to ALM0 */ +#define BITM_RTC_SR0_WSYNCCNT1 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronisation Status of Posted Writes to CNT1 */ +#define BITM_RTC_SR0_WSYNCCNT0 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronisation Status of Posted Writes to CNT0 */ +#define BITM_RTC_SR0_WSYNCSR0 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronisation Status of Posted Writes to SR0 */ +#define BITM_RTC_SR0_WSYNCCR0 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Synchronisation Status of Posted Writes to CR0 */ +#define BITM_RTC_SR0_WPNDINT (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Write Pending Interrupt */ +#define BITM_RTC_SR0_WSYNCINT (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Write Synchronisation Interrupt */ +#define BITM_RTC_SR0_WPNDERRINT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Write Pending Error Interrupt Source */ +#define BITM_RTC_SR0_ISOINT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* RTC Power-Domain Isolation Interrupt Source */ +#define BITM_RTC_SR0_MOD60ALMINT (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Modulo-60 RTC Alarm Interrupt Source */ +#define BITM_RTC_SR0_ALMINT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Alarm Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR1_WPNDTRM 13 /* Pending Status of Posted Writes to TRM */ +#define BITP_RTC_SR1_WPNDALM1 12 /* Pending Status of Posted Writes to ALM1 */ +#define BITP_RTC_SR1_WPNDALM0 11 /* Pending Status of Posted Writes to ALM0 */ +#define BITP_RTC_SR1_WPNDCNT1 10 /* Pending Status of Posted Writes to CNT1 */ +#define BITP_RTC_SR1_WPNDCNT0 9 /* Pending Status of Posted Writes to CNT0 */ +#define BITP_RTC_SR1_WPNDSR0 8 /* Pending Status of Posted Clearances of Interrupt Sources in SR0 */ +#define BITP_RTC_SR1_WPNDCR0 7 /* Pending Status of Posted Writes to CR0 */ +#define BITM_RTC_SR1_WPNDTRM (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to TRM */ +#define BITM_RTC_SR1_WPNDALM1 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to ALM1 */ +#define BITM_RTC_SR1_WPNDALM0 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Pending Status of Posted Writes to ALM0 */ +#define BITM_RTC_SR1_WPNDCNT1 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Writes to CNT1 */ +#define BITM_RTC_SR1_WPNDCNT0 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to CNT0 */ +#define BITM_RTC_SR1_WPNDSR0 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Clearances of Interrupt Sources in SR0 */ +#define BITM_RTC_SR1_WPNDCR0 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Pending Status of Posted Writes to CR0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT0_VALUE 0 /* Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT1_VALUE 0 /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM0_VALUE 0 /* Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ +#define BITM_RTC_ALM0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM1_VALUE 0 /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ +#define BITM_RTC_ALM1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_TRM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_TRM_IVL2EXPMIN 6 /* Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ +#define BITP_RTC_TRM_IVL 4 /* Trim Interval in Prescaled RTC Time Units */ +#define BITP_RTC_TRM_ADD 3 /* Trim Polarity */ +#define BITP_RTC_TRM_VALUE 0 /* Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ +#define BITM_RTC_TRM_IVL2EXPMIN (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t )) /* Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ +#define BITM_RTC_TRM_IVL (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* Trim Interval in Prescaled RTC Time Units */ +#define BITM_RTC_TRM_ADD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Trim Polarity */ +#define BITM_RTC_TRM_VALUE (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GWY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GWY_SWKEY 0 /* Software-keyed Command Issued by the CPU */ +#define BITM_RTC_GWY_SWKEY (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Software-keyed Command Issued by the CPU */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR1_PRESCALE2EXP 5 /* Prescale Power of 2 Division Factor for the RTC Base Clock */ +#define BITP_RTC_CR1_CNTMOD60ROLLINTEN 4 /* Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ +#define BITP_RTC_CR1_CNTROLLINTEN 3 /* Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ +#define BITP_RTC_CR1_TRMINTEN 2 /* Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ +#define BITP_RTC_CR1_PSINTEN 1 /* Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ +#define BITP_RTC_CR1_CNTINTEN 0 /* Enable for the RTC Count Interrupt Source */ +#define BITM_RTC_CR1_PRESCALE2EXP (_ADI_MSK_3(0x000001E0,0x000001E0U, uint16_t )) /* Prescale Power of 2 Division Factor for the RTC Base Clock */ +#define BITM_RTC_CR1_CNTMOD60ROLLINTEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ +#define BITM_RTC_CR1_CNTROLLINTEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ +#define BITM_RTC_CR1_TRMINTEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ +#define BITM_RTC_CR1_PSINTEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ +#define BITM_RTC_CR1_CNTINTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable for the RTC Count Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR2_WSYNCALM2MIR 15 /* Synchronization Status of Posted Writes to ALM2 */ +#define BITP_RTC_SR2_WSYNCCR1MIR 14 /* Synchronization Status of Posted Writes to CR1 */ +#define BITP_RTC_SR2_WPNDALM2MIR 13 /* Pending Status of Posted Writes to ALM2 */ +#define BITP_RTC_SR2_WPNDCR1MIR 12 /* Pending Status of Posted Writes to CR1 */ +#define BITP_RTC_SR2_TRMBDYMIR 7 /* Mirror of MOD:RTCTRMBDY */ +#define BITP_RTC_SR2_CNTMOD60ROLL 6 /* RTC Count Modulo-60 Roll-Over */ +#define BITP_RTC_SR2_CNTROLL 5 /* RTC Count Roll-Over */ +#define BITP_RTC_SR2_CNTMOD60ROLLINT 4 /* RTC Modulo-60 Count Roll-Over Interrupt Source */ +#define BITP_RTC_SR2_CNTROLLINT 3 /* RTC Count Roll-Over Interrupt Source */ +#define BITP_RTC_SR2_TRMINT 2 /* RTC Trim Interrupt Source */ +#define BITP_RTC_SR2_PSINT 1 /* RTC Prescaled, Modulo-1 Boundary Interrupt Source */ +#define BITP_RTC_SR2_CNTINT 0 /* RTC Count Interrupt Source */ +#define BITM_RTC_SR2_WSYNCALM2MIR (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Status of Posted Writes to ALM2 */ +#define BITM_RTC_SR2_WSYNCCR1MIR (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Synchronization Status of Posted Writes to CR1 */ +#define BITM_RTC_SR2_WPNDALM2MIR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to ALM2 */ +#define BITM_RTC_SR2_WPNDCR1MIR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to CR1 */ +#define BITM_RTC_SR2_TRMBDYMIR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Mirror of MOD:RTCTRMBDY */ +#define BITM_RTC_SR2_CNTMOD60ROLL (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* RTC Count Modulo-60 Roll-Over */ +#define BITM_RTC_SR2_CNTROLL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* RTC Count Roll-Over */ +#define BITM_RTC_SR2_CNTMOD60ROLLINT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* RTC Modulo-60 Count Roll-Over Interrupt Source */ +#define BITM_RTC_SR2_CNTROLLINT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* RTC Count Roll-Over Interrupt Source */ +#define BITM_RTC_SR2_TRMINT (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* RTC Trim Interrupt Source */ +#define BITM_RTC_SR2_PSINT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* RTC Prescaled, Modulo-1 Boundary Interrupt Source */ +#define BITM_RTC_SR2_CNTINT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* RTC Count Interrupt Source */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP0_VALUE 0 /* Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ +#define BITM_RTC_SNAP0_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP1_VALUE 0 /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ +#define BITM_RTC_SNAP1_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SNAP2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SNAP2_VALUE 0 /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ +#define BITM_RTC_SNAP2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_MOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_MOD_CNT0_4TOZERO 11 /* Mirror of CNT0[4:0] */ +#define BITP_RTC_MOD_TRMBDY 10 /* Trim Boundary Indicator */ +#define BITP_RTC_MOD_INCR 6 /* Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ +#define BITP_RTC_MOD_CNTMOD60 0 /* Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ +#define BITM_RTC_MOD_CNT0_4TOZERO (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t )) /* Mirror of CNT0[4:0] */ +#define BITM_RTC_MOD_TRMBDY (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Trim Boundary Indicator */ +#define BITM_RTC_MOD_INCR (_ADI_MSK_3(0x000003C0,0x000003C0U, uint16_t )) /* Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ +#define BITM_RTC_MOD_CNTMOD60 (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CNT2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CNT2_VALUE 0 /* Fractional Bits of the RTC Real-Time Count */ +#define BITM_RTC_CNT2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Fractional Bits of the RTC Real-Time Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_ALM2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_ALM2_VALUE 0 /* Fractional Bits of the Alarm Target Time */ +#define BITM_RTC_ALM2_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFU, uint16_t )) /* Fractional Bits of the Alarm Target Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR3_ALMINTMIR 13 /* Read-only Mirror of the SR0:ALMINT Interrupt Source */ +#define BITP_RTC_SR3_SS4IRQ 12 /* Sticky Interrupt Source for the SensorStrobe Channel 4 */ +#define BITP_RTC_SR3_SS3IRQ 11 /* Sticky Interrupt Source for the SensorStrobe Channel 3 */ +#define BITP_RTC_SR3_SS2IRQ 10 /* Sticky Interrupt Source for the SensorStrobe Channel 2 */ +#define BITP_RTC_SR3_SS1IRQ 9 /* Sticky Interrupt Source for SensorStrobe Channel 1 */ +#define BITP_RTC_SR3_SS4FEIRQ 8 /* Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */ +#define BITP_RTC_SR3_SS3FEIRQ 7 /* Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */ +#define BITP_RTC_SR3_SS2FEIRQ 6 /* Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */ +#define BITP_RTC_SR3_SS1FEIRQ 5 /* Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */ +#define BITP_RTC_SR3_IC4IRQ 4 /* Sticky Interrupt Source for the RTC Input Capture Channel 4 */ +#define BITP_RTC_SR3_IC3IRQ 3 /* Sticky Interrupt Source for the RTC Input Capture Channel 3 */ +#define BITP_RTC_SR3_IC2IRQ 2 /* Sticky Interrupt Source for the RTC Input Capture Channel 2 */ +#define BITP_RTC_SR3_IC0IRQ 0 /* Sticky Interrupt Source for the RTC Input Capture Channel 0 */ +#define BITM_RTC_SR3_ALMINTMIR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Read-only Mirror of the SR0:ALMINT Interrupt Source */ +#define BITM_RTC_SR3_SS4IRQ (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 4 */ +#define BITM_RTC_SR3_SS3IRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 3 */ +#define BITM_RTC_SR3_SS2IRQ (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 2 */ +#define BITM_RTC_SR3_SS1IRQ (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Sticky Interrupt Source for SensorStrobe Channel 1 */ +#define BITM_RTC_SR3_SS4FEIRQ (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */ +#define BITM_RTC_SR3_SS3FEIRQ (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */ +#define BITM_RTC_SR3_SS2FEIRQ (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */ +#define BITM_RTC_SR3_SS1FEIRQ (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */ +#define BITM_RTC_SR3_IC4IRQ (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 4 */ +#define BITM_RTC_SR3_IC3IRQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 3 */ +#define BITM_RTC_SR3_IC2IRQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 2 */ +#define BITM_RTC_SR3_IC0IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Sticky Interrupt Source for the RTC Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR2IC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR2IC_ICOWUSEN 15 /* Enable Overwrite of Unread Snapshots for All Input Capture Channels */ +#define BITP_RTC_CR2IC_IC4IRQEN 14 /* Interrupt Enable for the RTC Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3IRQEN 13 /* Interrupt Enable for the RTC Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2IRQEN 12 /* Interrupt Enable for the RTC Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0IRQEN 10 /* Interrupt Enable for the RTC Input Capture Channel 0 */ +#define BITP_RTC_CR2IC_IC4LH 9 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3LH 8 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2LH 7 /* Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0LH 5 /* Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ +#define BITP_RTC_CR2IC_IC4EN 4 /* Enable for the RTC Input Capture Channel 4 */ +#define BITP_RTC_CR2IC_IC3EN 3 /* Enable for the RTC Input Capture Channel 3 */ +#define BITP_RTC_CR2IC_IC2EN 2 /* Enable for the RTC Input Capture Channel 2 */ +#define BITP_RTC_CR2IC_IC0EN 0 /* Enable for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_ICOWUSEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Enable Overwrite of Unread Snapshots for All Input Capture Channels */ +#define BITM_RTC_CR2IC_IC4IRQEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3IRQEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2IRQEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0IRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Interrupt Enable for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_IC4LH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3LH (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2LH (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0LH (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ +#define BITM_RTC_CR2IC_IC4EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the RTC Input Capture Channel 4 */ +#define BITM_RTC_CR2IC_IC3EN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the RTC Input Capture Channel 3 */ +#define BITM_RTC_CR2IC_IC2EN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the RTC Input Capture Channel 2 */ +#define BITM_RTC_CR2IC_IC0EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable for the RTC Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR3SS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR3SS_SS4IRQEN 12 /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */ +#define BITP_RTC_CR3SS_SS3IRQEN 11 /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */ +#define BITP_RTC_CR3SS_SS2IRQEN 10 /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */ +#define BITP_RTC_CR3SS_SS1IRQEN 9 /* Interrupt Enable for SensorStrobe Channel 1 */ +#define BITP_RTC_CR3SS_SS4FEIRQEN 8 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */ +#define BITP_RTC_CR3SS_SS3FEIRQEN 7 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */ +#define BITP_RTC_CR3SS_SS2FEIRQEN 6 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */ +#define BITP_RTC_CR3SS_SS1FEIRQEN 5 /* Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */ +#define BITP_RTC_CR3SS_SS4EN 4 /* Enable for the SensorStrobe Channel 4 */ +#define BITP_RTC_CR3SS_SS3EN 3 /* Enable for the SensorStrobe Channel 3 */ +#define BITP_RTC_CR3SS_SS2EN 2 /* Enable for the SensorStrobe Channel 2 */ +#define BITP_RTC_CR3SS_SS1EN 1 /* Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS4IRQEN (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */ +#define BITM_RTC_CR3SS_SS3IRQEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */ +#define BITM_RTC_CR3SS_SS2IRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */ +#define BITM_RTC_CR3SS_SS1IRQEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Interrupt Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS4FEIRQEN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */ +#define BITM_RTC_CR3SS_SS3FEIRQEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */ +#define BITM_RTC_CR3SS_SS2FEIRQEN (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */ +#define BITM_RTC_CR3SS_SS1FEIRQEN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */ +#define BITM_RTC_CR3SS_SS4EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for the SensorStrobe Channel 4 */ +#define BITM_RTC_CR3SS_SS3EN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for the SensorStrobe Channel 3 */ +#define BITM_RTC_CR3SS_SS2EN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for the SensorStrobe Channel 2 */ +#define BITM_RTC_CR3SS_SS1EN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR4SS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR4SS_SS3ARLEN 11 /* Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */ +#define BITP_RTC_CR4SS_SS2ARLEN 10 /* Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */ +#define BITP_RTC_CR4SS_SS1ARLEN 9 /* Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */ +#define BITP_RTC_CR4SS_SS4POL 8 /* SensorStrobe Channel 4 Polarity Control */ +#define BITP_RTC_CR4SS_SS3POL 7 /* SensorStrobe Channel 3 Polarity Control */ +#define BITP_RTC_CR4SS_SS2POL 6 /* SensorStrobe Channel 2 Polarity Control */ +#define BITP_RTC_CR4SS_SS1POL 5 /* SensorSTrobe Channel 1 Polarity Control */ +#define BITP_RTC_CR4SS_SS4MSKEN 4 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */ +#define BITP_RTC_CR4SS_SS3MSKEN 3 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */ +#define BITP_RTC_CR4SS_SS2MSKEN 2 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */ +#define BITP_RTC_CR4SS_SS1MSKEN 1 /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ +#define BITM_RTC_CR4SS_SS3ARLEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */ +#define BITM_RTC_CR4SS_SS2ARLEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */ +#define BITM_RTC_CR4SS_SS1ARLEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */ +#define BITM_RTC_CR4SS_SS4POL (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* SensorStrobe Channel 4 Polarity Control */ +#define BITM_RTC_CR4SS_SS3POL (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SensorStrobe Channel 3 Polarity Control */ +#define BITM_RTC_CR4SS_SS2POL (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SensorStrobe Channel 2 Polarity Control */ +#define BITM_RTC_CR4SS_SS1POL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SensorSTrobe Channel 1 Polarity Control */ +#define BITM_RTC_CR4SS_SS4MSKEN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */ +#define BITM_RTC_CR4SS_SS3MSKEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */ +#define BITM_RTC_CR4SS_SS2MSKEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */ +#define BITM_RTC_CR4SS_SS1MSKEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ +#define ENUM_RTC_CR4SS_NO_MSK (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1MSKEN: Do not apply a mask to SensorStrobe Channel 1 Register */ +#define ENUM_RTC_CR4SS_THERM_MSK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SS1MSKEN: Apply thermometer decoded mask */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SSMSK Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SSMSK_SS4MSK 12 /* SensorStrobe Channel 4 Period Control */ +#define BITP_RTC_SSMSK_SS3MSK 8 /* SensorStrobe Channel 3 Period Control */ +#define BITP_RTC_SSMSK_SS2MSK 4 /* SensorStrobe Channel 2 Period Control */ +#define BITP_RTC_SSMSK_SS1MSK 0 /* Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */ +#define BITM_RTC_SSMSK_SS4MSK (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* SensorStrobe Channel 4 Period Control */ +#define BITM_RTC_SSMSK_SS3MSK (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SensorStrobe Channel 3 Period Control */ +#define BITM_RTC_SSMSK_SS2MSK (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* SensorStrobe Channel 2 Period Control */ +#define BITM_RTC_SSMSK_SS1MSK (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC2_IC2 0 /* RTC Input Capture Channel 2 */ +#define BITM_RTC_IC2_IC2 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC3_IC3 0 /* RTC Input Capture Channel 3 */ +#define BITM_RTC_IC3_IC3 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_IC4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_IC4_IC4 0 /* RTC Input Capture Channel 4 */ +#define BITM_RTC_IC4_IC4 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Input Capture Channel 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1_SS1 0 /* SensorStrobe Channel 1 */ +#define BITM_RTC_SS1_SS1 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2_SS2 0 /* SensorStrobe Channel 2 */ +#define BITM_RTC_SS2_SS2 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3_SS3 0 /* SensorStrobe Channel 3 */ +#define BITM_RTC_SS3_SS3 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS4_SS4 0 /* SensorStrobe Channel 4 */ +#define BITM_RTC_SS4_SS4 (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* SensorStrobe Channel 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR4_WSYNCSSMSKOT 15 /* Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */ +#define BITP_RTC_SR4_RSYNCIC4 14 /* Synchronization Status of Posted Reads of RTC Input Channel 4 */ +#define BITP_RTC_SR4_RSYNCIC3 13 /* Synchronization Status of Posted Reads of RTC Input Channel 3 */ +#define BITP_RTC_SR4_RSYNCIC2 12 /* Synchronization Status of Posted Reads of RTC Input Channel 2 */ +#define BITP_RTC_SR4_RSYNCIC0 10 /* Synchronization Status of Posted Reads of RTC Input Channel 0 */ +#define BITP_RTC_SR4_WSYNCSS4 9 /* Synchronization Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITP_RTC_SR4_WSYNCSS3 8 /* Synchronization Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITP_RTC_SR4_WSYNCSS2 7 /* Synchronization Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITP_RTC_SR4_WSYNCSS1 6 /* Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITP_RTC_SR4_WSYNCSSMSK 4 /* Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR4SS 3 /* Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR3SS 2 /* Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR4_WSYNCCR2IC 1 /* Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITP_RTC_SR4_WSYNCSR3 0 /* Synchronisation Status of Posted Writes to SR3 */ +#define BITM_RTC_SR4_WSYNCSSMSKOT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */ +#define BITM_RTC_SR4_RSYNCIC4 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 4 */ +#define BITM_RTC_SR4_RSYNCIC3 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 3 */ +#define BITM_RTC_SR4_RSYNCIC2 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 2 */ +#define BITM_RTC_SR4_RSYNCIC0 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronization Status of Posted Reads of RTC Input Channel 0 */ +#define BITM_RTC_SR4_WSYNCSS4 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITM_RTC_SR4_WSYNCSS3 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITM_RTC_SR4_WSYNCSS2 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITM_RTC_SR4_WSYNCSS1 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITM_RTC_SR4_WSYNCSSMSK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR4SS (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR3SS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR4_WSYNCCR2IC (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITM_RTC_SR4_WSYNCSR3 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Synchronisation Status of Posted Writes to SR3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR5_WPENDSSMSKOT 15 /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR5_RPENDIC4 14 /* Pending Status of Posted Reads of IC4 */ +#define BITP_RTC_SR5_RPENDIC3 13 /* Pending Status of Posted Reads of IC3 */ +#define BITP_RTC_SR5_RPENDIC2 12 /* Pending Status of Posted Reads of IC2 */ +#define BITP_RTC_SR5_RPENDIC0 10 /* Pending Status of Posted Reads of Input Capture Channel 0 */ +#define BITP_RTC_SR5_WPENDSS4 9 /* Pending Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITP_RTC_SR5_WPENDSS3 8 /* Pending Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITP_RTC_SR5_WPENDSS2 7 /* Pending Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITP_RTC_SR5_WPENDSS1 6 /* Pending Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITP_RTC_SR5_WPENDSSMSK 4 /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR4SS 3 /* Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR3SS 2 /* Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR5_WPENDCR2IC 1 /* Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITP_RTC_SR5_WPENDSR3 0 /* Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ +#define BITM_RTC_SR5_WPENDSSMSKOT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR5_RPENDIC4 (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Pending Status of Posted Reads of IC4 */ +#define BITM_RTC_SR5_RPENDIC3 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Reads of IC3 */ +#define BITM_RTC_SR5_RPENDIC2 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Reads of IC2 */ +#define BITM_RTC_SR5_RPENDIC0 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Reads of Input Capture Channel 0 */ +#define BITM_RTC_SR5_WPENDSS4 (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 4 */ +#define BITM_RTC_SR5_WPENDSS3 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 3 */ +#define BITM_RTC_SR5_WPENDSS2 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 2 */ +#define BITM_RTC_SR5_WPENDSS1 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Pending Status of Posted Writes to SensorStrobe Channel 1 */ +#define BITM_RTC_SR5_WPENDSSMSK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR4SS (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR3SS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR5_WPENDCR2IC (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ +#define BITM_RTC_SR5_WPENDSR3 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR6_FRZCNTPTR 9 /* Pointer for the Triple-Read Sequence of FRZCNT */ +#define BITP_RTC_SR6_IC0SNAP 8 /* Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ +#define BITP_RTC_SR6_IC4UNR 4 /* Sticky Unread Status of the Input Capture Channel 4 */ +#define BITP_RTC_SR6_IC3UNR 3 /* Sticky Unread Status of the Input Capture Channel 3 */ +#define BITP_RTC_SR6_IC2UNR 2 /* Sticky Unread Status of the Input Capture Channel 2 */ +#define BITP_RTC_SR6_IC0UNR 0 /* Sticky Unread Status of the Input Capture Channel 0 */ +#define BITM_RTC_SR6_FRZCNTPTR (_ADI_MSK_3(0x00000600,0x00000600U, uint16_t )) /* Pointer for the Triple-Read Sequence of FRZCNT */ +#define BITM_RTC_SR6_IC0SNAP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ +#define BITM_RTC_SR6_IC4UNR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 4 */ +#define BITM_RTC_SR6_IC3UNR (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 3 */ +#define BITM_RTC_SR6_IC2UNR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 2 */ +#define BITM_RTC_SR6_IC0UNR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Sticky Unread Status of the Input Capture Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1TGT_SS1TGT 0 /* Current Target Value for the SensorStrobe Channel 1 */ +#define BITM_RTC_SS1TGT_SS1TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Target Value for the SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_FRZCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_FRZCNT_FRZCNT 0 /* RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ +#define BITM_RTC_FRZCNT_FRZCNT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2TGT_SS2TGT 0 /* Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */ +#define BITM_RTC_SS2TGT_SS2TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3TGT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3TGT_SS3TGT 0 /* Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */ +#define BITM_RTC_SS3TGT_SS3TGT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1LOWDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1LOWDUR_SS1LOWDUR 0 /* Low Duration for SensorStrobe Channel 1. */ +#define BITM_RTC_SS1LOWDUR_SS1LOWDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Low Duration for SensorStrobe Channel 1. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2LOWDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2LOWDUR_SS2LOWDUR 0 /* Low Duration for SensorStrobe Channel 2. */ +#define BITM_RTC_SS2LOWDUR_SS2LOWDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Low Duration for SensorStrobe Channel 2. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3LOWDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3LOWDUR_SS3LOWDUR 0 /* Low Duration for SensorStrobe Channel 3. */ +#define BITM_RTC_SS3LOWDUR_SS3LOWDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Low Duration for SensorStrobe Channel 3. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS1HIGHDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS1HIGHDUR_SS1HIGHDUR 0 /* High Duration for SensorStrobe Channel 1. */ +#define BITM_RTC_SS1HIGHDUR_SS1HIGHDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* High Duration for SensorStrobe Channel 1. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS2HIGHDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS2HIGHDUR_SS2HIGHDUR 0 /* High Duration for SensorStrobe Channel 2. */ +#define BITM_RTC_SS2HIGHDUR_SS2HIGHDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* High Duration for SensorStrobe Channel 2. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SS3HIGHDUR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SS3HIGHDUR_SS3HIGHDUR 0 /* High Duration for SensorStrobe Channel 3. */ +#define BITM_RTC_SS3HIGHDUR_SS3HIGHDUR (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* High Duration for SensorStrobe Channel 3. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SSMSKOT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SSMSKOT_SS4MSKOT 12 /* SensorStrobe Channel 4 on Time Control */ +#define BITP_RTC_SSMSKOT_SS3MSKOT 8 /* SensorStrobe Channel 3 on Time Control */ +#define BITP_RTC_SSMSKOT_SS2MSKOT 4 /* SensorStrobe Channel 2 on Time Control */ +#define BITP_RTC_SSMSKOT_SS1MSKOT 0 /* Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */ +#define BITM_RTC_SSMSKOT_SS4MSKOT (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* SensorStrobe Channel 4 on Time Control */ +#define BITM_RTC_SSMSKOT_SS3MSKOT (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SensorStrobe Channel 3 on Time Control */ +#define BITM_RTC_SSMSKOT_SS2MSKOT (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* SensorStrobe Channel 2 on Time Control */ +#define BITM_RTC_SSMSKOT_SS1MSKOT (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR5SSS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR5SSS_SS3SMPMTCHIRQEN 11 /* Sample Activity Interrupt Enable for SensorStrobe Channel 3 */ +#define BITP_RTC_CR5SSS_SS3SMPEN 8 /* GPIO Input Sample Enable for SensorStrobe Channel 3 */ +#define BITP_RTC_CR5SSS_SS2SMPMTCHIRQEN 7 /* Sample Activity Interrupt Enable for SensorStrobe Channel 2 */ +#define BITP_RTC_CR5SSS_SS2SMPEN 4 /* GPIO Input Sample Enable for SensorStrobe Channel 2 */ +#define BITP_RTC_CR5SSS_SS1SMPMTCHIRQEN 3 /* Sample Activity Interrupt Enable for SensorStrobe Channel 1 */ +#define BITP_RTC_CR5SSS_SS1SMPEN 0 /* GPIO Input Sample Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR5SSS_SS3SMPMTCHIRQEN (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Sample Activity Interrupt Enable for SensorStrobe Channel 3 */ +#define BITM_RTC_CR5SSS_SS3SMPEN (_ADI_MSK_3(0x00000700,0x00000700U, uint16_t )) /* GPIO Input Sample Enable for SensorStrobe Channel 3 */ +#define BITM_RTC_CR5SSS_SS2SMPMTCHIRQEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Sample Activity Interrupt Enable for SensorStrobe Channel 2 */ +#define BITM_RTC_CR5SSS_SS2SMPEN (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* GPIO Input Sample Enable for SensorStrobe Channel 2 */ +#define BITM_RTC_CR5SSS_SS1SMPMTCHIRQEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sample Activity Interrupt Enable for SensorStrobe Channel 1 */ +#define BITM_RTC_CR5SSS_SS1SMPEN (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* GPIO Input Sample Enable for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR6SSS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR6SSS_SS3SMPONRE 10 /* GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */ +#define BITP_RTC_CR6SSS_SS3SMPONFE 8 /* GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */ +#define BITP_RTC_CR6SSS_SS2SMPONRE 6 /* GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */ +#define BITP_RTC_CR6SSS_SS2SMPONFE 4 /* GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */ +#define BITP_RTC_CR6SSS_SS1SMPONRE 2 /* GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */ +#define BITP_RTC_CR6SSS_SS1SMPONFE 0 /* GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */ +#define BITM_RTC_CR6SSS_SS3SMPONRE (_ADI_MSK_3(0x00000C00,0x00000C00U, uint16_t )) /* GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */ +#define BITM_RTC_CR6SSS_SS3SMPONFE (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */ +#define BITM_RTC_CR6SSS_SS2SMPONRE (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */ +#define BITM_RTC_CR6SSS_SS2SMPONFE (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */ +#define BITM_RTC_CR6SSS_SS1SMPONRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */ +#define BITM_RTC_CR6SSS_SS1SMPONFE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */ +#define ENUM_RTC_CR6SSS_SS3NORES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS3SMPONRE: No sampling of input around rising edge */ +#define ENUM_RTC_CR6SSS_SS3BRES (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* SS3SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3RES (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* SS3SMPONRE: Input sampled at rising edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3ARES (_ADI_MSK_3(0x00000C00,0x00000C00U, uint16_t )) /* SS3SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3NOFES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS3SMPONFE: No sampling of input around falling edge */ +#define ENUM_RTC_CR6SSS_SS3BFES (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* SS3SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3FES (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* SS3SMPONFE: Input sampled at falling edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS3AFES (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* SS3SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 */ +#define ENUM_RTC_CR6SSS_SS2NORES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS2SMPONRE: No sampling of input around rising edge */ +#define ENUM_RTC_CR6SSS_SS2BRES (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SS2SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2RES (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SS2SMPONRE: Input sampled at rising edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2ARES (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* SS2SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2NOFES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS2SMPONFE: No sampling of input around falling edge */ +#define ENUM_RTC_CR6SSS_SS2BFES (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SS2SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2FES (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SS2SMPONFE: Input sampled at falling edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS2AFES (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* SS2SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 */ +#define ENUM_RTC_CR6SSS_SS1NORES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1SMPONRE: No sampling of input around rising edge */ +#define ENUM_RTC_CR6SSS_SS1BRES (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* SS1SMPONRE: Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1RES (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SS1SMPONRE: Input sampled at rising edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1ARES (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* SS1SMPONRE: Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1NOFES (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1SMPONFE: No sampling of input around falling edge */ +#define ENUM_RTC_CR6SSS_SS1BFES (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SS1SMPONFE: Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1FES (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SS1SMPONFE: Input sampled at falling edge of the SensorStrobe channel 1 */ +#define ENUM_RTC_CR6SSS_SS1AFES (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* SS1SMPONFE: Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_CR7SSS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_CR7SSS_SS3SMPPTRN 13 /* Sample Activity Selection for SensorStrobe Channel 3 */ +#define BITP_RTC_CR7SSS_SS3SMPEXP 10 /* Expected GPIO Sample for SensorStrobe Channel 3 */ +#define BITP_RTC_CR7SSS_SS2SMPPTRN 8 /* Sample Activity Selection for SensorStrobe Channel 2 */ +#define BITP_RTC_CR7SSS_SS2SMPEXP 5 /* Expected GPIO Sample for SensorStrobe Channel 2 */ +#define BITP_RTC_CR7SSS_SS1SMPPTRN 3 /* Sample Activity Selection for SensorStrobe Channel 1 */ +#define BITP_RTC_CR7SSS_SS1SMPEXP 0 /* Expected GPIO Sample for SensorStrobe Channel 1 */ +#define BITM_RTC_CR7SSS_SS3SMPPTRN (_ADI_MSK_3(0x00006000,0x00006000U, uint16_t )) /* Sample Activity Selection for SensorStrobe Channel 3 */ +#define BITM_RTC_CR7SSS_SS3SMPEXP (_ADI_MSK_3(0x00001C00,0x00001C00U, uint16_t )) /* Expected GPIO Sample for SensorStrobe Channel 3 */ +#define BITM_RTC_CR7SSS_SS2SMPPTRN (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* Sample Activity Selection for SensorStrobe Channel 2 */ +#define BITM_RTC_CR7SSS_SS2SMPEXP (_ADI_MSK_3(0x000000E0,0x000000E0U, uint16_t )) /* Expected GPIO Sample for SensorStrobe Channel 2 */ +#define BITM_RTC_CR7SSS_SS1SMPPTRN (_ADI_MSK_3(0x00000018,0x00000018U, uint16_t )) /* Sample Activity Selection for SensorStrobe Channel 1 */ +#define BITM_RTC_CR7SSS_SS1SMPEXP (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Expected GPIO Sample for SensorStrobe Channel 1 */ +#define ENUM_RTC_CR7SSS_SS3SMPCHNG (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is not same as previous sample */ +#define ENUM_RTC_CR7SSS_SS3SMPSAME (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is same as previous sample */ +#define ENUM_RTC_CR7SSS_SS3SMPMTCH (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is same as expected sample */ +#define ENUM_RTC_CR7SSS_SS3SMPNOMTCH (_ADI_MSK_3(0x00006000,0x00006000U, uint16_t )) /* SS3SMPPTRN: Current GPIO sample is not same as expected sample */ +#define ENUM_RTC_CR7SSS_SS2SMPCHNG (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is not same as previous sample */ +#define ENUM_RTC_CR7SSS_SS2SMPSAME (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is same as previous sample */ +#define ENUM_RTC_CR7SSS_SS2SMPMTCH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is same as expected sample */ +#define ENUM_RTC_CR7SSS_SS2SMPNOMTCH (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* SS2SMPPTRN: Current GPIO sample is not same as expected sample */ +#define ENUM_RTC_CR7SSS_SS1SMPCHNG (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is not same as previous sample */ +#define ENUM_RTC_CR7SSS_SS1SMPSAME (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is same as previous sample */ +#define ENUM_RTC_CR7SSS_SS1SMPMTCH (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is same as expected sample */ +#define ENUM_RTC_CR7SSS_SS1SMPNOMTCH (_ADI_MSK_3(0x00000018,0x00000018U, uint16_t )) /* SS1SMPPTRN: Current GPIO sample is not same as expected sample */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR7_SS4OUT 15 /* Output Value for SensorStrobe Channel 4 */ +#define BITP_RTC_SR7_SS3OUT 14 /* Output Value for SensorStrobe Channel 3 */ +#define BITP_RTC_SR7_SS2OUT 13 /* Output Value for SensorStrobe Channel 2 */ +#define BITP_RTC_SR7_SS1OUT 12 /* Output Value for SensorStrobe Channel 1 */ +#define BITP_RTC_SR7_SS3SMPMTCHIRQ 11 /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */ +#define BITP_RTC_SR7_SS3SMP 8 /* Latest GPIO Sample for SensorStrobe Channel 3 */ +#define BITP_RTC_SR7_SS2SMPMTCHIRQ 7 /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */ +#define BITP_RTC_SR7_SS2SMP 4 /* Latest GPIO Sample for SensorStrobe Channel 2 */ +#define BITP_RTC_SR7_SS1SMPMTCHIRQ 3 /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */ +#define BITP_RTC_SR7_SS1SMP 0 /* Latest GPIO Sample for SensorStrobe Channel 1 */ +#define BITM_RTC_SR7_SS4OUT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Value for SensorStrobe Channel 4 */ +#define BITM_RTC_SR7_SS3OUT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Output Value for SensorStrobe Channel 3 */ +#define BITM_RTC_SR7_SS2OUT (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Output Value for SensorStrobe Channel 2 */ +#define BITM_RTC_SR7_SS1OUT (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Output Value for SensorStrobe Channel 1 */ +#define BITM_RTC_SR7_SS3SMPMTCHIRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */ +#define BITM_RTC_SR7_SS3SMP (_ADI_MSK_3(0x00000700,0x00000700U, uint16_t )) /* Latest GPIO Sample for SensorStrobe Channel 3 */ +#define BITM_RTC_SR7_SS2SMPMTCHIRQ (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */ +#define BITM_RTC_SR7_SS2SMP (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* Latest GPIO Sample for SensorStrobe Channel 2 */ +#define BITM_RTC_SR7_SS1SMPMTCHIRQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */ +#define BITM_RTC_SR7_SS1SMP (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* Latest GPIO Sample for SensorStrobe Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR8_WSYNCGPMUX1 13 /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */ +#define BITP_RTC_SR8_WSYNCGPMUX0 12 /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */ +#define BITP_RTC_SR8_WSYNCSR7 11 /* Synchronisation Status of Posted Writes to Status 7 Register */ +#define BITP_RTC_SR8_WSYNCCR7SSS 10 /* Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR8_WSYNCCR6SSS 9 /* Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR8_WSYNCCR5SSS 8 /* Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR8_WSYNCSS3HIGHDUR 6 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */ +#define BITP_RTC_SR8_WSYNCSS2HIGHDUR 5 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */ +#define BITP_RTC_SR8_WSYNCSS1HIGHDUR 4 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */ +#define BITP_RTC_SR8_WSYNCSS3LOWDUR 2 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */ +#define BITP_RTC_SR8_WSYNCSS2LOWDUR 1 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */ +#define BITP_RTC_SR8_WSYNCSS1LOWDUR 0 /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */ +#define BITM_RTC_SR8_WSYNCGPMUX1 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */ +#define BITM_RTC_SR8_WSYNCGPMUX0 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */ +#define BITM_RTC_SR8_WSYNCSR7 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Synchronisation Status of Posted Writes to Status 7 Register */ +#define BITM_RTC_SR8_WSYNCCR7SSS (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR8_WSYNCCR6SSS (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR8_WSYNCCR5SSS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR8_WSYNCSS3HIGHDUR (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */ +#define BITM_RTC_SR8_WSYNCSS2HIGHDUR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */ +#define BITM_RTC_SR8_WSYNCSS1HIGHDUR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */ +#define BITM_RTC_SR8_WSYNCSS3LOWDUR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */ +#define BITM_RTC_SR8_WSYNCSS2LOWDUR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */ +#define BITM_RTC_SR8_WSYNCSS1LOWDUR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_SR9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_SR9_WPENDGPMUX1 13 /* Pending Status of Posted Writes to GPMUX1 */ +#define BITP_RTC_SR9_WPENDGPMUX0 12 /* Pending Status of Posted Writes to GPMUX0 */ +#define BITP_RTC_SR9_WPENDSR7 11 /* Pending Status of Posted Writes to SR7 */ +#define BITP_RTC_SR9_WPENDCR7SSS 10 /* Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR9_WPENDCR6SSS 9 /* Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR9_WPENDCR5SSS 8 /* Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITP_RTC_SR9_WPENDSS3HIGHDUR 6 /* Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */ +#define BITP_RTC_SR9_WPENDSS2HIGHDUR 5 /* Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */ +#define BITP_RTC_SR9_WPENDSS1HIGHDUR 4 /* Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */ +#define BITP_RTC_SR9_WPENDSS3LOWDUR 2 /* Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */ +#define BITP_RTC_SR9_WPENDSS2LOWDUR 1 /* Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */ +#define BITP_RTC_SR9_WPENDSS1LOWDUR 0 /* Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */ +#define BITM_RTC_SR9_WPENDGPMUX1 (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Pending Status of Posted Writes to GPMUX1 */ +#define BITM_RTC_SR9_WPENDGPMUX0 (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Pending Status of Posted Writes to GPMUX0 */ +#define BITM_RTC_SR9_WPENDSR7 (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Pending Status of Posted Writes to SR7 */ +#define BITM_RTC_SR9_WPENDCR7SSS (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR9_WPENDCR6SSS (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR9_WPENDCR5SSS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ +#define BITM_RTC_SR9_WPENDSS3HIGHDUR (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */ +#define BITM_RTC_SR9_WPENDSS2HIGHDUR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */ +#define BITM_RTC_SR9_WPENDSS1HIGHDUR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */ +#define BITM_RTC_SR9_WPENDSS3LOWDUR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */ +#define BITM_RTC_SR9_WPENDSS2LOWDUR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */ +#define BITM_RTC_SR9_WPENDSS1LOWDUR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GPMUX0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GPMUX0_SS2GPIN1SEL 12 /* GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */ +#define BITP_RTC_GPMUX0_SS2GPIN0SEL 9 /* GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */ +#define BITP_RTC_GPMUX0_SS1GPIN2SEL 6 /* GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */ +#define BITP_RTC_GPMUX0_SS1GPIN1SEL 3 /* GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */ +#define BITP_RTC_GPMUX0_SS1GPIN0SEL 0 /* GPIO Mux Selection for SensorStrobe Channel 1 Input0 */ +#define BITM_RTC_GPMUX0_SS2GPIN1SEL (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */ +#define BITM_RTC_GPMUX0_SS2GPIN0SEL (_ADI_MSK_3(0x00000E00,0x00000E00U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */ +#define BITM_RTC_GPMUX0_SS1GPIN2SEL (_ADI_MSK_3(0x000001C0,0x000001C0U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */ +#define BITM_RTC_GPMUX0_SS1GPIN1SEL (_ADI_MSK_3(0x00000038,0x00000038U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */ +#define BITM_RTC_GPMUX0_SS1GPIN0SEL (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 1 Input0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RTC_GPMUX1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RTC_GPMUX1_SS3DIFFOUT 15 /* Differential SensorStrobe Out Option for SensorStrobe Channel 3 */ +#define BITP_RTC_GPMUX1_SS1DIFFOUT 14 /* Differential SensorStrobe Out Option for SensorStrobe Channel 1 */ +#define BITP_RTC_GPMUX1_SS3GPIN2SEL 9 /* GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */ +#define BITP_RTC_GPMUX1_SS3GPIN1SEL 6 /* GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */ +#define BITP_RTC_GPMUX1_SS3GPIN0SEL 3 /* GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */ +#define BITP_RTC_GPMUX1_SS2GPIN2SEL 0 /* GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */ +#define BITM_RTC_GPMUX1_SS3DIFFOUT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Differential SensorStrobe Out Option for SensorStrobe Channel 3 */ +#define BITM_RTC_GPMUX1_SS1DIFFOUT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Differential SensorStrobe Out Option for SensorStrobe Channel 1 */ +#define BITM_RTC_GPMUX1_SS3GPIN2SEL (_ADI_MSK_3(0x00000E00,0x00000E00U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */ +#define BITM_RTC_GPMUX1_SS3GPIN1SEL (_ADI_MSK_3(0x000001C0,0x000001C0U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */ +#define BITM_RTC_GPMUX1_SS3GPIN0SEL (_ADI_MSK_3(0x00000038,0x00000038U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */ +#define BITM_RTC_GPMUX1_SS2GPIN2SEL (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */ + + +/* ============================================================================================================================ + System Identification and Debug Enable + ============================================================================================================================ */ + +/* ============================================================================================================================ + SYS + ============================================================================================================================ */ +#define REG_SYS_ADIID 0x40002020 /* SYS ADI Identification */ +#define REG_SYS_CHIPID 0x40002024 /* SYS Chip Identifier */ +#define REG_SYS_SWDEN 0x40002040 /* SYS Serial Wire Debug Enable */ + +/* ============================================================================================================================ + SYS Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_ADIID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_ADIID_VALUE 0 /* Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */ +#define BITM_SYS_ADIID_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_CHIPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_CHIPID_PARTID 4 /* Part identifier */ +#define BITP_SYS_CHIPID_REV 0 /* Silicon revision */ +#define BITM_SYS_CHIPID_PARTID (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t )) /* Part identifier */ +#define BITM_SYS_CHIPID_REV (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Silicon revision */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SYS_SWDEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SYS_SWDEN_VALUE 0 /* To enable SWD interface */ +#define BITM_SYS_SWDEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* To enable SWD interface */ + + +/* ============================================================================================================================ + Watchdog Timer + ============================================================================================================================ */ + +/* ============================================================================================================================ + WDT0 + ============================================================================================================================ */ +#define REG_WDT0_LOAD 0x40002C00 /* WDT0 Load Value */ +#define REG_WDT0_CCNT 0x40002C04 /* WDT0 Current Count Value */ +#define REG_WDT0_CTL 0x40002C08 /* WDT0 Control */ +#define REG_WDT0_RESTART 0x40002C0C /* WDT0 Clear Interrupt */ +#define REG_WDT0_STAT 0x40002C18 /* WDT0 Status */ + +/* ============================================================================================================================ + WDT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_LOAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_LOAD_VALUE 0 /* Load Value */ +#define BITM_WDT_LOAD_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Load Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_CCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_CCNT_VALUE 0 /* Current Count Value */ +#define BITM_WDT_CCNT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Current Count Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_CTL_SPARE 7 /* Unused Spare Bit */ +#define BITP_WDT_CTL_MODE 6 /* Timer Mode */ +#define BITP_WDT_CTL_EN 5 /* Timer Enable */ +#define BITP_WDT_CTL_PRE 2 /* Prescaler */ +#define BITP_WDT_CTL_IRQ 1 /* Timer Interrupt */ +#define BITM_WDT_CTL_SPARE (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Unused Spare Bit */ +#define BITM_WDT_CTL_MODE (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Mode */ +#define BITM_WDT_CTL_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Timer Enable */ +#define BITM_WDT_CTL_PRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Prescaler */ +#define BITM_WDT_CTL_IRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Timer Interrupt */ +#define ENUM_WDT_CTL_FREE_RUN (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MODE: Free running mode */ +#define ENUM_WDT_CTL_PERIODIC (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* MODE: Periodic mode */ +#define ENUM_WDT_CTL_WDT_DIS (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* EN: WDT not enabled */ +#define ENUM_WDT_CTL_WDT_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* EN: WDT enabled */ +#define ENUM_WDT_CTL_DIV1 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* PRE: Source clock/1 */ +#define ENUM_WDT_CTL_DIV16 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* PRE: Source clock/16 */ +#define ENUM_WDT_CTL_DIV256 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* PRE: Source clock/256 (default) */ +#define ENUM_WDT_CTL_RST (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: WDT asserts reset when timed out */ +#define ENUM_WDT_CTL_INT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IRQ: WDT generates interrupt when timed out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_RESTART Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_RESTART_CLRWORD 0 /* Clear Watchdog */ +#define BITM_WDT_RESTART_CLRWORD (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Clear Watchdog */ + +/* ------------------------------------------------------------------------------------------------------------------------- + WDT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_WDT_STAT_RSTCTL 5 /* Reset Control Register Written and Locked */ +#define BITP_WDT_STAT_LOCKED 4 /* Lock Status Bit */ +#define BITP_WDT_STAT_COUNTING 3 /* Control Register Write Sync in Progress */ +#define BITP_WDT_STAT_LOADING 2 /* Load Register Write Sync in Progress */ +#define BITP_WDT_STAT_CLRIRQ 1 /* Clear Interrupt Register Write Sync in Progress */ +#define BITP_WDT_STAT_IRQ 0 /* WDT Interrupt */ +#define BITM_WDT_STAT_RSTCTL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Reset Control Register Written and Locked */ +#define BITM_WDT_STAT_LOCKED (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Lock Status Bit */ +#define BITM_WDT_STAT_COUNTING (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Control Register Write Sync in Progress */ +#define BITM_WDT_STAT_LOADING (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Load Register Write Sync in Progress */ +#define BITM_WDT_STAT_CLRIRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Interrupt Register Write Sync in Progress */ +#define BITM_WDT_STAT_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* WDT Interrupt */ + + +/* ============================================================================================================================ + I2C Master/Slave + ============================================================================================================================ */ + +/* ============================================================================================================================ + I2C0 + ============================================================================================================================ */ +#define REG_I2C0_MCTL 0x40003000 /* I2C0 Master Control */ +#define REG_I2C0_MSTAT 0x40003004 /* I2C0 Master Status */ +#define REG_I2C0_MRX 0x40003008 /* I2C0 Master Receive Data */ +#define REG_I2C0_MTX 0x4000300C /* I2C0 Master Transmit Data */ +#define REG_I2C0_MRXCNT 0x40003010 /* I2C0 Master Receive Data Count */ +#define REG_I2C0_MCRXCNT 0x40003014 /* I2C0 Master Current Receive Data Count */ +#define REG_I2C0_ADDR1 0x40003018 /* I2C0 Master Address Byte 1 */ +#define REG_I2C0_ADDR2 0x4000301C /* I2C0 Master Address Byte 2 */ +#define REG_I2C0_BYT 0x40003020 /* I2C0 Start Byte */ +#define REG_I2C0_DIV 0x40003024 /* I2C0 Serial Clock Period Divisor */ +#define REG_I2C0_SCTL 0x40003028 /* I2C0 Slave Control */ +#define REG_I2C0_SSTAT 0x4000302C /* I2C0 Slave I2C Status/Error/IRQ */ +#define REG_I2C0_SRX 0x40003030 /* I2C0 Slave Receive */ +#define REG_I2C0_STX 0x40003034 /* I2C0 Slave Transmit */ +#define REG_I2C0_ALT 0x40003038 /* I2C0 Hardware General Call ID */ +#define REG_I2C0_ID0 0x4000303C /* I2C0 First Slave Address Device ID */ +#define REG_I2C0_ID1 0x40003040 /* I2C0 Second Slave Address Device ID */ +#define REG_I2C0_ID2 0x40003044 /* I2C0 Third Slave Address Device ID */ +#define REG_I2C0_ID3 0x40003048 /* I2C0 Fourth Slave Address Device ID */ +#define REG_I2C0_STAT 0x4000304C /* I2C0 Master and Slave FIFO Status */ +#define REG_I2C0_SHCTL 0x40003050 /* I2C0 Shared Control */ +#define REG_I2C0_TCTL 0x40003054 /* I2C0 Timing Control Register */ +#define REG_I2C0_ASTRETCH_SCL 0x40003058 /* I2C0 Automatic Stretch SCL */ + +/* ============================================================================================================================ + I2C Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MCTL_STOPBUSCLR 13 /* Prestop Bus Clear */ +#define BITP_I2C_MCTL_BUSCLR 12 /* Bus-Clear Enable */ +#define BITP_I2C_MCTL_MTXDMA 11 /* Enable Master Tx DMA Request */ +#define BITP_I2C_MCTL_MRXDMA 10 /* Enable Master Rx DMA Request */ +#define BITP_I2C_MCTL_MXMITDEC 9 /* Decrement Master Tx FIFO Status When a Byte Txed */ +#define BITP_I2C_MCTL_IENCMP 8 /* Transaction Completed (or Stop Detected) Interrupt Enable */ +#define BITP_I2C_MCTL_IENACK 7 /* ACK Not Received Interrupt Enable */ +#define BITP_I2C_MCTL_IENALOST 6 /* Arbitration Lost Interrupt Enable */ +#define BITP_I2C_MCTL_IENMTX 5 /* Transmit Request Interrupt Enable */ +#define BITP_I2C_MCTL_IENMRX 4 /* Receive Request Interrupt Enable */ +#define BITP_I2C_MCTL_STRETCHSCL 3 /* Stretch SCL Enable */ +#define BITP_I2C_MCTL_LOOPBACK 2 /* Internal Loopback Enable */ +#define BITP_I2C_MCTL_COMPLETE 1 /* Start Back-off Disable */ +#define BITP_I2C_MCTL_MASEN 0 /* Master Enable */ +#define BITM_I2C_MCTL_STOPBUSCLR (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Prestop Bus Clear */ +#define BITM_I2C_MCTL_BUSCLR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Bus-Clear Enable */ +#define BITM_I2C_MCTL_MTXDMA (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Enable Master Tx DMA Request */ +#define BITM_I2C_MCTL_MRXDMA (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Enable Master Rx DMA Request */ +#define BITM_I2C_MCTL_MXMITDEC (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Decrement Master Tx FIFO Status When a Byte Txed */ +#define BITM_I2C_MCTL_IENCMP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Transaction Completed (or Stop Detected) Interrupt Enable */ +#define BITM_I2C_MCTL_IENACK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* ACK Not Received Interrupt Enable */ +#define BITM_I2C_MCTL_IENALOST (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Arbitration Lost Interrupt Enable */ +#define BITM_I2C_MCTL_IENMTX (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Transmit Request Interrupt Enable */ +#define BITM_I2C_MCTL_IENMRX (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Receive Request Interrupt Enable */ +#define BITM_I2C_MCTL_STRETCHSCL (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Stretch SCL Enable */ +#define BITM_I2C_MCTL_LOOPBACK (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Internal Loopback Enable */ +#define BITM_I2C_MCTL_COMPLETE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Start Back-off Disable */ +#define BITM_I2C_MCTL_MASEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Master Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MSTAT_SCLFILT 14 /* State of SCL Line */ +#define BITP_I2C_MSTAT_SDAFILT 13 /* State of SDA Line */ +#define BITP_I2C_MSTAT_MTXUNDR 12 /* Master Transmit Underflow */ +#define BITP_I2C_MSTAT_MSTOP 11 /* STOP Driven by This I2C Master */ +#define BITP_I2C_MSTAT_LINEBUSY 10 /* Line is Busy */ +#define BITP_I2C_MSTAT_MRXOVR 9 /* Master Receive FIFO Overflow */ +#define BITP_I2C_MSTAT_TCOMP 8 /* Transaction Complete or Stop Detected */ +#define BITP_I2C_MSTAT_NACKDATA 7 /* ACK Not Received in Response to Data Write */ +#define BITP_I2C_MSTAT_MBUSY 6 /* Master Busy */ +#define BITP_I2C_MSTAT_ALOST 5 /* Arbitration Lost */ +#define BITP_I2C_MSTAT_NACKADDR 4 /* ACK Not Received in Response to an Address */ +#define BITP_I2C_MSTAT_MRXREQ 3 /* Master Receive Request */ +#define BITP_I2C_MSTAT_MTXREQ 2 /* Master Transmit Request/Clear Master Transmit Interrupt */ +#define BITP_I2C_MSTAT_MTXF 0 /* Master Transmit FIFO Status */ +#define BITM_I2C_MSTAT_SCLFILT (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* State of SCL Line */ +#define BITM_I2C_MSTAT_SDAFILT (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* State of SDA Line */ +#define BITM_I2C_MSTAT_MTXUNDR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Master Transmit Underflow */ +#define BITM_I2C_MSTAT_MSTOP (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* STOP Driven by This I2C Master */ +#define BITM_I2C_MSTAT_LINEBUSY (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Line is Busy */ +#define BITM_I2C_MSTAT_MRXOVR (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Master Receive FIFO Overflow */ +#define BITM_I2C_MSTAT_TCOMP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Transaction Complete or Stop Detected */ +#define BITM_I2C_MSTAT_NACKDATA (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* ACK Not Received in Response to Data Write */ +#define BITM_I2C_MSTAT_MBUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Master Busy */ +#define BITM_I2C_MSTAT_ALOST (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Arbitration Lost */ +#define BITM_I2C_MSTAT_NACKADDR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* ACK Not Received in Response to an Address */ +#define BITM_I2C_MSTAT_MRXREQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Master Receive Request */ +#define BITM_I2C_MSTAT_MTXREQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Master Transmit Request/Clear Master Transmit Interrupt */ +#define BITM_I2C_MSTAT_MTXF (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Master Transmit FIFO Status */ +#define ENUM_I2C_MSTAT_FIFO_EMPTY (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* MTXF: FIFO Empty. */ +#define ENUM_I2C_MSTAT_FIFO_1BYTE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* MTXF: 1 byte in FIFO. */ +#define ENUM_I2C_MSTAT_FIFO_FULL (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* MTXF: FIFO Full. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MRX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MRX_VALUE 0 /* Master Receive Register */ +#define BITM_I2C_MRX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Master Receive Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MTX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MTX_VALUE 0 /* Master Transmit Register */ +#define BITM_I2C_MTX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Master Transmit Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MRXCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MRXCNT_EXTEND 8 /* Extended Read */ +#define BITP_I2C_MRXCNT_VALUE 0 /* Receive Count */ +#define BITM_I2C_MRXCNT_EXTEND (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Extended Read */ +#define BITM_I2C_MRXCNT_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Receive Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_MCRXCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_MCRXCNT_VALUE 0 /* Current Receive Count */ +#define BITM_I2C_MCRXCNT_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Current Receive Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ADDR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ADDR1_VALUE 0 /* Address Byte 1 */ +#define BITM_I2C_ADDR1_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Address Byte 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ADDR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ADDR2_VALUE 0 /* Address Byte 2 */ +#define BITM_I2C_ADDR2_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Address Byte 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_BYT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_BYT_SBYTE 0 /* Start Byte */ +#define BITM_I2C_BYT_SBYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Start Byte */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_DIV_HIGH 8 /* Serial Clock High Time */ +#define BITP_I2C_DIV_LOW 0 /* Serial Clock Low Time */ +#define BITM_I2C_DIV_HIGH (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* Serial Clock High Time */ +#define BITM_I2C_DIV_LOW (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Serial Clock Low Time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SCTL_STXDMA 14 /* Enable Slave Tx DMA Request */ +#define BITP_I2C_SCTL_SRXDMA 13 /* Enable Slave Rx DMA Request */ +#define BITP_I2C_SCTL_IENREPST 12 /* Repeated Start Interrupt Enable */ +#define BITP_I2C_SCTL_STXDEC 11 /* Decrement Slave Tx FIFO Status When a Byte is Txed */ +#define BITP_I2C_SCTL_IENSTX 10 /* Slave Transmit Request Interrupt Enable */ +#define BITP_I2C_SCTL_IENSRX 9 /* Slave Receive Request Interrupt Enable */ +#define BITP_I2C_SCTL_IENSTOP 8 /* Stop Condition Detected Interrupt Enable */ +#define BITP_I2C_SCTL_NACK 7 /* NACK Next Communication */ +#define BITP_I2C_SCTL_EARLYTXR 5 /* Early Transmit Request Mode */ +#define BITP_I2C_SCTL_GCSBCLR 4 /* General Call Status Bit Clear */ +#define BITP_I2C_SCTL_HGCEN 3 /* Hardware General Call Enable */ +#define BITP_I2C_SCTL_GCEN 2 /* General Call Enable */ +#define BITP_I2C_SCTL_ADR10EN 1 /* Enabled 10-bit Addressing */ +#define BITP_I2C_SCTL_SLVEN 0 /* Slave Enable */ +#define BITM_I2C_SCTL_STXDMA (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable Slave Tx DMA Request */ +#define BITM_I2C_SCTL_SRXDMA (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Enable Slave Rx DMA Request */ +#define BITM_I2C_SCTL_IENREPST (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Repeated Start Interrupt Enable */ +#define BITM_I2C_SCTL_STXDEC (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Decrement Slave Tx FIFO Status When a Byte is Txed */ +#define BITM_I2C_SCTL_IENSTX (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Slave Transmit Request Interrupt Enable */ +#define BITM_I2C_SCTL_IENSRX (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave Receive Request Interrupt Enable */ +#define BITM_I2C_SCTL_IENSTOP (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Stop Condition Detected Interrupt Enable */ +#define BITM_I2C_SCTL_NACK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* NACK Next Communication */ +#define BITM_I2C_SCTL_EARLYTXR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Early Transmit Request Mode */ +#define BITM_I2C_SCTL_GCSBCLR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* General Call Status Bit Clear */ +#define BITM_I2C_SCTL_HGCEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Hardware General Call Enable */ +#define BITM_I2C_SCTL_GCEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* General Call Enable */ +#define BITM_I2C_SCTL_ADR10EN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enabled 10-bit Addressing */ +#define BITM_I2C_SCTL_SLVEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Slave Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SSTAT_START 14 /* Start and Matching Address */ +#define BITP_I2C_SSTAT_REPSTART 13 /* Repeated Start and Matching Address */ +#define BITP_I2C_SSTAT_IDMAT 11 /* Device ID Matched */ +#define BITP_I2C_SSTAT_STOP 10 /* Stop After Start and Matching Address */ +#define BITP_I2C_SSTAT_GCID 8 /* General ID */ +#define BITP_I2C_SSTAT_GCINT 7 /* General Call Interrupt */ +#define BITP_I2C_SSTAT_SBUSY 6 /* Slave Busy */ +#define BITP_I2C_SSTAT_NOACK 5 /* ACK Not Generated by the Slave */ +#define BITP_I2C_SSTAT_SRXOVR 4 /* Slave Receive FIFO Overflow */ +#define BITP_I2C_SSTAT_SRXREQ 3 /* Slave Receive Request */ +#define BITP_I2C_SSTAT_STXREQ 2 /* Slave Transmit Request/Slave Transmit Interrupt */ +#define BITP_I2C_SSTAT_STXUNDR 1 /* Slave Transmit FIFO Underflow */ +#define BITP_I2C_SSTAT_STXFSEREQ 0 /* Slave Tx FIFO Status or Early Request */ +#define BITM_I2C_SSTAT_START (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Start and Matching Address */ +#define BITM_I2C_SSTAT_REPSTART (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Repeated Start and Matching Address */ +#define BITM_I2C_SSTAT_IDMAT (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t )) /* Device ID Matched */ +#define BITM_I2C_SSTAT_STOP (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Stop After Start and Matching Address */ +#define BITM_I2C_SSTAT_GCID (_ADI_MSK_3(0x00000300,0x00000300U, uint16_t )) /* General ID */ +#define BITM_I2C_SSTAT_GCINT (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* General Call Interrupt */ +#define BITM_I2C_SSTAT_SBUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Slave Busy */ +#define BITM_I2C_SSTAT_NOACK (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* ACK Not Generated by the Slave */ +#define BITM_I2C_SSTAT_SRXOVR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Slave Receive FIFO Overflow */ +#define BITM_I2C_SSTAT_SRXREQ (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Slave Receive Request */ +#define BITM_I2C_SSTAT_STXREQ (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Slave Transmit Request/Slave Transmit Interrupt */ +#define BITM_I2C_SSTAT_STXUNDR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Slave Transmit FIFO Underflow */ +#define BITM_I2C_SSTAT_STXFSEREQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Slave Tx FIFO Status or Early Request */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SRX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SRX_VALUE 0 /* Slave Receive Register */ +#define BITM_I2C_SRX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Receive Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_STX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_STX_VALUE 0 /* Slave Transmit Register */ +#define BITM_I2C_STX_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Transmit Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ALT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ALT_ID 0 /* Slave Alt */ +#define BITM_I2C_ALT_ID (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Alt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID0_VALUE 0 /* Slave Device ID 0 */ +#define BITM_I2C_ID0_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID1_VALUE 0 /* Slave Device ID 1 */ +#define BITM_I2C_ID1_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID2_VALUE 0 /* Slave Device ID 2 */ +#define BITM_I2C_ID2_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ID3_VALUE 0 /* Slave Device ID 3 */ +#define BITM_I2C_ID3_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Slave Device ID 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_STAT_MFLUSH 9 /* Flush the Master Transmit FIFO */ +#define BITP_I2C_STAT_SFLUSH 8 /* Flush the Slave Transmit FIFO */ +#define BITP_I2C_STAT_MRXF 6 /* Master Receive FIFO Status */ +#define BITP_I2C_STAT_MTXF 4 /* Master Transmit FIFO Status */ +#define BITP_I2C_STAT_SRXF 2 /* Slave Receive FIFO Status */ +#define BITP_I2C_STAT_STXF 0 /* Slave Transmit FIFO Status */ +#define BITM_I2C_STAT_MFLUSH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Flush the Master Transmit FIFO */ +#define BITM_I2C_STAT_SFLUSH (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Flush the Slave Transmit FIFO */ +#define BITM_I2C_STAT_MRXF (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* Master Receive FIFO Status */ +#define BITM_I2C_STAT_MTXF (_ADI_MSK_3(0x00000030,0x00000030U, uint16_t )) /* Master Transmit FIFO Status */ +#define BITM_I2C_STAT_SRXF (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Slave Receive FIFO Status */ +#define BITM_I2C_STAT_STXF (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Slave Transmit FIFO Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_SHCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_SHCTL_RST 0 /* Reset START STOP Detect Circuit */ +#define BITM_I2C_SHCTL_RST (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Reset START STOP Detect Circuit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_TCTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_TCTL_FILTEROFF 8 /* Input Filter Control */ +#define BITP_I2C_TCTL_THDATIN 0 /* Data in Hold Start */ +#define BITM_I2C_TCTL_FILTEROFF (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Input Filter Control */ +#define BITM_I2C_TCTL_THDATIN (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Data in Hold Start */ + +/* ------------------------------------------------------------------------------------------------------------------------- + I2C_ASTRETCH_SCL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_I2C_ASTRETCH_SCL_SLVTMO 9 /* Slave Automatic Stretch Timeout */ +#define BITP_I2C_ASTRETCH_SCL_MSTTMO 8 /* Master Automatic Stretch Timeout */ +#define BITP_I2C_ASTRETCH_SCL_SLV 4 /* Slave Automatic Stretch Mode */ +#define BITP_I2C_ASTRETCH_SCL_MST 0 /* Master Automatic Stretch Mode */ +#define BITM_I2C_ASTRETCH_SCL_SLVTMO (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave Automatic Stretch Timeout */ +#define BITM_I2C_ASTRETCH_SCL_MSTTMO (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Master Automatic Stretch Timeout */ +#define BITM_I2C_ASTRETCH_SCL_SLV (_ADI_MSK_3(0x000000F0,0x000000F0U, uint16_t )) /* Slave Automatic Stretch Mode */ +#define BITM_I2C_ASTRETCH_SCL_MST (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Master Automatic Stretch Mode */ + + +/* ============================================================================================================================ + Serial Peripheral Interface + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPI0 + ============================================================================================================================ */ +#define REG_SPI0_STAT 0x40004000 /* SPI0 Status */ +#define REG_SPI0_RX 0x40004004 /* SPI0 Receive */ +#define REG_SPI0_TX 0x40004008 /* SPI0 Transmit */ +#define REG_SPI0_DIV 0x4000400C /* SPI0 SPI Baud Rate Selection */ +#define REG_SPI0_CTL 0x40004010 /* SPI0 SPI Configuration */ +#define REG_SPI0_IEN 0x40004014 /* SPI0 SPI Interrupts Enable */ +#define REG_SPI0_CNT 0x40004018 /* SPI0 Transfer Byte Count */ +#define REG_SPI0_DMA 0x4000401C /* SPI0 SPI DMA Enable */ +#define REG_SPI0_FIFO_STAT 0x40004020 /* SPI0 FIFO Status */ +#define REG_SPI0_RD_CTL 0x40004024 /* SPI0 Read Control */ +#define REG_SPI0_FLOW_CTL 0x40004028 /* SPI0 Flow Control */ +#define REG_SPI0_WAIT_TMR 0x4000402C /* SPI0 Wait Timer for Flow Control */ +#define REG_SPI0_CS_CTL 0x40004030 /* SPI0 Chip Select Control for Multi-slave Connections */ +#define REG_SPI0_CS_OVERRIDE 0x40004034 /* SPI0 Chip Select Override */ + +/* ============================================================================================================================ + SPI1 + ============================================================================================================================ */ +#define REG_SPI1_STAT 0x40004400 /* SPI1 Status */ +#define REG_SPI1_RX 0x40004404 /* SPI1 Receive */ +#define REG_SPI1_TX 0x40004408 /* SPI1 Transmit */ +#define REG_SPI1_DIV 0x4000440C /* SPI1 SPI Baud Rate Selection */ +#define REG_SPI1_CTL 0x40004410 /* SPI1 SPI Configuration */ +#define REG_SPI1_IEN 0x40004414 /* SPI1 SPI Interrupts Enable */ +#define REG_SPI1_CNT 0x40004418 /* SPI1 Transfer Byte Count */ +#define REG_SPI1_DMA 0x4000441C /* SPI1 SPI DMA Enable */ +#define REG_SPI1_FIFO_STAT 0x40004420 /* SPI1 FIFO Status */ +#define REG_SPI1_RD_CTL 0x40004424 /* SPI1 Read Control */ +#define REG_SPI1_FLOW_CTL 0x40004428 /* SPI1 Flow Control */ +#define REG_SPI1_WAIT_TMR 0x4000442C /* SPI1 Wait Timer for Flow Control */ +#define REG_SPI1_CS_CTL 0x40004430 /* SPI1 Chip Select Control for Multi-slave Connections */ +#define REG_SPI1_CS_OVERRIDE 0x40004434 /* SPI1 Chip Select Override */ + +/* ============================================================================================================================ + SPI2 + ============================================================================================================================ */ +#define REG_SPI2_STAT 0x40024000 /* SPI2 Status */ +#define REG_SPI2_RX 0x40024004 /* SPI2 Receive */ +#define REG_SPI2_TX 0x40024008 /* SPI2 Transmit */ +#define REG_SPI2_DIV 0x4002400C /* SPI2 SPI Baud Rate Selection */ +#define REG_SPI2_CTL 0x40024010 /* SPI2 SPI Configuration */ +#define REG_SPI2_IEN 0x40024014 /* SPI2 SPI Interrupts Enable */ +#define REG_SPI2_CNT 0x40024018 /* SPI2 Transfer Byte Count */ +#define REG_SPI2_DMA 0x4002401C /* SPI2 SPI DMA Enable */ +#define REG_SPI2_FIFO_STAT 0x40024020 /* SPI2 FIFO Status */ +#define REG_SPI2_RD_CTL 0x40024024 /* SPI2 Read Control */ +#define REG_SPI2_FLOW_CTL 0x40024028 /* SPI2 Flow Control */ +#define REG_SPI2_WAIT_TMR 0x4002402C /* SPI2 Wait Timer for Flow Control */ +#define REG_SPI2_CS_CTL 0x40024030 /* SPI2 Chip Select Control for Multi-slave Connections */ +#define REG_SPI2_CS_OVERRIDE 0x40024034 /* SPI2 Chip Select Override */ + +/* ============================================================================================================================ + SPI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_STAT_RDY 15 /* Detected an Edge on Ready Indicator for Flow Control */ +#define BITP_SPI_STAT_CSFALL 14 /* Detected a Falling Edge on CS, in Slave CON Mode */ +#define BITP_SPI_STAT_CSRISE 13 /* Detected a Rising Edge on CS, in Slave CON Mode */ +#define BITP_SPI_STAT_CSERR 12 /* Detected a CS Error Condition in Slave Mode */ +#define BITP_SPI_STAT_CS 11 /* CS Status */ +#define BITP_SPI_STAT_RXOVR 7 /* SPI Rx FIFO Overflow */ +#define BITP_SPI_STAT_RXIRQ 6 /* SPI Rx IRQ */ +#define BITP_SPI_STAT_TXIRQ 5 /* SPI Tx IRQ */ +#define BITP_SPI_STAT_TXUNDR 4 /* SPI Tx FIFO Underflow */ +#define BITP_SPI_STAT_TXDONE 3 /* SPI Tx Done in Read Command Mode */ +#define BITP_SPI_STAT_TXEMPTY 2 /* SPI Tx FIFO Empty Interrupt */ +#define BITP_SPI_STAT_XFRDONE 1 /* SPI Transfer Completion */ +#define BITP_SPI_STAT_IRQ 0 /* SPI Interrupt Status */ +#define BITM_SPI_STAT_RDY (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Detected an Edge on Ready Indicator for Flow Control */ +#define BITM_SPI_STAT_CSFALL (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Detected a Falling Edge on CS, in Slave CON Mode */ +#define BITM_SPI_STAT_CSRISE (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Detected a Rising Edge on CS, in Slave CON Mode */ +#define BITM_SPI_STAT_CSERR (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Detected a CS Error Condition in Slave Mode */ +#define BITM_SPI_STAT_CS (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* CS Status */ +#define BITM_SPI_STAT_RXOVR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* SPI Rx FIFO Overflow */ +#define BITM_SPI_STAT_RXIRQ (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SPI Rx IRQ */ +#define BITM_SPI_STAT_TXIRQ (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SPI Tx IRQ */ +#define BITM_SPI_STAT_TXUNDR (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SPI Tx FIFO Underflow */ +#define BITM_SPI_STAT_TXDONE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SPI Tx Done in Read Command Mode */ +#define BITM_SPI_STAT_TXEMPTY (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* SPI Tx FIFO Empty Interrupt */ +#define BITM_SPI_STAT_XFRDONE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SPI Transfer Completion */ +#define BITM_SPI_STAT_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SPI Interrupt Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_RX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_RX_BYTE2 8 /* 8-bit Receive Buffer, Used Only in DMA Modes */ +#define BITP_SPI_RX_BYTE1 0 /* 8-bit Receive Buffer */ +#define BITM_SPI_RX_BYTE2 (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* 8-bit Receive Buffer, Used Only in DMA Modes */ +#define BITM_SPI_RX_BYTE1 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* 8-bit Receive Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_TX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_TX_BYTE2 8 /* 8-bit Transmit Buffer, Used Only in DMA Modes */ +#define BITP_SPI_TX_BYTE1 0 /* 8-bit Transmit Buffer */ +#define BITM_SPI_TX_BYTE2 (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* 8-bit Transmit Buffer, Used Only in DMA Modes */ +#define BITM_SPI_TX_BYTE1 (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* 8-bit Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DIV_VALUE 0 /* SPI Clock Divider */ +#define BITM_SPI_DIV_VALUE (_ADI_MSK_3(0x0000003F,0x0000003FU, uint16_t )) /* SPI Clock Divider */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CTL_CSRST 14 /* Reset Mode for CS Error Bit */ +#define BITP_SPI_CTL_TFLUSH 13 /* SPI Tx FIFO Flush Enable */ +#define BITP_SPI_CTL_RFLUSH 12 /* SPI Rx FIFO Flush Enable */ +#define BITP_SPI_CTL_CON 11 /* Continuous Transfer Enable */ +#define BITP_SPI_CTL_LOOPBACK 10 /* Loopback Enable */ +#define BITP_SPI_CTL_OEN 9 /* Slave MISO Output Enable */ +#define BITP_SPI_CTL_RXOF 8 /* Rx Overflow Overwrite Enable */ +#define BITP_SPI_CTL_ZEN 7 /* Transmit Zeros Enable */ +#define BITP_SPI_CTL_TIM 6 /* SPI Transfer and Interrupt Mode */ +#define BITP_SPI_CTL_LSB 5 /* LSB First Transfer Enable */ +#define BITP_SPI_CTL_WOM 4 /* SPI Wired-OR Mode */ +#define BITP_SPI_CTL_CPOL 3 /* Serial Clock Polarity */ +#define BITP_SPI_CTL_CPHA 2 /* Serial Clock Phase Mode */ +#define BITP_SPI_CTL_MASEN 1 /* Master Mode Enable */ +#define BITP_SPI_CTL_SPIEN 0 /* SPI Enable */ +#define BITM_SPI_CTL_CSRST (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Reset Mode for CS Error Bit */ +#define BITM_SPI_CTL_TFLUSH (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SPI Tx FIFO Flush Enable */ +#define BITM_SPI_CTL_RFLUSH (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* SPI Rx FIFO Flush Enable */ +#define BITM_SPI_CTL_CON (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Continuous Transfer Enable */ +#define BITM_SPI_CTL_LOOPBACK (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Loopback Enable */ +#define BITM_SPI_CTL_OEN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Slave MISO Output Enable */ +#define BITM_SPI_CTL_RXOF (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Rx Overflow Overwrite Enable */ +#define BITM_SPI_CTL_ZEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Transmit Zeros Enable */ +#define BITM_SPI_CTL_TIM (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* SPI Transfer and Interrupt Mode */ +#define BITM_SPI_CTL_LSB (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* LSB First Transfer Enable */ +#define BITM_SPI_CTL_WOM (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* SPI Wired-OR Mode */ +#define BITM_SPI_CTL_CPOL (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Serial Clock Polarity */ +#define BITM_SPI_CTL_CPHA (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Serial Clock Phase Mode */ +#define BITM_SPI_CTL_MASEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Master Mode Enable */ +#define BITM_SPI_CTL_SPIEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SPI Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_IEN_TXEMPTY 14 /* Tx FIFO Empty Interrupt Enable */ +#define BITP_SPI_IEN_XFRDONE 13 /* SPI Transfer Completion Interrupt Enable */ +#define BITP_SPI_IEN_TXDONE 12 /* SPI Transmit Done Interrupt Enable */ +#define BITP_SPI_IEN_RDY 11 /* Ready Signal Edge Interrupt Enable */ +#define BITP_SPI_IEN_RXOVR 10 /* Rx Overflow Interrupt Enable */ +#define BITP_SPI_IEN_TXUNDR 9 /* Tx Underflow Interrupt Enable */ +#define BITP_SPI_IEN_CS 8 /* Enable Interrupt on Every CS Edge in Slave CON Mode */ +#define BITP_SPI_IEN_IRQMODE 0 /* SPI IRQ Mode Bits */ +#define BITM_SPI_IEN_TXEMPTY (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Tx FIFO Empty Interrupt Enable */ +#define BITM_SPI_IEN_XFRDONE (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* SPI Transfer Completion Interrupt Enable */ +#define BITM_SPI_IEN_TXDONE (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* SPI Transmit Done Interrupt Enable */ +#define BITM_SPI_IEN_RDY (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Ready Signal Edge Interrupt Enable */ +#define BITM_SPI_IEN_RXOVR (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Rx Overflow Interrupt Enable */ +#define BITM_SPI_IEN_TXUNDR (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Tx Underflow Interrupt Enable */ +#define BITM_SPI_IEN_CS (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Enable Interrupt on Every CS Edge in Slave CON Mode */ +#define BITM_SPI_IEN_IRQMODE (_ADI_MSK_3(0x00000007,0x00000007U, uint16_t )) /* SPI IRQ Mode Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CNT_FRAMECONT 15 /* Continue Frame */ +#define BITP_SPI_CNT_VALUE 0 /* Transfer Byte Count */ +#define BITM_SPI_CNT_FRAMECONT (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Continue Frame */ +#define BITM_SPI_CNT_VALUE (_ADI_MSK_3(0x00003FFF,0x00003FFFU, uint16_t )) /* Transfer Byte Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DMA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DMA_RXEN 2 /* Enable Receive DMA Request */ +#define BITP_SPI_DMA_TXEN 1 /* Enable Transmit DMA Request */ +#define BITP_SPI_DMA_EN 0 /* Enable DMA for Data Transfer */ +#define BITM_SPI_DMA_RXEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Receive DMA Request */ +#define BITM_SPI_DMA_TXEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable Transmit DMA Request */ +#define BITM_SPI_DMA_EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable DMA for Data Transfer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_FIFO_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_FIFO_STAT_RX 8 /* SPI Rx FIFO Dtatus */ +#define BITP_SPI_FIFO_STAT_TX 0 /* SPI Tx FIFO Status */ +#define BITM_SPI_FIFO_STAT_RX (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* SPI Rx FIFO Dtatus */ +#define BITM_SPI_FIFO_STAT_TX (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* SPI Tx FIFO Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_RD_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_RD_CTL_THREEPIN 8 /* Three Pin SPI Mode */ +#define BITP_SPI_RD_CTL_TXBYTES 2 /* Transmit Byte Count - 1 (Read Command) */ +#define BITP_SPI_RD_CTL_OVERLAP 1 /* Tx/Rx Overlap Mode */ +#define BITP_SPI_RD_CTL_CMDEN 0 /* Read Command Enable */ +#define BITM_SPI_RD_CTL_THREEPIN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Three Pin SPI Mode */ +#define BITM_SPI_RD_CTL_TXBYTES (_ADI_MSK_3(0x0000003C,0x0000003CU, uint16_t )) /* Transmit Byte Count - 1 (Read Command) */ +#define BITM_SPI_RD_CTL_OVERLAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Tx/Rx Overlap Mode */ +#define BITM_SPI_RD_CTL_CMDEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Read Command Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_FLOW_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_FLOW_CTL_RDBURSTSZ 6 /* Read Data Burst Size - 1 */ +#define BITP_SPI_FLOW_CTL_RDYPOL 4 /* Polarity of RDY/MISO Line */ +#define BITP_SPI_FLOW_CTL_MODE 0 /* Flow Control Mode */ +#define BITM_SPI_FLOW_CTL_RDBURSTSZ (_ADI_MSK_3(0x0000FFC0,0x0000FFC0U, uint16_t )) /* Read Data Burst Size - 1 */ +#define BITM_SPI_FLOW_CTL_RDYPOL (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Polarity of RDY/MISO Line */ +#define BITM_SPI_FLOW_CTL_MODE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Flow Control Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_WAIT_TMR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_WAIT_TMR_VALUE 0 /* Wait Timer */ +#define BITM_SPI_WAIT_TMR_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Wait Timer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CS_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CS_CTL_SEL 0 /* Chip Select Control */ +#define BITM_SPI_CS_CTL_SEL (_ADI_MSK_3(0x0000000F,0x0000000FU, uint16_t )) /* Chip Select Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CS_OVERRIDE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CS_OVERRIDE_CTL 0 /* CS Override Control */ +#define BITM_SPI_CS_OVERRIDE_CTL (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* CS Override Control */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + UART0 + ============================================================================================================================ */ +#define REG_UART0_RX 0x40005000 /* UART0 Receive Buffer Register */ +#define REG_UART0_TX 0x40005000 /* UART0 Transmit Holding Register */ +#define REG_UART0_IEN 0x40005004 /* UART0 Interrupt Enable */ +#define REG_UART0_IIR 0x40005008 /* UART0 Interrupt ID */ +#define REG_UART0_LCR 0x4000500C /* UART0 Line Control */ +#define REG_UART0_MCR 0x40005010 /* UART0 Modem Control */ +#define REG_UART0_LSR 0x40005014 /* UART0 Line Status */ +#define REG_UART0_MSR 0x40005018 /* UART0 Modem Status */ +#define REG_UART0_SCR 0x4000501C /* UART0 Scratch Buffer */ +#define REG_UART0_FCR 0x40005020 /* UART0 FIFO Control */ +#define REG_UART0_FBR 0x40005024 /* UART0 Fractional Baud Rate */ +#define REG_UART0_DIV 0x40005028 /* UART0 Baud Rate Divider */ +#define REG_UART0_LCR2 0x4000502C /* UART0 Second Line Control */ +#define REG_UART0_CTL 0x40005030 /* UART0 UART Control Register */ +#define REG_UART0_RFC 0x40005034 /* UART0 RX FIFO Byte Count */ +#define REG_UART0_TFC 0x40005038 /* UART0 TX FIFO Byte Count */ +#define REG_UART0_RSC 0x4000503C /* UART0 RS485 Half-duplex Control */ +#define REG_UART0_ACR 0x40005040 /* UART0 Auto Baud Control */ +#define REG_UART0_ASRL 0x40005044 /* UART0 Auto Baud Status (Low) */ +#define REG_UART0_ASRH 0x40005048 /* UART0 Auto Baud Status (High) */ + +/* ============================================================================================================================ + UART1 + ============================================================================================================================ */ +#define REG_UART1_RX 0x40005400 /* UART1 Receive Buffer Register */ +#define REG_UART1_TX 0x40005400 /* UART1 Transmit Holding Register */ +#define REG_UART1_IEN 0x40005404 /* UART1 Interrupt Enable */ +#define REG_UART1_IIR 0x40005408 /* UART1 Interrupt ID */ +#define REG_UART1_LCR 0x4000540C /* UART1 Line Control */ +#define REG_UART1_MCR 0x40005410 /* UART1 Modem Control */ +#define REG_UART1_LSR 0x40005414 /* UART1 Line Status */ +#define REG_UART1_MSR 0x40005418 /* UART1 Modem Status */ +#define REG_UART1_SCR 0x4000541C /* UART1 Scratch Buffer */ +#define REG_UART1_FCR 0x40005420 /* UART1 FIFO Control */ +#define REG_UART1_FBR 0x40005424 /* UART1 Fractional Baud Rate */ +#define REG_UART1_DIV 0x40005428 /* UART1 Baud Rate Divider */ +#define REG_UART1_LCR2 0x4000542C /* UART1 Second Line Control */ +#define REG_UART1_CTL 0x40005430 /* UART1 UART Control Register */ +#define REG_UART1_RFC 0x40005434 /* UART1 RX FIFO Byte Count */ +#define REG_UART1_TFC 0x40005438 /* UART1 TX FIFO Byte Count */ +#define REG_UART1_RSC 0x4000543C /* UART1 RS485 Half-duplex Control */ +#define REG_UART1_ACR 0x40005440 /* UART1 Auto Baud Control */ +#define REG_UART1_ASRL 0x40005444 /* UART1 Auto Baud Status (Low) */ +#define REG_UART1_ASRH 0x40005448 /* UART1 Auto Baud Status (High) */ + +/* ============================================================================================================================ + UART Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RX_RBR 0 /* Receive Buffer Register */ +#define BITM_UART_RX_RBR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Receive Buffer Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_TX Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_TX_THR 0 /* Transmit Holding Register */ +#define BITM_UART_TX_THR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Transmit Holding Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_IEN_EDMAR 5 /* DMA Requests in Receive Mode */ +#define BITP_UART_IEN_EDMAT 4 /* DMA Requests in Transmit Mode */ +#define BITP_UART_IEN_EDSSI 3 /* Modem Status Interrupt */ +#define BITP_UART_IEN_ELSI 2 /* Rx Status Interrupt */ +#define BITP_UART_IEN_ETBEI 1 /* Transmit Buffer Empty Interrupt */ +#define BITP_UART_IEN_ERBFI 0 /* Receive Buffer Full Interrupt */ +#define BITM_UART_IEN_EDMAR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* DMA Requests in Receive Mode */ +#define BITM_UART_IEN_EDMAT (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* DMA Requests in Transmit Mode */ +#define BITM_UART_IEN_EDSSI (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Modem Status Interrupt */ +#define BITM_UART_IEN_ELSI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Rx Status Interrupt */ +#define BITM_UART_IEN_ETBEI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Transmit Buffer Empty Interrupt */ +#define BITM_UART_IEN_ERBFI (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Receive Buffer Full Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_IIR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_IIR_FEND 6 /* FIFO Enabled */ +#define BITP_UART_IIR_STAT 1 /* Interrupt Status */ +#define BITP_UART_IIR_NIRQ 0 /* Interrupt Flag */ +#define BITM_UART_IIR_FEND (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* FIFO Enabled */ +#define BITM_UART_IIR_STAT (_ADI_MSK_3(0x0000000E,0x0000000EU, uint16_t )) /* Interrupt Status */ +#define BITM_UART_IIR_NIRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Flag */ +#define ENUM_UART_IIR_STAT_EDSSI (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* STAT: Modem status interrupt (Read MSR register to clear) */ +#define ENUM_UART_IIR_STAT_ETBEI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* STAT: Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */ +#define ENUM_UART_IIR_STAT_ERBFI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* STAT: Receive buffer full interrupt (Read Rx register to clear) */ +#define ENUM_UART_IIR_STAT_RLSI (_ADI_MSK_3(0x00000006,0x00000006U, uint16_t )) /* STAT: Receive line status interrupt (Read LSR register to clear) */ +#define ENUM_UART_IIR_STAT_RFTOI (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* STAT: Receive FIFO time-out interrupt (Read Rx register to clear) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LCR_BRK 6 /* Set Break */ +#define BITP_UART_LCR_SP 5 /* Stick Parity */ +#define BITP_UART_LCR_EPS 4 /* Parity Select */ +#define BITP_UART_LCR_PEN 3 /* Parity Enable */ +#define BITP_UART_LCR_STOP 2 /* Stop Bit */ +#define BITP_UART_LCR_WLS 0 /* Word Length Select */ +#define BITM_UART_LCR_BRK (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Set Break */ +#define BITM_UART_LCR_SP (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Stick Parity */ +#define BITM_UART_LCR_EPS (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Parity Select */ +#define BITM_UART_LCR_PEN (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Parity Enable */ +#define BITM_UART_LCR_STOP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Stop Bit */ +#define BITM_UART_LCR_WLS (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Word Length Select */ +#define ENUM_UART_LCR_PAR_NOTFORCED (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SP: Parity will not be forced based on Parity Select and Parity Enable bits. */ +#define ENUM_UART_LCR_PAR_FORCED (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* SP: Parity forced based on Parity Select and Parity Enable bits. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_MCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_MCR_LOOPBACK 4 /* Loopback Mode */ +#define BITP_UART_MCR_OUT2 3 /* Output 2 */ +#define BITP_UART_MCR_OUT1 2 /* Output 1 */ +#define BITP_UART_MCR_RTS 1 /* Request to Send */ +#define BITP_UART_MCR_DTR 0 /* Data Terminal Ready */ +#define BITM_UART_MCR_LOOPBACK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Loopback Mode */ +#define BITM_UART_MCR_OUT2 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Output 2 */ +#define BITM_UART_MCR_OUT1 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Output 1 */ +#define BITM_UART_MCR_RTS (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Request to Send */ +#define BITM_UART_MCR_DTR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Data Terminal Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LSR_FIFOERR 7 /* Rx FIFO Parity Error/Frame Error/Break Indication */ +#define BITP_UART_LSR_TEMT 6 /* Transmit and Shift Register Empty Status */ +#define BITP_UART_LSR_THRE 5 /* Transmit Register Empty */ +#define BITP_UART_LSR_BI 4 /* Break Indicator */ +#define BITP_UART_LSR_FE 3 /* Framing Error */ +#define BITP_UART_LSR_PE 2 /* Parity Error */ +#define BITP_UART_LSR_OE 1 /* Overrun Error */ +#define BITP_UART_LSR_DR 0 /* Data Ready */ +#define BITM_UART_LSR_FIFOERR (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Rx FIFO Parity Error/Frame Error/Break Indication */ +#define BITM_UART_LSR_TEMT (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Transmit and Shift Register Empty Status */ +#define BITM_UART_LSR_THRE (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Transmit Register Empty */ +#define BITM_UART_LSR_BI (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Break Indicator */ +#define BITM_UART_LSR_FE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Framing Error */ +#define BITM_UART_LSR_PE (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Parity Error */ +#define BITM_UART_LSR_OE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Overrun Error */ +#define BITM_UART_LSR_DR (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Data Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_MSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_MSR_DCD 7 /* Data Carrier Detect */ +#define BITP_UART_MSR_RI 6 /* Ring Indicator */ +#define BITP_UART_MSR_DSR 5 /* Data Set Ready */ +#define BITP_UART_MSR_CTS 4 /* Clear to Send */ +#define BITP_UART_MSR_DDCD 3 /* Delta DCD */ +#define BITP_UART_MSR_TERI 2 /* Trailing Edge RI */ +#define BITP_UART_MSR_DDSR 1 /* Delta DSR */ +#define BITP_UART_MSR_DCTS 0 /* Delta CTS */ +#define BITM_UART_MSR_DCD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Data Carrier Detect */ +#define BITM_UART_MSR_RI (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Ring Indicator */ +#define BITM_UART_MSR_DSR (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Data Set Ready */ +#define BITM_UART_MSR_CTS (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Clear to Send */ +#define BITM_UART_MSR_DDCD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Delta DCD */ +#define BITM_UART_MSR_TERI (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Trailing Edge RI */ +#define BITM_UART_MSR_DDSR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Delta DSR */ +#define BITM_UART_MSR_DCTS (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Delta CTS */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_SCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_SCR_SCR 0 /* Scratch */ +#define BITM_UART_SCR_SCR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Scratch */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_FCR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_FCR_RFTRIG 6 /* Rx FIFO Trigger Level */ +#define BITP_UART_FCR_FDMAMD 3 /* FIFO DMA Mode */ +#define BITP_UART_FCR_TFCLR 2 /* Clear Tx FIFO */ +#define BITP_UART_FCR_RFCLR 1 /* Clear Rx FIFO */ +#define BITP_UART_FCR_FIFOEN 0 /* FIFO Enable as to Work in 16550 Mode */ +#define BITM_UART_FCR_RFTRIG (_ADI_MSK_3(0x000000C0,0x000000C0U, uint16_t )) /* Rx FIFO Trigger Level */ +#define BITM_UART_FCR_FDMAMD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* FIFO DMA Mode */ +#define BITM_UART_FCR_TFCLR (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Clear Tx FIFO */ +#define BITM_UART_FCR_RFCLR (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Rx FIFO */ +#define BITM_UART_FCR_FIFOEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* FIFO Enable as to Work in 16550 Mode */ +#define ENUM_UART_FCR_MODE0 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* FDMAMD: In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */ +#define ENUM_UART_FCR_MODE1 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* FDMAMD: in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_FBR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_FBR_FBEN 15 /* Fractional Baud Rate Generator Enable */ +#define BITP_UART_FBR_DIVM 11 /* Fractional Baud Rate M Divide Bits 1 to 3 */ +#define BITP_UART_FBR_DIVN 0 /* Fractional Baud Rate N Divide Bits 0 to 2047 */ +#define BITM_UART_FBR_FBEN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Fractional Baud Rate Generator Enable */ +#define BITM_UART_FBR_DIVM (_ADI_MSK_3(0x00001800,0x00001800U, uint16_t )) /* Fractional Baud Rate M Divide Bits 1 to 3 */ +#define BITM_UART_FBR_DIVN (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t )) /* Fractional Baud Rate N Divide Bits 0 to 2047 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_DIV Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_DIV_DIV 0 /* Baud Rate Divider */ +#define BITM_UART_DIV_DIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Baud Rate Divider */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_LCR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_LCR2_OSR 0 /* Over Sample Rate */ +#define BITM_UART_LCR2_OSR (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Over Sample Rate */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_CTL_REV 8 /* UART Revision ID */ +#define BITP_UART_CTL_RXINV 4 /* Invert Receiver Line */ +#define BITP_UART_CTL_FORCECLK 1 /* Force UCLK on */ +#define BITM_UART_CTL_REV (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* UART Revision ID */ +#define BITM_UART_CTL_RXINV (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Invert Receiver Line */ +#define BITM_UART_CTL_FORCECLK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Force UCLK on */ +#define ENUM_UART_CTL_NOTINV_RX (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* RXINV: Don't invert receiver line (idling high). */ +#define ENUM_UART_CTL_INV_RX (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* RXINV: Invert receiver line (idling low). */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RFC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RFC_RFC 0 /* Current Rx FIFO Data Bytes */ +#define BITM_UART_RFC_RFC (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Current Rx FIFO Data Bytes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_TFC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_TFC_TFC 0 /* Current Tx FIFO Data Bytes */ +#define BITM_UART_TFC_TFC (_ADI_MSK_3(0x0000001F,0x0000001FU, uint16_t )) /* Current Tx FIFO Data Bytes */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_RSC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_RSC_DISTX 3 /* Hold off Tx When Receiving */ +#define BITP_UART_RSC_DISRX 2 /* Disable Rx When Transmitting */ +#define BITP_UART_RSC_OENSP 1 /* SOUT_EN De-assert Before Full Stop Bit(s) */ +#define BITP_UART_RSC_OENP 0 /* SOUT_EN Polarity */ +#define BITM_UART_RSC_DISTX (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Hold off Tx When Receiving */ +#define BITM_UART_RSC_DISRX (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Disable Rx When Transmitting */ +#define BITM_UART_RSC_OENSP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* SOUT_EN De-assert Before Full Stop Bit(s) */ +#define BITM_UART_RSC_OENP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* SOUT_EN Polarity */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ACR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ACR_EEC 8 /* Ending Edge Count */ +#define BITP_UART_ACR_SEC 4 /* Starting Edge Count */ +#define BITP_UART_ACR_TOIEN 2 /* Enable Time-out Interrupt */ +#define BITP_UART_ACR_DNIEN 1 /* Enable Done Interrupt */ +#define BITP_UART_ACR_ABE 0 /* Auto Baud Enable */ +#define BITM_UART_ACR_EEC (_ADI_MSK_3(0x00000F00,0x00000F00U, uint16_t )) /* Ending Edge Count */ +#define BITM_UART_ACR_SEC (_ADI_MSK_3(0x00000070,0x00000070U, uint16_t )) /* Starting Edge Count */ +#define BITM_UART_ACR_TOIEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Enable Time-out Interrupt */ +#define BITM_UART_ACR_DNIEN (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Enable Done Interrupt */ +#define BITM_UART_ACR_ABE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Auto Baud Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ASRL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ASRL_CNT 4 /* Auto Baud Counter Value */ +#define BITP_UART_ASRL_NEETO 3 /* Timed Out Due to No Valid Ending Edge Found */ +#define BITP_UART_ASRL_NSETO 2 /* Timed Out Due to No Valid Start Edge Found */ +#define BITP_UART_ASRL_BRKTO 1 /* Timed Out Due to Long Time Break Condition */ +#define BITP_UART_ASRL_DONE 0 /* Auto Baud Done Successfully */ +#define BITM_UART_ASRL_CNT (_ADI_MSK_3(0x0000FFF0,0x0000FFF0U, uint16_t )) /* Auto Baud Counter Value */ +#define BITM_UART_ASRL_NEETO (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timed Out Due to No Valid Ending Edge Found */ +#define BITM_UART_ASRL_NSETO (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Timed Out Due to No Valid Start Edge Found */ +#define BITM_UART_ASRL_BRKTO (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Timed Out Due to Long Time Break Condition */ +#define BITM_UART_ASRL_DONE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Auto Baud Done Successfully */ + +/* ------------------------------------------------------------------------------------------------------------------------- + UART_ASRH Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_UART_ASRH_CNT 0 /* Auto Baud Counter Value */ +#define BITM_UART_ASRH_CNT (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Auto Baud Counter Value */ + + +/* ============================================================================================================================ + Beeper Driver + ============================================================================================================================ */ + +/* ============================================================================================================================ + BEEP0 + ============================================================================================================================ */ +#define REG_BEEP0_CFG 0x40005C00 /* BEEP0 Beeper Configuration */ +#define REG_BEEP0_STAT 0x40005C04 /* BEEP0 Beeper Status */ +#define REG_BEEP0_TONEA 0x40005C08 /* BEEP0 Tone A Data */ +#define REG_BEEP0_TONEB 0x40005C0C /* BEEP0 Tone B Data */ + +/* ============================================================================================================================ + BEEP Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_CFG_SEQATENDIRQ 15 /* Sequence End IRQ */ +#define BITP_BEEP_CFG_SEQNEARENDIRQ 14 /* Sequence 1 Cycle from End IRQ */ +#define BITP_BEEP_CFG_BENDIRQ 13 /* Tone B End IRQ */ +#define BITP_BEEP_CFG_BSTARTIRQ 12 /* Tone B Start IRQ */ +#define BITP_BEEP_CFG_AENDIRQ 11 /* Tone A End IRQ */ +#define BITP_BEEP_CFG_ASTARTIRQ 10 /* Tone A Start IRQ */ +#define BITP_BEEP_CFG_EN 8 /* Beeper Enable */ +#define BITP_BEEP_CFG_SEQREPEAT 0 /* Beeper Sequence Repeat Value */ +#define BITM_BEEP_CFG_SEQATENDIRQ (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Sequence End IRQ */ +#define BITM_BEEP_CFG_SEQNEARENDIRQ (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Sequence 1 Cycle from End IRQ */ +#define BITM_BEEP_CFG_BENDIRQ (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Tone B End IRQ */ +#define BITM_BEEP_CFG_BSTARTIRQ (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Tone B Start IRQ */ +#define BITM_BEEP_CFG_AENDIRQ (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Tone A End IRQ */ +#define BITM_BEEP_CFG_ASTARTIRQ (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Tone A Start IRQ */ +#define BITM_BEEP_CFG_EN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Beeper Enable */ +#define BITM_BEEP_CFG_SEQREPEAT (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Beeper Sequence Repeat Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_STAT_SEQENDED 15 /* Sequencer Has Ended */ +#define BITP_BEEP_STAT_SEQNEAREND 14 /* Sequencer Last Tone-pair Has Started */ +#define BITP_BEEP_STAT_BENDED 13 /* Tone B Has Ended */ +#define BITP_BEEP_STAT_BSTARTED 12 /* Tone B Has Started */ +#define BITP_BEEP_STAT_AENDED 11 /* Tone A Has Ended */ +#define BITP_BEEP_STAT_ASTARTED 10 /* Tone A Has Started */ +#define BITP_BEEP_STAT_BUSY 8 /* Beeper is Busy */ +#define BITP_BEEP_STAT_SEQREMAIN 0 /* Remaining Tone-pair Iterations to Play in Sequence Mode */ +#define BITM_BEEP_STAT_SEQENDED (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Sequencer Has Ended */ +#define BITM_BEEP_STAT_SEQNEAREND (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Sequencer Last Tone-pair Has Started */ +#define BITM_BEEP_STAT_BENDED (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Tone B Has Ended */ +#define BITM_BEEP_STAT_BSTARTED (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Tone B Has Started */ +#define BITM_BEEP_STAT_AENDED (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Tone A Has Ended */ +#define BITM_BEEP_STAT_ASTARTED (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Tone A Has Started */ +#define BITM_BEEP_STAT_BUSY (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Beeper is Busy */ +#define BITM_BEEP_STAT_SEQREMAIN (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Remaining Tone-pair Iterations to Play in Sequence Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_TONEA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_TONEA_DIS 15 /* Output Disable */ +#define BITP_BEEP_TONEA_FREQ 8 /* Tone Frequency */ +#define BITP_BEEP_TONEA_DUR 0 /* Tone Duration */ +#define BITM_BEEP_TONEA_DIS (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Disable */ +#define BITM_BEEP_TONEA_FREQ (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t )) /* Tone Frequency */ +#define BITM_BEEP_TONEA_DUR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Tone Duration */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BEEP_TONEB Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BEEP_TONEB_DIS 15 /* Output Disable */ +#define BITP_BEEP_TONEB_FREQ 8 /* Tone Frequency */ +#define BITP_BEEP_TONEB_DUR 0 /* Tone Duration */ +#define BITM_BEEP_TONEB_DIS (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Output Disable */ +#define BITM_BEEP_TONEB_FREQ (_ADI_MSK_3(0x00007F00,0x00007F00U, uint16_t )) /* Tone Frequency */ +#define BITM_BEEP_TONEB_DUR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Tone Duration */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + ADC0 + ============================================================================================================================ */ +#define REG_ADC0_CFG 0x40007000 /* ADC0 ADC Configuration */ +#define REG_ADC0_PWRUP 0x40007004 /* ADC0 ADC Power-up Time */ +#define REG_ADC0_CAL_WORD 0x40007008 /* ADC0 Calibration Word */ +#define REG_ADC0_CNV_CFG 0x4000700C /* ADC0 ADC Conversion Configuration */ +#define REG_ADC0_CNV_TIME 0x40007010 /* ADC0 ADC Conversion Time */ +#define REG_ADC0_AVG_CFG 0x40007014 /* ADC0 Averaging Configuration */ +#define REG_ADC0_IRQ_EN 0x40007020 /* ADC0 Interrupt Enable */ +#define REG_ADC0_STAT 0x40007024 /* ADC0 ADC Status */ +#define REG_ADC0_OVF 0x40007028 /* ADC0 Overflow of Output Registers */ +#define REG_ADC0_ALERT 0x4000702C /* ADC0 Alert Indication */ +#define REG_ADC0_CH0_OUT 0x40007030 /* ADC0 Conversion Result Channel 0 */ +#define REG_ADC0_CH1_OUT 0x40007034 /* ADC0 Conversion Result Channel 1 */ +#define REG_ADC0_CH2_OUT 0x40007038 /* ADC0 Conversion Result Channel 2 */ +#define REG_ADC0_CH3_OUT 0x4000703C /* ADC0 Conversion Result Channel 3 */ +#define REG_ADC0_CH4_OUT 0x40007040 /* ADC0 Conversion Result Channel 4 */ +#define REG_ADC0_CH5_OUT 0x40007044 /* ADC0 Conversion Result Channel 5 */ +#define REG_ADC0_CH6_OUT 0x40007048 /* ADC0 Conversion Result Channel 6 */ +#define REG_ADC0_CH7_OUT 0x4000704C /* ADC0 Conversion Result Channel 7 */ +#define REG_ADC0_BAT_OUT 0x40007050 /* ADC0 Battery Monitoring Result */ +#define REG_ADC0_TMP_OUT 0x40007054 /* ADC0 Temperature Result */ +#define REG_ADC0_TMP2_OUT 0x40007058 /* ADC0 Temperature Result 2 */ +#define REG_ADC0_DMA_OUT 0x4000705C /* ADC0 DMA Output Register */ +#define REG_ADC0_LIM0_LO 0x40007060 /* ADC0 Channel 0 Low Limit */ +#define REG_ADC0_LIM0_HI 0x40007064 /* ADC0 Channel 0 High Limit */ +#define REG_ADC0_HYS0 0x40007068 /* ADC0 Channel 0 Hysteresis */ +#define REG_ADC0_LIM1_LO 0x40007070 /* ADC0 Channel 1 Low Limit */ +#define REG_ADC0_LIM1_HI 0x40007074 /* ADC0 Channel 1 High Limit */ +#define REG_ADC0_HYS1 0x40007078 /* ADC0 Channel 1 Hysteresis */ +#define REG_ADC0_LIM2_LO 0x40007080 /* ADC0 Channel 2 Low Limit */ +#define REG_ADC0_LIM2_HI 0x40007084 /* ADC0 Channel 2 High Limit */ +#define REG_ADC0_HYS2 0x40007088 /* ADC0 Channel 2 Hysteresis */ +#define REG_ADC0_LIM3_LO 0x40007090 /* ADC0 Channel 3 Low Limit */ +#define REG_ADC0_LIM3_HI 0x40007094 /* ADC0 Channel 3 High Limit */ +#define REG_ADC0_HYS3 0x40007098 /* ADC0 Channel 3 Hysteresis */ +#define REG_ADC0_CFG1 0x400070C0 /* ADC0 Reference Buffer Low Power Mode */ + +/* ============================================================================================================================ + ADC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CFG_VREFVBAT_DEL 10 /* Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */ +#define BITP_ADC_CFG_FAST_DISCH 9 /* For fast switchover of Vref from 2.5 V to 1.25 V */ +#define BITP_ADC_CFG_TMPEN 8 /* To power up temperature sensor */ +#define BITP_ADC_CFG_SINKEN 7 /* To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */ +#define BITP_ADC_CFG_RST 6 /* Resets internal buffers and registers when high */ +#define BITP_ADC_CFG_STARTCAL 5 /* To start a new offset calibration cycle */ +#define BITP_ADC_CFG_EN 4 /* To enable ADC subsystem */ +#define BITP_ADC_CFG_VREFVBAT 3 /* VRef VBAT */ +#define BITP_ADC_CFG_REFBUFEN 2 /* To enable internal reference buffer */ +#define BITP_ADC_CFG_VREFSEL 1 /* To select Vref as 1.25 V or 2.5 V */ +#define BITP_ADC_CFG_PWRUP 0 /* Powering up ADC */ +#define BITM_ADC_CFG_VREFVBAT_DEL (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */ +#define BITM_ADC_CFG_FAST_DISCH (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* For fast switchover of Vref from 2.5 V to 1.25 V */ +#define BITM_ADC_CFG_TMPEN (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* To power up temperature sensor */ +#define BITM_ADC_CFG_SINKEN (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */ +#define BITM_ADC_CFG_RST (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Resets internal buffers and registers when high */ +#define BITM_ADC_CFG_STARTCAL (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* To start a new offset calibration cycle */ +#define BITM_ADC_CFG_EN (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* To enable ADC subsystem */ +#define BITM_ADC_CFG_VREFVBAT (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* VRef VBAT */ +#define BITM_ADC_CFG_REFBUFEN (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* To enable internal reference buffer */ +#define BITM_ADC_CFG_VREFSEL (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* To select Vref as 1.25 V or 2.5 V */ +#define BITM_ADC_CFG_PWRUP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Powering up ADC */ +#define ENUM_ADC_CFG_EXT_REF (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* REFBUFEN: External reference is used */ +#define ENUM_ADC_CFG_BUF_REF (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* REFBUFEN: Reference buffer is enabled */ +#define ENUM_ADC_CFG_V_2P5 (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* VREFSEL: Vref = 2.5 V */ +#define ENUM_ADC_CFG_V_1P25 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* VREFSEL: Vref = 1.25 V */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_PWRUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_PWRUP_WAIT 0 /* Program this count to generate 20us wait time with respect to the PCLK frequency */ +#define BITM_ADC_PWRUP_WAIT (_ADI_MSK_3(0x000007FF,0x000007FFU, uint16_t )) /* Program this count to generate 20us wait time with respect to the PCLK frequency */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CAL_WORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CAL_WORD_VALUE 0 /* Offset calibration word */ +#define BITM_ADC_CAL_WORD_VALUE (_ADI_MSK_3(0x0000007F,0x0000007FU, uint16_t )) /* Offset calibration word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CNV_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CNV_CFG_MULTI 15 /* Set to start multiple conversions */ +#define BITP_ADC_CNV_CFG_SINGLE 14 /* Set to start single conversion */ +#define BITP_ADC_CNV_CFG_DMAEN 13 /* To enable DMA channel */ +#define BITP_ADC_CNV_CFG_AUTOMODE 12 /* To enable auto mode */ +#define BITP_ADC_CNV_CFG_TMP2 10 /* To select temperature measurement 2 */ +#define BITP_ADC_CNV_CFG_TMP 9 /* To select temperature measurement 1 */ +#define BITP_ADC_CNV_CFG_BAT 8 /* To enable battery monitoring */ +#define BITP_ADC_CNV_CFG_SEL 0 /* To select channel(s) to convert */ +#define BITM_ADC_CNV_CFG_MULTI (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Set to start multiple conversions */ +#define BITM_ADC_CNV_CFG_SINGLE (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Set to start single conversion */ +#define BITM_ADC_CNV_CFG_DMAEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* To enable DMA channel */ +#define BITM_ADC_CNV_CFG_AUTOMODE (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* To enable auto mode */ +#define BITM_ADC_CNV_CFG_TMP2 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* To select temperature measurement 2 */ +#define BITM_ADC_CNV_CFG_TMP (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* To select temperature measurement 1 */ +#define BITM_ADC_CNV_CFG_BAT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* To enable battery monitoring */ +#define BITM_ADC_CNV_CFG_SEL (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* To select channel(s) to convert */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CNV_TIME Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CNV_TIME_DLY 8 /* Delay between two consecutive conversions in terms of number of ACLK cycles */ +#define BITP_ADC_CNV_TIME_SAMPTIME 0 /* Number of clock cycles (ACLK) required for sampling */ +#define BITM_ADC_CNV_TIME_DLY (_ADI_MSK_3(0x0000FF00,0x0000FF00U, uint16_t )) /* Delay between two consecutive conversions in terms of number of ACLK cycles */ +#define BITM_ADC_CNV_TIME_SAMPTIME (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Number of clock cycles (ACLK) required for sampling */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_AVG_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_AVG_CFG_EN 15 /* To enable averaging on Channels enabled in enable register */ +#define BITP_ADC_AVG_CFG_OS 14 /* Enable oversampling */ +#define BITP_ADC_AVG_CFG_FACTOR 0 /* Program averaging factor for averaging enabled channels (1-256) */ +#define BITM_ADC_AVG_CFG_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable averaging on Channels enabled in enable register */ +#define BITM_ADC_AVG_CFG_OS (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Enable oversampling */ +#define BITM_ADC_AVG_CFG_FACTOR (_ADI_MSK_3(0x000000FF,0x000000FFU, uint16_t )) /* Program averaging factor for averaging enabled channels (1-256) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_IRQ_EN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_IRQ_EN_RDY 13 /* Set to enable interrupt when ADC is ready to convert */ +#define BITP_ADC_IRQ_EN_ALERT 12 /* Set to enable interrupt on crossing lower or higher limit */ +#define BITP_ADC_IRQ_EN_OVF 11 /* Set to enable interrupt in case of overflow */ +#define BITP_ADC_IRQ_EN_CALDONE 10 /* Set it to enable interrupt for calibration done */ +#define BITP_ADC_IRQ_EN_CNVDONE 0 /* Set it to enable interrupt after conversion is done */ +#define BITM_ADC_IRQ_EN_RDY (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Set to enable interrupt when ADC is ready to convert */ +#define BITM_ADC_IRQ_EN_ALERT (_ADI_MSK_3(0x00001000,0x00001000U, uint16_t )) /* Set to enable interrupt on crossing lower or higher limit */ +#define BITM_ADC_IRQ_EN_OVF (_ADI_MSK_3(0x00000800,0x00000800U, uint16_t )) /* Set to enable interrupt in case of overflow */ +#define BITM_ADC_IRQ_EN_CALDONE (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Set it to enable interrupt for calibration done */ +#define BITM_ADC_IRQ_EN_CNVDONE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Set it to enable interrupt after conversion is done */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_STAT_RDY 15 /* Indicates ADC is ready to start converting, when using external reference buffer */ +#define BITP_ADC_STAT_CALDONE 14 /* Indicates calibration is done */ +#define BITP_ADC_STAT_TMP2DONE 10 /* Indicates conversion is done for temperature sensing 2 */ +#define BITP_ADC_STAT_TMPDONE 9 /* Indicates conversion is done for temperature sensing */ +#define BITP_ADC_STAT_BATDONE 8 /* Indicates conversion done for battery monitoring */ +#define BITP_ADC_STAT_DONE7 7 /* Indicates conversion done on Channel 7 */ +#define BITP_ADC_STAT_DONE6 6 /* Indicates conversion done on Channel 6 */ +#define BITP_ADC_STAT_DONE5 5 /* Indicates conversion done on Channel 5 */ +#define BITP_ADC_STAT_DONE4 4 /* Indicates conversion done on Channel 4 */ +#define BITP_ADC_STAT_DONE3 3 /* Indicates conversion done on Channel 3 */ +#define BITP_ADC_STAT_DONE2 2 /* Indicates conversion done on Channel 2 */ +#define BITP_ADC_STAT_DONE1 1 /* Indicates conversion done on Channel 1 */ +#define BITP_ADC_STAT_DONE0 0 /* Indicates conversion done on Channel 0 */ +#define BITM_ADC_STAT_RDY (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Indicates ADC is ready to start converting, when using external reference buffer */ +#define BITM_ADC_STAT_CALDONE (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Indicates calibration is done */ +#define BITM_ADC_STAT_TMP2DONE (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Indicates conversion is done for temperature sensing 2 */ +#define BITM_ADC_STAT_TMPDONE (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Indicates conversion is done for temperature sensing */ +#define BITM_ADC_STAT_BATDONE (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Indicates conversion done for battery monitoring */ +#define BITM_ADC_STAT_DONE7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Indicates conversion done on Channel 7 */ +#define BITM_ADC_STAT_DONE6 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Indicates conversion done on Channel 6 */ +#define BITM_ADC_STAT_DONE5 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Indicates conversion done on Channel 5 */ +#define BITM_ADC_STAT_DONE4 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Indicates conversion done on Channel 4 */ +#define BITM_ADC_STAT_DONE3 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Indicates conversion done on Channel 3 */ +#define BITM_ADC_STAT_DONE2 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Indicates conversion done on Channel 2 */ +#define BITM_ADC_STAT_DONE1 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Indicates conversion done on Channel 1 */ +#define BITM_ADC_STAT_DONE0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Indicates conversion done on Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_OVF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_OVF_TMP2 10 /* Indicates overflow in temperature 2 output register */ +#define BITP_ADC_OVF_TMP 9 /* Indicates overflow in temperature output register */ +#define BITP_ADC_OVF_BAT 8 /* Indicates overflow in battery monitoring output register */ +#define BITP_ADC_OVF_CH7 7 /* Indicates overflow in channel 7 output register */ +#define BITP_ADC_OVF_CH6 6 /* Indicates overflow in channel 6 output register */ +#define BITP_ADC_OVF_CH5 5 /* Indicates overflow in channel 5 output register */ +#define BITP_ADC_OVF_CH4 4 /* Indicates overflow in channel 4 output register */ +#define BITP_ADC_OVF_CH3 3 /* Indicates overflow in channel 3 output register */ +#define BITP_ADC_OVF_CH2 2 /* Indicates overflow in channel 2 output register */ +#define BITP_ADC_OVF_CH1 1 /* Indicates overflow in channel 1 output register */ +#define BITP_ADC_OVF_CH0 0 /* Indicates overflow in channel 0 output register */ +#define BITM_ADC_OVF_TMP2 (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* Indicates overflow in temperature 2 output register */ +#define BITM_ADC_OVF_TMP (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Indicates overflow in temperature output register */ +#define BITM_ADC_OVF_BAT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Indicates overflow in battery monitoring output register */ +#define BITM_ADC_OVF_CH7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Indicates overflow in channel 7 output register */ +#define BITM_ADC_OVF_CH6 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Indicates overflow in channel 6 output register */ +#define BITM_ADC_OVF_CH5 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Indicates overflow in channel 5 output register */ +#define BITM_ADC_OVF_CH4 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Indicates overflow in channel 4 output register */ +#define BITM_ADC_OVF_CH3 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Indicates overflow in channel 3 output register */ +#define BITM_ADC_OVF_CH2 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Indicates overflow in channel 2 output register */ +#define BITM_ADC_OVF_CH1 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Indicates overflow in channel 1 output register */ +#define BITM_ADC_OVF_CH0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Indicates overflow in channel 0 output register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_ALERT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_ALERT_LO3 7 /* Channel 3 Low alert status */ +#define BITP_ADC_ALERT_HI3 6 /* Channel 3 High alert status */ +#define BITP_ADC_ALERT_LO2 5 /* Channel 2 Low alert status */ +#define BITP_ADC_ALERT_HI2 4 /* Channel 2 High alert status */ +#define BITP_ADC_ALERT_LO1 3 /* Channel 1 Low alert status */ +#define BITP_ADC_ALERT_HI1 2 /* Channel 1 High alert status */ +#define BITP_ADC_ALERT_LO0 1 /* Channel 0 Low alert status */ +#define BITP_ADC_ALERT_HI0 0 /* Channel 0 High alert status */ +#define BITM_ADC_ALERT_LO3 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Channel 3 Low alert status */ +#define BITM_ADC_ALERT_HI3 (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Channel 3 High alert status */ +#define BITM_ADC_ALERT_LO2 (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Channel 2 Low alert status */ +#define BITM_ADC_ALERT_HI2 (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Channel 2 High alert status */ +#define BITM_ADC_ALERT_LO1 (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Channel 1 Low alert status */ +#define BITM_ADC_ALERT_HI1 (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Channel 1 High alert status */ +#define BITM_ADC_ALERT_LO0 (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Channel 0 Low alert status */ +#define BITM_ADC_ALERT_HI0 (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Channel 0 High alert status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH0_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH0_OUT_RESULT 0 /* Conversion result of channel 0 is stored here */ +#define BITM_ADC_CH0_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 0 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH1_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH1_OUT_RESULT 0 /* Conversion result of channel 1 is stored here */ +#define BITM_ADC_CH1_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 1 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH2_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH2_OUT_RESULT 0 /* Conversion result of channel 2 is stored here */ +#define BITM_ADC_CH2_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 2 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH3_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH3_OUT_RESULT 0 /* Conversion result of channel 3 is stored here */ +#define BITM_ADC_CH3_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 3 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH4_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH4_OUT_RESULT 0 /* Conversion result of channel 4 is stored here */ +#define BITM_ADC_CH4_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 4 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH5_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH5_OUT_RESULT 0 /* Conversion result of channel 5 is stored here */ +#define BITM_ADC_CH5_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 5 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH6_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH6_OUT_RESULT 0 /* Conversion result of channel 6 is stored here */ +#define BITM_ADC_CH6_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 6 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CH7_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CH7_OUT_RESULT 0 /* Conversion result of channel 7 is stored here */ +#define BITM_ADC_CH7_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of channel 7 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_BAT_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_BAT_OUT_RESULT 0 /* Conversion result of battery monitoring is stored here */ +#define BITM_ADC_BAT_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of battery monitoring is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_TMP_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_TMP_OUT_RESULT 0 /* Conversion result of Temperature measurement 1 is stored here */ +#define BITM_ADC_TMP_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of Temperature measurement 1 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_TMP2_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_TMP2_OUT_RESULT 0 /* Conversion result of Temperature measurement 2 is stored here */ +#define BITM_ADC_TMP2_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Conversion result of Temperature measurement 2 is stored here */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_DMA_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_DMA_OUT_RESULT 0 /* Register to store conversion result for DMA */ +#define BITM_ADC_DMA_OUT_RESULT (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Register to store conversion result for DMA */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM0_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM0_LO_EN 15 /* To enable low limit comparison on Channel 0 */ +#define BITP_ADC_LIM0_LO_VALUE 0 /* Low limit value for channel 0 */ +#define BITM_ADC_LIM0_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 0 */ +#define BITM_ADC_LIM0_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM0_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM0_HI_EN 15 /* To enable high limit comparison on Channel 0 */ +#define BITP_ADC_LIM0_HI_VALUE 0 /* High limit value for channel 0 */ +#define BITM_ADC_LIM0_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 0 */ +#define BITM_ADC_LIM0_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS0_EN 15 /* To enable hysteresis for comparison on Channel 0 */ +#define BITP_ADC_HYS0_MONCYC 12 /* Program number of conversion cycles to monitor channel 0 before raising alert */ +#define BITP_ADC_HYS0_VALUE 0 /* Hysteresis value for Channel 0 */ +#define BITM_ADC_HYS0_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 0 */ +#define BITM_ADC_HYS0_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 0 before raising alert */ +#define BITM_ADC_HYS0_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM1_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM1_LO_EN 15 /* To enable low limit comparison on Channel 1 */ +#define BITP_ADC_LIM1_LO_VALUE 0 /* Low limit value for channel 1 */ +#define BITM_ADC_LIM1_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 1 */ +#define BITM_ADC_LIM1_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM1_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM1_HI_EN 15 /* To enable high limit comparison on Channel 1 */ +#define BITP_ADC_LIM1_HI_VALUE 0 /* High limit value for channel 1 */ +#define BITM_ADC_LIM1_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 1 */ +#define BITM_ADC_LIM1_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS1_EN 15 /* To enable hysteresis for comparison on Channel 1 */ +#define BITP_ADC_HYS1_MONCYC 12 /* Program number of conversion cycles to monitor channel 1 before raising alert */ +#define BITP_ADC_HYS1_VALUE 0 /* Hysteresis value for Channel 1 */ +#define BITM_ADC_HYS1_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 1 */ +#define BITM_ADC_HYS1_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 1 before raising alert */ +#define BITM_ADC_HYS1_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM2_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM2_LO_EN 15 /* To enable low limit comparison on Channel 2 */ +#define BITP_ADC_LIM2_LO_VALUE 0 /* Low limit value for channel 2 */ +#define BITM_ADC_LIM2_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 2 */ +#define BITM_ADC_LIM2_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM2_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM2_HI_EN 15 /* To enable high limit comparison on Channel 2 */ +#define BITP_ADC_LIM2_HI_VALUE 0 /* High limit value for channel 2 */ +#define BITM_ADC_LIM2_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 2 */ +#define BITM_ADC_LIM2_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS2_EN 15 /* To enable hysteresis for comparison on Channel 2 */ +#define BITP_ADC_HYS2_MONCYC 12 /* Program number of conversion cycles to monitor channel 2 before raising alert */ +#define BITP_ADC_HYS2_VALUE 0 /* Hysteresis value for Channel 2 */ +#define BITM_ADC_HYS2_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 2 */ +#define BITM_ADC_HYS2_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 2 before raising alert */ +#define BITM_ADC_HYS2_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM3_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM3_LO_EN 15 /* To enable low limit comparison on Channel 3 */ +#define BITP_ADC_LIM3_LO_VALUE 0 /* Low limit value for channel 3 */ +#define BITM_ADC_LIM3_LO_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable low limit comparison on Channel 3 */ +#define BITM_ADC_LIM3_LO_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Low limit value for channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_LIM3_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_LIM3_HI_EN 15 /* To enable high limit comparison on Channel 3 */ +#define BITP_ADC_LIM3_HI_VALUE 0 /* High limit value for channel 3 */ +#define BITM_ADC_LIM3_HI_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable high limit comparison on Channel 3 */ +#define BITM_ADC_LIM3_HI_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* High limit value for channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_HYS3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_HYS3_EN 15 /* To enable hysteresis for comparison on Channel 3 */ +#define BITP_ADC_HYS3_MONCYC 12 /* Program number of conversion cycles to monitor channel 3 before raising alert */ +#define BITP_ADC_HYS3_VALUE 0 /* Hysteresis value for Channel 3 */ +#define BITM_ADC_HYS3_EN (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* To enable hysteresis for comparison on Channel 3 */ +#define BITM_ADC_HYS3_MONCYC (_ADI_MSK_3(0x00007000,0x00007000U, uint16_t )) /* Program number of conversion cycles to monitor channel 3 before raising alert */ +#define BITM_ADC_HYS3_VALUE (_ADI_MSK_3(0x000001FF,0x000001FFU, uint16_t )) /* Hysteresis value for Channel 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + ADC_CFG1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_ADC_CFG1_RBUFLP 0 /* Enable low power mode for reference buffer */ +#define BITM_ADC_CFG1_RBUFLP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Enable low power mode for reference buffer */ + + +/* ============================================================================================================================ + DMA + ============================================================================================================================ */ + +/* ============================================================================================================================ + DMA0 + ============================================================================================================================ */ +#define REG_DMA0_STAT 0x40010000 /* DMA0 DMA Status */ +#define REG_DMA0_CFG 0x40010004 /* DMA0 DMA Configuration */ +#define REG_DMA0_PDBPTR 0x40010008 /* DMA0 DMA Channel Primary Control Database Pointer */ +#define REG_DMA0_ADBPTR 0x4001000C /* DMA0 DMA Channel Alternate Control Database Pointer */ +#define REG_DMA0_SWREQ 0x40010014 /* DMA0 DMA Channel Software Request */ +#define REG_DMA0_RMSK_SET 0x40010020 /* DMA0 DMA Channel Request Mask Set */ +#define REG_DMA0_RMSK_CLR 0x40010024 /* DMA0 DMA Channel Request Mask Clear */ +#define REG_DMA0_EN_SET 0x40010028 /* DMA0 DMA Channel Enable Set */ +#define REG_DMA0_EN_CLR 0x4001002C /* DMA0 DMA Channel Enable Clear */ +#define REG_DMA0_ALT_SET 0x40010030 /* DMA0 DMA Channel Primary Alternate Set */ +#define REG_DMA0_ALT_CLR 0x40010034 /* DMA0 DMA Channel Primary Alternate Clear */ +#define REG_DMA0_PRI_SET 0x40010038 /* DMA0 DMA Channel Priority Set */ +#define REG_DMA0_PRI_CLR 0x4001003C /* DMA0 DMA Channel Priority Clear */ +#define REG_DMA0_ERRCHNL_CLR 0x40010048 /* DMA0 DMA per Channel Error Clear */ +#define REG_DMA0_ERR_CLR 0x4001004C /* DMA0 DMA Bus Error Clear */ +#define REG_DMA0_INVALIDDESC_CLR 0x40010050 /* DMA0 DMA per Channel Invalid Descriptor Clear */ +#define REG_DMA0_BS_SET 0x40010800 /* DMA0 DMA Channel Bytes Swap Enable Set */ +#define REG_DMA0_BS_CLR 0x40010804 /* DMA0 DMA Channel Bytes Swap Enable Clear */ +#define REG_DMA0_SRCADDR_SET 0x40010810 /* DMA0 DMA Channel Source Address Decrement Enable Set */ +#define REG_DMA0_SRCADDR_CLR 0x40010814 /* DMA0 DMA Channel Source Address Decrement Enable Clear */ +#define REG_DMA0_DSTADDR_SET 0x40010818 /* DMA0 DMA Channel Destination Address Decrement Enable Set */ +#define REG_DMA0_DSTADDR_CLR 0x4001081C /* DMA0 DMA Channel Destination Address Decrement Enable Clear */ +#define REG_DMA0_REVID 0x40010FE0 /* DMA0 DMA Controller Revision ID */ + +/* ============================================================================================================================ + DMA Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_STAT_CHANM1 16 /* Number of Available DMA Channels Minus 1 */ +#define BITP_DMA_STAT_MEN 0 /* Enable Status of the Controller */ +#define BITM_DMA_STAT_CHANM1 (_ADI_MSK_3(0x001F0000,0x001F0000UL, uint32_t )) /* Number of Available DMA Channels Minus 1 */ +#define BITM_DMA_STAT_MEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Status of the Controller */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_CFG_MEN 0 /* Controller Enable */ +#define BITM_DMA_CFG_MEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Controller Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PDBPTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PDBPTR_ADDR 0 /* Pointer to the Base Address of the Primary Data Structure */ +#define BITM_DMA_PDBPTR_ADDR (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Pointer to the Base Address of the Primary Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ADBPTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ADBPTR_ADDR 0 /* Base Address of the Alternate Data Structure */ +#define BITM_DMA_ADBPTR_ADDR (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Base Address of the Alternate Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SWREQ Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SWREQ_CHAN 0 /* Generate Software Request */ +#define BITM_DMA_SWREQ_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Generate Software Request */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_RMSK_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_RMSK_SET_CHAN 0 /* Mask Requests from DMA Channels */ +#define BITM_DMA_RMSK_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Mask Requests from DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_RMSK_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_RMSK_CLR_CHAN 0 /* Clear Request Mask Set Bits */ +#define BITM_DMA_RMSK_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Clear Request Mask Set Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_EN_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_EN_SET_CHAN 0 /* Enable DMA Channels */ +#define BITM_DMA_EN_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Enable DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_EN_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_EN_CLR_CHAN 0 /* Disable DMA Channels */ +#define BITM_DMA_EN_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable DMA Channels */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ALT_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ALT_SET_CHAN 0 /* Control Structure Status / Select Alternate Structure */ +#define BITM_DMA_ALT_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Control Structure Status / Select Alternate Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ALT_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ALT_CLR_CHAN 0 /* Select Primary Data Structure */ +#define BITM_DMA_ALT_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Select Primary Data Structure */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PRI_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PRI_SET_CHAN 0 /* Configure Channel for High Priority */ +#define BITM_DMA_PRI_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Configure Channel for High Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_PRI_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_PRI_CLR_CHPRICLR 0 /* Configure Channel for Default Priority Level */ +#define BITM_DMA_PRI_CLR_CHPRICLR (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Configure Channel for Default Priority Level */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ERRCHNL_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ERRCHNL_CLR_CHAN 0 /* Per Channel Bus Error Status/Clear */ +#define BITM_DMA_ERRCHNL_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Per Channel Bus Error Status/Clear */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_ERR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_ERR_CLR_CHAN 0 /* Bus Error Status */ +#define BITM_DMA_ERR_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Bus Error Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_INVALIDDESC_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_INVALIDDESC_CLR_CHAN 0 /* Per Channel Invalid Descriptor Status/Clear */ +#define BITM_DMA_INVALIDDESC_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Per Channel Invalid Descriptor Status/Clear */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_BS_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_BS_SET_CHAN 0 /* Byte Swap Status */ +#define BITM_DMA_BS_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Byte Swap Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_BS_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_BS_CLR_CHAN 0 /* Disable Byte Swap */ +#define BITM_DMA_BS_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable Byte Swap */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SRCADDR_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SRCADDR_SET_CHAN 0 /* Source Address Decrement Status */ +#define BITM_DMA_SRCADDR_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Source Address Decrement Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_SRCADDR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_SRCADDR_CLR_CHAN 0 /* Disable Source Address Decrement */ +#define BITM_DMA_SRCADDR_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable Source Address Decrement */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_DSTADDR_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_DSTADDR_SET_CHAN 0 /* Destination Address Decrement Status */ +#define BITM_DMA_DSTADDR_SET_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Destination Address Decrement Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_DSTADDR_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_DSTADDR_CLR_CHAN 0 /* Disable Destination Address Decrement */ +#define BITM_DMA_DSTADDR_CLR_CHAN (_ADI_MSK_3(0x07FFFFFF,0x07FFFFFFUL, uint32_t )) /* Disable Destination Address Decrement */ + +/* ------------------------------------------------------------------------------------------------------------------------- + DMA_REVID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_DMA_REVID_VALUE 0 /* DMA Controller Revision ID */ +#define BITM_DMA_REVID_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* DMA Controller Revision ID */ + + +/* ============================================================================================================================ + Flash Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + FLCC0 + ============================================================================================================================ */ +#define REG_FLCC0_STAT 0x40018000 /* FLCC0 Status */ +#define REG_FLCC0_IEN 0x40018004 /* FLCC0 Interrupt Enable */ +#define REG_FLCC0_CMD 0x40018008 /* FLCC0 Command */ +#define REG_FLCC0_KH_ADDR 0x4001800C /* FLCC0 Write Address */ +#define REG_FLCC0_KH_DATA0 0x40018010 /* FLCC0 Write Lower Data */ +#define REG_FLCC0_KH_DATA1 0x40018014 /* FLCC0 Write Upper Data */ +#define REG_FLCC0_PAGE_ADDR0 0x40018018 /* FLCC0 Lower Page Address */ +#define REG_FLCC0_PAGE_ADDR1 0x4001801C /* FLCC0 Upper Page Address */ +#define REG_FLCC0_KEY 0x40018020 /* FLCC0 Key */ +#define REG_FLCC0_WR_ABORT_ADDR 0x40018024 /* FLCC0 Write Abort Address */ +#define REG_FLCC0_WRPROT 0x40018028 /* FLCC0 Write Protection */ +#define REG_FLCC0_SIGNATURE 0x4001802C /* FLCC0 Signature */ +#define REG_FLCC0_UCFG 0x40018030 /* FLCC0 User Configuration */ +#define REG_FLCC0_TIME_PARAM0 0x40018034 /* FLCC0 Time Parameter 0 */ +#define REG_FLCC0_TIME_PARAM1 0x40018038 /* FLCC0 Time Parameter 1 */ +#define REG_FLCC0_ABORT_EN_LO 0x4001803C /* FLCC0 IRQ Abort Enable (Lower Bits) */ +#define REG_FLCC0_ABORT_EN_HI 0x40018040 /* FLCC0 IRQ Abort Enable (Upper Bits) */ +#define REG_FLCC0_ECC_CFG 0x40018044 /* FLCC0 ECC Configuration */ +#define REG_FLCC0_ECC_ADDR 0x40018048 /* FLCC0 ECC Status (Address) */ +#define REG_FLCC0_POR_SEC 0x40018050 /* FLCC0 Flash Security */ +#define REG_FLCC0_VOL_CFG 0x40018054 /* FLCC0 Volatile Flash Configuration */ + +/* ============================================================================================================================ + FLCC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_STAT_ACCESS_MODE 31 /* Access Mode */ +#define BITP_FLCC_STAT_CACHESRAMPERR 29 /* SRAM parity errors in Cache Controller */ +#define BITP_FLCC_STAT_ECCDCODE 27 /* DCode AHB Bus Error ECC status */ +#define BITP_FLCC_STAT_ECCICODE 25 /* ICode AHB Bus Error ECC status */ +#define BITP_FLCC_STAT_ECCERRCNT 17 /* ECC correction counter */ +#define BITP_FLCC_STAT_ECCINFOSIGN 15 /* ECC status of flash initialization */ +#define BITP_FLCC_STAT_INIT 14 /* Flash controller initialization in progress */ +#define BITP_FLCC_STAT_SIGNERR 13 /* Signature check failure during initialization */ +#define BITP_FLCC_STAT_OVERLAP 11 /* Overlapping Command */ +#define BITP_FLCC_STAT_ECCRDERR 9 /* ECC IRQ cause */ +#define BITP_FLCC_STAT_ECCERRCMD 7 /* ECC errors detected during user issued SIGN command */ +#define BITP_FLCC_STAT_SLEEPING 6 /* Flash array is in low power (sleep) mode */ +#define BITP_FLCC_STAT_CMDFAIL 4 /* Provides information on command failures */ +#define BITP_FLCC_STAT_WRALCOMP 3 /* Write almost complete */ +#define BITP_FLCC_STAT_CMDCOMP 2 /* Command complete */ +#define BITP_FLCC_STAT_WRCLOSE 1 /* WRITE registers are closed */ +#define BITP_FLCC_STAT_CMDBUSY 0 /* Command busy */ +#define BITM_FLCC_STAT_ACCESS_MODE (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Access Mode */ +#define BITM_FLCC_STAT_CACHESRAMPERR (_ADI_MSK_3(0x20000000,0x20000000UL, uint32_t )) /* SRAM parity errors in Cache Controller */ +#define BITM_FLCC_STAT_ECCDCODE (_ADI_MSK_3(0x18000000,0x18000000UL, uint32_t )) /* DCode AHB Bus Error ECC status */ +#define BITM_FLCC_STAT_ECCICODE (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t )) /* ICode AHB Bus Error ECC status */ +#define BITM_FLCC_STAT_ECCERRCNT (_ADI_MSK_3(0x000E0000,0x000E0000UL, uint32_t )) /* ECC correction counter */ +#define BITM_FLCC_STAT_ECCINFOSIGN (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t )) /* ECC status of flash initialization */ +#define BITM_FLCC_STAT_INIT (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Flash controller initialization in progress */ +#define BITM_FLCC_STAT_SIGNERR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Signature check failure during initialization */ +#define BITM_FLCC_STAT_OVERLAP (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Overlapping Command */ +#define BITM_FLCC_STAT_ECCRDERR (_ADI_MSK_3(0x00000600,0x00000600UL, uint32_t )) /* ECC IRQ cause */ +#define BITM_FLCC_STAT_ECCERRCMD (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* ECC errors detected during user issued SIGN command */ +#define BITM_FLCC_STAT_SLEEPING (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Flash array is in low power (sleep) mode */ +#define BITM_FLCC_STAT_CMDFAIL (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Provides information on command failures */ +#define BITM_FLCC_STAT_WRALCOMP (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Write almost complete */ +#define BITM_FLCC_STAT_CMDCOMP (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Command complete */ +#define BITM_FLCC_STAT_WRCLOSE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* WRITE registers are closed */ +#define BITM_FLCC_STAT_CMDBUSY (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Command busy */ +#define ENUM_FLCC_STAT_DIRECT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ACCESS_MODE: Flash controller is currently in Direct Access mode; user access to all registers is enabled */ +#define ENUM_FLCC_STAT_INDIRECT (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* ACCESS_MODE: Flash Controller is currently in Indirect Access mode; user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_IEN_ECC_ERROR 6 /* Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */ +#define BITP_FLCC_IEN_ECC_CORRECT 4 /* Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */ +#define BITP_FLCC_IEN_CMDFAIL 2 /* Command fail interrupt enable */ +#define BITP_FLCC_IEN_WRALCMPLT 1 /* Write almost complete interrupt enable */ +#define BITP_FLCC_IEN_CMDCMPLT 0 /* Command complete interrupt enable */ +#define BITM_FLCC_IEN_ECC_ERROR (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */ +#define BITM_FLCC_IEN_ECC_CORRECT (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */ +#define BITM_FLCC_IEN_CMDFAIL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Command fail interrupt enable */ +#define BITM_FLCC_IEN_WRALCMPLT (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Write almost complete interrupt enable */ +#define BITM_FLCC_IEN_CMDCMPLT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Command complete interrupt enable */ +#define ENUM_FLCC_IEN_NONE_ERR (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ECC_ERROR: Do not generate a response to ECC events */ +#define ENUM_FLCC_IEN_BUS_ERR_ERR (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* ECC_ERROR: Generate Bus Errors in response to ECC events */ +#define ENUM_FLCC_IEN_IRQ_ERR (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* ECC_ERROR: Generate IRQs in response to ECC events */ +#define ENUM_FLCC_IEN_NONE_COR (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ECC_CORRECT: Do not generate a response to ECC events */ +#define ENUM_FLCC_IEN_BUS_ERR_COR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* ECC_CORRECT: Generate Bus Errors in response to ECC events */ +#define ENUM_FLCC_IEN_IRQ_COR (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* ECC_CORRECT: Generate IRQs in response to ECC events */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CMD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CMD_VALUE 0 /* Commands */ +#define BITM_FLCC_CMD_VALUE (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Commands */ +#define ENUM_FLCC_CMD_IDLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VALUE: IDLE */ +#define ENUM_FLCC_CMD_ABORT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* VALUE: ABORT */ +#define ENUM_FLCC_CMD_SLEEP (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* VALUE: Requests flash to enter Sleep mode */ +#define ENUM_FLCC_CMD_SIGN (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* VALUE: SIGN */ +#define ENUM_FLCC_CMD_WRITE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* VALUE: WRITE */ +#define ENUM_FLCC_CMD_BLANK_CHECK (_ADI_MSK_3(0x00000005,0x00000005UL, uint32_t )) /* VALUE: Checks all of User Space; fails if any bits in user space are cleared */ +#define ENUM_FLCC_CMD_ERASEPAGE (_ADI_MSK_3(0x00000006,0x00000006UL, uint32_t )) /* VALUE: ERASEPAGE */ +#define ENUM_FLCC_CMD_MASSERASE (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t )) /* VALUE: MASSERASE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_ADDR_VALUE 3 /* Address to be written on a WRITE command */ +#define BITM_FLCC_KH_ADDR_VALUE (_ADI_MSK_3(0x000FFFF8,0x000FFFF8UL, uint32_t )) /* Address to be written on a WRITE command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_DATA0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_DATA0_VALUE 0 /* Lower half of 64-bit dual word data to be written on a Write command */ +#define BITM_FLCC_KH_DATA0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Lower half of 64-bit dual word data to be written on a Write command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KH_DATA1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KH_DATA1_VALUE 0 /* Upper half of 64-bit dual word data to be written on a Write command */ +#define BITM_FLCC_KH_DATA1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Upper half of 64-bit dual word data to be written on a Write command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_PAGE_ADDR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_PAGE_ADDR0_VALUE 10 /* Lower address bits of the page address */ +#define BITM_FLCC_PAGE_ADDR0_VALUE (_ADI_MSK_3(0x000FFC00,0x000FFC00UL, uint32_t )) /* Lower address bits of the page address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_PAGE_ADDR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_PAGE_ADDR1_VALUE 10 /* Upper address bits of the page address */ +#define BITM_FLCC_PAGE_ADDR1_VALUE (_ADI_MSK_3(0x000FFC00,0x000FFC00UL, uint32_t )) /* Upper address bits of the page address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_KEY_VALUE 0 /* Key register */ +#define BITM_FLCC_KEY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key register */ +#define ENUM_FLCC_KEY_USERKEY (_ADI_MSK_3(0x676C7565,0x676C7565UL, uint32_t )) /* VALUE: USERKEY */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_WR_ABORT_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_WR_ABORT_ADDR_VALUE 0 /* Address of recently aborted write command */ +#define BITM_FLCC_WR_ABORT_ADDR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Address of recently aborted write command */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_WRPROT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_WRPROT_WORD 0 /* Clear bits to write protect related groups of user space pages */ +#define BITM_FLCC_WRPROT_WORD (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Clear bits to write protect related groups of user space pages */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_SIGNATURE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_SIGNATURE_VALUE 0 /* Read signature */ +#define BITM_FLCC_SIGNATURE_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Read signature */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_UCFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_UCFG_AUTOINCEN 1 /* Auto Address Increment for Key Hole Access */ +#define BITP_FLCC_UCFG_KHDMAEN 0 /* Key hole DMA enable */ +#define BITM_FLCC_UCFG_AUTOINCEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Auto Address Increment for Key Hole Access */ +#define BITM_FLCC_UCFG_KHDMAEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Key hole DMA enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_TIME_PARAM0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_TIME_PARAM0_TNVH1 28 /* NVSTR Hold time during Mass Erase */ +#define BITP_FLCC_TIME_PARAM0_TERASE 24 /* Erase Time */ +#define BITP_FLCC_TIME_PARAM0_TRCV 20 /* Recovery time */ +#define BITP_FLCC_TIME_PARAM0_TNVH 16 /* NVSTR Hold time */ +#define BITP_FLCC_TIME_PARAM0_TPROG 12 /* Program time */ +#define BITP_FLCC_TIME_PARAM0_TPGS 8 /* NVSTR to Program setup time */ +#define BITP_FLCC_TIME_PARAM0_TNVS 4 /* PROG/ERASE to NVSTR setup time */ +#define BITP_FLCC_TIME_PARAM0_DIVREFCLK 0 /* Divide Reference Clock (by 2) */ +#define BITM_FLCC_TIME_PARAM0_TNVH1 (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* NVSTR Hold time during Mass Erase */ +#define BITM_FLCC_TIME_PARAM0_TERASE (_ADI_MSK_3(0x0F000000,0x0F000000UL, uint32_t )) /* Erase Time */ +#define BITM_FLCC_TIME_PARAM0_TRCV (_ADI_MSK_3(0x00F00000,0x00F00000UL, uint32_t )) /* Recovery time */ +#define BITM_FLCC_TIME_PARAM0_TNVH (_ADI_MSK_3(0x000F0000,0x000F0000UL, uint32_t )) /* NVSTR Hold time */ +#define BITM_FLCC_TIME_PARAM0_TPROG (_ADI_MSK_3(0x0000F000,0x0000F000UL, uint32_t )) /* Program time */ +#define BITM_FLCC_TIME_PARAM0_TPGS (_ADI_MSK_3(0x00000F00,0x00000F00UL, uint32_t )) /* NVSTR to Program setup time */ +#define BITM_FLCC_TIME_PARAM0_TNVS (_ADI_MSK_3(0x000000F0,0x000000F0UL, uint32_t )) /* PROG/ERASE to NVSTR setup time */ +#define BITM_FLCC_TIME_PARAM0_DIVREFCLK (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Divide Reference Clock (by 2) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_TIME_PARAM1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_TIME_PARAM1_CURWAITSTATES 8 /* Current wait states [2:0] */ +#define BITP_FLCC_TIME_PARAM1_WAITSTATES 4 /* Number of wait states to access flash */ +#define BITP_FLCC_TIME_PARAM1_TWK 0 /* Wake up time */ +#define BITM_FLCC_TIME_PARAM1_CURWAITSTATES (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t )) /* Current wait states [2:0] */ +#define BITM_FLCC_TIME_PARAM1_WAITSTATES (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t )) /* Number of wait states to access flash */ +#define BITM_FLCC_TIME_PARAM1_TWK (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Wake up time */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ABORT_EN_LO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ABORT_EN_LO_VALUE 0 /* Sys IRQ Abort Enable */ +#define BITM_FLCC_ABORT_EN_LO_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Sys IRQ Abort Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ABORT_EN_HI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ABORT_EN_HI_VALUE 0 /* Sys IRQ Abort Enable */ +#define BITM_FLCC_ABORT_EN_HI_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Sys IRQ Abort Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ECC_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ECC_CFG_PTR 8 /* ECC start page pointer */ +#define BITP_FLCC_ECC_CFG_INFOEN 1 /* Info space ECC Enable bit */ +#define BITP_FLCC_ECC_CFG_EN 0 /* ECC Enable */ +#define BITM_FLCC_ECC_CFG_PTR (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t )) /* ECC start page pointer */ +#define BITM_FLCC_ECC_CFG_INFOEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Info space ECC Enable bit */ +#define BITM_FLCC_ECC_CFG_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* ECC Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_ECC_ADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_ECC_ADDR_VALUE 0 /* This register has the address for which ECC error is detected */ +#define BITM_FLCC_ECC_ADDR_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* This register has the address for which ECC error is detected */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_POR_SEC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_POR_SEC_SECURE 0 /* Set this bit to prevent read or write access to User Space (sticky when set) */ +#define BITM_FLCC_POR_SEC_SECURE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Set this bit to prevent read or write access to User Space (sticky when set) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_VOL_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_VOL_CFG_INFO_REMAP 0 /* Alias the info space to the base address of user space */ +#define BITM_FLCC_VOL_CFG_INFO_REMAP (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Alias the info space to the base address of user space */ + + +/* ============================================================================================================================ + Cache Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + FLCC0_CACHE + ============================================================================================================================ */ +#define REG_FLCC0_CACHE_STAT 0x40018058 /* FLCC0_CACHE Cache Status Register */ +#define REG_FLCC0_CACHE_SETUP 0x4001805C /* FLCC0_CACHE Cache Setup Register */ +#define REG_FLCC0_CACHE_KEY 0x40018060 /* FLCC0_CACHE Cache Key Register */ + +/* ============================================================================================================================ + FLCC_CACHE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_STAT_ICEN 0 /* If this bit is set, I-Cache is enabled */ +#define BITM_FLCC_CACHE_STAT_ICEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* If this bit is set, I-Cache is enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_SETUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_SETUP_LCKIC 1 /* If this bit is set, I-Cache contents are locked */ +#define BITP_FLCC_CACHE_SETUP_ICEN 0 /* If this bit set, I-Cache is enabled for AHB accesses */ +#define BITM_FLCC_CACHE_SETUP_LCKIC (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* If this bit is set, I-Cache contents are locked */ +#define BITM_FLCC_CACHE_SETUP_ICEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* If this bit set, I-Cache is enabled for AHB accesses */ + +/* ------------------------------------------------------------------------------------------------------------------------- + FLCC_CACHE_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_FLCC_CACHE_KEY_VALUE 0 /* Cache Key */ +#define BITM_FLCC_CACHE_KEY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Cache Key */ + + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + GPIO0 + ============================================================================================================================ */ +#define REG_GPIO0_CFG 0x40020000 /* GPIO0 Port Configuration */ +#define REG_GPIO0_OEN 0x40020004 /* GPIO0 Port Output Enable */ +#define REG_GPIO0_PE 0x40020008 /* GPIO0 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO0_IEN 0x4002000C /* GPIO0 Port Input Path Enable */ +#define REG_GPIO0_IN 0x40020010 /* GPIO0 Port Registered Data Input */ +#define REG_GPIO0_OUT 0x40020014 /* GPIO0 Port Data Output */ +#define REG_GPIO0_SET 0x40020018 /* GPIO0 Port Data Out Set */ +#define REG_GPIO0_CLR 0x4002001C /* GPIO0 Port Data Out Clear */ +#define REG_GPIO0_TGL 0x40020020 /* GPIO0 Port Pin Toggle */ +#define REG_GPIO0_POL 0x40020024 /* GPIO0 Port Interrupt Polarity */ +#define REG_GPIO0_IENA 0x40020028 /* GPIO0 Port Interrupt A Enable */ +#define REG_GPIO0_IENB 0x4002002C /* GPIO0 Port Interrupt B Enable */ +#define REG_GPIO0_INT 0x40020030 /* GPIO0 Port Interrupt Status */ +#define REG_GPIO0_DS 0x40020034 /* GPIO0 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO1 + ============================================================================================================================ */ +#define REG_GPIO1_CFG 0x40020040 /* GPIO1 Port Configuration */ +#define REG_GPIO1_OEN 0x40020044 /* GPIO1 Port Output Enable */ +#define REG_GPIO1_PE 0x40020048 /* GPIO1 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO1_IEN 0x4002004C /* GPIO1 Port Input Path Enable */ +#define REG_GPIO1_IN 0x40020050 /* GPIO1 Port Registered Data Input */ +#define REG_GPIO1_OUT 0x40020054 /* GPIO1 Port Data Output */ +#define REG_GPIO1_SET 0x40020058 /* GPIO1 Port Data Out Set */ +#define REG_GPIO1_CLR 0x4002005C /* GPIO1 Port Data Out Clear */ +#define REG_GPIO1_TGL 0x40020060 /* GPIO1 Port Pin Toggle */ +#define REG_GPIO1_POL 0x40020064 /* GPIO1 Port Interrupt Polarity */ +#define REG_GPIO1_IENA 0x40020068 /* GPIO1 Port Interrupt A Enable */ +#define REG_GPIO1_IENB 0x4002006C /* GPIO1 Port Interrupt B Enable */ +#define REG_GPIO1_INT 0x40020070 /* GPIO1 Port Interrupt Status */ +#define REG_GPIO1_DS 0x40020074 /* GPIO1 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO2 + ============================================================================================================================ */ +#define REG_GPIO2_CFG 0x40020080 /* GPIO2 Port Configuration */ +#define REG_GPIO2_OEN 0x40020084 /* GPIO2 Port Output Enable */ +#define REG_GPIO2_PE 0x40020088 /* GPIO2 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO2_IEN 0x4002008C /* GPIO2 Port Input Path Enable */ +#define REG_GPIO2_IN 0x40020090 /* GPIO2 Port Registered Data Input */ +#define REG_GPIO2_OUT 0x40020094 /* GPIO2 Port Data Output */ +#define REG_GPIO2_SET 0x40020098 /* GPIO2 Port Data Out Set */ +#define REG_GPIO2_CLR 0x4002009C /* GPIO2 Port Data Out Clear */ +#define REG_GPIO2_TGL 0x400200A0 /* GPIO2 Port Pin Toggle */ +#define REG_GPIO2_POL 0x400200A4 /* GPIO2 Port Interrupt Polarity */ +#define REG_GPIO2_IENA 0x400200A8 /* GPIO2 Port Interrupt A Enable */ +#define REG_GPIO2_IENB 0x400200AC /* GPIO2 Port Interrupt B Enable */ +#define REG_GPIO2_INT 0x400200B0 /* GPIO2 Port Interrupt Status */ +#define REG_GPIO2_DS 0x400200B4 /* GPIO2 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO3 + ============================================================================================================================ */ +#define REG_GPIO3_CFG 0x400200C0 /* GPIO3 Port Configuration */ +#define REG_GPIO3_OEN 0x400200C4 /* GPIO3 Port Output Enable */ +#define REG_GPIO3_PE 0x400200C8 /* GPIO3 Port Output Pull-up/Pull-down Enable */ +#define REG_GPIO3_IEN 0x400200CC /* GPIO3 Port Input Path Enable */ +#define REG_GPIO3_IN 0x400200D0 /* GPIO3 Port Registered Data Input */ +#define REG_GPIO3_OUT 0x400200D4 /* GPIO3 Port Data Output */ +#define REG_GPIO3_SET 0x400200D8 /* GPIO3 Port Data Out Set */ +#define REG_GPIO3_CLR 0x400200DC /* GPIO3 Port Data Out Clear */ +#define REG_GPIO3_TGL 0x400200E0 /* GPIO3 Port Pin Toggle */ +#define REG_GPIO3_POL 0x400200E4 /* GPIO3 Port Interrupt Polarity */ +#define REG_GPIO3_IENA 0x400200E8 /* GPIO3 Port Interrupt A Enable */ +#define REG_GPIO3_IENB 0x400200EC /* GPIO3 Port Interrupt B Enable */ +#define REG_GPIO3_INT 0x400200F0 /* GPIO3 Port Interrupt Status */ +#define REG_GPIO3_DS 0x400200F4 /* GPIO3 Port Drive Strength Select */ + +/* ============================================================================================================================ + GPIO Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_CFG_PIN15 30 /* Pin 15 configuration bits */ +#define BITP_GPIO_CFG_PIN14 28 /* Pin 14 configuration bits */ +#define BITP_GPIO_CFG_PIN13 26 /* Pin 13 configuration bits */ +#define BITP_GPIO_CFG_PIN12 24 /* Pin 12 configuration bits */ +#define BITP_GPIO_CFG_PIN11 22 /* Pin 11 configuration bits */ +#define BITP_GPIO_CFG_PIN10 20 /* Pin 10 configuration bits */ +#define BITP_GPIO_CFG_PIN09 18 /* Pin 9 configuration bits */ +#define BITP_GPIO_CFG_PIN08 16 /* Pin 8 configuration bits */ +#define BITP_GPIO_CFG_PIN07 14 /* Pin 7 configuration bits */ +#define BITP_GPIO_CFG_PIN06 12 /* Pin 6 configuration bits */ +#define BITP_GPIO_CFG_PIN05 10 /* Pin 5 configuration bits */ +#define BITP_GPIO_CFG_PIN04 8 /* Pin 4 configuration bits */ +#define BITP_GPIO_CFG_PIN03 6 /* Pin 3 configuration bits */ +#define BITP_GPIO_CFG_PIN02 4 /* Pin 2 configuration bits */ +#define BITP_GPIO_CFG_PIN01 2 /* Pin 1 configuration bits */ +#define BITP_GPIO_CFG_PIN00 0 /* Pin 0 configuration bits */ +#define BITM_GPIO_CFG_PIN15 (_ADI_MSK_3(0xC0000000,0xC0000000UL, uint32_t )) /* Pin 15 configuration bits */ +#define BITM_GPIO_CFG_PIN14 (_ADI_MSK_3(0x30000000,0x30000000UL, uint32_t )) /* Pin 14 configuration bits */ +#define BITM_GPIO_CFG_PIN13 (_ADI_MSK_3(0x0C000000,0x0C000000UL, uint32_t )) /* Pin 13 configuration bits */ +#define BITM_GPIO_CFG_PIN12 (_ADI_MSK_3(0x03000000,0x03000000UL, uint32_t )) /* Pin 12 configuration bits */ +#define BITM_GPIO_CFG_PIN11 (_ADI_MSK_3(0x00C00000,0x00C00000UL, uint32_t )) /* Pin 11 configuration bits */ +#define BITM_GPIO_CFG_PIN10 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* Pin 10 configuration bits */ +#define BITM_GPIO_CFG_PIN09 (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Pin 9 configuration bits */ +#define BITM_GPIO_CFG_PIN08 (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* Pin 8 configuration bits */ +#define BITM_GPIO_CFG_PIN07 (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t )) /* Pin 7 configuration bits */ +#define BITM_GPIO_CFG_PIN06 (_ADI_MSK_3(0x00003000,0x00003000UL, uint32_t )) /* Pin 6 configuration bits */ +#define BITM_GPIO_CFG_PIN05 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* Pin 5 configuration bits */ +#define BITM_GPIO_CFG_PIN04 (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Pin 4 configuration bits */ +#define BITM_GPIO_CFG_PIN03 (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* Pin 3 configuration bits */ +#define BITM_GPIO_CFG_PIN02 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Pin 2 configuration bits */ +#define BITM_GPIO_CFG_PIN01 (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* Pin 1 configuration bits */ +#define BITM_GPIO_CFG_PIN00 (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Pin 0 configuration bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_OEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_OEN_VALUE 0 /* Pin Output Drive enable */ +#define BITM_GPIO_OEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Pin Output Drive enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_PE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_PE_VALUE 0 /* Pin Pull enable */ +#define BITM_GPIO_PE_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Pin Pull enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IEN_VALUE 0 /* Input path enable */ +#define BITM_GPIO_IEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Input path enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IN_VALUE 0 /* Registered data input */ +#define BITM_GPIO_IN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Registered data input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_OUT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_OUT_VALUE 0 /* Data out */ +#define BITM_GPIO_OUT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Data out */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_SET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_SET_VALUE 0 /* Set the output HIGH for the pin */ +#define BITM_GPIO_SET_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Set the output HIGH for the pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_CLR_VALUE 0 /* Set the output low for the port pin */ +#define BITM_GPIO_CLR_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Set the output low for the port pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_TGL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_TGL_VALUE 0 /* Toggle the output of the port pin */ +#define BITM_GPIO_TGL_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Toggle the output of the port pin */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_POL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_POL_VALUE 0 /* Interrupt polarity */ +#define BITM_GPIO_POL_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt polarity */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IENA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IENA_VALUE 0 /* Interrupt A enable */ +#define BITM_GPIO_IENA_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt A enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_IENB Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_IENB_VALUE 0 /* Interrupt B enable */ +#define BITM_GPIO_IENB_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt B enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_INT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_INT_VALUE 0 /* Interrupt Status */ +#define BITM_GPIO_INT_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Interrupt Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + GPIO_DS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_GPIO_DS_VALUE 0 /* Drive strength select */ +#define BITM_GPIO_DS_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Drive strength select */ + + +/* ============================================================================================================================ + Serial Port + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPORT0 + ============================================================================================================================ */ +#define REG_SPORT0_CTL_A 0x40038000 /* SPORT0 Half SPORT 'A' Control Register */ +#define REG_SPORT0_DIV_A 0x40038004 /* SPORT0 Half SPORT 'A' Divisor Register */ +#define REG_SPORT0_IEN_A 0x40038008 /* SPORT0 Half SPORT A's Interrupt Enable register */ +#define REG_SPORT0_STAT_A 0x4003800C /* SPORT0 Half SPORT 'A' Status register */ +#define REG_SPORT0_NUMTRAN_A 0x40038010 /* SPORT0 Half SPORT A Number of transfers register */ +#define REG_SPORT0_CNVT_A 0x40038014 /* SPORT0 Half SPORT 'A' CNV width */ +#define REG_SPORT0_TX_A 0x40038020 /* SPORT0 Half SPORT 'A' Tx Buffer Register */ +#define REG_SPORT0_RX_A 0x40038028 /* SPORT0 Half SPORT 'A' Rx Buffer Register */ +#define REG_SPORT0_CTL_B 0x40038040 /* SPORT0 Half SPORT 'B' Control Register */ +#define REG_SPORT0_DIV_B 0x40038044 /* SPORT0 Half SPORT 'B' Divisor Register */ +#define REG_SPORT0_IEN_B 0x40038048 /* SPORT0 Half SPORT B's Interrupt Enable register */ +#define REG_SPORT0_STAT_B 0x4003804C /* SPORT0 Half SPORT 'B' Status register */ +#define REG_SPORT0_NUMTRAN_B 0x40038050 /* SPORT0 Half SPORT B Number of transfers register */ +#define REG_SPORT0_CNVT_B 0x40038054 /* SPORT0 Half SPORT 'B' CNV width register */ +#define REG_SPORT0_TX_B 0x40038060 /* SPORT0 Half SPORT 'B' Tx Buffer Register */ +#define REG_SPORT0_RX_B 0x40038068 /* SPORT0 Half SPORT 'B' Rx Buffer Register */ + +/* ============================================================================================================================ + SPORT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CTL_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CTL_A_DMAEN 26 /* DMA Enable */ +#define BITP_SPORT_CTL_A_SPTRAN 25 /* Serial Port Transfer Direction */ +#define BITP_SPORT_CTL_A_GCLKEN 21 /* Gated Clock Enable */ +#define BITP_SPORT_CTL_A_FSERRMODE 20 /* Frame Sync Error Operation */ +#define BITP_SPORT_CTL_A_PACK 18 /* Packing Enable */ +#define BITP_SPORT_CTL_A_LAFS 17 /* Late Frame Sync */ +#define BITP_SPORT_CTL_A_LFS 16 /* Active-Low Frame Sync */ +#define BITP_SPORT_CTL_A_DIFS 15 /* Data-Independent Frame Sync */ +#define BITP_SPORT_CTL_A_IFS 14 /* Internal Frame Sync */ +#define BITP_SPORT_CTL_A_FSR 13 /* Frame Sync Required */ +#define BITP_SPORT_CTL_A_CKRE 12 /* Clock Rising Edge */ +#define BITP_SPORT_CTL_A_OPMODE 11 /* Operation mode */ +#define BITP_SPORT_CTL_A_ICLK 10 /* Internal Clock */ +#define BITP_SPORT_CTL_A_SLEN 4 /* Serial Word Length */ +#define BITP_SPORT_CTL_A_LSBF 3 /* Least-Significant Bit First */ +#define BITP_SPORT_CTL_A_CKMUXSEL 2 /* Clock Multiplexer Select */ +#define BITP_SPORT_CTL_A_FSMUXSEL 1 /* Frame Sync Multiplexer Select */ +#define BITP_SPORT_CTL_A_SPEN 0 /* Serial Port Enable */ +#define BITM_SPORT_CTL_A_DMAEN (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* DMA Enable */ +#define BITM_SPORT_CTL_A_SPTRAN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Serial Port Transfer Direction */ +#define BITM_SPORT_CTL_A_GCLKEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Gated Clock Enable */ +#define BITM_SPORT_CTL_A_FSERRMODE (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Frame Sync Error Operation */ +#define BITM_SPORT_CTL_A_PACK (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Packing Enable */ +#define BITM_SPORT_CTL_A_LAFS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Late Frame Sync */ +#define BITM_SPORT_CTL_A_LFS (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Active-Low Frame Sync */ +#define BITM_SPORT_CTL_A_DIFS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Data-Independent Frame Sync */ +#define BITM_SPORT_CTL_A_IFS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Internal Frame Sync */ +#define BITM_SPORT_CTL_A_FSR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Frame Sync Required */ +#define BITM_SPORT_CTL_A_CKRE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Clock Rising Edge */ +#define BITM_SPORT_CTL_A_OPMODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Operation mode */ +#define BITM_SPORT_CTL_A_ICLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Internal Clock */ +#define BITM_SPORT_CTL_A_SLEN (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t )) /* Serial Word Length */ +#define BITM_SPORT_CTL_A_LSBF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Least-Significant Bit First */ +#define BITM_SPORT_CTL_A_CKMUXSEL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Clock Multiplexer Select */ +#define BITM_SPORT_CTL_A_FSMUXSEL (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Frame Sync Multiplexer Select */ +#define BITM_SPORT_CTL_A_SPEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Serial Port Enable */ +#define ENUM_SPORT_CTL_A_CTL_RX (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* SPTRAN: Receive */ +#define ENUM_SPORT_CTL_A_CTL_TX (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* SPTRAN: Transmit */ +#define ENUM_SPORT_CTL_A_CTL_GCLK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* GCLKEN: Disable */ +#define ENUM_SPORT_CTL_A_CTL_GCLK_EN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* GCLKEN: Enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PACK: Disable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_8BIT (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* PACK: 8-bit packing enable */ +#define ENUM_SPORT_CTL_A_CTL_PACK_16BIT (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* PACK: 16-bit packing enable */ +#define ENUM_SPORT_CTL_A_CTL_EARLY_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LAFS: Early frame sync */ +#define ENUM_SPORT_CTL_A_CTL_LATE_FS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* LAFS: Late frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_LO (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LFS: Active high frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_HI (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* LFS: Active low frame sync */ +#define ENUM_SPORT_CTL_A_CTL_DATA_DEP_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DIFS: Data-dependent frame sync */ +#define ENUM_SPORT_CTL_A_CTL_DATA_INDP_FS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* DIFS: Data-independent frame sync */ +#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_FS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* IFS: External frame sync */ +#define ENUM_SPORT_CTL_A_CTL_INTERNAL_FS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* IFS: Internal frame sync */ +#define ENUM_SPORT_CTL_A_CTL_FS_NOT_REQ (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* FSR: No frame sync required */ +#define ENUM_SPORT_CTL_A_CTL_FS_REQ (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* FSR: Frame sync required */ +#define ENUM_SPORT_CTL_A_CTL_CLK_FALL_EDGE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CKRE: Clock falling edge */ +#define ENUM_SPORT_CTL_A_CTL_CLK_RISE_EDGE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* CKRE: Clock rising edge */ +#define ENUM_SPORT_CTL_A_CTL_SERIAL (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* OPMODE: DSP standard */ +#define ENUM_SPORT_CTL_A_CTL_TIMER_EN_MODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* OPMODE: Timer_enable mode */ +#define ENUM_SPORT_CTL_A_CTL_EXTERNAL_CLK (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* ICLK: External clock */ +#define ENUM_SPORT_CTL_A_CTL_INTERNAL_CLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* ICLK: Internal clock */ +#define ENUM_SPORT_CTL_A_CTL_MSB_FIRST (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LSBF: MSB first sent/received */ +#define ENUM_SPORT_CTL_A_CTL_LSB_FIRST (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* LSBF: LSB first sent/received */ +#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CKMUXSEL: Disable serial clock multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_CLK_MUX_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* CKMUXSEL: Enable serial clock multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_FS_MUX_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* FSMUXSEL: Disable frame sync multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_FS_MUX_EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* FSMUXSEL: Enable frame sync multiplexing */ +#define ENUM_SPORT_CTL_A_CTL_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* SPEN: Disable */ +#define ENUM_SPORT_CTL_A_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* SPEN: Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_DIV_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_DIV_A_FSDIV 16 /* Frame Sync Divisor */ +#define BITP_SPORT_DIV_A_CLKDIV 0 /* Clock Divisor */ +#define BITM_SPORT_DIV_A_FSDIV (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* Frame Sync Divisor */ +#define BITM_SPORT_DIV_A_CLKDIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Clock Divisor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_IEN_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_IEN_A_SYSDATERR 4 /* Data error for system writes or reads */ +#define BITP_SPORT_IEN_A_DATA 3 /* Data request interrupt to the core */ +#define BITP_SPORT_IEN_A_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_A_DERRMSK 1 /* Data Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_A_TF 0 /* Transfer Finish Interrupt Enable */ +#define BITM_SPORT_IEN_A_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Data error for system writes or reads */ +#define BITM_SPORT_IEN_A_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data request interrupt to the core */ +#define BITM_SPORT_IEN_A_FSERRMSK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_A_DERRMSK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_A_TF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transfer Finish Interrupt Enable */ +#define ENUM_SPORT_IEN_A_CTL_TXFIN_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TF: Transfer finish Interrupt is disabled */ +#define ENUM_SPORT_IEN_A_CTL_TXFIN_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TF: Transfer Finish Interrupt is Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_STAT_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_STAT_A_DXS 8 /* Data Transfer Buffer Status */ +#define BITP_SPORT_STAT_A_SYSDATERR 4 /* System Data Error Status */ +#define BITP_SPORT_STAT_A_DATA 3 /* Data Buffer status */ +#define BITP_SPORT_STAT_A_FSERR 2 /* Frame Sync Error Status */ +#define BITP_SPORT_STAT_A_DERR 1 /* Data Error Status */ +#define BITP_SPORT_STAT_A_TFI 0 /* Transmit Finish Interrupt Status */ +#define BITM_SPORT_STAT_A_DXS (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Data Transfer Buffer Status */ +#define BITM_SPORT_STAT_A_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* System Data Error Status */ +#define BITM_SPORT_STAT_A_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Buffer status */ +#define BITM_SPORT_STAT_A_FSERR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error Status */ +#define BITM_SPORT_STAT_A_DERR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error Status */ +#define BITM_SPORT_STAT_A_TFI (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Status */ +#define ENUM_SPORT_STAT_A_CTL_EMPTY (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DXS: Empty */ +#define ENUM_SPORT_STAT_A_CTL_PART_FULL (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* DXS: Partially full */ +#define ENUM_SPORT_STAT_A_CTL_FULL (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* DXS: Full */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_NUMTRAN_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_NUMTRAN_A_VALUE 0 /* Number of transfers (Half SPORT A) */ +#define BITM_SPORT_NUMTRAN_A_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* Number of transfers (Half SPORT A) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CNVT_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CNVT_A_CNVT2FS 16 /* CNV to FS duration: Half SPORT A */ +#define BITP_SPORT_CNVT_A_POL 8 /* Polarity of the CNV signal */ +#define BITP_SPORT_CNVT_A_WID 0 /* CNV signal width: Half SPORT A */ +#define BITM_SPORT_CNVT_A_CNVT2FS (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* CNV to FS duration: Half SPORT A */ +#define BITM_SPORT_CNVT_A_POL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Polarity of the CNV signal */ +#define BITM_SPORT_CNVT_A_WID (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* CNV signal width: Half SPORT A */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_TX_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_TX_A_VALUE 0 /* Transmit Buffer */ +#define BITM_SPORT_TX_A_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_RX_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_RX_A_VALUE 0 /* Receive Buffer */ +#define BITM_SPORT_RX_A_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Receive Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CTL_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CTL_B_DMAEN 26 /* DMA Enable */ +#define BITP_SPORT_CTL_B_SPTRAN 25 /* Serial Port Transfer Direction */ +#define BITP_SPORT_CTL_B_GCLKEN 21 /* Gated Clock Enable */ +#define BITP_SPORT_CTL_B_FSERRMODE 20 /* Frame Sync Error Operation */ +#define BITP_SPORT_CTL_B_PACK 18 /* Packing Enable */ +#define BITP_SPORT_CTL_B_LAFS 17 /* Late Frame Sync */ +#define BITP_SPORT_CTL_B_LFS 16 /* Active-Low Frame Sync */ +#define BITP_SPORT_CTL_B_DIFS 15 /* Data-Independent Frame Sync */ +#define BITP_SPORT_CTL_B_IFS 14 /* Internal Frame Sync */ +#define BITP_SPORT_CTL_B_FSR 13 /* Frame Sync Required */ +#define BITP_SPORT_CTL_B_CKRE 12 /* Clock Rising Edge */ +#define BITP_SPORT_CTL_B_OPMODE 11 /* Operation mode */ +#define BITP_SPORT_CTL_B_ICLK 10 /* Internal Clock */ +#define BITP_SPORT_CTL_B_SLEN 4 /* Serial Word Length */ +#define BITP_SPORT_CTL_B_LSBF 3 /* Least-Significant Bit First */ +#define BITP_SPORT_CTL_B_SPEN 0 /* Serial Port Enable */ +#define BITM_SPORT_CTL_B_DMAEN (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* DMA Enable */ +#define BITM_SPORT_CTL_B_SPTRAN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Serial Port Transfer Direction */ +#define BITM_SPORT_CTL_B_GCLKEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Gated Clock Enable */ +#define BITM_SPORT_CTL_B_FSERRMODE (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Frame Sync Error Operation */ +#define BITM_SPORT_CTL_B_PACK (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* Packing Enable */ +#define BITM_SPORT_CTL_B_LAFS (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Late Frame Sync */ +#define BITM_SPORT_CTL_B_LFS (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Active-Low Frame Sync */ +#define BITM_SPORT_CTL_B_DIFS (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Data-Independent Frame Sync */ +#define BITM_SPORT_CTL_B_IFS (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Internal Frame Sync */ +#define BITM_SPORT_CTL_B_FSR (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Frame Sync Required */ +#define BITM_SPORT_CTL_B_CKRE (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Clock Rising Edge */ +#define BITM_SPORT_CTL_B_OPMODE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Operation mode */ +#define BITM_SPORT_CTL_B_ICLK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Internal Clock */ +#define BITM_SPORT_CTL_B_SLEN (_ADI_MSK_3(0x000001F0,0x000001F0UL, uint32_t )) /* Serial Word Length */ +#define BITM_SPORT_CTL_B_LSBF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Least-Significant Bit First */ +#define BITM_SPORT_CTL_B_SPEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Serial Port Enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PACK: Disable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_8BIT (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* PACK: 8-bit packing enable */ +#define ENUM_SPORT_CTL_B_CTL_PACK_16BIT (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* PACK: 16-bit packing enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_DIV_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_DIV_B_FSDIV 16 /* Frame Sync Divisor */ +#define BITP_SPORT_DIV_B_CLKDIV 0 /* Clock Divisor */ +#define BITM_SPORT_DIV_B_FSDIV (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* Frame Sync Divisor */ +#define BITM_SPORT_DIV_B_CLKDIV (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Clock Divisor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_IEN_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_IEN_B_SYSDATERR 4 /* Data error for system writes or reads */ +#define BITP_SPORT_IEN_B_DATA 3 /* Data request interrupt to the core */ +#define BITP_SPORT_IEN_B_FSERRMSK 2 /* Frame Sync Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_B_DERRMSK 1 /* Data Error (Interrupt) Mask */ +#define BITP_SPORT_IEN_B_TF 0 /* Transmit Finish Interrupt Enable */ +#define BITM_SPORT_IEN_B_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Data error for system writes or reads */ +#define BITM_SPORT_IEN_B_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data request interrupt to the core */ +#define BITM_SPORT_IEN_B_FSERRMSK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_B_DERRMSK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error (Interrupt) Mask */ +#define BITM_SPORT_IEN_B_TF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Enable */ +#define ENUM_SPORT_IEN_B_CTL_TXFIN_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TF: Transfer Finish Interrupt is disabled */ +#define ENUM_SPORT_IEN_B_CTL_TXFIN_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TF: Transfer Finish Interrupt is Enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_STAT_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_STAT_B_DXS 8 /* Data Transfer Buffer Status */ +#define BITP_SPORT_STAT_B_SYSDATERR 4 /* System Data Error Status */ +#define BITP_SPORT_STAT_B_DATA 3 /* Data Buffer status */ +#define BITP_SPORT_STAT_B_FSERR 2 /* Frame Sync Error Status */ +#define BITP_SPORT_STAT_B_DERR 1 /* Data Error Status */ +#define BITP_SPORT_STAT_B_TFI 0 /* Transmit Finish Interrupt Status */ +#define BITM_SPORT_STAT_B_DXS (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Data Transfer Buffer Status */ +#define BITM_SPORT_STAT_B_SYSDATERR (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* System Data Error Status */ +#define BITM_SPORT_STAT_B_DATA (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Data Buffer status */ +#define BITM_SPORT_STAT_B_FSERR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Frame Sync Error Status */ +#define BITM_SPORT_STAT_B_DERR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Data Error Status */ +#define BITM_SPORT_STAT_B_TFI (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Transmit Finish Interrupt Status */ +#define ENUM_SPORT_STAT_B_CTL_EMPTY (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DXS: Empty */ +#define ENUM_SPORT_STAT_B_CTL_PART_FULL (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* DXS: Partially full */ +#define ENUM_SPORT_STAT_B_CTL_FULL (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* DXS: Full */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_NUMTRAN_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_NUMTRAN_B_VALUE 0 /* Number of transfers (Half SPORT A) */ +#define BITM_SPORT_NUMTRAN_B_VALUE (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* Number of transfers (Half SPORT A) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_CNVT_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_CNVT_B_CNVT2FS 16 /* CNV to FS duration: Half SPORT B */ +#define BITP_SPORT_CNVT_B_POL 8 /* Polarity of the CNV signal */ +#define BITP_SPORT_CNVT_B_WID 0 /* CNV signal width: Half SPORT B */ +#define BITM_SPORT_CNVT_B_CNVT2FS (_ADI_MSK_3(0x00FF0000,0x00FF0000UL, uint32_t )) /* CNV to FS duration: Half SPORT B */ +#define BITM_SPORT_CNVT_B_POL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Polarity of the CNV signal */ +#define BITM_SPORT_CNVT_B_WID (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* CNV signal width: Half SPORT B */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_TX_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_TX_B_VALUE 0 /* Transmit Buffer */ +#define BITM_SPORT_TX_B_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Transmit Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPORT_RX_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPORT_RX_B_VALUE 0 /* Receive Buffer */ +#define BITM_SPORT_RX_B_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Receive Buffer */ + + +/* ============================================================================================================================ + CRC Accelerator + ============================================================================================================================ */ + +/* ============================================================================================================================ + CRC0 + ============================================================================================================================ */ +#define REG_CRC0_CTL 0x40040000 /* CRC0 CRC Control */ +#define REG_CRC0_IPDATA 0x40040004 /* CRC0 Input Data Word */ +#define REG_CRC0_RESULT 0x40040008 /* CRC0 CRC Result */ +#define REG_CRC0_POLY 0x4004000C /* CRC0 Programmable CRC Polynomial */ +#define REG_CRC0_IPBITS0 0x40040010 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS1 0x40040011 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS2 0x40040012 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS3 0x40040013 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS4 0x40040014 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS5 0x40040015 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS6 0x40040016 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITS7 0x40040017 /* CRC0 Input Data Bits */ +#define REG_CRC0_IPBITSn(i) (REG_CRC0_IPBITS0 + ((i) * 1)) +#define REG_CRC0_IPBITSn_COUNT 8 +#define REG_CRC0_IPBYTE 0x40040010 /* CRC0 Input Data Byte */ + +/* ============================================================================================================================ + CRC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_CTL_REVID 28 /* Revision ID */ +#define BITP_CRC_CTL_W16SWP 4 /* Word16 Swap */ +#define BITP_CRC_CTL_BYTMIRR 3 /* Byte Mirroring */ +#define BITP_CRC_CTL_BITMIRR 2 /* Bit Mirroring */ +#define BITP_CRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ +#define BITP_CRC_CTL_EN 0 /* CRC Peripheral Enable */ +#define BITM_CRC_CTL_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Revision ID */ +#define BITM_CRC_CTL_W16SWP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Word16 Swap */ +#define BITM_CRC_CTL_BYTMIRR (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Byte Mirroring */ +#define BITM_CRC_CTL_BITMIRR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bit Mirroring */ +#define BITM_CRC_CTL_LSBFIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSB First Calculation Order */ +#define BITM_CRC_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Peripheral Enable */ +#define ENUM_CRC_CTL_W16SP_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* W16SWP: Word16 Swap disabled */ +#define ENUM_CRC_CTL_W16SP_EN (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* W16SWP: Word16 Swap enabled */ +#define ENUM_CRC_CTL_BYTEMIR_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BYTMIRR: Byte Mirroring is disabled */ +#define ENUM_CRC_CTL_BYTEMIR_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BYTMIRR: Byte Mirroring is enabled */ +#define ENUM_CRC_CTL_BITMIRR_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BITMIRR: Bit Mirroring is disabled */ +#define ENUM_CRC_CTL_BITMIRR_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* BITMIRR: Bit Mirroring is enabled */ +#define ENUM_CRC_CTL_MSB_FIRST (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LSBFIRST: MSB First CRC calculation is done */ +#define ENUM_CRC_CTL_LSB_FIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSBFIRST: LSB First CRC calculation is done */ +#define ENUM_CRC_CTL_CRC_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* EN: CRC peripheral is disabled */ +#define ENUM_CRC_CTL_CRC_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* EN: CRC peripheral is enabled */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPDATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPDATA_VALUE 0 /* Data Input */ +#define BITM_CRC_IPDATA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Data Input */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_RESULT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_RESULT_VALUE 0 /* CRC Residue */ +#define BITM_CRC_RESULT_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Residue */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_POLY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ +#define BITM_CRC_POLY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Reduction Polynomial */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPBITS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPBITS_DATA_BITS 0 /* Input Data Bits */ +#define BITM_CRC_IPBITS_DATA_BITS (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Bits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRC_IPBYTE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte */ +#define BITM_CRC_IPBYTE_DATA_BYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Byte */ + + +/* ============================================================================================================================ + Random Number Generator + ============================================================================================================================ */ + +/* ============================================================================================================================ + RNG0 + ============================================================================================================================ */ +#define REG_RNG0_CTL 0x40040400 /* RNG0 RNG Control Register */ +#define REG_RNG0_LEN 0x40040404 /* RNG0 RNG Sample Length Register */ +#define REG_RNG0_STAT 0x40040408 /* RNG0 RNG Status Register */ +#define REG_RNG0_DATA 0x4004040C /* RNG0 RNG Data Register */ +#define REG_RNG0_OSCCNT 0x40040410 /* RNG0 Oscillator Count */ +#define REG_RNG0_OSCDIFF0 0x40040414 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF1 0x40040415 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF2 0x40040416 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFF3 0x40040417 /* RNG0 Oscillator Difference */ +#define REG_RNG0_OSCDIFFn(i) (REG_RNG0_OSCDIFF0 + ((i) * 1)) +#define REG_RNG0_OSCDIFFn_COUNT 4 + +/* ============================================================================================================================ + RNG Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_CTL_SINGLE 3 /* Generate a Single Number */ +#define BITP_RNG_CTL_EN 0 /* RNG Enable */ +#define BITM_RNG_CTL_SINGLE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Generate a Single Number */ +#define BITM_RNG_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* RNG Enable */ +#define ENUM_RNG_CTL_WORD (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* SINGLE: Buffer Word */ +#define ENUM_RNG_CTL_SINGLE (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* SINGLE: Single Byte */ +#define ENUM_RNG_CTL_DISABLE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* EN: Disable the RNG */ +#define ENUM_RNG_CTL_ENABLE (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* EN: Enable the RNG */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_LEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_LEN_PRESCALE 12 /* Prescaler for the Sample Counter */ +#define BITP_RNG_LEN_RELOAD 0 /* Reload Value for the Sample Counter */ +#define BITM_RNG_LEN_PRESCALE (_ADI_MSK_3(0x0000F000,0x0000F000U, uint16_t )) /* Prescaler for the Sample Counter */ +#define BITM_RNG_LEN_RELOAD (_ADI_MSK_3(0x00000FFF,0x00000FFFU, uint16_t )) /* Reload Value for the Sample Counter */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_STAT_STUCK 1 /* Sampled Data Stuck High or Low */ +#define BITP_RNG_STAT_RNRDY 0 /* Random Number Ready */ +#define BITM_RNG_STAT_STUCK (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Sampled Data Stuck High or Low */ +#define BITM_RNG_STAT_RNRDY (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Random Number Ready */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_DATA_BUFF 8 /* Buffer for RNG Data */ +#define BITP_RNG_DATA_VALUE 0 /* Value of the CRC Accumulator */ +#define BITM_RNG_DATA_BUFF (_ADI_MSK_3(0xFFFFFF00,0xFFFFFF00UL, uint32_t )) /* Buffer for RNG Data */ +#define BITM_RNG_DATA_VALUE (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* Value of the CRC Accumulator */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_OSCCNT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_OSCCNT_VALUE 0 /* Oscillator Count */ +#define BITM_RNG_OSCCNT_VALUE (_ADI_MSK_3(0x0FFFFFFF,0x0FFFFFFFUL, uint32_t )) /* Oscillator Count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + RNG_OSCDIFF[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_RNG_OSCDIFF_DELTA 0 /* Oscillator Count Difference */ +#define BITM_RNG_OSCDIFF_DELTA (_ADI_MSK_3(0x000000FF,0x000000FF, int8_t )) /* Oscillator Count Difference */ + + +/* ============================================================================================================================ + Register Map for the Crypto Block + ============================================================================================================================ */ + +/* ============================================================================================================================ + CRYPT0 + ============================================================================================================================ */ +#define REG_CRYPT0_CFG 0x40044000 /* CRYPT0 Configuration Register */ +#define REG_CRYPT0_DATALEN 0x40044004 /* CRYPT0 Payload Data Length */ +#define REG_CRYPT0_PREFIXLEN 0x40044008 /* CRYPT0 Authentication Data Length */ +#define REG_CRYPT0_INTEN 0x4004400C /* CRYPT0 Interrupt Enable Register */ +#define REG_CRYPT0_STAT 0x40044010 /* CRYPT0 Status Register */ +#define REG_CRYPT0_INBUF 0x40044014 /* CRYPT0 Input Buffer */ +#define REG_CRYPT0_OUTBUF 0x40044018 /* CRYPT0 Output Buffer */ +#define REG_CRYPT0_NONCE0 0x4004401C /* CRYPT0 Nonce Bits [31:0] */ +#define REG_CRYPT0_NONCE1 0x40044020 /* CRYPT0 Nonce Bits [63:32] */ +#define REG_CRYPT0_NONCE2 0x40044024 /* CRYPT0 Nonce Bits [95:64] */ +#define REG_CRYPT0_NONCE3 0x40044028 /* CRYPT0 Nonce Bits [127:96] */ +#define REG_CRYPT0_AESKEY0 0x4004402C /* CRYPT0 AES Key Bits [31:0] */ +#define REG_CRYPT0_AESKEY1 0x40044030 /* CRYPT0 AES Key Bits [63:32] */ +#define REG_CRYPT0_AESKEY2 0x40044034 /* CRYPT0 AES Key Bits [95:64] */ +#define REG_CRYPT0_AESKEY3 0x40044038 /* CRYPT0 AES Key Bits [127:96] */ +#define REG_CRYPT0_AESKEY4 0x4004403C /* CRYPT0 AES Key Bits [159:128] */ +#define REG_CRYPT0_AESKEY5 0x40044040 /* CRYPT0 AES Key Bits [191:160] */ +#define REG_CRYPT0_AESKEY6 0x40044044 /* CRYPT0 AES Key Bits [223:192] */ +#define REG_CRYPT0_AESKEY7 0x40044048 /* CRYPT0 AES Key Bits [255:224] */ +#define REG_CRYPT0_CNTRINIT 0x4004404C /* CRYPT0 Counter Initialization Vector */ +#define REG_CRYPT0_SHAH0 0x40044050 /* CRYPT0 SHA Bits [31:0] */ +#define REG_CRYPT0_SHAH1 0x40044054 /* CRYPT0 SHA Bits [63:32] */ +#define REG_CRYPT0_SHAH2 0x40044058 /* CRYPT0 SHA Bits [95:64] */ +#define REG_CRYPT0_SHAH3 0x4004405C /* CRYPT0 SHA Bits [127:96] */ +#define REG_CRYPT0_SHAH4 0x40044060 /* CRYPT0 SHA Bits [159:128] */ +#define REG_CRYPT0_SHAH5 0x40044064 /* CRYPT0 SHA Bits [191:160] */ +#define REG_CRYPT0_SHAH6 0x40044068 /* CRYPT0 SHA Bits [223:192] */ +#define REG_CRYPT0_SHAH7 0x4004406C /* CRYPT0 SHA Bits [255:224] */ +#define REG_CRYPT0_SHA_LAST_WORD 0x40044070 /* CRYPT0 SHA Last Word and Valid Bits Information */ +#define REG_CRYPT0_CCM_NUM_VALID_BYTES 0x40044074 /* CRYPT0 NUM_VALID_BYTES */ +#define REG_CRYPT0_PRKSTORCFG 0x40044078 /* CRYPT0 PRKSTOR Configuration */ +#define REG_CRYPT0_KUW0 0x40044080 /* CRYPT0 Key Wrap Unwrap Register 0 */ +#define REG_CRYPT0_KUW1 0x40044084 /* CRYPT0 Key Wrap Unwrap Register 1 */ +#define REG_CRYPT0_KUW2 0x40044088 /* CRYPT0 Key Wrap Unwrap Register 2 */ +#define REG_CRYPT0_KUW3 0x4004408C /* CRYPT0 Key Wrap Unwrap Register 3 */ +#define REG_CRYPT0_KUW4 0x40044090 /* CRYPT0 Key Wrap Unwrap Register 4 */ +#define REG_CRYPT0_KUW5 0x40044094 /* CRYPT0 Key Wrap Unwrap Register 5 */ +#define REG_CRYPT0_KUW6 0x40044098 /* CRYPT0 Key Wrap Unwrap Register 6 */ +#define REG_CRYPT0_KUW7 0x4004409C /* CRYPT0 Key Wrap Unwrap Register 7 */ +#define REG_CRYPT0_KUW8 0x400440A0 /* CRYPT0 Key Wrap Unwrap Register 8 */ +#define REG_CRYPT0_KUW9 0x400440A4 /* CRYPT0 Key Wrap Unwrap Register 9 */ +#define REG_CRYPT0_KUW10 0x400440A8 /* CRYPT0 Key Wrap Unwrap Register 10 */ +#define REG_CRYPT0_KUW11 0x400440AC /* CRYPT0 Key Wrap Unwrap Register 11 */ +#define REG_CRYPT0_KUW12 0x400440B0 /* CRYPT0 Key Wrap Unwrap Register 12 */ +#define REG_CRYPT0_KUW13 0x400440B4 /* CRYPT0 Key Wrap Unwrap Register 13 */ +#define REG_CRYPT0_KUW14 0x400440B8 /* CRYPT0 Key Wrap Unwrap Register 14 */ +#define REG_CRYPT0_KUW15 0x400440BC /* CRYPT0 Key Wrap Unwrap Register 15 */ +#define REG_CRYPT0_KUWVALSTR1 0x400440C0 /* CRYPT0 Key Wrap Unwrap Validation String [63:32] */ +#define REG_CRYPT0_KUWVALSTR2 0x400440C4 /* CRYPT0 Key Wrap Unwrap Validation String [31:0] */ + +/* ============================================================================================================================ + CRYPT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CFG_REVID 28 /* Rev ID for Crypto */ +#define BITP_CRYPT_CFG_SHAINIT 26 /* Restarts SHA Computation */ +#define BITP_CRYPT_CFG_SHA256EN 25 /* Enable SHA-256 Operation */ +#define BITP_CRYPT_CFG_HMACEN 21 /* HMAC Enable */ +#define BITP_CRYPT_CFG_CMACEN 20 /* Enable CMAC Mode Operation */ +#define BITP_CRYPT_CFG_CCMEN 19 /* Enable CCM/CCM* Mode Operation */ +#define BITP_CRYPT_CFG_CBCEN 18 /* Enable CBC Mode Operation */ +#define BITP_CRYPT_CFG_CTREN 17 /* Enable CTR Mode Operation */ +#define BITP_CRYPT_CFG_ECBEN 16 /* Enable ECB Mode Operation */ +#define BITP_CRYPT_CFG_PRKSTOREN 15 /* Enable PRKSTOR Commands */ +#define BITP_CRYPT_CFG_KEY_BYTESWAP 14 /* Use Key Unwrap Before HMAC */ +#define BITP_CRYPT_CFG_SHA_BYTESWAP 13 /* Enable Key Wrap */ +#define BITP_CRYPT_CFG_AES_BYTESWAP 12 /* Byteswap for AES Input */ +#define BITP_CRYPT_CFG_KUWKEYLEN 10 /* Key Length Key Wrap Unwrap */ +#define BITP_CRYPT_CFG_AESKEYLEN 8 /* Select Key Length for AES Cipher */ +#define BITP_CRYPT_CFG_OUTFLUSH 5 /* Output Buffer Flush */ +#define BITP_CRYPT_CFG_INFLUSH 4 /* Input Buffer Flush */ +#define BITP_CRYPT_CFG_OUTDMAEN 3 /* Enable DMA Channel Request for Output Buffer */ +#define BITP_CRYPT_CFG_INDMAEN 2 /* Enable DMA Channel Request for Input Buffer */ +#define BITP_CRYPT_CFG_ENCR 1 /* Encrypt or Decrypt */ +#define BITP_CRYPT_CFG_BLKEN 0 /* Enable Bit for Crypto Block */ +#define BITM_CRYPT_CFG_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Rev ID for Crypto */ +#define BITM_CRYPT_CFG_SHAINIT (_ADI_MSK_3(0x04000000,0x04000000UL, uint32_t )) /* Restarts SHA Computation */ +#define BITM_CRYPT_CFG_SHA256EN (_ADI_MSK_3(0x02000000,0x02000000UL, uint32_t )) /* Enable SHA-256 Operation */ +#define BITM_CRYPT_CFG_HMACEN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* HMAC Enable */ +#define BITM_CRYPT_CFG_CMACEN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Enable CMAC Mode Operation */ +#define BITM_CRYPT_CFG_CCMEN (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* Enable CCM/CCM* Mode Operation */ +#define BITM_CRYPT_CFG_CBCEN (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* Enable CBC Mode Operation */ +#define BITM_CRYPT_CFG_CTREN (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Enable CTR Mode Operation */ +#define BITM_CRYPT_CFG_ECBEN (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Enable ECB Mode Operation */ +#define BITM_CRYPT_CFG_PRKSTOREN (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Enable PRKSTOR Commands */ +#define BITM_CRYPT_CFG_KEY_BYTESWAP (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Use Key Unwrap Before HMAC */ +#define BITM_CRYPT_CFG_SHA_BYTESWAP (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Enable Key Wrap */ +#define BITM_CRYPT_CFG_AES_BYTESWAP (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Byteswap for AES Input */ +#define BITM_CRYPT_CFG_KUWKEYLEN (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* Key Length Key Wrap Unwrap */ +#define BITM_CRYPT_CFG_AESKEYLEN (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Select Key Length for AES Cipher */ +#define BITM_CRYPT_CFG_OUTFLUSH (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Output Buffer Flush */ +#define BITM_CRYPT_CFG_INFLUSH (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Input Buffer Flush */ +#define BITM_CRYPT_CFG_OUTDMAEN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Enable DMA Channel Request for Output Buffer */ +#define BITM_CRYPT_CFG_INDMAEN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable DMA Channel Request for Input Buffer */ +#define BITM_CRYPT_CFG_ENCR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Encrypt or Decrypt */ +#define BITM_CRYPT_CFG_BLKEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Bit for Crypto Block */ +#define ENUM_CRYPT_CFG_LEN128 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* KUWKeyLen: The key size of KUW key is 128 bits */ +#define ENUM_CRYPT_CFG_LEN256 (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* KUWKeyLen: The key size of KUW key is 256 bits */ +#define ENUM_CRYPT_CFG_LEN512 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* KUWKeyLen: The key size of KUW key is 512 bits */ +#define ENUM_CRYPT_CFG_AESKEYLEN128 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* AESKEYLEN: Uses 128-bit long key */ +#define ENUM_CRYPT_CFG_AESKEYLEN256 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* AESKEYLEN: Uses 256-bit long key */ +#define ENUM_CRYPT_CFG_DMA_DISABLE_OUTBUF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* OUTDMAEN: Disable DMA Requesting for Output Buffer */ +#define ENUM_CRYPT_CFG_DMA_ENABLE_OUTBUF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* OUTDMAEN: Enable DMA Requesting for Output Buffer */ +#define ENUM_CRYPT_CFG_DMA_DISABLE_INBUF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* INDMAEN: Disable DMA Requesting for Input Buffer */ +#define ENUM_CRYPT_CFG_DMA_ENABLE_INBUF (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* INDMAEN: Enable DMA Requesting for Input Buffer */ +#define ENUM_CRYPT_CFG_ENABLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BLKEN: Enable Crypto Block */ +#define ENUM_CRYPT_CFG_DISABLE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* BLKEN: Disable Crypto Block */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_DATALEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_DATALEN_VALUE 0 /* Length of Payload Data */ +#define BITM_CRYPT_DATALEN_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* Length of Payload Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_PREFIXLEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_PREFIXLEN_VALUE 0 /* Length of Associated Data */ +#define BITM_CRYPT_PREFIXLEN_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Length of Associated Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_INTEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_INTEN_PRKSTRCMDONEEN 8 /* PRKSTOR CMD DONE INTEN */ +#define BITP_CRYPT_INTEN_HMACMSGRDYEN 7 /* Status Bit for HMAC Message Input Ready */ +#define BITP_CRYPT_INTEN_HMACDONEEN 6 /* Interrupt Enable for HMAC Done */ +#define BITP_CRYPT_INTEN_SHADONEN 5 /* Enable SHA_Done Interrupt */ +#define BITP_CRYPT_INTEN_INOVREN 2 /* Enable Input Overflow Interrupt */ +#define BITP_CRYPT_INTEN_OUTRDYEN 1 /* Enables the Output Ready Interrupt */ +#define BITP_CRYPT_INTEN_INRDYEN 0 /* Enable Input Ready Interrupt */ +#define BITM_CRYPT_INTEN_PRKSTRCMDONEEN (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* PRKSTOR CMD DONE INTEN */ +#define BITM_CRYPT_INTEN_HMACMSGRDYEN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* Status Bit for HMAC Message Input Ready */ +#define BITM_CRYPT_INTEN_HMACDONEEN (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Interrupt Enable for HMAC Done */ +#define BITM_CRYPT_INTEN_SHADONEN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Enable SHA_Done Interrupt */ +#define BITM_CRYPT_INTEN_INOVREN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Input Overflow Interrupt */ +#define BITM_CRYPT_INTEN_OUTRDYEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enables the Output Ready Interrupt */ +#define BITM_CRYPT_INTEN_INRDYEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Input Ready Interrupt */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_STAT_PRKSTOR_BUSY 31 /* Indicates PrKSTOR is Busy */ +#define BITP_CRYPT_STAT_CMD_ISSUED 27 /* Last Command Issued to PrKStor; */ +#define BITP_CRYPT_STAT_PRKSTOR_RET_STATUS 25 /* ECC Errors in the PRKSTOR_RETRIEVE Command */ +#define BITP_CRYPT_STAT_PRKSTOR_CMD_FAIL 24 /* Indicates Last Command Issued Failed */ +#define BITP_CRYPT_STAT_PRKSTOR_CMD_DONE 23 /* Indicates Command Done for PrKStor */ +#define BITP_CRYPT_STAT_HMACMSGRDY 15 /* Status Bit Indicates HMAC is Message Ready */ +#define BITP_CRYPT_STAT_HMACDONE 14 /* Status Bit Indicates HMAC Done */ +#define BITP_CRYPT_STAT_HMACBUSY 13 /* Status Bit Indicates HMAC Busy */ +#define BITP_CRYPT_STAT_OUTWORDS 10 /* Number of Words in the Output Buffer */ +#define BITP_CRYPT_STAT_INWORDS 7 /* Number of Words in the Input Buffer */ +#define BITP_CRYPT_STAT_SHABUSY 6 /* SHA Busy. in Computation */ +#define BITP_CRYPT_STAT_SHADONE 5 /* SHA Computation Complete */ +#define BITP_CRYPT_STAT_INOVR 2 /* Overflow in the Input Buffer */ +#define BITP_CRYPT_STAT_OUTRDY 1 /* Output Data Ready */ +#define BITP_CRYPT_STAT_INRDY 0 /* Input Buffer Status */ +#define BITM_CRYPT_STAT_PRKSTOR_BUSY (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Indicates PrKSTOR is Busy */ +#define BITM_CRYPT_STAT_CMD_ISSUED (_ADI_MSK_3(0x78000000,0x78000000UL, uint32_t )) /* Last Command Issued to PrKStor; */ +#define BITM_CRYPT_STAT_PRKSTOR_RET_STATUS (_ADI_MSK_3(0x06000000,0x06000000UL, uint32_t )) /* ECC Errors in the PRKSTOR_RETRIEVE Command */ +#define BITM_CRYPT_STAT_PRKSTOR_CMD_FAIL (_ADI_MSK_3(0x01000000,0x01000000UL, uint32_t )) /* Indicates Last Command Issued Failed */ +#define BITM_CRYPT_STAT_PRKSTOR_CMD_DONE (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t )) /* Indicates Command Done for PrKStor */ +#define BITM_CRYPT_STAT_HMACMSGRDY (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Status Bit Indicates HMAC is Message Ready */ +#define BITM_CRYPT_STAT_HMACDONE (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Status Bit Indicates HMAC Done */ +#define BITM_CRYPT_STAT_HMACBUSY (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Status Bit Indicates HMAC Busy */ +#define BITM_CRYPT_STAT_OUTWORDS (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* Number of Words in the Output Buffer */ +#define BITM_CRYPT_STAT_INWORDS (_ADI_MSK_3(0x00000380,0x00000380UL, uint32_t )) /* Number of Words in the Input Buffer */ +#define BITM_CRYPT_STAT_SHABUSY (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* SHA Busy. in Computation */ +#define BITM_CRYPT_STAT_SHADONE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* SHA Computation Complete */ +#define BITM_CRYPT_STAT_INOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Overflow in the Input Buffer */ +#define BITM_CRYPT_STAT_OUTRDY (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Output Data Ready */ +#define BITM_CRYPT_STAT_INRDY (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Input Buffer Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_INBUF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_INBUF_VALUE 0 /* Input Buffer */ +#define BITM_CRYPT_INBUF_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Input Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_OUTBUF Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_OUTBUF_VALUE 0 /* Output Buffer */ +#define BITM_CRYPT_OUTBUF_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Output Buffer */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE0_VALUE 0 /* Word 0: Nonce Bits [31:0] */ +#define BITM_CRYPT_NONCE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 0: Nonce Bits [31:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE1_VALUE 0 /* Word 1: Nonce Bits [63:32] */ +#define BITM_CRYPT_NONCE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 1: Nonce Bits [63:32] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE2_VALUE 0 /* Word 2: Nonce Bits [95:64] */ +#define BITM_CRYPT_NONCE2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 2: Nonce Bits [95:64] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_NONCE3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_NONCE3_VALUE 0 /* Word 3: Nonce Bits [127:96] */ +#define BITM_CRYPT_NONCE3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 3: Nonce Bits [127:96] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY0_VALUE 0 /* Key: Bytes [3:0] */ +#define BITM_CRYPT_AESKEY0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [3:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY1_VALUE 0 /* Key: Bytes [7:4] */ +#define BITM_CRYPT_AESKEY1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [7:4] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY2_VALUE 0 /* Key: Bytes [11:8] */ +#define BITM_CRYPT_AESKEY2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [11:8] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY3_VALUE 0 /* Key: Bytes [15:12] */ +#define BITM_CRYPT_AESKEY3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [15:12] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY4_VALUE 0 /* Key: Bytes [19:16] */ +#define BITM_CRYPT_AESKEY4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [19:16] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY5_VALUE 0 /* Key: Bytes [23:20] */ +#define BITM_CRYPT_AESKEY5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [23:20] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY6_VALUE 0 /* Key: Bytes [27:24] */ +#define BITM_CRYPT_AESKEY6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [27:24] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_AESKEY7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_AESKEY7_VALUE 0 /* Key: Bytes [31:28] */ +#define BITM_CRYPT_AESKEY7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Key: Bytes [31:28] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CNTRINIT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CNTRINIT_VALUE 0 /* Counter Initialization Value */ +#define BITM_CRYPT_CNTRINIT_VALUE (_ADI_MSK_3(0x000FFFFF,0x000FFFFFUL, uint32_t )) /* Counter Initialization Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH0_SHAHASH0 0 /* Word 0: SHA Hash */ +#define BITM_CRYPT_SHAH0_SHAHASH0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 0: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH1_SHAHASH1 0 /* Word 1: SHA Hash */ +#define BITM_CRYPT_SHAH1_SHAHASH1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 1: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH2_SHAHASH2 0 /* Word 2: SHA Hash */ +#define BITM_CRYPT_SHAH2_SHAHASH2 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 2: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH3_SHAHASH3 0 /* Word 3: SHA Hash */ +#define BITM_CRYPT_SHAH3_SHAHASH3 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 3: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH4_SHAHASH4 0 /* Word 4: SHA Hash */ +#define BITM_CRYPT_SHAH4_SHAHASH4 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 4: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH5_SHAHASH5 0 /* Word 5: SHA Hash */ +#define BITM_CRYPT_SHAH5_SHAHASH5 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 5: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH6_SHAHASH6 0 /* Word 6: SHA Hash */ +#define BITM_CRYPT_SHAH6_SHAHASH6 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 6: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHAH7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHAH7_SHAHASH7 0 /* Word 7: SHA Hash */ +#define BITM_CRYPT_SHAH7_SHAHASH7 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Word 7: SHA Hash */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_SHA_LAST_WORD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_SHA_LAST_WORD_O_BITS_VALID 1 /* Bits Valid in SHA Last Word Input */ +#define BITP_CRYPT_SHA_LAST_WORD_O_LAST_WORD 0 /* Last SHA Input Word */ +#define BITM_CRYPT_SHA_LAST_WORD_O_BITS_VALID (_ADI_MSK_3(0x0000003E,0x0000003EUL, uint32_t )) /* Bits Valid in SHA Last Word Input */ +#define BITM_CRYPT_SHA_LAST_WORD_O_LAST_WORD (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Last SHA Input Word */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_CCM_NUM_VALID_BYTES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES 0 /* Number of Valid Bytes in CCM Last Data */ +#define BITM_CRYPT_CCM_NUM_VALID_BYTES_NUM_VALID_BYTES (_ADI_MSK_3(0x0000000F,0x0000000FUL, uint32_t )) /* Number of Valid Bytes in CCM Last Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_PRKSTORCFG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_PRKSTORCFG_CMD 7 /* Command Input for PRKSTOR */ +#define BITP_CRYPT_PRKSTORCFG_KEY_INDEX 0 /* Index of Key in PRKSTOR */ +#define BITM_CRYPT_PRKSTORCFG_CMD (_ADI_MSK_3(0x00000780,0x00000780UL, uint32_t )) /* Command Input for PRKSTOR */ +#define BITM_CRYPT_PRKSTORCFG_KEY_INDEX (_ADI_MSK_3(0x0000007F,0x0000007FUL, uint32_t )) /* Index of Key in PRKSTOR */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW0_KUW0 0 /* KUW [31:0] */ +#define BITM_CRYPT_KUW0_KUW0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [31:0] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW1_KUW1 0 /* KUW [63:32] */ +#define BITM_CRYPT_KUW1_KUW1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [63:32] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW2_KUW2 0 /* KUW [95:64] */ +#define BITM_CRYPT_KUW2_KUW2 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [95:64] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW3_KUW3 0 /* KUW [127:96] */ +#define BITM_CRYPT_KUW3_KUW3 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [127:96] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW4_KUW4 0 /* KUW [159:128] */ +#define BITM_CRYPT_KUW4_KUW4 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [159:128] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW5_KUW5 0 /* KUW [191:160] */ +#define BITM_CRYPT_KUW5_KUW5 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [191:160] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW6_KUW6 0 /* KUW [223:192] */ +#define BITM_CRYPT_KUW6_KUW6 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [223:192] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW7_KUW7 0 /* KUW [255:224] */ +#define BITM_CRYPT_KUW7_KUW7 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [255:224] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW8_KUW8 0 /* KUW [287:256] */ +#define BITM_CRYPT_KUW8_KUW8 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [287:256] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW9_KUW9 0 /* KUW [319:288] */ +#define BITM_CRYPT_KUW9_KUW9 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [319:288] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW10 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW10_KUW10 0 /* KUW [351:320] */ +#define BITM_CRYPT_KUW10_KUW10 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [351:320] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW11 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW11_KUW11 0 /* KUW [383:352] */ +#define BITM_CRYPT_KUW11_KUW11 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [383:352] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW12 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW12_KUW12 0 /* KUW [415:384] */ +#define BITM_CRYPT_KUW12_KUW12 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [415:384] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW13 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW13_KUW13 0 /* KUW [447:416] */ +#define BITM_CRYPT_KUW13_KUW13 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [447:416] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW14 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW14_KUW14 0 /* KUW [479:448] */ +#define BITM_CRYPT_KUW14_KUW14 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [479:448] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUW15 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUW15_KUW15 0 /* KUW [511:480] */ +#define BITM_CRYPT_KUW15_KUW15 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* KUW [511:480] */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUWVALSTR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUWVALSTR1_INITALVALUE0 0 /* Initial Value */ +#define BITM_CRYPT_KUWVALSTR1_INITALVALUE0 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Initial Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CRYPT_KUWVALSTR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CRYPT_KUWVALSTR2_INITIALVALUE1 0 /* Initial Value */ +#define BITM_CRYPT_KUWVALSTR2_INITIALVALUE1 (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Initial Value */ + + +/* ============================================================================================================================ + Power Management Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + PMG0 + ============================================================================================================================ */ +#define REG_PMG0_IEN 0x4004C000 /* PMG0 Power Supply Monitor Interrupt Enable */ +#define REG_PMG0_PSM_STAT 0x4004C004 /* PMG0 Power Supply Monitor Status */ +#define REG_PMG0_PWRMOD 0x4004C008 /* PMG0 Power Mode Register */ +#define REG_PMG0_PWRKEY 0x4004C00C /* PMG0 Key Protection for PWRMOD and SRAMRET */ +#define REG_PMG0_SHDN_STAT 0x4004C010 /* PMG0 Shutdown Status Register */ +#define REG_PMG0_SRAMRET 0x4004C014 /* PMG0 Control for Retention SRAM in Hibernate Mode */ +#define REG_PMG0_TRIM 0x4004C038 /* PMG0 Trimming Bits */ +#define REG_PMG0_RST_STAT 0x4004C040 /* PMG0 Reset Status */ +#define REG_PMG0_CTL1 0x4004C044 /* PMG0 HPBUCK Control */ + +/* ============================================================================================================================ + PMG Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_IEN Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_IEN_IENBAT 10 /* Interrupt enable for VBAT range */ +#define BITP_PMG_IEN_RANGEBAT 8 /* Battery Monitor Range */ +#define BITP_PMG_IEN_VREGOVR 2 /* Enable Interrupt when VREG over-voltage (above 1.32 V) */ +#define BITP_PMG_IEN_VREGUNDR 1 /* Enable Interrupt when VREG under-voltage (below 1 V) */ +#define BITP_PMG_IEN_VBAT 0 /* Enable Interrupt for VBAT */ +#define BITM_PMG_IEN_IENBAT (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Interrupt enable for VBAT range */ +#define BITM_PMG_IEN_RANGEBAT (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Battery Monitor Range */ +#define BITM_PMG_IEN_VREGOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable Interrupt when VREG over-voltage (above 1.32 V) */ +#define BITM_PMG_IEN_VREGUNDR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable Interrupt when VREG under-voltage (below 1 V) */ +#define BITM_PMG_IEN_VBAT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Interrupt for VBAT */ +#define ENUM_PMG_IEN_REGION1 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT in Region1 */ +#define ENUM_PMG_IEN_REGION2 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT in Region2 */ +#define ENUM_PMG_IEN_REGION3 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* RANGEBAT: Configure to generate interrupt if VBAT in Region3 */ +#define ENUM_PMG_IEN_NA (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* RANGEBAT: NA */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PSM_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PSM_STAT_RORANGE3 15 /* VBAT range3 */ +#define BITP_PMG_PSM_STAT_RORANGE2 14 /* VBAT range2 */ +#define BITP_PMG_PSM_STAT_RORANGE1 13 /* VBAT range1 */ +#define BITP_PMG_PSM_STAT_RANGE3 10 /* VBAT range3 */ +#define BITP_PMG_PSM_STAT_RANGE2 9 /* VBAT range2 */ +#define BITP_PMG_PSM_STAT_RANGE1 8 /* VBAT range1 */ +#define BITP_PMG_PSM_STAT_WICENACK 7 /* WIC Enable Acknowledge from Cortex */ +#define BITP_PMG_PSM_STAT_VREGOVR 2 /* Status bit for alarm indicating Over Voltage for VREG */ +#define BITP_PMG_PSM_STAT_VREGUNDR 1 /* Status bit for Alarm indicating VREG is below 1 V */ +#define BITP_PMG_PSM_STAT_VBATUNDR 0 /* Status bit indicating an Alarm that battery is below 1.8 V */ +#define BITM_PMG_PSM_STAT_RORANGE3 (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* VBAT range3 */ +#define BITM_PMG_PSM_STAT_RORANGE2 (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* VBAT range2 */ +#define BITM_PMG_PSM_STAT_RORANGE1 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* VBAT range1 */ +#define BITM_PMG_PSM_STAT_RANGE3 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* VBAT range3 */ +#define BITM_PMG_PSM_STAT_RANGE2 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* VBAT range2 */ +#define BITM_PMG_PSM_STAT_RANGE1 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* VBAT range1 */ +#define BITM_PMG_PSM_STAT_WICENACK (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* WIC Enable Acknowledge from Cortex */ +#define BITM_PMG_PSM_STAT_VREGOVR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Status bit for alarm indicating Over Voltage for VREG */ +#define BITM_PMG_PSM_STAT_VREGUNDR (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Status bit for Alarm indicating VREG is below 1 V */ +#define BITM_PMG_PSM_STAT_VBATUNDR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Status bit indicating an Alarm that battery is below 1.8 V */ +#define ENUM_PMG_PSM_STAT_BATSTAT1 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RORANGE1: VBAT NOT in the range specified */ +#define ENUM_PMG_PSM_STAT_BATSTAT0 (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* RORANGE1: VBAT in the range specified */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PWRMOD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PWRMOD_MONVBATN 3 /* Monitor VBAT during Hibernate Mode. Monitors VBAT by default */ +#define BITP_PMG_PWRMOD_MODE 0 /* Power Mode Bits */ +#define BITM_PMG_PWRMOD_MONVBATN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Monitor VBAT during Hibernate Mode. Monitors VBAT by default */ +#define BITM_PMG_PWRMOD_MODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Power Mode Bits */ +#define ENUM_PMG_PWRMOD_FLEXI (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* MODE: Flexi Mode */ +#define ENUM_PMG_PWRMOD_HIBERNATE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* MODE: Hibernate Mode */ +#define ENUM_PMG_PWRMOD_SHUTDOWN (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* MODE: Shutdown Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_PWRKEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_PWRKEY_VALUE 0 /* Power Control Key */ +#define BITM_PMG_PWRKEY_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Power Control Key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_SHDN_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_SHDN_STAT_RTC 3 /* Interrupt from RTC */ +#define BITP_PMG_SHDN_STAT_EXTINT2 2 /* Interrupt from External Interrupt 2 */ +#define BITP_PMG_SHDN_STAT_EXTINT1 1 /* Interrupt from External Interrupt 1 */ +#define BITP_PMG_SHDN_STAT_EXTINT0 0 /* Interrupt from External Interrupt 0 */ +#define BITM_PMG_SHDN_STAT_RTC (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Interrupt from RTC */ +#define BITM_PMG_SHDN_STAT_EXTINT2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Interrupt from External Interrupt 2 */ +#define BITM_PMG_SHDN_STAT_EXTINT1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Interrupt from External Interrupt 1 */ +#define BITM_PMG_SHDN_STAT_EXTINT0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Interrupt from External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_SRAMRET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_SRAMRET_HIBERNATE_SRAM_LOAD_MODE 23 /* Hibernate mode SRAM load mode control */ +#define BITP_PMG_SRAMRET_RET4 9 /* Enable retention bank 6 and bank 7 (32 KB) */ +#define BITP_PMG_SRAMRET_RET3 8 /* Enable retention bank 5 (32 KB) */ +#define BITP_PMG_SRAMRET_RET2 1 /* Enable retention bank 3 and bank 4 (32 KB) */ +#define BITP_PMG_SRAMRET_RET1 0 /* Enable retention bank 1 (12 KB) */ +#define BITM_PMG_SRAMRET_HIBERNATE_SRAM_LOAD_MODE (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t )) /* Hibernate mode SRAM load mode control */ +#define BITM_PMG_SRAMRET_RET4 (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Enable retention bank 6 and bank 7 (32 KB) */ +#define BITM_PMG_SRAMRET_RET3 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Enable retention bank 5 (32 KB) */ +#define BITM_PMG_SRAMRET_RET2 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable retention bank 3 and bank 4 (32 KB) */ +#define BITM_PMG_SRAMRET_RET1 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable retention bank 1 (12 KB) */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TRIM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TRIM_HIBERNATE_LOAD_MODE 29 /* Hibernate mode load mode control */ +#define BITM_PMG_TRIM_HIBERNATE_LOAD_MODE (_ADI_MSK_3(0xE0000000,0xE0000000UL, uint32_t )) /* Hibernate mode load mode control */ +#define ENUM_PMG_TRIM_HIGH_LOAD (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* hibernate_load_mode: High hibernate load */ +#define ENUM_PMG_TRIM_LOW_LOAD (_ADI_MSK_3(0xE0000000,0xE0000000UL, uint32_t )) /* hibernate_load_mode: Low hibernate load */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_RST_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_RST_STAT_PORSRC 4 /* Power on reset Source */ +#define BITP_PMG_RST_STAT_SWRST 3 /* Software reset */ +#define BITP_PMG_RST_STAT_WDRST 2 /* Watchdog timeout */ +#define BITP_PMG_RST_STAT_EXTRST 1 /* External reset */ +#define BITP_PMG_RST_STAT_POR 0 /* Power-on reset */ +#define BITM_PMG_RST_STAT_PORSRC (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Power on reset Source */ +#define BITM_PMG_RST_STAT_SWRST (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Software reset */ +#define BITM_PMG_RST_STAT_WDRST (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Watchdog timeout */ +#define BITM_PMG_RST_STAT_EXTRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* External reset */ +#define BITM_PMG_RST_STAT_POR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Power-on reset */ +#define ENUM_PMG_RST_STAT_FAILSAFE_HV (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PORSRC: POR triggered because VBAT drops below Fail Safe */ +#define ENUM_PMG_RST_STAT_RST_VBAT (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* PORSRC: POR trigger because VBAT supply (VBAT < 1.7 V) */ +#define ENUM_PMG_RST_STAT_RST_VREG (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* PORSRC: POR triggered because VDD supply (VDD < 1.08 V) */ +#define ENUM_PMG_RST_STAT_FAILSAFE_LV (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* PORSRC: POR triggered because VREG drops below Fail Safe */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_CTL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_CTL1_HPBUCK_LOWPWR_MODE 2 /* HP Buck low power mode */ +#define BITP_PMG_CTL1_HPBUCK_LD_MODE 1 /* HP Buck load mode */ +#define BITP_PMG_CTL1_HPBUCKEN 0 /* Enable HP Buck */ +#define BITM_PMG_CTL1_HPBUCK_LOWPWR_MODE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* HP Buck low power mode */ +#define BITM_PMG_CTL1_HPBUCK_LD_MODE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* HP Buck load mode */ +#define BITM_PMG_CTL1_HPBUCKEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable HP Buck */ +#define ENUM_PMG_CTL1_LOWPWRDISABLE (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* HPBUCK_LOWPWR_MODE: HPBUCK Low power mode is disabled */ +#define ENUM_PMG_CTL1_LOWPWRENABLE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* HPBUCK_LOWPWR_MODE: HPBUCK Low power mode is enabled */ +#define ENUM_PMG_CTL1_HPBUCKLOWLOAD (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* HPBUCK_LD_MODE: HPBUCK Low load mode is enabled */ +#define ENUM_PMG_CTL1_HPBUCKHIGHLOAD (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* HPBUCK_LD_MODE: HPBUCK High load mode is enabled */ + + +/* ============================================================================================================================ + External interrupt configuration + ============================================================================================================================ */ + +/* ============================================================================================================================ + XINT0 + ============================================================================================================================ */ +#define REG_XINT0_CFG0 0x4004C080 /* XINT0 External Interrupt configuration */ +#define REG_XINT0_EXT_STAT 0x4004C084 /* XINT0 External Wakeup Interrupt Status register */ +#define REG_XINT0_CLR 0x4004C090 /* XINT0 External Interrupt clear */ +#define REG_XINT0_NMICLR 0x4004C094 /* XINT0 Non-maskable interrupt clear */ + +/* ============================================================================================================================ + XINT Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_CFG0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_CFG0_UART_RX_MDE 21 /* External Interrupt using UART_RX wakeup Mode registers */ +#define BITP_XINT_CFG0_UART_RX_EN 20 /* External Interrupt using SIP_UPDATE enable bit */ +#define BITP_XINT_CFG0_IRQ3EN 15 /* External Interrupt 3 enable bit */ +#define BITP_XINT_CFG0_IRQ3MDE 12 /* External Interrupt 3 Mode registers */ +#define BITP_XINT_CFG0_IRQ2EN 11 /* External Interrupt 2 Enable bit */ +#define BITP_XINT_CFG0_IRQ2MDE 8 /* External Interrupt 2 Mode registers */ +#define BITP_XINT_CFG0_IRQ1EN 7 /* External Interrupt 1 Enable bit */ +#define BITP_XINT_CFG0_IRQ1MDE 4 /* External Interrupt 1 Mode registers */ +#define BITP_XINT_CFG0_IRQ0EN 3 /* External Interrupt 0 Enable bit */ +#define BITP_XINT_CFG0_IRQ0MDE 0 /* External Interrupt 0 Mode registers */ +#define BITM_XINT_CFG0_UART_RX_MDE (_ADI_MSK_3(0x00E00000,0x00E00000UL, uint32_t )) /* External Interrupt using UART_RX wakeup Mode registers */ +#define BITM_XINT_CFG0_UART_RX_EN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* External Interrupt using SIP_UPDATE enable bit */ +#define BITM_XINT_CFG0_IRQ3EN (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* External Interrupt 3 enable bit */ +#define BITM_XINT_CFG0_IRQ3MDE (_ADI_MSK_3(0x00007000,0x00007000UL, uint32_t )) /* External Interrupt 3 Mode registers */ +#define BITM_XINT_CFG0_IRQ2EN (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* External Interrupt 2 Enable bit */ +#define BITM_XINT_CFG0_IRQ2MDE (_ADI_MSK_3(0x00000700,0x00000700UL, uint32_t )) /* External Interrupt 2 Mode registers */ +#define BITM_XINT_CFG0_IRQ1EN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* External Interrupt 1 Enable bit */ +#define BITM_XINT_CFG0_IRQ1MDE (_ADI_MSK_3(0x00000070,0x00000070UL, uint32_t )) /* External Interrupt 1 Mode registers */ +#define BITM_XINT_CFG0_IRQ0EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* External Interrupt 0 Enable bit */ +#define BITM_XINT_CFG0_IRQ0MDE (_ADI_MSK_3(0x00000007,0x00000007UL, uint32_t )) /* External Interrupt 0 Mode registers */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_EXT_STAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_EXT_STAT_STAT_UART_RXWKUP 5 /* Interrupt status bit for UART RX WAKEUP interrupt */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT3 3 /* Interrupt status bit for External Interrupt 3 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT2 2 /* Interrupt status bit for External Interrupt 2 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT1 1 /* Interrupt status bit for External Interrupt 1 */ +#define BITP_XINT_EXT_STAT_STAT_EXTINT0 0 /* Interrupt status bit for External Interrupt 0 */ +#define BITM_XINT_EXT_STAT_STAT_UART_RXWKUP (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Interrupt status bit for UART RX WAKEUP interrupt */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Interrupt status bit for External Interrupt 3 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Interrupt status bit for External Interrupt 2 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Interrupt status bit for External Interrupt 1 */ +#define BITM_XINT_EXT_STAT_STAT_EXTINT0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Interrupt status bit for External Interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_CLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_CLR_UART_RX_CLR 5 /* External interrupt Clear for UART_RX WAKEUP interrupt */ +#define BITP_XINT_CLR_IRQ3 3 /* External interrupt 3 */ +#define BITP_XINT_CLR_IRQ2 2 /* External interrupt 2 */ +#define BITP_XINT_CLR_IRQ1 1 /* External interrupt 1 */ +#define BITP_XINT_CLR_IRQ0 0 /* External interrupt 0 */ +#define BITM_XINT_CLR_UART_RX_CLR (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* External interrupt Clear for UART_RX WAKEUP interrupt */ +#define BITM_XINT_CLR_IRQ3 (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* External interrupt 3 */ +#define BITM_XINT_CLR_IRQ2 (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* External interrupt 2 */ +#define BITM_XINT_CLR_IRQ1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* External interrupt 1 */ +#define BITM_XINT_CLR_IRQ0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* External interrupt 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + XINT_NMICLR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_XINT_NMICLR_CLR 0 /* NMI clear */ +#define BITM_XINT_NMICLR_CLR (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* NMI clear */ + + +/* ============================================================================================================================ + Clocking registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CLKG0_OSC + ============================================================================================================================ */ +#define REG_CLKG0_OSC_KEY 0x4004C10C /* CLKG0_OSC Key Protection for OSCCTRL */ +#define REG_CLKG0_OSC_CTL 0x4004C110 /* CLKG0_OSC Oscillator Control */ + +/* ============================================================================================================================ + CLKG_OSC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_OSC_KEY Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_OSC_KEY_VALUE 0 /* Oscillator key */ +#define BITM_CLKG_OSC_KEY_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFUL, uint32_t )) /* Oscillator key */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_OSC_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_OSC_CTL_LFX_FAIL_STA 31 /* LF XTAL (crystal clock) Not Stable */ +#define BITP_CLKG_OSC_CTL_ROOT_FAIL_STA 30 /* Root clock (crystal clock) Not Stable */ +#define BITP_CLKG_OSC_CTL_ROOT_AUTSW_STA 22 /* Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */ +#define BITP_CLKG_OSC_CTL_ROOT_AUTSW_EN 21 /* Enables automatic Switching of the Root clock to HFOSC on Root clock Failure */ +#define BITP_CLKG_OSC_CTL_ROOT_MON_EN 20 /* ROOT clock monitor and Clock FAIL interrupt enable */ +#define BITP_CLKG_OSC_CTL_LFX_ROBUST_LD 15 /* LFXTAL Robust Mode Load select */ +#define BITP_CLKG_OSC_CTL_LFX_ROBUST_EN 14 /* LFXTAL Mode select */ +#define BITP_CLKG_OSC_CTL_LFX_AUTSW_STA 13 /* Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */ +#define BITP_CLKG_OSC_CTL_LFX_AUTSW_EN 12 /* Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */ +#define BITP_CLKG_OSC_CTL_HFX_OK 11 /* Status of HFXTAL oscillator */ +#define BITP_CLKG_OSC_CTL_LFX_OK 10 /* Status of LFXTAL oscillator */ +#define BITP_CLKG_OSC_CTL_HFOSC_OK 9 /* Status of HFOSC oscillator */ +#define BITP_CLKG_OSC_CTL_LFOSC_OK 8 /* Status of LFOSC oscillator */ +#define BITP_CLKG_OSC_CTL_LFX_MON_EN 5 /* LFXTAL clock monitor and Clock FAIL interrupt enable */ +#define BITP_CLKG_OSC_CTL_LFX_BYP 4 /* Low frequency crystal oscillator Bypass */ +#define BITP_CLKG_OSC_CTL_HFX_EN 3 /* High frequency crystal oscillator enable */ +#define BITP_CLKG_OSC_CTL_LFX_EN 2 /* Low frequency crystal oscillator enable */ +#define BITP_CLKG_OSC_CTL_HFOSC_EN 1 /* High frequency internal oscillator enable */ +#define BITP_CLKG_OSC_CTL_LFCLK_MUX 0 /* 32 kHz clock select mux */ +#define BITM_CLKG_OSC_CTL_LFX_FAIL_STA (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* LF XTAL (crystal clock) Not Stable */ +#define BITM_CLKG_OSC_CTL_ROOT_FAIL_STA (_ADI_MSK_3(0x40000000,0x40000000UL, uint32_t )) /* Root clock (crystal clock) Not Stable */ +#define BITM_CLKG_OSC_CTL_ROOT_AUTSW_STA (_ADI_MSK_3(0x00400000,0x00400000UL, uint32_t )) /* Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */ +#define BITM_CLKG_OSC_CTL_ROOT_AUTSW_EN (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Enables automatic Switching of the Root clock to HFOSC on Root clock Failure */ +#define BITM_CLKG_OSC_CTL_ROOT_MON_EN (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* ROOT clock monitor and Clock FAIL interrupt enable */ +#define BITM_CLKG_OSC_CTL_LFX_ROBUST_LD (_ADI_MSK_3(0x00018000,0x00018000UL, uint32_t )) /* LFXTAL Robust Mode Load select */ +#define BITM_CLKG_OSC_CTL_LFX_ROBUST_EN (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* LFXTAL Mode select */ +#define BITM_CLKG_OSC_CTL_LFX_AUTSW_STA (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */ +#define BITM_CLKG_OSC_CTL_LFX_AUTSW_EN (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */ +#define BITM_CLKG_OSC_CTL_HFX_OK (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* Status of HFXTAL oscillator */ +#define BITM_CLKG_OSC_CTL_LFX_OK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* Status of LFXTAL oscillator */ +#define BITM_CLKG_OSC_CTL_HFOSC_OK (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Status of HFOSC oscillator */ +#define BITM_CLKG_OSC_CTL_LFOSC_OK (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* Status of LFOSC oscillator */ +#define BITM_CLKG_OSC_CTL_LFX_MON_EN (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LFXTAL clock monitor and Clock FAIL interrupt enable */ +#define BITM_CLKG_OSC_CTL_LFX_BYP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Low frequency crystal oscillator Bypass */ +#define BITM_CLKG_OSC_CTL_HFX_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* High frequency crystal oscillator enable */ +#define BITM_CLKG_OSC_CTL_LFX_EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Low frequency crystal oscillator enable */ +#define BITM_CLKG_OSC_CTL_HFOSC_EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* High frequency internal oscillator enable */ +#define BITM_CLKG_OSC_CTL_LFCLK_MUX (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* 32 kHz clock select mux */ + + +/* ============================================================================================================================ + Power Management Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + PMG0_TST + ============================================================================================================================ */ +#define REG_PMG0_TST_SRAM_CTL 0x4004C260 /* PMG0_TST Control for SRAM Parity and Instruction SRAM */ +#define REG_PMG0_TST_SRAM_INITSTAT 0x4004C264 /* PMG0_TST Initialization Status Register */ +#define REG_PMG0_TST_CLR_LATCH_GPIOS 0x4004C268 /* PMG0_TST Clear GPIO After Shutdown Mode */ +#define REG_PMG0_TST_SCRPAD_IMG 0x4004C26C /* PMG0_TST Scratch Pad Image */ +#define REG_PMG0_TST_SCRPAD_3V_RD 0x4004C270 /* PMG0_TST Scratch Pad Saved in Battery Domain */ +#define REG_PMG0_TST_FAST_SHT_WAKEUP 0x4004C274 /* PMG0_TST Fast Shutdown Wake-up Enable */ + +/* ============================================================================================================================ + PMG_TST Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SRAM_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SRAM_CTL_INSTREN 31 /* Enables 32 KB instruction SRAM */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK7 23 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK6 22 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK5 21 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK4 20 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK3 19 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK2 18 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK1 17 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_PENBNK0 16 /* Enable parity check */ +#define BITP_PMG_TST_SRAM_CTL_ABTINIT 15 /* Abort current initialization. Self-cleared */ +#define BITP_PMG_TST_SRAM_CTL_AUTOINIT 14 /* Automatic initialization on wake up from hibernate mode */ +#define BITP_PMG_TST_SRAM_CTL_STARTINIT 13 /* Write one to trigger initialization. Self-cleared */ +#define BITP_PMG_TST_SRAM_CTL_BNK7EN 7 /* Enable initialization */ +#define BITP_PMG_TST_SRAM_CTL_BNK2EN 2 /* Enable initialization */ +#define BITP_PMG_TST_SRAM_CTL_BNK1EN 1 /* Enable initialization */ +#define BITM_PMG_TST_SRAM_CTL_INSTREN (_ADI_MSK_3(0x80000000,0x80000000UL, uint32_t )) /* Enables 32 KB instruction SRAM */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK7 (_ADI_MSK_3(0x00800000,0x00800000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK6 (_ADI_MSK_3(0x00400000,0x00400000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK5 (_ADI_MSK_3(0x00200000,0x00200000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK4 (_ADI_MSK_3(0x00100000,0x00100000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK3 (_ADI_MSK_3(0x00080000,0x00080000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK2 (_ADI_MSK_3(0x00040000,0x00040000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK1 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_PENBNK0 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* Enable parity check */ +#define BITM_PMG_TST_SRAM_CTL_ABTINIT (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* Abort current initialization. Self-cleared */ +#define BITM_PMG_TST_SRAM_CTL_AUTOINIT (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Automatic initialization on wake up from hibernate mode */ +#define BITM_PMG_TST_SRAM_CTL_STARTINIT (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* Write one to trigger initialization. Self-cleared */ +#define BITM_PMG_TST_SRAM_CTL_BNK7EN (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* Enable initialization */ +#define BITM_PMG_TST_SRAM_CTL_BNK2EN (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Enable initialization */ +#define BITM_PMG_TST_SRAM_CTL_BNK1EN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Enable initialization */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SRAM_INITSTAT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK7DONE 7 /* Bank 7 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK6DONE 6 /* Bank 6 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK5DONE 5 /* Bank 5 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK4DONE 4 /* Bank 4 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK3DONE 3 /* Bank 3 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK2DONE 2 /* Bank 2 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK1DONE 1 /* Bank 1 initialization status */ +#define BITP_PMG_TST_SRAM_INITSTAT_BNK0DONE 0 /* Bank 0 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK7DONE (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* Bank 7 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK6DONE (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Bank 6 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK5DONE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Bank 5 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK4DONE (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Bank 4 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK3DONE (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Bank 3 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK2DONE (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bank 2 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK1DONE (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* Bank 1 initialization status */ +#define BITM_PMG_TST_SRAM_INITSTAT_BNK0DONE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Bank 0 initialization status */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK7_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK7DONE: Bank 7 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK7_INIT (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* BNK7DONE: Bank 7 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK6_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK6DONE: Bank 6 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK6_INIT (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* BNK6DONE: Bank 6 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK5_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK5DONE: Bank 5 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK5_INIT (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* BNK5DONE: Bank 5 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK4_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK4DONE: Bank 4 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK4_INIT (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* BNK4DONE: Bank 4 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK3_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK3DONE: Bank 3 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK3_INIT (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BNK3DONE: Bank 3 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK2_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK2DONE: Bank 2 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK2_INIT (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* BNK2DONE: Bank 2 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK1_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK1DONE: Bank 1 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK1_INIT (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* BNK1DONE: Bank 1 initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_NO_BANK0_INIT (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* BNK0DONE: Bank 0 not initialized */ +#define ENUM_PMG_TST_SRAM_INITSTAT_BANK0_INIT (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* BNK0DONE: Bank 0 initialized */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_CLR_LATCH_GPIOS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_CLR_LATCH_GPIOS_VALUE 0 /* Writing 0x58FA creates a pulse to clear the latches for the GPIOs */ +#define BITM_PMG_TST_CLR_LATCH_GPIOS_VALUE (_ADI_MSK_3(0x0000FFFF,0x0000FFFFU, uint16_t )) /* Writing 0x58FA creates a pulse to clear the latches for the GPIOs */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SCRPAD_IMG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SCRPAD_IMG_DATA 0 /* Value written to this register is saved in 3 V when going to shutdown */ +#define BITM_PMG_TST_SCRPAD_IMG_DATA (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Value written to this register is saved in 3 V when going to shutdown */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_SCRPAD_3V_RD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_SCRPAD_3V_RD_DATA 0 /* Reading the scratch pad stored in shutdown mode */ +#define BITM_PMG_TST_SCRPAD_3V_RD_DATA (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Reading the scratch pad stored in shutdown mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + PMG_TST_FAST_SHT_WAKEUP Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PMG_TST_FAST_SHT_WAKEUP_FAST_SHT_WAKEUP 0 /* Enables fast shutdown wake-up */ +#define BITM_PMG_TST_FAST_SHT_WAKEUP_FAST_SHT_WAKEUP (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enables fast shutdown wake-up */ + + +/* ============================================================================================================================ + Clocking registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CLKG0_CLK + ============================================================================================================================ */ +#define REG_CLKG0_CLK_CTL0 0x4004C300 /* CLKG0_CLK Misc Clock Settings */ +#define REG_CLKG0_CLK_CTL1 0x4004C304 /* CLKG0_CLK Clock Dividers */ +#define REG_CLKG0_CLK_CTL2 0x4004C308 /* CLKG0_CLK HF Oscillator Divided Clock Select */ +#define REG_CLKG0_CLK_CTL3 0x4004C30C /* CLKG0_CLK System PLL */ +#define REG_CLKG0_CLK_CTL5 0x4004C314 /* CLKG0_CLK User Clock Gating Control */ +#define REG_CLKG0_CLK_STAT0 0x4004C318 /* CLKG0_CLK Clocking Status */ + +/* ============================================================================================================================ + CLKG_CLK Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL0_HFXTALIE 15 /* High frequency crystal interrupt enable */ +#define BITP_CLKG_CLK_CTL0_LFXTALIE 14 /* Low frequency crystal interrupt enable */ +#define BITP_CLKG_CLK_CTL0_PLL_IPSEL 11 /* SPLL source select mux */ +#define BITP_CLKG_CLK_CTL0_RCLKMUX 8 /* Flash reference clock and HPBUCK clock source mux */ +#define BITP_CLKG_CLK_CTL0_CLKOUT 3 /* GPIO clock out select */ +#define BITP_CLKG_CLK_CTL0_CLKMUX 0 /* Clock mux select */ +#define BITM_CLKG_CLK_CTL0_HFXTALIE (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* High frequency crystal interrupt enable */ +#define BITM_CLKG_CLK_CTL0_LFXTALIE (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* Low frequency crystal interrupt enable */ +#define BITM_CLKG_CLK_CTL0_PLL_IPSEL (_ADI_MSK_3(0x00001800,0x00001800UL, uint32_t )) /* SPLL source select mux */ +#define BITM_CLKG_CLK_CTL0_RCLKMUX (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* Flash reference clock and HPBUCK clock source mux */ +#define BITM_CLKG_CLK_CTL0_CLKOUT (_ADI_MSK_3(0x00000078,0x00000078UL, uint32_t )) /* GPIO clock out select */ +#define BITM_CLKG_CLK_CTL0_CLKMUX (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Clock mux select */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL1_ACLKDIVCNT 16 /* ACLK Divide Count */ +#define BITP_CLKG_CLK_CTL1_PCLKDIVCNT 8 /* PCLK divide count */ +#define BITP_CLKG_CLK_CTL1_HCLKDIVCNT 0 /* HCLK divide count */ +#define BITM_CLKG_CLK_CTL1_ACLKDIVCNT (_ADI_MSK_3(0x01FF0000,0x01FF0000UL, uint32_t )) /* ACLK Divide Count */ +#define BITM_CLKG_CLK_CTL1_PCLKDIVCNT (_ADI_MSK_3(0x00003F00,0x00003F00UL, uint32_t )) /* PCLK divide count */ +#define BITM_CLKG_CLK_CTL1_HCLKDIVCNT (_ADI_MSK_3(0x0000003F,0x0000003FUL, uint32_t )) /* HCLK divide count */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL2_HFOSCDIVCLKSEL 1 /* HF Oscillator divided clock select */ +#define BITP_CLKG_CLK_CTL2_HFOSCAUTODIV_EN 0 /* HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */ +#define BITM_CLKG_CLK_CTL2_HFOSCDIVCLKSEL (_ADI_MSK_3(0x0000000E,0x0000000EUL, uint32_t )) /* HF Oscillator divided clock select */ +#define BITM_CLKG_CLK_CTL2_HFOSCAUTODIV_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL3_SPLLMUL2 16 /* System PLL multiply by 2 */ +#define BITP_CLKG_CLK_CTL3_SPLLMSEL 11 /* System PLL M Divider */ +#define BITP_CLKG_CLK_CTL3_SPLLIE 10 /* System PLL interrupt enable */ +#define BITP_CLKG_CLK_CTL3_SPLLEN 9 /* System PLL enable */ +#define BITP_CLKG_CLK_CTL3_SPLLDIV2 8 /* System PLL division by 2 */ +#define BITP_CLKG_CLK_CTL3_SPLLNSEL 0 /* System PLL N multiplier */ +#define BITM_CLKG_CLK_CTL3_SPLLMUL2 (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* System PLL multiply by 2 */ +#define BITM_CLKG_CLK_CTL3_SPLLMSEL (_ADI_MSK_3(0x00007800,0x00007800UL, uint32_t )) /* System PLL M Divider */ +#define BITM_CLKG_CLK_CTL3_SPLLIE (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* System PLL interrupt enable */ +#define BITM_CLKG_CLK_CTL3_SPLLEN (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* System PLL enable */ +#define BITM_CLKG_CLK_CTL3_SPLLDIV2 (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* System PLL division by 2 */ +#define BITM_CLKG_CLK_CTL3_SPLLNSEL (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t )) /* System PLL N multiplier */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_CTL5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_CTL5_TMRRGBCLKOFF 6 /* Timer RGB user control */ +#define BITP_CLKG_CLK_CTL5_PERCLKOFF 5 /* This bit is used to disable all clocks connected to all peripherals */ +#define BITP_CLKG_CLK_CTL5_GPIOCLKOFF 4 /* GPIO clock control */ +#define BITP_CLKG_CLK_CTL5_UCLKI2COFF 3 /* I2C clock user control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK2OFF 2 /* GP Timer 2 user control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK1OFF 1 /* GP Timer 1 user control */ +#define BITP_CLKG_CLK_CTL5_GPTCLK0OFF 0 /* GP Timer 0 user control */ +#define BITM_CLKG_CLK_CTL5_TMRRGBCLKOFF (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* Timer RGB user control */ +#define BITM_CLKG_CLK_CTL5_PERCLKOFF (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* This bit is used to disable all clocks connected to all peripherals */ +#define BITM_CLKG_CLK_CTL5_GPIOCLKOFF (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* GPIO clock control */ +#define BITM_CLKG_CLK_CTL5_UCLKI2COFF (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* I2C clock user control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK2OFF (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* GP Timer 2 user control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK1OFF (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* GP Timer 1 user control */ +#define BITM_CLKG_CLK_CTL5_GPTCLK0OFF (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* GP Timer 0 user control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CLKG_CLK_STAT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CLKG_CLK_STAT0_HFXTALNOK 14 /* HF crystal not stable */ +#define BITP_CLKG_CLK_STAT0_HFXTALOK 13 /* HF crystal stable */ +#define BITP_CLKG_CLK_STAT0_HFXTAL 12 /* HF crystal status */ +#define BITP_CLKG_CLK_STAT0_LFXTALNOK 10 /* LF crystal not stable */ +#define BITP_CLKG_CLK_STAT0_LFXTALOK 9 /* LF crystal stable */ +#define BITP_CLKG_CLK_STAT0_LFXTAL 8 /* LF crystal status */ +#define BITP_CLKG_CLK_STAT0_SPLLUNLK 2 /* System PLL unlock */ +#define BITP_CLKG_CLK_STAT0_SPLLLK 1 /* System PLL lock */ +#define BITP_CLKG_CLK_STAT0_SPLL 0 /* System PLL status */ +#define BITM_CLKG_CLK_STAT0_HFXTALNOK (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* HF crystal not stable */ +#define BITM_CLKG_CLK_STAT0_HFXTALOK (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* HF crystal stable */ +#define BITM_CLKG_CLK_STAT0_HFXTAL (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* HF crystal status */ +#define BITM_CLKG_CLK_STAT0_LFXTALNOK (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* LF crystal not stable */ +#define BITM_CLKG_CLK_STAT0_LFXTALOK (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* LF crystal stable */ +#define BITM_CLKG_CLK_STAT0_LFXTAL (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* LF crystal status */ +#define BITM_CLKG_CLK_STAT0_SPLLUNLK (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* System PLL unlock */ +#define BITM_CLKG_CLK_STAT0_SPLLLK (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* System PLL lock */ +#define BITM_CLKG_CLK_STAT0_SPLL (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* System PLL status */ + + +/* ============================================================================================================================ + Bus matrix + ============================================================================================================================ */ + +/* ============================================================================================================================ + BUSM0 + ============================================================================================================================ */ +#define REG_BUSM0_ARBIT0 0x4004C800 /* BUSM0 Arbitration Priority Configuration for FLASH and SRAM0 */ +#define REG_BUSM0_ARBIT1 0x4004C804 /* BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */ +#define REG_BUSM0_ARBIT2 0x4004C808 /* BUSM0 Arbitration Priority Configuration for APB32 and APB16 */ +#define REG_BUSM0_ARBIT3 0x4004C80C /* BUSM0 Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ +#define REG_BUSM0_ARBIT4 0x4004C814 /* BUSM0 Arbitration Priority Configuration for SRAM1 and SIP */ + +/* ============================================================================================================================ + BUSM Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT0_SRAM0_DMA0 20 /* SRAM0 priority for DMA0 */ +#define BITP_BUSM_ARBIT0_SRAM0_SBUS 18 /* SRAM0 priority for SBUS */ +#define BITP_BUSM_ARBIT0_SRAM0_DCODE 16 /* SRAM0 priority for Dcode */ +#define BITP_BUSM_ARBIT0_FLSH_DMA0 4 /* Flash priority for DMA0 */ +#define BITP_BUSM_ARBIT0_FLSH_SBUS 2 /* Flash priority for SBUS */ +#define BITP_BUSM_ARBIT0_FLSH_DCODE 0 /* Flash priority for DCODE */ +#define BITM_BUSM_ARBIT0_SRAM0_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* SRAM0 priority for DMA0 */ +#define BITM_BUSM_ARBIT0_SRAM0_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* SRAM0 priority for SBUS */ +#define BITM_BUSM_ARBIT0_SRAM0_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* SRAM0 priority for Dcode */ +#define BITM_BUSM_ARBIT0_FLSH_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* Flash priority for DMA0 */ +#define BITM_BUSM_ARBIT0_FLSH_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* Flash priority for SBUS */ +#define BITM_BUSM_ARBIT0_FLSH_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* Flash priority for DCODE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT1_SIP_DMA0 20 /* SIP priority for DMA0 */ +#define BITP_BUSM_ARBIT1_SIP_SBUS 18 /* SIP priority for SBUS */ +#define BITP_BUSM_ARBIT1_SIP_DCODE 16 /* SIP priority for DCODE */ +#define BITP_BUSM_ARBIT1_SRAM1_DMA0 4 /* SRAM1 priority for DMA0 */ +#define BITP_BUSM_ARBIT1_SRAM1_SBUS 2 /* SRAM1 priority for SBUS */ +#define BITP_BUSM_ARBIT1_SRAM1_DCODE 0 /* SRAM1 priority for Dcode */ +#define BITM_BUSM_ARBIT1_SIP_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* SIP priority for DMA0 */ +#define BITM_BUSM_ARBIT1_SIP_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* SIP priority for SBUS */ +#define BITM_BUSM_ARBIT1_SIP_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* SIP priority for DCODE */ +#define BITM_BUSM_ARBIT1_SRAM1_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* SRAM1 priority for DMA0 */ +#define BITM_BUSM_ARBIT1_SRAM1_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* SRAM1 priority for SBUS */ +#define BITM_BUSM_ARBIT1_SRAM1_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* SRAM1 priority for Dcode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT2_APB16_DMA0 20 /* APB16 priority for DMA0 */ +#define BITP_BUSM_ARBIT2_APB16_SBUS 18 /* APB16 priority for SBUS */ +#define BITP_BUSM_ARBIT2_APB16_DCODE 16 /* APB16 priority for DCODE */ +#define BITP_BUSM_ARBIT2_APB32_DMA0 4 /* APB32 priority for DMA0 */ +#define BITP_BUSM_ARBIT2_APB32_SBUS 2 /* APB32 priority for SBUS */ +#define BITP_BUSM_ARBIT2_APB32_DCODE 0 /* APB32 priority for DCODE */ +#define BITM_BUSM_ARBIT2_APB16_DMA0 (_ADI_MSK_3(0x00300000,0x00300000UL, uint32_t )) /* APB16 priority for DMA0 */ +#define BITM_BUSM_ARBIT2_APB16_SBUS (_ADI_MSK_3(0x000C0000,0x000C0000UL, uint32_t )) /* APB16 priority for SBUS */ +#define BITM_BUSM_ARBIT2_APB16_DCODE (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* APB16 priority for DCODE */ +#define BITM_BUSM_ARBIT2_APB32_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* APB32 priority for DMA0 */ +#define BITM_BUSM_ARBIT2_APB32_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* APB32 priority for SBUS */ +#define BITM_BUSM_ARBIT2_APB32_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* APB32 priority for DCODE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT3_APB16_4DMA_DMA1 17 /* APB16 for dma priority for DMA1 */ +#define BITP_BUSM_ARBIT3_APB16_4DMA_CORE 16 /* APB16 for dma priority for CORE */ +#define BITP_BUSM_ARBIT3_APB16_DMA1 1 /* APB16 priority for DMA1 */ +#define BITP_BUSM_ARBIT3_APB16_CORE 0 /* APB16 priority for CORE */ +#define BITM_BUSM_ARBIT3_APB16_4DMA_DMA1 (_ADI_MSK_3(0x00020000,0x00020000UL, uint32_t )) /* APB16 for dma priority for DMA1 */ +#define BITM_BUSM_ARBIT3_APB16_4DMA_CORE (_ADI_MSK_3(0x00010000,0x00010000UL, uint32_t )) /* APB16 for dma priority for CORE */ +#define BITM_BUSM_ARBIT3_APB16_DMA1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* APB16 priority for DMA1 */ +#define BITM_BUSM_ARBIT3_APB16_CORE (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* APB16 priority for CORE */ + +/* ------------------------------------------------------------------------------------------------------------------------- + BUSM_ARBIT4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_BUSM_ARBIT4_SRAM2_DMA0 4 /* SRAM2 priority for DMA0 */ +#define BITP_BUSM_ARBIT4_SRAM2_SBUS 2 /* SRAM2 priority for SBUS */ +#define BITP_BUSM_ARBIT4_SRAM2_DCODE 0 /* SRAM2 priority for Dcode */ +#define BITM_BUSM_ARBIT4_SRAM2_DMA0 (_ADI_MSK_3(0x00000030,0x00000030UL, uint32_t )) /* SRAM2 priority for DMA0 */ +#define BITM_BUSM_ARBIT4_SRAM2_SBUS (_ADI_MSK_3(0x0000000C,0x0000000CUL, uint32_t )) /* SRAM2 priority for SBUS */ +#define BITM_BUSM_ARBIT4_SRAM2_DCODE (_ADI_MSK_3(0x00000003,0x00000003UL, uint32_t )) /* SRAM2 priority for Dcode */ + + +/* ============================================================================================================================ + Parallel Test Interface + ============================================================================================================================ */ + +/* ============================================================================================================================ + PTI0 + ============================================================================================================================ */ +#define REG_PTI0_RST_ISR_STARTADDR 0x4004CD00 /* PTI0 Reset ISR Start Address */ +#define REG_PTI0_RST_STACK_PTR 0x4004CD04 /* PTI0 Reset Stack Pointer */ +#define REG_PTI0_CTL 0x4004CD08 /* PTI0 Parallel Test Interface Control Register */ + +/* ============================================================================================================================ + PTI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_RST_ISR_STARTADDR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_RST_ISR_STARTADDR_VALUE 0 +#define BITM_PTI_RST_ISR_STARTADDR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) + +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_RST_STACK_PTR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_RST_STACK_PTR_VALUE 0 +#define BITM_PTI_RST_STACK_PTR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) + +/* ------------------------------------------------------------------------------------------------------------------------- + PTI_CTL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_PTI_CTL_EN 0 +#define BITM_PTI_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) + + +/* ============================================================================================================================ + Cortex-M3 Interrupt Controller + ============================================================================================================================ */ + +/* ============================================================================================================================ + NVIC0 + ============================================================================================================================ */ +#define REG_NVIC0_INTNUM 0xE000E004 /* NVIC0 Interrupt Control Type */ +#define REG_NVIC0_STKSTA 0xE000E010 /* NVIC0 Systick Control and Status */ +#define REG_NVIC0_STKLD 0xE000E014 /* NVIC0 Systick Reload Value */ +#define REG_NVIC0_STKVAL 0xE000E018 /* NVIC0 Systick Current Value */ +#define REG_NVIC0_STKCAL 0xE000E01C /* NVIC0 Systick Calibration Value */ +#define REG_NVIC0_INTSETE0 0xE000E100 /* NVIC0 IRQ0..31 Set_Enable */ +#define REG_NVIC0_INTSETE1 0xE000E104 /* NVIC0 IRQ32..63 Set_Enable */ +#define REG_NVIC0_INTCLRE0 0xE000E180 /* NVIC0 IRQ0..31 Clear_Enable */ +#define REG_NVIC0_INTCLRE1 0xE000E184 /* NVIC0 IRQ32..63 Clear_Enable */ +#define REG_NVIC0_INTSETP0 0xE000E200 /* NVIC0 IRQ0..31 Set_Pending */ +#define REG_NVIC0_INTSETP1 0xE000E204 /* NVIC0 IRQ32..63 Set_Pending */ +#define REG_NVIC0_INTCLRP0 0xE000E280 /* NVIC0 IRQ0..31 Clear_Pending */ +#define REG_NVIC0_INTCLRP1 0xE000E284 /* NVIC0 IRQ32..63 Clear_Pending */ +#define REG_NVIC0_INTACT0 0xE000E300 /* NVIC0 IRQ0..31 Active Bit */ +#define REG_NVIC0_INTACT1 0xE000E304 /* NVIC0 IRQ32..63 Active Bit */ +#define REG_NVIC0_INTPRI0 0xE000E400 /* NVIC0 IRQ0..3 Priority */ +#define REG_NVIC0_INTPRI1 0xE000E404 /* NVIC0 IRQ4..7 Priority */ +#define REG_NVIC0_INTPRI2 0xE000E408 /* NVIC0 IRQ8..11 Priority */ +#define REG_NVIC0_INTPRI3 0xE000E40C /* NVIC0 IRQ12..15 Priority */ +#define REG_NVIC0_INTPRI4 0xE000E410 /* NVIC0 IRQ16..19 Priority */ +#define REG_NVIC0_INTPRI5 0xE000E414 /* NVIC0 IRQ20..23 Priority */ +#define REG_NVIC0_INTPRI6 0xE000E418 /* NVIC0 IRQ24..27 Priority */ +#define REG_NVIC0_INTPRI7 0xE000E41C /* NVIC0 IRQ28..31 Priority */ +#define REG_NVIC0_INTPRI8 0xE000E420 /* NVIC0 IRQ32..35 Priority */ +#define REG_NVIC0_INTPRI9 0xE000E424 /* NVIC0 IRQ36..39 Priority */ +#define REG_NVIC0_INTPRI10 0xE000E428 /* NVIC0 IRQ40..43 Priority */ +#define REG_NVIC0_INTCPID 0xE000ED00 /* NVIC0 CPUID Base */ +#define REG_NVIC0_INTSTA 0xE000ED04 /* NVIC0 Interrupt Control State */ +#define REG_NVIC0_INTVEC 0xE000ED08 /* NVIC0 Vector Table Offset */ +#define REG_NVIC0_INTAIRC 0xE000ED0C /* NVIC0 Application Interrupt/Reset Control */ +#define REG_NVIC0_INTCON0 0xE000ED10 /* NVIC0 System Control */ +#define REG_NVIC0_INTCON1 0xE000ED14 /* NVIC0 Configuration Control */ +#define REG_NVIC0_INTSHPRIO0 0xE000ED18 /* NVIC0 System Handlers 4-7 Priority */ +#define REG_NVIC0_INTSHPRIO1 0xE000ED1C /* NVIC0 System Handlers 8-11 Priority */ +#define REG_NVIC0_INTSHPRIO3 0xE000ED20 /* NVIC0 System Handlers 12-15 Priority */ +#define REG_NVIC0_INTSHCSR 0xE000ED24 /* NVIC0 System Handler Control and State */ +#define REG_NVIC0_INTCFSR 0xE000ED28 /* NVIC0 Configurable Fault Status */ +#define REG_NVIC0_INTHFSR 0xE000ED2C /* NVIC0 Hard Fault Status */ +#define REG_NVIC0_INTDFSR 0xE000ED30 /* NVIC0 Debug Fault Status */ +#define REG_NVIC0_INTMMAR 0xE000ED34 /* NVIC0 Mem Manage Address */ +#define REG_NVIC0_INTBFAR 0xE000ED38 /* NVIC0 Bus Fault Address */ +#define REG_NVIC0_INTAFSR 0xE000ED3C /* NVIC0 Auxiliary Fault Status */ +#define REG_NVIC0_INTPFR0 0xE000ED40 /* NVIC0 Processor Feature Register 0 */ +#define REG_NVIC0_INTPFR1 0xE000ED44 /* NVIC0 Processor Feature Register 1 */ +#define REG_NVIC0_INTDFR0 0xE000ED48 /* NVIC0 Debug Feature Register 0 */ +#define REG_NVIC0_INTAFR0 0xE000ED4C /* NVIC0 Auxiliary Feature Register 0 */ +#define REG_NVIC0_INTMMFR0 0xE000ED50 /* NVIC0 Memory Model Feature Register 0 */ +#define REG_NVIC0_INTMMFR1 0xE000ED54 /* NVIC0 Memory Model Feature Register 1 */ +#define REG_NVIC0_INTMMFR2 0xE000ED58 /* NVIC0 Memory Model Feature Register 2 */ +#define REG_NVIC0_INTMMFR3 0xE000ED5C /* NVIC0 Memory Model Feature Register 3 */ +#define REG_NVIC0_INTISAR0 0xE000ED60 /* NVIC0 ISA Feature Register 0 */ +#define REG_NVIC0_INTISAR1 0xE000ED64 /* NVIC0 ISA Feature Register 1 */ +#define REG_NVIC0_INTISAR2 0xE000ED68 /* NVIC0 ISA Feature Register 2 */ +#define REG_NVIC0_INTISAR3 0xE000ED6C /* NVIC0 ISA Feature Register 3 */ +#define REG_NVIC0_INTISAR4 0xE000ED70 /* NVIC0 ISA Feature Register 4 */ +#define REG_NVIC0_INTTRGI 0xE000EF00 /* NVIC0 Software Trigger Interrupt Register */ +#define REG_NVIC0_INTPID4 0xE000EFD0 /* NVIC0 Peripheral Identification Register 4 */ +#define REG_NVIC0_INTPID5 0xE000EFD4 /* NVIC0 Peripheral Identification Register 5 */ +#define REG_NVIC0_INTPID6 0xE000EFD8 /* NVIC0 Peripheral Identification Register 6 */ +#define REG_NVIC0_INTPID7 0xE000EFDC /* NVIC0 Peripheral Identification Register 7 */ +#define REG_NVIC0_INTPID0 0xE000EFE0 /* NVIC0 Peripheral Identification Bits7:0 */ +#define REG_NVIC0_INTPID1 0xE000EFE4 /* NVIC0 Peripheral Identification Bits15:8 */ +#define REG_NVIC0_INTPID2 0xE000EFE8 /* NVIC0 Peripheral Identification Bits16:23 */ +#define REG_NVIC0_INTPID3 0xE000EFEC /* NVIC0 Peripheral Identification Bits24:31 */ +#define REG_NVIC0_INTCID0 0xE000EFF0 /* NVIC0 Component Identification Bits7:0 */ +#define REG_NVIC0_INTCID1 0xE000EFF4 /* NVIC0 Component Identification Bits15:8 */ +#define REG_NVIC0_INTCID2 0xE000EFF8 /* NVIC0 Component Identification Bits16:23 */ +#define REG_NVIC0_INTCID3 0xE000EFFC /* NVIC0 Component Identification Bits24:31 */ + +/* ============================================================================================================================ + NVIC Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTNUM Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTNUM_VALUE 0 /* Interrupt Control Type */ +#define BITM_NVIC_INTNUM_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Interrupt Control Type */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKSTA_VALUE 0 /* Systick Control and Status */ +#define BITM_NVIC_STKSTA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Control and Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKLD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKLD_VALUE 0 /* Systick Reload Value */ +#define BITM_NVIC_STKLD_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Reload Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKVAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKVAL_VALUE 0 /* Systick Current Value */ +#define BITM_NVIC_STKVAL_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Current Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_STKCAL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_STKCAL_VALUE 0 /* Systick Calibration Value */ +#define BITM_NVIC_STKCAL_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Systick Calibration Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETE0_VALUE 0 /* IRQ0..31 Set_Enable */ +#define BITM_NVIC_INTSETE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Set_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETE1_VALUE 0 /* IRQ32..63 Set_Enable */ +#define BITM_NVIC_INTSETE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Set_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRE0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRE0_VALUE 0 /* IRQ0..31 Clear_Enable */ +#define BITM_NVIC_INTCLRE0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Clear_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRE1_VALUE 0 /* IRQ32..63 Clear_Enable */ +#define BITM_NVIC_INTCLRE1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Clear_Enable */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETP0_VALUE 0 /* IRQ0..31 Set_Pending */ +#define BITM_NVIC_INTSETP0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Set_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSETP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSETP1_VALUE 0 /* IRQ32..63 Set_Pending */ +#define BITM_NVIC_INTSETP1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Set_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRP0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRP0_VALUE 0 /* IRQ0..31 Clear_Pending */ +#define BITM_NVIC_INTCLRP0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Clear_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCLRP1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCLRP1_VALUE 0 /* IRQ32..63 Clear_Pending */ +#define BITM_NVIC_INTCLRP1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Clear_Pending */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTACT0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTACT0_VALUE 0 /* IRQ0..31 Active Bit */ +#define BITM_NVIC_INTACT0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..31 Active Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTACT1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTACT1_VALUE 0 /* IRQ32..63 Active Bit */ +#define BITM_NVIC_INTACT1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..63 Active Bit */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI0_VALUE 0 /* IRQ0..3 Priority */ +#define BITM_NVIC_INTPRI0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ0..3 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI1_VALUE 0 /* IRQ4..7 Priority */ +#define BITM_NVIC_INTPRI1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ4..7 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI2_VALUE 0 /* IRQ8..11 Priority */ +#define BITM_NVIC_INTPRI2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ8..11 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI3_VALUE 0 /* IRQ12..15 Priority */ +#define BITM_NVIC_INTPRI3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ12..15 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI4_VALUE 0 /* IRQ16..19 Priority */ +#define BITM_NVIC_INTPRI4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ16..19 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI5_VALUE 0 /* IRQ20..23 Priority */ +#define BITM_NVIC_INTPRI5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ20..23 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI6_VALUE 0 /* IRQ24..27 Priority */ +#define BITM_NVIC_INTPRI6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ24..27 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI7_VALUE 0 /* IRQ28..31 Priority */ +#define BITM_NVIC_INTPRI7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ28..31 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI8 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI8_VALUE 0 /* IRQ32..35 Priority */ +#define BITM_NVIC_INTPRI8_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ32..35 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI9 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI9_VALUE 0 /* IRQ36..39 Priority */ +#define BITM_NVIC_INTPRI9_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ36..39 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPRI10 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPRI10_VALUE 0 /* IRQ40..43 Priority */ +#define BITM_NVIC_INTPRI10_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* IRQ40..43 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCPID Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCPID_VALUE 0 /* CPUID Base */ +#define BITM_NVIC_INTCPID_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CPUID Base */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSTA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSTA_VALUE 0 /* Interrupt Control State */ +#define BITM_NVIC_INTSTA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Interrupt Control State */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTVEC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTVEC_VALUE 0 /* Vector Table Offset */ +#define BITM_NVIC_INTVEC_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Vector Table Offset */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAIRC Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAIRC_VALUE 0 /* Application Interrupt/Reset Control */ +#define BITM_NVIC_INTAIRC_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Application Interrupt/Reset Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCON0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCON0_SLEEPDEEP 2 /* deep sleep flag for HIBERNATE mode */ +#define BITP_NVIC_INTCON0_SLEEPONEXIT 1 /* Sleeps the core on exit from an ISR */ +#define BITM_NVIC_INTCON0_SLEEPDEEP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* deep sleep flag for HIBERNATE mode */ +#define BITM_NVIC_INTCON0_SLEEPONEXIT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Sleeps the core on exit from an ISR */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCON1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCON1_VALUE 0 /* Configuration Control */ +#define BITM_NVIC_INTCON1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Configuration Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO0_VALUE 0 /* System Handlers 4-7 Priority */ +#define BITM_NVIC_INTSHPRIO0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 4-7 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO1_VALUE 0 /* System Handlers 8-11 Priority */ +#define BITM_NVIC_INTSHPRIO1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 8-11 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHPRIO3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHPRIO3_VALUE 0 /* System Handlers 12-15 Priority */ +#define BITM_NVIC_INTSHPRIO3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handlers 12-15 Priority */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTSHCSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTSHCSR_VALUE 0 /* System Handler Control and State */ +#define BITM_NVIC_INTSHCSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* System Handler Control and State */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCFSR_VALUE 0 /* Configurable Fault Status */ +#define BITM_NVIC_INTCFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Configurable Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTHFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTHFSR_VALUE 0 /* Hard Fault Status */ +#define BITM_NVIC_INTHFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Hard Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTDFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTDFSR_VALUE 0 /* Debug Fault Status */ +#define BITM_NVIC_INTDFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Debug Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMAR_VALUE 0 /* Mem Manage Address */ +#define BITM_NVIC_INTMMAR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Mem Manage Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTBFAR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTBFAR_VALUE 0 /* Bus Fault Address */ +#define BITM_NVIC_INTBFAR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Bus Fault Address */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAFSR Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAFSR_VALUE 0 /* Auxiliary Fault Status */ +#define BITM_NVIC_INTAFSR_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Auxiliary Fault Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPFR0_VALUE 0 /* Processor Feature Register 0 */ +#define BITM_NVIC_INTPFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Processor Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPFR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPFR1_VALUE 0 /* Processor Feature Register 1 */ +#define BITM_NVIC_INTPFR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Processor Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTDFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTDFR0_VALUE 0 /* Debug Feature Register 0 */ +#define BITM_NVIC_INTDFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Debug Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTAFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTAFR0_VALUE 0 /* Auxiliary Feature Register 0 */ +#define BITM_NVIC_INTAFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Auxiliary Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR0_VALUE 0 /* Memory Model Feature Register 0 */ +#define BITM_NVIC_INTMMFR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR1_VALUE 0 /* Memory Model Feature Register 1 */ +#define BITM_NVIC_INTMMFR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR2_VALUE 0 /* Memory Model Feature Register 2 */ +#define BITM_NVIC_INTMMFR2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTMMFR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTMMFR3_VALUE 0 /* Memory Model Feature Register 3 */ +#define BITM_NVIC_INTMMFR3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Memory Model Feature Register 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR0_VALUE 0 /* ISA Feature Register 0 */ +#define BITM_NVIC_INTISAR0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR1_VALUE 0 /* ISA Feature Register 1 */ +#define BITM_NVIC_INTISAR1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 1 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR2_VALUE 0 /* ISA Feature Register 2 */ +#define BITM_NVIC_INTISAR2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 2 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR3_VALUE 0 /* ISA Feature Register 3 */ +#define BITM_NVIC_INTISAR3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 3 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTISAR4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTISAR4_VALUE 0 /* ISA Feature Register 4 */ +#define BITM_NVIC_INTISAR4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* ISA Feature Register 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTTRGI Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTTRGI_VALUE 0 /* Software Trigger Interrupt Register */ +#define BITM_NVIC_INTTRGI_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Software Trigger Interrupt Register */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID4 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID4_VALUE 0 /* Peripheral Identification Register 4 */ +#define BITM_NVIC_INTPID4_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 4 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID5 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID5_VALUE 0 /* Peripheral Identification Register 5 */ +#define BITM_NVIC_INTPID5_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 5 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID6 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID6_VALUE 0 /* Peripheral Identification Register 6 */ +#define BITM_NVIC_INTPID6_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 6 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID7 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID7_VALUE 0 /* Peripheral Identification Register 7 */ +#define BITM_NVIC_INTPID7_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Register 7 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID0_VALUE 0 /* Peripheral Identification Bits7:0 */ +#define BITM_NVIC_INTPID0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits7:0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID1_VALUE 0 /* Peripheral Identification Bits15:8 */ +#define BITM_NVIC_INTPID1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits15:8 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID2_VALUE 0 /* Peripheral Identification Bits16:23 */ +#define BITM_NVIC_INTPID2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits16:23 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTPID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTPID3_VALUE 0 /* Peripheral Identification Bits24:31 */ +#define BITM_NVIC_INTPID3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Peripheral Identification Bits24:31 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID0_VALUE 0 /* Component Identification Bits7:0 */ +#define BITM_NVIC_INTCID0_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits7:0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID1_VALUE 0 /* Component Identification Bits15:8 */ +#define BITM_NVIC_INTCID1_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits15:8 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID2_VALUE 0 /* Component Identification Bits16:23 */ +#define BITM_NVIC_INTCID2_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits16:23 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + NVIC_INTCID3 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_NVIC_INTCID3_VALUE 0 /* Component Identification Bits24:31 */ +#define BITM_NVIC_INTCID3_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* Component Identification Bits24:31 */ + +/* ==================================================================================================== + * Interrupt Definitions + * ==================================================================================================== */ +#define INTR_RESET (-15) /* Cortex-M4 Reset */ +#define INTR_NonMaskableInt (-14) /* Cortex-M4 Non-maskable Interrupt */ +#define INTR_HardFault (-13) /* Cortex-M4 Hardware Fault */ +#define INTR_MemoryManagement (-12) /* Cortex-M4 Memory Management Interrupt */ +#define INTR_BusFault (-11) /* Cortex-M4 Bus Fault */ +#define INTR_UsageFault (-10) /* Cortex-M4 Usage Fault */ +#define INTR_SVCall ( -5) /* Cortex-M4 SVCall Interrupt */ +#define INTR_DebugMonitor ( -4) /* Cortex-M4 Debug Monitor */ +#define INTR_PendSV ( -2) /* Cortex-M4 PendSV Interrupt */ +#define INTR_SysTick ( -1) /* Cortex-M4 SysTick Interrupt */ +#define INTR_RTC1_EVT 0 /* Event */ +#define INTR_XINT_EVT0 1 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT1 2 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT2 3 /* External Wakeup Interrupt n */ +#define INTR_XINT_EVT3 4 /* External Wakeup Interrupt n */ +#define INTR_WDT_EXP 5 /* Expiration */ +#define INTR_PMG0_VREG_OVR 6 /* Voltage Regulator (VREG) Overvoltage */ +#define INTR_PMG0_BATT_RANGE 7 /* Battery Voltage (VBAT) Out of Range */ +#define INTR_RTC0_EVT 8 /* Event */ +#define INTR_SYS_GPIO_INTA 9 /* GPIO Interrupt A */ +#define INTR_SYS_GPIO_INTB 10 /* GPIO Interrupt B */ +#define INTR_TMR0_EVT 11 /* Event */ +#define INTR_TMR1_EVT 12 /* Event */ +#define INTR_FLCC_EVT 13 /* Event */ +#define INTR_UART0_EVT 14 /* UART0 Event */ +#define INTR_SPI0_EVT 15 /* Event */ +#define INTR_SPI2_EVT 16 /* Event */ +#define INTR_I2C_SLV_EVT 17 /* Slave Event */ +#define INTR_I2C_MST_EVT 18 /* Master Event */ +#define INTR_DMA_CHAN_ERR 19 /* Channel Error */ +#define INTR_DMA0_CH0_DONE 20 /* Channel 0 Done */ +#define INTR_DMA0_CH1_DONE 21 /* Channel 1 Done */ +#define INTR_DMA0_CH2_DONE 22 /* Channel 2 Done */ +#define INTR_DMA0_CH3_DONE 23 /* Channel 3 Done */ +#define INTR_DMA0_CH4_DONE 24 /* Channel 4 Done */ +#define INTR_DMA0_CH5_DONE 25 /* Channel 5 Done */ +#define INTR_DMA0_CH6_DONE 26 /* Channel 6 Done */ +#define INTR_DMA0_CH7_DONE 27 /* Channel 7 Done */ +#define INTR_DMA0_CH8_DONE 28 /* Channel 8 Done */ +#define INTR_DMA0_CH9_DONE 29 /* Channel 9 Done */ +#define INTR_DMA0_CH10_DONE 30 /* Channel 10 Done */ +#define INTR_DMA0_CH11_DONE 31 /* Channel 11 Done */ +#define INTR_DMA0_CH12_DONE 32 /* Channel 12 Done */ +#define INTR_DMA0_CH13_DONE 33 /* Channel 13 Done */ +#define INTR_DMA0_CH14_DONE 34 /* Channel 14 Done */ +#define INTR_DMA0_CH15_DONE 35 /* Channel 15 Done */ +#define INTR_SPORT_A_EVT 36 /* Channel A Event */ +#define INTR_SPORT_B_EVT 37 /* Channel B Event */ +#define INTR_CRYPT_EVT 38 /* Event */ +#define INTR_DMA0_CH24_DONE 39 /* Channel 24 Done */ +#define INTR_TMR2_EVT 40 /* Event */ +#define INTR_CLKG_XTAL_OSC_EVT 41 /* Crystal Oscillator Event */ +#define INTR_SPI1_EVT 42 /* Event */ +#define INTR_CLKG_PLL_EVT 43 /* PLL Event */ +#define INTR_RNG0_EVT 44 /* Event */ +#define INTR_BEEP_EVT 45 /* Event */ +#define INTR_ADC0_EVT 46 /* Event */ +#define INTR_DMA0_CH16_DONE 56 /* Channel 16 Done */ +#define INTR_DMA0_CH17_DONE 57 /* Channel 17 Done */ +#define INTR_DMA0_CH18_DONE 58 /* Channel 18 Done */ +#define INTR_DMA0_CH19_DONE 59 /* Channel 19 Done */ +#define INTR_DMA0_CH20_DONE 60 /* Channel 20 Done */ +#define INTR_DMA0_CH21_DONE 61 /* Channel 21 Done */ +#define INTR_DMA0_CH22_DONE 62 /* Channel 22 Done */ +#define INTR_DMA0_CH23_DONE 63 /* Channel 23 Done */ +#define INTR_UART1_EVT 66 /* Event */ +#define INTR_DMA0_CH25_DONE 67 /* Channel 25 Done */ +#define INTR_DMA0_CH26_DONE 68 /* Channel 26 Done */ +#define INTR_TMR_RGB_EVT 69 /* Event */ +#define INTR_CLKG_ROOTCLK_ERR 71 /* Root Clock Error */ + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + +#endif /* end ifndef _DEF_ADUCM4050_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h new file mode 100755 index 00000000000..067c0386a3d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_cdef.h @@ -0,0 +1,788 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050_cdef.h + Description : C MMR Pointer Definitions + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM4050_CDEF_H +#define _ADUCM4050_CDEF_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "adi_ADuCM4050.h" + + +#ifndef __IO +#ifdef __cplusplus +#define __I volatile /* read-only */ +#define __C +#else +#define __I volatile /* read-only */ +#define __C const +#endif +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif +#if defined (_MISRA_RULES) +#pragma diag(push) +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_19_7:"ADI header allows function-like macros") +#pragma diag(suppress:misra_rule_19_13:"ADI headers can use the # and ## preprocessor operators") +#endif /* _MISRA_RULES */ + + +/* ================================================================================= + * General Purpose Timer (TMR0) + * ================================================================================= */ +#define pREG_TMR0_LOAD ((__IO uint16_t *) REG_TMR0_LOAD) /* 16-bit Load Value */ +#define pREG_TMR0_CURCNT ((__I __C uint16_t *) REG_TMR0_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR0_CTL ((__IO uint16_t *) REG_TMR0_CTL) /* Control */ +#define pREG_TMR0_CLRINT ((__O uint16_t *) REG_TMR0_CLRINT) /* Clear Interrupt */ +#define pREG_TMR0_CAPTURE ((__I __C uint16_t *) REG_TMR0_CAPTURE) /* Capture */ +#define pREG_TMR0_ALOAD ((__IO uint16_t *) REG_TMR0_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR0_ACURCNT ((__I __C uint16_t *) REG_TMR0_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR0_STAT ((__I __C uint16_t *) REG_TMR0_STAT) /* Status */ +#define pREG_TMR0_PWMCTL ((__IO uint16_t *) REG_TMR0_PWMCTL) /* PWM Control Register */ +#define pREG_TMR0_PWMMATCH ((__IO uint16_t *) REG_TMR0_PWMMATCH) /* PWM Match Value */ +#define pREG_TMR0_EVENTSELECT ((__IO uint16_t *) REG_TMR0_EVENTSELECT) /* Timer Event Selection Register */ + +/* ================================================================================= + * General Purpose Timer (TMR1) + * ================================================================================= */ +#define pREG_TMR1_LOAD ((__IO uint16_t *) REG_TMR1_LOAD) /* 16-bit Load Value */ +#define pREG_TMR1_CURCNT ((__I __C uint16_t *) REG_TMR1_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR1_CTL ((__IO uint16_t *) REG_TMR1_CTL) /* Control */ +#define pREG_TMR1_CLRINT ((__O uint16_t *) REG_TMR1_CLRINT) /* Clear Interrupt */ +#define pREG_TMR1_CAPTURE ((__I __C uint16_t *) REG_TMR1_CAPTURE) /* Capture */ +#define pREG_TMR1_ALOAD ((__IO uint16_t *) REG_TMR1_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR1_ACURCNT ((__I __C uint16_t *) REG_TMR1_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR1_STAT ((__I __C uint16_t *) REG_TMR1_STAT) /* Status */ +#define pREG_TMR1_PWMCTL ((__IO uint16_t *) REG_TMR1_PWMCTL) /* PWM Control Register */ +#define pREG_TMR1_PWMMATCH ((__IO uint16_t *) REG_TMR1_PWMMATCH) /* PWM Match Value */ +#define pREG_TMR1_EVENTSELECT ((__IO uint16_t *) REG_TMR1_EVENTSELECT) /* Timer Event Selection Register */ + +/* ================================================================================= + * General Purpose Timer (TMR2) + * ================================================================================= */ +#define pREG_TMR2_LOAD ((__IO uint16_t *) REG_TMR2_LOAD) /* 16-bit Load Value */ +#define pREG_TMR2_CURCNT ((__I __C uint16_t *) REG_TMR2_CURCNT) /* 16-bit Timer Value */ +#define pREG_TMR2_CTL ((__IO uint16_t *) REG_TMR2_CTL) /* Control */ +#define pREG_TMR2_CLRINT ((__O uint16_t *) REG_TMR2_CLRINT) /* Clear Interrupt */ +#define pREG_TMR2_CAPTURE ((__I __C uint16_t *) REG_TMR2_CAPTURE) /* Capture */ +#define pREG_TMR2_ALOAD ((__IO uint16_t *) REG_TMR2_ALOAD) /* 16-bit Load Value, Asynchronous */ +#define pREG_TMR2_ACURCNT ((__I __C uint16_t *) REG_TMR2_ACURCNT) /* 16-bit Timer Value, Asynchronous */ +#define pREG_TMR2_STAT ((__I __C uint16_t *) REG_TMR2_STAT) /* Status */ +#define pREG_TMR2_PWMCTL ((__IO uint16_t *) REG_TMR2_PWMCTL) /* PWM Control Register */ +#define pREG_TMR2_PWMMATCH ((__IO uint16_t *) REG_TMR2_PWMMATCH) /* PWM Match Value */ +#define pREG_TMR2_EVENTSELECT ((__IO uint16_t *) REG_TMR2_EVENTSELECT) /* Timer Event Selection Register */ + +/* ================================================================================= + * Timer_RGB with 3 PWM outputs (TMR_RGB) + * ================================================================================= */ +#define pREG_TMR_RGB_LOAD ((__IO uint16_t *) REG_TMR_RGB_LOAD) /* 16-bit load value */ +#define pREG_TMR_RGB_CURCNT ((__I __C uint16_t *) REG_TMR_RGB_CURCNT) /* 16-bit timer value */ +#define pREG_TMR_RGB_CTL ((__IO uint16_t *) REG_TMR_RGB_CTL) /* Control */ +#define pREG_TMR_RGB_CLRINT ((__O uint16_t *) REG_TMR_RGB_CLRINT) /* Clear interrupt */ +#define pREG_TMR_RGB_CAPTURE ((__I __C uint16_t *) REG_TMR_RGB_CAPTURE) /* Capture */ +#define pREG_TMR_RGB_ALOAD ((__IO uint16_t *) REG_TMR_RGB_ALOAD) /* 16-bit load value, asynchronous */ +#define pREG_TMR_RGB_ACURCNT ((__I __C uint16_t *) REG_TMR_RGB_ACURCNT) /* 16-bit timer value, asynchronous */ +#define pREG_TMR_RGB_STAT ((__I __C uint16_t *) REG_TMR_RGB_STAT) /* Status */ +#define pREG_TMR_RGB_PWM0CTL ((__IO uint16_t *) REG_TMR_RGB_PWM0CTL) /* PWM0 Control Register */ +#define pREG_TMR_RGB_PWM0MATCH ((__IO uint16_t *) REG_TMR_RGB_PWM0MATCH) /* PWM0 Match Value */ +#define pREG_TMR_RGB_EVENTSELECT ((__IO uint16_t *) REG_TMR_RGB_EVENTSELECT) /* Timer Event selection Register */ +#define pREG_TMR_RGB_PWM1CTL ((__IO uint16_t *) REG_TMR_RGB_PWM1CTL) /* PWM1 Control Register */ +#define pREG_TMR_RGB_PWM1MATCH ((__IO uint16_t *) REG_TMR_RGB_PWM1MATCH) /* PWM1 Match Value */ +#define pREG_TMR_RGB_PWM2CTL ((__IO uint16_t *) REG_TMR_RGB_PWM2CTL) /* PWM2 Control Register */ +#define pREG_TMR_RGB_PWM2MATCH ((__IO uint16_t *) REG_TMR_RGB_PWM2MATCH) /* PWM2 Match Value */ + +/* ================================================================================= + * Real-Time Clock (RTC0) + * ================================================================================= */ +#define pREG_RTC0_CR0 ((__IO uint16_t *) REG_RTC0_CR0) /* RTC Control 0 */ +#define pREG_RTC0_SR0 ((__IO uint16_t *) REG_RTC0_SR0) /* RTC Status 0 */ +#define pREG_RTC0_SR1 ((__I __C uint16_t *) REG_RTC0_SR1) /* RTC Status 1 */ +#define pREG_RTC0_CNT0 ((__IO uint16_t *) REG_RTC0_CNT0) /* RTC Count 0 */ +#define pREG_RTC0_CNT1 ((__IO uint16_t *) REG_RTC0_CNT1) /* RTC Count 1 */ +#define pREG_RTC0_ALM0 ((__IO uint16_t *) REG_RTC0_ALM0) /* RTC Alarm 0 */ +#define pREG_RTC0_ALM1 ((__IO uint16_t *) REG_RTC0_ALM1) /* RTC Alarm 1 */ +#define pREG_RTC0_TRM ((__IO uint16_t *) REG_RTC0_TRM) /* RTC Trim */ +#define pREG_RTC0_GWY ((__O uint16_t *) REG_RTC0_GWY) /* RTC Gateway */ +#define pREG_RTC0_CR1 ((__IO uint16_t *) REG_RTC0_CR1) /* RTC Control 1 */ +#define pREG_RTC0_SR2 ((__IO uint16_t *) REG_RTC0_SR2) /* RTC Status 2 */ +#define pREG_RTC0_SNAP0 ((__I __C uint16_t *) REG_RTC0_SNAP0) /* RTC Snapshot 0 */ +#define pREG_RTC0_SNAP1 ((__I __C uint16_t *) REG_RTC0_SNAP1) /* RTC Snapshot 1 */ +#define pREG_RTC0_SNAP2 ((__I __C uint16_t *) REG_RTC0_SNAP2) /* RTC Snapshot 2 */ +#define pREG_RTC0_MOD ((__I __C uint16_t *) REG_RTC0_MOD) /* RTC Modulo */ +#define pREG_RTC0_CNT2 ((__I __C uint16_t *) REG_RTC0_CNT2) /* RTC Count 2 */ +#define pREG_RTC0_ALM2 ((__IO uint16_t *) REG_RTC0_ALM2) /* RTC Alarm 2 */ +#define pREG_RTC0_SR3 ((__IO uint16_t *) REG_RTC0_SR3) /* RTC Status 3 */ +#define pREG_RTC0_CR2IC ((__IO uint16_t *) REG_RTC0_CR2IC) /* RTC Control 2 for Configuring Input Capture Channels */ +#define pREG_RTC0_CR3SS ((__IO uint16_t *) REG_RTC0_CR3SS) /* RTC Control 3 for Configuring SensorStrobe Channel */ +#define pREG_RTC0_CR4SS ((__IO uint16_t *) REG_RTC0_CR4SS) /* RTC Control 4 for Configuring SensorStrobe Channel */ +#define pREG_RTC0_SSMSK ((__IO uint16_t *) REG_RTC0_SSMSK) /* RTC Mask for SensorStrobe Channel */ +#define pREG_RTC0_IC2 ((__I __C uint16_t *) REG_RTC0_IC2) /* RTC Input Capture Channel 2 */ +#define pREG_RTC0_IC3 ((__I __C uint16_t *) REG_RTC0_IC3) /* RTC Input Capture Channel 3 */ +#define pREG_RTC0_IC4 ((__I __C uint16_t *) REG_RTC0_IC4) /* RTC Input Capture Channel 4 */ +#define pREG_RTC0_SS1 ((__IO uint16_t *) REG_RTC0_SS1) /* RTC SensorStrobe Channel 1 */ +#define pREG_RTC0_SS2 ((__IO uint16_t *) REG_RTC0_SS2) /* RTC SensorStrobe Channel 2 */ +#define pREG_RTC0_SS3 ((__IO uint16_t *) REG_RTC0_SS3) /* RTC SensorStrobe Channel 3 */ +#define pREG_RTC0_SS4 ((__IO uint16_t *) REG_RTC0_SS4) /* RTC SensorStrobe Channel 4 */ +#define pREG_RTC0_SR4 ((__I __C uint16_t *) REG_RTC0_SR4) /* RTC Status 4 */ +#define pREG_RTC0_SR5 ((__I __C uint16_t *) REG_RTC0_SR5) /* RTC Status 5 */ +#define pREG_RTC0_SR6 ((__I __C uint16_t *) REG_RTC0_SR6) /* RTC Status 6 */ +#define pREG_RTC0_SS1TGT ((__I __C uint16_t *) REG_RTC0_SS1TGT) /* RTC SensorStrobe Channel 1 Target */ +#define pREG_RTC0_FRZCNT ((__I __C uint16_t *) REG_RTC0_FRZCNT) /* RTC Freeze Count */ +#define pREG_RTC0_SS2TGT ((__I __C uint16_t *) REG_RTC0_SS2TGT) /* RTC SensorStrobe Channel 2 Target */ +#define pREG_RTC0_SS3TGT ((__I __C uint16_t *) REG_RTC0_SS3TGT) /* RTC SensorStrobe Channel 3 Target */ +#define pREG_RTC0_SS1LOWDUR ((__IO uint16_t *) REG_RTC0_SS1LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define pREG_RTC0_SS2LOWDUR ((__IO uint16_t *) REG_RTC0_SS2LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define pREG_RTC0_SS3LOWDUR ((__IO uint16_t *) REG_RTC0_SS3LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define pREG_RTC0_SS1HIGHDUR ((__IO uint16_t *) REG_RTC0_SS1HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define pREG_RTC0_SS2HIGHDUR ((__IO uint16_t *) REG_RTC0_SS2HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define pREG_RTC0_SS3HIGHDUR ((__IO uint16_t *) REG_RTC0_SS3HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define pREG_RTC0_SSMSKOT ((__IO uint16_t *) REG_RTC0_SSMSKOT) /* RTC Masks for SensorStrobe Channels on Time Control */ +#define pREG_RTC0_CR5SSS ((__IO uint16_t *) REG_RTC0_CR5SSS) /* RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define pREG_RTC0_CR6SSS ((__IO uint16_t *) REG_RTC0_CR6SSS) /* RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define pREG_RTC0_CR7SSS ((__IO uint16_t *) REG_RTC0_CR7SSS) /* RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define pREG_RTC0_SR7 ((__IO uint16_t *) REG_RTC0_SR7) /* RTC Status 7 */ +#define pREG_RTC0_SR8 ((__I __C uint16_t *) REG_RTC0_SR8) /* RTC Status 8 */ +#define pREG_RTC0_SR9 ((__I __C uint16_t *) REG_RTC0_SR9) /* RTC Status 9 */ +#define pREG_RTC0_GPMUX0 ((__IO uint16_t *) REG_RTC0_GPMUX0) /* RTC GPIO Pin Mux Control Register 0 */ +#define pREG_RTC0_GPMUX1 ((__IO uint16_t *) REG_RTC0_GPMUX1) /* RTC GPIO Pin Mux Control Register 1 */ + +/* ================================================================================= + * Real-Time Clock (RTC1) + * ================================================================================= */ +#define pREG_RTC1_CR0 ((__IO uint16_t *) REG_RTC1_CR0) /* RTC Control 0 */ +#define pREG_RTC1_SR0 ((__IO uint16_t *) REG_RTC1_SR0) /* RTC Status 0 */ +#define pREG_RTC1_SR1 ((__I __C uint16_t *) REG_RTC1_SR1) /* RTC Status 1 */ +#define pREG_RTC1_CNT0 ((__IO uint16_t *) REG_RTC1_CNT0) /* RTC Count 0 */ +#define pREG_RTC1_CNT1 ((__IO uint16_t *) REG_RTC1_CNT1) /* RTC Count 1 */ +#define pREG_RTC1_ALM0 ((__IO uint16_t *) REG_RTC1_ALM0) /* RTC Alarm 0 */ +#define pREG_RTC1_ALM1 ((__IO uint16_t *) REG_RTC1_ALM1) /* RTC Alarm 1 */ +#define pREG_RTC1_TRM ((__IO uint16_t *) REG_RTC1_TRM) /* RTC Trim */ +#define pREG_RTC1_GWY ((__O uint16_t *) REG_RTC1_GWY) /* RTC Gateway */ +#define pREG_RTC1_CR1 ((__IO uint16_t *) REG_RTC1_CR1) /* RTC Control 1 */ +#define pREG_RTC1_SR2 ((__IO uint16_t *) REG_RTC1_SR2) /* RTC Status 2 */ +#define pREG_RTC1_SNAP0 ((__I __C uint16_t *) REG_RTC1_SNAP0) /* RTC Snapshot 0 */ +#define pREG_RTC1_SNAP1 ((__I __C uint16_t *) REG_RTC1_SNAP1) /* RTC Snapshot 1 */ +#define pREG_RTC1_SNAP2 ((__I __C uint16_t *) REG_RTC1_SNAP2) /* RTC Snapshot 2 */ +#define pREG_RTC1_MOD ((__I __C uint16_t *) REG_RTC1_MOD) /* RTC Modulo */ +#define pREG_RTC1_CNT2 ((__I __C uint16_t *) REG_RTC1_CNT2) /* RTC Count 2 */ +#define pREG_RTC1_ALM2 ((__IO uint16_t *) REG_RTC1_ALM2) /* RTC Alarm 2 */ +#define pREG_RTC1_SR3 ((__IO uint16_t *) REG_RTC1_SR3) /* RTC Status 3 */ +#define pREG_RTC1_CR2IC ((__IO uint16_t *) REG_RTC1_CR2IC) /* RTC Control 2 for Configuring Input Capture Channels */ +#define pREG_RTC1_CR3SS ((__IO uint16_t *) REG_RTC1_CR3SS) /* RTC Control 3 for Configuring SensorStrobe Channel */ +#define pREG_RTC1_CR4SS ((__IO uint16_t *) REG_RTC1_CR4SS) /* RTC Control 4 for Configuring SensorStrobe Channel */ +#define pREG_RTC1_SSMSK ((__IO uint16_t *) REG_RTC1_SSMSK) /* RTC Mask for SensorStrobe Channel */ +#define pREG_RTC1_IC2 ((__I __C uint16_t *) REG_RTC1_IC2) /* RTC Input Capture Channel 2 */ +#define pREG_RTC1_IC3 ((__I __C uint16_t *) REG_RTC1_IC3) /* RTC Input Capture Channel 3 */ +#define pREG_RTC1_IC4 ((__I __C uint16_t *) REG_RTC1_IC4) /* RTC Input Capture Channel 4 */ +#define pREG_RTC1_SS1 ((__IO uint16_t *) REG_RTC1_SS1) /* RTC SensorStrobe Channel 1 */ +#define pREG_RTC1_SS2 ((__IO uint16_t *) REG_RTC1_SS2) /* RTC SensorStrobe Channel 2 */ +#define pREG_RTC1_SS3 ((__IO uint16_t *) REG_RTC1_SS3) /* RTC SensorStrobe Channel 3 */ +#define pREG_RTC1_SS4 ((__IO uint16_t *) REG_RTC1_SS4) /* RTC SensorStrobe Channel 4 */ +#define pREG_RTC1_SR4 ((__I __C uint16_t *) REG_RTC1_SR4) /* RTC Status 4 */ +#define pREG_RTC1_SR5 ((__I __C uint16_t *) REG_RTC1_SR5) /* RTC Status 5 */ +#define pREG_RTC1_SR6 ((__I __C uint16_t *) REG_RTC1_SR6) /* RTC Status 6 */ +#define pREG_RTC1_SS1TGT ((__I __C uint16_t *) REG_RTC1_SS1TGT) /* RTC SensorStrobe Channel 1 Target */ +#define pREG_RTC1_FRZCNT ((__I __C uint16_t *) REG_RTC1_FRZCNT) /* RTC Freeze Count */ +#define pREG_RTC1_SS2TGT ((__I __C uint16_t *) REG_RTC1_SS2TGT) /* RTC SensorStrobe Channel 2 Target */ +#define pREG_RTC1_SS3TGT ((__I __C uint16_t *) REG_RTC1_SS3TGT) /* RTC SensorStrobe Channel 3 Target */ +#define pREG_RTC1_SS1LOWDUR ((__IO uint16_t *) REG_RTC1_SS1LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ +#define pREG_RTC1_SS2LOWDUR ((__IO uint16_t *) REG_RTC1_SS2LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ +#define pREG_RTC1_SS3LOWDUR ((__IO uint16_t *) REG_RTC1_SS3LOWDUR) /* RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ +#define pREG_RTC1_SS1HIGHDUR ((__IO uint16_t *) REG_RTC1_SS1HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ +#define pREG_RTC1_SS2HIGHDUR ((__IO uint16_t *) REG_RTC1_SS2HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ +#define pREG_RTC1_SS3HIGHDUR ((__IO uint16_t *) REG_RTC1_SS3HIGHDUR) /* RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ +#define pREG_RTC1_SSMSKOT ((__IO uint16_t *) REG_RTC1_SSMSKOT) /* RTC Masks for SensorStrobe Channels on Time Control */ +#define pREG_RTC1_CR5SSS ((__IO uint16_t *) REG_RTC1_CR5SSS) /* RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ +#define pREG_RTC1_CR6SSS ((__IO uint16_t *) REG_RTC1_CR6SSS) /* RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ +#define pREG_RTC1_CR7SSS ((__IO uint16_t *) REG_RTC1_CR7SSS) /* RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ +#define pREG_RTC1_SR7 ((__IO uint16_t *) REG_RTC1_SR7) /* RTC Status 7 */ +#define pREG_RTC1_SR8 ((__I __C uint16_t *) REG_RTC1_SR8) /* RTC Status 8 */ +#define pREG_RTC1_SR9 ((__I __C uint16_t *) REG_RTC1_SR9) /* RTC Status 9 */ +#define pREG_RTC1_GPMUX0 ((__IO uint16_t *) REG_RTC1_GPMUX0) /* RTC GPIO Pin Mux Control Register 0 */ +#define pREG_RTC1_GPMUX1 ((__IO uint16_t *) REG_RTC1_GPMUX1) /* RTC GPIO Pin Mux Control Register 1 */ + +/* ================================================================================= + * System Identification and Debug Enable (SYS) + * ================================================================================= */ +#define pREG_SYS_ADIID ((__I __C uint16_t *) REG_SYS_ADIID) /* ADI Identification */ +#define pREG_SYS_CHIPID ((__I __C uint16_t *) REG_SYS_CHIPID) /* Chip Identifier */ +#define pREG_SYS_SWDEN ((__O uint16_t *) REG_SYS_SWDEN) /* Serial Wire Debug Enable */ + +/* ================================================================================= + * Watchdog Timer (WDT0) + * ================================================================================= */ +#define pREG_WDT0_LOAD ((__IO uint16_t *) REG_WDT0_LOAD) /* Load Value */ +#define pREG_WDT0_CCNT ((__I __C uint16_t *) REG_WDT0_CCNT) /* Current Count Value */ +#define pREG_WDT0_CTL ((__IO uint16_t *) REG_WDT0_CTL) /* Control */ +#define pREG_WDT0_RESTART ((__O uint16_t *) REG_WDT0_RESTART) /* Clear Interrupt */ +#define pREG_WDT0_STAT ((__I __C uint16_t *) REG_WDT0_STAT) /* Status */ + +/* ================================================================================= + * I2C Master/Slave (I2C0) + * ================================================================================= */ +#define pREG_I2C0_MCTL ((__IO uint16_t *) REG_I2C0_MCTL) /* Master Control */ +#define pREG_I2C0_MSTAT ((__IO uint16_t *) REG_I2C0_MSTAT) /* Master Status */ +#define pREG_I2C0_MRX ((__I __C uint16_t *) REG_I2C0_MRX) /* Master Receive Data */ +#define pREG_I2C0_MTX ((__IO uint16_t *) REG_I2C0_MTX) /* Master Transmit Data */ +#define pREG_I2C0_MRXCNT ((__IO uint16_t *) REG_I2C0_MRXCNT) /* Master Receive Data Count */ +#define pREG_I2C0_MCRXCNT ((__I __C uint16_t *) REG_I2C0_MCRXCNT) /* Master Current Receive Data Count */ +#define pREG_I2C0_ADDR1 ((__IO uint16_t *) REG_I2C0_ADDR1) /* Master Address Byte 1 */ +#define pREG_I2C0_ADDR2 ((__IO uint16_t *) REG_I2C0_ADDR2) /* Master Address Byte 2 */ +#define pREG_I2C0_BYT ((__IO uint16_t *) REG_I2C0_BYT) /* Start Byte */ +#define pREG_I2C0_DIV ((__IO uint16_t *) REG_I2C0_DIV) /* Serial Clock Period Divisor */ +#define pREG_I2C0_SCTL ((__IO uint16_t *) REG_I2C0_SCTL) /* Slave Control */ +#define pREG_I2C0_SSTAT ((__IO uint16_t *) REG_I2C0_SSTAT) /* Slave I2C Status/Error/IRQ */ +#define pREG_I2C0_SRX ((__I __C uint16_t *) REG_I2C0_SRX) /* Slave Receive */ +#define pREG_I2C0_STX ((__IO uint16_t *) REG_I2C0_STX) /* Slave Transmit */ +#define pREG_I2C0_ALT ((__IO uint16_t *) REG_I2C0_ALT) /* Hardware General Call ID */ +#define pREG_I2C0_ID0 ((__IO uint16_t *) REG_I2C0_ID0) /* First Slave Address Device ID */ +#define pREG_I2C0_ID1 ((__IO uint16_t *) REG_I2C0_ID1) /* Second Slave Address Device ID */ +#define pREG_I2C0_ID2 ((__IO uint16_t *) REG_I2C0_ID2) /* Third Slave Address Device ID */ +#define pREG_I2C0_ID3 ((__IO uint16_t *) REG_I2C0_ID3) /* Fourth Slave Address Device ID */ +#define pREG_I2C0_STAT ((__IO uint16_t *) REG_I2C0_STAT) /* Master and Slave FIFO Status */ +#define pREG_I2C0_SHCTL ((__O uint16_t *) REG_I2C0_SHCTL) /* Shared Control */ +#define pREG_I2C0_TCTL ((__IO uint16_t *) REG_I2C0_TCTL) /* Timing Control Register */ +#define pREG_I2C0_ASTRETCH_SCL ((__IO uint16_t *) REG_I2C0_ASTRETCH_SCL) /* Automatic Stretch SCL */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI0) + * ================================================================================= */ +#define pREG_SPI0_STAT ((__IO uint16_t *) REG_SPI0_STAT) /* Status */ +#define pREG_SPI0_RX ((__I __C uint16_t *) REG_SPI0_RX) /* Receive */ +#define pREG_SPI0_TX ((__O uint16_t *) REG_SPI0_TX) /* Transmit */ +#define pREG_SPI0_DIV ((__IO uint16_t *) REG_SPI0_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI0_CTL ((__IO uint16_t *) REG_SPI0_CTL) /* SPI Configuration */ +#define pREG_SPI0_IEN ((__IO uint16_t *) REG_SPI0_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI0_CNT ((__IO uint16_t *) REG_SPI0_CNT) /* Transfer Byte Count */ +#define pREG_SPI0_DMA ((__IO uint16_t *) REG_SPI0_DMA) /* SPI DMA Enable */ +#define pREG_SPI0_FIFO_STAT ((__I __C uint16_t *) REG_SPI0_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI0_RD_CTL ((__IO uint16_t *) REG_SPI0_RD_CTL) /* Read Control */ +#define pREG_SPI0_FLOW_CTL ((__IO uint16_t *) REG_SPI0_FLOW_CTL) /* Flow Control */ +#define pREG_SPI0_WAIT_TMR ((__IO uint16_t *) REG_SPI0_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI0_CS_CTL ((__IO uint16_t *) REG_SPI0_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI0_CS_OVERRIDE ((__IO uint16_t *) REG_SPI0_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI1) + * ================================================================================= */ +#define pREG_SPI1_STAT ((__IO uint16_t *) REG_SPI1_STAT) /* Status */ +#define pREG_SPI1_RX ((__I __C uint16_t *) REG_SPI1_RX) /* Receive */ +#define pREG_SPI1_TX ((__O uint16_t *) REG_SPI1_TX) /* Transmit */ +#define pREG_SPI1_DIV ((__IO uint16_t *) REG_SPI1_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI1_CTL ((__IO uint16_t *) REG_SPI1_CTL) /* SPI Configuration */ +#define pREG_SPI1_IEN ((__IO uint16_t *) REG_SPI1_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI1_CNT ((__IO uint16_t *) REG_SPI1_CNT) /* Transfer Byte Count */ +#define pREG_SPI1_DMA ((__IO uint16_t *) REG_SPI1_DMA) /* SPI DMA Enable */ +#define pREG_SPI1_FIFO_STAT ((__I __C uint16_t *) REG_SPI1_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI1_RD_CTL ((__IO uint16_t *) REG_SPI1_RD_CTL) /* Read Control */ +#define pREG_SPI1_FLOW_CTL ((__IO uint16_t *) REG_SPI1_FLOW_CTL) /* Flow Control */ +#define pREG_SPI1_WAIT_TMR ((__IO uint16_t *) REG_SPI1_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI1_CS_CTL ((__IO uint16_t *) REG_SPI1_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI1_CS_OVERRIDE ((__IO uint16_t *) REG_SPI1_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * Serial Peripheral Interface (SPI2) + * ================================================================================= */ +#define pREG_SPI2_STAT ((__IO uint16_t *) REG_SPI2_STAT) /* Status */ +#define pREG_SPI2_RX ((__I __C uint16_t *) REG_SPI2_RX) /* Receive */ +#define pREG_SPI2_TX ((__O uint16_t *) REG_SPI2_TX) /* Transmit */ +#define pREG_SPI2_DIV ((__IO uint16_t *) REG_SPI2_DIV) /* SPI Baud Rate Selection */ +#define pREG_SPI2_CTL ((__IO uint16_t *) REG_SPI2_CTL) /* SPI Configuration */ +#define pREG_SPI2_IEN ((__IO uint16_t *) REG_SPI2_IEN) /* SPI Interrupts Enable */ +#define pREG_SPI2_CNT ((__IO uint16_t *) REG_SPI2_CNT) /* Transfer Byte Count */ +#define pREG_SPI2_DMA ((__IO uint16_t *) REG_SPI2_DMA) /* SPI DMA Enable */ +#define pREG_SPI2_FIFO_STAT ((__I __C uint16_t *) REG_SPI2_FIFO_STAT) /* FIFO Status */ +#define pREG_SPI2_RD_CTL ((__IO uint16_t *) REG_SPI2_RD_CTL) /* Read Control */ +#define pREG_SPI2_FLOW_CTL ((__IO uint16_t *) REG_SPI2_FLOW_CTL) /* Flow Control */ +#define pREG_SPI2_WAIT_TMR ((__IO uint16_t *) REG_SPI2_WAIT_TMR) /* Wait Timer for Flow Control */ +#define pREG_SPI2_CS_CTL ((__IO uint16_t *) REG_SPI2_CS_CTL) /* Chip Select Control for Multi-slave Connections */ +#define pREG_SPI2_CS_OVERRIDE ((__IO uint16_t *) REG_SPI2_CS_OVERRIDE) /* Chip Select Override */ + +/* ================================================================================= + * (UART0) + * ================================================================================= */ +#define pREG_UART0_TX ((__O uint16_t *) REG_UART0_TX) /* Transmit Holding Register */ +#define pREG_UART0_RX ((__I __C uint16_t *) REG_UART0_RX) /* Receive Buffer Register */ +#define pREG_UART0_IEN ((__IO uint16_t *) REG_UART0_IEN) /* Interrupt Enable */ +#define pREG_UART0_IIR ((__I __C uint16_t *) REG_UART0_IIR) /* Interrupt ID */ +#define pREG_UART0_LCR ((__IO uint16_t *) REG_UART0_LCR) /* Line Control */ +#define pREG_UART0_MCR ((__IO uint16_t *) REG_UART0_MCR) /* Modem Control */ +#define pREG_UART0_LSR ((__I __C uint16_t *) REG_UART0_LSR) /* Line Status */ +#define pREG_UART0_MSR ((__I __C uint16_t *) REG_UART0_MSR) /* Modem Status */ +#define pREG_UART0_SCR ((__IO uint16_t *) REG_UART0_SCR) /* Scratch Buffer */ +#define pREG_UART0_FCR ((__IO uint16_t *) REG_UART0_FCR) /* FIFO Control */ +#define pREG_UART0_FBR ((__IO uint16_t *) REG_UART0_FBR) /* Fractional Baud Rate */ +#define pREG_UART0_DIV ((__IO uint16_t *) REG_UART0_DIV) /* Baud Rate Divider */ +#define pREG_UART0_LCR2 ((__IO uint16_t *) REG_UART0_LCR2) /* Second Line Control */ +#define pREG_UART0_CTL ((__IO uint16_t *) REG_UART0_CTL) /* UART Control Register */ +#define pREG_UART0_RFC ((__I __C uint16_t *) REG_UART0_RFC) /* RX FIFO Byte Count */ +#define pREG_UART0_TFC ((__I __C uint16_t *) REG_UART0_TFC) /* TX FIFO Byte Count */ +#define pREG_UART0_RSC ((__IO uint16_t *) REG_UART0_RSC) /* RS485 Half-duplex Control */ +#define pREG_UART0_ACR ((__IO uint16_t *) REG_UART0_ACR) /* Auto Baud Control */ +#define pREG_UART0_ASRL ((__I __C uint16_t *) REG_UART0_ASRL) /* Auto Baud Status (Low) */ +#define pREG_UART0_ASRH ((__I __C uint16_t *) REG_UART0_ASRH) /* Auto Baud Status (High) */ + +/* ================================================================================= + * (UART1) + * ================================================================================= */ +#define pREG_UART1_RX ((__I __C uint16_t *) REG_UART1_RX) /* Receive Buffer Register */ +#define pREG_UART1_TX ((__O uint16_t *) REG_UART1_TX) /* Transmit Holding Register */ +#define pREG_UART1_IEN ((__IO uint16_t *) REG_UART1_IEN) /* Interrupt Enable */ +#define pREG_UART1_IIR ((__I __C uint16_t *) REG_UART1_IIR) /* Interrupt ID */ +#define pREG_UART1_LCR ((__IO uint16_t *) REG_UART1_LCR) /* Line Control */ +#define pREG_UART1_MCR ((__IO uint16_t *) REG_UART1_MCR) /* Modem Control */ +#define pREG_UART1_LSR ((__I __C uint16_t *) REG_UART1_LSR) /* Line Status */ +#define pREG_UART1_MSR ((__I __C uint16_t *) REG_UART1_MSR) /* Modem Status */ +#define pREG_UART1_SCR ((__IO uint16_t *) REG_UART1_SCR) /* Scratch Buffer */ +#define pREG_UART1_FCR ((__IO uint16_t *) REG_UART1_FCR) /* FIFO Control */ +#define pREG_UART1_FBR ((__IO uint16_t *) REG_UART1_FBR) /* Fractional Baud Rate */ +#define pREG_UART1_DIV ((__IO uint16_t *) REG_UART1_DIV) /* Baud Rate Divider */ +#define pREG_UART1_LCR2 ((__IO uint16_t *) REG_UART1_LCR2) /* Second Line Control */ +#define pREG_UART1_CTL ((__IO uint16_t *) REG_UART1_CTL) /* UART Control Register */ +#define pREG_UART1_RFC ((__I __C uint16_t *) REG_UART1_RFC) /* RX FIFO Byte Count */ +#define pREG_UART1_TFC ((__I __C uint16_t *) REG_UART1_TFC) /* TX FIFO Byte Count */ +#define pREG_UART1_RSC ((__IO uint16_t *) REG_UART1_RSC) /* RS485 Half-duplex Control */ +#define pREG_UART1_ACR ((__IO uint16_t *) REG_UART1_ACR) /* Auto Baud Control */ +#define pREG_UART1_ASRL ((__I __C uint16_t *) REG_UART1_ASRL) /* Auto Baud Status (Low) */ +#define pREG_UART1_ASRH ((__I __C uint16_t *) REG_UART1_ASRH) /* Auto Baud Status (High) */ + +/* ================================================================================= + * Beeper Driver (BEEP0) + * ================================================================================= */ +#define pREG_BEEP0_CFG ((__IO uint16_t *) REG_BEEP0_CFG) /* Beeper Configuration */ +#define pREG_BEEP0_STAT ((__IO uint16_t *) REG_BEEP0_STAT) /* Beeper Status */ +#define pREG_BEEP0_TONEA ((__IO uint16_t *) REG_BEEP0_TONEA) /* Tone A Data */ +#define pREG_BEEP0_TONEB ((__IO uint16_t *) REG_BEEP0_TONEB) /* Tone B Data */ + +/* ================================================================================= + * (ADC0) + * ================================================================================= */ +#define pREG_ADC0_CFG ((__IO uint16_t *) REG_ADC0_CFG) /* ADC Configuration */ +#define pREG_ADC0_PWRUP ((__IO uint16_t *) REG_ADC0_PWRUP) /* ADC Power-up Time */ +#define pREG_ADC0_CAL_WORD ((__IO uint16_t *) REG_ADC0_CAL_WORD) /* Calibration Word */ +#define pREG_ADC0_CNV_CFG ((__IO uint16_t *) REG_ADC0_CNV_CFG) /* ADC Conversion Configuration */ +#define pREG_ADC0_CNV_TIME ((__IO uint16_t *) REG_ADC0_CNV_TIME) /* ADC Conversion Time */ +#define pREG_ADC0_AVG_CFG ((__IO uint16_t *) REG_ADC0_AVG_CFG) /* Averaging Configuration */ +#define pREG_ADC0_IRQ_EN ((__IO uint16_t *) REG_ADC0_IRQ_EN) /* Interrupt Enable */ +#define pREG_ADC0_STAT ((__IO uint16_t *) REG_ADC0_STAT) /* ADC Status */ +#define pREG_ADC0_OVF ((__IO uint16_t *) REG_ADC0_OVF) /* Overflow of Output Registers */ +#define pREG_ADC0_ALERT ((__IO uint16_t *) REG_ADC0_ALERT) /* Alert Indication */ +#define pREG_ADC0_CH0_OUT ((__I __C uint16_t *) REG_ADC0_CH0_OUT) /* Conversion Result Channel 0 */ +#define pREG_ADC0_CH1_OUT ((__I __C uint16_t *) REG_ADC0_CH1_OUT) /* Conversion Result Channel 1 */ +#define pREG_ADC0_CH2_OUT ((__I __C uint16_t *) REG_ADC0_CH2_OUT) /* Conversion Result Channel 2 */ +#define pREG_ADC0_CH3_OUT ((__I __C uint16_t *) REG_ADC0_CH3_OUT) /* Conversion Result Channel 3 */ +#define pREG_ADC0_CH4_OUT ((__I __C uint16_t *) REG_ADC0_CH4_OUT) /* Conversion Result Channel 4 */ +#define pREG_ADC0_CH5_OUT ((__I __C uint16_t *) REG_ADC0_CH5_OUT) /* Conversion Result Channel 5 */ +#define pREG_ADC0_CH6_OUT ((__I __C uint16_t *) REG_ADC0_CH6_OUT) /* Conversion Result Channel 6 */ +#define pREG_ADC0_CH7_OUT ((__I __C uint16_t *) REG_ADC0_CH7_OUT) /* Conversion Result Channel 7 */ +#define pREG_ADC0_BAT_OUT ((__I __C uint16_t *) REG_ADC0_BAT_OUT) /* Battery Monitoring Result */ +#define pREG_ADC0_TMP_OUT ((__I __C uint16_t *) REG_ADC0_TMP_OUT) /* Temperature Result */ +#define pREG_ADC0_TMP2_OUT ((__I __C uint16_t *) REG_ADC0_TMP2_OUT) /* Temperature Result 2 */ +#define pREG_ADC0_DMA_OUT ((__I __C uint16_t *) REG_ADC0_DMA_OUT) /* DMA Output Register */ +#define pREG_ADC0_LIM0_LO ((__IO uint16_t *) REG_ADC0_LIM0_LO) /* Channel 0 Low Limit */ +#define pREG_ADC0_LIM0_HI ((__IO uint16_t *) REG_ADC0_LIM0_HI) /* Channel 0 High Limit */ +#define pREG_ADC0_HYS0 ((__IO uint16_t *) REG_ADC0_HYS0) /* Channel 0 Hysteresis */ +#define pREG_ADC0_LIM1_LO ((__IO uint16_t *) REG_ADC0_LIM1_LO) /* Channel 1 Low Limit */ +#define pREG_ADC0_LIM1_HI ((__IO uint16_t *) REG_ADC0_LIM1_HI) /* Channel 1 High Limit */ +#define pREG_ADC0_HYS1 ((__IO uint16_t *) REG_ADC0_HYS1) /* Channel 1 Hysteresis */ +#define pREG_ADC0_LIM2_LO ((__IO uint16_t *) REG_ADC0_LIM2_LO) /* Channel 2 Low Limit */ +#define pREG_ADC0_LIM2_HI ((__IO uint16_t *) REG_ADC0_LIM2_HI) /* Channel 2 High Limit */ +#define pREG_ADC0_HYS2 ((__IO uint16_t *) REG_ADC0_HYS2) /* Channel 2 Hysteresis */ +#define pREG_ADC0_LIM3_LO ((__IO uint16_t *) REG_ADC0_LIM3_LO) /* Channel 3 Low Limit */ +#define pREG_ADC0_LIM3_HI ((__IO uint16_t *) REG_ADC0_LIM3_HI) /* Channel 3 High Limit */ +#define pREG_ADC0_HYS3 ((__IO uint16_t *) REG_ADC0_HYS3) /* Channel 3 Hysteresis */ +#define pREG_ADC0_CFG1 ((__IO uint16_t *) REG_ADC0_CFG1) /* Reference Buffer Low Power Mode */ + +/* ================================================================================= + * DMA (DMA0) + * ================================================================================= */ +#define pREG_DMA0_STAT ((__I __C uint32_t *) REG_DMA0_STAT) /* DMA Status */ +#define pREG_DMA0_CFG ((__O uint32_t *) REG_DMA0_CFG) /* DMA Configuration */ +#define pREG_DMA0_PDBPTR ((__IO uint32_t *) REG_DMA0_PDBPTR) /* DMA Channel Primary Control Database Pointer */ +#define pREG_DMA0_ADBPTR ((__I __C uint32_t *) REG_DMA0_ADBPTR) /* DMA Channel Alternate Control Database Pointer */ +#define pREG_DMA0_SWREQ ((__O uint32_t *) REG_DMA0_SWREQ) /* DMA Channel Software Request */ +#define pREG_DMA0_RMSK_SET ((__IO uint32_t *) REG_DMA0_RMSK_SET) /* DMA Channel Request Mask Set */ +#define pREG_DMA0_RMSK_CLR ((__O uint32_t *) REG_DMA0_RMSK_CLR) /* DMA Channel Request Mask Clear */ +#define pREG_DMA0_EN_SET ((__IO uint32_t *) REG_DMA0_EN_SET) /* DMA Channel Enable Set */ +#define pREG_DMA0_EN_CLR ((__O uint32_t *) REG_DMA0_EN_CLR) /* DMA Channel Enable Clear */ +#define pREG_DMA0_ALT_SET ((__IO uint32_t *) REG_DMA0_ALT_SET) /* DMA Channel Primary Alternate Set */ +#define pREG_DMA0_ALT_CLR ((__O uint32_t *) REG_DMA0_ALT_CLR) /* DMA Channel Primary Alternate Clear */ +#define pREG_DMA0_PRI_SET ((__O uint32_t *) REG_DMA0_PRI_SET) /* DMA Channel Priority Set */ +#define pREG_DMA0_PRI_CLR ((__O uint32_t *) REG_DMA0_PRI_CLR) /* DMA Channel Priority Clear */ +#define pREG_DMA0_ERRCHNL_CLR ((__IO uint32_t *) REG_DMA0_ERRCHNL_CLR) /* DMA per Channel Error Clear */ +#define pREG_DMA0_ERR_CLR ((__IO uint32_t *) REG_DMA0_ERR_CLR) /* DMA Bus Error Clear */ +#define pREG_DMA0_INVALIDDESC_CLR ((__IO uint32_t *) REG_DMA0_INVALIDDESC_CLR) /* DMA per Channel Invalid Descriptor Clear */ +#define pREG_DMA0_BS_SET ((__IO uint32_t *) REG_DMA0_BS_SET) /* DMA Channel Bytes Swap Enable Set */ +#define pREG_DMA0_BS_CLR ((__O uint32_t *) REG_DMA0_BS_CLR) /* DMA Channel Bytes Swap Enable Clear */ +#define pREG_DMA0_SRCADDR_SET ((__IO uint32_t *) REG_DMA0_SRCADDR_SET) /* DMA Channel Source Address Decrement Enable Set */ +#define pREG_DMA0_SRCADDR_CLR ((__O uint32_t *) REG_DMA0_SRCADDR_CLR) /* DMA Channel Source Address Decrement Enable Clear */ +#define pREG_DMA0_DSTADDR_SET ((__IO uint32_t *) REG_DMA0_DSTADDR_SET) /* DMA Channel Destination Address Decrement Enable Set */ +#define pREG_DMA0_DSTADDR_CLR ((__O uint32_t *) REG_DMA0_DSTADDR_CLR) /* DMA Channel Destination Address Decrement Enable Clear */ +#define pREG_DMA0_REVID ((__I __C uint32_t *) REG_DMA0_REVID) /* DMA Controller Revision ID */ + +/* ================================================================================= + * Flash Controller (FLCC0) + * ================================================================================= */ +#define pREG_FLCC0_STAT ((__IO uint32_t *) REG_FLCC0_STAT) /* Status */ +#define pREG_FLCC0_IEN ((__IO uint32_t *) REG_FLCC0_IEN) /* Interrupt Enable */ +#define pREG_FLCC0_CMD ((__IO uint32_t *) REG_FLCC0_CMD) /* Command */ +#define pREG_FLCC0_KH_ADDR ((__IO uint32_t *) REG_FLCC0_KH_ADDR) /* Write Address */ +#define pREG_FLCC0_KH_DATA0 ((__IO uint32_t *) REG_FLCC0_KH_DATA0) /* Write Lower Data */ +#define pREG_FLCC0_KH_DATA1 ((__IO uint32_t *) REG_FLCC0_KH_DATA1) /* Write Upper Data */ +#define pREG_FLCC0_PAGE_ADDR0 ((__IO uint32_t *) REG_FLCC0_PAGE_ADDR0) /* Lower Page Address */ +#define pREG_FLCC0_PAGE_ADDR1 ((__IO uint32_t *) REG_FLCC0_PAGE_ADDR1) /* Upper Page Address */ +#define pREG_FLCC0_KEY ((__O uint32_t *) REG_FLCC0_KEY) /* Key */ +#define pREG_FLCC0_WR_ABORT_ADDR ((__I __C uint32_t *) REG_FLCC0_WR_ABORT_ADDR) /* Write Abort Address */ +#define pREG_FLCC0_WRPROT ((__IO uint32_t *) REG_FLCC0_WRPROT) /* Write Protection */ +#define pREG_FLCC0_SIGNATURE ((__I __C uint32_t *) REG_FLCC0_SIGNATURE) /* Signature */ +#define pREG_FLCC0_UCFG ((__IO uint32_t *) REG_FLCC0_UCFG) /* User Configuration */ +#define pREG_FLCC0_TIME_PARAM0 ((__IO uint32_t *) REG_FLCC0_TIME_PARAM0) /* Time Parameter 0 */ +#define pREG_FLCC0_TIME_PARAM1 ((__IO uint32_t *) REG_FLCC0_TIME_PARAM1) /* Time Parameter 1 */ +#define pREG_FLCC0_ABORT_EN_LO ((__IO uint32_t *) REG_FLCC0_ABORT_EN_LO) /* IRQ Abort Enable (Lower Bits) */ +#define pREG_FLCC0_ABORT_EN_HI ((__IO uint32_t *) REG_FLCC0_ABORT_EN_HI) /* IRQ Abort Enable (Upper Bits) */ +#define pREG_FLCC0_ECC_CFG ((__IO uint32_t *) REG_FLCC0_ECC_CFG) /* ECC Configuration */ +#define pREG_FLCC0_ECC_ADDR ((__I __C uint32_t *) REG_FLCC0_ECC_ADDR) /* ECC Status (Address) */ +#define pREG_FLCC0_POR_SEC ((__IO uint32_t *) REG_FLCC0_POR_SEC) /* Flash Security */ +#define pREG_FLCC0_VOL_CFG ((__IO uint32_t *) REG_FLCC0_VOL_CFG) /* Volatile Flash Configuration */ + +/* ================================================================================= + * Cache Controller (FLCC0_CACHE) + * ================================================================================= */ +#define pREG_FLCC0_CACHE_STAT ((__I __C uint32_t *) REG_FLCC0_CACHE_STAT) /* Cache Status Register */ +#define pREG_FLCC0_CACHE_SETUP ((__IO uint32_t *) REG_FLCC0_CACHE_SETUP) /* Cache Setup Register */ +#define pREG_FLCC0_CACHE_KEY ((__O uint32_t *) REG_FLCC0_CACHE_KEY) /* Cache Key Register */ + +/* ================================================================================= + * (GPIO0) + * ================================================================================= */ +#define pREG_GPIO0_CFG ((__IO uint32_t *) REG_GPIO0_CFG) /* Port Configuration */ +#define pREG_GPIO0_OEN ((__IO uint16_t *) REG_GPIO0_OEN) /* Port Output Enable */ +#define pREG_GPIO0_PE ((__IO uint16_t *) REG_GPIO0_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO0_IEN ((__IO uint16_t *) REG_GPIO0_IEN) /* Port Input Path Enable */ +#define pREG_GPIO0_IN ((__I __C uint16_t *) REG_GPIO0_IN) /* Port Registered Data Input */ +#define pREG_GPIO0_OUT ((__IO uint16_t *) REG_GPIO0_OUT) /* Port Data Output */ +#define pREG_GPIO0_SET ((__O uint16_t *) REG_GPIO0_SET) /* Port Data Out Set */ +#define pREG_GPIO0_CLR ((__O uint16_t *) REG_GPIO0_CLR) /* Port Data Out Clear */ +#define pREG_GPIO0_TGL ((__O uint16_t *) REG_GPIO0_TGL) /* Port Pin Toggle */ +#define pREG_GPIO0_POL ((__IO uint16_t *) REG_GPIO0_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO0_IENA ((__IO uint16_t *) REG_GPIO0_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO0_IENB ((__IO uint16_t *) REG_GPIO0_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO0_INT ((__IO uint16_t *) REG_GPIO0_INT) /* Port Interrupt Status */ +#define pREG_GPIO0_DS ((__IO uint16_t *) REG_GPIO0_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO1) + * ================================================================================= */ +#define pREG_GPIO1_CFG ((__IO uint32_t *) REG_GPIO1_CFG) /* Port Configuration */ +#define pREG_GPIO1_OEN ((__IO uint16_t *) REG_GPIO1_OEN) /* Port Output Enable */ +#define pREG_GPIO1_PE ((__IO uint16_t *) REG_GPIO1_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO1_IEN ((__IO uint16_t *) REG_GPIO1_IEN) /* Port Input Path Enable */ +#define pREG_GPIO1_IN ((__I __C uint16_t *) REG_GPIO1_IN) /* Port Registered Data Input */ +#define pREG_GPIO1_OUT ((__IO uint16_t *) REG_GPIO1_OUT) /* Port Data Output */ +#define pREG_GPIO1_SET ((__O uint16_t *) REG_GPIO1_SET) /* Port Data Out Set */ +#define pREG_GPIO1_CLR ((__O uint16_t *) REG_GPIO1_CLR) /* Port Data Out Clear */ +#define pREG_GPIO1_TGL ((__O uint16_t *) REG_GPIO1_TGL) /* Port Pin Toggle */ +#define pREG_GPIO1_POL ((__IO uint16_t *) REG_GPIO1_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO1_IENA ((__IO uint16_t *) REG_GPIO1_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO1_IENB ((__IO uint16_t *) REG_GPIO1_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO1_INT ((__IO uint16_t *) REG_GPIO1_INT) /* Port Interrupt Status */ +#define pREG_GPIO1_DS ((__IO uint16_t *) REG_GPIO1_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO2) + * ================================================================================= */ +#define pREG_GPIO2_CFG ((__IO uint32_t *) REG_GPIO2_CFG) /* Port Configuration */ +#define pREG_GPIO2_OEN ((__IO uint16_t *) REG_GPIO2_OEN) /* Port Output Enable */ +#define pREG_GPIO2_PE ((__IO uint16_t *) REG_GPIO2_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO2_IEN ((__IO uint16_t *) REG_GPIO2_IEN) /* Port Input Path Enable */ +#define pREG_GPIO2_IN ((__I __C uint16_t *) REG_GPIO2_IN) /* Port Registered Data Input */ +#define pREG_GPIO2_OUT ((__IO uint16_t *) REG_GPIO2_OUT) /* Port Data Output */ +#define pREG_GPIO2_SET ((__O uint16_t *) REG_GPIO2_SET) /* Port Data Out Set */ +#define pREG_GPIO2_CLR ((__O uint16_t *) REG_GPIO2_CLR) /* Port Data Out Clear */ +#define pREG_GPIO2_TGL ((__O uint16_t *) REG_GPIO2_TGL) /* Port Pin Toggle */ +#define pREG_GPIO2_POL ((__IO uint16_t *) REG_GPIO2_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO2_IENA ((__IO uint16_t *) REG_GPIO2_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO2_IENB ((__IO uint16_t *) REG_GPIO2_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO2_INT ((__IO uint16_t *) REG_GPIO2_INT) /* Port Interrupt Status */ +#define pREG_GPIO2_DS ((__IO uint16_t *) REG_GPIO2_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * (GPIO3) + * ================================================================================= */ +#define pREG_GPIO3_CFG ((__IO uint32_t *) REG_GPIO3_CFG) /* Port Configuration */ +#define pREG_GPIO3_OEN ((__IO uint16_t *) REG_GPIO3_OEN) /* Port Output Enable */ +#define pREG_GPIO3_PE ((__IO uint16_t *) REG_GPIO3_PE) /* Port Output Pull-up/Pull-down Enable */ +#define pREG_GPIO3_IEN ((__IO uint16_t *) REG_GPIO3_IEN) /* Port Input Path Enable */ +#define pREG_GPIO3_IN ((__I __C uint16_t *) REG_GPIO3_IN) /* Port Registered Data Input */ +#define pREG_GPIO3_OUT ((__IO uint16_t *) REG_GPIO3_OUT) /* Port Data Output */ +#define pREG_GPIO3_SET ((__O uint16_t *) REG_GPIO3_SET) /* Port Data Out Set */ +#define pREG_GPIO3_CLR ((__O uint16_t *) REG_GPIO3_CLR) /* Port Data Out Clear */ +#define pREG_GPIO3_TGL ((__O uint16_t *) REG_GPIO3_TGL) /* Port Pin Toggle */ +#define pREG_GPIO3_POL ((__IO uint16_t *) REG_GPIO3_POL) /* Port Interrupt Polarity */ +#define pREG_GPIO3_IENA ((__IO uint16_t *) REG_GPIO3_IENA) /* Port Interrupt A Enable */ +#define pREG_GPIO3_IENB ((__IO uint16_t *) REG_GPIO3_IENB) /* Port Interrupt B Enable */ +#define pREG_GPIO3_INT ((__IO uint16_t *) REG_GPIO3_INT) /* Port Interrupt Status */ +#define pREG_GPIO3_DS ((__IO uint16_t *) REG_GPIO3_DS) /* Port Drive Strength Select */ + +/* ================================================================================= + * Serial Port (SPORT0) + * ================================================================================= */ +#define pREG_SPORT0_CTL_A ((__IO uint32_t *) REG_SPORT0_CTL_A) /* Half SPORT 'A' Control Register */ +#define pREG_SPORT0_DIV_A ((__IO uint32_t *) REG_SPORT0_DIV_A) /* Half SPORT 'A' Divisor Register */ +#define pREG_SPORT0_IEN_A ((__IO uint32_t *) REG_SPORT0_IEN_A) /* Half SPORT A's Interrupt Enable register */ +#define pREG_SPORT0_STAT_A ((__IO uint32_t *) REG_SPORT0_STAT_A) /* Half SPORT 'A' Status register */ +#define pREG_SPORT0_NUMTRAN_A ((__IO uint32_t *) REG_SPORT0_NUMTRAN_A) /* Half SPORT A Number of transfers register */ +#define pREG_SPORT0_CNVT_A ((__IO uint32_t *) REG_SPORT0_CNVT_A) /* Half SPORT 'A' CNV width */ +#define pREG_SPORT0_TX_A ((__O uint32_t *) REG_SPORT0_TX_A) /* Half SPORT 'A' Tx Buffer Register */ +#define pREG_SPORT0_RX_A ((__I __C uint32_t *) REG_SPORT0_RX_A) /* Half SPORT 'A' Rx Buffer Register */ +#define pREG_SPORT0_CTL_B ((__IO uint32_t *) REG_SPORT0_CTL_B) /* Half SPORT 'B' Control Register */ +#define pREG_SPORT0_DIV_B ((__IO uint32_t *) REG_SPORT0_DIV_B) /* Half SPORT 'B' Divisor Register */ +#define pREG_SPORT0_IEN_B ((__IO uint32_t *) REG_SPORT0_IEN_B) /* Half SPORT B's Interrupt Enable register */ +#define pREG_SPORT0_STAT_B ((__IO uint32_t *) REG_SPORT0_STAT_B) /* Half SPORT 'B' Status register */ +#define pREG_SPORT0_NUMTRAN_B ((__IO uint32_t *) REG_SPORT0_NUMTRAN_B) /* Half SPORT B Number of transfers register */ +#define pREG_SPORT0_CNVT_B ((__IO uint32_t *) REG_SPORT0_CNVT_B) /* Half SPORT 'B' CNV width register */ +#define pREG_SPORT0_TX_B ((__O uint32_t *) REG_SPORT0_TX_B) /* Half SPORT 'B' Tx Buffer Register */ +#define pREG_SPORT0_RX_B ((__I __C uint32_t *) REG_SPORT0_RX_B) /* Half SPORT 'B' Rx Buffer Register */ + +/* ================================================================================= + * CRC Accelerator (CRC0) + * ================================================================================= */ +#define pREG_CRC0_CTL ((__IO uint32_t *) REG_CRC0_CTL) /* CRC Control */ +#define pREG_CRC0_IPDATA ((__O uint32_t *) REG_CRC0_IPDATA) /* Input Data Word */ +#define pREG_CRC0_RESULT ((__IO uint32_t *) REG_CRC0_RESULT) /* CRC Result */ +#define pREG_CRC0_POLY ((__IO uint32_t *) REG_CRC0_POLY) /* Programmable CRC Polynomial */ +#define pREG_CRC0_IPBYTE ((__O uint8_t *) REG_CRC0_IPBYTE) /* Input Data Byte */ +#define pREG_CRC0_IPBITS0 ((__O uint8_t *) REG_CRC0_IPBITS0) /* Input Data Bits */ +#define pREG_CRC0_IPBITS1 ((__O uint8_t *) REG_CRC0_IPBITS1) /* Input Data Bits */ +#define pREG_CRC0_IPBITS2 ((__O uint8_t *) REG_CRC0_IPBITS2) /* Input Data Bits */ +#define pREG_CRC0_IPBITS3 ((__O uint8_t *) REG_CRC0_IPBITS3) /* Input Data Bits */ +#define pREG_CRC0_IPBITS4 ((__O uint8_t *) REG_CRC0_IPBITS4) /* Input Data Bits */ +#define pREG_CRC0_IPBITS5 ((__O uint8_t *) REG_CRC0_IPBITS5) /* Input Data Bits */ +#define pREG_CRC0_IPBITS6 ((__O uint8_t *) REG_CRC0_IPBITS6) /* Input Data Bits */ +#define pREG_CRC0_IPBITS7 ((__O uint8_t *) REG_CRC0_IPBITS7) /* Input Data Bits */ + +/* ================================================================================= + * Random Number Generator (RNG0) + * ================================================================================= */ +#define pREG_RNG0_CTL ((__IO uint16_t *) REG_RNG0_CTL) /* RNG Control Register */ +#define pREG_RNG0_LEN ((__IO uint16_t *) REG_RNG0_LEN) /* RNG Sample Length Register */ +#define pREG_RNG0_STAT ((__IO uint16_t *) REG_RNG0_STAT) /* RNG Status Register */ +#define pREG_RNG0_DATA ((__I __C uint32_t *) REG_RNG0_DATA) /* RNG Data Register */ +#define pREG_RNG0_OSCCNT ((__I __C uint32_t *) REG_RNG0_OSCCNT) /* Oscillator Count */ +#define pREG_RNG0_OSCDIFF0 ((__I __C int8_t *) REG_RNG0_OSCDIFF0) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF1 ((__I __C int8_t *) REG_RNG0_OSCDIFF1) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF2 ((__I __C int8_t *) REG_RNG0_OSCDIFF2) /* Oscillator Difference */ +#define pREG_RNG0_OSCDIFF3 ((__I __C int8_t *) REG_RNG0_OSCDIFF3) /* Oscillator Difference */ + +/* ================================================================================= + * Register Map for the Crypto Block (CRYPT0) + * ================================================================================= */ +#define pREG_CRYPT0_CFG ((__IO uint32_t *) REG_CRYPT0_CFG) /* Configuration Register */ +#define pREG_CRYPT0_DATALEN ((__IO uint32_t *) REG_CRYPT0_DATALEN) /* Payload Data Length */ +#define pREG_CRYPT0_PREFIXLEN ((__IO uint32_t *) REG_CRYPT0_PREFIXLEN) /* Authentication Data Length */ +#define pREG_CRYPT0_INTEN ((__IO uint32_t *) REG_CRYPT0_INTEN) /* Interrupt Enable Register */ +#define pREG_CRYPT0_STAT ((__IO uint32_t *) REG_CRYPT0_STAT) /* Status Register */ +#define pREG_CRYPT0_INBUF ((__O uint32_t *) REG_CRYPT0_INBUF) /* Input Buffer */ +#define pREG_CRYPT0_OUTBUF ((__I __C uint32_t *) REG_CRYPT0_OUTBUF) /* Output Buffer */ +#define pREG_CRYPT0_NONCE0 ((__IO uint32_t *) REG_CRYPT0_NONCE0) /* Nonce Bits [31:0] */ +#define pREG_CRYPT0_NONCE1 ((__IO uint32_t *) REG_CRYPT0_NONCE1) /* Nonce Bits [63:32] */ +#define pREG_CRYPT0_NONCE2 ((__IO uint32_t *) REG_CRYPT0_NONCE2) /* Nonce Bits [95:64] */ +#define pREG_CRYPT0_NONCE3 ((__IO uint32_t *) REG_CRYPT0_NONCE3) /* Nonce Bits [127:96] */ +#define pREG_CRYPT0_AESKEY0 ((__O uint32_t *) REG_CRYPT0_AESKEY0) /* AES Key Bits [31:0] */ +#define pREG_CRYPT0_AESKEY1 ((__O uint32_t *) REG_CRYPT0_AESKEY1) /* AES Key Bits [63:32] */ +#define pREG_CRYPT0_AESKEY2 ((__O uint32_t *) REG_CRYPT0_AESKEY2) /* AES Key Bits [95:64] */ +#define pREG_CRYPT0_AESKEY3 ((__O uint32_t *) REG_CRYPT0_AESKEY3) /* AES Key Bits [127:96] */ +#define pREG_CRYPT0_AESKEY4 ((__O uint32_t *) REG_CRYPT0_AESKEY4) /* AES Key Bits [159:128] */ +#define pREG_CRYPT0_AESKEY5 ((__O uint32_t *) REG_CRYPT0_AESKEY5) /* AES Key Bits [191:160] */ +#define pREG_CRYPT0_AESKEY6 ((__O uint32_t *) REG_CRYPT0_AESKEY6) /* AES Key Bits [223:192] */ +#define pREG_CRYPT0_AESKEY7 ((__O uint32_t *) REG_CRYPT0_AESKEY7) /* AES Key Bits [255:224] */ +#define pREG_CRYPT0_CNTRINIT ((__IO uint32_t *) REG_CRYPT0_CNTRINIT) /* Counter Initialization Vector */ +#define pREG_CRYPT0_SHAH0 ((__IO uint32_t *) REG_CRYPT0_SHAH0) /* SHA Bits [31:0] */ +#define pREG_CRYPT0_SHAH1 ((__IO uint32_t *) REG_CRYPT0_SHAH1) /* SHA Bits [63:32] */ +#define pREG_CRYPT0_SHAH2 ((__IO uint32_t *) REG_CRYPT0_SHAH2) /* SHA Bits [95:64] */ +#define pREG_CRYPT0_SHAH3 ((__IO uint32_t *) REG_CRYPT0_SHAH3) /* SHA Bits [127:96] */ +#define pREG_CRYPT0_SHAH4 ((__IO uint32_t *) REG_CRYPT0_SHAH4) /* SHA Bits [159:128] */ +#define pREG_CRYPT0_SHAH5 ((__IO uint32_t *) REG_CRYPT0_SHAH5) /* SHA Bits [191:160] */ +#define pREG_CRYPT0_SHAH6 ((__IO uint32_t *) REG_CRYPT0_SHAH6) /* SHA Bits [223:192] */ +#define pREG_CRYPT0_SHAH7 ((__IO uint32_t *) REG_CRYPT0_SHAH7) /* SHA Bits [255:224] */ +#define pREG_CRYPT0_SHA_LAST_WORD ((__IO uint32_t *) REG_CRYPT0_SHA_LAST_WORD) /* SHA Last Word and Valid Bits Information */ +#define pREG_CRYPT0_CCM_NUM_VALID_BYTES ((__IO uint32_t *) REG_CRYPT0_CCM_NUM_VALID_BYTES) /* NUM_VALID_BYTES */ +#define pREG_CRYPT0_PRKSTORCFG ((__IO uint32_t *) REG_CRYPT0_PRKSTORCFG) /* PRKSTOR Configuration */ +#define pREG_CRYPT0_KUW0 ((__O uint32_t *) REG_CRYPT0_KUW0) /* Key Wrap Unwrap Register 0 */ +#define pREG_CRYPT0_KUW1 ((__O uint32_t *) REG_CRYPT0_KUW1) /* Key Wrap Unwrap Register 1 */ +#define pREG_CRYPT0_KUW2 ((__O uint32_t *) REG_CRYPT0_KUW2) /* Key Wrap Unwrap Register 2 */ +#define pREG_CRYPT0_KUW3 ((__O uint32_t *) REG_CRYPT0_KUW3) /* Key Wrap Unwrap Register 3 */ +#define pREG_CRYPT0_KUW4 ((__O uint32_t *) REG_CRYPT0_KUW4) /* Key Wrap Unwrap Register 4 */ +#define pREG_CRYPT0_KUW5 ((__O uint32_t *) REG_CRYPT0_KUW5) /* Key Wrap Unwrap Register 5 */ +#define pREG_CRYPT0_KUW6 ((__O uint32_t *) REG_CRYPT0_KUW6) /* Key Wrap Unwrap Register 6 */ +#define pREG_CRYPT0_KUW7 ((__O uint32_t *) REG_CRYPT0_KUW7) /* Key Wrap Unwrap Register 7 */ +#define pREG_CRYPT0_KUW8 ((__O uint32_t *) REG_CRYPT0_KUW8) /* Key Wrap Unwrap Register 8 */ +#define pREG_CRYPT0_KUW9 ((__O uint32_t *) REG_CRYPT0_KUW9) /* Key Wrap Unwrap Register 9 */ +#define pREG_CRYPT0_KUW10 ((__O uint32_t *) REG_CRYPT0_KUW10) /* Key Wrap Unwrap Register 10 */ +#define pREG_CRYPT0_KUW11 ((__O uint32_t *) REG_CRYPT0_KUW11) /* Key Wrap Unwrap Register 11 */ +#define pREG_CRYPT0_KUW12 ((__O uint32_t *) REG_CRYPT0_KUW12) /* Key Wrap Unwrap Register 12 */ +#define pREG_CRYPT0_KUW13 ((__O uint32_t *) REG_CRYPT0_KUW13) /* Key Wrap Unwrap Register 13 */ +#define pREG_CRYPT0_KUW14 ((__O uint32_t *) REG_CRYPT0_KUW14) /* Key Wrap Unwrap Register 14 */ +#define pREG_CRYPT0_KUW15 ((__O uint32_t *) REG_CRYPT0_KUW15) /* Key Wrap Unwrap Register 15 */ +#define pREG_CRYPT0_KUWVALSTR1 ((__O uint32_t *) REG_CRYPT0_KUWVALSTR1) /* Key Wrap Unwrap Validation String [63:32] */ +#define pREG_CRYPT0_KUWVALSTR2 ((__O uint32_t *) REG_CRYPT0_KUWVALSTR2) /* Key Wrap Unwrap Validation String [31:0] */ + +/* ================================================================================= + * Power Management (PMG0) + * ================================================================================= */ +#define pREG_PMG0_IEN ((__IO uint32_t *) REG_PMG0_IEN) /* Power Supply Monitor Interrupt Enable */ +#define pREG_PMG0_PSM_STAT ((__IO uint32_t *) REG_PMG0_PSM_STAT) /* Power Supply Monitor Status */ +#define pREG_PMG0_PWRMOD ((__IO uint32_t *) REG_PMG0_PWRMOD) /* Power Mode Register */ +#define pREG_PMG0_PWRKEY ((__O uint32_t *) REG_PMG0_PWRKEY) /* Key Protection for PWRMOD and SRAMRET */ +#define pREG_PMG0_SHDN_STAT ((__I __C uint32_t *) REG_PMG0_SHDN_STAT) /* Shutdown Status Register */ +#define pREG_PMG0_SRAMRET ((__IO uint32_t *) REG_PMG0_SRAMRET) /* Control for Retention SRAM in Hibernate Mode */ +#define pREG_PMG0_TRIM ((__IO uint32_t *) REG_PMG0_TRIM) /* Trimming Bits */ +#define pREG_PMG0_RST_STAT ((__IO uint32_t *) REG_PMG0_RST_STAT) /* Reset Status */ +#define pREG_PMG0_CTL1 ((__IO uint32_t *) REG_PMG0_CTL1) /* HPBUCK Control */ + +/* ================================================================================= + * External interrupt configuration (XINT0) + * ================================================================================= */ +#define pREG_XINT0_CFG0 ((__IO uint32_t *) REG_XINT0_CFG0) /* External Interrupt configuration */ +#define pREG_XINT0_EXT_STAT ((__I __C uint32_t *) REG_XINT0_EXT_STAT) /* External Wakeup Interrupt Status register */ +#define pREG_XINT0_CLR ((__IO uint32_t *) REG_XINT0_CLR) /* External Interrupt clear */ +#define pREG_XINT0_NMICLR ((__IO uint32_t *) REG_XINT0_NMICLR) /* Non-maskable interrupt clear */ + +/* ================================================================================= + * Clocking (CLKG0_OSC) + * ================================================================================= */ +#define pREG_CLKG0_OSC_KEY ((__O uint32_t *) REG_CLKG0_OSC_KEY) /* Key Protection for OSCCTRL */ +#define pREG_CLKG0_OSC_CTL ((__IO uint32_t *) REG_CLKG0_OSC_CTL) /* Oscillator Control */ + +/* ================================================================================= + * Power Management (PMG0_TST) + * ================================================================================= */ +#define pREG_PMG0_TST_SRAM_CTL ((__IO uint32_t *) REG_PMG0_TST_SRAM_CTL) /* Control for SRAM Parity and Instruction SRAM */ +#define pREG_PMG0_TST_SRAM_INITSTAT ((__I __C uint32_t *) REG_PMG0_TST_SRAM_INITSTAT) /* Initialization Status Register */ +#define pREG_PMG0_TST_CLR_LATCH_GPIOS ((__O uint16_t *) REG_PMG0_TST_CLR_LATCH_GPIOS) /* Clear GPIO After Shutdown Mode */ +#define pREG_PMG0_TST_SCRPAD_IMG ((__IO uint32_t *) REG_PMG0_TST_SCRPAD_IMG) /* Scratch Pad Image */ +#define pREG_PMG0_TST_SCRPAD_3V_RD ((__I __C uint32_t *) REG_PMG0_TST_SCRPAD_3V_RD) /* Scratch Pad Saved in Battery Domain */ +#define pREG_PMG0_TST_FAST_SHT_WAKEUP ((__IO uint32_t *) REG_PMG0_TST_FAST_SHT_WAKEUP) /* Fast Shutdown Wake-up Enable */ + +/* ================================================================================= + * Clocking (CLKG0_CLK) + * ================================================================================= */ +#define pREG_CLKG0_CLK_CTL0 ((__IO uint32_t *) REG_CLKG0_CLK_CTL0) /* Misc Clock Settings */ +#define pREG_CLKG0_CLK_CTL1 ((__IO uint32_t *) REG_CLKG0_CLK_CTL1) /* Clock Dividers */ +#define pREG_CLKG0_CLK_CTL2 ((__IO uint32_t *) REG_CLKG0_CLK_CTL2) /* HF Oscillator Divided Clock Select */ +#define pREG_CLKG0_CLK_CTL3 ((__IO uint32_t *) REG_CLKG0_CLK_CTL3) /* System PLL */ +#define pREG_CLKG0_CLK_CTL5 ((__IO uint32_t *) REG_CLKG0_CLK_CTL5) /* User Clock Gating Control */ +#define pREG_CLKG0_CLK_STAT0 ((__IO uint32_t *) REG_CLKG0_CLK_STAT0) /* Clocking Status */ + +/* ================================================================================= + * Bus matrix (BUSM0) + * ================================================================================= */ +#define pREG_BUSM0_ARBIT0 ((__IO uint32_t *) REG_BUSM0_ARBIT0) /* Arbitration Priority Configuration for FLASH and SRAM0 */ +#define pREG_BUSM0_ARBIT1 ((__IO uint32_t *) REG_BUSM0_ARBIT1) /* Arbitration Priority Configuration for SRAM1 and SIP */ +#define pREG_BUSM0_ARBIT2 ((__IO uint32_t *) REG_BUSM0_ARBIT2) /* Arbitration Priority Configuration for APB32 and APB16 */ +#define pREG_BUSM0_ARBIT3 ((__IO uint32_t *) REG_BUSM0_ARBIT3) /* Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ +#define pREG_BUSM0_ARBIT4 ((__IO uint32_t *) REG_BUSM0_ARBIT4) /* Arbitration Priority Configuration for SRAM1 and SIP */ + +/* ================================================================================= + * Parallel Test Interface (PTI0) + * ================================================================================= */ +#define pREG_PTI0_RST_ISR_STARTADDR ((__IO uint32_t *) REG_PTI0_RST_ISR_STARTADDR) /* Reset ISR Start Address */ +#define pREG_PTI0_RST_STACK_PTR ((__IO uint32_t *) REG_PTI0_RST_STACK_PTR) /* Reset Stack Pointer */ +#define pREG_PTI0_CTL ((__IO uint32_t *) REG_PTI0_CTL) /* Parallel Test Interface Control Register */ + +/* ================================================================================= + * Cortex-M3 Interrupt Controller (NVIC0) + * ================================================================================= */ +#define pREG_NVIC0_INTNUM ((__IO uint32_t *) REG_NVIC0_INTNUM) /* Interrupt Control Type */ +#define pREG_NVIC0_STKSTA ((__IO uint32_t *) REG_NVIC0_STKSTA) /* Systick Control and Status */ +#define pREG_NVIC0_STKLD ((__IO uint32_t *) REG_NVIC0_STKLD) /* Systick Reload Value */ +#define pREG_NVIC0_STKVAL ((__IO uint32_t *) REG_NVIC0_STKVAL) /* Systick Current Value */ +#define pREG_NVIC0_STKCAL ((__IO uint32_t *) REG_NVIC0_STKCAL) /* Systick Calibration Value */ +#define pREG_NVIC0_INTSETE0 ((__IO uint32_t *) REG_NVIC0_INTSETE0) /* IRQ0..31 Set_Enable */ +#define pREG_NVIC0_INTSETE1 ((__IO uint32_t *) REG_NVIC0_INTSETE1) /* IRQ32..63 Set_Enable */ +#define pREG_NVIC0_INTCLRE0 ((__IO uint32_t *) REG_NVIC0_INTCLRE0) /* IRQ0..31 Clear_Enable */ +#define pREG_NVIC0_INTCLRE1 ((__IO uint32_t *) REG_NVIC0_INTCLRE1) /* IRQ32..63 Clear_Enable */ +#define pREG_NVIC0_INTSETP0 ((__IO uint32_t *) REG_NVIC0_INTSETP0) /* IRQ0..31 Set_Pending */ +#define pREG_NVIC0_INTSETP1 ((__IO uint32_t *) REG_NVIC0_INTSETP1) /* IRQ32..63 Set_Pending */ +#define pREG_NVIC0_INTCLRP0 ((__IO uint32_t *) REG_NVIC0_INTCLRP0) /* IRQ0..31 Clear_Pending */ +#define pREG_NVIC0_INTCLRP1 ((__IO uint32_t *) REG_NVIC0_INTCLRP1) /* IRQ32..63 Clear_Pending */ +#define pREG_NVIC0_INTACT0 ((__IO uint32_t *) REG_NVIC0_INTACT0) /* IRQ0..31 Active Bit */ +#define pREG_NVIC0_INTACT1 ((__IO uint32_t *) REG_NVIC0_INTACT1) /* IRQ32..63 Active Bit */ +#define pREG_NVIC0_INTPRI0 ((__IO uint32_t *) REG_NVIC0_INTPRI0) /* IRQ0..3 Priority */ +#define pREG_NVIC0_INTPRI1 ((__IO uint32_t *) REG_NVIC0_INTPRI1) /* IRQ4..7 Priority */ +#define pREG_NVIC0_INTPRI2 ((__IO uint32_t *) REG_NVIC0_INTPRI2) /* IRQ8..11 Priority */ +#define pREG_NVIC0_INTPRI3 ((__IO uint32_t *) REG_NVIC0_INTPRI3) /* IRQ12..15 Priority */ +#define pREG_NVIC0_INTPRI4 ((__IO uint32_t *) REG_NVIC0_INTPRI4) /* IRQ16..19 Priority */ +#define pREG_NVIC0_INTPRI5 ((__IO uint32_t *) REG_NVIC0_INTPRI5) /* IRQ20..23 Priority */ +#define pREG_NVIC0_INTPRI6 ((__IO uint32_t *) REG_NVIC0_INTPRI6) /* IRQ24..27 Priority */ +#define pREG_NVIC0_INTPRI7 ((__IO uint32_t *) REG_NVIC0_INTPRI7) /* IRQ28..31 Priority */ +#define pREG_NVIC0_INTPRI8 ((__IO uint32_t *) REG_NVIC0_INTPRI8) /* IRQ32..35 Priority */ +#define pREG_NVIC0_INTPRI9 ((__IO uint32_t *) REG_NVIC0_INTPRI9) /* IRQ36..39 Priority */ +#define pREG_NVIC0_INTPRI10 ((__IO uint32_t *) REG_NVIC0_INTPRI10) /* IRQ40..43 Priority */ +#define pREG_NVIC0_INTCPID ((__IO uint32_t *) REG_NVIC0_INTCPID) /* CPUID Base */ +#define pREG_NVIC0_INTSTA ((__IO uint32_t *) REG_NVIC0_INTSTA) /* Interrupt Control State */ +#define pREG_NVIC0_INTVEC ((__IO uint32_t *) REG_NVIC0_INTVEC) /* Vector Table Offset */ +#define pREG_NVIC0_INTAIRC ((__IO uint32_t *) REG_NVIC0_INTAIRC) /* Application Interrupt/Reset Control */ +#define pREG_NVIC0_INTCON0 ((__IO uint16_t *) REG_NVIC0_INTCON0) /* System Control */ +#define pREG_NVIC0_INTCON1 ((__IO uint32_t *) REG_NVIC0_INTCON1) /* Configuration Control */ +#define pREG_NVIC0_INTSHPRIO0 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO0) /* System Handlers 4-7 Priority */ +#define pREG_NVIC0_INTSHPRIO1 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO1) /* System Handlers 8-11 Priority */ +#define pREG_NVIC0_INTSHPRIO3 ((__IO uint32_t *) REG_NVIC0_INTSHPRIO3) /* System Handlers 12-15 Priority */ +#define pREG_NVIC0_INTSHCSR ((__IO uint32_t *) REG_NVIC0_INTSHCSR) /* System Handler Control and State */ +#define pREG_NVIC0_INTCFSR ((__IO uint32_t *) REG_NVIC0_INTCFSR) /* Configurable Fault Status */ +#define pREG_NVIC0_INTHFSR ((__IO uint32_t *) REG_NVIC0_INTHFSR) /* Hard Fault Status */ +#define pREG_NVIC0_INTDFSR ((__IO uint32_t *) REG_NVIC0_INTDFSR) /* Debug Fault Status */ +#define pREG_NVIC0_INTMMAR ((__IO uint32_t *) REG_NVIC0_INTMMAR) /* Mem Manage Address */ +#define pREG_NVIC0_INTBFAR ((__IO uint32_t *) REG_NVIC0_INTBFAR) /* Bus Fault Address */ +#define pREG_NVIC0_INTAFSR ((__IO uint32_t *) REG_NVIC0_INTAFSR) /* Auxiliary Fault Status */ +#define pREG_NVIC0_INTPFR0 ((__IO uint32_t *) REG_NVIC0_INTPFR0) /* Processor Feature Register 0 */ +#define pREG_NVIC0_INTPFR1 ((__IO uint32_t *) REG_NVIC0_INTPFR1) /* Processor Feature Register 1 */ +#define pREG_NVIC0_INTDFR0 ((__IO uint32_t *) REG_NVIC0_INTDFR0) /* Debug Feature Register 0 */ +#define pREG_NVIC0_INTAFR0 ((__IO uint32_t *) REG_NVIC0_INTAFR0) /* Auxiliary Feature Register 0 */ +#define pREG_NVIC0_INTMMFR0 ((__IO uint32_t *) REG_NVIC0_INTMMFR0) /* Memory Model Feature Register 0 */ +#define pREG_NVIC0_INTMMFR1 ((__IO uint32_t *) REG_NVIC0_INTMMFR1) /* Memory Model Feature Register 1 */ +#define pREG_NVIC0_INTMMFR2 ((__IO uint32_t *) REG_NVIC0_INTMMFR2) /* Memory Model Feature Register 2 */ +#define pREG_NVIC0_INTMMFR3 ((__IO uint32_t *) REG_NVIC0_INTMMFR3) /* Memory Model Feature Register 3 */ +#define pREG_NVIC0_INTISAR0 ((__IO uint32_t *) REG_NVIC0_INTISAR0) /* ISA Feature Register 0 */ +#define pREG_NVIC0_INTISAR1 ((__IO uint32_t *) REG_NVIC0_INTISAR1) /* ISA Feature Register 1 */ +#define pREG_NVIC0_INTISAR2 ((__IO uint32_t *) REG_NVIC0_INTISAR2) /* ISA Feature Register 2 */ +#define pREG_NVIC0_INTISAR3 ((__IO uint32_t *) REG_NVIC0_INTISAR3) /* ISA Feature Register 3 */ +#define pREG_NVIC0_INTISAR4 ((__IO uint32_t *) REG_NVIC0_INTISAR4) /* ISA Feature Register 4 */ +#define pREG_NVIC0_INTTRGI ((__IO uint32_t *) REG_NVIC0_INTTRGI) /* Software Trigger Interrupt Register */ +#define pREG_NVIC0_INTPID4 ((__IO uint32_t *) REG_NVIC0_INTPID4) /* Peripheral Identification Register 4 */ +#define pREG_NVIC0_INTPID5 ((__IO uint32_t *) REG_NVIC0_INTPID5) /* Peripheral Identification Register 5 */ +#define pREG_NVIC0_INTPID6 ((__IO uint32_t *) REG_NVIC0_INTPID6) /* Peripheral Identification Register 6 */ +#define pREG_NVIC0_INTPID7 ((__IO uint32_t *) REG_NVIC0_INTPID7) /* Peripheral Identification Register 7 */ +#define pREG_NVIC0_INTPID0 ((__IO uint32_t *) REG_NVIC0_INTPID0) /* Peripheral Identification Bits7:0 */ +#define pREG_NVIC0_INTPID1 ((__IO uint32_t *) REG_NVIC0_INTPID1) /* Peripheral Identification Bits15:8 */ +#define pREG_NVIC0_INTPID2 ((__IO uint32_t *) REG_NVIC0_INTPID2) /* Peripheral Identification Bits16:23 */ +#define pREG_NVIC0_INTPID3 ((__IO uint32_t *) REG_NVIC0_INTPID3) /* Peripheral Identification Bits24:31 */ +#define pREG_NVIC0_INTCID0 ((__IO uint32_t *) REG_NVIC0_INTCID0) /* Component Identification Bits7:0 */ +#define pREG_NVIC0_INTCID1 ((__IO uint32_t *) REG_NVIC0_INTCID1) /* Component Identification Bits15:8 */ +#define pREG_NVIC0_INTCID2 ((__IO uint32_t *) REG_NVIC0_INTCID2) /* Component Identification Bits16:23 */ +#define pREG_NVIC0_INTCID3 ((__IO uint32_t *) REG_NVIC0_INTCID3) /* Component Identification Bits24:31 */ + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#endif + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h new file mode 100755 index 00000000000..858848297b3 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_device.h @@ -0,0 +1,1338 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050_device.h + Description : C Register Definitions + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM4050_DEVICE_H +#define _ADUCM4050_DEVICE_H + +/* pickup integer types */ +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "adi_ADuCM4050_typedefs.h" + +#if defined ( __CC_ARM ) +#pragma push +#pragma anon_unions +#endif + + +#ifndef __IO +#ifdef __cplusplus +#define __I volatile /* read-only */ +#define __C +#else +#define __I volatile /* read-only */ +#define __C const +#endif +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif + +#if defined (_MISRA_RULES) +/* + anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. + Use of unions violates MISRA Rule 18.4. + Anonymous unions are required for this implementation. + Re-use of identifiers violates MISRA Rule 5.7. + Field names are repeated for the ADuCM4050 register map. +*/ +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions") +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers") +#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope") +#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers") +#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union") +#endif /* _MISRA_RULES */ + +/** @defgroup TMR General Purpose Timer (TMR) Module + * General Purpose Timer + * @{ + */ + +/*! ========================================================================== + * \struct ADI_TMR_TypeDef + * \brief General Purpose Timer + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ +typedef struct _ADI_TMR_TypeDef +{ + __IO uint16_t LOAD; /*!< 16-bit Load Value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CURCNT; /*!< 16-bit Timer Value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t CLRINT; /*!< Clear Interrupt */ + __I __C uint8_t RESERVED3[2]; + __I __C uint16_t CAPTURE; /*!< Capture */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALOAD; /*!< 16-bit Load Value, Asynchronous */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t ACURCNT; /*!< 16-bit Timer Value, Asynchronous */ + __I __C uint8_t RESERVED6[2]; + __I __C uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t PWMCTL; /*!< PWM Control Register */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t PWMMATCH; /*!< PWM Match Value */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t EVENTSELECT; /*!< Timer Event Selection Register */ +} ADI_TMR_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_TypeDef__ */ + +/*!@}*/ + +/** @defgroup TMR_RGB Timer_RGB with 3 PWM outputs (TMR_RGB) Module + * Timer_RGB with 3 PWM outputs + * @{ + */ + +/*! ========================================================================== + * \struct ADI_TMR_RGB_TypeDef + * \brief Timer_RGB with 3 PWM outputs + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_TypeDef__ +typedef struct _ADI_TMR_RGB_TypeDef +{ + __IO uint16_t LOAD; /*!< 16-bit load value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CURCNT; /*!< 16-bit timer value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t CLRINT; /*!< Clear interrupt */ + __I __C uint8_t RESERVED3[2]; + __I __C uint16_t CAPTURE; /*!< Capture */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALOAD; /*!< 16-bit load value, asynchronous */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t ACURCNT; /*!< 16-bit timer value, asynchronous */ + __I __C uint8_t RESERVED6[2]; + __I __C uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t PWM0CTL; /*!< PWM0 Control Register */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t PWM0MATCH; /*!< PWM0 Match Value */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t EVENTSELECT; /*!< Timer Event selection Register */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t PWM1CTL; /*!< PWM1 Control Register */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t PWM1MATCH; /*!< PWM1 Match Value */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t PWM2CTL; /*!< PWM2 Control Register */ + __I __C uint8_t RESERVED13[2]; + __IO uint16_t PWM2MATCH; /*!< PWM2 Match Value */ +} ADI_TMR_RGB_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_TypeDef__ */ + +/*!@}*/ + +/** @defgroup RTC Real-Time Clock (RTC) Module + * Real-Time Clock + * @{ + */ + +/*! ========================================================================== + * \struct ADI_RTC_TypeDef + * \brief Real-Time Clock + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ +typedef struct _ADI_RTC_TypeDef +{ + __IO uint16_t CR0; /*!< RTC Control 0 */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t SR0; /*!< RTC Status 0 */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t SR1; /*!< RTC Status 1 */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNT0; /*!< RTC Count 0 */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNT1; /*!< RTC Count 1 */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t ALM0; /*!< RTC Alarm 0 */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ALM1; /*!< RTC Alarm 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t TRM; /*!< RTC Trim */ + __I __C uint8_t RESERVED7[2]; + __O uint16_t GWY; /*!< RTC Gateway */ + __I __C uint8_t RESERVED8[6]; + __IO uint16_t CR1; /*!< RTC Control 1 */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SR2; /*!< RTC Status 2 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t SNAP0; /*!< RTC Snapshot 0 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SNAP1; /*!< RTC Snapshot 1 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t SNAP2; /*!< RTC Snapshot 2 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t MOD; /*!< RTC Modulo */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CNT2; /*!< RTC Count 2 */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ALM2; /*!< RTC Alarm 2 */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t SR3; /*!< RTC Status 3 */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t CR2IC; /*!< RTC Control 2 for Configuring Input Capture Channels */ + __I __C uint8_t RESERVED18[2]; + __IO uint16_t CR3SS; /*!< RTC Control 3 for Configuring SensorStrobe Channel */ + __I __C uint8_t RESERVED19[2]; + __IO uint16_t CR4SS; /*!< RTC Control 4 for Configuring SensorStrobe Channel */ + __I __C uint8_t RESERVED20[2]; + __IO uint16_t SSMSK; /*!< RTC Mask for SensorStrobe Channel */ + __I __C uint8_t RESERVED21[10]; + __I __C uint16_t IC2; /*!< RTC Input Capture Channel 2 */ + __I __C uint8_t RESERVED22[2]; + __I __C uint16_t IC3; /*!< RTC Input Capture Channel 3 */ + __I __C uint8_t RESERVED23[2]; + __I __C uint16_t IC4; /*!< RTC Input Capture Channel 4 */ + __I __C uint8_t RESERVED24[2]; + __IO uint16_t SS1; /*!< RTC SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED25[2]; + __IO uint16_t SS2; /*!< RTC SensorStrobe Channel 2 */ + __I __C uint8_t RESERVED26[2]; + __IO uint16_t SS3; /*!< RTC SensorStrobe Channel 3 */ + __I __C uint8_t RESERVED27[2]; + __IO uint16_t SS4; /*!< RTC SensorStrobe Channel 4 */ + __I __C uint8_t RESERVED28[2]; + __I __C uint16_t SR4; /*!< RTC Status 4 */ + __I __C uint8_t RESERVED29[2]; + __I __C uint16_t SR5; /*!< RTC Status 5 */ + __I __C uint8_t RESERVED30[2]; + __I __C uint16_t SR6; /*!< RTC Status 6 */ + __I __C uint8_t RESERVED31[2]; + __I __C uint16_t SS1TGT; /*!< RTC SensorStrobe Channel 1 Target */ + __I __C uint8_t RESERVED32[2]; + __I __C uint16_t FRZCNT; /*!< RTC Freeze Count */ + __I __C uint8_t RESERVED33[2]; + __I __C uint16_t SS2TGT; /*!< RTC SensorStrobe Channel 2 Target */ + __I __C uint8_t RESERVED34[2]; + __I __C uint16_t SS3TGT; /*!< RTC SensorStrobe Channel 3 Target */ + __I __C uint8_t RESERVED35[6]; + __IO uint16_t SS1LOWDUR; /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED36[2]; + __IO uint16_t SS2LOWDUR; /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 2 */ + __I __C uint8_t RESERVED37[2]; + __IO uint16_t SS3LOWDUR; /*!< RTC Auto-Reload Low Duration for SensorStrobe Channel 3 */ + __I __C uint8_t RESERVED38[6]; + __IO uint16_t SS1HIGHDUR; /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 1 */ + __I __C uint8_t RESERVED39[2]; + __IO uint16_t SS2HIGHDUR; /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 2 */ + __I __C uint8_t RESERVED40[2]; + __IO uint16_t SS3HIGHDUR; /*!< RTC Auto-Reload High Duration for SensorStrobe Channel 3 */ + __I __C uint8_t RESERVED41[6]; + __IO uint16_t SSMSKOT; /*!< RTC Masks for SensorStrobe Channels on Time Control */ + __I __C uint8_t RESERVED42[2]; + __IO uint16_t CR5SSS; /*!< RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling */ + __I __C uint8_t RESERVED43[2]; + __IO uint16_t CR6SSS; /*!< RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge */ + __I __C uint8_t RESERVED44[2]; + __IO uint16_t CR7SSS; /*!< RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity */ + __I __C uint8_t RESERVED45[2]; + __IO uint16_t SR7; /*!< RTC Status 7 */ + __I __C uint8_t RESERVED46[2]; + __I __C uint16_t SR8; /*!< RTC Status 8 */ + __I __C uint8_t RESERVED47[2]; + __I __C uint16_t SR9; /*!< RTC Status 9 */ + __I __C uint8_t RESERVED48[6]; + __IO uint16_t GPMUX0; /*!< RTC GPIO Pin Mux Control Register 0 */ + __I __C uint8_t RESERVED49[2]; + __IO uint16_t GPMUX1; /*!< RTC GPIO Pin Mux Control Register 1 */ +} ADI_RTC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SYS System Identification and Debug Enable (SYS) Module + * System Identification and Debug Enable + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SYS_TypeDef + * \brief System Identification and Debug Enable + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ +typedef struct _ADI_SYS_TypeDef +{ + __I __C uint8_t RESERVED0[32]; + __I __C uint16_t ADIID; /*!< ADI Identification */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t CHIPID; /*!< Chip Identifier */ + __I __C uint8_t RESERVED2[26]; + __O uint16_t SWDEN; /*!< Serial Wire Debug Enable */ +} ADI_SYS_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_TypeDef__ */ + +/*!@}*/ + +/** @defgroup WDT Watchdog Timer (WDT) Module + * Watchdog Timer + * @{ + */ + +/*! ========================================================================== + * \struct ADI_WDT_TypeDef + * \brief Watchdog Timer + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ +typedef struct _ADI_WDT_TypeDef +{ + __IO uint16_t LOAD; /*!< Load Value */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t CCNT; /*!< Current Count Value */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CTL; /*!< Control */ + __I __C uint8_t RESERVED2[2]; + __O uint16_t RESTART; /*!< Clear Interrupt */ + __I __C uint8_t RESERVED3[10]; + __I __C uint16_t STAT; /*!< Status */ +} ADI_WDT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup I2C I2C Master/Slave (I2C) Module + * I2C Master/Slave + * @{ + */ + +/*! ========================================================================== + * \struct ADI_I2C_TypeDef + * \brief I2C Master/Slave + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ +typedef struct _ADI_I2C_TypeDef +{ + __IO uint16_t MCTL; /*!< Master Control */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t MSTAT; /*!< Master Status */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t MRX; /*!< Master Receive Data */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t MTX; /*!< Master Transmit Data */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t MRXCNT; /*!< Master Receive Data Count */ + __I __C uint8_t RESERVED4[2]; + __I __C uint16_t MCRXCNT; /*!< Master Current Receive Data Count */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t ADDR1; /*!< Master Address Byte 1 */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t ADDR2; /*!< Master Address Byte 2 */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t BYT; /*!< Start Byte */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t DIV; /*!< Serial Clock Period Divisor */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t SCTL; /*!< Slave Control */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t SSTAT; /*!< Slave I2C Status/Error/IRQ */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t SRX; /*!< Slave Receive */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t STX; /*!< Slave Transmit */ + __I __C uint8_t RESERVED13[2]; + __IO uint16_t ALT; /*!< Hardware General Call ID */ + __I __C uint8_t RESERVED14[2]; + __IO uint16_t ID0; /*!< First Slave Address Device ID */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ID1; /*!< Second Slave Address Device ID */ + __I __C uint8_t RESERVED16[2]; + __IO uint16_t ID2; /*!< Third Slave Address Device ID */ + __I __C uint8_t RESERVED17[2]; + __IO uint16_t ID3; /*!< Fourth Slave Address Device ID */ + __I __C uint8_t RESERVED18[2]; + __IO uint16_t STAT; /*!< Master and Slave FIFO Status */ + __I __C uint8_t RESERVED19[2]; + __O uint16_t SHCTL; /*!< Shared Control */ + __I __C uint8_t RESERVED20[2]; + __IO uint16_t TCTL; /*!< Timing Control Register */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t ASTRETCH_SCL; /*!< Automatic Stretch SCL */ +} ADI_I2C_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SPI Serial Peripheral Interface (SPI) Module + * Serial Peripheral Interface + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SPI_TypeDef + * \brief Serial Peripheral Interface + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ +typedef struct _ADI_SPI_TypeDef +{ + __IO uint16_t STAT; /*!< Status */ + __I __C uint8_t RESERVED0[2]; + __I __C uint16_t RX; /*!< Receive */ + __I __C uint8_t RESERVED1[2]; + __O uint16_t TX; /*!< Transmit */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t DIV; /*!< SPI Baud Rate Selection */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CTL; /*!< SPI Configuration */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t IEN; /*!< SPI Interrupts Enable */ + __I __C uint8_t RESERVED5[2]; + __IO uint16_t CNT; /*!< Transfer Byte Count */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t DMA; /*!< SPI DMA Enable */ + __I __C uint8_t RESERVED7[2]; + __I __C uint16_t FIFO_STAT; /*!< FIFO Status */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t RD_CTL; /*!< Read Control */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t FLOW_CTL; /*!< Flow Control */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t WAIT_TMR; /*!< Wait Timer for Flow Control */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t CS_CTL; /*!< Chip Select Control for Multi-slave Connections */ + __I __C uint8_t RESERVED12[2]; + __IO uint16_t CS_OVERRIDE; /*!< Chip Select Override */ + __I __C uint8_t RESERVED13[4]; +} ADI_SPI_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TypeDef__ */ + +/*!@}*/ + +/** @defgroup UART (UART) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_UART_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ +typedef struct _ADI_UART_TypeDef +{ + union { + __I __C uint16_t RX; /*!< Receive Buffer Register */ + __O uint16_t TX; /*!< Transmit Holding Register */ + }; + __I __C uint8_t RESERVED0[2]; + __IO uint16_t IEN; /*!< Interrupt Enable */ + __I __C uint8_t RESERVED1[2]; + __I __C uint16_t IIR; /*!< Interrupt ID */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t LCR; /*!< Line Control */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t MCR; /*!< Modem Control */ + __I __C uint8_t RESERVED4[2]; + __I __C uint16_t LSR; /*!< Line Status */ + __I __C uint8_t RESERVED5[2]; + __I __C uint16_t MSR; /*!< Modem Status */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t SCR; /*!< Scratch Buffer */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t FCR; /*!< FIFO Control */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t FBR; /*!< Fractional Baud Rate */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t DIV; /*!< Baud Rate Divider */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t LCR2; /*!< Second Line Control */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t CTL; /*!< UART Control Register */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t RFC; /*!< RX FIFO Byte Count */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t TFC; /*!< TX FIFO Byte Count */ + __I __C uint8_t RESERVED14[2]; + __IO uint16_t RSC; /*!< RS485 Half-duplex Control */ + __I __C uint8_t RESERVED15[2]; + __IO uint16_t ACR; /*!< Auto Baud Control */ + __I __C uint8_t RESERVED16[2]; + __I __C uint16_t ASRL; /*!< Auto Baud Status (Low) */ + __I __C uint8_t RESERVED17[2]; + __I __C uint16_t ASRH; /*!< Auto Baud Status (High) */ +} ADI_UART_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TypeDef__ */ + +/*!@}*/ + +/** @defgroup BEEP Beeper Driver (BEEP) Module + * Beeper Driver + * @{ + */ + +/*! ========================================================================== + * \struct ADI_BEEP_TypeDef + * \brief Beeper Driver + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ +typedef struct _ADI_BEEP_TypeDef +{ + __IO uint16_t CFG; /*!< Beeper Configuration */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t STAT; /*!< Beeper Status */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t TONEA; /*!< Tone A Data */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t TONEB; /*!< Tone B Data */ +} ADI_BEEP_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TypeDef__ */ + +/*!@}*/ + +/** @defgroup ADC (ADC) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_ADC_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ +typedef struct _ADI_ADC_TypeDef +{ + __IO uint16_t CFG; /*!< ADC Configuration */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t PWRUP; /*!< ADC Power-up Time */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t CAL_WORD; /*!< Calibration Word */ + __I __C uint8_t RESERVED2[2]; + __IO uint16_t CNV_CFG; /*!< ADC Conversion Configuration */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t CNV_TIME; /*!< ADC Conversion Time */ + __I __C uint8_t RESERVED4[2]; + __IO uint16_t AVG_CFG; /*!< Averaging Configuration */ + __I __C uint8_t RESERVED5[10]; + __IO uint16_t IRQ_EN; /*!< Interrupt Enable */ + __I __C uint8_t RESERVED6[2]; + __IO uint16_t STAT; /*!< ADC Status */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t OVF; /*!< Overflow of Output Registers */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t ALERT; /*!< Alert Indication */ + __I __C uint8_t RESERVED9[2]; + __I __C uint16_t CH0_OUT; /*!< Conversion Result Channel 0 */ + __I __C uint8_t RESERVED10[2]; + __I __C uint16_t CH1_OUT; /*!< Conversion Result Channel 1 */ + __I __C uint8_t RESERVED11[2]; + __I __C uint16_t CH2_OUT; /*!< Conversion Result Channel 2 */ + __I __C uint8_t RESERVED12[2]; + __I __C uint16_t CH3_OUT; /*!< Conversion Result Channel 3 */ + __I __C uint8_t RESERVED13[2]; + __I __C uint16_t CH4_OUT; /*!< Conversion Result Channel 4 */ + __I __C uint8_t RESERVED14[2]; + __I __C uint16_t CH5_OUT; /*!< Conversion Result Channel 5 */ + __I __C uint8_t RESERVED15[2]; + __I __C uint16_t CH6_OUT; /*!< Conversion Result Channel 6 */ + __I __C uint8_t RESERVED16[2]; + __I __C uint16_t CH7_OUT; /*!< Conversion Result Channel 7 */ + __I __C uint8_t RESERVED17[2]; + __I __C uint16_t BAT_OUT; /*!< Battery Monitoring Result */ + __I __C uint8_t RESERVED18[2]; + __I __C uint16_t TMP_OUT; /*!< Temperature Result */ + __I __C uint8_t RESERVED19[2]; + __I __C uint16_t TMP2_OUT; /*!< Temperature Result 2 */ + __I __C uint8_t RESERVED20[2]; + __I __C uint16_t DMA_OUT; /*!< DMA Output Register */ + __I __C uint8_t RESERVED21[2]; + __IO uint16_t LIM0_LO; /*!< Channel 0 Low Limit */ + __I __C uint8_t RESERVED22[2]; + __IO uint16_t LIM0_HI; /*!< Channel 0 High Limit */ + __I __C uint8_t RESERVED23[2]; + __IO uint16_t HYS0; /*!< Channel 0 Hysteresis */ + __I __C uint8_t RESERVED24[6]; + __IO uint16_t LIM1_LO; /*!< Channel 1 Low Limit */ + __I __C uint8_t RESERVED25[2]; + __IO uint16_t LIM1_HI; /*!< Channel 1 High Limit */ + __I __C uint8_t RESERVED26[2]; + __IO uint16_t HYS1; /*!< Channel 1 Hysteresis */ + __I __C uint8_t RESERVED27[6]; + __IO uint16_t LIM2_LO; /*!< Channel 2 Low Limit */ + __I __C uint8_t RESERVED28[2]; + __IO uint16_t LIM2_HI; /*!< Channel 2 High Limit */ + __I __C uint8_t RESERVED29[2]; + __IO uint16_t HYS2; /*!< Channel 2 Hysteresis */ + __I __C uint8_t RESERVED30[6]; + __IO uint16_t LIM3_LO; /*!< Channel 3 Low Limit */ + __I __C uint8_t RESERVED31[2]; + __IO uint16_t LIM3_HI; /*!< Channel 3 High Limit */ + __I __C uint8_t RESERVED32[2]; + __IO uint16_t HYS3; /*!< Channel 3 Hysteresis */ + __I __C uint8_t RESERVED33[38]; + __IO uint16_t CFG1; /*!< Reference Buffer Low Power Mode */ + __I __C uint8_t RESERVED34[576]; +} ADI_ADC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup DMA DMA (DMA) Module + * DMA + * @{ + */ + +/*! ========================================================================== + * \struct ADI_DMA_TypeDef + * \brief DMA + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ +typedef struct _ADI_DMA_TypeDef +{ + __I __C uint32_t STAT; /*!< DMA Status */ + __O uint32_t CFG; /*!< DMA Configuration */ + __IO uint32_t PDBPTR; /*!< DMA Channel Primary Control Database Pointer */ + __I __C uint32_t ADBPTR; /*!< DMA Channel Alternate Control Database Pointer */ + __I __C uint8_t RESERVED0[4]; + __O uint32_t SWREQ; /*!< DMA Channel Software Request */ + __I __C uint8_t RESERVED1[8]; + __IO uint32_t RMSK_SET; /*!< DMA Channel Request Mask Set */ + __O uint32_t RMSK_CLR; /*!< DMA Channel Request Mask Clear */ + __IO uint32_t EN_SET; /*!< DMA Channel Enable Set */ + __O uint32_t EN_CLR; /*!< DMA Channel Enable Clear */ + __IO uint32_t ALT_SET; /*!< DMA Channel Primary Alternate Set */ + __O uint32_t ALT_CLR; /*!< DMA Channel Primary Alternate Clear */ + __O uint32_t PRI_SET; /*!< DMA Channel Priority Set */ + __O uint32_t PRI_CLR; /*!< DMA Channel Priority Clear */ + __I __C uint8_t RESERVED2[8]; + __IO uint32_t ERRCHNL_CLR; /*!< DMA per Channel Error Clear */ + __IO uint32_t ERR_CLR; /*!< DMA Bus Error Clear */ + __IO uint32_t INVALIDDESC_CLR; /*!< DMA per Channel Invalid Descriptor Clear */ + __I __C uint8_t RESERVED3[1964]; + __IO uint32_t BS_SET; /*!< DMA Channel Bytes Swap Enable Set */ + __O uint32_t BS_CLR; /*!< DMA Channel Bytes Swap Enable Clear */ + __I __C uint8_t RESERVED4[8]; + __IO uint32_t SRCADDR_SET; /*!< DMA Channel Source Address Decrement Enable Set */ + __O uint32_t SRCADDR_CLR; /*!< DMA Channel Source Address Decrement Enable Clear */ + __IO uint32_t DSTADDR_SET; /*!< DMA Channel Destination Address Decrement Enable Set */ + __O uint32_t DSTADDR_CLR; /*!< DMA Channel Destination Address Decrement Enable Clear */ + __I __C uint8_t RESERVED5[1984]; + __I __C uint32_t REVID; /*!< DMA Controller Revision ID */ +} ADI_DMA_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_TypeDef__ */ + +/*!@}*/ + +/** @defgroup FLCC Flash Controller (FLCC) Module + * Flash Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_FLCC_TypeDef + * \brief Flash Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ +typedef struct _ADI_FLCC_TypeDef +{ + __IO uint32_t STAT; /*!< Status */ + __IO uint32_t IEN; /*!< Interrupt Enable */ + __IO uint32_t CMD; /*!< Command */ + __IO uint32_t KH_ADDR; /*!< Write Address */ + __IO uint32_t KH_DATA0; /*!< Write Lower Data */ + __IO uint32_t KH_DATA1; /*!< Write Upper Data */ + __IO uint32_t PAGE_ADDR0; /*!< Lower Page Address */ + __IO uint32_t PAGE_ADDR1; /*!< Upper Page Address */ + __O uint32_t KEY; /*!< Key */ + __I __C uint32_t WR_ABORT_ADDR; /*!< Write Abort Address */ + __IO uint32_t WRPROT; /*!< Write Protection */ + __I __C uint32_t SIGNATURE; /*!< Signature */ + __IO uint32_t UCFG; /*!< User Configuration */ + __IO uint32_t TIME_PARAM0; /*!< Time Parameter 0 */ + __IO uint32_t TIME_PARAM1; /*!< Time Parameter 1 */ + __IO uint32_t ABORT_EN_LO; /*!< IRQ Abort Enable (Lower Bits) */ + __IO uint32_t ABORT_EN_HI; /*!< IRQ Abort Enable (Upper Bits) */ + __IO uint32_t ECC_CFG; /*!< ECC Configuration */ + __I __C uint32_t ECC_ADDR; /*!< ECC Status (Address) */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t POR_SEC; /*!< Flash Security */ + __IO uint32_t VOL_CFG; /*!< Volatile Flash Configuration */ +} ADI_FLCC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup FLCC_CACHE Cache Controller (FLCC_CACHE) Module + * Cache Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_FLCC_CACHE_TypeDef + * \brief Cache Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ +typedef struct _ADI_FLCC_CACHE_TypeDef +{ + __I __C uint32_t STAT; /*!< Cache Status Register */ + __IO uint32_t SETUP; /*!< Cache Setup Register */ + __O uint32_t KEY; /*!< Cache Key Register */ + __I __C uint8_t RESERVED0[40]; +} ADI_FLCC_CACHE_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_TypeDef__ */ + +/*!@}*/ + +/** @defgroup GPIO (GPIO) Module + * + * @{ + */ + +/*! ========================================================================== + * \struct ADI_GPIO_TypeDef + * \brief + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ +typedef struct _ADI_GPIO_TypeDef +{ + __IO uint32_t CFG; /*!< Port Configuration */ + __IO uint16_t OEN; /*!< Port Output Enable */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t PE; /*!< Port Output Pull-up/Pull-down Enable */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t IEN; /*!< Port Input Path Enable */ + __I __C uint8_t RESERVED2[2]; + __I __C uint16_t IN; /*!< Port Registered Data Input */ + __I __C uint8_t RESERVED3[2]; + __IO uint16_t OUT; /*!< Port Data Output */ + __I __C uint8_t RESERVED4[2]; + __O uint16_t SET; /*!< Port Data Out Set */ + __I __C uint8_t RESERVED5[2]; + __O uint16_t CLR; /*!< Port Data Out Clear */ + __I __C uint8_t RESERVED6[2]; + __O uint16_t TGL; /*!< Port Pin Toggle */ + __I __C uint8_t RESERVED7[2]; + __IO uint16_t POL; /*!< Port Interrupt Polarity */ + __I __C uint8_t RESERVED8[2]; + __IO uint16_t IENA; /*!< Port Interrupt A Enable */ + __I __C uint8_t RESERVED9[2]; + __IO uint16_t IENB; /*!< Port Interrupt B Enable */ + __I __C uint8_t RESERVED10[2]; + __IO uint16_t INT; /*!< Port Interrupt Status */ + __I __C uint8_t RESERVED11[2]; + __IO uint16_t DS; /*!< Port Drive Strength Select */ +} ADI_GPIO_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TypeDef__ */ + +/*!@}*/ + +/** @defgroup SPORT Serial Port (SPORT) Module + * Serial Port + * @{ + */ + +/*! ========================================================================== + * \struct ADI_SPORT_TypeDef + * \brief Serial Port + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ +typedef struct _ADI_SPORT_TypeDef +{ + __IO uint32_t CTL_A; /*!< Half SPORT 'A' Control Register */ + __IO uint32_t DIV_A; /*!< Half SPORT 'A' Divisor Register */ + __IO uint32_t IEN_A; /*!< Half SPORT A's Interrupt Enable register */ + __IO uint32_t STAT_A; /*!< Half SPORT 'A' Status register */ + __IO uint32_t NUMTRAN_A; /*!< Half SPORT A Number of transfers register */ + __IO uint32_t CNVT_A; /*!< Half SPORT 'A' CNV width */ + __I __C uint8_t RESERVED0[8]; + __O uint32_t TX_A; /*!< Half SPORT 'A' Tx Buffer Register */ + __I __C uint8_t RESERVED1[4]; + __I __C uint32_t RX_A; /*!< Half SPORT 'A' Rx Buffer Register */ + __I __C uint8_t RESERVED2[20]; + __IO uint32_t CTL_B; /*!< Half SPORT 'B' Control Register */ + __IO uint32_t DIV_B; /*!< Half SPORT 'B' Divisor Register */ + __IO uint32_t IEN_B; /*!< Half SPORT B's Interrupt Enable register */ + __IO uint32_t STAT_B; /*!< Half SPORT 'B' Status register */ + __IO uint32_t NUMTRAN_B; /*!< Half SPORT B Number of transfers register */ + __IO uint32_t CNVT_B; /*!< Half SPORT 'B' CNV width register */ + __I __C uint8_t RESERVED3[8]; + __O uint32_t TX_B; /*!< Half SPORT 'B' Tx Buffer Register */ + __I __C uint8_t RESERVED4[4]; + __I __C uint32_t RX_B; /*!< Half SPORT 'B' Rx Buffer Register */ + __I __C uint8_t RESERVED5[16]; +} ADI_SPORT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CRC CRC Accelerator (CRC) Module + * CRC Accelerator + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CRC_TypeDef + * \brief CRC Accelerator + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ +typedef struct _ADI_CRC_TypeDef +{ + __IO uint32_t CTL; /*!< CRC Control */ + __O uint32_t IPDATA; /*!< Input Data Word */ + __IO uint32_t RESULT; /*!< CRC Result */ + __IO uint32_t POLY; /*!< Programmable CRC Polynomial */ + union { + __O uint8_t IPBITS[8]; /*!< Input Data Bits */ + __O uint8_t IPBYTE; /*!< Input Data Byte */ + }; +} ADI_CRC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup RNG Random Number Generator (RNG) Module + * Random Number Generator + * @{ + */ + +/*! ========================================================================== + * \struct ADI_RNG_TypeDef + * \brief Random Number Generator + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ +typedef struct _ADI_RNG_TypeDef +{ + __IO uint16_t CTL; /*!< RNG Control Register */ + __I __C uint8_t RESERVED0[2]; + __IO uint16_t LEN; /*!< RNG Sample Length Register */ + __I __C uint8_t RESERVED1[2]; + __IO uint16_t STAT; /*!< RNG Status Register */ + __I __C uint8_t RESERVED2[2]; + __I __C uint32_t DATA; /*!< RNG Data Register */ + __I __C uint32_t OSCCNT; /*!< Oscillator Count */ + __I __C int8_t OSCDIFF[4]; /*!< Oscillator Difference */ +} ADI_RNG_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CRYPT Register Map for the Crypto Block (CRYPT) Module + * Register Map for the Crypto Block + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CRYPT_TypeDef + * \brief Register Map for the Crypto Block + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ +typedef struct _ADI_CRYPT_TypeDef +{ + __IO uint32_t CFG; /*!< Configuration Register */ + __IO uint32_t DATALEN; /*!< Payload Data Length */ + __IO uint32_t PREFIXLEN; /*!< Authentication Data Length */ + __IO uint32_t INTEN; /*!< Interrupt Enable Register */ + __IO uint32_t STAT; /*!< Status Register */ + __O uint32_t INBUF; /*!< Input Buffer */ + __I __C uint32_t OUTBUF; /*!< Output Buffer */ + __IO uint32_t NONCE0; /*!< Nonce Bits [31:0] */ + __IO uint32_t NONCE1; /*!< Nonce Bits [63:32] */ + __IO uint32_t NONCE2; /*!< Nonce Bits [95:64] */ + __IO uint32_t NONCE3; /*!< Nonce Bits [127:96] */ + __O uint32_t AESKEY0; /*!< AES Key Bits [31:0] */ + __O uint32_t AESKEY1; /*!< AES Key Bits [63:32] */ + __O uint32_t AESKEY2; /*!< AES Key Bits [95:64] */ + __O uint32_t AESKEY3; /*!< AES Key Bits [127:96] */ + __O uint32_t AESKEY4; /*!< AES Key Bits [159:128] */ + __O uint32_t AESKEY5; /*!< AES Key Bits [191:160] */ + __O uint32_t AESKEY6; /*!< AES Key Bits [223:192] */ + __O uint32_t AESKEY7; /*!< AES Key Bits [255:224] */ + __IO uint32_t CNTRINIT; /*!< Counter Initialization Vector */ + __IO uint32_t SHAH0; /*!< SHA Bits [31:0] */ + __IO uint32_t SHAH1; /*!< SHA Bits [63:32] */ + __IO uint32_t SHAH2; /*!< SHA Bits [95:64] */ + __IO uint32_t SHAH3; /*!< SHA Bits [127:96] */ + __IO uint32_t SHAH4; /*!< SHA Bits [159:128] */ + __IO uint32_t SHAH5; /*!< SHA Bits [191:160] */ + __IO uint32_t SHAH6; /*!< SHA Bits [223:192] */ + __IO uint32_t SHAH7; /*!< SHA Bits [255:224] */ + __IO uint32_t SHA_LAST_WORD; /*!< SHA Last Word and Valid Bits Information */ + __IO uint32_t CCM_NUM_VALID_BYTES; /*!< NUM_VALID_BYTES */ + __IO uint32_t PRKSTORCFG; /*!< PRKSTOR Configuration */ + __I __C uint8_t RESERVED0[4]; + __O uint32_t KUW0; /*!< Key Wrap Unwrap Register 0 */ + __O uint32_t KUW1; /*!< Key Wrap Unwrap Register 1 */ + __O uint32_t KUW2; /*!< Key Wrap Unwrap Register 2 */ + __O uint32_t KUW3; /*!< Key Wrap Unwrap Register 3 */ + __O uint32_t KUW4; /*!< Key Wrap Unwrap Register 4 */ + __O uint32_t KUW5; /*!< Key Wrap Unwrap Register 5 */ + __O uint32_t KUW6; /*!< Key Wrap Unwrap Register 6 */ + __O uint32_t KUW7; /*!< Key Wrap Unwrap Register 7 */ + __O uint32_t KUW8; /*!< Key Wrap Unwrap Register 8 */ + __O uint32_t KUW9; /*!< Key Wrap Unwrap Register 9 */ + __O uint32_t KUW10; /*!< Key Wrap Unwrap Register 10 */ + __O uint32_t KUW11; /*!< Key Wrap Unwrap Register 11 */ + __O uint32_t KUW12; /*!< Key Wrap Unwrap Register 12 */ + __O uint32_t KUW13; /*!< Key Wrap Unwrap Register 13 */ + __O uint32_t KUW14; /*!< Key Wrap Unwrap Register 14 */ + __O uint32_t KUW15; /*!< Key Wrap Unwrap Register 15 */ + __O uint32_t KUWVALSTR1; /*!< Key Wrap Unwrap Validation String [63:32] */ + __O uint32_t KUWVALSTR2; /*!< Key Wrap Unwrap Validation String [31:0] */ +} ADI_CRYPT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PMG Power Management (PMG) Module + * Power Management + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PMG_TypeDef + * \brief Power Management + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ +typedef struct _ADI_PMG_TypeDef +{ + __IO uint32_t IEN; /*!< Power Supply Monitor Interrupt Enable */ + __IO uint32_t PSM_STAT; /*!< Power Supply Monitor Status */ + __IO uint32_t PWRMOD; /*!< Power Mode Register */ + __O uint32_t PWRKEY; /*!< Key Protection for PWRMOD and SRAMRET */ + __I __C uint32_t SHDN_STAT; /*!< Shutdown Status Register */ + __IO uint32_t SRAMRET; /*!< Control for Retention SRAM in Hibernate Mode */ + __I __C uint8_t RESERVED0[32]; + __IO uint32_t TRIM; /*!< Trimming Bits */ + __I __C uint8_t RESERVED1[4]; + __IO uint32_t RST_STAT; /*!< Reset Status */ + __IO uint32_t CTL1; /*!< HPBUCK Control */ + __I __C uint8_t RESERVED2[20]; +} ADI_PMG_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TypeDef__ */ + +/*!@}*/ + +/** @defgroup XINT External interrupt configuration (XINT) Module + * External interrupt configuration + * @{ + */ + +/*! ========================================================================== + * \struct ADI_XINT_TypeDef + * \brief External interrupt configuration + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ +typedef struct _ADI_XINT_TypeDef +{ + __IO uint32_t CFG0; /*!< External Interrupt configuration */ + __I __C uint32_t EXT_STAT; /*!< External Wakeup Interrupt Status register */ + __I __C uint8_t RESERVED0[8]; + __IO uint32_t CLR; /*!< External Interrupt clear */ + __IO uint32_t NMICLR; /*!< Non-maskable interrupt clear */ +} ADI_XINT_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CLKG_OSC Clocking (CLKG_OSC) Module + * Clocking + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CLKG_OSC_TypeDef + * \brief Clocking + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ +typedef struct _ADI_CLKG_OSC_TypeDef +{ + __I __C uint8_t RESERVED0[12]; + __O uint32_t KEY; /*!< Key Protection for OSCCTRL */ + __IO uint32_t CTL; /*!< Oscillator Control */ + __I __C uint8_t RESERVED1[8]; +} ADI_CLKG_OSC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PMG_TST Power Management (PMG_TST) Module + * Power Management + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PMG_TST_TypeDef + * \brief Power Management + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ +typedef struct _ADI_PMG_TST_TypeDef +{ + __I __C uint8_t RESERVED0[96]; + __IO uint32_t SRAM_CTL; /*!< Control for SRAM Parity and Instruction SRAM */ + __I __C uint32_t SRAM_INITSTAT; /*!< Initialization Status Register */ + __O uint16_t CLR_LATCH_GPIOS; /*!< Clear GPIO After Shutdown Mode */ + __I __C uint8_t RESERVED1[2]; + __IO uint32_t SCRPAD_IMG; /*!< Scratch Pad Image */ + __I __C uint32_t SCRPAD_3V_RD; /*!< Scratch Pad Saved in Battery Domain */ + __IO uint32_t FAST_SHT_WAKEUP; /*!< Fast Shutdown Wake-up Enable */ +} ADI_PMG_TST_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_TypeDef__ */ + +/*!@}*/ + +/** @defgroup CLKG_CLK Clocking (CLKG_CLK) Module + * Clocking + * @{ + */ + +/*! ========================================================================== + * \struct ADI_CLKG_CLK_TypeDef + * \brief Clocking + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ +typedef struct _ADI_CLKG_CLK_TypeDef +{ + __IO uint32_t CTL0; /*!< Misc Clock Settings */ + __IO uint32_t CTL1; /*!< Clock Dividers */ + __IO uint32_t CTL2; /*!< HF Oscillator Divided Clock Select */ + __IO uint32_t CTL3; /*!< System PLL */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t CTL5; /*!< User Clock Gating Control */ + __IO uint32_t STAT0; /*!< Clocking Status */ + __I __C uint8_t RESERVED1[20]; +} ADI_CLKG_CLK_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_TypeDef__ */ + +/*!@}*/ + +/** @defgroup BUSM Bus matrix (BUSM) Module + * Bus matrix + * @{ + */ + +/*! ========================================================================== + * \struct ADI_BUSM_TypeDef + * \brief Bus matrix + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ +typedef struct _ADI_BUSM_TypeDef +{ + __IO uint32_t ARBIT0; /*!< Arbitration Priority Configuration for FLASH and SRAM0 */ + __IO uint32_t ARBIT1; /*!< Arbitration Priority Configuration for SRAM1 and SIP */ + __IO uint32_t ARBIT2; /*!< Arbitration Priority Configuration for APB32 and APB16 */ + __IO uint32_t ARBIT3; /*!< Arbitration Priority Configuration for APB16 priority for core and for DMA1 */ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t ARBIT4; /*!< Arbitration Priority Configuration for SRAM1 and SIP */ +} ADI_BUSM_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_TypeDef__ */ + +/*!@}*/ + +/** @defgroup PTI Parallel Test Interface (PTI) Module + * Parallel Test Interface + * @{ + */ + +/*! ========================================================================== + * \struct ADI_PTI_TypeDef + * \brief Parallel Test Interface + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ +typedef struct _ADI_PTI_TypeDef +{ + __IO uint32_t RST_ISR_STARTADDR; /*!< Reset ISR Start Address */ + __IO uint32_t RST_STACK_PTR; /*!< Reset Stack Pointer */ + __IO uint32_t CTL; /*!< Parallel Test Interface Control Register */ +} ADI_PTI_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_TypeDef__ */ + +/*!@}*/ + +/** @defgroup NVIC Cortex-M3 Interrupt Controller (NVIC) Module + * Cortex-M3 Interrupt Controller + * @{ + */ + +/*! ========================================================================== + * \struct ADI_NVIC_TypeDef + * \brief Cortex-M3 Interrupt Controller + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ +typedef struct _ADI_NVIC_TypeDef +{ + __I __C uint8_t RESERVED0[4]; + __IO uint32_t INTNUM; /*!< Interrupt Control Type */ + __I __C uint8_t RESERVED1[8]; + __IO uint32_t STKSTA; /*!< Systick Control and Status */ + __IO uint32_t STKLD; /*!< Systick Reload Value */ + __IO uint32_t STKVAL; /*!< Systick Current Value */ + __IO uint32_t STKCAL; /*!< Systick Calibration Value */ + __I __C uint8_t RESERVED2[224]; + __IO uint32_t INTSETE0; /*!< IRQ0..31 Set_Enable */ + __IO uint32_t INTSETE1; /*!< IRQ32..63 Set_Enable */ + __I __C uint8_t RESERVED3[120]; + __IO uint32_t INTCLRE0; /*!< IRQ0..31 Clear_Enable */ + __IO uint32_t INTCLRE1; /*!< IRQ32..63 Clear_Enable */ + __I __C uint8_t RESERVED4[120]; + __IO uint32_t INTSETP0; /*!< IRQ0..31 Set_Pending */ + __IO uint32_t INTSETP1; /*!< IRQ32..63 Set_Pending */ + __I __C uint8_t RESERVED5[120]; + __IO uint32_t INTCLRP0; /*!< IRQ0..31 Clear_Pending */ + __IO uint32_t INTCLRP1; /*!< IRQ32..63 Clear_Pending */ + __I __C uint8_t RESERVED6[120]; + __IO uint32_t INTACT0; /*!< IRQ0..31 Active Bit */ + __IO uint32_t INTACT1; /*!< IRQ32..63 Active Bit */ + __I __C uint8_t RESERVED7[248]; + __IO uint32_t INTPRI0; /*!< IRQ0..3 Priority */ + __IO uint32_t INTPRI1; /*!< IRQ4..7 Priority */ + __IO uint32_t INTPRI2; /*!< IRQ8..11 Priority */ + __IO uint32_t INTPRI3; /*!< IRQ12..15 Priority */ + __IO uint32_t INTPRI4; /*!< IRQ16..19 Priority */ + __IO uint32_t INTPRI5; /*!< IRQ20..23 Priority */ + __IO uint32_t INTPRI6; /*!< IRQ24..27 Priority */ + __IO uint32_t INTPRI7; /*!< IRQ28..31 Priority */ + __IO uint32_t INTPRI8; /*!< IRQ32..35 Priority */ + __IO uint32_t INTPRI9; /*!< IRQ36..39 Priority */ + __IO uint32_t INTPRI10; /*!< IRQ40..43 Priority */ + __I __C uint8_t RESERVED8[2260]; + __IO uint32_t INTCPID; /*!< CPUID Base */ + __IO uint32_t INTSTA; /*!< Interrupt Control State */ + __IO uint32_t INTVEC; /*!< Vector Table Offset */ + __IO uint32_t INTAIRC; /*!< Application Interrupt/Reset Control */ + __IO uint16_t INTCON0; /*!< System Control */ + __I __C uint8_t RESERVED9[2]; + __IO uint32_t INTCON1; /*!< Configuration Control */ + __IO uint32_t INTSHPRIO0; /*!< System Handlers 4-7 Priority */ + __IO uint32_t INTSHPRIO1; /*!< System Handlers 8-11 Priority */ + __IO uint32_t INTSHPRIO3; /*!< System Handlers 12-15 Priority */ + __IO uint32_t INTSHCSR; /*!< System Handler Control and State */ + __IO uint32_t INTCFSR; /*!< Configurable Fault Status */ + __IO uint32_t INTHFSR; /*!< Hard Fault Status */ + __IO uint32_t INTDFSR; /*!< Debug Fault Status */ + __IO uint32_t INTMMAR; /*!< Mem Manage Address */ + __IO uint32_t INTBFAR; /*!< Bus Fault Address */ + __IO uint32_t INTAFSR; /*!< Auxiliary Fault Status */ + __IO uint32_t INTPFR0; /*!< Processor Feature Register 0 */ + __IO uint32_t INTPFR1; /*!< Processor Feature Register 1 */ + __IO uint32_t INTDFR0; /*!< Debug Feature Register 0 */ + __IO uint32_t INTAFR0; /*!< Auxiliary Feature Register 0 */ + __IO uint32_t INTMMFR0; /*!< Memory Model Feature Register 0 */ + __IO uint32_t INTMMFR1; /*!< Memory Model Feature Register 1 */ + __IO uint32_t INTMMFR2; /*!< Memory Model Feature Register 2 */ + __IO uint32_t INTMMFR3; /*!< Memory Model Feature Register 3 */ + __IO uint32_t INTISAR0; /*!< ISA Feature Register 0 */ + __IO uint32_t INTISAR1; /*!< ISA Feature Register 1 */ + __IO uint32_t INTISAR2; /*!< ISA Feature Register 2 */ + __IO uint32_t INTISAR3; /*!< ISA Feature Register 3 */ + __IO uint32_t INTISAR4; /*!< ISA Feature Register 4 */ + __I __C uint8_t RESERVED10[396]; + __IO uint32_t INTTRGI; /*!< Software Trigger Interrupt Register */ + __I __C uint8_t RESERVED11[204]; + __IO uint32_t INTPID4; /*!< Peripheral Identification Register 4 */ + __IO uint32_t INTPID5; /*!< Peripheral Identification Register 5 */ + __IO uint32_t INTPID6; /*!< Peripheral Identification Register 6 */ + __IO uint32_t INTPID7; /*!< Peripheral Identification Register 7 */ + __IO uint32_t INTPID0; /*!< Peripheral Identification Bits7:0 */ + __IO uint32_t INTPID1; /*!< Peripheral Identification Bits15:8 */ + __IO uint32_t INTPID2; /*!< Peripheral Identification Bits16:23 */ + __IO uint32_t INTPID3; /*!< Peripheral Identification Bits24:31 */ + __IO uint32_t INTCID0; /*!< Component Identification Bits7:0 */ + __IO uint32_t INTCID1; /*!< Component Identification Bits15:8 */ + __IO uint32_t INTCID2; /*!< Component Identification Bits16:23 */ + __IO uint32_t INTCID3; /*!< Component Identification Bits24:31 */ +} ADI_NVIC_TypeDef; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_TypeDef__ */ + +/*!@}*/ + +/* ****************************************************************************** + * Peripheral Memory Map Declarations + * *****************************************************************************/ +/*! @defgroup PMEMMAPDEC Peripheral Memory Map Declarations + * \addtogroup PMEMMAPDEC + * @{ */ +#define ADI_TMR0_BASE 0x40000000 /*!< Base address of TMR0 */ +#define ADI_TMR1_BASE 0x40000400 /*!< Base address of TMR1 */ +#define ADI_TMR2_BASE 0x40000800 /*!< Base address of TMR2 */ +#define ADI_TMR_RGB_BASE 0x40000c00 /*!< Base address of TMR_RGB */ +#define ADI_RTC0_BASE 0x40001000 /*!< Base address of RTC0 */ +#define ADI_RTC1_BASE 0x40001400 /*!< Base address of RTC1 */ +#define ADI_SYS_BASE 0x40002000 /*!< Base address of SYS */ +#define ADI_WDT0_BASE 0x40002c00 /*!< Base address of WDT0 */ +#define ADI_I2C0_BASE 0x40003000 /*!< Base address of I2C0 */ +#define ADI_SPI0_BASE 0x40004000 /*!< Base address of SPI0 */ +#define ADI_SPI1_BASE 0x40004400 /*!< Base address of SPI1 */ +#define ADI_SPI2_BASE 0x40024000 /*!< Base address of SPI2 */ +#define ADI_UART0_BASE 0x40005000 /*!< Base address of UART0 */ +#define ADI_UART1_BASE 0x40005400 /*!< Base address of UART1 */ +#define ADI_BEEP0_BASE 0x40005c00 /*!< Base address of BEEP0 */ +#define ADI_ADC0_BASE 0x40007000 /*!< Base address of ADC0 */ +#define ADI_DMA0_BASE 0x40010000 /*!< Base address of DMA0 */ +#define ADI_FLCC0_BASE 0x40018000 /*!< Base address of FLCC0 */ +#define ADI_FLCC0_CACHE_BASE 0x40018058 /*!< Base address of FLCC0_CACHE */ +#define ADI_GPIO0_BASE 0x40020000 /*!< Base address of GPIO0 */ +#define ADI_GPIO1_BASE 0x40020040 /*!< Base address of GPIO1 */ +#define ADI_GPIO2_BASE 0x40020080 /*!< Base address of GPIO2 */ +#define ADI_GPIO3_BASE 0x400200c0 /*!< Base address of GPIO3 */ +#define ADI_SPORT0_BASE 0x40038000 /*!< Base address of SPORT0 */ +#define ADI_CRC0_BASE 0x40040000 /*!< Base address of CRC0 */ +#define ADI_RNG0_BASE 0x40040400 /*!< Base address of RNG0 */ +#define ADI_CRYPT0_BASE 0x40044000 /*!< Base address of CRYPT0 */ +#define ADI_PMG0_BASE 0x4004c000 /*!< Base address of PMG0 */ +#define ADI_XINT0_BASE 0x4004c080 /*!< Base address of XINT0 */ +#define ADI_CLKG0_OSC_BASE 0x4004c100 /*!< Base address of CLKG0_OSC */ +#define ADI_PMG0_TST_BASE 0x4004c200 /*!< Base address of PMG0_TST */ +#define ADI_CLKG0_CLK_BASE 0x4004c300 /*!< Base address of CLKG0_CLK */ +#define ADI_BUSM0_BASE 0x4004c800 /*!< Base address of BUSM0 */ +#define ADI_PTI0_BASE 0x4004cd00 /*!< Base address of PTI0 */ +#define ADI_NVIC0_BASE 0xe000e000 /*!< Base address of NVIC0 */ + +/*! @} */ + +/* ****************************************************************************** + * Peripheral Pointer Declarations + * *****************************************************************************/ +/*! @Defgroup Pptrdec Peripheral Pointer Declarations + * \Addtogroup Pptrdec + * @{ */ +#define pADI_TMR0 ((ADI_TMR_TypeDef *) ADI_TMR0_BASE ) /*!< Pointer to General Purpose Timer (TMR0) */ +#define pADI_TMR1 ((ADI_TMR_TypeDef *) ADI_TMR1_BASE ) /*!< Pointer to General Purpose Timer (TMR1) */ +#define pADI_TMR2 ((ADI_TMR_TypeDef *) ADI_TMR2_BASE ) /*!< Pointer to General Purpose Timer (TMR2) */ +#define pADI_TMR_RGB ((ADI_TMR_RGB_TypeDef *) ADI_TMR_RGB_BASE ) /*!< Pointer to Timer_RGB with 3 PWM outputs (TMR_RGB) */ +#define pADI_RTC0 ((ADI_RTC_TypeDef *) ADI_RTC0_BASE ) /*!< Pointer to Real-Time Clock (RTC0) */ +#define pADI_RTC1 ((ADI_RTC_TypeDef *) ADI_RTC1_BASE ) /*!< Pointer to Real-Time Clock (RTC1) */ +#define pADI_SYS ((ADI_SYS_TypeDef *) ADI_SYS_BASE ) /*!< Pointer to System Identification and Debug Enable (SYS) */ +#define pADI_WDT0 ((ADI_WDT_TypeDef *) ADI_WDT0_BASE ) /*!< Pointer to Watchdog Timer (WDT0) */ +#define pADI_I2C0 ((ADI_I2C_TypeDef *) ADI_I2C0_BASE ) /*!< Pointer to I2C Master/Slave (I2C0) */ +#define pADI_SPI0 ((ADI_SPI_TypeDef *) ADI_SPI0_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI0) */ +#define pADI_SPI1 ((ADI_SPI_TypeDef *) ADI_SPI1_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI1) */ +#define pADI_SPI2 ((ADI_SPI_TypeDef *) ADI_SPI2_BASE ) /*!< Pointer to Serial Peripheral Interface (SPI2) */ +#define pADI_UART0 ((ADI_UART_TypeDef *) ADI_UART0_BASE ) /*!< Pointer to (UART0) */ +#define pADI_UART1 ((ADI_UART_TypeDef *) ADI_UART1_BASE ) /*!< Pointer to (UART1) */ +#define pADI_BEEP0 ((ADI_BEEP_TypeDef *) ADI_BEEP0_BASE ) /*!< Pointer to Beeper Driver (BEEP0) */ +#define pADI_ADC0 ((ADI_ADC_TypeDef *) ADI_ADC0_BASE ) /*!< Pointer to (ADC0) */ +#define pADI_DMA0 ((ADI_DMA_TypeDef *) ADI_DMA0_BASE ) /*!< Pointer to DMA (DMA0) */ +#define pADI_FLCC0 ((ADI_FLCC_TypeDef *) ADI_FLCC0_BASE ) /*!< Pointer to Flash Controller (FLCC0) */ +#define pADI_FLCC0_CACHE ((ADI_FLCC_CACHE_TypeDef *) ADI_FLCC0_CACHE_BASE) /*!< Pointer to Cache Controller (FLCC0_CACHE) */ +#define pADI_GPIO0 ((ADI_GPIO_TypeDef *) ADI_GPIO0_BASE ) /*!< Pointer to (GPIO0) */ +#define pADI_GPIO1 ((ADI_GPIO_TypeDef *) ADI_GPIO1_BASE ) /*!< Pointer to (GPIO1) */ +#define pADI_GPIO2 ((ADI_GPIO_TypeDef *) ADI_GPIO2_BASE ) /*!< Pointer to (GPIO2) */ +#define pADI_GPIO3 ((ADI_GPIO_TypeDef *) ADI_GPIO3_BASE ) /*!< Pointer to (GPIO3) */ +#define pADI_SPORT0 ((ADI_SPORT_TypeDef *) ADI_SPORT0_BASE ) /*!< Pointer to Serial Port (SPORT0) */ +#define pADI_CRC0 ((ADI_CRC_TypeDef *) ADI_CRC0_BASE ) /*!< Pointer to CRC Accelerator (CRC0) */ +#define pADI_RNG0 ((ADI_RNG_TypeDef *) ADI_RNG0_BASE ) /*!< Pointer to Random Number Generator (RNG0) */ +#define pADI_CRYPT0 ((ADI_CRYPT_TypeDef *) ADI_CRYPT0_BASE ) /*!< Pointer to Register Map for the Crypto Block (CRYPT0) */ +#define pADI_PMG0 ((ADI_PMG_TypeDef *) ADI_PMG0_BASE ) /*!< Pointer to Power Management (PMG0) */ +#define pADI_XINT0 ((ADI_XINT_TypeDef *) ADI_XINT0_BASE ) /*!< Pointer to External interrupt configuration (XINT0) */ +#define pADI_CLKG0_OSC ((ADI_CLKG_OSC_TypeDef *) ADI_CLKG0_OSC_BASE ) /*!< Pointer to Clocking (CLKG0_OSC) */ +#define pADI_PMG0_TST ((ADI_PMG_TST_TypeDef *) ADI_PMG0_TST_BASE ) /*!< Pointer to Power Management (PMG0_TST) */ +#define pADI_CLKG0_CLK ((ADI_CLKG_CLK_TypeDef *) ADI_CLKG0_CLK_BASE ) /*!< Pointer to Clocking (CLKG0_CLK) */ +#define pADI_BUSM0 ((ADI_BUSM_TypeDef *) ADI_BUSM0_BASE ) /*!< Pointer to Bus matrix (BUSM0) */ +#define pADI_PTI0 ((ADI_PTI_TypeDef *) ADI_PTI0_BASE ) /*!< Pointer to Parallel Test Interface (PTI0) */ +#define pADI_NVIC0 ((ADI_NVIC_TypeDef *) ADI_NVIC0_BASE ) /*!< Pointer to Cortex-M3 Interrupt Controller (NVIC0) */ + +/*! @} */ + + +/* ========================================================================= + *! \enum IRQn_Type + *! \brief Interrupt Number Assignments + * ========================================================================= */ +#ifndef __ADI_NO_DECL_ENUM_IRQn_Type__ + +typedef enum +{ + RESET_IRQn = -15, /*!< Cortex-M4 Reset */ + NonMaskableInt_IRQn = -14, /*!< Cortex-M4 Non-maskable Interrupt */ + HardFault_IRQn = -13, /*!< Cortex-M4 Hardware Fault */ + MemoryManagement_IRQn = -12, /*!< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< Cortex-M4 Bus Fault */ + UsageFault_IRQn = -10, /*!< Cortex-M4 Usage Fault */ + SVCall_IRQn = -5, /*!< Cortex-M4 SVCall Interrupt */ + DebugMonitor_IRQn = -4, /*!< Cortex-M4 Debug Monitor */ + PendSV_IRQn = -2, /*!< Cortex-M4 PendSV Interrupt */ + SysTick_IRQn = -1, /*!< Cortex-M4 SysTick Interrupt */ + RTC1_EVT_IRQn = 0, /*!< Event */ + XINT_EVT0_IRQn = 1, /*!< External Wakeup Interrupt n */ + XINT_EVT1_IRQn = 2, /*!< External Wakeup Interrupt n */ + XINT_EVT2_IRQn = 3, /*!< External Wakeup Interrupt n */ + XINT_EVT3_IRQn = 4, /*!< External Wakeup Interrupt n */ + WDT_EXP_IRQn = 5, /*!< Expiration */ + PMG0_VREG_OVR_IRQn = 6, /*!< Voltage Regulator (VREG) Overvoltage */ + PMG0_BATT_RANGE_IRQn = 7, /*!< Battery Voltage (VBAT) Out of Range */ + RTC0_EVT_IRQn = 8, /*!< Event */ + SYS_GPIO_INTA_IRQn = 9, /*!< GPIO Interrupt A */ + SYS_GPIO_INTB_IRQn = 10, /*!< GPIO Interrupt B */ + TMR0_EVT_IRQn = 11, /*!< Event */ + TMR1_EVT_IRQn = 12, /*!< Event */ + FLCC_EVT_IRQn = 13, /*!< Event */ + UART0_EVT_IRQn = 14, /*!< UART0 Event */ + SPI0_EVT_IRQn = 15, /*!< Event */ + SPI2_EVT_IRQn = 16, /*!< Event */ + I2C_SLV_EVT_IRQn = 17, /*!< Slave Event */ + I2C_MST_EVT_IRQn = 18, /*!< Master Event */ + DMA_CHAN_ERR_IRQn = 19, /*!< Channel Error */ + DMA0_CH0_DONE_IRQn = 20, /*!< Channel 0 Done */ + DMA0_CH1_DONE_IRQn = 21, /*!< Channel 1 Done */ + DMA0_CH2_DONE_IRQn = 22, /*!< Channel 2 Done */ + DMA0_CH3_DONE_IRQn = 23, /*!< Channel 3 Done */ + DMA0_CH4_DONE_IRQn = 24, /*!< Channel 4 Done */ + DMA0_CH5_DONE_IRQn = 25, /*!< Channel 5 Done */ + DMA0_CH6_DONE_IRQn = 26, /*!< Channel 6 Done */ + DMA0_CH7_DONE_IRQn = 27, /*!< Channel 7 Done */ + DMA0_CH8_DONE_IRQn = 28, /*!< Channel 8 Done */ + DMA0_CH9_DONE_IRQn = 29, /*!< Channel 9 Done */ + DMA0_CH10_DONE_IRQn = 30, /*!< Channel 10 Done */ + DMA0_CH11_DONE_IRQn = 31, /*!< Channel 11 Done */ + DMA0_CH12_DONE_IRQn = 32, /*!< Channel 12 Done */ + DMA0_CH13_DONE_IRQn = 33, /*!< Channel 13 Done */ + DMA0_CH14_DONE_IRQn = 34, /*!< Channel 14 Done */ + DMA0_CH15_DONE_IRQn = 35, /*!< Channel 15 Done */ + SPORT_A_EVT_IRQn = 36, /*!< Channel A Event */ + SPORT_B_EVT_IRQn = 37, /*!< Channel B Event */ + CRYPT_EVT_IRQn = 38, /*!< Event */ + DMA0_CH24_DONE_IRQn = 39, /*!< Channel 24 Done */ + TMR2_EVT_IRQn = 40, /*!< Event */ + CLKG_XTAL_OSC_EVT_IRQn = 41, /*!< Crystal Oscillator Event */ + SPI1_EVT_IRQn = 42, /*!< Event */ + CLKG_PLL_EVT_IRQn = 43, /*!< PLL Event */ + RNG0_EVT_IRQn = 44, /*!< Event */ + BEEP_EVT_IRQn = 45, /*!< Event */ + ADC0_EVT_IRQn = 46, /*!< Event */ + DMA0_CH16_DONE_IRQn = 56, /*!< Channel 16 Done */ + DMA0_CH17_DONE_IRQn = 57, /*!< Channel 17 Done */ + DMA0_CH18_DONE_IRQn = 58, /*!< Channel 18 Done */ + DMA0_CH19_DONE_IRQn = 59, /*!< Channel 19 Done */ + DMA0_CH20_DONE_IRQn = 60, /*!< Channel 20 Done */ + DMA0_CH21_DONE_IRQn = 61, /*!< Channel 21 Done */ + DMA0_CH22_DONE_IRQn = 62, /*!< Channel 22 Done */ + DMA0_CH23_DONE_IRQn = 63, /*!< Channel 23 Done */ + UART1_EVT_IRQn = 66, /*!< Event */ + DMA0_CH25_DONE_IRQn = 67, /*!< Channel 25 Done */ + DMA0_CH26_DONE_IRQn = 68, /*!< Channel 26 Done */ + TMR_RGB_EVT_IRQn = 69, /*!< Event */ + CLKG_ROOTCLK_ERR_IRQn = 71, /*!< Root Clock Error */ +} IRQn_Type; /* typedef name for fixed interrupt numbers */ +#endif /* !__ADI_NO_DECL_ENUM_IRQn_Type__ */ + + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#if defined (__CC_ARM) +#pragma pop +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h new file mode 100755 index 00000000000..356eea0165d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_ADuCM4050_typedefs.h @@ -0,0 +1,11252 @@ +/* ================================================================================ + + Project : ADuCM4050 + File : ADuCM4050_typedefs.h + Description : C Register Structures + + Date : Feb 7, 2017 + + Copyright (c) 2014-2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + ================================================================================ */ + +#ifndef _ADUCM4050_TYPEDEFS_H +#define _ADUCM4050_TYPEDEFS_H + +/* pickup integer types */ +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include +#endif /* _LANGUAGE_C */ + +#if defined ( __CC_ARM ) +#pragma push +#pragma anon_unions +#endif + + +#if defined (_MISRA_RULES) +/* + anonymous unions violate ISO 9899:1990 and therefore MISRA Rule 1.1. + Use of unions violates MISRA Rule 18.4. + Anonymous unions are required for this implementation. + Re-use of identifiers violates MISRA Rule 5.7. + Field names are repeated for the ADuCM4050 register map. +*/ +#pragma diag(push) +#pragma diag(suppress:misra_rule_1_1:"Allow anonymous unions") +#pragma diag(suppress:misra_rule_5_1:"Allow names over 32 character limit") +#pragma diag(suppress:misra_rule_5_3:"Header will re-use typedef identifiers") +#pragma diag(suppress:misra_rule_5_6:"Header will re-use identifiers in the same scope") +#pragma diag(suppress:misra_rule_5_7:"Header will re-use identifiers") +#pragma diag(suppress:misra_rule_18_4:"Allow the use of a union") +#endif /* _MISRA_RULES */ + +/** @defgroup LOAD 16-bit Load Value (LOAD) Register + * 16-bit Load Value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_LOAD_Struct + *! \brief 16-bit Load Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ +typedef struct _ADI_TMR_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CURCNT 16-bit Timer Value (CURCNT) Register + * 16-bit Timer Value (CURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CURCNT_Struct + *! \brief 16-bit Timer Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ +typedef struct _ADI_TMR_CURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current Count */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CURCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ +typedef struct _ADI_TMR_CTL_t { + union { + struct { + unsigned int PRE : 2; /**< Prescaler */ + unsigned int UP : 1; /**< Count up */ + unsigned int MODE : 1; /**< Timer Mode */ + unsigned int EN : 1; /**< Timer Enable */ + unsigned int CLK : 2; /**< Clock Select */ + unsigned int RLD : 1; /**< Reload Control */ + unsigned int reserved8 : 5; + unsigned int EVTEN : 1; /**< Event Select */ + unsigned int RSTEN : 1; /**< Counter and Prescale Reset Enable */ + unsigned int SYNCBYP : 1; /**< Synchronization Bypass */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CTL_t__ */ + +/*@}*/ + +/** @defgroup CLRINT Clear Interrupt (CLRINT) Register + * Clear Interrupt (CLRINT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CLRINT_Struct + *! \brief Clear Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ +typedef struct _ADI_TMR_CLRINT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Clear Timeout Interrupt */ + unsigned int EVTCAPT : 1; /**< Clear Captured Event Interrupt */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_CLRINT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CLRINT_t__ */ + +/*@}*/ + +/** @defgroup CAPTURE Capture (CAPTURE) Register + * Capture (CAPTURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_CAPTURE_Struct + *! \brief Capture Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ +typedef struct _ADI_TMR_CAPTURE_t { + union { + struct { + unsigned int VALUE : 16; /**< 16-bit Captured Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_CAPTURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_CAPTURE_t__ */ + +/*@}*/ + +/** @defgroup ALOAD 16-bit Load Value, Asynchronous (ALOAD) Register + * 16-bit Load Value, Asynchronous (ALOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_ALOAD_Struct + *! \brief 16-bit Load Value, Asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ +typedef struct _ADI_TMR_ALOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value, Asynchronous */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_ALOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ALOAD_t__ */ + +/*@}*/ + +/** @defgroup ACURCNT 16-bit Timer Value, Asynchronous (ACURCNT) Register + * 16-bit Timer Value, Asynchronous (ACURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_ACURCNT_Struct + *! \brief 16-bit Timer Value, Asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ +typedef struct _ADI_TMR_ACURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Counter Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_ACURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_ACURCNT_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ +typedef struct _ADI_TMR_STAT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Timeout Event Occurred */ + unsigned int CAPTURE : 1; /**< Capture Event Pending */ + unsigned int reserved2 : 4; + unsigned int BUSY : 1; /**< Timer Busy */ + unsigned int PDOK : 1; /**< Clear Interrupt Register Synchronization */ + unsigned int CNTRST : 1; /**< Counter Reset Occurring */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_TMR_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWMCTL PWM Control Register (PWMCTL) Register + * PWM Control Register (PWMCTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_TMR_PWMCTL_MATCH + *! \brief PWM Match Enabled (MATCH) Enumerations + * ========================================================================= */ +typedef enum +{ + TMR_PWMCTL_PWM_TOGGLE = 0, /**< PWM in toggle mode */ + TMR_PWMCTL_PWM_MATCH = 1 /**< PWM in match mode */ +} ADI_TMR_PWMCTL_MATCH; + + +/* ========================================================================= + *! \enum ADI_TMR_PWMCTL_IDLESTATE + *! \brief PWM Idle State (IDLESTATE) Enumerations + * ========================================================================= */ +typedef enum +{ + TMR_PWMCTL_IDLE_LOW = 0, /**< PWM idles low */ + TMR_PWMCTL_IDLE_HIGH = 1 /**< PWM idles high */ +} ADI_TMR_PWMCTL_IDLESTATE; + + +/* ========================================================================== + *! \struct ADI_TMR_PWMCTL_Struct + *! \brief PWM Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ +typedef struct _ADI_TMR_PWMCTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match Enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_PWMCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMCTL_t__ */ + +/*@}*/ + +/** @defgroup PWMMATCH PWM Match Value (PWMMATCH) Register + * PWM Match Value (PWMMATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_PWMMATCH_Struct + *! \brief PWM Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ +typedef struct _ADI_TMR_PWMMATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_PWMMATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_PWMMATCH_t__ */ + +/*@}*/ + +/** @defgroup EVENTSELECT Timer Event Selection Register (EVENTSELECT) Register + * Timer Event Selection Register (EVENTSELECT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_EVENTSELECT_Struct + *! \brief Timer Event Selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_EVENTSELECT_t__ +typedef struct _ADI_TMR_EVENTSELECT_t { + union { + struct { + unsigned int EVTRANGE : 6; /**< Event Select Range */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_TMR_EVENTSELECT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_EVENTSELECT_t__ */ + +/*@}*/ + +/** @defgroup LOAD 16-bit load value (LOAD) Register + * 16-bit load value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_LOAD_Struct + *! \brief 16-bit load value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_LOAD_t__ +typedef struct _ADI_TMR_RGB_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CURCNT 16-bit timer value (CURCNT) Register + * 16-bit timer value (CURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CURCNT_Struct + *! \brief 16-bit timer value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CURCNT_t__ +typedef struct _ADI_TMR_RGB_CURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current count */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CURCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CTL_t__ +typedef struct _ADI_TMR_RGB_CTL_t { + union { + struct { + unsigned int PRE : 2; /**< Prescaler */ + unsigned int UP : 1; /**< Count up */ + unsigned int MODE : 1; /**< Timer mode */ + unsigned int EN : 1; /**< Timer enable */ + unsigned int CLK : 2; /**< Clock select */ + unsigned int RLD : 1; /**< Reload control */ + unsigned int reserved8 : 5; + unsigned int EVTEN : 1; /**< Event select */ + unsigned int RSTEN : 1; /**< Counter and prescale reset enable */ + unsigned int SYNCBYP : 1; /**< Synchronization bypass */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CTL_t__ */ + +/*@}*/ + +/** @defgroup CLRINT Clear interrupt (CLRINT) Register + * Clear interrupt (CLRINT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CLRINT_Struct + *! \brief Clear interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CLRINT_t__ +typedef struct _ADI_TMR_RGB_CLRINT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Clear timeout interrupt */ + unsigned int EVTCAPT : 1; /**< Clear captured event interrupt */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CLRINT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CLRINT_t__ */ + +/*@}*/ + +/** @defgroup CAPTURE Capture (CAPTURE) Register + * Capture (CAPTURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_CAPTURE_Struct + *! \brief Capture Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CAPTURE_t__ +typedef struct _ADI_TMR_RGB_CAPTURE_t { + union { + struct { + unsigned int VALUE : 16; /**< 16-bit captured value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_CAPTURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_CAPTURE_t__ */ + +/*@}*/ + +/** @defgroup ALOAD 16-bit load value, asynchronous (ALOAD) Register + * 16-bit load value, asynchronous (ALOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_ALOAD_Struct + *! \brief 16-bit load value, asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ALOAD_t__ +typedef struct _ADI_TMR_RGB_ALOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load value, asynchronous */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_ALOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ALOAD_t__ */ + +/*@}*/ + +/** @defgroup ACURCNT 16-bit timer value, asynchronous (ACURCNT) Register + * 16-bit timer value, asynchronous (ACURCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_ACURCNT_Struct + *! \brief 16-bit timer value, asynchronous Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ACURCNT_t__ +typedef struct _ADI_TMR_RGB_ACURCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Counter value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_ACURCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_ACURCNT_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_STAT_t__ +typedef struct _ADI_TMR_RGB_STAT_t { + union { + struct { + unsigned int TIMEOUT : 1; /**< Timeout event occurred */ + unsigned int CAPTURE : 1; /**< Capture event pending */ + unsigned int reserved2 : 4; + unsigned int BUSY : 1; /**< Timer Busy */ + unsigned int PDOK : 1; /**< Clear Interrupt Register synchronization */ + unsigned int CNTRST : 1; /**< Counter reset occurring */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWM0CTL PWM0 Control Register (PWM0CTL) Register + * PWM0 Control Register (PWM0CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM0CTL_Struct + *! \brief PWM0 Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0CTL_t__ +typedef struct _ADI_TMR_RGB_PWM0CTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM0CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0CTL_t__ */ + +/*@}*/ + +/** @defgroup PWM0MATCH PWM0 Match Value (PWM0MATCH) Register + * PWM0 Match Value (PWM0MATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM0MATCH_Struct + *! \brief PWM0 Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0MATCH_t__ +typedef struct _ADI_TMR_RGB_PWM0MATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM0MATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM0MATCH_t__ */ + +/*@}*/ + +/** @defgroup EVENTSELECT Timer Event selection Register (EVENTSELECT) Register + * Timer Event selection Register (EVENTSELECT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_EVENTSELECT_Struct + *! \brief Timer Event selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_EVENTSELECT_t__ +typedef struct _ADI_TMR_RGB_EVENTSELECT_t { + union { + struct { + unsigned int EVTRANGE : 6; /**< Event select range */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_EVENTSELECT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_EVENTSELECT_t__ */ + +/*@}*/ + +/** @defgroup PWM1CTL PWM1 Control Register (PWM1CTL) Register + * PWM1 Control Register (PWM1CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM1CTL_Struct + *! \brief PWM1 Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1CTL_t__ +typedef struct _ADI_TMR_RGB_PWM1CTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM1CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1CTL_t__ */ + +/*@}*/ + +/** @defgroup PWM1MATCH PWM1 Match Value (PWM1MATCH) Register + * PWM1 Match Value (PWM1MATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM1MATCH_Struct + *! \brief PWM1 Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1MATCH_t__ +typedef struct _ADI_TMR_RGB_PWM1MATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM1MATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM1MATCH_t__ */ + +/*@}*/ + +/** @defgroup PWM2CTL PWM2 Control Register (PWM2CTL) Register + * PWM2 Control Register (PWM2CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM2CTL_Struct + *! \brief PWM2 Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2CTL_t__ +typedef struct _ADI_TMR_RGB_PWM2CTL_t { + union { + struct { + unsigned int MATCH : 1; /**< PWM Match enabled */ + unsigned int IDLESTATE : 1; /**< PWM Idle State */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM2CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2CTL_t__ */ + +/*@}*/ + +/** @defgroup PWM2MATCH PWM2 Match Value (PWM2MATCH) Register + * PWM2 Match Value (PWM2MATCH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_TMR_RGB_PWM2MATCH_Struct + *! \brief PWM2 Match Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2MATCH_t__ +typedef struct _ADI_TMR_RGB_PWM2MATCH_t { + union { + struct { + unsigned int VALUE : 16; /**< PWM Match Value */ + }; + uint16_t VALUE16; + }; +} ADI_TMR_RGB_PWM2MATCH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_TMR_RGB_PWM2MATCH_t__ */ + +/*@}*/ + +/** @defgroup CR0 RTC Control 0 (CR0) Register + * RTC Control 0 (CR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR0_Struct + *! \brief RTC Control 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ +typedef struct _ADI_RTC_CR0_t { + union { + struct { + unsigned int CNTEN : 1; /**< Global Enable for the RTC */ + unsigned int ALMEN : 1; /**< Enable the RTC Alarm (Absolute) Operation */ + unsigned int ALMINTEN : 1; /**< Enable ALMINT Sourced Alarm Interrupts to the CPU */ + unsigned int TRMEN : 1; /**< Enable RTC Digital Trimming */ + unsigned int MOD60ALMEN : 1; /**< Enable RTC Modulo-60 Counting of Time Past a Modulo-60 Boundary */ + unsigned int MOD60ALM : 6; /**< Periodic, Modulo-60 Alarm Time in Prescaled RTC Time Units Beyond a Modulo-60 Boundary */ + unsigned int MOD60ALMINTEN : 1; /**< Enable Periodic Modulo-60 RTC Alarm Sourced Interrupts to the CPU */ + unsigned int ISOINTEN : 1; /**< Enable ISOINT Sourced Interrupts to the CPU When Isolation of the RTC Power Domain is Activated and Subsequently De-activated */ + unsigned int WPNDERRINTEN : 1; /**< Enable Write Pending Error Sourced Interrupts to the CPU When an RTC Register-write Pending Error Occurs */ + unsigned int WSYNCINTEN : 1; /**< Enable Write Synchronization Sourced Interrupts to the CPU */ + unsigned int WPNDINTEN : 1; /**< Enable Write Pending Sourced Interrupts to the CPU */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR0_t__ */ + +/*@}*/ + +/** @defgroup SR0 RTC Status 0 (SR0) Register + * RTC Status 0 (SR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR0_Struct + *! \brief RTC Status 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ +typedef struct _ADI_RTC_SR0_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int ALMINT : 1; /**< Alarm Interrupt Source */ + unsigned int MOD60ALMINT : 1; /**< Modulo-60 RTC Alarm Interrupt Source */ + unsigned int ISOINT : 1; /**< RTC Power-Domain Isolation Interrupt Source */ + unsigned int WPNDERRINT : 1; /**< Write Pending Error Interrupt Source */ + unsigned int WSYNCINT : 1; /**< Write Synchronisation Interrupt */ + unsigned int WPNDINT : 1; /**< Write Pending Interrupt */ + unsigned int WSYNCCR0 : 1; /**< Synchronisation Status of Posted Writes to CR0 */ + unsigned int WSYNCSR0 : 1; /**< Synchronisation Status of Posted Writes to SR0 */ + unsigned int WSYNCCNT0 : 1; /**< Synchronisation Status of Posted Writes to CNT0 */ + unsigned int WSYNCCNT1 : 1; /**< Synchronisation Status of Posted Writes to CNT1 */ + unsigned int WSYNCALM0 : 1; /**< Synchronisation Status of Posted Writes to ALM0 */ + unsigned int WSYNCALM1 : 1; /**< Synchronisation Status of Posted Writes to ALM1 */ + unsigned int WSYNCTRM : 1; /**< Synchronisation Status of Posted Writes to TRM */ + unsigned int ISOENB : 1; /**< Visibility of 32kHz Sourced Registers */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR0_t__ */ + +/*@}*/ + +/** @defgroup SR1 RTC Status 1 (SR1) Register + * RTC Status 1 (SR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR1_Struct + *! \brief RTC Status 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ +typedef struct _ADI_RTC_SR1_t { + union { + struct { + unsigned int reserved0 : 7; + unsigned int WPNDCR0 : 1; /**< Pending Status of Posted Writes to CR0 */ + unsigned int WPNDSR0 : 1; /**< Pending Status of Posted Clearances of Interrupt Sources in SR0 */ + unsigned int WPNDCNT0 : 1; /**< Pending Status of Posted Writes to CNT0 */ + unsigned int WPNDCNT1 : 1; /**< Pending Status of Posted Writes to CNT1 */ + unsigned int WPNDALM0 : 1; /**< Pending Status of Posted Writes to ALM0 */ + unsigned int WPNDALM1 : 1; /**< Pending Status of Posted Writes to ALM1 */ + unsigned int WPNDTRM : 1; /**< Pending Status of Posted Writes to TRM */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR1_t__ */ + +/*@}*/ + +/** @defgroup CNT0 RTC Count 0 (CNT0) Register + * RTC Count 0 (CNT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT0_Struct + *! \brief RTC Count 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ +typedef struct _ADI_RTC_CNT0_t { + union { + struct { + unsigned int VALUE : 16; /**< Lower 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT0_t__ */ + +/*@}*/ + +/** @defgroup CNT1 RTC Count 1 (CNT1) Register + * RTC Count 1 (CNT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT1_Struct + *! \brief RTC Count 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ +typedef struct _ADI_RTC_CNT1_t { + union { + struct { + unsigned int VALUE : 16; /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Real-Time Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT1_t__ */ + +/*@}*/ + +/** @defgroup ALM0 RTC Alarm 0 (ALM0) Register + * RTC Alarm 0 (ALM0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM0_Struct + *! \brief RTC Alarm 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ +typedef struct _ADI_RTC_ALM0_t { + union { + struct { + unsigned int VALUE : 16; /**< Lower 16 Prescaled (i.e. Non-Fractional) Bits of the RTC Alarm Target Time */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM0_t__ */ + +/*@}*/ + +/** @defgroup ALM1 RTC Alarm 1 (ALM1) Register + * RTC Alarm 1 (ALM1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM1_Struct + *! \brief RTC Alarm 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ +typedef struct _ADI_RTC_ALM1_t { + union { + struct { + unsigned int VALUE : 16; /**< Upper 16 Prescaled (Non-Fractional) Bits of the RTC Alarm Target Time */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM1_t__ */ + +/*@}*/ + +/** @defgroup TRM RTC Trim (TRM) Register + * RTC Trim (TRM) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_TRM_Struct + *! \brief RTC Trim Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ +typedef struct _ADI_RTC_TRM_t { + union { + struct { + unsigned int VALUE : 3; /**< Trim Value in Prescaled RTC Time Units to Be Added or Subtracted from the RTC Count at the End of a Periodic Interval Selected by TRM:TRMIVL */ + unsigned int ADD : 1; /**< Trim Polarity */ + unsigned int IVL : 2; /**< Trim Interval in Prescaled RTC Time Units */ + unsigned int IVL2EXPMIN : 4; /**< Minimum Power-of-two Interval of Prescaled RTC Time Units Which TRM:TRMIVL TRMIVL Can Select */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_RTC_TRM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_TRM_t__ */ + +/*@}*/ + +/** @defgroup GWY RTC Gateway (GWY) Register + * RTC Gateway (GWY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GWY_Struct + *! \brief RTC Gateway Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ +typedef struct _ADI_RTC_GWY_t { + union { + struct { + unsigned int SWKEY : 16; /**< Software-keyed Command Issued by the CPU */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_GWY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GWY_t__ */ + +/*@}*/ + +/** @defgroup CR1 RTC Control 1 (CR1) Register + * RTC Control 1 (CR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR1_Struct + *! \brief RTC Control 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ +typedef struct _ADI_RTC_CR1_t { + union { + struct { + unsigned int CNTINTEN : 1; /**< Enable for the RTC Count Interrupt Source */ + unsigned int PSINTEN : 1; /**< Enable for the Prescaled, Modulo-1 Interrupt Source, in SR2:RTCPSINT */ + unsigned int TRMINTEN : 1; /**< Enable for the RTC Trim Interrupt Source, in SR2:RTCTRMINT */ + unsigned int CNTROLLINTEN : 1; /**< Enable for the RTC Count Roll-Over Interrupt Source, in SR2:RTCCNTROLLINT */ + unsigned int CNTMOD60ROLLINTEN : 1; /**< Enable for the RTC Modulo-60 Count Roll-Over Interrupt Source, in SR2:RTCCNTMOD60ROLLINT */ + unsigned int PRESCALE2EXP : 4; /**< Prescale Power of 2 Division Factor for the RTC Base Clock */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR1_t__ */ + +/*@}*/ + +/** @defgroup SR2 RTC Status 2 (SR2) Register + * RTC Status 2 (SR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR2_Struct + *! \brief RTC Status 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ +typedef struct _ADI_RTC_SR2_t { + union { + struct { + unsigned int CNTINT : 1; /**< RTC Count Interrupt Source */ + unsigned int PSINT : 1; /**< RTC Prescaled, Modulo-1 Boundary Interrupt Source */ + unsigned int TRMINT : 1; /**< RTC Trim Interrupt Source */ + unsigned int CNTROLLINT : 1; /**< RTC Count Roll-Over Interrupt Source */ + unsigned int CNTMOD60ROLLINT : 1; /**< RTC Modulo-60 Count Roll-Over Interrupt Source */ + unsigned int CNTROLL : 1; /**< RTC Count Roll-Over */ + unsigned int CNTMOD60ROLL : 1; /**< RTC Count Modulo-60 Roll-Over */ + unsigned int TRMBDYMIR : 1; /**< Mirror of MOD:RTCTRMBDY */ + unsigned int reserved8 : 4; + unsigned int WPNDCR1MIR : 1; /**< Pending Status of Posted Writes to CR1 */ + unsigned int WPNDALM2MIR : 1; /**< Pending Status of Posted Writes to ALM2 */ + unsigned int WSYNCCR1MIR : 1; /**< Synchronization Status of Posted Writes to CR1 */ + unsigned int WSYNCALM2MIR : 1; /**< Synchronization Status of Posted Writes to ALM2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR2_t__ */ + +/*@}*/ + +/** @defgroup SNAP0 RTC Snapshot 0 (SNAP0) Register + * RTC Snapshot 0 (SNAP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP0_Struct + *! \brief RTC Snapshot 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ +typedef struct _ADI_RTC_SNAP0_t { + union { + struct { + unsigned int VALUE : 16; /**< Constituent Part of the 47-bit Input Capture Channel 0, Containing a Sticky Snapshot of CNT0 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP0_t__ */ + +/*@}*/ + +/** @defgroup SNAP1 RTC Snapshot 1 (SNAP1) Register + * RTC Snapshot 1 (SNAP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP1_Struct + *! \brief RTC Snapshot 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ +typedef struct _ADI_RTC_SNAP1_t { + union { + struct { + unsigned int VALUE : 16; /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP1_t__ */ + +/*@}*/ + +/** @defgroup SNAP2 RTC Snapshot 2 (SNAP2) Register + * RTC Snapshot 2 (SNAP2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SNAP2_Struct + *! \brief RTC Snapshot 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ +typedef struct _ADI_RTC_SNAP2_t { + union { + struct { + unsigned int VALUE : 15; /**< Part of the 47-bit Input Capture Channel 0 Containing a Sticky Snapshot of CNT2 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SNAP2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SNAP2_t__ */ + +/*@}*/ + +/** @defgroup MOD RTC Modulo (MOD) Register + * RTC Modulo (MOD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_MOD_Struct + *! \brief RTC Modulo Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ +typedef struct _ADI_RTC_MOD_t { + union { + struct { + unsigned int CNTMOD60 : 6; /**< Modulo-60 Value of the RTC Count: CNT1 and CNT0 */ + unsigned int INCR : 4; /**< Most Recent Increment Value Added to the RTC Count in CNT1 and CNT0 */ + unsigned int TRMBDY : 1; /**< Trim Boundary Indicator */ + unsigned int CNT0_4TOZERO : 5; /**< Mirror of CNT0[4:0] */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_MOD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_MOD_t__ */ + +/*@}*/ + +/** @defgroup CNT2 RTC Count 2 (CNT2) Register + * RTC Count 2 (CNT2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CNT2_Struct + *! \brief RTC Count 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ +typedef struct _ADI_RTC_CNT2_t { + union { + struct { + unsigned int VALUE : 15; /**< Fractional Bits of the RTC Real-Time Count */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CNT2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CNT2_t__ */ + +/*@}*/ + +/** @defgroup ALM2 RTC Alarm 2 (ALM2) Register + * RTC Alarm 2 (ALM2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_ALM2_Struct + *! \brief RTC Alarm 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ +typedef struct _ADI_RTC_ALM2_t { + union { + struct { + unsigned int VALUE : 15; /**< Fractional Bits of the Alarm Target Time */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_ALM2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_ALM2_t__ */ + +/*@}*/ + +/** @defgroup SR3 RTC Status 3 (SR3) Register + * RTC Status 3 (SR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR3_Struct + *! \brief RTC Status 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ +typedef struct _ADI_RTC_SR3_t { + union { + struct { + unsigned int IC0IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 2 */ + unsigned int IC3IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 3 */ + unsigned int IC4IRQ : 1; /**< Sticky Interrupt Source for the RTC Input Capture Channel 4 */ + unsigned int SS1FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 1 Falling Edge */ + unsigned int SS2FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 2 Falling Edge */ + unsigned int SS3FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 3 Falling Edge */ + unsigned int SS4FEIRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 4 Falling Edge */ + unsigned int SS1IRQ : 1; /**< Sticky Interrupt Source for SensorStrobe Channel 1 */ + unsigned int SS2IRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 2 */ + unsigned int SS3IRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 3 */ + unsigned int SS4IRQ : 1; /**< Sticky Interrupt Source for the SensorStrobe Channel 4 */ + unsigned int ALMINTMIR : 1; /**< Read-only Mirror of the SR0:ALMINT Interrupt Source */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR3_t__ */ + +/*@}*/ + +/** @defgroup CR2IC RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register + * RTC Control 2 for Configuring Input Capture Channels (CR2IC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR2IC_Struct + *! \brief RTC Control 2 for Configuring Input Capture Channels Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ +typedef struct _ADI_RTC_CR2IC_t { + union { + struct { + unsigned int IC0EN : 1; /**< Enable for the RTC Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2EN : 1; /**< Enable for the RTC Input Capture Channel 2 */ + unsigned int IC3EN : 1; /**< Enable for the RTC Input Capture Channel 3 */ + unsigned int IC4EN : 1; /**< Enable for the RTC Input Capture Channel 4 */ + unsigned int IC0LH : 1; /**< Polarity of the Active-Going Capture Edge for the RTC Input Capture Channel 0 */ + unsigned int reserved6 : 1; + unsigned int IC2LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 2 */ + unsigned int IC3LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 3 */ + unsigned int IC4LH : 1; /**< Polarity of the Active-going Capture Edge for the Input Capture Channel 4 */ + unsigned int IC0IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 0 */ + unsigned int reserved11 : 1; + unsigned int IC2IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 2 */ + unsigned int IC3IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 3 */ + unsigned int IC4IRQEN : 1; /**< Interrupt Enable for the RTC Input Capture Channel 4 */ + unsigned int ICOWUSEN : 1; /**< Enable Overwrite of Unread Snapshots for All Input Capture Channels */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR2IC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR2IC_t__ */ + +/*@}*/ + +/** @defgroup CR3SS RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register + * RTC Control 3 for Configuring SensorStrobe Channel (CR3SS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR3SS_Struct + *! \brief RTC Control 3 for Configuring SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ +typedef struct _ADI_RTC_CR3SS_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SS1EN : 1; /**< Enable for SensorStrobe Channel 1 */ + unsigned int SS2EN : 1; /**< Enable for the SensorStrobe Channel 2 */ + unsigned int SS3EN : 1; /**< Enable for the SensorStrobe Channel 3 */ + unsigned int SS4EN : 1; /**< Enable for the SensorStrobe Channel 4 */ + unsigned int SS1FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 1 */ + unsigned int SS2FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 2 */ + unsigned int SS3FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 3 */ + unsigned int SS4FEIRQEN : 1; /**< Falling Edge Interrupt Enable for the SensorStrobe Channel 4 */ + unsigned int SS1IRQEN : 1; /**< Interrupt Enable for SensorStrobe Channel 1 */ + unsigned int SS2IRQEN : 1; /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 2 */ + unsigned int SS3IRQEN : 1; /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 3 */ + unsigned int SS4IRQEN : 1; /**< Posedge EdgeInterrupt Enable for the SensorStrobe Channel 4 */ + unsigned int reserved13 : 3; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR3SS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR3SS_t__ */ + +/*@}*/ + +/** @defgroup CR4SS RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register + * RTC Control 4 for Configuring SensorStrobe Channel (CR4SS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR4SS_SS1MSKEN + *! \brief Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 (SS1MSKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR4SS_NO_MSK = 0, /**< Do not apply a mask to SensorStrobe Channel 1 Register */ + RTC_CR4SS_THERM_MSK = 1 /**< Apply thermometer decoded mask */ +} ADI_RTC_CR4SS_SS1MSKEN; + + +/* ========================================================================== + *! \struct ADI_RTC_CR4SS_Struct + *! \brief RTC Control 4 for Configuring SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ +typedef struct _ADI_RTC_CR4SS_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SS1MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 1 */ + unsigned int SS2MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 2 */ + unsigned int SS3MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 3 */ + unsigned int SS4MSKEN : 1; /**< Enable for Thermometer-Code Masking of the SensorStrobe Channel 4 */ + unsigned int SS1POL : 1; /**< SensorSTrobe Channel 1 Polarity Control */ + unsigned int SS2POL : 1; /**< SensorStrobe Channel 2 Polarity Control */ + unsigned int SS3POL : 1; /**< SensorStrobe Channel 3 Polarity Control */ + unsigned int SS4POL : 1; /**< SensorStrobe Channel 4 Polarity Control */ + unsigned int SS1ARLEN : 1; /**< Enable for Fine Control on SensorStrobe Channel 1 Period and Duty Cycle */ + unsigned int SS2ARLEN : 1; /**< Enable for Fine Control on SensorStrobe Channel 2 Period and Duty Cycle */ + unsigned int SS3ARLEN : 1; /**< Enable for Fine Control on SensorStrobe Channel 3 Period and Duty Cycle */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR4SS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR4SS_t__ */ + +/*@}*/ + +/** @defgroup SSMSK RTC Mask for SensorStrobe Channel (SSMSK) Register + * RTC Mask for SensorStrobe Channel (SSMSK) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SSMSK_Struct + *! \brief RTC Mask for SensorStrobe Channel Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ +typedef struct _ADI_RTC_SSMSK_t { + union { + struct { + unsigned int SS1MSK : 4; /**< Concatenation of Thermometer-Encoded Masks for the 16-bit SensorStrobe Channels */ + unsigned int SS2MSK : 4; /**< SensorStrobe Channel 2 Period Control */ + unsigned int SS3MSK : 4; /**< SensorStrobe Channel 3 Period Control */ + unsigned int SS4MSK : 4; /**< SensorStrobe Channel 4 Period Control */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SSMSK_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSK_t__ */ + +/*@}*/ + +/** @defgroup IC2 RTC Input Capture Channel 2 (IC2) Register + * RTC Input Capture Channel 2 (IC2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC2_Struct + *! \brief RTC Input Capture Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ +typedef struct _ADI_RTC_IC2_t { + union { + struct { + unsigned int IC2 : 16; /**< RTC Input Capture Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC2_t__ */ + +/*@}*/ + +/** @defgroup IC3 RTC Input Capture Channel 3 (IC3) Register + * RTC Input Capture Channel 3 (IC3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC3_Struct + *! \brief RTC Input Capture Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ +typedef struct _ADI_RTC_IC3_t { + union { + struct { + unsigned int IC3 : 16; /**< RTC Input Capture Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC3_t__ */ + +/*@}*/ + +/** @defgroup IC4 RTC Input Capture Channel 4 (IC4) Register + * RTC Input Capture Channel 4 (IC4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_IC4_Struct + *! \brief RTC Input Capture Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ +typedef struct _ADI_RTC_IC4_t { + union { + struct { + unsigned int IC4 : 16; /**< RTC Input Capture Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_IC4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_IC4_t__ */ + +/*@}*/ + +/** @defgroup SS1 RTC SensorStrobe Channel 1 (SS1) Register + * RTC SensorStrobe Channel 1 (SS1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1_Struct + *! \brief RTC SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ +typedef struct _ADI_RTC_SS1_t { + union { + struct { + unsigned int SS1 : 16; /**< SensorStrobe Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1_t__ */ + +/*@}*/ + +/** @defgroup SS2 RTC SensorStrobe Channel 2 (SS2) Register + * RTC SensorStrobe Channel 2 (SS2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2_Struct + *! \brief RTC SensorStrobe Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2_t__ +typedef struct _ADI_RTC_SS2_t { + union { + struct { + unsigned int SS2 : 16; /**< SensorStrobe Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2_t__ */ + +/*@}*/ + +/** @defgroup SS3 RTC SensorStrobe Channel 3 (SS3) Register + * RTC SensorStrobe Channel 3 (SS3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3_Struct + *! \brief RTC SensorStrobe Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3_t__ +typedef struct _ADI_RTC_SS3_t { + union { + struct { + unsigned int SS3 : 16; /**< SensorStrobe Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3_t__ */ + +/*@}*/ + +/** @defgroup SS4 RTC SensorStrobe Channel 4 (SS4) Register + * RTC SensorStrobe Channel 4 (SS4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS4_Struct + *! \brief RTC SensorStrobe Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS4_t__ +typedef struct _ADI_RTC_SS4_t { + union { + struct { + unsigned int SS4 : 16; /**< SensorStrobe Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS4_t__ */ + +/*@}*/ + +/** @defgroup SR4 RTC Status 4 (SR4) Register + * RTC Status 4 (SR4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR4_Struct + *! \brief RTC Status 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ +typedef struct _ADI_RTC_SR4_t { + union { + struct { + unsigned int WSYNCSR3 : 1; /**< Synchronisation Status of Posted Writes to SR3 */ + unsigned int WSYNCCR2IC : 1; /**< Synchronization Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ + unsigned int WSYNCCR3SS : 1; /**< Synchronization Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR4SS : 1; /**< Synchronization Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCSSMSK : 1; /**< Synchronization Status of Posted Writes to Masks for SensorStrobe Channel Register */ + unsigned int reserved5 : 1; + unsigned int WSYNCSS1 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 1 */ + unsigned int WSYNCSS2 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 2 */ + unsigned int WSYNCSS3 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 3 */ + unsigned int WSYNCSS4 : 1; /**< Synchronization Status of Posted Writes to SensorStrobe Channel 4 */ + unsigned int RSYNCIC0 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 0 */ + unsigned int reserved11 : 1; + unsigned int RSYNCIC2 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 2 */ + unsigned int RSYNCIC3 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 3 */ + unsigned int RSYNCIC4 : 1; /**< Synchronization Status of Posted Reads of RTC Input Channel 4 */ + unsigned int WSYNCSSMSKOT : 1; /**< Synchronization Status of Posted Reads Writes to Mask for SensorStrobe Channels on Time Control Register */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR4_t__ */ + +/*@}*/ + +/** @defgroup SR5 RTC Status 5 (SR5) Register + * RTC Status 5 (SR5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR5_Struct + *! \brief RTC Status 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ +typedef struct _ADI_RTC_SR5_t { + union { + struct { + unsigned int WPENDSR3 : 1; /**< Pending Status of Posted Clearances of Interrupt Sources in RTC Status 3 Register */ + unsigned int WPENDCR2IC : 1; /**< Pending Status of Posted Writes to RTC Control 2 for Configuring Input Capture Channels Register */ + unsigned int WPENDCR3SS : 1; /**< Pending Status of Posted Writes to RTC Control 3 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR4SS : 1; /**< Pending Status of Posted Writes to RTC Control 4 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDSSMSK : 1; /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ + unsigned int reserved5 : 1; + unsigned int WPENDSS1 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 1 */ + unsigned int WPENDSS2 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 2 */ + unsigned int WPENDSS3 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 3 */ + unsigned int WPENDSS4 : 1; /**< Pending Status of Posted Writes to SensorStrobe Channel 4 */ + unsigned int RPENDIC0 : 1; /**< Pending Status of Posted Reads of Input Capture Channel 0 */ + unsigned int reserved11 : 1; + unsigned int RPENDIC2 : 1; /**< Pending Status of Posted Reads of IC2 */ + unsigned int RPENDIC3 : 1; /**< Pending Status of Posted Reads of IC3 */ + unsigned int RPENDIC4 : 1; /**< Pending Status of Posted Reads of IC4 */ + unsigned int WPENDSSMSKOT : 1; /**< Pending Status of Posted Writes to RTC Masks for SensorStrobe Channel Register */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR5_t__ */ + +/*@}*/ + +/** @defgroup SR6 RTC Status 6 (SR6) Register + * RTC Status 6 (SR6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR6_Struct + *! \brief RTC Status 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ +typedef struct _ADI_RTC_SR6_t { + union { + struct { + unsigned int IC0UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 0 */ + unsigned int reserved1 : 1; + unsigned int IC2UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 2 */ + unsigned int IC3UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 3 */ + unsigned int IC4UNR : 1; /**< Sticky Unread Status of the Input Capture Channel 4 */ + unsigned int reserved5 : 3; + unsigned int IC0SNAP : 1; /**< Confirmation That RTC Snapshot 0, 1, 2 Registers Reflect the Value of Input-Capture Channel RTC Input Capture Channel 0 */ + unsigned int FRZCNTPTR : 2; /**< Pointer for the Triple-Read Sequence of FRZCNT */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR6_t__ */ + +/*@}*/ + +/** @defgroup SS1TGT RTC SensorStrobe Channel 1 Target (SS1TGT) Register + * RTC SensorStrobe Channel 1 Target (SS1TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1TGT_Struct + *! \brief RTC SensorStrobe Channel 1 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ +typedef struct _ADI_RTC_SS1TGT_t { + union { + struct { + unsigned int SS1TGT : 16; /**< Current Target Value for the SensorStrobe Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1TGT_t__ */ + +/*@}*/ + +/** @defgroup FRZCNT RTC Freeze Count (FRZCNT) Register + * RTC Freeze Count (FRZCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_FRZCNT_Struct + *! \brief RTC Freeze Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ +typedef struct _ADI_RTC_FRZCNT_t { + union { + struct { + unsigned int FRZCNT : 16; /**< RTC Freeze Count. Coherent, Triple 16-Bit Read of the 47-Bit RTC Count */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_FRZCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_FRZCNT_t__ */ + +/*@}*/ + +/** @defgroup SS2TGT RTC SensorStrobe Channel 2 Target (SS2TGT) Register + * RTC SensorStrobe Channel 2 Target (SS2TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2TGT_Struct + *! \brief RTC SensorStrobe Channel 2 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2TGT_t__ +typedef struct _ADI_RTC_SS2TGT_t { + union { + struct { + unsigned int SS2TGT : 16; /**< Current, Cumulative Target Time for SensorStrobe Channel 2, Taking Account of Any Auto-reloading */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2TGT_t__ */ + +/*@}*/ + +/** @defgroup SS3TGT RTC SensorStrobe Channel 3 Target (SS3TGT) Register + * RTC SensorStrobe Channel 3 Target (SS3TGT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3TGT_Struct + *! \brief RTC SensorStrobe Channel 3 Target Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3TGT_t__ +typedef struct _ADI_RTC_SS3TGT_t { + union { + struct { + unsigned int SS3TGT : 16; /**< Current, Cumulative Target Time for SensorStrobe Channel 3, Taking Account of Any Auto-reloading */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3TGT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3TGT_t__ */ + +/*@}*/ + +/** @defgroup SS1LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 1 (SS1LOWDUR) Register + * RTC Auto-Reload Low Duration for SensorStrobe Channel 1 (SS1LOWDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1LOWDUR_Struct + *! \brief RTC Auto-Reload Low Duration for SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1LOWDUR_t__ +typedef struct _ADI_RTC_SS1LOWDUR_t { + union { + struct { + unsigned int SS1LOWDUR : 16; /**< Low Duration for SensorStrobe Channel 1. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1LOWDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1LOWDUR_t__ */ + +/*@}*/ + +/** @defgroup SS2LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 2 (SS2LOWDUR) Register + * RTC Auto-Reload Low Duration for SensorStrobe Channel 2 (SS2LOWDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2LOWDUR_Struct + *! \brief RTC Auto-Reload Low Duration for SensorStrobe Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2LOWDUR_t__ +typedef struct _ADI_RTC_SS2LOWDUR_t { + union { + struct { + unsigned int SS2LOWDUR : 16; /**< Low Duration for SensorStrobe Channel 2. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2LOWDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2LOWDUR_t__ */ + +/*@}*/ + +/** @defgroup SS3LOWDUR RTC Auto-Reload Low Duration for SensorStrobe Channel 3 (SS3LOWDUR) Register + * RTC Auto-Reload Low Duration for SensorStrobe Channel 3 (SS3LOWDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3LOWDUR_Struct + *! \brief RTC Auto-Reload Low Duration for SensorStrobe Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3LOWDUR_t__ +typedef struct _ADI_RTC_SS3LOWDUR_t { + union { + struct { + unsigned int SS3LOWDUR : 16; /**< Low Duration for SensorStrobe Channel 3. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3LOWDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3LOWDUR_t__ */ + +/*@}*/ + +/** @defgroup SS1HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 1 (SS1HIGHDUR) Register + * RTC Auto-Reload High Duration for SensorStrobe Channel 1 (SS1HIGHDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS1HIGHDUR_Struct + *! \brief RTC Auto-Reload High Duration for SensorStrobe Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS1HIGHDUR_t__ +typedef struct _ADI_RTC_SS1HIGHDUR_t { + union { + struct { + unsigned int SS1HIGHDUR : 16; /**< High Duration for SensorStrobe Channel 1. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS1HIGHDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS1HIGHDUR_t__ */ + +/*@}*/ + +/** @defgroup SS2HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 2 (SS2HIGHDUR) Register + * RTC Auto-Reload High Duration for SensorStrobe Channel 2 (SS2HIGHDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS2HIGHDUR_Struct + *! \brief RTC Auto-Reload High Duration for SensorStrobe Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS2HIGHDUR_t__ +typedef struct _ADI_RTC_SS2HIGHDUR_t { + union { + struct { + unsigned int SS2HIGHDUR : 16; /**< High Duration for SensorStrobe Channel 2. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS2HIGHDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS2HIGHDUR_t__ */ + +/*@}*/ + +/** @defgroup SS3HIGHDUR RTC Auto-Reload High Duration for SensorStrobe Channel 3 (SS3HIGHDUR) Register + * RTC Auto-Reload High Duration for SensorStrobe Channel 3 (SS3HIGHDUR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SS3HIGHDUR_Struct + *! \brief RTC Auto-Reload High Duration for SensorStrobe Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SS3HIGHDUR_t__ +typedef struct _ADI_RTC_SS3HIGHDUR_t { + union { + struct { + unsigned int SS3HIGHDUR : 16; /**< High Duration for SensorStrobe Channel 3. */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SS3HIGHDUR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SS3HIGHDUR_t__ */ + +/*@}*/ + +/** @defgroup SSMSKOT RTC Masks for SensorStrobe Channels on Time Control (SSMSKOT) Register + * RTC Masks for SensorStrobe Channels on Time Control (SSMSKOT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SSMSKOT_Struct + *! \brief RTC Masks for SensorStrobe Channels on Time Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SSMSKOT_t__ +typedef struct _ADI_RTC_SSMSKOT_t { + union { + struct { + unsigned int SS1MSKOT : 4; /**< Concatenation of Thermometer-encoded Masks for the 16-bit SensorStrobe Channels */ + unsigned int SS2MSKOT : 4; /**< SensorStrobe Channel 2 on Time Control */ + unsigned int SS3MSKOT : 4; /**< SensorStrobe Channel 3 on Time Control */ + unsigned int SS4MSKOT : 4; /**< SensorStrobe Channel 4 on Time Control */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SSMSKOT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SSMSKOT_t__ */ + +/*@}*/ + +/** @defgroup CR5SSS RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling (CR5SSS) Register + * RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling (CR5SSS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_CR5SSS_Struct + *! \brief RTC Control 5 for Configuring SensorStrobe Channel GPIO Sampling Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR5SSS_t__ +typedef struct _ADI_RTC_CR5SSS_t { + union { + struct { + unsigned int SS1SMPEN : 3; /**< GPIO Input Sample Enable for SensorStrobe Channel 1 */ + unsigned int SS1SMPMTCHIRQEN : 1; /**< Sample Activity Interrupt Enable for SensorStrobe Channel 1 */ + unsigned int SS2SMPEN : 3; /**< GPIO Input Sample Enable for SensorStrobe Channel 2 */ + unsigned int SS2SMPMTCHIRQEN : 1; /**< Sample Activity Interrupt Enable for SensorStrobe Channel 2 */ + unsigned int SS3SMPEN : 3; /**< GPIO Input Sample Enable for SensorStrobe Channel 3 */ + unsigned int SS3SMPMTCHIRQEN : 1; /**< Sample Activity Interrupt Enable for SensorStrobe Channel 3 */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR5SSS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR5SSS_t__ */ + +/*@}*/ + +/** @defgroup CR6SSS RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge (CR6SSS) Register + * RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge (CR6SSS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS1SMPONFE + *! \brief GPIO Sample Around Falling Edge of SensorStrobe Channel 1 (SS1SMPONFE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS1NOFES = 0, /**< No sampling of input around falling edge */ + RTC_CR6SSS_SS1BFES = 1, /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1FES = 2, /**< Input sampled at falling edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1AFES = 3 /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 1 */ +} ADI_RTC_CR6SSS_SS1SMPONFE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS1SMPONRE + *! \brief GPIO Sample Around Rising Edge of SensorStrobe Channel 1 (SS1SMPONRE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS1NORES = 0, /**< No sampling of input around rising edge */ + RTC_CR6SSS_SS1BRES = 1, /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1RES = 2, /**< Input sampled at rising edge of the SensorStrobe channel 1 */ + RTC_CR6SSS_SS1ARES = 3 /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 1 */ +} ADI_RTC_CR6SSS_SS1SMPONRE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS2SMPONFE + *! \brief GPIO Sample Around Falling Edge of SensorStrobe Channel 2 (SS2SMPONFE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS2NOFES = 0, /**< No sampling of input around falling edge */ + RTC_CR6SSS_SS2BFES = 1, /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2FES = 2, /**< Input sampled at falling edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2AFES = 3 /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 2 */ +} ADI_RTC_CR6SSS_SS2SMPONFE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS2SMPONRE + *! \brief GPIO Sample Around Rising Edge of SensorStrobe Channel 2 (SS2SMPONRE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS2NORES = 0, /**< No sampling of input around rising edge */ + RTC_CR6SSS_SS2BRES = 1, /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2RES = 2, /**< Input sampled at rising edge of the SensorStrobe channel 2 */ + RTC_CR6SSS_SS2ARES = 3 /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 2 */ +} ADI_RTC_CR6SSS_SS2SMPONRE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS3SMPONFE + *! \brief GPIO Sample Around Falling Edge of SensorStrobe Channel 3 (SS3SMPONFE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS3NOFES = 0, /**< No sampling of input around falling edge */ + RTC_CR6SSS_SS3BFES = 1, /**< Input sampled one clock cycle before falling edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3FES = 2, /**< Input sampled at falling edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3AFES = 3 /**< Input sampled one clock cycle after falling edge of the SensorStrobe channel 3 */ +} ADI_RTC_CR6SSS_SS3SMPONFE; + + +/* ========================================================================= + *! \enum ADI_RTC_CR6SSS_SS3SMPONRE + *! \brief GPIO Sample Around Rising Edge of SensorStrobe Channel 3 (SS3SMPONRE) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR6SSS_SS3NORES = 0, /**< No sampling of input around rising edge */ + RTC_CR6SSS_SS3BRES = 1, /**< Input sampled one clock cycle before rising edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3RES = 2, /**< Input sampled at rising edge of the SensorStrobe channel 3 */ + RTC_CR6SSS_SS3ARES = 3 /**< Input sampled one clock cycle after rising edge of the SensorStrobe channel 3 */ +} ADI_RTC_CR6SSS_SS3SMPONRE; + + +/* ========================================================================== + *! \struct ADI_RTC_CR6SSS_Struct + *! \brief RTC Control 6 for Configuring SensorStrobe Channel GPIO Sampling Edge Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR6SSS_t__ +typedef struct _ADI_RTC_CR6SSS_t { + union { + struct { + unsigned int SS1SMPONFE : 2; /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 1 */ + unsigned int SS1SMPONRE : 2; /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 1 */ + unsigned int SS2SMPONFE : 2; /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 2 */ + unsigned int SS2SMPONRE : 2; /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 2 */ + unsigned int SS3SMPONFE : 2; /**< GPIO Sample Around Falling Edge of SensorStrobe Channel 3 */ + unsigned int SS3SMPONRE : 2; /**< GPIO Sample Around Rising Edge of SensorStrobe Channel 3 */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR6SSS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR6SSS_t__ */ + +/*@}*/ + +/** @defgroup CR7SSS RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity (CR7SSS) Register + * RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity (CR7SSS) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RTC_CR7SSS_SS1SMPPTRN + *! \brief Sample Activity Selection for SensorStrobe Channel 1 (SS1SMPPTRN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR7SSS_SS1SMPCHNG = 0, /**< Current GPIO sample is not same as previous sample */ + RTC_CR7SSS_SS1SMPSAME = 1, /**< Current GPIO sample is same as previous sample */ + RTC_CR7SSS_SS1SMPMTCH = 2, /**< Current GPIO sample is same as expected sample */ + RTC_CR7SSS_SS1SMPNOMTCH = 3 /**< Current GPIO sample is not same as expected sample */ +} ADI_RTC_CR7SSS_SS1SMPPTRN; + + +/* ========================================================================= + *! \enum ADI_RTC_CR7SSS_SS2SMPPTRN + *! \brief Sample Activity Selection for SensorStrobe Channel 2 (SS2SMPPTRN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR7SSS_SS2SMPCHNG = 0, /**< Current GPIO sample is not same as previous sample */ + RTC_CR7SSS_SS2SMPSAME = 1, /**< Current GPIO sample is same as previous sample */ + RTC_CR7SSS_SS2SMPMTCH = 2, /**< Current GPIO sample is same as expected sample */ + RTC_CR7SSS_SS2SMPNOMTCH = 3 /**< Current GPIO sample is not same as expected sample */ +} ADI_RTC_CR7SSS_SS2SMPPTRN; + + +/* ========================================================================= + *! \enum ADI_RTC_CR7SSS_SS3SMPPTRN + *! \brief Sample Activity Selection for SensorStrobe Channel 3 (SS3SMPPTRN) Enumerations + * ========================================================================= */ +typedef enum +{ + RTC_CR7SSS_SS3SMPCHNG = 0, /**< Current GPIO sample is not same as previous sample */ + RTC_CR7SSS_SS3SMPSAME = 1, /**< Current GPIO sample is same as previous sample */ + RTC_CR7SSS_SS3SMPMTCH = 2, /**< Current GPIO sample is same as expected sample */ + RTC_CR7SSS_SS3SMPNOMTCH = 3 /**< Current GPIO sample is not same as expected sample */ +} ADI_RTC_CR7SSS_SS3SMPPTRN; + + +/* ========================================================================== + *! \struct ADI_RTC_CR7SSS_Struct + *! \brief RTC Control 7 for Configuring SensorStrobe Channel GPIO Sampling Activity Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_CR7SSS_t__ +typedef struct _ADI_RTC_CR7SSS_t { + union { + struct { + unsigned int SS1SMPEXP : 3; /**< Expected GPIO Sample for SensorStrobe Channel 1 */ + unsigned int SS1SMPPTRN : 2; /**< Sample Activity Selection for SensorStrobe Channel 1 */ + unsigned int SS2SMPEXP : 3; /**< Expected GPIO Sample for SensorStrobe Channel 2 */ + unsigned int SS2SMPPTRN : 2; /**< Sample Activity Selection for SensorStrobe Channel 2 */ + unsigned int SS3SMPEXP : 3; /**< Expected GPIO Sample for SensorStrobe Channel 3 */ + unsigned int SS3SMPPTRN : 2; /**< Sample Activity Selection for SensorStrobe Channel 3 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_CR7SSS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_CR7SSS_t__ */ + +/*@}*/ + +/** @defgroup SR7 RTC Status 7 (SR7) Register + * RTC Status 7 (SR7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR7_Struct + *! \brief RTC Status 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR7_t__ +typedef struct _ADI_RTC_SR7_t { + union { + struct { + unsigned int SS1SMP : 3; /**< Latest GPIO Sample for SensorStrobe Channel 1 */ + unsigned int SS1SMPMTCHIRQ : 1; /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 1 */ + unsigned int SS2SMP : 3; /**< Latest GPIO Sample for SensorStrobe Channel 2 */ + unsigned int SS2SMPMTCHIRQ : 1; /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 2 */ + unsigned int SS3SMP : 3; /**< Latest GPIO Sample for SensorStrobe Channel 3 */ + unsigned int SS3SMPMTCHIRQ : 1; /**< Sticky Status of GPIO Sample Pattern Match for SensorStrobe Channel 3 */ + unsigned int SS1OUT : 1; /**< Output Value for SensorStrobe Channel 1 */ + unsigned int SS2OUT : 1; /**< Output Value for SensorStrobe Channel 2 */ + unsigned int SS3OUT : 1; /**< Output Value for SensorStrobe Channel 3 */ + unsigned int SS4OUT : 1; /**< Output Value for SensorStrobe Channel 4 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR7_t__ */ + +/*@}*/ + +/** @defgroup SR8 RTC Status 8 (SR8) Register + * RTC Status 8 (SR8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR8_Struct + *! \brief RTC Status 8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR8_t__ +typedef struct _ADI_RTC_SR8_t { + union { + struct { + unsigned int WSYNCSS1LOWDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 1 Low Duration Register */ + unsigned int WSYNCSS2LOWDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 2 Low Duration Register */ + unsigned int WSYNCSS3LOWDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 3 Low Duration Register */ + unsigned int reserved3 : 1; + unsigned int WSYNCSS1HIGHDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 1 High Duration Register */ + unsigned int WSYNCSS2HIGHDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 2 High Duration Register */ + unsigned int WSYNCSS3HIGHDUR : 1; /**< Synchronisation Status of Posted Writes to SensorStrobe Channel 3 High Duration Register */ + unsigned int reserved7 : 1; + unsigned int WSYNCCR5SSS : 1; /**< Synchronisation Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR6SSS : 1; /**< Synchronisation Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCCR7SSS : 1; /**< Synchronisation Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ + unsigned int WSYNCSR7 : 1; /**< Synchronisation Status of Posted Writes to Status 7 Register */ + unsigned int WSYNCGPMUX0 : 1; /**< Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 0 */ + unsigned int WSYNCGPMUX1 : 1; /**< Synchronisation Status of Posted Writes to GPIO Pin Mux Control Register 1 */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR8_t__ */ + +/*@}*/ + +/** @defgroup SR9 RTC Status 9 (SR9) Register + * RTC Status 9 (SR9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_SR9_Struct + *! \brief RTC Status 9 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_SR9_t__ +typedef struct _ADI_RTC_SR9_t { + union { + struct { + unsigned int WPENDSS1LOWDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 1 Low Duration Register */ + unsigned int WPENDSS2LOWDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 2 Low Duration Register */ + unsigned int WPENDSS3LOWDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 3 Low Duration Register */ + unsigned int reserved3 : 1; + unsigned int WPENDSS1HIGHDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 1 High Duration Register */ + unsigned int WPENDSS2HIGHDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 2 High Duration Register */ + unsigned int WPENDSS3HIGHDUR : 1; /**< Pending Status of Posted Writes to SensortStrobe Channel 3 High Duration Register */ + unsigned int reserved7 : 1; + unsigned int WPENDCR5SSS : 1; /**< Pending Status of Posted Writes to Control 5 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR6SSS : 1; /**< Pending Status of Posted Writes to Control 6 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDCR7SSS : 1; /**< Pending Status of Posted Writes to Control 7 for Configuring SensorStrobe Channel Register */ + unsigned int WPENDSR7 : 1; /**< Pending Status of Posted Writes to SR7 */ + unsigned int WPENDGPMUX0 : 1; /**< Pending Status of Posted Writes to GPMUX0 */ + unsigned int WPENDGPMUX1 : 1; /**< Pending Status of Posted Writes to GPMUX1 */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_RTC_SR9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_SR9_t__ */ + +/*@}*/ + +/** @defgroup GPMUX0 RTC GPIO Pin Mux Control Register 0 (GPMUX0) Register + * RTC GPIO Pin Mux Control Register 0 (GPMUX0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GPMUX0_Struct + *! \brief RTC GPIO Pin Mux Control Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX0_t__ +typedef struct _ADI_RTC_GPMUX0_t { + union { + struct { + unsigned int SS1GPIN0SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 1 Input0 */ + unsigned int SS1GPIN1SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 1 Input 1 */ + unsigned int SS1GPIN2SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 1 Input 2 */ + unsigned int SS2GPIN0SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 0 */ + unsigned int SS2GPIN1SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 1 */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_RTC_GPMUX0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX0_t__ */ + +/*@}*/ + +/** @defgroup GPMUX1 RTC GPIO Pin Mux Control Register 1 (GPMUX1) Register + * RTC GPIO Pin Mux Control Register 1 (GPMUX1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RTC_GPMUX1_Struct + *! \brief RTC GPIO Pin Mux Control Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX1_t__ +typedef struct _ADI_RTC_GPMUX1_t { + union { + struct { + unsigned int SS2GPIN2SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 2 Input 2 */ + unsigned int SS3GPIN0SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 0 */ + unsigned int SS3GPIN1SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 1 */ + unsigned int SS3GPIN2SEL : 3; /**< GPIO Mux Selection for SensorStrobe Channel 3 Input 2 */ + unsigned int reserved12 : 2; + unsigned int SS1DIFFOUT : 1; /**< Differential SensorStrobe Out Option for SensorStrobe Channel 1 */ + unsigned int SS3DIFFOUT : 1; /**< Differential SensorStrobe Out Option for SensorStrobe Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_RTC_GPMUX1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RTC_GPMUX1_t__ */ + +/*@}*/ + +/** @defgroup ADIID ADI Identification (ADIID) Register + * ADI Identification (ADIID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_ADIID_Struct + *! \brief ADI Identification Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ +typedef struct _ADI_SYS_ADIID_t { + union { + struct { + unsigned int VALUE : 16; /**< Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an Analog Devices implemented Cortex based part */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_ADIID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_ADIID_t__ */ + +/*@}*/ + +/** @defgroup CHIPID Chip Identifier (CHIPID) Register + * Chip Identifier (CHIPID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_CHIPID_Struct + *! \brief Chip Identifier Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ +typedef struct _ADI_SYS_CHIPID_t { + union { + struct { + unsigned int REV : 4; /**< Silicon revision */ + unsigned int PARTID : 12; /**< Part identifier */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_CHIPID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_CHIPID_t__ */ + +/*@}*/ + +/** @defgroup SWDEN Serial Wire Debug Enable (SWDEN) Register + * Serial Wire Debug Enable (SWDEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SYS_SWDEN_Struct + *! \brief Serial Wire Debug Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ +typedef struct _ADI_SYS_SWDEN_t { + union { + struct { + unsigned int VALUE : 16; /**< To enable SWD interface */ + }; + uint16_t VALUE16; + }; +} ADI_SYS_SWDEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SYS_SWDEN_t__ */ + +/*@}*/ + +/** @defgroup LOAD Load Value (LOAD) Register + * Load Value (LOAD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_LOAD_Struct + *! \brief Load Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ +typedef struct _ADI_WDT_LOAD_t { + union { + struct { + unsigned int VALUE : 16; /**< Load Value */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_LOAD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_LOAD_t__ */ + +/*@}*/ + +/** @defgroup CCNT Current Count Value (CCNT) Register + * Current Count Value (CCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_CCNT_Struct + *! \brief Current Count Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ +typedef struct _ADI_WDT_CCNT_t { + union { + struct { + unsigned int VALUE : 16; /**< Current Count Value */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_CCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CCNT_t__ */ + +/*@}*/ + +/** @defgroup CTL Control (CTL) Register + * Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_WDT_CTL_IRQ + *! \brief Timer Interrupt (IRQ) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_RST = 0, /**< WDT asserts reset when timed out */ + WDT_CTL_INT = 1 /**< WDT generates interrupt when timed out */ +} ADI_WDT_CTL_IRQ; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_PRE + *! \brief Prescaler (PRE) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_DIV1 = 0, /**< Source clock/1 */ + WDT_CTL_DIV16 = 1, /**< Source clock/16 */ + WDT_CTL_DIV256 = 2 /**< Source clock/256 (default) */ +} ADI_WDT_CTL_PRE; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_EN + *! \brief Timer Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_WDT_DIS = 0, /**< WDT not enabled */ + WDT_CTL_WDT_EN = 1 /**< WDT enabled */ +} ADI_WDT_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_WDT_CTL_MODE + *! \brief Timer Mode (MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + WDT_CTL_FREE_RUN = 0, /**< Free running mode */ + WDT_CTL_PERIODIC = 1 /**< Periodic mode */ +} ADI_WDT_CTL_MODE; + + +/* ========================================================================== + *! \struct ADI_WDT_CTL_Struct + *! \brief Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ +typedef struct _ADI_WDT_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int IRQ : 1; /**< Timer Interrupt */ + unsigned int PRE : 2; /**< Prescaler */ + unsigned int reserved4 : 1; + unsigned int EN : 1; /**< Timer Enable */ + unsigned int MODE : 1; /**< Timer Mode */ + unsigned int SPARE : 1; /**< Unused Spare Bit */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_WDT_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_CTL_t__ */ + +/*@}*/ + +/** @defgroup RESTART Clear Interrupt (RESTART) Register + * Clear Interrupt (RESTART) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_RESTART_Struct + *! \brief Clear Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ +typedef struct _ADI_WDT_RESTART_t { + union { + struct { + unsigned int CLRWORD : 16; /**< Clear Watchdog */ + }; + uint16_t VALUE16; + }; +} ADI_WDT_RESTART_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_RESTART_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_WDT_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ +typedef struct _ADI_WDT_STAT_t { + union { + struct { + unsigned int IRQ : 1; /**< WDT Interrupt */ + unsigned int CLRIRQ : 1; /**< Clear Interrupt Register Write Sync in Progress */ + unsigned int LOADING : 1; /**< Load Register Write Sync in Progress */ + unsigned int COUNTING : 1; /**< Control Register Write Sync in Progress */ + unsigned int LOCKED : 1; /**< Lock Status Bit */ + unsigned int RSTCTL : 1; /**< Reset Control Register Written and Locked */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_WDT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_WDT_STAT_t__ */ + +/*@}*/ + +/** @defgroup MCTL Master Control (MCTL) Register + * Master Control (MCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MCTL_Struct + *! \brief Master Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ +typedef struct _ADI_I2C_MCTL_t { + union { + struct { + unsigned int MASEN : 1; /**< Master Enable */ + unsigned int COMPLETE : 1; /**< Start Back-off Disable */ + unsigned int LOOPBACK : 1; /**< Internal Loopback Enable */ + unsigned int STRETCHSCL : 1; /**< Stretch SCL Enable */ + unsigned int IENMRX : 1; /**< Receive Request Interrupt Enable */ + unsigned int IENMTX : 1; /**< Transmit Request Interrupt Enable */ + unsigned int IENALOST : 1; /**< Arbitration Lost Interrupt Enable */ + unsigned int IENACK : 1; /**< ACK Not Received Interrupt Enable */ + unsigned int IENCMP : 1; /**< Transaction Completed (or Stop Detected) Interrupt Enable */ + unsigned int MXMITDEC : 1; /**< Decrement Master Tx FIFO Status When a Byte Txed */ + unsigned int MRXDMA : 1; /**< Enable Master Rx DMA Request */ + unsigned int MTXDMA : 1; /**< Enable Master Tx DMA Request */ + unsigned int BUSCLR : 1; /**< Bus-Clear Enable */ + unsigned int STOPBUSCLR : 1; /**< Prestop Bus Clear */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCTL_t__ */ + +/*@}*/ + +/** @defgroup MSTAT Master Status (MSTAT) Register + * Master Status (MSTAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_I2C_MSTAT_MTXF + *! \brief Master Transmit FIFO Status (MTXF) Enumerations + * ========================================================================= */ +typedef enum +{ + I2C_MSTAT_FIFO_EMPTY = 0, /**< FIFO Empty. */ + I2C_MSTAT_FIFO_1BYTE = 2, /**< 1 byte in FIFO. */ + I2C_MSTAT_FIFO_FULL = 3 /**< FIFO Full. */ +} ADI_I2C_MSTAT_MTXF; + + +/* ========================================================================== + *! \struct ADI_I2C_MSTAT_Struct + *! \brief Master Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ +typedef struct _ADI_I2C_MSTAT_t { + union { + struct { + unsigned int MTXF : 2; /**< Master Transmit FIFO Status */ + unsigned int MTXREQ : 1; /**< Master Transmit Request/Clear Master Transmit Interrupt */ + unsigned int MRXREQ : 1; /**< Master Receive Request */ + unsigned int NACKADDR : 1; /**< ACK Not Received in Response to an Address */ + unsigned int ALOST : 1; /**< Arbitration Lost */ + unsigned int MBUSY : 1; /**< Master Busy */ + unsigned int NACKDATA : 1; /**< ACK Not Received in Response to Data Write */ + unsigned int TCOMP : 1; /**< Transaction Complete or Stop Detected */ + unsigned int MRXOVR : 1; /**< Master Receive FIFO Overflow */ + unsigned int LINEBUSY : 1; /**< Line is Busy */ + unsigned int MSTOP : 1; /**< STOP Driven by This I2C Master */ + unsigned int MTXUNDR : 1; /**< Master Transmit Underflow */ + unsigned int SDAFILT : 1; /**< State of SDA Line */ + unsigned int SCLFILT : 1; /**< State of SCL Line */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MSTAT_t__ */ + +/*@}*/ + +/** @defgroup MRX Master Receive Data (MRX) Register + * Master Receive Data (MRX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MRX_Struct + *! \brief Master Receive Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ +typedef struct _ADI_I2C_MRX_t { + union { + struct { + unsigned int VALUE : 8; /**< Master Receive Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MRX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRX_t__ */ + +/*@}*/ + +/** @defgroup MTX Master Transmit Data (MTX) Register + * Master Transmit Data (MTX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MTX_Struct + *! \brief Master Transmit Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ +typedef struct _ADI_I2C_MTX_t { + union { + struct { + unsigned int VALUE : 8; /**< Master Transmit Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MTX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MTX_t__ */ + +/*@}*/ + +/** @defgroup MRXCNT Master Receive Data Count (MRXCNT) Register + * Master Receive Data Count (MRXCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MRXCNT_Struct + *! \brief Master Receive Data Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ +typedef struct _ADI_I2C_MRXCNT_t { + union { + struct { + unsigned int VALUE : 8; /**< Receive Count */ + unsigned int EXTEND : 1; /**< Extended Read */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MRXCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MRXCNT_t__ */ + +/*@}*/ + +/** @defgroup MCRXCNT Master Current Receive Data Count (MCRXCNT) Register + * Master Current Receive Data Count (MCRXCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_MCRXCNT_Struct + *! \brief Master Current Receive Data Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ +typedef struct _ADI_I2C_MCRXCNT_t { + union { + struct { + unsigned int VALUE : 8; /**< Current Receive Count */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_MCRXCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_MCRXCNT_t__ */ + +/*@}*/ + +/** @defgroup ADDR1 Master Address Byte 1 (ADDR1) Register + * Master Address Byte 1 (ADDR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ADDR1_Struct + *! \brief Master Address Byte 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ +typedef struct _ADI_I2C_ADDR1_t { + union { + struct { + unsigned int VALUE : 8; /**< Address Byte 1 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ADDR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR1_t__ */ + +/*@}*/ + +/** @defgroup ADDR2 Master Address Byte 2 (ADDR2) Register + * Master Address Byte 2 (ADDR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ADDR2_Struct + *! \brief Master Address Byte 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ +typedef struct _ADI_I2C_ADDR2_t { + union { + struct { + unsigned int VALUE : 8; /**< Address Byte 2 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ADDR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ADDR2_t__ */ + +/*@}*/ + +/** @defgroup BYT Start Byte (BYT) Register + * Start Byte (BYT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_BYT_Struct + *! \brief Start Byte Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ +typedef struct _ADI_I2C_BYT_t { + union { + struct { + unsigned int SBYTE : 8; /**< Start Byte */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_BYT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_BYT_t__ */ + +/*@}*/ + +/** @defgroup DIV Serial Clock Period Divisor (DIV) Register + * Serial Clock Period Divisor (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_DIV_Struct + *! \brief Serial Clock Period Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ +typedef struct _ADI_I2C_DIV_t { + union { + struct { + unsigned int LOW : 8; /**< Serial Clock Low Time */ + unsigned int HIGH : 8; /**< Serial Clock High Time */ + }; + uint16_t VALUE16; + }; +} ADI_I2C_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_DIV_t__ */ + +/*@}*/ + +/** @defgroup SCTL Slave Control (SCTL) Register + * Slave Control (SCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SCTL_Struct + *! \brief Slave Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ +typedef struct _ADI_I2C_SCTL_t { + union { + struct { + unsigned int SLVEN : 1; /**< Slave Enable */ + unsigned int ADR10EN : 1; /**< Enabled 10-bit Addressing */ + unsigned int GCEN : 1; /**< General Call Enable */ + unsigned int HGCEN : 1; /**< Hardware General Call Enable */ + unsigned int GCSBCLR : 1; /**< General Call Status Bit Clear */ + unsigned int EARLYTXR : 1; /**< Early Transmit Request Mode */ + unsigned int reserved6 : 1; + unsigned int NACK : 1; /**< NACK Next Communication */ + unsigned int IENSTOP : 1; /**< Stop Condition Detected Interrupt Enable */ + unsigned int IENSRX : 1; /**< Slave Receive Request Interrupt Enable */ + unsigned int IENSTX : 1; /**< Slave Transmit Request Interrupt Enable */ + unsigned int STXDEC : 1; /**< Decrement Slave Tx FIFO Status When a Byte is Txed */ + unsigned int IENREPST : 1; /**< Repeated Start Interrupt Enable */ + unsigned int SRXDMA : 1; /**< Enable Slave Rx DMA Request */ + unsigned int STXDMA : 1; /**< Enable Slave Tx DMA Request */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SCTL_t__ */ + +/*@}*/ + +/** @defgroup SSTAT Slave I2C Status/Error/IRQ (SSTAT) Register + * Slave I2C Status/Error/IRQ (SSTAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SSTAT_Struct + *! \brief Slave I2C Status/Error/IRQ Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ +typedef struct _ADI_I2C_SSTAT_t { + union { + struct { + unsigned int STXFSEREQ : 1; /**< Slave Tx FIFO Status or Early Request */ + unsigned int STXUNDR : 1; /**< Slave Transmit FIFO Underflow */ + unsigned int STXREQ : 1; /**< Slave Transmit Request/Slave Transmit Interrupt */ + unsigned int SRXREQ : 1; /**< Slave Receive Request */ + unsigned int SRXOVR : 1; /**< Slave Receive FIFO Overflow */ + unsigned int NOACK : 1; /**< ACK Not Generated by the Slave */ + unsigned int SBUSY : 1; /**< Slave Busy */ + unsigned int GCINT : 1; /**< General Call Interrupt */ + unsigned int GCID : 2; /**< General ID */ + unsigned int STOP : 1; /**< Stop After Start and Matching Address */ + unsigned int IDMAT : 2; /**< Device ID Matched */ + unsigned int REPSTART : 1; /**< Repeated Start and Matching Address */ + unsigned int START : 1; /**< Start and Matching Address */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SSTAT_t__ */ + +/*@}*/ + +/** @defgroup SRX Slave Receive (SRX) Register + * Slave Receive (SRX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SRX_Struct + *! \brief Slave Receive Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ +typedef struct _ADI_I2C_SRX_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Receive Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SRX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SRX_t__ */ + +/*@}*/ + +/** @defgroup STX Slave Transmit (STX) Register + * Slave Transmit (STX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_STX_Struct + *! \brief Slave Transmit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ +typedef struct _ADI_I2C_STX_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Transmit Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_STX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STX_t__ */ + +/*@}*/ + +/** @defgroup ALT Hardware General Call ID (ALT) Register + * Hardware General Call ID (ALT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ALT_Struct + *! \brief Hardware General Call ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ +typedef struct _ADI_I2C_ALT_t { + union { + struct { + unsigned int ID : 8; /**< Slave Alt */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ALT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ALT_t__ */ + +/*@}*/ + +/** @defgroup ID0 First Slave Address Device ID (ID0) Register + * First Slave Address Device ID (ID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID0_Struct + *! \brief First Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ +typedef struct _ADI_I2C_ID0_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 0 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID0_t__ */ + +/*@}*/ + +/** @defgroup ID1 Second Slave Address Device ID (ID1) Register + * Second Slave Address Device ID (ID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID1_Struct + *! \brief Second Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ +typedef struct _ADI_I2C_ID1_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 1 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID1_t__ */ + +/*@}*/ + +/** @defgroup ID2 Third Slave Address Device ID (ID2) Register + * Third Slave Address Device ID (ID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID2_Struct + *! \brief Third Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ +typedef struct _ADI_I2C_ID2_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 2 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID2_t__ */ + +/*@}*/ + +/** @defgroup ID3 Fourth Slave Address Device ID (ID3) Register + * Fourth Slave Address Device ID (ID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ID3_Struct + *! \brief Fourth Slave Address Device ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ +typedef struct _ADI_I2C_ID3_t { + union { + struct { + unsigned int VALUE : 8; /**< Slave Device ID 3 */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ID3_t__ */ + +/*@}*/ + +/** @defgroup STAT Master and Slave FIFO Status (STAT) Register + * Master and Slave FIFO Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_STAT_Struct + *! \brief Master and Slave FIFO Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ +typedef struct _ADI_I2C_STAT_t { + union { + struct { + unsigned int STXF : 2; /**< Slave Transmit FIFO Status */ + unsigned int SRXF : 2; /**< Slave Receive FIFO Status */ + unsigned int MTXF : 2; /**< Master Transmit FIFO Status */ + unsigned int MRXF : 2; /**< Master Receive FIFO Status */ + unsigned int SFLUSH : 1; /**< Flush the Slave Transmit FIFO */ + unsigned int MFLUSH : 1; /**< Flush the Master Transmit FIFO */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_I2C_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_STAT_t__ */ + +/*@}*/ + +/** @defgroup SHCTL Shared Control (SHCTL) Register + * Shared Control (SHCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_SHCTL_Struct + *! \brief Shared Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ +typedef struct _ADI_I2C_SHCTL_t { + union { + struct { + unsigned int RST : 1; /**< Reset START STOP Detect Circuit */ + unsigned int reserved1 : 15; + }; + uint16_t VALUE16; + }; +} ADI_I2C_SHCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_SHCTL_t__ */ + +/*@}*/ + +/** @defgroup TCTL Timing Control Register (TCTL) Register + * Timing Control Register (TCTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_TCTL_Struct + *! \brief Timing Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ +typedef struct _ADI_I2C_TCTL_t { + union { + struct { + unsigned int THDATIN : 5; /**< Data in Hold Start */ + unsigned int reserved5 : 3; + unsigned int FILTEROFF : 1; /**< Input Filter Control */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_I2C_TCTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_TCTL_t__ */ + +/*@}*/ + +/** @defgroup ASTRETCH_SCL Automatic Stretch SCL (ASTRETCH_SCL) Register + * Automatic Stretch SCL (ASTRETCH_SCL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_I2C_ASTRETCH_SCL_Struct + *! \brief Automatic Stretch SCL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ +typedef struct _ADI_I2C_ASTRETCH_SCL_t { + union { + struct { + unsigned int MST : 4; /**< Master Automatic Stretch Mode */ + unsigned int SLV : 4; /**< Slave Automatic Stretch Mode */ + unsigned int MSTTMO : 1; /**< Master Automatic Stretch Timeout */ + unsigned int SLVTMO : 1; /**< Slave Automatic Stretch Timeout */ + unsigned int reserved10 : 6; + }; + uint16_t VALUE16; + }; +} ADI_I2C_ASTRETCH_SCL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_I2C_ASTRETCH_SCL_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ +typedef struct _ADI_SPI_STAT_t { + union { + struct { + unsigned int IRQ : 1; /**< SPI Interrupt Status */ + unsigned int XFRDONE : 1; /**< SPI Transfer Completion */ + unsigned int TXEMPTY : 1; /**< SPI Tx FIFO Empty Interrupt */ + unsigned int TXDONE : 1; /**< SPI Tx Done in Read Command Mode */ + unsigned int TXUNDR : 1; /**< SPI Tx FIFO Underflow */ + unsigned int TXIRQ : 1; /**< SPI Tx IRQ */ + unsigned int RXIRQ : 1; /**< SPI Rx IRQ */ + unsigned int RXOVR : 1; /**< SPI Rx FIFO Overflow */ + unsigned int reserved8 : 3; + unsigned int CS : 1; /**< CS Status */ + unsigned int CSERR : 1; /**< Detected a CS Error Condition in Slave Mode */ + unsigned int CSRISE : 1; /**< Detected a Rising Edge on CS, in Slave CON Mode */ + unsigned int CSFALL : 1; /**< Detected a Falling Edge on CS, in Slave CON Mode */ + unsigned int RDY : 1; /**< Detected an Edge on Ready Indicator for Flow Control */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_STAT_t__ */ + +/*@}*/ + +/** @defgroup RX Receive (RX) Register + * Receive (RX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_RX_Struct + *! \brief Receive Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ +typedef struct _ADI_SPI_RX_t { + union { + struct { + unsigned int BYTE1 : 8; /**< 8-bit Receive Buffer */ + unsigned int BYTE2 : 8; /**< 8-bit Receive Buffer, Used Only in DMA Modes */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_RX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RX_t__ */ + +/*@}*/ + +/** @defgroup TX Transmit (TX) Register + * Transmit (TX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_TX_Struct + *! \brief Transmit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ +typedef struct _ADI_SPI_TX_t { + union { + struct { + unsigned int BYTE1 : 8; /**< 8-bit Transmit Buffer */ + unsigned int BYTE2 : 8; /**< 8-bit Transmit Buffer, Used Only in DMA Modes */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_TX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_TX_t__ */ + +/*@}*/ + +/** @defgroup DIV SPI Baud Rate Selection (DIV) Register + * SPI Baud Rate Selection (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_DIV_Struct + *! \brief SPI Baud Rate Selection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ +typedef struct _ADI_SPI_DIV_t { + union { + struct { + unsigned int VALUE : 6; /**< SPI Clock Divider */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_SPI_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DIV_t__ */ + +/*@}*/ + +/** @defgroup CTL SPI Configuration (CTL) Register + * SPI Configuration (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CTL_Struct + *! \brief SPI Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ +typedef struct _ADI_SPI_CTL_t { + union { + struct { + unsigned int SPIEN : 1; /**< SPI Enable */ + unsigned int MASEN : 1; /**< Master Mode Enable */ + unsigned int CPHA : 1; /**< Serial Clock Phase Mode */ + unsigned int CPOL : 1; /**< Serial Clock Polarity */ + unsigned int WOM : 1; /**< SPI Wired-OR Mode */ + unsigned int LSB : 1; /**< LSB First Transfer Enable */ + unsigned int TIM : 1; /**< SPI Transfer and Interrupt Mode */ + unsigned int ZEN : 1; /**< Transmit Zeros Enable */ + unsigned int RXOF : 1; /**< Rx Overflow Overwrite Enable */ + unsigned int OEN : 1; /**< Slave MISO Output Enable */ + unsigned int LOOPBACK : 1; /**< Loopback Enable */ + unsigned int CON : 1; /**< Continuous Transfer Enable */ + unsigned int RFLUSH : 1; /**< SPI Rx FIFO Flush Enable */ + unsigned int TFLUSH : 1; /**< SPI Tx FIFO Flush Enable */ + unsigned int CSRST : 1; /**< Reset Mode for CS Error Bit */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CTL_t__ */ + +/*@}*/ + +/** @defgroup IEN SPI Interrupts Enable (IEN) Register + * SPI Interrupts Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_IEN_Struct + *! \brief SPI Interrupts Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ +typedef struct _ADI_SPI_IEN_t { + union { + struct { + unsigned int IRQMODE : 3; /**< SPI IRQ Mode Bits */ + unsigned int reserved3 : 5; + unsigned int CS : 1; /**< Enable Interrupt on Every CS Edge in Slave CON Mode */ + unsigned int TXUNDR : 1; /**< Tx Underflow Interrupt Enable */ + unsigned int RXOVR : 1; /**< Rx Overflow Interrupt Enable */ + unsigned int RDY : 1; /**< Ready Signal Edge Interrupt Enable */ + unsigned int TXDONE : 1; /**< SPI Transmit Done Interrupt Enable */ + unsigned int XFRDONE : 1; /**< SPI Transfer Completion Interrupt Enable */ + unsigned int TXEMPTY : 1; /**< Tx FIFO Empty Interrupt Enable */ + unsigned int reserved15 : 1; + }; + uint16_t VALUE16; + }; +} ADI_SPI_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_IEN_t__ */ + +/*@}*/ + +/** @defgroup CNT Transfer Byte Count (CNT) Register + * Transfer Byte Count (CNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CNT_Struct + *! \brief Transfer Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ +typedef struct _ADI_SPI_CNT_t { + union { + struct { + unsigned int VALUE : 14; /**< Transfer Byte Count */ + unsigned int reserved14 : 1; + unsigned int FRAMECONT : 1; /**< Continue Frame */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_CNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CNT_t__ */ + +/*@}*/ + +/** @defgroup DMA SPI DMA Enable (DMA) Register + * SPI DMA Enable (DMA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_DMA_Struct + *! \brief SPI DMA Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ +typedef struct _ADI_SPI_DMA_t { + union { + struct { + unsigned int EN : 1; /**< Enable DMA for Data Transfer */ + unsigned int TXEN : 1; /**< Enable Transmit DMA Request */ + unsigned int RXEN : 1; /**< Enable Receive DMA Request */ + unsigned int reserved3 : 13; + }; + uint16_t VALUE16; + }; +} ADI_SPI_DMA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_DMA_t__ */ + +/*@}*/ + +/** @defgroup FIFO_STAT FIFO Status (FIFO_STAT) Register + * FIFO Status (FIFO_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_FIFO_STAT_Struct + *! \brief FIFO Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ +typedef struct _ADI_SPI_FIFO_STAT_t { + union { + struct { + unsigned int TX : 4; /**< SPI Tx FIFO Status */ + unsigned int reserved4 : 4; + unsigned int RX : 4; /**< SPI Rx FIFO Dtatus */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_SPI_FIFO_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FIFO_STAT_t__ */ + +/*@}*/ + +/** @defgroup RD_CTL Read Control (RD_CTL) Register + * Read Control (RD_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_RD_CTL_Struct + *! \brief Read Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ +typedef struct _ADI_SPI_RD_CTL_t { + union { + struct { + unsigned int CMDEN : 1; /**< Read Command Enable */ + unsigned int OVERLAP : 1; /**< Tx/Rx Overlap Mode */ + unsigned int TXBYTES : 4; /**< Transmit Byte Count - 1 (Read Command) */ + unsigned int reserved6 : 2; + unsigned int THREEPIN : 1; /**< Three Pin SPI Mode */ + unsigned int reserved9 : 7; + }; + uint16_t VALUE16; + }; +} ADI_SPI_RD_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_RD_CTL_t__ */ + +/*@}*/ + +/** @defgroup FLOW_CTL Flow Control (FLOW_CTL) Register + * Flow Control (FLOW_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_FLOW_CTL_Struct + *! \brief Flow Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ +typedef struct _ADI_SPI_FLOW_CTL_t { + union { + struct { + unsigned int MODE : 2; /**< Flow Control Mode */ + unsigned int reserved2 : 2; + unsigned int RDYPOL : 1; /**< Polarity of RDY/MISO Line */ + unsigned int reserved5 : 1; + unsigned int RDBURSTSZ : 10; /**< Read Data Burst Size - 1 */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_FLOW_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_FLOW_CTL_t__ */ + +/*@}*/ + +/** @defgroup WAIT_TMR Wait Timer for Flow Control (WAIT_TMR) Register + * Wait Timer for Flow Control (WAIT_TMR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_WAIT_TMR_Struct + *! \brief Wait Timer for Flow Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ +typedef struct _ADI_SPI_WAIT_TMR_t { + union { + struct { + unsigned int VALUE : 16; /**< Wait Timer */ + }; + uint16_t VALUE16; + }; +} ADI_SPI_WAIT_TMR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_WAIT_TMR_t__ */ + +/*@}*/ + +/** @defgroup CS_CTL Chip Select Control for Multi-slave Connections (CS_CTL) Register + * Chip Select Control for Multi-slave Connections (CS_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CS_CTL_Struct + *! \brief Chip Select Control for Multi-slave Connections Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ +typedef struct _ADI_SPI_CS_CTL_t { + union { + struct { + unsigned int SEL : 4; /**< Chip Select Control */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CS_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_CTL_t__ */ + +/*@}*/ + +/** @defgroup CS_OVERRIDE Chip Select Override (CS_OVERRIDE) Register + * Chip Select Override (CS_OVERRIDE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPI_CS_OVERRIDE_Struct + *! \brief Chip Select Override Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ +typedef struct _ADI_SPI_CS_OVERRIDE_t { + union { + struct { + unsigned int CTL : 2; /**< CS Override Control */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_SPI_CS_OVERRIDE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPI_CS_OVERRIDE_t__ */ + +/*@}*/ + +/** @defgroup RX Receive Buffer Register (RX) Register + * Receive Buffer Register (RX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RX_Struct + *! \brief Receive Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ +typedef struct _ADI_UART_RX_t { + union { + struct { + unsigned int RBR : 8; /**< Receive Buffer Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_RX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RX_t__ */ + +/*@}*/ + +/** @defgroup TX Transmit Holding Register (TX) Register + * Transmit Holding Register (TX) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_TX_Struct + *! \brief Transmit Holding Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ +typedef struct _ADI_UART_TX_t { + union { + struct { + unsigned int THR : 8; /**< Transmit Holding Register */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_TX_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TX_t__ */ + +/*@}*/ + +/** @defgroup IEN Interrupt Enable (IEN) Register + * Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_IEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ +typedef struct _ADI_UART_IEN_t { + union { + struct { + unsigned int ERBFI : 1; /**< Receive Buffer Full Interrupt */ + unsigned int ETBEI : 1; /**< Transmit Buffer Empty Interrupt */ + unsigned int ELSI : 1; /**< Rx Status Interrupt */ + unsigned int EDSSI : 1; /**< Modem Status Interrupt */ + unsigned int EDMAT : 1; /**< DMA Requests in Transmit Mode */ + unsigned int EDMAR : 1; /**< DMA Requests in Receive Mode */ + unsigned int reserved6 : 10; + }; + uint16_t VALUE16; + }; +} ADI_UART_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IEN_t__ */ + +/*@}*/ + +/** @defgroup IIR Interrupt ID (IIR) Register + * Interrupt ID (IIR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_IIR_STAT + *! \brief Interrupt Status (STAT) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_IIR_STAT_EDSSI = 0, /**< Modem status interrupt (Read MSR register to clear) */ + UART_IIR_STAT_ETBEI = 1, /**< Transmit buffer empty interrupt (Write to Tx register or read IIR register to clear) */ + UART_IIR_STAT_ERBFI = 2, /**< Receive buffer full interrupt (Read Rx register to clear) */ + UART_IIR_STAT_RLSI = 3, /**< Receive line status interrupt (Read LSR register to clear) */ + UART_IIR_STAT_RFTOI = 6 /**< Receive FIFO time-out interrupt (Read Rx register to clear) */ +} ADI_UART_IIR_STAT; + + +/* ========================================================================== + *! \struct ADI_UART_IIR_Struct + *! \brief Interrupt ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ +typedef struct _ADI_UART_IIR_t { + union { + struct { + unsigned int NIRQ : 1; /**< Interrupt Flag */ + unsigned int STAT : 3; /**< Interrupt Status */ + unsigned int reserved4 : 2; + unsigned int FEND : 2; /**< FIFO Enabled */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_IIR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_IIR_t__ */ + +/*@}*/ + +/** @defgroup LCR Line Control (LCR) Register + * Line Control (LCR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_LCR_SP + *! \brief Stick Parity (SP) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_LCR_PAR_NOTFORCED = 0, /**< Parity will not be forced based on Parity Select and Parity Enable bits. */ + UART_LCR_PAR_FORCED = 1 /**< Parity forced based on Parity Select and Parity Enable bits. */ +} ADI_UART_LCR_SP; + + +/* ========================================================================== + *! \struct ADI_UART_LCR_Struct + *! \brief Line Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ +typedef struct _ADI_UART_LCR_t { + union { + struct { + unsigned int WLS : 2; /**< Word Length Select */ + unsigned int STOP : 1; /**< Stop Bit */ + unsigned int PEN : 1; /**< Parity Enable */ + unsigned int EPS : 1; /**< Parity Select */ + unsigned int SP : 1; /**< Stick Parity */ + unsigned int BRK : 1; /**< Set Break */ + unsigned int reserved7 : 9; + }; + uint16_t VALUE16; + }; +} ADI_UART_LCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR_t__ */ + +/*@}*/ + +/** @defgroup MCR Modem Control (MCR) Register + * Modem Control (MCR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_MCR_Struct + *! \brief Modem Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ +typedef struct _ADI_UART_MCR_t { + union { + struct { + unsigned int DTR : 1; /**< Data Terminal Ready */ + unsigned int RTS : 1; /**< Request to Send */ + unsigned int OUT1 : 1; /**< Output 1 */ + unsigned int OUT2 : 1; /**< Output 2 */ + unsigned int LOOPBACK : 1; /**< Loopback Mode */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_MCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MCR_t__ */ + +/*@}*/ + +/** @defgroup LSR Line Status (LSR) Register + * Line Status (LSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_LSR_Struct + *! \brief Line Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ +typedef struct _ADI_UART_LSR_t { + union { + struct { + unsigned int DR : 1; /**< Data Ready */ + unsigned int OE : 1; /**< Overrun Error */ + unsigned int PE : 1; /**< Parity Error */ + unsigned int FE : 1; /**< Framing Error */ + unsigned int BI : 1; /**< Break Indicator */ + unsigned int THRE : 1; /**< Transmit Register Empty */ + unsigned int TEMT : 1; /**< Transmit and Shift Register Empty Status */ + unsigned int FIFOERR : 1; /**< Rx FIFO Parity Error/Frame Error/Break Indication */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_LSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LSR_t__ */ + +/*@}*/ + +/** @defgroup MSR Modem Status (MSR) Register + * Modem Status (MSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_MSR_Struct + *! \brief Modem Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ +typedef struct _ADI_UART_MSR_t { + union { + struct { + unsigned int DCTS : 1; /**< Delta CTS */ + unsigned int DDSR : 1; /**< Delta DSR */ + unsigned int TERI : 1; /**< Trailing Edge RI */ + unsigned int DDCD : 1; /**< Delta DCD */ + unsigned int CTS : 1; /**< Clear to Send */ + unsigned int DSR : 1; /**< Data Set Ready */ + unsigned int RI : 1; /**< Ring Indicator */ + unsigned int DCD : 1; /**< Data Carrier Detect */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_MSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_MSR_t__ */ + +/*@}*/ + +/** @defgroup SCR Scratch Buffer (SCR) Register + * Scratch Buffer (SCR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_SCR_Struct + *! \brief Scratch Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ +typedef struct _ADI_UART_SCR_t { + union { + struct { + unsigned int SCR : 8; /**< Scratch */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_SCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_SCR_t__ */ + +/*@}*/ + +/** @defgroup FCR FIFO Control (FCR) Register + * FIFO Control (FCR) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_FCR_FDMAMD + *! \brief FIFO DMA Mode (FDMAMD) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_FCR_MODE0 = 0, /**< In DMA mode 0, RX DMA request will be asserted whenever there's data in RBR or RX FIFO and de-assert whenever RBR or RX FIFO is empty; TX DMA request will be asserted whenever THR or TX FIFO is empty and de-assert whenever data written to. */ + UART_FCR_MODE1 = 1 /**< in DMA mode 1, RX DMA request will be asserted whenever RX FIFO trig level or time out reached and de-assert thereafter when RX FIFO is empty; TX DMA request will be asserted whenever TX FIFO is empty and de-assert thereafter when TX FIFO is completely filled up full. */ +} ADI_UART_FCR_FDMAMD; + + +/* ========================================================================== + *! \struct ADI_UART_FCR_Struct + *! \brief FIFO Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ +typedef struct _ADI_UART_FCR_t { + union { + struct { + unsigned int FIFOEN : 1; /**< FIFO Enable as to Work in 16550 Mode */ + unsigned int RFCLR : 1; /**< Clear Rx FIFO */ + unsigned int TFCLR : 1; /**< Clear Tx FIFO */ + unsigned int FDMAMD : 1; /**< FIFO DMA Mode */ + unsigned int reserved4 : 2; + unsigned int RFTRIG : 2; /**< Rx FIFO Trigger Level */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_FCR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FCR_t__ */ + +/*@}*/ + +/** @defgroup FBR Fractional Baud Rate (FBR) Register + * Fractional Baud Rate (FBR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_FBR_Struct + *! \brief Fractional Baud Rate Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ +typedef struct _ADI_UART_FBR_t { + union { + struct { + unsigned int DIVN : 11; /**< Fractional Baud Rate N Divide Bits 0 to 2047 */ + unsigned int DIVM : 2; /**< Fractional Baud Rate M Divide Bits 1 to 3 */ + unsigned int reserved13 : 2; + unsigned int FBEN : 1; /**< Fractional Baud Rate Generator Enable */ + }; + uint16_t VALUE16; + }; +} ADI_UART_FBR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_FBR_t__ */ + +/*@}*/ + +/** @defgroup DIV Baud Rate Divider (DIV) Register + * Baud Rate Divider (DIV) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_DIV_Struct + *! \brief Baud Rate Divider Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ +typedef struct _ADI_UART_DIV_t { + union { + struct { + unsigned int DIV : 16; /**< Baud Rate Divider */ + }; + uint16_t VALUE16; + }; +} ADI_UART_DIV_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_DIV_t__ */ + +/*@}*/ + +/** @defgroup LCR2 Second Line Control (LCR2) Register + * Second Line Control (LCR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_LCR2_Struct + *! \brief Second Line Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ +typedef struct _ADI_UART_LCR2_t { + union { + struct { + unsigned int OSR : 2; /**< Over Sample Rate */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_UART_LCR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_LCR2_t__ */ + +/*@}*/ + +/** @defgroup CTL UART Control Register (CTL) Register + * UART Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_UART_CTL_RXINV + *! \brief Invert Receiver Line (RXINV) Enumerations + * ========================================================================= */ +typedef enum +{ + UART_CTL_NOTINV_RX = 0, /**< Don't invert receiver line (idling high). */ + UART_CTL_INV_RX = 1 /**< Invert receiver line (idling low). */ +} ADI_UART_CTL_RXINV; + + +/* ========================================================================== + *! \struct ADI_UART_CTL_Struct + *! \brief UART Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ +typedef struct _ADI_UART_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int FORCECLK : 1; /**< Force UCLK on */ + unsigned int reserved2 : 2; + unsigned int RXINV : 1; /**< Invert Receiver Line */ + unsigned int reserved5 : 3; + unsigned int REV : 8; /**< UART Revision ID */ + }; + uint16_t VALUE16; + }; +} ADI_UART_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_CTL_t__ */ + +/*@}*/ + +/** @defgroup RFC RX FIFO Byte Count (RFC) Register + * RX FIFO Byte Count (RFC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RFC_Struct + *! \brief RX FIFO Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ +typedef struct _ADI_UART_RFC_t { + union { + struct { + unsigned int RFC : 5; /**< Current Rx FIFO Data Bytes */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_RFC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RFC_t__ */ + +/*@}*/ + +/** @defgroup TFC TX FIFO Byte Count (TFC) Register + * TX FIFO Byte Count (TFC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_TFC_Struct + *! \brief TX FIFO Byte Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ +typedef struct _ADI_UART_TFC_t { + union { + struct { + unsigned int TFC : 5; /**< Current Tx FIFO Data Bytes */ + unsigned int reserved5 : 11; + }; + uint16_t VALUE16; + }; +} ADI_UART_TFC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_TFC_t__ */ + +/*@}*/ + +/** @defgroup RSC RS485 Half-duplex Control (RSC) Register + * RS485 Half-duplex Control (RSC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_RSC_Struct + *! \brief RS485 Half-duplex Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ +typedef struct _ADI_UART_RSC_t { + union { + struct { + unsigned int OENP : 1; /**< SOUT_EN Polarity */ + unsigned int OENSP : 1; /**< SOUT_EN De-assert Before Full Stop Bit(s) */ + unsigned int DISRX : 1; /**< Disable Rx When Transmitting */ + unsigned int DISTX : 1; /**< Hold off Tx When Receiving */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_UART_RSC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_RSC_t__ */ + +/*@}*/ + +/** @defgroup ACR Auto Baud Control (ACR) Register + * Auto Baud Control (ACR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ACR_Struct + *! \brief Auto Baud Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ +typedef struct _ADI_UART_ACR_t { + union { + struct { + unsigned int ABE : 1; /**< Auto Baud Enable */ + unsigned int DNIEN : 1; /**< Enable Done Interrupt */ + unsigned int TOIEN : 1; /**< Enable Time-out Interrupt */ + unsigned int reserved3 : 1; + unsigned int SEC : 3; /**< Starting Edge Count */ + unsigned int reserved7 : 1; + unsigned int EEC : 4; /**< Ending Edge Count */ + unsigned int reserved12 : 4; + }; + uint16_t VALUE16; + }; +} ADI_UART_ACR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ACR_t__ */ + +/*@}*/ + +/** @defgroup ASRL Auto Baud Status (Low) (ASRL) Register + * Auto Baud Status (Low) (ASRL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ASRL_Struct + *! \brief Auto Baud Status (Low) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ +typedef struct _ADI_UART_ASRL_t { + union { + struct { + unsigned int DONE : 1; /**< Auto Baud Done Successfully */ + unsigned int BRKTO : 1; /**< Timed Out Due to Long Time Break Condition */ + unsigned int NSETO : 1; /**< Timed Out Due to No Valid Start Edge Found */ + unsigned int NEETO : 1; /**< Timed Out Due to No Valid Ending Edge Found */ + unsigned int CNT : 12; /**< CNT[11:0] Auto Baud Counter Value */ + }; + uint16_t VALUE16; + }; +} ADI_UART_ASRL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRL_t__ */ + +/*@}*/ + +/** @defgroup ASRH Auto Baud Status (High) (ASRH) Register + * Auto Baud Status (High) (ASRH) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_UART_ASRH_Struct + *! \brief Auto Baud Status (High) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ +typedef struct _ADI_UART_ASRH_t { + union { + struct { + unsigned int CNT : 8; /**< CNT[19:12] Auto Baud Counter Value */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_UART_ASRH_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_UART_ASRH_t__ */ + +/*@}*/ + +/** @defgroup CFG Beeper Configuration (CFG) Register + * Beeper Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_CFG_Struct + *! \brief Beeper Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ +typedef struct _ADI_BEEP_CFG_t { + union { + struct { + unsigned int SEQREPEAT : 8; /**< Beeper Sequence Repeat Value */ + unsigned int EN : 1; /**< Beeper Enable */ + unsigned int reserved9 : 1; + unsigned int ASTARTIRQ : 1; /**< Tone A Start IRQ */ + unsigned int AENDIRQ : 1; /**< Tone A End IRQ */ + unsigned int BSTARTIRQ : 1; /**< Tone B Start IRQ */ + unsigned int BENDIRQ : 1; /**< Tone B End IRQ */ + unsigned int SEQNEARENDIRQ : 1; /**< Sequence 1 Cycle from End IRQ */ + unsigned int SEQATENDIRQ : 1; /**< Sequence End IRQ */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_CFG_t__ */ + +/*@}*/ + +/** @defgroup STAT Beeper Status (STAT) Register + * Beeper Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_STAT_Struct + *! \brief Beeper Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ +typedef struct _ADI_BEEP_STAT_t { + union { + struct { + unsigned int SEQREMAIN : 8; /**< Remaining Tone-pair Iterations to Play in Sequence Mode */ + unsigned int BUSY : 1; /**< Beeper is Busy */ + unsigned int reserved9 : 1; + unsigned int ASTARTED : 1; /**< Tone A Has Started */ + unsigned int AENDED : 1; /**< Tone A Has Ended */ + unsigned int BSTARTED : 1; /**< Tone B Has Started */ + unsigned int BENDED : 1; /**< Tone B Has Ended */ + unsigned int SEQNEAREND : 1; /**< Sequencer Last Tone-pair Has Started */ + unsigned int SEQENDED : 1; /**< Sequencer Has Ended */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_STAT_t__ */ + +/*@}*/ + +/** @defgroup TONEA Tone A Data (TONEA) Register + * Tone A Data (TONEA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_TONEA_Struct + *! \brief Tone A Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ +typedef struct _ADI_BEEP_TONEA_t { + union { + struct { + unsigned int DUR : 8; /**< Tone Duration */ + unsigned int FREQ : 7; /**< Tone Frequency */ + unsigned int DIS : 1; /**< Output Disable */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_TONEA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEA_t__ */ + +/*@}*/ + +/** @defgroup TONEB Tone B Data (TONEB) Register + * Tone B Data (TONEB) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BEEP_TONEB_Struct + *! \brief Tone B Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ +typedef struct _ADI_BEEP_TONEB_t { + union { + struct { + unsigned int DUR : 8; /**< Tone Duration */ + unsigned int FREQ : 7; /**< Tone Frequency */ + unsigned int DIS : 1; /**< Output Disable */ + }; + uint16_t VALUE16; + }; +} ADI_BEEP_TONEB_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BEEP_TONEB_t__ */ + +/*@}*/ + +/** @defgroup CFG ADC Configuration (CFG) Register + * ADC Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_ADC_CFG_VREFSEL + *! \brief To select Vref as 1.25 V or 2.5 V (VREFSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + ADC_CFG_V_2P5 = 0, /**< Vref = 2.5 V */ + ADC_CFG_V_1P25 = 1 /**< Vref = 1.25 V */ +} ADI_ADC_CFG_VREFSEL; + + +/* ========================================================================= + *! \enum ADI_ADC_CFG_REFBUFEN + *! \brief To enable internal reference buffer (REFBUFEN) Enumerations + * ========================================================================= */ +typedef enum +{ + ADC_CFG_EXT_REF = 0, /**< External reference is used */ + ADC_CFG_BUF_REF = 1 /**< Reference buffer is enabled */ +} ADI_ADC_CFG_REFBUFEN; + + +/* ========================================================================== + *! \struct ADI_ADC_CFG_Struct + *! \brief ADC Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ +typedef struct _ADI_ADC_CFG_t { + union { + struct { + unsigned int PWRUP : 1; /**< Powering up ADC */ + unsigned int VREFSEL : 1; /**< To select Vref as 1.25 V or 2.5 V */ + unsigned int REFBUFEN : 1; /**< To enable internal reference buffer */ + unsigned int VREFVBAT : 1; /**< VRef VBAT */ + unsigned int EN : 1; /**< To enable ADC subsystem */ + unsigned int STARTCAL : 1; /**< To start a new offset calibration cycle */ + unsigned int RST : 1; /**< Resets internal buffers and registers when high */ + unsigned int SINKEN : 1; /**< To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability @2.5 V */ + unsigned int TMPEN : 1; /**< To power up temperature sensor */ + unsigned int FAST_DISCH : 1; /**< For fast switchover of Vref from 2.5 V to 1.25 V */ + unsigned int VREFVBAT_DEL : 1; /**< Set to 1 after minimum delay of 700 us from VREFBAT field being set to 1 */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG_t__ */ + +/*@}*/ + +/** @defgroup PWRUP ADC Power-up Time (PWRUP) Register + * ADC Power-up Time (PWRUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_PWRUP_Struct + *! \brief ADC Power-up Time Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ +typedef struct _ADI_ADC_PWRUP_t { + union { + struct { + unsigned int WAIT : 11; /**< Program this count to generate 20us wait time with respect to the PCLK frequency */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_PWRUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_PWRUP_t__ */ + +/*@}*/ + +/** @defgroup CAL_WORD Calibration Word (CAL_WORD) Register + * Calibration Word (CAL_WORD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CAL_WORD_Struct + *! \brief Calibration Word Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ +typedef struct _ADI_ADC_CAL_WORD_t { + union { + struct { + unsigned int VALUE : 7; /**< Offset calibration word */ + unsigned int reserved7 : 9; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CAL_WORD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CAL_WORD_t__ */ + +/*@}*/ + +/** @defgroup CNV_CFG ADC Conversion Configuration (CNV_CFG) Register + * ADC Conversion Configuration (CNV_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CNV_CFG_Struct + *! \brief ADC Conversion Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ +typedef struct _ADI_ADC_CNV_CFG_t { + union { + struct { + unsigned int SEL : 8; /**< To select channel(s) to convert */ + unsigned int BAT : 1; /**< To enable battery monitoring */ + unsigned int TMP : 1; /**< To select temperature measurement 1 */ + unsigned int TMP2 : 1; /**< To select temperature measurement 2 */ + unsigned int reserved11 : 1; + unsigned int AUTOMODE : 1; /**< To enable auto mode */ + unsigned int DMAEN : 1; /**< To enable DMA channel */ + unsigned int SINGLE : 1; /**< Set to start single conversion */ + unsigned int MULTI : 1; /**< Set to start multiple conversions */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CNV_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_CFG_t__ */ + +/*@}*/ + +/** @defgroup CNV_TIME ADC Conversion Time (CNV_TIME) Register + * ADC Conversion Time (CNV_TIME) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CNV_TIME_Struct + *! \brief ADC Conversion Time Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ +typedef struct _ADI_ADC_CNV_TIME_t { + union { + struct { + unsigned int SAMPTIME : 8; /**< Number of clock cycles (ACLK) required for sampling */ + unsigned int DLY : 8; /**< Delay between two consecutive conversions in terms of number of ACLK cycles */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CNV_TIME_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CNV_TIME_t__ */ + +/*@}*/ + +/** @defgroup AVG_CFG Averaging Configuration (AVG_CFG) Register + * Averaging Configuration (AVG_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_AVG_CFG_Struct + *! \brief Averaging Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ +typedef struct _ADI_ADC_AVG_CFG_t { + union { + struct { + unsigned int FACTOR : 8; /**< Program averaging factor for averaging enabled channels (1-256) */ + unsigned int reserved8 : 6; + unsigned int OS : 1; /**< Enable oversampling */ + unsigned int EN : 1; /**< To enable averaging on Channels enabled in enable register */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_AVG_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_AVG_CFG_t__ */ + +/*@}*/ + +/** @defgroup IRQ_EN Interrupt Enable (IRQ_EN) Register + * Interrupt Enable (IRQ_EN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_IRQ_EN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ +typedef struct _ADI_ADC_IRQ_EN_t { + union { + struct { + unsigned int CNVDONE : 1; /**< Set it to enable interrupt after conversion is done */ + unsigned int reserved1 : 9; + unsigned int CALDONE : 1; /**< Set it to enable interrupt for calibration done */ + unsigned int OVF : 1; /**< Set to enable interrupt in case of overflow */ + unsigned int ALERT : 1; /**< Set to enable interrupt on crossing lower or higher limit */ + unsigned int RDY : 1; /**< Set to enable interrupt when ADC is ready to convert */ + unsigned int reserved14 : 2; + }; + uint16_t VALUE16; + }; +} ADI_ADC_IRQ_EN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_IRQ_EN_t__ */ + +/*@}*/ + +/** @defgroup STAT ADC Status (STAT) Register + * ADC Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_STAT_Struct + *! \brief ADC Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ +typedef struct _ADI_ADC_STAT_t { + union { + struct { + unsigned int DONE0 : 1; /**< Indicates conversion done on Channel 0 */ + unsigned int DONE1 : 1; /**< Indicates conversion done on Channel 1 */ + unsigned int DONE2 : 1; /**< Indicates conversion done on Channel 2 */ + unsigned int DONE3 : 1; /**< Indicates conversion done on Channel 3 */ + unsigned int DONE4 : 1; /**< Indicates conversion done on Channel 4 */ + unsigned int DONE5 : 1; /**< Indicates conversion done on Channel 5 */ + unsigned int DONE6 : 1; /**< Indicates conversion done on Channel 6 */ + unsigned int DONE7 : 1; /**< Indicates conversion done on Channel 7 */ + unsigned int BATDONE : 1; /**< Indicates conversion done for battery monitoring */ + unsigned int TMPDONE : 1; /**< Indicates conversion is done for temperature sensing */ + unsigned int TMP2DONE : 1; /**< Indicates conversion is done for temperature sensing 2 */ + unsigned int reserved11 : 3; + unsigned int CALDONE : 1; /**< Indicates calibration is done */ + unsigned int RDY : 1; /**< Indicates ADC is ready to start converting, when using external reference buffer */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_STAT_t__ */ + +/*@}*/ + +/** @defgroup OVF Overflow of Output Registers (OVF) Register + * Overflow of Output Registers (OVF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_OVF_Struct + *! \brief Overflow of Output Registers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ +typedef struct _ADI_ADC_OVF_t { + union { + struct { + unsigned int CH0 : 1; /**< Indicates overflow in channel 0 output register */ + unsigned int CH1 : 1; /**< Indicates overflow in channel 1 output register */ + unsigned int CH2 : 1; /**< Indicates overflow in channel 2 output register */ + unsigned int CH3 : 1; /**< Indicates overflow in channel 3 output register */ + unsigned int CH4 : 1; /**< Indicates overflow in channel 4 output register */ + unsigned int CH5 : 1; /**< Indicates overflow in channel 5 output register */ + unsigned int CH6 : 1; /**< Indicates overflow in channel 6 output register */ + unsigned int CH7 : 1; /**< Indicates overflow in channel 7 output register */ + unsigned int BAT : 1; /**< Indicates overflow in battery monitoring output register */ + unsigned int TMP : 1; /**< Indicates overflow in temperature output register */ + unsigned int TMP2 : 1; /**< Indicates overflow in temperature 2 output register */ + unsigned int reserved11 : 5; + }; + uint16_t VALUE16; + }; +} ADI_ADC_OVF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_OVF_t__ */ + +/*@}*/ + +/** @defgroup ALERT Alert Indication (ALERT) Register + * Alert Indication (ALERT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_ALERT_Struct + *! \brief Alert Indication Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ +typedef struct _ADI_ADC_ALERT_t { + union { + struct { + unsigned int HI0 : 1; /**< Channel 0 High alert status */ + unsigned int LO0 : 1; /**< Channel 0 Low alert status */ + unsigned int HI1 : 1; /**< Channel 1 High alert status */ + unsigned int LO1 : 1; /**< Channel 1 Low alert status */ + unsigned int HI2 : 1; /**< Channel 2 High alert status */ + unsigned int LO2 : 1; /**< Channel 2 Low alert status */ + unsigned int HI3 : 1; /**< Channel 3 High alert status */ + unsigned int LO3 : 1; /**< Channel 3 Low alert status */ + unsigned int reserved8 : 8; + }; + uint16_t VALUE16; + }; +} ADI_ADC_ALERT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_ALERT_t__ */ + +/*@}*/ + +/** @defgroup CH0_OUT Conversion Result Channel 0 (CH0_OUT) Register + * Conversion Result Channel 0 (CH0_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH0_OUT_Struct + *! \brief Conversion Result Channel 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ +typedef struct _ADI_ADC_CH0_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 0 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH0_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH0_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH1_OUT Conversion Result Channel 1 (CH1_OUT) Register + * Conversion Result Channel 1 (CH1_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH1_OUT_Struct + *! \brief Conversion Result Channel 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ +typedef struct _ADI_ADC_CH1_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 1 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH1_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH1_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH2_OUT Conversion Result Channel 2 (CH2_OUT) Register + * Conversion Result Channel 2 (CH2_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH2_OUT_Struct + *! \brief Conversion Result Channel 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ +typedef struct _ADI_ADC_CH2_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 2 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH2_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH2_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH3_OUT Conversion Result Channel 3 (CH3_OUT) Register + * Conversion Result Channel 3 (CH3_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH3_OUT_Struct + *! \brief Conversion Result Channel 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ +typedef struct _ADI_ADC_CH3_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 3 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH3_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH3_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH4_OUT Conversion Result Channel 4 (CH4_OUT) Register + * Conversion Result Channel 4 (CH4_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH4_OUT_Struct + *! \brief Conversion Result Channel 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ +typedef struct _ADI_ADC_CH4_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 4 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH4_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH4_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH5_OUT Conversion Result Channel 5 (CH5_OUT) Register + * Conversion Result Channel 5 (CH5_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH5_OUT_Struct + *! \brief Conversion Result Channel 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ +typedef struct _ADI_ADC_CH5_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 5 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH5_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH5_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH6_OUT Conversion Result Channel 6 (CH6_OUT) Register + * Conversion Result Channel 6 (CH6_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH6_OUT_Struct + *! \brief Conversion Result Channel 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ +typedef struct _ADI_ADC_CH6_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 6 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH6_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH6_OUT_t__ */ + +/*@}*/ + +/** @defgroup CH7_OUT Conversion Result Channel 7 (CH7_OUT) Register + * Conversion Result Channel 7 (CH7_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CH7_OUT_Struct + *! \brief Conversion Result Channel 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ +typedef struct _ADI_ADC_CH7_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of channel 7 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_CH7_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CH7_OUT_t__ */ + +/*@}*/ + +/** @defgroup BAT_OUT Battery Monitoring Result (BAT_OUT) Register + * Battery Monitoring Result (BAT_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_BAT_OUT_Struct + *! \brief Battery Monitoring Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ +typedef struct _ADI_ADC_BAT_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of battery monitoring is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_BAT_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_BAT_OUT_t__ */ + +/*@}*/ + +/** @defgroup TMP_OUT Temperature Result (TMP_OUT) Register + * Temperature Result (TMP_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_TMP_OUT_Struct + *! \brief Temperature Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ +typedef struct _ADI_ADC_TMP_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of Temperature measurement 1 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_TMP_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP_OUT_t__ */ + +/*@}*/ + +/** @defgroup TMP2_OUT Temperature Result 2 (TMP2_OUT) Register + * Temperature Result 2 (TMP2_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_TMP2_OUT_Struct + *! \brief Temperature Result 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ +typedef struct _ADI_ADC_TMP2_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Conversion result of Temperature measurement 2 is stored here */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_TMP2_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_TMP2_OUT_t__ */ + +/*@}*/ + +/** @defgroup DMA_OUT DMA Output Register (DMA_OUT) Register + * DMA Output Register (DMA_OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_DMA_OUT_Struct + *! \brief DMA Output Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ +typedef struct _ADI_ADC_DMA_OUT_t { + union { + struct { + unsigned int RESULT : 16; /**< Register to store conversion result for DMA */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_DMA_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_DMA_OUT_t__ */ + +/*@}*/ + +/** @defgroup LIM0_LO Channel 0 Low Limit (LIM0_LO) Register + * Channel 0 Low Limit (LIM0_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM0_LO_Struct + *! \brief Channel 0 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ +typedef struct _ADI_ADC_LIM0_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 0 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM0_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM0_HI Channel 0 High Limit (LIM0_HI) Register + * Channel 0 High Limit (LIM0_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM0_HI_Struct + *! \brief Channel 0 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ +typedef struct _ADI_ADC_LIM0_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 0 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM0_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM0_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS0 Channel 0 Hysteresis (HYS0) Register + * Channel 0 Hysteresis (HYS0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS0_Struct + *! \brief Channel 0 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ +typedef struct _ADI_ADC_HYS0_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 0 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 0 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 0 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS0_t__ */ + +/*@}*/ + +/** @defgroup LIM1_LO Channel 1 Low Limit (LIM1_LO) Register + * Channel 1 Low Limit (LIM1_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM1_LO_Struct + *! \brief Channel 1 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ +typedef struct _ADI_ADC_LIM1_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 1 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM1_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM1_HI Channel 1 High Limit (LIM1_HI) Register + * Channel 1 High Limit (LIM1_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM1_HI_Struct + *! \brief Channel 1 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ +typedef struct _ADI_ADC_LIM1_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 1 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM1_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM1_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS1 Channel 1 Hysteresis (HYS1) Register + * Channel 1 Hysteresis (HYS1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS1_Struct + *! \brief Channel 1 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ +typedef struct _ADI_ADC_HYS1_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 1 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 1 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 1 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS1_t__ */ + +/*@}*/ + +/** @defgroup LIM2_LO Channel 2 Low Limit (LIM2_LO) Register + * Channel 2 Low Limit (LIM2_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM2_LO_Struct + *! \brief Channel 2 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ +typedef struct _ADI_ADC_LIM2_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 2 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM2_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM2_HI Channel 2 High Limit (LIM2_HI) Register + * Channel 2 High Limit (LIM2_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM2_HI_Struct + *! \brief Channel 2 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ +typedef struct _ADI_ADC_LIM2_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 2 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM2_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM2_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS2 Channel 2 Hysteresis (HYS2) Register + * Channel 2 Hysteresis (HYS2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS2_Struct + *! \brief Channel 2 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ +typedef struct _ADI_ADC_HYS2_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 2 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 2 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 2 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS2_t__ */ + +/*@}*/ + +/** @defgroup LIM3_LO Channel 3 Low Limit (LIM3_LO) Register + * Channel 3 Low Limit (LIM3_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM3_LO_Struct + *! \brief Channel 3 Low Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ +typedef struct _ADI_ADC_LIM3_LO_t { + union { + struct { + unsigned int VALUE : 12; /**< Low limit value for channel 3 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable low limit comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM3_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_LO_t__ */ + +/*@}*/ + +/** @defgroup LIM3_HI Channel 3 High Limit (LIM3_HI) Register + * Channel 3 High Limit (LIM3_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_LIM3_HI_Struct + *! \brief Channel 3 High Limit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ +typedef struct _ADI_ADC_LIM3_HI_t { + union { + struct { + unsigned int VALUE : 12; /**< High limit value for channel 3 */ + unsigned int reserved12 : 3; + unsigned int EN : 1; /**< To enable high limit comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_LIM3_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_LIM3_HI_t__ */ + +/*@}*/ + +/** @defgroup HYS3 Channel 3 Hysteresis (HYS3) Register + * Channel 3 Hysteresis (HYS3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_HYS3_Struct + *! \brief Channel 3 Hysteresis Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ +typedef struct _ADI_ADC_HYS3_t { + union { + struct { + unsigned int VALUE : 9; /**< Hysteresis value for Channel 3 */ + unsigned int reserved9 : 3; + unsigned int MONCYC : 3; /**< Program number of conversion cycles to monitor channel 3 before raising alert */ + unsigned int EN : 1; /**< To enable hysteresis for comparison on Channel 3 */ + }; + uint16_t VALUE16; + }; +} ADI_ADC_HYS3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_HYS3_t__ */ + +/*@}*/ + +/** @defgroup CFG1 Reference Buffer Low Power Mode (CFG1) Register + * Reference Buffer Low Power Mode (CFG1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_ADC_CFG1_Struct + *! \brief Reference Buffer Low Power Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ +typedef struct _ADI_ADC_CFG1_t { + union { + struct { + unsigned int RBUFLP : 1; /**< Enable low power mode for reference buffer */ + unsigned int reserved1 : 15; + }; + uint16_t VALUE16; + }; +} ADI_ADC_CFG1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_ADC_CFG1_t__ */ + +/*@}*/ + +/** @defgroup STAT DMA Status (STAT) Register + * DMA Status (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_STAT_Struct + *! \brief DMA Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ +typedef struct _ADI_DMA_STAT_t { + union { + struct { + unsigned int MEN : 1; /**< Enable Status of the Controller */ + unsigned int reserved1 : 15; + unsigned int CHANM1 : 5; /**< Number of Available DMA Channels Minus 1 */ + unsigned int reserved21 : 11; + }; + uint32_t VALUE32; + }; +} ADI_DMA_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_STAT_t__ */ + +/*@}*/ + +/** @defgroup CFG DMA Configuration (CFG) Register + * DMA Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_CFG_Struct + *! \brief DMA Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ +typedef struct _ADI_DMA_CFG_t { + union { + struct { + unsigned int MEN : 1; /**< Controller Enable */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_DMA_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_CFG_t__ */ + +/*@}*/ + +/** @defgroup PDBPTR DMA Channel Primary Control Database Pointer (PDBPTR) Register + * DMA Channel Primary Control Database Pointer (PDBPTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PDBPTR_Struct + *! \brief DMA Channel Primary Control Database Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ +typedef struct _ADI_DMA_PDBPTR_t { + union { + struct { + unsigned int ADDR : 32; /**< Pointer to the Base Address of the Primary Data Structure */ + }; + uint32_t VALUE32; + }; +} ADI_DMA_PDBPTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PDBPTR_t__ */ + +/*@}*/ + +/** @defgroup ADBPTR DMA Channel Alternate Control Database Pointer (ADBPTR) Register + * DMA Channel Alternate Control Database Pointer (ADBPTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ADBPTR_Struct + *! \brief DMA Channel Alternate Control Database Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ +typedef struct _ADI_DMA_ADBPTR_t { + union { + struct { + unsigned int ADDR : 32; /**< Base Address of the Alternate Data Structure */ + }; + uint32_t VALUE32; + }; +} ADI_DMA_ADBPTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ADBPTR_t__ */ + +/*@}*/ + +/** @defgroup SWREQ DMA Channel Software Request (SWREQ) Register + * DMA Channel Software Request (SWREQ) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SWREQ_Struct + *! \brief DMA Channel Software Request Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ +typedef struct _ADI_DMA_SWREQ_t { + union { + struct { + unsigned int CHAN : 27; /**< Generate Software Request */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SWREQ_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SWREQ_t__ */ + +/*@}*/ + +/** @defgroup RMSK_SET DMA Channel Request Mask Set (RMSK_SET) Register + * DMA Channel Request Mask Set (RMSK_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_RMSK_SET_Struct + *! \brief DMA Channel Request Mask Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ +typedef struct _ADI_DMA_RMSK_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Mask Requests from DMA Channels */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_RMSK_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_SET_t__ */ + +/*@}*/ + +/** @defgroup RMSK_CLR DMA Channel Request Mask Clear (RMSK_CLR) Register + * DMA Channel Request Mask Clear (RMSK_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_RMSK_CLR_Struct + *! \brief DMA Channel Request Mask Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ +typedef struct _ADI_DMA_RMSK_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Clear Request Mask Set Bits */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_RMSK_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_RMSK_CLR_t__ */ + +/*@}*/ + +/** @defgroup EN_SET DMA Channel Enable Set (EN_SET) Register + * DMA Channel Enable Set (EN_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_EN_SET_Struct + *! \brief DMA Channel Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ +typedef struct _ADI_DMA_EN_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Enable DMA Channels */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_EN_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_SET_t__ */ + +/*@}*/ + +/** @defgroup EN_CLR DMA Channel Enable Clear (EN_CLR) Register + * DMA Channel Enable Clear (EN_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_EN_CLR_Struct + *! \brief DMA Channel Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ +typedef struct _ADI_DMA_EN_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable DMA Channels */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_EN_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_EN_CLR_t__ */ + +/*@}*/ + +/** @defgroup ALT_SET DMA Channel Primary Alternate Set (ALT_SET) Register + * DMA Channel Primary Alternate Set (ALT_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ALT_SET_Struct + *! \brief DMA Channel Primary Alternate Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ +typedef struct _ADI_DMA_ALT_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Control Structure Status / Select Alternate Structure */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ALT_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_SET_t__ */ + +/*@}*/ + +/** @defgroup ALT_CLR DMA Channel Primary Alternate Clear (ALT_CLR) Register + * DMA Channel Primary Alternate Clear (ALT_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ALT_CLR_Struct + *! \brief DMA Channel Primary Alternate Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ +typedef struct _ADI_DMA_ALT_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Select Primary Data Structure */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ALT_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ALT_CLR_t__ */ + +/*@}*/ + +/** @defgroup PRI_SET DMA Channel Priority Set (PRI_SET) Register + * DMA Channel Priority Set (PRI_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PRI_SET_Struct + *! \brief DMA Channel Priority Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ +typedef struct _ADI_DMA_PRI_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Configure Channel for High Priority */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_PRI_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_SET_t__ */ + +/*@}*/ + +/** @defgroup PRI_CLR DMA Channel Priority Clear (PRI_CLR) Register + * DMA Channel Priority Clear (PRI_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_PRI_CLR_Struct + *! \brief DMA Channel Priority Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ +typedef struct _ADI_DMA_PRI_CLR_t { + union { + struct { + unsigned int CHPRICLR : 27; /**< Configure Channel for Default Priority Level */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_PRI_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_PRI_CLR_t__ */ + +/*@}*/ + +/** @defgroup ERRCHNL_CLR DMA per Channel Error Clear (ERRCHNL_CLR) Register + * DMA per Channel Error Clear (ERRCHNL_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ERRCHNL_CLR_Struct + *! \brief DMA per Channel Error Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ +typedef struct _ADI_DMA_ERRCHNL_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Per Channel Bus Error Status/Clear */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ERRCHNL_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERRCHNL_CLR_t__ */ + +/*@}*/ + +/** @defgroup ERR_CLR DMA Bus Error Clear (ERR_CLR) Register + * DMA Bus Error Clear (ERR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_ERR_CLR_Struct + *! \brief DMA Bus Error Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ +typedef struct _ADI_DMA_ERR_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Bus Error Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_ERR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_ERR_CLR_t__ */ + +/*@}*/ + +/** @defgroup INVALIDDESC_CLR DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register + * DMA per Channel Invalid Descriptor Clear (INVALIDDESC_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_INVALIDDESC_CLR_Struct + *! \brief DMA per Channel Invalid Descriptor Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ +typedef struct _ADI_DMA_INVALIDDESC_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Per Channel Invalid Descriptor Status/Clear */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_INVALIDDESC_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_INVALIDDESC_CLR_t__ */ + +/*@}*/ + +/** @defgroup BS_SET DMA Channel Bytes Swap Enable Set (BS_SET) Register + * DMA Channel Bytes Swap Enable Set (BS_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_BS_SET_Struct + *! \brief DMA Channel Bytes Swap Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ +typedef struct _ADI_DMA_BS_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Byte Swap Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_BS_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_SET_t__ */ + +/*@}*/ + +/** @defgroup BS_CLR DMA Channel Bytes Swap Enable Clear (BS_CLR) Register + * DMA Channel Bytes Swap Enable Clear (BS_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_BS_CLR_Struct + *! \brief DMA Channel Bytes Swap Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ +typedef struct _ADI_DMA_BS_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable Byte Swap */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_BS_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_BS_CLR_t__ */ + +/*@}*/ + +/** @defgroup SRCADDR_SET DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register + * DMA Channel Source Address Decrement Enable Set (SRCADDR_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SRCADDR_SET_Struct + *! \brief DMA Channel Source Address Decrement Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ +typedef struct _ADI_DMA_SRCADDR_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Source Address Decrement Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SRCADDR_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_SET_t__ */ + +/*@}*/ + +/** @defgroup SRCADDR_CLR DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register + * DMA Channel Source Address Decrement Enable Clear (SRCADDR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_SRCADDR_CLR_Struct + *! \brief DMA Channel Source Address Decrement Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ +typedef struct _ADI_DMA_SRCADDR_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable Source Address Decrement */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_SRCADDR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_SRCADDR_CLR_t__ */ + +/*@}*/ + +/** @defgroup DSTADDR_SET DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register + * DMA Channel Destination Address Decrement Enable Set (DSTADDR_SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_DSTADDR_SET_Struct + *! \brief DMA Channel Destination Address Decrement Enable Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ +typedef struct _ADI_DMA_DSTADDR_SET_t { + union { + struct { + unsigned int CHAN : 27; /**< Destination Address Decrement Status */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_DSTADDR_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_SET_t__ */ + +/*@}*/ + +/** @defgroup DSTADDR_CLR DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register + * DMA Channel Destination Address Decrement Enable Clear (DSTADDR_CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_DSTADDR_CLR_Struct + *! \brief DMA Channel Destination Address Decrement Enable Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ +typedef struct _ADI_DMA_DSTADDR_CLR_t { + union { + struct { + unsigned int CHAN : 27; /**< Disable Destination Address Decrement */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_DMA_DSTADDR_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_DSTADDR_CLR_t__ */ + +/*@}*/ + +/** @defgroup REVID DMA Controller Revision ID (REVID) Register + * DMA Controller Revision ID (REVID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_DMA_REVID_Struct + *! \brief DMA Controller Revision ID Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ +typedef struct _ADI_DMA_REVID_t { + union { + struct { + unsigned int VALUE : 8; /**< DMA Controller Revision ID */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_DMA_REVID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_DMA_REVID_t__ */ + +/*@}*/ + +/** @defgroup STAT Status (STAT) Register + * Status (STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_STAT_ACCESS_MODE + *! \brief Access Mode (ACCESS_MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_STAT_DIRECT = 0, /**< Flash controller is currently in Direct Access mode; user access to all registers is enabled */ + FLCC_STAT_INDIRECT = 1 /**< Flash Controller is currently in Indirect Access mode; user access to registers is limited to read-only access of the status register. Full register access will be restored when the Cryptographic module releases control of the flash controller (crypto completes the ongoing operation within the protected key storage region) */ +} ADI_FLCC_STAT_ACCESS_MODE; + + +/* ========================================================================== + *! \struct ADI_FLCC_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ +typedef struct _ADI_FLCC_STAT_t { + union { + struct { + unsigned int CMDBUSY : 1; /**< Command busy */ + unsigned int WRCLOSE : 1; /**< WRITE registers are closed */ + unsigned int CMDCOMP : 1; /**< Command complete */ + unsigned int WRALCOMP : 1; /**< Write almost complete */ + unsigned int CMDFAIL : 2; /**< Provides information on command failures */ + unsigned int SLEEPING : 1; /**< Flash array is in low power (sleep) mode */ + unsigned int ECCERRCMD : 2; /**< ECC errors detected during user issued SIGN command */ + unsigned int ECCRDERR : 2; /**< ECC IRQ cause */ + unsigned int OVERLAP : 1; /**< Overlapping Command */ + unsigned int reserved12 : 1; + unsigned int SIGNERR : 1; /**< Signature check failure during initialization */ + unsigned int INIT : 1; /**< Flash controller initialization in progress */ + unsigned int ECCINFOSIGN : 2; /**< ECC status of flash initialization */ + unsigned int ECCERRCNT : 3; /**< ECC correction counter */ + unsigned int reserved20 : 5; + unsigned int ECCICODE : 2; /**< ICode AHB Bus Error ECC status */ + unsigned int ECCDCODE : 2; /**< DCode AHB Bus Error ECC status */ + unsigned int CACHESRAMPERR : 1; /**< SRAM parity errors in Cache Controller */ + unsigned int reserved30 : 1; + unsigned int ACCESS_MODE : 1; /**< Access Mode */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_STAT_t__ */ + +/*@}*/ + +/** @defgroup IEN Interrupt Enable (IEN) Register + * Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_IEN_ECC_CORRECT + *! \brief Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events (ECC_CORRECT) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_IEN_NONE_COR = 0, /**< Do not generate a response to ECC events */ + FLCC_IEN_BUS_ERR_COR = 1, /**< Generate Bus Errors in response to ECC events */ + FLCC_IEN_IRQ_COR = 2 /**< Generate IRQs in response to ECC events */ +} ADI_FLCC_IEN_ECC_CORRECT; + + +/* ========================================================================= + *! \enum ADI_FLCC_IEN_ECC_ERROR + *! \brief Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events (ECC_ERROR) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_IEN_NONE_ERR = 0, /**< Do not generate a response to ECC events */ + FLCC_IEN_BUS_ERR_ERR = 1, /**< Generate Bus Errors in response to ECC events */ + FLCC_IEN_IRQ_ERR = 2 /**< Generate IRQs in response to ECC events */ +} ADI_FLCC_IEN_ECC_ERROR; + + +/* ========================================================================== + *! \struct ADI_FLCC_IEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ +typedef struct _ADI_FLCC_IEN_t { + union { + struct { + unsigned int CMDCMPLT : 1; /**< Command complete interrupt enable */ + unsigned int WRALCMPLT : 1; /**< Write almost complete interrupt enable */ + unsigned int CMDFAIL : 1; /**< Command fail interrupt enable */ + unsigned int reserved3 : 1; + unsigned int ECC_CORRECT : 2; /**< Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC Correction events */ + unsigned int ECC_ERROR : 2; /**< Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC Error events */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_IEN_t__ */ + +/*@}*/ + +/** @defgroup CMD Command (CMD) Register + * Command (CMD) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_CMD_VALUE + *! \brief Commands (VALUE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_CMD_IDLE = 0, /**< IDLE */ + FLCC_CMD_ABORT = 1, /**< ABORT */ + FLCC_CMD_SLEEP = 2, /**< Requests flash to enter Sleep mode */ + FLCC_CMD_SIGN = 3, /**< SIGN */ + FLCC_CMD_WRITE = 4, /**< WRITE */ + FLCC_CMD_BLANK_CHECK = 5, /**< Checks all of User Space; fails if any bits in user space are cleared */ + FLCC_CMD_ERASEPAGE = 6, /**< ERASEPAGE */ + FLCC_CMD_MASSERASE = 7 /**< MASSERASE */ +} ADI_FLCC_CMD_VALUE; + + +/* ========================================================================== + *! \struct ADI_FLCC_CMD_Struct + *! \brief Command Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ +typedef struct _ADI_FLCC_CMD_t { + union { + struct { + unsigned int VALUE : 4; /**< Commands */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CMD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CMD_t__ */ + +/*@}*/ + +/** @defgroup KH_ADDR Write Address (KH_ADDR) Register + * Write Address (KH_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_ADDR_Struct + *! \brief Write Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ +typedef struct _ADI_FLCC_KH_ADDR_t { + union { + struct { + unsigned int reserved0 : 3; + unsigned int VALUE : 17; /**< Address to be written on a WRITE command */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_ADDR_t__ */ + +/*@}*/ + +/** @defgroup KH_DATA0 Write Lower Data (KH_DATA0) Register + * Write Lower Data (KH_DATA0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_DATA0_Struct + *! \brief Write Lower Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ +typedef struct _ADI_FLCC_KH_DATA0_t { + union { + struct { + unsigned int VALUE : 32; /**< Lower half of 64-bit dual word data to be written on a Write command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_DATA0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA0_t__ */ + +/*@}*/ + +/** @defgroup KH_DATA1 Write Upper Data (KH_DATA1) Register + * Write Upper Data (KH_DATA1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_KH_DATA1_Struct + *! \brief Write Upper Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ +typedef struct _ADI_FLCC_KH_DATA1_t { + union { + struct { + unsigned int VALUE : 32; /**< Upper half of 64-bit dual word data to be written on a Write command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KH_DATA1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KH_DATA1_t__ */ + +/*@}*/ + +/** @defgroup PAGE_ADDR0 Lower Page Address (PAGE_ADDR0) Register + * Lower Page Address (PAGE_ADDR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_PAGE_ADDR0_Struct + *! \brief Lower Page Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ +typedef struct _ADI_FLCC_PAGE_ADDR0_t { + union { + struct { + unsigned int reserved0 : 10; + unsigned int VALUE : 10; /**< Lower address bits of the page address */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_PAGE_ADDR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR0_t__ */ + +/*@}*/ + +/** @defgroup PAGE_ADDR1 Upper Page Address (PAGE_ADDR1) Register + * Upper Page Address (PAGE_ADDR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_PAGE_ADDR1_Struct + *! \brief Upper Page Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ +typedef struct _ADI_FLCC_PAGE_ADDR1_t { + union { + struct { + unsigned int reserved0 : 10; + unsigned int VALUE : 10; /**< Upper address bits of the page address */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_PAGE_ADDR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_PAGE_ADDR1_t__ */ + +/*@}*/ + +/** @defgroup KEY Key (KEY) Register + * Key (KEY) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_FLCC_KEY_VALUE + *! \brief Key register (VALUE) Enumerations + * ========================================================================= */ +typedef enum +{ + FLCC_KEY_USERKEY = 1735161189 /**< USERKEY */ +} ADI_FLCC_KEY_VALUE; + + +/* ========================================================================== + *! \struct ADI_FLCC_KEY_Struct + *! \brief Key Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ +typedef struct _ADI_FLCC_KEY_t { + union { + struct { + unsigned int VALUE : 32; /**< Key register */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_KEY_t__ */ + +/*@}*/ + +/** @defgroup WR_ABORT_ADDR Write Abort Address (WR_ABORT_ADDR) Register + * Write Abort Address (WR_ABORT_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_WR_ABORT_ADDR_Struct + *! \brief Write Abort Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ +typedef struct _ADI_FLCC_WR_ABORT_ADDR_t { + union { + struct { + unsigned int VALUE : 32; /**< Address of recently aborted write command */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_WR_ABORT_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WR_ABORT_ADDR_t__ */ + +/*@}*/ + +/** @defgroup WRPROT Write Protection (WRPROT) Register + * Write Protection (WRPROT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_WRPROT_Struct + *! \brief Write Protection Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ +typedef struct _ADI_FLCC_WRPROT_t { + union { + struct { + unsigned int WORD : 32; /**< Clear bits to write protect related groups of user space pages */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_WRPROT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_WRPROT_t__ */ + +/*@}*/ + +/** @defgroup SIGNATURE Signature (SIGNATURE) Register + * Signature (SIGNATURE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_SIGNATURE_Struct + *! \brief Signature Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ +typedef struct _ADI_FLCC_SIGNATURE_t { + union { + struct { + unsigned int VALUE : 32; /**< Read signature */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_SIGNATURE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_SIGNATURE_t__ */ + +/*@}*/ + +/** @defgroup UCFG User Configuration (UCFG) Register + * User Configuration (UCFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_UCFG_Struct + *! \brief User Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ +typedef struct _ADI_FLCC_UCFG_t { + union { + struct { + unsigned int KHDMAEN : 1; /**< Key hole DMA enable */ + unsigned int AUTOINCEN : 1; /**< Auto Address Increment for Key Hole Access */ + unsigned int reserved2 : 30; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_UCFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_UCFG_t__ */ + +/*@}*/ + +/** @defgroup TIME_PARAM0 Time Parameter 0 (TIME_PARAM0) Register + * Time Parameter 0 (TIME_PARAM0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_TIME_PARAM0_Struct + *! \brief Time Parameter 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ +typedef struct _ADI_FLCC_TIME_PARAM0_t { + union { + struct { + unsigned int DIVREFCLK : 1; /**< Divide Reference Clock (by 2) */ + unsigned int reserved1 : 3; + unsigned int TNVS : 4; /**< PROG/ERASE to NVSTR setup time */ + unsigned int TPGS : 4; /**< NVSTR to Program setup time */ + unsigned int TPROG : 4; /**< Program time */ + unsigned int TNVH : 4; /**< NVSTR Hold time */ + unsigned int TRCV : 4; /**< Recovery time */ + unsigned int TERASE : 4; /**< Erase Time */ + unsigned int TNVH1 : 4; /**< NVSTR Hold time during Mass Erase */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_TIME_PARAM0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM0_t__ */ + +/*@}*/ + +/** @defgroup TIME_PARAM1 Time Parameter 1 (TIME_PARAM1) Register + * Time Parameter 1 (TIME_PARAM1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_TIME_PARAM1_Struct + *! \brief Time Parameter 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ +typedef struct _ADI_FLCC_TIME_PARAM1_t { + union { + struct { + unsigned int TWK : 4; /**< Wake up time */ + unsigned int WAITSTATES : 3; /**< Number of wait states to access flash */ + unsigned int reserved7 : 1; + unsigned int CURWAITSTATES : 3; /**< Current wait states [2:0] */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_TIME_PARAM1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_TIME_PARAM1_t__ */ + +/*@}*/ + +/** @defgroup ABORT_EN_LO IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register + * IRQ Abort Enable (Lower Bits) (ABORT_EN_LO) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ABORT_EN_LO_Struct + *! \brief IRQ Abort Enable (Lower Bits) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ +typedef struct _ADI_FLCC_ABORT_EN_LO_t { + union { + struct { + unsigned int VALUE : 32; /**< VALUE[31:0] Sys IRQ Abort Enable */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ABORT_EN_LO_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_LO_t__ */ + +/*@}*/ + +/** @defgroup ABORT_EN_HI IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register + * IRQ Abort Enable (Upper Bits) (ABORT_EN_HI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ABORT_EN_HI_Struct + *! \brief IRQ Abort Enable (Upper Bits) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ +typedef struct _ADI_FLCC_ABORT_EN_HI_t { + union { + struct { + unsigned int VALUE : 32; /**< VALUE[63:32] Sys IRQ Abort Enable */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ABORT_EN_HI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ABORT_EN_HI_t__ */ + +/*@}*/ + +/** @defgroup ECC_CFG ECC Configuration (ECC_CFG) Register + * ECC Configuration (ECC_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ECC_CFG_Struct + *! \brief ECC Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ +typedef struct _ADI_FLCC_ECC_CFG_t { + union { + struct { + unsigned int EN : 1; /**< ECC Enable */ + unsigned int INFOEN : 1; /**< Info space ECC Enable bit */ + unsigned int reserved2 : 6; + unsigned int PTR : 24; /**< ECC start page pointer */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ECC_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_CFG_t__ */ + +/*@}*/ + +/** @defgroup ECC_ADDR ECC Status (Address) (ECC_ADDR) Register + * ECC Status (Address) (ECC_ADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_ECC_ADDR_Struct + *! \brief ECC Status (Address) Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ +typedef struct _ADI_FLCC_ECC_ADDR_t { + union { + struct { + unsigned int VALUE : 20; /**< This register has the address for which ECC error is detected */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_ECC_ADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_ECC_ADDR_t__ */ + +/*@}*/ + +/** @defgroup POR_SEC Flash Security (POR_SEC) Register + * Flash Security (POR_SEC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_POR_SEC_Struct + *! \brief Flash Security Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ +typedef struct _ADI_FLCC_POR_SEC_t { + union { + struct { + unsigned int SECURE : 1; /**< Set this bit to prevent read or write access to User Space (sticky when set) */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_POR_SEC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_POR_SEC_t__ */ + +/*@}*/ + +/** @defgroup VOL_CFG Volatile Flash Configuration (VOL_CFG) Register + * Volatile Flash Configuration (VOL_CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_VOL_CFG_Struct + *! \brief Volatile Flash Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ +typedef struct _ADI_FLCC_VOL_CFG_t { + union { + struct { + unsigned int INFO_REMAP : 1; /**< Alias the info space to the base address of user space */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_VOL_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_VOL_CFG_t__ */ + +/*@}*/ + +/** @defgroup STAT Cache Status Register (STAT) Register + * Cache Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_STAT_Struct + *! \brief Cache Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ +typedef struct _ADI_FLCC_CACHE_STAT_t { + union { + struct { + unsigned int ICEN : 1; /**< If this bit is set, I-Cache is enabled */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_STAT_t__ */ + +/*@}*/ + +/** @defgroup SETUP Cache Setup Register (SETUP) Register + * Cache Setup Register (SETUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_SETUP_Struct + *! \brief Cache Setup Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ +typedef struct _ADI_FLCC_CACHE_SETUP_t { + union { + struct { + unsigned int ICEN : 1; /**< If this bit set, I-Cache is enabled for AHB accesses */ + unsigned int LCKIC : 1; /**< If this bit is set, I-Cache contents are locked */ + unsigned int reserved2 : 30; + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_SETUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_SETUP_t__ */ + +/*@}*/ + +/** @defgroup KEY Cache Key Register (KEY) Register + * Cache Key Register (KEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_FLCC_CACHE_KEY_Struct + *! \brief Cache Key Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ +typedef struct _ADI_FLCC_CACHE_KEY_t { + union { + struct { + unsigned int VALUE : 32; /**< Cache Key */ + }; + uint32_t VALUE32; + }; +} ADI_FLCC_CACHE_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_FLCC_CACHE_KEY_t__ */ + +/*@}*/ + +/** @defgroup CFG Port Configuration (CFG) Register + * Port Configuration (CFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_CFG_Struct + *! \brief Port Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ +typedef struct _ADI_GPIO_CFG_t { + union { + struct { + unsigned int PIN00 : 2; /**< Pin 0 configuration bits */ + unsigned int PIN01 : 2; /**< Pin 1 configuration bits */ + unsigned int PIN02 : 2; /**< Pin 2 configuration bits */ + unsigned int PIN03 : 2; /**< Pin 3 configuration bits */ + unsigned int PIN04 : 2; /**< Pin 4 configuration bits */ + unsigned int PIN05 : 2; /**< Pin 5 configuration bits */ + unsigned int PIN06 : 2; /**< Pin 6 configuration bits */ + unsigned int PIN07 : 2; /**< Pin 7 configuration bits */ + unsigned int PIN08 : 2; /**< Pin 8 configuration bits */ + unsigned int PIN09 : 2; /**< Pin 9 configuration bits */ + unsigned int PIN10 : 2; /**< Pin 10 configuration bits */ + unsigned int PIN11 : 2; /**< Pin 11 configuration bits */ + unsigned int PIN12 : 2; /**< Pin 12 configuration bits */ + unsigned int PIN13 : 2; /**< Pin 13 configuration bits */ + unsigned int PIN14 : 2; /**< Pin 14 configuration bits */ + unsigned int PIN15 : 2; /**< Pin 15 configuration bits */ + }; + uint32_t VALUE32; + }; +} ADI_GPIO_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CFG_t__ */ + +/*@}*/ + +/** @defgroup OEN Port Output Enable (OEN) Register + * Port Output Enable (OEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_OEN_Struct + *! \brief Port Output Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ +typedef struct _ADI_GPIO_OEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Pin Output Drive enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_OEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OEN_t__ */ + +/*@}*/ + +/** @defgroup PE Port Output Pull-up/Pull-down Enable (PE) Register + * Port Output Pull-up/Pull-down Enable (PE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_PE_Struct + *! \brief Port Output Pull-up/Pull-down Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ +typedef struct _ADI_GPIO_PE_t { + union { + struct { + unsigned int VALUE : 16; /**< Pin Pull enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_PE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_PE_t__ */ + +/*@}*/ + +/** @defgroup IEN Port Input Path Enable (IEN) Register + * Port Input Path Enable (IEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IEN_Struct + *! \brief Port Input Path Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ +typedef struct _ADI_GPIO_IEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Input path enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IEN_t__ */ + +/*@}*/ + +/** @defgroup IN Port Registered Data Input (IN) Register + * Port Registered Data Input (IN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IN_Struct + *! \brief Port Registered Data Input Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ +typedef struct _ADI_GPIO_IN_t { + union { + struct { + unsigned int VALUE : 16; /**< Registered data input */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IN_t__ */ + +/*@}*/ + +/** @defgroup OUT Port Data Output (OUT) Register + * Port Data Output (OUT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_OUT_Struct + *! \brief Port Data Output Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ +typedef struct _ADI_GPIO_OUT_t { + union { + struct { + unsigned int VALUE : 16; /**< Data out */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_OUT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_OUT_t__ */ + +/*@}*/ + +/** @defgroup SET Port Data Out Set (SET) Register + * Port Data Out Set (SET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_SET_Struct + *! \brief Port Data Out Set Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ +typedef struct _ADI_GPIO_SET_t { + union { + struct { + unsigned int VALUE : 16; /**< Set the output HIGH for the pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_SET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_SET_t__ */ + +/*@}*/ + +/** @defgroup CLR Port Data Out Clear (CLR) Register + * Port Data Out Clear (CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_CLR_Struct + *! \brief Port Data Out Clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ +typedef struct _ADI_GPIO_CLR_t { + union { + struct { + unsigned int VALUE : 16; /**< Set the output low for the port pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_CLR_t__ */ + +/*@}*/ + +/** @defgroup TGL Port Pin Toggle (TGL) Register + * Port Pin Toggle (TGL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_TGL_Struct + *! \brief Port Pin Toggle Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ +typedef struct _ADI_GPIO_TGL_t { + union { + struct { + unsigned int VALUE : 16; /**< Toggle the output of the port pin */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_TGL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_TGL_t__ */ + +/*@}*/ + +/** @defgroup POL Port Interrupt Polarity (POL) Register + * Port Interrupt Polarity (POL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_POL_Struct + *! \brief Port Interrupt Polarity Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ +typedef struct _ADI_GPIO_POL_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt polarity */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_POL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_POL_t__ */ + +/*@}*/ + +/** @defgroup IENA Port Interrupt A Enable (IENA) Register + * Port Interrupt A Enable (IENA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IENA_Struct + *! \brief Port Interrupt A Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ +typedef struct _ADI_GPIO_IENA_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt A enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IENA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENA_t__ */ + +/*@}*/ + +/** @defgroup IENB Port Interrupt B Enable (IENB) Register + * Port Interrupt B Enable (IENB) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_IENB_Struct + *! \brief Port Interrupt B Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ +typedef struct _ADI_GPIO_IENB_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt B enable */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_IENB_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_IENB_t__ */ + +/*@}*/ + +/** @defgroup INT Port Interrupt Status (INT) Register + * Port Interrupt Status (INT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_INT_Struct + *! \brief Port Interrupt Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ +typedef struct _ADI_GPIO_INT_t { + union { + struct { + unsigned int VALUE : 16; /**< Interrupt Status */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_INT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_INT_t__ */ + +/*@}*/ + +/** @defgroup DS Port Drive Strength Select (DS) Register + * Port Drive Strength Select (DS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_GPIO_DS_Struct + *! \brief Port Drive Strength Select Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ +typedef struct _ADI_GPIO_DS_t { + union { + struct { + unsigned int VALUE : 16; /**< Drive strength select */ + }; + uint16_t VALUE16; + }; +} ADI_GPIO_DS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_GPIO_DS_t__ */ + +/*@}*/ + +/** @defgroup CTL_A Half SPORT 'A' Control Register (CTL_A) Register + * Half SPORT 'A' Control Register (CTL_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_SPEN + *! \brief Serial Port Enable (SPEN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_EN = 1 /**< Enable */ +} ADI_SPORT_CTL_A_SPEN; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_FSMUXSEL + *! \brief Frame Sync Multiplexer Select (FSMUXSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_MUX_DIS = 0, /**< Disable frame sync multiplexing */ + SPORT_CTL_A_CTL_FS_MUX_EN = 1 /**< Enable frame sync multiplexing */ +} ADI_SPORT_CTL_A_FSMUXSEL; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_CKMUXSEL + *! \brief Clock Multiplexer Select (CKMUXSEL) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_CLK_MUX_DIS = 0, /**< Disable serial clock multiplexing */ + SPORT_CTL_A_CTL_CLK_MUX_EN = 1 /**< Enable serial clock multiplexing */ +} ADI_SPORT_CTL_A_CKMUXSEL; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LSBF + *! \brief Least-Significant Bit First (LSBF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_MSB_FIRST = 0, /**< MSB first sent/received */ + SPORT_CTL_A_CTL_LSB_FIRST = 1 /**< LSB first sent/received */ +} ADI_SPORT_CTL_A_LSBF; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_ICLK + *! \brief Internal Clock (ICLK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EXTERNAL_CLK = 0, /**< External clock */ + SPORT_CTL_A_CTL_INTERNAL_CLK = 1 /**< Internal clock */ +} ADI_SPORT_CTL_A_ICLK; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_OPMODE + *! \brief Operation mode (OPMODE) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_SERIAL = 0, /**< DSP standard */ + SPORT_CTL_A_CTL_TIMER_EN_MODE = 1 /**< Timer_enable mode */ +} ADI_SPORT_CTL_A_OPMODE; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_CKRE + *! \brief Clock Rising Edge (CKRE) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_CLK_FALL_EDGE = 0, /**< Clock falling edge */ + SPORT_CTL_A_CTL_CLK_RISE_EDGE = 1 /**< Clock rising edge */ +} ADI_SPORT_CTL_A_CKRE; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_FSR + *! \brief Frame Sync Required (FSR) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_NOT_REQ = 0, /**< No frame sync required */ + SPORT_CTL_A_CTL_FS_REQ = 1 /**< Frame sync required */ +} ADI_SPORT_CTL_A_FSR; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_IFS + *! \brief Internal Frame Sync (IFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EXTERNAL_FS = 0, /**< External frame sync */ + SPORT_CTL_A_CTL_INTERNAL_FS = 1 /**< Internal frame sync */ +} ADI_SPORT_CTL_A_IFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_DIFS + *! \brief Data-Independent Frame Sync (DIFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_DATA_DEP_FS = 0, /**< Data-dependent frame sync */ + SPORT_CTL_A_CTL_DATA_INDP_FS = 1 /**< Data-independent frame sync */ +} ADI_SPORT_CTL_A_DIFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LFS + *! \brief Active-Low Frame Sync (LFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_FS_LO = 0, /**< Active high frame sync */ + SPORT_CTL_A_CTL_FS_HI = 1 /**< Active low frame sync */ +} ADI_SPORT_CTL_A_LFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_LAFS + *! \brief Late Frame Sync (LAFS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_EARLY_FS = 0, /**< Early frame sync */ + SPORT_CTL_A_CTL_LATE_FS = 1 /**< Late frame sync */ +} ADI_SPORT_CTL_A_LAFS; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_PACK + *! \brief Packing Enable (PACK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_PACK_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_PACK_8BIT = 1, /**< 8-bit packing enable */ + SPORT_CTL_A_CTL_PACK_16BIT = 2 /**< 16-bit packing enable */ +} ADI_SPORT_CTL_A_PACK; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_GCLKEN + *! \brief Gated Clock Enable (GCLKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_GCLK_DIS = 0, /**< Disable */ + SPORT_CTL_A_CTL_GCLK_EN = 1 /**< Enable */ +} ADI_SPORT_CTL_A_GCLKEN; + + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_A_SPTRAN + *! \brief Serial Port Transfer Direction (SPTRAN) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_A_CTL_RX = 0, /**< Receive */ + SPORT_CTL_A_CTL_TX = 1 /**< Transmit */ +} ADI_SPORT_CTL_A_SPTRAN; + + +/* ========================================================================== + *! \struct ADI_SPORT_CTL_A_Struct + *! \brief Half SPORT 'A' Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ +typedef struct _ADI_SPORT_CTL_A_t { + union { + struct { + unsigned int SPEN : 1; /**< Serial Port Enable */ + unsigned int FSMUXSEL : 1; /**< Frame Sync Multiplexer Select */ + unsigned int CKMUXSEL : 1; /**< Clock Multiplexer Select */ + unsigned int LSBF : 1; /**< Least-Significant Bit First */ + unsigned int SLEN : 5; /**< Serial Word Length */ + unsigned int reserved9 : 1; + unsigned int ICLK : 1; /**< Internal Clock */ + unsigned int OPMODE : 1; /**< Operation mode */ + unsigned int CKRE : 1; /**< Clock Rising Edge */ + unsigned int FSR : 1; /**< Frame Sync Required */ + unsigned int IFS : 1; /**< Internal Frame Sync */ + unsigned int DIFS : 1; /**< Data-Independent Frame Sync */ + unsigned int LFS : 1; /**< Active-Low Frame Sync */ + unsigned int LAFS : 1; /**< Late Frame Sync */ + unsigned int PACK : 2; /**< Packing Enable */ + unsigned int FSERRMODE : 1; /**< Frame Sync Error Operation */ + unsigned int GCLKEN : 1; /**< Gated Clock Enable */ + unsigned int reserved22 : 3; + unsigned int SPTRAN : 1; /**< Serial Port Transfer Direction */ + unsigned int DMAEN : 1; /**< DMA Enable */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CTL_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_A_t__ */ + +/*@}*/ + +/** @defgroup DIV_A Half SPORT 'A' Divisor Register (DIV_A) Register + * Half SPORT 'A' Divisor Register (DIV_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_DIV_A_Struct + *! \brief Half SPORT 'A' Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ +typedef struct _ADI_SPORT_DIV_A_t { + union { + struct { + unsigned int CLKDIV : 16; /**< Clock Divisor */ + unsigned int FSDIV : 8; /**< Frame Sync Divisor */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_DIV_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_A_t__ */ + +/*@}*/ + +/** @defgroup IEN_A Half SPORT A's Interrupt Enable register (IEN_A) Register + * Half SPORT A's Interrupt Enable register (IEN_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_IEN_A_TF + *! \brief Transfer Finish Interrupt Enable (TF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_IEN_A_CTL_TXFIN_DIS = 0, /**< Transfer finish Interrupt is disabled */ + SPORT_IEN_A_CTL_TXFIN_EN = 1 /**< Transfer Finish Interrupt is Enabled */ +} ADI_SPORT_IEN_A_TF; + + +/* ========================================================================== + *! \struct ADI_SPORT_IEN_A_Struct + *! \brief Half SPORT A's Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ +typedef struct _ADI_SPORT_IEN_A_t { + union { + struct { + unsigned int TF : 1; /**< Transfer Finish Interrupt Enable */ + unsigned int DERRMSK : 1; /**< Data Error (Interrupt) Mask */ + unsigned int FSERRMSK : 1; /**< Frame Sync Error (Interrupt) Mask */ + unsigned int DATA : 1; /**< Data request interrupt to the core */ + unsigned int SYSDATERR : 1; /**< Data error for system writes or reads */ + unsigned int reserved5 : 27; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_IEN_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_A_t__ */ + +/*@}*/ + +/** @defgroup STAT_A Half SPORT 'A' Status register (STAT_A) Register + * Half SPORT 'A' Status register (STAT_A) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_STAT_A_DXS + *! \brief Data Transfer Buffer Status (DXS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_STAT_A_CTL_EMPTY = 0, /**< Empty */ + SPORT_STAT_A_CTL_PART_FULL = 2, /**< Partially full */ + SPORT_STAT_A_CTL_FULL = 3 /**< Full */ +} ADI_SPORT_STAT_A_DXS; + + +/* ========================================================================== + *! \struct ADI_SPORT_STAT_A_Struct + *! \brief Half SPORT 'A' Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ +typedef struct _ADI_SPORT_STAT_A_t { + union { + struct { + unsigned int TFI : 1; /**< Transmit Finish Interrupt Status */ + unsigned int DERR : 1; /**< Data Error Status */ + unsigned int FSERR : 1; /**< Frame Sync Error Status */ + unsigned int DATA : 1; /**< Data Buffer status */ + unsigned int SYSDATERR : 1; /**< System Data Error Status */ + unsigned int reserved5 : 3; + unsigned int DXS : 2; /**< Data Transfer Buffer Status */ + unsigned int reserved10 : 22; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_STAT_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_A_t__ */ + +/*@}*/ + +/** @defgroup NUMTRAN_A Half SPORT A Number of transfers register (NUMTRAN_A) Register + * Half SPORT A Number of transfers register (NUMTRAN_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_NUMTRAN_A_Struct + *! \brief Half SPORT A Number of transfers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ +typedef struct _ADI_SPORT_NUMTRAN_A_t { + union { + struct { + unsigned int VALUE : 12; /**< Number of transfers (Half SPORT A) */ + unsigned int reserved12 : 20; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_NUMTRAN_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_A_t__ */ + +/*@}*/ + +/** @defgroup CNVT_A Half SPORT 'A' CNV width (CNVT_A) Register + * Half SPORT 'A' CNV width (CNVT_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_CNVT_A_Struct + *! \brief Half SPORT 'A' CNV width Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ +typedef struct _ADI_SPORT_CNVT_A_t { + union { + struct { + unsigned int WID : 4; /**< CNV signal width: Half SPORT A */ + unsigned int reserved4 : 4; + unsigned int POL : 1; /**< Polarity of the CNV signal */ + unsigned int reserved9 : 7; + unsigned int CNVT2FS : 8; /**< CNV to FS duration: Half SPORT A */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CNVT_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_A_t__ */ + +/*@}*/ + +/** @defgroup TX_A Half SPORT 'A' Tx Buffer Register (TX_A) Register + * Half SPORT 'A' Tx Buffer Register (TX_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_TX_A_Struct + *! \brief Half SPORT 'A' Tx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ +typedef struct _ADI_SPORT_TX_A_t { + union { + struct { + unsigned int VALUE : 32; /**< Transmit Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_TX_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_A_t__ */ + +/*@}*/ + +/** @defgroup RX_A Half SPORT 'A' Rx Buffer Register (RX_A) Register + * Half SPORT 'A' Rx Buffer Register (RX_A) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_RX_A_Struct + *! \brief Half SPORT 'A' Rx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ +typedef struct _ADI_SPORT_RX_A_t { + union { + struct { + unsigned int VALUE : 32; /**< Receive Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_RX_A_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_A_t__ */ + +/*@}*/ + +/** @defgroup CTL_B Half SPORT 'B' Control Register (CTL_B) Register + * Half SPORT 'B' Control Register (CTL_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_CTL_B_PACK + *! \brief Packing Enable (PACK) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_CTL_B_CTL_PACK_DIS = 0, /**< Disable */ + SPORT_CTL_B_CTL_PACK_8BIT = 1, /**< 8-bit packing enable */ + SPORT_CTL_B_CTL_PACK_16BIT = 2 /**< 16-bit packing enable */ +} ADI_SPORT_CTL_B_PACK; + + +/* ========================================================================== + *! \struct ADI_SPORT_CTL_B_Struct + *! \brief Half SPORT 'B' Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ +typedef struct _ADI_SPORT_CTL_B_t { + union { + struct { + unsigned int SPEN : 1; /**< Serial Port Enable */ + unsigned int reserved1 : 2; + unsigned int LSBF : 1; /**< Least-Significant Bit First */ + unsigned int SLEN : 5; /**< Serial Word Length */ + unsigned int reserved9 : 1; + unsigned int ICLK : 1; /**< Internal Clock */ + unsigned int OPMODE : 1; /**< Operation mode */ + unsigned int CKRE : 1; /**< Clock Rising Edge */ + unsigned int FSR : 1; /**< Frame Sync Required */ + unsigned int IFS : 1; /**< Internal Frame Sync */ + unsigned int DIFS : 1; /**< Data-Independent Frame Sync */ + unsigned int LFS : 1; /**< Active-Low Frame Sync */ + unsigned int LAFS : 1; /**< Late Frame Sync */ + unsigned int PACK : 2; /**< Packing Enable */ + unsigned int FSERRMODE : 1; /**< Frame Sync Error Operation */ + unsigned int GCLKEN : 1; /**< Gated Clock Enable */ + unsigned int reserved22 : 3; + unsigned int SPTRAN : 1; /**< Serial Port Transfer Direction */ + unsigned int DMAEN : 1; /**< DMA Enable */ + unsigned int reserved27 : 5; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CTL_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CTL_B_t__ */ + +/*@}*/ + +/** @defgroup DIV_B Half SPORT 'B' Divisor Register (DIV_B) Register + * Half SPORT 'B' Divisor Register (DIV_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_DIV_B_Struct + *! \brief Half SPORT 'B' Divisor Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ +typedef struct _ADI_SPORT_DIV_B_t { + union { + struct { + unsigned int CLKDIV : 16; /**< Clock Divisor */ + unsigned int FSDIV : 8; /**< Frame Sync Divisor */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_DIV_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_DIV_B_t__ */ + +/*@}*/ + +/** @defgroup IEN_B Half SPORT B's Interrupt Enable register (IEN_B) Register + * Half SPORT B's Interrupt Enable register (IEN_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_IEN_B_TF + *! \brief Transmit Finish Interrupt Enable (TF) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_IEN_B_CTL_TXFIN_DIS = 0, /**< Transfer Finish Interrupt is disabled */ + SPORT_IEN_B_CTL_TXFIN_EN = 1 /**< Transfer Finish Interrupt is Enabled */ +} ADI_SPORT_IEN_B_TF; + + +/* ========================================================================== + *! \struct ADI_SPORT_IEN_B_Struct + *! \brief Half SPORT B's Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ +typedef struct _ADI_SPORT_IEN_B_t { + union { + struct { + unsigned int TF : 1; /**< Transmit Finish Interrupt Enable */ + unsigned int DERRMSK : 1; /**< Data Error (Interrupt) Mask */ + unsigned int FSERRMSK : 1; /**< Frame Sync Error (Interrupt) Mask */ + unsigned int DATA : 1; /**< Data request interrupt to the core */ + unsigned int SYSDATERR : 1; /**< Data error for system writes or reads */ + unsigned int reserved5 : 27; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_IEN_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_IEN_B_t__ */ + +/*@}*/ + +/** @defgroup STAT_B Half SPORT 'B' Status register (STAT_B) Register + * Half SPORT 'B' Status register (STAT_B) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_SPORT_STAT_B_DXS + *! \brief Data Transfer Buffer Status (DXS) Enumerations + * ========================================================================= */ +typedef enum +{ + SPORT_STAT_B_CTL_EMPTY = 0, /**< Empty */ + SPORT_STAT_B_CTL_PART_FULL = 2, /**< Partially full */ + SPORT_STAT_B_CTL_FULL = 3 /**< Full */ +} ADI_SPORT_STAT_B_DXS; + + +/* ========================================================================== + *! \struct ADI_SPORT_STAT_B_Struct + *! \brief Half SPORT 'B' Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ +typedef struct _ADI_SPORT_STAT_B_t { + union { + struct { + unsigned int TFI : 1; /**< Transmit Finish Interrupt Status */ + unsigned int DERR : 1; /**< Data Error Status */ + unsigned int FSERR : 1; /**< Frame Sync Error Status */ + unsigned int DATA : 1; /**< Data Buffer status */ + unsigned int SYSDATERR : 1; /**< System Data Error Status */ + unsigned int reserved5 : 3; + unsigned int DXS : 2; /**< Data Transfer Buffer Status */ + unsigned int reserved10 : 22; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_STAT_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_STAT_B_t__ */ + +/*@}*/ + +/** @defgroup NUMTRAN_B Half SPORT B Number of transfers register (NUMTRAN_B) Register + * Half SPORT B Number of transfers register (NUMTRAN_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_NUMTRAN_B_Struct + *! \brief Half SPORT B Number of transfers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ +typedef struct _ADI_SPORT_NUMTRAN_B_t { + union { + struct { + unsigned int VALUE : 12; /**< Number of transfers (Half SPORT A) */ + unsigned int reserved12 : 20; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_NUMTRAN_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_NUMTRAN_B_t__ */ + +/*@}*/ + +/** @defgroup CNVT_B Half SPORT 'B' CNV width register (CNVT_B) Register + * Half SPORT 'B' CNV width register (CNVT_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_CNVT_B_Struct + *! \brief Half SPORT 'B' CNV width Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ +typedef struct _ADI_SPORT_CNVT_B_t { + union { + struct { + unsigned int WID : 4; /**< CNV signal width: Half SPORT B */ + unsigned int reserved4 : 4; + unsigned int POL : 1; /**< Polarity of the CNV signal */ + unsigned int reserved9 : 7; + unsigned int CNVT2FS : 8; /**< CNV to FS duration: Half SPORT B */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_SPORT_CNVT_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_CNVT_B_t__ */ + +/*@}*/ + +/** @defgroup TX_B Half SPORT 'B' Tx Buffer Register (TX_B) Register + * Half SPORT 'B' Tx Buffer Register (TX_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_TX_B_Struct + *! \brief Half SPORT 'B' Tx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ +typedef struct _ADI_SPORT_TX_B_t { + union { + struct { + unsigned int VALUE : 32; /**< Transmit Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_TX_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_TX_B_t__ */ + +/*@}*/ + +/** @defgroup RX_B Half SPORT 'B' Rx Buffer Register (RX_B) Register + * Half SPORT 'B' Rx Buffer Register (RX_B) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_SPORT_RX_B_Struct + *! \brief Half SPORT 'B' Rx Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ +typedef struct _ADI_SPORT_RX_B_t { + union { + struct { + unsigned int VALUE : 32; /**< Receive Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_SPORT_RX_B_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_SPORT_RX_B_t__ */ + +/*@}*/ + +/** @defgroup CTL CRC Control (CTL) Register + * CRC Control (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CRC_CTL_EN + *! \brief CRC Peripheral Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_CRC_DIS = 0, /**< CRC peripheral is disabled */ + CRC_CTL_CRC_EN = 1 /**< CRC peripheral is enabled */ +} ADI_CRC_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_LSBFIRST + *! \brief LSB First Calculation Order (LSBFIRST) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_MSB_FIRST = 0, /**< MSB First CRC calculation is done */ + CRC_CTL_LSB_FIRST = 1 /**< LSB First CRC calculation is done */ +} ADI_CRC_CTL_LSBFIRST; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_BITMIRR + *! \brief Bit Mirroring (BITMIRR) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_BITMIRR_DIS = 0, /**< Bit Mirroring is disabled */ + CRC_CTL_BITMIRR_EN = 1 /**< Bit Mirroring is enabled */ +} ADI_CRC_CTL_BITMIRR; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_BYTMIRR + *! \brief Byte Mirroring (BYTMIRR) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_BYTEMIR_DIS = 0, /**< Byte Mirroring is disabled */ + CRC_CTL_BYTEMIR_EN = 1 /**< Byte Mirroring is enabled */ +} ADI_CRC_CTL_BYTMIRR; + + +/* ========================================================================= + *! \enum ADI_CRC_CTL_W16SWP + *! \brief Word16 Swap (W16SWP) Enumerations + * ========================================================================= */ +typedef enum +{ + CRC_CTL_W16SP_DIS = 0, /**< Word16 Swap disabled */ + CRC_CTL_W16SP_EN = 1 /**< Word16 Swap enabled */ +} ADI_CRC_CTL_W16SWP; + + +/* ========================================================================== + *! \struct ADI_CRC_CTL_Struct + *! \brief CRC Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ +typedef struct _ADI_CRC_CTL_t { + union { + struct { + unsigned int EN : 1; /**< CRC Peripheral Enable */ + unsigned int LSBFIRST : 1; /**< LSB First Calculation Order */ + unsigned int BITMIRR : 1; /**< Bit Mirroring */ + unsigned int BYTMIRR : 1; /**< Byte Mirroring */ + unsigned int W16SWP : 1; /**< Word16 Swap */ + unsigned int reserved5 : 23; + unsigned int RevID : 4; /**< Revision ID */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_CTL_t__ */ + +/*@}*/ + +/** @defgroup IPDATA Input Data Word (IPDATA) Register + * Input Data Word (IPDATA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPDATA_Struct + *! \brief Input Data Word Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ +typedef struct _ADI_CRC_IPDATA_t { + union { + struct { + unsigned int VALUE : 32; /**< Data Input */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_IPDATA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPDATA_t__ */ + +/*@}*/ + +/** @defgroup RESULT CRC Result (RESULT) Register + * CRC Result (RESULT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_RESULT_Struct + *! \brief CRC Result Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ +typedef struct _ADI_CRC_RESULT_t { + union { + struct { + unsigned int VALUE : 32; /**< CRC Residue */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_RESULT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_RESULT_t__ */ + +/*@}*/ + +/** @defgroup POLY Programmable CRC Polynomial (POLY) Register + * Programmable CRC Polynomial (POLY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_POLY_Struct + *! \brief Programmable CRC Polynomial Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ +typedef struct _ADI_CRC_POLY_t { + union { + struct { + unsigned int VALUE : 32; /**< CRC Reduction Polynomial */ + }; + uint32_t VALUE32; + }; +} ADI_CRC_POLY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_POLY_t__ */ + +/*@}*/ + +/** @defgroup IPBITS Input Data Bits (IPBITS) Register + * Input Data Bits (IPBITS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPBITS_Struct + *! \brief Input Data Bits Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ +typedef struct _ADI_CRC_IPBITS_t { + union { + struct { + unsigned int DATA_BITS : 8; /**< Input Data Bits */ + }; + uint8_t VALUE8; + }; +} ADI_CRC_IPBITS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBITS_t__ */ + +/*@}*/ + +/** @defgroup IPBYTE Input Data Byte (IPBYTE) Register + * Input Data Byte (IPBYTE) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRC_IPBYTE_Struct + *! \brief Input Data Byte Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ +typedef struct _ADI_CRC_IPBYTE_t { + union { + struct { + unsigned int DATA_BYTE : 8; /**< Input Data Byte */ + }; + uint8_t VALUE8; + }; +} ADI_CRC_IPBYTE_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRC_IPBYTE_t__ */ + +/*@}*/ + +/** @defgroup CTL RNG Control Register (CTL) Register + * RNG Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_RNG_CTL_EN + *! \brief RNG Enable (EN) Enumerations + * ========================================================================= */ +typedef enum +{ + RNG_CTL_DISABLE = 0, /**< Disable the RNG */ + RNG_CTL_ENABLE = 1 /**< Enable the RNG */ +} ADI_RNG_CTL_EN; + + +/* ========================================================================= + *! \enum ADI_RNG_CTL_SINGLE + *! \brief Generate a Single Number (SINGLE) Enumerations + * ========================================================================= */ +typedef enum +{ + RNG_CTL_WORD = 0, /**< Buffer Word */ + RNG_CTL_SINGLE = 1 /**< Single Byte */ +} ADI_RNG_CTL_SINGLE; + + +/* ========================================================================== + *! \struct ADI_RNG_CTL_Struct + *! \brief RNG Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ +typedef struct _ADI_RNG_CTL_t { + union { + struct { + unsigned int EN : 1; /**< RNG Enable */ + unsigned int reserved1 : 2; + unsigned int SINGLE : 1; /**< Generate a Single Number */ + unsigned int reserved4 : 12; + }; + uint16_t VALUE16; + }; +} ADI_RNG_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_CTL_t__ */ + +/*@}*/ + +/** @defgroup LEN RNG Sample Length Register (LEN) Register + * RNG Sample Length Register (LEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_LEN_Struct + *! \brief RNG Sample Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ +typedef struct _ADI_RNG_LEN_t { + union { + struct { + unsigned int RELOAD : 12; /**< Reload Value for the Sample Counter */ + unsigned int PRESCALE : 4; /**< Prescaler for the Sample Counter */ + }; + uint16_t VALUE16; + }; +} ADI_RNG_LEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_LEN_t__ */ + +/*@}*/ + +/** @defgroup STAT RNG Status Register (STAT) Register + * RNG Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_STAT_Struct + *! \brief RNG Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ +typedef struct _ADI_RNG_STAT_t { + union { + struct { + unsigned int RNRDY : 1; /**< Random Number Ready */ + unsigned int STUCK : 1; /**< Sampled Data Stuck High or Low */ + unsigned int reserved2 : 14; + }; + uint16_t VALUE16; + }; +} ADI_RNG_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_STAT_t__ */ + +/*@}*/ + +/** @defgroup DATA RNG Data Register (DATA) Register + * RNG Data Register (DATA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_DATA_Struct + *! \brief RNG Data Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ +typedef struct _ADI_RNG_DATA_t { + union { + struct { + unsigned int VALUE : 8; /**< Value of the CRC Accumulator */ + unsigned int BUFF : 24; /**< Buffer for RNG Data */ + }; + uint32_t VALUE32; + }; +} ADI_RNG_DATA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_DATA_t__ */ + +/*@}*/ + +/** @defgroup OSCCNT Oscillator Count (OSCCNT) Register + * Oscillator Count (OSCCNT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_OSCCNT_Struct + *! \brief Oscillator Count Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ +typedef struct _ADI_RNG_OSCCNT_t { + union { + struct { + unsigned int VALUE : 28; /**< Oscillator Count */ + unsigned int reserved28 : 4; + }; + uint32_t VALUE32; + }; +} ADI_RNG_OSCCNT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCCNT_t__ */ + +/*@}*/ + +/** @defgroup OSCDIFF Oscillator Difference (OSCDIFF) Register + * Oscillator Difference (OSCDIFF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_RNG_OSCDIFF_Struct + *! \brief Oscillator Difference Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ +typedef struct _ADI_RNG_OSCDIFF_t { + union { + struct { + signed int DELTA : 8; /**< Oscillator Count Difference */ + }; + int8_t VALUE8; + }; +} ADI_RNG_OSCDIFF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_RNG_OSCDIFF_t__ */ + +/*@}*/ + +/** @defgroup CFG Configuration Register (CFG) Register + * Configuration Register (CFG) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_BLKEN + *! \brief Enable Bit for Crypto Block (BLKEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_ENABLE = 0, /**< Enable Crypto Block */ + CRYPT_CFG_DISABLE = 1 /**< Disable Crypto Block */ +} ADI_CRYPT_CFG_BLKEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_INDMAEN + *! \brief Enable DMA Channel Request for Input Buffer (INDMAEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_DMA_DISABLE_INBUF = 0, /**< Disable DMA Requesting for Input Buffer */ + CRYPT_CFG_DMA_ENABLE_INBUF = 1 /**< Enable DMA Requesting for Input Buffer */ +} ADI_CRYPT_CFG_INDMAEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_OUTDMAEN + *! \brief Enable DMA Channel Request for Output Buffer (OUTDMAEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_DMA_DISABLE_OUTBUF = 0, /**< Disable DMA Requesting for Output Buffer */ + CRYPT_CFG_DMA_ENABLE_OUTBUF = 1 /**< Enable DMA Requesting for Output Buffer */ +} ADI_CRYPT_CFG_OUTDMAEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_AESKEYLEN + *! \brief Select Key Length for AES Cipher (AESKEYLEN) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_AESKEYLEN128 = 0, /**< Uses 128-bit long key */ + CRYPT_CFG_AESKEYLEN256 = 2 /**< Uses 256-bit long key */ +} ADI_CRYPT_CFG_AESKEYLEN; + + +/* ========================================================================= + *! \enum ADI_CRYPT_CFG_KUWKeyLen + *! \brief Key Length Key Wrap Unwrap (KUWKeyLen) Enumerations + * ========================================================================= */ +typedef enum +{ + CRYPT_CFG_LEN128 = 1, /**< The key size of KUW key is 128 bits */ + CRYPT_CFG_LEN256 = 2, /**< The key size of KUW key is 256 bits */ + CRYPT_CFG_LEN512 = 3 /**< The key size of KUW key is 512 bits */ +} ADI_CRYPT_CFG_KUWKeyLen; + + +/* ========================================================================== + *! \struct ADI_CRYPT_CFG_Struct + *! \brief Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ +typedef struct _ADI_CRYPT_CFG_t { + union { + struct { + unsigned int BLKEN : 1; /**< Enable Bit for Crypto Block */ + unsigned int ENCR : 1; /**< Encrypt or Decrypt */ + unsigned int INDMAEN : 1; /**< Enable DMA Channel Request for Input Buffer */ + unsigned int OUTDMAEN : 1; /**< Enable DMA Channel Request for Output Buffer */ + unsigned int INFLUSH : 1; /**< Input Buffer Flush */ + unsigned int OUTFLUSH : 1; /**< Output Buffer Flush */ + unsigned int reserved6 : 2; + unsigned int AESKEYLEN : 2; /**< Select Key Length for AES Cipher */ + unsigned int KUWKeyLen : 2; /**< Key Length Key Wrap Unwrap */ + unsigned int AES_BYTESWAP : 1; /**< Byteswap for AES Input */ + unsigned int SHA_BYTESWAP : 1; /**< Enable Key Wrap */ + unsigned int KEY_BYTESWAP : 1; /**< Use Key Unwrap Before HMAC */ + unsigned int PRKSTOREN : 1; /**< Enable PRKSTOR Commands */ + unsigned int ECBEN : 1; /**< Enable ECB Mode Operation */ + unsigned int CTREN : 1; /**< Enable CTR Mode Operation */ + unsigned int CBCEN : 1; /**< Enable CBC Mode Operation */ + unsigned int CCMEN : 1; /**< Enable CCM/CCM* Mode Operation */ + unsigned int CMACEN : 1; /**< Enable CMAC Mode Operation */ + unsigned int HMACEN : 1; /**< HMAC Enable */ + unsigned int reserved22 : 3; + unsigned int SHA256EN : 1; /**< Enable SHA-256 Operation */ + unsigned int SHAINIT : 1; /**< Restarts SHA Computation */ + unsigned int reserved27 : 1; + unsigned int RevID : 4; /**< Rev ID for Crypto */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CFG_t__ */ + +/*@}*/ + +/** @defgroup DATALEN Payload Data Length (DATALEN) Register + * Payload Data Length (DATALEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_DATALEN_Struct + *! \brief Payload Data Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ +typedef struct _ADI_CRYPT_DATALEN_t { + union { + struct { + unsigned int VALUE : 20; /**< Length of Payload Data */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_DATALEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_DATALEN_t__ */ + +/*@}*/ + +/** @defgroup PREFIXLEN Authentication Data Length (PREFIXLEN) Register + * Authentication Data Length (PREFIXLEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_PREFIXLEN_Struct + *! \brief Authentication Data Length Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ +typedef struct _ADI_CRYPT_PREFIXLEN_t { + union { + struct { + unsigned int VALUE : 16; /**< Length of Associated Data */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_PREFIXLEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PREFIXLEN_t__ */ + +/*@}*/ + +/** @defgroup INTEN Interrupt Enable Register (INTEN) Register + * Interrupt Enable Register (INTEN) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_INTEN_Struct + *! \brief Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ +typedef struct _ADI_CRYPT_INTEN_t { + union { + struct { + unsigned int INRDYEN : 1; /**< Enable Input Ready Interrupt */ + unsigned int OUTRDYEN : 1; /**< Enables the Output Ready Interrupt */ + unsigned int INOVREN : 1; /**< Enable Input Overflow Interrupt */ + unsigned int reserved3 : 2; + unsigned int SHADONEN : 1; /**< Enable SHA_Done Interrupt */ + unsigned int HMACDONEEN : 1; /**< Interrupt Enable for HMAC Done */ + unsigned int HMACMSGRDYEN : 1; /**< Status Bit for HMAC Message Input Ready */ + unsigned int PRKSTRCMDONEEN : 1; /**< PRKSTOR CMD DONE INTEN */ + unsigned int reserved9 : 23; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_INTEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INTEN_t__ */ + +/*@}*/ + +/** @defgroup STAT Status Register (STAT) Register + * Status Register (STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_STAT_Struct + *! \brief Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ +typedef struct _ADI_CRYPT_STAT_t { + union { + struct { + unsigned int INRDY : 1; /**< Input Buffer Status */ + unsigned int OUTRDY : 1; /**< Output Data Ready */ + unsigned int INOVR : 1; /**< Overflow in the Input Buffer */ + unsigned int reserved3 : 2; + unsigned int SHADONE : 1; /**< SHA Computation Complete */ + unsigned int SHABUSY : 1; /**< SHA Busy. in Computation */ + unsigned int INWORDS : 3; /**< Number of Words in the Input Buffer */ + unsigned int OUTWORDS : 3; /**< Number of Words in the Output Buffer */ + unsigned int HMACBUSY : 1; /**< Status Bit Indicates HMAC Busy */ + unsigned int HMACDONE : 1; /**< Status Bit Indicates HMAC Done */ + unsigned int HMACMSGRDY : 1; /**< Status Bit Indicates HMAC is Message Ready */ + unsigned int reserved16 : 7; + unsigned int PRKSTOR_CMD_DONE : 1; /**< Indicates Command Done for PrKStor */ + unsigned int PRKSTOR_CMD_FAIL : 1; /**< Indicates Last Command Issued Failed */ + unsigned int PRKSTOR_RET_STATUS : 2; /**< ECC Errors in the PRKSTOR_RETRIEVE Command */ + unsigned int CMD_ISSUED : 4; /**< Last Command Issued to PrKStor; */ + unsigned int PRKSTOR_BUSY : 1; /**< Indicates PrKSTOR is Busy */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_STAT_t__ */ + +/*@}*/ + +/** @defgroup INBUF Input Buffer (INBUF) Register + * Input Buffer (INBUF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_INBUF_Struct + *! \brief Input Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ +typedef struct _ADI_CRYPT_INBUF_t { + union { + struct { + unsigned int VALUE : 32; /**< Input Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_INBUF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_INBUF_t__ */ + +/*@}*/ + +/** @defgroup OUTBUF Output Buffer (OUTBUF) Register + * Output Buffer (OUTBUF) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_OUTBUF_Struct + *! \brief Output Buffer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ +typedef struct _ADI_CRYPT_OUTBUF_t { + union { + struct { + unsigned int VALUE : 32; /**< Output Buffer */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_OUTBUF_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_OUTBUF_t__ */ + +/*@}*/ + +/** @defgroup NONCE0 Nonce Bits [31:0] (NONCE0) Register + * Nonce Bits [31:0] (NONCE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE0_Struct + *! \brief Nonce Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ +typedef struct _ADI_CRYPT_NONCE0_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 0: Nonce Bits [31:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE0_t__ */ + +/*@}*/ + +/** @defgroup NONCE1 Nonce Bits [63:32] (NONCE1) Register + * Nonce Bits [63:32] (NONCE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE1_Struct + *! \brief Nonce Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ +typedef struct _ADI_CRYPT_NONCE1_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 1: Nonce Bits [63:32] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE1_t__ */ + +/*@}*/ + +/** @defgroup NONCE2 Nonce Bits [95:64] (NONCE2) Register + * Nonce Bits [95:64] (NONCE2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE2_Struct + *! \brief Nonce Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ +typedef struct _ADI_CRYPT_NONCE2_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 2: Nonce Bits [95:64] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE2_t__ */ + +/*@}*/ + +/** @defgroup NONCE3 Nonce Bits [127:96] (NONCE3) Register + * Nonce Bits [127:96] (NONCE3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_NONCE3_Struct + *! \brief Nonce Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ +typedef struct _ADI_CRYPT_NONCE3_t { + union { + struct { + unsigned int VALUE : 32; /**< Word 3: Nonce Bits [127:96] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_NONCE3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_NONCE3_t__ */ + +/*@}*/ + +/** @defgroup AESKEY0 AES Key Bits [31:0] (AESKEY0) Register + * AES Key Bits [31:0] (AESKEY0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY0_Struct + *! \brief AES Key Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ +typedef struct _ADI_CRYPT_AESKEY0_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [3:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY0_t__ */ + +/*@}*/ + +/** @defgroup AESKEY1 AES Key Bits [63:32] (AESKEY1) Register + * AES Key Bits [63:32] (AESKEY1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY1_Struct + *! \brief AES Key Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ +typedef struct _ADI_CRYPT_AESKEY1_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [7:4] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY1_t__ */ + +/*@}*/ + +/** @defgroup AESKEY2 AES Key Bits [95:64] (AESKEY2) Register + * AES Key Bits [95:64] (AESKEY2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY2_Struct + *! \brief AES Key Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ +typedef struct _ADI_CRYPT_AESKEY2_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [11:8] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY2_t__ */ + +/*@}*/ + +/** @defgroup AESKEY3 AES Key Bits [127:96] (AESKEY3) Register + * AES Key Bits [127:96] (AESKEY3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY3_Struct + *! \brief AES Key Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ +typedef struct _ADI_CRYPT_AESKEY3_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [15:12] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY3_t__ */ + +/*@}*/ + +/** @defgroup AESKEY4 AES Key Bits [159:128] (AESKEY4) Register + * AES Key Bits [159:128] (AESKEY4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY4_Struct + *! \brief AES Key Bits [159:128] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ +typedef struct _ADI_CRYPT_AESKEY4_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [19:16] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY4_t__ */ + +/*@}*/ + +/** @defgroup AESKEY5 AES Key Bits [191:160] (AESKEY5) Register + * AES Key Bits [191:160] (AESKEY5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY5_Struct + *! \brief AES Key Bits [191:160] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ +typedef struct _ADI_CRYPT_AESKEY5_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [23:20] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY5_t__ */ + +/*@}*/ + +/** @defgroup AESKEY6 AES Key Bits [223:192] (AESKEY6) Register + * AES Key Bits [223:192] (AESKEY6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY6_Struct + *! \brief AES Key Bits [223:192] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ +typedef struct _ADI_CRYPT_AESKEY6_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [27:24] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY6_t__ */ + +/*@}*/ + +/** @defgroup AESKEY7 AES Key Bits [255:224] (AESKEY7) Register + * AES Key Bits [255:224] (AESKEY7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_AESKEY7_Struct + *! \brief AES Key Bits [255:224] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ +typedef struct _ADI_CRYPT_AESKEY7_t { + union { + struct { + unsigned int VALUE : 32; /**< Key: Bytes [31:28] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_AESKEY7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_AESKEY7_t__ */ + +/*@}*/ + +/** @defgroup CNTRINIT Counter Initialization Vector (CNTRINIT) Register + * Counter Initialization Vector (CNTRINIT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_CNTRINIT_Struct + *! \brief Counter Initialization Vector Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ +typedef struct _ADI_CRYPT_CNTRINIT_t { + union { + struct { + unsigned int VALUE : 20; /**< Counter Initialization Value */ + unsigned int reserved20 : 12; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CNTRINIT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CNTRINIT_t__ */ + +/*@}*/ + +/** @defgroup SHAH0 SHA Bits [31:0] (SHAH0) Register + * SHA Bits [31:0] (SHAH0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH0_Struct + *! \brief SHA Bits [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ +typedef struct _ADI_CRYPT_SHAH0_t { + union { + struct { + unsigned int SHAHASH0 : 32; /**< Word 0: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH0_t__ */ + +/*@}*/ + +/** @defgroup SHAH1 SHA Bits [63:32] (SHAH1) Register + * SHA Bits [63:32] (SHAH1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH1_Struct + *! \brief SHA Bits [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ +typedef struct _ADI_CRYPT_SHAH1_t { + union { + struct { + unsigned int SHAHASH1 : 32; /**< Word 1: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH1_t__ */ + +/*@}*/ + +/** @defgroup SHAH2 SHA Bits [95:64] (SHAH2) Register + * SHA Bits [95:64] (SHAH2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH2_Struct + *! \brief SHA Bits [95:64] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ +typedef struct _ADI_CRYPT_SHAH2_t { + union { + struct { + unsigned int SHAHASH2 : 32; /**< Word 2: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH2_t__ */ + +/*@}*/ + +/** @defgroup SHAH3 SHA Bits [127:96] (SHAH3) Register + * SHA Bits [127:96] (SHAH3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH3_Struct + *! \brief SHA Bits [127:96] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ +typedef struct _ADI_CRYPT_SHAH3_t { + union { + struct { + unsigned int SHAHASH3 : 32; /**< Word 3: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH3_t__ */ + +/*@}*/ + +/** @defgroup SHAH4 SHA Bits [159:128] (SHAH4) Register + * SHA Bits [159:128] (SHAH4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH4_Struct + *! \brief SHA Bits [159:128] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ +typedef struct _ADI_CRYPT_SHAH4_t { + union { + struct { + unsigned int SHAHASH4 : 32; /**< Word 4: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH4_t__ */ + +/*@}*/ + +/** @defgroup SHAH5 SHA Bits [191:160] (SHAH5) Register + * SHA Bits [191:160] (SHAH5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH5_Struct + *! \brief SHA Bits [191:160] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ +typedef struct _ADI_CRYPT_SHAH5_t { + union { + struct { + unsigned int SHAHASH5 : 32; /**< Word 5: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH5_t__ */ + +/*@}*/ + +/** @defgroup SHAH6 SHA Bits [223:192] (SHAH6) Register + * SHA Bits [223:192] (SHAH6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH6_Struct + *! \brief SHA Bits [223:192] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ +typedef struct _ADI_CRYPT_SHAH6_t { + union { + struct { + unsigned int SHAHASH6 : 32; /**< Word 6: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH6_t__ */ + +/*@}*/ + +/** @defgroup SHAH7 SHA Bits [255:224] (SHAH7) Register + * SHA Bits [255:224] (SHAH7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHAH7_Struct + *! \brief SHA Bits [255:224] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ +typedef struct _ADI_CRYPT_SHAH7_t { + union { + struct { + unsigned int SHAHASH7 : 32; /**< Word 7: SHA Hash */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHAH7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHAH7_t__ */ + +/*@}*/ + +/** @defgroup SHA_LAST_WORD SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register + * SHA Last Word and Valid Bits Information (SHA_LAST_WORD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_SHA_LAST_WORD_Struct + *! \brief SHA Last Word and Valid Bits Information Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ +typedef struct _ADI_CRYPT_SHA_LAST_WORD_t { + union { + struct { + unsigned int O_Last_Word : 1; /**< Last SHA Input Word */ + unsigned int O_Bits_Valid : 5; /**< Bits Valid in SHA Last Word Input */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_SHA_LAST_WORD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_SHA_LAST_WORD_t__ */ + +/*@}*/ + +/** @defgroup CCM_NUM_VALID_BYTES NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register + * NUM_VALID_BYTES (CCM_NUM_VALID_BYTES) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_CCM_NUM_VALID_BYTES_Struct + *! \brief NUM_VALID_BYTES Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ +typedef struct _ADI_CRYPT_CCM_NUM_VALID_BYTES_t { + union { + struct { + unsigned int NUM_VALID_BYTES : 4; /**< Number of Valid Bytes in CCM Last Data */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_CCM_NUM_VALID_BYTES_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_CCM_NUM_VALID_BYTES_t__ */ + +/*@}*/ + +/** @defgroup PRKSTORCFG PRKSTOR Configuration (PRKSTORCFG) Register + * PRKSTOR Configuration (PRKSTORCFG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_PRKSTORCFG_Struct + *! \brief PRKSTOR Configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_PRKSTORCFG_t__ +typedef struct _ADI_CRYPT_PRKSTORCFG_t { + union { + struct { + unsigned int KEY_INDEX : 7; /**< Index of Key in PRKSTOR */ + unsigned int CMD : 4; /**< Command Input for PRKSTOR */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_PRKSTORCFG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_PRKSTORCFG_t__ */ + +/*@}*/ + +/** @defgroup KUW0 Key Wrap Unwrap Register 0 (KUW0) Register + * Key Wrap Unwrap Register 0 (KUW0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW0_Struct + *! \brief Key Wrap Unwrap Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW0_t__ +typedef struct _ADI_CRYPT_KUW0_t { + union { + struct { + unsigned int KUW0 : 32; /**< KUW [31:0] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW0_t__ */ + +/*@}*/ + +/** @defgroup KUW1 Key Wrap Unwrap Register 1 (KUW1) Register + * Key Wrap Unwrap Register 1 (KUW1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW1_Struct + *! \brief Key Wrap Unwrap Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW1_t__ +typedef struct _ADI_CRYPT_KUW1_t { + union { + struct { + unsigned int KUW1 : 32; /**< KUW [63:32] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW1_t__ */ + +/*@}*/ + +/** @defgroup KUW2 Key Wrap Unwrap Register 2 (KUW2) Register + * Key Wrap Unwrap Register 2 (KUW2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW2_Struct + *! \brief Key Wrap Unwrap Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW2_t__ +typedef struct _ADI_CRYPT_KUW2_t { + union { + struct { + unsigned int KUW2 : 32; /**< KUW [95:64] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW2_t__ */ + +/*@}*/ + +/** @defgroup KUW3 Key Wrap Unwrap Register 3 (KUW3) Register + * Key Wrap Unwrap Register 3 (KUW3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW3_Struct + *! \brief Key Wrap Unwrap Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW3_t__ +typedef struct _ADI_CRYPT_KUW3_t { + union { + struct { + unsigned int KUW3 : 32; /**< KUW [127:96] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW3_t__ */ + +/*@}*/ + +/** @defgroup KUW4 Key Wrap Unwrap Register 4 (KUW4) Register + * Key Wrap Unwrap Register 4 (KUW4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW4_Struct + *! \brief Key Wrap Unwrap Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW4_t__ +typedef struct _ADI_CRYPT_KUW4_t { + union { + struct { + unsigned int KUW4 : 32; /**< KUW [159:128] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW4_t__ */ + +/*@}*/ + +/** @defgroup KUW5 Key Wrap Unwrap Register 5 (KUW5) Register + * Key Wrap Unwrap Register 5 (KUW5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW5_Struct + *! \brief Key Wrap Unwrap Register 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW5_t__ +typedef struct _ADI_CRYPT_KUW5_t { + union { + struct { + unsigned int KUW5 : 32; /**< KUW [191:160] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW5_t__ */ + +/*@}*/ + +/** @defgroup KUW6 Key Wrap Unwrap Register 6 (KUW6) Register + * Key Wrap Unwrap Register 6 (KUW6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW6_Struct + *! \brief Key Wrap Unwrap Register 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW6_t__ +typedef struct _ADI_CRYPT_KUW6_t { + union { + struct { + unsigned int KUW6 : 32; /**< KUW [223:192] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW6_t__ */ + +/*@}*/ + +/** @defgroup KUW7 Key Wrap Unwrap Register 7 (KUW7) Register + * Key Wrap Unwrap Register 7 (KUW7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW7_Struct + *! \brief Key Wrap Unwrap Register 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW7_t__ +typedef struct _ADI_CRYPT_KUW7_t { + union { + struct { + unsigned int KUW7 : 32; /**< KUW [255:224] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW7_t__ */ + +/*@}*/ + +/** @defgroup KUW8 Key Wrap Unwrap Register 8 (KUW8) Register + * Key Wrap Unwrap Register 8 (KUW8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW8_Struct + *! \brief Key Wrap Unwrap Register 8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW8_t__ +typedef struct _ADI_CRYPT_KUW8_t { + union { + struct { + unsigned int KUW8 : 32; /**< KUW [287:256] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW8_t__ */ + +/*@}*/ + +/** @defgroup KUW9 Key Wrap Unwrap Register 9 (KUW9) Register + * Key Wrap Unwrap Register 9 (KUW9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW9_Struct + *! \brief Key Wrap Unwrap Register 9 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW9_t__ +typedef struct _ADI_CRYPT_KUW9_t { + union { + struct { + unsigned int KUW9 : 32; /**< KUW [319:288] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW9_t__ */ + +/*@}*/ + +/** @defgroup KUW10 Key Wrap Unwrap Register 10 (KUW10) Register + * Key Wrap Unwrap Register 10 (KUW10) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW10_Struct + *! \brief Key Wrap Unwrap Register 10 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW10_t__ +typedef struct _ADI_CRYPT_KUW10_t { + union { + struct { + unsigned int KUW10 : 32; /**< KUW [351:320] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW10_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW10_t__ */ + +/*@}*/ + +/** @defgroup KUW11 Key Wrap Unwrap Register 11 (KUW11) Register + * Key Wrap Unwrap Register 11 (KUW11) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW11_Struct + *! \brief Key Wrap Unwrap Register 11 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW11_t__ +typedef struct _ADI_CRYPT_KUW11_t { + union { + struct { + unsigned int KUW11 : 32; /**< KUW [383:352] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW11_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW11_t__ */ + +/*@}*/ + +/** @defgroup KUW12 Key Wrap Unwrap Register 12 (KUW12) Register + * Key Wrap Unwrap Register 12 (KUW12) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW12_Struct + *! \brief Key Wrap Unwrap Register 12 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW12_t__ +typedef struct _ADI_CRYPT_KUW12_t { + union { + struct { + unsigned int KUW12 : 32; /**< KUW [415:384] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW12_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW12_t__ */ + +/*@}*/ + +/** @defgroup KUW13 Key Wrap Unwrap Register 13 (KUW13) Register + * Key Wrap Unwrap Register 13 (KUW13) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW13_Struct + *! \brief Key Wrap Unwrap Register 13 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW13_t__ +typedef struct _ADI_CRYPT_KUW13_t { + union { + struct { + unsigned int KUW13 : 32; /**< KUW [447:416] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW13_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW13_t__ */ + +/*@}*/ + +/** @defgroup KUW14 Key Wrap Unwrap Register 14 (KUW14) Register + * Key Wrap Unwrap Register 14 (KUW14) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW14_Struct + *! \brief Key Wrap Unwrap Register 14 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW14_t__ +typedef struct _ADI_CRYPT_KUW14_t { + union { + struct { + unsigned int KUW14 : 32; /**< KUW [479:448] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW14_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW14_t__ */ + +/*@}*/ + +/** @defgroup KUW15 Key Wrap Unwrap Register 15 (KUW15) Register + * Key Wrap Unwrap Register 15 (KUW15) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUW15_Struct + *! \brief Key Wrap Unwrap Register 15 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW15_t__ +typedef struct _ADI_CRYPT_KUW15_t { + union { + struct { + unsigned int KUW15 : 32; /**< KUW [511:480] */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUW15_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUW15_t__ */ + +/*@}*/ + +/** @defgroup KUWValStr1 Key Wrap Unwrap Validation String [63:32] (KUWValStr1) Register + * Key Wrap Unwrap Validation String [63:32] (KUWValStr1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUWValStr1_Struct + *! \brief Key Wrap Unwrap Validation String [63:32] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr1_t__ +typedef struct _ADI_CRYPT_KUWValStr1_t { + union { + struct { + unsigned int InitalValue0 : 32; /**< Initial Value */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUWValStr1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr1_t__ */ + +/*@}*/ + +/** @defgroup KUWValStr2 Key Wrap Unwrap Validation String [31:0] (KUWValStr2) Register + * Key Wrap Unwrap Validation String [31:0] (KUWValStr2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CRYPT_KUWValStr2_Struct + *! \brief Key Wrap Unwrap Validation String [31:0] Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr2_t__ +typedef struct _ADI_CRYPT_KUWValStr2_t { + union { + struct { + unsigned int InitialValue1 : 32; /**< Initial Value */ + }; + uint32_t VALUE32; + }; +} ADI_CRYPT_KUWValStr2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CRYPT_KUWValStr2_t__ */ + +/*@}*/ + +/** @defgroup IEN Power Supply Monitor Interrupt Enable (IEN) Register + * Power Supply Monitor Interrupt Enable (IEN) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_IEN_RANGEBAT + *! \brief Battery Monitor Range (RANGEBAT) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_IEN_REGION1 = 0, /**< Configure to generate interrupt if VBAT in Region1 */ + PMG_IEN_REGION2 = 1, /**< Configure to generate interrupt if VBAT in Region2 */ + PMG_IEN_REGION3 = 2, /**< Configure to generate interrupt if VBAT in Region3 */ + PMG_IEN_NA = 3 /**< NA */ +} ADI_PMG_IEN_RANGEBAT; + + +/* ========================================================================== + *! \struct ADI_PMG_IEN_Struct + *! \brief Power Supply Monitor Interrupt Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ +typedef struct _ADI_PMG_IEN_t { + union { + struct { + unsigned int VBAT : 1; /**< Enable Interrupt for VBAT */ + unsigned int VREGUNDR : 1; /**< Enable Interrupt when VREG under-voltage (below 1 V) */ + unsigned int VREGOVR : 1; /**< Enable Interrupt when VREG over-voltage (above 1.32 V) */ + unsigned int reserved3 : 5; + unsigned int RANGEBAT : 2; /**< Battery Monitor Range */ + unsigned int IENBAT : 1; /**< Interrupt enable for VBAT range */ + unsigned int reserved11 : 21; + }; + uint32_t VALUE32; + }; +} ADI_PMG_IEN_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_IEN_t__ */ + +/*@}*/ + +/** @defgroup PSM_STAT Power Supply Monitor Status (PSM_STAT) Register + * Power Supply Monitor Status (PSM_STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_PSM_STAT_RORANGE1 + *! \brief VBAT range1 (RORANGE1) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PSM_STAT_BATSTAT1 = 0, /**< VBAT NOT in the range specified */ + PMG_PSM_STAT_BATSTAT0 = 1 /**< VBAT in the range specified */ +} ADI_PMG_PSM_STAT_RORANGE1; + + +/* ========================================================================== + *! \struct ADI_PMG_PSM_STAT_Struct + *! \brief Power Supply Monitor Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ +typedef struct _ADI_PMG_PSM_STAT_t { + union { + struct { + unsigned int VBATUNDR : 1; /**< Status bit indicating an Alarm that battery is below 1.8 V */ + unsigned int VREGUNDR : 1; /**< Status bit for Alarm indicating VREG is below 1 V */ + unsigned int VREGOVR : 1; /**< Status bit for alarm indicating Over Voltage for VREG */ + unsigned int reserved3 : 4; + unsigned int WICENACK : 1; /**< WIC Enable Acknowledge from Cortex */ + unsigned int RANGE1 : 1; /**< VBAT range1 */ + unsigned int RANGE2 : 1; /**< VBAT range2 */ + unsigned int RANGE3 : 1; /**< VBAT range3 */ + unsigned int reserved11 : 2; + unsigned int RORANGE1 : 1; /**< VBAT range1 */ + unsigned int RORANGE2 : 1; /**< VBAT range2 */ + unsigned int RORANGE3 : 1; /**< VBAT range3 */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PSM_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PSM_STAT_t__ */ + +/*@}*/ + +/** @defgroup PWRMOD Power Mode Register (PWRMOD) Register + * Power Mode Register (PWRMOD) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_PWRMOD_MODE + *! \brief Power Mode Bits (MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_PWRMOD_FLEXI = 0, /**< Flexi Mode */ + PMG_PWRMOD_HIBERNATE = 2, /**< Hibernate Mode */ + PMG_PWRMOD_SHUTDOWN = 3 /**< Shutdown Mode */ +} ADI_PMG_PWRMOD_MODE; + + +/* ========================================================================== + *! \struct ADI_PMG_PWRMOD_Struct + *! \brief Power Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ +typedef struct _ADI_PMG_PWRMOD_t { + union { + struct { + unsigned int MODE : 2; /**< Power Mode Bits */ + unsigned int reserved2 : 1; + unsigned int MONVBATN : 1; /**< Monitor VBAT during Hibernate Mode. Monitors VBAT by default */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PWRMOD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRMOD_t__ */ + +/*@}*/ + +/** @defgroup PWRKEY Key Protection for PWRMOD and SRAMRET (PWRKEY) Register + * Key Protection for PWRMOD and SRAMRET (PWRKEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_PWRKEY_Struct + *! \brief Key Protection for PWRMOD and SRAMRET Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ +typedef struct _ADI_PMG_PWRKEY_t { + union { + struct { + unsigned int VALUE : 16; /**< Power Control Key */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_PMG_PWRKEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_PWRKEY_t__ */ + +/*@}*/ + +/** @defgroup SHDN_STAT Shutdown Status Register (SHDN_STAT) Register + * Shutdown Status Register (SHDN_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_SHDN_STAT_Struct + *! \brief Shutdown Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ +typedef struct _ADI_PMG_SHDN_STAT_t { + union { + struct { + unsigned int EXTINT0 : 1; /**< Interrupt from External Interrupt 0 */ + unsigned int EXTINT1 : 1; /**< Interrupt from External Interrupt 1 */ + unsigned int EXTINT2 : 1; /**< Interrupt from External Interrupt 2 */ + unsigned int RTC : 1; /**< Interrupt from RTC */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_PMG_SHDN_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SHDN_STAT_t__ */ + +/*@}*/ + +/** @defgroup SRAMRET Control for Retention SRAM in Hibernate Mode (SRAMRET) Register + * Control for Retention SRAM in Hibernate Mode (SRAMRET) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_SRAMRET_Struct + *! \brief Control for Retention SRAM in Hibernate Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ +typedef struct _ADI_PMG_SRAMRET_t { + union { + struct { + unsigned int RET1 : 1; /**< Enable retention bank 1 (12 KB) */ + unsigned int RET2 : 1; /**< Enable retention bank 3 and bank 4 (32 KB) */ + unsigned int reserved2 : 6; + unsigned int RET3 : 1; /**< Enable retention bank 5 (32 KB) */ + unsigned int RET4 : 1; /**< Enable retention bank 6 and bank 7 (32 KB) */ + unsigned int reserved10 : 13; + unsigned int HIBERNATE_SRAM_LOAD_MODE : 1; /**< Hibernate mode SRAM load mode control */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_PMG_SRAMRET_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_SRAMRET_t__ */ + +/*@}*/ + +/** @defgroup TRIM Trimming Bits (TRIM) Register + * Trimming Bits (TRIM) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_TRIM_hibernate_load_mode + *! \brief Hibernate mode load mode control (hibernate_load_mode) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TRIM_HIGH_LOAD = 0, /**< High hibernate load */ + PMG_TRIM_LOW_LOAD = 7 /**< Low hibernate load */ +} ADI_PMG_TRIM_hibernate_load_mode; + + +/* ========================================================================== + *! \struct ADI_PMG_TRIM_Struct + *! \brief Trimming Bits Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TRIM_t__ +typedef struct _ADI_PMG_TRIM_t { + union { + struct { + unsigned int reserved0 : 29; + unsigned int hibernate_load_mode : 3; /**< Hibernate mode load mode control */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TRIM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TRIM_t__ */ + +/*@}*/ + +/** @defgroup RST_STAT Reset Status (RST_STAT) Register + * Reset Status (RST_STAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_RST_STAT_PORSRC + *! \brief Power on reset Source (PORSRC) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_RST_STAT_FAILSAFE_HV = 0, /**< POR triggered because VBAT drops below Fail Safe */ + PMG_RST_STAT_RST_VBAT = 1, /**< POR trigger because VBAT supply (VBAT < 1.7 V) */ + PMG_RST_STAT_RST_VREG = 2, /**< POR triggered because VDD supply (VDD < 1.08 V) */ + PMG_RST_STAT_FAILSAFE_LV = 3 /**< POR triggered because VREG drops below Fail Safe */ +} ADI_PMG_RST_STAT_PORSRC; + + +/* ========================================================================== + *! \struct ADI_PMG_RST_STAT_Struct + *! \brief Reset Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ +typedef struct _ADI_PMG_RST_STAT_t { + union { + struct { + unsigned int POR : 1; /**< Power-on reset */ + unsigned int EXTRST : 1; /**< External reset */ + unsigned int WDRST : 1; /**< Watchdog timeout */ + unsigned int SWRST : 1; /**< Software reset */ + unsigned int PORSRC : 2; /**< Power on reset Source */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_PMG_RST_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_RST_STAT_t__ */ + +/*@}*/ + +/** @defgroup CTL1 HPBUCK Control (CTL1) Register + * HPBUCK Control (CTL1) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_CTL1_HPBUCK_LD_MODE + *! \brief HP Buck load mode (HPBUCK_LD_MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_CTL1_HPBUCKLOWLOAD = 0, /**< HPBUCK Low load mode is enabled */ + PMG_CTL1_HPBUCKHIGHLOAD = 1 /**< HPBUCK High load mode is enabled */ +} ADI_PMG_CTL1_HPBUCK_LD_MODE; + + +/* ========================================================================= + *! \enum ADI_PMG_CTL1_HPBUCK_LOWPWR_MODE + *! \brief HP Buck low power mode (HPBUCK_LOWPWR_MODE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_CTL1_LOWPWRDISABLE = 0, /**< HPBUCK Low power mode is disabled */ + PMG_CTL1_LOWPWRENABLE = 1 /**< HPBUCK Low power mode is enabled */ +} ADI_PMG_CTL1_HPBUCK_LOWPWR_MODE; + + +/* ========================================================================== + *! \struct ADI_PMG_CTL1_Struct + *! \brief HPBUCK Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ +typedef struct _ADI_PMG_CTL1_t { + union { + struct { + unsigned int HPBUCKEN : 1; /**< Enable HP Buck */ + unsigned int HPBUCK_LD_MODE : 1; /**< HP Buck load mode */ + unsigned int HPBUCK_LOWPWR_MODE : 1; /**< HP Buck low power mode */ + unsigned int reserved3 : 29; + }; + uint32_t VALUE32; + }; +} ADI_PMG_CTL1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_CTL1_t__ */ + +/*@}*/ + +/** @defgroup CFG0 External Interrupt configuration (CFG0) Register + * External Interrupt configuration (CFG0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_CFG0_Struct + *! \brief External Interrupt configuration Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ +typedef struct _ADI_XINT_CFG0_t { + union { + struct { + unsigned int IRQ0MDE : 3; /**< External Interrupt 0 Mode registers */ + unsigned int IRQ0EN : 1; /**< External Interrupt 0 Enable bit */ + unsigned int IRQ1MDE : 3; /**< External Interrupt 1 Mode registers */ + unsigned int IRQ1EN : 1; /**< External Interrupt 1 Enable bit */ + unsigned int IRQ2MDE : 3; /**< External Interrupt 2 Mode registers */ + unsigned int IRQ2EN : 1; /**< External Interrupt 2 Enable bit */ + unsigned int IRQ3MDE : 3; /**< External Interrupt 3 Mode registers */ + unsigned int IRQ3EN : 1; /**< External Interrupt 3 enable bit */ + unsigned int reserved16 : 4; + unsigned int UART_RX_EN : 1; /**< External Interrupt using SIP_UPDATE enable bit */ + unsigned int UART_RX_MDE : 3; /**< External Interrupt using UART_RX wakeup Mode registers */ + unsigned int reserved24 : 8; + }; + uint32_t VALUE32; + }; +} ADI_XINT_CFG0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CFG0_t__ */ + +/*@}*/ + +/** @defgroup EXT_STAT External Wakeup Interrupt Status register (EXT_STAT) Register + * External Wakeup Interrupt Status register (EXT_STAT) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_EXT_STAT_Struct + *! \brief External Wakeup Interrupt Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ +typedef struct _ADI_XINT_EXT_STAT_t { + union { + struct { + unsigned int STAT_EXTINT0 : 1; /**< Interrupt status bit for External Interrupt 0 */ + unsigned int STAT_EXTINT1 : 1; /**< Interrupt status bit for External Interrupt 1 */ + unsigned int STAT_EXTINT2 : 1; /**< Interrupt status bit for External Interrupt 2 */ + unsigned int STAT_EXTINT3 : 1; /**< Interrupt status bit for External Interrupt 3 */ + unsigned int reserved4 : 1; + unsigned int STAT_UART_RXWKUP : 1; /**< Interrupt status bit for UART RX WAKEUP interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_XINT_EXT_STAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_EXT_STAT_t__ */ + +/*@}*/ + +/** @defgroup CLR External Interrupt clear (CLR) Register + * External Interrupt clear (CLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_CLR_Struct + *! \brief External Interrupt clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ +typedef struct _ADI_XINT_CLR_t { + union { + struct { + unsigned int IRQ0 : 1; /**< External interrupt 0 */ + unsigned int IRQ1 : 1; /**< External interrupt 1 */ + unsigned int IRQ2 : 1; /**< External interrupt 2 */ + unsigned int IRQ3 : 1; /**< External interrupt 3 */ + unsigned int reserved4 : 1; + unsigned int UART_RX_CLR : 1; /**< External interrupt Clear for UART_RX WAKEUP interrupt */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_XINT_CLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_CLR_t__ */ + +/*@}*/ + +/** @defgroup NMICLR Non-maskable interrupt clear (NMICLR) Register + * Non-maskable interrupt clear (NMICLR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_XINT_NMICLR_Struct + *! \brief Non-maskable interrupt clear Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ +typedef struct _ADI_XINT_NMICLR_t { + union { + struct { + unsigned int CLR : 1; /**< NMI clear */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_XINT_NMICLR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_XINT_NMICLR_t__ */ + +/*@}*/ + +/** @defgroup KEY Key Protection for OSCCTRL (KEY) Register + * Key Protection for OSCCTRL (KEY) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_OSC_KEY_Struct + *! \brief Key Protection for OSCCTRL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ +typedef struct _ADI_CLKG_OSC_KEY_t { + union { + struct { + unsigned int VALUE : 16; /**< Oscillator key */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_OSC_KEY_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_KEY_t__ */ + +/*@}*/ + +/** @defgroup CTL Oscillator Control (CTL) Register + * Oscillator Control (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_OSC_CTL_Struct + *! \brief Oscillator Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ +typedef struct _ADI_CLKG_OSC_CTL_t { + union { + struct { + unsigned int LFCLK_MUX : 1; /**< 32 kHz clock select mux */ + unsigned int HFOSC_EN : 1; /**< High frequency internal oscillator enable */ + unsigned int LFX_EN : 1; /**< Low frequency crystal oscillator enable */ + unsigned int HFX_EN : 1; /**< High frequency crystal oscillator enable */ + unsigned int LFX_BYP : 1; /**< Low frequency crystal oscillator Bypass */ + unsigned int LFX_MON_EN : 1; /**< LFXTAL clock monitor and Clock FAIL interrupt enable */ + unsigned int reserved6 : 2; + unsigned int LFOSC_OK : 1; /**< Status of LFOSC oscillator */ + unsigned int HFOSC_OK : 1; /**< Status of HFOSC oscillator */ + unsigned int LFX_OK : 1; /**< Status of LFXTAL oscillator */ + unsigned int HFX_OK : 1; /**< Status of HFXTAL oscillator */ + unsigned int LFX_AUTSW_EN : 1; /**< Enables automatic Switching of the LF Mux to LFOSC on LFXTAL Failure */ + unsigned int LFX_AUTSW_STA : 1; /**< Status of automatic switching of the LF Mux to LFOSC upon detection of LFXTAL failure */ + unsigned int LFX_ROBUST_EN : 1; /**< LFXTAL Mode select */ + unsigned int LFX_ROBUST_LD : 2; /**< LFXTAL Robust Mode Load select */ + unsigned int reserved17 : 3; + unsigned int ROOT_MON_EN : 1; /**< ROOT clock monitor and Clock FAIL interrupt enable */ + unsigned int ROOT_AUTSW_EN : 1; /**< Enables automatic Switching of the Root clock to HFOSC on Root clock Failure */ + unsigned int ROOT_AUTSW_STA : 1; /**< Status of automatic switching of the Root clock to HFOSC upon detection of Root clock failure */ + unsigned int reserved23 : 7; + unsigned int ROOT_FAIL_STA : 1; /**< Root clock (crystal clock) Not Stable */ + unsigned int LFX_FAIL_STA : 1; /**< LF XTAL (crystal clock) Not Stable */ + }; + uint32_t VALUE32; + }; +} ADI_CLKG_OSC_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_OSC_CTL_t__ */ + +/*@}*/ + +/** @defgroup SRAM_CTL Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register + * Control for SRAM Parity and Instruction SRAM (SRAM_CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SRAM_CTL_Struct + *! \brief Control for SRAM Parity and Instruction SRAM Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ +typedef struct _ADI_PMG_TST_SRAM_CTL_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int BNK1EN : 1; /**< Enable initialization */ + unsigned int BNK2EN : 1; /**< Enable initialization */ + unsigned int reserved3 : 4; + unsigned int BNK7EN : 1; /**< Enable initialization */ + unsigned int reserved8 : 5; + unsigned int STARTINIT : 1; /**< Write one to trigger initialization. Self-cleared */ + unsigned int AUTOINIT : 1; /**< Automatic initialization on wake up from hibernate mode */ + unsigned int ABTINIT : 1; /**< Abort current initialization. Self-cleared */ + unsigned int PENBNK0 : 1; /**< Enable parity check */ + unsigned int PENBNK1 : 1; /**< Enable parity check */ + unsigned int PENBNK2 : 1; /**< Enable parity check */ + unsigned int PENBNK3 : 1; /**< Enable parity check */ + unsigned int PENBNK4 : 1; /**< Enable parity check */ + unsigned int PENBNK5 : 1; /**< Enable parity check */ + unsigned int PENBNK6 : 1; /**< Enable parity check */ + unsigned int PENBNK7 : 1; /**< Enable parity check */ + unsigned int reserved24 : 7; + unsigned int INSTREN : 1; /**< Enables 32 KB instruction SRAM */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SRAM_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_CTL_t__ */ + +/*@}*/ + +/** @defgroup SRAM_INITSTAT Initialization Status Register (SRAM_INITSTAT) Register + * Initialization Status Register (SRAM_INITSTAT) Register. + * @{ + */ + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK0DONE + *! \brief Bank 0 initialization status (BNK0DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK0_INIT = 0, /**< Bank 0 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK0_INIT = 1 /**< Bank 0 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK0DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK1DONE + *! \brief Bank 1 initialization status (BNK1DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK1_INIT = 0, /**< Bank 1 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK1_INIT = 1 /**< Bank 1 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK1DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK2DONE + *! \brief Bank 2 initialization status (BNK2DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK2_INIT = 0, /**< Bank 2 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK2_INIT = 1 /**< Bank 2 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK2DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK3DONE + *! \brief Bank 3 initialization status (BNK3DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK3_INIT = 0, /**< Bank 3 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK3_INIT = 1 /**< Bank 3 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK3DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK4DONE + *! \brief Bank 4 initialization status (BNK4DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK4_INIT = 0, /**< Bank 4 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK4_INIT = 1 /**< Bank 4 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK4DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK5DONE + *! \brief Bank 5 initialization status (BNK5DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK5_INIT = 0, /**< Bank 5 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK5_INIT = 1 /**< Bank 5 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK5DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK6DONE + *! \brief Bank 6 initialization status (BNK6DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK6_INIT = 0, /**< Bank 6 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK6_INIT = 1 /**< Bank 6 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK6DONE; + + +/* ========================================================================= + *! \enum ADI_PMG_TST_SRAM_INITSTAT_BNK7DONE + *! \brief Bank 7 initialization status (BNK7DONE) Enumerations + * ========================================================================= */ +typedef enum +{ + PMG_TST_SRAM_INITSTAT_NO_BANK7_INIT = 0, /**< Bank 7 not initialized */ + PMG_TST_SRAM_INITSTAT_BANK7_INIT = 1 /**< Bank 7 initialized */ +} ADI_PMG_TST_SRAM_INITSTAT_BNK7DONE; + + +/* ========================================================================== + *! \struct ADI_PMG_TST_SRAM_INITSTAT_Struct + *! \brief Initialization Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ +typedef struct _ADI_PMG_TST_SRAM_INITSTAT_t { + union { + struct { + unsigned int BNK0DONE : 1; /**< Bank 0 initialization status */ + unsigned int BNK1DONE : 1; /**< Bank 1 initialization status */ + unsigned int BNK2DONE : 1; /**< Bank 2 initialization status */ + unsigned int BNK3DONE : 1; /**< Bank 3 initialization status */ + unsigned int BNK4DONE : 1; /**< Bank 4 initialization status */ + unsigned int BNK5DONE : 1; /**< Bank 5 initialization status */ + unsigned int BNK6DONE : 1; /**< Bank 6 initialization status */ + unsigned int BNK7DONE : 1; /**< Bank 7 initialization status */ + unsigned int reserved8 : 24; + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SRAM_INITSTAT_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SRAM_INITSTAT_t__ */ + +/*@}*/ + +/** @defgroup CLR_LATCH_GPIOS Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register + * Clear GPIO After Shutdown Mode (CLR_LATCH_GPIOS) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_CLR_LATCH_GPIOS_Struct + *! \brief Clear GPIO After Shutdown Mode Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ +typedef struct _ADI_PMG_TST_CLR_LATCH_GPIOS_t { + union { + struct { + unsigned int VALUE : 16; /**< Writing 0x58FA creates a pulse to clear the latches for the GPIOs */ + }; + uint16_t VALUE16; + }; +} ADI_PMG_TST_CLR_LATCH_GPIOS_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_CLR_LATCH_GPIOS_t__ */ + +/*@}*/ + +/** @defgroup SCRPAD_IMG Scratch Pad Image (SCRPAD_IMG) Register + * Scratch Pad Image (SCRPAD_IMG) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SCRPAD_IMG_Struct + *! \brief Scratch Pad Image Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ +typedef struct _ADI_PMG_TST_SCRPAD_IMG_t { + union { + struct { + unsigned int DATA : 32; /**< Value written to this register is saved in 3 V when going to shutdown */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SCRPAD_IMG_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_IMG_t__ */ + +/*@}*/ + +/** @defgroup SCRPAD_3V_RD Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register + * Scratch Pad Saved in Battery Domain (SCRPAD_3V_RD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_SCRPAD_3V_RD_Struct + *! \brief Scratch Pad Saved in Battery Domain Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ +typedef struct _ADI_PMG_TST_SCRPAD_3V_RD_t { + union { + struct { + unsigned int DATA : 32; /**< Reading the scratch pad stored in shutdown mode */ + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_SCRPAD_3V_RD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_SCRPAD_3V_RD_t__ */ + +/*@}*/ + +/** @defgroup FAST_SHT_WAKEUP Fast Shutdown Wake-up Enable (FAST_SHT_WAKEUP) Register + * Fast Shutdown Wake-up Enable (FAST_SHT_WAKEUP) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PMG_TST_FAST_SHT_WAKEUP_Struct + *! \brief Fast Shutdown Wake-up Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PMG_TST_FAST_SHT_WAKEUP_t__ +typedef struct _ADI_PMG_TST_FAST_SHT_WAKEUP_t { + union { + struct { + unsigned int FAST_SHT_WAKEUP : 1; /**< Enables fast shutdown wake-up */ + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_PMG_TST_FAST_SHT_WAKEUP_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PMG_TST_FAST_SHT_WAKEUP_t__ */ + +/*@}*/ + +/** @defgroup CTL0 Misc Clock Settings (CTL0) Register + * Misc Clock Settings (CTL0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL0_Struct + *! \brief Misc Clock Settings Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ +typedef struct _ADI_CLKG_CLK_CTL0_t { + union { + struct { + unsigned int CLKMUX : 2; /**< Clock mux select */ + unsigned int reserved2 : 1; + unsigned int CLKOUT : 4; /**< GPIO clock out select */ + unsigned int reserved7 : 1; + unsigned int RCLKMUX : 2; /**< Flash reference clock and HPBUCK clock source mux */ + unsigned int reserved10 : 1; + unsigned int PLL_IPSEL : 2; /**< SPLL source select mux */ + unsigned int reserved13 : 1; + unsigned int LFXTALIE : 1; /**< Low frequency crystal interrupt enable */ + unsigned int HFXTALIE : 1; /**< High frequency crystal interrupt enable */ + unsigned int reserved16 : 16; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL0_t__ */ + +/*@}*/ + +/** @defgroup CTL1 Clock Dividers (CTL1) Register + * Clock Dividers (CTL1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL1_Struct + *! \brief Clock Dividers Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ +typedef struct _ADI_CLKG_CLK_CTL1_t { + union { + struct { + unsigned int HCLKDIVCNT : 6; /**< HCLK divide count */ + unsigned int reserved6 : 2; + unsigned int PCLKDIVCNT : 6; /**< PCLK divide count */ + unsigned int reserved14 : 2; + unsigned int ACLKDIVCNT : 9; /**< ACLK Divide Count */ + unsigned int reserved25 : 7; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL1_t__ */ + +/*@}*/ + +/** @defgroup CTL2 HF Oscillator Divided Clock Select (CTL2) Register + * HF Oscillator Divided Clock Select (CTL2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL2_Struct + *! \brief HF Oscillator Divided Clock Select Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL2_t__ +typedef struct _ADI_CLKG_CLK_CTL2_t { + union { + struct { + unsigned int HFOSCAUTODIV_EN : 1; /**< HF Oscillator auto divide by one clock selection during wakeup from Flexi power mode */ + unsigned int HFOSCDIVCLKSEL : 3; /**< HF Oscillator divided clock select */ + unsigned int reserved4 : 28; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL2_t__ */ + +/*@}*/ + +/** @defgroup CTL3 System PLL (CTL3) Register + * System PLL (CTL3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL3_Struct + *! \brief System PLL Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ +typedef struct _ADI_CLKG_CLK_CTL3_t { + union { + struct { + unsigned int SPLLNSEL : 5; /**< System PLL N multiplier */ + unsigned int reserved5 : 3; + unsigned int SPLLDIV2 : 1; /**< System PLL division by 2 */ + unsigned int SPLLEN : 1; /**< System PLL enable */ + unsigned int SPLLIE : 1; /**< System PLL interrupt enable */ + unsigned int SPLLMSEL : 4; /**< System PLL M Divider */ + unsigned int reserved15 : 1; + unsigned int SPLLMUL2 : 1; /**< System PLL multiply by 2 */ + unsigned int reserved17 : 15; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL3_t__ */ + +/*@}*/ + +/** @defgroup CTL5 User Clock Gating Control (CTL5) Register + * User Clock Gating Control (CTL5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_CTL5_Struct + *! \brief User Clock Gating Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ +typedef struct _ADI_CLKG_CLK_CTL5_t { + union { + struct { + unsigned int GPTCLK0OFF : 1; /**< GP Timer 0 user control */ + unsigned int GPTCLK1OFF : 1; /**< GP Timer 1 user control */ + unsigned int GPTCLK2OFF : 1; /**< GP Timer 2 user control */ + unsigned int UCLKI2COFF : 1; /**< I2C clock user control */ + unsigned int GPIOCLKOFF : 1; /**< GPIO clock control */ + unsigned int PERCLKOFF : 1; /**< This bit is used to disable all clocks connected to all peripherals */ + unsigned int TMRRGBCLKOFF : 1; /**< Timer RGB user control */ + unsigned int reserved7 : 25; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_CTL5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_CTL5_t__ */ + +/*@}*/ + +/** @defgroup STAT0 Clocking Status (STAT0) Register + * Clocking Status (STAT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_CLKG_CLK_STAT0_Struct + *! \brief Clocking Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ +typedef struct _ADI_CLKG_CLK_STAT0_t { + union { + struct { + unsigned int SPLL : 1; /**< System PLL status */ + unsigned int SPLLLK : 1; /**< System PLL lock */ + unsigned int SPLLUNLK : 1; /**< System PLL unlock */ + unsigned int reserved3 : 5; + unsigned int LFXTAL : 1; /**< LF crystal status */ + unsigned int LFXTALOK : 1; /**< LF crystal stable */ + unsigned int LFXTALNOK : 1; /**< LF crystal not stable */ + unsigned int reserved11 : 1; + unsigned int HFXTAL : 1; /**< HF crystal status */ + unsigned int HFXTALOK : 1; /**< HF crystal stable */ + unsigned int HFXTALNOK : 1; /**< HF crystal not stable */ + unsigned int reserved15 : 17; + }; + uint32_t VALUE32; + }; +} ADI_CLKG_CLK_STAT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_CLKG_CLK_STAT0_t__ */ + +/*@}*/ + +/** @defgroup ARBIT0 Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register + * Arbitration Priority Configuration for FLASH and SRAM0 (ARBIT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT0_Struct + *! \brief Arbitration Priority Configuration for FLASH and SRAM0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ +typedef struct _ADI_BUSM_ARBIT0_t { + union { + struct { + unsigned int FLSH_DCODE : 2; /**< Flash priority for DCODE */ + unsigned int FLSH_SBUS : 2; /**< Flash priority for SBUS */ + unsigned int FLSH_DMA0 : 2; /**< Flash priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int SRAM0_DCODE : 2; /**< SRAM0 priority for Dcode */ + unsigned int SRAM0_SBUS : 2; /**< SRAM0 priority for SBUS */ + unsigned int SRAM0_DMA0 : 2; /**< SRAM0 priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT0_t__ */ + +/*@}*/ + +/** @defgroup ARBIT1 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register + * Arbitration Priority Configuration for SRAM1 and SIP (ARBIT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT1_Struct + *! \brief Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ +typedef struct _ADI_BUSM_ARBIT1_t { + union { + struct { + unsigned int SRAM1_DCODE : 2; /**< SRAM1 priority for Dcode */ + unsigned int SRAM1_SBUS : 2; /**< SRAM1 priority for SBUS */ + unsigned int SRAM1_DMA0 : 2; /**< SRAM1 priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int SIP_DCODE : 2; /**< SIP priority for DCODE */ + unsigned int SIP_SBUS : 2; /**< SIP priority for SBUS */ + unsigned int SIP_DMA0 : 2; /**< SIP priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT1_t__ */ + +/*@}*/ + +/** @defgroup ARBIT2 Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register + * Arbitration Priority Configuration for APB32 and APB16 (ARBIT2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT2_Struct + *! \brief Arbitration Priority Configuration for APB32 and APB16 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ +typedef struct _ADI_BUSM_ARBIT2_t { + union { + struct { + unsigned int APB32_DCODE : 2; /**< APB32 priority for DCODE */ + unsigned int APB32_SBUS : 2; /**< APB32 priority for SBUS */ + unsigned int APB32_DMA0 : 2; /**< APB32 priority for DMA0 */ + unsigned int reserved6 : 10; + unsigned int APB16_DCODE : 2; /**< APB16 priority for DCODE */ + unsigned int APB16_SBUS : 2; /**< APB16 priority for SBUS */ + unsigned int APB16_DMA0 : 2; /**< APB16 priority for DMA0 */ + unsigned int reserved22 : 10; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT2_t__ */ + +/*@}*/ + +/** @defgroup ARBIT3 Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register + * Arbitration Priority Configuration for APB16 priority for core and for DMA1 (ARBIT3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT3_Struct + *! \brief Arbitration Priority Configuration for APB16 priority for core and for DMA1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ +typedef struct _ADI_BUSM_ARBIT3_t { + union { + struct { + unsigned int APB16_CORE : 1; /**< APB16 priority for CORE */ + unsigned int APB16_DMA1 : 1; /**< APB16 priority for DMA1 */ + unsigned int reserved2 : 14; + unsigned int APB16_4DMA_CORE : 1; /**< APB16 for dma priority for CORE */ + unsigned int APB16_4DMA_DMA1 : 1; /**< APB16 for dma priority for DMA1 */ + unsigned int reserved18 : 14; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT3_t__ */ + +/*@}*/ + +/** @defgroup ARBIT4 Arbitration Priority Configuration for SRAM1 and SIP (ARBIT4) Register + * Arbitration Priority Configuration for SRAM1 and SIP (ARBIT4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_BUSM_ARBIT4_Struct + *! \brief Arbitration Priority Configuration for SRAM1 and SIP Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT4_t__ +typedef struct _ADI_BUSM_ARBIT4_t { + union { + struct { + unsigned int SRAM2_DCODE : 2; /**< SRAM2 priority for Dcode */ + unsigned int SRAM2_SBUS : 2; /**< SRAM2 priority for SBUS */ + unsigned int SRAM2_DMA0 : 2; /**< SRAM2 priority for DMA0 */ + unsigned int reserved6 : 26; + }; + uint32_t VALUE32; + }; +} ADI_BUSM_ARBIT4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_BUSM_ARBIT4_t__ */ + +/*@}*/ + +/** @defgroup RST_ISR_STARTADDR Reset ISR Start Address (RST_ISR_STARTADDR) Register + * Reset ISR Start Address (RST_ISR_STARTADDR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_RST_ISR_STARTADDR_Struct + *! \brief Reset ISR Start Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ +typedef struct _ADI_PTI_RST_ISR_STARTADDR_t { + union { + struct { + unsigned int VALUE : 32; + }; + uint32_t VALUE32; + }; +} ADI_PTI_RST_ISR_STARTADDR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_ISR_STARTADDR_t__ */ + +/*@}*/ + +/** @defgroup RST_STACK_PTR Reset Stack Pointer (RST_STACK_PTR) Register + * Reset Stack Pointer (RST_STACK_PTR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_RST_STACK_PTR_Struct + *! \brief Reset Stack Pointer Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ +typedef struct _ADI_PTI_RST_STACK_PTR_t { + union { + struct { + unsigned int VALUE : 32; + }; + uint32_t VALUE32; + }; +} ADI_PTI_RST_STACK_PTR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_RST_STACK_PTR_t__ */ + +/*@}*/ + +/** @defgroup CTL Parallel Test Interface Control Register (CTL) Register + * Parallel Test Interface Control Register (CTL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_PTI_CTL_Struct + *! \brief Parallel Test Interface Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ +typedef struct _ADI_PTI_CTL_t { + union { + struct { + unsigned int EN : 1; + unsigned int reserved1 : 31; + }; + uint32_t VALUE32; + }; +} ADI_PTI_CTL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_PTI_CTL_t__ */ + +/*@}*/ + +/** @defgroup INTNUM Interrupt Control Type (INTNUM) Register + * Interrupt Control Type (INTNUM) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTNUM_Struct + *! \brief Interrupt Control Type Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ +typedef struct _ADI_NVIC_INTNUM_t { + union { + struct { + unsigned int VALUE : 32; /**< Interrupt Control Type */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTNUM_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTNUM_t__ */ + +/*@}*/ + +/** @defgroup STKSTA Systick Control and Status (STKSTA) Register + * Systick Control and Status (STKSTA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKSTA_Struct + *! \brief Systick Control and Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ +typedef struct _ADI_NVIC_STKSTA_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Control and Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKSTA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKSTA_t__ */ + +/*@}*/ + +/** @defgroup STKLD Systick Reload Value (STKLD) Register + * Systick Reload Value (STKLD) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKLD_Struct + *! \brief Systick Reload Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ +typedef struct _ADI_NVIC_STKLD_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Reload Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKLD_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKLD_t__ */ + +/*@}*/ + +/** @defgroup STKVAL Systick Current Value (STKVAL) Register + * Systick Current Value (STKVAL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKVAL_Struct + *! \brief Systick Current Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ +typedef struct _ADI_NVIC_STKVAL_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Current Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKVAL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKVAL_t__ */ + +/*@}*/ + +/** @defgroup STKCAL Systick Calibration Value (STKCAL) Register + * Systick Calibration Value (STKCAL) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_STKCAL_Struct + *! \brief Systick Calibration Value Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ +typedef struct _ADI_NVIC_STKCAL_t { + union { + struct { + unsigned int VALUE : 32; /**< Systick Calibration Value */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_STKCAL_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_STKCAL_t__ */ + +/*@}*/ + +/** @defgroup INTSETE0 IRQ0..31 Set_Enable (INTSETE0) Register + * IRQ0..31 Set_Enable (INTSETE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETE0_Struct + *! \brief IRQ0..31 Set_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ +typedef struct _ADI_NVIC_INTSETE0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Set_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE0_t__ */ + +/*@}*/ + +/** @defgroup INTSETE1 IRQ32..63 Set_Enable (INTSETE1) Register + * IRQ32..63 Set_Enable (INTSETE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETE1_Struct + *! \brief IRQ32..63 Set_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ +typedef struct _ADI_NVIC_INTSETE1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Set_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETE1_t__ */ + +/*@}*/ + +/** @defgroup INTCLRE0 IRQ0..31 Clear_Enable (INTCLRE0) Register + * IRQ0..31 Clear_Enable (INTCLRE0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRE0_Struct + *! \brief IRQ0..31 Clear_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ +typedef struct _ADI_NVIC_INTCLRE0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Clear_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRE0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE0_t__ */ + +/*@}*/ + +/** @defgroup INTCLRE1 IRQ32..63 Clear_Enable (INTCLRE1) Register + * IRQ32..63 Clear_Enable (INTCLRE1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRE1_Struct + *! \brief IRQ32..63 Clear_Enable Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ +typedef struct _ADI_NVIC_INTCLRE1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Clear_Enable */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRE1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRE1_t__ */ + +/*@}*/ + +/** @defgroup INTSETP0 IRQ0..31 Set_Pending (INTSETP0) Register + * IRQ0..31 Set_Pending (INTSETP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETP0_Struct + *! \brief IRQ0..31 Set_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ +typedef struct _ADI_NVIC_INTSETP0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Set_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP0_t__ */ + +/*@}*/ + +/** @defgroup INTSETP1 IRQ32..63 Set_Pending (INTSETP1) Register + * IRQ32..63 Set_Pending (INTSETP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSETP1_Struct + *! \brief IRQ32..63 Set_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ +typedef struct _ADI_NVIC_INTSETP1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Set_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSETP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSETP1_t__ */ + +/*@}*/ + +/** @defgroup INTCLRP0 IRQ0..31 Clear_Pending (INTCLRP0) Register + * IRQ0..31 Clear_Pending (INTCLRP0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRP0_Struct + *! \brief IRQ0..31 Clear_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ +typedef struct _ADI_NVIC_INTCLRP0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Clear_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRP0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP0_t__ */ + +/*@}*/ + +/** @defgroup INTCLRP1 IRQ32..63 Clear_Pending (INTCLRP1) Register + * IRQ32..63 Clear_Pending (INTCLRP1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCLRP1_Struct + *! \brief IRQ32..63 Clear_Pending Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ +typedef struct _ADI_NVIC_INTCLRP1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Clear_Pending */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCLRP1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCLRP1_t__ */ + +/*@}*/ + +/** @defgroup INTACT0 IRQ0..31 Active Bit (INTACT0) Register + * IRQ0..31 Active Bit (INTACT0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTACT0_Struct + *! \brief IRQ0..31 Active Bit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ +typedef struct _ADI_NVIC_INTACT0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..31 Active Bit */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTACT0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT0_t__ */ + +/*@}*/ + +/** @defgroup INTACT1 IRQ32..63 Active Bit (INTACT1) Register + * IRQ32..63 Active Bit (INTACT1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTACT1_Struct + *! \brief IRQ32..63 Active Bit Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ +typedef struct _ADI_NVIC_INTACT1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..63 Active Bit */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTACT1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTACT1_t__ */ + +/*@}*/ + +/** @defgroup INTPRI0 IRQ0..3 Priority (INTPRI0) Register + * IRQ0..3 Priority (INTPRI0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI0_Struct + *! \brief IRQ0..3 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ +typedef struct _ADI_NVIC_INTPRI0_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ0..3 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI0_t__ */ + +/*@}*/ + +/** @defgroup INTPRI1 IRQ4..7 Priority (INTPRI1) Register + * IRQ4..7 Priority (INTPRI1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI1_Struct + *! \brief IRQ4..7 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ +typedef struct _ADI_NVIC_INTPRI1_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ4..7 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI1_t__ */ + +/*@}*/ + +/** @defgroup INTPRI2 IRQ8..11 Priority (INTPRI2) Register + * IRQ8..11 Priority (INTPRI2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI2_Struct + *! \brief IRQ8..11 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ +typedef struct _ADI_NVIC_INTPRI2_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ8..11 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI2_t__ */ + +/*@}*/ + +/** @defgroup INTPRI3 IRQ12..15 Priority (INTPRI3) Register + * IRQ12..15 Priority (INTPRI3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI3_Struct + *! \brief IRQ12..15 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ +typedef struct _ADI_NVIC_INTPRI3_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ12..15 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI3_t__ */ + +/*@}*/ + +/** @defgroup INTPRI4 IRQ16..19 Priority (INTPRI4) Register + * IRQ16..19 Priority (INTPRI4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI4_Struct + *! \brief IRQ16..19 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ +typedef struct _ADI_NVIC_INTPRI4_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ16..19 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI4_t__ */ + +/*@}*/ + +/** @defgroup INTPRI5 IRQ20..23 Priority (INTPRI5) Register + * IRQ20..23 Priority (INTPRI5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI5_Struct + *! \brief IRQ20..23 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ +typedef struct _ADI_NVIC_INTPRI5_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ20..23 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI5_t__ */ + +/*@}*/ + +/** @defgroup INTPRI6 IRQ24..27 Priority (INTPRI6) Register + * IRQ24..27 Priority (INTPRI6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI6_Struct + *! \brief IRQ24..27 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ +typedef struct _ADI_NVIC_INTPRI6_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ24..27 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI6_t__ */ + +/*@}*/ + +/** @defgroup INTPRI7 IRQ28..31 Priority (INTPRI7) Register + * IRQ28..31 Priority (INTPRI7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI7_Struct + *! \brief IRQ28..31 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ +typedef struct _ADI_NVIC_INTPRI7_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ28..31 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI7_t__ */ + +/*@}*/ + +/** @defgroup INTPRI8 IRQ32..35 Priority (INTPRI8) Register + * IRQ32..35 Priority (INTPRI8) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI8_Struct + *! \brief IRQ32..35 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ +typedef struct _ADI_NVIC_INTPRI8_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ32..35 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI8_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI8_t__ */ + +/*@}*/ + +/** @defgroup INTPRI9 IRQ36..39 Priority (INTPRI9) Register + * IRQ36..39 Priority (INTPRI9) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI9_Struct + *! \brief IRQ36..39 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ +typedef struct _ADI_NVIC_INTPRI9_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ36..39 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI9_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI9_t__ */ + +/*@}*/ + +/** @defgroup INTPRI10 IRQ40..43 Priority (INTPRI10) Register + * IRQ40..43 Priority (INTPRI10) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPRI10_Struct + *! \brief IRQ40..43 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ +typedef struct _ADI_NVIC_INTPRI10_t { + union { + struct { + unsigned int VALUE : 32; /**< IRQ40..43 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPRI10_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPRI10_t__ */ + +/*@}*/ + +/** @defgroup INTCPID CPUID Base (INTCPID) Register + * CPUID Base (INTCPID) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCPID_Struct + *! \brief CPUID Base Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ +typedef struct _ADI_NVIC_INTCPID_t { + union { + struct { + unsigned int VALUE : 32; /**< CPUID Base */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCPID_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCPID_t__ */ + +/*@}*/ + +/** @defgroup INTSTA Interrupt Control State (INTSTA) Register + * Interrupt Control State (INTSTA) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSTA_Struct + *! \brief Interrupt Control State Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ +typedef struct _ADI_NVIC_INTSTA_t { + union { + struct { + unsigned int VALUE : 32; /**< Interrupt Control State */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSTA_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSTA_t__ */ + +/*@}*/ + +/** @defgroup INTVEC Vector Table Offset (INTVEC) Register + * Vector Table Offset (INTVEC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTVEC_Struct + *! \brief Vector Table Offset Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ +typedef struct _ADI_NVIC_INTVEC_t { + union { + struct { + unsigned int VALUE : 32; /**< Vector Table Offset */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTVEC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTVEC_t__ */ + +/*@}*/ + +/** @defgroup INTAIRC Application Interrupt/Reset Control (INTAIRC) Register + * Application Interrupt/Reset Control (INTAIRC) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAIRC_Struct + *! \brief Application Interrupt/Reset Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ +typedef struct _ADI_NVIC_INTAIRC_t { + union { + struct { + unsigned int VALUE : 32; /**< Application Interrupt/Reset Control */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAIRC_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAIRC_t__ */ + +/*@}*/ + +/** @defgroup INTCON0 System Control (INTCON0) Register + * System Control (INTCON0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCON0_Struct + *! \brief System Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ +typedef struct _ADI_NVIC_INTCON0_t { + union { + struct { + unsigned int reserved0 : 1; + unsigned int SLEEPONEXIT : 1; /**< Sleeps the core on exit from an ISR */ + unsigned int SLEEPDEEP : 1; /**< deep sleep flag for HIBERNATE mode */ + unsigned int reserved3 : 13; + }; + uint16_t VALUE16; + }; +} ADI_NVIC_INTCON0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON0_t__ */ + +/*@}*/ + +/** @defgroup INTCON1 Configuration Control (INTCON1) Register + * Configuration Control (INTCON1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCON1_Struct + *! \brief Configuration Control Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ +typedef struct _ADI_NVIC_INTCON1_t { + union { + struct { + unsigned int VALUE : 32; /**< Configuration Control */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCON1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCON1_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO0 System Handlers 4-7 Priority (INTSHPRIO0) Register + * System Handlers 4-7 Priority (INTSHPRIO0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO0_Struct + *! \brief System Handlers 4-7 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ +typedef struct _ADI_NVIC_INTSHPRIO0_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 4-7 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO0_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO1 System Handlers 8-11 Priority (INTSHPRIO1) Register + * System Handlers 8-11 Priority (INTSHPRIO1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO1_Struct + *! \brief System Handlers 8-11 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ +typedef struct _ADI_NVIC_INTSHPRIO1_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 8-11 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO1_t__ */ + +/*@}*/ + +/** @defgroup INTSHPRIO3 System Handlers 12-15 Priority (INTSHPRIO3) Register + * System Handlers 12-15 Priority (INTSHPRIO3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHPRIO3_Struct + *! \brief System Handlers 12-15 Priority Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ +typedef struct _ADI_NVIC_INTSHPRIO3_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handlers 12-15 Priority */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHPRIO3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHPRIO3_t__ */ + +/*@}*/ + +/** @defgroup INTSHCSR System Handler Control and State (INTSHCSR) Register + * System Handler Control and State (INTSHCSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTSHCSR_Struct + *! \brief System Handler Control and State Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ +typedef struct _ADI_NVIC_INTSHCSR_t { + union { + struct { + unsigned int VALUE : 32; /**< System Handler Control and State */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTSHCSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTSHCSR_t__ */ + +/*@}*/ + +/** @defgroup INTCFSR Configurable Fault Status (INTCFSR) Register + * Configurable Fault Status (INTCFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCFSR_Struct + *! \brief Configurable Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ +typedef struct _ADI_NVIC_INTCFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Configurable Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCFSR_t__ */ + +/*@}*/ + +/** @defgroup INTHFSR Hard Fault Status (INTHFSR) Register + * Hard Fault Status (INTHFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTHFSR_Struct + *! \brief Hard Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ +typedef struct _ADI_NVIC_INTHFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Hard Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTHFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTHFSR_t__ */ + +/*@}*/ + +/** @defgroup INTDFSR Debug Fault Status (INTDFSR) Register + * Debug Fault Status (INTDFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTDFSR_Struct + *! \brief Debug Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ +typedef struct _ADI_NVIC_INTDFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Debug Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTDFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFSR_t__ */ + +/*@}*/ + +/** @defgroup INTMMAR Mem Manage Address (INTMMAR) Register + * Mem Manage Address (INTMMAR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMAR_Struct + *! \brief Mem Manage Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ +typedef struct _ADI_NVIC_INTMMAR_t { + union { + struct { + unsigned int VALUE : 32; /**< Mem Manage Address */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMAR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMAR_t__ */ + +/*@}*/ + +/** @defgroup INTBFAR Bus Fault Address (INTBFAR) Register + * Bus Fault Address (INTBFAR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTBFAR_Struct + *! \brief Bus Fault Address Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ +typedef struct _ADI_NVIC_INTBFAR_t { + union { + struct { + unsigned int VALUE : 32; /**< Bus Fault Address */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTBFAR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTBFAR_t__ */ + +/*@}*/ + +/** @defgroup INTAFSR Auxiliary Fault Status (INTAFSR) Register + * Auxiliary Fault Status (INTAFSR) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAFSR_Struct + *! \brief Auxiliary Fault Status Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ +typedef struct _ADI_NVIC_INTAFSR_t { + union { + struct { + unsigned int VALUE : 32; /**< Auxiliary Fault Status */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAFSR_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFSR_t__ */ + +/*@}*/ + +/** @defgroup INTPFR0 Processor Feature Register 0 (INTPFR0) Register + * Processor Feature Register 0 (INTPFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPFR0_Struct + *! \brief Processor Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ +typedef struct _ADI_NVIC_INTPFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Processor Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR0_t__ */ + +/*@}*/ + +/** @defgroup INTPFR1 Processor Feature Register 1 (INTPFR1) Register + * Processor Feature Register 1 (INTPFR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPFR1_Struct + *! \brief Processor Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ +typedef struct _ADI_NVIC_INTPFR1_t { + union { + struct { + unsigned int VALUE : 32; /**< Processor Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPFR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPFR1_t__ */ + +/*@}*/ + +/** @defgroup INTDFR0 Debug Feature Register 0 (INTDFR0) Register + * Debug Feature Register 0 (INTDFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTDFR0_Struct + *! \brief Debug Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ +typedef struct _ADI_NVIC_INTDFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Debug Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTDFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTDFR0_t__ */ + +/*@}*/ + +/** @defgroup INTAFR0 Auxiliary Feature Register 0 (INTAFR0) Register + * Auxiliary Feature Register 0 (INTAFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTAFR0_Struct + *! \brief Auxiliary Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ +typedef struct _ADI_NVIC_INTAFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Auxiliary Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTAFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTAFR0_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR0 Memory Model Feature Register 0 (INTMMFR0) Register + * Memory Model Feature Register 0 (INTMMFR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR0_Struct + *! \brief Memory Model Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ +typedef struct _ADI_NVIC_INTMMFR0_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR0_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR1 Memory Model Feature Register 1 (INTMMFR1) Register + * Memory Model Feature Register 1 (INTMMFR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR1_Struct + *! \brief Memory Model Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ +typedef struct _ADI_NVIC_INTMMFR1_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR1_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR2 Memory Model Feature Register 2 (INTMMFR2) Register + * Memory Model Feature Register 2 (INTMMFR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR2_Struct + *! \brief Memory Model Feature Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ +typedef struct _ADI_NVIC_INTMMFR2_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 2 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR2_t__ */ + +/*@}*/ + +/** @defgroup INTMMFR3 Memory Model Feature Register 3 (INTMMFR3) Register + * Memory Model Feature Register 3 (INTMMFR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTMMFR3_Struct + *! \brief Memory Model Feature Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ +typedef struct _ADI_NVIC_INTMMFR3_t { + union { + struct { + unsigned int VALUE : 32; /**< Memory Model Feature Register 3 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTMMFR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTMMFR3_t__ */ + +/*@}*/ + +/** @defgroup INTISAR0 ISA Feature Register 0 (INTISAR0) Register + * ISA Feature Register 0 (INTISAR0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR0_Struct + *! \brief ISA Feature Register 0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ +typedef struct _ADI_NVIC_INTISAR0_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR0_t__ */ + +/*@}*/ + +/** @defgroup INTISAR1 ISA Feature Register 1 (INTISAR1) Register + * ISA Feature Register 1 (INTISAR1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR1_Struct + *! \brief ISA Feature Register 1 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ +typedef struct _ADI_NVIC_INTISAR1_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 1 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR1_t__ */ + +/*@}*/ + +/** @defgroup INTISAR2 ISA Feature Register 2 (INTISAR2) Register + * ISA Feature Register 2 (INTISAR2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR2_Struct + *! \brief ISA Feature Register 2 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ +typedef struct _ADI_NVIC_INTISAR2_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 2 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR2_t__ */ + +/*@}*/ + +/** @defgroup INTISAR3 ISA Feature Register 3 (INTISAR3) Register + * ISA Feature Register 3 (INTISAR3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR3_Struct + *! \brief ISA Feature Register 3 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ +typedef struct _ADI_NVIC_INTISAR3_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 3 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR3_t__ */ + +/*@}*/ + +/** @defgroup INTISAR4 ISA Feature Register 4 (INTISAR4) Register + * ISA Feature Register 4 (INTISAR4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTISAR4_Struct + *! \brief ISA Feature Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ +typedef struct _ADI_NVIC_INTISAR4_t { + union { + struct { + unsigned int VALUE : 32; /**< ISA Feature Register 4 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTISAR4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTISAR4_t__ */ + +/*@}*/ + +/** @defgroup INTTRGI Software Trigger Interrupt Register (INTTRGI) Register + * Software Trigger Interrupt Register (INTTRGI) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTTRGI_Struct + *! \brief Software Trigger Interrupt Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ +typedef struct _ADI_NVIC_INTTRGI_t { + union { + struct { + unsigned int VALUE : 32; /**< Software Trigger Interrupt Register */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTTRGI_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTTRGI_t__ */ + +/*@}*/ + +/** @defgroup INTPID4 Peripheral Identification Register 4 (INTPID4) Register + * Peripheral Identification Register 4 (INTPID4) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID4_Struct + *! \brief Peripheral Identification Register 4 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ +typedef struct _ADI_NVIC_INTPID4_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 4 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID4_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID4_t__ */ + +/*@}*/ + +/** @defgroup INTPID5 Peripheral Identification Register 5 (INTPID5) Register + * Peripheral Identification Register 5 (INTPID5) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID5_Struct + *! \brief Peripheral Identification Register 5 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ +typedef struct _ADI_NVIC_INTPID5_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 5 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID5_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID5_t__ */ + +/*@}*/ + +/** @defgroup INTPID6 Peripheral Identification Register 6 (INTPID6) Register + * Peripheral Identification Register 6 (INTPID6) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID6_Struct + *! \brief Peripheral Identification Register 6 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ +typedef struct _ADI_NVIC_INTPID6_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 6 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID6_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID6_t__ */ + +/*@}*/ + +/** @defgroup INTPID7 Peripheral Identification Register 7 (INTPID7) Register + * Peripheral Identification Register 7 (INTPID7) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID7_Struct + *! \brief Peripheral Identification Register 7 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ +typedef struct _ADI_NVIC_INTPID7_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Register 7 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID7_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID7_t__ */ + +/*@}*/ + +/** @defgroup INTPID0 Peripheral Identification Bits7:0 (INTPID0) Register + * Peripheral Identification Bits7:0 (INTPID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID0_Struct + *! \brief Peripheral Identification Bits7:0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ +typedef struct _ADI_NVIC_INTPID0_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits7:0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID0_t__ */ + +/*@}*/ + +/** @defgroup INTPID1 Peripheral Identification Bits15:8 (INTPID1) Register + * Peripheral Identification Bits15:8 (INTPID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID1_Struct + *! \brief Peripheral Identification Bits15:8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ +typedef struct _ADI_NVIC_INTPID1_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits15:8 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID1_t__ */ + +/*@}*/ + +/** @defgroup INTPID2 Peripheral Identification Bits16:23 (INTPID2) Register + * Peripheral Identification Bits16:23 (INTPID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID2_Struct + *! \brief Peripheral Identification Bits16:23 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ +typedef struct _ADI_NVIC_INTPID2_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits16:23 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID2_t__ */ + +/*@}*/ + +/** @defgroup INTPID3 Peripheral Identification Bits24:31 (INTPID3) Register + * Peripheral Identification Bits24:31 (INTPID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTPID3_Struct + *! \brief Peripheral Identification Bits24:31 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ +typedef struct _ADI_NVIC_INTPID3_t { + union { + struct { + unsigned int VALUE : 32; /**< Peripheral Identification Bits24:31 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTPID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTPID3_t__ */ + +/*@}*/ + +/** @defgroup INTCID0 Component Identification Bits7:0 (INTCID0) Register + * Component Identification Bits7:0 (INTCID0) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID0_Struct + *! \brief Component Identification Bits7:0 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ +typedef struct _ADI_NVIC_INTCID0_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits7:0 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID0_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID0_t__ */ + +/*@}*/ + +/** @defgroup INTCID1 Component Identification Bits15:8 (INTCID1) Register + * Component Identification Bits15:8 (INTCID1) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID1_Struct + *! \brief Component Identification Bits15:8 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ +typedef struct _ADI_NVIC_INTCID1_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits15:8 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID1_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID1_t__ */ + +/*@}*/ + +/** @defgroup INTCID2 Component Identification Bits16:23 (INTCID2) Register + * Component Identification Bits16:23 (INTCID2) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID2_Struct + *! \brief Component Identification Bits16:23 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ +typedef struct _ADI_NVIC_INTCID2_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits16:23 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID2_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID2_t__ */ + +/*@}*/ + +/** @defgroup INTCID3 Component Identification Bits24:31 (INTCID3) Register + * Component Identification Bits24:31 (INTCID3) Register. + * @{ + */ + +/* ========================================================================== + *! \struct ADI_NVIC_INTCID3_Struct + *! \brief Component Identification Bits24:31 Register bit field structure + * ========================================================================== */ +#ifndef __ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ +typedef struct _ADI_NVIC_INTCID3_t { + union { + struct { + unsigned int VALUE : 32; /**< Component Identification Bits24:31 */ + }; + uint32_t VALUE32; + }; +} ADI_NVIC_INTCID3_t; +#endif /* !__ADI_NO_DECL_STRUCT_ADI_NVIC_INTCID3_t__ */ + +/*@}*/ + + +#if defined (_MISRA_RULES) +#pragma diag(pop) +#endif /* _MISRA_RULES */ + + +#if defined (__CC_ARM) +#pragma pop +#endif + +#endif diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h new file mode 100755 index 00000000000..45f235b44be --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/adi_cio_macros.h @@ -0,0 +1,50 @@ +/* +** adi_cio_macros.h +** +** Copyright (C) 2016 Analog Devices, Inc. All Rights Reserved. +** +*/ + +#ifndef _ADI_CIO_MACROS_H +#define _ADI_CIO_MACROS_H + +/* + * Macro definitions in adi_ADuCM4*50_cdef.h and the struct definitions + * in adi_ADuCM4*50_device.h use macros "__I __C", "__O" and "__IO" to + * represent read-only, write-only and read/write register attributes. + * + * The core_cm4.h include file will define macros __I, __O and __IO as below + * but it does not define __C. + * + * The __C macro is defined to nothing here. The __C macro is intended for + * the proprietary compilers in CCES to avoid MISRA Rule 19.4 errors regarding + * permitted macro expansions. The iccarm.exe MISRA checking does not fault + * the combined "volatile const" __I macro so __C is not required. + * + * Each of the macro defines is guarded by a #ifndef check to allow them + * to be redefined if required. + * + * Workaround for 01-00-0757 / 01-00-0759 + */ + +#ifndef __I + #ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ + #else + #define __I volatile const /*!< Defines 'read only' permissions */ + #endif +#endif + +#ifndef __O + #define __O volatile /*!< Defines 'write only' permissions */ +#endif + +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +#ifndef __C + #define __C /*nothing*/ +#endif + +#endif /* _ADI_CIO_MACROS_H */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h new file mode 100755 index 00000000000..c21be7b2935 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/sys/platform.h @@ -0,0 +1,56 @@ +/*! + ***************************************************************************** + * @file: platform.h + * @brief: Include appropriate architecture definitions. + *----------------------------------------------------------------------------- + * +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef __ADI_SYS_PLATFORM_H__ +#define __ADI_SYS_PLATFORM_H__ + +/* Include the ADI cdef header for the selected target. */ + +#if defined(__ADUCM4050__) +#include +#else +#error not configured for this target. +#endif + +#endif /* __ADI_SYS_PLATFORM_H__ */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h new file mode 100755 index 00000000000..5bde78d691e --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/system_ADuCM4050.h @@ -0,0 +1,159 @@ +/*! + ***************************************************************************** + * @file: system_ADuCM4050.h + * @brief: CMSIS Cortex-M4 Device Peripheral Access Layer Header File + * for ADuCM4050 + * @version V3.10 + * @date 23. November 2012 + * + * @note Modified September 21 2016 Analog Devices +******************************************************************************/ +/* Copyright (c) 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef SYSTEM_ADUCM4050_H +#define SYSTEM_ADUCM4050_H + +#include /* for 'NULL' */ +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +#if defined (__ICCARM__) +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): Types which specify sign and size should be used +* We use bool which is accepted by MISRA but the toolchain does not accept it +* +*/ +#pragma diag_suppress=Pm011 + +#endif + +/*! \addtogroup SYS_Driver System Interfaces + * @{ + * System global interfaces and CMSIS required variables + */ + +/*! System API function return codes */ +typedef enum +{ + ADI_SYS_SUCCESS = 0, /*!< No error detected. */ + ADI_SYS_FAILURE, /*!< The API call failed. */ +} ADI_SYS_RESULT; + + +/*! \cond PRIVATE */ +/* System clock constant */ +#define __HFOSC 26000000u + +/* System clock constant (may also be 16000000) */ +#define __HFXTAL 26000000u + + /*System clock constant (same whether internal osc or external xtal) */ +#define __LFCLK 32768u + + /*Selecting HFOSC as input for generating root clock*/ +#define HFMUX_INTERNAL_OSC_VAL (0u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting HFXTAL as input for generating root clock*/ +#define HFMUX_EXTERNAL_XTAL_VAL (1u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting SPLL as input for generating root clock*/ +#define HFMUX_SYSTEM_SPLL_VAL (2u << BITP_CLKG_CLK_CTL0_CLKMUX) + + /*Selecting GPIO as input for generating root clock*/ +#define HFMUX_GPIO_VAL (3u << BITP_CLKG_CLK_CTL0_CLKMUX) + +/*! Cache controller key */ +#define CACHE_CONTROLLER_KEY 0xF123F456u +/*! Power key */ +#define PWRKEY_VALUE_KEY 0x4859u + +/** + * Security options + */ +typedef struct { + const uint32_t ReadProtectKeyHash[4]; + const uint32_t CrcOfReadProtectKeyHash; + const uint32_t LastCRCPage; + const uint32_t InCircuitWriteProtectCode; + const uint32_t FlashBlockWriteProtect; + +} ADI_ADUCM4X50_SECURITY_OPTIONS; + +/*! \endcond*/ + +/** + * SRAM banks + */ +typedef uint32_t ADI_SRAM_BANK; + +/*! SRAM_BANK_0 */ +#define ADI_SRAM_BANK_0 (1u << 0) +/*! SRAM_BANK_1 */ +#define ADI_SRAM_BANK_1 (1u << 1) +/*! SRAM_BANK_2 */ +#define ADI_SRAM_BANK_2 (1u << 2) +/*! SRAM_BANK_3 */ +#define ADI_SRAM_BANK_3 (1u << 3) +/*! SRAM_BANK_4 */ +#define ADI_SRAM_BANK_4 (1u << 4) +/*! SRAM_BANK_5 */ +#define ADI_SRAM_BANK_5 (1u << 5) +/*! SRAM_BANK_6 */ +#define ADI_SRAM_BANK_6 (1u << 6) +/*! SRAM_BANK_7 */ +#define ADI_SRAM_BANK_7 (1u << 7) + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +void adi_system_EnableCache(bool bEnable); +ADI_SYS_RESULT adi_system_EnableRetention(ADI_SRAM_BANK eBank, bool bEnable); +void adi_system_EnableISRAM(bool bEnable); + +#if defined (__ICCARM__) +#pragma diag_default=Pm011 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ADUCM4050_H */ + +/*@}*/ +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c new file mode 100755 index 00000000000..b7153b79a8d --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c @@ -0,0 +1,611 @@ +/*! ***************************************************************************** + * @file adi_tmr.c + * @brief GP and RGB timer device driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used +* Necessary for stdbool. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm123 (rule 8.5): there shall be no definition of objects or functions in a header file +* Static configuration data file is included. +* +* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type +* This violation appears when deferencing the pointer to the register typedef. No way around this. +* +* Pm141 (Rule 11.4): a cast should not be performed between a pointer to object type and a different pointer to object type +* The pointer casting is necessary to allow the GP and RGB timers to abstracted into one driver. This has been approved by the PO. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm123,Pm140,Pm141,Pm143 +#endif /* __ICCARM__ */ + + +/** @addtogroup TMR_Driver Timer Driver + * @{ + * @brief General Purpose and RGB Timer Driver + * @details The timer driver controls the timer period, event capture, and + * pulse width modulation (PWM) features of the General Purpose (GP) Timers and + * the RGB Timer. + * @note The application must include drivers/tmr/adi_tmr.h to use this driver + */ + +#include +#include +#include +#include + +/* Static configuration data */ +#if ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT == 1u +#include "adi_tmr_data.c" +#endif + + +/* In adi_tmr_ConfigPwm, the bit positions for just PWM0 are used for PWM1 and PWM2 to simplify the code. Check here to make sure this is safe. */ +#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM1CTL_IDLESTATE +#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_IDLESTATE != BITP_TMR_RGB_PWM2CTL_IDLESTATE +#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM1CTL_MATCH +#error "Bit positions for PWM0 and PWM1 do not match. Fix adi_tmr_ConfigPwm." +#endif +#if BITP_TMR_RGB_PWM0CTL_MATCH != BITP_TMR_RGB_PWM2CTL_MATCH +#error "Bit positions for PWM0 and PWM2 do not match. Fix adi_tmr_ConfigPwm." +#endif + +/*! Number of events that can be captured */ +#define ADI_TMR_NUM_EVENTS (40u) + +/*! \cond PRIVATE */ + +/* Since the RGB typedef is a superset of the GP typedef, treat the GP timers as RGB timers and restrict top register access */ +static ADI_TMR_RGB_TypeDef * adi_tmr_registers[ADI_TMR_DEVICE_NUM] = {(ADI_TMR_RGB_TypeDef *) pADI_TMR0, (ADI_TMR_RGB_TypeDef *) pADI_TMR1, (ADI_TMR_RGB_TypeDef *) pADI_TMR2, pADI_TMR_RGB}; + +/* Interrupt enums */ +static const IRQn_Type adi_tmr_interrupt[ADI_TMR_DEVICE_NUM] = {TMR0_EVT_IRQn, TMR1_EVT_IRQn, TMR2_EVT_IRQn, TMR_RGB_EVT_IRQn}; + +/* Private data that the driver needs to retain between function calls */ +static ADI_CALLBACK adi_tmr_callbacks[ADI_TMR_DEVICE_NUM]; +static void * adi_tmr_parameters[ADI_TMR_DEVICE_NUM]; + +static ADI_TMR_RESULT WaitForStatusBit (ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit); +static void CommonIntHandler (ADI_TMR_DEVICE const eDevice); + void GP_Tmr0_Int_Handler(void); + void GP_Tmr1_Int_Handler(void); + void GP_Tmr2_Int_Handler(void); + void RGB_Tmr_Int_Handler(void); + +/*! \endcond */ + + +/********************************************************************************* + API IMPLEMENTATIONS +*********************************************************************************/ + + +/*! + * @brief Initialize GP or RGB Timer + * + * @details Setup callback function, device interrupt, and perform static configuration (if applicable). + * + * @note This function can only be called when the timer is disabled. This function should be called + * before any other functions are called. + * + * @param [in] eDevice : Device number + * + * @param [in] pfCallback : Callback function + * + * @param [in] pCBParam : Callback function parameter + * + * @param [in] bEnableInt : True to enable the device interrupt, false to disable it + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Init(ADI_TMR_DEVICE const eDevice, ADI_CALLBACK const pfCallback, void * const pCBParam, bool bEnableInt) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Setup the callback function */ + adi_tmr_callbacks [eDevice] = pfCallback; + adi_tmr_parameters[eDevice] = pCBParam; + + /* IF(Enable interrupt) */ + if (bEnableInt == true) { + NVIC_EnableIRQ(adi_tmr_interrupt[eDevice]); + /* ELSE(Disable interrupt) */ + } else { + NVIC_DisableIRQ(adi_tmr_interrupt[eDevice]); + } /* ENDIF */ + + /* Static configuration */ +#if ADI_TIMER_ENABLE_STATIC_CONFIG_SUPPORT == 1u + adi_tmr_registers[eDevice]->CTL = aTimerCtlConfig [eDevice]; + adi_tmr_registers[eDevice]->LOAD = aTimerLoadConfig [eDevice]; + adi_tmr_registers[eDevice]->ALOAD = aTimerALoadConfig [eDevice]; + adi_tmr_registers[eDevice]->EVENTSELECT = aTimerEventConfig [eDevice]; + adi_tmr_registers[eDevice]->PWM0CTL = aTimerPwmCtlConfig [eDevice]; + adi_tmr_registers[eDevice]->PWM0MATCH = aTimerPwmMatchConfig[eDevice]; + + /* IF(Initializing the RGB timer, there are 2 other PWM outputs to configure) */ + if (eDevice == ADI_TMR_DEVICE_RGB) { + /* The array is bumped by 1 to get to the 5th entry in the static config array, which contains RGB PWM1 */ + adi_tmr_registers[eDevice]->PWM1CTL = aTimerPwmCtlConfig [eDevice+1u]; + adi_tmr_registers[eDevice]->PWM1MATCH = aTimerPwmMatchConfig[eDevice+1u]; + /* The array is bumped by 2 to get to the 6th entry in the static config array, which contains RGB PWM2 */ + adi_tmr_registers[eDevice]->PWM2CTL = aTimerPwmCtlConfig [eDevice+2u]; + adi_tmr_registers[eDevice]->PWM2MATCH = aTimerPwmMatchConfig[eDevice+2u]; + } /* ENDIF */ +#endif + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Configure GP or RGB Timer + * + * @details Configure the basic hardware timer parameters. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] timerConfig : Timer configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_BAD_RELOAD_CONFIGURATION [D] bPeriodic is false and bReloading is true + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG timerConfig) { + uint16_t nTemp; +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Bad configuration, cannot enable reloading while in free running mode) */ + if ((timerConfig.bPeriodic == false) && (timerConfig.bReloading == true)) { + return ADI_TMR_BAD_RELOAD_CONFIGURATION; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Set the load registers */ + adi_tmr_registers[eDevice]->LOAD = timerConfig.nLoad; + adi_tmr_registers[eDevice]->ALOAD = timerConfig.nAsyncLoad; + + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Read the control register and clear everything aside to the event capture bits, which are the only fields not set in this function */ + nTemp = adi_tmr_registers[eDevice]->CTL; + nTemp &= (uint16_t) (BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN); + + /* Setup the prescaler and the clock source */ + nTemp |= (uint16_t)(((uint16_t) timerConfig.ePrescaler ) << BITP_TMR_RGB_CTL_PRE); + nTemp |= (uint16_t)(((uint16_t) timerConfig.eClockSource) << BITP_TMR_RGB_CTL_CLK); + + /* IF(Periodic mode) */ + if (timerConfig.bPeriodic == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_MODE); + } /* ENDIF */ + + /* IF(Counting up) */ + if (timerConfig.bCountingUp == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_UP); + } /* ENDIF */ + + /* IF(Reloading is enabled) */ + if (timerConfig.bReloading == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_RLD); + } /* ENDIF */ + + /* IF(Sync bypass is enabled) */ + if (timerConfig.bSyncBypass == true) { + nTemp |= (1u << BITP_TMR_RGB_CTL_SYNCBYP); + } /* ENDIF */ + + /* Update the control register with the new configuration */ + adi_tmr_registers[eDevice]->CTL = nTemp; + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Setup GP or RGB Timer Event Capture + * + * @details The timer can be configured to capture the timer value when a specific event occurs. The + * list of events can be found in the hardware reference manual. The callback function specified + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The + * user can then read the captured value by calling #adi_tmr_GetCaptureCount. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] eventConfig : Event configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_BAD_EVENT_ID [D] Event ID was not out of the valid range [0,#ADI_TMR_NUM_EVENTS] + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigEvent(ADI_TMR_DEVICE const eDevice, ADI_TMR_EVENT_CONFIG eventConfig) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Bad event input parameter) */ + if (eventConfig.nEventID >= ADI_TMR_NUM_EVENTS) { + return ADI_TMR_BAD_EVENT_ID; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ +#endif + /* Set the event number */ + adi_tmr_registers[eDevice]->EVENTSELECT = (uint16_t) eventConfig.nEventID; + + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Clear the event enable bit and keep the other bits */ + adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~(BITM_TMR_RGB_CTL_EVTEN | BITM_TMR_RGB_CTL_RSTEN); + + /* IF(Turning event capture on) */ + if (eventConfig.bEnable == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EVTEN; + } /* ENDIF */ + + /* IF(Enabling reset on event capture) */ + if (eventConfig.bPrescaleReset == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_RSTEN; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Setup GP or RGB Timer Pulse Width Modulation + * + * @details The timer can be configured to generate a pulse width modulation output signal. + * The period of this signal is simply determined by the period of timer. The duty + * cycle will be 50% in toggle mode, or can be configured by the user for a different + * value using the match value. The pulse will toggle when the timer count matches + * the match value. The user can also specify the polarity of the signal by choosing + * if the signal idles low or high. GPIO muxing will be required to use the PWM output. + * + * @note This function can only be called when the timer is disabled. + * + * @param [in] eDevice : Device number + * + * @param [in] pwmConfig : PWM configuration structure, filled by user prior to function call + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_OPERATION_NOT_ALLOWED [D] Timer is currently running + * - #ADI_TMR_BAD_PWM_NUM [D] Invalid eOutput parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_ConfigPwm(ADI_TMR_DEVICE const eDevice, ADI_TMR_PWM_CONFIG pwmConfig) { + uint16_t nControl = 0u; +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(The timer is already running) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_EN) == BITM_TMR_RGB_CTL_EN) { + return ADI_TMR_OPERATION_NOT_ALLOWED; + } /* ENDIF */ + /* IF(Bad PWM output and device combo OR bad PWM output) */ + if (((eDevice != ADI_TMR_DEVICE_RGB) && (pwmConfig.eOutput != ADI_TMR_PWM_OUTPUT_0)) || (pwmConfig.eOutput >= ADI_TMR_PWM_OUTPUT_NUM)) { + return ADI_TMR_BAD_PWM_NUM; + } /* ENDIF */ +#endif + /* IF(Idle high is set) */ + if (pwmConfig.bIdleHigh == true) { + nControl = (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_IDLESTATE)); + } /* ENDIF */ + + /* IF(Match mode is enabled) */ + if (pwmConfig.bMatch == true) { + nControl |= (1u << ((uint16_t) BITP_TMR_RGB_PWM0CTL_MATCH)); + } /* ENDIF */ + + /* IF(PWM output 0) */ + if (pwmConfig.eOutput == ADI_TMR_PWM_OUTPUT_0) { + adi_tmr_registers[eDevice]->PWM0CTL = nControl; + adi_tmr_registers[eDevice]->PWM0MATCH = pwmConfig.nMatchValue; + /* IF(PWM output 1) */ + } else if (pwmConfig.eOutput == ADI_TMR_PWM_OUTPUT_1) { + adi_tmr_registers[eDevice]->PWM1CTL = nControl; + adi_tmr_registers[eDevice]->PWM1MATCH = pwmConfig.nMatchValue; + /* ELSE(PWM output 2) */ + } else { + adi_tmr_registers[eDevice]->PWM2CTL = nControl; + adi_tmr_registers[eDevice]->PWM2MATCH = pwmConfig.nMatchValue; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Enable or Disable the GP or RGB Timer + * + * @details Start or stop the timer. + * + * @param [in] eDevice : Device number + * + * @param [in] bEnable : True to enable, false to disable + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_DEVICE_BUSY Timer is busy processing a previous control register write + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Enable(ADI_TMR_DEVICE const eDevice, bool bEnable) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ +#endif + /* IF(Busy bit does not clear after waiting) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_BUSY)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + + /* Clear the enable bit and keep the other bits */ + adi_tmr_registers[eDevice]->CTL &= (uint16_t) ~BITM_TMR_RGB_CTL_EN; + + /* IF(Turning the timer on) */ + if (bEnable == true) { + adi_tmr_registers[eDevice]->CTL |= (uint16_t) BITM_TMR_RGB_CTL_EN; + } /* ENDIF */ + + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Get GP or RGB Timer Current Count + * + * @details Read the timer. + * + * @param [in] eDevice : Device number + * + * @param [out] pCount : Pointer to the result. + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_NULL_POINTER [D] Invalid pCount parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_GetCurrentCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Null pointer) */ + if (pCount == NULL) { + return ADI_TMR_NULL_POINTER; + } /* ENDIF */ +#endif + *pCount = adi_tmr_registers[eDevice]->CURCNT; + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Get GP or RGB Timer Captured Count + * + * @details Read the captured timer value. This should be called after the callback function + * is called with #ADI_TMR_EVENT_CAPTURE in the Event field. + * + * @param [in] eDevice : Device number + * + * @param [out] pCount : Pointer to the result. + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_NULL_POINTER [D] Invalid pCount parameter supplied + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_GetCaptureCount(ADI_TMR_DEVICE const eDevice, uint16_t *pCount) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Null pointer) */ + if (pCount == NULL) { + return ADI_TMR_NULL_POINTER; + } /* ENDIF */ +#endif + *pCount = adi_tmr_registers[eDevice]->CAPTURE; + return ADI_TMR_SUCCESS; +} + + +/*! + * @brief Reload GP or RGB Timer + * + * @details Only relevent in peridic mode and when bReloading was set to + * true when configuring the timer. Calling this function will + * reload (i.e. reset) the timer to the LOAD value. + * + * @param [in] eDevice : Device number + * + * @return ADI_TMR_RESULT + * - #ADI_TMR_BAD_DEVICE_NUM [D] Invalid eDevice parameter supplied + * - #ADI_TMR_RELOAD_DISABLED [D] Reloading not enabled for this timer + * - #ADI_TMR_DEVICE_BUSY Reload did not take effect in time + * - #ADI_TMR_SUCCESS Function call completed successfully + * + */ +ADI_TMR_RESULT adi_tmr_Reload(ADI_TMR_DEVICE const eDevice) { +#ifdef ADI_DEBUG + /* IF(Bad device input parameter) */ + if (eDevice >= ADI_TMR_DEVICE_NUM) { + return ADI_TMR_BAD_DEVICE_NUM; + } /* ENDIF */ + /* IF(Reloading has not been enabled) */ + if ((adi_tmr_registers[eDevice]->CTL & BITM_TMR_RGB_CTL_RLD) != BITM_TMR_RGB_CTL_RLD) { + return ADI_TMR_RELOAD_DISABLED; + } /* ENDIF */ +#endif + /* Clear the timeout bit to cause a reload to happen */ + adi_tmr_registers[eDevice]->CLRINT = BITM_TMR_RGB_CLRINT_TIMEOUT; + /* IF(The clear interrupt does not take effect in a reasonable amount of time) */ + if (ADI_TMR_SUCCESS != WaitForStatusBit(eDevice, (uint16_t) BITM_TMR_RGB_STAT_PDOK)) { + return ADI_TMR_DEVICE_BUSY; + } /* ENDIF */ + return ADI_TMR_SUCCESS; +} + + +/********************************************************************************* + PRIVATE FUNCTIONS +*********************************************************************************/ + + /*! \cond PRIVATE */ + +static ADI_TMR_RESULT WaitForStatusBit(ADI_TMR_DEVICE const eDevice, uint16_t nBusyBit) { + /* FOR(Number of arbitrary iterations) */ + for (uint16_t i = 0u; i < 1000u; i++) { + /* IF(Busy bit is low) */ + if ((adi_tmr_registers[(eDevice)]->STAT & nBusyBit) == ((uint16_t) 0u)) { + return ADI_TMR_SUCCESS; + } /* ENDIF */ + } /* ENDFOR */ + return ADI_TMR_DEVICE_BUSY; +} + +static void CommonIntHandler(ADI_TMR_DEVICE const eDevice) { + /* Read status register */ + uint16_t IntStatus = adi_tmr_registers[eDevice]->STAT; + /* IF(Callback function has been set) */ + if(adi_tmr_callbacks[eDevice] != NULL) { + /* IF(Timeout interrupt occurred) */ + if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_TIMEOUT)) != ((uint16_t) 0u)) { + adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_TIMEOUT, NULL); + } /* ENDIF */ + /* IF(Event capture interrupt occurred) */ + if((IntStatus & ((uint16_t) BITM_TMR_RGB_STAT_CAPTURE)) != ((uint16_t) 0u)) { + adi_tmr_callbacks[eDevice](adi_tmr_parameters[eDevice], ADI_TMR_EVENT_CAPTURE, NULL); + } /* ENDIF */ + } /* ENDIF */ + /* Clear pending interrupt */ + adi_tmr_registers[eDevice]->CLRINT = (BITM_TMR_RGB_CLRINT_EVTCAPT | BITM_TMR_RGB_CLRINT_TIMEOUT); +} + +void GP_Tmr0_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP0); + ISR_EPILOG() +} + +void GP_Tmr1_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP1); + ISR_EPILOG() +} + +void GP_Tmr2_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_GP2); + ISR_EPILOG() +} + +void RGB_Tmr_Int_Handler(void) { + ISR_PROLOG() + CommonIntHandler(ADI_TMR_DEVICE_RGB); + ISR_EPILOG() +} + +/*! \endcond */ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c new file mode 100755 index 00000000000..31b2dbe8fc8 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c @@ -0,0 +1,154 @@ +/*! ***************************************************************************** + * @file adi_tmr_data.c + * @brief GP and RGB timer static configuration data + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + + +#ifndef ADI_TMR_DATA +#define ADI_TMR_DATA + +#include +#include +#include +#include + +/* CTL register static configuration */ +static uint16_t aTimerCtlConfig[] = +{ + (TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR0_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR0_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR1_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR1_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), + + (TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) | + (TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) | + (TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) | + (TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) | + (TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) | + (TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) | + (TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) | + (TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN), +}; + +/* LOAD register static configuration */ +static uint16_t aTimerLoadConfig[] = +{ + TMR0_CFG_LOAD_VALUE, + TMR1_CFG_LOAD_VALUE, + TMR2_CFG_LOAD_VALUE, + TMR3_CFG_LOAD_VALUE, +}; + +/* Asynchronous LOAD static configuraton */ +static uint16_t aTimerALoadConfig[] = +{ + TMR0_CFG_ASYNC_LOAD_VALUE, + TMR1_CFG_ASYNC_LOAD_VALUE, + TMR2_CFG_ASYNC_LOAD_VALUE, + TMR3_CFG_ASYNC_LOAD_VALUE, +}; + +/* EVENTSELECT static configuration */ +static uint16_t aTimerEventConfig[] = +{ + TMR0_CFG_EVENT_CAPTURE, + TMR1_CFG_EVENT_CAPTURE, + TMR2_CFG_EVENT_CAPTURE, + TMR3_CFG_EVENT_CAPTURE, +}; + +/* PWM CTL static configuration */ +static uint16_t aTimerPwmCtlConfig[] = +{ + (TMR0_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR0_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR1_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR1_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) | + (TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH), + + (TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) | + (TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH), + + (TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) | + (TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH), +}; + +/* PWM MATCH static configuration */ +static uint16_t aTimerPwmMatchConfig[] = { + TMR0_CFG_PWM0_MATCH_VALUE, + TMR1_CFG_PWM0_MATCH_VALUE, + TMR2_CFG_PWM0_MATCH_VALUE, + TMR3_CFG_PWM0_MATCH_VALUE, + TMR3_CFG_PWM1_MATCH_VALUE, + TMR3_CFG_PWM2_MATCH_VALUE +}; + + +#endif /* ADI_TMR_DATA */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c new file mode 100755 index 00000000000..d1f72d60482 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c @@ -0,0 +1,2779 @@ +/*! ***************************************************************************** + * @file: adi_uart.c + * @brief: uart device driver implementation + * @details: This file contains the UART device driver functions + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +/** @addtogroup UART_Driver + * @{ + * @brief UART Driver + * @note The application must include drivers/uart/adi_uart.h to use this + * driver + * @note This driver requires the DMA driver.The application must + * include the DMA driver sources to avoid link errors. + */ + +/*! \cond PRIVATE */ +#include +#include +#include "adi_uart_def.h" +#include + + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm50: (MISRA C 2004 rule 14.3): a null statement shall only occur on a line by itself, +* and shall not have any other text on the same line +* Some Macros, such as ISR_PROLOGUE, may not have any expansion +* resulting in just the terminating ';'. +* +* Pm073 (rule 14.7): A function should have a single point of exit. +* Pm143 (rule 14.7): A function should have a single point of exit at the end of the function. +* Multiple returns are used for error handling. +* +* Pm088 (rule 17.4): Pointer arithmetic should not be used. +* Relying on pointer arithmetic for buffer handling. +* +* Pm123 (rule 18.5): There shall be no definition of objects in a header file. +* +* Pm140 (rule 11.3): A cast should not be performed between a pointer type and an integral type. +* MMR addresses are defined as simple constants. Accessing the MMR requires casting to a pointer type. +* +* Pm152 (rule 17.4): Array indexing shall only be applied to objects defined as an array type. +* Relying on pointer arithmetic for buffer handling and +* Accessing the DMA descriptors, which are defined in the system as a pointer to an array of descriptors. +* +* Pm008: Code should not be commented out. + This code was commented out to show what the autobaud equations would look like if there were floating point precision. + Ideally this would be the case but for the sake of footprint size we will leave it at single point precision. +*/ +#pragma diag_suppress=Pm050,Pm073,Pm088,Pm123,Pm140,Pm143,Pm152,Pm008 +#endif /* __ICCARM__ */ + + + + +/********************************************************** + * UART Data + **********************************************************/ +static ADI_UART_DEVICE_INFO uart_device_info[ ] = +{ + { + UART0_TX_CHANn, /*!< DMA channel number for UART0 Tx. */ + UART0_RX_CHANn, /*!< DMA channel number for UART0 Rx. */ + DMA0_CH8_DONE_IRQn, /*!< DMA channel IRQ for UART0 Tx. */ + DMA0_CH9_DONE_IRQn, /*!< DMA channel IRQ for UART0 Rx. */ + (IRQn_Type)INTR_UART0_EVT, /*!< UART0 interrupt ID. */ + pADI_UART0, /*!< Start address of UART0. */ + NULL /*!< Device Handle for UART0. */ + }, + { + UART1_TX_CHANn, /*!< DMA channel number for UART1 Tx. */ + UART1_RX_CHANn, /*!< DMA channel number for UART1 Rx. */ + DMA0_CH25_DONE_IRQn, /*!< DMA channel IRQ for UART1 Tx. */ + DMA0_CH26_DONE_IRQn, /*!< DMA channel IRQ for UART1 Rx. */ + (IRQn_Type)INTR_UART1_EVT, /*!< UART1 interrupt ID. */ + pADI_UART1, /*!< Start address of UART1. */ + NULL /*!< Device Handle for UART1. */ + }, +}; + +static const ADI_UART_CONFIG gUARTCfg[ ] = +{ + { + /* Line control register. */ + ((ADI_UART0_CFG_WORD_LENGTH << BITP_UART_LCR_WLS) | + (ADI_UART0_CFG_STOP_BIT << BITP_UART_LCR_STOP) | + (ADI_UART0_CFG_ENABLE_PARITY << BITP_UART_LCR_PEN) | + (ADI_UART0_CFG_PARITY_SELECTION << BITP_UART_LCR_EPS) | + (ADI_UART0_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)), + + /* Div-C in baudrate divider register. */ + ADI_UART0_CFG_DIVC, + + /* Div-M and Div-N in fractional baudrate Register. */ + (((uint32_t)ADI_UART0_CFG_DIVN << BITP_UART_FBR_DIVN) | + ((uint32_t)ADI_UART0_CFG_DIVM << BITP_UART_FBR_DIVM) | + ((uint32_t)BITM_UART_FBR_FBEN)), + + /* Over sample rate in second line control register. */ + ADI_UART0_CFG_OSR, + + /* FIFO control register. */ + ((ADI_UART0_CFG_ENABLE_FIFO << BITP_UART_FCR_FIFOEN)| + (ADI_UART0_CFG_TRIG_LEVEL << BITP_UART_FCR_RFTRIG)), + + /* Half duplex control register. */ + ((ADI_UART0_CFG_SOUT_POLARITY << BITP_UART_RSC_OENP) | + (ADI_UART0_CFG_DEASSERTION << BITP_UART_RSC_OENSP) | + (ADI_UART0_CFG_DISABLE_RX << BITP_UART_RSC_DISRX) | + (ADI_UART0_CFG_HOLD_TX << BITP_UART_RSC_DISTX)), + + /* Interrupt enable register. */ + ((ADI_UART0_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) | + (ADI_UART0_CFG_ENABLE_RX_STATUS_INTERRUPT << BITP_UART_IEN_ELSI)) + + }, + + { + /* Line control register. */ + ((ADI_UART1_CFG_WORD_LENGTH << BITP_UART_LCR_WLS) | + (ADI_UART1_CFG_STOP_BIT << BITP_UART_LCR_STOP) | + (ADI_UART1_CFG_ENABLE_PARITY << BITP_UART_LCR_PEN) | + (ADI_UART1_CFG_PARITY_SELECTION << BITP_UART_LCR_EPS) | + (ADI_UART1_CFG_ENABLE_STICKY_PARITY << BITP_UART_LCR_SP)), + + /* Div-C in Baudrate divider register. */ + ADI_UART1_CFG_DIVC, + + /* Div-M and Div-N in fractional baudrate Register. */ + (((uint32_t)ADI_UART1_CFG_DIVN << BITP_UART_FBR_DIVN) | + ((uint32_t)ADI_UART1_CFG_DIVM << BITP_UART_FBR_DIVM) | + ((uint32_t)BITM_UART_FBR_FBEN)), + + /* Over sample rate in second line control register. */ + ADI_UART1_CFG_OSR, + + /* FIFO control register. */ + ((ADI_UART1_CFG_ENABLE_FIFO << BITP_UART_FCR_FIFOEN)| + (ADI_UART1_CFG_TRIG_LEVEL << BITP_UART_FCR_RFTRIG)), + + /* Half duplex control register. */ + ((ADI_UART1_CFG_SOUT_POLARITY << BITP_UART_RSC_OENP) | + (ADI_UART1_CFG_DEASSERTION << BITP_UART_RSC_OENSP) | + (ADI_UART1_CFG_DISABLE_RX << BITP_UART_RSC_DISRX) | + (ADI_UART1_CFG_HOLD_TX << BITP_UART_RSC_DISTX)), + + /* Interrupt enable register. */ + ((ADI_UART1_CFG_ENABLE_MODEM_STATUS_INTERRUPT << BITP_UART_IEN_EDSSI) | + (ADI_UART1_CFG_ENABLE_RX_STATUS_INTERRUPT << BITP_UART_IEN_ELSI)) + } +}; + +/*! \endcond */ + +/*! Number of UART devices available on the chip. */ +#define ADI_UART_NUM_DEVICES (sizeof(uart_device_info)/sizeof(ADI_UART_DEVICE_INFO)) + +/* Override "weak" default binding in startup.c */ +/*! \cond PRIVATE */ +extern void UART0_Int_Handler(void); +extern void UART1_Int_Handler(void); +extern void DMA_UART0_TX_Int_Handler(void); +extern void DMA_UART0_RX_Int_Handler(void); +extern void DMA_UART1_TX_Int_Handler(void); +extern void DMA_UART1_RX_Int_Handler(void); + +/* Internal DMA Callback for receiving DMA faults from common DMA error handler. */ +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); +static void RxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam; + ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelRx->pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_INVALID_DESCR; + break; + default: + nEvent |= (uint32_t)ADI_UART_HW_ERR_RX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + + if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true)) + { + hDevice->nHwError |= nEvent; + pNextBuff->bInUse = false; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); + + } + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +} + +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg); +static void TxDmaErrorCallback(void *pCBParam, uint32_t Event, void *pArg) { + + /* Recover the device handle. */ + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)pCBParam; + ADI_UART_BUFF_INFO * pNextBuff = hDevice->pChannelTx->pFillBuffer->pNextBuffer; + uint32_t nEvent = 0u; + + /* Save the DMA error. */ + switch (Event) { + case ADI_DMA_EVENT_ERR_BUS: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_BUS_FAULT; + break; + case ADI_DMA_EVENT_ERR_INVALID_DESCRIPTOR: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_INVALID_DESCR; + break; + default: + nEvent |= (uint32_t)ADI_UART_HW_ERR_TX_CHAN_DMA_UNKNOWN_ERROR; + break; + } + if((pNextBuff->pStartAddress != NULL) && (pNextBuff->bDMA == true)) + { + hDevice->nHwError |= nEvent; + pNextBuff->bInUse = false; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); + + } + + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +} +/*! \endcond */ + +/********************************************************** + * General UART APIs + **********************************************************/ + +/*! + * @brief Initialization function for the UART device. + * @details Opens the specified UART device. This function must be called before operating any UART device. + * + * + * @param [in] nDeviceNum UART device instance to be opened. + * @param [in] eDirection Direction of the UART operation. (i.e Rx or Tx) + * @param [in] pMemory Pointer to a 32 bit aligned buffer the size of #ADI_UART_UNIDIR_MEMORY_SIZE + * or #ADI_UART_BIDIR_MEMORY_SIZE. + * @param [in] nMemSize Size of the buffer to which "pMemory" points. This will vary based on + * direction of operation for this device instance. (i.e Rx and Tx, Rx, Tx) + * + * @param [out] phDevice The caller's device handle pointer for storing the initialized device instance data pointer. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully initialized UART device. + * - #ADI_UART_SEMAPHORE_FAILED Failed to create semaphore. + * - #ADI_UART_INVALID_DEVICE_NUM [D] Device instance is invalid. + * - #ADI_UART_INSUFFICIENT_MEMORY [D] Supplied memory is insufficient for the operation of specified UART device. + * - #ADI_UART_DEVICE_IN_USE [D] Device is already open. + * + * @sa adi_uart_Close() + * + * @note: Memory supplied by the API will be used by the driver for managing the UART device. This memory can be reused once + * device is closed. + * + */ +ADI_UART_RESULT adi_uart_Open( + uint32_t const nDeviceNum, + ADI_UART_DIRECTION const eDirection, + void *pMemory, + uint32_t const nMemSize, + ADI_UART_HANDLE *const phDevice + ) +{ +#ifdef ADI_DEBUG + /* Check if the given device number is within the range of UART + * devices present in the processor. There are two devices present here + * so this can be a 0 or 1. + */ + if(nDeviceNum >= ADI_UART_NUM_DEVICES) + { + return(ADI_UART_INVALID_DEVICE_NUM); + } + + /* Verify the device is not already open. */ + if(uart_device_info[nDeviceNum].hDevice != NULL) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure there is enough memory for the device instance to operate in a single direction. */ + if(eDirection != ADI_UART_DIR_BIDIRECTION) + { + if(nMemSize < (uint32_t)ADI_UART_UNIDIR_MEMORY_SIZE) + { + return(ADI_UART_INSUFFICIENT_MEMORY); + } + assert(nMemSize == (sizeof(ADI_UART_DEVICE) + sizeof(ADI_UART_DATA_CHANNEL))); + } + + /* Make sure there is enough memory for the device instance to operate in both directions. */ + else + { + if(nMemSize < (uint32_t)ADI_UART_BIDIR_MEMORY_SIZE) + { + return(ADI_UART_INSUFFICIENT_MEMORY); + } + assert(nMemSize == (sizeof(ADI_UART_DEVICE) + (sizeof(ADI_UART_DATA_CHANNEL)*2u))); + } +#endif /* ADI_DEBUG */ + + /* Initialize the device handle to NULL in case of a failure. */ + *phDevice = NULL; + + /* Link the ADI_UART_HANDLE to the ADI_UART_DEVICE structure. */ + ADI_UART_HANDLE hDevice = pMemory; + + /* Zero the device handle memory so we do not have to explicitely initialize + the structure members to 0. + */ + memset(pMemory, 0, nMemSize); + + + /* Set the device information. */ + hDevice->pUartInfo = &uart_device_info[nDeviceNum]; + + /* Set the base of the UART register address. We do this to minimize + the cycle count when accessing the UART registers. + */ + hDevice->pUARTRegs = uart_device_info[nDeviceNum].pUartRegs; + + /* Store the direction that this device will operate in. */ + hDevice->eDirection = eDirection; + + /* Increment the device handle with the size of the UART device structure + so we can set the channel data next without overwriting + the #ADI_UART_DEVICE data. + */ + pMemory = ((uint8_t *)pMemory +(sizeof(ADI_UART_DEVICE))); + + /* Set up the DMA Controller. */ + adi_dma_Init(); + + /* Initialize the TX-channel. */ + if(ADI_UART_DIR_RECEIVE != eDirection) + { + hDevice->pChannelTx = (ADI_UART_DATA_CHANNEL *)pMemory; + + /* Initialize the data transfer mode. */ + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + + /* Initialize Tx buffer pointers. */ + hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0]; + + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + SEM_CREATE(hDevice->pChannelTx, "UART_TX_SEM", ADI_UART_SEMAPHORE_FAILED); + + /* Set submit buffer function pointer. */ + hDevice->pChannelTx->pfSubmitBuffer = &uart_submittxbuffer; + + hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1]; + hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0]; + + /*Register DMA Callback. */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaTxChannelNum, TxDmaErrorCallback, (void*)hDevice)) + { + adi_uart_Close(hDevice); + return ADI_UART_ERR_DMA_REGISTER; + } + + /* Increment the device handle the size of #ADI_UART_DATA_CHANNEL + structure in case there is another channel to configure. + */ + pMemory = ((uint8_t *)pMemory + sizeof(ADI_UART_DATA_CHANNEL)); + } + /* Initialize the RX-channel. */ + if(ADI_UART_DIR_TRANSMIT != eDirection) + { + hDevice->pChannelRx = (ADI_UART_DATA_CHANNEL *)pMemory; + + /* Initialize the data transfer mode. */ + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + + /* Initialize Rx buffer pointers. */ + hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Create a "semaphore" (varies per OS) used for blocking buffer resource management. */ + SEM_CREATE(hDevice->pChannelRx, "UART_RX_SEM", ADI_UART_SEMAPHORE_FAILED); + + /* Set submit buffer function pointer. */ + hDevice->pChannelRx->pfSubmitBuffer = &uart_submitrxbuffer; + + hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1]; + hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0]; + + /*Register DMA Callback. */ + if (ADI_DMA_SUCCESS != adi_dma_RegisterCallback(hDevice->pUartInfo->dmaRxChannelNum, RxDmaErrorCallback, (void*)hDevice)) + { + adi_uart_Close(hDevice); + return ADI_UART_ERR_DMA_REGISTER; + } + } + + /* Initialize the device with the static config values.*/ + uart_init(hDevice, nDeviceNum); + + /* Write the device data pointer to the application's handle. */ + *phDevice = hDevice; + + /* Store the device handle. */ + uart_device_info[nDeviceNum].hDevice = hDevice; + + + /* Enable UART Interrupt. */ + NVIC_ClearPendingIRQ(hDevice->pUartInfo->eIRQn); + NVIC_EnableIRQ(hDevice->pUartInfo->eIRQn); + + /* Enable the interrupt for the DMA. */ + NVIC_EnableIRQ(hDevice->pUartInfo->eDMATx); + NVIC_EnableIRQ(hDevice->pUartInfo->eDMARx); + + /* Return SUCCESS */ + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Uninitialize the memory for the specified UART instance. + * + * @param [in] hDevice UART device handle whose operation is to be closed. This handle was obtained when the UART + * device instance was opened successfully. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully closed the UART device instance. + * - #ADI_UART_SEMAPHORE_FAILED Failed to delete the semaphore. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_DEVICE_IN_USE [D] Specified UART device is in the process of a transaction or autobaud has not completed. + * + * @details Closes the operation of specified UART device. Device needs to be opened again for any further use. + * + * @sa adi_uart_Open() + * + * @note: It is the user's responsibility to free/reuse the memory supplied during the opening of the device. + */ +ADI_UART_RESULT adi_uart_Close( + ADI_UART_HANDLE const hDevice + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel, autobaud is not in progress and the + Tx shift register is completely empty. This can be an issue if you submitted a nonblocking transmit + because you will receive interrupt before the hardware has fully finished the transaction. The start + address of the active buffer will remain in use until the buffer has been completely processed. + Therefore if the start address is NULL it means it has not been submitted for a transaction. + */ + if(((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) != BITM_UART_LSR_TEMT) || + ((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Disable UART status interrupts. */ + hDevice->pUARTRegs->IEN = 0x00U; + + /* Disable DMA UART interrupts. */ + NVIC_DisableIRQ(hDevice->pUartInfo->eDMARx); + NVIC_DisableIRQ(hDevice->pUartInfo->eDMATx); + + /* Disable UART event interrupt. */ + NVIC_DisableIRQ(hDevice->pUartInfo->eIRQn); + + /* Delete Tx-Channel semaphore. */ + if(hDevice->eDirection != ADI_UART_DIR_RECEIVE) + { + SEM_DELETE(hDevice->pChannelTx, ADI_UART_SEMAPHORE_FAILED); + } + + /* Delete Rx-Channel semaphore. */ + if(hDevice->eDirection != ADI_UART_DIR_TRANSMIT) + { + SEM_DELETE(hDevice->pChannelRx, ADI_UART_SEMAPHORE_FAILED); + } + + /* Free up the device memory. */ + hDevice->pUartInfo->hDevice = NULL; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Submit a "filled" buffer for transmitting data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * This function sets up the apropriate interrupts associated with the transaction and marks + * the buffer as submitted. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to data supplied by the API that is to be transmitted. + * @param [in] nBufSize Size of the buffer to be transmitted(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using the DMA flag. + + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for transmission. + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete + * a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_IsTxBufferAvailable() + * @sa adi_uart_GetTxBuffer() + * @sa adi_uart_SubmitRxBuffer() + * + * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode + * and then right away another using the DMA, this transaction will be denied. + * + */ +ADI_UART_RESULT adi_uart_SubmitTxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA + ) +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure we are transmitting. */ + if(ADI_UART_DIR_RECEIVE == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check the data transfer mode (only allowed in nonblocking mode). */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this transmit operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has finished being processed in "adi_uart_GetBuffer()" or "adi_uart_PendForBuffer()". + */ + if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the start address of the data buffer we are going to submit. */ + hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the buffer size to the size of the data buffer passed down from the API. */ + hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to zero because we will start shifting out + the Tx data from the first position of the buffer. + */ + hDevice->pChannelTx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use so no other transactions can use it until this one is complete. */ + hDevice->pChannelTx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer; + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. Then, if a buffer is not currently active, set up the + interrupts for this transaction. Otherwise if a buffer is currently active, + this will be taken care of in the ISR. + */ + if (hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE) + { + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING; + hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer); + } + + return(ADI_UART_SUCCESS); + } + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_SubmitTxBuffer(). It sets up the Tx channel DMA + or device interrupts for the Tx channel to transmit data. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from where data will be transmitted. + * @param [in] nBufSize Size of the buffer containing the data to be transmitted(in bytes). + * @param [in] bDMA Submit the buffer using the DMA. +*/ +static void uart_submittxbuffer( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ) +{ + /* If this transmission is using DMA... */ + if (pBuffer->bDMA) + { + /* Enable clear source address decrement for TX channel DMA. */ + pADI_DMA0->SRCADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaTxChannelNum; + + /* Enable Tx channel DMA. */ + pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Enable UART peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Set the primary control data structure as the current DMA descriptor. */ + pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaTxChannelNum; + + /* Fill in the DMA RAM descriptors */ + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMASRCEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u)); + + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMADSTEND = (uint32_t)&hDevice->pUARTRegs->TX; + + pPrimaryCCD[hDevice->pUartInfo->dmaTxChannelNum].DMACDC = ((uint32_t)ADI_DMA_INCR_NONE << DMA_BITP_CTL_DST_INC) | + ((uint32_t)ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE) | + (0u << DMA_BITP_CTL_R_POWER) | + ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + /* Enable UART DMA request interrupt for the Tx channel. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAT); + } + else + /* If this transmission is using UART interrupts.. */ + { + /* Enable buffer empty interrupts. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ETBEI); + } +} + +/*! \endcond */ + +/*! + * @brief Submit an empty buffer for receiving the data in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * This will set up the Rx channel for notification on incoming data using either the DMA + * or UART interrupts, as well as mark the buffer as submitted. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from that will be filled by the driver when data has been received. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using DMA flag. + + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for receiving data. + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete + * a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_IsRxBufferAvailable() + * @sa adi_uart_GetRxBuffer() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: Only one transfer mode (DMA vs. PIO) can be used at once. For example, if you submit a buffer in PIO mode + * and then right away another using the DMA, this transaction will be denied. +*/ +ADI_UART_RESULT adi_uart_SubmitRxBuffer( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA + ) +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure the UART device is configured to operate in the receive direction. */ + if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode(only allowed in nonblocking mode). */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this operation. pFreeBuffer + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. If the start address is not set to NULL, then we + can conclude the buffer has not finished being processed because this gets set in + adi_uart_pend_for_buffer() and adi_uart_get_buffer(). + */ + if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the start address of the buffer you are going to submit. */ + hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the size of the buffer. */ + hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to 0, because as we receive data it will be put into + the buffer starting at the first position. + */ + hDevice->pChannelRx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use. */ + hDevice->pChannelRx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer; + + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. Then, if a buffer is not currently active, set up the + interrupts for this transaction. Otherwise if a buffer is currently active, + this will be taken care of in the ISR. + */ + if (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONE) + { + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING; + hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer); + } + + return(ADI_UART_SUCCESS); +} + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_SubmitRxBuffer(). It sets up the DMA + * or device receive interrupts for the Rx channel to receive data. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to the empty receive buffer. + * @param [in] nBufSize Size of the receive buffer(in bytes). + * @param [in] bDMA Submit the buffer using the DMA. +*/ +static void uart_submitrxbuffer( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ) +{ + + + /* If this transaction is using the DMA.. */ + if (pBuffer->bDMA) + { + /* Enable source address decrement for RX DMA channel. */ + pADI_DMA0->DSTADDR_CLR = 1u << (uint32_t)hDevice->pUartInfo->dmaRxChannelNum; + + /* Enable Rx DMA channel. */ + pADI_DMA0->EN_SET = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Enable UART peripheral to generate DMA requests. */ + pADI_DMA0->RMSK_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Set the primary data structure as the current DMA descriptor. */ + pADI_DMA0->ALT_CLR = 1u << hDevice->pUartInfo->dmaRxChannelNum; + + /* Fill in the DMA RAM descriptors. */ + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMASRCEND = (uint32_t)&hDevice->pUARTRegs->RX; + + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMADSTEND = ((uint32_t)pBuffer->pStartAddress + (uint32_t)(pBuffer->nCount - 1u)); + + pPrimaryCCD[hDevice->pUartInfo->dmaRxChannelNum].DMACDC = (uint32_t)(ADI_DMA_INCR_1_BYTE << DMA_BITP_CTL_DST_INC) | + (uint32_t)(ADI_DMA_INCR_NONE << DMA_BITP_CTL_SRC_INC) | + (ADI_DMA_WIDTH_1_BYTE << DMA_BITP_CTL_SRC_SIZE) | + (0u << DMA_BITP_CTL_R_POWER) | + ((pBuffer->nCount - 1u) << DMA_BITP_CTL_N_MINUS_1) | + (DMA_ENUM_CTL_CYCLE_CTL_BASIC << DMA_BITP_CTL_CYCLE_CTL); + /* Enable UART receive DMA requests. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_EDMAR); + } + /* If this transaction is using UART interrupts.. */ + else + { + /* Enable buffer full interrupt. */ + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI); + } +} + +/*! \endcond */ + +/*! + * @brief Transfer buffer ownership from the device back to the API if the data + * transmit has completed. Otherwise it will block until completion. + * This allows a nonblocking call to become blocking. + * This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] ppBuffer Contains the address of the buffer passed down from the API + * for transmitting data. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully returned buffer to the API. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_BUFFER_NOT_SUBMITTED [D] The buffer has not been submitted to the driver. + * + * @sa adi_uart_IsTxBufferAvailable() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: If the transaction has already completed, this will return immediately rather than block. + */ +ADI_UART_RESULT adi_uart_GetTxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError + ) + +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate that this buffer has actually been submitted. */ + if(hDevice->pChannelTx->pActiveBuffer->pStartAddress == NULL) + { + return(ADI_UART_BUFFER_NOT_SUBMITTED); + } + + /* This function is allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Blocking call to get the submitted buffer */ + return(uart_getbuffer(hDevice, hDevice->pChannelTx, ppBuffer, pHwError)); +} + + + +/*! + * @brief Transfer buffer ownership from the device back to the API if the data + * receive has completed. Otherwise it will block until completion. + * This allows a nonblocking call to become blocking. + * This function is only called in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] ppBuffer Contains the address of the buffer passed down from the API + * for receiving data. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully returned buffer to the API. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_BUFFER_NOT_SUBMITTED [D] The buffer has not been submitted to the driver. + * + * @sa adi_uart_IsRxBufferAvailable() + * @sa adi_uart_SubmitRxBuffer() + * + * @note: If the transaction has already completed, this will return immediately rather than block. +*/ +ADI_UART_RESULT adi_uart_GetRxBuffer( + ADI_UART_HANDLE const hDevice, + void **const ppBuffer, + uint32_t *pHwError + ) + +{ + +#ifdef ADI_DEBUG + /* Validate the device handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate that this buffer has actually been submitted. */ + if(hDevice->pChannelRx->pActiveBuffer->pStartAddress == NULL) + { + return(ADI_UART_BUFFER_NOT_SUBMITTED); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Blocking call to get the full Rx Buffer */ + return(uart_getbuffer(hDevice, hDevice->pChannelRx, ppBuffer, pHwError)); +} + +/*! \cond PRIVATE */ + +/* + * @brief This is an internal helper function for adi_uart_GetRxBuffer() and adi_uart_GetTxBuffer(). + * It blocks until until the completion of the data transaction. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Pointer to UART channel data structure. + * @param [out] ppBuffer Contains the address of the buffer passed down from the API. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully got buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * +*/ +static ADI_UART_RESULT uart_getbuffer( + ADI_UART_HANDLE hDevice, + ADI_UART_DATA_CHANNEL *pChannel, + void **ppBuffer, + uint32_t *pHwError + ) +{ + /* Set ppBuffer to NULL in case there is an error. */ + *ppBuffer = NULL; + + /* Wait until the peripheral has finished processing the buffer. */ + SEM_PEND(pChannel,ADI_UART_FAILED); + + /* Save the address of the buffer that has just been processed, so it can be + returned back to the API. + */ + *ppBuffer = pChannel->pActiveBuffer->pStartAddress; + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + + /* If there are hardware errors and no callback, then return failure. */ + if(hDevice->nHwError != 0u) + { + /* Save the hardware error detected. This will be passed back to the API. */ + *pHwError = hDevice->nHwError; + + /* Clear any hardware errors detected. */ + hDevice->nHwError = 0u; + + return(ADI_UART_HW_ERROR_DETECTED); + } + else + { + return(ADI_UART_SUCCESS); + } +} + +/*! \endcond */ + + +/*! + * @brief Submit the buffer for transmitting the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * Call to this function will not return until the entire buffer is transmitted. + * Returns error if this function is called when device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. + * i.e Function "adi_uart_SubmitTxBuffer()" is called and the transfer is not yet complete. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to data supplied by the API that is to be transmitted. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using the DMA flag. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully transmitted the data from the submitted buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_RECEIVE, so we can not complete + * a transmit operation. The required directions are #ADI_UART_DIR_TRANSMIT or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_INVALID_POINTER [D] The pointer to the buffer being submitted is a NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_Read() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: This function is a blocking function which means that the function returns only after the completion of + * buffer transmission. +*/ +ADI_UART_RESULT adi_uart_Write( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure we are transmitting. */ + if(ADI_UART_DIR_RECEIVE == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode (only allowed in blocking mode). */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this transmit operation. "pFreeBuffer" + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address is set to NULL once the buffer + has been processed. + */ + if(hDevice->pChannelTx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. */ + hDevice->pChannelTx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING; + + /* Set the start address of the data buffer we are going to submit. */ + hDevice->pChannelTx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the buffer size to the size of the data buffer passed down from the API. */ + hDevice->pChannelTx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to zero because we will start shifting out + the Tx data from the first position of the buffer. + */ + hDevice->pChannelTx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use so no other transactions can use it until this one is complete. */ + hDevice->pChannelTx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelTx->pFreeBuffer->bDMA = bDMA; + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelTx->pFreeBuffer = hDevice->pChannelTx->pFreeBuffer->pNextBuffer; + + hDevice->pChannelTx->pfSubmitBuffer(hDevice, hDevice->pChannelTx->pFillBuffer); + + /* Block for the active buffer to complete. */ + return(uart_PendForBuffer(hDevice, hDevice->pChannelTx, pHwError)); +} + +/*! + * @brief Submit the buffer for reading the data in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. Call to this function will not + * return until the entire buffer is filled up. Returns error if this function is called when + * device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. i.e The function "adi_uart_SubmitRxBuffer()" is called + * when the transfer is not yet complete. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pBuffer Pointer to buffer from that will be filled by the driver when data has been received. + * @param [in] nBufSize Size of the buffer(in bytes). Must be smaller than 1024 bytes for DMA transfers. + * @param [in] bDMA Submit the buffer using DMA flag. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully submitted the buffer for receiving data. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * - #ADI_UART_FAILED [D] Generic failure. In this case the size of the data buffer we are trying + * to submit is NULL. + * - #ADI_UART_INVALID_DATA_TRANSFER_MODE [D] Device is operating in #ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING. This + * operation is only allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Device direction is set up as #ADI_UART_DIR_TRANSMIT, so we can not complete + * a receive operation. The required directions are #ADI_UART_DIR_RECEIVE or + * #ADI_UART_DIR_BIDIRECTION. + * - #ADI_UART_INVALID_POINTER [D] Pointer to the buffer being submitted is NULL. + * - #ADI_UART_DEVICE_IN_USE [D] Autobaud in progress. + * - #ADI_UART_INVALID_DATA_SIZE [D] DMA transfers must be smaller than 1025 bytes. + * + * @sa adi_uart_Write() + * @sa adi_uart_SubmitTxBuffer() + * + * @note: This function is a blocking function which means that the function returns only after the completion of + * data receive. +*/ +ADI_UART_RESULT adi_uart_Read( + ADI_UART_HANDLE const hDevice, + void *const pBuffer, + uint32_t const nBufSize, + bool const bDMA, + uint32_t *pHwError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate the pointer to the buffer memory. */ + if(pBuffer == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + + /* Validate the buffer size. */ + if(nBufSize == 0U ) + { + return(ADI_UART_FAILED); + } + + /* Autobaud in progress. */ + if(hDevice->bAutobaudInProgress == true) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Make sure the UART device is configured to operate in the receive direction. */ + if(ADI_UART_DIR_TRANSMIT == hDevice->eDirection) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Check for the data transfer mode(only allowed in blocking mode).*/ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING) + { + return(ADI_UART_INVALID_DATA_TRANSFER_MODE); + } + + /* Check that there is a free buffer to use for this receive operation. "pFreeBuffer" + is the next buffer available, so if it is in use we can make the assumption that + there are no buffers available. The start address gets set to NULL once the buffer + processing has completed. + */ + if(hDevice->pChannelRx->pFreeBuffer->pStartAddress != NULL) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } + + /* Make sure the DMA transfer size is not too large. */ + if((bDMA == true) && (nBufSize > DMA_TRANSFER_LIMIT)) + { + return(ADI_UART_INVALID_DATA_SIZE); + } + +#endif /* ADI_DEBUG */ + + /* Set the data transfer mode in case it was #ADI_UART_DATA_TRANSFER_MODE_NONE. + This will be set back to #ADI_UART_DATA_TRANSFER_MODE_NONE once this + transaction is complete. + */ + hDevice->pChannelRx->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_BLOCKING; + + /* Set the start address of the buffer you are going to submit. */ + hDevice->pChannelRx->pFreeBuffer->pStartAddress = pBuffer; + + /* Set the size of the buffer. */ + hDevice->pChannelRx->pFreeBuffer->nCount = nBufSize; + + /* Initialize the buffer index to 0, because as we receive data it will be put into + the buffer starting at the first position. + */ + hDevice->pChannelRx->pFreeBuffer->nIndex = 0U; + + /* Mark the buffer as in use. */ + hDevice->pChannelRx->pFreeBuffer->bInUse = true; + + /* Mark the DMA as in use. */ + hDevice->pChannelRx->pFreeBuffer->bDMA = bDMA; + + + /* Now that this "pFreeBuffer" is no longer free for use, update the + "pFreeBuffer" to the other PingPong buffer. Because there are only two + buffers in the PingPong structure, this will be the opposite of the one + we just submitted. "pFreeBuffer" will only be updated during the process of + submitting a buffer or a read/write operation. + */ + hDevice->pChannelRx->pFreeBuffer = hDevice->pChannelRx->pFreeBuffer->pNextBuffer; + + hDevice->pChannelRx->pfSubmitBuffer(hDevice, hDevice->pChannelRx->pFillBuffer); + + /* Block for the active buffer to complete. */ + return(uart_PendForBuffer(hDevice, hDevice->pChannelRx, pHwError)); +} + +/*! \cond PRIVATE */ + +/* + * @brief Pends for data transaction to complete. Buffer gets returned to API. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Pointer to UART channel data structure. + * @param [out] pBuffer Address of buffer on which data transfer being carried out. + * @param [out] pHwError Pointer to an integer that correlates with #ADI_UART_HW_ERRORS, containg the hardware status. + * If there is no hardware event, this will be 0. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully got buffer. + * - #ADI_UART_HW_ERROR_DETECTED Hardware error(s) detected. "pHwError" can be checked for the specific error code(s). + * +*/ +static ADI_UART_RESULT uart_PendForBuffer( + ADI_UART_HANDLE const hDevice, + ADI_UART_DATA_CHANNEL *pChannel, + uint32_t *pHwError + ) +{ + + /* Wait until the peripheral has finished processing the buffer. */ + SEM_PEND(pChannel,ADI_UART_FAILED); + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. This will only be updated in places where transactions are completed, + such as uart_PendForBuffer() and uart_GetBuffer(). + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + Only if there are no active buffers. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + + /* If there are hardware errors and no callback, then return failure. */ + if(hDevice->nHwError != 0u) + { + /* Save the hardware error detected. This will be passed back to the API. */ + *pHwError = hDevice->nHwError; + + /* Clear any hardware errors detected. */ + hDevice->nHwError = 0u; + + return(ADI_UART_HW_ERROR_DETECTED); + } + else + { + return(ADI_UART_SUCCESS); + } + +} +/*! \endcond */ + + +/*! + * @brief Peek function to know if an empty buffer is avilable. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbAvailable Pointer to a boolean variable. Contains "true" if there is an empty buffer + * and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains + * "false" if there is no empty buffer. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * + * @sa adi_uart_GetTxBuffer() + * @sa adi_uart_IsRxBufferAvailable + * + */ + +ADI_UART_RESULT adi_uart_IsTxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelTx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Initialize to "false" in case of an error. */ + *pbAvailable = false; + + /* Make sure the buffer has not already been processed. This would mean that there are + currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is + called once a transaction has completed. + */ + if (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL) + { + /* If the buffer has reached the interrupt handler, "bInUse" will be + updated so we know that the buffer has become available. + */ + if (hDevice->pChannelTx->pActiveBuffer->bInUse == false) + { + *pbAvailable = true; + } + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Peek function to know if a filled buffer is available. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbAvailable Pointer to a boolean variable. Contains "true" if there is an empty buffer + * and a call to "adi_uart_GetTxBuffer" is ensured to be successful. Contains + * "false" if there is no empty buffer. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of availability of the buffer. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_OPERATION_NOT_ALLOWED [D] Call to this function is not allowed in #ADI_UART_DATA_TRANSFER_MODE_BLOCKING. + * + * @sa adi_uart_GetRxBuffer() + * + */ +ADI_UART_RESULT adi_uart_IsRxBufferAvailable( + ADI_UART_HANDLE const hDevice, + bool *const pbAvailable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* This function is only allowed to be called when the channel is operating in NONBLOCKING mode. */ + if(hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_BLOCKING) + { + return(ADI_UART_OPERATION_NOT_ALLOWED); + } +#endif /* ADI_DEBUG */ + + /* Initialize to "false" in case of an error. */ + *pbAvailable = false; + + /* Make sure the buffer has not already been processed. This would mean that there are + currently no active buffers. This is only updated in adi_uart_GetBuffer(), which is + called once a transaction has completed. + */ + if(hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL) + { + /* If the buffer has reached the interrupt handler, "bInUse" will be + updated so we know that the buffer has become available. + */ + if (hDevice->pChannelRx->pActiveBuffer->bInUse == false) + { + *pbAvailable = true; + } + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Function to let the API know if all the data had been drained from the Tx shift registers. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pbComplete Pointer to a boolean variable. Contains "true" if there is no data left in the + * device to transmit and device can be disabled without data loss. Contains "false" + * if the data transmission is not complete. + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the status of data transmission. + * - #ADI_UART_INVALID_HANDLE [D] Specified handle is invalid. + * + * @note adi_uart_getTxBuffer() or the callback may indicate that a transmit transaction is complete when the + * device is using the DMA. This is because the interrupt will trigger once the transmit holding register is empty. + However, there may still be a some data in the shift register. If the transmit channel needs + * to be closed then the application must poll the transmit channel to see if all data has indeed been transmitted before + * shutting down the channel. Otherwise data will be lost. + * + */ + +ADI_UART_RESULT adi_uart_IsTxComplete( + ADI_UART_HANDLE const hDevice, + bool *const pbComplete + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Initialize to false. */ + *pbComplete = false; + + /* If the register is empty, set the return variable to "true". + This register is empty, when the value becomes a 1. + */ + if((hDevice->pUARTRegs->LSR & BITM_UART_LSR_TEMT) == BITM_UART_LSR_TEMT) + { + *pbComplete = true; + } + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Registering a callback function. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pfCallback Function pointer to callback. Passing a NULL pointer will unregister + * the callback function. + * @param [in] pCBParam Callback function parameter. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully registered callback function. + * - #ADI_UART_DEVICE_IN_USE [D] This operation is not allowed when a data transfer is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * + * +*/ +ADI_UART_RESULT adi_uart_RegisterCallback( + ADI_UART_HANDLE const hDevice, + const ADI_CALLBACK pfCallback, + void *const pCBParam + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Set the device callback. */ + hDevice->pfCallback = pfCallback; + + /* Set the callback parameter. */ + hDevice->pCBParam = pCBParam; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Configuration of UART data. + * + * @details Sets the configuration parameters for the specified UART device such as wordlength, whether to + * enable/disable the parity, and the number of stop bits. This function returns an error if the + * device has active data or autobaud is in progress. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] eParity Specify the type of parity check for the UART device. + * @param [in] eStopBits Specify the stop-bits for the UART device. + * @param [in] eWordLength Specify the word size of the data for the UART device. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the data configuration. + * - #ADI_UART_DEVICE_IN_USE [D] This operation is not allowed when a data transfer or autobaud is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * +*/ +ADI_UART_RESULT adi_uart_SetConfiguration( + ADI_UART_HANDLE const hDevice, + ADI_UART_PARITY const eParity, + ADI_UART_STOPBITS const eStopBits, + ADI_UART_WORDLEN const eWordLength + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL)) || + (hDevice->bAutobaudInProgress == true)) + { + return(ADI_UART_DEVICE_IN_USE); + } +#endif /* ADI_DEBUG */ + + /* Clear all the fields. */ + uint16_t nDataCfg = hDevice->pUARTRegs->LCR & (uint16_t)(~(BITM_UART_LCR_WLS |BITM_UART_LCR_STOP |BITM_UART_LCR_PEN)); + + /* Construct the configuration word. */ + nDataCfg |= (uint16_t)(((uint16_t)((uint16_t)eWordLength |(uint16_t)eStopBits) |(uint16_t)eParity)); + + /* Write to the register */ + hDevice->pUARTRegs->LCR = nDataCfg; + + /* Return Success */ + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Set baudrate by configuring the fractional dividors. + * + * @details Baudrate is calculated as per below equation. + * + * Baudrate = (UARTCLK / (nDivM + nDivN/2048)*pow(2,nOSR+2)* nDivC)). + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] nDivC Specify the "nDivC" in the above equation. + * @param [in] nDivM Specify the "nDivM" in the above equation. + * @param [in] nDivN Specify the "nDivN" in the above equation. + * @param [in] nOSR Specify the "nOSR" " in the above equation. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the baudrate for the device. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_DEVICE_IN_USE [D] Device is in use + * - #ADI_UART_INVALID_PARAMETER [D] Input for baud rate values are out of range. + * + * @sa adi_uart_GetBaudRate() + * @sa adi_uart_EnableAutobaud(); + * + * @note It is expected that initialization of the power management + * driver is done before calling this function. + * + */ +ADI_UART_RESULT adi_uart_ConfigBaudRate( + ADI_UART_HANDLE const hDevice, + uint16_t const nDivC, + uint8_t const nDivM, + uint16_t const nDivN, + uint8_t const nOSR + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL))) + { + return(ADI_UART_DEVICE_IN_USE); + } + + /* Check if the given baudrate is valid */ + if( (nDivM < 1u) || (nDivM > 3u)|| (nDivN > 2047u ) || (nOSR > 3u)) + { + return ADI_UART_INVALID_PARAMETER; + } + +#endif /* ADI_DEBUG */ + + /* Write back the register contents for baudrate detection in the hardware. */ + hDevice->pUARTRegs->DIV = nDivC; + hDevice->pUARTRegs->FBR = (uint16_t)((uint16_t)nDivN | (uint16_t)((uint16_t)nDivM <pUARTRegs->LCR2 = nOSR; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Get the baudrate of the UART device instance. This is used in the scenario when a callback has not been initialized. + * This allows the the API to know if autobaud is complete. If this returns a baudrate other than 0, + * it indicates that the autobaud completed, otherwise autobaud is still in progress. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [out] pnBaudRate Pointer to a location where baudrate is to be written. + * @param [out] pAutobaudError Pointer to an integer that will hold the value of any baudrate error(s), that correlates with + * #ADI_UART_AUTOBAUD_ERRORS. This will be 0 if there are no errors. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully retrieved the baudrate. + * - #ADI_UART_AUTOBAUD_ERROR_DETECTED There has been an autobaud error. The API can get the specific error(s) + * by checking "pAutobaudError". + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * - #ADI_UART_INVALID_POINTER [D] The pointer to baudrate or autobaud error is NULL. + + * +*/ +ADI_UART_RESULT adi_uart_GetBaudRate( + ADI_UART_HANDLE const hDevice, + uint32_t *pnBaudRate, + uint32_t *pAutobaudError + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Validate pointers. */ + if(pnBaudRate == NULL) + { + return(ADI_UART_INVALID_POINTER); + } + +#endif /* ADI_DEBUG */ + + /* If an error occured during autobaud this value will be set to a + non-zero value. The specific error can be found by checking against + #ADI_UART_EVENT. + */ + if(hDevice->nAutobaudError != 0u) + { + /* Save the autobaud error to pass back to the API.*/ + *pAutobaudError = hDevice->nAutobaudError; + + /* Clear the autobaud errors found. */ + hDevice->nAutobaudError = 0u; + + return(ADI_UART_AUTOBAUD_ERROR_DETECTED); + } + + /* Return the baudrate. If this is 0, then autobaud has not completed. */ + *pnBaudRate = hDevice->nBaudRate; + + return(ADI_UART_SUCCESS); +} + + +/*! + * @brief Enable/Disable UART autobaud detection as well as configures the device for autobaud detection. + * + * @details The baud rate is detected using the hardware support. + * After the baud rate is detected the interrupt handler is notified of the completion. + * When a callback is not registered with UART driver, the API adi_uart_GetBaudRate() + * can be used to know if autobaud is complete. Autobaud needs to be disabled in order to + * clear the internal counter and to close the device. + * + * @param [in] hDevice Handle to UART device whose autobaud detection to be enabled/disabled. + * @param [in] bEnable Boolean flag to indicate whether to enable or disable the autobaud. + * @param [in] bAutobaudCallbackMode Use a callback to report autobaud errors or type #ADI_UART_AUTOBAUD_ERRORS. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully enabled/disabled Autobaud detection. + * - #ADI_UART_DEVICE_IN_USE [D] Trying to enable/disable Autobaud when + * dataflow is enabled or autobaud is in progress. + * - #ADI_UART_INVALID_HANDLE [D] Invalid UART device handle. + * + * @sa adi_uart_GetBaudRate() + * + * @note: For autobaud we assume the key character being used is a carrige return (0xD), so the start edge count is + * hardcoded to the second edge (first edge after start edge) and the last edge count is set to the fouth edge. + * This will give us a total bit count of 8 bits that we will time in order to figure out the baud rate (bits/second). + */ +ADI_UART_RESULT adi_uart_EnableAutobaud( + ADI_UART_HANDLE const hDevice, + bool const bEnable, + bool const bAutobaudCallbackMode + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } + + /* Make sure there are no active buffers on any active channel and autobaud is not in progress. */ + if(((hDevice->eDirection != ADI_UART_DIR_TRANSMIT) && (hDevice->pChannelRx->pActiveBuffer->pStartAddress != NULL)) || + ((hDevice->eDirection != ADI_UART_DIR_RECEIVE ) && (hDevice->pChannelTx->pActiveBuffer->pStartAddress != NULL))) + { + return(ADI_UART_DEVICE_IN_USE); + } + +#endif /* ADI_DEBUG */ + + if(bEnable) + { + /* Enable Autobaud, timeout interrupt and done interrupt in the autobaud control register. + Set the starting edge trigger to the second edge. Set the ending edge count to + the fourth edge, for the carrige return key character (0xD). + */ + hDevice->pUARTRegs->ACR |=(BITM_UART_ACR_ABE | BITM_UART_ACR_DNIEN | BITM_UART_ACR_TOIEN |(1u << 4u) | (3u << 8u)); + + /* Initialize device baudrate to 0. This will be set once autobaud is complete. */ + hDevice->nBaudRate = 0u; + + /* Change the state to indicate autobaud is in progress. */ + hDevice->bAutobaudInProgress = true; + + /* Set the callback mode for autobaud based on the user input. */ + hDevice->bAutobaudCallbackMode = bAutobaudCallbackMode; + } + else + { + /* Change the state to indicate autobaud is not in progress. */ + hDevice->bAutobaudInProgress = false; + + /* Disable Autobaud, timeout interrupt and done interrupt in the autobaud control register. */ + hDevice->pUARTRegs->ACR |= (uint16_t)(~(uint32_t)BITM_UART_ACR_ABE | ~(uint32_t)BITM_UART_ACR_DNIEN | ~(uint32_t)BITM_UART_ACR_TOIEN); + + /* Initialize device baudrate to 0. */ + hDevice->nBaudRate = 0u; + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Forces the UART to send out a break signal. + * + * @details Sets the UART Tx pin to a logic-low/high (depending upon the + * Tx polarity) asynchronously. The UART keeps transmitting break + * until it is disabled to send the break. + * + * @param [in] hDevice Handle to the UART whose Tx is forced to + * send a break. + * @param [in] bEnable Flag which indicates whether to enable or + * disable transmitting the break. + * + * @return Status + * + * - #ADI_UART_SUCCESS If successfully enabled or disabled sending break. + * - #ADI_UART_INVALID_HANDLE [D] If the given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_ForceTxBreak( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(bEnable == true) + { + /* Set the force break bit. */ + hDevice->pUARTRegs->LCR |= BITM_UART_LCR_BRK; + } + else + { + /* Clear the force break bit. */ + hDevice->pUARTRegs->LCR &= (uint16_t)~(BITM_UART_LCR_BRK); + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Enable/Disable the loopback for the specified UART device. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] bEnable Boolean flag to indicate whether to enable or disable the loopback mode. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully enable/disable the loopback. + * - #ADI_UART_INVALID_HANDLE Invalid UART device handle. + * +*/ +ADI_UART_RESULT adi_uart_EnableLoopBack( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(true == bEnable) + { + /* Enable loopback. */ + hDevice->pUARTRegs->MCR |= (BITM_UART_MCR_LOOPBACK); + } + else + { + /* Disable loopback. */ + hDevice->pUARTRegs->MCR &= (uint16_t)~(BITM_UART_MCR_LOOPBACK); + } + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Sets the RX FIFO trigger level. This will be the amount of data in the FIFO + * that will trigger an interrupt. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] eTriglevel Trigger level to be set in terms of number of bytes. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully set the trigger level. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_SetRxFifoTriggerLevel( + ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_TRIG_LEVEL const eTriglevel + ) +{ +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Clear existing FIFO trigger level. */ + hDevice->pUARTRegs->FCR &= (uint16_t)~BITM_UART_FCR_RFTRIG; + + /* Set the FIFO trigger level. */ + hDevice->pUARTRegs->FCR |= (uint16_t)eTriglevel; + + return(ADI_UART_SUCCESS); +} +/*! + * @brief Enables internal FIFO as to work in 16550 mode. This helps to minimize system overhead + * and maximize system efficiency. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] bEnable Boolean flag to indicate whether to enable or disable FIFO. + * + * @return Status + * - #ADI_UART_SUCCESS If successfully enabled FIFO for UART device. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_EnableFifo( + ADI_UART_HANDLE const hDevice, + bool const bEnable + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + if(bEnable == true) + { + /* Enable TX/RX FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_FIFOEN; + hDevice->pUARTRegs->IEN |= (BITM_UART_IEN_ERBFI); + + hDevice->bRxFifoEn = true; + + } + else + { + /* Disable TX/RX FIFO. */ + hDevice->pUARTRegs->FCR &= (uint16_t)~(BITM_UART_FCR_FIFOEN); + + hDevice->bRxFifoEn = false; + } + + return ADI_UART_SUCCESS; +} + +/*! + * @brief To flush the TX FIFO. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed TX Fifo. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushTxFifo( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Flush the Tx FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Flush the RX FIFO. + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed RX Fifo. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushRxFifo( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Flush RX FIFO. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR; + + return ADI_UART_SUCCESS; +} + +/*! + * @brief Flush the Rx channel and disable interrupts. This will stop any buffers in flight and + * clear out any data that was in the RX holding register as well as the Rx fifo. Once this is done, + * in order to turn back on Rx interrupts, a new transaction will need to be started (adi_uart_Read() + * or adi_uart_SubmitRxBuffer()). + * + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed the Rx channel. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushRxChannel( + ADI_UART_CONST_HANDLE const hDevice + ) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Disable receive interrupts in PIO mode as well as DMA mode. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI | BITM_UART_IEN_EDMAR); + + /* Clear any data in the Rx Fifo. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_RFCLR; + + /* Reset the buffers to 0. */ + memset(hDevice->pChannelRx->PingPong,0, sizeof (hDevice->pChannelRx->PingPong)); + + hDevice->pChannelRx->PingPong[0].pNextBuffer = &hDevice->pChannelRx->PingPong[1]; + hDevice->pChannelRx->PingPong[1].pNextBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Reset the buffer pointers. */ + hDevice->pChannelRx->pActiveBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFreeBuffer = &hDevice->pChannelRx->PingPong[0]; + hDevice->pChannelRx->pFillBuffer = &hDevice->pChannelRx->PingPong[0]; + + /* Dummy read to flush the RX register. */ + hDevice->pUARTRegs->RX; + + return(ADI_UART_SUCCESS); +} + +/*! + * @brief Flush the Tx channel and disable interrupts.This will stop any buffers in flight and + * clear out any data that was in the TX holding register. Any data in the TX shift register + * will still finish transmitting. + * + * + * @param [in] hDevice Device handle to UART device obtained when an UART device is opened successfully. + * + * @return Status + * - #ADI_UART_SUCCESS Successfully flushed the Tx channel. + * - #ADI_UART_INVALID_HANDLE [D] The given UART handle is invalid. + */ +ADI_UART_RESULT adi_uart_FlushTxChannel(ADI_UART_CONST_HANDLE const hDevice) +{ + +#ifdef ADI_DEBUG + /* Validate the given handle. */ + if(ValidateHandle(hDevice) != ADI_UART_SUCCESS) + { + return(ADI_UART_INVALID_HANDLE); + } +#endif /* ADI_DEBUG */ + + /* Disable transmit interrupts in PIO mode as well as DMA mode. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT); + + /* Clear any data in the Rx Fifo. */ + hDevice->pUARTRegs->FCR |= BITM_UART_FCR_TFCLR; + + /* Reset the buffers to 0. */ + memset(hDevice->pChannelTx->PingPong,0, sizeof (hDevice->pChannelTx->PingPong)); + + hDevice->pChannelTx->PingPong[0].pNextBuffer = &hDevice->pChannelTx->PingPong[1]; + hDevice->pChannelTx->PingPong[1].pNextBuffer = &hDevice->pChannelTx->PingPong[0]; + + /* Reset the buffer pointers. */ + hDevice->pChannelTx->pActiveBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFreeBuffer = &hDevice->pChannelTx->PingPong[0]; + hDevice->pChannelTx->pFillBuffer = &hDevice->pChannelTx->PingPong[0]; + + return(ADI_UART_SUCCESS); +} + + +/*! \cond PRIVATE */ + +void UART0_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + Common_Uart_Interrupt_Handler(hDevice); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART); +#endif + ISR_EPILOG(); + return; +} + +void UART1_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + Common_Uart_Interrupt_Handler(hDevice); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_UART); +#endif + ISR_EPILOG(); + return; +} + +static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice) +{ + switch(hDevice->pUARTRegs->IIR & BITM_UART_IIR_STAT ) + { + /* Tx buffer empty interrupt. This means that the data has successfully left the holding register and is + now in transmit shift register or has completed its transfer. + */ + case ENUM_UART_IIR_STAT_ETBEI: + uart_TxDataHandler(hDevice); + break; + + /* Rx buffer FIFO timeout interrupt. This means that we have data in the RX FIFO + but there is not enough data to trigger an interrupt so we will process this data here. + */ + case ENUM_UART_IIR_STAT_RFTOI: + uart_RxDataHandler(hDevice); + break; + + /* Rx buffer full interrupt. This means that the RX buffer has finished receiving data. */ + case ENUM_UART_IIR_STAT_ERBFI: + uart_RxDataHandler(hDevice); + break; + + /* Line status interrupt. */ + case ENUM_UART_IIR_STAT_RLSI: + { + /* Initialze the line status event to 0. */ + uint32_t nEvent = 0u; + + /* Get the interrupts status. */ + uint16_t nStatus = hDevice->pUARTRegs->LSR; + + /* If a break signal is detected.. */ + if((BITM_UART_LSR_BI & nStatus) == BITM_UART_LSR_BI) + { + /* Dummy read to flush the RX register. We do this because + we do not actaully want to do anything with this data as it + is only a break indicator. */ + hDevice->pUARTRegs->RX; + + /* Set the event to a break interrupt. */ + nEvent = (uint32_t)ADI_UART_BREAK_INTERRUPT; + } + + /* Ignore the framing error if the break is asserted. + We do this because a break can trigger a false framing error. + */ + else if((BITM_UART_LSR_FE & nStatus) == BITM_UART_LSR_FE) + { + /* Set the event to show a framing error has been detected. */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_FRAMING; + } + else + { + /* Do nothing. This is required for MISRA. */ + } + + if((BITM_UART_LSR_PE & nStatus) == BITM_UART_LSR_PE) + { + /* Set the event to show a parity error has been detected. */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_PARITY; + } + if((BITM_UART_LSR_OE & nStatus) == BITM_UART_LSR_OE) + { + /* Set the event to show a hardware overrun error has been detected, meaning receive data has + been overwritten. + */ + nEvent |= (uint32_t)ADI_UART_HW_ERR_OVERRUN; + } + + /* If there was an event and autobaud is not in progress, notify the API. */ + if((nEvent != 0u) && (hDevice->bAutobaudInProgress == false)) + { + /* Set the UART device hw error bit field. This will allow us to return the + specific failure to the application once we return from this ISR. + */ + hDevice->nHwError |= nEvent; + uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_HW_ERROR_DETECTED); + } + break; + } + + /* If there was a modem status interrupt. For our purposes, we will only check if this is related to autobaud. */ + case ENUM_UART_IIR_STAT_EDSSI: + { +#if (ADI_UART_CFG_ENABLE_AUTOBAUD == 1) + /* Initialize the autobaud event to 0. */ + uint32_t nEvent = 0u; + + /* Get the autobaud interrupt status but not the counter value. */ + uint16_t nStatus = hDevice->pUARTRegs->ASRL & 0xFu; + + /* Read the autobaud control register to see if autobaud was enabled. */ + uint16_t acr = (hDevice->pUARTRegs->ACR & BITM_UART_ACR_ABE); + + /* If there is an autobaud event and autobaud is enabled */ + if((nStatus != 0u) && (acr != 0u)) + { + uint32_t nClock; + uint32_t nCount; + + /*Get the clock frequency. */ + if(adi_pwr_GetClockFrequency(ADI_CLOCK_PCLK,&nClock) != ADI_PWR_SUCCESS) + { + nClock = 0u; + } + + /* Get the autobaud counter bits 12-19. */ + nCount = (uint32_t)hDevice->pUARTRegs->ASRH << 12u; + + /* Get the autobaud counter bits 0-11. */ + nCount |= (uint32_t)hDevice->pUARTRegs->ASRL >> 4u; + + /* if the autobaud event was that the autobaud is done.. */ + if((nStatus & BITM_UART_ASRL_DONE) == BITM_UART_ASRL_DONE) + { + /* If the fractional baud generator is enabled, calculate the fractional portional of the baudrate. + It seems that in order to get a correct baudrate reading, we need the fractional divider enabled. + */ + if ((hDevice->pUARTRegs->FBR & 0x8000u) == 0x8000u) + { + uint8_t nOSR = 0u; + uint32_t nDivN; + uint32_t nDivNSubtractor = 2048u; + + /* DIVC is always 1, unless the oversample rate is 32. */ + uint16_t nDivC = 1u; + + /* If the oversample rate is 4.. */ + if(nCount < (8u << 3u)) + { + nDivN = ((nCount << 9u) / 8u) - nDivNSubtractor; + } + + /* If the oversample rate is 8.. */ + else if(nCount < (8u << 4u)) + { + nDivN = ((nCount << 8u) / 8u) - nDivNSubtractor; + nOSR = 1u; + } + + /* If the oversample rate is 16.. */ + else if(nCount < (8u << 5u)) + { + nDivN = ((nCount << 7u) / 8u) - nDivNSubtractor; + nOSR = 2u; + } + + /* If the oversample rate is 32.. */ + else + { + nDivC = (uint16_t) (nCount / 32u / 8u); + nDivN = ((nCount << 6u) / (8u * nDivC)) - nDivNSubtractor; + nOSR = 3u; + } + + /* Write back the register contents for baudrate detection in the hardware. */ + adi_uart_ConfigBaudRate(hDevice, nDivC, 1u, (uint16_t)nDivN, nOSR); + + /* For more precise calculations we would use floating point math here. Integer precision will do for now. + This avoids bringing in extra libraries for floating point math. */ + + /* Baudrate = (UARTCLK / (nDivM + nDivN / 2048) * pow(2, nOSR + 2) * nDivC) + nOSR = (1u << (nOSR + 2u)); Seperate this out of the equation for misra compliance + hDevice->nBaudRate = ((float)nClock / (((float)1 + (float)nDivN / (float)2048) * (float)nOSR * (float)nDivC)); + */ + + /* In order to avoid bringing in the extra floating point libraries, we will use the non fractional baudrate for the API. */ + hDevice->nBaudRate = ((nClock * 8u) / nCount); + } + else + { + /* No Fractional divider: Baudrate (bits/second) = (UARTCLK (cycles/second) * counted bits (bits)) / nCount (cycles)*/ + hDevice->nBaudRate = ((nClock * 8u) / nCount); + } + + /* If there is a callback, notify the API that autobaud is complete. + If there is not a callback, the baudrate will be set to a non zero value so the user can call "Get_BaudRate" + to know that autobaud has completed. + */ + if((hDevice->pfCallback != NULL) && (hDevice->bAutobaudCallbackMode == true)) + { + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_COMPLETE, (void*)hDevice->nBaudRate); + } + } + else + { + if((nStatus & BITM_UART_ASRL_BRKTO) == BITM_UART_ASRL_BRKTO) + { + /* Autobaud timed out due to break error. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_LONGBREAK; + } + if((nStatus & BITM_UART_ASRL_NSETO) == BITM_UART_ASRL_NSETO) + { + /* Autobaud timed out due to no valid start edge found. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_START_EDGE; + } + if((nStatus & BITM_UART_ASRL_NEETO) == BITM_UART_ASRL_NEETO) + { + /* Autobaud timed out due to no valid end edge found. */ + nEvent |= (uint32_t)ADI_UART_AUTOBAUD_TIMEOUT_NO_END_EDGE; + } + /* If there is an event callback.. */ + if((hDevice->pfCallback != NULL) && (hDevice->pChannelRx->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)) + { + /* Notify application of errors through callback. */ + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_AUTOBAUD_ERROR_DETECTED, (void*)nEvent); + } + else + { + /* Notify application of errors through autobaud return value. */ + hDevice->nAutobaudError = nEvent; + } + + } + + /* Dummy read to flush the RX register to clear the key character that was sent while configuring autobaud. */ + hDevice->pUARTRegs->RX; + } +#endif + /* Clear auto baud enable and interrupt registers. We disable autobaud here because it is required in order to clear the counter. */ + hDevice->pUARTRegs->ACR &=(uint16_t)~( BITM_UART_ACR_ABE | + BITM_UART_ACR_DNIEN | + BITM_UART_ACR_TOIEN ); + + hDevice->bAutobaudInProgress = false; + break; + } + default: + break; + } + return; +} + + +/* DMA interrupt handlers */ +void DMA_UART0_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX); +#endif + ISR_EPILOG(); +} + +void DMA_UART0_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[0].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX); +#endif + ISR_EPILOG(); +} + +void DMA_UART1_TX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_TX); +#endif + ISR_EPILOG(); +} + +void DMA_UART1_RX_Int_Handler(void) +{ + ISR_PROLOG(); + ADI_UART_HANDLE const hDevice = (ADI_UART_HANDLE)uart_device_info[1].hDevice; + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelRx,ADI_UART_EVENT_RX_BUFFER_PROCESSED); +#if defined(ADI_CYCLECOUNT_UART_ISR_ENABLED) && (ADI_CYCLECOUNT_UART_ISR_ENABLED == 1u) + ADI_CYCLECOUNT_STORE(ADI_CYCLECOUNT_ISR_DMA_UART_RX); +#endif + ISR_EPILOG(); +} + + +/* + * @brief UART interrupt handler for receiving the data in interrupt mode. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * +*/ +static void uart_RxDataHandler(ADI_UART_HANDLE hDevice) +{ + volatile uint8_t *pNextData; + + /* If there is an active buffer.. */ + if((hDevice->pChannelRx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == true)) + { + /* Get the address of the buffer we are filling. */ + pNextData = (uint8_t *)hDevice->pChannelRx->pFillBuffer->pStartAddress; + + /* Read data from the RX holding register into the buffer at the indexed location. */ + pNextData[hDevice->pChannelRx->pFillBuffer->nIndex] = (uint8_t) hDevice->pUARTRegs->RX; + + /* Increment the buffer index so we don't overwrite this data in the buffer. */ + hDevice->pChannelRx->pFillBuffer->nIndex++; + + /* If all of the data has been processed, manage the processed data buffer. Otherwise we will + leave everything as is and continue to receive interrupts for the incoming data, until this + buffer has been filled. + */ + if(hDevice->pChannelRx->pFillBuffer->nIndex == hDevice->pChannelRx->pFillBuffer->nCount) + { + uart_ManageProcessedBuffer(hDevice, hDevice->pChannelRx, ADI_UART_EVENT_RX_BUFFER_PROCESSED); + } + } + /* If we do not have a buffer submitted.. */ + else + { + /* Ask the API for a buffer so we can process this data before having an overflow. + if there is no callback, the API will not be able to submit a buffer in time. + */ + if (hDevice->pfCallback != NULL) + { + hDevice->pfCallback(hDevice->pCBParam, (uint32_t)ADI_UART_EVENT_NO_RX_BUFFER_EVENT, NULL); + } + + /* This check here is in case in the callback the application submitted a buffer. If they did + not then we need to clear the RX register in order to clear this interrupt. + */ + if((hDevice->pChannelRx->pFillBuffer->pStartAddress == NULL) && (hDevice->pChannelRx->pFillBuffer->bInUse == false)) + { + hDevice->pUARTRegs->RX; + } + } + + return; +} + +/* + * @brief UART interrupt handler transmitting the data in interrupt mode. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * +*/ +static void uart_TxDataHandler(ADI_UART_HANDLE hDevice) +{ + volatile uint8_t *pNextData; + + /* If there is an active buffer.. */ + if((hDevice->pChannelTx->pFillBuffer->pStartAddress != NULL) && (hDevice->pChannelTx->pFillBuffer->bInUse == true)) + { + /* Get the start address of the buffer we are transmitting data from. */ + pNextData = (uint8_t *)hDevice->pChannelTx->pFillBuffer->pStartAddress; + + /* Write data to the TX holding register. This will be shifted out at the baud rate by the shift register. */ + hDevice->pUARTRegs->TX = (uint16_t)pNextData[hDevice->pChannelTx->pFillBuffer->nIndex]; + + /* Increment the buffer index. */ + hDevice->pChannelTx->pFillBuffer->nIndex++; + + + /* If all of the characters have been transmitted, manage the data buffer. Otherwise we will leave everything + as is and continue to transmit this data until everything is out of the buffer. */ + if(hDevice->pChannelTx->pFillBuffer->nIndex >= hDevice->pChannelTx->pFillBuffer->nCount) + { + uart_ManageProcessedBuffer(hDevice,hDevice->pChannelTx,ADI_UART_EVENT_TX_BUFFER_PROCESSED); + } + } + return; +} + + +/* + * @brief Function for managing the processed buffer. This gets called after the receive buffer has been filled + * and when the transmit buffer has been emptied. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] pChannel Channel handler for the Tx or Rx. + * @param [in] eEvent Indicate the event ID to be passed to registered callback function, if one has been registered. + * +*/ + +static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice,ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent) +{ + + + /* Now that this transaction has completed, this buffer is no longer in use. */ + pChannel->pFillBuffer->bInUse = false; + + pChannel->pFillBuffer = pChannel->pFillBuffer->pNextBuffer; + + if(eEvent == ADI_UART_EVENT_TX_BUFFER_PROCESSED) + { + /* Disable Tx buffer interrupts. */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ETBEI | BITM_UART_IEN_EDMAT); + } + else + { + /* Disable Rx buffer interrupts for the DMA. We do not disable receive buffer full interrupts to allow + the use of the RX FIFO. + */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_EDMAR); + + if (hDevice->bRxFifoEn != true) + { + /* Disable Rx buffer interrupts for PIO mode if the FIFO is not enabled. + */ + hDevice->pUARTRegs->IEN &= (uint16_t)~(BITM_UART_IEN_ERBFI); + } + + } + + /* If there is a callback registered, notify the API that a buffer has been processed. Clean up the buffer. */ + if((hDevice->pfCallback != NULL) && (pChannel->eDataTranferMode == ADI_UART_DATA_TRANSFER_MODE_NONBLOCKING)) + { + uint32_t nEvent = hDevice->nHwError; + hDevice->nHwError = 0u; + + uint32_t *pBuffer = pChannel->pActiveBuffer->pStartAddress; + + /* Reinitialize the start address to NULL so this buffer can be used for a new transaction. */ + pChannel->pActiveBuffer->pStartAddress = NULL; + + /* Now that the desired data has either been transmitted or received, this buffer is no longer + in use. We can update "pActiveBuffer" to point to the next buffer that will become or is already + active. + */ + pChannel->pActiveBuffer = pChannel->pActiveBuffer->pNextBuffer; + + /* Set the data transfer mode to none so that the next transfer can be either in blocking or in nonblocking mode. + This will only be done if there are no other active buffers in flight to avoid disrupting an active transfer. + */ + if(pChannel->pActiveBuffer->pStartAddress == NULL) + { + pChannel->eDataTranferMode = ADI_UART_DATA_TRANSFER_MODE_NONE; + } + if(nEvent != 0u) + { + hDevice->pfCallback(hDevice->pCBParam, ADI_UART_EVENT_HW_ERROR_DETECTED,(void*)nEvent); + + } + else + { + hDevice->pfCallback(hDevice->pCBParam, (uint32_t)eEvent, (void*)pBuffer); + } + + } + else + { + /* Post to the blocking function. If we are in blocking mode, this will allow the buffer to be returned to the API. + If we are in nonblocking mode, this will allow adi_uart_GetBuffer() to return immediately so the API can have + control over the buffer again. + */ + SEM_POST(pChannel); + } + + /* If there is another buffer active. The buffer we want to check is "pFillBuffer" because that is the next one that would + be processed. So if it has been submitted, now would be the time to set up the interrupts based on its requirements. + */ + if(pChannel->pFillBuffer->bInUse == true) + { + pChannel->pfSubmitBuffer(hDevice, pChannel->pFillBuffer); + } +} + + +/* + * @brief Initialize the UART instance to the default values specified in "adi_uart_config.h". + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * @param [in] nDeviceNum UART device number +*/ + +static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum) +{ + + ADI_UART_CONFIG const* pUARTCfg = &gUARTCfg[nDeviceNum]; + + /* Line Control Register. */ + hDevice->pUARTRegs->LCR = pUARTCfg->LCR; + + /* Div-C in Baudrate divider register. */ + hDevice->pUARTRegs->DIV = pUARTCfg->DIV; + + /* Div-M and Div-N in Fractional Baudrate register. */ + hDevice->pUARTRegs->FBR = pUARTCfg->FBR; + + /* Second line control register. */ + hDevice->pUARTRegs->LCR2 = pUARTCfg->LCR2; + + /* FIFO control register. */ + hDevice->pUARTRegs->FCR = pUARTCfg->FCR; + + /* Half Duplex Control Register. */ + hDevice->pUARTRegs->RSC = pUARTCfg->RSC; + + /* Interrupt enable register. */ + hDevice->pUARTRegs->IEN = pUARTCfg->IEN; +} + +#ifdef ADI_DEBUG +/* + * @brief Validate the device handle. + * + * @param [in] hDevice Device handle obtained from adi_uart_Open(). + * + * @return Status + * - #ADI_UART_SUCCESS Specified handle is valid. + * - #ADI_UART_INVALID_HANDLE Specified handle is invalid. + * +*/ + +static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice) +{ + uint32_t i; + + + for(i = 0U; i < ADI_UART_NUM_DEVICES; i++) + { + + if((hDevice == uart_device_info[i].hDevice) && (hDevice != NULL)) + { + return(ADI_UART_SUCCESS); + } + } + return(ADI_UART_INVALID_HANDLE); +} +#endif /* ADI_DEBUG */ +/*! \endcond */ +/*@}*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h new file mode 100755 index 00000000000..0762d9d13ba --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart_def.h @@ -0,0 +1,214 @@ +/*! ***************************************************************************** + * @file: adi_uart_def.h + * @brief: UART Device Driver definition for processor + ----------------------------------------------------------------------------- +Copyright (c) 2010-2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +/*! \cond PRIVATE */ +#ifndef DEF_UART_DEF_H +#define DEF_UART_DEF_H + + +/*! + ***************************************************************************** + * \struct ADI_UART_BUFF_INFO + * Structure for managing the submitted buffers. + *****************************************************************************/ + +typedef struct UART_BUFF_INFO +{ + void *pStartAddress; /*!< Address of buffer passed down to the UART driver. */ + uint32_t nCount; /*!< Size of buffer in bytes. */ + uint32_t nIndex; /*!< Buffer index. */ + bool bInUse; /*!< Buffer in use flag. */ + bool bDMA; /*!< Transaction is using the DMA flag. */ + struct UART_BUFF_INFO *pNextBuffer; /*!< Pointer to the next buffer in the list. */ + + +}ADI_UART_BUFF_INFO; + + +/*! Function pointer typedef for the function which submit the buffer */ +typedef void (*UART_BUFFER_SUBMIT) (ADI_UART_CONST_HANDLE const hDevice, + ADI_UART_BUFF_INFO *const pBuffer + ); + + +/*! + ***************************************************************************** + * \struct ADI_UART_DATA_CHANNEL + * Structure to manage the data transfer for a given channel. + * One instance of this structure will be created for managing the + * data transfer in each direction. + *****************************************************************************/ + +typedef struct _ADI_UART_DATA_CHANNEL +{ + ADI_UART_BUFF_INFO PingPong[2]; /*!< Ping Pong Buffers. */ + ADI_UART_BUFF_INFO *pFreeBuffer; /*!< Pointer to free buffer (next buffer to submit). */ + ADI_UART_BUFF_INFO *pFillBuffer; /*!< Pointer to the next buffer to be filled. This is needed for + the case where two buffers are "submitted" before a "get" is + called. */ + ADI_UART_BUFF_INFO *pActiveBuffer; /*!< Pointer to active buffer (next buffer waiting for completion).*/ + ADI_UART_TRANSFER_MODE eDataTranferMode; /*!< Data transfer mode. */ + UART_BUFFER_SUBMIT pfSubmitBuffer; /*!< Pointer to a function used for submitting a buffer. */ + SEM_VAR_DECLR + +}ADI_UART_DATA_CHANNEL; + + +/*! + ***************************************************************************** + * \struct ADI_UART_DEVICE_INFO + * Structure for storing basic device information. + *****************************************************************************/ + +typedef struct _ADI_UART_DEVICE_INFO +{ + DMA_CHANn_TypeDef dmaTxChannelNum; /*!< DMA channel ID-Tx. */ + DMA_CHANn_TypeDef dmaRxChannelNum; /*!< DMA channel ID-Rx. */ + IRQn_Type eDMATx; /*!< DMA channel IRQ-Tx. */ + IRQn_Type eDMARx; /*!< DMA channel IRQ-Rx. */ + IRQn_Type eIRQn; /*!< UART interrupt ID. */ + ADI_UART_TypeDef *pUartRegs; /*!< Base address of the UART registers. */ + ADI_UART_HANDLE hDevice; /*!< Handle for the device instance. */ + +}ADI_UART_DEVICE_INFO; + + +/*! + ***************************************************************************** + * \struct ADI_UART_DEVICE + * Structure for managing the UART device. + *****************************************************************************/ + +typedef struct _ADI_UART_DEVICE +{ + ADI_UART_DIRECTION eDirection; /*!< UART operation direction. */ + ADI_UART_DEVICE_INFO *pUartInfo; /*!< Access to device information about the uart instance. */ + volatile ADI_UART_TypeDef *pUARTRegs; /*!< Access to UART Memory Mapped Registers. */ + ADI_CALLBACK pfCallback; /*!< Callback function. */ + void *pCBParam; /*!< Parameter for callback function. */ + bool bAutobaudInProgress; /*!< Autobaud in progress flag. */ + volatile uint32_t nHwError; /*!< Line status error(s). */ + volatile uint32_t nAutobaudError; /*!< Autobaud error(s). */ + ADI_UART_DATA_CHANNEL *pChannelTx; /*!< Tx channel. */ + ADI_UART_DATA_CHANNEL *pChannelRx; /*!< Rx channel. */ + volatile uint32_t nBaudRate; /*!< Baudrate. */ + bool bAutobaudCallbackMode;/*!< Autobaud detection is using callback mode flag. */ + bool bRxFifoEn; /*!< Rx FIFO enabled. Rx buffer full interrupts will remain enabled. */ + +} ADI_UART_DEVICE; + + +/*! + ***************************************************************************** + * \struct ADI_UART_CONFIG + * Structure for initializing the static config. + *****************************************************************************/ + +typedef struct _ADI_UART_CONFIG +{ + uint16_t LCR; /*!< UART_COMLCR Register. */ + + uint16_t DIV; /*!< UART_COMDIV Register. */ + + uint16_t FBR; /*!< UART_COMFBR Register. */ + + uint16_t LCR2; /*!< UART_COMLCR2 Register.*/ + + uint16_t FCR; /*!< UART_COMFCR Register. */ + + uint16_t RSC; /*!< UART_COMRSC Register. */ + + uint16_t IEN; /*!< UART_COMIEN Register .*/ + +} ADI_UART_CONFIG; + + +/****************************************************************************** + * UART Device internal API function prototypes + *****************************************************************************/ + +/* + * UART device initialization helper function. +*/ +static void uart_init(ADI_UART_CONST_HANDLE const hDevice, uint32_t const nDeviceNum); + + +/* + * Data transfer helper functions. +*/ +static void uart_submittxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer); + +static void uart_submitrxbuffer(ADI_UART_CONST_HANDLE const hDevice, ADI_UART_BUFF_INFO *const pBuffer); + + +/* + * Data management helper functions. +*/ +static ADI_UART_RESULT uart_getbuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, void **ppBuffer, uint32_t *pHwError); + +static ADI_UART_RESULT uart_PendForBuffer(ADI_UART_HANDLE const hDevice , ADI_UART_DATA_CHANNEL *pChannel, uint32_t *pHwError); + +static void uart_ManageProcessedBuffer(ADI_UART_HANDLE hDevice, ADI_UART_DATA_CHANNEL *pChannel, ADI_UART_EVENT eEvent); + +static void uart_TxDataHandler(ADI_UART_HANDLE hDevice); + +static void uart_RxDataHandler(ADI_UART_HANDLE hDevice); + + +/* + * Interrupt Handler. +*/ +static void Common_Uart_Interrupt_Handler(ADI_UART_HANDLE hDevice); + + +/* + * Handle Validation function +*/ +#ifdef ADI_DEBUG +static ADI_UART_RESULT ValidateHandle(ADI_UART_CONST_HANDLE hDevice); +#endif /* ADI_DEBUG */ + +#endif /* end of ifndef DEF_UART_DEF_H */ +/*! \endcond */ + + diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c new file mode 100755 index 00000000000..b2f34894a25 --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/wdt/adi_wdt.c @@ -0,0 +1,225 @@ +/*! ***************************************************************************** + * @file adi_wdt.c + * @brief WDT device driver implementation + ----------------------------------------------------------------------------- +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* +* Pm011 (rule 6.3): the basic types of char, int, short, long, float, and double should not be used +* Necessary for stdbool. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* +* Pm140 (Rule 11.4): a cast should not be performed between a pointer type and an integral type +* This violation appears when deferencing the pointer to the register typedef. No way around this. +*/ +#pragma diag_suppress=Pm011,Pm073,Pm140,Pm143 +#endif /* __ICCARM__ */ + + +/** @addtogroup WDT_Driver WDT Driver + * @{ + * @brief Watchdog Timer (WDT) Driver + * @details The watchdog timer driver allows the user to enable the timer with + * the static configuration parameters, reset the timer, and read the timer + * count. No interface is provided for setting the timer parameters are + * runtime since the WDT may only be configured once for the program lifetime. + * The timer is disabled by default by the ADuCM4x50 boot kernel. + * @note The application must include drivers/wdt/adi_wdt.h to use this driver + */ + +#include +#include +#include +#include +#include + +/*! \cond PRIVATE */ + +/*! Bus synchronization bits that must go low before writing to the CTL or RESET registers */ +#define ADI_WDT_SYNC_BITS ((0x1u << BITP_WDT_STAT_COUNTING) | (0x1u << BITP_WDT_STAT_LOADING) | (0x1u << BITP_WDT_STAT_CLRIRQ)) + +/*! Value that is written to the reset register to kick the dog */ +#define ADI_WDT_CLR_VALUE (0xCCCCu) + +/*! Store the callback locally if we are using interrupt mode */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) +static ADI_CALLBACK gAppCallback; +#endif + +/*! \endcond */ + +/********************************************************************************* + API IMPLEMENTATIONS +*********************************************************************************/ + + +/*! + * @brief WDT Enable + * + * @details Enables/disables the WDT with the paramters supplied in adi_wdt_config.h + * + * @param [in] bEnable : True to turn WDT on, false to turn it off + * + * @param [in] pfCallback : If interrupt mode is enabled, specify application callback function, + * otherwise simply pass NULL for the argument. + * + * @return ADI_WDT_RESULT + * - #ADI_WDT_FAILURE_LOCKED WDT has already been initialized + * - #ADI_WDT_SUCCESS Function call completed successfully + */ +ADI_WDT_RESULT adi_wdt_Enable(bool const bEnable, ADI_CALLBACK const pfCallback) { + /* IF(Device is enabled, application can't modify it) */ + if ((pADI_WDT0->STAT & ((uint16_t) BITM_WDT_STAT_LOCKED)) != ((uint16_t) 0x0u)) { + return ADI_WDT_FAILURE_LOCKED; + } /* ENDIF */ + + /* Setup interrupts if we are in interrupt mode */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) + gAppCallback = pfCallback; + /* IF(We are enabling the WDT) */ + if (bEnable == true) { + NVIC_EnableIRQ (WDT_EXP_IRQn); + /* ELSE (We are disabling the WDT, this might not be necessary, depends on startup config) */ + } else { + NVIC_DisableIRQ(WDT_EXP_IRQn); + } /* ENDIF */ +#endif + + /* WHILE(Bus sync is underway) */ + while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) { + ; + } /* ENDWHILE */ + + + ADI_INT_STATUS_ALLOC(); + ADI_ENTER_CRITICAL_REGION(); + + pADI_WDT0->LOAD = ADI_WDT_LOAD_VALUE; + + /* IF(Turning the WDT on) */ + if (bEnable == true) { + pADI_WDT0->CTL = (ADI_WDT_CONTROL_TIMER_MODE << BITP_WDT_CTL_MODE) | + (0x1u << BITP_WDT_CTL_EN ) | + (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) | + (ADI_WDT_CONTROL_TIMEOUT_MODE << BITP_WDT_CTL_IRQ ) | + (ADI_WDT_CONTROL_POWER_MODE << 0u ); + /* ELSE(Turning the WDT off) */ + } else { + pADI_WDT0->CTL = (ADI_WDT_CONTROL_TIMER_MODE << BITP_WDT_CTL_MODE) | + (0x0u << BITP_WDT_CTL_EN ) | + (ADI_WDT_CONTROL_CLOCK_PRESCALER << BITP_WDT_CTL_PRE ) | + (ADI_WDT_CONTROL_TIMEOUT_MODE << BITP_WDT_CTL_IRQ ) | + (ADI_WDT_CONTROL_POWER_MODE << 0u ); + } /* ENDIF */ + + ADI_EXIT_CRITICAL_REGION(); + + return ADI_WDT_SUCCESS; +} + +/*! + * @brief WDT Reset + * + * @details Resets the WDT + * + * @return None + */ +void adi_wdt_Kick(void) { + /* WHILE(Bus sync is underway) */ + while((pADI_WDT0->STAT & ADI_WDT_SYNC_BITS) != 0u) { + ; + } /* ENDWHILE */ + + /* Kick the dog! */ + pADI_WDT0->RESTART = ADI_WDT_CLR_VALUE; +} + +/*! + * @brief WDT Read Count + * + * @details Read the current WDT count + * + * @param [out] pCurCount : Pointer to memory to read the count into + * + * @return None + */ +void adi_wdt_GetCount(uint16_t * const pCurCount) { + /* Read the count */ + *pCurCount = pADI_WDT0->CCNT; +} + +/*! \cond PRIVATE */ + +/*! + * @brief WDT0 Interrupt Handler + * + * @details Kicks the dog and calls the user supplied callback function + * + * @return None + * + * @note Do not need to explicitly clear the interrupt status, + * kicking the dog performs this action. + */ +#if (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) +extern void WDog_Tmr_Int_Handler(void); +void WDog_Tmr_Int_Handler(void) { + ISR_PROLOG() + /* Kick the dog */ + adi_wdt_Kick(); + /* IF(Application supplied a callback) */ + if(gAppCallback != NULL) { + /* Call the callback */ + gAppCallback(NULL, 0x0u, NULL); + } /* ENDIF */ + ISR_EPILOG() +} +#endif /* (ADI_WDT_CONTROL_TIMEOUT_MODE == 1u) */ + +/*! \endcond */ + +/*! @} */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c new file mode 100755 index 00000000000..53e763cb70b --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint.c @@ -0,0 +1,413 @@ +/****************************************************************************** + @file: adi_xint.c + @brief: External Interrupt device driver implementation. + ----------------------------------------------------------------------------- + +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ +/*****************************************************************************/ + +#include +#include +#include +#include +#include +#include "adi_xint_def.h" + +#ifdef __ICCARM__ +/* +* IAR MISRA C 2004 error suppressions. +* +* Pm073 (rule 14.7): a function should have a single point of exit +* Pm143 (rule 14.7): a function should have a single point of exit at the end of the function +* Multiple returns are used for error handling. +* Pm140 (rule 11.3): a cast should not be performed between a pointer type and an integral type +* The rule makes an exception for memory-mapped register accesses. +* Pm140 (rule 10.3): illegal explicit conversion from underlying MISRA type unsigned int to enum +* The typecast is used for efficiency of the code. +* Pm140 (rule 17.4): array indexing shall only be applied to objects defined as an array +* Array indexing is required on the pointer. The memory for gpCallbackTable is passed from application +*/ +#pragma diag_suppress=Pm073,Pm143,Pm140,Pm136,Pm152 +#endif /* __ICCARM__ */ + +static inline void XIntCommonInterruptHandler (const ADI_XINT_EVENT eEvent); +void Ext_Int0_Handler(void); +void Ext_Int1_Handler(void); +void Ext_Int2_Handler(void); +void Ext_Int3_Handler(void); + + + +/*========== D A T A ==========*/ + +static ADI_XINT_CALLBACK_INFO *gpCallbackTable; + +/*! \endcond */ + +/*! \addtogroup XINT_Driver External Interrupt Driver + * @{ + * @brief External Interrupt (XINT) Driver + * @note The application must include drivers/xint/adi_xint.h to use this driver + */ + +/*! + @brief Initializes the External Interrupt Driver. + + @details This function does the external interrupt driver initialization. This function should be called + before calling any of the XINT driver APIs. + + @param[in] pMemory Pointer to the memory to be used by the driver. + Size of the memory should be at equal to #ADI_XINT_MEMORY_SIZE bytes. + @param[in] MemorySize Size of the memory passed in pMemory parameter. + + @return Status + - ADI_XINT_SUCCESS If successfully initialized XINT driver. + - ADI_XINT_NULL_PARAMETER [D] If the given pointer to the driver memory is pointing to NULL. + - ADI_XINT_INVALID_MEMORY_SIZE [D] If the given memory size is not sufficient to operate the driver. + + @sa adi_xint_UnInit +*/ +ADI_XINT_RESULT adi_xint_Init(void* const pMemory, + uint32_t const MemorySize +) +{ + +#ifdef ADI_DEBUG + /* Verify the given memory pointer */ + if(NULL == pMemory) + { + return ADI_XINT_NULL_PARAMETER; + } + /* Check if the memory size is sufficient to operate the driver */ + if(MemorySize < ADI_XINT_MEMORY_SIZE) + { + return ADI_XINT_INVALID_MEMORY_SIZE; + } + assert(MemorySize == (sizeof(ADI_XINT_CALLBACK_INFO) * ADI_XINT_EVENT_MAX)); +#endif + + /* Only initialize on 1st init call, i.e., preserve callbacks on multiple inits */ + if (gpCallbackTable == NULL) + { + /* Clear the memory passed by the application */ + memset(pMemory, 0, MemorySize); + + gpCallbackTable = (ADI_XINT_CALLBACK_INFO *)pMemory; + } + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Un-initialize the external interrupt driver. + + @details Terminates the XINT functions, leaving everything unchanged. + + @return Status + - #ADI_XINT_SUCCESS If successfully uninitialized XINT driver. + - #ADI_XINT_NOT_INITIALIZED [D] If XINT driver not yet initialized. + + @sa adi_xint_Init +*/ +ADI_XINT_RESULT adi_xint_UnInit(void) +{ + +#ifdef ADI_DEBUG + /* IF (not initialized) */ + if (NULL == gpCallbackTable) + { + /* return error if not initialized */ + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* Clear the callback pointer */ + gpCallbackTable = NULL; + + return (ADI_XINT_SUCCESS); +} + + + +/*! + @brief Enable an External Interrupt + + @details Enables and sets the triggering mode for the given external interrupt. + Applications may register a callback using the #adi_xint_RegisterCallback + API to get a notification when the interrupt occurs. + + To get the external interrupt working application has to enable the input + (using the GPIO driver API \a adi_gpio_InputEnable) for the corresponding GPIO + pin. Please refer the GPIO chapter pin-muxing section of the Hardware Reference + Manual to see the GPIO pin that is mapped to the required external interrupt. + + @param[in] eEvent Event which needs to be enabled. + @param[in] eMode Interrupt trigger mode for the external interrupt. + + @return Status + - #ADI_XINT_SUCCESS If successfully enabled the external interrupt. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver not yet initialized. + + @sa adi_xint_DisableIRQ + @sa adi_xint_RegisterCallback +*/ +ADI_XINT_RESULT adi_xint_EnableIRQ(const ADI_XINT_EVENT eEvent, const ADI_XINT_IRQ_MODE eMode) +{ + uint32_t Mask; /* mask to manipulate the register */ + uint32_t Pattern; /* bit pattern that will be written into the register */ + uint32_t CfgReg; /* interrupt config register value */ + IRQn_Type XintIrq; + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* create the mask we'll use to clear the relevant bits in the config register */ + Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + /* The Pattern has to be created differently for UART RX wakeup and other events as the + mode and enable bits are flipped in case of UART RX */ + + /* Based on the event figure out the interrupt it is mapped to */ + if(eEvent == ADI_XINT_EVENT_UART_RX) + { + /* create the bit pattern we're going to write into the configuration register */ + Pattern = (BITM_XINT_CFG0_UART_RX_EN | ((uint32_t)eMode << BITP_XINT_CFG0_UART_RX_MDE)); + + XintIrq = XINT_EVT3_IRQn; + } + else + { + /* create the bit pattern we're going to write into the configuration register */ + Pattern = (BITM_XINT_CFG0_IRQ0EN | eMode) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent); + } + + + ADI_ENTER_CRITICAL_REGION(); + + /* read/modify/write the appropriate bits in the register */ + CfgReg = pADI_XINT0->CFG0; + CfgReg &= ~Mask; + CfgReg |= Pattern; + pADI_XINT0->CFG0 = CfgReg; + + ADI_EXIT_CRITICAL_REGION(); + + /* enable the interrupt */ + NVIC_EnableIRQ(XintIrq); + + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Disable an External Interrupt + + @details Disables an external interrupt + + @param[in] eEvent External Interrupt event that should be disabled. + + @return Status + - #ADI_XINT_SUCCESS If successfully disabled the external interrupt. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized. + + @sa adi_xint_EnableIRQ + @sa adi_xint_RegisterCallback +*/ +ADI_XINT_RESULT adi_xint_DisableIRQ(const ADI_XINT_EVENT eEvent) +{ + uint32_t Mask; /* mask to manipulate the register */ + uint32_t CfgReg; /* interrupt config register value */ + IRQn_Type XintIrq; /* External interrupt IRQ the event is mapped to */ + + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + /* Based on the event figure out the interrupt it is mapped to */ + if(eEvent == ADI_XINT_EVENT_UART_RX) + { + XintIrq = XINT_EVT3_IRQn; + } + else + { + XintIrq = (IRQn_Type)((uint32_t)XINT_EVT0_IRQn + (uint32_t)eEvent); + } + + /* disable the interrupt */ + NVIC_DisableIRQ(XintIrq); + + /* create the mask we'll use to clear the relevant bits in the config register */ + Mask = (BITM_XINT_CFG0_IRQ0MDE | BITM_XINT_CFG0_IRQ0EN) << (ADI_XINT_CFG_BITS * (uint32_t)eEvent); + + ADI_ENTER_CRITICAL_REGION(); + /* read/modify/write the appropriate bits in the register */ + CfgReg = pADI_XINT0->CFG0; + CfgReg &= ~Mask; + pADI_XINT0->CFG0 = CfgReg; + ADI_EXIT_CRITICAL_REGION(); + + return (ADI_XINT_SUCCESS); +} + + +/*! + @brief Register or unregister an application callback function for external pin interrupts. + + @details Applications may register a callback function that will be called when an + external interrupt occurs. In addition to registering the interrupt, + the application should call the #adi_xint_EnableIRQ API to enable the + external pin interrupt. + + The driver dispatches calls to registered callback functions when the + properly configured pin(s) latches an external interrupt input on the XINT + pin(s). The callback is dispatched with the following parameters, respectively: + + - application-provided callback parameter (\a pCBParam), + - the interrupt ID (#ADI_XINT_EVENT) that initiated the interrupt, + - NULL. + + @param[in] eEvent The interrupt for which the callback is being registered. + @param[in] pfCallback Pointer to the callback function. This can be passed as NULL to + unregister the callback. + @param[in] pCBParam Callback parameter which will be passed back to the application + when the callback is called.. + + @return Status + - #ADI_XINT_SUCCESS If successfully registered the callback. + - #ADI_XINT_NOT_INITIALIZED [D] If external interrupt driver is not yet initialized. + + @sa adi_xint_EnableIRQ + @sa adi_xint_DisableIRQ +*/ +ADI_XINT_RESULT adi_xint_RegisterCallback (const ADI_XINT_EVENT eEvent, ADI_CALLBACK const pfCallback, void *const pCBParam ) +{ + ADI_INT_STATUS_ALLOC(); + +#ifdef ADI_DEBUG + /* make sure we're initialized */ + if (NULL == gpCallbackTable) + { + return (ADI_XINT_NOT_INITIALIZED); + } +#endif + + ADI_ENTER_CRITICAL_REGION(); + gpCallbackTable[eEvent].pfCallback = pfCallback; + gpCallbackTable[eEvent].pCBParam = pCBParam; + ADI_EXIT_CRITICAL_REGION(); + + /* return the status */ + return (ADI_XINT_SUCCESS); +} + +/*@}*/ + +/*! \cond PRIVATE */ +/* All of the following is excluded from the doxygen output... */ + +/* Common external interrupt handler */ +static inline void XIntCommonInterruptHandler(const ADI_XINT_EVENT eEvent) +{ + /* Clear the IRQ */ + pADI_XINT0->CLR = (1u << (uint32_t)eEvent); + + /* params list is: application-registered cbParam, Event ID, and NULL */ + if(gpCallbackTable[eEvent].pfCallback != NULL) + { + gpCallbackTable[eEvent].pfCallback (gpCallbackTable[eEvent].pCBParam, (uint32_t) eEvent, NULL); + } +} + +/* strongly-bound interrupt handlers to override the default weak bindings */ +void Ext_Int0_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT0); + ISR_EPILOG() +} + +void Ext_Int1_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT1); + ISR_EPILOG() +} + +void Ext_Int2_Handler(void) +{ + ISR_PROLOG() + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT2); + ISR_EPILOG() + +} + +void Ext_Int3_Handler(void) +{ + ISR_PROLOG() + if((pADI_XINT0->EXT_STAT & BITM_XINT_EXT_STAT_STAT_UART_RXWKUP)==BITM_XINT_EXT_STAT_STAT_UART_RXWKUP) + { + XIntCommonInterruptHandler(ADI_XINT_EVENT_UART_RX); + } + else + { + XIntCommonInterruptHandler(ADI_XINT_EVENT_INT3); + } + ISR_EPILOG() +} + +/*! \endcond */ + +/* +** EOF +*/ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h new file mode 100755 index 00000000000..205602215cd --- /dev/null +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/xint/adi_xint_def.h @@ -0,0 +1,61 @@ +/*! + ***************************************************************************** + * @file: adi_xint_def.h + * @brief: External Interrupt Driver definition + ***************************************************************************** +Copyright (c) 2016 Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON- +INFRINGEMENT, TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF +CLAIMS OF INTELLECTUAL PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. + +*****************************************************************************/ +#ifndef ADI_XINT_DEF_H +#define ADI_XINT_DEF_H +/*! \cond PRIVATE */ + +/* General macros */ +#define ADI_XINT_CFG_BITS (4u) /*!< number of bits for each external interrupt configuration */ + +/*! Structure to hold callback function and parameter */ +typedef struct _ADI_XINT_CALLBACK_INFO +{ + ADI_CALLBACK pfCallback; /*!< Callback function pointer */ + void *pCBParam; /*!< Callback parameter */ +} ADI_XINT_CALLBACK_INFO; + + +/*! \endcond */ +#endif /* ADI_XINT_DEF_H */ diff --git a/targets/TARGET_Analog_Devices/mbed_rtx.h b/targets/TARGET_Analog_Devices/mbed_rtx.h new file mode 100755 index 00000000000..04f126e9a09 --- /dev/null +++ b/targets/TARGET_Analog_Devices/mbed_rtx.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#if defined(TARGET_EV_COG_AD3029LZ) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20004000UL) +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 26000000 +#endif + +#elif defined(TARGET_EV_COG_AD4050LZ) + +#ifndef INITIAL_SP +#define INITIAL_SP (0x20048000UL) +#endif +#ifndef OS_CLOCK +#define OS_CLOCK 26000000 +#endif + +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct index 49d7a9ae4ac..a3b5b01f763 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_ARM_STD/MK66FN2M0xxx18.sct @@ -52,14 +52,22 @@ #define __ram_vector_table_size__ 0x00000000 #endif -#define m_interrupts_start 0x00000000 +#if !defined(MBED_APP_START) + #define MBED_APP_START 0 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + +#define m_interrupts_start MBED_APP_START #define m_interrupts_size 0x00000400 -#define m_flash_config_start 0x00000400 +#define m_flash_config_start MBED_APP_START + 0x400 #define m_flash_config_size 0x00000010 -#define m_text_start 0x00000410 -#define m_text_size 0x001FFBF0 +#define m_text_start MBED_APP_START + 0x410 +#define m_text_size MBED_APP_SIZE - 0x410 #define m_interrupts_ram_start 0x1FFF0000 #define m_interrupts_ram_size __ram_vector_table_size__ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld index 0287cf769d4..6cf07e2c19c 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_GCC_ARM/MK66FN2M0xxx18.ld @@ -59,6 +59,14 @@ __stack_size__ = 0x400; * heap and the page heap in uVisor applications. */ __heap_size__ = 0x6000; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x200000 +#endif + HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400; STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400; M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; @@ -66,9 +74,9 @@ M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x0400 : 0x0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010 - m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0 + m_interrupts (RX) : ORIGIN = MBED_APP_START, LENGTH = 0x400 + m_flash_config (RX) : ORIGIN = MBED_APP_START + 0x400, LENGTH = 0x10 + m_text (RX) : ORIGIN = MBED_APP_START + 0x410, LENGTH = MBED_APP_SIZE - 0x410 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000 } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf index 6d7fb6135ea..54de75b7bd4 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/device/TOOLCHAIN_IAR/MK66FN2M0xxx18.icf @@ -49,17 +49,25 @@ define symbol __ram_vector_table__ = 1; define symbol __stack_size__=0x8000; define symbol __heap_size__=0x10000; +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = 0; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = 0x200000; +} + define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0; define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0; -define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x000003FF; +define symbol m_interrupts_start = MBED_APP_START; +define symbol m_interrupts_end = MBED_APP_START + 0x3FF; -define symbol m_flash_config_start = 0x00000400; -define symbol m_flash_config_end = 0x0000040F; +define symbol m_flash_config_start = MBED_APP_START + 0x400; +define symbol m_flash_config_end = MBED_APP_START + 0x40F; -define symbol m_text_start = 0x00000410; -define symbol m_text_end = 0x001FFFFF; +define symbol m_text_start = MBED_APP_START + 0x410; +define symbol m_text_end = MBED_APP_START + MBED_APP_SIZE - 1; define symbol m_interrupts_ram_start = 0x1FFF0000; define symbol m_interrupts_ram_end = 0x1FFF0000 + __ram_vector_table_offset__; @@ -112,4 +120,3 @@ place in DATA_region { block ZI }; place in DATA_region { last block HEAP }; place in CSTACK_region { block CSTACK }; place in m_interrupts_ram_region { section m_interrupts_ram }; - diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c index 1be03651e44..dc6ab710f40 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT3_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c index 1be03651e44..dc6ab710f40 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT3_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c index 6af039a5a37..43f7dc0bb4d 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c @@ -22,6 +22,14 @@ static int us_ticker_inited = 0; +static void lptmr_isr(void) +{ + LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); + LPTMR_StopTimer(LPTMR0); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -56,7 +64,7 @@ void us_ticker_init(void) busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk); LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1); /* Set interrupt handler */ - NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr); NVIC_EnableIRQ(LPTMR0_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c index 6af039a5a37..43f7dc0bb4d 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c @@ -22,6 +22,14 @@ static int us_ticker_inited = 0; +static void lptmr_isr(void) +{ + LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); + LPTMR_StopTimer(LPTMR0); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -56,7 +64,7 @@ void us_ticker_init(void) busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk); LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1); /* Set interrupt handler */ - NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr); NVIC_EnableIRQ(LPTMR0_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c index 613483583eb..39142267596 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT0_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT0_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c index 1be03651e44..dc6ab710f40 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT3_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c index b376ce0d260..5246cf8d62f 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c @@ -22,7 +22,16 @@ static int us_ticker_inited = 0; -void us_ticker_init(void) { +static void lptmr_isr(void) +{ + LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); + LPTMR_StopTimer(LPTMR0); + + us_ticker_irq_handler(); +} + +void us_ticker_init(void) +{ if (us_ticker_inited) { return; } @@ -55,12 +64,13 @@ void us_ticker_init(void) { busClock = CLOCK_GetFreq(kCLOCK_McgInternalRefClk); LPTMR_SetTimerPeriod(LPTMR0, busClock / 1000000 - 1); /* Set interrupt handler */ - NVIC_SetVector(LPTMR0_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr); NVIC_EnableIRQ(LPTMR0_IRQn); } -uint32_t us_ticker_read() { +uint32_t us_ticker_read() +{ if (!us_ticker_inited) { us_ticker_init(); } @@ -68,15 +78,18 @@ uint32_t us_ticker_read() { return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1)); } -void us_ticker_disable_interrupt(void) { +void us_ticker_disable_interrupt(void) +{ LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); } -void us_ticker_clear_interrupt(void) { +void us_ticker_clear_interrupt(void) +{ LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); } -void us_ticker_set_interrupt(timestamp_t timestamp) { +void us_ticker_set_interrupt(timestamp_t timestamp) +{ uint32_t delta = timestamp - us_ticker_read(); LPTMR_StopTimer(LPTMR0); LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c index 1be03651e44..dc6ab710f40 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT3_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c index 9594b3dd486..a4b32f8c3f2 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT3_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c index 1be03651e44..dc6ab710f40 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c @@ -21,6 +21,16 @@ static int us_ticker_inited = 0; +static void pit_isr(void) +{ + PIT_ClearStatusFlags(PIT, kPIT_Chnl_3, PIT_TFLG_TIF_MASK); + PIT_ClearStatusFlags(PIT, kPIT_Chnl_2, PIT_TFLG_TIF_MASK); + PIT_StopTimer(PIT, kPIT_Chnl_2); + PIT_StopTimer(PIT, kPIT_Chnl_3); + + us_ticker_irq_handler(); +} + void us_ticker_init(void) { if (us_ticker_inited) { @@ -47,7 +57,7 @@ void us_ticker_init(void) //Ticker PIT_SetTimerPeriod(PIT, kPIT_Chnl_2, busClock / 1000000 - 1); PIT_SetTimerChainMode(PIT, kPIT_Chnl_3, true); - NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler); + NVIC_SetVector(PIT3_IRQn, (uint32_t)pit_isr); NVIC_EnableIRQ(PIT3_IRQn); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c index 18fc6e1dfe3..7b57feaf476 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c @@ -139,6 +139,11 @@ void lp_ticker_set_interrupt(timestamp_t timestamp) /* Checking if LPTRM can handle this sleep */ delta_ticks = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk)); + if (delta_ticks == 0) { + /* The requested delay is less than the minimum resolution of this counter */ + delta_ticks = 1; + } + if (delta_ticks > MAX_LPTMR_SLEEP) { /* Using RTC if wait time is over 16b (2s @32kHz) */ uint32_t delta_sec; @@ -154,6 +159,11 @@ void lp_ticker_set_interrupt(timestamp_t timestamp) /* Set aditional, subsecond, sleep time */ if (delta_us) { lptmr_schedule = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk)); + if (lptmr_schedule == 0) { + /* The requested delay is less than the minimum resolution of this counter */ + lptmr_schedule = 1; + } + } } else { /* Below RTC resolution using LPTMR */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_lock.h index 28bb062f6ec..475024adbaa 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/mxc_lock.h @@ -69,7 +69,7 @@ __STATIC_INLINE int mxc_get_lock(uint32_t *lock, uint32_t value) do { // Return if the lock is taken by a different thread - if(__LDREXW((volatile unsigned long *)lock) != 0) { + if(__LDREXW((volatile uint32_t *)lock) != 0) { return E_BUSY; } diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h index 3c17a9298e7..bd2988eb658 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_lock.h @@ -80,12 +80,12 @@ __STATIC_INLINE int mxc_get_lock(uint32_t *lock, uint32_t value) do { // Return if the lock is taken by a different thread - if(__LDREXW((volatile unsigned long *)lock) != 0) { + if(__LDREXW((volatile uint32_t *)lock) != 0) { return E_BUSY; } // Attempt to take the lock - } while(__STREXW(value, (volatile unsigned long *)lock) != 0); + } while(__STREXW(value, (volatile uint32_t *)lock) != 0); // Do not start any other memory access until memory barrier is complete __DMB(); diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c index aaf82a83ada..5788ec04797 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c @@ -67,7 +67,7 @@ uint16_t analogin_read_u16(analogin_t *obj) // initialization by assigment because IAR dosen't support variable initializer in declaration statement. adc_channel.config.config.resolution = NRF_ADC_CONFIG_RES_10BIT; - adc_channel.config.config.input = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE; + adc_channel.config.config.input = NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD; adc_channel.config.config.reference = NRF_ADC_CONFIG_REF_VBG; adc_channel.config.config.ain = (obj->adc_pin); adc_channel.p_next = NULL; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h new file mode 100644 index 00000000000..0798e678c1e --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/PinNames.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2016 Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA + * integrated circuit in a product or a software update for such product, must reproduce + * the above copyright notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be + * used to endorse or promote products derived from this software without specific prior + * written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary or object form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + + LED1 = p11, + LED2 = p11, + LED3 = p11, + LED4 = p11, + + RX_PIN_NUMBER = p30, + TX_PIN_NUMBER = p29, + CTS_PIN_NUMBER = p28, + RTS_PIN_NUMBER = p2, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_PSELMOSI0 = p6, + SPI_PSELMISO0 = p7, + SPI_PSELSS0 = p3, + SPI_PSELSCK0 = p8, + + SPI_PSELMOSI1 = p29, + SPI_PSELMISO1 = p30, + SPI_PSELSS1 = p28, + SPI_PSELSCK1 = p2, + + SPIS_PSELMOSI = p29, + SPIS_PSELMISO = p30, + SPIS_PSELSS = p28, + SPIS_PSELSCK = p2, + + I2C_SDA0 = p28, + I2C_SCL0 = p2, + + D0 = p30, + D1 = p29, + D2 = p28, + D3 = p2, + + D4 = p3, + D5 = p6, + D6 = p7, + D7 = p8, + D8 = p21, + + D9 = p4, + D10 = p5, + + D13 = p11, + + A0 = p28, + A1 = p29, + A2 = p30, + A3 = p2, + A4 = p4, + A5 = p5, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h new file mode 100644 index 00000000000..493844b8012 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_RBLAB_BLENANO2/device.h @@ -0,0 +1,23 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c index ec73afa6a3f..9e12311e8e3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c @@ -33,7 +33,6 @@ typedef struct { bool used_as_gpio : 1; PinDirection direction : 1; - bool init_high : 1; PinMode pull : 2; bool used_as_irq : 1; bool irq_fall : 1; @@ -151,12 +150,12 @@ static void gpio_apply_config(uint8_t pin) cfg.pull = NRF_GPIO_PIN_NOPULL; break; } - nrf_drv_gpiote_in_init(pin, &cfg, NULL); + nrf_gpio_cfg_input(pin,cfg.pull); } } else { // Configure as output. - nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high); + nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(nrf_gpio_pin_out_read(pin)); nrf_drv_gpiote_out_init(pin, &cfg); } m_gpio_initialized |= ((gpio_mask_t)1UL << pin); diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c index e8d07601fcd..c6629680174 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/i2c_api.c @@ -50,10 +50,14 @@ #include "nrf_gpio.h" #include "nrf_delay.h" -// An arbitrary value used as the counter in loops waiting for given event -// (e.g. STOPPED), needed to avoid infinite loops (and not involve any timers -// or tickers). -#define TIMEOUT_VALUE 1000 +#include "us_ticker_api.h" + +// An arbitrary value used as the timeout in loops waiting for given event +// (e.g. STOPPED), needed to avoid infinite loops. +// This value might be defined externally. +#ifndef I2C_TIMEOUT_VALUE_US + #define I2C_TIMEOUT_VALUE_US 1000000 +#endif #if DEVICE_I2C_ASYNCH #define TWI_IDX(obj) ((obj)->i2c.twi_idx) @@ -371,17 +375,20 @@ int i2c_start(i2c_t *obj) int i2c_stop(i2c_t *obj) { NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; + uint32_t t0; // The current transfer may be suspended (if it is RX), so it must be // resumed before the STOP task is triggered. nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - uint32_t remaining_time = TIMEOUT_VALUE; + + t0 = ticker_read(get_us_ticker_data()); + do { if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED)) { return 0; } - } while (--remaining_time); + } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US); return 1; } @@ -464,11 +471,15 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data) { + uint32_t t0; + nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); nrf_twi_txd_set(twi, data); - uint32_t remaining_time = TIMEOUT_VALUE; + + t0 = ticker_read(get_us_ticker_data()); + do { if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) { nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); @@ -478,7 +489,7 @@ static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data) nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); return 0; // some error occurred } - } while (--remaining_time); + } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US); return 2; // timeout; } @@ -500,6 +511,9 @@ static void start_twi_write(NRF_TWI_Type *twi, int address) int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { twi_info_t *twi_info = TWI_INFO(obj); + bool timeout = false; + uint32_t t0, t1; + #if DEVICE_I2C_ASYNCH if (twi_info->active) { return I2C_ERROR_BUS_BUSY; @@ -522,12 +536,16 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) nrf_twi_event_clear(twi, event); nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); } - uint32_t remaining_time = TIMEOUT_VALUE; + + t0 = ticker_read(get_us_ticker_data()); + do { if (nrf_twi_event_check(twi, event)) { break; } - } while (--remaining_time); + t1 = ticker_read(get_us_ticker_data()); + timeout = (t1 - t0) >= I2C_TIMEOUT_VALUE_US; + } while (!timeout); uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) { @@ -537,7 +555,7 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) return I2C_ERROR_NO_SLAVE; } - return (remaining_time ? 0 : I2C_ERROR_BUS_BUSY); + return (timeout ? I2C_ERROR_BUS_BUSY : 0); } int result = length; @@ -574,13 +592,15 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) int i2c_byte_read(i2c_t *obj, int last) { NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; + uint32_t t0; if (last) { nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); } nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - uint32_t remaining_time = TIMEOUT_VALUE; + t0 = ticker_read(get_us_ticker_data()); + do { if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) { nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); @@ -590,7 +610,7 @@ int i2c_byte_read(i2c_t *obj, int last) nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); return I2C_ERROR_NO_SLAVE; } - } while (--remaining_time); + } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US); return I2C_ERROR_BUS_BUSY; } diff --git a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h index 6744a32ce9a..9c633835d98 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/objects.h @@ -117,10 +117,6 @@ struct pwmout_s { uint32_t pulsewidth_us; }; -struct sleep_s { - int powerdown; -}; - struct can_s { CANName can; char index; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c index 8b05fe86275..7f918418cd8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c @@ -339,25 +339,6 @@ static int i2c_set_int(i2c_t *obj, int inten) return inten_back; } -int i2c_allow_powerdown(void) -{ - uint32_t modinit_mask = i2c_modinit_mask; - while (modinit_mask) { - int i2c_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx; - struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; - if (var->obj) { - // Disallow entering power-down mode if I2C transfer is enabled. - if (i2c_active(var->obj)) { - return 0; - } - } - modinit_mask &= ~(1 << i2c_idx); - } - - return 1; -} - static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) { if (! buf || ! length) { diff --git a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c index f89dc4f6a00..d95197c3e4e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/pwmout_api.c @@ -172,26 +172,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) pwmout_config(obj); } -int pwmout_allow_powerdown(void) -{ - uint32_t modinit_mask = pwm_modinit_mask; - while (modinit_mask) { - int pwm_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx; - if (modinit->modname != NC) { - PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname); - uint32_t chn = NU_MODSUBINDEX(modinit->modname); - // Disallow entering power-down mode if PWM counter is enabled. - if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) { - return 0; - } - } - modinit_mask &= ~(1 << pwm_idx); - } - - return 1; -} - static void pwmout_config(pwmout_t* obj) { PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm); diff --git a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c index 292adcf8938..fd3fa1b1a04 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c @@ -87,6 +87,9 @@ time_t rtc_read(void) timeinfo.tm_mday = rtc_datetime.u32Day; timeinfo.tm_wday = rtc_datetime.u32DayOfWeek; timeinfo.tm_hour = rtc_datetime.u32Hour; + if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) { + timeinfo.tm_hour += 12; + } timeinfo.tm_min = rtc_datetime.u32Minute; timeinfo.tm_sec = rtc_datetime.u32Second; diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c index b0965477c70..382ea3e7e78 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c @@ -656,33 +656,6 @@ int serial_irq_handler_asynch(serial_t *obj) return (obj->serial.event & (event_rx | event_tx)); } -int serial_allow_powerdown(void) -{ - uint32_t modinit_mask = uart_modinit_mask; - while (modinit_mask) { - int uart_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx; - if (modinit->modname != NC) { - UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if Tx FIFO has data to flush - if (! UART_IS_TX_EMPTY((uart_base))) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going - if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going - if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << uart_idx); - } - - return 1; -} - static void uart0_vec_async(void) { uart_irq_async(uart0_var.obj); diff --git a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c index ab1b9daa37d..c2bb24eb7ef 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/sleep.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/sleep.c @@ -15,8 +15,6 @@ */ #include "sleep_api.h" -#include "serial_api.h" -#include "lp_ticker_api.h" #if DEVICE_SLEEP @@ -25,77 +23,24 @@ #include "objects.h" #include "PeripheralPins.h" -static void mbed_enter_sleep(struct sleep_s *obj); -static void mbed_exit_sleep(struct sleep_s *obj); - -int serial_allow_powerdown(void); -int spi_allow_powerdown(void); -int i2c_allow_powerdown(void); -int pwmout_allow_powerdown(void); - /** - * Enter Idle mode. + * Enter idle mode, in which just CPU is halted. */ void hal_sleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 0; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); } /** - * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode. + * Enter power-down mode, in which HXT/HIRC are halted. */ void hal_deepsleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 1; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); -} - -static void mbed_enter_sleep(struct sleep_s *obj) -{ - // Check if serial allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = serial_allow_powerdown(); - } - // Check if spi allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = spi_allow_powerdown(); - } - // Check if i2c allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = i2c_allow_powerdown(); - } - // Check if pwmout allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = pwmout_allow_powerdown(); - } - // TODO: Check if other peripherals allow entering power-down mode - - if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_PowerDown(); - SYS_LockReg(); - } - else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_Idle(); - SYS_LockReg(); - } - __NOP(); - __NOP(); - __NOP(); - __NOP(); -} - -static void mbed_exit_sleep(struct sleep_s *obj) -{ - // TODO: TO BE CONTINUED - - (void)obj; + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c index 5616bd60cc6..5d035ccf994 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/spi_api.c @@ -470,25 +470,6 @@ uint8_t spi_active(spi_t *obj) return (spi_base->CTL & SPI_CTL_SPIEN_Msk); } -int spi_allow_powerdown(void) -{ - uint32_t modinit_mask = spi_modinit_mask; - while (modinit_mask) { - int spi_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx; - if (modinit->modname != NC) { - SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if SPI transfer is enabled. - if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << spi_idx); - } - - return 1; -} - static int spi_writeable(spi_t * obj) { // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive diff --git a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h index fef01cfdafd..e3d24534d81 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h @@ -118,10 +118,6 @@ struct pwmout_s { uint32_t pulsewidth_us; }; -struct sleep_s { - int powerdown; -}; - struct trng_s { uint8_t dummy; }; diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h index 070104eb74d..d3e5669df71 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h @@ -35908,8 +35908,12 @@ typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile #define NULL (0) ///< NULL pointer #endif +#ifndef TRUE #define TRUE (1UL) ///< Boolean true, define to use in API parameters or return value +#endif +#ifndef FALSE #define FALSE (0UL) ///< Boolean false, define to use in API parameters or return value +#endif #define ENABLE (1UL) ///< Enable, define to use in API parameters #define DISABLE (0UL) ///< Disable, define to use in API parameters diff --git a/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c index 2313d4f9283..bf8e92a87c0 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c @@ -330,25 +330,6 @@ static int i2c_set_int(i2c_t *obj, int inten) return inten_back; } -int i2c_allow_powerdown(void) -{ - uint32_t modinit_mask = i2c_modinit_mask; - while (modinit_mask) { - int i2c_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx; - struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; - if (var->obj) { - // Disallow entering power-down mode if I2C transfer is enabled. - if (i2c_active(var->obj)) { - return 0; - } - } - modinit_mask &= ~(1 << i2c_idx); - } - - return 1; -} - static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) { if (! buf || ! length) { diff --git a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c index 6e07e785fa1..033b9e5898a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c @@ -103,8 +103,6 @@ void lp_ticker_init(void) // Schedule wakeup to match semantics of lp_ticker_get_compare_match() lp_ticker_set_interrupt(wakeup_tick); - - } timestamp_t lp_ticker_read() @@ -144,21 +142,13 @@ timestamp_t lp_ticker_read() void lp_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t now = lp_ticker_read(); + uint32_t delta = timestamp - lp_ticker_read(); wakeup_tick = timestamp; TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - int delta = (int) (timestamp - now); - if (delta > 0) { - cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC; - lp_ticker_arm_cd(); - } else { - // NOTE: With lp_ticker_fire_interrupt() introduced, upper layer would handle past event case. - // This code fragment gets redundant, but it is still kept here for backward-compatible. - void lp_ticker_fire_interrupt(void); - lp_ticker_fire_interrupt(); - } + cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC; + lp_ticker_arm_cd(); } void lp_ticker_fire_interrupt(void) diff --git a/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c index 93bfe68116c..12d49872563 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/pwmout_api.c @@ -167,26 +167,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) pwmout_config(obj, 1); } -int pwmout_allow_powerdown(void) -{ - uint32_t modinit_mask = pwm_modinit_mask; - while (modinit_mask) { - int pwm_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx; - if (modinit->modname != NC) { - EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(modinit->modname); - uint32_t chn = NU_MODSUBINDEX(modinit->modname); - // Disallow entering power-down mode if PWM counter is enabled. - if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) { - return 0; - } - } - modinit_mask &= ~(1 << pwm_idx); - } - - return 1; -} - static void pwmout_config(pwmout_t* obj, int start) { EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c index 5047ccad033..7535c3a72fa 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c @@ -22,6 +22,7 @@ #include "mbed_error.h" #include "nu_modutil.h" #include "nu_miscutil.h" +#include "mbed_mktime.h" #define YEAR0 1900 //#define EPOCH_YR 1970 @@ -88,11 +89,14 @@ time_t rtc_read(void) timeinfo.tm_mday = rtc_datetime.u32Day; timeinfo.tm_wday = rtc_datetime.u32DayOfWeek; timeinfo.tm_hour = rtc_datetime.u32Hour; + if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) { + timeinfo.tm_hour += 12; + } timeinfo.tm_min = rtc_datetime.u32Minute; timeinfo.tm_sec = rtc_datetime.u32Second; // Convert to timestamp - time_t t = mktime(&timeinfo); + time_t t = _rtc_mktime(&timeinfo); return t; } @@ -104,18 +108,21 @@ void rtc_write(time_t t) } // Convert timestamp to struct tm - struct tm *timeinfo = localtime(&t); + struct tm timeinfo; + if (_rtc_localtime(t, &timeinfo) == false) { + return; + } S_RTC_TIME_DATA_T rtc_datetime; // Convert S_RTC_TIME_DATA_T to struct tm - rtc_datetime.u32Year = timeinfo->tm_year + YEAR0; - rtc_datetime.u32Month = timeinfo->tm_mon + 1; - rtc_datetime.u32Day = timeinfo->tm_mday; - rtc_datetime.u32DayOfWeek = timeinfo->tm_wday; - rtc_datetime.u32Hour = timeinfo->tm_hour; - rtc_datetime.u32Minute = timeinfo->tm_min; - rtc_datetime.u32Second = timeinfo->tm_sec; + rtc_datetime.u32Year = timeinfo.tm_year + YEAR0; + rtc_datetime.u32Month = timeinfo.tm_mon + 1; + rtc_datetime.u32Day = timeinfo.tm_mday; + rtc_datetime.u32DayOfWeek = timeinfo.tm_wday; + rtc_datetime.u32Hour = timeinfo.tm_hour; + rtc_datetime.u32Minute = timeinfo.tm_min; + rtc_datetime.u32Second = timeinfo.tm_sec; rtc_datetime.u32TimeScale = RTC_CLOCK_24; // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational. diff --git a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c index e45867c118c..25695156a39 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c @@ -710,33 +710,6 @@ int serial_irq_handler_asynch(serial_t *obj) return (obj->serial.event & (event_rx | event_tx)); } -int serial_allow_powerdown(void) -{ - uint32_t modinit_mask = uart_modinit_mask; - while (modinit_mask) { - int uart_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx; - if (modinit->modname != NC) { - UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if Tx FIFO has data to flush - if (! UART_IS_TX_EMPTY((uart_base))) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going - if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going - if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << uart_idx); - } - - return 1; -} - static void uart0_vec_async(void) { uart_irq_async(uart0_var.obj); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/sleep.c b/targets/TARGET_NUVOTON/TARGET_M480/sleep.c index a6fde61172b..c2bb24eb7ef 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/sleep.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/sleep.c @@ -15,8 +15,6 @@ */ #include "sleep_api.h" -#include "serial_api.h" -#include "lp_ticker_api.h" #if DEVICE_SLEEP @@ -25,74 +23,24 @@ #include "objects.h" #include "PeripheralPins.h" -static void mbed_enter_sleep(struct sleep_s *obj); -static void mbed_exit_sleep(struct sleep_s *obj); - -int serial_allow_powerdown(void); -int spi_allow_powerdown(void); -int i2c_allow_powerdown(void); -int pwmout_allow_powerdown(void); - /** - * Enter Idle mode. + * Enter idle mode, in which just CPU is halted. */ void hal_sleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 0; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); } /** - * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode. + * Enter power-down mode, in which HXT/HIRC are halted. */ void hal_deepsleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 1; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); -} - -static void mbed_enter_sleep(struct sleep_s *obj) -{ - // Check if serial allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = serial_allow_powerdown(); - } - // Check if spi allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = spi_allow_powerdown(); - } - // Check if i2c allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = i2c_allow_powerdown(); - } - // Check if pwmout allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = pwmout_allow_powerdown(); - } - // TODO: Check if other peripherals allow entering power-down mode - - if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_PowerDown(); - SYS_LockReg(); - } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_Idle(); - SYS_LockReg(); - } - __NOP(); - __NOP(); - __NOP(); - __NOP(); -} - -static void mbed_exit_sleep(struct sleep_s *obj) -{ - (void)obj; + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c index 88ae09d6ff8..79e6818d28a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/spi_api.c @@ -461,25 +461,6 @@ uint8_t spi_active(spi_t *obj) return (spi_base->CTL & SPI_CTL_SPIEN_Msk); } -int spi_allow_powerdown(void) -{ - uint32_t modinit_mask = spi_modinit_mask; - while (modinit_mask) { - int spi_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx; - if (modinit->modname != NC) { - SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if SPI transfer is enabled. - if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << spi_idx); - } - - return 1; -} - static int spi_writeable(spi_t * obj) { // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive diff --git a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c index 4f3c6efd52c..24d15537e44 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/trng_api.c @@ -25,9 +25,17 @@ /* * Get Random number generator. */ + +#define PRNG_KEY_SIZE (0x20UL) + static volatile int g_PRNG_done; volatile int g_AES_done; +/* Implementation that should never be optimized out by the compiler */ +static void trng_zeroize( void *v, size_t n ) { + volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +} + void CRYPTO_IRQHandler() { if (PRNG_GET_INT_FLAG()) { @@ -77,21 +85,22 @@ void trng_free(trng_t *obj) int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { (void)obj; - - *output_length = 0; - if (length < 32) { - unsigned char tmpBuff[32]; + unsigned char tmpBuff[PRNG_KEY_SIZE]; + size_t cur_length = 0; + + while (length >= sizeof(tmpBuff)) { + trng_get(output); + output += sizeof(tmpBuff); + cur_length += sizeof(tmpBuff); + length -= sizeof(tmpBuff); + } + if (length > 0) { trng_get(tmpBuff); - memcpy(output, &tmpBuff, length); - *output_length = length; - } else { - for (unsigned i = 0; i < (length/32); i++) { - trng_get(output); - *output_length += 32; - output += 32; - } + memcpy(output, tmpBuff, length); + cur_length += length; + trng_zeroize(tmpBuff, sizeof(tmpBuff)); } - + *output_length = cur_length; return 0; } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c index 6665c3cfa46..cae36145014 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c @@ -147,16 +147,9 @@ void us_ticker_set_interrupt(timestamp_t timestamp) { TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - int delta = (int) (timestamp - us_ticker_read()); - if (delta > 0) { - cd_major_minor_us = delta * US_PER_TICK; - us_ticker_arm_cd(); - } else { - // NOTE: With us_ticker_fire_interrupt() introduced, upper layer would handle past event case. - // This code fragment gets redundant, but it is still kept here for backward-compatible. - void us_ticker_fire_interrupt(void); - us_ticker_fire_interrupt(); - } + uint32_t delta = timestamp - us_ticker_read(); + cd_major_minor_us = delta * US_PER_TICK; + us_ticker_arm_cd(); } void us_ticker_fire_interrupt(void) diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h index acd1297e01d..57661d2639e 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h @@ -118,8 +118,8 @@ typedef enum { LED_GREEN = LED1, LED_YELLOW = LED2, // Button naming - SW2 = PE_5, - SW3 = PE_6, + SW1 = PE_5, + SW2 = PE_6, } PinName; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h index 8ec51b38e86..12476fd7c14 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/objects.h @@ -110,9 +110,6 @@ struct pwmout_s { uint32_t pulsewidth_us; }; -struct sleep_s { - int powerdown; -}; #ifdef __cplusplus } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h index c6655323a64..6a6520e57cd 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h @@ -11831,8 +11831,12 @@ typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile #define NULL (0) ///< NULL pointer #endif +#ifndef TRUE #define TRUE (1) ///< Boolean true, define to use in API parameters or return value +#endif +#ifndef FALSE #define FALSE (0) ///< Boolean false, define to use in API parameters or return value +#endif #define ENABLE (1) ///< Enable, define to use in API parameters #define DISABLE (0) ///< Disable, define to use in API parameters diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c index 07d92ddd307..fb26ccc24fe 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/gpio_irq_api.c @@ -49,23 +49,23 @@ static struct nu_gpio_irq_var gpio_irq_var_arr[] = { #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0])) -#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE -#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE 0 +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0 #endif -#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST -#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC #endif static PinName gpio_irq_debounce_arr[] = { - MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE_LIST + MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST }; -#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE -#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCLKSRC_IRC10K +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCLKSRC_IRC10K #endif -#ifndef MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE -#define MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCLKSEL_16 +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCLKSEL_16 #endif int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) @@ -90,12 +90,12 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 // There is no need to call gpio_set() redundantly. { -#if MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_ENABLE +#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE // Suppress compiler warning (void) gpio_irq_debounce_arr; // Configure de-bounce clock source and sampling cycle time - GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); #else // Enable de-bounce if the pin is in the de-bounce enable list @@ -112,7 +112,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 if (pin_index == pin_index_debunce && port_index == port_index_debounce) { // Configure de-bounce clock source and sampling cycle time - GPIO_SET_DEBOUNCE_TIME(MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_NANO100_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); break; } diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c index 375602b461e..3e146ee8b17 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/i2c_api.c @@ -358,25 +358,6 @@ static int i2c_set_int(i2c_t *obj, int inten) return inten_back; } -int i2c_allow_powerdown(void) -{ - uint32_t modinit_mask = i2c_modinit_mask; - while (modinit_mask) { - int i2c_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx; - struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; - if (var->obj) { - // Disallow entering power-down mode if I2C transfer is enabled. - if (i2c_active(var->obj)) { - return 0; - } - } - modinit_mask &= ~(1 << i2c_idx); - } - - return 1; -} - static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) { if (! buf || ! length) { diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c index 87b67b5ba87..7a9bf129b00 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c @@ -141,7 +141,7 @@ timestamp_t lp_ticker_read() while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT); // Add power-down compensation - return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK); + return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK); } while (0); } @@ -222,6 +222,6 @@ static void lp_ticker_arm_cd(void) TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); // Wait 2 cycles of engine clock to ensure previous CTL write action is finish wait_us(30 * 2); - timer3_base->CTL = ctl_timer3 | TIMER_CTL_TMR_EN_Msk; + timer3_base->CTL |= ctl_timer3 | TIMER_CTL_TMR_EN_Msk; } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json b/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json deleted file mode 100644 index 1494a976ff2..00000000000 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_lib.json +++ /dev/null @@ -1,22 +0,0 @@ -{ - "name": "NANO100", - "config": { - "gpio-irq-debounce-enable": { - "help": "Enable GPIO IRQ debounce", - "value": 0 - }, - "gpio-irq-debounce-enable-list": { - "help": "Comma separated pin list to enable GPIO IRQ debounce", - "value": "NC" - }, - "gpio-irq-debounce-clock-source": { - "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K", - "value": "GPIO_DBCLKSRC_IRC10K" - }, - - "gpio-irq-debounce-sample-rate": { - "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768", - "value": "GPIO_DBCLKSEL_16" - } - } -} diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c index eb648492079..7eca1a1ab33 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/pwmout_api.c @@ -176,26 +176,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) pwmout_config(obj); } -int pwmout_allow_powerdown(void) -{ - uint32_t modinit_mask = pwm_modinit_mask; - while (modinit_mask) { - int pwm_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx; - if (modinit->modname != NC) { - PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname); - uint32_t chn = NU_MODSUBINDEX(modinit->modname); - // Disallow entering power-down mode if PWM counter is enabled. - if (pwm_base->OE & (1 << chn)) { - return 0; - } - } - modinit_mask &= ~(1 << pwm_idx); - } - - return 1; -} - static void pwmout_config(pwmout_t* obj) { PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm); diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c index c6836291377..a4a6bc0675a 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c @@ -87,6 +87,9 @@ time_t rtc_read(void) timeinfo.tm_mday = rtc_datetime.u32Day; timeinfo.tm_wday = rtc_datetime.u32DayOfWeek; timeinfo.tm_hour = rtc_datetime.u32Hour; + if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) { + timeinfo.tm_hour += 12; + } timeinfo.tm_min = rtc_datetime.u32Minute; timeinfo.tm_sec = rtc_datetime.u32Second; diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c index 93f91467515..7810d009776 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c @@ -597,33 +597,6 @@ int serial_irq_handler_asynch(serial_t *obj) return (obj->serial.event & (event_rx | event_tx)); } -int serial_allow_powerdown(void) -{ - uint32_t modinit_mask = uart_modinit_mask; - while (modinit_mask) { - int uart_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx; - if (modinit->modname != NC) { - UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if Tx FIFO has data to flush - if (! UART_IS_TX_EMPTY((uart_base))) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going - if (uart_base->IER & (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk)) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going - if (uart_base->CTL & UART_CTL_DMA_RX_EN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << uart_idx); - } - - return 1; -} - static void uart_irq_async(serial_t *obj) { if (serial_is_irq_en(obj, RxIrq)) { diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c b/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c index ec5126ec20d..dd32dd41718 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/sleep.c @@ -15,8 +15,6 @@ */ #include "sleep_api.h" -#include "serial_api.h" -#include "lp_ticker_api.h" #if DEVICE_SLEEP @@ -25,74 +23,24 @@ #include "objects.h" #include "PeripheralPins.h" -static void mbed_enter_sleep(struct sleep_s *obj); -static void mbed_exit_sleep(struct sleep_s *obj); - -int serial_allow_powerdown(void); -int spi_allow_powerdown(void); -int i2c_allow_powerdown(void); -int pwmout_allow_powerdown(void); - /** - * Enter Idle mode. + * Enter idle mode, in which just CPU is halted. */ void hal_sleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 0; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); } /** - * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode. + * Enter power-down mode, in which HXT/HIRC are halted. */ void hal_deepsleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 1; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); -} - -static void mbed_enter_sleep(struct sleep_s *obj) -{ - // Check if serial allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = serial_allow_powerdown(); - } - // Check if spi allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = spi_allow_powerdown(); - } - // Check if i2c allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = i2c_allow_powerdown(); - } - // Check if pwmout allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = pwmout_allow_powerdown(); - } - // TODO: Check if other peripherals allow entering power-down mode - - if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_PowerDown(); - SYS_LockReg(); - } else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_Idle(); - SYS_LockReg(); - } - __NOP(); - __NOP(); - __NOP(); - __NOP(); -} - -static void mbed_exit_sleep(struct sleep_s *obj) -{ - (void)obj; + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c index 86def36d767..0bc47ae67f3 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/spi_api.c @@ -505,24 +505,6 @@ uint8_t spi_active(spi_t *obj) return SPI_IS_BUSY(spi_base); } -int spi_allow_powerdown(void) -{ - uint32_t modinit_mask = spi_modinit_mask; - while (modinit_mask) { - int spi_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx; - if (modinit->modname != NC) { - SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname); - if (SPI_IS_BUSY(spi_base)) { - return 0; - } - } - modinit_mask &= ~(1 << spi_idx); - } - - return 1; -} - void SPI0_IRQHandler(void) { spi_irq(spi0_var.obj); diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h index 2e62f15efc7..da3db2d54b2 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/objects.h @@ -118,10 +118,6 @@ struct pwmout_s { uint32_t pulsewidth_us; }; -struct sleep_s { - int powerdown; -}; - struct trng_s { uint8_t dummy; }; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h index 664551ec71f..00af9638dea 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h @@ -32511,8 +32511,12 @@ typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile #define NULL (0) ///< NULL pointer #endif +#ifndef TRUE #define TRUE (1) ///< Boolean true, define to use in API parameters or return value +#endif +#ifndef FALSE #define FALSE (0) ///< Boolean false, define to use in API parameters or return value +#endif #define ENABLE (1) ///< Enable, define to use in API parameters #define DISABLE (0) ///< Disable, define to use in API parameters diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h index 9a87f8a6bb3..3d633b166d4 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_rtc.h @@ -129,7 +129,7 @@ typedef struct { * 1 = This year is a leap year. * \hideinitializer */ -#define RTC_IS_LEAP_YEAR ((RTC->LEAPYEAR & (RTC_LEAPYEAR_LEAPYEAR_Msk))?1:0) +#define RTC_IS_LEAP_YEAR() ((RTC->LEAPYEAR & (RTC_LEAPYEAR_LEAPYEAR_Msk))?1:0) /** * @brief Clear alarm interrupt status. @@ -139,7 +139,7 @@ typedef struct { * @return None * \hideinitializer */ -#define RTC_CLEAR_ALARM_INT_FLAG (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) +#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk) /** * @brief Clear tick interrupt status. @@ -149,7 +149,7 @@ typedef struct { * @return None * \hideinitializer */ -#define RTC_CLEAR_TICK_INT_FLAG (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) +#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk) /** * @brief Clear tamper detect pin status. @@ -169,7 +169,7 @@ typedef struct { * @return Alarm interrupt status * \hideinitializer */ -#define RTC_GET_ALARM_INT_FLAG ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk) >> RTC_INTSTS_ALMIF_Pos) +#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk) >> RTC_INTSTS_ALMIF_Pos) /** * @brief Get alarm interrupt status. @@ -179,7 +179,7 @@ typedef struct { * @return Alarm interrupt status * \hideinitializer */ -#define RTC_GET_TICK_INT_FLAG ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk) >> RTC_INTSTS_TICKIF_Pos) +#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk) >> RTC_INTSTS_TICKIF_Pos) /** * @brief Get tamper detect pin status. diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c index 481f7d6bd05..450451d89f2 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/i2c_api.c @@ -356,25 +356,6 @@ static int i2c_set_int(i2c_t *obj, int inten) return inten_back; } -int i2c_allow_powerdown(void) -{ - uint32_t modinit_mask = i2c_modinit_mask; - while (modinit_mask) { - int i2c_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx; - struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; - if (var->obj) { - // Disallow entering power-down mode if I2C transfer is enabled. - if (i2c_active(var->obj)) { - return 0; - } - } - modinit_mask &= ~(1 << i2c_idx); - } - - return 1; -} - static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) { if (! buf || ! length) { diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c index 90165697c63..bd2409ff8ce 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/pwmout_api.c @@ -195,26 +195,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) pwmout_config(obj); } -int pwmout_allow_powerdown(void) -{ - uint32_t modinit_mask = pwm_modinit_mask; - while (modinit_mask) { - int pwm_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = pwm_modinit_tab + pwm_idx; - if (modinit->modname != NC) { - PWM_T *pwm_base = (PWM_T *) NU_MODBASE(modinit->modname); - uint32_t chn = NU_MODSUBINDEX(modinit->modname); - // Disallow entering power-down mode if PWM counter is enabled. - if ((pwm_base->CNTEN & (1 << chn)) && pwm_base->CMPDAT[chn]) { - return 0; - } - } - modinit_mask &= ~(1 << pwm_idx); - } - - return 1; -} - static void pwmout_config(pwmout_t* obj) { PWM_T *pwm_base = (PWM_T *) NU_MODBASE(obj->pwm); diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c index cf7dfbf2d2a..41ec6042d9d 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c @@ -87,6 +87,9 @@ time_t rtc_read(void) timeinfo.tm_mday = rtc_datetime.u32Day; timeinfo.tm_wday = rtc_datetime.u32DayOfWeek; timeinfo.tm_hour = rtc_datetime.u32Hour; + if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) { + timeinfo.tm_hour += 12; + } timeinfo.tm_min = rtc_datetime.u32Minute; timeinfo.tm_sec = rtc_datetime.u32Second; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c index b3dd9737aaa..be8e304c4e9 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c @@ -694,33 +694,6 @@ int serial_irq_handler_asynch(serial_t *obj) return (obj->serial.event & (event_rx | event_tx)); } -int serial_allow_powerdown(void) -{ - uint32_t modinit_mask = uart_modinit_mask; - while (modinit_mask) { - int uart_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = uart_modinit_tab + uart_idx; - if (modinit->modname != NC) { - UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if Tx FIFO has data to flush - if (! UART_IS_TX_EMPTY((uart_base))) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (not PDMA) is on-going - if (uart_base->INTEN & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { - return 0; - } - // Disallow entering power-down mode if async Rx transfer (PDMA) is on-going - if (uart_base->INTEN & UART_INTEN_RXPDMAEN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << uart_idx); - } - - return 1; -} - static void uart0_vec_async(void) { uart_irq_async(uart0_var.obj); diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c b/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c index 87f53ab6f61..c2bb24eb7ef 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/sleep.c @@ -15,8 +15,6 @@ */ #include "sleep_api.h" -#include "serial_api.h" -#include "lp_ticker_api.h" #if DEVICE_SLEEP @@ -25,80 +23,24 @@ #include "objects.h" #include "PeripheralPins.h" -static void mbed_enter_sleep(struct sleep_s *obj); -static void mbed_exit_sleep(struct sleep_s *obj); - -int serial_allow_powerdown(void); -int spi_allow_powerdown(void); -int i2c_allow_powerdown(void); -int pwmout_allow_powerdown(void); - /** - * Enter Idle mode. + * Enter idle mode, in which just CPU is halted. */ void hal_sleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 0; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); } /** - * Enter Power-down mode while no peripheral is active; otherwise, enter Idle mode. + * Enter power-down mode, in which HXT/HIRC are halted. */ void hal_deepsleep(void) { - struct sleep_s sleep_obj; - sleep_obj.powerdown = 1; - mbed_enter_sleep(&sleep_obj); - mbed_exit_sleep(&sleep_obj); -} - -static void mbed_enter_sleep(struct sleep_s *obj) -{ - // Check if serial allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = serial_allow_powerdown(); - } - // Check if spi allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = spi_allow_powerdown(); - } - // Check if i2c allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = i2c_allow_powerdown(); - } - // Check if pwmout allows entering power-down mode - if (obj->powerdown) { - obj->powerdown = pwmout_allow_powerdown(); - } - // TODO: Check if other peripherals allow entering power-down mode - - if (obj->powerdown) { // Power-down mode (HIRC/HXT disabled, LIRC/LXT enabled) - SYS_UnlockReg(); - CLK_PowerDown(); - SYS_LockReg(); - } - else { // CPU halt mode (HIRC/HXT enabled, LIRC/LXT enabled) - // NOTE: NUC472's CLK_Idle() will also disable HIRC/HXT. - SYS_UnlockReg(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; - __WFI(); - SYS_LockReg(); - } - __NOP(); - __NOP(); - __NOP(); - __NOP(); -} - -static void mbed_exit_sleep(struct sleep_s *obj) -{ - // TODO: TO BE CONTINUED - - (void)obj; + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); } #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c index 6b12a925f29..1ab0704fc26 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/spi_api.c @@ -469,25 +469,6 @@ uint8_t spi_active(spi_t *obj) return (spi_base->CTL & SPI_CTL_SPIEN_Msk); } -int spi_allow_powerdown(void) -{ - uint32_t modinit_mask = spi_modinit_mask; - while (modinit_mask) { - int spi_idx = nu_ctz(modinit_mask); - const struct nu_modinit_s *modinit = spi_modinit_tab + spi_idx; - if (modinit->modname != NC) { - SPI_T *spi_base = (SPI_T *) NU_MODBASE(modinit->modname); - // Disallow entering power-down mode if SPI transfer is enabled. - if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { - return 0; - } - } - modinit_mask &= ~(1 << spi_idx); - } - - return 1; -} - static int spi_writeable(spi_t * obj) { // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c index 6fab1b43063..a1f55b48f6a 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/trng_api.c @@ -30,9 +30,17 @@ /* * Get Random number generator. */ + +#define PRNG_KEY_SIZE (0x20UL) + static volatile int g_PRNG_done; volatile int g_AES_done; +/* Implementation that should never be optimized out by the compiler */ +static void trng_zeroize( void *v, size_t n ) { + volatile unsigned char *p = (unsigned char*)v; while( n-- ) *p++ = 0; +} + void CRYPTO_IRQHandler() { if (PRNG_GET_INT_FLAG()) { @@ -82,21 +90,22 @@ void trng_free(trng_t *obj) int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { (void)obj; - - *output_length = 0; - if (length < 32) { - unsigned char tmpBuff[32]; + unsigned char tmpBuff[PRNG_KEY_SIZE]; + size_t cur_length = 0; + + while (length >= sizeof(tmpBuff)) { + trng_get(output); + output += sizeof(tmpBuff); + cur_length += sizeof(tmpBuff); + length -= sizeof(tmpBuff); + } + if (length > 0) { trng_get(tmpBuff); - memcpy(output, &tmpBuff, length); - *output_length = length; - } else { - for (int i = 0; i < (length/32); i++) { - trng_get(output); - *output_length += 32; - output += 32; - } + memcpy(output, tmpBuff, length); + cur_length += length; + trng_zeroize(tmpBuff, sizeof(tmpBuff)); } - + *output_length = cur_length; return 0; } diff --git a/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h b/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h index 8ed4113f1f4..fa0b722f704 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h +++ b/targets/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h @@ -55,6 +55,32 @@ typedef enum { p18 = P0_26, p19 = P1_30, p20 = P1_31, +#if defined(TARGET_LPC1769) + p21 = P0_2, + p22 = P0_3, + p23 = P0_21, + p24 = P0_22, + p25 = P0_27, + p26 = P0_28, + p27 = P2_13, + + p38 = P0_4, + p39 = P0_5, + p40 = P0_10, + p41 = P0_11, + p42 = P2_0, + p43 = P2_1, + p44 = P2_2, + p45 = P2_3, + p46 = P2_4, + p47 = P2_5, + p48 = P2_6, + p49 = P2_7, + p50 = P2_8, + p51 = P2_10, + p52 = P2_11, + p53 = P2_12, +#else p21 = P2_5, p22 = P2_4, p23 = P2_3, @@ -65,6 +91,7 @@ typedef enum { p28 = P0_10, p29 = P0_5, p30 = P0_4, +#endif // Other mbed Pin Names #ifdef MCB1700 @@ -72,6 +99,11 @@ typedef enum { LED2 = P1_29, LED3 = P1_31, LED4 = P2_2, +#elif defined(TARGET_LPC1769) + LED1 = P0_22, + LED2 = P0_22, + LED3 = P0_22, + LED4 = P0_22, #else LED1 = P1_18, LED2 = P1_20, @@ -113,8 +145,8 @@ typedef enum { I2C_SDA0 = NC, I2C_SCL1 = p10, I2C_SDA1 = p9, - I2C_SCL2 = p27, // pin used by application board - I2C_SDA2 = p28, // pin used by application board + I2C_SCL2 = P0_11, // pin used by application board + I2C_SDA2 = P0_10, // pin used by application board I2C_SCL = I2C_SCL2, I2C_SDA = I2C_SDA2, } PinName; diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/CRP.c b/targets/TARGET_NXP/TARGET_LPC176X/device/CRP.c new file mode 100644 index 00000000000..f2ae329670b --- /dev/null +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/CRP.c @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include "mbed_toolchain.h" + + /* Code Read Protection + +NONE 0xFFFFFFFF - No code protection. + +CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200. + - Read Memory command: disabled. + - Copy RAM to Flash command: cannot write to Sector 0. + - "Go" command: disabled. + - Erase sector(s) command: can erase any individual sector except + sector 0 only, or can erase all sectors at once. + - Compare command: disabled + +CRP2 0x87654321 - Write to RAM command: disabled. + - Copy RAM to Flash: disabled. + - Erase command: only allows erase of all sectors. + +CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry + by pulling PIO0_1 LOW is disabled if a valid user code is + present in flash sector 0. +Caution: If CRP3 is selected, no future factory testing can be +performed on the device. +*/ +#if !defined(APPLICATION_ADDR) // Relocate CRP if there is a bootloader. + #define APPLICATION_ADDR 0 +#endif + +#define CRP_NONE 0xFFFFFFFF +#define CRP_1 0x12345678 +#define CRP_2 0x87654321 +#define CRP_3 0x43218765 + +#ifndef CRP +#define CRP CRP_NONE +#endif + +MBED_SECTION(".CRPSection") MBED_USED const long CRP_Key = CRP; diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct index 6af8037232f..44d51132a1d 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct @@ -1,9 +1,24 @@ +#! armcc -E -LR_IROM1 0x00000000 0x80000 { ; load region size_region - ER_IROM1 0x00000000 0x80000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x80000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + ER_IROM0 MBED_APP_START 0x2FC { ; load address = execution address + *.o (RESET, +First) + .ANY (+RO) + } + ER_CRP (MBED_APP_START + 0x2FC) FIXED 4 { + *.o (.CRPSection) + } + ER_IROM1 (MBED_APP_START + (0x2FC + 4)) FIXED (MBED_APP_SIZE - (0x2FC + 4)) { + *(InRoot$$Sections) + .ANY (+RO) } ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8 ; 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18 diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S index 9646f2f17c7..01b19858c3a 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/startup_LPC17xx.S @@ -99,12 +99,6 @@ __Vectors DCD __initial_sp ; Top of Stack DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - AREA |.text|, CODE, READONLY diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct index 2e5afcd5e1e..f56aae73897 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/LPC1768.sct @@ -1,9 +1,24 @@ +#! armcc -E -LR_IROM1 0x00000000 0x80000 { ; load region size_region - ER_IROM1 0x00000000 0x80000 { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x80000 +#endif + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + ER_IROM0 MBED_APP_START 0x2FC { ; load address = execution address + *.o (RESET, +First) + .ANY (+RO) + } + ER_CRP (MBED_APP_START + 0x2FC) FIXED 4 { + *.o (.CRPSection) + } + ER_IROM1 (MBED_APP_START + (0x2FC + 4)) FIXED (MBED_APP_SIZE - (0x2FC + 4)) { + *(InRoot$$Sections) + .ANY (+RO) } ; 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8 ; 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18 diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S index 32e2abf7fbf..e844d2f9acb 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_STD/startup_LPC17xx.S @@ -82,12 +82,6 @@ __Vectors DCD __initial_sp ; Top of Stack DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL) - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - AREA |.text|, CODE, READONLY diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld index 8ab5bcaf22e..a4a05fcbfb9 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_ARM/LPC1768.ld @@ -1,9 +1,15 @@ /* Linker script for mbed LPC1768 */ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x00000000 +#endif +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 512K +#endif /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8 - 32) /* topmost 32 bytes used by IAP functions */ USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K @@ -43,6 +49,10 @@ SECTIONS .text : { KEEP(*(.isr_vector)) + /* Code Read Protect data */ + . = 0x000002FC ; + KEEP(*(.CRPSection)) + /* End of Code Read Protect */ *(.text*) KEEP(*(.init)) @@ -65,6 +75,8 @@ SECTIONS *(.rodata*) KEEP(*(.eh_frame*)) + + } > FLASH .ARM.extab : diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf index 57037ba6900..0cea4b47c71 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/LPC17xx.icf @@ -1,11 +1,13 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; } /*###ICF### Section handled by ICF editor, don't touch! ****/ /*-Editor annotation file-*/ /* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ /*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; define symbol __ICFEDIT_region_NVIC_end__ = 0x100000C7; define symbol __ICFEDIT_region_RAM_start__ = 0x100000C8; @@ -17,8 +19,8 @@ define symbol __ICFEDIT_size_cstack__ = 0x1000; define symbol __ICFEDIT_size_heap__ = 0x2000; /**** End of ICF editor section. ###ICF###*/ -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; +define symbol __CRP_start__ = MBED_APP_START + 0x000002FC; +define symbol __CRP_end__ = MBED_APP_START + 0x000002FF; define symbol __RAM1_start__ = 0x2007C000; define symbol __RAM1_end__ = 0x20083FFF; @@ -41,5 +43,5 @@ place in ROM_region { readonly }; place in RAM_region { readwrite, block HEAP, block CSTACK }; -place in CRP_region { section .crp }; +place in CRP_region { section .CRPSection }; place in RAM1_region { section .ethusbram }; diff --git a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S index 4ffb5331abf..52b1c39d4f8 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S +++ b/targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_IAR/startup_LPC17xx.S @@ -350,26 +350,4 @@ USBActivity_IRQHandler CANActivity_IRQHandler B CANActivity_IRQHandler -#ifndef SRAM - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -CRP1 0x12345678 - Write to RAM command can not access RAM below 0x10000200. - - Read Memory command: disabled. - - Copy RAM to Flash command: cannot write to Sector 0. - - "Go" command: disabled. - - Erase sector(s) command: can erase any individual sector except - sector 0 only, or can erase all sectors at once. - - Compare command: disabled -CRP2 0x87654321 - Write to RAM command: disabled. - - Copy RAM to Flash: disabled. - - Erase command: only allows erase of all sectors. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF -#endif END diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c index 54d97dbb0d2..7ea6885fbf2 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c @@ -52,25 +52,25 @@ const int ethernet_MTU_SIZE = 0x300; #define ETHERNET_ADDR_SIZE 6 -PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */ +MBED_PACKED(struct) RX_DESC_TypeDef { /* RX Descriptor struct */ unsigned int Packet; unsigned int Ctrl; }; typedef struct RX_DESC_TypeDef RX_DESC_TypeDef; -PACKED struct RX_STAT_TypeDef { /* RX Status struct */ +MBED_PACKED(struct) RX_STAT_TypeDef { /* RX Status struct */ unsigned int Info; unsigned int HashCRC; }; typedef struct RX_STAT_TypeDef RX_STAT_TypeDef; -PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */ +MBED_PACKED(struct) TX_DESC_TypeDef { /* TX Descriptor struct */ unsigned int Packet; unsigned int Ctrl; }; typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; -PACKED struct TX_STAT_TypeDef { /* TX Status struct */ +MBED_PACKED(struct) TX_STAT_TypeDef { /* TX Status struct */ unsigned int Info; }; typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; @@ -436,9 +436,9 @@ int ethernet_init() { int regv, tout; char mac[ETHERNET_ADDR_SIZE]; unsigned int clock = clockselect(); - + LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */ - + LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */ LPC_IOCON->P1_1 &= ~0x07; @@ -459,7 +459,7 @@ int ethernet_init() { LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */ LPC_IOCON->P1_17 &= ~0x07; LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */ - + /* Reset all EMAC internal modules. */ LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; @@ -523,7 +523,7 @@ int ethernet_init() { LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */ LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */ - + LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */ LPC_EMAC->MAC1 |= MAC1_REC_EN; @@ -548,9 +548,9 @@ int ethernet_init() { void ethernet_free() { LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE); LPC_EMAC->IntClear = 0xFFFF; - + LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */ - + LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */ LPC_IOCON->P1_1 &= ~0x07; LPC_IOCON->P1_4 &= ~0x07; @@ -908,22 +908,22 @@ void ethernet_address(char *mac) { void ethernet_set_link(int speed, int duplex) { unsigned short phy_data; int tout; - + if((speed < 0) || (speed > 1)) { phy_data = PHY_AUTO_NEG; } else { phy_data = (((unsigned short) speed << 13) | ((unsigned short) duplex << 8)); } - + phy_write(PHY_REG_BMCR, phy_data); - + for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */ - + switch(phy_id) { case DP83848C_ID: phy_data = phy_read(PHY_REG_STS); - + if(phy_data & PHY_STS_DUPLEX) { LPC_EMAC->MAC2 |= MAC2_FULL_DUP; LPC_EMAC->Command |= CR_FULL_DUP; @@ -933,17 +933,17 @@ void ethernet_set_link(int speed, int duplex) { LPC_EMAC->Command &= ~CR_FULL_DUP; LPC_EMAC->IPGT = IPGT_HALF_DUP; } - + if(phy_data & PHY_STS_SPEED) { LPC_EMAC->SUPP &= ~SUPP_SPEED; } else { LPC_EMAC->SUPP |= SUPP_SPEED; } break; - + case LAN8720_ID: phy_data = phy_read(PHY_REG_SCSR); - + if (phy_data & PHY_SCSR_DUPLEX) { LPC_EMAC->MAC2 |= MAC2_FULL_DUP; LPC_EMAC->Command |= CR_FULL_DUP; @@ -952,13 +952,13 @@ void ethernet_set_link(int speed, int duplex) { LPC_EMAC->Command &= ~CR_FULL_DUP; LPC_EMAC->IPGT = IPGT_HALF_DUP; } - + if(phy_data & PHY_SCSR_100MBIT) { LPC_EMAC->SUPP |= SUPP_SPEED; } else { LPC_EMAC->SUPP &= ~SUPP_SPEED; } - + break; } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a deleted file mode 100644 index f5e2ab0bdb0..00000000000 Binary files a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/libpower.a and /dev/null differ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a deleted file mode 100644 index f5f23f69e50..00000000000 Binary files a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/libpower.a and /dev/null differ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h new file mode 100644 index 00000000000..7efa1e5c20e --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h @@ -0,0 +1,113 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PortNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + OSC32KCLK = 0, +} RTCName; + +typedef enum { + UART_0 = Flexcomm0, + UART_2 = Flexcomm2, + UART_7 = Flexcomm7 +} UARTName; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART UART_0 + +typedef enum { + I2C_7 = Flexcomm7, + I2C_2 = Flexcomm2 +} I2CName; + +#define TPM_SHIFT 8 +typedef enum { + PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0 + PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1 + PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2 + PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3 + PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4 + PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5 + PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6 + PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7 + PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0 + PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1 + PWM_11 = (1 << TPM_SHIFT) | (2), // FTM1 CH2 + PWM_12 = (1 << TPM_SHIFT) | (3), // FTM1 CH3 + PWM_13 = (1 << TPM_SHIFT) | (4), // FTM1 CH4 + PWM_14 = (1 << TPM_SHIFT) | (5), // FTM1 CH5 + PWM_15 = (1 << TPM_SHIFT) | (6), // FTM1 CH6 + PWM_16 = (1 << TPM_SHIFT) | (7), // FTM1 CH7 + PWM_17 = (2 << TPM_SHIFT) | (0), // FTM2 CH0 + PWM_18 = (2 << TPM_SHIFT) | (1), // FTM2 CH1 + PWM_19 = (2 << TPM_SHIFT) | (2), // FTM2 CH2 + PWM_20 = (2 << TPM_SHIFT) | (3), // FTM2 CH3 + PWM_21 = (2 << TPM_SHIFT) | (4), // FTM2 CH4 + PWM_22 = (2 << TPM_SHIFT) | (5), // FTM2 CH5 + PWM_23 = (2 << TPM_SHIFT) | (6), // FTM2 CH6 + PWM_24 = (2 << TPM_SHIFT) | (7), // FTM2 CH7 + PWM_25 = (3 << TPM_SHIFT) | (0), // FTM3 CH0 + PWM_26 = (3 << TPM_SHIFT) | (1), // FTM3 CH1 + PWM_27 = (3 << TPM_SHIFT) | (2), // FTM3 CH2 + PWM_28 = (3 << TPM_SHIFT) | (3), // FTM3 CH3 + PWM_29 = (3 << TPM_SHIFT) | (4), // FTM3 CH4 + PWM_30 = (3 << TPM_SHIFT) | (5), // FTM3 CH5 + PWM_31 = (3 << TPM_SHIFT) | (6), // FTM3 CH6 + PWM_32 = (3 << TPM_SHIFT) | (7), // FTM3 CH7 +} PWMName; + +#define ADC_INSTANCE_SHIFT 8 +#define ADC_B_CHANNEL_SHIFT 5 + +typedef enum { + ADC0_SE0 = 0, + ADC0_SE1 = 1, + ADC0_SE2 = 2, + ADC0_SE3 = 3, + ADC0_SE4 = 4, + ADC0_SE5 = 5, + ADC0_SE6 = 6, + ADC0_SE7 = 7, + ADC0_SE8 = 8, + ADC0_SE9 = 9, + ADC0_SE10 = 10, + ADC0_SE11 = 11, +} ADCName; + +typedef enum { + CAN_1 = 1 +} CANName; + +typedef enum { + SPI_0 = Flexcomm0, + SPI_2 = Flexcomm2, + SPI_3 = Flexcomm3 +} SPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c new file mode 100644 index 00000000000..bb555ca3b71 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PeripheralPins.c @@ -0,0 +1,125 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +/************RTC***************/ +const PinMap PinMap_RTC[] = { + {NC, OSC32KCLK, 0}, +}; + +/************ADC***************/ +const PinMap PinMap_ADC[] = { + {P0_15, ADC0_SE3, 0}, + {P0_16, ADC0_SE4, 0}, + {P0_23, ADC0_SE11, 0}, + {P0_31, ADC0_SE5, 0}, + {P1_0, ADC0_SE6, 0}, + {P0_10, ADC0_SE0, 0}, + {NC , NC , 0} +}; + +/************CAN***************/ +const PinMap PinMap_CAN_TD[] = { + {P0_1, CAN_1, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_CAN_RD[] = { + {P0_0, CAN_1, 1}, + {NC , NC , 0} +}; + + +/************DAC***************/ +const PinMap PinMap_DAC[] = { + {NC , NC , 0} +}; + +/************I2C***************/ +const PinMap PinMap_I2C_SDA[] = { + {P0_26, I2C_2, 1}, + {P1_29, I2C_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {P0_27, I2C_2, 1}, + {P1_30, I2C_7, 1}, + {NC , NC , 0} +}; + +/************UART***************/ +const PinMap PinMap_UART_TX[] = { + {P0_30, UART_0, 1}, + {P0_27, UART_2, 1}, + {P1_30, UART_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RX[] = { + {P0_29, UART_0, 1}, + {P0_26, UART_2, 1}, + {P1_29, UART_7, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {NC , NC , 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {NC , NC , 0} +}; + +/************SPI***************/ +const PinMap PinMap_SPI_SCLK[] = { + {P1_4, SPI_0, 1}, + {P1_23, SPI_2, 1}, + {P0_6, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MOSI[] = { + {P1_5, SPI_0, 1}, + {P1_24, SPI_2, 1}, + {P0_8, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {P1_6, SPI_0, 1}, + {P1_25, SPI_2, 1}, + {P0_9, SPI_3, 1}, + {NC , NC , 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {P1_7, SPI_0, 1}, + {P0_7, SPI_3, 1}, + {NC , NC , 0} +}; + +/************PWM***************/ +const PinMap PinMap_PWM[] = { + {P0_17 , PWM_1, 4}, + {P0_18 , PWM_2, 4}, + {P0_19 , PWM_3, 4}, + {P0_22 , PWM_4, 4}, + {P0_28 , PWM_8, 4}, + {P0_29 , PWM_9, 4}, + {NC , NC, 0} +}; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h new file mode 100644 index 00000000000..bc22e8e4bce --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/PinNames.h @@ -0,0 +1,250 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 5 + +typedef enum { + P0_0 = (0 << PORT_SHIFT | 0), + P0_1 = (0 << PORT_SHIFT | 1), + P0_2 = (0 << PORT_SHIFT | 2), + P0_3 = (0 << PORT_SHIFT | 3), + P0_4 = (0 << PORT_SHIFT | 4), + P0_5 = (0 << PORT_SHIFT | 5), + P0_6 = (0 << PORT_SHIFT | 6), + P0_7 = (0 << PORT_SHIFT | 7), + P0_8 = (0 << PORT_SHIFT | 8), + P0_9 = (0 << PORT_SHIFT | 9), + P0_10 = (0 << PORT_SHIFT | 10), + P0_11 = (0 << PORT_SHIFT | 11), + P0_12 = (0 << PORT_SHIFT | 12), + P0_13 = (0 << PORT_SHIFT | 13), + P0_14 = (0 << PORT_SHIFT | 14), + P0_15 = (0 << PORT_SHIFT | 15), + P0_16 = (0 << PORT_SHIFT | 16), + P0_17 = (0 << PORT_SHIFT | 17), + P0_18 = (0 << PORT_SHIFT | 18), + P0_19 = (0 << PORT_SHIFT | 19), + P0_20 = (0 << PORT_SHIFT | 20), + P0_21 = (0 << PORT_SHIFT | 21), + P0_22 = (0 << PORT_SHIFT | 22), + P0_23 = (0 << PORT_SHIFT | 23), + P0_24 = (0 << PORT_SHIFT | 24), + P0_25 = (0 << PORT_SHIFT | 25), + P0_26 = (0 << PORT_SHIFT | 26), + P0_27 = (0 << PORT_SHIFT | 27), + P0_28 = (0 << PORT_SHIFT | 28), + P0_29 = (0 << PORT_SHIFT | 29), + P0_30 = (0 << PORT_SHIFT | 30), + P0_31 = (0 << PORT_SHIFT | 31), + + P1_0 = (1 << PORT_SHIFT | 0), + P1_1 = (1 << PORT_SHIFT | 1), + P1_2 = (1 << PORT_SHIFT | 2), + P1_3 = (1 << PORT_SHIFT | 3), + P1_4 = (1 << PORT_SHIFT | 4), + P1_5 = (1 << PORT_SHIFT | 5), + P1_6 = (1 << PORT_SHIFT | 6), + P1_7 = (1 << PORT_SHIFT | 7), + P1_8 = (1 << PORT_SHIFT | 8), + P1_9 = (1 << PORT_SHIFT | 9), + P1_10 = (1 << PORT_SHIFT | 10), + P1_11 = (1 << PORT_SHIFT | 11), + P1_12 = (1 << PORT_SHIFT | 12), + P1_13 = (1 << PORT_SHIFT | 13), + P1_14 = (1 << PORT_SHIFT | 14), + P1_15 = (1 << PORT_SHIFT | 15), + P1_16 = (1 << PORT_SHIFT | 16), + P1_17 = (1 << PORT_SHIFT | 17), + P1_18 = (1 << PORT_SHIFT | 18), + P1_19 = (1 << PORT_SHIFT | 19), + P1_20 = (1 << PORT_SHIFT | 20), + P1_21 = (1 << PORT_SHIFT | 21), + P1_22 = (1 << PORT_SHIFT | 22), + P1_23 = (1 << PORT_SHIFT | 23), + P1_24 = (1 << PORT_SHIFT | 24), + P1_25 = (1 << PORT_SHIFT | 25), + P1_26 = (1 << PORT_SHIFT | 26), + P1_27 = (1 << PORT_SHIFT | 27), + P1_28 = (1 << PORT_SHIFT | 28), + P1_29 = (1 << PORT_SHIFT | 29), + P1_30 = (1 << PORT_SHIFT | 30), + P1_31 = (1 << PORT_SHIFT | 31), + + P2_0 = (2 << PORT_SHIFT | 0), + P2_1 = (2 << PORT_SHIFT | 1), + P2_2 = (2 << PORT_SHIFT | 2), + P2_3 = (2 << PORT_SHIFT | 3), + P2_4 = (2 << PORT_SHIFT | 4), + P2_5 = (2 << PORT_SHIFT | 5), + P2_6 = (2 << PORT_SHIFT | 6), + P2_7 = (2 << PORT_SHIFT | 7), + P2_8 = (2 << PORT_SHIFT | 8), + P2_9 = (2 << PORT_SHIFT | 9), + P2_10 = (2 << PORT_SHIFT | 10), + P2_11 = (2 << PORT_SHIFT | 11), + P2_12 = (2 << PORT_SHIFT | 12), + P2_13 = (2 << PORT_SHIFT | 13), + P2_14 = (2 << PORT_SHIFT | 14), + P2_15 = (2 << PORT_SHIFT | 15), + P2_16 = (2 << PORT_SHIFT | 16), + P2_17 = (2 << PORT_SHIFT | 17), + P2_18 = (2 << PORT_SHIFT | 18), + P2_19 = (2 << PORT_SHIFT | 19), + P2_20 = (2 << PORT_SHIFT | 20), + P2_21 = (2 << PORT_SHIFT | 21), + P2_22 = (2 << PORT_SHIFT | 22), + P2_23 = (2 << PORT_SHIFT | 23), + P2_24 = (2 << PORT_SHIFT | 24), + P2_25 = (2 << PORT_SHIFT | 25), + P2_26 = (2 << PORT_SHIFT | 26), + P2_27 = (2 << PORT_SHIFT | 27), + P2_28 = (2 << PORT_SHIFT | 28), + P2_29 = (2 << PORT_SHIFT | 29), + P2_30 = (2 << PORT_SHIFT | 30), + P2_31 = (2 << PORT_SHIFT | 31), + + P3_0 = (3 << PORT_SHIFT | 0), + P3_1 = (3 << PORT_SHIFT | 1), + P3_2 = (3 << PORT_SHIFT | 2), + P3_3 = (3 << PORT_SHIFT | 3), + P3_4 = (3 << PORT_SHIFT | 4), + P3_5 = (3 << PORT_SHIFT | 5), + P3_6 = (3 << PORT_SHIFT | 6), + P3_7 = (3 << PORT_SHIFT | 7), + P3_8 = (3 << PORT_SHIFT | 8), + P3_9 = (3 << PORT_SHIFT | 9), + P3_10 = (3 << PORT_SHIFT | 10), + P3_11 = (3 << PORT_SHIFT | 11), + P3_12 = (3 << PORT_SHIFT | 12), + P3_13 = (3 << PORT_SHIFT | 13), + P3_14 = (3 << PORT_SHIFT | 14), + P3_15 = (3 << PORT_SHIFT | 15), + P3_16 = (3 << PORT_SHIFT | 16), + P3_17 = (3 << PORT_SHIFT | 17), + P3_18 = (3 << PORT_SHIFT | 18), + P3_19 = (3 << PORT_SHIFT | 19), + P3_20 = (3 << PORT_SHIFT | 20), + P3_21 = (3 << PORT_SHIFT | 21), + P3_22 = (3 << PORT_SHIFT | 22), + P3_23 = (3 << PORT_SHIFT | 23), + P3_24 = (3 << PORT_SHIFT | 24), + P3_25 = (3 << PORT_SHIFT | 25), + P3_26 = (3 << PORT_SHIFT | 26), + P3_27 = (3 << PORT_SHIFT | 27), + P3_28 = (3 << PORT_SHIFT | 28), + P3_29 = (3 << PORT_SHIFT | 29), + P3_30 = (3 << PORT_SHIFT | 30), + P3_31 = (3 << PORT_SHIFT | 31), + + P4_0 = (4 << PORT_SHIFT | 0), + P4_1 = (4 << PORT_SHIFT | 1), + P4_2 = (4 << PORT_SHIFT | 2), + P4_3 = (4 << PORT_SHIFT | 3), + P4_4 = (4 << PORT_SHIFT | 4), + P4_5 = (4 << PORT_SHIFT | 5), + P4_6 = (4 << PORT_SHIFT | 6), + P4_7 = (4 << PORT_SHIFT | 7), + P4_8 = (4 << PORT_SHIFT | 8), + P4_9 = (4 << PORT_SHIFT | 9), + P4_10 = (4 << PORT_SHIFT | 10), + P4_11 = (4 << PORT_SHIFT | 11), + P4_12 = (4 << PORT_SHIFT | 12), + P4_13 = (4 << PORT_SHIFT | 13), + P4_14 = (4 << PORT_SHIFT | 14), + P4_15 = (4 << PORT_SHIFT | 15), + P4_16 = (4 << PORT_SHIFT | 16), + + + + // mbed original LED naming + LED1 = P0_13, + LED2 = P1_27, + LED3 = P0_14, + LED4 = P1_28, + + + // USB Pins + USBTX = P0_30, + USBRX = P0_29, + + + A0 = P0_16, + A1 = P0_31, + A2 = P1_0, + A3 = P2_0, + A4 = P3_4, + A5 = P1_1, + + + p5 = P1_24, + p6 = P1_25, + p7 = P1_23, + p8 = P1_8, + p9 = P0_26, + p10 = P0_27, + p11 = P1_4, + p12 = P1_5, + p13 = P1_6, + p14 = P1_7, + p15 = P0_15, + p16 = P0_16, + p17 = P0_23, + p18 = P0_31, + p19 = P1_0, + p20 = P0_10, + p21 = P0_17, + p22 = P0_18, + p23 = P0_19, + p24 = P0_22, + p25 = P0_28, + p26 = P0_29, + p27 = P1_30, + p28 = P1_29, + p29 = P0_0, + p30 = P0_1, + + + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 2, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c index fd94300ab2c..cea986a6c04 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c @@ -45,11 +45,11 @@ /* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** !!ClocksProfile product: Clocks v1.0 -processor: LPC54608J512 -package_id: LPC54608J512ET180 +processor: LPC54618J512 +package_id: LPC54618J512ET180 mcu_data: ksdk2_0 processor_version: 0.0.0 -board: LPCXpresso54608 +board: LPCXpresso54618 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ #include "fsl_power.h" diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/clock_config.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/device.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/device.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/mbed_overrides.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralNames.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PeripheralPins.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/TARGET_LPCXpresso/PinNames.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/PinNames.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c new file mode 100644 index 00000000000..cea986a6c04 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Setup voltage for the fastest of the clock outputs + * + * 3. Set up wait states of the flash. + * + * 4. Set up all dividers. + * + * 5. Set up all selectors to provide selected clocks. + */ + +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!ClocksProfile +product: Clocks v1.0 +processor: LPC54618J512 +package_id: LPC54618J512ET180 +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: LPCXpresso54618 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +} + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF48M +outputs: +- {id: System_clock.outFreq, value: 48 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF48M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf} +sources: +- {id: SYSCON.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + /*!< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +} + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL ***************************** +!!Configuration +name: BOARD_BootClockPLL180M +outputs: +- {id: FRO12M_clock.outFreq, value: 12 MHz} +- {id: FROHF_clock.outFreq, value: 48 MHz} +- {id: SYSPLL_clock.outFreq, value: 180 MHz} +- {id: System_clock.outFreq, value: 180 MHz} +settings: +- {id: SYSCON.M_MULT.scale, value: '30', locked: true} +- {id: SYSCON.N_DIV.scale, value: '1', locked: true} +- {id: SYSCON.PDEC.scale, value: '2', locked: true} +- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up} +sources: +- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +void BOARD_BootClockPLL180M(void) +{ + /*!< Set up the clock sources */ + /*!< Set up FRO */ + POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */ + CLOCK_AttachClk( + kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally + being below the voltage for current speed */ + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up SYS PLL */ + const pll_setup_t pllSetup = { + .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U), + .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)), + .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)), + .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)), + .pllRate = 180000000U, + .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP}; + CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source from external crystal */ + CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */ + POWER_SetVoltageForFreq( + 180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(180000000U); /*!< Set FLASH wait states for core */ + CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */ + + /* Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK; +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h new file mode 100644 index 00000000000..f9cdab4d95f --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ +#define BOARD_BootClockRUN BOARD_BootClockFROHF48M + + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFRO12M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************** Configuration BOARD_BootClockFROHF48M *********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF48M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF48M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockFROHF96M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ********************* Configuration BOARD_BootClockPLL180M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL180M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL180M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h new file mode 100644 index 00000000000..de347c375d8 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/device.h @@ -0,0 +1,39 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define NUMBER_OF_GPIO_INTS 8 + +#define APP_EXCLUDE_FROM_DEEPSLEEP \ + (SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK | SYSCON_PDRUNCFG_PDEN_SRAMX_MASK | \ + SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK) + +/* Defines used by the sleep code */ +#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M +#define LPC_CLOCK_RUN BOARD_BootClockFROHF48M + +#define DEVICE_ID_LENGTH 24 + + + + + +#include "objects.h" + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c new file mode 100644 index 00000000000..b727924a6a7 --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c @@ -0,0 +1,121 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "clock_config.h" +#include "fsl_emc.h" +#include "fsl_power.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* The SDRAM timing. */ +#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */ +#define SDRAM_TRP_NS (18u) +#define SDRAM_TRAS_NS (42u) +#define SDRAM_TSREX_NS (67u) +#define SDRAM_TAPR_NS (18u) +#define SDRAM_TWRDELT_NS (6u) +#define SDRAM_TRC_NS (60u) +#define SDRAM_RFC_NS (60u) +#define SDRAM_XSR_NS (67u) +#define SDRAM_RRD_NS (12u) +#define SDRAM_MRD_NCLK (2u) +#define SDRAM_RAS_NCLK (2u) +#define SDRAM_MODEREG_VALUE (0x23u) +#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/ + +// called before main +void mbed_sdk_init() +{ + BOARD_BootClockFROHF48M(); +} + +// Change the NMI pin to an input. This allows NMI pin to +// be used as a low power mode wakeup. The application will +// need to change the pin back to NMI_b or wakeup only occurs once! +void NMI_Handler(void) +{ + //gpio_t gpio; + //gpio_init_in(&gpio, PTA4); +} + +// Enable the RTC oscillator if available on the board +void rtc_setup_oscillator(void) +{ + /* Enable the RTC 32K Oscillator */ + SYSCON->RTCOSCCTRL |= SYSCON_RTCOSCCTRL_EN_MASK; +} + +void ADC_ClockPower_Configuration(void) +{ + /* SYSCON power. */ + POWER_DisablePD(kPDRUNCFG_PD_VDDA); /* Power on VDDA. */ + POWER_DisablePD(kPDRUNCFG_PD_ADC0); /* Power on the ADC converter. */ + POWER_DisablePD(kPDRUNCFG_PD_VD2_ANA); /* Power on the analog power supply. */ + POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ + POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ + + /* Enable the clock. */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); + + /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ + /* Sync clock source is not used. Using sync clock source and would be divided by 2. + * The divider would be set when configuring the converter. + */ + CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ +} + +/* Initialize the external memory. */ +void BOARD_InitSDRAM(void) +{ + emc_basic_config_t basicConfig; + emc_dynamic_timing_config_t dynTiming; + emc_dynamic_chip_config_t dynChipConfig; + + /* Basic configuration. */ + basicConfig.endian = kEMC_LittleEndian; + basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk; + /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M. + * If you change the divide to 0 and EMC clock is larger than 100M + * please take refer to emc.dox to adjust EMC clock delay. + */ + basicConfig.emcClkDiv = 1; + /* Dynamic memory timing configuration. */ + dynTiming.readConfig = kEMC_Cmddelay; + dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS; + dynTiming.tRp_Ns = SDRAM_TRP_NS; + dynTiming.tRas_Ns = SDRAM_TRAS_NS; + dynTiming.tSrex_Ns = SDRAM_TSREX_NS; + dynTiming.tApr_Ns = SDRAM_TAPR_NS; + dynTiming.tWr_Ns = (1000000000 / CLOCK_GetFreq(kCLOCK_EMC) + SDRAM_TWRDELT_NS); /* one clk + 6ns */ + dynTiming.tDal_Ns = dynTiming.tWr_Ns + dynTiming.tRp_Ns; + dynTiming.tRc_Ns = SDRAM_TRC_NS; + dynTiming.tRfc_Ns = SDRAM_RFC_NS; + dynTiming.tXsr_Ns = SDRAM_XSR_NS; + dynTiming.tRrd_Ns = SDRAM_RRD_NS; + dynTiming.tMrd_Nclk = SDRAM_MRD_NCLK; + /* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */ + dynChipConfig.chipIndex = 0; + dynChipConfig.dynamicDevice = kEMC_Sdram; + dynChipConfig.rAS_Nclk = SDRAM_RAS_NCLK; + dynChipConfig.sdramModeReg = SDRAM_MODEREG_VALUE; + dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */ + dynChipConfig.devAddrMap = SDRAM_DEV_MEMORYMAP; + /* EMC Basic configuration. */ + EMC_Init(EMC, &basicConfig); + /* EMC Dynamc memory configuration. */ + EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1); +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h old mode 100644 new mode 100755 similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h index b0d51d03b8b..358d93ddb70 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 +** Processors: LPC54618J512BD208 +** LPC54618J512ET180 ** ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler @@ -13,7 +13,7 @@ ** Build: b170214 ** ** Abstract: -** CMSIS Peripheral Access Layer for LPC54608 +** CMSIS Peripheral Access Layer for LPC54618 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. ** Copyright 2016-2017 NXP @@ -56,16 +56,16 @@ */ /*! - * @file LPC54608.h + * @file LPC54618.h * @version 1.1 * @date 2016-11-25 - * @brief CMSIS Peripheral Access Layer for LPC54608 + * @brief CMSIS Peripheral Access Layer for LPC54618 * - * CMSIS Peripheral Access Layer for LPC54608 + * CMSIS Peripheral Access Layer for LPC54618 */ -#ifndef _LPC54608_H_ -#define _LPC54608_H_ /**< Symbol preventing repeated inclusion */ +#ifndef _LPC54618_H_ +#define _LPC54618_H_ /**< Symbol preventing repeated inclusion */ /** Memory map major version (memory maps with equal major version number are * compatible) */ @@ -181,7 +181,7 @@ typedef enum IRQn { #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ -#include "system_LPC54608.h" /* Device specific configuration file */ +#include "system_LPC54618.h" /* Device specific configuration file */ /*! * @} @@ -713,7 +713,8 @@ typedef struct { /** CAN - Register Layout Typedef */ typedef struct { - uint8_t RESERVED_0[16]; + uint8_t RESERVED_0[12]; + __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ uint8_t RESERVED_1[4]; __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ @@ -779,6 +780,23 @@ typedef struct { * @{ */ +/*! @name DBTP - Data Bit Timing Prescaler Register */ +#define CAN_DBTP_DSJW_MASK (0xFU) +#define CAN_DBTP_DSJW_SHIFT (0U) +#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) +#define CAN_DBTP_DTSEG2_MASK (0xF0U) +#define CAN_DBTP_DTSEG2_SHIFT (4U) +#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) +#define CAN_DBTP_DTSEG1_MASK (0x1F00U) +#define CAN_DBTP_DTSEG1_SHIFT (8U) +#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) +#define CAN_DBTP_DBRP_MASK (0x1F0000U) +#define CAN_DBTP_DBRP_SHIFT (16U) +#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) +#define CAN_DBTP_TDC_MASK (0x800000U) +#define CAN_DBTP_TDC_SHIFT (23U) +#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) + /*! @name TEST - Test Register */ #define CAN_TEST_LBCK_MASK (0x10U) #define CAN_TEST_LBCK_SHIFT (4U) @@ -815,6 +833,12 @@ typedef struct { #define CAN_CCCR_TEST_MASK (0x80U) #define CAN_CCCR_TEST_SHIFT (7U) #define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) +#define CAN_CCCR_FDOE_MASK (0x100U) +#define CAN_CCCR_FDOE_SHIFT (8U) +#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) +#define CAN_CCCR_BRSE_MASK (0x200U) +#define CAN_CCCR_BRSE_SHIFT (9U) +#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) #define CAN_CCCR_PXHD_MASK (0x1000U) #define CAN_CCCR_PXHD_SHIFT (12U) #define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) @@ -824,6 +848,9 @@ typedef struct { #define CAN_CCCR_TXP_MASK (0x4000U) #define CAN_CCCR_TXP_SHIFT (14U) #define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) +#define CAN_CCCR_NISO_MASK (0x8000U) +#define CAN_CCCR_NISO_SHIFT (15U) +#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) /*! @name NBTP - Nominal Bit Timing and Prescaler Register */ #define CAN_NBTP_NTSEG2_MASK (0x7FU) @@ -898,6 +925,18 @@ typedef struct { #define CAN_PSR_BO_MASK (0x80U) #define CAN_PSR_BO_SHIFT (7U) #define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) +#define CAN_PSR_DLEC_MASK (0x700U) +#define CAN_PSR_DLEC_SHIFT (8U) +#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) +#define CAN_PSR_RESI_MASK (0x800U) +#define CAN_PSR_RESI_SHIFT (11U) +#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) +#define CAN_PSR_RBRS_MASK (0x1000U) +#define CAN_PSR_RBRS_SHIFT (12U) +#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) +#define CAN_PSR_RFDF_MASK (0x2000U) +#define CAN_PSR_RFDF_SHIFT (13U) +#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) #define CAN_PSR_PXE_MASK (0x4000U) #define CAN_PSR_PXE_SHIFT (14U) #define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) @@ -12367,5 +12406,5 @@ typedef struct { */ /* end of group SDK_Compatibility_Symbols */ -#endif /* _LPC54608_H_ */ +#endif /* _LPC54618_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h old mode 100644 new mode 100755 similarity index 98% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h index 1bdb5d04e33..02e279d0787 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/LPC54608_features.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h @@ -46,8 +46,8 @@ ** ################################################################### */ -#ifndef _LPC54608_FEATURES_H_ -#define _LPC54608_FEATURES_H_ +#ifndef _LPC54618_FEATURES_H_ +#define _LPC54618_FEATURES_H_ /* SOC module features */ @@ -133,7 +133,7 @@ /* CAN module features */ /* @brief Support CANFD or not */ -#define FSL_FEATURE_CAN_SUPPORT_CANFD (0) +#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) /* DMA module features */ @@ -227,5 +227,5 @@ /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) -#endif /* _LPC54608_FEATURES_H_ */ +#endif /* _LPC54618_FEATURES_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct similarity index 97% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct index 348ada9c3cc..f6a981b2c3e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/LPC54608J512.sct +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct @@ -1,8 +1,8 @@ #! armcc -E /* ** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 +** Processors: LPC54618J512BD208 +** LPC54618J512ET180 ** ** Compiler: Keil ARM C/C++ Compiler ** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar old mode 100644 new mode 100755 similarity index 86% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar index 9e4944c5a4d..2cab4e5e686 Binary files a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/libpower.ar and b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar differ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S index 7416e0e5449..6ebe3baf63a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_ARM_STD/startup_LPC54608.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S @@ -1,7 +1,7 @@ ;/***************************************************************************** -; * @file: startup_LPC54608.s +; * @file: startup_LPC54618.s ; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the -; * LPC54608 +; * LPC54618 ; * @version: 1.1 ; * @date: 2016-11-25 ; * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld similarity index 76% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld index 0391dfbd37d..47aaf977952 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/LPC54608J512_flash.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld @@ -1,61 +1,28 @@ /* ** ################################################################### -** Processors: LPC54608J512 +** Processors: LPC54618J512 ** ** Compiler: GNU C Compiler -** Reference manual: LPC54608 Series Reference Manual, Rev. 0 , 06/2017 +** Reference manual: LPC54618 Series Reference Manual, Rev. 0 , 06/2017 ** Version: rev. 1.0, 2017-6-06 ** Build: b161214 ** ** Abstract: ** Linker file for the GNU C Compiler ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright (c) 2016 - 2017 , NXP -** All rights reserved. -** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** -** o Redistributions of source code must retain the above copyright notice, this list +** 1. Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** -** o Redistributions in binary form must reproduce the above copyright notice, this +** 2. Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** -** o Neither the name of copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com -** -** Copyright (c) 2016 NXP Semiconductors, Inc. -** All rights reserved. -** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of NXP Semiconductors, Inc. nor the names of its +** 3. Neither the name of the copyright holder nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** @@ -97,8 +64,6 @@ MEMORY m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000 m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000 m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00002000 - - } /* Define output sections */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a new file mode 100755 index 00000000000..4503c056334 Binary files /dev/null and b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a differ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S similarity index 91% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S index 22667a8de17..b801b029220 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_GCC_ARM/startup_LPC54608.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S @@ -1,54 +1,25 @@ /* ---------------------------------------------------------------------------------------*/ -/* @file: startup_LPC54608.S */ +/* @file: startup_LPC54618.S */ /* @purpose: CMSIS Cortex-M4 Core Device Startup File */ -/* LPC54608 */ +/* LPC54618 */ /* @version: 1.0 */ /* @date: 2017-6-6 */ /* @build: b161214 */ /* ---------------------------------------------------------------------------------------*/ /* */ -/* Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. */ -/* Copyright (c) 2016 - 2017 , NXP */ -/* */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* o Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* o Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* o Neither the name of copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* */ -/* Copyright (c) 2016 , NXP Semiconductors, Inc. */ -/* All rights reserved. */ -/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2017 NXP */ /* Redistribution and use in source and binary forms, with or without modification, */ /* are permitted provided that the following conditions are met: */ /* */ -/* o Redistributions of source code must retain the above copyright notice, this list */ +/* 1. Redistributions of source code must retain the above copyright notice, this list */ /* of conditions and the following disclaimer. */ /* */ -/* o Redistributions in binary form must reproduce the above copyright notice, this */ +/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ /* list of conditions and the following disclaimer in the documentation and/or */ /* other materials provided with the distribution. */ /* */ -/* o Neither the name of NXP Semiconductors, Inc. nor the names of its */ +/* 3. Neither the name of the copyright holder nor the names of its */ /* contributors may be used to endorse or promote products derived from this */ /* software without specific prior written permission. */ /* */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf similarity index 98% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf index 3e46c7e9baa..eb219474d99 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/LPC54608J512.icf +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf @@ -1,7 +1,7 @@ /* ** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 +** Processors: LPC54618J512BD208 +** LPC54618J512ET180 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM ** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016 diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a new file mode 100755 index 00000000000..755b29878d6 Binary files /dev/null and b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a differ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S index bc7e9e45502..442949881ae 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/TOOLCHAIN_IAR/startup_LPC54608.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S @@ -1,7 +1,7 @@ ;/***************************************************************************** -; * @file: startup_LPC54608.s +; * @file: startup_LPC54618.s ; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * LPC54608 +; * LPC54618 ; * @version: 1.1 ; * @date: 2016-11-25 ; *---------------------------------------------------------------------------- diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis_nvic.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/cmsis_nvic.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/cmsis_nvic.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h similarity index 93% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h index ac8dd79f0e3..aff433895d8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/fsl_device_registers.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h @@ -36,14 +36,14 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_LPC54608J512BD208) || defined(CPU_LPC54608J512ET180)) +#if (defined(CPU_LPC54618J512BD208) || defined(CPU_LPC54618J512ET180)) -#define LPC54608_SERIES +#define LPC54618_SERIES /* CMSIS-style register definitions */ -#include "LPC54608.h" +#include "LPC54618.h" /* CPU specific feature definitions */ -#include "LPC54608_features.h" +#include "LPC54618_features.h" #else #error "No valid CPU defined!" diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c old mode 100644 new mode 100755 similarity index 98% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c index b16179714ae..51e13ce43b1 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c @@ -1,7 +1,7 @@ /* ** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 +** Processors: LPC54618J512BD208 +** LPC54618J512ET180 ** ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler @@ -58,10 +58,10 @@ */ /*! - * @file LPC54608 + * @file LPC54618 * @version 1.1 * @date 2016-11-25 - * @brief Device specific configuration file for LPC54608 (implementation file) + * @brief Device specific configuration file for LPC54618 (implementation file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h old mode 100644 new mode 100755 similarity index 94% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h index 79194524e49..edcefbd0ed4 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/device/system_LPC54608.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Processors: LPC54608J512BD208 -** LPC54608J512ET180 +** Processors: LPC54618J512BD208 +** LPC54618J512ET180 ** ** Compilers: Keil ARM C/C++ Compiler ** GNU C Compiler @@ -58,18 +58,18 @@ */ /*! - * @file LPC54608 + * @file LPC54618 * @version 1.1 * @date 2016-11-25 - * @brief Device specific configuration file for LPC54608 (header file) + * @brief Device specific configuration file for LPC54618 (header file) * * Provides a system configuration function and a global variable that contains * the system frequency. It configures the device and initializes the oscillator * (PLL) that is part of the microcontroller device. */ -#ifndef _SYSTEM_LPC54608_H_ -#define _SYSTEM_LPC54608_H_ /**< Symbol preventing repeated inclusion */ +#ifndef _SYSTEM_LPC54618_H_ +#define _SYSTEM_LPC54618_H_ /**< Symbol preventing repeated inclusion */ #ifdef __cplusplus extern "C" { @@ -118,4 +118,4 @@ void SystemCoreClockUpdate (void); } #endif -#endif /* _SYSTEM_LPC54608_H_ */ +#endif /* _SYSTEM_LPC54618_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_adc.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c similarity index 96% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c index f239799c0da..90a32de9d36 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c @@ -984,8 +984,13 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) return m; } -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal( uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) { uint32_t nDivOutHz, fccoHz, multFccoDiv; @@ -1098,6 +1103,64 @@ static pll_error_t CLOCK_GetPllConfig( return kStatus_PLL_Success; } +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +uint32_t gPllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) ) + { + /* Hit the target in cache buffer. */ + pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = gPllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec; + pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec; + retErr = kStatus_PLL_Success; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + /* No cache or did not hit the cache. */ + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + if (kStatus_PLL_Success == retErr) + { + /* Cache the most recent calulation result into buffer. */ + gFinHzCache[gPllSetupCacheIdx] = finHz; + gFoutHzCache[gPllSetupCacheIdx] = foutHz; + + gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl; + gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec; + gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec; + gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec; + /* Update the index for next available buffer. */ + gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} /* Update SYSTEM PLL rate variable */ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h index 5093b03232d..a602dc9fba7 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_clock.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h @@ -59,6 +59,18 @@ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 #endif + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + /*! @brief Clock ip name array for ROM. */ #define ADC_CLOCKS \ { \ @@ -656,7 +668,7 @@ typedef enum _clock_attach_id kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), - kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), + kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_common.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_crc.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_ctimer.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_dmic_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_eeprom.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_emc.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_enet.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flashiap.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_flexcomm.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmc.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_fmeas.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gint.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_gpio.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2c_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c index 3b69be4772e..6501b169611 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c @@ -575,7 +575,7 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui i2s_dma_handle_t *i2sHandle = privateHandle->handle; I2S_Type *base = privateHandle->base; - if (!transferDone || (i2sHandle->state == kI2S_DmaStateIdle)) + if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) { return; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_i2s_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h similarity index 99% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h index 20c210d41ca..1c8cf763439 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_inputmux_connections.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016, NXP + * Copyright (c) 2013-2016, NXP Semiconductors. * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_iocon.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_iocon.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_lcdc.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mcan.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_mrt.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_otp.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_otp.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_pint.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h similarity index 95% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h index e36168283fe..ef1a5434bd2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_power.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h @@ -230,15 +230,6 @@ void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd); */ void POWER_SetVoltageForFreq(uint32_t freq); -/*! - * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency. - * - * @param freq - The desired frequency at which the part would like to operate, - * note that the voltage and flash wait states should be set before changing frequency - * @return none - */ -void POWER_SetVoltageForFreq(uint32_t freq); - /*! * @brief Power Library API to return the library version. * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_reset.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rit.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rng.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rng.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_rtc.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sctimer.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_sdif.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spi_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_spifi_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_usart_dma.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_utick.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.c rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h similarity index 100% rename from targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54608/drivers/fsl_wwdt.h rename to targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c index 01bd11da78d..d958c8d2b2d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/analogin_api.c @@ -38,6 +38,13 @@ void analogin_init(analogin_t *obj, PinName pin) uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; adc_config_t adc_config; + uint32_t reg; + uint32_t pin_number = pin & 0x1F; + uint8_t port_number = pin / 32; + + /* Clear the DIGIMODE bit */ + reg = IOCON->PIO[port_number][pin_number] & ~IOCON_PIO_DIGIMODE_MASK; + IOCON->PIO[port_number][pin_number] = reg; ADC_ClockPower_Configuration(); @@ -69,6 +76,7 @@ uint16_t analogin_read_u16(analogin_t *obj) adcConvSeqConfigStruct.interruptMode = kADC_InterruptForEachSequence; ADC_SetConvSeqAConfig(adc_addrs[instance], &adcConvSeqConfigStruct); + ADC_EnableConvSeqA(adc_addrs[instance], true); ADC_DoSoftwareTriggerConvSeqA(adc_addrs[instance]); /* Wait for the converter to be done. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c index 75d906156ca..bdacb00b6df 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/api/spi_api.c @@ -68,7 +68,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) if (slave) { /* Slave config */ SPI_SlaveGetDefaultConfig(&slave_config); - slave_config.dataWidth = (uint32_t)bits - 1; + slave_config.dataWidth = (spi_data_width_t)(bits - 1); slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; @@ -76,7 +76,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) } else { /* Master config */ SPI_MasterGetDefaultConfig(&master_config); - master_config.dataWidth = (uint32_t)bits - 1; + master_config.dataWidth = (spi_data_width_t)(bits - 1); master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; master_config.direction = kSPI_MsbFirst; @@ -154,7 +154,7 @@ int spi_master_write(spi_t *obj, int value) return rx_data & 0xffff; } -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) { int total = (tx_length > rx_length) ? tx_length : rx_length; diff --git a/targets/TARGET_NXP/mbed_rtx.h b/targets/TARGET_NXP/mbed_rtx.h index d2c4256b942..26e8c630a72 100644 --- a/targets/TARGET_NXP/mbed_rtx.h +++ b/targets/TARGET_NXP/mbed_rtx.h @@ -50,7 +50,7 @@ #define INITIAL_SP (0x02009000UL) #endif -#elif defined(TARGET_LPC1768) +#elif defined(TARGET_LPC1768) || defined(TARGET_LPC1769) #ifndef INITIAL_SP #define INITIAL_SP (0x10008000UL) @@ -86,7 +86,7 @@ #define INITIAL_SP (0x20010000UL) #endif -#elif defined(TARGET_LPC54608) +#elif defined(TARGET_LPC546XX) #ifndef INITIAL_SP #define INITIAL_SP (0x20028000UL) diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h index bcbafbe0002..2b5f3233438 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c.h @@ -48,7 +48,6 @@ #define I2C_SPEED_400K_AT_8MHZ (uint8_t)0x03 #define I2C_SPEED_400K_AT_16MHZ (uint8_t)0x08 - /* I2C commands */ #define I2C_CMD_NULL 0x00 #define I2C_CMD_WDAT0 0x10 @@ -93,7 +92,10 @@ #define I2C_API_STATUS_SUCCESS 0 #define PAD_REG_ADRS_BYTE_SIZE 4 -#define SEND_COMMAND(cmd) while(!I2C_FIFO_EMPTY); wait_us(1); obj->membase->CMD_REG = cmd; +// The wait_us(0) command is needed so the I2C state machines have enough +// time for data to settle across all clock domain crossings in their +// synchronizers, both directions. +#define SEND_COMMAND(cmd) wait_us(0); obj->membase->CMD_REG = cmd; wait_us(0); /** Init I2C device. * @details @@ -158,4 +160,4 @@ extern int32_t fI2cReadB(i2c_t *d, char *buf, int len); */ extern int32_t fI2cWriteB(i2c_t *d, const char *buf, int len); -#endif /* I2C_H_ */ \ No newline at end of file +#endif /* I2C_H_ */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c index cc57ed834d6..12845ed0695 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/i2c_api.c @@ -169,9 +169,7 @@ int i2c_byte_write(i2c_t *obj, int data) return Count; } - while(obj->membase->STATUS.WORD & I2C_STATUS_CMD_FIFO_OFL_BIT); /* Wait till command overflow ends */ - - if(obj->membase->STATUS.WORD & I2C_STATUS_BUS_ERR_BIT) { + if(I2C_BUS_ERR_CHECK) { /* Bus error means NAK received */ return 0; } else { @@ -180,4 +178,4 @@ int i2c_byte_write(i2c_t *obj, int data) } } -#endif /* DEVICE_I2C */ \ No newline at end of file +#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c index 1b3e5daf202..8ae4a9b9356 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c @@ -65,7 +65,6 @@ /* See i2c.h for details */ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) { - uint32_t clockDivisor; /* determine the I2C to use */ I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); @@ -93,9 +92,7 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) obj->membase->CR.BITS.I2C_APB_CD_EN = True; /* set default baud rate at 100k */ - clockDivisor = ((fClockGetPeriphClockfrequency() / 100000) >> 2) - 2; - obj->membase->CR.BITS.CD_VAL = (clockDivisor & I2C_CLOCKDIVEDER_VAL_MASK); - obj->membase->PRE_SCALE_REG = (clockDivisor & I2C_APB_CLK_DIVIDER_VAL_MASK) >> 5; /**< Zero pre-scale value not allowed */ + fI2cFrequency(obj, 100000); /* Cross bar setting */ pinmap_pinout(sda, PinMap_I2C_SDA); @@ -110,8 +107,8 @@ void fI2cInit(i2c_t *obj,PinName sda,PinName scl) PadReg_t *padRegScl = (PadReg_t*)(PADREG_BASE + (scl * PAD_REG_ADRS_BYTE_SIZE)); CLOCK_ENABLE(CLOCK_PAD); - padRegSda->PADIO0.BITS.POWER = 1; /* sda: Drive strength */ - padRegScl->PADIO0.BITS.POWER = 1; /* scl: Drive strength */ + padRegSda->PADIO0.BITS.POWER = 3; /* sda: Drive strength */ + padRegScl->PADIO0.BITS.POWER = 3; /* scl: Drive strength */ CLOCK_DISABLE(CLOCK_PAD); CLOCK_ENABLE(CLOCK_GPIO); @@ -160,7 +157,10 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) int32_t read = 0; while (read < len) { - /* Send read command */ + + while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ + + /* Send read command */ SEND_COMMAND(I2C_CMD_RDAT8); while(!RD_DATA_READY) { if (I2C_BUS_ERR_CHECK) { @@ -170,8 +170,8 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) } buf[read++] = obj->membase->RD_FIFO_REG; /**< Reading 'read FIFO register' will clear status register */ - if(!(read>=len)) { /* No ACK will be generated for the last read, upper level I2C protocol should generate */ - SEND_COMMAND(I2C_CMD_WDAT0); /* TODO based on requirement generate ACK or NACK Based on the requirement. */ + if(!(read>=len)) { + SEND_COMMAND(I2C_CMD_WDAT0); } else { /* No ack */ SEND_COMMAND(I2C_CMD_WDAT1); @@ -179,7 +179,7 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) /* check for FIFO underflow */ if(I2C_UFL_CHECK) { - return I2C_ERROR_NO_SLAVE; /* TODO No error available for this in i2c_api.h */ + return I2C_EVENT_ERROR; } if(I2C_BUS_ERR_CHECK) { /* Bus error */ @@ -196,8 +196,8 @@ int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len) int32_t write = 0; while (write < len) { - /* Send write command */ - SEND_COMMAND(I2C_CMD_WDAT8); + + while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ if(buf[write] == I2C_CMD_RDAT8) { /* SW work around to counter FSM issue. If the only command in the CMD FIFO is the WDAT8 command (data of 0x13) @@ -205,35 +205,27 @@ int32_t fI2cWriteB(i2c_t *obj, const char *buf, int len) RDAT8 command by the data FSM; resulting in an I2C bus error (NACK instead of an ACK). */ /* Send 0x13 bit wise */ SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT1); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT0); - SEND_COMMAND(I2C_CMD_WDAT1); - SEND_COMMAND(I2C_CMD_WDAT1); + write++; } else { /* Send data */ + SEND_COMMAND(I2C_CMD_WDAT8); SEND_COMMAND(buf[write++]); } - SEND_COMMAND(I2C_CMD_VRFY_ACK); /* TODO Verify ACK based on requirement, Do we need? */ + SEND_COMMAND(I2C_CMD_VRFY_ACK); if (I2C_BUS_ERR_CHECK) { /* Bus error */ return I2C_ERROR_BUS_BUSY; } - - while(FIFO_OFL_CHECK); /* Wait till command overflow ends */ } - return write; } -#endif /* DEVICE_I2C */ \ No newline at end of file +#endif /* DEVICE_I2C */ diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c index 75fa1b398bf..e0b07b9cbce 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_us_ticker_api.c @@ -130,7 +130,8 @@ uint32_t us_ticker_read() void us_ticker_fire_interrupt(void) { - NVIC_SetPendingIRQ(Tim0_IRQn); + us_ticker_target = 0; + NVIC_SetPendingIRQ(Tim1_IRQn); } /******************************************************************************* diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h index d3a8174ef98..27dc426d44b 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h @@ -626,7 +626,7 @@ typedef enum IRQn #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#include +#include #include "system_MBRZA1H.h" diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h new file mode 100644 index 00000000000..75193d4863c --- /dev/null +++ b/targets/TARGET_RENESAS/mbed_rtx.h @@ -0,0 +1,19 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_MBED_RTX_H +#define MBED_MBED_RTX_H + +#endif // MBED_MBED_RTX_H \ No newline at end of file diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar index 9ab2e81f22a..7aff54937f7 100644 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_peripheral_mbed_arm.ar differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar index fb75e4a5c70..980575aa8b6 100644 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/lib_wlan_mbed_arm.ar differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index 20a476ba541..4cf7eea1a8d 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -22,12 +22,10 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { *(i.mbedtls*) *libc.a (+RO) *rtx_*.o (+RO) - *lib_peripheral_mbed_arm.ar (+RO) } RW_IRAM1 +0 UNINIT FIXED { *rtl8195a_crypto.o(+RW) - ;*mbedtls*.o(+RW) *libc.a (+RW) *(.sdram.data*) *lib_peripheral_mbed_arm.ar (+RW) @@ -35,7 +33,6 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { RW_IRAM2 +0 UNINIT FIXED { *rtl8195a_crypto.o(+ZI, COMMON) - ;*mbedtls*.o(+ZI, COMMON) *libc.a (+ZI, COMMON) *(.bss.thread_stack_main) *lib_peripheral_mbed_arm.ar (+ZI, COMMON) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a index 352cdf86f64..2f6ab3f0c9b 100644 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a index b16999a7748..312525c6181 100644 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_wlan_mbed_gcc.a differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld index 6a99b066b57..ed3661c6af7 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld @@ -70,7 +70,6 @@ SECTIONS *rtl8195a_crypto.o (.text* .rodata*) *mbedtls*.o (.text* .rodata*) *libc.a: (.text* .rodata*) - *lib_peripheral_mbed_gcc.a: (.text*) } > SRAM1 .text.sram2 : diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a index 63c8d704d43..e906f7fd123 100644 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a index 17b29337882..a19c10c6367 100644 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a and b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_wlan_mbed_iar.a differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/librom.a b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/librom.a deleted file mode 100644 index 4978f11c11e..00000000000 Binary files a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/librom.a and /dev/null differ diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf index ed434c93555..abf86b9e16f 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf @@ -1,323 +1,212 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -//define symbol __ICFEDIT_intvec_start__ = 0x00000000; - -//include "main.icf"; +/* + * Copyright (c) 2013-2017 Realtek Semiconductor Corp. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF; -define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000; -define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF; -define symbol __ICFEDIT_region_ROM_USED_RAM_start__ = 0x10000000; -define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF; -//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090; -//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF; -if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) { - define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10007000; -} -if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) { - define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF; -} -define symbol __ICFEDIT_region_SDRAM_RAM_start__ = 0x30000000; -define symbol __ICFEDIT_region_SDRAM_RAM_end__ = 0x301FFFFF; - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x1000; -define symbol __ICFEDIT_size_heap__ = 0x19000; -/**** End of ICF editor section. ###ICF###*/ - +define symbol __SRAM_start__ = 0x10007000; +define symbol __SRAM_end__ = 0x1006FFFF; +define symbol __DTCM_start__ = 0x1FFF0000; +define symbol __DTCM_end__ = 0x1FFFFFFF; +define symbol __DRAM_start__ = 0x30000000; +define symbol __DRAM_end__ = 0x301FFFFF; define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__]; -define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__]; -//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__]; -define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__]; -define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -//initialize by copy { readwrite }; -//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application - -//do not initialize { section * }; - -//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table }; - - -/*place in RAM_region { readwrite, block CSTACK, block HEAP };*/ -//place in TCM_region { readwrite }; - -/**************************************** - * ROM Section config * - ****************************************/ -keep { section .rom }; -place at start of ROM_region { section .rom }; - -/**************************************** - * BD RAM Section config * - ****************************************/ -keep { section .ram_dedecated_vector_table* }; -define block .vector_table with fixed order{section .ram_dedecated_vector_table*}; - -keep { section .ram_user_define_irq_table* }; -define block .user_vector_table with fixed order{section .ram_user_define_irq_table*}; - -keep { section .ram_user_define_data_table* }; -define block .user_data_table with fixed order{section .ram_user_define_data_table*}; - -define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o, - section .hal.ram.bss* object hal_pinmux.o, - section .hal.ram.bss* object diag.o, - section .hal.ram.bss* object rtl8195a_ssi_rom.o, - section .hal.ram.bss* object rtl8195a_gpio.o, - section .hal.ram.bss*, - section .timer2_7_vector_table.data*, - section .infra.ram.bss*, - section .mon.ram.bss*, - section .wlan_ram_map* object rom_wlan_ram_map.o, - section .wlan_ram_map*, - section .libc.ram.bss*, - }; - -keep { section .start.ram.data* }; -define block .ram.start.table with fixed order{ section .start.ram.data* }; - -keep { section .image1.validate.rodata* }; -keep { section .infra.ram.data* }; -keep { section .timer.ram.data* }; -keep { section .hal.ram.data* }; -define block .ram_image1.data with fixed order{ section .image1.validate.rodata*, - section .infra.ram.data*, - section .timer.ram.data*, - section .cutb.ram.data*, - section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr - section .cutc.ram.data*, - section .hal.ram.data* - }; -define block .ram_image1.bss with fixed order{ //section .hal.flash.data*, - section .hal.sdrc.data* - }; - -define block .ram_image1.text with fixed order{ section .hal.ram.text*, - section .hal.sdrc.text*, - //section .text* object startup.o, - section .infra.ram.text*, - }; - -define block IMAGE1 with fixed order { section LOADER }; -define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text }; - -place at start of ROM_USED_RAM_region { - block .vector_table, - block .user_vector_table, - block .user_data_table, - block .rom.bss, - block IMAGE1 - }; - - -keep { section .image2.ram.data* }; -define block .image2.start.table1 with fixed order{ section .image2.ram.data* }; - -keep { section .image2.validate.rodata*, section .custom.validate.rodata* }; -define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* }; - -define block SHT$$PREINIT_ARRAY { preinit_array }; -define block SHT$$INIT_ARRAY { init_array }; -define block CPP_INIT with alignment = 8, fixed order { - block SHT$$PREINIT_ARRAY, - block SHT$$INIT_ARRAY - }; -define block FPB_REMAP with alignment = 256,fixed order { - section .fpb.remap* - }; - -define block MBEDTLS_TEXT with alignment = 8, fixed order{ - section .text* object aes.o, - section .text* object aesni.o, - section .text* object arc4.o, - section .text* object asn1parse.o, - section .text* object asn1write.o, - section .text* object base64.o, - section .text* object bignum.o, - section .text* object blowfish.o, - section .text* object camellia.o, - section .text* object ccm.o, - section .text* object certs.o, - section .text* object cipher.o, - section .text* object cipher_wrap.o, - section .text* object cmac.o, - section .text* object ctr_drbg.o, - section .text* object debug.o, - section .text* object des.o, - section .text* object dhm.o, - section .text* object ecdh.o, - section .text* object ecdsa.o, - section .text* object ecjpake.o, - section .text* object ecp.o, - section .text* object ecp_curves.o, - section .text* object entropy.o, - section .text* object entropy_poll.o, - section .text* object error.o, - section .text* object gcm.o, - section .text* object havege.o, - section .text* object hmac_drbg.o, - section .text* object md.o, - section .text* object md2.o, - section .text* object md4.o, - section .text* object md5.o, - section .text* object md_wrap.o, - section .text* object memory_buffer_alloc.o, - section .text* object net_sockets.o, - section .text* object oid.o, - section .text* object padlock.o, - section .text* object pem.o, - section .text* object pk.o, - section .text* object pk_wrap.o, - section .text* object pkcs11.o, - section .text* object pkcs12.o, - section .text* object pkcs5.o, - section .text* object pkparse.o, - section .text* object pkwrite.o, - section .text* object platform.o, - section .text* object ripemd160.o, - section .text* object rsa.o, - section .text* object sha1.o, - section .text* object sha256.o, - section .text* object sha512.o, - section .text* object ssl_cache.o, - section .text* object ssl_ciphersuites.o, - section .text* object ssl_cli.o, - section .text* object ssl_cookie.o, - section .text* object ssl_srv.o, - section .text* object ssl_ticket.o, - section .text* object ssl_tls.o, - section .text* object threading.o, - section .text* object timing.o, - section .text* object version.o, - section .text* object version_features.o, - section .text* object x509.o, - section .text* object x509_create.o, - section .text* object x509_crl.o, - section .text* object x509_crt.o, - section .text* object x509_csr.o, - section .text* object x509write_crt.o, - section .text* object x509write_csr.o, - section .text* object xtea.o, - }; - -define block .sram1.text with fixed order { - block MBEDTLS_TEXT, - section .text* object lib_peripheral_mbed_iar.a, - }; - -define block .sram2.text with fixed order { - block .image2.start.table1, - block .image2.start.table2, - section .mon.ram.text*, - section .hal.flash.text*, - section .hal.sdrc.text*, - section .hal.gpio.text*, - section .text*, - section .infra.ram.start*, - section .rodata*, - }; - -define block .sram2.data with fixed order { - //section .infra.ram.start*, - //section .rodata*, - //section .wlan.text, - //section .wps.text, - section CODE, - //section .otg.rom.text, - section Veneer object startup.o, - section __DLIB_PERTHREAD, - section .iar.dynexit*, - block CPP_INIT, - //section .mdns.text - }; -define block .ram.data with fixed order { - readwrite, readonly, - section .data*, - section .wlan.data, - section .wps.data, - section DATA, - section .ram.otg.data.a, - section .iar.init_table, - //section .mdns.data, - //section .data* object lib_peripheral_mbed_iar.a, - }; - -define block .ram.bss with fixed order { - section .bss*, - section COMMON, - section .bdsram.data*, - }; - -define block IMAGE2 with fixed order { - block .sram1.text, - block .ram.data, - block .ram.bss - }; - -define block .bf_data with fixed order{ section .bfsram.data* }; -define block .heap with fixed order{ section .heap* }; -define block .stack_dummy with fixed order { section .stack }; -place at start of BD_RAM_region { - block IMAGE2, - //block IMAGE1_DBG, - //block .ram.bss, - //block .bf_data, - }; - -place at end of BD_RAM_region { - block .bf_data, - block HEAP, - }; - -define block SDRAM with fixed order { - block .sram2.text, - block .sram2.data, - section .sdram.text*, - section .sdram.data*, - section .mdns.text*, - section .mdns.data*, - block FPB_REMAP - }; -define block SDRBSS with fixed order{ - section .sdram.bss* - }; - -place at start of SDRAM_RAM_region { - block SDRAM, - block SDRBSS, - //block IMAGE1_DBG - }; - - -/* TCM placement */ -define overlay TCM_overlay { - section .tcm.heap, - section .bss object lwip_mem.o, - section .bss object lwip_memp.o, - block .heap, - block .stack_dummy - }; -/* dummy code placement */ -define overlay TCM_overlay { block IMAGE1_DBG }; -place at start of TCM_region { overlay TCM_overlay }; -place at end of TCM_region { block CSTACK}; - -define exported symbol __rom_bss_start__ = 0x10000300; // use in rom -define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom -define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom -define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code -define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library - -define exported symbol __sdio_rom_bss_start__ = 0x1006D000; -define exported symbol __sdio_rom_bss_end__ = 0x1006fa10; +define region TCM_region = mem:[from __DTCM_start__ to __DTCM_end__]; +define region RAM_region = mem:[from __SRAM_start__ to __SRAM_end__] | + mem:[from __DRAM_start__ to __DRAM_end__]; + +define block CSTACK with alignment = 8, size = 0x1000 { }; +define block HEAP with alignment = 8, size = 0x19000 { }; + +do not initialize { section .noinit }; + +/** + IMAGE2 +**/ +keep { + section .image2.ram.data*, + section .image2.validate.rodata*, +}; + +define block .image2.table with fixed order { + section .image2.ram.data*, + section .image2.validate.rodata*, +}; + +define block FPB_REMAP with alignment = 256, fixed order { + section .fpb.remap* +}; + +define block .text.mbedtls { + readonly object aes.o, + readonly object aesni.o, + readonly object arc4.o, + readonly object asn1parse.o, + readonly object asn1write.o, + readonly object base64.o, + readonly object bignum.o, + readonly object blowfish.o, + readonly object camellia.o, + readonly object ccm.o, + readonly object certs.o, + readonly object cipher.o, + readonly object cipher_wrap.o, + readonly object cmac.o, + readonly object ctr_drbg.o, + readonly object debug.o, + readonly object des.o, + readonly object dhm.o, + readonly object ecdh.o, + readonly object ecdsa.o, + readonly object ecjpake.o, + readonly object ecp.o, + readonly object ecp_curves.o, + readonly object entropy.o, + readonly object entropy_poll.o, + readonly object error.o, + readonly object gcm.o, + readonly object havege.o, + readonly object hmac_drbg.o, + readonly object md.o, + readonly object md2.o, + readonly object md4.o, + readonly object md5.o, + readonly object md_wrap.o, + readonly object memory_buffer_alloc.o, + readonly object net_sockets.o, + readonly object oid.o, + readonly object padlock.o, + readonly object pem.o, + readonly object pk.o, + readonly object pk_wrap.o, + readonly object pkcs11.o, + readonly object pkcs12.o, + readonly object pkcs5.o, + readonly object pkparse.o, + readonly object pkwrite.o, + readonly object platform.o, + readonly object ripemd160.o, + readonly object rsa.o, + readonly object sha1.o, + readonly object sha256.o, + readonly object sha512.o, + readonly object ssl_cache.o, + readonly object ssl_ciphersuites.o, + readonly object ssl_cli.o, + readonly object ssl_cookie.o, + readonly object ssl_srv.o, + readonly object ssl_ticket.o, + readonly object ssl_tls.o, + readonly object threading.o, + readonly object timing.o, + readonly object version.o, + readonly object version_features.o, + readonly object x509.o, + readonly object x509_create.o, + readonly object x509_crl.o, + readonly object x509_crt.o, + readonly object x509_csr.o, + readonly object x509write_crt.o, + readonly object x509write_csr.o, + readonly object xtea.o, +}; + +define block .text.sram { + readonly object rtl8195a_crypto.o, + readonly object vector_table_M.o, + section .text.sram*, +}; + +define block .text.dram { + section .text.dram*, + section .text*, + section .rodata*, + section .sdram.text*, + section .mdns.text*, + section CODE, +}; + +define block .data.sram { + readwrite object rtl8195a_crypto.o, + readwrite object vector_table_M.o, + readwrite object lib_peripheral_mbed_iar.a, + section .data.os.*, + section .data.sram*, + section .wlan.data, + section .wps.data, + section .ram.otg.data.a, + section .bfsram.data*, +}; + +define block .data.dram { + section .data*, + section .data.dram*, + section .sdram.data*, + section .mdns.data*, + section .iar.init_table, + section .iar.dynexit*, + section DATA, + section __DLIB_PERTHREAD, +}; + +define block .data.dtcm { + section .data.dtcm*, +}; + +define block .bss.sram { + zeroinit object rtl8195a_crypto.o, + section .bss.os.*, + section .bss.sram*, + section .bdsram.data*, +}; + +define block .bss.dram { + zeroinit, + section .sdram.bss*, +}; + +define block .bss.dtcm { + zeroinit object lwip_mem.o, + zeroinit object lwip_memp.o, + section .bss.dtcm*, +}; + +place in TCM_region { + section .tcm.heap, + block .data.dtcm, + block .bss.dtcm, +}; + +place in RAM_region { + readonly, + block .text.sram, + block .text.mbedtls, + readwrite, + block .data.sram, + block .bss.sram, + block HEAP, + block CSTACK, + readonly, + block .image2.table, + block .text.dram, + readwrite, + block .data.dram, + block .bss.dram, + block FPB_REMAP, +}; + +include "rtl8195a_rom.h"; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h new file mode 100644 index 00000000000..d9a7b284d9d --- /dev/null +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a_rom.h @@ -0,0 +1,740 @@ +define exported symbol __vectors_table = 0x00000000; +define exported symbol Reset_Handler = 0x00000101; +define exported symbol NMI_Handler = 0x00000109; +define exported symbol HardFault_Handler = 0x0000010d; +define exported symbol MemManage_Handler = 0x00000121; +define exported symbol BusFault_Handler = 0x00000125; +define exported symbol UsageFault_Handler = 0x00000129; +define exported symbol HalLogUartInit = 0x00000201; +define exported symbol HalSerialPutcRtl8195a = 0x000002d9; +define exported symbol HalSerialGetcRtl8195a = 0x00000309; +define exported symbol HalSerialGetIsrEnRegRtl8195a = 0x00000329; +define exported symbol HalSerialSetIrqEnRegRtl8195a = 0x00000335; +define exported symbol HalCpuClkConfig = 0x00000341; +define exported symbol HalGetCpuClk = 0x00000355; +define exported symbol HalRomInfo = 0x0000039d; +define exported symbol HalGetRomInfo = 0x000003b5; +define exported symbol HalResetVsr = 0x000003c5; +define exported symbol HalDelayUs = 0x00000899; +define exported symbol HalNMIHandler = 0x000008e1; +define exported symbol HalHardFaultHandler = 0x00000911; +define exported symbol HalMemManageHandler = 0x00000c09; +define exported symbol HalBusFaultHandler = 0x00000c39; +define exported symbol HalUsageFaultHandler = 0x00000c69; +define exported symbol HalUart0PinCtrlRtl8195A = 0x00000cfd; +define exported symbol HalUart1PinCtrlRtl8195A = 0x00000dc9; +define exported symbol HalUart2PinCtrlRtl8195A = 0x00000e9d; +define exported symbol HalSPI0PinCtrlRtl8195A = 0x00000f75; +define exported symbol HalSPI1PinCtrlRtl8195A = 0x00001015; +define exported symbol HalSPI2PinCtrlRtl8195A = 0x000010e5; +define exported symbol HalSPI0MCSPinCtrlRtl8195A = 0x000011b5; +define exported symbol HalI2C0PinCtrlRtl8195A = 0x00001275; +define exported symbol HalI2C1PinCtrlRtl8195A = 0x00001381; +define exported symbol HalI2C2PinCtrlRtl8195A = 0x00001459; +define exported symbol HalI2C3PinCtrlRtl8195A = 0x00001529; +define exported symbol HalI2S0PinCtrlRtl8195A = 0x00001639; +define exported symbol HalI2S1PinCtrlRtl8195A = 0x0000176d; +define exported symbol HalPCM0PinCtrlRtl8195A = 0x00001845; +define exported symbol HalPCM1PinCtrlRtl8195A = 0x00001949; +define exported symbol HalSDIODPinCtrlRtl8195A = 0x00001a1d; +define exported symbol HalSDIOHPinCtrlRtl8195A = 0x00001a6d; +define exported symbol HalMIIPinCtrlRtl8195A = 0x00001ab9; +define exported symbol HalWLLEDPinCtrlRtl8195A = 0x00001b51; +define exported symbol HalWLANT0PinCtrlRtl8195A = 0x00001c0d; +define exported symbol HalWLANT1PinCtrlRtl8195A = 0x00001c61; +define exported symbol HalWLBTCOEXPinCtrlRtl8195A = 0x00001cb5; +define exported symbol HalWLBTCMDPinCtrlRtl8195A = 0x00001d05; +define exported symbol HalNFCPinCtrlRtl8195A = 0x00001d59; +define exported symbol HalPWM0PinCtrlRtl8195A = 0x00001da9; +define exported symbol HalPWM1PinCtrlRtl8195A = 0x00001ead; +define exported symbol HalPWM2PinCtrlRtl8195A = 0x00001fb5; +define exported symbol HalPWM3PinCtrlRtl8195A = 0x000020b1; +define exported symbol HalETE0PinCtrlRtl8195A = 0x000021b9; +define exported symbol HalETE1PinCtrlRtl8195A = 0x000022c1; +define exported symbol HalETE2PinCtrlRtl8195A = 0x000023c9; +define exported symbol HalETE3PinCtrlRtl8195A = 0x000024d1; +define exported symbol HalEGTIMPinCtrlRtl8195A = 0x000025d9; +define exported symbol HalSPIFlashPinCtrlRtl8195A = 0x00002679; +define exported symbol HalSDRPinCtrlRtl8195A = 0x00002725; +define exported symbol HalJTAGPinCtrlRtl8195A = 0x0000280d; +define exported symbol HalTRACEPinCtrlRtl8195A = 0x00002861; +define exported symbol HalLOGUartPinCtrlRtl8195A = 0x000028b9; +define exported symbol HalLOGUartIRPinCtrlRtl8195A = 0x0000291d; +define exported symbol HalSICPinCtrlRtl8195A = 0x00002981; +define exported symbol HalEEPROMPinCtrlRtl8195A = 0x000029d9; +define exported symbol HalDEBUGPinCtrlRtl8195A = 0x00002a31; +define exported symbol HalPinCtrlRtl8195A = 0x00002b39; +define exported symbol SpicRxCmdRtl8195A = 0x00002e5d; +define exported symbol SpicWaitBusyDoneRtl8195A = 0x00002ea5; +define exported symbol SpicGetFlashStatusRtl8195A = 0x00002eb5; +define exported symbol SpicWaitWipDoneRtl8195A = 0x00002f55; +define exported symbol SpicTxCmdRtl8195A = 0x00002f6d; +define exported symbol SpicSetFlashStatusRtl8195A = 0x00002fc1; +define exported symbol SpicCmpDataForCalibrationRtl8195A = 0x00003049; +define exported symbol SpicLoadInitParaFromClockRtl8195A = 0x00003081; +define exported symbol SpicInitRtl8195A = 0x000030e5; +define exported symbol SpicEraseFlashRtl8195A = 0x000031bd; +define exported symbol SpiFlashApp = 0x00003279; +define exported symbol HalPeripheralIntrHandle = 0x000033b5; +define exported symbol HalSysOnIntrHandle = 0x00003439; +define exported symbol HalWdgIntrHandle = 0x00003485; +define exported symbol HalTimer0IntrHandle = 0x000034d5; +define exported symbol HalTimer1IntrHandle = 0x00003525; +define exported symbol HalI2C3IntrHandle = 0x00003575; +define exported symbol HalTimer2To7IntrHandle = 0x000035c5; +define exported symbol HalSpi0IntrHandle = 0x00003615; +define exported symbol HalGpioIntrHandle = 0x00003665; +define exported symbol HalUart0IntrHandle = 0x000036b5; +define exported symbol HalSpiFlashIntrHandle = 0x00003705; +define exported symbol HalUsbOtgIntrHandle = 0x00003755; +define exported symbol HalSdioHostIntrHandle = 0x000037a5; +define exported symbol HalI2s0OrPcm0IntrHandle = 0x000037f5; +define exported symbol HalI2s1OrPcm1IntrHandle = 0x00003845; +define exported symbol HalWlDmaIntrHandle = 0x00003895; +define exported symbol HalWlProtocolIntrHandle = 0x000038e5; +define exported symbol HalCryptoIntrHandle = 0x00003935; +define exported symbol HalGmacIntrHandle = 0x00003985; +define exported symbol HalGdma0Ch0IntrHandle = 0x000039d5; +define exported symbol HalGdma0Ch1IntrHandle = 0x00003a25; +define exported symbol HalGdma0Ch2IntrHandle = 0x00003a75; +define exported symbol HalGdma0Ch3IntrHandle = 0x00003ac5; +define exported symbol HalGdma0Ch4IntrHandle = 0x00003b15; +define exported symbol HalGdma0Ch5IntrHandle = 0x00003b65; +define exported symbol HalGdma1Ch0IntrHandle = 0x00003bb5; +define exported symbol HalGdma1Ch1IntrHandle = 0x00003c05; +define exported symbol HalGdma1Ch2IntrHandle = 0x00003c55; +define exported symbol HalGdma1Ch3IntrHandle = 0x00003ca5; +define exported symbol HalGdma1Ch4IntrHandle = 0x00003cf5; +define exported symbol HalGdma1Ch5IntrHandle = 0x00003d45; +define exported symbol HalSdioDeviceIntrHandle = 0x00003d95; +define exported symbol VectorTableInitRtl8195A = 0x00003de5; +define exported symbol VectorTableInitForOSRtl8195A = 0x00004019; +define exported symbol VectorIrqRegisterRtl8195A = 0x00004029; +define exported symbol VectorIrqUnRegisterRtl8195A = 0x00004091; +define exported symbol VectorIrqEnRtl8195A = 0x000040f1; +define exported symbol VectorIrqDisRtl8195A = 0x0000418d; +define exported symbol _UartRxDmaIrqHandle = 0x0000422d; +define exported symbol HalRuartPutCRtl8195a = 0x00004281; +define exported symbol HalRuartGetCRtl8195a = 0x0000429d; +define exported symbol HalRuartRTSCtrlRtl8195a = 0x000042bd; +define exported symbol HalRuartGetDebugValueRtl8195a = 0x000042e1; +define exported symbol HalRuartGetIMRRtl8195a = 0x000043e1; +define exported symbol HalRuartSetIMRRtl8195a = 0x0000442d; +define exported symbol _UartIrqHandle = 0x00004465; +define exported symbol HalRuartDmaInitRtl8195a = 0x00004681; +define exported symbol HalRuartIntDisableRtl8195a = 0x00004845; +define exported symbol HalRuartDeInitRtl8195a = 0x00004855; +define exported symbol HalRuartIntEnableRtl8195a = 0x00004985; +define exported symbol _UartTxDmaIrqHandle = 0x00004995; +define exported symbol HalRuartRegIrqRtl8195a = 0x000049d1; +define exported symbol HalRuartAdapterLoadDefRtl8195a = 0x00004a4d; +define exported symbol HalRuartTxGdmaLoadDefRtl8195a = 0x00004add; +define exported symbol HalRuartRxGdmaLoadDefRtl8195a = 0x00004bc9; +define exported symbol RuartLock = 0x00004cc9; +define exported symbol RuartUnLock = 0x00004ced; +define exported symbol HalRuartIntSendRtl8195a = 0x00004d09; +define exported symbol HalRuartDmaSendRtl8195a = 0x00004e35; +define exported symbol HalRuartStopSendRtl8195a = 0x00004f89; +define exported symbol HalRuartIntRecvRtl8195a = 0x0000504d; +define exported symbol HalRuartDmaRecvRtl8195a = 0x000051ad; +define exported symbol HalRuartStopRecvRtl8195a = 0x000052cd; +define exported symbol RuartIsTimeout = 0x00005385; +define exported symbol HalRuartSendRtl8195a = 0x000053b1; +define exported symbol HalRuartRecvRtl8195a = 0x00005599; +define exported symbol RuartResetRxFifoRtl8195a = 0x00005751; +define exported symbol HalRuartResetRxFifoRtl8195a = 0x00005775; +define exported symbol HalRuartInitRtl8195a = 0x00005829; +define exported symbol HalGdmaOnOffRtl8195a = 0x00005df1; +define exported symbol HalGdmaChIsrEnAndDisRtl8195a = 0x00005e0d; +define exported symbol HalGdmaChEnRtl8195a = 0x00005e51; +define exported symbol HalGdmaChDisRtl8195a = 0x00005e6d; +define exported symbol HalGdamChInitRtl8195a = 0x00005e91; +define exported symbol HalGdmaChSetingRtl8195a = 0x00005ebd; +define exported symbol HalGdmaChBlockSetingRtl8195a = 0x000060dd; +define exported symbol HalGdmaChIsrCleanRtl8195a = 0x00006419; +define exported symbol HalGdmaChCleanAutoSrcRtl8195a = 0x000064a1; +define exported symbol HalGdmaChCleanAutoDstRtl8195a = 0x00006501; +define exported symbol HalEFUSEPowerSwitch8195AROM = 0x00006561; +define exported symbol HALEFUSEOneByteReadROM = 0x000065f9; +define exported symbol HALEFUSEOneByteWriteROM = 0x00006699; +define exported symbol __rtl_memcmpb_v1_00 = 0x0000681d; +define exported symbol __rtl_random_v1_00 = 0x00006861; +define exported symbol __rtl_align_to_be32_v1_00 = 0x00006881; +define exported symbol __rtl_memsetw_v1_00 = 0x00006899; +define exported symbol __rtl_memsetb_v1_00 = 0x000068ad; +define exported symbol __rtl_memcpyw_v1_00 = 0x000068bd; +define exported symbol __rtl_memcpyb_v1_00 = 0x000068dd; +define exported symbol __rtl_memDump_v1_00 = 0x000068f5; +define exported symbol __rtl_AES_set_encrypt_key = 0x00006901; +define exported symbol __rtl_cryptoEngine_AES_set_decrypt_key = 0x00006c11; +define exported symbol __rtl_cryptoEngine_set_security_mode_v1_00 = 0x00006c95; +define exported symbol __rtl_cryptoEngine_init_v1_00 = 0x00006ea9; +define exported symbol __rtl_cryptoEngine_exit_v1_00 = 0x00007055; +define exported symbol __rtl_cryptoEngine_reset_v1_00 = 0x000070b1; +define exported symbol __rtl_cryptoEngine_v1_00 = 0x000070ed; +define exported symbol __rtl_crypto_cipher_init_v1_00 = 0x00007c69; +define exported symbol __rtl_crypto_cipher_encrypt_v1_00 = 0x00007c89; +define exported symbol __rtl_crypto_cipher_decrypt_v1_00 = 0x00007cad; +define exported symbol HalSsiPinmuxEnableRtl8195a = 0x00007cd5; +define exported symbol HalSsiEnableRtl8195a = 0x00007e45; +define exported symbol HalSsiDisableRtl8195a = 0x00007ef9; +define exported symbol HalSsiLoadSettingRtl8195a = 0x00007fad; +define exported symbol HalSsiSetInterruptMaskRtl8195a = 0x00008521; +define exported symbol HalSsiGetInterruptMaskRtl8195a = 0x000085c9; +define exported symbol HalSsiSetSclkPolarityRtl8195a = 0x0000863d; +define exported symbol HalSsiSetSclkPhaseRtl8195a = 0x00008715; +define exported symbol HalSsiWriteRtl8195a = 0x000087e9; +define exported symbol HalSsiSetDeviceRoleRtl8195a = 0x00008861; +define exported symbol HalSsiSetRxFifoThresholdLevelRtl8195a = 0x000088c9; +define exported symbol HalSsiSetTxFifoThresholdLevelRtl8195a = 0x00008941; +define exported symbol HalSsiReadRtl8195a = 0x000089b9; +define exported symbol HalSsiGetRxFifoLevelRtl8195a = 0x00008a2d; +define exported symbol HalSsiGetTxFifoLevelRtl8195a = 0x00008aa5; +define exported symbol HalSsiGetStatusRtl8195a = 0x00008b1d; +define exported symbol HalSsiWriteableRtl8195a = 0x00008b91; +define exported symbol HalSsiReadableRtl8195a = 0x00008c09; +define exported symbol HalSsiBusyRtl8195a = 0x00008c81; +define exported symbol HalSsiReadInterruptRtl8195a = 0x00008cf9; +define exported symbol HalSsiWriteInterruptRtl8195a = 0x00008efd; +define exported symbol HalSsiSetSlaveEnableRegisterRtl8195a = 0x00009009; +define exported symbol HalSsiGetInterruptStatusRtl8195a = 0x000090d9; +define exported symbol HalSsiInterruptEnableRtl8195a = 0x0000914d; +define exported symbol HalSsiInterruptDisableRtl8195a = 0x00009299; +define exported symbol HalSsiGetRawInterruptStatusRtl8195a = 0x000093e9; +define exported symbol HalSsiGetSlaveEnableRegisterRtl8195a = 0x0000945d; +define exported symbol HalSsiInitRtl8195a = 0x000094d1; +define exported symbol _SsiReadInterrupt = 0x00009ba5; +define exported symbol _SsiWriteInterrupt = 0x00009db1; +define exported symbol _SsiIrqHandle = 0x00009eb1; +define exported symbol HalI2CWrite32 = 0x0000a061; +define exported symbol HalI2CRead32 = 0x0000a09d; +define exported symbol HalI2CDeInit8195a = 0x0000a0dd; +define exported symbol HalI2CSendRtl8195a = 0x0000a1f1; +define exported symbol HalI2CReceiveRtl8195a = 0x0000a25d; +define exported symbol HalI2CEnableRtl8195a = 0x0000a271; +define exported symbol HalI2CIntrCtrl8195a = 0x0000a389; +define exported symbol HalI2CReadRegRtl8195a = 0x0000a3a1; +define exported symbol HalI2CWriteRegRtl8195a = 0x0000a3b1; +define exported symbol HalI2CSetCLKRtl8195a = 0x0000a3c5; +define exported symbol HalI2CMassSendRtl8195a = 0x0000a6e9; +define exported symbol HalI2CClrIntrRtl8195a = 0x0000a749; +define exported symbol HalI2CClrAllIntrRtl8195a = 0x0000a761; +define exported symbol HalI2CInit8195a = 0x0000a775; +define exported symbol HalI2CDMACtrl8195a = 0x0000aa31; +define exported symbol RtkI2CIoCtrl = 0x0000aa61; +define exported symbol RtkI2CPowerCtrl = 0x0000aa65; +define exported symbol HalI2COpInit = 0x0000aa69; +define exported symbol I2CIsTimeout = 0x0000ac65; +define exported symbol I2CTXGDMAISRHandle = 0x0000b435; +define exported symbol I2CRXGDMAISRHandle = 0x0000b4c1; +define exported symbol RtkI2CIrqInit = 0x0000b54d; +define exported symbol RtkI2CIrqDeInit = 0x0000b611; +define exported symbol RtkI2CPinMuxInit = 0x0000b675; +define exported symbol RtkI2CPinMuxDeInit = 0x0000b7c9; +define exported symbol RtkI2CDMAInit = 0x0000b955; +define exported symbol RtkI2CInit = 0x0000bc95; +define exported symbol RtkI2CDMADeInit = 0x0000bdad; +define exported symbol RtkI2CDeInit = 0x0000be4d; +define exported symbol RtkI2CSendUserAddr = 0x0000bee5; +define exported symbol RtkI2CSend = 0x0000c07d; +define exported symbol RtkI2CLoadDefault = 0x0000ce51; +define exported symbol RtkSalI2COpInit = 0x0000cf21; +define exported symbol HalI2SWrite32 = 0x0000cf65; +define exported symbol HalI2SRead32 = 0x0000cf85; +define exported symbol HalI2SDeInitRtl8195a = 0x0000cfa9; +define exported symbol HalI2STxRtl8195a = 0x0000cfc9; +define exported symbol HalI2SRxRtl8195a = 0x0000d011; +define exported symbol HalI2SEnableRtl8195a = 0x0000d05d; +define exported symbol HalI2SIntrCtrlRtl8195a = 0x0000d0b1; +define exported symbol HalI2SReadRegRtl8195a = 0x0000d0d1; +define exported symbol HalI2SClrIntrRtl8195a = 0x0000d0dd; +define exported symbol HalI2SClrAllIntrRtl8195a = 0x0000d0fd; +define exported symbol HalI2SInitRtl8195a = 0x0000d11d; +define exported symbol GPIO_GetIPPinName_8195a = 0x0000d2e5; +define exported symbol GPIO_GetChipPinName_8195a = 0x0000d331; +define exported symbol GPIO_PullCtrl_8195a = 0x0000d39d; +define exported symbol GPIO_FuncOn_8195a = 0x0000d421; +define exported symbol GPIO_FuncOff_8195a = 0x0000d481; +define exported symbol GPIO_Int_Mask_8195a = 0x0000d4e9; +define exported symbol GPIO_Int_SetType_8195a = 0x0000d511; +define exported symbol HAL_GPIO_IrqHandler_8195a = 0x0000d5fd; +define exported symbol HAL_GPIO_MbedIrqHandler_8195a = 0x0000d645; +define exported symbol HAL_GPIO_UserIrqHandler_8195a = 0x0000d6a1; +define exported symbol HAL_GPIO_IntCtrl_8195a = 0x0000d6cd; +define exported symbol HAL_GPIO_Init_8195a = 0x0000d805; +define exported symbol HAL_GPIO_DeInit_8195a = 0x0000dac1; +define exported symbol HAL_GPIO_ReadPin_8195a = 0x0000dbd1; +define exported symbol HAL_GPIO_WritePin_8195a = 0x0000dc91; +define exported symbol HAL_GPIO_RegIrq_8195a = 0x0000ddad; +define exported symbol HAL_GPIO_UnRegIrq_8195a = 0x0000ddf5; +define exported symbol HAL_GPIO_UserRegIrq_8195a = 0x0000de15; +define exported symbol HAL_GPIO_UserUnRegIrq_8195a = 0x0000def9; +define exported symbol HAL_GPIO_MaskIrq_8195a = 0x0000dfc1; +define exported symbol HAL_GPIO_UnMaskIrq_8195a = 0x0000e061; +define exported symbol HAL_GPIO_IntDebounce_8195a = 0x0000e101; +define exported symbol HAL_GPIO_GetIPPinName_8195a = 0x0000e1c1; +define exported symbol HAL_GPIO_PullCtrl_8195a = 0x0000e1c9; +define exported symbol DumpForOneBytes = 0x0000e259; +define exported symbol CmdRomHelp = 0x0000e419; +define exported symbol CmdWriteWord = 0x0000e491; +define exported symbol CmdDumpHelfWord = 0x0000e505; +define exported symbol CmdDumpWord = 0x0000e5f1; +define exported symbol CmdDumpByte = 0x0000e6f5; +define exported symbol CmdSpiFlashTool = 0x0000e751; +define exported symbol GetRomCmdNum = 0x0000e7a9; +define exported symbol CmdWriteByte = 0x0000e7ad; +define exported symbol Isspace = 0x0000e7ed; +define exported symbol Strtoul = 0x0000e801; +define exported symbol ArrayInitialize = 0x0000e8b1; +define exported symbol GetArgc = 0x0000e8c9; +define exported symbol GetArgv = 0x0000e8f9; +define exported symbol UartLogCmdExecute = 0x0000e95d; +define exported symbol UartLogShowBackSpace = 0x0000e9fd; +define exported symbol UartLogRecallOldCmd = 0x0000ea39; +define exported symbol UartLogHistoryCmd = 0x0000ea71; +define exported symbol UartLogCmdChk = 0x0000eadd; +define exported symbol UartLogIrqHandle = 0x0000ebf5; +define exported symbol RtlConsolInit = 0x0000ecc5; +define exported symbol RtlConsolTaskRom = 0x0000ed49; +define exported symbol RtlExitConsol = 0x0000ed79; +define exported symbol RtlConsolRom = 0x0000edcd; +define exported symbol HalTimerOpInit = 0x0000ee0d; +define exported symbol HalTimerIrq2To7Handle = 0x0000ee59; +define exported symbol HalGetTimerIdRtl8195a = 0x0000ef09; +define exported symbol HalTimerInitRtl8195a = 0x0000ef3d; +define exported symbol HalTimerDisRtl8195a = 0x0000f069; +define exported symbol HalTimerEnRtl8195a = 0x0000f089; +define exported symbol HalTimerReadCountRtl8195a = 0x0000f0a9; +define exported symbol HalTimerIrqClearRtl8195a = 0x0000f0bd; +define exported symbol HalTimerDumpRegRtl8195a = 0x0000f0d1; +define exported symbol VSprintf = 0x0000f129; +define exported symbol DiagPrintf = 0x0000f39d; +define exported symbol DiagSPrintf = 0x0000f3b9; +define exported symbol DiagSnPrintf = 0x0000f3d1; +define exported symbol prvDiagPrintf = 0x0000f3ed; +define exported symbol prvDiagSPrintf = 0x0000f40d; +define exported symbol _memcmp = 0x0000f429; +define exported symbol __memcmp = 0x0000f429; +define exported symbol _memcpy = 0x0000f465; +define exported symbol __memcpy = 0x0000f465; +define exported symbol _memset = 0x0000f511; +define exported symbol __memset = 0x0000f511; +define exported symbol Rand = 0x0000f585; +define exported symbol _strncpy = 0x0000f60d; +define exported symbol __strncpy = 0x0000f60d; +define exported symbol _strcpy = 0x0000f629; +define exported symbol __strcpy = 0x0000f629; +define exported symbol prvStrCpy = 0x0000f639; +define exported symbol _strlen = 0x0000f651; +define exported symbol __strlen = 0x0000f651; +define exported symbol _strnlen = 0x0000f669; +define exported symbol __strnlen = 0x0000f669; +define exported symbol prvStrLen = 0x0000f699; +define exported symbol _strcmp = 0x0000f6b1; +define exported symbol __strcmp = 0x0000f6b1; +define exported symbol _strncmp = 0x0000f6d1; +define exported symbol __strncmp = 0x0000f6d1; +define exported symbol prvStrCmp = 0x0000f719; +define exported symbol StrUpr = 0x0000f749; +define exported symbol prvAtoi = 0x0000f769; +define exported symbol prvStrStr = 0x0000f7bd; +define exported symbol _strsep = 0x0000f7d5; +define exported symbol __strsep = 0x0000f7d5; +define exported symbol skip_spaces = 0x0000f815; +define exported symbol skip_atoi = 0x0000f831; +define exported symbol _parse_integer_fixup_radix = 0x0000f869; +define exported symbol _parse_integer = 0x0000f8bd; +define exported symbol __strtoull = 0x0000f915; +define exported symbol __strtoll = 0x0000f945; +define exported symbol __strtoul = 0x0000f965; +define exported symbol __strtol = 0x0000f96d; +define exported symbol simple_strtoull = 0x0000f915; +define exported symbol simple_strtoll = 0x0000f945; +define exported symbol simple_strtoul = 0x0000f965; +define exported symbol simple_strtol = 0x0000f96d; +define exported symbol __vsscanf = 0x0000f985; +define exported symbol __sscanf = 0x0000ff71; +define exported symbol div_u64 = 0x0000ff91; +define exported symbol div_s64 = 0x0000ff99; +define exported symbol div_u64_rem = 0x0000ffa1; +define exported symbol div_s64_rem = 0x0000ffb1; +define exported symbol __strpbrk = 0x0000ffc1; +define exported symbol __strchr = 0x0000ffed; +define exported symbol aes_set_key = 0x00010005; +define exported symbol aes_encrypt = 0x000103d1; +define exported symbol aes_decrypt = 0x000114a5; +define exported symbol AES_WRAP = 0x000125c9; +define exported symbol AES_UnWRAP = 0x00012701; +define exported symbol crc32_get = 0x00012861; +define exported symbol arc4_byte = 0x00012895; +define exported symbol rt_arc4_init = 0x000128bd; +define exported symbol rt_arc4_crypt = 0x00012901; +define exported symbol rt_md5_init = 0x000131c1; +define exported symbol rt_md5_append = 0x000131f5; +define exported symbol rt_md5_final = 0x0001327d; +define exported symbol rt_md5_hmac = 0x000132d5; +define exported symbol rtw_get_bit_value_from_ieee_value = 0x00013449; +define exported symbol rtw_is_cckrates_included = 0x00013475; +define exported symbol rtw_is_cckratesonly_included = 0x000134b5; +define exported symbol rtw_check_network_type = 0x000134dd; +define exported symbol rtw_set_fixed_ie = 0x0001350d; +define exported symbol rtw_set_ie = 0x0001352d; +define exported symbol rtw_get_ie = 0x0001355d; +define exported symbol rtw_set_supported_rate = 0x00013591; +define exported symbol rtw_get_rateset_len = 0x00013611; +define exported symbol rtw_get_wpa_ie = 0x0001362d; +define exported symbol rtw_get_wpa2_ie = 0x000136c9; +define exported symbol rtw_get_wpa_cipher_suite = 0x00013701; +define exported symbol rtw_get_wpa2_cipher_suite = 0x00013769; +define exported symbol rtw_parse_wpa_ie = 0x000137d1; +define exported symbol rtw_parse_wpa2_ie = 0x000138ad; +define exported symbol rtw_get_sec_ie = 0x00013965; +define exported symbol rtw_get_wps_ie = 0x00013a15; +define exported symbol rtw_get_wps_attr = 0x00013a99; +define exported symbol rtw_get_wps_attr_content = 0x00013b49; +define exported symbol rtw_ieee802_11_parse_elems = 0x00013b91; +define exported symbol str_2char2num = 0x00013d9d; +define exported symbol key_2char2num = 0x00013db9; +define exported symbol convert_ip_addr = 0x00013dd1; +define exported symbol rom_psk_PasswordHash = 0x00013e9d; +define exported symbol rom_psk_CalcGTK = 0x00013ed5; +define exported symbol rom_psk_CalcPTK = 0x00013f69; +define exported symbol wep_80211_encrypt = 0x00014295; +define exported symbol wep_80211_decrypt = 0x000142f5; +define exported symbol tkip_micappendbyte = 0x00014389; +define exported symbol rtw_secmicsetkey = 0x000143d9; +define exported symbol rtw_secmicappend = 0x00014419; +define exported symbol rtw_secgetmic = 0x00014435; +define exported symbol rtw_seccalctkipmic = 0x0001449d; +define exported symbol tkip_phase1 = 0x000145a5; +define exported symbol tkip_phase2 = 0x00014725; +define exported symbol tkip_80211_encrypt = 0x00014941; +define exported symbol tkip_80211_decrypt = 0x000149d5; +define exported symbol aes1_encrypt = 0x00014a8d; +define exported symbol aesccmp_construct_mic_iv = 0x00014c65; +define exported symbol aesccmp_construct_mic_header1 = 0x00014ccd; +define exported symbol aesccmp_construct_mic_header2 = 0x00014d21; +define exported symbol aesccmp_construct_ctr_preload = 0x00014db5; +define exported symbol aes_80211_encrypt = 0x00014e29; +define exported symbol aes_80211_decrypt = 0x000151ad; +define exported symbol _sha1_process_message_block = 0x000155b9; +define exported symbol _sha1_pad_message = 0x00015749; +define exported symbol rt_sha1_init = 0x000157e5; +define exported symbol rt_sha1_update = 0x00015831; +define exported symbol rt_sha1_finish = 0x000158a9; +define exported symbol rt_hmac_sha1 = 0x00015909; +define exported symbol rom_aes_128_cbc_encrypt = 0x00015a65; +define exported symbol rom_aes_128_cbc_decrypt = 0x00015ae1; +define exported symbol rom_rijndaelKeySetupEnc = 0x00015b5d; +define exported symbol rom_aes_decrypt_init = 0x00015c39; +define exported symbol rom_aes_internal_decrypt = 0x00015d15; +define exported symbol rom_aes_decrypt_deinit = 0x00016071; +define exported symbol rom_aes_encrypt_init = 0x00016085; +define exported symbol rom_aes_internal_encrypt = 0x0001609d; +define exported symbol rom_aes_encrypt_deinit = 0x00016451; +define exported symbol bignum_init = 0x00017b35; +define exported symbol bignum_deinit = 0x00017b61; +define exported symbol bignum_get_unsigned_bin_len = 0x00017b81; +define exported symbol bignum_get_unsigned_bin = 0x00017b85; +define exported symbol bignum_set_unsigned_bin = 0x00017c21; +define exported symbol bignum_cmp = 0x00017cd1; +define exported symbol bignum_cmp_d = 0x00017cd5; +define exported symbol bignum_add = 0x00017cfd; +define exported symbol bignum_sub = 0x00017d0d; +define exported symbol bignum_mul = 0x00017d1d; +define exported symbol bignum_exptmod = 0x00017d2d; +define exported symbol WPS_realloc = 0x00017d51; +define exported symbol os_zalloc = 0x00017d99; +define exported symbol rom_hmac_sha256_vector = 0x00017dc1; +define exported symbol rom_hmac_sha256 = 0x00017ebd; +define exported symbol rom_sha256_vector = 0x00018009; +define exported symbol phy_CalculateBitShift = 0x00018221; +define exported symbol PHY_SetBBReg_8195A = 0x00018239; +define exported symbol PHY_QueryBBReg_8195A = 0x00018279; +define exported symbol ROM_odm_QueryRxPwrPercentage = 0x0001829d; +define exported symbol ROM_odm_EVMdbToPercentage = 0x000182bd; +define exported symbol ROM_odm_SignalScaleMapping_8195A = 0x000182e5; +define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x000183cd; +define exported symbol ROM_odm_SetEDCCAThreshold = 0x00018721; +define exported symbol ROM_odm_SetTRxMux = 0x00018749; +define exported symbol ROM_odm_SetCrystalCap = 0x00018771; +define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x000187d5; +define exported symbol ROM_ODM_CfoTrackingReset = 0x000187e9; +define exported symbol ROM_odm_CfoTrackingFlow = 0x00018811; +define exported symbol curve25519_donna = 0x0001965d; +define exported symbol aes_test_alignment_detection = 0x0001a391; +define exported symbol aes_mode_reset = 0x0001a3ed; +define exported symbol aes_ecb_encrypt = 0x0001a3f9; +define exported symbol aes_ecb_decrypt = 0x0001a431; +define exported symbol aes_cbc_encrypt = 0x0001a469; +define exported symbol aes_cbc_decrypt = 0x0001a579; +define exported symbol aes_cfb_encrypt = 0x0001a701; +define exported symbol aes_cfb_decrypt = 0x0001a9e5; +define exported symbol aes_ofb_crypt = 0x0001acc9; +define exported symbol aes_ctr_crypt = 0x0001af7d; +define exported symbol aes_encrypt_key128 = 0x0001b289; +define exported symbol aes_encrypt_key192 = 0x0001b2a5; +define exported symbol aes_encrypt_key256 = 0x0001b2c1; +define exported symbol aes_encrypt_key = 0x0001b2e1; +define exported symbol aes_decrypt_key128 = 0x0001b351; +define exported symbol aes_decrypt_key192 = 0x0001b36d; +define exported symbol aes_decrypt_key256 = 0x0001b389; +define exported symbol aes_decrypt_key = 0x0001b3a9; +define exported symbol aes_init = 0x0001b419; +define exported symbol CRYPTO_chacha_20 = 0x0001b41d; +define exported symbol CRYPTO_poly1305_init = 0x0001bc25; +define exported symbol CRYPTO_poly1305_update = 0x0001bd09; +define exported symbol CRYPTO_poly1305_finish = 0x0001bd8d; +define exported symbol rom_sha512_starts = 0x0001ceb5; +define exported symbol rom_sha512_update = 0x0001d009; +define exported symbol rom_sha512_finish = 0x0001d011; +define exported symbol rom_sha512 = 0x0001d261; +define exported symbol rom_sha512_hmac_starts = 0x0001d299; +define exported symbol rom_sha512_hmac_update = 0x0001d35d; +define exported symbol rom_sha512_hmac_finish = 0x0001d365; +define exported symbol rom_sha512_hmac_reset = 0x0001d3b5; +define exported symbol rom_sha512_hmac = 0x0001d3d1; +define exported symbol rom_sha512_hkdf = 0x0001d40d; +define exported symbol rom_ed25519_gen_keypair = 0x0001d501; +define exported symbol rom_ed25519_gen_signature = 0x0001d505; +define exported symbol rom_ed25519_verify_signature = 0x0001d51d; +define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x0001d521; +define exported symbol rom_ed25519_crypto_sign_detached = 0x0001d579; +define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x0001d655; +define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x0001f86d; +define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x0001fc35; +define exported symbol rom_ed25519_ge_p3_tobytes = 0x000207d5; +define exported symbol rom_ed25519_ge_scalarmult_base = 0x00020821; +define exported symbol rom_ed25519_ge_tobytes = 0x000209e1; +define exported symbol rom_ed25519_sc_muladd = 0x00020a2d; +define exported symbol rom_ed25519_sc_reduce = 0x0002603d; +define exported symbol __rtl_memchr_v1_00 = 0x00028a4d; +define exported symbol __rtl_memcmp_v1_00 = 0x00028ae1; +define exported symbol __rtl_memcpy_v1_00 = 0x00028b49; +define exported symbol __rtl_memmove_v1_00 = 0x00028bed; +define exported symbol __rtl_memset_v1_00 = 0x00028cb5; +define exported symbol __rtl_strcat_v1_00 = 0x00028d49; +define exported symbol __rtl_strchr_v1_00 = 0x00028d91; +define exported symbol __rtl_strcmp_v1_00 = 0x00028e55; +define exported symbol __rtl_strcpy_v1_00 = 0x00028ec9; +define exported symbol __rtl_strlen_v1_00 = 0x00028f15; +define exported symbol __rtl_strncat_v1_00 = 0x00028f69; +define exported symbol __rtl_strncmp_v1_00 = 0x00028fc5; +define exported symbol __rtl_strncpy_v1_00 = 0x0002907d; +define exported symbol __rtl_strstr_v1_00 = 0x000293cd; +define exported symbol __rtl_strsep_v1_00 = 0x0002960d; +define exported symbol __rtl_strtok_v1_00 = 0x00029619; +define exported symbol __rtl__strtok_r_v1_00 = 0x0002962d; +define exported symbol __rtl_strtok_r_v1_00 = 0x00029691; +define exported symbol __rtl_close_v1_00 = 0x00029699; +define exported symbol __rtl_fstat_v1_00 = 0x000296ad; +define exported symbol __rtl_isatty_v1_00 = 0x000296c1; +define exported symbol __rtl_lseek_v1_00 = 0x000296d5; +define exported symbol __rtl_open_v1_00 = 0x000296e9; +define exported symbol __rtl_read_v1_00 = 0x000296fd; +define exported symbol __rtl_write_v1_00 = 0x00029711; +define exported symbol __rtl_sbrk_v1_00 = 0x00029725; +define exported symbol __rtl_ltoa_v1_00 = 0x000297bd; +define exported symbol __rtl_ultoa_v1_00 = 0x00029855; +define exported symbol __rtl_dtoi_v1_00 = 0x000298c5; +define exported symbol __rtl_dtoi64_v1_00 = 0x00029945; +define exported symbol __rtl_dtoui_v1_00 = 0x000299dd; +define exported symbol __rtl_ftol_v1_00 = 0x000299e5; +define exported symbol __rtl_itof_v1_00 = 0x00029a51; +define exported symbol __rtl_itod_v1_00 = 0x00029ae9; +define exported symbol __rtl_i64tod_v1_00 = 0x00029b79; +define exported symbol __rtl_uitod_v1_00 = 0x00029c55; +define exported symbol __rtl_ftod_v1_00 = 0x00029d2d; +define exported symbol __rtl_dtof_v1_00 = 0x00029de9; +define exported symbol __rtl_uitof_v1_00 = 0x00029e89; +define exported symbol __rtl_fadd_v1_00 = 0x00029f65; +define exported symbol __rtl_fsub_v1_00 = 0x0002a261; +define exported symbol __rtl_fmul_v1_00 = 0x0002a559; +define exported symbol __rtl_fdiv_v1_00 = 0x0002a695; +define exported symbol __rtl_dadd_v1_00 = 0x0002a825; +define exported symbol __rtl_dsub_v1_00 = 0x0002aed9; +define exported symbol __rtl_dmul_v1_00 = 0x0002b555; +define exported symbol __rtl_ddiv_v1_00 = 0x0002b8ad; +define exported symbol __rtl_dcmpeq_v1_00 = 0x0002be4d; +define exported symbol __rtl_dcmplt_v1_00 = 0x0002bebd; +define exported symbol __rtl_dcmpgt_v1_00 = 0x0002bf51; +define exported symbol __rtl_dcmple_v1_00 = 0x0002c049; +define exported symbol __rtl_fcmplt_v1_00 = 0x0002c139; +define exported symbol __rtl_fcmpgt_v1_00 = 0x0002c195; +define exported symbol __rtl_cos_f32_v1_00 = 0x0002c229; +define exported symbol __rtl_sin_f32_v1_00 = 0x0002c435; +define exported symbol __rtl_fabs_v1_00 = 0x0002c639; +define exported symbol __rtl_fabsf_v1_00 = 0x0002c641; +define exported symbol __rtl_dtoa_r_v1_00 = 0x0002c77d; +define exported symbol __rom_mallocr_init_v1_00 = 0x0002d7d1; +define exported symbol __rtl_free_r_v1_00 = 0x0002d841; +define exported symbol __rtl_malloc_r_v1_00 = 0x0002da31; +define exported symbol __rtl_realloc_r_v1_00 = 0x0002df55; +define exported symbol __rtl_memalign_r_v1_00 = 0x0002e331; +define exported symbol __rtl_valloc_r_v1_00 = 0x0002e421; +define exported symbol __rtl_pvalloc_r_v1_00 = 0x0002e42d; +define exported symbol __rtl_calloc_r_v1_00 = 0x0002e441; +define exported symbol __rtl_cfree_r_v1_00 = 0x0002e4a9; +define exported symbol __rtl_Balloc_v1_00 = 0x0002e515; +define exported symbol __rtl_Bfree_v1_00 = 0x0002e571; +define exported symbol __rtl_i2b_v1_00 = 0x0002e585; +define exported symbol __rtl_multadd_v1_00 = 0x0002e599; +define exported symbol __rtl_mult_v1_00 = 0x0002e629; +define exported symbol __rtl_pow5mult_v1_00 = 0x0002e769; +define exported symbol __rtl_hi0bits_v1_00 = 0x0002e809; +define exported symbol __rtl_d2b_v1_00 = 0x0002e845; +define exported symbol __rtl_lshift_v1_00 = 0x0002e901; +define exported symbol __rtl_cmp_v1_00 = 0x0002e9bd; +define exported symbol __rtl_diff_v1_00 = 0x0002ea01; +define exported symbol __rtl_sread_v1_00 = 0x0002eae9; +define exported symbol __rtl_seofread_v1_00 = 0x0002eb39; +define exported symbol __rtl_swrite_v1_00 = 0x0002eb3d; +define exported symbol __rtl_sseek_v1_00 = 0x0002ebc1; +define exported symbol __rtl_sclose_v1_00 = 0x0002ec11; +define exported symbol __rtl_sbrk_r_v1_00 = 0x0002ec41; +define exported symbol __rtl_fflush_r_v1_00 = 0x0002ef8d; +define exported symbol __rtl_vfprintf_r_v1_00 = 0x0002f661; +define exported symbol __rtl_fpclassifyd = 0x00030c15; +define exported symbol CpkClkTbl = 0x00030c68; +define exported symbol ROM_IMG1_VALID_PATTEN = 0x00030c80; +define exported symbol SpicCalibrationPattern = 0x00030c88; +define exported symbol SpicInitCPUCLK = 0x00030c98; +define exported symbol BAUDRATE = 0x00030ca8; +define exported symbol OVSR = 0x00030d1c; +define exported symbol DIV = 0x00030d90; +define exported symbol OVSR_ADJ = 0x00030e04; +define exported symbol __AES_rcon = 0x00030e78; +define exported symbol __AES_Te4 = 0x00030ea0; +define exported symbol I2CDmaChNo = 0x000312a0; +define exported symbol _GPIO_PinMap_Chip2IP_8195a = 0x000312b4; +define exported symbol _GPIO_PinMap_PullCtrl_8195a = 0x0003136c; +define exported symbol _GPIO_SWPORT_DDR_TBL = 0x00031594; +define exported symbol _GPIO_EXT_PORT_TBL = 0x00031598; +define exported symbol _GPIO_SWPORT_DR_TBL = 0x0003159c; +define exported symbol UartLogRomCmdTable = 0x000316a0; +define exported symbol _HalRuartOp = 0x00031700; +define exported symbol _HalGdmaOp = 0x00031760; +define exported symbol RTW_WPA_OUI_TYPE = 0x0003540c; +define exported symbol WPA_CIPHER_SUITE_NONE = 0x00035410; +define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x00035414; +define exported symbol WPA_CIPHER_SUITE_TKIP = 0x00035418; +define exported symbol WPA_CIPHER_SUITE_CCMP = 0x0003541c; +define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x00035420; +define exported symbol RSN_CIPHER_SUITE_NONE = 0x00035424; +define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x00035428; +define exported symbol RSN_CIPHER_SUITE_TKIP = 0x0003542c; +define exported symbol RSN_CIPHER_SUITE_CCMP = 0x00035430; +define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x00035434; +define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x00035444; +define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x00035448; +define exported symbol RSN_VERSION_BSD = 0x0003544c; +define exported symbol rom_wps_Te0 = 0x00035988; +define exported symbol rom_wps_rcons = 0x00035d88; +define exported symbol rom_wps_Td4s = 0x00035d94; +define exported symbol rom_wps_Td0 = 0x00035e94; +define exported symbol __rom_b_cut_end__ = 0x0004467c; +define exported symbol __rom_c_cut_text_start__ = 0x0004467c; +define exported symbol HalInitPlatformLogUartV02 = 0x0004467d; +define exported symbol HalReInitPlatformLogUartV02 = 0x0004471d; +define exported symbol HalInitPlatformTimerV02 = 0x00044755; +define exported symbol HalShowBuildInfoV02 = 0x000447cd; +define exported symbol SpicReleaseDeepPowerDownFlashRtl8195A = 0x00044831; +define exported symbol HalSpiInitV02 = 0x0004488d; +define exported symbol HalBootFlowV02 = 0x00044a29; +define exported symbol HalInitialROMCodeGlobalVarV02 = 0x00044ae5; +define exported symbol HalResetVsrV02 = 0x00044b41; +define exported symbol HalI2CSendRtl8195aV02 = 0x00044ce1; +define exported symbol HalI2CSetCLKRtl8195aV02 = 0x00044d59; +define exported symbol RtkI2CSendV02 = 0x0004508d; +define exported symbol RtkI2CReceiveV02 = 0x000459a1; +define exported symbol HalI2COpInitV02 = 0x000461ed; +define exported symbol I2CISRHandleV02 = 0x000463e9; +define exported symbol RtkSalI2COpInitV02 = 0x00046be1; +define exported symbol SpicLoadInitParaFromClockRtl8195AV02 = 0x00046c25; +define exported symbol SpiFlashAppV02 = 0x00046c85; +define exported symbol SpicInitRtl8195AV02 = 0x00046dc5; +define exported symbol SpicEraseFlashRtl8195AV02 = 0x00046ea1; +define exported symbol HalTimerIrq2To7HandleV02 = 0x00046f5d; +define exported symbol HalTimerIrqRegisterRtl8195aV02 = 0x00046fe1; +define exported symbol HalTimerInitRtl8195aV02 = 0x0004706d; +define exported symbol HalTimerReadCountRtl8195aV02 = 0x000471b5; +define exported symbol HalTimerReLoadRtl8195aV02 = 0x000471d1; +define exported symbol HalTimerIrqUnRegisterRtl8195aV02 = 0x0004722d; +define exported symbol HalTimerDeInitRtl8195aV02 = 0x000472c1; +define exported symbol HalTimerOpInitV02 = 0x000472f9; +define exported symbol GPIO_LockV02 = 0x00047345; +define exported symbol GPIO_UnLockV02 = 0x00047379; +define exported symbol GPIO_Int_Clear_8195aV02 = 0x000473a5; +define exported symbol HAL_GPIO_IntCtrl_8195aV02 = 0x000473b5; +define exported symbol FindElementIndexV02 = 0x00047541; +define exported symbol HalRuartInitRtl8195aV02 = 0x0004756d; +define exported symbol DramInit_rom = 0x00047619; +define exported symbol ChangeRandSeed_rom = 0x00047979; +define exported symbol Sdr_Rand2_rom = 0x00047985; +define exported symbol MemTest_rom = 0x000479dd; +define exported symbol SdrCalibration_rom = 0x00047a45; +define exported symbol SdrControllerInit_rom = 0x00047d99; +define exported symbol SDIO_EnterCritical = 0x00047e39; +define exported symbol SDIO_ExitCritical = 0x00047e85; +define exported symbol SDIO_IRQ_Handler_Rom = 0x00047ec5; +define exported symbol SDIO_Interrupt_Init_Rom = 0x00047f31; +define exported symbol SDIO_Device_Init_Rom = 0x00047f81; +define exported symbol SDIO_Interrupt_DeInit_Rom = 0x00048215; +define exported symbol SDIO_Device_DeInit_Rom = 0x00048255; +define exported symbol SDIO_Enable_Interrupt_Rom = 0x00048281; +define exported symbol SDIO_Disable_Interrupt_Rom = 0x000482a1; +define exported symbol SDIO_Clear_ISR_Rom = 0x000482c1; +define exported symbol SDIO_Alloc_Rx_Pkt_Rom = 0x000482d9; +define exported symbol SDIO_Free_Rx_Pkt_Rom = 0x00048331; +define exported symbol SDIO_Recycle_Rx_BD_Rom = 0x00048355; +define exported symbol SDIO_RX_IRQ_Handler_BH_Rom = 0x000484f1; +define exported symbol SDIO_RxTask_Rom = 0x0004851d; +define exported symbol SDIO_Process_H2C_IOMsg_Rom = 0x0004856d; +define exported symbol SDIO_Send_C2H_IOMsg_Rom = 0x0004859d; +define exported symbol SDIO_Process_RPWM_Rom = 0x000485b5; +define exported symbol SDIO_Reset_Cmd_Rom = 0x000485e9; +define exported symbol SDIO_Rx_Data_Transaction_Rom = 0x00048611; +define exported symbol SDIO_Send_C2H_PktMsg_Rom = 0x00048829; +define exported symbol SDIO_Register_Tx_Callback_Rom = 0x000488f5; +define exported symbol SDIO_ReadMem_Rom = 0x000488fd; +define exported symbol SDIO_WriteMem_Rom = 0x000489a9; +define exported symbol SDIO_SetMem_Rom = 0x00048a69; +define exported symbol SDIO_TX_Pkt_Handle_Rom = 0x00048b29; +define exported symbol SDIO_TX_FIFO_DataReady_Rom = 0x00048c69; +define exported symbol SDIO_IRQ_Handler_BH_Rom = 0x00048d95; +define exported symbol SDIO_TxTask_Rom = 0x00048e9d; +define exported symbol SDIO_TaskUp_Rom = 0x00048eed; +define exported symbol SDIO_Boot_Up = 0x00048f55; +define exported symbol __rom_c_cut_text_end__ = 0x00049070; +define exported symbol __rom_c_cut_rodata_start__ = 0x00049070; +define exported symbol BAUDRATE_v02 = 0x00049070; +define exported symbol OVSR_v02 = 0x000490fc; +define exported symbol DIV_v02 = 0x00049188; +define exported symbol OVSR_ADJ_v02 = 0x00049214; +define exported symbol SdrDramInfo_rom = 0x000492a0; +define exported symbol SdrDramTiming_rom = 0x000492b4; +define exported symbol NewVectorTable = 0x10000000; +define exported symbol UserIrqFunTable = 0x10000100; +define exported symbol UserIrqDataTable = 0x10000200; +define exported symbol __rom_bss_start__ = 0x10000300; +define exported symbol CfgSysDebugWarn = 0x10000300; +define exported symbol CfgSysDebugInfo = 0x10000304; +define exported symbol CfgSysDebugErr = 0x10000308; +define exported symbol ConfigDebugWarn = 0x1000030c; +define exported symbol ConfigDebugInfo = 0x10000310; +define exported symbol ConfigDebugErr = 0x10000314; +define exported symbol HalTimerOp = 0x10000318; +define exported symbol GPIOState = 0x10000334; +define exported symbol gTimerRecord = 0x1000034c; +define exported symbol SSI_DBG_CONFIG = 0x10000350; +define exported symbol _pHAL_Gpio_Adapter = 0x10000354; +define exported symbol Timer2To7VectorTable = 0x10000358; +define exported symbol rom_wlan_ram_map = 0x100006d4; +define exported symbol ROMInfo = 0x10000720; +define exported symbol rom_libgloss_ram_map = 0x10000760; +define exported symbol __rtl_errno = 0x10000bc4; +define exported symbol __rom_bss_end__ = 0x10000bc8; +define exported symbol __ram_table_start__ = 0x10000bc8; +define exported symbol _rtl_impure_ptr = 0x10001c60; +define exported symbol FalseAlmCnt = 0x100006d4; +define exported symbol DM_CfoTrack = 0x1000072c; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c index fbef79b6ca4..68d7f44edfa 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c @@ -15,17 +15,6 @@ */ #include "rtl8195a.h" -#if defined(__CC_ARM) -#include "cmsis_armcc.h" -#elif (defined(__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050) -#include "cmsis_armclang.h" -#elif defined(__GNUC__) -#include "cmsis_gcc.h" -#else -#include -#endif - - #if defined(__CC_ARM) || \ (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050) @@ -44,15 +33,25 @@ extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[]; #elif defined (__ICCARM__) -#pragma section=".ram.bss" +#pragma section=".bss.sram" +#pragma section=".bss.dtcm" +#pragma section=".bss.dram" -uint8_t *__bss_start__; -uint8_t *__bss_end__; +uint8_t *__bss_sram_start__; +uint8_t *__bss_sram_end__; +uint8_t *__bss_dtcm_start__; +uint8_t *__bss_dtcm_end__; +uint8_t *__bss_dram_start__; +uint8_t *__bss_dram_end__; void __iar_data_init_app(void) { - __bss_start__ = (uint8_t *)__section_begin(".ram.bss"); - __bss_end__ = (uint8_t *)__section_end(".ram.bss"); + __bss_sram_start__ = (uint8_t *)__section_begin(".bss.sram"); + __bss_sram_end__ = (uint8_t *)__section_end(".bss.sram"); + __bss_dtcm_start__ = (uint8_t *)__section_begin(".bss.dtcm"); + __bss_dtcm_end__ = (uint8_t *)__section_end(".bss.dtcm"); + __bss_dram_start__ = (uint8_t *)__section_begin(".bss.dram"); + __bss_dram_end__ = (uint8_t *)__section_end(".bss.dram"); } #else @@ -181,12 +180,10 @@ void PLAT_Init(void) // Clear RAM BSS #if defined (__ICCARM__) __iar_data_init_app(); - __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__); -#else +#endif __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__); __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__); __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__); -#endif extern HAL_TIMER_OP_EXT HalTimerOpExt; __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt)); diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h deleted file mode 100644 index 8b55a13e17c..00000000000 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_rom.h +++ /dev/null @@ -1,748 +0,0 @@ -/* - * Copyright (c) 2013-2016 Realtek Semiconductor Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -SECTIONS -{ - __vectors_table = 0x0; - Reset_Handler = 0x101; - NMI_Handler = 0x109; - HardFault_Handler = 0x10d; - MemManage_Handler = 0x121; - BusFault_Handler = 0x125; - UsageFault_Handler = 0x129; - HalLogUartInit = 0x201; - HalSerialPutcRtl8195a = 0x2d9; - HalSerialGetcRtl8195a = 0x309; - HalSerialGetIsrEnRegRtl8195a = 0x329; - HalSerialSetIrqEnRegRtl8195a = 0x335; - HalCpuClkConfig = 0x341; - HalGetCpuClk = 0x355; - HalRomInfo = 0x39d; - HalGetRomInfo = 0x3b5; - HalResetVsr = 0x3c5; - HalDelayUs = 0x899; - HalNMIHandler = 0x8e1; - HalHardFaultHandler = 0x911; - HalMemManageHandler = 0xc09; - HalBusFaultHandler = 0xc39; - HalUsageFaultHandler = 0xc69; - HalUart0PinCtrlRtl8195A = 0xcfd; - HalUart1PinCtrlRtl8195A = 0xdc9; - HalUart2PinCtrlRtl8195A = 0xe9d; - HalSPI0PinCtrlRtl8195A = 0xf75; - HalSPI1PinCtrlRtl8195A = 0x1015; - HalSPI2PinCtrlRtl8195A = 0x10e5; - HalSPI0MCSPinCtrlRtl8195A = 0x11b5; - HalI2C0PinCtrlRtl8195A = 0x1275; - HalI2C1PinCtrlRtl8195A = 0x1381; - HalI2C2PinCtrlRtl8195A = 0x1459; - HalI2C3PinCtrlRtl8195A = 0x1529; - HalI2S0PinCtrlRtl8195A = 0x1639; - HalI2S1PinCtrlRtl8195A = 0x176d; - HalPCM0PinCtrlRtl8195A = 0x1845; - HalPCM1PinCtrlRtl8195A = 0x1949; - HalSDIODPinCtrlRtl8195A = 0x1a1d; - HalSDIOHPinCtrlRtl8195A = 0x1a6d; - HalMIIPinCtrlRtl8195A = 0x1ab9; - HalWLLEDPinCtrlRtl8195A = 0x1b51; - HalWLANT0PinCtrlRtl8195A = 0x1c0d; - HalWLANT1PinCtrlRtl8195A = 0x1c61; - HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5; - HalWLBTCMDPinCtrlRtl8195A = 0x1d05; - HalNFCPinCtrlRtl8195A = 0x1d59; - HalPWM0PinCtrlRtl8195A = 0x1da9; - HalPWM1PinCtrlRtl8195A = 0x1ead; - HalPWM2PinCtrlRtl8195A = 0x1fb5; - HalPWM3PinCtrlRtl8195A = 0x20b1; - HalETE0PinCtrlRtl8195A = 0x21b9; - HalETE1PinCtrlRtl8195A = 0x22c1; - HalETE2PinCtrlRtl8195A = 0x23c9; - HalETE3PinCtrlRtl8195A = 0x24d1; - HalEGTIMPinCtrlRtl8195A = 0x25d9; - HalSPIFlashPinCtrlRtl8195A = 0x2679; - HalSDRPinCtrlRtl8195A = 0x2725; - HalJTAGPinCtrlRtl8195A = 0x280d; - HalTRACEPinCtrlRtl8195A = 0x2861; - HalLOGUartPinCtrlRtl8195A = 0x28b9; - HalLOGUartIRPinCtrlRtl8195A = 0x291d; - HalSICPinCtrlRtl8195A = 0x2981; - HalEEPROMPinCtrlRtl8195A = 0x29d9; - HalDEBUGPinCtrlRtl8195A = 0x2a31; - HalPinCtrlRtl8195A = 0x2b39; - SpicRxCmdRtl8195A = 0x2e5d; - SpicWaitBusyDoneRtl8195A = 0x2ea5; - SpicGetFlashStatusRtl8195A = 0x2eb5; - SpicWaitWipDoneRtl8195A = 0x2f55; - SpicTxCmdRtl8195A = 0x2f6d; - SpicSetFlashStatusRtl8195A = 0x2fc1; - SpicCmpDataForCalibrationRtl8195A = 0x3049; - SpicLoadInitParaFromClockRtl8195A = 0x3081; - SpicInitRtl8195A = 0x30e5; - SpicEraseFlashRtl8195A = 0x31bd; - SpiFlashApp = 0x3279; - HalPeripheralIntrHandle = 0x33b5; - HalSysOnIntrHandle = 0x3439; - HalWdgIntrHandle = 0x3485; - HalTimer0IntrHandle = 0x34d5; - HalTimer1IntrHandle = 0x3525; - HalI2C3IntrHandle = 0x3575; - HalTimer2To7IntrHandle = 0x35c5; - HalSpi0IntrHandle = 0x3615; - HalGpioIntrHandle = 0x3665; - HalUart0IntrHandle = 0x36b5; - HalSpiFlashIntrHandle = 0x3705; - HalUsbOtgIntrHandle = 0x3755; - HalSdioHostIntrHandle = 0x37a5; - HalI2s0OrPcm0IntrHandle = 0x37f5; - HalI2s1OrPcm1IntrHandle = 0x3845; - HalWlDmaIntrHandle = 0x3895; - HalWlProtocolIntrHandle = 0x38e5; - HalCryptoIntrHandle = 0x3935; - HalGmacIntrHandle = 0x3985; - HalGdma0Ch0IntrHandle = 0x39d5; - HalGdma0Ch1IntrHandle = 0x3a25; - HalGdma0Ch2IntrHandle = 0x3a75; - HalGdma0Ch3IntrHandle = 0x3ac5; - HalGdma0Ch4IntrHandle = 0x3b15; - HalGdma0Ch5IntrHandle = 0x3b65; - HalGdma1Ch0IntrHandle = 0x3bb5; - HalGdma1Ch1IntrHandle = 0x3c05; - HalGdma1Ch2IntrHandle = 0x3c55; - HalGdma1Ch3IntrHandle = 0x3ca5; - HalGdma1Ch4IntrHandle = 0x3cf5; - HalGdma1Ch5IntrHandle = 0x3d45; - HalSdioDeviceIntrHandle = 0x3d95; - VectorTableInitRtl8195A = 0x3de5; - VectorTableInitForOSRtl8195A = 0x4019; - VectorIrqRegisterRtl8195A = 0x4029; - VectorIrqUnRegisterRtl8195A = 0x4091; - VectorIrqEnRtl8195A = 0x40f1; - VectorIrqDisRtl8195A = 0x418d; - _UartRxDmaIrqHandle = 0x422d; - HalRuartPutCRtl8195a = 0x4281; - HalRuartGetCRtl8195a = 0x429d; - HalRuartRTSCtrlRtl8195a = 0x42bd; - HalRuartGetDebugValueRtl8195a = 0x42e1; - HalRuartGetIMRRtl8195a = 0x43e1; - HalRuartSetIMRRtl8195a = 0x442d; - _UartIrqHandle = 0x4465; - HalRuartDmaInitRtl8195a = 0x4681; - HalRuartIntDisableRtl8195a = 0x4845; - HalRuartDeInitRtl8195a = 0x4855; - HalRuartIntEnableRtl8195a = 0x4985; - _UartTxDmaIrqHandle = 0x4995; - HalRuartRegIrqRtl8195a = 0x49d1; - HalRuartAdapterLoadDefRtl8195a = 0x4a4d; - HalRuartTxGdmaLoadDefRtl8195a = 0x4add; - HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9; - RuartLock = 0x4cc9; - RuartUnLock = 0x4ced; - HalRuartIntSendRtl8195a = 0x4d09; - HalRuartDmaSendRtl8195a = 0x4e35; - HalRuartStopSendRtl8195a = 0x4f89; - HalRuartIntRecvRtl8195a = 0x504d; - HalRuartDmaRecvRtl8195a = 0x51ad; - HalRuartStopRecvRtl8195a = 0x52cd; - RuartIsTimeout = 0x5385; - HalRuartSendRtl8195a = 0x53b1; - HalRuartRecvRtl8195a = 0x5599; - RuartResetRxFifoRtl8195a = 0x5751; - HalRuartResetRxFifoRtl8195a = 0x5775; - HalRuartInitRtl8195a = 0x5829; - HalGdmaOnOffRtl8195a = 0x5df1; - HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d; - HalGdmaChEnRtl8195a = 0x5e51; - HalGdmaChDisRtl8195a = 0x5e6d; - HalGdamChInitRtl8195a = 0x5e91; - HalGdmaChSetingRtl8195a = 0x5ebd; - HalGdmaChIsrCleanRtl8195a = 0x6419; - HalGdmaChCleanAutoSrcRtl8195a = 0x64a1; - HalGdmaChCleanAutoDstRtl8195a = 0x6501; - HalEFUSEPowerSwitch8195AROM = 0x6561; - HALEFUSEOneByteReadROM = 0x65f9; - HALEFUSEOneByteWriteROM = 0x6699; - __rtl_memcmpb_v1_00 = 0x681d; - __rtl_random_v1_00 = 0x6861; - __rtl_align_to_be32_v1_00 = 0x6881; - __rtl_memsetw_v1_00 = 0x6899; - __rtl_memsetb_v1_00 = 0x68ad; - __rtl_memcpyw_v1_00 = 0x68bd; - __rtl_memcpyb_v1_00 = 0x68dd; - __rtl_memDump_v1_00 = 0x68f5; - __rtl_AES_set_encrypt_key = 0x6901; - __rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11; - __rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95; - __rtl_cryptoEngine_init_v1_00 = 0x6ea9; - __rtl_cryptoEngine_exit_v1_00 = 0x7055; - __rtl_cryptoEngine_reset_v1_00 = 0x70b1; - __rtl_cryptoEngine_v1_00 = 0x70ed; - __rtl_crypto_cipher_init_v1_00 = 0x7c69; - __rtl_crypto_cipher_encrypt_v1_00 = 0x7c89; - __rtl_crypto_cipher_decrypt_v1_00 = 0x7cad; - HalSsiPinmuxEnableRtl8195a = 0x7cd5; - HalSsiEnableRtl8195a = 0x7e45; - HalSsiDisableRtl8195a = 0x7ef9; - HalSsiLoadSettingRtl8195a = 0x7fad; - HalSsiSetInterruptMaskRtl8195a = 0x8521; - HalSsiGetInterruptMaskRtl8195a = 0x85c9; - HalSsiSetSclkPolarityRtl8195a = 0x863d; - HalSsiSetSclkPhaseRtl8195a = 0x8715; - HalSsiWriteRtl8195a = 0x87e9; - HalSsiSetDeviceRoleRtl8195a = 0x8861; - HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9; - HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941; - HalSsiReadRtl8195a = 0x89b9; - HalSsiGetRxFifoLevelRtl8195a = 0x8a2d; - HalSsiGetTxFifoLevelRtl8195a = 0x8aa5; - HalSsiGetStatusRtl8195a = 0x8b1d; - HalSsiWriteableRtl8195a = 0x8b91; - HalSsiReadableRtl8195a = 0x8c09; - HalSsiBusyRtl8195a = 0x8c81; - HalSsiReadInterruptRtl8195a = 0x8cf9; - HalSsiWriteInterruptRtl8195a = 0x8efd; - HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009; - HalSsiGetInterruptStatusRtl8195a = 0x90d9; - HalSsiInterruptEnableRtl8195a = 0x914d; - HalSsiInterruptDisableRtl8195a = 0x9299; - HalSsiGetRawInterruptStatusRtl8195a = 0x93e9; - HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d; - HalSsiInitRtl8195a = 0x94d1; - _SsiReadInterrupt = 0x9ba5; - _SsiWriteInterrupt = 0x9db1; - _SsiIrqHandle = 0x9eb1; - HalI2CWrite32 = 0xa061; - HalI2CRead32 = 0xa09d; - HalI2CDeInit8195a = 0xa0dd; - HalI2CSendRtl8195a = 0xa1f1; - HalI2CReceiveRtl8195a = 0xa25d; - HalI2CEnableRtl8195a = 0xa271; - HalI2CIntrCtrl8195a = 0xa389; - HalI2CReadRegRtl8195a = 0xa3a1; - HalI2CWriteRegRtl8195a = 0xa3b1; - HalI2CSetCLKRtl8195a = 0xa3c5; - HalI2CMassSendRtl8195a = 0xa6e9; - HalI2CClrIntrRtl8195a = 0xa749; - HalI2CClrAllIntrRtl8195a = 0xa761; - HalI2CInit8195a = 0xa775; - HalI2CDMACtrl8195a = 0xaa31; - RtkI2CIoCtrl = 0xaa61; - RtkI2CPowerCtrl = 0xaa65; - HalI2COpInit = 0xaa69; - I2CIsTimeout = 0xac65; - I2CTXGDMAISRHandle = 0xb435; - I2CRXGDMAISRHandle = 0xb4c1; - RtkI2CIrqInit = 0xb54d; - RtkI2CIrqDeInit = 0xb611; - RtkI2CPinMuxInit = 0xb675; - RtkI2CPinMuxDeInit = 0xb7c9; - RtkI2CDMAInit = 0xb955; - RtkI2CInit = 0xbc95; - RtkI2CDMADeInit = 0xbdad; - RtkI2CDeInit = 0xbe4d; - RtkI2CSendUserAddr = 0xbee5; - RtkI2CSend = 0xc07d; - RtkI2CLoadDefault = 0xce51; - RtkSalI2COpInit = 0xcf21; - HalI2SWrite32 = 0xcf65; - HalI2SRead32 = 0xcf85; - HalI2SDeInitRtl8195a = 0xcfa9; - HalI2STxRtl8195a = 0xcfc9; - HalI2SRxRtl8195a = 0xd011; - HalI2SEnableRtl8195a = 0xd05d; - HalI2SIntrCtrlRtl8195a = 0xd0b1; - HalI2SReadRegRtl8195a = 0xd0d1; - HalI2SClrIntrRtl8195a = 0xd0dd; - HalI2SClrAllIntrRtl8195a = 0xd0fd; - HalI2SInitRtl8195a = 0xd11d; - GPIO_GetIPPinName_8195a = 0xd2e5; - GPIO_GetChipPinName_8195a = 0xd331; - GPIO_PullCtrl_8195a = 0xd39d; - GPIO_FuncOn_8195a = 0xd421; - GPIO_FuncOff_8195a = 0xd481; - GPIO_Int_Mask_8195a = 0xd4e9; - GPIO_Int_SetType_8195a = 0xd511; - HAL_GPIO_IrqHandler_8195a = 0xd5fd; - HAL_GPIO_MbedIrqHandler_8195a = 0xd645; - HAL_GPIO_UserIrqHandler_8195a = 0xd6a1; - HAL_GPIO_IntCtrl_8195a = 0xd6cd; - HAL_GPIO_Init_8195a = 0xd805; - HAL_GPIO_DeInit_8195a = 0xdac1; - HAL_GPIO_ReadPin_8195a = 0xdbd1; - HAL_GPIO_WritePin_8195a = 0xdc91; - HAL_GPIO_RegIrq_8195a = 0xddad; - HAL_GPIO_UnRegIrq_8195a = 0xddf5; - HAL_GPIO_UserRegIrq_8195a = 0xde15; - HAL_GPIO_UserUnRegIrq_8195a = 0xdef9; - HAL_GPIO_MaskIrq_8195a = 0xdfc1; - HAL_GPIO_UnMaskIrq_8195a = 0xe061; - HAL_GPIO_IntDebounce_8195a = 0xe101; - HAL_GPIO_GetIPPinName_8195a = 0xe1c1; - HAL_GPIO_PullCtrl_8195a = 0xe1c9; - DumpForOneBytes = 0xe259; - CmdRomHelp = 0xe419; - CmdWriteWord = 0xe491; - CmdDumpHelfWord = 0xe505; - CmdDumpWord = 0xe5f1; - CmdDumpByte = 0xe6f5; - CmdSpiFlashTool = 0xe751; - GetRomCmdNum = 0xe7a9; - CmdWriteByte = 0xe7ad; - Isspace = 0xe7ed; - Strtoul = 0xe801; - ArrayInitialize = 0xe8b1; - GetArgc = 0xe8c9; - GetArgv = 0xe8f9; - UartLogCmdExecute = 0xe95d; - UartLogShowBackSpace = 0xe9fd; - UartLogRecallOldCmd = 0xea39; - UartLogHistoryCmd = 0xea71; - UartLogCmdChk = 0xeadd; - UartLogIrqHandle = 0xebf5; - RtlConsolInit = 0xecc5; - RtlConsolTaskRom = 0xed49; - RtlExitConsol = 0xed79; - RtlConsolRom = 0xedcd; - HalTimerOpInit = 0xee0d; - HalTimerIrq2To7Handle = 0xee59; - HalGetTimerIdRtl8195a = 0xef09; - HalTimerInitRtl8195a = 0xef3d; - HalTimerDisRtl8195a = 0xf069; - HalTimerEnRtl8195a = 0xf089; - HalTimerReadCountRtl8195a = 0xf0a9; - HalTimerIrqClearRtl8195a = 0xf0bd; - HalTimerDumpRegRtl8195a = 0xf0d1; - VSprintf = 0xf129; - DiagPrintf = 0xf39d; - DiagSPrintf = 0xf3b9; - DiagSnPrintf = 0xf3d1; - prvDiagPrintf = 0xf3ed; - prvDiagSPrintf = 0xf40d; - _memcmp = 0xf429; - _memcpy = 0xf465; - _memset = 0xf511; - Rand = 0xf585; - _strncpy = 0xf60d; - _strcpy = 0xf629; - prvStrCpy = 0xf639; - _strlen = 0xf651; - _strnlen = 0xf669; - prvStrLen = 0xf699; - _strcmp = 0xf6b1; - _strncmp = 0xf6d1; - prvStrCmp = 0xf719; - StrUpr = 0xf749; - prvAtoi = 0xf769; - prvStrStr = 0xf7bd; - _strsep = 0xf7d5; - skip_spaces = 0xf815; - skip_atoi = 0xf831; - _parse_integer_fixup_radix = 0xf869; - _parse_integer = 0xf8bd; - simple_strtoull = 0xf915; - simple_strtoll = 0xf945; - simple_strtoul = 0xf965; - simple_strtol = 0xf96d; - _vsscanf = 0xf985; - _sscanf = 0xff71; - div_u64 = 0xff91; - div_s64 = 0xff99; - div_u64_rem = 0xffa1; - div_s64_rem = 0xffb1; - _strpbrk = 0xffc1; - _strchr = 0xffed; - aes_set_key = 0x10005; - aes_encrypt = 0x103d1; - aes_decrypt = 0x114a5; - AES_WRAP = 0x125c9; - AES_UnWRAP = 0x12701; - crc32_get = 0x12861; - arc4_byte = 0x12895; - rt_arc4_init = 0x128bd; - rt_arc4_crypt = 0x12901; - rt_md5_init = 0x131c1; - rt_md5_append = 0x131f5; - rt_md5_final = 0x1327d; - rt_md5_hmac = 0x132d5; - rtw_get_bit_value_from_ieee_value = 0x13449; - rtw_is_cckrates_included = 0x13475; - rtw_is_cckratesonly_included = 0x134b5; - rtw_check_network_type = 0x134dd; - rtw_set_fixed_ie = 0x1350d; - rtw_set_ie = 0x1352d; - rtw_get_ie = 0x1355d; - rtw_set_supported_rate = 0x13591; - rtw_get_rateset_len = 0x13611; - rtw_get_wpa_ie = 0x1362d; - rtw_get_wpa2_ie = 0x136c9; - rtw_get_wpa_cipher_suite = 0x13701; - rtw_get_wpa2_cipher_suite = 0x13769; - rtw_parse_wpa_ie = 0x137d1; - rtw_parse_wpa2_ie = 0x138ad; - rtw_get_sec_ie = 0x13965; - rtw_get_wps_ie = 0x13a15; - rtw_get_wps_attr = 0x13a99; - rtw_get_wps_attr_content = 0x13b49; - rtw_ieee802_11_parse_elems = 0x13b91; - str_2char2num = 0x13d9d; - key_2char2num = 0x13db9; - convert_ip_addr = 0x13dd1; - rom_psk_PasswordHash = 0x13e9d; - rom_psk_CalcGTK = 0x13ed5; - rom_psk_CalcPTK = 0x13f69; - wep_80211_encrypt = 0x14295; - wep_80211_decrypt = 0x142f5; - tkip_micappendbyte = 0x14389; - rtw_secmicsetkey = 0x143d9; - rtw_secmicappend = 0x14419; - rtw_secgetmic = 0x14435; - rtw_seccalctkipmic = 0x1449d; - tkip_phase1 = 0x145a5; - tkip_phase2 = 0x14725; - tkip_80211_encrypt = 0x14941; - tkip_80211_decrypt = 0x149d5; - aes1_encrypt = 0x14a8d; - aesccmp_construct_mic_iv = 0x14c65; - aesccmp_construct_mic_header1 = 0x14ccd; - aesccmp_construct_mic_header2 = 0x14d21; - aesccmp_construct_ctr_preload = 0x14db5; - aes_80211_encrypt = 0x14e29; - aes_80211_decrypt = 0x151ad; - _sha1_process_message_block = 0x155b9; - _sha1_pad_message = 0x15749; - rt_sha1_init = 0x157e5; - rt_sha1_update = 0x15831; - rt_sha1_finish = 0x158a9; - rt_hmac_sha1 = 0x15909; - rom_aes_128_cbc_encrypt = 0x15a65; - rom_aes_128_cbc_decrypt = 0x15ae1; - rom_rijndaelKeySetupEnc = 0x15b5d; - rom_aes_decrypt_init = 0x15c39; - rom_aes_internal_decrypt = 0x15d15; - rom_aes_decrypt_deinit = 0x16071; - rom_aes_encrypt_init = 0x16085; - rom_aes_internal_encrypt = 0x1609d; - rom_aes_encrypt_deinit = 0x16451; - bignum_init = 0x17b35; - bignum_deinit = 0x17b61; - bignum_get_unsigned_bin_len = 0x17b81; - bignum_get_unsigned_bin = 0x17b85; - bignum_set_unsigned_bin = 0x17c21; - bignum_cmp = 0x17cd1; - bignum_cmp_d = 0x17cd5; - bignum_add = 0x17cfd; - bignum_sub = 0x17d0d; - bignum_mul = 0x17d1d; - bignum_exptmod = 0x17d2d; - WPS_realloc = 0x17d51; - os_zalloc = 0x17d99; - rom_hmac_sha256_vector = 0x17dc1; - rom_hmac_sha256 = 0x17ebd; - rom_sha256_vector = 0x18009; - phy_CalculateBitShift = 0x18221; - PHY_SetBBReg_8195A = 0x18239; - PHY_QueryBBReg_8195A = 0x18279; - ROM_odm_QueryRxPwrPercentage = 0x1829d; - ROM_odm_EVMdbToPercentage = 0x182bd; - ROM_odm_SignalScaleMapping_8195A = 0x182e5; - ROM_odm_FalseAlarmCounterStatistics = 0x183cd; - ROM_odm_SetEDCCAThreshold = 0x18721; - ROM_odm_SetTRxMux = 0x18749; - ROM_odm_SetCrystalCap = 0x18771; - ROM_odm_GetDefaultCrytaltalCap = 0x187d5; - ROM_ODM_CfoTrackingReset = 0x187e9; - ROM_odm_CfoTrackingFlow = 0x18811; - curve25519_donna = 0x1965d; - aes_test_alignment_detection = 0x1a391; - aes_mode_reset = 0x1a3ed; - aes_ecb_encrypt = 0x1a3f9; - aes_ecb_decrypt = 0x1a431; - aes_cbc_encrypt = 0x1a469; - aes_cbc_decrypt = 0x1a579; - aes_cfb_encrypt = 0x1a701; - aes_cfb_decrypt = 0x1a9e5; - aes_ofb_crypt = 0x1acc9; - aes_ctr_crypt = 0x1af7d; - aes_encrypt_key128 = 0x1b289; - aes_encrypt_key192 = 0x1b2a5; - aes_encrypt_key256 = 0x1b2c1; - aes_encrypt_key = 0x1b2e1; - aes_decrypt_key128 = 0x1b351; - aes_decrypt_key192 = 0x1b36d; - aes_decrypt_key256 = 0x1b389; - aes_decrypt_key = 0x1b3a9; - aes_init = 0x1b419; - CRYPTO_chacha_20 = 0x1b41d; - CRYPTO_poly1305_init = 0x1bc25; - CRYPTO_poly1305_update = 0x1bd09; - CRYPTO_poly1305_finish = 0x1bd8d; - rom_sha512_starts = 0x1ceb5; - rom_sha512_update = 0x1d009; - rom_sha512_finish = 0x1d011; - rom_sha512 = 0x1d261; - rom_sha512_hmac_starts = 0x1d299; - rom_sha512_hmac_update = 0x1d35d; - rom_sha512_hmac_finish = 0x1d365; - rom_sha512_hmac_reset = 0x1d3b5; - rom_sha512_hmac = 0x1d3d1; - rom_sha512_hkdf = 0x1d40d; - rom_ed25519_gen_keypair = 0x1d501; - rom_ed25519_gen_signature = 0x1d505; - rom_ed25519_verify_signature = 0x1d51d; - rom_ed25519_crypto_sign_seed_keypair = 0x1d521; - rom_ed25519_crypto_sign_detached = 0x1d579; - rom_ed25519_crypto_sign_verify_detached = 0x1d655; - rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d; - rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35; - rom_ed25519_ge_p3_tobytes = 0x207d5; - rom_ed25519_ge_scalarmult_base = 0x20821; - rom_ed25519_ge_tobytes = 0x209e1; - rom_ed25519_sc_muladd = 0x20a2d; - rom_ed25519_sc_reduce = 0x2603d; - __rtl_memchr_v1_00 = 0x28a4d; - __rtl_memcmp_v1_00 = 0x28ae1; - __rtl_memcpy_v1_00 = 0x28b49; - __rtl_memmove_v1_00 = 0x28bed; - __rtl_memset_v1_00 = 0x28cb5; - __rtl_strcat_v1_00 = 0x28d49; - __rtl_strchr_v1_00 = 0x28d91; - __rtl_strcmp_v1_00 = 0x28e55; - __rtl_strcpy_v1_00 = 0x28ec9; - __rtl_strlen_v1_00 = 0x28f15; - __rtl_strncat_v1_00 = 0x28f69; - __rtl_strncmp_v1_00 = 0x28fc5; - __rtl_strncpy_v1_00 = 0x2907d; - __rtl_strstr_v1_00 = 0x293cd; - __rtl_strsep_v1_00 = 0x2960d; - __rtl_strtok_v1_00 = 0x29619; - __rtl__strtok_r_v1_00 = 0x2962d; - __rtl_strtok_r_v1_00 = 0x29691; - __rtl_close_v1_00 = 0x29699; - __rtl_fstat_v1_00 = 0x296ad; - __rtl_isatty_v1_00 = 0x296c1; - __rtl_lseek_v1_00 = 0x296d5; - __rtl_open_v1_00 = 0x296e9; - __rtl_read_v1_00 = 0x296fd; - __rtl_write_v1_00 = 0x29711; - __rtl_sbrk_v1_00 = 0x29725; - __rtl_ltoa_v1_00 = 0x297bd; - __rtl_ultoa_v1_00 = 0x29855; - __rtl_dtoi_v1_00 = 0x298c5; - __rtl_dtoi64_v1_00 = 0x29945; - __rtl_dtoui_v1_00 = 0x299dd; - __rtl_ftol_v1_00 = 0x299e5; - __rtl_itof_v1_00 = 0x29a51; - __rtl_itod_v1_00 = 0x29ae9; - __rtl_i64tod_v1_00 = 0x29b79; - __rtl_uitod_v1_00 = 0x29c55; - __rtl_ftod_v1_00 = 0x29d2d; - __rtl_dtof_v1_00 = 0x29de9; - __rtl_uitof_v1_00 = 0x29e89; - __rtl_fadd_v1_00 = 0x29f65; - __rtl_fsub_v1_00 = 0x2a261; - __rtl_fmul_v1_00 = 0x2a559; - __rtl_fdiv_v1_00 = 0x2a695; - __rtl_dadd_v1_00 = 0x2a825; - __rtl_dsub_v1_00 = 0x2aed9; - __rtl_dmul_v1_00 = 0x2b555; - __rtl_ddiv_v1_00 = 0x2b8ad; - __rtl_dcmpeq_v1_00 = 0x2be4d; - __rtl_dcmplt_v1_00 = 0x2bebd; - __rtl_dcmpgt_v1_00 = 0x2bf51; - __rtl_dcmple_v1_00 = 0x2c049; - __rtl_fcmplt_v1_00 = 0x2c139; - __rtl_fcmpgt_v1_00 = 0x2c195; - __rtl_cos_f32_v1_00 = 0x2c229; - __rtl_sin_f32_v1_00 = 0x2c435; - __rtl_fabs_v1_00 = 0x2c639; - __rtl_fabsf_v1_00 = 0x2c641; - __rtl_dtoa_r_v1_00 = 0x2c77d; - __rom_mallocr_init_v1_00 = 0x2d7d1; - __rtl_free_r_v1_00 = 0x2d841; - __rtl_malloc_r_v1_00 = 0x2da31; - __rtl_realloc_r_v1_00 = 0x2df55; - __rtl_memalign_r_v1_00 = 0x2e331; - __rtl_valloc_r_v1_00 = 0x2e421; - __rtl_pvalloc_r_v1_00 = 0x2e42d; - __rtl_calloc_r_v1_00 = 0x2e441; - __rtl_cfree_r_v1_00 = 0x2e4a9; - __rtl_Balloc_v1_00 = 0x2e515; - __rtl_Bfree_v1_00 = 0x2e571; - __rtl_i2b_v1_00 = 0x2e585; - __rtl_multadd_v1_00 = 0x2e599; - __rtl_mult_v1_00 = 0x2e629; - __rtl_pow5mult_v1_00 = 0x2e769; - __rtl_hi0bits_v1_00 = 0x2e809; - __rtl_d2b_v1_00 = 0x2e845; - __rtl_lshift_v1_00 = 0x2e901; - __rtl_cmp_v1_00 = 0x2e9bd; - __rtl_diff_v1_00 = 0x2ea01; - __rtl_sread_v1_00 = 0x2eae9; - __rtl_seofread_v1_00 = 0x2eb39; - __rtl_swrite_v1_00 = 0x2eb3d; - __rtl_sseek_v1_00 = 0x2ebc1; - __rtl_sclose_v1_00 = 0x2ec11; - __rtl_sbrk_r_v1_00 = 0x2ec41; - __rtl_fflush_r_v1_00 = 0x2ef8d; - __rtl_vfprintf_r_v1_00 = 0x2f661; - __rtl_fpclassifyd = 0x30c15; - CpkClkTbl = 0x30c68; - ROM_IMG1_VALID_PATTEN = 0x30c80; - SpicCalibrationPattern = 0x30c88; - SpicInitCPUCLK = 0x30c98; - BAUDRATE = 0x30ca8; - OVSR = 0x30d1c; - DIV = 0x30d90; - OVSR_ADJ = 0x30e04; - __AES_rcon = 0x30e78; - __AES_Te4 = 0x30ea0; - I2CDmaChNo = 0x312a0; - _GPIO_PinMap_Chip2IP_8195a = 0x312b4; - _GPIO_PinMap_PullCtrl_8195a = 0x3136c; - _GPIO_SWPORT_DDR_TBL = 0x31594; - _GPIO_EXT_PORT_TBL = 0x31598; - _GPIO_SWPORT_DR_TBL = 0x3159c; - UartLogRomCmdTable = 0x316a0; - _HalRuartOp = 0x31700; - _HalGdmaOp = 0x31760; - RTW_WPA_OUI_TYPE = 0x3540c; - WPA_CIPHER_SUITE_NONE = 0x35410; - WPA_CIPHER_SUITE_WEP40 = 0x35414; - WPA_CIPHER_SUITE_TKIP = 0x35418; - WPA_CIPHER_SUITE_CCMP = 0x3541c; - WPA_CIPHER_SUITE_WEP104 = 0x35420; - RSN_CIPHER_SUITE_NONE = 0x35424; - RSN_CIPHER_SUITE_WEP40 = 0x35428; - RSN_CIPHER_SUITE_TKIP = 0x3542c; - RSN_CIPHER_SUITE_CCMP = 0x35430; - RSN_CIPHER_SUITE_WEP104 = 0x35434; - RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444; - RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448; - RSN_VERSION_BSD = 0x3544c; - rom_wps_Te0 = 0x35988; - rom_wps_rcons = 0x35d88; - rom_wps_Td4s = 0x35d94; - rom_wps_Td0 = 0x35e94; - __rom_b_cut_end__ = 0x4467c; - __rom_c_cut_text_start__ = 0x4467c; - HalInitPlatformLogUartV02 = 0x4467d; - HalReInitPlatformLogUartV02 = 0x4471d; - HalInitPlatformTimerV02 = 0x44755; - HalShowBuildInfoV02 = 0x447cd; - SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831; - HalSpiInitV02 = 0x4488d; - HalBootFlowV02 = 0x44a29; - HalInitialROMCodeGlobalVarV02 = 0x44ae5; - HalResetVsrV02 = 0x44b41; - HalI2CSendRtl8195aV02 = 0x44ce1; - HalI2CSetCLKRtl8195aV02 = 0x44d59; - RtkI2CSendV02 = 0x4508d; - RtkI2CReceiveV02 = 0x459a1; - HalI2COpInitV02 = 0x461ed; - I2CISRHandleV02 = 0x463e9; - RtkSalI2COpInitV02 = 0x46be1; - SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25; - SpiFlashAppV02 = 0x46c85; - SpicInitRtl8195AV02 = 0x46dc5; - SpicEraseFlashRtl8195AV02 = 0x46ea1; - HalTimerIrq2To7HandleV02 = 0x46f5d; - HalTimerIrqRegisterRtl8195aV02 = 0x46fe1; - HalTimerInitRtl8195aV02 = 0x4706d; - HalTimerReadCountRtl8195aV02 = 0x471b5; - HalTimerReLoadRtl8195aV02 = 0x471d1; - HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d; - HalTimerDeInitRtl8195aV02 = 0x472c1; - HalTimerOpInitV02 = 0x472f9; - GPIO_LockV02 = 0x47345; - GPIO_UnLockV02 = 0x47379; - GPIO_Int_Clear_8195aV02 = 0x473a5; - HAL_GPIO_IntCtrl_8195aV02 = 0x473b5; - FindElementIndexV02 = 0x47541; - HalRuartInitRtl8195aV02 = 0x4756d; - DramInit_rom = 0x47619; - ChangeRandSeed_rom = 0x47979; - Sdr_Rand2_rom = 0x47985; - MemTest_rom = 0x479dd; - SdrCalibration_rom = 0x47a45; - SdrControllerInit_rom = 0x47d99; - SDIO_EnterCritical = 0x47e39; - SDIO_ExitCritical = 0x47e85; - SDIO_IRQ_Handler_Rom = 0x47ec5; - SDIO_Interrupt_Init_Rom = 0x47f31; - SDIO_Device_Init_Rom = 0x47f81; - SDIO_Interrupt_DeInit_Rom = 0x48215; - SDIO_Device_DeInit_Rom = 0x48255; - SDIO_Enable_Interrupt_Rom = 0x48281; - SDIO_Disable_Interrupt_Rom = 0x482a1; - SDIO_Clear_ISR_Rom = 0x482c1; - SDIO_Alloc_Rx_Pkt_Rom = 0x482d9; - SDIO_Free_Rx_Pkt_Rom = 0x48331; - SDIO_Recycle_Rx_BD_Rom = 0x48355; - SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1; - SDIO_RxTask_Rom = 0x4851d; - SDIO_Process_H2C_IOMsg_Rom = 0x4856d; - SDIO_Send_C2H_IOMsg_Rom = 0x4859d; - SDIO_Process_RPWM_Rom = 0x485b5; - SDIO_Reset_Cmd_Rom = 0x485e9; - SDIO_Rx_Data_Transaction_Rom = 0x48611; - SDIO_Send_C2H_PktMsg_Rom = 0x48829; - SDIO_Register_Tx_Callback_Rom = 0x488f5; - SDIO_ReadMem_Rom = 0x488fd; - SDIO_WriteMem_Rom = 0x489a9; - SDIO_SetMem_Rom = 0x48a69; - SDIO_TX_Pkt_Handle_Rom = 0x48b29; - SDIO_TX_FIFO_DataReady_Rom = 0x48c69; - SDIO_IRQ_Handler_BH_Rom = 0x48d95; - SDIO_TxTask_Rom = 0x48e9d; - SDIO_TaskUp_Rom = 0x48eed; - SDIO_Boot_Up = 0x48f55; - __rom_c_cut_text_end__ = 0x49070; - __rom_c_cut_rodata_start__ = 0x49070; - BAUDRATE_v02 = 0x49070; - OVSR_v02 = 0x490fc; - DIV_v02 = 0x49188; - OVSR_ADJ_v02 = 0x49214; - SdrDramInfo_rom = 0x492a0; - SdrDramTiming_rom = 0x492b4; - SdrDramModeReg_rom = 0x492e8; - SdrDramDev_rom = 0x49304; - __rom_c_cut_rodata_end__ = 0x49314; - NewVectorTable = 0x10000000; - UserhandlerTable = 0x10000100; - UserIrqDataTable = 0x10000200; - __rom_bss_start__ = 0x10000300; - CfgSysDebugWarn = 0x10000300; - CfgSysDebugInfo = 0x10000304; - CfgSysDebugErr = 0x10000308; - ConfigDebugWarn = 0x1000030c; - ConfigDebugInfo = 0x10000310; - ConfigDebugErr = 0x10000314; - HalTimerOp = 0x10000318; - GPIOState = 0x10000334; - gTimerRecord = 0x1000034c; - SSI_DBG_CONFIG = 0x10000350; - _pHAL_Gpio_Adapter = 0x10000354; - Timer2To7VectorTable = 0x10000358; - pUartLogCtl = 0x10000384; - UartLogBuf = 0x10000388; - UartLogCtl = 0x10000408; - UartLogHistoryBuf = 0x10000430; - ArgvArray = 0x100006ac; - rom_wlan_ram_map = 0x100006d4; - FalseAlmCnt = 0x100006e0; - ROMInfo = 0x10000720; - DM_CfoTrack = 0x10000738; - rom_libgloss_ram_map = 0x10000760; - __rtl_errno = 0x10000bc4; -} diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h index caf8223d118..42d5c62e0c1 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_timer.h @@ -94,6 +94,11 @@ HalTimerReadCountRtl8195a_Patch( IN u32 TimerId ); +VOID +HalTimerSync( + IN u32 TimerId +); + VOID HalTimerIrqEnRtl8195a( IN u32 TimerId diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c index c8ebf87a07a..c8e3849aaef 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_api.c @@ -56,7 +56,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) uint32_t flash_get_page_size(const flash_t *obj) { - return FLASH_PAGE_SIZE; + return 1; } uint32_t flash_get_start_address(const flash_t *obj) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h index 6ad5c799dac..b2d287bf619 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/flash_ext.h @@ -24,7 +24,7 @@ extern "C" { #endif #define FLASH_PAGE_SIZE 256 -#define FLASH_SIZE 0x100000 +#define FLASH_SIZE 0x200000 #define FLASH_OFS_START 0x0 #define FLASH_OFS_END (FLASH_OFS_START + FLASH_SIZE) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c index 890a8ad5600..5b6215a78e7 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.c @@ -19,28 +19,11 @@ #include "mbed_wait_api.h" #include "rtl8195a.h" +#include "ota_api.h" #include "flash_ext.h" -#define FLASH_TOP 0x200000 -#define FLASH_SECTOR_SIZE 0x1000 -#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1) -#define OTA_REGION1 0x0b000 -#define OTA_REGION2 0xc0000 -#define TAG_OFS 0xc -#define VER_OFS 0x10 - -#define TAG_DOWNLOAD 0x81950001 -#define TAG_VERIFIED 0x81950003 - static flash_t flash_obj; -typedef struct imginfo_s { - uint32_t base; - uint32_t tag; - uint64_t ver; -} imginfo_t; - - void OTA_GetImageInfo(imginfo_t *info) { uint32_t ver_hi, ver_lo; diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h index 2b978a32368..8fe91694cee 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/ota_api.h @@ -1,10 +1,30 @@ #ifndef MBED_OTA_API_H #define MBED_OTA_API_H +#define FLASH_TOP 0x200000 +#define FLASH_SECTOR_SIZE 0x1000 +#define FLASH_SECTOR_MASK ~(FLASH_SECTOR_SIZE - 1) +#define OTA_REGION1 0x0b000 +#define OTA_REGION2 0xc0000 +#define TAG_OFS 0xc +#define VER_OFS 0x10 + +#define TAG_DOWNLOAD 0x81950001 +#define TAG_VERIFIED 0x81950003 + +typedef struct imginfo_s { + uint32_t base; + uint32_t tag; + uint64_t ver; +} imginfo_t; + #ifdef __cplusplus - extern "C" { +extern "C" { #endif +extern void OTA_GetImageInfo(imginfo_t *info); +extern uint32_t OTA_GetBase(void); + extern uint32_t OTA_UpdateImage(uint32_t offset, uint32_t len, uint8_t *data); extern uint32_t OTA_ReadImage(uint32_t offset, uint32_t len, uint8_t *data); extern uint32_t OTA_MarkUpdateDone(void); diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h index 93b08da5da7..819454c28f8 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_adc.h @@ -45,8 +45,7 @@ enum _ADC_DBG_LVL_ { typedef uint32_t ADC_DBG_LVL; typedef uint32_t * PADC_DBG_LVL; -#ifdef CONFIG_DEBUG_LOG -#ifdef CONFIG_DEBUG_LOG_ADC_HAL +#if defined (CONFIG_DEBUG_LOG) && defined (CONFIG_DEBUG_LOG_ADC_HAL) #define DBG_8195A_ADC(...) do{ \ _DbgDump("\r"ADC_PREFIX __VA_ARGS__);\ @@ -64,7 +63,6 @@ typedef uint32_t * PADC_DBG_LVL; #define DBG_8195A_ADC(...) #define DBG_8195A_ADC_LVL(...) #endif -#endif //================ ADC HAL Related Enumeration ================== diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h index 3e0b6cce154..b716cbaae32 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/hal_timer.h @@ -53,9 +53,10 @@ typedef struct _HAL_TIMER_OP_ { }HAL_TIMER_OP, *PHAL_TIMER_OP; typedef struct _HAL_TIMER_OP_EXT_ { - PHAL_TIMER_OP phal_timer_op_rom; - VOID (*HalTimerIrqEn)(u32 TimerId); - VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs); + PHAL_TIMER_OP phal_timer_op_rom; + VOID (*HalTimerIrqEn)(u32 TimerId); + VOID (*HalTimerReLoad)(u32 TimerId, u32 LoadUs); + VOID (*HalTimerSync)(u32 TimerId); }HAL_TIMER_OP_EXT, *PHAL_TIMER_OP_EXT; #ifdef CONFIG_TIMER_MODULE diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c index 504eb7c1bd9..91d7f40027c 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/us_ticker.c @@ -19,9 +19,8 @@ #include "us_ticker_api.h" #include "PeripheralNames.h" -#define TICK_READ_FROM_CPU 0 // 1: read tick from CPU, 0: read tick from G-Timer #define SYS_TIM_ID 1 // the G-Timer ID for System -#define APP_TIM_ID 6 // the G-Timer ID for Application +#define APP_TIM_ID 2 // the G-Timer ID for Application /* * For RTL8195AM, clock source is 32k @@ -33,8 +32,6 @@ * * Define the following macros to convert between TICK and US. */ -#define MS_TO_TICK(x) (uint64_t)(((x)*327) / 10) -#define US_TO_TICK(x) (uint64_t)(((x)*32) / 1000) #define TICK_TO_US(x) (uint64_t)(((x)/2) * 61 + ((x)%2) * TIMER_TICK_US) static int us_ticker_inited = 0; @@ -73,49 +70,45 @@ void us_ticker_init(void) TimerAdapter.TimerMode = USER_DEFINED; HalTimerOp.HalTimerInit((void *) &TimerAdapter); - - DBG_TIMER_INFO("%s: Timer_Id=%d\n", __FUNCTION__, APP_TIM_ID); } uint32_t us_ticker_read(void) { uint32_t tick_cnt; - uint64_t tick_us; if (!us_ticker_inited) { us_ticker_init(); } tick_cnt = HalTimerOp.HalTimerReadCount(SYS_TIM_ID); - tick_us = TICK_TO_US(0xFFFFFFFFUL - tick_cnt); - - return ((uint32_t)tick_us); //return ticker value in micro-seconds (us) + return (uint32_t)TICK_TO_US(0xFFFFFFFFUL - tick_cnt); } void us_ticker_set_interrupt(timestamp_t timestamp) { uint32_t time_cur; - uint32_t time_cnt; - HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); time_cur = us_ticker_read(); if (timestamp > time_cur + TIMER_TICK_US) { - time_cnt = timestamp - time_cur; + TimerAdapter.TimerLoadValueUs = timestamp - time_cur; } else { - HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, 0xffffffff); - HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); - us_ticker_fire_interrupt(); - return; + TimerAdapter.TimerLoadValueUs = TIMER_TICK_US; } - TimerAdapter.TimerLoadValueUs = MAX(MS_TO_TICK(time_cnt/1000) + US_TO_TICK(time_cnt%1000), 1); + HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs); + HalTimerOpExt.HalTimerSync(SYS_TIM_ID); HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); } void us_ticker_fire_interrupt(void) { - NVIC_SetPendingIRQ(TIMER2_7_IRQ); + TimerAdapter.TimerLoadValueUs = TIMER_TICK_US; + + HalTimerOp.HalTimerDis((u32)TimerAdapter.TimerId); + HalTimerOpExt.HalTimerReLoad((u32)TimerAdapter.TimerId, TimerAdapter.TimerLoadValueUs); + HalTimerOpExt.HalTimerSync(SYS_TIM_ID); + HalTimerOp.HalTimerEn((u32)TimerAdapter.TimerId); } void us_ticker_disable_interrupt(void) @@ -125,5 +118,4 @@ void us_ticker_disable_interrupt(void) void us_ticker_clear_interrupt(void) { - HalTimerOp.HalTimerIrqClear((u32)TimerAdapter.TimerId); } diff --git a/targets/TARGET_Realtek/mbed_rtx.h b/targets/TARGET_Realtek/mbed_rtx.h index cbf7b73fbc1..1da2503cd2c 100644 --- a/targets/TARGET_Realtek/mbed_rtx.h +++ b/targets/TARGET_Realtek/mbed_rtx.h @@ -20,7 +20,7 @@ #include "rtl8195a.h" -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) || (__ARMCC_VERSION >= 6010050)) +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[]; extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[]; #define ISR_STACK_START (unsigned char *)(Image$$ARM_LIB_STACK$$ZI$$Base) @@ -33,22 +33,11 @@ #define INITIAL_SP (__StackTop) #endif - -#if defined(__CC_ARM) || defined(__GNUC__) +#if defined(__GNUC__) #ifndef ISR_STACK_SIZE #define ISR_STACK_SIZE (0x1000) #endif #endif -#ifndef OS_TASKCNT -#define OS_TASKCNT 14 -#endif -#ifndef OS_MAINSTKSIZE -#define OS_MAINSTKSIZE 256 -#endif -#ifndef OS_CLOCK -#define OS_CLOCK PLATFORM_CLK -#endif - #endif #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h index 2c662d8d403..3f0c4e35f60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h @@ -47,6 +47,7 @@ #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h index 2c662d8d403..3f0c4e35f60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h @@ -47,6 +47,7 @@ #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h index 760f6b9c748..e8d74550477 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h @@ -46,6 +46,7 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c index 79eaa6c91e2..3ef6261bf95 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library - '******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,33 +30,42 @@ #include "PeripheralPins.h" -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 - {NC, NC, 0} + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 + {NC, NC, 0} }; const PinMap PinMap_ADC_Internal[] = { {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC_IN16 {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC_IN17 {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 - {NC, NC, 0} + {NC, NC, 0} }; //*** I2C *** @@ -66,48 +75,46 @@ const PinMap PinMap_I2C_SDA[] = { {PA_12, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C1)}, {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, {PF_0, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_I2C_SCL[] = { {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PA_11, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C1)}, {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, {PF_1, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {NC, NC, 0} + {NC, NC, 0} }; //*** PWM *** -// TIM2 cannot be used because already used by the us_ticker +// TIM2 (PWM_2) cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { -// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX -// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 - {PA_4, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 - {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 -// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 - {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 -// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N -// {PA_7, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 -// {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 - {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 -// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 - {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 -// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 - {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 - {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N - {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N -// {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 - {NC, NC, 0} +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PA_4, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - Connected to LED + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {NC, NC, 0} }; //*** SERIAL *** @@ -115,9 +122,9 @@ const PinMap PinMap_PWM[] = { const PinMap PinMap_UART_TX[] = { {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, -// {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // SWCLK +// {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to SWCLK {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { @@ -125,54 +132,55 @@ const PinMap PinMap_UART_RX[] = { {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, - {NC, NC, 0} + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} }; const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, - {NC, NC, 0} + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {NC, NC, 0} }; const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, - {NC, NC, 0} + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to LED + {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX - {NC, NC, 0} + {NC, NC, 0} }; +//*** CAN *** + const PinMap PinMap_CAN_RD[] = { -// {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)}, {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_CAN_TD[] = { {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_CAN)}, - {NC, NC, 0} + {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h index 14d009eef16..a148910e590 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/PinNames.h @@ -37,6 +37,13 @@ extern "C" { #endif +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + typedef enum { PA_0 = 0x00, PA_1 = 0x01, @@ -45,7 +52,11 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT1 = PA_7|ALT1, + PA_7_ALT2 = PA_7|ALT2, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, @@ -56,7 +67,10 @@ typedef enum { PA_15 = 0x0F, PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT1 = PB_1|ALT1, PB_3 = 0x13, PB_4 = 0x14, PB_5 = 0x15, diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h index 34e8fead9a7..0caa0508c08 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h @@ -46,6 +46,7 @@ extern "C" { #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h index 2c662d8d403..3f0c4e35f60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h @@ -47,6 +47,7 @@ #define TIM_MST_UP_IRQ TIM1_BRK_UP_TRG_COM_IRQn #define TIM_MST_OC_IRQ TIM1_CC_IRQn #define TIM_MST_RCC __TIM1_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM1() #define TIM_MST_RESET_ON __TIM1_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM1_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h index 082b22cebba..42c96c85c60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h index 082b22cebba..42c96c85c60 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c similarity index 70% rename from targets/TARGET_STM/TARGET_STM32F0/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32F0/analogin_device.c index bfa8adc4433..f60f6bc02c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32F0/analogin_device.c @@ -33,12 +33,13 @@ #include "mbed_wait_api.h" #include "cmsis.h" #include "pinmap.h" -#include "PeripheralPins.h" #include "mbed_error.h" +#include "PeripheralPins.h" +#include -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) { +void analogin_init(analogin_t *obj, PinName pin) +{ + static bool adc_calibrated = false; uint32_t function = (uint32_t)NC; // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) @@ -47,14 +48,14 @@ void analogin_init(analogin_t *obj, PinName pin) { if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -66,40 +67,38 @@ void analogin_init(analogin_t *obj, PinName pin) { // Save pin number for the read function obj->pin = pin; - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; - obj->handle.Init.Resolution = ADC_RESOLUTION12b; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; - obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; - obj->handle.Init.LowPowerAutoWait = DISABLE; - obj->handle.Init.LowPowerAutoPowerOff = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; - if (HAL_ADC_Init(&obj->handle) != HAL_OK) { - error("Cannot initialize ADC"); - } - // Run the ADC calibration - if (HAL_ADCEx_Calibration_Start(&obj->handle) != HAL_OK) { - error("Cannot Start ADC_Calibration"); - } + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; + obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; + obj->handle.Init.LowPowerAutoWait = DISABLE; + obj->handle.Init.LowPowerAutoPowerOff = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; + + __HAL_RCC_ADC1_CLK_ENABLE(); + + if (HAL_ADC_Init(&obj->handle) != HAL_OK) { + error("Cannot initialize ADC"); + } + + // ADC calibration is done only once + if (!adc_calibrated) { + adc_calibrated = true; + HAL_ADCEx_Calibration_Start(&obj->handle); } } -static inline uint16_t adc_read(analogin_t *obj) { - ADC_ChannelConfTypeDef sConfig; +uint16_t adc_read(analogin_t *obj) +{ + ADC_ChannelConfTypeDef sConfig = {0}; // Configure ADC channel sConfig.Rank = ADC_RANK_CHANNEL_NUMBER; @@ -182,22 +181,10 @@ static inline uint16_t adc_read(analogin_t *obj) { // Wait end of conversion and get value if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) { - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) { - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c index c8891f85d8a..da73e70b309 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/analogout_device.c @@ -36,7 +36,7 @@ #include "PeripheralPins.h" void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); @@ -71,6 +71,8 @@ void analogout_init(dac_t *obj, PinName pin) { // Configure DAC obj->handle.Instance = (DAC_TypeDef *)(obj->dac); + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32F0/can_device.h b/targets/TARGET_STM/TARGET_STM32F0/can_device.h index cff47d6a4c6..c1fa6fab6ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F0/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32f0xx_hal.h" +#include "stm32f0xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie +#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie #define CAN1_IRQ_RX_IRQN CEC_CAN_IRQn #define CAN1_IRQ_RX_VECT CAN_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index 600642db789..36023d28e75 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -478,9 +478,7 @@ void serial_clear(serial_t *obj) void serial_break_set(serial_t *obj) { struct serial_s *obj_s = SERIAL_S(obj); - UART_HandleTypeDef *huart = &uart_handlers[obj_s->index]; - - //HAL_LIN_SendBreak(huart); + UART_HandleTypeDef *huart __attribute__((unused)) = &uart_handlers[obj_s->index]; } #if DEVICE_SERIAL_ASYNCH @@ -798,9 +796,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -874,8 +872,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF); - volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag - UNUSED(tmpval); + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h index 91fd0c3789e..ac309396258 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn #define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() #define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h index 91fd0c3789e..ac309396258 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn #define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() #define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h index 91fd0c3789e..ac309396258 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM4 #define TIM_MST_IRQ TIM4_IRQn #define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4() #define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c b/targets/TARGET_STM/TARGET_STM32F1/analogin_device.c similarity index 79% rename from targets/TARGET_STM/TARGET_STM32F1/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32F1/analogin_device.c index c617a3420dd..4dd0e6cdec8 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32F1/analogin_device.c @@ -33,12 +33,13 @@ #include "mbed_wait_api.h" #include "cmsis.h" #include "pinmap.h" +#include "mbed_error.h" #include "PeripheralPins.h" - -int adc_inited = 0; +#include void analogin_init(analogin_t *obj, PinName pin) { + static bool adc_calibrated = false; RCC_PeriphCLKInitTypeDef PeriphClkInit; uint32_t function = (uint32_t)NC; @@ -48,14 +49,14 @@ void analogin_init(analogin_t *obj, PinName pin) if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -67,13 +68,26 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __HAL_RCC_ADC1_CLK_ENABLE(); + // Enable ADC clock + __HAL_RCC_ADC1_CLK_ENABLE(); + + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.ScanConvMode = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.NbrOfConversion = 1; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.NbrOfDiscConversion = 0; + obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; + + if (HAL_ADC_Init(&obj->handle) != HAL_OK) { + error("Cannot initialize ADC"); + } + // This section is done only once + if (!adc_calibrated) { + adc_calibrated = true; // Configure ADC clock prescaler // Caution: On STM32F1, ADC clock frequency max is 14 MHz (refer to device datasheet). // Therefore, ADC clock prescaler must be configured in function @@ -83,23 +97,14 @@ void analogin_init(analogin_t *obj, PinName pin) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); - - // Configure ADC - obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.ScanConvMode = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.NbrOfConversion = 1; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.NbrOfDiscConversion = 0; - obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; - HAL_ADC_Init(&obj->handle); + // Calibration + HAL_ADCEx_Calibration_Start(&obj->handle); } } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { - ADC_ChannelConfTypeDef sConfig; + ADC_ChannelConfTypeDef sConfig = {0}; // Configure ADC channel sConfig.Rank = 1; @@ -170,24 +175,10 @@ static inline uint16_t adc_read(analogin_t *obj) // Wait end of conversion and get value if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/can_device.h b/targets/TARGET_STM/TARGET_STM32F1/can_device.h index 3792d0743e9..3a8438faed5 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F1/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32f1xx_hal.h" +#include "stm32f1xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie +#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie #define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn #define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c index bec0085ea28..106f15e691b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_smartcard.c @@ -500,7 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; uint32_t tickstart = 0U; if(hsc->RxState == HAL_SMARTCARD_STATE_READY) @@ -530,8 +529,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData; - *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); + *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); pData +=1U; } diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c index d427407f6d1..8c9cf38f214 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c @@ -172,7 +172,7 @@ static void uart_irq(int id) } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } } @@ -542,13 +542,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } @@ -599,9 +599,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -675,7 +675,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); - volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h index cc5b124ad1d..94a71d0eef6 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h @@ -46,6 +46,7 @@ extern "C" { #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c b/targets/TARGET_STM/TARGET_STM32F2/analogin_device.c similarity index 79% rename from targets/TARGET_STM/TARGET_STM32F2/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32F2/analogin_device.c index 19c82c20362..c014c2f5726 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32F2/analogin_device.c @@ -40,29 +40,20 @@ void analogin_init(analogin_t *obj, PinName pin) { uint32_t function = (uint32_t)NC; -#if defined(ADC1) - static int adc1_inited = 0; -#endif -#if defined(ADC2) - static int adc2_inited = 0; -#endif -#if defined(ADC3) - static int adc3_inited = 0; -#endif // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) // are described in PinNames.h and PeripheralPins.c // Pin value must be between 0xF0 and 0xFF if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -74,55 +65,49 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // Check if ADC is already initialized - // Enable ADC clock + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.ScanConvMode = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.NbrOfDiscConversion = 0; + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.NbrOfConversion = 1; + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.EOCSelection = DISABLE; + #if defined(ADC1) - if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return; if ((ADCName)obj->handle.Instance == ADC_1) { - __ADC1_CLK_ENABLE(); - adc1_inited = 1; + __HAL_RCC_ADC1_CLK_ENABLE(); } #endif #if defined(ADC2) - if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return; if ((ADCName)obj->handle.Instance == ADC_2) { - __ADC2_CLK_ENABLE(); - adc2_inited = 1; + __HAL_RCC_ADC2_CLK_ENABLE(); } #endif #if defined(ADC3) - if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return; if ((ADCName)obj->handle.Instance == ADC_3) { - __ADC3_CLK_ENABLE(); - adc3_inited = 1; + __HAL_RCC_ADC3_CLK_ENABLE(); } #endif - // Configure ADC - obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; - obj->handle.Init.Resolution = ADC_RESOLUTION12b; - obj->handle.Init.ScanConvMode = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.NbrOfDiscConversion = 0; - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.NbrOfConversion = 1; - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.EOCSelection = DISABLE; + if (HAL_ADC_Init(&obj->handle) != HAL_OK) { - error("Cannot initialize ADC\n"); + error("Cannot initialize ADC"); } } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig = {0}; // Configure ADC channel sConfig.Rank = 1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + sConfig.SamplingTime = ADC_SAMPLETIME_15CYCLES; sConfig.Offset = 0; switch (obj->channel) { @@ -193,24 +178,10 @@ static inline uint16_t adc_read(analogin_t *obj) // Wait end of conversion and get value if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c index 584034fc85f..3976d5b0840 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/analogout_device.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -25,6 +25,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "mbed_assert.h" #include "analogout_api.h" #if DEVICE_ANALOGOUT @@ -32,19 +33,20 @@ #include "cmsis.h" #include "pinmap.h" #include "mbed_error.h" -#include "stm32f2xx_hal.h" #include "PeripheralPins.h" void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; - // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object + // Get the peripheral name from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); - // Get the functions (dac channel) from the pin and assign it to the object + MBED_ASSERT(obj->dac != (DACName)NC); + + // Get the pin function and assign the used channel to the object uint32_t function = pinmap_function(pin, PinMap_DAC); MBED_ASSERT(function != (uint32_t)NC); - // Save the channel for the write and read functions + switch (STM_PIN_CHANNEL(function)) { case 1: obj->channel = DAC_CHANNEL_1; @@ -59,18 +61,19 @@ void analogout_init(dac_t *obj, PinName pin) break; } - if (obj->dac == (DACName)NC) { - error("DAC pin mapping failed"); - } - // Configure GPIO pinmap_pinout(pin, PinMap_DAC); - __GPIOA_CLK_ENABLE(); + // Save the pin for future use + obj->pin = pin; + + // Enable DAC clock + __HAL_RCC_DAC_CLK_ENABLE(); - __DAC_CLK_ENABLE(); + // Configure DAC + obj->handle.Instance = (DAC_TypeDef *)(obj->dac); + obj->handle.State = HAL_DAC_STATE_RESET; - obj->handle.Instance = DAC; if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } @@ -87,8 +90,13 @@ void analogout_init(dac_t *obj, PinName pin) void analogout_free(dac_t *obj) { -} - + // Reset DAC and disable clock + __HAL_RCC_DAC_FORCE_RESET(); + __HAL_RCC_DAC_RELEASE_RESET(); + __HAL_RCC_DAC_CLK_DISABLE(); + // Configure GPIO + pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); +} #endif // DEVICE_ANALOGOUT diff --git a/targets/TARGET_STM/TARGET_STM32F2/can_device.h b/targets/TARGET_STM/TARGET_STM32F2/can_device.h index 97a54210a06..cb95b44ea83 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F2/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32f2xx_hal.h" +#include "stm32f2xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2) +#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie #define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn #define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h index 546122d81ec..ea2397fe571 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h @@ -130,9 +130,9 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask; + newValue = (uint32_t)__LDREXW(ptr) | mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } @@ -140,9 +140,9 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask; + newValue = (uint32_t)__LDREXW(ptr) &~mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } #if defined ( __GNUC__ ) && !defined ( __CC_ARM ) diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c index e76577faa30..b04749ff634 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_smartcard.c @@ -496,7 +496,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; uint32_t tickstart = 0U; if(hsc->RxState == HAL_SMARTCARD_STATE_READY) @@ -526,8 +525,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData; - *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); + *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); pData +=1U; } diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h index e87ecf78a7c..a961a63a448 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -62,7 +62,8 @@ struct analogin_s { struct dac_s { DACName dac; - uint8_t channel; + PinName pin; + uint32_t channel; DAC_HandleTypeDef handle; }; diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index c1d16826937..7f238971756 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -259,7 +259,7 @@ static void uart_irq(int id) } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } } @@ -720,13 +720,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } @@ -777,9 +777,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -853,7 +853,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); - volatile uint32_t tmpval = huart->Instance->DR; // Clear error flags + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear error flags // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h index 8ff2fb0ace0..8bd5f6b136e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c index 7f6fa41ee5b..1478979209a 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,28 +30,35 @@ #include "PeripheralPins.h" -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO A0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO A1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A2 - {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO A3 - {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO A4 - {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - ARDUINO A5 - {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A7 - + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO A0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO A1 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 - Connected to STDIO_UART_TX + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO A2 + {PA_4, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO A3 + {PA_5, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO A4 + {PA_6, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 - ARDUINO A5 + {PA_7, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO A7 {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 - ARDUINO D3 {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 - ARDUINO D6 - - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_ADC_Internal[] = { @@ -60,8 +67,7 @@ const PinMap PinMap_ADC_Internal[] = { {ADC_VREF2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_IN18 {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 {ADC_VOPAMP2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC2_IN17 - - {NC, NC, 0} + {NC, NC, 0} }; //*** DAC *** @@ -70,136 +76,135 @@ const PinMap PinMap_DAC[] = { {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 - ARDUINO A3 {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - ARDUINO A4 {PA_6, DAC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC2_OUT1 - ARDUINO A5 - {NC, NC, 0} + {NC, NC, 0} }; //*** I2C *** const PinMap PinMap_I2C_SDA[] = { - {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PA_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_I2C_SCL[] = { - {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, +// {PA_15, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, - {NC, NC, 0} + {NC, NC, 0} }; //*** PWM *** -// TIM2 cannot be used because already used by the us_ticker +// TIM2 (PWM_2) cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { -// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 -// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 - {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 - {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 -// {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 -// {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 - {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 -// {PA_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 - {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 -// {PA_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 - {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 -// {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N - {PA_12, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 -// {PA_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N - {PA_13, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N -// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - -// {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 - {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N -// {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 - {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - {PB_4, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 -// {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -// {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - {PB_5, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)},// TIM17_CH1 - {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - ARDUINO - {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N -// {PB_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 - - {PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N - - {NC, NC, 0} +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX +// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM15, 2, 0)}, // TIM15_CH2 + {PA_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 3, 0)}, // TIM2_CH3 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 0)}, // TIM1_CH3 +// {PA_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM2, 4, 0)}, // TIM2_CH4 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_TIM1, 4, 0)}, // TIM1_CH4 + {PA_11_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 1, 1)}, // TIM1_CH1N + {PA_12, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PA_12_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PA_13, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - Connected to STDIO_UART_RX + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - Connected to LED + {PB_4, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_4_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM17, 1, 0)},// TIM17_CH1 + {PB_5_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N - ARDUINO + {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_TIM3, 4, 0)}, // TIM3_CH4 + {PF_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NC, 0} }; //*** SERIAL *** const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to LED {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {NC, NC, 0} + {NC, NC, 0} }; //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} }; const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} }; const PinMap PinMap_SPI_SCLK[] = { - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Warning: LED1 is connected on this pin - {NC, NC, 0} + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to LED + {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} +// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to STDIO_UART_RX + {NC, NC, 0} }; +//*** CAN *** + const PinMap PinMap_CAN_RD[] = { {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_CAN_TD[] = { - {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, - {NC, NC, 0} + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN)}, + {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h index c46b324dfc6..65b8674ddf7 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/TARGET_NUCLEO_F303K8/PinNames.h @@ -37,6 +37,13 @@ extern "C" { #endif +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + typedef enum { PA_0 = 0x00, PA_1 = 0x01, @@ -45,23 +52,33 @@ typedef enum { PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT1 = PA_7|ALT1, PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_11_ALT0 = PA_11|ALT0, PA_12 = 0x0C, + PA_12_ALT0 = PA_12|ALT0, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, PB_3 = 0x13, PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, PB_6 = 0x16, PB_7 = 0x17, + PB_7_ALT0 = PB_7|ALT0, PF_0 = 0x50, PF_1 = 0x51, diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h index 8ff2fb0ace0..8bd5f6b136e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h index 8ff2fb0ace0..8bd5f6b136e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h index 8ff2fb0ace0..8bd5f6b136e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h index 8ff2fb0ace0..8bd5f6b136e 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c b/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c similarity index 79% rename from targets/TARGET_STM/TARGET_STM32F3/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32F3/analogin_device.c index 80a4de12f86..ba4970e3a8c 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32F3/analogin_device.c @@ -35,23 +35,11 @@ #include "pinmap.h" #include "mbed_error.h" #include "PeripheralPins.h" - +#include void analogin_init(analogin_t *obj, PinName pin) { -#if defined(ADC1) - static int adc1_inited = 0; -#endif -#if defined(ADC2) - static int adc2_inited = 0; -#endif -#if defined(ADC3) - static int adc3_inited = 0; -#endif -#if defined(ADC4) - static int adc4_inited = 0; -#endif - + static bool adc_calibrated = false; uint32_t function = (uint32_t)NC; // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) @@ -60,14 +48,14 @@ void analogin_init(analogin_t *obj, PinName pin) if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -79,60 +67,56 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // Check if ADC is already initialized - // Enable ADC clock + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.ScanConvMode = DISABLE; + obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; + obj->handle.Init.LowPowerAutoWait = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.NbrOfConversion = 1; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.NbrOfDiscConversion = 0; + obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; + #if defined(ADC1) - if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return; if ((ADCName)obj->handle.Instance == ADC_1) { - __ADC1_CLK_ENABLE(); - adc1_inited = 1; + __HAL_RCC_ADC1_CLK_ENABLE(); } #endif #if defined(ADC2) - if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return; if ((ADCName)obj->handle.Instance == ADC_2) { - __ADC2_CLK_ENABLE(); - adc2_inited = 1; + __HAL_RCC_ADC2_CLK_ENABLE(); } #endif #if defined(ADC3) - if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return; if ((ADCName)obj->handle.Instance == ADC_3) { - __ADC34_CLK_ENABLE(); - adc3_inited = 1; + __HAL_RCC_ADC34_CLK_ENABLE(); } #endif #if defined(ADC4) - if (((ADCName)obj->handle.Instance == ADC_4) && adc4_inited) return; if ((ADCName)obj->handle.Instance == ADC_4) { - __ADC34_CLK_ENABLE(); - adc4_inited = 1; + __HAL_RCC_ADC34_CLK_ENABLE(); } #endif - // Configure ADC - obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2; - obj->handle.Init.Resolution = ADC_RESOLUTION12b; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.ScanConvMode = DISABLE; - obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; - obj->handle.Init.LowPowerAutoWait = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.NbrOfConversion = 1; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.NbrOfDiscConversion = 0; - obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; - if (HAL_ADC_Init(&obj->handle) != HAL_OK) { error("Cannot initialize ADC"); } + + // ADC calibration is done only once + if (!adc_calibrated) { + adc_calibrated = true; + HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED); + } } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig = {0}; @@ -208,24 +192,10 @@ static inline uint16_t adc_read(analogin_t *obj) // Wait end of conversion and get value if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c index 6bc7da1e5b0..4b17b6e5f2f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/analogout_device.c @@ -40,7 +40,7 @@ static int pa4_used = 0; static int pa5_used = 0; void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); @@ -83,6 +83,8 @@ void analogout_init(dac_t *obj, PinName pin) { // Configure DAC obj->handle.Instance = (DAC_TypeDef *)(obj->dac); + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32F3/can_device.h b/targets/TARGET_STM/TARGET_STM32F3/can_device.h index 1d777682008..121999c6811 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F3/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32f3xx_hal.h" +#include "stm32f3xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie +#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie #define CAN1_IRQ_RX_IRQN CAN_RX0_IRQn #define CAN1_IRQ_RX_VECT CAN_RX0_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h index 757a6e8458d..87328a7192c 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h @@ -129,9 +129,9 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask; + newValue = (uint32_t)__LDREXW(ptr) | mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } @@ -139,9 +139,9 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask; + newValue = (uint32_t)__LDREXW(ptr) &~mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } #if defined ( __GNUC__ ) && !defined ( __CC_ARM ) diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c index be5660a0863..b1f2de8ca06 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c @@ -697,9 +697,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -773,8 +773,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF); - volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag - UNUSED(tmpval); + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf index f702047a09c..46363c1caf5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/stm32f412xx.icf @@ -10,7 +10,7 @@ define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE; define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x200001C7; /* Aligned on 8 bytes */ define symbol __region_RAM_start__ = 0x200001C8; -define symbol __region_RAM_end__ = 0x2001FFFF; +define symbol __region_RAM_end__ = 0x2003FFFF; /* Memory regions */ define memory mem with size = 4G; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h index e428968d4a6..5627990658b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h index d5ede91000a..02aa6028c22 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h index d5ede91000a..02aa6028c22 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h similarity index 97% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h index fb1cdab06b6..fcd76d01523 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralNames.h @@ -57,9 +57,8 @@ typedef enum { UART_8 = (int)UART8_BASE } UARTName; -#define STDIO_UART_TX PA_9 -#define STDIO_UART_RX PA_10 -#define STDIO_UART UART_1 +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX typedef enum { SPI_1 = (int)SPI1_BASE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PeripheralPins.c rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h new file mode 100644 index 00000000000..ea26b948073 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MBED_CONNECT_ODIN/PinNames.h @@ -0,0 +1,173 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, PA_3 = 0x03, + PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, + PA_8 = 0x08, PA_9 = 0x09, PA_10 = 0x0A, PA_11 = 0x0B, + PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, PA_15 = 0x0F, + + PB_0 = 0x10, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, PB_7 = 0x17, + PB_8 = 0x18, PB_9 = 0x19, PB_10 = 0x1A, PB_11 = 0x1B, + PB_12 = 0x1C, PB_13 = 0x1D, PB_14 = 0x1E, PB_15 = 0x1F, + + PC_0 = 0x20, PC_1 = 0x21, PC_2 = 0x22, PC_3 = 0x23, + PC_4 = 0x24, PC_5 = 0x25, PC_6 = 0x26, PC_7 = 0x27, + PC_8 = 0x28, PC_9 = 0x29, PC_10 = 0x2A, PC_11 = 0x2B, + PC_12 = 0x2C, PC_13 = 0x2D, PC_14 = 0x2E, PC_15 = 0x2F, + + PD_0 = 0x30, PD_1 = 0x31, PD_2 = 0x32, PD_3 = 0x33, + PD_4 = 0x34, PD_5 = 0x35, PD_6 = 0x36, PD_7 = 0x37, + PD_8 = 0x38, PD_9 = 0x39, PD_10 = 0x3A, PD_11 = 0x3B, + PD_12 = 0x3C, PD_13 = 0x3D, PD_14 = 0x3E, PD_15 = 0x3F, + + PE_0 = 0x40, PE_1 = 0x41, PE_2 = 0x42, PE_3 = 0x43, + PE_4 = 0x44, PE_5 = 0x45, PE_6 = 0x46, PE_7 = 0x47, + PE_8 = 0x48, PE_9 = 0x49, PE_10 = 0x4A, PE_11 = 0x4B, + PE_12 = 0x4C, PE_13 = 0x4D, PE_14 = 0x4E, PE_15 = 0x4F, + + PF_0 = 0x50, PF_1 = 0x51, PF_2 = 0x52, PF_3 = 0x53, + PF_4 = 0x54, PF_5 = 0x55, PF_6 = 0x56, PF_7 = 0x57, + PF_8 = 0x58, PF_9 = 0x59, PF_10 = 0x5A, PF_11 = 0x5B, + PF_12 = 0x5C, PF_13 = 0x5D, PF_14 = 0x5E, PF_15 = 0x5F, + + PG_0 = 0x60, PG_1 = 0x61, PG_2 = 0x62, PG_3 = 0x63, + PG_4 = 0x64, PG_5 = 0x65, PG_6 = 0x66, PG_7 = 0x67, + PG_8 = 0x68, PG_9 = 0x69, PG_10 = 0x6A, PG_11 = 0x6B, + PG_12 = 0x6C, PG_13 = 0x6D, PG_14 = 0x6E, PG_15 = 0x6F, + + PH_0 = 0x70, PH_1 = 0x71, PH_2 = 0x72, PH_3 = 0x73, + PH_4 = 0x74, PH_5 = 0x75, PH_6 = 0x76, PH_7 = 0x77, + PH_8 = 0x78, PH_9 = 0x79, PH_10 = 0x7A, PH_11 = 0x7B, + PH_12 = 0x7C, PH_13 = 0x7D, PH_14 = 0x7E, PH_15 = 0x7F, + + // Module Pins + // A + P_A5 = PC_2, // UART-DTR + P_A6 = PF_2, // Switch-0 + P_A7 = PE_0, // Red, Mode + P_A8 = PB_6, // Green, Switch-1 + P_A9 = PB_8, // Blue + P_A10 = PA_11, // UART-CTS + P_A11 = PA_9, // UART-TXD + P_A12 = PA_12, // UART-RTS + P_A13 = PA_10, // UART-RXD + P_A14 = PD_9, // GPIO-0 + P_A15 = PD_8, // GPIO-1 + P_A16 = PD_11, // GPIO-2 + P_A17 = PD_12, // GPIO-3 + P_A18 = PA_3, // UART-DSR + // B + // C + P_C5 = PG_4, // SPI-IRQ + P_C6 = PE_13, // SPI-MISO + P_C8 = PE_12, // Res + P_C10 = PE_14, // SPI-MOSI + P_C11 = PE_11, // SPI-CS0 + P_C12 = PE_9, // Res + P_C13 = PF_6, // GPIO-4 + P_C14 = PC_1, // RMII-MDC + P_C15 = PA_2, // RMII-MDIO + P_C16 = PF_7, // GPIO-7 + P_C17 = PF_1, // I2C-SCL + P_C18 = PF_0, // I2C-SDA + // D + P_D1 = PB_12, // RMII-TXD0 + P_D2 = PB_13, // RMII-TXD1 + P_D3 = PB_11, // RMII-TXEN + P_D4 = PA_7, // RMII-CRSDV + P_D5 = PC_4, // RMII-RXD0 + P_D6 = PC_5, // RMII-RXD1 + P_D8 = PA_1, // RMII-REFCLK + // TP + P_TP5 = PB_4, // NTRST + P_TP7 = PA_13, // TMS SWDIO + P_TP8 = PA_15, // TDI + P_TP9 = PA_14, // TCK SWCLK + P_TP10 = PB_3, // TDO + //P_TP11, // BOOT0 + + // Internal + LED1 = PD_9, + LED2 = PA_12, + LED3 = PD_8, + LED4 = PA_11, + LED5 = PC_2, + LED6 = PA_3, + LED7 = PF_6, + LED_RED = PE_0, + LED_GREEN = PB_6, + LED_BLUE = PB_8, + SW1 = PF_2, + SW2 = PG_4, + + // Standardized button names + BUTTON1 = SW1, + BUTTON2 = SW2, + + I2C_SDA = PF_0, + I2C_SCL = PF_1, + SPI0_MOSI = PE_14, + SPI0_MISO = PE_13, + SPI0_SCK = PE_12, + SPI0_CS = PE_11, + SPI1_CS = PE_9, + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, + + // DAPLink + USBRX = MBED_CONF_TARGET_USB_RX, + USBTX = MBED_CONF_TARGET_USB_TX, + SWDIO = PA_15, + SWCLK = PA_14, + NTRST = PB_4, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h similarity index 94% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h index c4137a2e0f8..e6b09b75023 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_UBLOX_EVK_ODIN_W2/PinNames.h @@ -159,6 +159,19 @@ typedef enum { LED_BLUE = LED3, SW0 = PF_2, // Switch-0 SW1 = PB_6, // Green / Switch-1 + + I2C_SCL = D15, + I2C_SDA = D14, + SPI0_MOSI = D11, + SPI0_MISO = D12, + SPI0_SCK = D13, + SPI0_CS = D10, + SPI1_CS = D9, + + SPI_MOSI = SPI0_MOSI, + SPI_MISO = SPI0_MISO, + SPI_SCK = SPI0_SCK, + SPI_CS = SPI0_CS, // Standardized button names @@ -166,8 +179,8 @@ typedef enum { BUTTON2 = SW1, // ST-Link - USBRX = PA_10, - USBTX = PA_9, + USBRX = MBED_CONF_TARGET_USB_RX, + USBTX = MBED_CONF_TARGET_USB_TX, SWDIO = PA_15, SWCLK = PA_14, NTRST = PB_4, diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/LICENSE b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/LICENSE similarity index 100% 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a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_test_man.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_bt_utils.h rename to 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targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_comdefs.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_client.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_server.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_gatt_utils.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_hw.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_main.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_otp.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_platform_basic_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_port_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_status.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_watchdog.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_target_data.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/cb_wlan_types.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.cpp diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/wifi_emac/wifi_emac_api.h diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c similarity index 100% rename from targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/system_clock.c rename to targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar deleted file mode 100644 index 4273207630a..00000000000 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar and /dev/null differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a deleted file mode 100644 index 389522c320c..00000000000 Binary files a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_UBLOX_EVK_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a and /dev/null differ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h index 19d9584eee3..cedecee5453 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c index 48acec0abe1..4c2293602a8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c @@ -37,13 +37,6 @@ #include "stm32f4xx.h" #include "mbed_assert.h" -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - // clock source is selected with CLOCK_SOURCE in json config #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) @@ -97,13 +90,6 @@ void SystemInit(void) SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif - } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld index 5453f9629e6..e8fea5d8b20 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/STM32F446XE.ld @@ -1,7 +1,15 @@ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 512K +#endif + /* Linker script to configure memory regions. */ MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = 0x200001C4, LENGTH = 128k - 0x1C4 } @@ -9,7 +17,7 @@ MEMORY * with other linker script that defines memory regions FLASH and RAM. * It references following symbols, which must be defined in code: * Reset_Handler : Entry of reset handler - * + * * It defines following symbols, which code can use without definition: * __exidx_start * __exidx_end diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h index 35154709357..dede60361a7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h index 90f6a00776c..7f7c8cb4f7a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c b/targets/TARGET_STM/TARGET_STM32F4/analogin_device.c similarity index 85% rename from targets/TARGET_STM/TARGET_STM32F4/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32F4/analogin_device.c index ada98bc4d79..54d266e4c12 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/analogin_device.c @@ -40,29 +40,20 @@ void analogin_init(analogin_t *obj, PinName pin) { uint32_t function = (uint32_t)NC; -#if defined(ADC1) - static int adc1_inited = 0; -#endif -#if defined(ADC2) - static int adc2_inited = 0; -#endif -#if defined(ADC3) - static int adc3_inited = 0; -#endif // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) // are described in PinNames.h and PeripheralPins.c // Pin value must be between 0xF0 and 0xFF if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -74,50 +65,43 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // Check if ADC is already initialized - // Enable ADC clock + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.ScanConvMode = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.NbrOfDiscConversion = 0; + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.NbrOfConversion = 1; + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.EOCSelection = DISABLE; + #if defined(ADC1) - if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return; if ((ADCName)obj->handle.Instance == ADC_1) { __HAL_RCC_ADC1_CLK_ENABLE(); - adc1_inited = 1; } #endif #if defined(ADC2) - if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return; if ((ADCName)obj->handle.Instance == ADC_2) { __HAL_RCC_ADC2_CLK_ENABLE(); - adc2_inited = 1; } #endif #if defined(ADC3) - if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return; if ((ADCName)obj->handle.Instance == ADC_3) { __HAL_RCC_ADC3_CLK_ENABLE(); - adc3_inited = 1; } #endif - // Configure ADC - obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; - obj->handle.Init.Resolution = ADC_RESOLUTION_12B; - obj->handle.Init.ScanConvMode = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.NbrOfDiscConversion = 0; - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.NbrOfConversion = 1; - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.EOCSelection = DISABLE; if (HAL_ADC_Init(&obj->handle) != HAL_OK) { - error("Cannot initialize ADC\n"); + error("Cannot initialize ADC"); } } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig = {0}; @@ -210,18 +194,4 @@ static inline uint16_t adc_read(analogin_t *obj) } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c index 802fad6bbb1..da07ad678bc 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/analogout_device.c @@ -36,7 +36,7 @@ #include "PeripheralPins.h" void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); @@ -71,6 +71,8 @@ void analogout_init(dac_t *obj, PinName pin) { __HAL_RCC_DAC_CLK_ENABLE(); obj->handle.Instance = DAC; + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32F4/can_device.h b/targets/TARGET_STM/TARGET_STM32F4/can_device.h index ffc85b663c2..16377c24c9f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32f4xx_hal.h" +#include "stm32f4xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,26 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2) +#if defined(CAN3_BASE) && defined(CAN_3) + +#define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie + +#define CAN3_IRQ_RX_IRQN CAN3_RX0_IRQn +#define CAN3_IRQ_RX_VECT CAN3_RX0_IRQHandler +#define CAN3_IRQ_TX_IRQN CAN3_TX_IRQn +#define CAN3_IRQ_TX_VECT CAN3_TX_IRQHandler +#define CAN3_IRQ_ERROR_IRQN CAN3_SCE_IRQn +#define CAN3_IRQ_ERROR_VECT CAN3_SCE_IRQHandler +#define CAN3_IRQ_PASSIVE_IRQN CAN3_SCE_IRQn +#define CAN3_IRQ_PASSIVE_VECT CAN3_SCE_IRQHandler +#define CAN3_IRQ_BUS_IRQN CAN3_SCE_IRQn +#define CAN3_IRQ_BUS_VECT CAN3_SCE_IRQHandler + +#else + +#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie + +#endif #define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn #define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h index 8462aa4fe02..efa60dee6ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h @@ -129,9 +129,9 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask; + newValue = (uint32_t)__LDREXW(ptr) | mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } @@ -139,9 +139,9 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask; + newValue = (uint32_t)__LDREXW(ptr) &~mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } #endif /* USE_RTOS */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_msp_template.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_msp_template.c deleted file mode 100644 index 5f5a6ca1760..00000000000 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_msp_template.c +++ /dev/null @@ -1,119 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hal_msp_template.c - * @author MCD Application Team - * @version V1.4.1 - * @date 09-October-2015 - * @brief This file contains the HAL System and Peripheral (PPP) MSP initialization - * and de-initialization functions. - * It should be copied to the application folder and renamed into 'stm32f4xx_hal_msp.c'. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2015 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hal.h" - -/** @addtogroup STM32F4xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL_MSP HAL MSP - * @brief HAL MSP module. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions - * @{ - */ - -/** - * @brief Initializes the Global MSP. - * @note This function is called from HAL_Init() function to perform system - * level initialization (GPIOs, clock, DMA, interrupt). - * @retval None - */ -void HAL_MspInit(void) -{ - -} - -/** - * @brief DeInitializes the Global MSP. - * @note This functiona is called from HAL_DeInit() function to perform system - * level de-initialization (GPIOs, clock, DMA, interrupt). - * @retval None - */ -void HAL_MspDeInit(void) -{ - -} - -/** - * @brief Initializes the PPP MSP. - * @note This functiona is called from HAL_PPP_Init() function to perform - * peripheral(PPP) system level initialization (GPIOs, clock, DMA, interrupt) - * @retval None - */ -void HAL_PPP_MspInit(void) -{ - -} - -/** - * @brief DeInitializes the PPP MSP. - * @note This functiona is called from HAL_PPP_DeInit() function to perform - * peripheral(PPP) system level de-initialization (GPIOs, clock, DMA, interrupt) - * @retval None - */ -void HAL_PPP_MspDeInit(void) -{ - -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c index 5acd5c89bc5..e08f974c4ca 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c @@ -497,7 +497,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * */ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t* tmp; uint32_t tickstart = 0U; if(hsc->RxState == HAL_SMARTCARD_STATE_READY) @@ -527,8 +526,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { return HAL_TIMEOUT; } - tmp = (uint16_t*) pData; - *tmp = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); + *pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF); pData +=1U; } diff --git a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c index 1455f07aab7..5ba7fb9e495 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32F4/flash_api.c @@ -145,7 +145,6 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { - if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; } @@ -165,7 +164,7 @@ uint32_t flash_get_start_address(const flash_t *obj) } uint32_t flash_get_size(const flash_t *obj) { - return FLASH_SIZE; + return FLASH_SIZE; } /** @@ -175,13 +174,15 @@ uint32_t flash_get_size(const flash_t *obj) */ static uint32_t GetSector(uint32_t address) { - uint32_t sector = 0; + uint32_t sector = 0; uint32_t tmp = address - ADDR_FLASH_SECTOR_0; /* This function supports 1Mb and 2Mb flash sizes */ #if defined(ADDR_FLASH_SECTOR_16) if (address & 0x100000) { // handle 2nd bank + /* Sector will be at least 12 */ sector = FLASH_SECTOR_12; - tmp = address - ADDR_FLASH_SECTOR_12; + tmp -= 0x100000; + address -= 0x100000; } #endif if (address < ADDR_FLASH_SECTOR_4) { // 16k sectorsize @@ -189,14 +190,14 @@ static uint32_t GetSector(uint32_t address) } #if defined(ADDR_FLASH_SECTOR_5) else if (address < ADDR_FLASH_SECTOR_5) { //64k sector size - sector += FLASH_SECTOR_4; + sector += FLASH_SECTOR_4; } else { sector += 4 + (tmp >>17); } #else // In case ADDR_FLASH_SECTOR_5 is not defined, sector 4 is the last one. else { //64k sector size - sector += FLASH_SECTOR_4; + sector += FLASH_SECTOR_4; } #endif return sector; @@ -225,7 +226,7 @@ if((Sector == FLASH_SECTOR_0) || (Sector == FLASH_SECTOR_1) || (Sector == FLASH_ sectorsize = 64 * 1024; } else { sectorsize = 128 * 1024; - } + } return sectorsize; } diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index 0cf5d9be77e..02a3811ccd4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -286,7 +286,7 @@ static void uart_irq(int id) } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, USART_IT_ERR) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } } @@ -782,13 +782,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } @@ -839,9 +839,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -915,7 +915,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); - volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h index fa8cc979639..e67b911185d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h index fa8cc979639..e67b911185d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h index fa8cc979639..e67b911185d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h index fa8cc979639..e67b911185d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c b/targets/TARGET_STM/TARGET_STM32F7/analogin_device.c similarity index 79% rename from targets/TARGET_STM/TARGET_STM32F7/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32F7/analogin_device.c index b0b566bd584..6592383e19f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32F7/analogin_device.c @@ -33,35 +33,27 @@ #include "mbed_wait_api.h" #include "cmsis.h" #include "pinmap.h" -#include "PeripheralPins.h" #include "mbed_error.h" +#include "PeripheralPins.h" void analogin_init(analogin_t *obj, PinName pin) { uint32_t function = (uint32_t)NC; -#if defined(ADC1) - static int adc1_inited = 0; -#endif -#if defined(ADC2) - static int adc2_inited = 0; -#endif -#if defined(ADC3) - static int adc3_inited = 0; -#endif // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) // are described in PinNames.h and PeripheralPins.c // Pin value must be between 0xF0 and 0xFF if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); + // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -73,51 +65,43 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // Check if ADC is already initialized - // Enable ADC clock + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.ScanConvMode = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.NbrOfDiscConversion = 0; + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.NbrOfConversion = 1; + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.EOCSelection = DISABLE; + #if defined(ADC1) - if (((ADCName)obj->handle.Instance == ADC_1) && adc1_inited) return; if ((ADCName)obj->handle.Instance == ADC_1) { __HAL_RCC_ADC1_CLK_ENABLE(); - adc1_inited = 1; } #endif #if defined(ADC2) - if (((ADCName)obj->handle.Instance == ADC_2) && adc2_inited) return; if ((ADCName)obj->handle.Instance == ADC_2) { __HAL_RCC_ADC2_CLK_ENABLE(); - adc2_inited = 1; } #endif #if defined(ADC3) - if (((ADCName)obj->handle.Instance == ADC_3) && adc3_inited) return; if ((ADCName)obj->handle.Instance == ADC_3) { __HAL_RCC_ADC3_CLK_ENABLE(); - adc3_inited = 1; } #endif - // Configure ADC - obj->handle.State = HAL_ADC_STATE_RESET; - obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV4; - obj->handle.Init.Resolution = ADC_RESOLUTION_12B; - obj->handle.Init.ScanConvMode = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.NbrOfDiscConversion = 0; - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T1_CC1; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.NbrOfConversion = 1; - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.EOCSelection = DISABLE; - if (HAL_ADC_Init(&obj->handle) != HAL_OK) { error("Cannot initialize ADC"); } } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig = {0}; @@ -188,33 +172,16 @@ static inline uint16_t adc_read(analogin_t *obj) return 0; } - if (HAL_ADC_ConfigChannel(&obj->handle, &sConfig) != HAL_OK) { - error("Cannot configure ADC channel"); - } + HAL_ADC_ConfigChannel(&obj->handle, &sConfig); HAL_ADC_Start(&obj->handle); // Start conversion // Wait end of conversion and get value - HAL_ADC_PollForConversion(&obj->handle, 10); - if (HAL_ADC_GetState(&obj->handle) & HAL_ADC_STATE_EOC_REG) { - return (HAL_ADC_GetValue(&obj->handle)); + if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c b/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c index 8003d35a51c..d817d3d2808 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/analogout_device.c @@ -36,7 +36,7 @@ #include "PeripheralPins.h" void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); @@ -71,6 +71,8 @@ void analogout_init(dac_t *obj, PinName pin) { __DAC_CLK_ENABLE(); obj->handle.Instance = DAC; + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32F7/can_device.h b/targets/TARGET_STM/TARGET_STM32F7/can_device.h index 7f4f6bf253f..0581da55843 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F7/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32f7xx_hal.h" +#include "stm32f7xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,26 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie (1 or 2) +#if defined(CAN3_BASE) && defined(CAN_3) + +#define CAN_NUM 3 // Number of CAN peripherals present in the STM32 serie + +#define CAN3_IRQ_RX_IRQN CAN3_RX0_IRQn +#define CAN3_IRQ_RX_VECT CAN3_RX0_IRQHandler +#define CAN3_IRQ_TX_IRQN CAN3_TX_IRQn +#define CAN3_IRQ_TX_VECT CAN3_TX_IRQHandler +#define CAN3_IRQ_ERROR_IRQN CAN3_SCE_IRQn +#define CAN3_IRQ_ERROR_VECT CAN3_SCE_IRQHandler +#define CAN3_IRQ_PASSIVE_IRQN CAN3_SCE_IRQn +#define CAN3_IRQ_PASSIVE_VECT CAN3_SCE_IRQHandler +#define CAN3_IRQ_BUS_IRQN CAN3_SCE_IRQn +#define CAN3_IRQ_BUS_VECT CAN3_SCE_IRQHandler + +#else + +#define CAN_NUM 2 // Number of CAN peripherals present in the STM32 serie + +#endif #define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn #define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h index 825d7fd0a15..fbdf3875009 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h @@ -130,9 +130,9 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask; + newValue = (uint32_t)__LDREXW(ptr) | mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } @@ -140,9 +140,9 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask; + newValue = (uint32_t)__LDREXW(ptr) &~mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } #if defined ( __GNUC__ ) && !defined ( __CC_ARM ) diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c index 323c8aae5f8..14cd418e9ff 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c @@ -1063,33 +1063,54 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Get tick */ - tickstart = HAL_GetTick(); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ + /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) { - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ __HAL_UNLOCK(hrtc); - + return HAL_TIMEOUT; } } } - + /* Disable the Wake-Up timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + + /* Clear flag Wake-Up */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } + /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; @@ -1098,15 +1119,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; - + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; - - /* Clear RTC Wake Up timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - + + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); + /* Configure the Interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c index 34f4fc7bbe1..a4bece18154 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c @@ -763,9 +763,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -838,7 +838,7 @@ void serial_rx_abort_asynch(serial_t *obj) __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); // clear flags - volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct similarity index 97% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct index c4e915ba952..384ce7e0754 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct @@ -27,7 +27,7 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000) +; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000) LR_IROM1 0x08000000 0x30000 { ; load region size_region ER_IROM1 0x08000000 0x30000 { ; load address = execution address diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct similarity index 97% rename from targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct rename to targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct index c4e915ba952..384ce7e0754 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct @@ -27,7 +27,7 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000) +; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000) LR_IROM1 0x08000000 0x30000 { ; load region size_region ER_IROM1 0x08000000 0x30000 { ; load address = execution address diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h index 966ce876ae6..80a92081d32 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c index afe7ff433a5..f8bd4e85480 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_clock.c @@ -41,6 +41,9 @@ #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) #define USE_PLL_HSI 0x2 // Use HSI internal clock +// Uncomment to output the MCO on PA8 for debugging +//#define DEBUG_MCO + #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) uint8_t SetSysClock_PLL_HSE(uint8_t bypass); #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ @@ -118,10 +121,6 @@ void SetSysClock(void) } } } - - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); } #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) @@ -130,9 +129,10 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_ClkInitTypeDef RCC_ClkInitStruct; - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; /* Used to gain time after DeepSleep in case HSI is used */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { @@ -144,11 +144,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) regarding system frequency refer to product datasheet. */ __PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + __HAL_RCC_PWR_CLK_DISABLE(); /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; if (bypass == 0) { - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 8 MHz xtal on OSC_IN/OSC_OUT */ } else { RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ } @@ -163,6 +164,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } + /* Select HSI48 as USB clock source */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz @@ -173,17 +181,30 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) return 0; // FAIL } - RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; - RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { - return 0; // FAIL - } + /* Configure the clock recovery system (CRS) ********************************/ + /* Enable CRS Clock */ + __HAL_RCC_CRS_CLK_ENABLE(); + /* Default Synchro Signal division factor (not divided) */ + RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; + /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ + RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; + /* HSI48 is synchronized with USB SOF at 1KHz rate */ + RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); + RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT; + /* Set the TRIM[5:0] to the default value */ + RCC_CRSInitStruct.HSI48CalibrationValue = 0x20; + /* Start automatic synchronization */ + HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //if (bypass == 0) - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz - //else - // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#ifdef DEBUG_MCO + // Output clock on MCO1 pin(PA8) for debugging purpose + if (bypass == 0) { // Xtal used + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_2); // 16 MHz + } + else { // External clock used + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_4); // 8 MHz + } +#endif return 1; // OK } @@ -252,8 +273,10 @@ uint8_t SetSysClock_PLL_HSI(void) /* Start automatic synchronization */ HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); - /* Output clock on MCO1 pin(PA8) for debugging purpose */ - //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#ifdef DEBUG_MCO + // Output clock on MCO1 pin(PA8) for debugging purpose + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 32 MHz (not precise due to HSI not calibrated) +#endif return 1; // OK } diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c index 47cb630d20e..18df1cdc09c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,118 +30,126 @@ #include "PeripheralPins.h" -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== //*** ADC *** const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 - {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 - {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 - {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 - {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 - {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 - {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 - {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 - {NC, NC, 0} + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC_IN1 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC_IN2 - Connected to STDIO_UART_TX + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 + {NC, NC, 0} }; const PinMap PinMap_ADC_Internal[] = { {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used - {NC, NC, 0} + {NC, NC, 0} }; //*** DAC *** const PinMap PinMap_DAC[] = { - {NC, NC, 0} + {NC, NC, 0} }; - //*** I2C *** const PinMap PinMap_I2C_SDA[] = { {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, {PA_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C1)}, {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_I2C_SCL[] = { - {PA_4, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C1)}, - {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, - {NC, NC, 0} + {PA_4, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C1)}, + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)}, + {NC, NC, 0} }; //*** PWM *** -// TIM21 cannot be used because already used by the us_ticker +// TIM21 (PWM_21) cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { - {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 - {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_2, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - used by STDIO TX -// {PA_3, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2 - {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 - {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 - {PA_8, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 -// {PA_9, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2 -// {PA_10, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - {PA_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 -// {PA_11, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2 -// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 - used by STDIO RX -// {PB_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - {PB_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 - {PB_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 4, 0)}, // TIM2_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 -// {PB_5, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 1, 0)}, // TIM21_CH1 - {PB_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 - {PB_7, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 4, 0)}, // TIM2_CH4 - {NC, NC, 0} + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_2, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - Connected to STDIO_UART_TX +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX +// {PA_3, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2 + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 + {PA_8, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_9, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2 +// {PA_10, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 + {PA_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_11, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 - Connected to STDIO_UART_RX + {PB_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 + {PB_0_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PB_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 4, 0)}, // TIM2_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - Connected to LED +// {PB_5, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 1, 0)}, // TIM21_CH1 + {PB_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 + {PB_7, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 4, 0)}, // TIM2_CH4 + {NC, NC, 0} }; //*** SERIAL *** const PinMap PinMap_UART_TX[] = { - {PA_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, -// {PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_4, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_9, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, -// {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, -// {PB_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PB_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, - {NC, NC, 0} + {PA_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX (Warning: no LPUART_1 on STDIO_UART_RX = PA_15) + {PA_4, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_9, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PB_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PB_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { -// {PA_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, -// {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_10, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, -// {PB_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PB_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, - {NC, NC, 0} + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PA_0_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_10, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX + {PB_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {NC, NC, 0} }; const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_12, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, - {PA_12, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_UART_CTS[] = { @@ -149,7 +157,7 @@ const PinMap PinMap_UART_CTS[] = { {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)}, {PA_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, {PA_11, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {NC, NC, 0} + {NC, NC, 0} }; //*** SPI *** @@ -159,7 +167,7 @@ const PinMap PinMap_SPI_MOSI[] = { {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, {PB_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_SPI1)}, {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_SPI_MISO[] = { @@ -168,18 +176,18 @@ const PinMap PinMap_SPI_MISO[] = { {PA_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_SPI1)}, {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {NC, NC, 0} + {NC, NC, 0} }; const PinMap PinMap_SPI_SCLK[] = { {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, {PA_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {NC, NC, 0} + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to LED + {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, -// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - used by STDIO RX - {NC, NC, 0} +// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX + {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h index adcd8901a8e..ca509321045 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/PinNames.h @@ -33,15 +33,25 @@ #include "cmsis.h" #include "PinNamesTypes.h" +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + #ifdef __cplusplus extern "C" { #endif typedef enum { PA_0 = 0x00, + PA_0_ALT0 = PA_0|ALT0, PA_1 = 0x01, PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, @@ -53,16 +63,20 @@ typedef enum { PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, + PA_14_ALT0 = PA_14|ALT0, PA_15 = 0x0F, PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, PB_4 = 0x14, PB_5 = 0x15, PB_6 = 0x16, + PB_6_ALT0 = PB_6|ALT0, PB_7 = 0x17, + PB_7_ALT0 = PB_7|ALT0, PC_14 = 0x2E, PC_15 = 0x2F, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h index 7724b546fb4..4f43c6e22eb 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c index d8ffa050c8d..79f19e7239a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,18 +30,27 @@ #include "PeripheralPins.h" -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== //*** ADC *** const PinMap PinMap_ADC[] = { {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - Connected to STDIO_UART_TX {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 @@ -84,8 +93,8 @@ const PinMap PinMap_I2C_SCL[] = { const PinMap PinMap_PWM[] = { {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_2, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - used by STDIO TX +// {PA_2, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1 - Connected to STDIO_UART_TX +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX // {PA_3, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2 {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 @@ -95,10 +104,10 @@ const PinMap PinMap_PWM[] = { {PA_9, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1 {PA_10, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2 // {PA_11, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM21, 2, 0)}, // TIM21_CH2 -// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 - used by STDIO RX +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)}, // TIM2_CH1 - Connected to STDIO_UART_RX {PB_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 3, 0)}, // TIM2_CH3 {PB_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 4, 0)}, // TIM2_CH4 - {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - used also to drive the LED + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - Connected to LED {PB_4, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1 {PB_5, PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2 // {PB_6, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM21, 1, 0)}, // TIM21_CH1 @@ -108,23 +117,23 @@ const PinMap PinMap_PWM[] = { //*** SERIAL *** const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_9, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK - {PB_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, -// {PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, -// {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {NC, NC, 0} + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX + {PA_9, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to SWCLK + {PA_14_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to SWCLK + {PB_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_10, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, - {PB_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, -// {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, -// {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {NC, NC, 0} + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_10, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Connected to STDIO_UART_RX + {PB_7, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART2)}, + {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to SWDIO + {NC, NC, 0} }; const PinMap PinMap_UART_RTS[] = { @@ -163,12 +172,12 @@ const PinMap PinMap_SPI_MISO[] = { const PinMap PinMap_SPI_SCLK[] = { {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, - {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // used also to drive the LED + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to LED {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, -// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // used by STDIO RX +// {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_RX {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h index adcd8901a8e..8302724210b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/PinNames.h @@ -37,11 +37,20 @@ extern "C" { #endif +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, PA_4 = 0x04, PA_5 = 0x05, PA_6 = 0x06, @@ -53,6 +62,7 @@ typedef enum { PA_12 = 0x0C, PA_13 = 0x0D, PA_14 = 0x0E, + PA_14_ALT0 = PA_14|ALT0, PA_15 = 0x0F, PB_0 = 0x10, diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h index 7724b546fb4..4f43c6e22eb 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h index 7724b546fb4..4f43c6e22eb 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h index 7724b546fb4..4f43c6e22eb 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM21 #define TIM_MST_IRQ TIM21_IRQn #define TIM_MST_RCC __TIM21_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM21() #define TIM_MST_RESET_ON __TIM21_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM21_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c b/targets/TARGET_STM/TARGET_STM32L0/analogin_device.c similarity index 71% rename from targets/TARGET_STM/TARGET_STM32L0/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32L0/analogin_device.c index e6d68e29cf7..f1ac6a8764d 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/analogin_device.c @@ -35,13 +35,12 @@ #include "pinmap.h" #include "mbed_error.h" #include "PeripheralPins.h" - -int adc_inited = 0; +#include void analogin_init(analogin_t *obj, PinName pin) { + static bool adc_calibrated = false; uint32_t function = (uint32_t)NC; - obj->handle.Instance = (ADC_TypeDef *)NC; // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) // are described in PinNames.h and PeripheralPins.c @@ -68,44 +67,41 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - obj->handle.State = HAL_ADC_STATE_RESET; - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - obj->handle.Init.OversamplingMode = DISABLE; - obj->handle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV1; - obj->handle.Init.Resolution = ADC_RESOLUTION12b; - obj->handle.Init.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; - obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.ContinuousConvMode = DISABLE; - obj->handle.Init.DiscontinuousConvMode = DISABLE; - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIG_EDGE_NONE; - obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; - obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; - obj->handle.Init.LowPowerAutoWait = ENABLE; - obj->handle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz - obj->handle.Init.LowPowerAutoPowerOff = DISABLE; - - if (HAL_ADC_Init(&obj->handle) != HAL_OK) { - error("Cannot initialize ADC"); - } - - // Calibration - HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED); + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.OversamplingMode = DISABLE; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.SamplingTime = ADC_SAMPLETIME_239CYCLES_5; + obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.ContinuousConvMode = DISABLE; + obj->handle.Init.DiscontinuousConvMode = DISABLE; + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIG_EDGE_NONE; + obj->handle.Init.ExternalTrigConv = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; + obj->handle.Init.Overrun = OVR_DATA_OVERWRITTEN; + obj->handle.Init.LowPowerAutoWait = ENABLE; + obj->handle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz + obj->handle.Init.LowPowerAutoPowerOff = DISABLE; + + __HAL_RCC_ADC1_CLK_ENABLE(); + + if (HAL_ADC_Init(&obj->handle) != HAL_OK) { + error("Cannot initialize ADC"); + } - __HAL_ADC_ENABLE(&obj->handle); + // ADC calibration is done only once + if (!adc_calibrated) { + adc_calibrated = true; + HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED); } + + __HAL_ADC_ENABLE(&obj->handle); } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig = {0}; @@ -182,24 +178,10 @@ static inline uint16_t adc_read(analogin_t *obj) // Wait end of conversion and get value if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c index dbf8f9cab12..499008b73a8 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/analogout_device.c @@ -40,7 +40,7 @@ static int channel1_used = 0; static int channel2_used = 0; void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); @@ -74,6 +74,8 @@ void analogout_init(dac_t *obj, PinName pin) { // Configure DAC obj->handle.Instance = DAC; + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c index d7dc35fc52e..bd4a411cb02 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c @@ -57,7 +57,6 @@ static int32_t flash_lock(void) int32_t flash_erase_sector(flash_t *obj, uint32_t address) { - uint32_t FirstPage = 0; uint32_t PAGEError = 0; FLASH_EraseInitTypeDef EraseInitStruct; int32_t status = 0; diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c index cef163dd9c6..74107fd42fb 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c @@ -673,9 +673,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -749,7 +749,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF | UART_CLEAR_FEF | UART_CLEAR_OREF); - volatile uint32_t tmpval = huart->Instance->RDR; // Clear RXNE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear RXNE flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h index 408bc75d4fe..f38bbe0fca0 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h index 408bc75d4fe..f38bbe0fca0 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h index dc2245e8f8a..15cb9f2c4e8 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h index dc2245e8f8a..15cb9f2c4e8 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c b/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c similarity index 68% rename from targets/TARGET_STM/TARGET_STM32L1/analogin_api.c rename to targets/TARGET_STM/TARGET_STM32L1/analogin_device.c index d4eead2bbbf..dfef3a3eb0f 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/analogin_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c @@ -35,11 +35,11 @@ #include "pinmap.h" #include "mbed_error.h" #include "PeripheralPins.h" - -int adc_inited = 0; +#include void analogin_init(analogin_t *obj, PinName pin) { + static bool adc_hsi_inited = false; RCC_OscInitTypeDef RCC_OscInitStruct; uint32_t function = (uint32_t)NC; @@ -49,14 +49,14 @@ void analogin_init(analogin_t *obj, PinName pin) if ((pin < 0xF0) || (pin >= 0x100)) { // Normal channels // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); // Get the functions (adc channel) from the pin and assign it to the object function = pinmap_function(pin, PinMap_ADC); // Configure GPIO pinmap_pinout(pin, PinMap_ADC); } else { // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); function = pinmap_function(pin, PinMap_ADC_Internal); // No GPIO configuration for internal channels } @@ -68,45 +68,43 @@ void analogin_init(analogin_t *obj, PinName pin) // Save pin number for the read function obj->pin = pin; - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4; + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1) + obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example). + obj->handle.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software. + obj->handle.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_IDLE_PHASE; // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). + obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_A; + obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig + obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled + obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled + obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled + obj->handle.Init.ExternalTrigConv = 0; // Not used + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.DMAContinuousRequests = DISABLE; + + __HAL_RCC_ADC1_CLK_ENABLE(); + + if (HAL_ADC_Init(&obj->handle) != HAL_OK) { + error("Cannot initialize ADC"); + } + // This section is done only once + if (!adc_hsi_inited) { + adc_hsi_inited = true; // Enable the HSI (to clock the ADC) RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; HAL_RCC_OscConfig(&RCC_OscInitStruct); - - obj->handle.State = HAL_ADC_STATE_RESET; - // Enable ADC clock - __ADC1_CLK_ENABLE(); - - // Configure ADC - obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV4; - obj->handle.Init.Resolution = ADC_RESOLUTION12b; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1) - obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example). - obj->handle.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software. - obj->handle.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_IDLE_PHASE; // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). - obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_A; - obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig - obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled - obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled - obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled - obj->handle.Init.ExternalTrigConv = 0; // Not used - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.DMAContinuousRequests = DISABLE; - - if (HAL_ADC_Init(&obj->handle) != HAL_OK) { - error("Cannot initialize ADC"); - } } } -static inline uint16_t adc_read(analogin_t *obj) +uint16_t adc_read(analogin_t *obj) { ADC_ChannelConfTypeDef sConfig = {0}; @@ -231,24 +229,10 @@ static inline uint16_t adc_read(analogin_t *obj) // Wait end of conversion and get value if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); + return (uint16_t)HAL_ADC_GetValue(&obj->handle); } else { return 0; } } -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c index 7dd2cb7eac5..2220b7d592e 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/analogout_device.c @@ -40,7 +40,7 @@ static int pa4_used = 0; static int pa5_used = 0; void analogout_init(dac_t *obj, PinName pin) { - DAC_ChannelConfTypeDef sConfig; + DAC_ChannelConfTypeDef sConfig = {0}; // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); @@ -68,6 +68,8 @@ void analogout_init(dac_t *obj, PinName pin) { obj->pin = pin; obj->handle.Instance = DAC; + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c index a5b0796cbeb..5e6932071f0 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c @@ -57,7 +57,6 @@ static int32_t flash_lock(void) int32_t flash_erase_sector(flash_t *obj, uint32_t address) { - uint32_t FirstPage = 0; uint32_t PAGEError = 0; FLASH_EraseInitTypeDef EraseInitStruct; int32_t status = 0; diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c index 3859270e225..bcf53156b05 100755 --- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c @@ -203,7 +203,7 @@ static void uart_irq(int id) } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } } @@ -607,13 +607,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear PE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear FE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear FE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear NE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear NE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { - volatile uint32_t tmpval = huart->Instance->DR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear ORE flag } } @@ -664,9 +664,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -740,7 +740,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); - volatile uint32_t tmpval = huart->Instance->DR; // Clear errors flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->DR; // Clear errors flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c index 279491f6acc..4713a839d7e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PeripheralPins.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics + * Copyright (c) 2017, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,18 +30,27 @@ #include "PeripheralPins.h" -// ===== -// Note: Commented lines are alternative possibilities which are not used per default. -// If you change them, you will have also to modify the corresponding xxx_api.c file -// for pwmout, analogin, analogout, ... -// ===== +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== //*** ADC *** const PinMap PinMap_ADC[] = { {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 -// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - used by STDIO_UART_TX +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - Connected to STDIO_UART_TX {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 @@ -85,13 +94,13 @@ const PinMap PinMap_I2C_SCL[] = { //*** PWM *** -// TIM2 cannot be used because already used by the us_ticker +// TIM2 (PWM_2) cannot be used because already used by the us_ticker const PinMap PinMap_PWM[] = { // {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N // {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 -// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - used by STDIO_UART_TX -// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 // {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 @@ -103,7 +112,7 @@ const PinMap PinMap_PWM[] = { {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - Connected to LED {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N {NC, NC, 0} }; @@ -111,27 +120,27 @@ const PinMap PinMap_PWM[] = { //*** SERIAL *** const PinMap PinMap_UART_TX[] = { -// {PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} }; const PinMap PinMap_UART_RX[] = { -// {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {NC, NC, 0} + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, // Connected to STDIO_UART_RX + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} }; const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED {NC, NC, 0} }; @@ -146,34 +155,34 @@ const PinMap PinMap_UART_CTS[] = { //*** SPI *** const PinMap PinMap_SPI_MOSI[] = { - {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} }; const PinMap PinMap_SPI_MISO[] = { - {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} }; const PinMap PinMap_SPI_SCLK[] = { - {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, -// {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {NC, NC, 0} + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // Connected to LED + {PB_3_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // Connected to LED + {NC, NC, 0} }; const PinMap PinMap_SPI_SSEL[] = { -// {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, - {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, - {NC, NC, 0} + {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {NC, NC, 0} }; //*** CAN *** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h index 8f7e2673cad..f0f0f79cac6 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/PinNames.h @@ -33,6 +33,13 @@ #include "cmsis.h" #include "PinNamesTypes.h" +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + #ifdef __cplusplus extern "C" { #endif @@ -41,8 +48,11 @@ typedef enum { PA_0 = 0x00, PA_1 = 0x01, PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, PA_5 = 0x05, PA_6 = 0x06, PA_7 = 0x07, @@ -59,8 +69,11 @@ typedef enum { PB_1 = 0x11, PB_2 = 0x12, PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, PB_6 = 0x16, PB_7 = 0x17, diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c index a1ca68c41cc..59bc3ee8e4f 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/TARGET_NUCLEO_L432KC/system_clock.c @@ -110,7 +110,7 @@ void SystemInit(void) #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ #endif } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct index 9da54cc7c7e..53e420abbe4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_MICRO/stm32l432xx.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2015, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + ; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) -LR_IROM1 0x08000000 0x40000 { ; load region size_region +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - ER_IROM1 0x08000000 0x40000 { ; load address = execution address + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct index 9da54cc7c7e..53e420abbe4 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_ARM_STD/stm32l432xx.sct @@ -1,3 +1,4 @@ +#! armcc -E ; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Copyright (c) 2015, STMicroelectronics @@ -27,10 +28,18 @@ ; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + ; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) -LR_IROM1 0x08000000 0x40000 { ; load region size_region +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - ER_IROM1 0x08000000 0x40000 { ; load address = execution address + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address *.o (RESET, +First) *(InRoot$$Sections) .ANY (+RO) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld index 04dcddcecea..6bdf1dfc43c 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_GCC_ARM/STM32L432XX.ld @@ -1,7 +1,15 @@ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 256k +#endif + /* Linker script to configure memory regions. */ MEMORY { - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE SRAM1 (rwx) : ORIGIN = 0x20000188, LENGTH = 64k - 0x188 } diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf index 9c478c51e2e..061e6768451 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/TOOLCHAIN_IAR/stm32l432xx.icf @@ -1,9 +1,12 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; } + /* [ROM = 256kb = 0x40000] */ -define symbol __intvec_start__ = 0x08000000; -define symbol __region_ROM_start__ = 0x08000000; -define symbol __region_ROM_end__ = 0x0803FFFF; +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; -/* [RAM = 48kb + 16kb = 0xC000] */ +/* [RAM = 48kb + 16kb = 0x10000] */ /* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ define symbol __NVIC_start__ = 0x20000000; define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h index bdcb1570c38..934e8ed9d23 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() #define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralNames.h new file mode 100644 index 00000000000..84ee47f42dc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralNames.h @@ -0,0 +1,87 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +#define STDIO_UART_TX PA_2 +#define STDIO_UART_RX PA_3 +#define STDIO_UART UART_2 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_6 = (int)TIM6_BASE, + PWM_7 = (int)TIM7_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c new file mode 100644 index 00000000000..7b0edbc79c5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PeripheralPins.c @@ -0,0 +1,264 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - All mapping tables are declared as weak to allow custom overwrites for similar MCU models. +// +//============================================================================== + +//*** ADC *** + +__weak const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {NC, NC, 0} +}; + +__weak const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +__weak const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +__weak const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + + +//*** PWM *** + +__weak const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_13_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_14_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PB_15_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NC, 0} +}; + +//*** SERIAL *** + +__weak const PinMap PinMap_UART_TX[] = { + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},// connected to STDIO_UART_TX + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // connected to STDIO_UART_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_UART_RX[] = { + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},// connected to STDIO_UART_RX + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // connected to STDIO_UART_RX + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {NC, NC, 0} +}; + +//*** SPI *** + +__weak const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +//*** CAN *** + +__weak const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; + +__weak const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h new file mode 100644 index 00000000000..72ac0c6a0a1 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h @@ -0,0 +1,219 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_1_ALT0 = PA_1|ALT0, + PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13|ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14|ALT0, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15|ALT0, + +#ifndef STM32L433_48PINS // 48 pin versions don't have PC0-PC15 pins + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, +#endif + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + + PD_2 = 0x32, +#ifdef STM32L433_100PINS // LQFP100 or UFBGA100 versions + PD_0 = 0x30, + PD_1 = 0x31, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, +#endif + + PH_0 = 0x70, + PH_1 = 0x71, + + PH_3 = 0x73, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PC_3, + A3 = PC_2, + A4 = PC_1, + A5 = PC_0, + + A6 = PA_7, + A7 = PA_2, + + D0 = PA_2, + D1 = PA_3, + D2 = PA_12, + D3 = PB_3, + D4 = PB_5, + D5 = PA_15, + D6 = PB_10, + D7 = PC_7, + D8 = PB_6, + D9 = PA_8, + D10 = PA_11, + D11 = PB_15, + D12 = PB_14, + D13 = PB_13, + + // Generic signals namings + LED1 = PA_5, + LED2 = PA_5, + LED3 = PA_5, + LED4 = PA_5, + USER_BUTTON = PC_13, + BUTTON1 = USER_BUTTON, + SERIAL_TX = PA_2, + SERIAL_RX = PA_3, + USBTX = SERIAL_TX, + USBRX = SERIAL_RX, + I2C_SCL = PB_8, + I2C_SDA = PB_7, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + //USB pins + USB_DM = PA_11, + USB_DP = PA_12, + USB_NOE = PA_13, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c new file mode 100644 index 00000000000..59bc3ee8e4f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/system_clock.c @@ -0,0 +1,374 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @version V1.3.1 + * @date 21-April-2017 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI + * | (external 8 MHz clock) | (internal 16 MHz) + * | 2- PLL_HSE_XTAL | or PLL_MSI + * | (external 8 MHz xtal) | (internal 4 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * AHBCLK (MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * APB1CLK (MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * APB2CLK (MHz) | 48 | 80 + *----------------------------------------------------------------------------- + * USB capable (48 MHz precise clock) | YES | NO + *----------------------------------------------------------------------------- +**/ + +#include "stm32l4xx.h" +#include "nvic_addr.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock +#define USE_PLL_MSI 0x1 // Use MSI internal clock + +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +uint8_t SetSysClock_PLL_MSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI()==0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + } + + HAL_RCCEx_DisableLSECSS(); + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S new file mode 100644 index 00000000000..895d8e662b9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l433xx.S @@ -0,0 +1,378 @@ +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l432xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x20010000 ; Top of RAM + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x0F800 ; 62KB (64KB, -2*1KB for main thread and scheduler) + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +SDMMC1_IRQHandler +SPI3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +USB_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct new file mode 100644 index 00000000000..53e420abbe4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_MICRO/stm32l433xx.sct @@ -0,0 +1,53 @@ +#! armcc -E +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + +; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188) { + .ANY (+RW +ZI) + } + +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S new file mode 100644 index 00000000000..e8397decd92 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/startup_stm32l433xx.S @@ -0,0 +1,361 @@ +;********************** COPYRIGHT(c) 2016 STMicroelectronics ****************** +;* File Name : startup_stm32l432xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L432xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + +__initial_sp EQU 0x20010000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +SDMMC1_IRQHandler +SPI3_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +USB_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct new file mode 100644 index 00000000000..53e420abbe4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_ARM_STD/stm32l433xx.sct @@ -0,0 +1,53 @@ +#! armcc -E +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x40000 +#endif + +; 256KB FLASH (0x40000) + 64KB SRAM (0x10000) +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM + RW_IRAM1 (0x20000000+0x188) (0x00010000-0x188) { + .ANY (+RW +ZI) + } + +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld new file mode 100644 index 00000000000..6bdf1dfc43c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/STM32L433XX.ld @@ -0,0 +1,161 @@ +#if !defined(MBED_APP_START) + #define MBED_APP_START 0x08000000 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 256k +#endif + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + SRAM1 (rwx) : ORIGIN = 0x20000188, LENGTH = 64k - 0x188 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > SRAM1 + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > SRAM1 + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > SRAM1 + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM1 + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S new file mode 100644 index 00000000000..df1beb6f779 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_GCC_ARM/startup_stm32l433xx.S @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file startup_stm32l432xx.s + * @author MCD Application Team + * @version V1.1.1 + * @date 29-April-2016 + * @brief STM32L432xx devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word 0 + .word 0 + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SDMMC1_IRQHandler + .word 0 + .word SPI3_IRQHandler + .word 0 + .word 0 + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word 0 + .word 0 + .word 0 + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word USB_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word 0 + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word LCD_IRQHandler + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S new file mode 100644 index 00000000000..8688b7e8a7f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/startup_stm32l433xx.S @@ -0,0 +1,563 @@ +;/********************* COPYRIGHT(c) 2016 STMicroelectronics ******************** +;* File Name : startup_stm32l432xx.s +;* Author : MCD Application Team +;* Version : V1.1.1 +;* Date : 29-April-2016 +;* Description : STM32L432xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD USB_IRQHandler ; USB FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD 0 ; Reserved + DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU interrupt + DCD CRS_IRQHandler ; CRS interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_IRQHandler + B TIM1_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf new file mode 100644 index 00000000000..061e6768451 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/TOOLCHAIN_IAR/stm32l433xx.icf @@ -0,0 +1,33 @@ +if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x40000; } + +/* [ROM = 256kb = 0x40000] */ +define symbol __intvec_start__ = MBED_APP_START; +define symbol __region_ROM_start__ = MBED_APP_START; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; + +/* [RAM = 48kb + 16kb = 0x10000] */ +/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x20000187; /* Aligned on 8 bytes (392 = 49 x 8) */ +define symbol __region_SRAM1_start__ = 0x20000188; +define symbol __region_SRAM1_end__ = 0x2000FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; + +define symbol __size_cstack__ = 0x2000; +define symbol __size_heap__ = 0x4000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in SRAM1_region { readwrite, block STACKHEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h new file mode 100644 index 00000000000..41a1233f3b7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h new file mode 100644 index 00000000000..49f64adf45c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/cmsis_nvic.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 82 vectors = 328 bytes from 0x40 to 0x187 +// Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM +#define NVIC_NUM_VECTORS 98 +#define NVIC_RAM_VECTOR_ADDRESS SRAM1_BASE // Vectors positioned at start of SRAM1 + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h new file mode 100644 index 00000000000..bdcb1570c38 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/hal_tick.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l4xx.h" +#include "stm32l4xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() + +#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h new file mode 100644 index 00000000000..6bc15d0a904 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h @@ -0,0 +1,15973 @@ +/** + ****************************************************************************** + * @file stm32l433xx.h + * @author MCD Application Team + * @version V1.3.2 + * @date 16-June-2017 + * @brief CMSIS STM32L433xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral’s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l433xx + * @{ + */ + +#ifndef __STM32L433xx_H +#define __STM32L433xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + USB_IRQn = 67, /*!< USB event Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ + SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + LCD_IRQn = 78, /*!< LCD global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + CRS_IRQn = 82 /*!< CRS global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ +} FLASH_TypeDef; + + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 48 KB) base address */ +#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(16 KB) base address */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ +#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ + +#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX ((uint32_t)0x0000C000U) /*!< maximum SRAM1 size (up to 48 KBytes) */ +#define SRAM2_SIZE ((uint32_t)0x00004000U) /*!< SRAM2 size (16 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) + + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define USB_BASE (APB1PERIPH_BASE + 0x6800U) /*!< USB_IP Peripheral Registers base address */ +#define USB_PMAADDR (APB1PERIPH_BASE + 0x6C00U) /*!< USB_IP Packet Memory Area base address */ +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) + + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) +#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) + + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) + + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t)0xE0042000U) + + +#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ +#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +// #define CAN ((CAN_TypeDef *) CAN1_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC1_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) + + + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) + */ +/* Note: No specific macro feature on this device */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx + * @{ + */ + +#ifndef __STM32L4xx_H +#define __STM32L4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L4) +#define STM32L4 +#endif /* STM32L4 */ + +/* Uncomment the line below according to the target STM32L4 device used in your + application + */ + +#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ + !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ + !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ + !defined (STM32L496xx) && !defined (STM32L4A6xx) + /* #define STM32L431xx */ /*!< STM32L431xx Devices */ + /* #define STM32L432xx */ /*!< STM32L432xx Devices */ +#define STM32L433xx /*!< STM32L433xx Devices */ + /* #define STM32L442xx */ /*!< STM32L442xx Devices */ + /* #define STM32L443xx */ /*!< STM32L443xx Devices */ + /* #define STM32L451xx */ /*!< STM32L451xx Devices */ + /* #define STM32L452xx */ /*!< STM32L452xx Devices */ + /* #define STM32L462xx */ /*!< STM32L462xx Devices */ + /* #define STM32L471xx */ /*!< STM32L471xx Devices */ + /* #define STM32L475xx */ /*!< STM32L475xx Devices */ + /* #define STM32L476xx */ /*!< STM32L476xx Devices */ + /* #define STM32L485xx */ /*!< STM32L485xx Devices */ + /* #define STM32L486xx */ /*!< STM32L486xx Devices */ + /* #define STM32L496xx */ /*!< STM32L496xx Devices */ + /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.3.1 + */ +#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L4_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L431xx) + #include "stm32l431xx.h" +#elif defined(STM32L432xx) + #include "stm32l432xx.h" +#elif defined(STM32L433xx) + #include "stm32l433xx.h" +#elif defined(STM32L442xx) + #include "stm32l442xx.h" +#elif defined(STM32L443xx) + #include "stm32l443xx.h" +#elif defined(STM32L451xx) + #include "stm32l451xx.h" +#elif defined(STM32L452xx) + #include "stm32l452xx.h" +#elif defined(STM32L462xx) + #include "stm32l462xx.h" +#elif defined(STM32L471xx) + #include "stm32l471xx.h" +#elif defined(STM32L475xx) + #include "stm32l475xx.h" +#elif defined(STM32L476xx) + #include "stm32l476xx.h" +#elif defined(STM32L485xx) + #include "stm32l485xx.h" +#elif defined(STM32L486xx) + #include "stm32l486xx.h" +#elif defined(STM32L496xx) + #include "stm32l496xx.h" +#elif defined(STM32L4A6xx) + #include "stm32l4a6xx.h" +#else + #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h similarity index 51% rename from targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c rename to targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h index 833c42059ca..3f229fa3d0e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_msp_template.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/system_stm32l4xx.h @@ -1,16 +1,14 @@ /** ****************************************************************************** - * @file stm32l4xx_hal_msp_template.c + * @file system_stm32l4xx.h * @author MCD Application Team - * @version V1.5.1 - * @date 31-May-2016 - * @brief HAL MSP module. - * This file template is located in the HAL folder and should be copied - * to the user folder. + * @version V1.3.1 + * @date 21-April-2017 + * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2016 STMicroelectronics

+ *

© COPYRIGHT(c) 2017 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -34,90 +32,96 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l4xx_hal.h" + ****************************************************************************** + */ -/** @addtogroup STM32L4xx_HAL_Driver +/** @addtogroup CMSIS * @{ */ -/** @defgroup HAL_MSP HAL MSP module driver - * @brief HAL MSP module. +/** @addtogroup stm32l4xx_system * @{ */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L4XX_H +#define __SYSTEM_STM32L4XX_H + +#ifdef __cplusplus + extern "C" { +#endif -/** @defgroup HAL_MSP_Private_Functions +/** @addtogroup STM32L4xx_System_Includes * @{ */ /** - * @brief Initialize the Global MSP. - * @param None - * @retval None - */ -void HAL_MspInit(void) -{ - /* NOTE : This function is generated automatically by STM32CubeMX and eventually - modified by the user - */ -} + * @} + */ -/** - * @brief DeInitialize the Global MSP. - * @param None - * @retval None - */ -void HAL_MspDeInit(void) -{ - /* NOTE : This function is generated automatically by STM32CubeMX and eventually - modified by the user - */ -} + +/** @addtogroup STM32L4xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ /** - * @brief Initialize the PPP MSP. - * @param None - * @retval None - */ -void HAL_PPP_MspInit(void) -{ - /* NOTE : This function is generated automatically by STM32CubeMX and eventually - modified by the user - */ -} + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Constants + * @{ + */ /** - * @brief DeInitialize the PPP MSP. - * @param None - * @retval None - */ -void HAL_PPP_MspDeInit(void) -{ - /* NOTE : This function is generated automatically by STM32CubeMX and eventually - modified by the user - */ -} + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Macros + * @{ + */ /** * @} */ +/** @addtogroup STM32L4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + /** * @} */ +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L4XX_H */ + /** * @} */ +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h new file mode 100644 index 00000000000..ece5f1679fa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/objects.h @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct trng_s { + RNG_HandleTypeDef handle; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h index 315a9bf43fc..11cd6c10df8 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h new file mode 100644 index 00000000000..d260c726cb9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralNames.h @@ -0,0 +1,94 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +#define STDIO_UART_TX PC_12 +#define STDIO_UART_RX PD_2 +#define STDIO_UART UART_5 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c new file mode 100644 index 00000000000..b2cf6b0af1f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PeripheralPins.c @@ -0,0 +1,269 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +// ===== +// Note: Commented lines are alternative possibilities which are not used per default. +// If you change them, you will have also to modify the corresponding xxx_api.c file +// for pwmout, analogin, analogout, ... +// ===== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 5, 0)}, // IN5 - ARDUINO A0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 6, 0)}, // IN6 - ARDUINO A1 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 7, 0)}, // IN7 // PA_2 is used as SERIAL_TX +// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 8, 0)}, // IN8 // PA_3 is used as SERIAL_RX + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 9, 0)}, // IN9 - ARDUINO A2 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 10, 0)}, // IN10 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 11, 0)}, // IN11 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 12, 0)}, // IN12 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 15, 0)}, // IN15 - ARDUINO A3 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 16, 0)}, // IN16 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 1, 0)}, // IN1 - ARDUINO A5 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 2, 0)}, // IN2 - ARDUINO A4 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 3, 0)}, // IN3 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 4, 0)}, // IN4 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 13, 0)}, // IN13 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CONTROL, GPIO_NOPULL, 0, 14, 0)}, // IN14 + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // OUT2 (Warning: LED1 is also on this pin) + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// Warning: TIM5 cannot be used because already used by the us_ticker. +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 (used by us_ticker) + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 (used by us_ticker) +// {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // PA_2 is used as SERIAL_TX +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 (used by us_ticker) +// {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // PA_3 is used as SERIAL_RX +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 (used by us_ticker) +// {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 +// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1 + {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO D11 +// {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PA_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N +// {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 +// {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 +// {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO D3 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO D5 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 - ARDUINO D10 +// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)},// TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 +// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)},// TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 +// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)},// TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 +// {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)},// TIM17_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - ARDUINO D6 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N +// {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)},// TIM15_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N +// {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)},// TIM15_CH1 +// {PB_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N +// {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)},// TIM15_CH2 +// {PB_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PC_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 +// {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO D9 +// {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 +// {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 +// {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // SERIAL_RX + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, +// {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // MEMs +// {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, +// {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, +// {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, +// {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, +// {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)}, +// {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, +// {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART3)}, // LED D4 + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12 + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13 + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PG_9, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, +// {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_RD[] = { + {PB_8 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PB_9 , CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h new file mode 100644 index 00000000000..7a919852018 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/PinNames.h @@ -0,0 +1,168 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_2 = 0x32, + + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_4, + A3 = PB_0, + A4 = PC_1, + A5 = PC_0, + D0 = PA_3, + D1 = PA_2, + D2 = PA_10, + D3 = PB_3, + D4 = PB_5, + D5 = PB_4, + D6 = PB_10, + D7 = PA_8, + D8 = PA_9, + D9 = PC_7, + D10 = PB_6, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PG_12, + LED2 = PG_12, + LED3 = PG_12, + LED4 = PG_12, + USER_BUTTON = PC_13, + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = PC_12, + SERIAL_RX = PD_2, + USBTX = PC_12, + USBRX = PD_2, + I2C_SCL = PC_0, + I2C_SDA = PC_1, + SPI_MOSI = PG_11, + SPI_MISO = PG_10, + SPI_SCK = PG_9, + SPI_CS = PG_12, + PWM_OUT = PB_3, + + //USB pins + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_NOE_ALT = PA_13, + USB_OTG_FS_NOE = PC_9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c new file mode 100644 index 00000000000..ee5ac4b40cb --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/TARGET_SILICA_SENSOR_NODE/system_clock.c @@ -0,0 +1,361 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32l4xx.h" +#include "nvic_addr.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock +#define USE_PLL_MSI 0x1 // Use MSI internal clock + +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +uint8_t SetSysClock_PLL_MSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI()==0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + } + + HAL_RCCEx_DisableLSECSS(); + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h index 173f8e7cb9b..6c533d19975 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h index 173f8e7cb9b..6c533d19975 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h @@ -46,6 +46,7 @@ #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM5() #define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h new file mode 100644 index 00000000000..c87dfc103ee --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralNames.h @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +#define STDIO_UART_TX SERIAL_TX +#define STDIO_UART_RX SERIAL_RX +#define STDIO_UART LPUART_1 + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + I2C_4 = (int)I2C4_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c new file mode 100644 index 00000000000..890c0e7842d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PeripheralPins.c @@ -0,0 +1,406 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" + +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +//============================================================================== + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 + {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 + {NC, NC, 0} +}; + +const PinMap PinMap_ADC_Internal[] = { + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LED2 + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, // Connected to LED2 + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED3 + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PC_1_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to STDIO_UART_RX + {PG_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PC_0_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to STDIO_UART_TX + {PG_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** +// Warning: Pins using PWM_5 cannot be used as TIMER5 is already used by the us_ticker. + +const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PA_1_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1_ALT1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2_ALT1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3_ALT1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_7_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_6_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N Connected to LED2 + {PB_7_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 Connected to LED2 + {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 - ARDUINO D15 + {PB_8_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 - ARDUINO D14 + {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PB_13_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 Connected to LED3 + {PB_14_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N Connected to LED3 + {PB_14_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N Connected to LED3 + {PB_15, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PB_15_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 Connected to LED1 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 Connected to LED1 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO D10 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 - ARDUINO D14 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 - ARDUINO D3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PF_6, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PF_7, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PF_8, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PF_9, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 +// {PF_9_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PF_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PG_9, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PG_11, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_2_ALT0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A3 + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO A4 + {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_10_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D1 + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A0 + {PA_3_ALT0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO A0 + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LED2 + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO A1 + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO A5 + {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_11_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX + {PG_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_15_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED3 + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO D12 + {PA_6_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D12 + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LED2 + {PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT0, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D11 + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, // ARDUINO A3 + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO A2 + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D12 + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED3 + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO D13 + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO D14 + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {NC, NC, 0} +}; + +//*** CAN *** + +const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_CAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D15 + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO D14 + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h new file mode 100644 index 00000000000..e51ea37f501 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/PinNames.h @@ -0,0 +1,286 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0|ALT0, + PA_1 = 0x01, + PA_1_ALT0 = PA_1|ALT0, + PA_1_ALT1 = PA_1|ALT1, + PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT1 = PA_2|ALT1, + PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT1 = PA_3|ALT1, + PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, + PA_5 = 0x05, + PA_5_ALT0 = PA_5|ALT0, + PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT1 = PA_7|ALT1, + PA_7_ALT2 = PA_7|ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT1 = PB_0|ALT1, + PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT1 = PB_1|ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_6_ALT0 = PB_6|ALT0, + PB_7 = 0x17, + PB_7_ALT0 = PB_7|ALT0, + PB_8 = 0x18, + PB_8_ALT0 = PB_8|ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9|ALT0, + PB_10 = 0x1A, + PB_10_ALT0 = PB_10|ALT0, + PB_11 = 0x1B, + PB_11_ALT0 = PB_11|ALT0, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13|ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT1 = PB_14|ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15|ALT0, + PB_15_ALT1 = PB_15|ALT1, + + PC_0 = 0x20, + PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT1 = PC_0|ALT1, + PC_1 = 0x21, + PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT1 = PC_1|ALT1, + PC_2 = 0x22, + PC_2_ALT0 = PC_2|ALT0, + PC_2_ALT1 = PC_2|ALT1, + PC_3 = 0x23, + PC_3_ALT0 = PC_3|ALT0, + PC_3_ALT1 = PC_3|ALT1, + PC_4 = 0x24, + PC_4_ALT0 = PC_4|ALT0, + PC_5 = 0x25, + PC_5_ALT0 = PC_5|ALT0, + PC_6 = 0x26, + PC_6_ALT0 = PC_6|ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7|ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8|ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9|ALT0, + PC_10 = 0x2A, + PC_10_ALT0 = PC_10|ALT0, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11|ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_6 = 0x56, + PF_7 = 0x57, + PF_8 = 0x58, + PF_9 = 0x59, + PF_9_ALT0 = PF_9|ALT0, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino J3 connector namings + A0 = PA_3, + A1 = PC_0, + A2 = PC_3, + A3 = PC_1, + A4 = PC_4, + A5 = PC_5, + D0 = PD_9, + D1 = PD_8, + D2 = PF_15, + D3 = PE_13, + D4 = PF_14, + D5 = PE_11, + D6 = PE_9, + D7 = PF_13, + D8 = PF_12, + D9 = PD_15, + D10 = PD_14, + D11 = PA_7, + D12 = PA_6, + D13 = PA_5, + D14 = PB_9, + D15 = PB_8, + + // Generic signals namings + LED1 = PC_7, + LED2 = PB_7, + LED3 = PB_14, + LED4 = LED1, + USER_BUTTON = PC_13, + + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = PG_7, // Virtual Com Port + SERIAL_RX = PG_8, // Virtual Com Port + USBTX = PG_7, // Virtual Com Port + USBRX = PG_8, // Virtual Com Port + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_NOE_ALT = PA_13, + USB_OTG_FS_SOF_ALT = PA_14, + USB_OTG_FS_NOE = PC_9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c new file mode 100644 index 00000000000..e8d5be0049b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c @@ -0,0 +1,382 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32l4xx.h" +#include "nvic_addr.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock +#define USE_PLL_MSI 0x1 // Use MSI internal clock + +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +uint8_t SetSysClock_PLL_MSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI()==0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + } + + HAL_RCCEx_DisableLSECSS(); + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + /* Select LSE as clock source for LPUART1 */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S new file mode 100644 index 00000000000..ec2258b0d9b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32l496xx.S @@ -0,0 +1,434 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l496xx.s +;* Author : MCD Application Team +;* Version : V1.7.0 +;* Date : 17-February-2017 +;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x20050000 ; Top of RAM + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x17800 ; 94KB (96KB, -2*1KB for main thread and scheduler) + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD DMA2D_IRQHandler ; DMA2D global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +DCMI_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +DMA2D_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct new file mode 100644 index 00000000000..b7d0a9fccdc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_MICRO/stm32l496xx.sct @@ -0,0 +1,44 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 1MB FLASH (0x100000) + 320KB SRAM (0xxxxx) +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1AC) (0x00500000-0x1AC) { ; RW data 320k L4-SRAM1 + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S new file mode 100644 index 00000000000..b233de792f3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/startup_stm32l496xx.S @@ -0,0 +1,417 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l496xx.s +;* Author : MCD Application Team +;* Version : V1.7.0 +;* Date : 17-February-2017 +;* Description : STM32L496xx Ultra Low Power devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* + +__initial_sp EQU 0x20050000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD DMA2D_IRQHandler ; DMA2D global interrupt + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_PVM_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_IRQHandler [WEAK] + EXPORT DMA1_Channel3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_IRQHandler [WEAK] + EXPORT DMA1_Channel5_IRQHandler [WEAK] + EXPORT DMA1_Channel6_IRQHandler [WEAK] + EXPORT DMA1_Channel7_IRQHandler [WEAK] + EXPORT ADC1_2_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DFSDM1_FLT3_IRQHandler [WEAK] + EXPORT TIM8_BRK_IRQHandler [WEAK] + EXPORT TIM8_UP_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT ADC3_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Channel1_IRQHandler [WEAK] + EXPORT DMA2_Channel2_IRQHandler [WEAK] + EXPORT DMA2_Channel3_IRQHandler [WEAK] + EXPORT DMA2_Channel4_IRQHandler [WEAK] + EXPORT DMA2_Channel5_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT DFSDM1_FLT2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT LPTIM2_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Channel6_IRQHandler [WEAK] + EXPORT DMA2_Channel7_IRQHandler [WEAK] + EXPORT LPUART1_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT SWPMI1_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT CRS_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_PVM_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_IRQHandler +DMA1_Channel3_IRQHandler +DMA1_Channel4_IRQHandler +DMA1_Channel5_IRQHandler +DMA1_Channel6_IRQHandler +DMA1_Channel7_IRQHandler +ADC1_2_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM15_IRQHandler +TIM1_UP_TIM16_IRQHandler +TIM1_TRG_COM_TIM17_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DFSDM1_FLT3_IRQHandler +TIM8_BRK_IRQHandler +TIM8_UP_IRQHandler +TIM8_TRG_COM_IRQHandler +TIM8_CC_IRQHandler +ADC3_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Channel1_IRQHandler +DMA2_Channel2_IRQHandler +DMA2_Channel3_IRQHandler +DMA2_Channel4_IRQHandler +DMA2_Channel5_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +DFSDM1_FLT2_IRQHandler +COMP_IRQHandler +LPTIM1_IRQHandler +LPTIM2_IRQHandler +OTG_FS_IRQHandler +DMA2_Channel6_IRQHandler +DMA2_Channel7_IRQHandler +LPUART1_IRQHandler +QUADSPI_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +SWPMI1_IRQHandler +TSC_IRQHandler +LCD_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +CRS_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +DCMI_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +DMA2D_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct new file mode 100644 index 00000000000..b7d0a9fccdc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_ARM_STD/stm32l496xx.sct @@ -0,0 +1,44 @@ +; Scatter-Loading Description File +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 1MB FLASH (0x100000) + 320KB SRAM (0xxxxx) +LR_IROM1 0x08000000 0x100000 { ; load region size_region + + ER_IROM1 0x08000000 0x100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM + RW_IRAM1 (0x20000000+0x1AC) (0x00500000-0x1AC) { ; RW data 320k L4-SRAM1 + .ANY (+RW +ZI) + } +} + diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld new file mode 100644 index 00000000000..628e11f0cf4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/STM32L496XX.ld @@ -0,0 +1,153 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + SRAM1 (rwx) : ORIGIN = 0x200001AC, LENGTH = 320k - 0x1AC +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * _estack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + _sidata = .; + + .data : AT (__etext) + { + __data_start__ = .; + _sdata = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; + + } > SRAM1 + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > SRAM1 + + .heap (COPY): + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > SRAM1 + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM1 + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S new file mode 100644 index 00000000000..1e5ac5b16f4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_GCC_ARM/startup_stm32l496xx.S @@ -0,0 +1,549 @@ +/** + ****************************************************************************** + * @file startup_stm32l496xx.s + * @author MCD Application Team + * @version V1.1.1 + * @date 29-April-2016 + * @brief STM32L496xx devices vector table GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address, + * - Configure the clock system + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata + +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* Atollic update: set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex-M4. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_PVM_IRQHandler + .word TAMP_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_2_IRQHandler + .word CAN1_TX_IRQHandler + .word CAN1_RX0_IRQHandler + .word CAN1_RX1_IRQHandler + .word CAN1_SCE_IRQHandler + .word EXTI9_5_IRQHandler + .word TIM1_BRK_TIM15_IRQHandler + .word TIM1_UP_TIM16_IRQHandler + .word TIM1_TRG_COM_TIM17_IRQHandler + .word TIM1_CC_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word DFSDM1_FLT3_IRQHandler + .word TIM8_BRK_IRQHandler + .word TIM8_UP_IRQHandler + .word TIM8_TRG_COM_IRQHandler + .word TIM8_CC_IRQHandler + .word ADC3_IRQHandler + .word FMC_IRQHandler + .word SDMMC1_IRQHandler + .word TIM5_IRQHandler + .word SPI3_IRQHandler + .word UART4_IRQHandler + .word UART5_IRQHandler + .word TIM6_DAC_IRQHandler + .word TIM7_IRQHandler + .word DMA2_Channel1_IRQHandler + .word DMA2_Channel2_IRQHandler + .word DMA2_Channel3_IRQHandler + .word DMA2_Channel4_IRQHandler + .word DMA2_Channel5_IRQHandler + .word DFSDM1_FLT0_IRQHandler + .word DFSDM1_FLT1_IRQHandler + .word DFSDM1_FLT2_IRQHandler + .word COMP_IRQHandler + .word LPTIM1_IRQHandler + .word LPTIM2_IRQHandler + .word OTG_FS_IRQHandler + .word DMA2_Channel6_IRQHandler + .word DMA2_Channel7_IRQHandler + .word LPUART1_IRQHandler + .word QUADSPI_IRQHandler + .word I2C3_EV_IRQHandler + .word I2C3_ER_IRQHandler + .word SAI1_IRQHandler + .word SAI2_IRQHandler + .word SWPMI1_IRQHandler + .word TSC_IRQHandler + .word LCD_IRQHandler + .word 0 + .word RNG_IRQHandler + .word FPU_IRQHandler + .word CRS_IRQHandler + .word I2C4_EV_IRQHandler + .word I2C4_ER_IRQHandler + .word DCMI_IRQHandler + .word CAN2_TX_IRQHandler + .word CAN2_RX0_IRQHandler + .word CAN2_RX1_IRQHandler + .word CAN2_SCE_IRQHandler + .word DMA2D_IRQHandler + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM15_IRQHandler + .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM16_IRQHandler + .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM17_IRQHandler + .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak TIM8_BRK_IRQHandler + .thumb_set TIM8_BRK_IRQHandler,Default_Handler + + .weak TIM8_UP_IRQHandler + .thumb_set TIM8_UP_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_IRQHandler + .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S new file mode 100644 index 00000000000..71698fcbb1f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/startup_stm32l496xx.S @@ -0,0 +1,691 @@ +;/********************* COPYRIGHT(c) 2017 STMicroelectronics ******************** +;* File Name : startup_stm32l496xx.s +;* Author : MCD Application Team +;* Version : V1.7.0 +;* Date : 17-February-2017 +;* Description : STM32L496xx Ultra Low Power Devices vector +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1, ADC2 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10] + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt + DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt + DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt + DCD ADC3_IRQHandler ; ADC3 global Interrupt + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt + DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt + DCD COMP_IRQHandler ; COMP Interrupt + DCD LPTIM1_IRQHandler ; LP TIM1 interrupt + DCD LPTIM2_IRQHandler ; LP TIM2 interrupt + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 + DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 + DCD LPUART1_IRQHandler ; LP UART 1 interrupt + DCD QUADSPI_IRQHandler ; Quad SPI global interrupt + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt + DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt + DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt + DCD TSC_IRQHandler ; Touch Sense Controller global interrupt + DCD LCD_IRQHandler ; LCD global interrupt + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG global interrupt + DCD FPU_IRQHandler ; FPU + DCD CRS_IRQHandler ; CRS error + DCD I2C4_EV_IRQHandler ; I2C4 event + DCD I2C4_ER_IRQHandler ; I2C4 error + DCD DCMI_IRQHandler ; DCMI global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD DMA2D_IRQHandler ; DMA2D global interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_PVM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_PVM_IRQHandler + B PVD_PVM_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DFSDM1_FLT3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT3_IRQHandler + B DFSDM1_FLT3_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDMMC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SDMMC1_IRQHandler + B SDMMC1_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK DFSDM1_FLT2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DFSDM1_FLT2_IRQHandler + B DFSDM1_FLT2_IRQHandler + + PUBWEAK COMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP_IRQHandler + B COMP_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + PUBWEAK LPTIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM2_IRQHandler + B LPTIM2_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel6_IRQHandler + B DMA2_Channel6_IRQHandler + + PUBWEAK DMA2_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel7_IRQHandler + B DMA2_Channel7_IRQHandler + + PUBWEAK LPUART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART1_IRQHandler + B LPUART1_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK SWPMI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SWPMI1_IRQHandler + B SWPMI1_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_IRQHandler + B CRS_IRQHandler + + PUBWEAK I2C4_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_EV_IRQHandler + B I2C4_EV_IRQHandler + + PUBWEAK I2C4_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C4_ER_IRQHandler + B I2C4_ER_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf new file mode 100644 index 00000000000..af06fd3e650 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf @@ -0,0 +1,32 @@ +/* [ROM = 1024kb = 0x100000] */ +define symbol __intvec_start__ = 0x08000000; +define symbol __region_ROM_start__ = 0x08000000; +define symbol __region_ROM_end__ = 0x08000000 + 0x100000 - 1; + +/* [RAM = 0x50000] */ +/* Vector table dynamic copy: Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM */ +define symbol __NVIC_start__ = 0x20000000; +define symbol __NVIC_end__ = 0x200001AC - 1; +define symbol __region_SRAM1_start__ = 0x200001AC; /* Aligned on 8 bytes (428 = 53 x 8) */ +define symbol __region_SRAM1_end__ = 0x2004FFFF; + +/* Memory regions */ +define memory mem with size = 4G; +define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]; +define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__]; + +/* Stack 1/8 and Heap 1/4 of RAM */ +define symbol __size_cstack__ = 0x8000; +define symbol __size_heap__ = 0xa000; +define block CSTACK with alignment = 8, size = __size_cstack__ { }; +define block HEAP with alignment = 8, size = __size_heap__ { }; +define block STACKHEAP with fixed order { block HEAP, block CSTACK }; + +initialize by copy with packing = zeros { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in SRAM1_region { readwrite, block STACKHEAP }; + diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis.h new file mode 100644 index 00000000000..41a1233f3b7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis.h @@ -0,0 +1,38 @@ +/* mbed Microcontroller Library + * A generic CMSIS include header + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "stm32l4xx.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis_nvic.h new file mode 100644 index 00000000000..ad22074ad6e --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/cmsis_nvic.h @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB +// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM +#define NVIC_NUM_VECTORS 107 +#define NVIC_RAM_VECTOR_ADDRESS 0X20000000 // Vectors positioned at start of SRAM + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/hal_tick.h new file mode 100644 index 00000000000..173f8e7cb9b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/hal_tick.h @@ -0,0 +1,65 @@ +/** + ****************************************************************************** + * @file hal_tick.h + * @author MCD Application Team + * @brief Initialization of HAL tick + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HAL_TICK_H +#define __HAL_TICK_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stm32l4xx.h" +#include "stm32l4xx_ll_tim.h" +#include "cmsis_nvic.h" + +#define TIM_MST TIM5 +#define TIM_MST_IRQ TIM5_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM5_CLK_ENABLE() + +#define TIM_MST_RESET_ON __HAL_RCC_TIM5_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM5_RELEASE_RESET() + +#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer + +#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2) + +#define HAL_TICK_DELAY (1000) // 1 ms + +#ifdef __cplusplus +} +#endif + +#endif // __HAL_TICK_H + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h new file mode 100644 index 00000000000..cf136503df9 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h @@ -0,0 +1,19771 @@ +/** + ****************************************************************************** + * @file stm32l496xx.h + * @author MCD Application Team + * @version V1.3.0 + * @date 17-February-2017 + * @brief CMSIS STM32L496xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral�s registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup stm32l496xx + * @{ + */ + +#ifndef __STM32L496xx_H +#define __STM32L496xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ +#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ +#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief STM32L4XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum +{ +/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + DFSDM1_FLT3_IRQn = 42, /*!< DFSDM1 Filter 3 global Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FMC_IRQn = 48, /*!< FMC global Interrupt */ + SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ + DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ + DFSDM1_FLT2_IRQn = 63, /*!< DFSDM1 Filter 2 global Interrupt */ + COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ + LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ + DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ + LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ + QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ + SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ + TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ + LCD_IRQn = 78, /*!< LCD global interrupt */ + RNG_IRQn = 80, /*!< RNG global interrupt */ + FPU_IRQn = 81, /*!< FPU global interrupt */ + CRS_IRQn = 82, /*!< CRS global interrupt */ + I2C4_EV_IRQn = 83, /*!< I2C4 Event interrupt */ + I2C4_ER_IRQn = 84, /*!< I2C4 Error interrupt */ + DCMI_IRQn = 85, /*!< DCMI global interrupt */ + CAN2_TX_IRQn = 86, /*!< CAN2 TX interrupt */ + CAN2_RX0_IRQn = 87, /*!< CAN2 RX0 interrupt */ + CAN2_RX1_IRQn = 88, /*!< CAN2 RX1 interrupt */ + CAN2_SCE_IRQn = 89, /*!< CAN2 SCE interrupt */ + DMA2D_IRQn = 90 /*!< DMA2D global interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "system_stm32l4xx.h" +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, 0x1C */ + __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */ + __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */ + uint32_t RESERVED2; /*!< Reserved, 0x2C */ + __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + uint32_t RESERVED3; /*!< Reserved, 0x44 */ + uint32_t RESERVED4; /*!< Reserved, 0x48 */ + __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */ + uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ + uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */ + __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */ + __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */ + __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */ + __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */ + uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ + uint32_t RESERVED9; /*!< Reserved, 0x0AC */ + __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */ + __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */ + +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ + __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: ADC1 base address + 0x30C */ +} ADC_Common_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ +} DAC_TypeDef; + +/** + * @brief DFSDM module registers + */ +typedef struct +{ + __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ + __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ + __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ + __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ + __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ + __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ + __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ + __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ + __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ + __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ + __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ + __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ + __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ + __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ + __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ +} DFSDM_Filter_TypeDef; + +/** + * @brief DFSDM channel configuration registers + */ +typedef struct +{ + __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ + __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ + __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and + short circuit detector register, Address offset: 0x08 */ + __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ + __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ +} DFSDM_Channel_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CSELR; /*!< DMA channel selection register */ +} DMA_Request_TypeDef; + +/* Legacy define */ +#define DMA_request_TypeDef DMA_Request_TypeDef + + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ + __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ + __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ + __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ + __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ + __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved, 0x18 */ + uint32_t RESERVED2; /*!< Reserved, 0x1C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ + __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ + __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ + __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ + __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ + __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ +} EXTI_TypeDef; + + +/** + * @brief Firewall + */ + +typedef struct +{ + __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ + __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ + __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ + __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ + __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ + __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ +} FIREWALL_TypeDef; + + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ + __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ + __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ + __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ + __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ + __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ + uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ + __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ + __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ + __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ + __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ +} FLASH_TypeDef; + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + +} GPIO_TypeDef; + + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ + __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ + __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ + __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ + __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ + __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ + __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ + __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ + __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ + __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ + __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ + __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ + __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ + __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ + __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ + __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ + __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ + __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ + __IO uint32_t PUCRI; /*!< Pull_up control register of portI, Address offset: 0x60 */ + __IO uint32_t PDCRI; /*!< Pull_Down control register of portI, Address offset: 0x64 */ +} PWR_TypeDef; + + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */ + __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */ + __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 configuration register, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ + __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */ + __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ + __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */ + __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ + __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */ + __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */ + __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ + __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */ + __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */ + __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ + __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ + __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ + __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */ + __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + + +/** + * @brief Secure digital input/output Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ +} SPI_TypeDef; + + +/** + * @brief Single Wire Protocol Master Interface SPWMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ + __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved, 0x08 */ + __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ + __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ + __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ + __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ + __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ + __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ +} SWPMI_TypeDef; + + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ + __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ + __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ + __IO uint32_t SWPR2; /*!< SYSCFG SRAM2 write protection register 2, Address offset: 0x28 */ +} SYSCFG_TypeDef; + + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ + __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ + __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ +} TIM_TypeDef; + + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + uint16_t RESERVED2; /*!< Reserved, 0x12 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ + uint16_t RESERVED3; /*!< Reserved, 0x1A */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + uint16_t RESERVED4; /*!< Reserved, 0x26 */ + __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + uint16_t RESERVED5; /*!< Reserved, 0x2A */ +} USART_TypeDef; + +/** + * @brief VREFBUF + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ + __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ + uint32_t Reserved30[2]; /* Reserved 030h*/ + __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ + __IO uint32_t CID; /* User ID Register 03Ch*/ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ + uint32_t Reserved6; /* Reserved 050h*/ + __IO uint32_t GLPMCFG; /* LPM Register 054h*/ + __IO uint32_t GPWRDN; /* Power Down Register 058h*/ + __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ + __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ + uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ + __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ + __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /* dev Configuration Register 800h*/ + __IO uint32_t DCTL; /* dev Control Register 804h*/ + __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ + uint32_t Reserved0C; /* Reserved 80Ch*/ + __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ + __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ + __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ + __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ + uint32_t Reserved20; /* Reserved 820h*/ + uint32_t Reserved9; /* Reserved 824h*/ + __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ + __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ + __IO uint32_t DTHRCTL; /* dev thr 830h*/ + __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ + __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ + __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ + uint32_t Reserved40; /* dedicated EP mask 840h*/ + __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ + uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ + __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ +} USB_OTG_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ + __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ + __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ + __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ + uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ + uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ + __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ + uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ + __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ + __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ + uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /* Host Configuration Register 400h*/ + __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ + __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ + uint32_t Reserved40C; /* Reserved 40Ch*/ + __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ + __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ + __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; + __IO uint32_t HCSPLT; + __IO uint32_t HCINT; + __IO uint32_t HCINTMSK; + __IO uint32_t HCTSIZ; + __IO uint32_t HCDMA; + uint32_t Reserved[2]; +} USB_OTG_HostChannelTypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH(up to 1 MB) base address */ +#define SRAM1_BASE ((uint32_t)0x20000000U) /*!< SRAM1(up to 256 KB) base address */ +#define SRAM2_BASE ((uint32_t)0x10000000U) /*!< SRAM2(64 KB) base address */ +#define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address */ +#define FMC_BASE ((uint32_t)0x60000000U) /*!< FMC base address */ +#define QSPI_BASE ((uint32_t)0x90000000U) /*!< QUADSPI memories accessible over AHB base address */ + +#define FMC_R_BASE ((uint32_t)0xA0000000U) /*!< FMC control registers base address */ +#define QSPI_R_BASE ((uint32_t)0xA0001000U) /*!< QUADSPI control registers base address */ +#define SRAM1_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM1(96 KB) base address in the bit-band region */ +#define SRAM2_BB_BASE ((uint32_t)0x12000000U) /*!< SRAM2(32 KB) base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */ + +/* Legacy defines */ +#define SRAM_BASE SRAM1_BASE +#define SRAM_BB_BASE SRAM1_BB_BASE + +#define SRAM1_SIZE_MAX ((uint32_t)0x00040000U) /*!< maximum SRAM1 size (up to 256 KBytes) */ +#define SRAM2_SIZE ((uint32_t)0x00010000U) /*!< SRAM2 size (64 KBytes) */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000U) + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000U) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000U) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000U) +#define FMC_BANK3 (FMC_BASE + 0x20000000U) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400U) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) +#define CRS_BASE (APB1PERIPH_BASE + 0x6000U) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) +#define I2C4_BASE (APB1PERIPH_BASE + 0x8400U) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) +#define DAC1_BASE (APB1PERIPH_BASE + 0x7400U) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800U) +#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800U) +#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810U) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00U) +#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000U) +#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800U) +#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400U) + + +/*!< APB2 peripherals */ +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000U) +#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030U) +#define COMP1_BASE (APB2PERIPH_BASE + 0x0200U) +#define COMP2_BASE (APB2PERIPH_BASE + 0x0204U) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400U) +#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00U) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800U) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00U) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400U) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800U) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000U) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400U) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800U) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5400U) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5800U) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) +#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000U) +#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) +#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) +#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) +#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) +#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80) +#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0) +#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0) +#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0) +#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) +#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) +#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200) +#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280) + +/*!< AHB1 peripherals */ +#define DMA1_BASE (AHB1PERIPH_BASE) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400U) +#define RCC_BASE (AHB1PERIPH_BASE + 0x1000U) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000U) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) +#define TSC_BASE (AHB1PERIPH_BASE + 0x4000U) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) + + +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008U) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CU) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030U) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044U) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058U) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CU) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080U) +#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8U) + + +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008U) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CU) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030U) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044U) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058U) +#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CU) +#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080U) +#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8U) + + +/*!< AHB2 peripherals */ +#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000U) +#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400U) +#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800U) +#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00U) +#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000U) +#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400U) +#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800U) +#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00U) +#define GPIOI_BASE (AHB2PERIPH_BASE + 0x2000U) + +#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000U) + +#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000U) +#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100U) +#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200U) +#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300U) + +#define DCMI_BASE (AHB2PERIPH_BASE + 0x08050000U) + +#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800U) + + +/*!< FMC Banks registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE ((uint32_t)0xE0042000U) + +/*!< USB registers base address */ +#define USB_OTG_FS_PERIPH_BASE ((uint32_t)0x50000000U) + +#define USB_OTG_GLOBAL_BASE ((uint32_t)0x00000000U) +#define USB_OTG_DEVICE_BASE ((uint32_t)0x00000800U) +#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t)0x00000900U) +#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t)0x00000B00U) +#define USB_OTG_EP_REG_SIZE ((uint32_t)0x00000020U) +#define USB_OTG_HOST_BASE ((uint32_t)0x00000400U) +#define USB_OTG_HOST_PORT_BASE ((uint32_t)0x00000440U) +#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t)0x00000500U) +#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t)0x00000020U) +#define USB_OTG_PCGCCTL_BASE ((uint32_t)0x00000E00U) +#define USB_OTG_FIFO_BASE ((uint32_t)0x00001000U) +#define USB_OTG_FIFO_SIZE ((uint32_t)0x00001000U) + + +#define PACKAGE_BASE ((uint32_t)0x1FFF7500U) /*!< Package data register base address */ +#define UID_BASE ((uint32_t)0x1FFF7590U) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE ((uint32_t)0x1FFF75E0U) /*!< Flash size data register base address */ +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC1_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) +#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) +#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define LPUART1 ((USART_TypeDef *) LPUART1_BASE) +#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) +#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) + +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) +#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) +#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) +#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) +#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE) +#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE) +#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE) +#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE) +#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE) +#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE) +#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE) +#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE) +/* Aliases to keep compatibility after DFSDM renaming */ +#define DFSDM_Channel0 DFSDM1_Channel0 +#define DFSDM_Channel1 DFSDM1_Channel1 +#define DFSDM_Channel2 DFSDM1_Channel2 +#define DFSDM_Channel3 DFSDM1_Channel3 +#define DFSDM_Channel4 DFSDM1_Channel4 +#define DFSDM_Channel5 DFSDM1_Channel5 +#define DFSDM_Channel6 DFSDM1_Channel6 +#define DFSDM_Channel7 DFSDM1_Channel7 +#define DFSDM_Filter0 DFSDM1_Filter0 +#define DFSDM_Filter1 DFSDM1_Filter1 +#define DFSDM_Filter2 DFSDM1_Filter2 +#define DFSDM_Filter3 DFSDM1_Filter3 +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define TSC ((TSC_TypeDef *) TSC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) + + +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) + + +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE) + + +#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) + +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ + +/* + * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie) + */ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ + +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1U << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1U << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1U << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1U << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1U << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1U << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1U << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1U << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1U << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1U << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/* Legacy defines */ +#define ADC_IER_ADRDY (ADC_IER_ADRDYIE) +#define ADC_IER_EOSMP (ADC_IER_EOSMPIE) +#define ADC_IER_EOC (ADC_IER_EOCIE) +#define ADC_IER_EOS (ADC_IER_EOSIE) +#define ADC_IER_OVR (ADC_IER_OVRIE) +#define ADC_IER_JEOC (ADC_IER_JEOCIE) +#define ADC_IER_JEOS (ADC_IER_JEOSIE) +#define ADC_IER_AWD1 (ADC_IER_AWD1IE) +#define ADC_IER_AWD2 (ADC_IER_AWD2IE) +#define ADC_IER_AWD3 (ADC_IER_AWD3IE) +#define ADC_IER_JQOVF (ADC_IER_JQOVFIE) + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1U << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1U << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1U << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1U << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1U << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1U << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_DFSDMCFG_Pos (2U) +#define ADC_CFGR_DFSDMCFG_Msk (0x1U << ADC_CFGR_DFSDMCFG_Pos) /*!< 0x00000004 */ +#define ADC_CFGR_DFSDMCFG ADC_CFGR_DFSDMCFG_Msk /*!< ADC DFSDM mode configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3U << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1U << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2U << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_ALIGN_Pos (5U) +#define ADC_CFGR_ALIGN_Msk (0x1U << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */ + +#define ADC_CFGR_EXTSEL_Pos (6U) +#define ADC_CFGR_EXTSEL_Msk (0xFU << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_1 (0x2U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_2 (0x4U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_3 (0x8U << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2U << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1U << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1U << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1U << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ + +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1U << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7U << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4U << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1U << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1U << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1U << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1U << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1U << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1U << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FU << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01U << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02U << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04U << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08U << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10U << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1U << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1U << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1U << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1U << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1U << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4U << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4U << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7U << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4U << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4U << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7U << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1U << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2U << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4U << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7U << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1U << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2U << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4U << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7U << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1U << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2U << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4U << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7U << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1U << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2U << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4U << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7U << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1U << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2U << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4U << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7U << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1U << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2U << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4U << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1U << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFU << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_TR2_LT2_0 (0x01U << ADC_TR2_LT2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x02U << ADC_TR2_LT2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x04U << ADC_TR2_LT2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x08U << ADC_TR2_LT2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10U << ADC_TR2_LT2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20U << ADC_TR2_LT2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40U << ADC_TR2_LT2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80U << ADC_TR2_LT2_Pos) /*!< 0x00000080 */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFU << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_TR2_HT2_0 (0x01U << ADC_TR2_HT2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x02U << ADC_TR2_HT2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x04U << ADC_TR2_HT2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x08U << ADC_TR2_HT2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x10U << ADC_TR2_HT2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x20U << ADC_TR2_HT2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x40U << ADC_TR2_HT2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x80U << ADC_TR2_HT2_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFU << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_TR3_LT3_0 (0x01U << ADC_TR3_LT3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x02U << ADC_TR3_LT3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x04U << ADC_TR3_LT3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x08U << ADC_TR3_LT3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10U << ADC_TR3_LT3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20U << ADC_TR3_LT3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40U << ADC_TR3_LT3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80U << ADC_TR3_LT3_Pos) /*!< 0x00000080 */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFU << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_TR3_HT3_0 (0x01U << ADC_TR3_HT3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x02U << ADC_TR3_HT3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x04U << ADC_TR3_HT3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x08U << ADC_TR3_HT3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x10U << ADC_TR3_HT3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x20U << ADC_TR3_HT3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x40U << ADC_TR3_HT3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x80U << ADC_TR3_HT3_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FU << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01U << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02U << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04U << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08U << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10U << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FU << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01U << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02U << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04U << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08U << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10U << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FU << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01U << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02U << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04U << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08U << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10U << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FU << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01U << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02U << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04U << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08U << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10U << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FU << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01U << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02U << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04U << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08U << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10U << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FU << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01U << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02U << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04U << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08U << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10U << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FU << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01U << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02U << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04U << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08U << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10U << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FU << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01U << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02U << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04U << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08U << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10U << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FU << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01U << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02U << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04U << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08U << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10U << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FU << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01U << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02U << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04U << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08U << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10U << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FU << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01U << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02U << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04U << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08U << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10U << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFU << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_RDATA_0 (0x0001U << ADC_DR_RDATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x0002U << ADC_DR_RDATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x0004U << ADC_DR_RDATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x0008U << ADC_DR_RDATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x0010U << ADC_DR_RDATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x0020U << ADC_DR_RDATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x0040U << ADC_DR_RDATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x0080U << ADC_DR_RDATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x0100U << ADC_DR_RDATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x0200U << ADC_DR_RDATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x0400U << ADC_DR_RDATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x0800U << ADC_DR_RDATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000U << ADC_DR_RDATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000U << ADC_DR_RDATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000U << ADC_DR_RDATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000U << ADC_DR_RDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0xFU << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8U << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ + +#define ADC_JSQR_JEXTEN_Pos (6U) +#define ADC_JSQR_JEXTEN_Msk (0x3U << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTEN_1 (0x2U << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ + +#define ADC_JSQR_JSQ1_Pos (8U) +#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ + +#define ADC_JSQR_JSQ2_Pos (14U) +#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (20U) +#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ + +#define ADC_JSQR_JSQ4_Pos (26U) +#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */ +#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFU << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ +#define ADC_OFR1_OFFSET1_0 (0x001U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x002U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x004U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x008U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x010U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x020U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x040U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x080U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x100U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x200U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x400U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x800U << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FU << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10U << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1U << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFU << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ +#define ADC_OFR2_OFFSET2_0 (0x001U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x002U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x004U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x008U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x010U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x020U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x040U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x080U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x100U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x200U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x400U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x800U << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FU << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10U << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1U << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFU << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ +#define ADC_OFR3_OFFSET3_0 (0x001U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x002U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x004U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x008U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x010U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x020U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x040U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x080U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x100U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x200U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x400U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x800U << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FU << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10U << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1U << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFU << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ +#define ADC_OFR4_OFFSET4_0 (0x001U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x002U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x004U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x008U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x010U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x020U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x040U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x080U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x100U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x200U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x400U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x800U << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FU << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10U << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1U << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ +#define ADC_JDR1_JDATA_0 (0x0001U << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x0002U << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x0004U << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x0008U << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x0010U << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x0020U << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x0040U << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x0080U << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x0100U << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x0200U << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x0400U << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x0800U << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000U << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000U << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000U << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000U << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ +#define ADC_JDR2_JDATA_0 (0x0001U << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x0002U << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x0004U << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x0008U << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x0010U << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x0020U << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x0040U << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x0080U << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x0100U << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x0200U << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x0400U << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x0800U << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000U << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000U << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000U << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000U << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ +#define ADC_JDR3_JDATA_0 (0x0001U << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x0002U << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x0004U << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x0008U << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x0010U << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x0020U << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x0040U << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x0080U << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x0100U << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x0200U << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x0400U << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x0800U << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000U << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000U << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000U << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000U << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ +#define ADC_JDR4_JDATA_0 (0x0001U << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x0002U << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x0004U << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x0008U << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x0010U << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x0020U << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x0040U << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x0080U << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x0100U << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x0200U << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x0400U << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x0800U << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000U << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000U << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000U << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000U << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFU << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000U << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFU << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000U << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFU << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000U << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FU << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40U << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FU << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40U << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1U << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1U << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1U << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1U << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1U << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1U << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1U << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1U << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1U << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1U << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1U << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1U << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1U << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1U << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1U << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1U << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1U << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1U << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1U << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1U << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1U << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1U << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FU << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01U << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02U << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04U << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08U << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10U << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1U << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3U << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1U << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2U << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3U << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1U << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2U << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFU << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ +#define ADC_CDR_RDATA_MST_0 (0x0001U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000001 */ +#define ADC_CDR_RDATA_MST_1 (0x0002U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000002 */ +#define ADC_CDR_RDATA_MST_2 (0x0004U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000004 */ +#define ADC_CDR_RDATA_MST_3 (0x0008U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000008 */ +#define ADC_CDR_RDATA_MST_4 (0x0010U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000010 */ +#define ADC_CDR_RDATA_MST_5 (0x0020U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000020 */ +#define ADC_CDR_RDATA_MST_6 (0x0040U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000040 */ +#define ADC_CDR_RDATA_MST_7 (0x0080U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000080 */ +#define ADC_CDR_RDATA_MST_8 (0x0100U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000100 */ +#define ADC_CDR_RDATA_MST_9 (0x0200U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000200 */ +#define ADC_CDR_RDATA_MST_10 (0x0400U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000400 */ +#define ADC_CDR_RDATA_MST_11 (0x0800U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00000800 */ +#define ADC_CDR_RDATA_MST_12 (0x1000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00001000 */ +#define ADC_CDR_RDATA_MST_13 (0x2000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00002000 */ +#define ADC_CDR_RDATA_MST_14 (0x4000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00004000 */ +#define ADC_CDR_RDATA_MST_15 (0x8000U << ADC_CDR_RDATA_MST_Pos) /*!< 0x00008000 */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFU << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ +#define ADC_CDR_RDATA_SLV_0 (0x0001U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CDR_RDATA_SLV_1 (0x0002U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CDR_RDATA_SLV_2 (0x0004U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CDR_RDATA_SLV_3 (0x0008U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CDR_RDATA_SLV_4 (0x0010U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CDR_RDATA_SLV_5 (0x0020U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CDR_RDATA_SLV_6 (0x0040U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CDR_RDATA_SLV_7 (0x0080U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CDR_RDATA_SLV_8 (0x0100U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CDR_RDATA_SLV_9 (0x0200U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CDR_RDATA_SLV_10 (0x0400U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CDR_RDATA_SLV_11 (0x0800U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x08000000 */ +#define ADC_CDR_RDATA_SLV_12 (0x1000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CDR_RDATA_SLV_13 (0x2000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x20000000 */ +#define ADC_CDR_RDATA_SLV_14 (0x4000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x40000000 */ +#define ADC_CDR_RDATA_SLV_15 (0x8000U << ADC_CDR_RDATA_SLV_Pos) /*!< 0x80000000 */ + +/******************************************************************************/ +/* */ +/* Controller Area Network */ +/* */ +/******************************************************************************/ +/*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1U << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ + +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1U << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx + * @{ + */ + +#ifndef __STM32L4xx_H +#define __STM32L4xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32L4) +#define STM32L4 +#endif /* STM32L4 */ + +/* Uncomment the line below according to the target STM32L4 device used in your + application + */ + +#if !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ + !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ + !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ + !defined (STM32L496xx) && !defined (STM32L4A6xx) + /* #define STM32L431xx */ /*!< STM32L431xx Devices */ + /* #define STM32L432xx */ /*!< STM32L432xx Devices */ + /* #define STM32L433xx */ /*!< STM32L433xx Devices */ + /* #define STM32L442xx */ /*!< STM32L442xx Devices */ + /* #define STM32L443xx */ /*!< STM32L443xx Devices */ + /* #define STM32L451xx */ /*!< STM32L451xx Devices */ + /* #define STM32L452xx */ /*!< STM32L452xx Devices */ + /* #define STM32L462xx */ /*!< STM32L462xx Devices */ + /* #define STM32L471xx */ /*!< STM32L471xx Devices */ + /* #define STM32L475xx */ /*!< STM32L475xx Devices */ + /* #define STM32L476xx */ /*!< STM32L476xx Devices */ + /* #define STM32L485xx */ /*!< STM32L485xx Devices */ + /* #define STM32L486xx */ /*!< STM32L486xx Devices */ + #define STM32L496xx /*!< STM32L496xx Devices */ + /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + #define USE_HAL_DRIVER +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number V1.3.1 + */ +#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L4_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ + |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ + |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ + |(__STM32L4_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32L431xx) + #include "stm32l431xx.h" +#elif defined(STM32L432xx) + #include "stm32l432xx.h" +#elif defined(STM32L433xx) + #include "stm32l433xx.h" +#elif defined(STM32L442xx) + #include "stm32l442xx.h" +#elif defined(STM32L443xx) + #include "stm32l443xx.h" +#elif defined(STM32L451xx) + #include "stm32l451xx.h" +#elif defined(STM32L452xx) + #include "stm32l452xx.h" +#elif defined(STM32L462xx) + #include "stm32l462xx.h" +#elif defined(STM32L471xx) + #include "stm32l471xx.h" +#elif defined(STM32L475xx) + #include "stm32l475xx.h" +#elif defined(STM32L476xx) + #include "stm32l476xx.h" +#elif defined(STM32L485xx) + #include "stm32l485xx.h" +#elif defined(STM32L486xx) + #include "stm32l486xx.h" +#elif defined(STM32L496xx) + #include "stm32l496xx.h" +#elif defined(STM32L4A6xx) + #include "stm32l4a6xx.h" +#elif defined(STM32L4R5xx) + #include "stm32l4r5xx.h" +#elif defined(STM32L4R9xx) + #include "stm32l4r9xx.h" +#elif defined(STM32L4S5xx) + #include "stm32l4s5xx.h" +#elif defined(STM32L4S9xx) + #include "stm32l4s9xx.h" +#else + #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32l4xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __STM32L4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h new file mode 100644 index 00000000000..b2b77363aee --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/system_stm32l4xx.h @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file system_stm32l4xx.h + * @author MCD Application Team + * @version V1.3.1 + * @date 21-April-2017 + * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32L4XX_H +#define __SYSTEM_STM32L4XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32L4xx_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32L4xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32L4XX_H */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h new file mode 100644 index 00000000000..ece5f1679fa --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h @@ -0,0 +1,67 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2015, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + IRQn_Type irq_n; + uint32_t irq_index; + uint32_t event; + PinName pin; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; + __IO uint32_t *reg_in; + __IO uint32_t *reg_out; +}; + +struct trng_s { + RNG_HandleTypeDef handle; +}; + +#include "common_objects.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c b/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c deleted file mode 100644 index 064e21cc992..00000000000 --- a/targets/TARGET_STM/TARGET_STM32L4/analogin_api.c +++ /dev/null @@ -1,201 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "mbed_assert.h" -#include "analogin_api.h" - -#if DEVICE_ANALOGIN - -#include "mbed_wait_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" -#include "PeripheralPins.h" - -int adc_inited = 0; - -void analogin_init(analogin_t *obj, PinName pin) -{ - uint32_t function = (uint32_t)NC; - - // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) - // are described in PinNames.h and PeripheralPins.c - // Pin value must be between 0xF0 and 0xFF - if ((pin < 0xF0) || (pin >= 0x100)) { - // Normal channels - // Get the peripheral name from the pin and assign it to the object - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC); - // Get the functions (adc channel) from the pin and assign it to the object - function = pinmap_function(pin, PinMap_ADC); - // Configure GPIO - pinmap_pinout(pin, PinMap_ADC); - } else { - // Internal channels - obj->handle.Instance = (ADC_TypeDef *) pinmap_peripheral(pin, PinMap_ADC_Internal); - function = pinmap_function(pin, PinMap_ADC_Internal); - // No GPIO configuration for internal channels - } - MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC); - MBED_ASSERT(function != (uint32_t)NC); - - obj->channel = STM_PIN_CHANNEL(function); - - // Save pin number for the read function - obj->pin = pin; - - // The ADC initialization is done once - if (adc_inited == 0) { - adc_inited = 1; - - // Enable ADC clock - __HAL_RCC_ADC_CLK_ENABLE(); - __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK); - - obj->handle.State = HAL_ADC_STATE_RESET; - // Configure ADC - obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; // Asynchronous clock mode, input ADC clock - obj->handle.Init.Resolution = ADC_RESOLUTION_12B; - obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; - obj->handle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1) - obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example). - obj->handle.Init.LowPowerAutoWait = DISABLE; - obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig - obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled - obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled - obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled - obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event - obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - obj->handle.Init.DMAContinuousRequests = DISABLE; - obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun - obj->handle.Init.OversamplingMode = DISABLE; // No oversampling - - if (HAL_ADC_Init(&obj->handle) != HAL_OK) { - error("Cannot initialize ADC\n"); - } - } -} - -static inline uint16_t adc_read(analogin_t *obj) -{ - ADC_ChannelConfTypeDef sConfig = {0}; - - // Configure ADC channel - switch (obj->channel) { - case 0: - sConfig.Channel = ADC_CHANNEL_VREFINT; - break; - case 1: - sConfig.Channel = ADC_CHANNEL_1; - break; - case 2: - sConfig.Channel = ADC_CHANNEL_2; - break; - case 3: - sConfig.Channel = ADC_CHANNEL_3; - break; - case 4: - sConfig.Channel = ADC_CHANNEL_4; - break; - case 5: - sConfig.Channel = ADC_CHANNEL_5; - break; - case 6: - sConfig.Channel = ADC_CHANNEL_6; - break; - case 7: - sConfig.Channel = ADC_CHANNEL_7; - break; - case 8: - sConfig.Channel = ADC_CHANNEL_8; - break; - case 9: - sConfig.Channel = ADC_CHANNEL_9; - break; - case 10: - sConfig.Channel = ADC_CHANNEL_10; - break; - case 11: - sConfig.Channel = ADC_CHANNEL_11; - break; - case 12: - sConfig.Channel = ADC_CHANNEL_12; - break; - case 13: - sConfig.Channel = ADC_CHANNEL_13; - break; - case 14: - sConfig.Channel = ADC_CHANNEL_14; - break; - case 15: - sConfig.Channel = ADC_CHANNEL_15; - break; - case 16: - sConfig.Channel = ADC_CHANNEL_16; - break; - case 17: - sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; - break; - case 18: - sConfig.Channel = ADC_CHANNEL_VBAT; - break; - default: - return 0; - } - - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5; - sConfig.SingleDiff = ADC_SINGLE_ENDED; - sConfig.OffsetNumber = ADC_OFFSET_NONE; - sConfig.Offset = 0; - - HAL_ADC_ConfigChannel(&obj->handle, &sConfig); - - HAL_ADC_Start(&obj->handle); // Start conversion - - // Wait end of conversion and get value - if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { - return (HAL_ADC_GetValue(&obj->handle)); - } else { - return 0; - } -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - // 12-bit to 16-bit conversion - value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); - return value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = adc_read(obj); - return (float)value * (1.0f / (float)0xFFF); // 12 bits range -} - -#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c new file mode 100644 index 00000000000..550589f3119 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c @@ -0,0 +1,188 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "mbed_wait_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" +#include + +void analogin_init(analogin_t *obj, PinName pin) +{ + static bool adc_calibrated = false; + uint32_t function = (uint32_t)NC; + + // ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...) + // are described in PinNames.h and PeripheralPins.c + // Pin value must be between 0xF0 and 0xFF + if ((pin < 0xF0) || (pin >= 0x100)) { + // Normal channels + // Get the peripheral name from the pin and assign it to the object + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC); + // Get the functions (adc channel) from the pin and assign it to the object + function = pinmap_function(pin, PinMap_ADC); + // Configure GPIO + pinmap_pinout(pin, PinMap_ADC); + } else { + // Internal channels + obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal); + function = pinmap_function(pin, PinMap_ADC_Internal); + // No GPIO configuration for internal channels + } + MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC); + MBED_ASSERT(function != (uint32_t)NC); + + obj->channel = STM_PIN_CHANNEL(function); + + // Save pin number for the read function + obj->pin = pin; + + // Configure ADC object structures + obj->handle.State = HAL_ADC_STATE_RESET; + obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; // Asynchronous clock mode, input ADC clock + obj->handle.Init.Resolution = ADC_RESOLUTION_12B; + obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; + obj->handle.Init.ScanConvMode = DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1) + obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example). + obj->handle.Init.LowPowerAutoWait = DISABLE; + obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig + obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled + obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled + obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled + obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event + obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + obj->handle.Init.DMAContinuousRequests = DISABLE; + obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun + obj->handle.Init.OversamplingMode = DISABLE; // No oversampling + + // Enable ADC clock + __HAL_RCC_ADC_CLK_ENABLE(); + __HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK); + + if (HAL_ADC_Init(&obj->handle) != HAL_OK) { + error("Cannot initialize ADC"); + } + + // ADC calibration is done only once + if (!adc_calibrated) { + adc_calibrated = true; + HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED); + } +} + +uint16_t adc_read(analogin_t *obj) +{ + ADC_ChannelConfTypeDef sConfig = {0}; + + // Configure ADC channel + switch (obj->channel) { + case 0: + sConfig.Channel = ADC_CHANNEL_VREFINT; + break; + case 1: + sConfig.Channel = ADC_CHANNEL_1; + break; + case 2: + sConfig.Channel = ADC_CHANNEL_2; + break; + case 3: + sConfig.Channel = ADC_CHANNEL_3; + break; + case 4: + sConfig.Channel = ADC_CHANNEL_4; + break; + case 5: + sConfig.Channel = ADC_CHANNEL_5; + break; + case 6: + sConfig.Channel = ADC_CHANNEL_6; + break; + case 7: + sConfig.Channel = ADC_CHANNEL_7; + break; + case 8: + sConfig.Channel = ADC_CHANNEL_8; + break; + case 9: + sConfig.Channel = ADC_CHANNEL_9; + break; + case 10: + sConfig.Channel = ADC_CHANNEL_10; + break; + case 11: + sConfig.Channel = ADC_CHANNEL_11; + break; + case 12: + sConfig.Channel = ADC_CHANNEL_12; + break; + case 13: + sConfig.Channel = ADC_CHANNEL_13; + break; + case 14: + sConfig.Channel = ADC_CHANNEL_14; + break; + case 15: + sConfig.Channel = ADC_CHANNEL_15; + break; + case 16: + sConfig.Channel = ADC_CHANNEL_16; + break; + case 17: + sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; + break; + case 18: + sConfig.Channel = ADC_CHANNEL_VBAT; + break; + default: + return 0; + } + + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5; + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + + HAL_ADC_ConfigChannel(&obj->handle, &sConfig); + + HAL_ADC_Start(&obj->handle); // Start conversion + + // Wait end of conversion and get value + if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) { + return (uint16_t)HAL_ADC_GetValue(&obj->handle); + } else { + return 0; + } +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c b/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c index bd5bafbd92b..92386ab594b 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/analogout_device.c @@ -75,6 +75,8 @@ void analogout_init(dac_t *obj, PinName pin) { // Configure DAC obj->handle.Instance = DAC; + obj->handle.State = HAL_DAC_STATE_RESET; + if (HAL_DAC_Init(&obj->handle) != HAL_OK ) { error("HAL_DAC_Init failed"); } diff --git a/targets/TARGET_STM/TARGET_STM32L4/can_device.h b/targets/TARGET_STM/TARGET_STM32L4/can_device.h index 3cb1c1b6c17..997a1b1087d 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32L4/can_device.h @@ -17,7 +17,7 @@ #define MBED_CAN_DEVICE_H #include "cmsis.h" -#include "stm32l4xx_hal.h" +#include "stm32l4xx.h" #ifdef __cplusplus extern "C" { @@ -25,7 +25,7 @@ extern "C" { #ifdef DEVICE_CAN -#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie +#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie #define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn #define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h index ad596e5534f..9dde4bccd2e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h @@ -132,9 +132,9 @@ static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask; + newValue = (uint32_t)__LDREXW(ptr) | mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } @@ -142,9 +142,9 @@ static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask) { uint32_t newValue; do { - newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask; + newValue = (uint32_t)__LDREXW(ptr) &~mask; - } while (__STREXW(newValue,(volatile unsigned long*) ptr)); + } while (__STREXW(newValue, ptr)); } #if defined ( __GNUC__ ) && !defined ( __CC_ARM ) diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index cb3354530af..e7e5b634078 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -230,7 +230,7 @@ static void uart_irq(int id) } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { if (__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) { - volatile uint32_t tmpval = huart->Instance->RDR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear ORE flag } } } @@ -490,10 +490,11 @@ static IRQn_Type serial_get_irq_n(serial_t *obj) case 1: irq_n = USART2_IRQn; break; - +#if defined(USART3_BASE) case 2: irq_n = USART3_IRQn; break; +#endif #if defined(UART4_BASE) case 3: irq_n = UART4_IRQn; @@ -659,13 +660,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) { void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_PE) != RESET) { - volatile uint32_t tmpval = huart->Instance->RDR; // Clear PE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear PE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_FE) != RESET) { - volatile uint32_t tmpval = huart->Instance->RDR; // Clear FE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear FE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_NE) != RESET) { - volatile uint32_t tmpval = huart->Instance->RDR; // Clear NE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear NE flag } else if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) != RESET) { - volatile uint32_t tmpval = huart->Instance->RDR; // Clear ORE flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear ORE flag } } @@ -716,9 +717,9 @@ int serial_irq_handler_asynch(serial_t *obj) HAL_UART_IRQHandler(huart); // Abort if an error occurs - if (return_event & SERIAL_EVENT_RX_PARITY_ERROR || - return_event & SERIAL_EVENT_RX_FRAMING_ERROR || - return_event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + if ((return_event & SERIAL_EVENT_RX_PARITY_ERROR) || + (return_event & SERIAL_EVENT_RX_FRAMING_ERROR) || + (return_event & SERIAL_EVENT_RX_OVERRUN_ERROR)) { return return_event; } @@ -792,7 +793,7 @@ void serial_rx_abort_asynch(serial_t *obj) // clear flags __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_RXNE); - volatile uint32_t tmpval = huart->Instance->RDR; // Clear errors flag + volatile uint32_t tmpval __attribute__((unused)) = huart->Instance->RDR; // Clear errors flag // reset states huart->RxXferCount = 0; diff --git a/targets/TARGET_STM/analogin_api.c b/targets/TARGET_STM/analogin_api.c new file mode 100644 index 00000000000..bb16c628165 --- /dev/null +++ b/targets/TARGET_STM/analogin_api.c @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +uint16_t adc_read(analogin_t *obj); + +uint16_t analogin_read_u16(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + // 12-bit to 16-bit conversion + value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F); + return value; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = adc_read(obj); + return (float)value * (1.0f / (float)0xFFF); // 12 bits range +} + +#endif diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index b89f62891cf..bd2d7342472 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -57,12 +57,18 @@ void can_init_freq (can_t *obj, PinName rd, PinName td, int hz) __HAL_RCC_CAN1_CLK_ENABLE(); obj->index = 0; } -#if defined(CAN2_BASE) && (CAN_NUM == 2) +#if defined(CAN2_BASE) && defined(CAN_2) else if (can == CAN_2) { __HAL_RCC_CAN1_CLK_ENABLE(); // needed to set filters __HAL_RCC_CAN2_CLK_ENABLE(); obj->index = 1; } +#endif +#if defined(CAN3_BASE) && defined(CAN_3) + else if (can == CAN_3) { + __HAL_RCC_CAN3_CLK_ENABLE(); + obj->index = 2; + } #endif else { return; @@ -126,13 +132,20 @@ void can_free(can_t *obj) __HAL_RCC_CAN1_RELEASE_RESET(); __HAL_RCC_CAN1_CLK_DISABLE(); } -#if defined(CAN2_BASE) && (CAN_NUM == 2) +#if defined(CAN2_BASE) && defined(CAN_2) if (can == CAN_2) { __HAL_RCC_CAN2_FORCE_RESET(); __HAL_RCC_CAN2_RELEASE_RESET(); __HAL_RCC_CAN2_CLK_DISABLE(); } #endif +#if defined(CAN3_BASE) && defined(CAN_3) + if (can == CAN_3) { + __HAL_RCC_CAN3_FORCE_RESET(); + __HAL_RCC_CAN3_RELEASE_RESET(); + __HAL_RCC_CAN3_CLK_DISABLE(); + } +#endif } // The following table is used to program bit_timing. It is an adjustment of the sample @@ -549,7 +562,7 @@ void CAN1_SCE_IRQHandler(void) { can_irq(CAN_1, 0); } -#if defined(CAN2_BASE) && (CAN_NUM == 2) +#if defined(CAN2_BASE) && defined(CAN_2) void CAN2_RX0_IRQHandler(void) { can_irq(CAN_2, 1); @@ -562,7 +575,21 @@ void CAN2_SCE_IRQHandler(void) { can_irq(CAN_2, 1); } -#endif // defined(CAN2_BASE) && (CAN_NUM == 2) +#endif +#if defined(CAN3_BASE) && defined(CAN_3) +void CAN3_RX0_IRQHandler(void) +{ + can_irq(CAN_3, 1); +} +void CAN3_TX_IRQHandler(void) +{ + can_irq(CAN_3, 1); +} +void CAN3_SCE_IRQHandler(void) +{ + can_irq(CAN_3, 1); +} +#endif #endif // else void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) @@ -603,7 +630,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) return; } } -#if defined(CAN2_BASE) && (CAN_NUM == 2) +#if defined(CAN2_BASE) && defined(CAN_2) else if ((CANName) can == CAN_2) { switch (type) { case IRQ_RX: @@ -635,6 +662,39 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) return; } } +#endif +#if defined(CAN3_BASE) && defined(CAN_3) + else if ((CANName) can == CAN_3) { + switch (type) { + case IRQ_RX: + ier = CAN_IT_FMP0; + irq_n = CAN3_IRQ_RX_IRQN; + vector = (uint32_t)&CAN3_IRQ_RX_VECT; + break; + case IRQ_TX: + ier = CAN_IT_TME; + irq_n = CAN3_IRQ_TX_IRQN; + vector = (uint32_t)&CAN3_IRQ_TX_VECT; + break; + case IRQ_ERROR: + ier = CAN_IT_ERR; + irq_n = CAN3_IRQ_ERROR_IRQN; + vector = (uint32_t)&CAN3_IRQ_ERROR_VECT; + break; + case IRQ_PASSIVE: + ier = CAN_IT_EPV; + irq_n = CAN3_IRQ_PASSIVE_IRQN; + vector = (uint32_t)&CAN3_IRQ_PASSIVE_VECT; + break; + case IRQ_BUS: + ier = CAN_IT_BOF; + irq_n = CAN3_IRQ_BUS_IRQN; + vector = (uint32_t)&CAN3_IRQ_BUS_VECT; + break; + default: + return; + } + } #endif else { return; diff --git a/targets/TARGET_STM/hal_tick_16b.c b/targets/TARGET_STM/hal_tick_16b.c index 23263d5a958..f8e39f58a0d 100644 --- a/targets/TARGET_STM/hal_tick_16b.c +++ b/targets/TARGET_STM/hal_tick_16b.c @@ -148,12 +148,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) // Enable timer HAL_TIM_Base_Start(&TimMasterHandle); -#ifndef NDEBUG -#ifdef TIM_MST_DBGMCU_FREEZE // Freeze timer on stop/breakpoint + // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example +#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE) TIM_MST_DBGMCU_FREEZE; #endif -#endif #if DEBUG_TICK > 0 __HAL_RCC_GPIOB_CLK_ENABLE(); diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c index 924df8b692e..7e84f34418e 100644 --- a/targets/TARGET_STM/hal_tick_32b.c +++ b/targets/TARGET_STM/hal_tick_32b.c @@ -118,12 +118,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) __HAL_TIM_SET_COMPARE(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY); __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); -#ifndef NDEBUG -#ifdef TIM_MST_DBGMCU_FREEZE // Freeze timer on stop/breakpoint + // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example +#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE) TIM_MST_DBGMCU_FREEZE; #endif -#endif #if DEBUG_TICK > 0 __HAL_RCC_GPIOB_CLK_ENABLE(); diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index dd95931a462..31330863d88 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -274,10 +274,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { obj_s->index = 0; __HAL_RCC_I2C1_CLK_ENABLE(); // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrainPullUp); - pin_mode(scl, OpenDrainPullUp); obj_s->event_i2cIRQ = I2C1_EV_IRQn; obj_s->error_i2cIRQ = I2C1_ER_IRQn; } @@ -287,11 +283,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { if (obj_s->i2c == I2C_2) { obj_s->index = 1; __HAL_RCC_I2C2_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrainPullUp); - pin_mode(scl, OpenDrainPullUp); obj_s->event_i2cIRQ = I2C2_EV_IRQn; obj_s->error_i2cIRQ = I2C2_ER_IRQn; } @@ -301,11 +292,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { if (obj_s->i2c == I2C_3) { obj_s->index = 2; __HAL_RCC_I2C3_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrainPullUp); - pin_mode(scl, OpenDrainPullUp); obj_s->event_i2cIRQ = I2C3_EV_IRQn; obj_s->error_i2cIRQ = I2C3_ER_IRQn; } @@ -315,11 +301,6 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { if (obj_s->i2c == I2C_4) { obj_s->index = 3; __HAL_RCC_I2C4_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrainPullUp); - pin_mode(scl, OpenDrainPullUp); obj_s->event_i2cIRQ = I2C4_EV_IRQn; obj_s->error_i2cIRQ = I2C4_ER_IRQn; } @@ -329,16 +310,17 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { if (obj_s->i2c == FMPI2C_1) { obj_s->index = 4; __HAL_RCC_FMPI2C1_CLK_ENABLE(); - // Configure I2C pins - pinmap_pinout(sda, PinMap_I2C_SDA); - pinmap_pinout(scl, PinMap_I2C_SCL); - pin_mode(sda, OpenDrainPullUp); - pin_mode(scl, OpenDrainPullUp); obj_s->event_i2cIRQ = FMPI2C1_EV_IRQn; obj_s->error_i2cIRQ = FMPI2C1_ER_IRQn; } #endif + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrainNoPull); + pin_mode(scl, OpenDrainNoPull); + // I2C configuration // Default hz value used for timeout computation if(!obj_s->hz) @@ -743,8 +725,10 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count = I2C_ERROR_BUS_BUSY, ret = 0; uint32_t timeout = 0; - if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) || - (obj_s->XferOperation == I2C_LAST_FRAME)) { + // Trick to remove compiler warning "left and right operands are identical" in some cases + uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; + uint32_t op2 = I2C_LAST_FRAME; + if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { if (stop) obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME; else @@ -795,8 +779,10 @@ int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { int count = I2C_ERROR_BUS_BUSY, ret = 0; uint32_t timeout = 0; - if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) || - (obj_s->XferOperation == I2C_LAST_FRAME)) { + // Trick to remove compiler warning "left and right operands are identical" in some cases + uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; + uint32_t op2 = I2C_LAST_FRAME; + if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { if (stop) obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME; else @@ -1083,8 +1069,10 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, /* Set operation step depending if stop sending required or not */ if ((tx_length && !rx_length) || (!tx_length && rx_length)) { - if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) || - (obj_s->XferOperation == I2C_LAST_FRAME)) { + // Trick to remove compiler warning "left and right operands are identical" in some cases + uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; + uint32_t op2 = I2C_LAST_FRAME; + if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { if (stop) obj_s->XferOperation = I2C_FIRST_AND_LAST_FRAME; else @@ -1106,8 +1094,10 @@ void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, } else if (tx_length && rx_length) { /* Two steps operation, don't modify XferOperation, keep it for next step */ - if ((obj_s->XferOperation == I2C_FIRST_AND_LAST_FRAME) || - (obj_s->XferOperation == I2C_LAST_FRAME)) { + // Trick to remove compiler warning "left and right operands are identical" in some cases + uint32_t op1 = I2C_FIRST_AND_LAST_FRAME; + uint32_t op2 = I2C_LAST_FRAME; + if ((obj_s->XferOperation == op1) || (obj_s->XferOperation == op2)) { HAL_I2C_Master_Sequential_Transmit_IT(handle, address, (uint8_t*)tx, tx_length, I2C_FIRST_FRAME); } else if ((obj_s->XferOperation == I2C_FIRST_FRAME) || (obj_s->XferOperation == I2C_NEXT_FRAME)) { diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index 133587e31e4..98c6c500dd7 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -52,7 +52,8 @@ #elif defined(TARGET_STM32F303VC) #define INITIAL_SP (0x2000A000UL) -#elif defined(TARGET_STM32L432KC) +#elif defined(TARGET_STM32L432KC) ||\ + defined (TARGET_STM32L433RC) #define INITIAL_SP (0x20010000UL) #elif (defined(TARGET_STM32F303RE) ||\ @@ -66,6 +67,7 @@ #elif (defined(TARGET_STM32F401RE) ||\ defined(TARGET_STM32L475VG) ||\ defined(TARGET_STM32L476RG) ||\ + defined(TARGET_STM32L476JG) ||\ defined(TARGET_STM32L476VG) ||\ defined(TARGET_STM32L486RG)) #define INITIAL_SP (0x20018000UL) @@ -91,7 +93,8 @@ defined(TARGET_STM32F469NI) ||\ defined(TARGET_STM32F746NG) ||\ defined(TARGET_STM32F746ZG) ||\ - defined(TARGET_STM32F756ZG)) + defined(TARGET_STM32F756ZG) ||\ + defined(TARGET_STM32L496ZG)) #define INITIAL_SP (0x20050000UL) #elif (defined(TARGET_STM32F767ZI) ||\ diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index c9e9341cf8d..23f7625012b 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -57,13 +57,14 @@ static void RTC_IRQHandler(void); void rtc_init(void) { - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; // Enable access to Backup domain HAL_PWR_EnableBkUpAccess(); RtcHandle.Instance = RTC; + RtcHandle.State = HAL_RTC_STATE_RESET; #if !RTC_LSI RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; @@ -162,7 +163,7 @@ void rtc_free(void) #endif // Disable LSI and LSE clocks - RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; RCC_OscInitStruct.LSIState = RCC_LSI_OFF; @@ -217,8 +218,8 @@ It is then not a problem to not use shifts. time_t rtc_read(void) { - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; + RTC_DateTypeDef dateStruct = {0}; + RTC_TimeTypeDef timeStruct = {0}; struct tm timeinfo; RtcHandle.Instance = RTC; @@ -247,8 +248,8 @@ time_t rtc_read(void) void rtc_write(time_t t) { - RTC_DateTypeDef dateStruct; - RTC_TimeTypeDef timeStruct; + RTC_DateTypeDef dateStruct = {0}; + RTC_TimeTypeDef timeStruct = {0}; RtcHandle.Instance = RTC; @@ -295,13 +296,10 @@ int rtc_isenabled(void) static void RTC_IRQHandler(void) { + /* Update HAL state */ HAL_RTCEx_WakeUpTimerIRQHandler(&RtcHandle); -} - -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ + /* In case of registered handler, call it. */ if (irq_handler) { - // Fire the user callback irq_handler(); } } diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c index f10bf69e06e..f77f2b31518 100644 --- a/targets/TARGET_STM/trng_api.c +++ b/targets/TARGET_STM/trng_api.c @@ -23,19 +23,20 @@ #include #include "cmsis.h" #include "trng_api.h" +#include "mbed_error.h" +#include "mbed_critical.h" -/** trng_get_byte - * @brief Get one byte of entropy from the RNG, assuming it is up and running. - * @param obj TRNG obj - * @param pointer to the hardware generated random byte. - */ -static void trng_get_byte(trng_t *obj, unsigned char *byte ) -{ - *byte = (unsigned char)HAL_RNG_GetRandomNumber(&obj->handle); -} +static uint8_t users = 0; void trng_init(trng_t *obj) { + uint32_t dummy; + + /* We're only supporting a single user of RNG */ + if (core_util_atomic_incr_u8(&users, 1) > 1 ) { + error("Only 1 RNG instance supported\r\n"); + } + #if defined(TARGET_STM32L4) RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; @@ -50,11 +51,13 @@ void trng_init(trng_t *obj) /* Initialize RNG instance */ obj->handle.Instance = RNG; + obj->handle.State = HAL_RNG_STATE_RESET; + obj->handle.Lock = HAL_UNLOCKED; + HAL_RNG_Init(&obj->handle); /* first random number generated after setting the RNGEN bit should not be used */ - HAL_RNG_GetRandomNumber(&obj->handle); - + HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy); } void trng_free(trng_t *obj) @@ -63,23 +66,32 @@ void trng_free(trng_t *obj) HAL_RNG_DeInit(&obj->handle); /* RNG Peripheral clock disable - assume we're the only users of RNG */ __HAL_RCC_RNG_CLK_DISABLE(); + + users = 0; } int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) { - int ret; + int ret = 0; + volatile uint8_t random[4]; + *output_length = 0; /* Get Random byte */ - for( uint32_t i = 0; i < length; i++ ){ - trng_get_byte(obj, output + i ); + while ((*output_length < length) && (ret ==0)) { + if ( HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random ) != HAL_OK) { + ret = -1; + } else { + for (uint8_t i =0; (i < 4) && (*output_length < length) ; i++) { + *output++ = random[i]; + *output_length += 1; + random[i] = 0; + } + } } - *output_length = length; /* Just be extra sure that we didn't do it wrong */ if( ( __HAL_RNG_GET_FLAG(&obj->handle, (RNG_FLAG_CECS | RNG_FLAG_SECS)) ) != 0 ) { ret = -1; - } else { - ret = 0; } return( ret ); diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c index c690cb499a1..0de7a2a8bf8 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/analogin_api.c @@ -99,8 +99,8 @@ uint16_t analogin_read_u16(analogin_t *obj) float analogin_read(analogin_t *obj) { - /* Convert from a uint16 to a float between 0 and 1 by division by 0xFFFF */ - return analogin_read_u16(obj) / (float) 0xFFFF; + /* Convert from a uint16 to a float between 0 and 1 by division by 0xFFF0 */ + return analogin_read_u16(obj) / (float) 0xFFF0; } #endif diff --git a/targets/targets.json b/targets/targets.json old mode 100644 new mode 100755 index 444399ceb13..3d4015991e5 --- a/targets/targets.json +++ b/targets/targets.json @@ -110,7 +110,7 @@ "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"], - "default_lib": "small", + "default_lib": "small", "device_name": "LPC11U34FBD48/311" }, "MICRONFCBOARD": { @@ -241,7 +241,12 @@ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"], "release_versions": ["2", "5"], "features": ["LWIP"], - "device_name": "LPC1768" + "device_name": "LPC1768", + "bootloader_supported": true + }, + "LPC1769": { + "inherits": ["LPC1768"], + "device_name": "LPC1769" }, "ARCH_PRO": { "supported_form_factors": ["ARDUINO"], @@ -253,7 +258,8 @@ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"], "release_versions": ["2", "5"], "features": ["LWIP"], - "device_name": "LPC1768" + "device_name": "LPC1768", + "bootloader_supported": true }, "UBLOX_C027": { "supported_form_factors": ["ARDUINO"], @@ -277,7 +283,8 @@ "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"], "release_versions": ["2", "5"], "features": ["LWIP"], - "device_name": "LPC1768" + "device_name": "LPC1768", + "bootloader_supported": true }, "XBED_LPC1768": { "inherits": ["LPCTarget"], @@ -613,6 +620,28 @@ "device_name": "MK64FN1M0xxx12", "bootloader_supported": true }, + "EV_COG_AD4050LZ": { + "inherits": ["Target"], + "core": "Cortex-M4", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"], + "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"], + "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"], + "device_name": "ADuCM4050", + "detect_code": ["0603"], + "release_versions": ["5"] + }, + "EV_COG_AD3029LZ": { + "inherits": ["Target"], + "core": "Cortex-M3", + "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], + "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"], + "extra_labels": ["Analog_Devices", "ADUCM302X", "ADUCM3029", "EV_COG_AD3029LZ", "FLASH_CMSIS_ALGO"], + "device_has": ["SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "RTC", "SPI", "I2C", "FLASH", "ANALOGIN"], + "device_name": "ADuCM3029", + "detect_code": ["0602"], + "release_versions": ["5"] + }, "MTS_GAMBIT": { "inherits": ["Target"], "core": "Cortex-M4F", @@ -635,7 +664,8 @@ "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], "default_lib": "std", "release_versions": ["2", "5"], - "device_name": "MK64FN1M0xxx12" + "device_name": "MK64FN1M0xxx12", + "bootloader_supported": true }, "K66F": { "supported_form_factors": ["ARDUINO"], @@ -646,10 +676,11 @@ "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"], "inherits": ["Target"], "detect_code": ["0311"], - "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG"], + "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"], "features": ["LWIP"], "release_versions": ["2", "5"], - "device_name": "MK66FN2M0xxx18" + "device_name": "MK66FN2M0xxx18", + "bootloader_supported": true }, "K82F": { "supported_form_factors": ["ARDUINO"], @@ -690,18 +721,24 @@ "release_versions": ["2", "5"], "device_name" : "LPC54114J256BD64" }, - "LPC54608": { + "LPC546XX": { "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", "supported_toolchains": ["ARM", "IAR", "GCC_ARM"], - "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPC54608", "LPCXpresso"], + "extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso"], "is_disk_virtual": true, - "macros": ["CPU_LPC54608J512ET180", "FSL_RTOS_MBED"], + "macros": ["CPU_LPC54618J512ET180", "FSL_RTOS_MBED"], "inherits": ["Target"], "detect_code": ["1056"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "release_versions": ["2", "5"], - "device_name" : "LPC54608J512ET180" + "device_name" : "LPC54618J512ET180" + }, + "FF_LPC546XX": { + "inherits": ["LPC546XX"], + "extra_labels_remove" : ["LPCXpresso"], + "supported_form_factors": [""], + "detect_code": ["8081"] }, "NUCLEO_F030R8": { "inherits": ["FAMILY_STM32"], @@ -711,7 +748,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -770,7 +807,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -788,7 +825,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -806,7 +843,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -824,7 +861,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" }, "clock_source_usb": { @@ -851,7 +888,7 @@ }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -870,7 +907,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -907,7 +944,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -924,7 +961,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -941,7 +978,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -959,7 +996,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -977,7 +1014,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -995,7 +1032,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" }, "clock_source_usb": { @@ -1017,7 +1054,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1036,7 +1073,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1071,7 +1108,7 @@ }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" }, "clock_source_usb": { @@ -1101,7 +1138,7 @@ }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" }, "clock_source_usb": { @@ -1127,7 +1164,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1135,7 +1172,8 @@ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"], "release_versions": ["2", "5"], - "device_name": "STM32F446RE" + "device_name": "STM32F446RE", + "bootloader_supported": true }, "NUCLEO_F446ZE": { "inherits": ["FAMILY_STM32"], @@ -1145,7 +1183,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1177,7 +1215,7 @@ }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1201,7 +1239,7 @@ }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1225,7 +1263,7 @@ }, "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1247,7 +1285,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1284,7 +1322,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1302,7 +1340,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1319,7 +1357,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1341,9 +1379,28 @@ } }, "detect_code": ["0770"], - "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "CAN", "TRNG", "FLASH"], + "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "CAN", "TRNG", "FLASH"], "release_versions": ["2", "5"], - "device_name": "STM32L432KC" + "device_name": "STM32L432KC", + "bootloader_supported": true + }, + "NUCLEO_L433RC_P": { + "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO", "MORPHO"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_MSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "detect_code": ["0770"], + "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "CAN", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32L433RC", + "bootloader_supported": true }, "NUCLEO_L476RG": { "inherits": ["FAMILY_STM32"], @@ -1364,6 +1421,24 @@ "device_name": "STM32L476RG", "bootloader_supported": true }, + "SILICA_SENSOR_NODE": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "default_toolchain": "GCC_ARM", + "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476JG"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_MSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "detect_code": ["0766"], + "macros_add": ["USBHOST_OTHER"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], + "release_versions": ["5"], + "device_name": "STM32L476JG" + }, "NUCLEO_L486RG": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], @@ -1401,7 +1476,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1434,7 +1509,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1449,7 +1524,7 @@ "core": "Cortex-M4F", "extra_labels_add": ["STM32F4", "STM32F407", "STM32F407xG", "STM32F407VG"], "supported_toolchains": ["ARM", "uARM", "GCC_ARM"], - "macros_add": ["USB_STM_HAL"], + "macros_add": ["RTC_LSI=1", "USB_STM_HAL"], "device_has_add": ["ANALOGOUT"], "device_name": "STM32F407VG" }, @@ -1459,7 +1534,7 @@ "extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xI", "STM32F429xx"], "config": { "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI", "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" }, @@ -1469,7 +1544,7 @@ "macro_name": "CLOCK_SOURCE_USB" } }, - "macros_add": ["RTC_LSI=1", "USBHOST_OTHER"], + "macros_add": ["RTC_LSI=1", "USB_STM_HAL", "USBHOST_OTHER"], "device_has_add": ["ANALOGOUT", "CAN", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32F429ZI" @@ -1481,7 +1556,7 @@ "extra_labels_add": ["STM32F4", "STM32F469", "STM32F469NI", "STM32F469xI", "STM32F469xx"], "config": { "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI", "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } @@ -1500,7 +1575,7 @@ "config": { "clock_source": { "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", - "value": "USE_PLL_HSE_EXTC|USE_PLL_HSE_XTAL|USE_PLL_HSI", + "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, @@ -1514,16 +1589,15 @@ "core": "Cortex-M0+", "extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"], "supported_form_factors": ["ARDUINO", "MORPHO"], - "macros": ["RTC_LSI=1"], "config": { "clock_source": { - "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI", "value": "USE_PLL_HSI", "macro_name": "CLOCK_SOURCE" } }, "detect_code": ["0833"], - "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG"], + "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "SERIAL_ASYNCH", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32L072CZ" }, @@ -1577,9 +1651,10 @@ "supported_form_factors": ["ARDUINO"], "detect_code": ["0764"], "macros_add": ["USBHOST_OTHER"], - "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], - "device_name": "STM32L475VG" + "device_name": "STM32L475VG", + "bootloader_supported": true }, "DISCO_L476VG": { "inherits": ["FAMILY_STM32"], @@ -1690,19 +1765,56 @@ "device_has_add": [], "device_name": "STM32F401VC" }, - "UBLOX_EVK_ODIN_W2": { + "MODULE_UBLOX_ODIN_W2": { "inherits": ["FAMILY_STM32"], - "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439ZI","STM32F439xx", "STM32F439xI"], "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "HSE_VALUE=24000000", "HSE_STARTUP_TIMEOUT=5000", "CB_INTERFACE_SDIO","CB_CHIP_WL18XX","SUPPORT_80211D_ALWAYS","WLAN_ENABLED","MBEDTLS_ARC4_C","MBEDTLS_DES_C","MBEDTLS_MD4_C","MBEDTLS_MD5_C","MBEDTLS_SHA1_C"], "device_has_add": ["CAN", "EMAC", "TRNG", "FLASH"], "device_has_remove": ["RTC", "SLEEP"], "features": ["LWIP"], - "release_versions": ["5"], "device_name": "STM32F439ZI", "bootloader_supported": true }, + "UBLOX_EVK_ODIN_W2": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "supported_form_factors": ["ARDUINO"], + "release_versions": ["5"], + "config": { + "usb_tx": { + "help": "Value: D8(default) or D1", + "value": "D8" + }, + "usb_rx": { + "help": "Value: D2(default) or D0", + "value": "D2" + }, + "stdio_uart": { + "help": "Value: UART_1(default) or UART_3", + "value": "UART_1", + "macro_name": "STDIO_UART" + } + } + }, + "MBED_CONNECT_ODIN": { + "inherits": ["MODULE_UBLOX_ODIN_W2"], + "release_versions": ["5"], + "config": { + "usb_tx": { + "help": "Value: PA_9(default) or PD_8", + "value": "PA_9" + }, + "usb_rx": { + "help": "Value: PA_10(default) or PD_9", + "value": "PA_10" + }, + "stdio_uart": { + "help": "Value: UART_1(default) or UART_3", + "value": "UART_1", + "macro_name": "STDIO_UART" + } + } + }, "UBLOX_C030": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO"], @@ -1721,7 +1833,7 @@ "macro_name": "MODEM_ON_BOARD_UART" } }, - "macros_add": ["RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"], + "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "RTC_LSI=1", "HSE_VALUE=12000000", "GNSSBAUD=9600"], "device_has_add": ["ANALOGOUT", "SERIAL_FC", "TRNG", "FLASH"], "features": ["LWIP"], "public": false, @@ -2000,6 +2112,15 @@ "extra_labels_add": ["RBLAB_BLENANO"], "macros_add": ["TARGET_RBLAB_BLENANO"] }, + "RBLAB_BLENANO2": { + "supported_form_factors": ["ARDUINO"], + "inherits": ["MCU_NRF52"], + "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], + "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "release_versions": ["2", "5"], + "overrides": {"uart_hwfc": 0}, + "device_name": "nRF52832_xxAA" + }, "NRF51822_Y5_MBUG": { "inherits": ["MCU_NRF51_16K"] }, @@ -2330,13 +2451,14 @@ "EFM32": { "inherits": ["Target"], "extra_labels": ["Silicon_Labs", "EFM32"], + "macros": ["MBEDTLS_CONFIG_HW_SUPPORT"], "public": false }, "EFM32GG990F1024": { "inherits": ["EFM32"], "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"], "core": "Cortex-M3", - "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "device_name": "EFM32GG990F1024", @@ -2390,7 +2512,7 @@ "inherits": ["EFM32"], "extra_labels_add": ["EFM32LG", "256K", "SL_AES"], "core": "Cortex-M3", - "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "device_name": "EFM32LG990F256", @@ -2444,7 +2566,7 @@ "inherits": ["EFM32"], "extra_labels_add": ["EFM32WG", "256K", "SL_AES"], "core": "Cortex-M4F", - "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "device_name": "EFM32WG990F256", @@ -2499,7 +2621,7 @@ "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"], "core": "Cortex-M0+", "default_toolchain": "uARM", - "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"], + "macros_add": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"], "supported_toolchains": ["GCC_ARM", "uARM", "IAR"], "default_lib": "small", "release_versions": ["2"], @@ -2553,7 +2675,7 @@ "extra_labels_add": ["EFM32HG", "64K", "SL_AES"], "core": "Cortex-M0+", "default_toolchain": "uARM", - "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"], + "macros_add": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"], "supported_toolchains": ["GCC_ARM", "uARM", "IAR"], "default_lib": "small", "release_versions": ["2"], @@ -2606,7 +2728,7 @@ "inherits": ["EFM32"], "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"], "core": "Cortex-M4F", - "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "device_name": "EFM32PG1B100F256GM32", @@ -2659,7 +2781,7 @@ "inherits": ["EFM32"], "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", - "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "device_name": "EFR32MG1P132F256GM48", @@ -2670,7 +2792,7 @@ "inherits": ["EFM32"], "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", - "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "public": false, @@ -2760,7 +2882,7 @@ "inherits": ["EFM32"], "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"], "core": "Cortex-M4F", - "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "public": false, @@ -2808,17 +2930,17 @@ } } }, - "EFR32MG12P332F1024GL125": { + "EFR32MG12P332F1024GL125": { "inherits": ["EFM32"], "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"], "core": "Cortex-M4F", - "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], + "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"], "release_versions": ["2", "5"], "public": false, "bootloader_supported": true }, - "TB_SENSE_12": { + "TB_SENSE_12": { "inherits": ["EFR32MG12P332F1024GL125"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG", "FLASH"], "forced_reset_timeout": 5, @@ -3007,6 +3129,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"], + "device_has": ["STCLK_OFF_DURING_SLEEP"], "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"], "OUTPUT_EXT": "hex", "is_disk_virtual": true, @@ -3044,14 +3167,14 @@ "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], - "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"], "device_name": "nRF52832_xxAA" }, "UBLOX_EVA_NINA": { "inherits": ["MCU_NRF52"], "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], - "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"], "overrides": {"uart_hwfc": 0}, "device_name": "nRF52832_xxAA" @@ -3060,7 +3183,7 @@ "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], - "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"], "device_name": "nRF52832_xxAA" }, @@ -3068,7 +3191,7 @@ "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], - "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], "release_versions": ["2", "5"], "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"}, "config": { @@ -3087,6 +3210,7 @@ "inherits": ["Target"], "core": "Cortex-M4F", "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "device_has": ["STCLK_OFF_DURING_SLEEP"], "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"], "OUTPUT_EXT": "hex", "is_disk_virtual": true, @@ -3125,7 +3249,7 @@ "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52840"], "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"], - "device_has": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"], + "device_has_add": ["FLASH", "ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "TRNG"], "release_versions": ["2", "5"], "device_name": "nRF52840_xxAA" }, @@ -3244,6 +3368,24 @@ "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"], "is_disk_virtual": true, "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"], + "config": { + "gpio-irq-debounce-enable": { + "help": "Enable GPIO IRQ debounce", + "value": 0 + }, + "gpio-irq-debounce-enable-list": { + "help": "Comma separated pin list to enable GPIO IRQ debounce", + "value": "NC" + }, + "gpio-irq-debounce-clock-source": { + "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K", + "value": "GPIO_DBCLKSRC_IRC10K" + }, + "gpio-irq-debounce-sample-rate": { + "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768", + "value": "GPIO_DBCLKSEL_16" + } + }, "inherits": ["Target"], "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"], @@ -3317,6 +3459,27 @@ "release_versions": ["2"], "device_name": "nRF51822_xxAC" }, + "NUCLEO_L496ZG": { + "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO", "MORPHO"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32L4", "STM32L496ZG", "STM32L496xG"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_MSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "detect_code": ["0823"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32L496ZG" + }, + "NUCLEO_L496ZG_P": { + "inherits": ["NUCLEO_L496ZG"], + "detect_code": ["0828"] + }, "VBLUNO52": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], diff --git a/tools/build.py b/tools/build.py old mode 100644 new mode 100755 diff --git a/tools/build_api.py b/tools/build_api.py index 790b1bcb65b..cbe2f8d2531 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -575,7 +575,8 @@ def build_project(src_paths, build_path, target, toolchain_name, cur_result["elapsed_time"] = end - start cur_result["output"] = toolchain.get_output() + memap_table cur_result["result"] = "OK" - cur_result["memory_usage"] = memap_instance.mem_report + cur_result["memory_usage"] = (memap_instance.mem_report + if memap_instance is not None else None) cur_result["bin"] = res cur_result["elf"] = splitext(res)[0] + ".elf" cur_result.update(toolchain.report) diff --git a/tools/build_travis.py b/tools/build_travis.py index 0982ee1a932..66f946c005e 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -54,6 +54,7 @@ { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F412ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L432KC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, + { "target": "NUCLEO_L433RC_P", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L476RG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L011K4", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_L031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] }, @@ -63,6 +64,7 @@ { "target": "NUCLEO_F446ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F746ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F767ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "NUCLEO_L496ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "MOTE_L152RC", "toolchains": "GCC_ARM", "libs": ["dsp"] }, diff --git a/tools/detect_targets.py b/tools/detect_targets.py index 5f32801db82..b9aa80df1ca 100644 --- a/tools/detect_targets.py +++ b/tools/detect_targets.py @@ -31,8 +31,13 @@ # Imports related to mbed build api from tools.build_api import mcu_toolchain_matrix from tools.test_api import get_autodetected_MUTS_list +from tools.test_api import get_module_avail from argparse import ArgumentParser +try: + import mbed_lstools +except: + pass def main(): """Entry Point""" @@ -75,15 +80,17 @@ def main(): count = 0 for mut in muts.values(): if re.match(mcu_filter, mut['mcu']): + interface_version = get_interface_version(mut['disk']) print "" - print "[mbed] Detected %s, port %s, mounted %s" % \ - (mut['mcu'], mut['port'], mut['disk']) + print "[mbed] Detected %s, port %s, mounted %s, interface version %s:" % \ + (mut['mcu'], mut['port'], mut['disk'], interface_version) + print "[mbed] Supported toolchains for %s" % mut['mcu'] print mcu_toolchain_matrix(platform_filter=mut['mcu']) count += 1 if count == 0: - print "[mbed] No mbed targets where detected on your system." + print "[mbed] No mbed targets were detected on your system." except KeyboardInterrupt: print "\n[CTRL+c] exit" @@ -92,6 +99,32 @@ def main(): traceback.print_exc(file=sys.stdout) print "[ERROR] %s" % str(exc) sys.exit(1) + +def get_interface_version(mount_point): + """ Function returns interface version from the target mounted on the specified mount point + + mount_point can be acquired via the following: + muts = get_autodetected_MUTS_list() + for mut in muts.values(): + mount_point = mut['disk'] + + @param mount_point Name of disk where platform is connected to host machine. + """ + if get_module_avail('mbed_lstools'): + try : + mbeds = mbed_lstools.create() + details_txt = mbeds.get_details_txt(mount_point) + + if 'Interface Version' in details_txt: + return details_txt['Interface Version'] + + elif 'Version' in details_txt: + return details_txt['Version'] + + except : + return 'unknown' + + return 'unknown' if __name__ == '__main__': main() diff --git a/tools/export/gnuarmeclipse/__init__.py b/tools/export/gnuarmeclipse/__init__.py index 1a432a4c458..5d4dcc8b7d9 100644 --- a/tools/export/gnuarmeclipse/__init__.py +++ b/tools/export/gnuarmeclipse/__init__.py @@ -244,7 +244,7 @@ def create_jinja_ctx(self): opts['ld']['system_libraries'] = self.system_libraries opts['ld']['script'] = join(id.capitalize(), "linker-script-%s.ld" % id) - opts['cpp_cmd'] = " ".join(toolchain.preproc) + opts['cpp_cmd'] = '"{}"'.format(toolchain.preproc[0]) + " " + " ".join(toolchain.preproc[1:]) # Unique IDs used in multiple places. # Those used only once are implemented with {{u.id}}. diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index be9069d40a6..ac1861727e4 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -1,4 +1,7 @@ { + "STM32L496ZG": { + "OGChipSelectEditMenu": "STM32L496ZG\tST STM32L496ZG" + }, "STM32L476VG": { "OGChipSelectEditMenu": "STM32L476VG\tST STM32L476VG" }, @@ -23,6 +26,12 @@ "STM32L476RG": { "OGChipSelectEditMenu": "STM32L476RG\tST STM32L476RG" }, + "STM32L486RG": { + "OGChipSelectEditMenu": "STM32L486RG\tST STM32L486RG" + }, + "STM32L476JG": { + "OGChipSelectEditMenu": "STM32L476JG\tST STM32L476JG" + }, "STM32L011K4": { "OGChipSelectEditMenu": "STM32L011x4\tST STM32L011x4" }, @@ -68,8 +77,8 @@ "LPC54114J256BD64": { "OGChipSelectEditMenu": "LPC54114J256_M4\tNXP LPC54114J256_M4" }, - "LPC54608J512ET180": { - "OGChipSelectEditMenu": "LPC54608J512\tNXP LPC54608J512" + "LPC54618J512ET180": { + "OGChipSelectEditMenu": "LPC54618J512\tNXP LPC54618J512" }, "STM32F072RB": { "OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB" @@ -104,6 +113,9 @@ "LPC1768": { "OGChipSelectEditMenu": "LPC1768\tNXP LPC1768" }, + "LPC1769": { + "OGChipSelectEditMenu": "LPC1769\tNXP LPC1769" + }, "STM32F446RE": { "OGChipSelectEditMenu": "STM32F446RE\tST STM32F446RE" }, @@ -228,5 +240,10 @@ "CExtraOptionsCheck": 1, "CExtraOptions": "--drv_vector_table_base=0x0", "CMSISDAPJtagSpeedList": 10 + }, + "TMPM066FWUG":{ + "OGChipSelectEditMenu": "TMPM066FWUG\tToshiba TMPM066FWUG", + "GFPUCoreSlave": 21, + "GBECoreSlave": 21 } } diff --git a/tools/export/makefile/Makefile.tmpl b/tools/export/makefile/Makefile.tmpl index 2c7240d5ba9..52a3d3d42bc 100644 --- a/tools/export/makefile/Makefile.tmpl +++ b/tools/export/makefile/Makefile.tmpl @@ -101,10 +101,10 @@ all: $(PROJECT).bin $(PROJECT).hex size +@$(call MAKEDIR,$(dir $@)) +@echo "Assemble: $(notdir $<)" {% if needs_asm_preproc %} - @$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -E -o $(@:.o=.E.s) $< - @$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $(@:.o=.E.s) + @$(AS) -c $(ASM_FLAGS) -E -o $(@:.o=.E.s) $< + @$(AS) -c $(ASM_FLAGS) -o $@ $(@:.o=.E.s) {% else %} - @$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $< + @$(AS) -c $(ASM_FLAGS) -o $@ $< {% endif %} @@ -112,10 +112,10 @@ all: $(PROJECT).bin $(PROJECT).hex size +@$(call MAKEDIR,$(dir $@)) +@echo "Assemble: $(notdir $<)" {% if needs_asm_preproc %} - @$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -E -o $(@:.o=.E.s) $< - @$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $(@:.o=.E.s) + @$(AS) -c $(ASM_FLAGS) -E -o $(@:.o=.E.s) $< + @$(AS) -c $(ASM_FLAGS) -o $@ $(@:.o=.E.s) {% else %} - @$(AS) -c $(ASM_FLAGS) $(INCLUDE_PATHS) -o $@ $< + @$(AS) -c $(ASM_FLAGS) -o $@ $< {% endif %} .c.o: diff --git a/tools/export/mcuxpresso/LPC54608_cproject.tmpl b/tools/export/mcuxpresso/LPC546XX_cproject.tmpl similarity index 100% rename from tools/export/mcuxpresso/LPC54608_cproject.tmpl rename to tools/export/mcuxpresso/LPC546XX_cproject.tmpl diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index f76770b202f..e51a11a2d47 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -244,11 +244,31 @@ class Sw4STM32(GNUARMEclipse): 'name': 'NUCLEO-L432KC', 'mcuId': 'STM32L432KCUx' }, + 'NUCLEO_L433RC_P': + { + 'name': 'NUCLEO-L433RC-P', + 'mcuId': 'STM32L433RCTxP' + }, 'NUCLEO_L476RG': { 'name': 'NUCLEO-L476RG', 'mcuId': 'STM32L476RGTx' }, + 'NUCLEO_L486RG': + { + 'name': 'NUCLEO-L486RG', + 'mcuId': 'STM32L486RGTx' + }, + 'NUCLEO_L496ZG': + { + 'name': 'NUCLEO-L496ZG', + 'mcuId': 'STM32L496ZGTx' + }, + 'NUCLEO_L496ZG_P': + { + 'name': 'NUCLEO-L496ZG', + 'mcuId': 'STM32L496ZGTx' + }, } TARGETS = BOARDS.keys() diff --git a/tools/importer/README.md b/tools/importer/README.md new file mode 100644 index 00000000000..a1e993bde45 --- /dev/null +++ b/tools/importer/README.md @@ -0,0 +1,50 @@ +## Importing repositories into mbed-os + +importer.py script can be used to import code base from different repositories into mbed-os. + +### Pre-requisties +1. Get the required repository clone and update it to commit required. Note: Repository should be placed outside the mbed-os. +2. Create json file as per template + +### JSON file template + +You can list all the files and folders which are required to be copied in config file in `file` and `folder` arrays respectively. Script will remove the files/folders specified in `src` section from mbed-os repository before copy operation is performed. +New commit is created on branch `feature_+repo_name+last_sha` with commit message "[REPO_NAME]: Updated to last_sha" + +Note: Only files present in folder will be copied, directories inside the folder will not be copied. + +`commit_sha` is list of commits present in mbed-os repo. These commits will be applied after copying files and folders listed above.Each commit in the commit_sha list is cherry-picked and applied with the -x option, which records the SHA of the source commit in the commit message. +Note: You must resolve any conflicts that arise during this cherry-pick process. Make sure that the "(cherry picked from commit ...)" statement is present in the commit message. Re-execute the python script to apply rest of the SHA commits. + +{ + "files" : [ + { + "src_file" : "CMSIS/Core/Template/ARMv8-M/tz_context.c", + "dest_file" : "cmsis/TARGET_CORTEX_M/mbed_tz_context.c" + }, + ... + { + "src_file" : "", + "dest_file" : "" + } + ], + "folders" : [ + { + "src_folder" : "CMSIS/Core/Include/", + "dest_folder" : "cmsis/TARGET_CORTEX_M/" + }, + ... + { + "src_folder" : "", + "dest_folder" : "" + } + ], + "commit_sha" : [ + "428acae1b2ac15c3ad523e8d40755a9301220822", + "d9d622afe0ca8c7ab9d24c17f9fe59b54dcc61c9", + ] +} + +### Input to importer.py +1. Repository: -r ( Example: CMSIS / Mbed-tls / uVisor) +2. `repo`_importer.json: -c (Example: cmsis_importer.json) diff --git a/tools/importer/cmsis_importer.json b/tools/importer/cmsis_importer.json new file mode 100644 index 00000000000..e2571c259d6 --- /dev/null +++ b/tools/importer/cmsis_importer.json @@ -0,0 +1,154 @@ +{ + "files" : [ + { + "src_file" : "CMSIS/Core/Template/ARMv8-M/tz_context.c", + "dest_file" : "cmsis/TARGET_CORTEX_M/mbed_tz_context.c" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Config/handlers.c", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Config/TARGET_CORTEX_A/handlers.c" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Config/RTX_Config.h", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.h" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Config/RTX_Config.c", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Config/RTX_Config.c" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0/irq_cm0.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_cm0.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M0P/irq_cm0.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mbl.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_cm3.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M3/irq_cm3.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_armv8mml.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_cm4f.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/ARM/irq_ca.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_CORTEX_A/irq_ca.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_cm0.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mbl.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_cm3.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M3/irq_cm3.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_armv8mml.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_cm4f.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/GCC/irq_ca.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0/irq_cm0.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_cm0.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M0P/irq_cm0.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mbl_common.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_cm3.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M3/irq_cm3.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_armv8mml_common.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_cm4f.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S" + }, + { + "src_file" : "CMSIS/RTOS2/RTX/Source/IAR/irq_ca.S", + "dest_file" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S" + } + ], + "folders" : [ + { + "src_folder" : "CMSIS/Core/Include/", + "dest_folder" : "cmsis/TARGET_CORTEX_M/" + }, + { + "src_folder" : "CMSIS/RTOS2/Include/", + "dest_folder" : "rtos/TARGET_CORTEX/rtx5/Include/" + }, + { + "src_folder" : "CMSIS/RTOS2/RTX/Include1/", + "dest_folder" : "rtos/TARGET_CORTEX/rtx4/" + }, + { + "src_folder" : "CMSIS/RTOS2/RTX/Include/", + "dest_folder" : "rtos/TARGET_CORTEX/rtx5/RTX/Include/" + }, + { + "src_folder" : "CMSIS/RTOS2/RTX/Source/", + "dest_folder" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/" + }, + { + "src_folder" : "CMSIS/RTOS2/RTX/Source/", + "dest_folder" : "rtos/TARGET_CORTEX/rtx5/RTX/Source/" + }, + { + "src_folder" : "CMSIS/Core_A/Include/", + "dest_folder" : "cmsis/TARGET_CORTEX_A/" + }, + { + "src_folder" : "CMSIS/Core_A/Source/", + "dest_folder" : "cmsis/TARGET_CORTEX_A/" + } + ], + "commit_sha" : [ + "428acae1b2ac15c3ad523e8d40755a9301220822", + "d9d622afe0ca8c7ab9d24c17f9fe59b54dcc61c9", + "a1fcd36be8ee00aba2c9c1b079f5728368922bc8", + "f3db103d481d8729950414868cfc8123b8055601", + "c07cc6b0f42ff4fe215aa1641a043e205d9128a5", + "dd8fdf4c768e5fef3a7ce2e014de4339dbafe5ce", + "2a837ea97900cc30f82e5a23b95b3f293d17eae1", + "c03b3f9eedab7cb0732d1519c4f1a8d90b08eede", + "314a9eb559752132a89b0dbd986db960b3ab9055", + "e83fd0099a69e6eb865e4e6fcadbfb1328c04c85", + "a019acaf8d6fb1f0512414d072f667cc2749b1d9", + "a884fdc0639ae4e17299838ec9de4fddd83cf93c", + "6c827cb5879bc096e45efd992dfadcb96c1d50bc" + ] +} + diff --git a/tools/importer/importer.py b/tools/importer/importer.py new file mode 100644 index 00000000000..e3a6401d936 --- /dev/null +++ b/tools/importer/importer.py @@ -0,0 +1,254 @@ +import os +import json +import sys +import subprocess +import logging +import argparse +from os.path import dirname, abspath, join + +# Be sure that the tools directory is in the search path +ROOT = abspath(join(dirname(__file__), "../..")) +sys.path.insert(0, ROOT) + +from tools.utils import run_cmd, delete_dir_files, mkdir, copy_file + +def del_file(name): + """ Delete the file in RTOS/CMSIS/features directory of mbed-os + Args: + name - name of the file + """ + result = [] + search_path = [join(ROOT, 'rtos'), join(ROOT, 'cmsis'), join(ROOT, 'features')] + for path in search_path: + for root, dirs, files in os.walk(path): + if name in files: + result.append(os.path.join(root, name)) + for file in result: + os.remove(file) + rel_log.debug("Deleted: %s", os.path.relpath(file, ROOT)) + +def copy_folder(src, dest): + """ Copy contents of folder in mbed-os listed path + Args: + src - src folder path + dest - destination folder path + """ + files = os.listdir(src) + for file in files: + abs_src_file = os.path.join(src, file) + if os.path.isfile(abs_src_file): + abs_dst_file = os.path.join(dest, file) + mkdir(os.path.dirname(abs_dst_file)) + copy_file(abs_src_file, abs_dst_file) + +def run_cmd_with_output(command, exit_on_failure=False): + """ Passes a command to the system and returns a True/False result once the + command has been executed, indicating success/failure. If the command was + successful then the output from the command is returned to the caller. + Commands are passed as a list of tokens. + E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v'] + + Args: + command - system command as a list of tokens + exit_on_failure - If True exit the program on failure (default = False) + + Returns: + result - True/False indicating the success/failure of the command + output - The output of the command if it was successful, else empty string + """ + rel_log.debug('[Exec] %s', ' '.join(command)) + returncode = 0 + output = "" + try: + output = subprocess.check_output(command, shell=True) + except subprocess.CalledProcessError as e: + returncode = e.returncode + + if exit_on_failure: + rel_log.error("The command %s failed with return code: %s", + (' '.join(command)), returncode) + sys.exit(1) + return returncode, output + +def get_curr_sha(repo_path): + """ Gets the latest SHA for the specified repo + Args: + repo_path - path to the repository + + Returns: + sha - last commit SHA + """ + cwd = os.getcwd() + os.chdir(abspath(repo_path)) + + cmd = "git log --pretty=format:%h -n 1" + _, sha = run_cmd_with_output(cmd, exit_on_failure=True) + + os.chdir(cwd) + return sha + +def branch_exists(name): + """ Check if branch already exists in mbed-os local repository. + It will not verify if branch is present in remote repository. + Args: + name - branch name + Returns: + True - If branch is already present + """ + + cmd = "git branch" + _, output = run_cmd_with_output(cmd, exit_on_failure=False) + if name in output: + return True + return False + +def branch_checkout(name): + """ + Checkout the required branch + Args: + name - branch name + """ + cmd = "git checkout " + name + run_cmd_with_output(cmd, exit_on_failure=False) + +def get_last_cherry_pick_sha(branch): + """ + SHA of last cherry pick commit is returned. SHA should be added to all + cherry-pick commits with -x option. + + Args: + branch - Hash to be verified. + Returns - SHA if found, else None + """ + cmd = "git checkout " + branch + run_cmd_with_output(cmd, exit_on_failure=False) + + sha = None + get_commit = "git log -n 1" + _, output = run_cmd_with_output(get_commit, exit_on_failure=True) + lines = output.split('\n') + for line in lines: + if 'cherry picked from' in line: + sha = line.split(' ')[-1] + return sha[:-1] + return sha + +if __name__ == "__main__": + + parser = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + parser.add_argument('-l', '--log-level', + help="Level for providing logging output", + default='INFO') + parser.add_argument('-r', '--repo-path', + help="Git Repository to be imported", + default=None, + required=True) + parser.add_argument('-c', '--config-file', + help="Configuration file", + default=None, + required=True) + args = parser.parse_args() + level = getattr(logging, args.log_level.upper()) + + # Set logging level + logging.basicConfig(level=level) + rel_log = logging.getLogger("Importer") + + if (args.repo_path is None) or (args.config_file is None): + rel_log.error("Repository path and config file required as input. Use \"--help\" for more info.") + exit(1) + + json_file = os.path.abspath(args.config_file) + if not os.path.isfile(json_file): + rel_log.error("%s not found.", args.config_file) + exit(1) + + repo = os.path.abspath(args.repo_path) + if not os.path.exists(repo): + rel_log.error("%s not found.", args.repo_path) + exit(1) + + sha = get_curr_sha(repo) + if not sha: + rel_log.error("Could not obtain latest SHA") + exit(1) + rel_log.info("%s SHA = %s", os.path.basename(repo), sha) + + branch = 'feature_' + os.path.basename(repo) + '_' + sha + commit_msg = "[" + os.path.basename(repo) + "]" + ": Updated to " + sha + + # Read configuration data + with open(json_file, 'r') as config: + json_data = json.load(config) + + ''' + Check if branch exists already, in case branch is present + we will skip all file transfer and merge operations and will + jump to cherry-pick + ''' + if branch_exists(branch): + rel_log.info("Branch present = %s", branch) + else: + data_files = json_data["files"] + data_folders = json_data["folders"] + + ## Remove all files listed in .json from mbed-os repo to avoid duplications + for file in data_files: + src_file = file['src_file'] + del_file(os.path.basename(src_file)) + + for folder in data_folders: + dest_folder = folder['dest_folder'] + delete_dir_files(dest_folder) + rel_log.debug("Deleted = %s", folder) + + rel_log.info("Removed files/folders listed in json file") + + ## Copy all the CMSIS files listed in json file to mbed-os + for file in data_files: + repo_file = os.path.join(repo, file['src_file']) + mbed_path = os.path.join(ROOT, file['dest_file']) + mkdir(os.path.dirname(mbed_path)) + copy_file(repo_file, mbed_path) + rel_log.debug("Copied = %s", mbed_path) + + for folder in data_folders: + repo_folder = os.path.join(repo, folder['src_folder']) + mbed_path = os.path.join(ROOT, folder['dest_folder']) + copy_folder(repo_folder, mbed_path) + rel_log.debug("Copied = %s", mbed_path) + + ## Create new branch with all changes + create_branch = "git checkout -b "+ branch + run_cmd_with_output(create_branch, exit_on_failure=True) + rel_log.info("Branch created = %s", branch) + + add_files = "git add -A" + run_cmd_with_output(add_files, exit_on_failure=True) + + commit_branch = "git commit -m \"" + commit_msg + "\"" + run_cmd_with_output(commit_branch, exit_on_failure=True) + rel_log.info("Commit added = %s", mbed_path) + + ## Checkout the feature branch + branch_checkout(branch) + commit_sha = json_data["commit_sha"] + last_sha = get_last_cherry_pick_sha(branch) + if not last_sha: + ## Apply commits specific to mbed-os changes + for sha in commit_sha: + cherry_pick_sha = "git cherry-pick -x " + sha + run_cmd_with_output(cherry_pick_sha, exit_on_failure=True) + rel_log.info("Commit added = %s", cherry_pick_sha) + ## Few commits are already applied, check the next in sequence + ## and skip to last applied + else: + found = False + for sha in commit_sha: + if sha == last_sha: + found = True + continue + if found is True: + cherry_pick_sha = "git cherry-pick -x " + sha + run_cmd_with_output(cherry_pick_sha, exit_on_failure=True) diff --git a/tools/memap.py b/tools/memap.py index 458cb510f2e..a2efd0e230d 100644 --- a/tools/memap.py +++ b/tools/memap.py @@ -469,7 +469,6 @@ def parse_map_file_iar(self, file_desc): object_name = self.check_new_object_lib_iar(line) if object_name and current_library: - print("Replacing module", object_name, current_library) temp = '[lib]' + '/'+ current_library + '/'+ object_name self.module_replace(object_name, temp) diff --git a/tools/profiles/debug.json b/tools/profiles/debug.json index ad4fab345a7..ff8d9ed0561 100644 --- a/tools/profiles/debug.json +++ b/tools/profiles/debug.json @@ -51,7 +51,7 @@ "common": [ "--no_wrap_diagnostics", "-e", "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-On", "-r", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 6142485a5fa..465a1853f80 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -46,7 +46,7 @@ "IAR": { "common": [ "--no_wrap_diagnostics", "-e", - "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh"], + "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/profiles/release.json b/tools/profiles/release.json index eedbce067f6..11207322d66 100644 --- a/tools/profiles/release.json +++ b/tools/profiles/release.json @@ -46,7 +46,7 @@ "IAR": { "common": [ "--no_wrap_diagnostics", "-e", - "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG"], + "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Ohz", "-DNDEBUG", "--enable_restrict"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py index 86eda42934f..be991645aef 100644 --- a/tools/targets/REALTEK_RTL8195AM.py +++ b/tools/targets/REALTEK_RTL8195AM.py @@ -9,6 +9,7 @@ import shutil from tools.paths import TOOLS_BOOTLOADERS +from tools.toolchains import TOOLCHAIN_PATHS from datetime import datetime # Constant Variables @@ -122,7 +123,8 @@ def parse_load_segment_gcc(image_elf): # LOAD 0x000034 0x10006000 0x10006000 0x026bc 0x026bc RW 0x8 # LOAD 0x0026f0 0x30000000 0x30000000 0x06338 0x06338 RWE 0x4 segment_list = [] - cmd = 'arm-none-eabi-readelf -l ' + image_elf + cmd = os.path.join(TOOLCHAIN_PATHS['GCC_ARM'], 'arm-none-eabi-readelf') + cmd = '"' + cmd + '"' + ' -l ' + image_elf for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"): if not line.startswith(" LOAD"): continue @@ -153,7 +155,8 @@ def parse_load_segment_armcc(image_elf): (offset, addr, size) = (0, 0, 0) segment_list = [] in_segment = False - cmd = 'fromelf --text -v --only=none ' + image_elf + cmd = os.path.join(TOOLCHAIN_PATHS['ARM'], 'bin', 'fromelf') + cmd = '"' + cmd + '"' + ' --text -v --only=none ' + image_elf for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"): if line == "": pass @@ -201,7 +204,8 @@ def parse_load_segment_iar(image_elf): segment_list = [] in_segment = False - cmd = 'ielfdumparm ' + image_elf + cmd = os.path.join(TOOLCHAIN_PATHS['IAR'], 'bin', 'ielfdumparm') + cmd = '"' + cmd + '"' + ' ' + image_elf for line in subprocess.check_output(cmd, shell=True, universal_newlines=True).split("\n"): if line.startswith(" SEGMENTS:"): in_segment = True diff --git a/tools/targets/lint.py b/tools/targets/lint.py index f83838d8b3e..0202d45a315 100644 --- a/tools/targets/lint.py +++ b/tools/targets/lint.py @@ -82,7 +82,7 @@ def check_inherits(dict): "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "TRNG","SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", - "STORAGE"] + "STORAGE", "STCLK_OFF_DURING_SLEEP"] def check_device_has(dict): for name in dict.get("device_has", []): if name not in DEVICE_HAS_ALLOWED: diff --git a/tools/test/detect_targets_test.py b/tools/test/detect_targets_test.py new file mode 100644 index 00000000000..be21a32956b --- /dev/null +++ b/tools/test/detect_targets_test.py @@ -0,0 +1,160 @@ +""" +mbed SDK +Copyright (c) 2017 ARM Limited + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + +http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +""" + +import unittest +from mock import patch +from tools.detect_targets import get_interface_version + + +class MbedLsToolsMock(): + """ + Mock of mbedls tools + """ + + def __init__(self, test_type): + self.interface_test_type = test_type + + def get_details_txt(self, mount_point): + return self.details_txt_types[self.interface_test_type]; + + # Static details.txt types. + details_txt_types = { + 'details_valid_interface_version' : { + 'Unique ID': '0226000029164e45002f0012706e0006f301000097969900', + 'HIF ID': '97969900', + 'Auto Reset': '0', + 'Automation allowed': '0', + 'Daplink Mode': 'Interface', + 'Interface Version': '0240', + 'Git SHA': 'c765cbb590f57598756683254ca38b211693ae5e', + 'Local Mods': '0', + 'USB Interfaces': 'MSD, CDC, HID', + 'Interface CRC': '0x26764ebf' + }, + 'details_valid_version' : { + 'Version': '0226', + 'Build': 'Aug 24 2015 17:06:30', + 'Git Commit SHA': '27a236b9fe39c674a703c5c89655fbd26b8e27e1', + 'Git Local mods': 'Yes' + }, + 'details_missing_interface_version' : { + 'Unique ID': '0226000033514e450044500585d4001de981000097969900', + 'HIC ID': '97969900', + 'Auto Reset': '0', + 'Automation allowed': '0', + 'Overflow detection': '0', + 'Daplink Mode': 'Interface', + 'Git SHA': 'b403a07e3696cee1e116d44cbdd64446e056ce38', + 'Local Mods': '0', + 'USB Interfaces': 'MSD, CDC, HID', + 'Interface CRC': '0x4d98bf7e', + 'Remount count': '0' + }, + 'details_invalid_none' : None + } + +""" +Tests for detect_targets.py +""" + +class DetectTargetsTest(unittest.TestCase): + """ + Test cases for Detect Target functionality + """ + + def setUp(self): + """ + Called before each test case + + :return: + """ + self.missing_mount_point = None + self.mount_point = "D:" + + def tearDown(self): + """ + Nothing to tear down. + Called after each test case + + :return: + """ + pass + + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_interface_version')) + def test_interface_version_valid(self, mbed_lstools_mock): + """ + Test that checks function returns correctly when given a valid Interface Version + + :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock + :return + """ + + interface_version = get_interface_version(self.mount_point) + assert interface_version == '0240' + + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_valid_version')) + def test_version_valid(self, mbed_lstools_mock): + """ + Test that checks function returns correctly when given a valid Version + + :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock + :return + """ + + interface_version = get_interface_version(self.mount_point) + assert interface_version == '0226' + + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_missing_interface_version')) + def test_interface_version_missing_interface_version(self, mbed_lstools_mock): + """ + Test that checks function returns correctly when DETAILS.txt is present + but an interface version is not listed. + + :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock + :return + """ + + interface_version = get_interface_version(self.mount_point) + assert interface_version == 'unknown' + + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none')) + def test_version_none(self, mbed_lstools_mock): + """ + Test that checks function returns correctly when a valid mount point is supplied + but DETAILS.txt is not present. + + :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock + :return + """ + + interface_version = get_interface_version(self.mount_point) + assert interface_version == 'unknown' + + @patch("mbed_lstools.create", return_value=MbedLsToolsMock('details_invalid_none')) + def test_interface_version_missing_mount_point(self, mbed_lstools_mock): + """ + Test that checks function returns correctly when no mount point is supplied. + + :param mbed_lstools_mock: Mocks Mbed LS tools with MbedLsToolsMock + :return + """ + + interface_version = get_interface_version(self.missing_mount_point) + assert interface_version == 'unknown' + +if __name__ == '__main__': + unittest.main() diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index 884dd8e22bb..23f17c1ff80 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -7,17 +7,17 @@ }, "via-branch" : { "help" : "-b cmd line option. Update dst branch, created from src branch", - "src-branch" : "mbed-os-5.5.0-rc1-oob", - "dst-branch" : "mbed-os-5.5.0-rc2-oob" + "src-branch" : "mbed-os-5.6.0-oob2", + "dst-branch" : "mbed-os-5.6.0-oob2" }, - "tag" : "mbed-os-5.5.0-rc2" + "tag" : "mbed-os-5.6.2" }, "examples": [ { "name": "mbed-os-example-blinky", "github": "https://github.com/ARMmbed/mbed-os-example-blinky", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-blinky" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-blinky" ], "test-repo-source": "github", "features" : [], @@ -32,10 +32,10 @@ "name": "mbed-os-example-tls", "github": "https://github.com/ARMmbed/mbed-os-example-tls", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-benchmark", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-tls-client", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-hashing", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-tls-authcrypt" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-benchmark", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-tls-client", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-hashing", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-tls-authcrypt" ], "test-repo-source": "mbed", "features" : [], @@ -50,7 +50,7 @@ "name": "mbed-os-example-mesh-minimal", "github":"https://github.com/ARMmbed/mbed-os-example-mesh-minimal", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-mesh-minimal" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-mesh-minimal" ], "test-repo-source": "github", "features" : [], @@ -68,16 +68,14 @@ "name": "mbed-os-example-ble", "github":"https://github.com/ARMmbed/mbed-os-example-ble", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Beacon", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-HeartRate", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Thermometer", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-LEDBlinker", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-LED", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-GAPButton", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-EddystoneService", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-EddystoneObserver", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-Button", - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-ble-BatteryLevel" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-Beacon", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-HeartRate", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-Thermometer", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-LEDBlinker", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-LED", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-GAPButton", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-Button", + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-ble-BatteryLevel" ], "test-repo-source": "mbed", "features" : ["BLE"], @@ -92,7 +90,7 @@ "name": "mbed-os-example-client", "github":"https://github.com/ARMmbed/mbed-os-example-client", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-client" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-client" ], "test-repo-source": "github", "features" : ["LWIP"], @@ -174,7 +172,7 @@ "name": "mbed-os-example-bootloader", "github":"https://github.com/ARMmbed/mbed-os-example-bootloader", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-bootloader" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-bootloader" ], "test-repo-source": "github", "features" : [], @@ -189,7 +187,7 @@ "name": "mbed-os-example-fat-filesystem", "github":"https://github.com/ARMmbed/mbed-os-example-fat-filesystem", "mbed": [ - "https://developer.mbed.org/teams/mbed-os-examples/code/mbed-os-example-fat-filesystem" + "https://os.mbed.com/teams/mbed-os-examples/code/mbed-os-example-fat-filesystem" ], "test-repo-source": "github", "features" : [], diff --git a/tools/test/examples/examples.py b/tools/test/examples/examples.py index 4a6adcd6474..fcc3485baf2 100644 --- a/tools/test/examples/examples.py +++ b/tools/test/examples/examples.py @@ -54,6 +54,11 @@ def main(): argparse_force_uppercase_type( official_target_names, "MCU")), default=official_target_names) + + compile_cmd.add_argument("--profile", + help=("build profile file"), + metavar="profile") + export_cmd = subparsers.add_parser("export") export_cmd.set_defaults(fn=do_export), export_cmd.add_argument( @@ -111,7 +116,7 @@ def do_deploy(_, config, examples): def do_compile(args, config, examples): """Do the compile step""" results = {} - results = lib.compile_repos(config, args.toolchains, args.mcu, examples) + results = lib.compile_repos(config, args.toolchains, args.mcu, args.profile, examples) lib.print_summary(results) failures = lib.get_num_failures(results) diff --git a/tools/test/examples/examples_lib.py b/tools/test/examples/examples_lib.py index 99aa11a5d42..5ff5de8444c 100644 --- a/tools/test/examples/examples_lib.py +++ b/tools/test/examples/examples_lib.py @@ -169,7 +169,7 @@ def source_repos(config, examples): subprocess.call(["mbed-cli", "import", repo_info['repo']]) -def clone_repos(config, examples): +def clone_repos(config, examples , retry = 3): """ Clones each of the repos associated with the specific examples name from the json config file. Note if there is already a clone of the repo then it will first be removed to ensure a clean, up to date cloning. @@ -185,8 +185,11 @@ def clone_repos(config, examples): if os.path.exists(name): print("'%s' example directory already exists. Deleting..." % name) rmtree(name) - - subprocess.call([repo_info['type'], "clone", repo_info['repo']]) + for i in range(0, retry): + if subprocess.call([repo_info['type'], "clone", repo_info['repo']]) == 0: + break + else: + print("ERROR : unable to clone the repo {}".format(name)) def deploy_repos(config, examples): """ If the example directory exists as provided by the json config file, @@ -289,7 +292,7 @@ def status(message): status("SUCCESS exporting") status("Building") try: - if EXPORTERS[ide].build(example_project_name): + if EXPORTERS[ide].build(example_project_name, cleanup=False): status("FAILURE building") build_failures.append(example_name) else: @@ -311,7 +314,7 @@ def status(message): return results -def compile_repos(config, toolchains, targets, examples): +def compile_repos(config, toolchains, targets, profile, examples): """Compiles combinations of example programs, targets and compile chains. The results are returned in a [key: value] dictionary format: @@ -355,8 +358,14 @@ def compile_repos(config, toolchains, targets, examples): valid_choices(example['toolchains'], toolchains), example['features']): print("Compiling %s for %s, %s" % (name, target, toolchain)) - proc = subprocess.Popen(["mbed-cli", "compile", "-t", toolchain, - "-m", target, "-v"]) + build_command = ["mbed-cli", "compile", "-t", toolchain, "-m", target, "-v"] + + if profile: + build_command.append("--profile") + build_command.append(profile) + + proc = subprocess.Popen(build_command) + proc.wait() example_summary = "{} {} {}".format(name, target, toolchain) if proc.returncode: diff --git a/tools/test/examples/update.py b/tools/test/examples/update.py index 64b6a66fc73..a385d6fbe15 100644 --- a/tools/test/examples/update.py +++ b/tools/test/examples/update.py @@ -36,22 +36,21 @@ # # Command usage: # -# update.py -c - T -l -f -b +# update.py -c - T -f -b -s # # Where: # -c - Optional path to an examples file. # If not proved the default is 'examples.json' # -T - GitHub token for secure access (required) -# -l - Optional Level for providing logging output. Can be one of, -# CRITICAL, ERROR, WARNING, INFO, DEBUG -# If not provided the default is 'INFO' # -f - Update forked repos. This will use the 'github-user' parameter in # the 'via-fork' section. # -b - Update branched repos. This will use the "src-branch" and # "dst-branch" parameters in the 'via-branch' section. The destination # branch is created from the source branch (if it doesn't already exist). +# -s - Show the status of any pull requests with a tag matching that in the +# json config file # -# The options -f and -b are mutually exlusive. Only one can be specified. +# The options -f, -b and -s are mutually exlusive. Only one can be specified. # # @@ -75,16 +74,34 @@ import examples_lib as lib from examples_lib import SUPPORTED_TOOLCHAINS +userlog = logging.getLogger("Update") + +# Set logging level +userlog.setLevel(logging.DEBUG) + +# Everything is output to the log file +logfile = os.path.join(os.getcwd(), 'update.log') +fh = logging.FileHandler(logfile) +fh.setLevel(logging.DEBUG) + +# create console handler with a higher log level +ch = logging.StreamHandler() +ch.setLevel(logging.INFO) + +formatter = logging.Formatter('%(name)s: %(levelname)s - %(message)s') +ch.setFormatter(formatter) +fh.setFormatter(formatter) + +# add the handlers to the logger +userlog.addHandler(fh) +userlog.addHandler(ch) + def run_cmd(command, exit_on_failure=False): - """ Run a system command and return the result status + """ Run a system command returning a status result - Description: + This is just a wrapper for the run_cmd_with_output() function, but + only returns the status of the call. - Passes a command to the system and returns a True/False result, once the - command has been executed, indicating success/failure. Commands are passed - as a list of tokens. - E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v'] - Args: command - system command as a list of tokens exit_on_failure - If True exit the program on failure (default = False) @@ -92,49 +109,41 @@ def run_cmd(command, exit_on_failure=False): Returns: return_code - True/False indicating the success/failure of the command """ - update_log.debug('[Exec] %s', ' '.join(command)) - return_code = subprocess.call(command, shell=True) - - if return_code: - update_log.warning("Command '%s' failed with return code: %s", - ' '.join(command), return_code) - if exit_on_failure: - sys.exit(1) - + return_code, _ = run_cmd_with_output(command, exit_on_failure) return return_code def run_cmd_with_output(command, exit_on_failure=False): - """ Run a system command and return the result status plus output + """ Run a system command returning a status result and any command output - Description: - Passes a command to the system and returns a True/False result once the command has been executed, indicating success/failure. If the command was successful then the output from the command is returned to the caller. - Commands are passed as a list of tokens. - E.g. The command 'git remote -v' would be passed in as ['git', 'remote', '-v'] + Commands are passed as a string. + E.g. The command 'git remote -v' would be passed in as "git remote -v" Args: - command - system command as a list of tokens + command - system command as a string exit_on_failure - If True exit the program on failure (default = False) Returns: - returncode - True/False indicating the success/failure of the command + return_code - True/False indicating the success/failure of the command output - The output of the command if it was successful, else empty string """ - update_log.debug('[Exec] %s', ' '.join(command)) + text = '[Exec] ' + command + userlog.debug(text) returncode = 0 output = "" try: output = subprocess.check_output(command, shell=True) except subprocess.CalledProcessError as e: - update_log.warning("Command '%s' failed with return code: %s", - ' '.join(command), e.returncode) + text = "The command " + str(command) + "failed with return code: " + str(e.returncode) + userlog.warning(text) returncode = e.returncode if exit_on_failure: sys.exit(1) return returncode, output + def rmtree_readonly(directory): """ Deletes a readonly directory tree. @@ -198,7 +207,7 @@ def upgrade_single_example(example, tag, directory, ref): os.rename("mbed-os.lib", "mbed-os.lib_bak") else: - update_log.error("Failed to backup mbed-os.lib prior to updating.") + userlog.error("Failed to backup mbed-os.lib prior to updating.") return False # mbed-os.lib file contains one line with the following format @@ -221,7 +230,7 @@ def upgrade_single_example(example, tag, directory, ref): if updated: # Setup and run the git add command - cmd = ['git', 'add', 'mbed-os.lib'] + cmd = "git add mbed-os.lib" return_code = run_cmd(cmd) os.chdir(cwd) @@ -242,12 +251,12 @@ def prepare_fork(arm_example): """ logstr = "In: " + os.getcwd() - update_log.debug(logstr) + userlog.debug(logstr) - for cmd in [['git', 'remote', 'add', 'armmbed', arm_example], - ['git', 'fetch', 'armmbed'], - ['git', 'reset', '--hard', 'armmbed/master'], - ['git', 'push', '-f', 'origin']]: + for cmd in ["git remote add armmbed " + str(arm_example), + "git fetch armmbed", + "git reset --hard armmbed/master", + "git push -f origin"]: run_cmd(cmd, exit_on_failure=True) def prepare_branch(src, dst): @@ -265,25 +274,34 @@ def prepare_branch(src, dst): """ - update_log.debug("Preparing branch: %s", dst) + userlog.debug("Preparing branch: %s", dst) # Check if branch already exists or not. - cmd = ['git', 'branch'] + # We can use the 'git branch -r' command. This returns all the remote branches for + # the current repo. + # The output consists of a list of lines of the form: + # origin/ + # From these we need to extract just the branch names to a list and then check if + # the specified dst exists in that list + branches = [] + cmd = "git branch -r" _, output = run_cmd_with_output(cmd, exit_on_failure=True) - if not dst in output: + branches = [line.split('/')[1] for line in output.split('\n') if 'origin' in line and not '->' in line] + + if not dst in branches: # OOB branch does not exist thus create it, first ensuring we are on # the src branch and then check it out - for cmd in [['git', 'checkout', src], - ['git', 'checkout', '-b', dst], - ['git', 'push', '-u', 'origin', dst]]: + for cmd in ["git checkout " + str(src), + "git checkout -b " + str(dst), + "git push -u origin " + str(dst)]: run_cmd(cmd, exit_on_failure=True) else: - cmd = ['git', 'checkout', dst] + cmd = "git checkout " + str(dst) run_cmd(cmd, exit_on_failure=True) def upgrade_example(github, example, tag, ref, user, src, dst, template): @@ -321,18 +339,18 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template): user = 'ARMmbed' ret = False - update_log.info("Updating example '%s'", example['name']) - update_log.debug("User: %s", user) - update_log.debug("Src branch: %s", (src or "None")) - update_log.debug("Dst branch: %s", (dst or "None")) + userlog.info("Updating example '%s'", example['name']) + userlog.debug("User: %s", user) + userlog.debug("Src branch: %s", (src or "None")) + userlog.debug("Dst branch: %s", (dst or "None")) cwd = os.getcwd() update_repo = "https://github.com/" + user + '/' + example['name'] - update_log.debug("Update repository: %s", update_repo) + userlog.debug("Update repository: %s", update_repo) # Clone the example repo - clone_cmd = ['git', 'clone', update_repo] + clone_cmd = "git clone " + str(update_repo) return_code = run_cmd(clone_cmd) if not return_code: @@ -353,16 +371,13 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template): os.chdir(cwd) return False - # Setup the default commit message - commit_message = 'Updating mbed-os to ' + tag - # Setup and run the commit command - commit_cmd = ['git', 'commit', '-m', commit_message] + commit_cmd = "git commit -m \"Updating mbed-os to " + tag + "\"" return_code = run_cmd(commit_cmd) if not return_code: # Setup and run the push command - push_cmd = ['git', 'push', 'origin'] + push_cmd = "git push origin" return_code = run_cmd(push_cmd) if not return_code: @@ -370,13 +385,13 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template): if user != 'ARMmbed': upstream_repo = 'ARMmbed/'+ example['name'] - update_log.debug("Upstream repository: %s", upstream_repo) + userlog.debug("Upstream repository: %s", upstream_repo) # Check access to mbed-os repo try: repo = github.get_repo(upstream_repo, False) except: - update_log.error("Upstream repo: %s, does not exist - skipping", upstream_repo) + userlog.error("Upstream repo: %s, does not exist - skipping", upstream_repo) return False jinja_loader = FileSystemLoader(template) @@ -391,15 +406,15 @@ def upgrade_example(github, example, tag, ref, user, src, dst, template): ret = True except GithubException as e: # Default to False - update_log.error("Pull request creation failed with error: %s", e) + userlog.error("Pull request creation failed with error: %s", e) else: ret = True else: - update_log.error("Git push command failed.") + userlog.error("Git push command failed.") else: - update_log.error("Git commit command failed.") + userlog.error("Git commit command failed.") else: - update_log.error("Git clone %s failed", update_repo) + userlog.error("Git clone %s failed", update_repo) os.chdir(cwd) return ret @@ -413,44 +428,73 @@ def create_work_directory(path): """ if os.path.exists(path): - update_log.info("'%s' directory already exists. Deleting...", path) + userlog.info("'%s' directory already exists. Deleting...", path) rmtree_readonly(path) os.makedirs(path) +def check_update_status(examples, github, tag): + """ Check the status of previously raised update pull requests + + Args: + examples - list of examples which should have had PRs raised against them. + github - github rest API instance + tag - release tag used for the update + + """ + + for example in examples: + + repo_name = ''.join(['ARMmbed/', example['name']]) + try: + repo = github.get_repo(repo_name, False) + + except Exception as exc: + text = "Cannot access: " + str(repo_name) + userlog.error(text) + userlog.exception(exc) + sys.exit(1) + + # Create the full repository filter component + org_str = ''.join(['repo:ARMmbed/', example['name']]) + filt = ' '.join([org_str, 'is:pr', tag]) + merged = False + + issues = github.search_issues(query=(filt)) + pr_list = [repo.get_pull(issue.number) for issue in issues] + + # Should only be one matching PR but just in case, go through paginated list + for pr in pr_list: + if pr.merged: + userlog.info("%s - '%s': MERGED", example['name'], pr.title) + elif pr.state == 'open': + userlog.info("%s - '%s': PENDING", example['name'], pr.title) + elif pr.state == 'closed': + userlog.info("%s - '%s': CLOSED NOT MERGED", example['name'], pr.title) + else: + userlog.error("%s: Cannot find a pull request for %s", example['name'], tag) + if __name__ == '__main__': parser = argparse.ArgumentParser(description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter) parser.add_argument('-c', '--config_file', help="Path to the configuration file (default is 'examples.json')", default='examples.json') parser.add_argument('-T', '--github_token', help="GitHub token for secure access") - parser.add_argument('-l', '--log-level', - help="Level for providing logging output", - default='INFO') exclusive = parser.add_mutually_exclusive_group(required=True) exclusive.add_argument('-f', '--fork', help="Update a fork", action='store_true') exclusive.add_argument('-b', '--branch', help="Update a branch", action='store_true') + exclusive.add_argument('-s', '--status', help="Show examples update status", action='store_true') args = parser.parse_args() - default = getattr(logging, 'INFO') - level = getattr(logging, args.log_level.upper(), default) - - # Set logging level - logging.basicConfig(level=level) - - update_log = logging.getLogger("Update") - # Load the config file with open(os.path.join(os.path.dirname(__file__), args.config_file)) as config: if not config: - update_log.error("Failed to load config file '%s'", args.config_file) + userlog.error("Failed to load config file '%s'", args.config_file) sys.exit(1) json_data = json.load(config) - # Create working directory - create_work_directory('examples') github = Github(args.github_token) config = json_data['update-config'] @@ -460,6 +504,15 @@ def create_work_directory(path): src = "master" dst = None + if args.status: + + # This option should only be called after an update has been performed + check_update_status(json_data['examples'], github, tag) + exit(0) + + # Create working directory + create_work_directory('examples') + if args.fork: user = config['via-fork']['github-user'] elif args.branch: @@ -470,11 +523,11 @@ def create_work_directory(path): exit(1) # Get the github sha corresponding to the specified mbed-os tag - cmd = ['git', 'rev-list', '-1', tag] + cmd = "git rev-list -1 " + tag return_code, ref = run_cmd_with_output(cmd) if return_code: - update_log.error("Could not obtain SHA for tag: %s", tag) + userlog.error("Could not obtain SHA for tag: %s", tag) sys.exit(1) # Loop through the examples @@ -499,11 +552,11 @@ def create_work_directory(path): os.chdir('../') # Finish the script and report the results - update_log.info("Finished updating examples") + userlog.info("Finished updating examples") if successes: for success in successes: - update_log.info(" SUCCEEDED: %s", success) + userlog.info(" SUCCEEDED: %s", success) if failures: for fail in failures: - update_log.info(" FAILED: %s", fail) + userlog.info(" FAILED: %s", fail) diff --git a/tools/test/toolchains/arm_support_test.py b/tools/test/toolchains/arm_support_test.py new file mode 100644 index 00000000000..f26935a8f7d --- /dev/null +++ b/tools/test/toolchains/arm_support_test.py @@ -0,0 +1,65 @@ +"""Tests for the arm toolchain supported checks""" +import sys +import os +from string import printable +from copy import deepcopy +from mock import MagicMock, patch +from hypothesis import given, settings +from hypothesis.strategies import text, lists, sampled_from + +ROOT = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "..", + "..")) +sys.path.insert(0, ROOT) + +from tools.toolchains.arm import ARM_STD, ARM_MICRO, ARMC6 +from tools.utils import NotSupportedException + +ARMC5_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", + "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"] +ARMC6_CORES = ARMC5_CORES + ["Cortex-M23", "Cortex-M23-NS", + "Cortex-M33", "CortexM33-NS"] + +CORE_SUF_ALPHA = ["MDFNS02347-+"] + +@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])), + text(alphabet=CORE_SUF_ALPHA)) +def test_arm_std(supported_toolchains, core): + mock_target = MagicMock() + mock_target.core = "Cortex-" + core + mock_target.supported_toolchains = supported_toolchains + try: + ARM_STD(mock_target) + assert "ARM" in supported_toolchains + assert mock_target.core in ARMC5_CORES + except NotSupportedException: + assert "ARM" not in supported_toolchains or mock_target.core not in ARMC5_CORES + + +@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])), + text(alphabet=CORE_SUF_ALPHA)) +def test_arm_micro(supported_toolchains, core): + mock_target = MagicMock() + mock_target.core = "Cortex-" + core + mock_target.supported_toolchains = supported_toolchains + try: + ARM_MICRO(mock_target) + assert "ARM" in supported_toolchains or "uARM" in supported_toolchains + assert mock_target.core in ARMC5_CORES + except NotSupportedException: + assert ("ARM" not in supported_toolchains and "uARM" not in supported_toolchains)\ + or mock_target.core not in ARMC5_CORES + + +@given(lists(sampled_from(["ARM", "uARM", "GCC_ARM", "ARMC6", "IAR", "GARBAGE"])), + text(alphabet=CORE_SUF_ALPHA)) +def test_armc6(supported_toolchains, core): + mock_target = MagicMock() + mock_target.core = "Cortex-" + core + mock_target.supported_toolchains = supported_toolchains + try: + ARMC6(mock_target) + assert "ARM" in supported_toolchains or "ARMC6" in supported_toolchains + assert mock_target.core in ARMC6_CORES + except NotSupportedException: + assert ("ARM" not in supported_toolchains and "ARMC6" not in supported_toolchains)\ + or mock_target.core not in ARMC6_CORES diff --git a/tools/test_api.py b/tools/test_api.py index 7bebb8da755..2e7d60a275f 100644 --- a/tools/test_api.py +++ b/tools/test_api.py @@ -1644,11 +1644,10 @@ def detect_database_verbose(db_url): def get_module_avail(module_name): - """ This function returns True if module_name is already impored module + """ This function returns True if module_name is already imported module """ return module_name in sys.modules.keys() - def get_autodetected_MUTS_list(platform_name_filter=None): oldError = None if os.name == 'nt': @@ -2004,7 +2003,7 @@ def get_test_config(config_name, target_name): """Finds the path to a test configuration file config_name: path to a custom configuration file OR mbed OS interface "ethernet, wifi_odin, etc" target_name: name of target to determing if mbed OS interface given is valid - returns path to config, boolean of whether it is a module or mbed OS interface + returns path to config, will return None if no valid config is found """ # If they passed in a full path if exists(config_name): diff --git a/tools/test_configs/RealtekInterface.json b/tools/test_configs/RealtekInterface.json new file mode 100644 index 00000000000..ad4a9ef31b7 --- /dev/null +++ b/tools/test_configs/RealtekInterface.json @@ -0,0 +1,27 @@ +{ + "config": { + "header-file": { + "help" : "String for including your driver header file", + "value" : "\"RTWInterface.h\"" + }, + "object-construction" : { + "value" : "new RTWInterface()" + }, + "connect-statement" : { + "help" : "Must use 'net' variable name, replace WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL with your WiFi settings", + "value" : "((RTWInterface *)net)->connect(WIFI_SSID, WIFI_PASSWORD, WIFI_SECURITY, WIFI_CHANNEL)" + }, + "echo-server-addr" : { + "help" : "IP address of echo server", + "value" : "\"195.34.89.241\"" + }, + "echo-server-port" : { + "help" : "Port of echo server", + "value" : "7" + }, + "tcp-echo-prefix" : { + "help" : "Some servers send a prefix before echoed message", + "value" : "\"Realtek Ameba TCP/UDP test service\\n\"" + } + } +} diff --git a/tools/test_configs/__init__.py b/tools/test_configs/__init__.py index 85ea5c92aee..90666baf248 100644 --- a/tools/test_configs/__init__.py +++ b/tools/test_configs/__init__.py @@ -1,6 +1,7 @@ from os.path import dirname, abspath, join from tools.utils import json_file_to_dict +from tools.targets import TARGET_MAP CONFIG_DIR = dirname(abspath(__file__)) CONFIG_MAP = json_file_to_dict(join(CONFIG_DIR, "config_paths.json")) @@ -9,6 +10,8 @@ def get_valid_configs(target_name): if target_name in TARGET_CONFIGS: target_config = TARGET_CONFIGS[target_name] + elif (target_name in TARGET_MAP and 'LWIP' in TARGET_MAP[target_name].features): + target_config = { "default_test_configuration": "ETHERNET", "test_configurations": ["ETHERNET"] } else: return {} @@ -31,5 +34,7 @@ def get_default_config(target_name): if config_name == "NONE": return None return join(CONFIG_DIR, CONFIG_MAP[config_name]) + elif (target_name in TARGET_MAP and 'LWIP' in TARGET_MAP[target_name].features): + return join(CONFIG_DIR, CONFIG_MAP["ETHERNET"]) else: return None diff --git a/tools/test_configs/config_paths.json b/tools/test_configs/config_paths.json index c543176906c..098c9442c32 100644 --- a/tools/test_configs/config_paths.json +++ b/tools/test_configs/config_paths.json @@ -1,5 +1,6 @@ { "ETHERNET" : "EthernetInterface.json", "ODIN_WIFI" : "OdinInterface.json", - "ODIN_ETHERNET" : "Odin_EthernetInterface.json" + "ODIN_ETHERNET" : "Odin_EthernetInterface.json", + "REALTEK_WIFI" : "RealtekInterface.json" } diff --git a/tools/test_configs/target_configs.json b/tools/test_configs/target_configs.json index eaff8b55b99..528889622a3 100644 --- a/tools/test_configs/target_configs.json +++ b/tools/test_configs/target_configs.json @@ -3,8 +3,8 @@ "default_test_configuration": "NONE", "test_configurations": ["ODIN_WIFI", "ODIN_ETHERNET"] }, - "K64F": { - "default_test_configuration": "ETHERNET", - "test_configurations": ["ETHERNET"] + "REALTEK_RTL8195AM": { + "default_test_configuration": "NONE", + "test_configurations": ["REALTEK_WIFI"] } } diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index e7423b09a6b..0df502303f0 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -615,7 +615,8 @@ def add_ignore_patterns(self, root, base_path, patterns): self.ignore_patterns.extend(normcase(p) for p in patterns) else: self.ignore_patterns.extend(normcase(join(real_base, pat)) for pat in patterns) - self._ignore_regex = re.compile("|".join(fnmatch.translate(p) for p in self.ignore_patterns)) + if self.ignore_patterns: + self._ignore_regex = re.compile("|".join(fnmatch.translate(p) for p in self.ignore_patterns)) # Create a Resources object from the path pointed to by *path* by either traversing a # a directory structure, when *path* is a directory, or adding *path* to the resources, diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 08b3179dab3..4cc46aa0c2b 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -33,6 +33,8 @@ class ARM(mbedToolchain): INDEX_PATTERN = re.compile('(?P\s*)\^') DEP_PATTERN = re.compile('\S+:\s(?P.+)\n') SHEBANG = "#! armcc -E" + SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", + "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD"] @staticmethod def check_executable(): @@ -48,9 +50,9 @@ def __init__(self, target, notify=None, macros=None, build_dir=build_dir, extra_verbose=extra_verbose, build_profile=build_profile) - - if "ARM" not in target.supported_toolchains: - raise NotSupportedException("ARM compiler support is required for ARM build") + if target.core not in self.SUPPORTED_CORES: + raise NotSupportedException( + "this compiler does not support the core %s" % target.core) if target.core == "Cortex-M0+": cpu = "Cortex-M0" @@ -265,19 +267,42 @@ def redirect_symbol(source, sync, build_dir): class ARM_STD(ARM): - pass + def __init__(self, target, notify=None, macros=None, + silent=False, extra_verbose=False, build_profile=None, + build_dir=None): + ARM.__init__(self, target, notify, macros, silent, + build_dir=build_dir, extra_verbose=extra_verbose, + build_profile=build_profile) + if "ARM" not in target.supported_toolchains: + raise NotSupportedException("ARM compiler support is required for ARM build") + class ARM_MICRO(ARM): PATCHED_LIBRARY = False + def __init__(self, target, notify=None, macros=None, + silent=False, extra_verbose=False, build_profile=None, + build_dir=None): + ARM.__init__(self, target, notify, macros, silent, + build_dir=build_dir, extra_verbose=extra_verbose, + build_profile=build_profile) + if not set(("ARM", "uARM")).intersection(set(target.supported_toolchains)): + raise NotSupportedException("ARM/uARM compiler support is required for ARM build") class ARMC6(ARM_STD): SHEBANG = "#! armclang -E --target=arm-arm-none-eabi -x c" + SUPPORTED_CORES = ["Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", + "Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD", + "Cortex-M23", "Cortex-M23-NS", "Cortex-M33", + "CortexM33-NS"] @staticmethod def check_executable(): return mbedToolchain.generic_check_executable("ARMC6", "armclang", 1) def __init__(self, target, *args, **kwargs): mbedToolchain.__init__(self, target, *args, **kwargs) + if target.core not in self.SUPPORTED_CORES: + raise NotSupportedException( + "this compiler does not support the core %s" % target.core) if not set(("ARM", "ARMC6")).intersection(set(target.supported_toolchains)): raise NotSupportedException("ARM/ARMC6 compiler support is required for ARMC6 build") diff --git a/tools/utils.py b/tools/utils.py index 68c9631ba16..7ab791f7f7c 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -199,7 +199,7 @@ def delete_dir_files(directory): for element in listdir(directory): to_remove = join(directory, element) if not isdir(to_remove): - remove(file) + remove(to_remove) def get_caller_name(steps=2):