diff --git a/README.md b/README.md
index bd7ad99c65b..9ce262d16f5 100644
--- a/README.md
+++ b/README.md
@@ -24,6 +24,7 @@ NXP:
* [LPC1768](http://mbed.org/handbook/mbed-NXP-LPC1768) (Cortex-M3)
* [LPC11U24](http://mbed.org/handbook/mbed-NXP-LPC11U24) (Cortex-M0)
* LPC2368 (ARM7TDMI-S)
+* LPC810 (Cortex-M0+)
* LPC812 (Cortex-M0+)
* LPC4088 (Cortex-M4)
* LPC4330 (Cortex-M4 + Cortex-M0)
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/LPC8xx.h
new file mode 100644
index 00000000000..4dcffe44967
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/LPC8xx.h
@@ -0,0 +1,687 @@
+/****************************************************************************
+ * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
+ * Project: NXP LPC8xx software example
+ *
+ * Description:
+ * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
+ * NXP LPC800 Device Series
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors'
+ * relevant copyright in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers. This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+****************************************************************************/
+#ifndef __LPC8xx_H__
+#define __LPC8xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
+ This file defines all structures and symbols for LPC8xx:
+ - Registers and bitfields
+ - peripheral base address
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
+ Configuration of the Cortex-M0+ Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** LPC8xx Specific Interrupt Numbers ********************************************************/
+ SPI0_IRQn = 0, /*!< SPI0 */
+ SPI1_IRQn = 1, /*!< SPI1 */
+ Reserved0_IRQn = 2, /*!< Reserved Interrupt */
+ UART0_IRQn = 3, /*!< USART0 */
+ UART1_IRQn = 4, /*!< USART1 */
+ UART2_IRQn = 5, /*!< USART2 */
+ Reserved1_IRQn = 6, /*!< Reserved Interrupt */
+ Reserved2_IRQn = 7, /*!< Reserved Interrupt */
+ I2C_IRQn = 8, /*!< I2C */
+ SCT_IRQn = 9, /*!< SCT */
+ MRT_IRQn = 10, /*!< MRT */
+ CMP_IRQn = 11, /*!< CMP */
+ WDT_IRQn = 12, /*!< WDT */
+ BOD_IRQn = 13, /*!< BOD */
+ Reserved3_IRQn = 14, /*!< Reserved Interrupt */
+ WKT_IRQn = 15, /*!< WKT Interrupt */
+ Reserved4_IRQn = 16, /*!< Reserved Interrupt */
+ Reserved5_IRQn = 17, /*!< Reserved Interrupt */
+ Reserved6_IRQn = 18, /*!< Reserved Interrupt */
+ Reserved7_IRQn = 19, /*!< Reserved Interrupt */
+ Reserved8_IRQn = 20, /*!< Reserved Interrupt */
+ Reserved9_IRQn = 21, /*!< Reserved Interrupt */
+ Reserved10_IRQn = 22, /*!< Reserved Interrupt */
+ Reserved11_IRQn = 23, /*!< Reserved Interrupt */
+ PININT0_IRQn = 24, /*!< External Interrupt 0 */
+ PININT1_IRQn = 25, /*!< External Interrupt 1 */
+ PININT2_IRQn = 26, /*!< External Interrupt 2 */
+ PININT3_IRQn = 27, /*!< External Interrupt 3 */
+ PININT4_IRQn = 28, /*!< External Interrupt 4 */
+ PININT5_IRQn = 29, /*!< External Interrupt 5 */
+ PININT6_IRQn = 30, /*!< External Interrupt 6 */
+ PININT7_IRQn = 31, /*!< External Interrupt 7 */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC8xx_CMSIS */
+
+
+#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
+#include "system_LPC8xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
+ __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
+ uint32_t RESERVED0[4];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+ uint32_t RESERVED1[2];
+ __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+ uint32_t RESERVED3[10];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
+ uint32_t RESERVED5[4];
+ __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
+ uint32_t RESERVED6[18];
+
+ __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+ uint32_t RESERVED7;
+ __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
+ __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
+ uint32_t RESERVED8[1];
+ __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
+ __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+ uint32_t RESERVED9[12];
+ __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
+ uint32_t RESERVED10[6];
+ __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
+ __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
+ __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
+ uint32_t RESERVED11[27];
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+ uint32_t RESERVED12[3];
+ __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
+ uint32_t RESERVED13[6];
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+ uint32_t RESERVED14[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_SYSCON */
+
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
+ */
+
+typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
+ __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
+ __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
+ __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
+ __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
+ __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
+ __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
+ __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
+ __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
+ __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
+ __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
+ __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
+ __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
+ __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
+ __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
+ __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
+ __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
+ __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
+ __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
+ __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC8xx_IOCON */
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
+ */
+typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
+ __I uint32_t RESERVED0[4];
+ __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
+ __I uint32_t RESERVED1[3];
+ __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
+ __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
+ __I uint32_t RESERVED2;
+ __I uint32_t FMSW0;
+} LPC_FLASHCTRL_TypeDef;
+/*@}*/ /* end of group LPC8xx_FLASHCTRL */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+ __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC8xx_PMU */
+
+
+/*------------- Switch Matrix Port --------------------------*/
+/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
+ @{
+*/
+typedef struct
+{
+ union {
+ __IO uint32_t PINASSIGN[9];
+ struct {
+ __IO uint32_t PINASSIGN0;
+ __IO uint32_t PINASSIGN1;
+ __IO uint32_t PINASSIGN2;
+ __IO uint32_t PINASSIGN3;
+ __IO uint32_t PINASSIGN4;
+ __IO uint32_t PINASSIGN5;
+ __IO uint32_t PINASSIGN6;
+ __IO uint32_t PINASSIGN7;
+ __IO uint32_t PINASSIGN8;
+ };
+ };
+ __I uint32_t RESERVED0[103];
+ __IO uint32_t PINENABLE0;
+} LPC_SWM_TypeDef;
+/*@}*/ /* end of group LPC8xx_SWM */
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO_PORT -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
+ */
+
+typedef struct {
+ __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
+ __I uint16_t RESERVED0[2039];
+ __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
+ uint32_t RESERVED1[1006];
+ __IO uint32_t DIR0; /* 0x2000 */
+ uint32_t RESERVED2[31];
+ __IO uint32_t MASK0; /* 0x2080 */
+ uint32_t RESERVED3[31];
+ __IO uint32_t PIN0; /* 0x2100 */
+ uint32_t RESERVED4[31];
+ __IO uint32_t MPIN0; /* 0x2180 */
+ uint32_t RESERVED5[31];
+ __IO uint32_t SET0; /* 0x2200 */
+ uint32_t RESERVED6[31];
+ __O uint32_t CLR0; /* 0x2280 */
+ uint32_t RESERVED7[31];
+ __O uint32_t NOT0; /* 0x2300 */
+
+} LPC_GPIO_PORT_TypeDef;
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- PIN_INT -----
+// ------------------------------------------------------------------------------------------------
+
+/**
+ * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
+ */
+
+typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
+ __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
+ __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
+ __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
+ __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
+ __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
+ __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
+ __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
+ __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
+ __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
+ __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
+ __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
+ __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
+} LPC_PIN_INT_TypeDef;
+
+
+/*------------- CRC Engine (CRC) -----------------------------------------*/
+/** @addtogroup LPC8xx_CRC
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MODE;
+ __IO uint32_t SEED;
+ union {
+ __I uint32_t SUM;
+ __O uint32_t WR_DATA_DWORD;
+ __O uint16_t WR_DATA_WORD;
+ uint16_t RESERVED_WORD;
+ __O uint8_t WR_DATA_BYTE;
+ uint8_t RESERVED_BYTE[3];
+ };
+} LPC_CRC_TypeDef;
+/*@}*/ /* end of group LPC8xx_CRC */
+
+/*------------- Comparator (CMP) --------------------------------------------------*/
+/** @addtogroup LPC8xx_CMP LPC8xx Comparator
+ @{
+*/
+typedef struct { /*!< (@ 0x40024000) CMP Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
+ __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
+} LPC_CMP_TypeDef;
+/*@}*/ /* end of group LPC8xx_CMP */
+
+
+/*------------- Wakeup Timer (WKT) --------------------------------------------------*/
+/** @addtogroup LPC8xx_WKT
+ @{
+*/
+typedef struct { /*!< (@ 0x40028000) WKT Structure */
+ __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
+ uint32_t Reserved[2];
+ __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
+} LPC_WKT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WKT */
+
+
+/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
+typedef struct {
+__IO uint32_t INTVAL;
+__IO uint32_t TIMER;
+__IO uint32_t CTRL;
+__IO uint32_t STAT;
+} MRT_Channel_cfg_Type;
+
+typedef struct {
+ MRT_Channel_cfg_Type Channel[4];
+ uint32_t Reserved0[1];
+ __IO uint32_t IDLE_CH;
+ __IO uint32_t IRQ_FLAG;
+} LPC_MRT_TypeDef;
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
+/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+/**
+ * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
+ */
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t CTRL;
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR; /* 0x10 */
+ __I uint32_t RXDATA;
+ __I uint32_t RXDATA_STAT;
+ __IO uint32_t TXDATA;
+ __IO uint32_t BRG; /* 0x20 */
+ __IO uint32_t INTSTAT;
+} LPC_USART_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_USART */
+
+
+/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
+/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t DLY;
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR; /* 0x10 */
+ __I uint32_t RXDAT;
+ __IO uint32_t TXDATCTL;
+ __IO uint32_t TXDAT;
+ __IO uint32_t TXCTRL; /* 0x20 */
+ __IO uint32_t DIV;
+ __I uint32_t INTSTAT;
+} LPC_SPI_TypeDef;
+/*@}*/ /* end of group LPC8xx_SPI */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC8xx_I2C I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CFG; /* 0x00 */
+ __IO uint32_t STAT;
+ __IO uint32_t INTENSET;
+ __O uint32_t INTENCLR;
+ __IO uint32_t TIMEOUT; /* 0x10 */
+ __IO uint32_t DIV;
+ __IO uint32_t INTSTAT;
+ uint32_t Reserved0[1];
+ __IO uint32_t MSTCTL; /* 0x20 */
+ __IO uint32_t MSTTIME;
+ __IO uint32_t MSTDAT;
+ uint32_t Reserved1[5];
+ __IO uint32_t SLVCTL; /* 0x40 */
+ __IO uint32_t SLVDAT;
+ __IO uint32_t SLVADR0;
+ __IO uint32_t SLVADR1;
+ __IO uint32_t SLVADR2; /* 0x50 */
+ __IO uint32_t SLVADR3;
+ __IO uint32_t SLVQUAL0;
+ uint32_t Reserved2[9];
+ __I uint32_t MONRXDAT; /* 0x80 */
+} LPC_I2C_TypeDef;
+
+/*@}*/ /* end of group LPC8xx_I2C */
+
+/**
+ * @brief State Configurable Timer (SCT) (SCT)
+ */
+
+/**
+ * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
+ */
+
+#define CONFIG_SCT_nEV (6) /* Number of events */
+#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
+#define CONFIG_SCT_nOU (4) /* Number of outputs */
+
+typedef struct
+{
+ __IO uint32_t CONFIG; /* 0x000 Configuration Register */
+ union {
+ __IO uint32_t CTRL_U; /* 0x004 Control Register */
+ struct {
+ __IO uint16_t CTRL_L; /* 0x004 low control register */
+ __IO uint16_t CTRL_H; /* 0x006 high control register */
+ };
+ };
+ __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
+ __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
+ __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
+ __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
+ __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
+ __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
+ __IO uint16_t START_L; /* 0x014 start register for counter L */
+ __IO uint16_t START_H; /* 0x016 start register for counter H */
+ uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
+ union {
+ __IO uint32_t COUNT_U; /* 0x040 counter register */
+ struct {
+ __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
+ __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
+ };
+ };
+ __IO uint16_t STATE_L; /* 0x044 state register for counter L */
+ __IO uint16_t STATE_H; /* 0x046 state register for counter H */
+ __I uint32_t INPUT; /* 0x048 input register */
+ __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
+ __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
+ __IO uint32_t OUTPUT; /* 0x050 output register */
+ __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
+ __IO uint32_t RES; /* 0x058 conflict resolution register */
+ uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
+ __IO uint32_t EVEN; /* 0x0F0 event enable register */
+ __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
+ __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
+ __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
+
+ union {
+ __IO union { /* 0x100-... Match / Capture value */
+ uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCH[i].L Access to L value */
+ uint16_t H; /* SCTMATCH[i].H Access to H value */
+ };
+ } MATCH[CONFIG_SCT_nRG];
+ __I union {
+ uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAP[i].L Access to H value */
+ uint16_t H; /* SCTCAP[i].H Access to H value */
+ };
+ } CAP[CONFIG_SCT_nRG];
+ };
+
+
+ uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
+
+ union {
+ __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
+ __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
+ };
+ uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
+ union {
+ __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
+ __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
+ };
+
+ uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
+
+
+ union {
+ __IO union { /* 0x200-... Match Reload / Capture Control value */
+ uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTMATCHREL[i].L Access to L value */
+ uint16_t H; /* SCTMATCHREL[i].H Access to H value */
+ };
+ } MATCHREL[CONFIG_SCT_nRG];
+ __IO union {
+ uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
+ struct {
+ uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
+ uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
+ };
+ } CAPCTRL[CONFIG_SCT_nRG];
+ };
+
+ uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
+
+ union {
+ __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
+ __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
+ };
+ uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
+ union {
+ __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
+ __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
+ };
+ uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
+
+ __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
+ uint32_t STATE; /* Event State Register */
+ uint32_t CTRL; /* Event Control Register */
+ } EVENT[CONFIG_SCT_nEV];
+
+ uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
+
+ __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
+ uint32_t SET; /* Output n Set Register */
+ uint32_t CLR; /* Output n Clear Register */
+ } OUT[CONFIG_SCT_nOU];
+
+ uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
+
+ __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
+
+} LPC_SCT_TypeDef;
+/*@}*/ /* end of group LPC8xx_SCT */
+
+
+/*------------- Watchdog Timer (WWDT) -----------------------------------------*/
+/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+ __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
+ __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
+ uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
+ __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
+ __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
+} LPC_WWDT_TypeDef;
+/*@}*/ /* end of group LPC8xx_WDT */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_ROM_BASE (0x1FFF0000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
+#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
+
+#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
+#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
+#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
+#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
+#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
+#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
+
+/* AHB peripherals */
+#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
+
+#define LPC_GPIO_PORT_BASE (0xA0000000)
+#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
+#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
+
+
+#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
+#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
+
+#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
+#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
+#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
+#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
+#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
+
+#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
+#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
+
+#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
+#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC8xx_H__ */
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct
new file mode 100644
index 00000000000..84f5f32f5e4
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/LPC810.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x1000 { ; load region size_region (4k)
+ ER_IROM1 0x00000000 0x1000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 0xC0
+ ; 1KB(0x0400) - 0xC0 = 0x340
+ RW_IRAM1 (0x10000000+0xC0) (0x400-0xC0) {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
new file mode 100644
index 00000000000..816264f05b5
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s
@@ -0,0 +1,211 @@
+;/*****************************************************************************
+; * @file: startup_LPC8xx.s
+; * @purpose: CMSIS Cortex-M0+ Core Device Startup File
+; * for the NXP LPC8xx Device Series
+; * @version: V1.0
+; * @date: 16. Aug. 2012
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2012 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x10000400
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD SPI0_IRQHandler ; SPI0 controller
+ DCD SPI1_IRQHandler ; SPI1 controller
+ DCD 0 ; Reserved
+ DCD UART0_IRQHandler ; UART0
+ DCD UART1_IRQHandler ; UART1
+ DCD UART2_IRQHandler ; UART2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD I2C_IRQHandler ; I2C controller
+ DCD SCT_IRQHandler ; Smart Counter Timer
+ DCD MRT_IRQHandler ; Multi-Rate Timer
+ DCD CMP_IRQHandler ; Comparator
+ DCD WDT_IRQHandler ; PIO1 (0:11)
+ DCD BOD_IRQHandler ; Brown Out Detect
+ DCD 0 ; Reserved
+ DCD WKT_IRQHandler ; Wakeup timer
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PININT0_IRQHandler ; PIO INT0
+ DCD PININT1_IRQHandler ; PIO INT1
+ DCD PININT2_IRQHandler ; PIO INT2
+ DCD PININT3_IRQHandler ; PIO INT3
+ DCD PININT4_IRQHandler ; PIO INT4
+ DCD PININT5_IRQHandler ; PIO INT5
+ DCD PININT6_IRQHandler ; PIO INT6
+ DCD PININT7_IRQHandler ; PIO INT7
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled
+; for particular peripheral.
+;NMI_Handler PROC
+; EXPORT NMI_Handler [WEAK]
+; B .
+; ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT NMI_Handler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT MRT_IRQHandler [WEAK]
+ EXPORT CMP_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+
+ EXPORT WKT_IRQHandler [WEAK]
+
+ EXPORT PININT0_IRQHandler [WEAK]
+ EXPORT PININT1_IRQHandler [WEAK]
+ EXPORT PININT2_IRQHandler [WEAK]
+ EXPORT PININT3_IRQHandler [WEAK]
+ EXPORT PININT4_IRQHandler [WEAK]
+ EXPORT PININT5_IRQHandler [WEAK]
+ EXPORT PININT6_IRQHandler [WEAK]
+ EXPORT PININT7_IRQHandler [WEAK]
+
+NMI_Handler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+I2C_IRQHandler
+SCT_IRQHandler
+MRT_IRQHandler
+CMP_IRQHandler
+WDT_IRQHandler
+BOD_IRQHandler
+WKT_IRQHandler
+PININT0_IRQHandler
+PININT1_IRQHandler
+PININT2_IRQHandler
+PININT3_IRQHandler
+PININT4_IRQHandler
+PININT5_IRQHandler
+PININT6_IRQHandler
+PININT7_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+ END
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 00000000000..2f1024ace8b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+#include
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis.h
new file mode 100644
index 00000000000..12302cc3ade
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC8xx specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "LPC8xx.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.c
new file mode 100644
index 00000000000..6b8912505b1
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.h
new file mode 100644
index 00000000000..6acdca9efdd
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/cmsis_nvic.h
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.c
new file mode 100644
index 00000000000..24e656353be
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.c
@@ -0,0 +1,367 @@
+/******************************************************************************
+ * @file: system_LPC8xx.c
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#include
+#include "LPC8xx.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- Clock Configuration ----------------------------------
+//
+// Clock Configuration
+// System Oscillator Control Register (SYSOSCCTRL)
+// BYPASS: System Oscillator Bypass Enable
+// If enabled then PLL input (sys_osc_clk) is fed
+// directly from XTALIN and XTALOUT pins.
+// FREQRANGE: System Oscillator Frequency Range
+// Determines frequency range for Low-power oscillator.
+// <0=> 1 - 20 MHz
+// <1=> 15 - 25 MHz
+//
+//
+// Watchdog Oscillator Control Register (WDTOSCCTRL)
+// DIVSEL: Select Divider for Fclkana
+// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
+// <0-31>
+// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
+// <0=> Undefined
+// <1=> 0.5 MHz
+// <2=> 0.8 MHz
+// <3=> 1.1 MHz
+// <4=> 1.4 MHz
+// <5=> 1.6 MHz
+// <6=> 1.8 MHz
+// <7=> 2.0 MHz
+// <8=> 2.2 MHz
+// <9=> 2.4 MHz
+// <10=> 2.6 MHz
+// <11=> 2.7 MHz
+// <12=> 2.9 MHz
+// <13=> 3.1 MHz
+// <14=> 3.2 MHz
+// <15=> 3.4 MHz
+//
+//
+// System PLL Control Register (SYSPLLCTRL)
+// F_clkout = M * F_clkin = F_CCO / (2 * P)
+// F_clkin must be in the range of 10 MHz to 25 MHz
+// F_CCO must be in the range of 156 MHz to 320 MHz
+// MSEL: Feedback Divider Selection
+// M = MSEL + 1
+// <0-31>
+// PSEL: Post Divider Selection
+// <0=> P = 1
+// <1=> P = 2
+// <2=> P = 4
+// <3=> P = 8
+//
+//
+// System PLL Clock Source Select Register (SYSPLLCLKSEL)
+// SEL: System PLL Clock Source
+// <0=> IRC Oscillator
+// <1=> System Oscillator
+// <2=> Reserved
+// <3=> CLKIN pin
+//
+//
+// Main Clock Source Select Register (MAINCLKSEL)
+// SEL: Clock Source for Main Clock
+// <0=> IRC Oscillator
+// <1=> Input Clock to System PLL
+// <2=> WDT Oscillator
+// <3=> System PLL Clock Out
+//
+//
+// System AHB Clock Divider Register (SYSAHBCLKDIV)
+// DIV: System AHB Clock Divider
+// Divides main clock to provide system clock to core, memories, and peripherals.
+// 0 = is disabled
+// <0-255>
+//
+//
+*/
+#define CLOCK_SETUP 1
+#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
+#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
+#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
+#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
+#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+
+/*
+//-------- <<< end of configuration section >>> ------------------------------
+*/
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
+ #error "SYSOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
+ #error "WDTOSCCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3))
+ #error "SYSPLLCLKSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
+ #error "SYSPLLCTRL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
+ #error "MAINCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
+ #error "SYSAHBCLKDIV: Value out of range!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (12000000UL) /* Oscillator frequency */
+#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
+#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
+#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */
+
+
+#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
+#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
+
+#if (CLOCK_SETUP) /* Clock Setup */
+ #if (__FREQSEL == 0)
+ #define __WDT_OSC_CLK ( 0) /* undefined */
+ #elif (__FREQSEL == 1)
+ #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
+ #elif (__FREQSEL == 2)
+ #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
+ #elif (__FREQSEL == 3)
+ #define __WDT_OSC_CLK (1100000 / __DIVSEL)
+ #elif (__FREQSEL == 4)
+ #define __WDT_OSC_CLK (1400000 / __DIVSEL)
+ #elif (__FREQSEL == 5)
+ #define __WDT_OSC_CLK (1600000 / __DIVSEL)
+ #elif (__FREQSEL == 6)
+ #define __WDT_OSC_CLK (1800000 / __DIVSEL)
+ #elif (__FREQSEL == 7)
+ #define __WDT_OSC_CLK (2000000 / __DIVSEL)
+ #elif (__FREQSEL == 8)
+ #define __WDT_OSC_CLK (2200000 / __DIVSEL)
+ #elif (__FREQSEL == 9)
+ #define __WDT_OSC_CLK (2400000 / __DIVSEL)
+ #elif (__FREQSEL == 10)
+ #define __WDT_OSC_CLK (2600000 / __DIVSEL)
+ #elif (__FREQSEL == 11)
+ #define __WDT_OSC_CLK (2700000 / __DIVSEL)
+ #elif (__FREQSEL == 12)
+ #define __WDT_OSC_CLK (2900000 / __DIVSEL)
+ #elif (__FREQSEL == 13)
+ #define __WDT_OSC_CLK (3100000 / __DIVSEL)
+ #elif (__FREQSEL == 14)
+ #define __WDT_OSC_CLK (3200000 / __DIVSEL)
+ #else
+ #define __WDT_OSC_CLK (3400000 / __DIVSEL)
+ #endif
+
+ /* sys_pllclkin calculation */
+ #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
+ #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
+ #elif ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ #define __SYS_PLLCLKIN (__CLKIN_CLK)
+ #else
+ #define __SYS_PLLCLKIN (0)
+ #endif
+
+ #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
+
+ /* main clock calculation */
+ #if ((MAINCLKSEL_Val & 0x03) == 0)
+ #define __MAIN_CLOCK (__IRC_OSC_CLK)
+ #elif ((MAINCLKSEL_Val & 0x03) == 1)
+ #define __MAIN_CLOCK (__SYS_PLLCLKIN)
+ #elif ((MAINCLKSEL_Val & 0x03) == 2)
+ #if (__FREQSEL == 0)
+ #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
+ #else
+ #define __MAIN_CLOCK (__WDT_OSC_CLK)
+ #endif
+ #elif ((MAINCLKSEL_Val & 0x03) == 3)
+ #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
+ #else
+ #define __MAIN_CLOCK (0)
+ #endif
+
+ #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
+
+#else
+ #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
+#endif // CLOCK_SETUP
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ uint32_t wdt_osc = 0;
+
+ /* Determine clock frequency according to clock register values */
+ switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
+ case 0: wdt_osc = 0; break;
+ case 1: wdt_osc = 500000; break;
+ case 2: wdt_osc = 800000; break;
+ case 3: wdt_osc = 1100000; break;
+ case 4: wdt_osc = 1400000; break;
+ case 5: wdt_osc = 1600000; break;
+ case 6: wdt_osc = 1800000; break;
+ case 7: wdt_osc = 2000000; break;
+ case 8: wdt_osc = 2200000; break;
+ case 9: wdt_osc = 2400000; break;
+ case 10: wdt_osc = 2600000; break;
+ case 11: wdt_osc = 2700000; break;
+ case 12: wdt_osc = 2900000; break;
+ case 13: wdt_osc = 3100000; break;
+ case 14: wdt_osc = 3200000; break;
+ case 15: wdt_osc = 3400000; break;
+ }
+ wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
+
+ switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* Input Clock to System PLL */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK;
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK;
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK;
+ break;
+ }
+ break;
+ case 2: /* WDT Oscillator */
+ SystemCoreClock = wdt_osc;
+ break;
+ case 3: /* System PLL Clock Out */
+ switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
+ case 0: /* Internal RC oscillator */
+ SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 1: /* System oscillator */
+ SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ case 2: /* Reserved */
+ SystemCoreClock = 0;
+ break;
+ case 3: /* CLKIN pin */
+ SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ break;
+ }
+ break;
+ }
+
+ SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void) {
+ volatile uint32_t i;
+
+ /* System clock to the IOCON & the SWM need to be enabled or
+ most of the I/O related peripherals won't work. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) );
+
+#if (CLOCK_SETUP) /* Clock Setup */
+
+#if ((SYSPLLCLKSEL_Val & 0x03) == 1)
+ LPC_IOCON->PIO0_8 &= ~(0x3 << 3);
+ LPC_IOCON->PIO0_9 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x3 << 4);
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */
+ LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+#if ((SYSPLLCLKSEL_Val & 0x03) == 3)
+ LPC_IOCON->PIO0_1 &= ~(0x3 << 3);
+ LPC_SWM->PINENABLE0 &= ~(0x1 << 7);
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
+ LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
+ while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
+#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
+ LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */
+ while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
+#endif
+
+#if (((MAINCLKSEL_Val & 0x03) == 2) )
+ LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
+ LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */
+ for (i = 0; i < 200; i++) __NOP();
+#endif
+
+ LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
+ LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
+ while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
+
+ LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
+#endif
+}
diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.h b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.h
new file mode 100644
index 00000000000..f559e944c6c
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC810/system_LPC8xx.h
@@ -0,0 +1,62 @@
+/******************************************************************************
+ * @file: system_LPC8xx.h
+ * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File
+ * for the NXP LPC8xx Device Series
+ * @version: V1.0
+ * @date: 16. Aug. 2012
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2012 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M0+
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC8xx_H
+#define __SYSTEM_LPC8xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC8xx_H */
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PeripheralNames.h
new file mode 100644
index 00000000000..988c1cb898b
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PeripheralNames.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PinNames.h
new file mode 100644
index 00000000000..c651b1e56ed
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PinNames.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+ P0_0 = 0,
+ P0_1 = 1,
+ P0_2 = 2,
+ P0_3 = 3,
+ P0_4 = 4,
+ P0_5 = 5,
+
+ dp1 = P0_5,
+ dp2 = P0_4,
+ dp3 = P0_3,
+ dp4 = P0_2,
+ dp5 = P0_1,
+ dp8 = P0_0,
+
+ // mbed original LED naming
+ LED1 = P0_2,
+ LED2 = P0_2,
+ LED3 = P0_2,
+ LED4 = P0_2,
+ LED_RED = P0_2,
+
+ // Serial to USB pins
+ USBTX = P0_4,
+ USBRX = P0_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+ PullUp = 2,
+ PullDown = 1,
+ PullNone = 0,
+ Repeater = 3,
+ OpenDrain = 4
+} PinMode;
+
+#define STDIO_UART_TX USBTX
+#define STDIO_UART_RX USBRX
+
+typedef struct {
+ unsigned char n;
+ unsigned char offset;
+} SWM_Map;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PortNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PortNames.h
new file mode 100644
index 00000000000..bbd5b31103a
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/PortNames.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ Port0 = 0,
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/device.h
new file mode 100644
index 00000000000..ddb923bb838
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/device.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN 0
+#define DEVICE_PORTOUT 0
+#define DEVICE_PORTINOUT 0
+
+#define DEVICE_INTERRUPTIN 1
+
+#define DEVICE_ANALOGIN 0
+#define DEVICE_ANALOGOUT 0
+
+#define DEVICE_SERIAL 1
+
+#define DEVICE_I2C 1
+#define DEVICE_I2CSLAVE 0
+
+#define DEVICE_SPI 1
+#define DEVICE_SPISLAVE 0
+
+#define DEVICE_CAN 0
+
+#define DEVICE_RTC 0
+
+#define DEVICE_ETHERNET 0
+
+#define DEVICE_PWMOUT 0
+
+#define DEVICE_SEMIHOST 0
+#define DEVICE_LOCALFILESYSTEM 0
+
+#define DEVICE_SLEEP 0
+
+#define DEVICE_DEBUG_AWARENESS 0
+
+#define DEVICE_STDIO_MESSAGES 1
+
+#define DEVICE_ERROR_RED 1
+
+#include "objects.h"
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_api.c
new file mode 100644
index 00000000000..62754bc3b5a
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_api.c
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "pinmap.h"
+
+static int gpio_enabled = 0;
+static void gpio_enable(void) {
+ gpio_enabled = 1;
+
+ /* Enable AHB clock to the GPIO domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+
+ /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */
+ LPC_SYSCON->PRESETCTRL &= ~(0x1<<10);
+ LPC_SYSCON->PRESETCTRL |= (0x1<<10);
+}
+
+uint32_t gpio_set(PinName pin) {
+ int f = 0;
+
+ if (!gpio_enabled)
+ gpio_enable();
+
+ pin_function(pin, f);
+
+ return (1 << ((int)pin & 0x1F));
+}
+
+void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
+ if(pin == NC) return;
+
+ obj->pin = pin;
+ obj->mask = gpio_set(pin);
+
+ obj->reg_set = &LPC_GPIO_PORT->SET0;
+ obj->reg_clr = &LPC_GPIO_PORT->CLR0;
+ obj->reg_in = &LPC_GPIO_PORT->PIN0;
+ obj->reg_dir = &LPC_GPIO_PORT->DIR0;
+
+ gpio_dir(obj, direction);
+ switch (direction) {
+ case PIN_OUTPUT: pin_mode(pin, PullNone); break;
+ case PIN_INPUT : pin_mode(pin, PullDown); break;
+ }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode) {
+ pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction) {
+ switch (direction) {
+ case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
+ case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
+ }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_irq_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_irq_api.c
new file mode 100644
index 00000000000..c90c31a3da5
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_irq_api.c
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include
+
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "error.h"
+
+#define CHANNEL_NUM 8
+#define LPC_GPIO_X LPC_PIN_INT
+#define PININT_IRQ PININT0_IRQn
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler irq_handler;
+
+static inline void handle_interrupt_in(uint32_t channel) {
+ uint32_t ch_bit = (1 << channel);
+ // Return immediately if:
+ // * The interrupt was already served
+ // * There is no user handler
+ // * It is a level interrupt, not an edge interrupt
+ if ( ((LPC_GPIO_X->IST & ch_bit) == 0) ||
+ (channel_ids[channel] == 0 ) ||
+ (LPC_GPIO_X->ISEL & ch_bit ) ) return;
+
+ if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_RISE);
+ LPC_GPIO_X->RISE = ch_bit;
+ }
+ if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) {
+ irq_handler(channel_ids[channel], IRQ_FALL);
+ }
+ LPC_GPIO_X->IST = ch_bit;
+}
+
+void gpio_irq0(void) {handle_interrupt_in(0);}
+void gpio_irq1(void) {handle_interrupt_in(1);}
+void gpio_irq2(void) {handle_interrupt_in(2);}
+void gpio_irq3(void) {handle_interrupt_in(3);}
+void gpio_irq4(void) {handle_interrupt_in(4);}
+void gpio_irq5(void) {handle_interrupt_in(5);}
+void gpio_irq6(void) {handle_interrupt_in(6);}
+void gpio_irq7(void) {handle_interrupt_in(7);}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
+ if (pin == NC) return -1;
+
+ irq_handler = handler;
+
+ int found_free_channel = 0;
+ int i = 0;
+ for (i=0; ich = i;
+ found_free_channel = 1;
+ break;
+ }
+ }
+ if (!found_free_channel) return -1;
+
+ /* Enable AHB clock to the GPIO domain. */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
+
+ LPC_SYSCON->PINTSEL[obj->ch] = pin;
+
+ // Interrupt Wake-Up Enable
+ LPC_SYSCON->STARTERP0 |= 1 << obj->ch;
+
+ void (*channels_irq)(void) = NULL;
+ switch (obj->ch) {
+ case 0: channels_irq = &gpio_irq0; break;
+ case 1: channels_irq = &gpio_irq1; break;
+ case 2: channels_irq = &gpio_irq2; break;
+ case 3: channels_irq = &gpio_irq3; break;
+ case 4: channels_irq = &gpio_irq4; break;
+ case 5: channels_irq = &gpio_irq5; break;
+ case 6: channels_irq = &gpio_irq6; break;
+ case 7: channels_irq = &gpio_irq7; break;
+ }
+ NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
+ NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+
+ return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj) {
+ channel_ids[obj->ch] = 0;
+ LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch);
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
+ unsigned int ch_bit = (1 << obj->ch);
+
+ // Clear interrupt
+ if (!(LPC_GPIO_X->ISEL & ch_bit))
+ LPC_GPIO_X->IST = ch_bit;
+
+ // Edge trigger
+ LPC_GPIO_X->ISEL &= ~ch_bit;
+ if (event == IRQ_RISE) {
+ if (enable) {
+ LPC_GPIO_X->IENR |= ch_bit;
+ } else {
+ LPC_GPIO_X->IENR &= ~ch_bit;
+ }
+ } else {
+ if (enable) {
+ LPC_GPIO_X->IENF |= ch_bit;
+ } else {
+ LPC_GPIO_X->IENF &= ~ch_bit;
+ }
+ }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_object.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_object.h
new file mode 100644
index 00000000000..8f8d5eb5952
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/gpio_object.h
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ uint32_t mask;
+
+ __IO uint32_t *reg_dir;
+ __IO uint32_t *reg_set;
+ __IO uint32_t *reg_clr;
+ __I uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+ if (value)
+ *obj->reg_set = obj->mask;
+ else
+ *obj->reg_clr = obj->mask;
+}
+
+static inline int gpio_read(gpio_t *obj) {
+ return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/i2c_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/i2c_api.c
new file mode 100644
index 00000000000..f6424724c84
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/i2c_api.c
@@ -0,0 +1,242 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const SWM_Map SWM_I2C_SDA[] = {
+ {7, 24},
+};
+
+static const SWM_Map SWM_I2C_SCL[] = {
+ {8, 0},
+};
+
+static uint8_t repeated_start = 0;
+
+#define I2C_DAT(x) (x->i2c->MSTDAT)
+#define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07))
+
+static inline int i2c_status(i2c_t *obj) {
+ return I2C_STAT(obj);
+}
+
+// Wait until the Serial Interrupt (SI) is set
+static int i2c_wait_SI(i2c_t *obj) {
+ int timeout = 0;
+ while (!(obj->i2c->STAT & (1 << 0))) {
+ timeout++;
+ if (timeout > 100000) return -1;
+ }
+ return 0;
+}
+
+static inline void i2c_interface_enable(i2c_t *obj) {
+ obj->i2c->CFG |= (1 << 0);
+}
+
+static inline void i2c_power_enable(i2c_t *obj) {
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5);
+ LPC_SYSCON->PRESETCTRL &= ~(0x1<<6);
+ LPC_SYSCON->PRESETCTRL |= (0x1<<6);
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
+ obj->i2c = (LPC_I2C_TypeDef *)LPC_I2C;
+
+ const SWM_Map *swm;
+ uint32_t regVal;
+
+ swm = &SWM_I2C_SDA[0];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (sda << swm->offset);
+
+ swm = &SWM_I2C_SCL[0];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (scl << swm->offset);
+
+ // enable power
+ i2c_power_enable(obj);
+ // set default frequency at 100k
+ i2c_frequency(obj, 100000);
+ i2c_interface_enable(obj);
+}
+
+inline int i2c_start(i2c_t *obj) {
+ int status = 0;
+ if (repeated_start) {
+ obj->i2c->MSTCTL = (1 << 1) | (1 << 0);
+ repeated_start = 0;
+ } else {
+ obj->i2c->MSTCTL = (1 << 1);
+ }
+ return status;
+}
+
+inline int i2c_stop(i2c_t *obj) {
+ int timeout = 0;
+
+ obj->i2c->MSTCTL = (1 << 2) | (1 << 0);
+ while ((obj->i2c->STAT & ((1 << 0) | (7 << 1))) != ((1 << 0) | (0 << 1))) {
+ timeout ++;
+ if (timeout > 100000) return 1;
+ }
+
+ return 0;
+}
+
+
+static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
+ // write the data
+ I2C_DAT(obj) = value;
+
+ if (!addr)
+ obj->i2c->MSTCTL = (1 << 0);
+
+ // wait and return status
+ i2c_wait_SI(obj);
+ return i2c_status(obj);
+}
+
+static inline int i2c_do_read(i2c_t *obj, int last) {
+ // wait for it to arrive
+ i2c_wait_SI(obj);
+ if (!last)
+ obj->i2c->MSTCTL = (1 << 0);
+
+ // return the data
+ return (I2C_DAT(obj) & 0xFF);
+}
+
+void i2c_frequency(i2c_t *obj, int hz) {
+ // No peripheral clock divider on the M0
+ uint32_t PCLK = SystemCoreClock;
+
+ uint32_t clkdiv = PCLK / (hz * 4) - 1;
+
+ obj->i2c->DIV = clkdiv;
+ obj->i2c->MSTTIME = 0;
+}
+
+// The I2C does a read or a write as a whole operation
+// There are two types of error conditions it can encounter
+// 1) it can not obtain the bus
+// 2) it gets error responses at part of the transmission
+//
+// We tackle them as follows:
+// 1) we retry until we get the bus. we could have a "timeout" if we can not get it
+// which basically turns it in to a 2)
+// 2) on error, we use the standard error mechanisms to report/debug
+//
+// Therefore an I2C transaction should always complete. If it doesn't it is usually
+// because something is setup wrong (e.g. wiring), and we don't need to programatically
+// check for that
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
+ int count, status;
+
+ i2c_start(obj);
+
+ status = i2c_do_write(obj, (address | 0x01), 1);
+ if (status != 0x01) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ // Read in all except last byte
+ for (count = 0; count < (length - 1); count++) {
+ int value = i2c_do_read(obj, 0);
+ status = i2c_status(obj);
+ if (status != 0x00) {
+ i2c_stop(obj);
+ return count;
+ }
+ data[count] = (char) value;
+ }
+
+ // read in last byte
+ int value = i2c_do_read(obj, 1);
+ status = i2c_status(obj);
+ if (status != 0x01) {
+ i2c_stop(obj);
+ return length - 1;
+ }
+
+ data[count] = (char) value;
+
+ // If not repeated start, send stop.
+ if (stop) {
+ i2c_stop(obj);
+ } else {
+ repeated_start = 1;
+ }
+
+ return length;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
+ int i, status;
+
+ i2c_start(obj);
+
+ status = i2c_do_write(obj, (address & 0xFE), 1);
+ if (status != 0x02) {
+ i2c_stop(obj);
+ return I2C_ERROR_NO_SLAVE;
+ }
+
+ for (i=0; iPIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 ,
+ &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 ,
+ &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 ,
+ &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11,
+ &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14,
+ &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17,
+};
+
+void pin_function(PinName pin, int function) {
+
+}
+
+void pin_mode(PinName pin, PinMode mode) {
+ if (pin == (uint32_t)NC) { return; }
+
+ if ((pin == 10) || (pin == 11)) {
+ // True open-drain pins can be configured for different I2C-bus speeds
+ return;
+ }
+
+ __IO uint32_t *reg = IOCON_REGISTERS[pin];
+
+ if (mode == OpenDrain) {
+ *reg |= (1 << 10);
+ } else {
+ uint32_t tmp = *reg;
+ tmp &= ~(0x3 << 3);
+ tmp |= (mode & 0x3) << 3;
+ *reg = tmp;
+ }
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/serial_api.c
new file mode 100644
index 00000000000..9a98f82e870
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/serial_api.c
@@ -0,0 +1,280 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// math.h required for floating point operations for baud rate calculation
+#include
+#include
+
+#include "serial_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+/******************************************************************************
+ * INITIALIZATION
+ ******************************************************************************/
+#define UART_NUM 3
+
+static const SWM_Map SWM_UART_TX[] = {
+ {0, 0},
+ {1, 8},
+ {2, 16},
+};
+
+static const SWM_Map SWM_UART_RX[] = {
+ {0, 8},
+ {1, 16},
+ {2, 24},
+};
+
+// bit flags for used UARTs
+static unsigned char uart_used = 0;
+static int get_available_uart(void) {
+ int i;
+ for (i=0; i<3; i++) {
+ if ((uart_used & (1 << i)) == 0)
+ return i;
+ }
+ return -1;
+}
+
+#define UART_EN (0x01<<0)
+
+#define CTS_DELTA (0x01<<5)
+#define RXBRK (0x01<<10)
+#define DELTA_RXBRK (0x01<<11)
+
+#define RXRDY (0x01<<0)
+#define TXRDY (0x01<<2)
+
+#define TXBRKEN (0x01<<1)
+
+static uint32_t UARTSysClk;
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+ int is_stdio_uart = 0;
+
+ int uart_n = get_available_uart();
+ if (uart_n == -1) {
+ error("No available UART");
+ }
+ obj->index = uart_n;
+ obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n));
+ uart_used |= (1 << uart_n);
+
+ const SWM_Map *swm;
+ uint32_t regVal;
+
+ swm = &SWM_UART_TX[uart_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset);
+
+ swm = &SWM_UART_RX[uart_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset);
+
+ /* uart clock divided by 1 */
+ LPC_SYSCON->UARTCLKDIV = 1;
+
+ /* disable uart interrupts */
+ NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
+
+ /* Enable UART clock */
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n));
+
+ /* Peripheral reset control to UART, a "1" bring it out of reset. */
+ LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
+ LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
+
+ UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
+
+ // set default baud rate and format
+ serial_baud (obj, 9600);
+ serial_format(obj, 8, ParityNone, 1);
+
+ /* Clear all status bits. */
+ obj->uart->STAT = CTS_DELTA | DELTA_RXBRK;
+
+ /* enable uart interrupts */
+ NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n));
+
+ /* Enable UART interrupt */
+ // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK;
+
+ /* Enable UART */
+ obj->uart->CFG |= UART_EN;
+
+ is_stdio_uart = ((tx == USBTX) && (rx == USBRX));
+
+ if (is_stdio_uart) {
+ stdio_uart_inited = 1;
+ memcpy(&stdio_uart, obj, sizeof(serial_t));
+ }
+}
+
+void serial_free(serial_t *obj) {
+ uart_used &= ~(1 << obj->index);
+ serial_irq_ids[obj->index] = 0;
+}
+
+// serial_baud
+// set the baud rate, taking in to account the current SystemFrequency
+void serial_baud(serial_t *obj, int baudrate) {
+ /* Integer divider:
+ BRG = UARTSysClk/(Baudrate * 16) - 1
+
+ Frational divider:
+ FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1)
+
+ where
+ FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1)
+
+ (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB
+ register is 0xFF.
+ (2) In ADD register value, depending on the value of UartSysClk,
+ baudrate, BRG register value, and SUB register value, be careful
+ about the order of multiplier and divider and make sure any
+ multiplier doesn't exceed 32-bit boundary and any divider doesn't get
+ down below one(integer 0).
+ (3) ADD should be always less than SUB.
+ */
+ obj->uart->BRG = UARTSysClk / 16 / baudrate - 1;
+
+ LPC_SYSCON->UARTFRGDIV = 0xFF;
+ LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) /
+ (baudrate * (obj->uart->BRG + 1))
+ ) - (LPC_SYSCON->UARTFRGDIV + 1);
+
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
+ // 0: 1 stop bits, 1: 2 stop bits
+ if (stop_bits != 1 && stop_bits != 2) {
+ error("Invalid stop bits specified");
+ }
+ stop_bits -= 1;
+
+ // 0: 7 data bits ... 2: 9 data bits
+ if (data_bits < 7 || data_bits > 9) {
+ error("Invalid number of bits (%d) in serial format, should be 7..9", data_bits);
+ }
+ data_bits -= 7;
+
+ int paritysel;
+ switch (parity) {
+ case ParityNone: paritysel = 0; break;
+ case ParityEven: paritysel = 2; break;
+ case ParityOdd : paritysel = 3; break;
+ default:
+ error("Invalid serial parity setting");
+ return;
+ }
+
+ obj->uart->CFG = (data_bits << 2)
+ | (paritysel << 4)
+ | (stop_bits << 6);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+static inline void uart_irq(uint32_t iir, uint32_t index) {
+ // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
+ SerialIrq irq_type;
+ switch (iir) {
+ case 1: irq_type = TxIrq; break;
+ case 2: irq_type = RxIrq; break;
+ default: return;
+ }
+
+ if (serial_irq_ids[index] != 0)
+ irq_handler(serial_irq_ids[index], irq_type);
+}
+
+void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);}
+void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);}
+void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
+ irq_handler = handler;
+ serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
+ IRQn_Type irq_n = (IRQn_Type)0;
+ uint32_t vector = 0;
+ switch ((int)obj->uart) {
+ case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
+ case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
+ case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
+ }
+
+ if (enable) {
+ obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2));
+ NVIC_SetVector(irq_n, vector);
+ NVIC_EnableIRQ(irq_n);
+ } else { // disable
+ int all_disabled = 0;
+ SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
+ obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2));
+ all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0;
+ if (all_disabled)
+ NVIC_DisableIRQ(irq_n);
+ }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+int serial_getc(serial_t *obj) {
+ while (!serial_readable(obj));
+ return obj->uart->RXDATA;
+}
+
+void serial_putc(serial_t *obj, int c) {
+ while (!serial_writable(obj));
+ obj->uart->TXDATA = c;
+}
+
+int serial_readable(serial_t *obj) {
+ return obj->uart->STAT & RXRDY;
+}
+
+int serial_writable(serial_t *obj) {
+ return obj->uart->STAT & TXRDY;
+}
+
+void serial_clear(serial_t *obj) {
+ // [TODO]
+}
+
+void serial_pinout_tx(PinName tx) {
+
+}
+
+void serial_break_set(serial_t *obj) {
+ obj->uart->CTRL |= TXBRKEN;
+}
+
+void serial_break_clear(serial_t *obj) {
+ obj->uart->CTRL &= ~TXBRKEN;
+}
+
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/spi_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/spi_api.c
new file mode 100644
index 00000000000..0a5d9797fd6
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/spi_api.c
@@ -0,0 +1,210 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "error.h"
+
+static const SWM_Map SWM_SPI_SSEL[] = {
+ {4, 16},
+ {5, 16},
+};
+
+static const SWM_Map SWM_SPI_SCLK[] = {
+ {3, 24},
+ {4, 24},
+};
+
+static const SWM_Map SWM_SPI_MOSI[] = {
+ {4, 0},
+ {5, 0},
+};
+
+static const SWM_Map SWM_SPI_MISO[] = {
+ {4, 8},
+ {5, 16},
+};
+
+// bit flags for used SPIs
+static unsigned char spi_used = 0;
+static int get_available_spi(void) {
+ int i;
+ for (i=0; i<2; i++) {
+ if ((spi_used & (1 << i)) == 0)
+ return i;
+ }
+ return -1;
+}
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+ int spi_n = get_available_spi();
+ if (spi_n == -1) {
+ error("No available SPI");
+ }
+ obj->spi_n = spi_n;
+ spi_used |= (1 << spi_n);
+
+ obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE);
+
+ const SWM_Map *swm;
+ uint32_t regVal;
+
+ swm = &SWM_SPI_SCLK[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset);
+
+ swm = &SWM_SPI_MOSI[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset);
+
+ swm = &SWM_SPI_MISO[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset);
+
+ swm = &SWM_SPI_SSEL[obj->spi_n];
+ regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset);
+ LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset);
+
+ // clear interrupts
+ obj->spi->INTENCLR = 0x3f;
+
+ // enable power and clocking
+ switch (obj->spi_n) {
+ case 0:
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
+ LPC_SYSCON->PRESETCTRL &= ~(0x1<<0);
+ LPC_SYSCON->PRESETCTRL |= (0x1<<0);
+ break;
+ case 1:
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12);
+ LPC_SYSCON->PRESETCTRL &= ~(0x1<<1);
+ LPC_SYSCON->PRESETCTRL |= (0x1<<1);
+ break;
+ }
+
+ // set default format and frequency
+ if (ssel == NC) {
+ spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
+ } else {
+ spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
+ }
+ spi_frequency(obj, 1000000);
+
+ // enable the ssp channel
+ ssp_enable(obj);
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+ ssp_disable(obj);
+
+ if (!(bits >= 1 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+ error("SPI format error");
+ }
+
+
+ int polarity = (mode & 0x2) ? 1 : 0;
+ int phase = (mode & 0x1) ? 1 : 0;
+
+ // set it up
+ int DSS = bits - 1; // DSS (data select size)
+ int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
+ int SPH = (phase) ? 1 : 0; // SPH - clock out phase
+
+ uint32_t tmp = obj->spi->CFG;
+ tmp &= ~((1 << 2) | (1 << 4) | (1 << 5));
+ tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2);
+ obj->spi->CFG = tmp;
+
+ // select frame length
+ tmp = obj->spi->TXDATCTL;
+ tmp &= ~(0xf << 24);
+ tmp |= (DSS << 24);
+ obj->spi->TXDATCTL = tmp;
+
+ ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+ ssp_disable(obj);
+
+ uint32_t PCLK = SystemCoreClock;
+
+ obj->spi->DIV = PCLK/hz - 1;
+ obj->spi->DLY = 0;
+ ssp_enable(obj);
+}
+
+static inline int ssp_disable(spi_t *obj) {
+ return obj->spi->CFG &= ~(1 << 0);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+ return obj->spi->CFG |= (1 << 0);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+ return obj->spi->STAT & (1 << 0);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+ return obj->spi->STAT & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+ while (!ssp_writeable(obj));
+ // end of transfer
+ obj->spi->TXDATCTL |= (1 << 20);
+ obj->spi->TXDAT = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+ while (!ssp_readable(obj));
+ return obj->spi->RXDAT;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+ // TODO
+ return 0;
+}
+
+int spi_master_write(spi_t *obj, int value) {
+ ssp_write(obj, value);
+ return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+ return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+};
+
+int spi_slave_read(spi_t *obj) {
+ return obj->spi->RXDAT;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+ while (ssp_writeable(obj) == 0) ;
+ obj->spi->TXDAT = value;
+}
+
+int spi_busy(spi_t *obj) {
+ return ssp_busy(obj);
+}
diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/us_ticker.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/us_ticker.c
new file mode 100644
index 00000000000..cf03fc931a7
--- /dev/null
+++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC810/us_ticker.c
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+#define US_TICKER_TIMER_IRQn SCT_IRQn
+
+int us_ticker_inited = 0;
+
+void us_ticker_init(void) {
+ if (us_ticker_inited) return;
+ us_ticker_inited = 1;
+
+ // Enable the SCT clock
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8);
+
+ // Clear peripheral reset the SCT:
+ LPC_SYSCON->PRESETCTRL |= (1 << 8);
+
+ // Unified counter (32 bits)
+ LPC_SCT->CONFIG |= 1;
+
+ // halt and clear the counter
+ LPC_SCT->CTRL_L |= (1 << 2) | (1 << 3);
+
+ // System Clock (12)MHz -> us_ticker (1)MHz
+ LPC_SCT->CTRL_L |= ((SystemCoreClock/1000000 - 1) << 5);
+
+ // unhalt the counter:
+ // - clearing bit 2 of the CTRL register
+ LPC_SCT->CTRL_L &= ~(1 << 2);
+
+ NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
+ NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
+}
+
+uint32_t us_ticker_read() {
+ if (!us_ticker_inited)
+ us_ticker_init();
+
+ return LPC_SCT->COUNT_U;
+}
+
+void us_ticker_set_interrupt(unsigned int timestamp) {
+ // halt the counter:
+ // - setting bit 2 of the CTRL register
+ LPC_SCT->CTRL_L |= (1 << 2);
+
+ // set timestamp in compare register
+ LPC_SCT->MATCH[0].U = timestamp;
+
+ // unhalt the counter:
+ // - clearing bit 2 of the CTRL register
+ LPC_SCT->CTRL_L &= ~(1 << 2);
+
+ // if events are not enabled, enable them
+ if (!(LPC_SCT->EVEN & 0x01)) {
+
+ // comb mode = match only
+ LPC_SCT->EVENT[0].CTRL = (1 << 12);
+
+ // ref manual:
+ // In simple applications that do not
+ // use states, write 0x01 to this
+ // register to enable an event
+ LPC_SCT->EVENT[0].STATE |= 0x1;
+
+ // enable events
+ LPC_SCT->EVEN |= 0x1;
+ }
+}
+
+void us_ticker_disable_interrupt(void) {
+ LPC_SCT->EVEN &= ~1;
+}
+
+void us_ticker_clear_interrupt(void) {
+ LPC_SCT->EVFLAG = 1;
+}
diff --git a/workspace_tools/export/uvision4_lpc1114.uvopt.tmpl b/workspace_tools/export/uvision4_lpc1114.uvopt.tmpl
index 26ca506ab8c..4734a72b06f 100644
--- a/workspace_tools/export/uvision4_lpc1114.uvopt.tmpl
+++ b/workspace_tools/export/uvision4_lpc1114.uvopt.tmpl
@@ -21,7 +21,7 @@
- mbed NXP LPC1768
+ mbed NXP LPC1114
0x4
ARM-ADS
diff --git a/workspace_tools/export/uvision4_lpc1114.uvproj.tmpl b/workspace_tools/export/uvision4_lpc1114.uvproj.tmpl
index 3274ae7279c..ddb8e210933 100644
--- a/workspace_tools/export/uvision4_lpc1114.uvproj.tmpl
+++ b/workspace_tools/export/uvision4_lpc1114.uvproj.tmpl
@@ -75,7 +75,7 @@
0
0
- fromelf --bin -o build\{{name}}_LPC1768.bin build\{{name}}.axf
+ fromelf --bin -o build\{{name}}_LPC1114.bin build\{{name}}.axf
0
0
@@ -165,7 +165,7 @@
0
-1
- 0
+ 1
BIN\UL2CM3.DLL
@@ -201,7 +201,7 @@
0
"Cortex-M0"
- 0
+ 1
0
0
1
@@ -212,7 +212,7 @@
0
0
8
- 0
+ 1
0
0
3
diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py
index 4bc73becdc4..20cf2d598e1 100644
--- a/workspace_tools/targets.py
+++ b/workspace_tools/targets.py
@@ -134,6 +134,19 @@ def __init__(self):
self.is_disk_virtual = True
+class LPC810(Target):
+ def __init__(self):
+ Target.__init__(self)
+
+ self.core = "Cortex-M0+"
+
+ self.extra_labels = ['NXP', 'LPC810']
+
+ self.supported_toolchains = ["uARM"]
+
+ self.is_disk_virtual = True
+
+
class LPC4088(Target):
def __init__(self):
Target.__init__(self)
@@ -287,6 +300,7 @@ def __init__(self):
KL05Z(),
KL25Z(),
LPC812(),
+ LPC810(),
LPC4088(),
LPC4330_M4(),
STM32F407(),