diff --git a/.gitignore b/.gitignore index e89472c010a..119a82d5254 100644 --- a/.gitignore +++ b/.gitignore @@ -96,4 +96,4 @@ log test_suite.json # default delivery dir -DELIVERY/ +DELIVERY/ \ No newline at end of file diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/inc/ble_status.h b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/ble_status.h new file mode 100644 index 00000000000..9569bb28b9a --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/ble_status.h @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __BLE_STATUS_H__ +#define __BLE_STATUS_H__ + +#include + +/* @brief Standard Error Codes as specified by the Bluetooth Specifications + * Vol.2, Part D ("Error Codes"). + * According to the spec the error codes range is from 0x00 to 0x3F. + */ +#define BLE_STATUS_SUCCESS ((tBleStatus)(0x00)) + +#define BLE_ERROR_UNKNOWN_HCI_COMMAND ((tBleStatus)(0x01)) +#define BLE_ERROR_UNKNOWN_CONNECTION_ID ((tBleStatus)(0x02)) + +#define BLE_ERROR_HARDWARE_FAILURE ((tBleStatus)(0x03)) + +#define BLE_ERROR_AUTHENTICATION_FAILURE ((tBleStatus)(0x05)) +#define BLE_ERROR_KEY_MISSING ((tBleStatus)(0x06)) +#define BLE_ERROR_MEMORY_CAPACITY_EXCEEDED ((tBleStatus)(0x07)) +#define BLE_ERROR_CONNECTION_TIMEOUT ((tBleStatus)(0x08)) + +#define BLE_ERROR_COMMAND_DISALLOWED ((tBleStatus)(0x0C)) + +#define BLE_ERROR_UNSUPPORTED_FEATURE ((tBleStatus)(0x11)) + +#define BLE_ERROR_INVALID_HCI_CMD_PARAMS ((tBleStatus)(0x12)) + +#define BLE_ERROR_TERMINATED_REMOTE_USER ((tBleStatus)(0x13)) + +#define BLE_ERROR_TERMINATED_LOCAL_HOST ((tBleStatus)(0x16)) + +#define BLE_ERROR_UNSUPP_RMT_FEATURE ((tBleStatus)(0x1A)) + +#define BLE_ERROR_UNSPECIFIED ((tBleStatus)(0x1F)) + +#define BLE_ERROR_PROCEDURE_TIMEOUT ((tBleStatus)(0x22)) + +#define BLE_ERROR_INSTANT_PASSED ((tBleStatus)(0x28)) + +#define BLE_ERROR_PARAMETER_OUT_OF_RANGE ((tBleStatus)(0x30)) + +#define BLE_ERROR_HOST_BUSY_PAIRING ((tBleStatus)(0x38)) + +#define BLE_ERROR_CONTROLLER_BUSY ((tBleStatus)(0x3A)) + +#define BLE_ERROR_DIRECTED_ADVERTISING_TIMEOUT ((tBleStatus)(0x3C)) + +#define BLE_ERROR_CONNECTION_END_WITH_MIC_FAILURE ((tBleStatus)(0x3D)) +#define BLE_ERROR_CONNECTION_FAILED_TO_ESTABLISH ((tBleStatus)(0x3E)) + + +/** +* @name Generic/System error codes +* @brief The error codes as reported by the different Protocol layers. +* They start with 0x40 +* @{ +*/ + +/** + * @brief The Connection Identifier does not exist. + * Temporary remapped to corresponding Controller Error. + */ +#define BLE_STATUS_UNKNOWN_CONNECTION_ID ((tBleStatus)(0x40)) + +/** + * @brief The Host failed while performing the requested operation. + */ +#define BLE_STATUS_FAILED ((tBleStatus)(0x41)) + +/*! @enum tBleStatus::BLE_STATUS_INVALID_PARAMS + * + */ +#define BLE_STATUS_INVALID_PARAMS ((tBleStatus)(0x42)) + +/** + * @brief The Host is already processing another request received in advance. + */ +#define BLE_STATUS_BUSY ((tBleStatus)(0x43)) + +/* + * Currently not used, because this error is always signalled with an explicit + * Error Response message seny by the relative layer. + */ +//#define BLE_STATUS_INVALID_LEN_PDU ((tBleStatus)(0x44)) + +/** + * @brief The operation requested cannot be completed immediately by the Host + * (usually because of lack of resources). + * The operation is generally put on hold by the caller and it's usually + * retried on later time. + */ +#define BLE_STATUS_PENDING ((tBleStatus)(0x45)) + +/** + * @brief The requested operation cannot be performed by the Host in the current status. + */ +#define BLE_STATUS_NOT_ALLOWED ((tBleStatus)(0x46)) + +/** + * @brief The requested operation violates the logic of the called layer/function or + * the format of the data to be processed during the operation. + */ +#define BLE_STATUS_ERROR ((tBleStatus)(0x47)) + +/** + * @brief The requested operation failed because of lack of memory. + * Out of memory shall be returned for situations where memory will never + * become available again (e.g. ATT database) + */ +#define BLE_STATUS_OUT_OF_MEMORY ((tBleStatus)(0x48)) + +/** +*@} +*/ + + +/** + * @name L2CAP error codes + * @{ + */ + +/** + * @brief An invalid L2CAP CID/channel has been selected to send data over. + */ +#define BLE_STATUS_INVALID_CID ((tBleStatus)(0x50)) + +/** +*@} +*/ + + +/** +* @name Security Manager error codes +* @brief Error codes returned by the Security Manager Protocol (SMP) +* @{ +*/ + +/** + * @brief The remote device in in the Blacklist and the pairing operation it requested + * cannot be performed. + */ +#define BLE_STATUS_DEV_IN_BLACKLIST ((tBleStatus)(0x59)) + +/** + * @brief CSRK not found during validation of an incoming signed packet + */ +#define BLE_STATUS_CSRK_NOT_FOUND ((tBleStatus)(0x5A)) + +/** + * @brief Currently not used! + */ +#define BLE_STATUS_IRK_NOT_FOUND ((tBleStatus)(0x5B)) + +/** + * @brief A search for a specific remote device was unsuccessfull because no entry exists + * either into Security/GATT Database (flash-based) or in volatile database. + */ +#define BLE_STATUS_DEV_NOT_FOUND ((tBleStatus)(0x5C)) + +/** + * @brief The security database is full and no more records can be added. + */ +#define BLE_STATUS_SEC_DB_FULL ((tBleStatus)(0x5D)) + +/** + * @brief The remote device is not bonded, and no operations related to bonded devices + * may be performed (e.g. writing Gatt Client data). + */ +#define BLE_STATUS_DEV_NOT_BONDED ((tBleStatus)(0x5E)) + +/** + * @brief The encryption key size used for encrypting the link is insufficient\n + */ +#define BLE_INSUFFICIENT_ENC_KEYSIZE ((tBleStatus)(0x5F)) + +/** +*@} +*/ + + +/** +* @name Gatt layer Error Codes +* @brief Error codes returned by the Gatt layer +* @{ +*/ +#define BLE_STATUS_INVALID_HANDLE ((tBleStatus)(0x60)) + +/** + * @brief There aren't sufficient Attributes handles available for allocation during + * creation of Services, Characteristics or Descriptors. + */ +#define BLE_STATUS_OUT_OF_HANDLE ((tBleStatus)(0x61)) + +/** + * @brief The requested GATT operation is not allowed in this context/status or using + * the provided parameters. + * This is a specific GATT error, different from generic Not Allowed error, + * because it refers to specific GATT specifications/rules. + */ +#define BLE_STATUS_INVALID_OPERATION ((tBleStatus)(0x62)) + +/** + * @brief The characteristic has already been added to the database. + */ +#define BLE_STATUS_CHARAC_ALREADY_EXISTS ((tBleStatus)(0x63)) + +/** + * @brief The requested operation failed for a temporary lack of resources + * (e.g. packet pool or timers), but it may be retried later when resources may + * become available (packets or timers may have been released by other consumers). + */ +#define BLE_STATUS_INSUFFICIENT_RESOURCES ((tBleStatus)(0x64)) + +/** + * @brief Notification/Indication can't be sent to the requested remote device because + * it doesn't satisfy the needed security permission. + */ +#define BLE_STATUS_SEC_PERMISSION_ERROR ((tBleStatus)(0x65)) + +/** +*@} +*/ + + +/** +* @name GAP layer Error Codes +* @brief Error codes returned externally by the GAP layer +* @{ +*/ + +/** + * @brief The address of the device could not be resolved using the IRK stored\n + */ +#define BLE_STATUS_ADDRESS_NOT_RESOLVED ((tBleStatus)(0x70)) + +/** +*@} +*/ + + +/** +* @name Link Layer error Codes +* @brief Error codes returned by the Link layer during advertising/conection. +* @{ +*/ + +/** + * @brief Returned when no valid slots are available (e.g. when there are no available state machines). + */ +#define BLE_STATUS_NO_VALID_SLOT ((tBleStatus)(0x82)) + +/** + * @brief Returned when a scan window shorter than minimum allowed value has been requested (i.e. 2ms) + */ +#define BLE_STATUS_SCAN_WINDOW_SHORT ((tBleStatus)(0x83)) + +/** + * @brief Returned when the maximum requested interval to be allocated is shorter then the current + * anchor period and a there is no submultiple for the current anchor period that is between + * the minimum and the maximum requested intervals. + */ +#define BLE_STATUS_NEW_INTERVAL_FAILED ((tBleStatus)(0x84)) + +/** + * @brief Returned when the maximum requested interval to be allocated is greater than the current anchor + * period, and there is no multiple of the anchor period that is between the minimum and the maximum + * requested intervals. + */ +#define BLE_STATUS_INTERVAL_TOO_LARGE ((tBleStatus)(0x85)) + +/** + * @brief Returned when the current anchor period or a new one can be found that is compatible to the + * interval range requested by the new slot, but the maximum available length that can be allocated is + * less than the minimum requested slot length. + */ +#define BLE_STATUS_LENGTH_FAILED ((tBleStatus)(0x86)) + +/** +*@} +*/ + +/** +* @name flash error codes +* @brief Flash sector read write error codes, which used to start with 0x49 +* and are currently remapped from 0xFA to 0xFC +* @{ +*/ +#define FLASH_READ_FAILED ((tBleStatus)(0xFA)) +#define FLASH_WRITE_FAILED ((tBleStatus)(0xFB)) +#define FLASH_ERASE_FAILED ((tBleStatus)(0xFC)) + +/** + * @name Profiles Library Error Codes + * @{ + */ +#define BLE_STATUS_TIMEOUT (0xFF) +#define BLE_STATUS_PROFILE_ALREADY_INITIALIZED (0xF0) +#define BLE_STATUS_NULL_PARAM (0xF1) + +/** +*@} +*/ + + +#endif diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_api.h b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_api.h new file mode 100644 index 00000000000..6588dfcd327 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_api.h @@ -0,0 +1,3693 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef _BLUENRG1_API_H_ +#define _BLUENRG1_API_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +/** Documentation for C struct Whitelist_Entry_t */ +typedef struct Whitelist_Entry_t_s { + /** Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + */ + uint8_t Peer_Address_Type; + /** Public Device Address or Random Device Address of the device +to be added to the white list. + */ + uint8_t Peer_Address[6]; +} Whitelist_Entry_t; +/** Documentation for C struct Bonded_Device_Entry_t */ +typedef struct Bonded_Device_Entry_t_s { + /** Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + */ + uint8_t Address_Type; + /** Public Device Address or Random Device Address of the device +to be added to the white list. + */ + uint8_t Address[6]; +} Bonded_Device_Entry_t; +/** Documentation for C struct Whitelist_Identity_Entry_t */ +typedef struct Whitelist_Identity_Entry_t_s { + /** Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + */ + uint8_t Peer_Identity_Address_Type; + /** Public or Random (static) Identity address of the peer device + */ + uint8_t Peer_Identity_Address[6]; +} Whitelist_Identity_Entry_t; +/** Documentation for C union Service_UUID_t */ +typedef union Service_UUID_t_s { + /** 16-bit UUID + */ + uint16_t Service_UUID_16; + /** 128-bit UUID + */ + uint8_t Service_UUID_128[16]; +} Service_UUID_t; +/** Documentation for C union Include_UUID_t */ +typedef union Include_UUID_t_s { + /** 16-bit UUID + */ + uint16_t Include_UUID_16; + /** 128-bit UUID + */ + uint8_t Include_UUID_128[16]; +} Include_UUID_t; +/** Documentation for C union Char_UUID_t */ +typedef union Char_UUID_t_s { + /** 16-bit UUID + */ + uint16_t Char_UUID_16; + /** 128-bit UUID + */ + uint8_t Char_UUID_128[16]; +} Char_UUID_t; +/** Documentation for C union Char_Desc_Uuid_t */ +typedef union Char_Desc_Uuid_t_s { + /** 16-bit UUID + */ + uint16_t Char_UUID_16; + /** 128-bit UUID + */ + uint8_t Char_UUID_128[16]; +} Char_Desc_Uuid_t; +/** Documentation for C union UUID_t */ +typedef union UUID_t_s { + /** 16-bit UUID + */ + uint16_t UUID_16; + /** 128-bit UUID + */ + uint8_t UUID_128[16]; +} UUID_t; +/** Documentation for C struct Handle_Entry_t */ +typedef struct Handle_Entry_t_s { + /** The handles for which the attribute value has to be read + */ + uint16_t Handle; +} Handle_Entry_t; +typedef uint8_t tBleStatus; +/** + *@defgroup HCI_API HCI API + *@brief HCI API layer. + *@{ + */ +/** + * @brief The @ref hci_disconnect is used to terminate an existing connection. The +Connection_Handle command parameter indicates which connection is to be +disconnected. The Reason command parameter indicates the reason for ending +the connection. The remote Controller will receive the Reason command +parameter in the @ref hci_disconnection_complete_event event. All synchronous connections +on a physical link should be disconnected before the ACL connection on the +same physical connection is disconnected. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.1.6) +It is important to leave an 100 ms blank window before sending any new command (including system hardware reset), +since immediately after @ref hci_disconnection_complete_event event, system could save important information in non volatile memory. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Reason The reason for ending the connection. + * Values: + - 0x05: Authentication Failure + - 0x13: Remote User Terminated Connection + - 0x14: Remote Device Terminated Connection due to Low Resources + - 0x15: Remote Device Terminated Connection due to Power Off + - 0x1A: Unsupported Remote Feature + - 0x3B: Unacceptable Connection Parameters + * @retval Value indicating success or error code. +*/ +tBleStatus hci_disconnect(uint16_t Connection_Handle, + uint8_t Reason); +/** + * @brief This command will obtain the values for the version information for the remote +device identified by the Connection_Handle parameter. The Connection_Handle +must be a Connection_Handle for an ACL or LE connection. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.1.23) + * @param Connection_Handle Specifies which Connection_Handle's version information to get. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_remote_version_information(uint16_t Connection_Handle); +/** + * @brief The Set_Event_Mask command is used to control which events are generated +by the HCI for the Host. + +If the bit in the Event_Mask is set to a one, then the +event associated with that bit will be enabled. For an LE Controller, the LE +Meta Event bit in the Event_Mask shall enable or disable all LE events in the +LE Meta Event (see Section 7.7.65). The Host has to deal with each event that +occurs. The event mask allows the Host to control how much it is interrupted. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.3.1) + * @param Event_Mask Event mask. Default: 0x00001FFFFFFFFFFF + * Flags: + - 0x0000000000000000: No events specified + - 0x0000000000000001: Inquiry Complete Event + - 0x0000000000000002: Inquiry Result Event + - 0x0000000000000004: Connection Complete Event + - 0x0000000000000008: Connection Request Event + - 0x0000000000000010: Disconnection Complete Event + - 0x0000000000000020: Authentication Complete Event + - 0x0000000000000040: Remote Name Request Complete Event + - 0x0000000000000080: Encryption Change Event + - 0x0000000000000100: Change Connection Link Key Complete Event + - 0x0000000000000200: Master Link Key Complete Event + - 0x0000000000000400: Read Remote Supported Features Complete Event + - 0x0000000000000800: Read Remote Version Information Complete Event + - 0x0000000000001000: QoS Setup Complete Event + - 0x0000000000008000: Hardware Error Event + - 0x0000000000010000: Flush Occurred Event + - 0x0000000000020000: Role Change Event + - 0x0000000000080000: Mode Change Event + - 0x0000000000100000: Return Link Keys Event + - 0x0000000000200000: PIN Code Request Event + - 0x0000000000400000: Link Key Request Event + - 0x0000000000800000: Link Key Notification Event + - 0x0000000001000000: Loopback Command Event + - 0x0000000002000000: Data Buffer Overflow Event + - 0x0000000004000000: Max Slots Change Event + - 0x0000000008000000: Read Clock Offset Complete Event + - 0x0000000010000000: Connection Packet Type Changed Event + - 0x0000000020000000: QoS Violation Event + - 0x0000000040000000: Page Scan Mode Change Event + - 0x0000000080000000: Page Scan Repetition Mode Change Event + - 0x0000000100000000: Flow Specification Complete Event + - 0x0000000200000000: Inquiry Result with RSSI Event + - 0x0000000400000000: Read Remote Extended Features Complete Event + - 0x0000080000000000: Synchronous Connection Complete Event + - 0x0000100000000000: Synchronous Connection Changed Event + - 0x0000200000000000: Sniff Subrating Event + - 0x0000400000000000: Extended Inquiry Result Event + - 0x0000800000000000: Encryption Key Refresh Complete Event + - 0x0001000000000000: IO Capability Request Event + - 0x0002000000000000: IO Capability Request Reply Event + - 0x0004000000000000: User Confirmation Request Event + - 0x0008000000000000: User Passkey Request Event + - 0x0010000000000000: Remote OOB Data Request Event + - 0x0020000000000000: Simple Pairing Complete Event + - 0x0080000000000000: Link Supervision Timeout Changed Event + - 0x0100000000000000: Enhanced Flush Complete Event + - 0x0400000000000000: User Passkey Notification Event + - 0x0800000000000000: Keypress Notification Event + - 0x1000000000000000: Remote Host Supported Features Notification Event + - 0x2000000000000000: LE Meta-Event + * @retval Value indicating success or error code. +*/ +tBleStatus hci_set_event_mask(uint8_t Event_Mask[8]); +/** + * @brief The Reset command will reset the Link Layer on an LE +Controller. + +The Reset command shall not affect the used HCI transport layer since the HCI transport +layers may have reset mechanisms of their own. After the reset is completed, +the current operational state will be lost, the Controller will enter standby mode +and the Controller will automatically revert to the default values for the parameters +for which default values are defined in the specification. +Note: The Reset command will not necessarily perform a hardware reset. This +is implementation defined. +The Host shall not send additional HCI commands before the Command Complete +event related to the Reset command has been received. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.3.2) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_reset(void); +/** + * @brief This command reads the values for the Transmit_Power_Level parameter for +the specified Connection_Handle. The Connection_Handle shall be a Connection_Handle +for an ACL connection. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.3.35) + * @param Connection_Handle Specifies which Connection_Handle's Transmit Power Level setting to read. + * Values: + - 0x0000 ... 0x0EFF + * @param Type Current or maximum transmit power level. + * Values: + - 0x00: Read Current Transmit Power Level. + - 0x01: Read Maximum Transmit Power Level. + * @param[out] Transmit_Power_Level Size: 1 Octet (signed integer) +Units: dBm + * Values: + - -30 ... 20 + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_transmit_power_level(uint16_t Connection_Handle, + uint8_t Type, + uint8_t *Transmit_Power_Level); +/** + * @brief This command reads the values for the version information for the local Controller. +The HCI Version information defines the version information of the HCI layer. +The LMP/PAL Version information defines the version of the LMP or PAL. The +Manufacturer_Name information indicates the manufacturer of the local device. +The HCI Revision and LMP/PAL Subversion are implementation dependent. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.4.1) + * @param[out] HCI_Version See Bluetooth Assigned Numbers (https://www.bluetooth.org/en-us/specification/assigned-numbers) + * @param[out] HCI_Revision Revision of the Current HCI in the BR/EDR Controller. + * @param[out] LMP_PAL_Version Version of the Current LMP or PAL in the Controller. +See Bluetooth Assigned Numbers (https://www.bluetooth.org/en-us/specification/assigned-numbers) + * @param[out] Manufacturer_Name Manufacturer Name of the BR/EDR Controller. +See Bluetooth Assigned Numbers (https://www.bluetooth.org/en-us/specification/assigned-numbers) + * @param[out] LMP_PAL_Subversion Subversion of the Current LMP or PAL in the Controller. This value is +implementation dependent. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_local_version_information(uint8_t *HCI_Version, + uint16_t *HCI_Revision, + uint8_t *LMP_PAL_Version, + uint16_t *Manufacturer_Name, + uint16_t *LMP_PAL_Subversion); +/** + * @brief This command reads the list of HCI commands supported for the local Controller. +This command shall return the Supported_Commands configuration parameter. +It is implied that if a command is listed as supported, the feature underlying +that command is also supported. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.4.2) + * @param[out] Supported_Commands Bit mask for each HCI Command. If a bit is 1, the Controller supports the +corresponding command and the features required for the command. +Unsupported or undefined commands shall be set to 0. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_local_supported_commands(uint8_t Supported_Commands[64]); +/** + * @brief This command requests a list of the supported features for the local +Controller. This command will return a list of the LMP features. For details see +Part C, Link Manager Protocol Specification on page 227. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.4.3) + * @param[out] LMP_Features Bit Mask List of LMP features. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_local_supported_features(uint8_t LMP_Features[8]); +/** + * @brief On an LE Controller, this command shall read the Public Device Address as +defined in [Vol 6] Part B, Section 1.3, Device Address. If this Controller does +not have a Public Device Address, the value 0x000000000000 shall be +returned. +On an LE Controller, the public address shall be the same as the +BD_ADDR. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.4.6) + * @param[out] BD_ADDR BD_ADDR ( Bluetooth Device Address) of the Device. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_bd_addr(uint8_t BD_ADDR[6]); +/** + * @brief This command reads the Received Signal Strength Indication (RSSI) value from +a Controller. +For an LE transport, a Connection_Handle is used as the Handle command +parameter and return parameter. The meaning of the RSSI metric is an absolute +receiver signal strength value in dBm to +/- 6 dB accuracy. If the RSSI cannot +be read, the RSSI metric shall be set to 127. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.5.4) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param[out] RSSI N Size: 1 Octet (signed integer) +Units: dBm + * Values: + - 127: RSSI not available + - -127 ... 20 + * @retval Value indicating success or error code. +*/ +tBleStatus hci_read_rssi(uint16_t Connection_Handle, + uint8_t *RSSI); +/** + * @brief The LE_Set_Event_Mask command is used to control which LE events are +generated by the HCI for the Host. If the bit in the LE_Event_Mask is set to a +one, then the event associated with that bit will be enabled. The Host has to +deal with each event that is generated by an LE Controller. The event mask +allows the Host to control which events will interrupt it. +For LE events to be generated, the LE Meta-Event bit in the Event_Mask shall +also be set. If that bit is not set, then LE events shall not be generated, regardless +of how the LE_Event_Mask is set. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.1) + * @param LE_Event_Mask LE event mask. Default: 0x000000000000001F. + * Flags: + - 0x0000000000000000: No LE events specified + - 0x0000000000000001: LE Connection Complete Event + - 0x0000000000000002: LE Advertising Report Event + - 0x0000000000000004: LE Connection Update Complete Event + - 0x0000000000000008: LE Read Remote Used Features Complete Event + - 0x0000000000000010: LE Long Term Key Request Event + - 0x0000000000000020: LE Remote Connection Parameter Request Event + - 0x0000000000000040: LE Data Length Change Event + - 0x0000000000000080: LE Read Local P-256 Public Key Complete Event + - 0x0000000000000100: LE Generate DHKey Complete Event + - 0x0000000000000200: LE Enhanced Connection Complete Event + - 0x0000000000000400: LE Direct Advertising Report Event + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_event_mask(uint8_t LE_Event_Mask[8]); +/** + * @brief The LE_Read_Buffer_Size command is used to read the maximum size of the +data portion of HCI LE ACL Data Packets sent from the Host to the Controller. +The Host will segment the data transmitted to the Controller according to these +values, so that the HCI Data Packets will contain data with up to this size. The +LE_Read_Buffer_Size command also returns the total number of HCI LE ACL +Data Packets that can be stored in the data buffers of the Controller. The +LE_Read_Buffer_Size command must be issued by the Host before it sends +any data to an LE Controller (see Section 4.1.1). +If the Controller returns a length value of zero, the Host shall use the +Read_Buffer_Size command to determine the size of the data buffers +Note: Both the Read_Buffer_Size and LE_Read_Buffer_Size commands may +return buffer length and number of packets parameter values that are nonzero. +The HC_LE_ACL_Data_Packet_Length return parameter shall be used to +determine the size of the L2CAP PDU segments contained in ACL Data +Packets, which are transferred from the Host to the Controller to be broken up +into packets by the Link Layer. Both the Host and the Controller shall support +command and event packets, where the data portion (excluding header) +contained in the packets is 255 octets in size. The +HC_Total_Num_LE_ACL_Data_Packets return parameter contains the total +number of HCI ACL Data Packets that can be stored in the data buffers of the +Controller. The Host determines how the buffers are to be divided between +different Connection Handles. +Note: The HC_LE_ACL_Data_Packet_Length return parameter does not +include the length of the HCI Data Packet header. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.2) + * @param[out] HC_LE_ACL_Data_Packet_Length 0x0000 No dedicated LE Buffer - use Read_Buffer_Size command. +0x0001 - 0xFFFF Maximum length (in octets) of the data portion of each HCI ACL Data +Packet that the Controller is able to accept. + * @param[out] HC_Total_Num_LE_ACL_Data_Packets 0x00 No dedicated LE Buffer - use Read_Buffer_Size command. +0x01 - 0xFF Total number of HCI ACL Data Packets that can be stored in the data +buffers of the Controller. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_buffer_size(uint16_t *HC_LE_ACL_Data_Packet_Length, + uint8_t *HC_Total_Num_LE_ACL_Data_Packets); +/** + * @brief This command requests the list of the supported LE features for the Controller. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.3) + * @param[out] LE_Features Bit Mask List of LE features. See Core v4.1, Vol. 6, Part B, Section 4.6. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_local_supported_features(uint8_t LE_Features[8]); +/** + * @brief The LE_Set_Random_Address command is used by the Host to set the LE +Random Device Address in the Controller (see [Vol 6] Part B, Section 1.3). +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.4) + * @param Random_Address Random Device Address. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_random_address(uint8_t Random_Address[6]); +/** + * @brief The LE_Set_Advertising_Parameters command is used by the Host to set the +advertising parameters. +The Advertising_Interval_Min shall be less than or equal to the +Advertising_Interval_Max. The Advertising_Interval_Min and +Advertising_Interval_Max should not be the same value to enable the +Controller to determine the best advertising interval given other activities. +For high duty cycle directed advertising, i.e. when Advertising_Type is 0x01 +(ADV_DIRECT_IND, high duty cycle), the Advertising_Interval_Min and +Advertising_Interval_Max parameters are not used and shall be ignored. +The Advertising_Type is used to determine the packet type that is used for +advertising when advertising is enabled. +Own_Address_Type parameter indicates the type of address being used in the +advertising packets. +If Own_Address_Type equals 0x02 or 0x03, the Peer_Address parameter +contains the peer's Identity Address and the Peer_Address_Type parameter +contains the Peer's Identity Type (i.e. 0x00 or 0x01). These parameters are +used to locate the corresponding local IRK in the resolving list; this IRK is used +to generate the own address used in the advertisement. +If directed advertising is performed, i.e. when Advertising_Type is set to 0x01 +(ADV_DIRECT_IND, high duty cycle) or 0x04 (ADV_DIRECT_IND, low duty +cycle mode), then the Peer_Address_Type and Peer_Address shall be valid. +If Own_Address_Type equals 0x02 or 0x03, the Controller generates the +peer's Resolvable Private Address using the peer's IRK corresponding to the +peer's Identity Address contained in the Peer_Address parameter and peer's +Identity Address Type (i.e. 0x00 or 0x01) contained in the Peer_Address_Type +parameter. +The Advertising_Channel_Map is a bit field that indicates the advertising +channels that shall be used when transmitting advertising packets. At least one +channel bit shall be set in the Advertising_Channel_Map parameter. +The Advertising_Filter_Policy parameter shall be ignored when directed +advertising is enabled. +The Host shall not issue this command when advertising is enabled in the +Controller; if it is the Command Disallowed error code shall be used. +If the advertising interval range provided by the Host (Advertising_Interval_Min, +Advertising_Interval_Max) is outside the advertising interval range supported +by the Controller, then the Controller shall return the Unsupported Feature or +Parameter Value (0x11) error code. + * @param Advertising_Interval_Min Minimum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Interval_Max Maximum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Type Advertising type. + * Values: + - 0x00: ADV_IND (Connectable undirected advertising) + - 0x01: ADV_DIRECT_IND, high duty cycle (Connectable high duty cycle directed advertising) + - 0x02: ADV_SCAN_IND (Scannable undirected advertising) + - 0x03: ADV_NONCONN_IND (Non connectable undirected advertising) + - 0x04: ADV_DIRECT_IND, low duty cycle (Connectable low duty cycle directed advertising) + * @param Own_Address_Type Own address type. + - 0x00: Public Device Address + - 0x01 Random Device Address + - 0x02: Controller generates Resolvable Private Address based on the local + IRK from resolving list. If resolving list contains no matching entry, + use public address. + - 0x03: Controller generates Resolvable Private Address based on the local + IRK from resolving list. If resolving list contains no matching entry, + use random address from LE_Set_Random_Address. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address or Public Address + - 0x03: Resolvable Private Address or Random Address + * @param Peer_Address_Type Peer Address type. + * Values: + - 0x00: Public Device Address or Public Identity Address + - 0x01: Random Device Address or Random (static) Identity Address + * @param Peer_Address Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the device to be connected. + * @param Advertising_Channel_Map Advertising channel map. +Default: 00000111b (all channels enabled). + * Flags: + - 0x01: ch 37 + - 0x02: ch 38 + - 0x04: ch 39 + * @param Advertising_Filter_Policy Advertising filter policy. + * Values: + - 0x00: Allow Scan Request from Any, Allow Connect Request from Any + - 0x01: Allow Scan Request from White List Only, Allow Connect Request from Any + - 0x02: Allow Scan Request from Any, Allow Connect Request from White List Only + - 0x03: Allow Scan Request from White List Only, Allow Connect Request from White List Only + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_advertising_parameters(uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max, + uint8_t Advertising_Type, + uint8_t Own_Address_Type, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Advertising_Channel_Map, + uint8_t Advertising_Filter_Policy); +/** + * @brief The LE_Read_Advertising_Channel_Tx_Power command is used by the Host +to read the transmit power level used for LE advertising channel packets. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.6) + * @param[out] Transmit_Power_Level Size: 1 Octet (signed integer) +Units: dBm +Accuracy: +/- 4 dBm + * Values: + - -20 ... 10 + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_advertising_channel_tx_power(uint8_t *Transmit_Power_Level); +/** + * @brief The LE_Set_Advertising_Data command is used to set the data used in advertising +packets that have a data field. +Only the significant part of the Advertising_Data is transmitted in the advertising +packets, as defined in [Vol 3] Part C, Section 11., +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.7) + * @param Advertising_Data_Length The number of significant octets in the following data field + * @param Advertising_Data 31 octets of data formatted as defined in [Vol 3] Part +C, Section 11. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_advertising_data(uint8_t Advertising_Data_Length, + uint8_t Advertising_Data[31]); +/** + * @brief This command is used to provide data used in Scanning Packets that have a +data field. +Only the significant part of the Scan_Response_Data is transmitted in the +Scanning Packets, as defined in [Vol 3] Part C, Section 11. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.8) + * @param Scan_Response_Data_Length The number of significant octets in the following data field + * @param Scan_Response_Data 31 octets of data formatted as defined in [Vol 3] Part +C, Section 11. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_scan_response_data(uint8_t Scan_Response_Data_Length, + uint8_t Scan_Response_Data[31]); +/** + * @brief The LE_Set_Advertise_Enable command is used to request the Controller to +start or stop advertising. The Controller manages the timing of advertisements +as per the advertising parameters given in the LE_Set_Advertising_Parameters +command. +The Controller shall continue advertising until the Host issues an LE_Set_Advertise_Enable +command with Advertising_Enable set to 0x00 (Advertising is +disabled) or until a connection is created or until the Advertising is timed out +due to high duty cycle Directed Advertising. In these cases, advertising is then +disabled. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.9) + * @param Advertising_Enable Enable/disable advertise. Default is 0 (disabled). + * Values: + - 0x00: Advertising is disabled + - 0x01: Advertising is enabled + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_advertise_enable(uint8_t Advertising_Enable); +/** + * @brief The LE_Set_Scan_Parameters command is used to set the scan parameters. +The LE_Scan_Type parameter controls the type of scan to perform. +The LE_Scan_Interval and LE_Scan_Window parameters are recommendations +from the Host on how long (LE_Scan_Window) and how frequently +(LE_Scan_Interval) the Controller should scan (See [Vol 6] Part B, Section +4.5.3). The LE_Scan_Window parameter shall always be set to a value smaller +or equal to the value set for the LE_Scan_Interval parameter. If they are set to +the same value scanning should be run continuously. +The Own_Address_Type parameter determines the address used (Public or +Random Device Address) when performing active scan. +The Host shall not issue this command when scanning is enabled in the Controller; +if it is the Command Disallowed error code shall be used. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.10) + * @param LE_Scan_Type Passive or active scanning. With active scanning SCAN_REQ packets are sent. + * Values: + - 0x00: Passive Scanning + - 0x01: Active scanning + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type. + - 0x00: Public Device Address + - 0x01 Random Device Address + - 0x02: Controller generates Resolvable Private Address based on the local + IRK from resolving list. If resolving list contains no matching entry, + use public address. + - 0x03: Controller generates Resolvable Private Address based on the local + IRK from resolving list. If resolving list contains no matching entry, + use random address from LE_Set_Random_Address. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address or Public Address + - 0x03: Resolvable Private Address or Random Address + * @param Scanning_Filter_Policy 0x00 Accept all advertisement packets. +Directed advertising packets which are not addressed for this device +shall be ignored. +0x01 Ignore advertisement packets from devices not in the White List Only. +Directed advertising packets which are not addressed for this device +shall be ignored +0x02 Accept all undirected advertisement packets. +Directed advertisement packets where initiator address is a RPA and +Directed advertisement packets addressed to this device shall be accepted. +0x03 Accept all undirected advertisement packets from devices that are in +the White List.Directed advertisement packets where initiator address is RPA and Directed advertisement packets addressed to this device shall be accepted. + * Values: + - 0x00: Accept all + - 0x01: Ignore devices not in the White List + - 0x02: Accept all (use resolving list) + - 0x03: Ignore devices not in the White List (use resolving list) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_scan_parameters(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy); +/** + * @brief The LE_Set_Scan_Enable command is used to start scanning. Scanning is +used to discover advertising devices nearby. +The Filter_Duplicates parameter controls whether the Link Layer shall filter +duplicate advertising reports to the Host, or if the Link Layer should generate +advertising reports for each packet received. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.11) + * @param LE_Scan_Enable Enable/disable scan. Default is 0 (disabled). + * Values: + - 0x00: Scanning disabled + - 0x01: Scanning enabled + * @param Filter_Duplicates Enable/disable duplicate filtering. + * Values: + - 0x00: Duplicate filtering disabled + - 0x01: Duplicate filtering enabled + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_scan_enable(uint8_t LE_Scan_Enable, + uint8_t Filter_Duplicates); +/** + * @brief The LE_Create_Connection command is used to create a Link Layer connection +to a connectable advertiser. +The LE_Scan_Interval and LE_Scan_Window parameters are recommendations +from the Host on how long (LE_Scan_Window) and how frequently +(LE_Scan_Interval) the Controller should scan. The LE_Scan_Window parameter +shall be set to a value smaller or equal to the value set for the LE_Scan_Interval +parameter. If both are set to the same value, scanning should run +continuously. +The Initiator_Filter_Policy is used to determine whether the White List is used. +If the White List is not used, the Peer_Address_Type and the Peer_Address +parameters specify the address type and address of the advertising device to +connect to. +The Link Layer shall set the address in the CONNECT_REQ packets to either +the Public Device Address or the Random Device Addressed based on the +Own_Address_Type parameter. +The Conn_Interval_Min and Conn_Interval_Max parameters define the minimum +and maximum allowed connection interval. The Conn_Interval_Min +parameter shall not be greater than the Conn_Interval_Max parameter. +The Conn_Latency parameter defines the maximum allowed connection +latency (see [Vol 6] Part B, Section 4.5.1). +The Supervision_Timeout parameter defines the link supervision timeout for +the connection. The Supervision_Timeout in milliseconds shall be larger than +(1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is +given in milliseconds. (See [Vol 6] Part B, Section 4.5.2). +The Minimum_CE_Length and Maximum_CE_Length parameters are informative +parameters providing the Controller with the expected minimum and maximum +length of the connection events. The Minimum_CE_Length parameter +shall be less than or equal to the Maximum_CE_Length parameter. +The Host shall not issue this command when another LE_Create_Connection +is pending in the Controller; if this does occur the Controller shall return the +Command Disallowed error code shall be used. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.12) + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Initiator_Filter_Policy 0x00 White list is not used to determine which advertiser to connect to. +Peer_Address_Type and Peer_Address shall be used. +0x01 White list is used to determine which advertiser to connect to. +Peer_Address_Type and Peer_Address shall be ignored. + * Values: + - 0x00: White list not used + - 0x01: White list used + * @param Peer_Address_Type 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + * @param Peer_Address Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising +device. + * @param Own_Address_Type Own address type. + - 0x00: Public Device Address + - 0x01 Random Device Address + - 0x02: Controller generates Resolvable Private Address based on the local + IRK from resolving list. If resolving list contains no matching entry, + use public address. + - 0x03: Controller generates Resolvable Private Address based on the local + IRK from resolving list. If resolving list contains no matching entry, + use random address from LE_Set_Random_Address. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address or Public Address + - 0x03: Resolvable Private Address or Random Address + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Initiator_Filter_Policy, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); +/** + * @brief The LE_Create_Connection_Cancel command is used to cancel the LE_Create_Connection +command. This command shall only be issued after the +LE_Create_Connection command has been issued, a Command Status event +has been received for the LE Create Connection command and before the LE +Connection Complete event. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.13) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_create_connection_cancel(void); +/** + * @brief The LE_Read_White_List_Size command is used to read the total number of +white list entries that can be stored in the Controller. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.14) + * @param[out] White_List_Size Total number of white list entries that can be stored in the Controller. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_white_list_size(uint8_t *White_List_Size); +/** + * @brief The LE_Clear_White_List command is used to clear the white list stored in the +Controller. +This command can be used at any time except when: +- the advertising filter policy uses the white list and advertising is enabled. +- the scanning filter policy uses the white list and scanning is enabled. +- the initiator filter policy uses the white list and an LE_Create_Connection +command is outstanding. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.15) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_clear_white_list(void); +/** + * @brief The LE_Add_Device_To_White_List command is used to add a single device +to the white list stored in the Controller. +This command can be used at any time except when: +- the advertising filter policy uses the white list and advertising is enabled. +- the scanning filter policy uses the white list and scanning is enabled. +- the initiator filter policy uses the white list and a create connection command +is outstanding. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.16) + * @param Address_Type Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + * @param Address Public Device Address or Random Device Address of the device +to be added to the white list. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_add_device_to_white_list(uint8_t Address_Type, + uint8_t Address[6]); +/** + * @brief The LE_Remove_Device_From_White_List command is used to remove a single +device from the white list stored in the Controller. +This command can be used at any time except when: +- the advertising filter policy uses the white list and advertising is enabled. +- the scanning filter policy uses the white list and scanning is enabled. +- the initiator filter policy uses the white list and a create connection command +is outstanding. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.17) + * @param Address_Type Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + * @param Address Public Device Address or Random Device Address of the device +to be removed from the white list. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_remove_device_from_white_list(uint8_t Address_Type, + uint8_t Address[6]); +/** + * @brief The LE_Connection_Update command is used to change the Link Layer connection +parameters of a connection. This command is supported only on master side. +The Conn_Interval_Min and Conn_Interval_Max parameters are used to define +the minimum and maximum allowed connection interval. The Conn_Interval_Min +parameter shall not be greater than the Conn_Interval_Max parameter. +The Conn_Latency parameter shall define the maximum allowed connection +latency. +The Supervision_Timeout parameter shall define the link supervision timeout +for the LE link. The Supervision_Timeout in milliseconds shall be larger than (1 ++ Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given +in milliseconds. +The Minimum_CE_Length and Maximum_CE_Length are information parameters +providing the Controller with a hint about the expected minimum and maximum +length of the connection events. The Minimum_CE_Length shall be less +than or equal to the Maximum_CE_Length. +The actual parameter values selected by the Link Layer may be different from +the parameter values provided by the Host through this command. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.18) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); +/** + * @brief The LE_Set_Host_Channel_Classification command allows the Host to specify +a channel classification for data channels based on its "local information". This +classification persists until overwritten with a subsequent LE_Set_Host_Channel_Classification +command or until the Controller is reset using the Reset +command (see [Vol 6] Part B, Section 4.5.8.1). +If this command is used, the Host should send it within 10 seconds of knowing +that the channel classification has changed. The interval between two successive +commands sent shall be at least one second. +This command shall only be used when the local device supports the Master +role. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.19) + * @param LE_Channel_Map This parameter contains 37 1-bit fields. +The nth such field (in the range 0 to 36) contains the value for the +link layer channel index n. +Channel n is bad = 0. +Channel n is unknown = 1. +The most significant bits are reserved and shall be set to 0. +At least one channel shall be marked as unknown. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_host_channel_classification(uint8_t LE_Channel_Map[5]); +/** + * @brief The LE_Read_Channel_Map command returns the current Channel_Map for +the specified Connection_Handle. The returned value indicates the state of the +Channel_Map specified by the last transmitted or received Channel_Map (in a +CONNECT_REQ or LL_CHANNEL_MAP_REQ message) for the specified +Connection_Handle, regardless of whether the Master has received an +acknowledgement. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.20) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param[out] LE_Channel_Map This parameter contains 37 1-bit fields. +The nth such field (in the range 0 to 36) contains the value for the +link layer channel index n. +Channel n is unused = 0. +Channel n is used = 1. +The most significant bits are reserved and shall be set to 0. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_channel_map(uint16_t Connection_Handle, + uint8_t LE_Channel_Map[5]); +/** + * @brief This command requests a list of the used LE features from the remote device. +This command shall return a list of the used LE features. For details see [Vol 6] +Part B, Section 4.6. +This command may be issued on both the master and slave. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.21) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_remote_used_features(uint16_t Connection_Handle); +/** + * @brief The LE_Encrypt command is used to request the Controller to encrypt the +Plaintext_Data in the command using the Key given in the command and +returns the Encrypted_Data to the Host. The AES-128 bit block cypher is +defined in NIST Publication FIPS-197 (http://csrc.nist.gov/publications/fips/ +fips197/fips-197.pdf). +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.22) + * @param Key 128 bit key for the encryption of the data given in the command. + * @param Plaintext_Data 128 bit data block that is requested to be encrypted. + * @param[out] Encrypted_Data 128 bit encrypted data block. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_encrypt(uint8_t Key[16], + uint8_t Plaintext_Data[16], + uint8_t Encrypted_Data[16]); +/** + * @brief The LE_Rand command is used to request the Controller to generate 8 octets +of random data to be sent to the Host. The Random_Number shall be generated +according to [Vol 2] Part H, Section 2 if the LE Feature (LL Encryption) is +supported. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.23) + * @param[out] Random_Number Random Number + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_rand(uint8_t Random_Number[8]); +/** + * @brief The LE_Start_Encryption command is used to authenticate the given encryption +key associated with the remote device specified by the connection handle, +and once authenticated will encrypt the connection. The parameters are as +defined in [Vol 3] Part H, Section 2.4.4. +If the connection is already encrypted then the Controller shall pause connection +encryption before attempting to authenticate the given encryption key, and +then re-encrypt the connection. While encryption is paused no user data shall +be transmitted. +On an authentication failure, the connection shall be automatically disconnected +by the Link Layer. If this command succeeds, then the connection shall +be encrypted. +This command shall only be used when the local device's role is Master. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.24) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Random_Number 64 bit random number. + * @param Encrypted_Diversifier 16 bit encrypted diversifier. + * @param Long_Term_Key 128 bit long term key. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_start_encryption(uint16_t Connection_Handle, + uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier, + uint8_t Long_Term_Key[16]); +/** + * @brief The LE_Long_Term_Key_Request_Reply command is used to reply to an LE +Long Term Key Request event from the Controller, and specifies the +Long_Term_Key parameter that shall be used for this Connection_Handle. The +Long_Term_Key is used as defined in [Vol 6] Part B, Section 5.1.3. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.25) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Long_Term_Key 128 bit long term key. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_long_term_key_request_reply(uint16_t Connection_Handle, + uint8_t Long_Term_Key[16]); +/** + * @brief The LE_Long_Term_Key_Request_Negative_Reply command is used to reply +to an LE Long Term Key Request event from the Controller if the Host cannot +provide a Long Term Key for this Connection_Handle. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.26) + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_long_term_key_requested_negative_reply(uint16_t Connection_Handle); +/** + * @brief The LE_Read_Supported_States command reads the states and state combinations +that the link layer supports. See [Vol 6] Part B, Section 1.1.1. +LE_States is an 8-octet bit field. If a bit is set to 1 then this state or state combination +is supported by the Controller. Multiple bits in LE_States may be set to 1 +to indicate support for multiple state and state combinations. +All the Advertising type with the Initiate State combinations shall be set only if +the corresponding Advertising types and Master Role combination are set. +All the Scanning types and the Initiate State combinations shall be set only if +the corresponding Scanning types and Master Role combination are set. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.27) + * @param[out] LE_States State or state combination is supported by the Controller. +See Core v4.1, Vol.2, part E, Ch. 7.8.27. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_supported_states(uint8_t LE_States[8]); +/** + * @brief The LE_Set_Data_Length command allows the Host to suggest maximum transmission packet size and maximum packet transmission time (connMaxTxOctets and connMaxTxTime - see [Vol 6] Part B, Section 4.5.10) to be used for a given connection. The Controller may use smaller or larger values based on local information. + * @param Connection_Handle Connection_Handle to be used to identify a connection. + * @param TxOctets Preferred maximum number of payload octets that the local Controller should include in a single Link Layer Data Channel PDU. +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF) Reserved for future use). Default: 27 bytes. + * @param TxTime Preferred maximum number of microseconds that the local Controller should use to transmit a single Link Layer Data Channel PDU. +Range 0x0148-0x0848 (0x0000 - 0x0147 and 0x0849 - 0xFFFF Reserved for future use). Default: 328 bytes. + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_data_length(uint16_t Connection_Handle, + uint16_t TxOctets, + uint16_t TxTime); +/** + * @brief The LE_Read_Suggested_Default_Data_Length command allows the Host to read the Host preferred values for the Controller maximum transmitted number of payload octets and maximum packet transmission time to be used for new connections (connInitialMaxTxOctets and connInitialMaxTxTime - see ([Vol 6] Part B, Section 4.5.10). + * @param[out] SuggestedMaxTxOctets The Host suggested value for the Controller maximum transmitted number of payload octets to be used for new connections - connInitialMaxTxOctets. +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) +Default: 0x001B + * @param[out] SuggestedMaxTxTime The Host suggested value for the Controller maximum packet transmission time to be used for new connections - connInitialMaxTx-Time. +Range 0x0148-0x0848 (0x0000 - 0x0147 and 0x0849 - 0xFFFF Reserved for future use) +Default: 0x0148 + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_suggested_default_data_length(uint16_t *SuggestedMaxTxOctets, + uint16_t *SuggestedMaxTxTime); +/** + * @brief The LE_Write_Suggested_Default_Data_Length command allows the Host to specify its preferred values for the Controller maximum transmission number of payload octets and maximum packet transmission time to be used for new connections (connInitialMaxTxOctets and connInitialMaxTxTime - see [Vol 6] Part B, Section 4.5.10). The Controller may use smaller or larger values based on local information. + * @param SuggestedMaxTxOctets The Host suggested value for the Controller maximum transmitted number of payload octets to be used for new connections - connInitialMaxTxOctets. +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param SuggestedMaxTxTime The Host suggested value for the Controller maximum packet transmission time to be used for new connections - connInitialMaxTx-Time. +Range 0x0148-0x0848 (0x0000 - 0x0147 and 0x0849 - 0xFFFF Reserved for future use) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_write_suggested_default_data_length(uint16_t SuggestedMaxTxOctets, + uint16_t SuggestedMaxTxTime); +/** + * @brief The LE_Read_Local_P-256_Public_Key command is used to return the local +P-256 public key from the Controller. The Controller shall generate a new P-256 public/private key pair upon receipt of this command. +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.36) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_local_p256_public_key(void); +/** + * @brief The LE_Generate_DHKey command is used to initiate generation of a Diffie- +Hellman key in the Controller for use over the LE transport. This command +takes the remote P-256 public key as input. The Diffie-Hellman key generation +uses the private key generated by LE_Read_Local_P256_Public_Key command. +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.37) + * @param Remote_P256_Public_Key The remote P-256 public key: +X, Y format +Octets 31-0: X co-ordinate +Octets 63-32: Y co-ordinate +Little Endian Format + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_generate_dhkey(uint8_t Remote_P256_Public_Key[64]); +/** + * @brief The LE_Add_Device_To_Resolving_List command is used to add one device +to the list of address translations used to resolve Resolvable Private Addresses +in the Controller. +This command cannot be used when address translation is enabled in the +Controller and: +- Advertising is enabled +- Scanning is enabled +- Create connection command is outstanding +This command can be used at any time when address translation is disabled in +the Controller. +When a Controller cannot add a device to the resolving list because the list is +full, it shall respond with error code 0x07 (Memory Capacity Exceeded). +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.38) + * @param Peer_Identity_Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param Peer_Identity_Address Public or Random (static) Identity address of the peer device + * @param Peer_IRK IRK of the peer device + * @param Local_IRK IRK of the local device + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_add_device_to_resolving_list(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6], + uint8_t Peer_IRK[16], + uint8_t Local_IRK[16]); +/** + * @brief The LE_Remove_Device_From_Resolving_List command is used to remove +one device from the list of address translations used to resolve Resolvable +Private Addresses in the controller. +This command cannot be used when address translation is enabled in the +Controller and: +- Advertising is enabled +- Scanning is enabled +- Create connection command is outstanding +This command can be used at any time when address translation is disabled in +the Controller. +When a Controller cannot remove a device from the resolving list because it is +not found, it shall respond with error code 0x02 (Unknown Connection +Identifier). +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.39) + * @param Peer_Identity_Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param Peer_Identity_Address Public or Random (static) Identity address of the peer device + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_remove_device_from_resolving_list(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6]); +/** + * @brief The LE_Clear_Resolving_List command is used to remove all devices from the +list of address translations used to resolve Resolvable Private Addresses in the +Controller. +This command cannot be used when address translation is enabled in the +Controller and: +- Advertising is enabled +- Scanning is enabled +- Create connection command is outstanding +This command can be used at any time when address translation is disabled in +the Controller. +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.40) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_clear_resolving_list(void); +/** + * @brief The LE_Read_Resolving_List_Size command is used to read the total number +of address translation entries in the resolving list that can be stored in the +Controller. +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.41) + * @param[out] Resolving_List_Size Number of address translation entries in the resolving list + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_resolving_list_size(uint8_t *Resolving_List_Size); +/** + * @brief The LE_Read_Peer_Resolvable_Address command is used to get the current +peer Resolvable Private Address being used for the corresponding peer Public +and Random (static) Identity Address. The peer's resolvable address being +used may change after the command is called. +This command can be used at any time. +When a Controller cannot find a Resolvable Private Address associated with +the Peer Identity Address, it shall respond with error code 0x02 (Unknown +Connection Identifier). +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.42) + * @param Peer_Identity_Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param Peer_Identity_Address Public or Random (static) Identity address of the peer device + * @param[out] Peer_Resolvable_Address Resolvable Private Address being used by the peer device + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_peer_resolvable_address(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6], + uint8_t Peer_Resolvable_Address[6]); +/** + * @brief The LE_Read_Local_Resolvable_Address command is used to get the current +local Resolvable Private Address being used for the corresponding peer +Identity Address. The local's resolvable address being used may change after +the command is called. +This command can be used at any time. +When a Controller cannot find a Resolvable Private Address associated with +the Peer Identity Address, it shall respond with error code 0x02 (Unknown +Connection Identifier). +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.43) + * @param Peer_Identity_Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param Peer_Identity_Address Public or Random (static) Identity address of the peer device + * @param[out] Local_Resolvable_Address Resolvable Private Address being used by the local device + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_local_resolvable_address(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6], + uint8_t Local_Resolvable_Address[6]); +/** + * @brief The LE_Set_Address_Resolution_Enable command is used to enable +resolution of Resolvable Private Addresses in the Controller. This causes the +Controller to use the resolving list whenever the Controller receives a local or +peer Resolvable Private Address. +This command can be used at any time except when: +- Advertising is enabled +- Scanning is enabled +- Create connection command is outstanding +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.44) + * @param Address_Resolution_Enable Enable/disable address resolution in the controller. +0x00: Address Resolution in controller disabled (default), +0x01: Address Resolution in controller enabled + * Values: + - 0x00: Address Resolution in controller disabled (default) + - 0x01: Address Resolution in controller enabled + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_address_resolution_enable(uint8_t Address_Resolution_Enable); +/** + * @brief The LE_Set_Resolvable_Private_Address_Timeout command set the length of +time the controller uses a Resolvable Private Address before a new resolvable +private address is generated and starts being used. +This timeout applies to all addresses generated by the controller. +(See Bluetooth Specification v.4.2, Vol. 2, Part E, 7.8.45) + * @param RPA_Timeout RPA_Timeout measured in seconds. +Range for N: 0x0001 - 0xA1B8 (1 sec - approximately 11.5 hours) +Default: N= 0x0384 (900 secs or 15 minutes) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_set_resolvable_private_address_timeout(uint16_t RPA_Timeout); +/** + * @brief The LE_Read_Maximum_Data_Length command allows the Host to read the Controller maximum supported payload octets and packet duration times for transmission and reception (supportedMaxTxOctets and supportedMaxTxTime, supportedMaxRxOctets, and supportedMaxRxTime, see [Vol 6] Part B, Section 4.5.10). + * @param[out] supportedMaxTxOctets Maximum number of payload octets that the local Controller supports for transmission of a single Link Layer Data Channel PDU. +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param[out] supportedMaxTxTime Maximum time, in microseconds, that the local Controller supports for transmission of a single Link Layer Data Channel PDU. +Range 0x0148-0x0848 (0x0000 - 0x0147 and 0x0849 - 0xFFFF Reserved for future use) + * @param[out] supportedMaxRxOctets Maximum number of payload octets that the local Controller supports for reception of a single Link Layer Data Channel PDU. +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param[out] supportedMaxRxTime Maximum time, in microseconds, that the local Controller supports for reception of a single Link Layer Data Channel PDU. +Range 0x0148-0x0848 (0x0000 - 0x0147 and 0x0849 - 0xFFFF Reserved for future use) + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_read_maximum_data_length(uint16_t *supportedMaxTxOctets, + uint16_t *supportedMaxTxTime, + uint16_t *supportedMaxRxOctets, + uint16_t *supportedMaxRxTime); +/** + * @} + */ +/** + *@defgroup HCI_TESTING_API HCI TESTING API + *@brief HCI TESTING API layer. + *@{ + */ +/** + * @brief This command is used to start a test where the DUT receives test reference +packets at a fixed interval. The tester generates the test reference packets. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.28) + * @param RX_Frequency N = (F - 2402) / 2 +Frequency Range : 2402 MHz to 2480 MHz + * Values: + - 0x00 ... 0x27 + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_receiver_test(uint8_t RX_Frequency); +/** + * @brief This command is used to start a test where the DUT generates test reference +packets at a fixed interval. The Controller shall transmit at maximum power. +An LE Controller supporting the LE_Transmitter_Test command shall support +Packet_Payload values 0x00, 0x01 and 0x02. An LE Controller may support +other values of Packet_Payload. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.29) + * @param TX_Frequency N = (F - 2402) / 2 + Frequency Range : 2402 MHz to 2480 MHz + * Values: + - 0x00 ... 0x27 + * @param Length_Of_Test_Data Length in bytes of payload data in each packet. + Supported ranges: + - (0x00,0x25): BlueNRG-1 and BlueNRG-2 with BLE stack version < 2.1 + - (0x00,0xFF): BlueNRG-2 with BLE stack version >= 2.1 and extended packet length. + * Values: + - 0x00 ... 0xFF + * @param Packet_Payload Type of packet payload. + * Values: + - 0x00: Pseudo-Random bit sequence 9 + - 0x01: Pattern of alternating bits '11110000' + - 0x02: Pattern of alternating bits '10101010' + - 0x03: Pseudo-Random bit sequence 15 + - 0x04: Pattern of All '1' bits + - 0x05: Pattern of All '0' bits + - 0x06: Pattern of alternating bits '00001111' + - 0x07: Pattern of alternating bits '0101' + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_transmitter_test(uint8_t TX_Frequency, + uint8_t Length_Of_Test_Data, + uint8_t Packet_Payload); +/** + * @brief This command is used to stop any test which is in progress. The Number_Of_Packets +for a transmitter test shall be reported as 0x0000. The Number_Of_Packets +is an unsigned number and contains the number of received +packets. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.8.30) + * @param[out] Number_Of_Packets Number of packets received + * @retval Value indicating success or error code. +*/ +tBleStatus hci_le_test_end(uint16_t *Number_Of_Packets); +/** + * @} + */ +/** + *@defgroup HAL_API HAL API + *@brief HAL API layer. + *@{ + */ +/** + * @brief This command returns the build number associated with the firmware version currently running + * @param[out] Build_Number Build number of the firmware. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_get_fw_build_number(uint16_t *Build_Number); +/** + * @brief This command writes a value to a low level configure data structure. It is useful to setup +directly some low level parameters for the system in the runtime.NOTE: This command shall not be called if a command different than Stack Init, HCI_RESET, ACI_HAL_WRITE_CONFIG_DATA or ACI_HAL_READ_CONFIG_DATA has already been called. + * @param Offset Offset of the element in the configuration data structure +which has to be written. The valid offsets are: + +- 0x00: Bluetooth public address, Value length to be written: 6 bytes +- 0x06: DIV used to derive CSRK, Value length to be written: 2 bytes +- 0x08: Encryption root key used to derive LTK and CSRK, Value length to be written: 16 bytes +- 0x18: Identity root key used to derive LTK and CSRK, Value length to be written: 16 bytes +- 0x2C: Link layer without host (for certification purposes), Value length to be written: 1 byte +- 0x2E: If set, the stack uses this address as the static random address instead of the one stored in NVM. +- 0x2F: Disable watchdog (1=disable, 0=enable). Value length to be written: 1 byte +- 0xD1: Set the maximum allowed parameter values for Data Length Extension: 8 bytes, 2 bytes for each of the following parameters: + supportedMaxTxOctets, supportedMaxTxTime, supportedMaxRxOctets, supportedMaxRxTime, in little-endian order. + (default 251,2120,251,2120). + * Values: + - 0x00: CONFIG_DATA_PUBADDR_OFFSET + - 0x06: CONFIG_DATA_DIV_OFFSET + - 0x08: CONFIG_DATA_ER_OFFSET + - 0x18: CONFIG_DATA_IR_OFFSET + - 0x2C: LL_WITHOUT_HOST + - 0x2E: CONFIG_DATA_STATIC_RANDOM_ADDRESS + - 0x2F: CONFIG_DATA_WATCHDOG_DISABLE + - 0xD1: CONFIG_DATA_DLE + * @param Length Length of data to be written + * @param Value Data to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_write_config_data(uint8_t Offset, + uint8_t Length, + uint8_t Value[]); +/** + * @brief This command requests the value in the low level configure data structure. +The number of read bytes changes for different Offset. + * @param Offset Offset of the element in the configuration data structure +which has to be read. The valid offsets are: + +* 0x00: Bluetooth public address, Value length returned: 6 bytes +* 0x06: DIV used to derive CSRK, Value length returned: 2 bytes +* 0x08: Encryption root key used to derive LTK and CSRK, Value length returned: 16 bytes +* 0x18: Identity root key used to derive LTK and CSRK, Value length returned: 16 bytes +* 0x2C: Link layer without host (for certification purposes), Value length returned: 1 byte +* 0x2F: Disable watchdog (1=disabled, 0=enable). Value length returned: 1 byte +* 0x80: The static random address stored in NVM. Value length returned: 6 bytes (read-only) + * Values: + - 0x00: CONFIG_DATA_PUBADDR_OFFSET + - 0x06: CONFIG_DATA_DIV_OFFSET + - 0x08: CONFIG_DATA_ER_OFFSET + - 0x18: CONFIG_DATA_IR_OFFSET + - 0x2C: LL_WITHOUT_HOST + - 0x2F: CONFIG_DATA_WATCHDOG_DISABLE + - 0x80: CONFIG_DATA_STORED_STATIC_RANDOM_ADDRESS + * @param[out] Data_Length Length of Data in octets + * @param[out] Data Data field associated with Offset parameter + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_read_config_data(uint8_t Offset, + uint8_t *Data_Length, + uint8_t Data[]); +/** + * @brief This command sets the TX power level of the device. By controlling the +EN_HIGH_POWER and the PA_LEVEL, the combination of the 2 determines the output +power level (dBm). +When the system starts up or reboots, the default TX power level will be used, which is the +maximum value of 8 dBm. Once this command is given, the output power will be changed +instantly, regardless if there is Bluetooth communication going on or not. For example, for +debugging purpose, the device can be set to advertise all the time. And use this +command to observe the signal strength changing. +The system will keep the last received TX power level from the command, i.e. the 2nd +command overwrites the previous TX power level. The new TX power level remains until +another Set TX Power command, or the system reboots. + * @param En_High_Power Enable High Power mode + * Values: + - 0x01: High Power + * @param PA_Level Power amplifier output level. Output power is indicative and it depends on the PCB layout and associated components + * Values: + - 0x00: -14 dBm (High Power) + - 0x01: -11 dBm (High Power) + - 0x02: -8 dBm (High Power) + - 0x03: -5 dBm (High Power) + - 0x04: -2 dBm (High Power) + - 0x05: 2 dBm (High Power) + - 0x06: 4 dBm (High Power) + - 0x07: 8 dBm (High Power) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_set_tx_power_level(uint8_t En_High_Power, + uint8_t PA_Level); +/** + * @brief This command returns the number of packets sent in Direct Test Mode. +When the Direct TX test is started, a 32-bit counter is used to count how many packets have been transmitted. +This command can be used to check how many packets have been sent during the Direct TX test. +The counter starts from 0 and counts upwards. The counter can wrap and start from 0 again. +The counter is not cleared until the next Direct TX test starts. + * @param[out] Number_Of_Packets Number of packets sent during the last Direct TX test. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_le_tx_test_packet_number(uint32_t *Number_Of_Packets); +/** + * @brief This command starts a carrier frequency, i.e. a tone, on a specific channel. The frequency +sine wave at the specific channel may be used for debugging purpose only. The channel ID +is a parameter from 0x00 to 0x27 for the 40 BLE channels, e.g. 0x00 for 2.402 GHz, 0x01 +for 2.404 GHz etc. +This command should not be used when normal Bluetooth activities are ongoing. +The tone should be stopped by @ref aci_hal_tone_stop command. + * @param RF_Channel BLE Channel ID, from 0x00 to 0x27 meaning (2.402 + 2*0xXX) GHz. + * Values: + - 0x00 ... 0x27 + * @param Offset Specify if the tone must be emitted with an offset from the channel center frequency. If 0, the tone is emitted at the channel center frequency. +If 1 or 2, the device will continuously emit the tone at the center frequency plus or minus 250 kHz respectively. + * Values: + - 0x00: 0 kHz offset + - 0x01: +250 kHz offset + - 0x02: -250 kHz offset + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_tone_start(uint8_t RF_Channel, + uint8_t Offset); +/** + * @brief This command is used to stop the previously started @ref aci_hal_tone_start command. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_tone_stop(void); +/** + * @brief This command returns the status of the 8 Bluetooth low energy links managed by the device + * @param[out] Link_Status Array of link status (8 links). Each link status is 1 byte. + * @param[out] Link_Connection_Handle Array of connection handles (2 bytes) for 8 links. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_get_link_status(uint8_t Link_Status[8], + uint16_t Link_Connection_Handle[16 / 2]); +/** + * @brief This command set the bitmask associated to @ref aci_hal_end_of_radio_activity_event. +Only the radio activities enabled in the mask will be reported to application by @ref aci_hal_end_of_radio_activity_event + * @param Radio_Activity_Mask Bitmask of radio events + * Flags: + - 0x0001: Idle + - 0x0002: Advertising + - 0x0004: Connection event slave + - 0x0008: Scanning + - 0x0010: Connection request + - 0x0020: Connection event master + - 0x0040: TX test mode + - 0x0080: RX test mode + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_set_radio_activity_mask(uint16_t Radio_Activity_Mask); +/** + * @brief This command returns information about the Anchor Period to help application in selecting + slot timings when operating in multi-link scenarios. + * @param[out] Anchor_Period Current anchor period. +T = N * 0.625 ms. + * @param[out] Max_Free_Slot Maximum available time that can be allocated for a new slot. +T = N * 0.625 ms. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_get_anchor_period(uint32_t *Anchor_Period, + uint32_t *Max_Free_Slot); +/** + * @brief + * @param Event_Mask Mask to enable/disable generation of HAL events + * Flags: + - 0x00000000: No events specified (Default) + - 0x00000001: ACI_HAL_SCAN_REQ_REPORT_EVENT + * @retval Value indicating success or error code. +*/ +tBleStatus aci_hal_set_event_mask(uint32_t Event_Mask); +/** + * @} + */ +/** + *@defgroup GAP_API GAP API + *@brief GAP API layer. + *@{ + */ +/** + * @brief Put the device in non-discoverable mode. This command disables the LL advertising. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_non_discoverable(void); +/** + * @brief Put the device in limited discoverable mode (as defined in Bluetooth Specification v.4.1, +Vol. 3, Part C, section 9.2.3). The device will be discoverable for maximum period of TGAP +(lim_adv_timeout) = 180 seconds (from errata). The advertising can be disabled at any time +by issuing @ref aci_gap_set_non_discoverable command. +The Adv_Interval_Min and Adv_Interval_Max parameters are optional. If both are set to 0, +the GAP will use default values for adv intervals for limited discoverable mode (250 ms +and 500 ms respectively). +To allow a fast connection, the host can set Local_Name, Service_Uuid_List, +Slave_Conn_Interval_Min and Slave_Conn_Interval_Max. If provided, these data will be +inserted into the advertising packet payload as AD data. These parameters are optional +in this command. These values can be set in advertised data using GAP_Update_Adv_Data +command separately. +The total size of data in advertising packet cannot exceed 31 bytes. +With this command, the BLE Stack will also add automatically the following +standard AD types: +- AD Flags +- Power Level +When advertising timeout happens (i.e. limited discovery period has elapsed), controller generates +@ref aci_gap_limited_discoverable_event event. + * @param Advertising_Type Advertising type. Advertising_Type type cannot be any of GAP_ADV_HIGH_DC_DIRECT_IND or GAP_ADV_HIGH_DC_DIRECT_IND. + * Values: + - 0x00: ADV_IND (Connectable undirected advertising) + - 0x01: ADV_DIRECT_IND (Connectable directed advertising) + - 0x02: ADV_SCAN_IND (Scannable undirected advertising) + - 0x03: ADV_NONCONN_IND (Non connectable undirected advertising) + * @param Advertising_Interval_Min Minimum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Interval_Max Maximum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Advertising_Filter_Policy Advertising filter policy: not applicable (the value of Advertising_Filter_Policy parameter is not used inside the Stack) + * @param Local_Name_Length Length of the local_name field in octets. +If length is set to 0x00, Local_Name parameter is not used. + * @param Local_Name Local name of the device. First byte must be 0x08 for Shortened Local Name +or 0x09 for Complete Local Name. No NULL character at the end. + * @param Service_Uuid_length Length of the Service Uuid List in octets. +If there is no service to be advertised, set this field to 0x00. + * @param Service_Uuid_List This is the list of the UUIDs as defined in Volume 3, +Section 11 of GAP Specification. First byte is the AD Type. +See also Supplement to the Bluetooth Core specification. + * @param Slave_Conn_Interval_Min Slave connection interval minimum value suggested by Peripheral. +If Slave_Conn_Interval_Min and Slave_Conn_Interval_Max are not 0x0000, +Slave Connection Interval Range AD structure will be added in advertising +data. +Connection interval is defined in the following manner: +connIntervalmin = Slave_Conn_Interval_Min x 1.25ms. + * Values: + - 0x0000 (NaN) + - 0xFFFF (NaN) : No specific minimum + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Slave_Conn_Interval_Max Slave connection interval maximum value suggested by Peripheral. +If Slave_Conn_Interval_Min and Slave_Conn_Interval_Max are not 0x0000, +Slave Connection Interval Range AD structure will be added in advertising +data. +Connection interval is defined in the following manner: +connIntervalmax = Slave_Conn_Interval_Max x 1.25ms + * Values: + - 0x0000 (NaN) + - 0xFFFF (NaN) : No specific maximum + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_limited_discoverable(uint8_t Advertising_Type, + uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max, + uint8_t Own_Address_Type, + uint8_t Advertising_Filter_Policy, + uint8_t Local_Name_Length, + uint8_t Local_Name[], + uint8_t Service_Uuid_length, + uint8_t Service_Uuid_List[], + uint16_t Slave_Conn_Interval_Min, + uint16_t Slave_Conn_Interval_Max); +/** + * @brief Put the device in general discoverable mode (as defined in Bluetooth Specification v.4.1, +Vol. 3, Part C, section 9.2.4). The device will be discoverable until the host issues +the @ref aci_gap_set_non_discoverable command. The Adv_Interval_Min and Adv_Interval_Max +parameters are optional. If both are set to 0, the GAP uses the default values for adv +intervals for general discoverable mode. +When using connectable undirected advertising events: +- Adv_Interval_Min = 30 ms +- Adv_Interval_Max = 60 ms +When using non-connectable advertising events or scannable undirected advertising events: +- Adv_Interval_Min = 100 ms +- Adv_Interval_Max = 150 ms +Host can set the Local Name, a Service UUID list and the Slave Connection Interval Range. +If provided, these data will be inserted into the advertising packet payload as AD data. +These parameters are optional in this command. These values can be also set using +aci_gap_update_adv_data() separately. +The total size of data in advertising packet cannot exceed 31 bytes. +With this command, the BLE Stack will also add automatically the following standard +AD types: +- AD Flags +- TX Power Level + * @param Advertising_Type Advertising type. Advertising_Type type cannot be any of GAP_ADV_HIGH_DC_DIRECT_IND or GAP_ADV_HIGH_DC_DIRECT_IND. + * Values: + - 0x00: ADV_IND (Connectable undirected advertising) + - 0x01: ADV_DIRECT_IND (Connectable directed advertising) + - 0x02: ADV_SCAN_IND (Scannable undirected advertising) + - 0x03: ADV_NONCONN_IND (Non connectable undirected advertising) + * @param Advertising_Interval_Min Minimum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Interval_Max Maximum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Advertising_Filter_Policy Advertising filter policy: not applicable (the value of Advertising_Filter_Policy parameter is not used inside the Stack) + * @param Local_Name_Length Length of the local_name field in octets. +If length is set to 0x00, Local_Name parameter is not used. + * @param Local_Name Local name of the device. First byte must be 0x08 for Shortened Local Name +or 0x09 for Complete Local Name. No NULL character at the end. + * @param Service_Uuid_length Length of the Service Uuid List in octets. +If there is no service to be advertised, set this field to 0x00. + * @param Service_Uuid_List This is the list of the UUIDs as defined in Volume 3, +Section 11 of GAP Specification. First byte is the AD Type. +See also Supplement to the Bluetooth Core specification. + * @param Slave_Conn_Interval_Min Slave connection interval minimum value suggested by Peripheral. +If Slave_Conn_Interval_Min and Slave_Conn_Interval_Max are not 0x0000, +Slave Connection Interval Range AD structure will be added in advertising +data. +Connection interval is defined in the following manner: +connIntervalmin = Slave_Conn_Interval_Min x 1.25ms. + * Values: + - 0x0000 (NaN) + - 0xFFFF (NaN) : No specific minimum + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Slave_Conn_Interval_Max Slave connection interval maximum value suggested by Peripheral. +If Slave_Conn_Interval_Min and Slave_Conn_Interval_Max are not 0x0000, +Slave Connection Interval Range AD structure will be added in advertising +data. +Connection interval is defined in the following manner: +connIntervalmax = Slave_Conn_Interval_Max x 1.25ms + * Values: + - 0x0000 (NaN) + - 0xFFFF (NaN) : No specific maximum + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_discoverable(uint8_t Advertising_Type, + uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max, + uint8_t Own_Address_Type, + uint8_t Advertising_Filter_Policy, + uint8_t Local_Name_Length, + uint8_t Local_Name[], + uint8_t Service_Uuid_length, + uint8_t Service_Uuid_List[], + uint16_t Slave_Conn_Interval_Min, + uint16_t Slave_Conn_Interval_Max); +/** + * @brief + Set the device in direct connectable mode (as defined in Bluetooth Specification v.4.1, +Vol. 3, Part C, section 9.3.3). Device uses direct connectable mode to advertise using High Duty +cycle advertisement events or Low Duty cycle advertisement events and the address as +either what is specified in the Own Address Type parameter. The command specifies the type of the advertising used. +If the privacy is enabled, the Type parameter in reconnection address is used for advertising, otherwise the address +of the type specified in OwnAddrType is used. +The device will be in directed connectable mode only for 1.28 seconds. If no connection +is established within this duration, the device enters non discoverable mode and +advertising will have to be again enabled explicitly. +The controller generates a @ref hci_le_connection_complete_event event with the status set to +0x3C (Directed Advertising Timeout) if the connection was not established and 0x00 if the +connection was successfully established. +If Host privacy (i.e. privacy 1.1) is enabled this command returns BLE_STATUS_INVALID_PARAMS. + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (only if privacy is disabled) + - 0x01: Random Device Address (only if privacy is disabled) + - 0x02: Resolvable Private Address (only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + * @param Directed_Advertising_Type Type of directed advertising. + * Values: + - 0x01: High Duty Cycle Directed Advertising + - 0x04: Low Duty Cycle Directed Advertising + * @param Direct_Address_Type Peer Address type. + * Values: + - 0x00: Public Device Address or Public Identity Address + - 0x01: Random Device Address or Random (static) Identity Address + * @param Direct_Address Initiator Bluetooth address + * @param Advertising_Interval_Min Minimum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Interval_Max Maximum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_direct_connectable(uint8_t Own_Address_Type, + uint8_t Directed_Advertising_Type, + uint8_t Direct_Address_Type, + uint8_t Direct_Address[6], + uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max); +/** + * @brief Set the IO capabilities of the device. This command has to be given only when the device is +not in a connected state. + + * @param IO_Capability IO capability of the device. + * Values: + - 0x00: IO_CAP_DISPLAY_ONLY + - 0x01: IO_CAP_DISPLAY_YES_NO + - 0x02: IO_CAP_KEYBOARD_ONLY + - 0x03: IO_CAP_NO_INPUT_NO_OUTPUT + - 0x04: IO_CAP_KEYBOARD_DISPLAY + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_io_capability(uint8_t IO_Capability); +/** + * @brief Set the authentication requirements for the device. This command has to be +given only when the device is not in a connected state. + * @param Bonding_Mode Bonding mode. +Only if bonding is enabled (0x01), the bonding +information is stored in flash + * Values: + - 0x00: No-bonding mode + - 0x01: Bonding mode + * @param MITM_Mode MITM mode. + * Values: + - 0x00: MITM protection not required + - 0x01: MITM protection required + * @param SC_Support LE Secure connections support + * Values: + - 0x00: Secure Connections Pairing not supported + - 0x01: Secure Connections Pairing supported but optional + - 0x02: Secure Connections Pairing supported and mandatory (SC Only Mode) + * @param KeyPress_Notification_Support Keypress notification support + * Values: + - 0x00: Keypress notification not supported + - 0x01: Keypress notification supported + * @param Min_Encryption_Key_Size Minimum encryption key size to be used during pairing + * @param Max_Encryption_Key_Size Maximum encryption key size to be used during pairing + * @param Use_Fixed_Pin Use or not fixed pin. If set to 0x00, then during the pairing process +the application will not be requested for a pin (Fixed_Pin will be used). +If set to 0x01, then during pairing process if a +passkey is required the application will be +notified + * Values: + - 0x00: use a fixed pin + - 0x01: do not use a fixed pin + * @param Fixed_Pin Fixed pin to be used during pairing if MIMT protection is enabled. +Any random value between 0 to 999999 + * Values: + - 0 ... 999999 + * @param Identity_Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_authentication_requirement(uint8_t Bonding_Mode, + uint8_t MITM_Mode, + uint8_t SC_Support, + uint8_t KeyPress_Notification_Support, + uint8_t Min_Encryption_Key_Size, + uint8_t Max_Encryption_Key_Size, + uint8_t Use_Fixed_Pin, + uint32_t Fixed_Pin, + uint8_t Identity_Address_Type); +/** + * @brief Set the authorization requirements of the device. This command has to be given when connected +to a device if authorization is required to access services which require authorization. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Authorization_Enable Enable the authorization in the device +and when a remote device tries to read/write a characteristic with authorization +requirements, the stack will send back an error response with +"Insufficient authorization" error code. After pairing is complete a +ACI_GAP_AUTHORIZATION_REQ_EVENT will be sent to the Host. + * Values: + - 0x00: Authorization not required + - 0x01: Authorization required + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_authorization_requirement(uint16_t Connection_Handle, + uint8_t Authorization_Enable); +/** + * @brief This command should be send by the host in response to @ref aci_gap_pass_key_req_event +event. The command parameter contains the pass key which will be used during the pairing +process. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Pass_Key Pass key that will be used during the pairing process. +Must be a six-digit decimal number. + * Values: + - 0 ... 999999 + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_pass_key_resp(uint16_t Connection_Handle, + uint32_t Pass_Key); +/** + * @brief Authorize a device to access attributes. This command should be send by the host in +response to @ref aci_gap_authorization_req_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Authorize Authorization response. + * Values: + - 0x01: Authorize + - 0x02: Reject + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_authorization_resp(uint16_t Connection_Handle, + uint8_t Authorize); +/** + * @brief Initialize the GAP layer. Register the GAP service with the GATT. +All the standard GAP characteristics will also be added: +- Device Name +- Appearance +- Peripheral Preferred Connection Parameters (peripheral role only) + * @param Role Bitmap of allowed roles. + * Flags: + - 0x01: Peripheral + - 0x02: Broadcaster + - 0x04: Central + - 0x08: Observer + * @param privacy_enabled Specify if privacy is enabled or not and which one . + * Values: + - 0x00: Privacy disabled + - 0x01: Privacy host enabled + - 0x02: Privacy controller enabled + * @param device_name_char_len Length of the device name characteristic + * @param[out] Service_Handle Handle of the GAP service + * @param[out] Dev_Name_Char_Handle Device Name Characteristic handle + * @param[out] Appearance_Char_Handle Appearance Characteristic handle + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_init(uint8_t Role, + uint8_t privacy_enabled, + uint8_t device_name_char_len, + uint16_t *Service_Handle, + uint16_t *Dev_Name_Char_Handle, + uint16_t *Appearance_Char_Handle); +/** + * @brief Put the device into non connectable mode. This mode does not support connection. The +privacy setting done in the @ref aci_gap_init command plays a role in deciding the valid +parameters for this command. +Advertiser filter policy is internally set to 0x00 + * @param Advertising_Event_Type Advertising type. + * Values: + - 0x02: ADV_SCAN_IND (Scannable undirected advertising) + - 0x03: ADV_NONCONN_IND (Non connectable undirected advertising) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_non_connectable(uint8_t Advertising_Event_Type, + uint8_t Own_Address_Type); +/** + * @brief Put the device into undirected connectable mode. +If privacy is enabled in the device, a resolvable private address is generated and used as the +advertiser's address. If not, the address of the type specified in own_addr_type is used for +advertising. + * @param Advertising_Interval_Min Minimum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Interval_Max Maximum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if controller privacy is enabled or if Host privacy (i.e. privacy 1.1) is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if Host privacy (i.e. privacy 1.1) is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Adv_Filter_Policy Advertising filter policy. + * Values: + - 0x00: Allow Scan Request from Any, Allow Connect Request from Any + - 0x03: Allow Scan Request from White List Only, Allow Connect Request from White List Only + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_undirected_connectable(uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max, + uint8_t Own_Address_Type, + uint8_t Adv_Filter_Policy); +/** + * @brief Send a slave security request to the master. +This command has to be issued to notify the master of the security requirements of the slave. +The master may encrypt the link, initiate the pairing procedure, or reject the request. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_slave_security_req(uint16_t Connection_Handle); +/** + * @brief This command can be used to update the advertising data for a particular AD type. If the AD +type specified does not exist, then it is added to the advertising data. If the overall +advertising data length is more than 31 octets after the update, then the command is +rejected and the old data is retained. + * @param AdvDataLen Length of AdvData in octets + * @param AdvData Advertising data used by the device while advertising. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_update_adv_data(uint8_t AdvDataLen, + uint8_t AdvData[]); +/** + * @brief This command can be used to delete the specified AD type from the advertisement data if +present. + * @param ADType One of the AD types like in Bluetooth specification (see volume 3, Part C, 11.1) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_delete_ad_type(uint8_t ADType); +/** + * @brief This command can be used to get the current security settings of the device. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param[out] Security_Mode Security mode. + * Values: + - 0x01: Security Mode 1 + - 0x02: Security Mode 2 + * @param[out] Security_Level Security Level. + * Values: + - 0x01: Security Level 1 + - 0x02: Security Level 2 + - 0x03: Security Level 3 + - 0x04: Security Level 4 + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_get_security_level(uint16_t Connection_Handle, + uint8_t *Security_Mode, + uint8_t *Security_Level); +/** + * @brief It allows masking events from the GAP. The default configuration is all the events masked. + * @param GAP_Evt_Mask GAP event mask. Default: 0xFFFF. + * Flags: + - 0x0000: No events + - 0x0001: ACI_GAP_LIMITED_DISCOVERABLE_EVENT + - 0x0002: ACI_GAP_PAIRING_COMPLETE_EVENT + - 0x0004: ACI_GAP_PASS_KEY_REQ_EVENT + - 0x0008: ACI_GAP_AUTHORIZATION_REQ_EVENT + - 0x0010: ACI_GAP_SLAVE_SECURITY_INITIATED_EVENT + - 0x0020: ACI_GAP_BOND_LOST_EVENT + - 0x0080: ACI_GAP_PROC_COMPLETE_EVENT + - 0x0100: ACI_L2CAP_CONNECTION_UPDATE_REQ_EVENT + - 0x0200: ACI_L2CAP_CONNECTION_UPDATE_RESP_EVENT + - 0x0400: ACI_L2CAP_PROC_TIMEOUT_EVENT + - 0x0800: ACI_GAP_ADDR_NOT_RESOLVED_EVENT + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_event_mask(uint16_t GAP_Evt_Mask); +/** + * @brief Add addresses of bonded devices into the controller's whitelist. +The command will return an error if there are no devices in the database or if it was +unable to add the device into the whitelist. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_configure_whitelist(void); +/** + * @brief Command the controller to terminate the connection. +A @ref hci_disconnection_complete_event event will be generated when the link is disconnected. It is important to leave an 100 ms blank window +before sending any new command (including system hardware reset), since immediately after @ref hci_disconnection_complete_event event, +system could save important information in non volatile memory. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Reason The reason for ending the connection. + * Values: + - 0x05: Authentication Failure + - 0x13: Remote User Terminated Connection + - 0x14: Remote Device Terminated Connection due to Low Resources + - 0x15: Remote Device Terminated Connection due to Power Off + - 0x1A: Unsupported Remote Feature + - 0x3B: Unacceptable Connection Parameters + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_terminate(uint16_t Connection_Handle, + uint8_t Reason); +/** + * @brief Clear the security database. All the devices in the security database will be removed. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_clear_security_db(void); +/** + * @brief Allows the security manager to complete the pairing procedure and re-bond with the master. +This command should be given by the application when it receives the +ACI_GAP_BOND_LOST_EVENT if it wants the re-bonding to happen successfully. If this +command is not given on receiving the event, the bonding procedure will timeout. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_allow_rebond(uint16_t Connection_Handle); +/** + * @brief Start the limited discovery procedure. The controller is commanded to start active scanning. +When this procedure is started, only the devices in limited discoverable mode are returned +to the upper layers. +The procedure is terminated when either the upper layers issue a command to terminate +the procedure by issuing the command @ref aci_gap_terminate_gap_proc with the procedure +code set to 0x01 or a timeout happens. When the procedure is terminated due to any of the +above reasons, @ref aci_gap_proc_complete_event event is returned with the procedure code +set to 0x01. +The device found when the procedure is ongoing is returned to the upper layers through the +event @ref hci_le_advertising_report_event. + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Filter_Duplicates Enable/disable duplicate filtering. + * Values: + - 0x00: Duplicate filtering disabled + - 0x01: Duplicate filtering enabled + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_limited_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates); +/** + * @brief Start the general discovery procedure. The controller is commanded to start active +scanning. The procedure is terminated when either the upper layers issue a command +to terminate the procedure by issuing the command @ref aci_gap_terminate_gap_proc +with the procedure code set to 0x02 or a timeout happens. When the procedure is +terminated due to any of the above reasons, @ref aci_gap_proc_complete_event event +is returned with the procedure code set to 0x02. The device found when the procedure +is ongoing is returned to @ref hci_le_advertising_report_event. + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Filter_Duplicates Enable/disable duplicate filtering. + * Values: + - 0x00: Duplicate filtering disabled + - 0x01: Duplicate filtering enabled + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_general_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates); +/** + * @brief Start the name discovery procedure. A LE_Create_Connection call will be made to the +controller by GAP with the initiator filter policy set to "ignore whitelist and process +connectable advertising packets only for the specified device". Once a connection is +established, GATT procedure is started to read the device name characteristic. When the +read is completed (successfully or unsuccessfully), a @ref aci_gap_proc_complete_event +event is given to the upper layer. The event also contains the name of the device if the +device name was read successfully. + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Peer_Address_Type Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + * @param Peer_Address Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising +device. + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_name_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); +/** + * @brief Start the auto connection establishment procedure. The devices specified are added to the +white list of the controller and a LE_Create_Connection call will be made to the controller by +GAP with the initiator filter policy set to "use whitelist to determine which advertiser to +connect to". When a command is issued to terminate the procedure by upper layer, a +LE_Create_Connection_Cancel call will be made to the controller by GAP. +The procedure is terminated when either a connection is successfully established with one of +the specified devices in the white list or the procedure is explicitly terminated by issuing +the command @ref aci_gap_terminate_gap_proc with the procedure code set to 0x08. A +@ref aci_gap_proc_complete_event event is returned with the procedure code set to 0x08. +If controller privacy is enabled and the peer device (advertiser) is in the resolving list then + the link layer will generate a RPA, if it is not then the RPA/NRPA generated by the Host will be used. + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @param Num_of_Whitelist_Entries Number of devices that have to be added to the whitelist. + * @param Whitelist_Entry See @ref Whitelist_Entry_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_auto_connection_establish_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]); +/** + * @brief Start a general connection establishment procedure. The host enables scanning in the +controller with the scanner filter policy set to "accept all advertising packets" and from the +scanning results, all the devices are sent to the upper layer using the event +LE_Advertising_Report. The upper layer then has to select one of the devices to which it +wants to connect by issuing the command @ref aci_gap_create_connection. If privacy is +enabled, then either a private resolvable address or a non resolvable address, based on the +address type specified in the command is set as the scanner address but the gap create +connection always uses a private resolvable address if the general connection +establishment procedure is active. +The procedure is terminated when a connection is established or the upper layer terminates +the procedure by issuing the command @ref aci_gap_terminate_gap_proc with the procedure +code set to 0x10. On completion of the procedure a @ref aci_gap_proc_complete_event event +is generated with the procedure code set to 0x10. +If controller privacy is enabled and the peer device (advertiser) is in the resolving list then +the link layer will generate a RPA, if it is not then the RPA/NRPA generated by the Host will be used. + * @param LE_Scan_Type Passive or active scanning. With active scanning SCAN_REQ packets are sent. + * Values: + - 0x00: Passive Scanning + - 0x01: Active scanning + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Scanning_Filter_Policy Scanning filter policy: + - 0x00 Accept all advertisement packets.Directed advertising packets which are not addressed for this device shall be ignored. + - 0x01 Ignore advertisement packets from devices not in the White List Only.Directed advertising packets which are not addressed for this device shall be ignored. + - 0x02 Accept all undirected advertisement packets (it is allowed only if controller privacy or host privacy is enabled).Directed advertisement packets where initiator address is a RPA and Directed advertisement packets addressed to this device shall be accepted. + - 0x03 Accept all undirected advertisement packets from devices that are in the White List.Directed advertisement packets where initiator address is RPA and Directed advertisement packets addressed to this device shall be accepted. + - NOTE: if controller privacy is enabled Scanning_Filter_Policy can only assume values 0x00 or 0x02; if Host privacy is enabled Scanning_Filter_Policy can only assume value 0x00. + * Values: + - 0x00: Accept all + - 0x01: Ignore devices not in the White List + - 0x02: Accept all (use resolving list) + - 0x03: Ignore devices not in the White List (use resolving list) + * @param Filter_Duplicates Enable/disable duplicate filtering. + * Values: + - 0x00: Duplicate filtering disabled + - 0x01: Duplicate filtering enabled + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_general_connection_establish_proc(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy, + uint8_t Filter_Duplicates); +/** + * @brief Start a selective connection establishment procedure. The GAP adds the specified device +addresses into white list and enables scanning in the controller with the scanner filter policy +set to "accept packets only from devices in whitelist". All the devices found are sent to the +upper layer by the event @ref hci_le_advertising_report_event. The upper layer then has to select one of +the devices to which it wants to connect by issuing the command @ref aci_gap_create_connection. +On completion of the procedure a @ref aci_gap_proc_complete_event event is generated with +the procedure code set to 0x20. The procedure is terminated when a connection is established +or the upper layer terminates the procedure by issuing the command +@ref aci_gap_terminate_gap_proc with the procedure code set to 0x20. +If controller privacy is enabled and the peer device (advertiser) is in the resolving list then + the link layer will generate a RPA, if it is not then the RPA/NRPA generated by the Host will be used. + * @param LE_Scan_Type Passive or active scanning. With active scanning SCAN_REQ packets are sent. + * Values: + - 0x00: Passive Scanning + - 0x01: Active scanning + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Scanning_Filter_Policy Scanning filter policy: + - 0x00 Accept all advertisement packets.Directed advertising packets which are not addressed for this device shall be ignored. + - 0x01 Ignore advertisement packets from devices not in the White List Only.Directed advertising packets which are not addressed for this device shall be ignored. + - 0x02 Accept all undirected advertisement packets (it is allowed only if controller privacy or host privacy is enabled).Directed advertisement packets where initiator address is a RPA and Directed advertisement packets addressed to this device shall be accepted. + - 0x03 Accept all undirected advertisement packets from devices that are in the White List.Directed advertisement packets where initiator address is RPA and Directed advertisement packets addressed to this device shall be accepted. + - NOTE: if controller privacy is enabled Scanning_Filter_Policy can only assume values 0x01 or 0x03; if Host privacy is enabled Scanning_Filter_Policy can only assume value 0x01. + * Values: + - 0x00: Accept all + - 0x01: Ignore devices not in the White List + - 0x02: Accept all (use resolving list) + - 0x03: Ignore devices not in the White List (use resolving list) + * @param Filter_Duplicates Enable/disable duplicate filtering. + * Values: + - 0x00: Duplicate filtering disabled + - 0x01: Duplicate filtering enabled + * @param Num_of_Whitelist_Entries Number of devices that have to be added to the whitelist. + * @param Whitelist_Entry See @ref Whitelist_Entry_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_selective_connection_establish_proc(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy, + uint8_t Filter_Duplicates, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]); +/** + * @brief Start the direct connection establishment procedure. A LE_Create_Connection call will be +made to the controller by GAP with the initiator filter policy set to "ignore whitelist and +process connectable advertising packets only for the specified device". The procedure can +be terminated explicitly by the upper layer by issuing the command +@ref aci_gap_terminate_gap_proc. When a command is issued to terminate the +procedure by upper layer, a @ref hci_le_create_connection_cancel call will be made to the +controller by GAP. +On termination of the procedure, a @ref hci_le_connection_complete_event event is returned. The +procedure can be explicitly terminated by the upper layer by issuing the command +@ref aci_gap_terminate_gap_proc with the procedure_code set to 0x40. +If controller privacy is enabled and the peer device (advertiser) is in the resolving list then +the link layer will generate a RPA, if it is not then the RPA/NRPA generated by the Host will be used. + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param Peer_Address_Type Peer Address type. + * Values: + - 0x00: Public Device Address or Public Identity Address + - 0x01: Random Device Address or Random (static) Identity Address + * @param Peer_Address Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising +device. + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); +/** + * @brief Terminate the specified GATT procedure. An @ref aci_gap_proc_complete_event event is +returned with the procedure code set to the corresponding procedure. + * @param Procedure_Code GAP procedure bitmap. + * Values: + - 0x00: No events + - 0x01: LIMITED_DISCOVERY_PROC + - 0x02: GENERAL_DISCOVERY_PROC + - 0x04: NAME_DISCOVERY_PROC + - 0x08: AUTO_CONNECTION_ESTABLISHMENT_PROC + - 0x10: GENERAL_CONNECTION_ESTABLISHMENT_PROC + - 0x20: SELECTIVE_CONNECTION_ESTABLISHMENT_PROC + - 0x40: DIRECT_CONNECTION_ESTABLISHMENT_PROC + - 0x80: OBSERVATION_PROC + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_terminate_gap_proc(uint8_t Procedure_Code); +/** + * @brief Start the connection update procedure (only when role is Master). A @ref hci_le_connection_update is called. +On completion of the procedure, an @ref hci_le_connection_update_complete_event event is returned to +the upper layer. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); +/** + * @brief Send the SM pairing request to start a pairing process. The authentication requirements and +IO capabilities should be set before issuing this command using the +@ref aci_gap_set_io_capability and @ref aci_gap_set_authentication_requirement commands. +A @ref aci_gap_pairing_complete_event event is returned after the pairing process is completed. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Force_Rebond If 1, Pairing request will be sent even if the device was previously bonded, + otherwise pairing request is not sent. + * Values: + - 0x00: NO + - 0x01: YES + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_send_pairing_req(uint16_t Connection_Handle, + uint8_t Force_Rebond); +/** + * @brief This command tries to resolve the address provided with the IRKs present in its database. If +the address is resolved successfully with any one of the IRKs present in the database, it +returns success and also the corresponding public/static random address stored with the +IRK in the database. + * @param Address Address to be resolved + * @param[out] Actual_Address The public or static random address of the peer device, distributed during pairing phase. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_resolve_private_addr(uint8_t Address[6], + uint8_t Actual_Address[6]); +/** + * @brief This command puts the device into broadcast mode. A privacy enabled device uses either a +resolvable private address or a non-resolvable private address as specified in the +Own_Addr_Type parameter of the command. + * @param Advertising_Interval_Min Minimum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Interval_Max Maximum advertising interval. +Time = N * 0.625 msec. + * Values: + - 0x0020 (20.000 ms) ... 0x4000 (10240.000 ms) + * @param Advertising_Type Non connectable advertising type + * Values: + - 0x02: ADV_SCAN_IND (Scannable undirected advertising) + - 0x03: ADV_NONCONN_IND (Non connectable undirected advertising) + * @param Own_Address_Type If Privacy is disabled, then the address can be public or static random. +If Privacy is enabled, then the address can be a resolvable private address or a non-resolvable private address. + * Values: + - 0x00: Public address + - 0x01: Static random address + - 0x02: Resolvable private address + - 0x03: Non-resolvable private address + * @param Adv_Data_Length Length of the advertising data in the advertising packet. + * @param Adv_Data Advertising data used by the device while advertising. + * @param Num_of_Whitelist_Entries Number of devices that have to be added to the whitelist. + * @param Whitelist_Entry See @ref Whitelist_Entry_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_broadcast_mode(uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max, + uint8_t Advertising_Type, + uint8_t Own_Address_Type, + uint8_t Adv_Data_Length, + uint8_t Adv_Data[], + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]); +/** + * @brief Starts an Observation procedure, when the device is in Observer Role. The host enables +scanning in the controller. The advertising reports are sent to the upper layer using standard +LE Advertising Report Event. (See Bluetooth Core v4.1, Vol. 2, part E, Ch. 7.7.65.2, LE +Advertising Report Event). +If controller privacy is enabled and the peer device (advertiser) is in the resolving list then +the link layer will generate a RPA, if it is not then the RPA/NRPA generated by the Host will be used. + * @param LE_Scan_Interval This is defined as the time interval from when the Controller started +its last LE scan until it begins the subsequent LE scan. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Window Amount of time for the duration of the LE scan. LE_Scan_Window +shall be less than or equal to LE_Scan_Interval. +Time = N * 0.625 msec. + * Values: + - 0x0004 (2.500 ms) ... 0x4000 (10240.000 ms) + * @param LE_Scan_Type Passive or active scanning. With active scanning SCAN_REQ packets are sent. + * Values: + - 0x00: Passive Scanning + - 0x01: Active scanning + * @param Own_Address_Type Own address type: + - 0x00: Public Device Address (it is allowed only if privacy is disabled) + - 0x01: Random Device Address (it is allowed only if privacy is disabled) + - 0x02: Resolvable Private Address (it is allowed only if privacy is enabled) + - 0x03: Non Resolvable Private Address (it is allowed only if privacy is enabled) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Resolvable Private Address + - 0x03: Non Resolvable Private Address + * @param Filter_Duplicates Enable/disable duplicate filtering. + * Values: + - 0x00: Duplicate filtering disabled + - 0x01: Duplicate filtering enabled + * @param Scanning_Filter_Policy Scanning filter policy: + - 0x00 Accept all advertisement packets (it is allowed only if controller privacy is enabled).Directed advertising packets which are not addressed for this device shall be ignored. + - 0x01 Ignore advertisement packets from devices not in the White List Only.Directed advertising packets which are not addressed for this device shall be ignored. + - 0x02 Accept all undirected advertisement packets (it is allowed only if controller privacy or host privacy is enabled).Directed advertisement packets where initiator address is a RPA and Directed advertisement packets addressed to this device shall be accepted. + - 0x03 Accept all undirected advertisement packets from devices that are in the White List.Directed advertisement packets where initiator address is RPA and Directed advertisement packets addressed to this device shall be accepted. + - NOTE: If Host privacy is enabled Scanning_Filter_Policy can only take values 0x00 or 0x01; + * Values: + - 0x00: Accept all + - 0x01: Ignore devices not in the White List + - 0x02: Accept all (use resolving list) + - 0x03: Ignore devices not in the White List (use resolving list) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_start_observation_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t LE_Scan_Type, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates, + uint8_t Scanning_Filter_Policy); +/** + * @brief This command gets the list of the devices which are bonded. It returns the +number of addresses and the corresponding address types and values. + * @param[out] Num_of_Addresses The number of bonded devices + * @param[out] Bonded_Device_Entry See @ref Bonded_Device_Entry_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_get_bonded_devices(uint8_t *Num_of_Addresses, + Bonded_Device_Entry_t Bonded_Device_Entry[]); +/** + * @brief The command finds whether the device, whose address is specified in the command, is +bonded. If the device is using a resolvable private address and it has been bonded, then the +command will return BLE_STATUS_SUCCESS. + * @param Peer_Address_Type Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + * @param Peer_Address Address used by the peer device while advertising + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_is_device_bonded(uint8_t Peer_Address_Type, + uint8_t Peer_Address[6]); +/** + * @brief This command allows the User to validate/confirm or not the Numeric Comparison value showed through the ACI_GAP_Numeric_Comparison_Value_Event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Confirm_Yes_No 0 : The Numeric Values showed on both local and peer device are different! +1 : The Numeric Values showed on both local and peer device are equal! + * Values: + - 0x00: No + - 0x01: YES + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_numeric_comparison_value_confirm_yesno(uint16_t Connection_Handle, + uint8_t Confirm_Yes_No); +/** + * @brief This command permits to signal to the Stack the input type detected during Passkey input. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Input_Type Passkey input type detected + * Values: + - 0x00: Passkey entry started + - 0x01: Passkey digit entered + - 0x02: Passkey digit erased + - 0x03: Passkey cleared + - 0x04: Passkey entry completed + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_passkey_input(uint16_t Connection_Handle, + uint8_t Input_Type); +/** + * @brief This command is sent by the User to get (i.e. to extract from the Stack) the OOB data generated by the Stack itself. +In a complete system (i.e. having an OOB channel fully handled) this command should be invoked by the OOB Channel manager to require the local OOB data +(hence without user interaction) to be sent via OOB to the remote peer candidate device. +The requested OOB data are returned in response to the incoming command. The OOB data are not generated on the fly, but they are already available in the Stack. + * @param OOB_Data_Type OOB Data type + * Values: + - 0x00: Legacy Privacy (LP) v.4.1 TK (Temporary Key) + - 0x01: Secure Connections (SC) v.4.2 Random value r used for generation of Confirm + - 0x02: Secure Connections (SC) v.4.2 Confirm value C generated through AES-CMAC-128 based cryptographic function: C=f4(PKx, PKx, r, 0) + * @param[out] Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param[out] Address Public or Random (static) address of this device + * @param[out] OOB_Data_Len Length of OOB Data carried by next data field + * @param[out] OOB_Data OOB Data to be exported via OOB. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_get_oob_data(uint8_t OOB_Data_Type, + uint8_t *Address_Type, + uint8_t Address[6], + uint8_t *OOB_Data_Len, + uint8_t OOB_Data[16]); +/** + * @brief This command is sent (by the User) to input the OOB data arrived via OOB communication. +It may be sent to set either the OOB Authentication data of the Local device, or the data received via OOB by the Remote peer candidate device. +It can be used with OOB_Data_Len set to 0 to generate OOB authentication data for Secure Connections. +In a complete system (i.e. having an OOB channel fully handled) this command should be invoked by the OOB Channel manager when receiving the OOB data (hence without user interaction). +Since the BLE stack v 2.x implementation supports just one entry for the Remote peer candidate list containing the OOB data, at every command invocation the data existing in that entry are overwritten. + * @param Device_Type OOB Device type: + - 0x00: The Address information are ignored. + - OOB_Data_Len= 0x00: this triggers the automatic regeneration of OOB Authentication data (for Secure Connections only; a ECDH-Public Key must). + - OOB_Data_Len in [0..16]: the OOB_Data carried by the command will overwrite the current local Authentication OOB Data. + - 0x01: The Address information is used to search the entry of the Remote peer candidate list containing the OOB data for that specific remote device; if no entry exists, the a new entry is used, if available (current implementation supports just 1 entry in this list). + - OOB_Data_Len in [0..16]: the OOB_Data carried by the command overwrites (if present) the remote Authentication OOB Data. + * Values: + - 0x00: Local device + - 0x01: Remote device + * @param Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param Address Public or Random (static) address of the peer device + * @param OOB_Data_Type OOB Data type + * Values: + - 0x00: Legacy Privacy (LP) v.4.1 TK (Temporary Key) + - 0x01: Secure Connections (SC) v.4.2 Random value r used for generation of Confirm + - 0x02: Secure Connections (SC) v.4.2 Confirm value C generated through AES-CMAC-128 based cryptographic function: C=f4(PKx, PKx, r, 0) + * @param OOB_Data_Len Length of OOB Data carried by next data field + * @param OOB_Data OOB Data to be exported via OOB. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_set_oob_data(uint8_t Device_Type, + uint8_t Address_Type, + uint8_t Address[6], + uint8_t OOB_Data_Type, + uint8_t OOB_Data_Len, + uint8_t OOB_Data[16]); +/** + * @brief This command is used to add one device to the list of address translations used to resolve Resolvable Private Addresses in the Controller. + * @param Num_of_Resolving_list_Entries Number of devices that have to be added to the resolving list. + * @param Whitelist_Identity_Entry See @ref Whitelist_Identity_Entry_t + * @param Clear_Resolving_List Clear the resolving list + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_add_devices_to_resolving_list(uint8_t Num_of_Resolving_list_Entries, + Whitelist_Identity_Entry_t Whitelist_Identity_Entry[], + uint8_t Clear_Resolving_List); +/** + * @brief This command can be used to remove a specified device from the bonding table. + * @param Peer_Identity_Address_Type Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + * @param Peer_Identity_Address Public or Random (static) Identity address of the peer device + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gap_remove_bonded_device(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6]); +/** + * @} + */ +/** + *@defgroup GATT_API GATT API + *@brief GATT API layer. + *@{ + */ +/** + * @brief Initialize the GATT layer for server and client roles. +It adds also the GATT service with Service Changed Characteristic. +Until this command is issued the GATT channel will not process any commands even if the +connection is opened. This command has to be given before using any of the GAP features. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_init(void); +/** + * @brief Add a service to GATT Server. When a service is created in the server, the host needs to +reserve the handle ranges for this service using Max_Attribute_Records parameter. This +parameter specifies the maximum number of attribute records that can be added to this +service (including the service attribute, include attribute, characteristic attribute, +characteristic value attribute and characteristic descriptor attribute). Handle of the created +service is returned in command complete event. Service declaration is taken from the service pool. +The attributes for characteristics and descriptors are allocated from the attribute pool. + * @param Service_UUID_Type UUID type. + * @param Service_UUID See @ref Service_UUID_t + * @param Service_Type Service type. + * Values: + - 0x01: Primary Service + - 0x02: Secondary Service + * @param Max_Attribute_Records Maximum number of attribute records that can be added to this service + * @param[out] Service_Handle Handle of the Service. +When this service is added, a handle is allocated by the server for this service. +Server also allocates a range of handles for this service from serviceHandle to + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_add_service(uint8_t Service_UUID_Type, + Service_UUID_t *Service_UUID, + uint8_t Service_Type, + uint8_t Max_Attribute_Records, + uint16_t *Service_Handle); +/** + * @brief Include a service given by Include_Start_Handle and Include_End_Handle to another +service given by Service_Handle. Attribute server creates an INCLUDE definition +attribute and return the handle of this attribute in Included_handle. + * @param Service_Handle Handle of the Service to which another service has to be included. + * @param Include_Start_Handle Start Handle of the Service which has to be included in service + * @param Include_End_Handle End Handle of the Service which has to be included in service + * @param Include_UUID_Type UUID type. + * @param Include_UUID See @ref Include_UUID_t + * @param[out] Include_Handle Handle of the include declaration + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_include_service(uint16_t Service_Handle, + uint16_t Include_Start_Handle, + uint16_t Include_End_Handle, + uint8_t Include_UUID_Type, + Include_UUID_t *Include_UUID, + uint16_t *Include_Handle); +/** + * @brief Add a characteristic to a service. + * @param Service_Handle Handle of the Service to which the characteristic will be added + * @param Char_UUID_Type UUID type. + * @param Char_UUID See @ref Char_UUID_t + * @param Char_Value_Length Maximum length of the characteristic value. + * @param Char_Properties Characteristic Properties (Volume 3, Part G, section 3.3.1.1 of Bluetooth Specification 4.1) + * Flags: + - 0x00: CHAR_PROP_NONE + - 0x01: CHAR_PROP_BROADCAST (Broadcast) + - 0x02: CHAR_PROP_READ (Read) + - 0x04: CHAR_PROP_WRITE_WITHOUT_RESP (Write w/o resp) + - 0x08: CHAR_PROP_WRITE (Write) + - 0x10: CHAR_PROP_NOTIFY (Notify) + - 0x20: CHAR_PROP_INDICATE (Indicate) + - 0x40: CHAR_PROP_SIGNED_WRITE (Authenticated Signed Writes) + - 0x80: CHAR_PROP_EXT (Extended Properties) + * @param Security_Permissions Security permission flags. + * Flags: + - 0x00: None + - 0x01: AUTHEN_READ (Need authentication to read) + - 0x02: AUTHOR_READ (Need authorization to read) + - 0x04: ENCRY_READ (Need encryption to read) + - 0x08: AUTHEN_WRITE (need authentication to write) + - 0x10: AUTHOR_WRITE (need authorization to write) + - 0x20: ENCRY_WRITE (need encryption to write) + * @param GATT_Evt_Mask GATT event mask. + * Flags: + - 0x00: GATT_DONT_NOTIFY_EVENTS + - 0x01: GATT_NOTIFY_ATTRIBUTE_WRITE + - 0x02: GATT_NOTIFY_WRITE_REQ_AND_WAIT_FOR_APPL_RESP + - 0x04: GATT_NOTIFY_READ_REQ_AND_WAIT_FOR_APPL_RESP + * @param Enc_Key_Size Minimum encryption key size required to read the characteristic. + * Values: + - 0x07 ... 0x10 + * @param Is_Variable Specify if the characteristic value has a fixed length or +a variable length. + * Values: + - 0x00: Fixed length + - 0x01: Variable length + * @param[out] Char_Handle Handle of the Characteristic that has been added. +It is the handle of the characteristic declaration. +The attribute that holds the characteristic value is allocated at the next handle, +followed by the Client Characteristic Configuration descriptor if the characteristic +has CHAR_PROP_NOTIFY or CHAR_PROP_INDICATE properties. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_add_char(uint16_t Service_Handle, + uint8_t Char_UUID_Type, + Char_UUID_t *Char_UUID, + uint16_t Char_Value_Length, + uint8_t Char_Properties, + uint8_t Security_Permissions, + uint8_t GATT_Evt_Mask, + uint8_t Enc_Key_Size, + uint8_t Is_Variable, + uint16_t *Char_Handle); +/** + * @brief Add a characteristic descriptor to a service. + * @param Service_Handle Handle of service to which the characteristic belongs + * @param Char_Handle Handle of the characteristic to which description has to be added + * @param Char_Desc_Uuid_Type UUID type. + * @param Char_Desc_Uuid See @ref Char_Desc_Uuid_t + * @param Char_Desc_Value_Max_Len The maximum length of the descriptor value + * @param Char_Desc_Value_Length Current Length of the characteristic descriptor value + * @param Char_Desc_Value Value of the characteristic description + * @param Security_Permissions Security permission flags. + * Flags: + - 0x00: None + - 0x01: AUTHEN_READ (Need authentication to read) + - 0x02: AUTHOR_READ (Need authorization to read) + - 0x04: ENCRY_READ (Need encryption to read) + - 0x08: AUTHEN_WRITE (need authentication to write) + - 0x10: AUTHOR_WRITE (need authorization to write) + - 0x20: ENCRY_WRITE (need encryption to write) + * @param Access_Permissions Access permission + * Flags: + - 0x00: None + - 0x01: READ + - 0x02: WRITE + - 0x04: WRITE_WO_RESP + - 0x08: SIGNED_WRITE + * @param GATT_Evt_Mask GATT event mask. + * Flags: + - 0x00: GATT_DONT_NOTIFY_EVENTS + - 0x01: GATT_NOTIFY_ATTRIBUTE_WRITE + - 0x02: GATT_NOTIFY_WRITE_REQ_AND_WAIT_FOR_APPL_RESP + - 0x04: GATT_NOTIFY_READ_REQ_AND_WAIT_FOR_APPL_RESP + * @param Enc_Key_Size Minimum encryption key size required to read the characteristic. + * Values: + - 0x07 ... 0x10 + * @param Is_Variable Specify if the characteristic value has a fixed length or +a variable length. + * Values: + - 0x00: Fixed length + - 0x01: Variable length + * @param[out] Char_Desc_Handle Handle of the characteristic descriptor + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_add_char_desc(uint16_t Service_Handle, + uint16_t Char_Handle, + uint8_t Char_Desc_Uuid_Type, + Char_Desc_Uuid_t *Char_Desc_Uuid, + uint8_t Char_Desc_Value_Max_Len, + uint8_t Char_Desc_Value_Length, + uint8_t Char_Desc_Value[], + uint8_t Security_Permissions, + uint8_t Access_Permissions, + uint8_t GATT_Evt_Mask, + uint8_t Enc_Key_Size, + uint8_t Is_Variable, + uint16_t *Char_Desc_Handle); +/** + * @brief Update a characteristic value in a service. +If notifications (or indications) are enabled on that characteristic, +a notification (or indication) will be sent to the client after sending +this command to the BlueNRG. The command is queued into the BlueNRG command queue. +If the buffer is full, because previous commands could not be still processed, +the function will return BLE_STATUS_INSUFFICIENT_RESOURCES. This will happen +if notifications (or indications) are enabled and the application calls +@ref aci_gatt_update_char_value at an higher rate than what is allowed by the link. +Throughput on BLE link depends on connection interval and connection length +parameters (decided by the master, see aci_l2cap_connection_parameter_update_request() +for more info on how to suggest new connection parameters from a slave). If the +application does not want to lose notifications because BlueNRG buffer becomes full, +it has to retry again till the function returns BLE_STATUS_SUCCESS or any other error code. +DEPRECATED API (still supported but not recommended). + * @param Service_Handle Handle of service to which the characteristic belongs + * @param Char_Handle Handle of the characteristic + * @param Val_Offset The offset from which the attribute value has to be updated. +If this is set to 0 and the attribute value is of variable length, then the length of the attribute will be set to the Char_Value_Length. +If the Val_Offset is set to a value greater than 0, then the length of the attribute will be set to the maximum length as +specified for the attribute while adding the characteristic. + * @param Char_Value_Length Length of the characteristic value in octets + * @param Char_Value Characteristic value + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_update_char_value(uint16_t Service_Handle, + uint16_t Char_Handle, + uint8_t Val_Offset, + uint8_t Char_Value_Length, + uint8_t Char_Value[]); +/** + * @brief Delete the specified characteristic from the service. + * @param Serv_Handle Handle of service to which the characteristic belongs + * @param Char_Handle Handle of the characteristic which has to be deleted + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_del_char(uint16_t Serv_Handle, + uint16_t Char_Handle); +/** + * @brief Delete the specified service from the GATT server database. + * @param Serv_Handle Handle of the service to be deleted + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_del_service(uint16_t Serv_Handle); +/** + * @brief Delete the Include definition from the service. + * @param Serv_Handle Handle of the service to which the include service belongs + * @param Include_Handle Handle of the included service which has to be deleted + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_del_include_service(uint16_t Serv_Handle, + uint16_t Include_Handle); +/** + * @brief Mask events from the GATT. The default configuration is all the events masked. + * @param GATT_Evt_Mask GATT/ATT event mask. + * Values: + - 0x00000001: ACI_GATT_ATTRIBUTE_MODIFIED_EVENT + - 0x00000002: ACI_GATT_PROC_TIMEOUT_EVENT + - 0x00000004: ACI_ATT_EXCHANGE_MTU_RESP_EVENT + - 0x00000008: ACI_ATT_FIND_INFO_RESP_EVENT + - 0x00000010: ACI_ATT_FIND_BY_TYPE_VALUE_RESP_EVENT + - 0x00000020: ACI_ATT_READ_BY_TYPE_RESP_EVENT + - 0x00000040: ACI_ATT_READ_RESP_EVENT + - 0x00000080: ACI_ATT_READ_BLOB_RESP_EVENT + - 0x00000100: ACI_ATT_READ_MULTIPLE_RESP_EVENT + - 0x00000200: ACI_ATT_READ_BY_GROUP_TYPE_RESP_EVENT + - 0x00000800: ACI_ATT_PREPARE_WRITE_RESP_EVENT + - 0x00001000: ACI_ATT_EXEC_WRITE_RESP_EVENT + - 0x00002000: ACI_GATT_INDICATION_EVENT + - 0x00004000: ACI_GATT_NOTIFICATION_EVENT + - 0x00008000: ACI_GATT_ERROR_RESP_EVENT + - 0x00010000: ACI_GATT_PROC_COMPLETE_EVENT + - 0x00020000: ACI_GATT_DISC_READ_CHAR_BY_UUID_RESP_EVENT + - 0x00040000: ACI_GATT_TX_POOL_AVAILABLE_EVENT + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_set_event_mask(uint32_t GATT_Evt_Mask); +/** + * @brief Perform an ATT MTU exchange procedure. +When the ATT MTU exchange procedure is completed, a @ref aci_att_exchange_mtu_resp_event +event is generated. A @ref aci_gatt_proc_complete_event event is also generated +to indicate the end of the procedure. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_exchange_config(uint16_t Connection_Handle); +/** + * @brief Send a Find Information Request. +This command is used to obtain the mapping of attribute handles with their associated +types. The responses of the procedure are given through the +@ref aci_att_find_info_resp_event event. The end of the procedure is indicated by +a @ref aci_gatt_proc_complete_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle First requested handle number + * @param End_Handle Last requested handle number + * @retval Value indicating success or error code. +*/ +tBleStatus aci_att_find_info_req(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle); +/** + * @brief Send a Find By Type Value Request +The Find By Type Value Request is used to obtain the handles of attributes that +have a given 16-bit UUID attribute type and a given attribute value. +The responses of the procedure are given through the @ref aci_att_find_by_type_value_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle First requested handle number + * @param End_Handle Last requested handle number + * @param UUID 2 octet UUID to find (little-endian) + * @param Attribute_Val_Length Length of attribute value (maximum value is ATT_MTU - 7). + * @param Attribute_Val Attribute value to find + * @retval Value indicating success or error code. +*/ +tBleStatus aci_att_find_by_type_value_req(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle, + uint16_t UUID, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Send a Read By Type Request. +The Read By Type Request is used to obtain the values of attributes where the attribute +type is known but the handle is not known. +The responses of the procedure are given through the @ref aci_att_read_by_type_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle First requested handle number + * @param End_Handle Last requested handle number + * @param UUID_Type UUID type. + * @param UUID See @ref UUID_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_att_read_by_type_req(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle, + uint8_t UUID_Type, + UUID_t *UUID); +/** + * @brief Send a Read By Group Type Request. +The Read By Group Type Request is used to obtain the values of grouping attributes where +the attribute type is known but the handle is not known. Grouping attributes are defined +at GATT layer. The grouping attribute types are: "Primary Service", "Secondary Service" +and "Characteristic". +The responses of the procedure are given through the @ref aci_att_read_by_group_type_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle First requested handle number + * @param End_Handle Last requested handle number + * @param UUID_Type UUID type. + * @param UUID See @ref UUID_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_att_read_by_group_type_req(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle, + uint8_t UUID_Type, + UUID_t *UUID); +/** + * @brief Send a Prepare Write Request. +The Prepare Write Request is used to request the server to prepare to write the value of an attribute. +The responses of the procedure are given through the @ref aci_att_prepare_write_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Val_Offset The offset of the first octet to be written + * @param Attribute_Val_Length Length of attribute value (maximum value is ATT_MTU - 5). + * @param Attribute_Val The value of the attribute to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_att_prepare_write_req(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Val_Offset, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Send an Execute Write Request. +The Execute Write Request is used to request the server to write or cancel the write +of all the prepared values currently held in the prepare queue from this client. +The result of the procedure is given through the @ref aci_att_exec_write_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Execute Execute or cancel writes. + * Values: + - 0x00: Cancel all prepared writes + - 0x01: Immediately write all pending prepared values + * @retval Value indicating success or error code. +*/ +tBleStatus aci_att_execute_write_req(uint16_t Connection_Handle, + uint8_t Execute); +/** + * @brief Start the GATT client procedure to discover all primary services on the server. +The responses of the procedure are given through the @ref aci_att_read_by_group_type_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_disc_all_primary_services(uint16_t Connection_Handle); +/** + * @brief Start the procedure to discover the primary services of the specified UUID on the server. +The responses of the procedure are given through the @ref aci_att_find_by_type_value_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param UUID_Type UUID type. + * @param UUID See @ref UUID_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_disc_primary_service_by_uuid(uint16_t Connection_Handle, + uint8_t UUID_Type, + UUID_t *UUID); +/** + * @brief Start the procedure to find all included services. +The responses of the procedure are given through the @ref aci_att_read_by_type_resp_event event. +The end of the procedure is indicated by a @ref aci_gatt_proc_complete_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle Start attribute handle of the service + * @param End_Handle End attribute handle of the service + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_find_included_services(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle); +/** + * @brief Start the procedure to discover all the characteristics of a given service. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packets are given through +@ref aci_att_read_by_type_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle Start attribute handle of the service + * @param End_Handle End attribute handle of the service + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_disc_all_char_of_service(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle); +/** + * @brief Start the procedure to discover all the characteristics specified by a UUID. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packets are given through +@ref aci_gatt_disc_read_char_by_uuid_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle Start attribute handle of the service + * @param End_Handle End attribute handle of the service + * @param UUID_Type UUID type. + * @param UUID See @ref UUID_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_disc_char_by_uuid(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle, + uint8_t UUID_Type, + UUID_t *UUID); +/** + * @brief Start the procedure to discover all characteristic descriptors on the server. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packets are given through +@ref aci_att_find_info_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Char_Handle Handle of the characteristic value + * @param End_Handle End handle of the characteristic + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_disc_all_char_desc(uint16_t Connection_Handle, + uint16_t Char_Handle, + uint16_t End_Handle); +/** + * @brief Start the procedure to read the attribute value. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packet is given through @ref aci_att_read_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the characteristic to be read + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_char_value(uint16_t Connection_Handle, + uint16_t Attr_Handle); +/** + * @brief Start the procedure to read all the characteristics specified by the UUID. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packets are given through +@ref aci_gatt_disc_read_char_by_uuid_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Start_Handle Starting handle of the range to be searched + * @param End_Handle End handle of the range to be searched + * @param UUID_Type UUID type. + * @param UUID See @ref UUID_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_using_char_uuid(uint16_t Connection_Handle, + uint16_t Start_Handle, + uint16_t End_Handle, + uint8_t UUID_Type, + UUID_t *UUID); +/** + * @brief Start the procedure to read a long characteristic value. +the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packets are given through @ref aci_att_read_blob_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the characteristic to be read + * @param Val_Offset Offset from which the value needs to be read + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_long_char_value(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Val_Offset); +/** + * @brief Start a procedure to read multiple characteristic values from a server. +This sub-procedure is used to read multiple Characteristic Values from a server when the +client knows the Characteristic Value Handles. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packets are given through +@ref aci_att_read_multiple_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Number_of_Handles The number of handles for which the value has to be read + * @param Handle_Entry See @ref Handle_Entry_t + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_multiple_char_value(uint16_t Connection_Handle, + uint8_t Number_of_Handles, + Handle_Entry_t Handle_Entry[]); +/** + * @brief Start the procedure to write a long characteristic value. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +During the procedure, @ref aci_att_prepare_write_resp_event and @ref aci_att_exec_write_resp_event +events are raised. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the characteristic to be written + * @param Attribute_Val_Length Length of the value to be written + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_char_value(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Start the procedure to write a long characteristic value. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +During the procedure, @ref aci_att_prepare_write_resp_event and @ref aci_att_exec_write_resp_event +events are raised. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Val_Offset Offset at which the attribute has to be written + * @param Attribute_Val_Length Length of the value to be written + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_long_char_value(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Val_Offset, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Start the procedure to write a characteristic reliably. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +During the procedure, @ref aci_att_prepare_write_resp_event and @ref aci_att_exec_write_resp_event +events are raised. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Val_Offset Offset at which the attribute has to be written + * @param Attribute_Val_Length Length of the value to be written + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_char_reliable(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Val_Offset, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Start the procedure to write a long characteristic descriptor. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +During the procedure, @ref aci_att_prepare_write_resp_event and @ref aci_att_exec_write_resp_event +events are raised. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Val_Offset Offset at which the attribute has to be written + * @param Attribute_Val_Length Length of the value to be written + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_long_char_desc(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Val_Offset, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Start the procedure to read a long characteristic value. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is +generated. Before procedure completion the response packets are given through +@ref aci_att_read_blob_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the characteristic descriptor + * @param Val_Offset Offset from which the value needs to be read + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_long_char_desc(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Val_Offset); +/** + * @brief Start the procedure to write a characteristic descriptor. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Attribute_Val_Length Length of the value to be written + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_char_desc(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Start the procedure to read the descriptor specified. +When the procedure is completed, a @ref aci_gatt_proc_complete_event event is generated. +Before procedure completion the response packet is given through @ref aci_att_read_resp_event event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the descriptor to be read + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_char_desc(uint16_t Connection_Handle, + uint16_t Attr_Handle); +/** + * @brief Start the procedure to write a characteristic value without waiting for any response from the +server. No events are generated after this command is executed. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Attribute_Val_Length Length of the value to be written (maximum value is ATT_MTU - 3) + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_without_resp(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Start a signed write without response from the server. +The procedure is used to write a characteristic value with an authentication signature without waiting +for any response from the server. It cannot be used when the link is encrypted. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute to be written + * @param Attribute_Val_Length Length of the value to be written (up to ATT_MTU - 13) + * @param Attribute_Val Value to be written + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_signed_write_without_resp(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Allow application to confirm indication. This command has to be sent when the application +receives the event @ref aci_gatt_indication_event. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_confirm_indication(uint16_t Connection_Handle); +/** + * @brief Allow or reject a write request from a client. +This command has to be sent by the application when it receives the +@ref aci_gatt_write_permit_req_event. If the write can be allowed, then the status and error +code has to be set to 0. If the write cannot be allowed, then the status has to be set to 1 and +the error code has to be set to the error code that has to be passed to the client. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Attr_Handle Handle of the attribute that was passed in the event EVT_BLUE_GATT_WRITE_PERMIT_REQ + * @param Write_status If the value can be written or not. + * Values: + - 0x00: The value can be written to the attribute specified by attr_handle + - 0x01: The value cannot be written to the attribute specified by the attr_handle + * @param Error_Code The error code that has to be passed to the client in case the write has to be rejected + * @param Attribute_Val_Length Length of the value to be written as passed in the event EVT_BLUE_GATT_WRITE_PERMIT_REQ + * @param Attribute_Val Value as passed in the event EVT_BLUE_GATT_WRITE_PERMIT_REQ + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_write_resp(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint8_t Write_status, + uint8_t Error_Code, + uint8_t Attribute_Val_Length, + uint8_t Attribute_Val[]); +/** + * @brief Allow the GATT server to send a response to a read request from a client. +The application has to send this command when it receives the +@ref aci_gatt_read_permit_req_event or @ref aci_gatt_read_multi_permit_req_event. This +command indicates to the stack that the response can be sent to the client. So if the +application wishes to update any of the attributes before they are read by the client, it has to +update the characteristic values using the @ref aci_gatt_update_char_value and then give +this command. The application should perform the required operations within 30 seconds. +Otherwise the GATT procedure will be timeout. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_allow_read(uint16_t Connection_Handle); +/** + * @brief This command sets the security permission for the attribute handle specified. Currently the +setting of security permission is allowed only for client configuration descriptor. + * @param Serv_Handle Handle of the service which contains the attribute whose security permission has to be modified + * @param Attr_Handle Handle of the attribute whose security permission has to be modified + * @param Security_Permissions Security permission flags. + * Flags: + - 0x00: None + - 0x01: AUTHEN_READ (Need authentication to read) + - 0x02: AUTHOR_READ (Need authorization to read) + - 0x04: ENCRY_READ (Need encryption to read) + - 0x08: AUTHEN_WRITE (need authentication to write) + - 0x10: AUTHOR_WRITE (need authorization to write) + - 0x20: ENCRY_WRITE (need encryption to write) + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_set_security_permission(uint16_t Serv_Handle, + uint16_t Attr_Handle, + uint8_t Security_Permissions); +/** + * @brief This command sets the value of the descriptor specified by charDescHandle. + * @param Serv_Handle Handle of the service which contains the characteristic descriptor + * @param Char_Handle Handle of the characteristic which contains the descriptor + * @param Char_Desc_Handle Handle of the descriptor whose value has to be set + * @param Val_Offset Offset from which the descriptor value has to be updated + * @param Char_Desc_Value_Length Length of the descriptor value + * @param Char_Desc_Value Descriptor value + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_set_desc_value(uint16_t Serv_Handle, + uint16_t Char_Handle, + uint16_t Char_Desc_Handle, + uint16_t Val_Offset, + uint8_t Char_Desc_Value_Length, + uint8_t Char_Desc_Value[]); +/** + * @brief Reads the value of the attribute handle specified from the local GATT database. + * @param Attr_Handle Handle of the attribute to read + * @param Offset Offset from which the value needs to be read + * @param Value_Length_Requested Maximum number of octets to be returned as attribute value + * @param[out] Length Length of the attribute value + * @param[out] Value_Length Length in octets of the Value parameter + * @param[out] Value Attribute value + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_read_handle_value(uint16_t Attr_Handle, + uint16_t Offset, + uint16_t Value_Length_Requested, + uint16_t *Length, + uint16_t *Value_Length, + uint8_t Value[]); +/** + * @brief This command is a more flexible version of @ref aci_gatt_update_char_value + to support update of long attribute up to 512 bytes and indicate selectively the generation of Indication/Notification. + * @param Conn_Handle_To_Notify Connection handle to notify. Notify all subscribed clients if equal to 0x0000: DEPRECATED feature (still supported but not recommended). + * @param Service_Handle Handle of service to which the characteristic belongs + * @param Char_Handle Handle of the characteristic + * @param Update_Type Allow Notification or Indication generation, if enabled in the client characteristic configuration descriptor. It also allows to enable the no retry feature if supported + * Flags: + - 0x00: No notification or indication (local characteristic value update) + - 0x01: Notification + - 0x02: Indication + - 0x04: Disable standard BLE Link Layer retransmission mechanism for notifications PDUs that are not acknowledged by the Link Layer of the peer device + * @param Char_Length Total length of the characteristic value. + In case of a variable size characteristic, this field specifies the new length of the characteristic value after the update; in case of fixed length characteristic this field is ignored. + * @param Value_Offset The offset from which the attribute value has to be updated. + * @param Value_Length Length of the Value parameter in octets + * @param Value Updated characteristic value + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_update_char_value_ext(uint16_t Conn_Handle_To_Notify, + uint16_t Service_Handle, + uint16_t Char_Handle, + uint8_t Update_Type, + uint16_t Char_Length, + uint16_t Value_Offset, + uint8_t Value_Length, + uint8_t Value[]); +/** + * @brief Deny the GATT server to send a response to a read request from a client. +The application may send this command when it receives the @ref aci_gatt_read_permit_req_event or @ref aci_gatt_read_multi_permit_req_event. +This command indicates to the stack that the client is not allowed to read the requested characteristic due to e.g. application restrictions. +The Error code shall be either 0x08 (Insufficient Authorization) or a value in the range 0x80-0x9F (Application Error). +The application should issue the @ref aci_gatt_deny_read or @ref aci_gatt_allow_read command within 30 seconds from the reception of +the @ref aci_gatt_read_permit_req_event or @ref aci_gatt_read_multi_permit_req_event events otherwise the GATT procedure will issue a timeout. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Error_Code Error code for the command + * Values: + - 0x08: Insufficient Authorization + - 0x80 ... 0x9F: Application Error + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_deny_read(uint16_t Connection_Handle, + uint8_t Error_Code); +/** + * @brief This command sets the access permission for the attribute handle specified. + * @param Serv_Handle Handle of the service which contains the attribute whose access permission has to be modified + * @param Attr_Handle Handle of the attribute whose security permission has to be modified + * @param Access_Permissions Access permission + * Values: + - 0x00: None + - 0x01: READ + - 0x02: WRITE + - 0x04: WRITE_NO_RESP + - 0x08: SIGNED_WRITE + * @retval Value indicating success or error code. +*/ +tBleStatus aci_gatt_set_access_permission(uint16_t Serv_Handle, + uint16_t Attr_Handle, + uint8_t Access_Permissions); +/** + * @} + */ +/** + *@defgroup L2CAP_API L2CAP API + *@brief L2CAP API layer. + *@{ + */ +/** + * @brief Send an L2CAP connection parameter update request from the slave to the master. +An @ref aci_l2cap_connection_update_resp_event event will be raised when the master will respond to the +request (accepts or rejects). + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Slave_latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Timeout_Multiplier Defines connection timeout parameter in the following manner: Timeout Multiplier * 10ms. + * @retval Value indicating success or error code. +*/ +tBleStatus aci_l2cap_connection_parameter_update_req(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Slave_latency, + uint16_t Timeout_Multiplier); +/** + * @brief Accept or reject a connection update. This command should be sent in response +to a @ref aci_l2cap_connection_update_req_event event from the controller. The accept parameter has to be +set if the connection parameters given in the event are acceptable. + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Conn_Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Slave_latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Timeout_Multiplier Defines connection timeout parameter in the following manner: Timeout Multiplier * 10ms. + * @param Minimum_CE_Length Information parameter about the minimum length of connection +needed for this LE connection. +Time = N * 0.625 msec. + * @param Maximum_CE_Length Information parameter about the maximum length of connection needed +for this LE connection. +Time = N * 0.625 msec. + * @param Identifier Identifier received in ACI_L2CAP_Connection_Update_Req event. + * @param Accept Specify if connection update parameters are acceptable or not. + * Values: + - 0x00: Reject + - 0x01: Accept + * @retval Value indicating success or error code. +*/ +tBleStatus aci_l2cap_connection_parameter_update_resp(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Slave_latency, + uint16_t Timeout_Multiplier, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Identifier, + uint8_t Accept); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BLUENRG1_API_H_ */ diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_events.h b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_events.h new file mode 100644 index 00000000000..4497453a629 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_events.h @@ -0,0 +1,1352 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef _BLUENRG1_EVENTS_H_ +#define _BLUENRG1_EVENTS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +/** + *@defgroup HCI_events HCI events + *@brief HCI events layer. + *@{ + */ +/* HCI events */ +/** Documentation for C struct Handle_Packets_Pair_Entry_t */ +typedef struct Handle_Packets_Pair_Entry_t_s { + /** Connection handle + */ + uint16_t Connection_Handle; + /** The number of HCI Data Packets that have been completed (transmitted +or flushed) for the associated Connection_Handle since the previous time +the event was returned. + */ + uint16_t HC_Num_Of_Completed_Packets; +} Handle_Packets_Pair_Entry_t; +/** + * @brief The Disconnection Complete event occurs when a connection is terminated. +The status parameter indicates if the disconnection was successful or not. The +reason parameter indicates the reason for the disconnection if the disconnection +was successful. If the disconnection was not successful, the value of the +reason parameter can be ignored by the Host. For example, this can be the +case if the Host has issued the Disconnect command and there was a parameter +error, or the command was not presently allowed, or a Connection_Handle +that didn't correspond to a connection was given. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection_Handle which was disconnected. + * Values: + - 0x0000 ... 0x0EFF + * @param Reason Reason for disconnection. + * Values: + - 0x00: Success + - 0x01: Unknown HCI Command + - 0x02: Unknown Connection Identifier + - 0x03: Hardware Failure + - 0x04: Page Timeout + - 0x05: Authentication Failure + - 0x06: PIN or Key Missing + - 0x07: Memory Capacity Exceeded + - 0x08: Connection Timeout + - 0x09: Connection Limit Exceeded + - 0x0A: Synchronous Connection Limit to a Device Exceeded + - 0x0B: ACL Connection Already Exists + - 0x0C: Command Disallowed + - 0x0D: Connection Rejected Due To Limited Resources + - 0x0E: Connection Rejected Due To Security Reasons + - 0x0F: Connection Rejected due to Unacceptable BD_ADDR + - 0x10: Connection Accept Timeout Exceeded + - 0x11: Unsupported Feature Or Parameter Value + - 0x12: Invalid HCI Command Parameters + - 0x13: Remote User Terminated Connection + - 0x14: Remote Device Terminated Connection due to Low Resources + - 0x15: Remote Device Terminated Connection due to Power Off + - 0x16: Connection Terminated By Local Host + - 0x17: Repeated Attempts + - 0x18: Pairing Not Allowed + - 0x19: Unknown LMP PDU + - 0x1A: Unsupported Remote Feature / Unsupported LMP Feature + - 0x1B: SCO Offset Rejected + - 0x1C: SCO Interval Rejected + - 0x1D: SCO Air Mode Rejected + - 0x1E: Invalid LMP Parameters + - 0x1F: Unspecified Error + - 0x20: Unsupported LMP Parameter Value + - 0x21: Role Change Not Allowed + - 0x22: LMP Response Timeout / LL Response Timeout + - 0x23: LMP Error Transaction Collision + - 0x24: LMP PDU Not Allowed + - 0x25: Encryption Mode Not Acceptable + - 0x26: Link Key cannot be Changed + - 0x27: Requested QoS Not Supported + - 0x28: Instant Passed + - 0x29: Pairing With Unit Key Not Supported + - 0x2A: Different Transaction Collision + - 0x2C: QoS Unacceptable Parameter + - 0x2D: QoS Rejected + - 0x2E: Channel Assessment Not Supported + - 0x2F: Insufficient Security + - 0x30: Parameter Out Of Mandatory Range + - 0x32: Role Switch Pending + - 0x34: Reserved Slot Violation + - 0x35: Role Switch Failed + - 0x36: Extended Inquiry Response Too Large + - 0x37: Secure Simple Pairing Not Supported by Host + - 0x38: Host Busy - Pairing + - 0x39: Connection Rejected due to No Suitable Channel Found + - 0x3A: Controller Busy + - 0x3B: Unacceptable Connection Interval + - 0x3C: Directed Advertising Timeout + - 0x3D: Connection Terminated Due to MIC Failure + - 0x3E: Connection Failed to be Established + - 0x3F: MAC of the 802.11 AMP + - 0x41: Failed + - 0x42: Invalid parameters + - 0x43: Busy + - 0x44: Invalid length + - 0x45: Pending + - 0x46: Not allowed + - 0x47: GATT error + - 0x48: Address not resolved + - 0x50: Invalid CID + - 0x5A: CSRK not found + - 0x5B: IRK not found + - 0x5C: Device not found in DB + - 0x5D: Security DB full + - 0x5E: Device not bonded + - 0x5F: Device in blacklist + - 0x60: Invalid handle + - 0x61: Invalid parameter + - 0x62: Out of handles + - 0x63: Invalid operation + - 0x64: Insufficient resources + - 0x65: Insufficient encryption key size + - 0x66: Characteristic already exist + - 0x82: No valid slot + - 0x83: Short window + - 0x84: New interval failed + - 0x85: Too large interval + - 0x86: Slot length failed + - 0xFA: Flash read failed + - 0xFB: Flash write failed + - 0xFC: Flash erase failed + * @retval None +*/ +void hci_disconnection_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Reason); +/** + * @brief The Encryption Change event is used to indicate that the change of the encryption +mode has been completed. The Connection_Handle will be a Connection_Handle +for an ACL connection. The Encryption_Enabled event parameter +specifies the new Encryption_Enabled parameter for the Connection_Handle +specified by the Connection_Handle event parameter. This event will occur on +both devices to notify the Hosts when Encryption has changed for the specified +Connection_Handle between two devices. Note: This event shall not be generated +if encryption is paused or resumed; during a role switch, for example. +The meaning of the Encryption_Enabled parameter depends on whether the +Host has indicated support for Secure Connections in the Secure_Connections_Host_Support +parameter. When Secure_Connections_Host_Support is +'disabled' or the Connection_Handle refers to an LE link, the Controller shall +only use Encryption_Enabled values 0x00 (OFF) and 0x01 (ON). +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.7.8) + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Encryption_Enabled Link Level Encryption. + * Values: + - 0x00: Link Level Encryption OFF + - 0x01: Link Level Encryption is ON with AES-CCM + * @retval None +*/ +void hci_encryption_change_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Encryption_Enabled); +/** + * @brief The Read Remote Version Information Complete event is used to indicate the +completion of the process obtaining the version information of the remote Controller +specified by the Connection_Handle event parameter. The Connection_Handle +shall be for an ACL connection. +The Version event parameter defines the specification version of the LE Controller. +The Manufacturer_Name event parameter indicates the manufacturer +of the remote Controller. The Subversion event parameter is controlled +by the manufacturer and is implementation dependent. The Subversion +event parameter defines the various revisions that each version of the Bluetooth +hardware will go through as design processes change and errors are +fixed. This allows the software to determine what Bluetooth hardware is being +used and, if necessary, to work around various bugs in the hardware. +When the Connection_Handle is associated with an LE-U logical link, the Version +event parameter shall be Link Layer VersNr parameter, the Manufacturer_Name +event parameter shall be the CompId parameter, and the Subversion +event parameter shall be the SubVersNr parameter. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.7.12) + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Version Version of the Current LMP in the remote Controller + * @param Manufacturer_Name Manufacturer Name of the remote Controller + * @param Subversion Subversion of the LMP in the remote Controller + * @retval None +*/ +void hci_read_remote_version_information_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Version, + uint16_t Manufacturer_Name, + uint16_t Subversion); +/** + * @brief The Hardware Error event is used to indicate some implementation specific type of hardware failure for the controller. This event is used to notify the Host that a hardware failure has occurred in the Controller. + * @param Hardware_Code Hardware Error Event code. +Error code 0x01 and 0x02 are errors generally caused by hardware issue on the PCB; another possible cause is a slow crystal startup. +In the latter case, the HS_STARTUP_TIME in the device configuration needs to be tuned. +Error code 0x03 indicates an internal error of the protocol stack. +After this event is recommended to force device reset. + * Values: + - 0x01: Radio state error + - 0x02: Timer overrun error + - 0x03: Internal queue overflow error + * @retval None +*/ +void hci_hardware_error_event(uint8_t Hardware_Code); +/** + * @brief 'The Number Of Completed Packets event is used by the Controller to indicate +to the Host how many HCI Data Packets have been completed (transmitted or +flushed) for each Connection_Handle since the previous Number Of Completed +Packets event was sent to the Host. This means that the corresponding +buffer space has been freed in the Controller. Based on this information, and +the HC_Total_Num_ACL_Data_Packets and HC_Total_Num_Synchronous_- +Data_Packets return parameter of the Read_Buffer_Size command, the Host +can determine for which Connection_Handles the following HCI Data Packets +should be sent to the Controller. The Number Of Completed Packets event +must not be sent before the corresponding Connection Complete event. While +the Controller has HCI data packets in its buffer, it must keep sending the Number +Of Completed Packets event to the Host at least periodically, until it finally +reports that all the pending ACL Data Packets have been transmitted or +flushed. + * @param Number_of_Handles The number of Connection_Handles and Num_HCI_Data_Packets parameters pairs contained in this event + * @param Handle_Packets_Pair_Entry See @ref Handle_Packets_Pair_Entry_t + * @retval None +*/ +void hci_number_of_completed_packets_event(uint8_t Number_of_Handles, + Handle_Packets_Pair_Entry_t Handle_Packets_Pair_Entry[]); +/** + * @brief 'This event is used to indicate that the Controller's data buffers have been overflowed. +This can occur if the Host has sent more packets than allowed. The +Link_Type parameter is used to indicate that the overflow was caused by ACL data. + * @param Link_Type On wich type of channel overflow has occurred. + * Values: + - 0x01: ACL Buffer Overflow + * @retval None +*/ +void hci_data_buffer_overflow_event(uint8_t Link_Type); +/** + * @brief 'The Encryption Key Refresh Complete event is used to indicate to the Host +that the encryption key was refreshed on the given Connection_Handle any +time encryption is paused and then resumed. +If the Encryption Key Refresh Complete event was generated due to an +encryption pause and resume operation embedded within a change connection +link key procedure, the Encryption Key Refresh Complete event shall be sent +prior to the Change Connection Link Key Complete event. +If the Encryption Key Refresh Complete event was generated due to an +encryption pause and resume operation embedded within a role switch procedure, +the Encryption Key Refresh Complete event shall be sent prior to the +Role Change event. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval None +*/ +void hci_encryption_key_refresh_complete_event(uint8_t Status, + uint16_t Connection_Handle); +/** + * @} + */ +/** + *@defgroup HCI_LE_meta_events HCI LE meta events + *@brief HCI LE meta events layer. + *@{ + */ +/* HCI LE meta events */ +/** Documentation for C struct Advertising_Report_t */ +typedef struct Advertising_Report_t_s { + /** Type of advertising report event: +ADV_IND: Connectable undirected advertising', +ADV_DIRECT_IND: Connectable directed advertising, +ADV_SCAN_IND: Scannable undirected advertising, +ADV_NONCONN_IND: Non connectable undirected advertising, +SCAN_RSP: Scan response. + * Values: + - 0x00: ADV_IND + - 0x01: ADV_DIRECT_IND + - 0x02: ADV_SCAN_IND + - 0x03: ADV_NONCONN_IND + - 0x04: SCAN_RSP + */ + uint8_t Event_Type; + /** 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + */ + uint8_t Address_Type; + /** Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising +device. + */ + uint8_t Address[6]; + /** Length of the Data[i] field for each device which responded. + * Values: + - 0 ... 31 + */ + uint8_t Length_Data; + /** Length_Data[i] octets of advertising or scan response data formatted +as defined in [Vol 3] Part C, Section 8. + */ + uint8_t *Data; + /** N Size: 1 Octet (signed integer) +Units: dBm + * Values: + - 127: RSSI not available + - -127 ... 20 + */ + uint8_t RSSI; +} Advertising_Report_t; +/** Documentation for C struct Direct_Advertising_Report_t */ +typedef struct Direct_Advertising_Report_t_s { + /** Advertising type + * Values: + - 0x01: Connectable directed advertising (ADV_DIRECT_IND) + */ + uint8_t Event_Type; + /** 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + */ + uint8_t Address_Type; + /** Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising device. + */ + uint8_t Address[6]; + /** 0x01 Random Device Address + * Values: + - 0x01: Random Device Address + */ + uint8_t Direct_Address_Type; + /** Random Device Address + */ + uint8_t Direct_Address[6]; + /** N Size: 1 Octet (signed integer) +Units: dBm + * Values: + - 127: RSSI not available + - -127 ... 20 + */ + uint8_t RSSI; +} Direct_Advertising_Report_t; +/** + * @brief The LE Connection Complete event indicates to both of the Hosts forming the +connection that a new connection has been created. Upon the creation of the +connection a Connection_Handle shall be assigned by the Controller, and +passed to the Host in this event. If the connection establishment fails this event +shall be provided to the Host that had issued the LE_Create_Connection command. +This event indicates to the Host which issued a LE_Create_Connection +command and received a Command Status event if the connection +establishment failed or was successful. +The Master_Clock_Accuracy parameter is only valid for a slave. On a master, +this parameter shall be set to 0x00. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Role Role of the local device in the connection. + * Values: + - 0x00: Master + - 0x01: Slave + * @param Peer_Address_Type The address type of the peer device. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + * @param Peer_Address Public Device Address or Random Device Address of the peer +device + * @param Conn_Interval Connection interval used on this connection. +Time = N * 1.25 msec + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Master_Clock_Accuracy Master clock accuracy. Only valid for a slave. + * Values: + - 0x00: 500 ppm + - 0x01: 250 ppm + - 0x02: 150 ppm + - 0x03: 100 ppm + - 0x04: 75 ppm + - 0x05: 50 ppm + - 0x06: 30 ppm + - 0x07: 20 ppm + * @retval None +*/ +void hci_le_connection_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Role, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint16_t Conn_Interval, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint8_t Master_Clock_Accuracy); +/** + * @brief The LE Advertising Report event indicates that a Bluetooth device or multiple +Bluetooth devices have responded to an active scan or received some information +during a passive scan. The Controller may queue these advertising reports +and send information from multiple devices in one LE Advertising Report event. + * @param Num_Reports Number of responses in this event. + * Values: + - 0x01 + * @param Advertising_Report See @ref Advertising_Report_t + * @retval None +*/ +void hci_le_advertising_report_event(uint8_t Num_Reports, + Advertising_Report_t Advertising_Report[]); +/** + * @brief The LE Connection Update Complete event is used to indicate that the Controller +process to update the connection has completed. +On a slave, if no connection parameters are updated, then this event shall not be issued. +On a master, this event shall be issued if the Connection_Update command was sent. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Conn_Interval Connection interval used on this connection. +Time = N * 1.25 msec + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @retval None +*/ +void hci_le_connection_update_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint16_t Conn_Interval, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout); +/** + * @brief The LE Read Remote Used Features Complete event is used to indicate the +completion of the process of the Controller obtaining the used features of the +remote Bluetooth device specified by the Connection_Handle event parameter. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param LE_Features Bit Mask List of used LE features. For details see LE Link Layer specification. + * @retval None +*/ +void hci_le_read_remote_used_features_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t LE_Features[8]); +/** + * @brief The LE Long Term Key Request event indicates that the master device is +attempting to encrypt or re-encrypt the link and is requesting the Long Term +Key from the Host. (See [Vol 6] Part B, Section 5.1.3). + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Random_Number 64-bit random number + * @param Encrypted_Diversifier 16-bit encrypted diversifier + * @retval None +*/ +void hci_le_long_term_key_request_event(uint16_t Connection_Handle, + uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier); +/** + * @brief The LE Data Length Change event notifies the Host of a change to either the maximum Payload length or the maximum transmission time of Data Channel PDUs in either direction. The values reported are the maximum that will actually be used on the connection following the change. + * @param Connection_Handle Connection_Handle to be used to identify a connection. + * @param MaxTxOctets The maximum number of payload octets in a Link Layer Data Channel PDU that the local Controller will send on this connection (connEffectiveMaxTxOctets defined in [Vol 6] Part B, Section 4.5.10). +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param MaxTxTime The maximum time that the local Controller will take to send a Link Layer Data Channel PDU on this connection (connEffectiveMaxTx-Time defined in [Vol 6] Part B, Section 4.5.10). +Range 0x0148-0x0848 (0x0000 - 0x0127 and 0x0849 - 0xFFFF +Reserved for future use) + * @param MaxRxOctets The maximum number of payload octets in a Link Layer Data Channel PDU that the local controller expects to receive on this connection (connEfectiveMaxRxOctets defined in [Vol 6] Part B, Section 4.5.10). +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param MaxRxTime The maximum time that the local Controller expects to take to receive a Link Layer Data Channel PDU on this connection (connEffectiveMax-RxTime defined in [Vol 6] Part B, Section 4.5.10). +Range 0x0148-0x0848 (0x0000 - 0x0127 and 0x0849 - 0xFFFF Reserved for future use) + * @retval None +*/ +void hci_le_data_length_change_event(uint16_t Connection_Handle, + uint16_t MaxTxOctets, + uint16_t MaxTxTime, + uint16_t MaxRxOctets, + uint16_t MaxRxTime); +/** + * @brief This event is generated when local P-256 key generation is complete. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Local_P256_Public_Key Local P-256 public key. + * @retval None +*/ +void hci_le_read_local_p256_public_key_complete_event(uint8_t Status, + uint8_t Local_P256_Public_Key[64]); +/** + * @brief This event indicates that LE Diffie Hellman key generation has been completed +by the Controller. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param DHKey Diffie Hellman Key + * @retval None +*/ +void hci_le_generate_dhkey_complete_event(uint8_t Status, + uint8_t DHKey[32]); +/** + * @brief The LE Enhanced Connection Complete event indicates to both of the Hosts +forming the connection that a new connection has been created. Upon the +creation of the connection a Connection_Handle shall be assigned by the +Controller, and passed to the Host in this event. If the connection establishment +fails, this event shall be provided to the Host that had issued the +LE_Create_Connection command. +If this event is unmasked and LE Connection Complete event is unmasked, +only the LE Enhanced Connection Complete event is sent when a new +connection has been completed. +This event indicates to the Host that issued a LE_Create_Connection +command and received a Command Status event if the connection +establishment failed or was successful. +The Master_Clock_Accuracy parameter is only valid for a slave. On a master, +this parameter shall be set to 0x00. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Role Role of the local device in the connection. + * Values: + - 0x00: Master + - 0x01: Slave + * @param Peer_Address_Type 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + * @param Peer_Address Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the device to be connected. + * @param Local_Resolvable_Private_Address Resolvable Private Address being used by the local device for this connection. +This is only valid when the Own_Address_Type is set to 0x02 or 0x03. For other Own_Address_Type values, +the Controller shall return all zeros. + * @param Peer_Resolvable_Private_Address Resolvable Private Address being used by the peer device for this connection. +This is only valid for Peer_Address_Type 0x02 and 0x03. For +other Peer_Address_Type values, the Controller shall return all zeros. + * @param Conn_Interval Connection interval used on this connection. +Time = N * 1.25 msec + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Master_Clock_Accuracy Master clock accuracy. Only valid for a slave. + * Values: + - 0x00: 500 ppm + - 0x01: 250 ppm + - 0x02: 150 ppm + - 0x03: 100 ppm + - 0x04: 75 ppm + - 0x05: 50 ppm + - 0x06: 30 ppm + - 0x07: 20 ppm + * @retval None +*/ +void hci_le_enhanced_connection_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Role, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Local_Resolvable_Private_Address[6], + uint8_t Peer_Resolvable_Private_Address[6], + uint16_t Conn_Interval, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint8_t Master_Clock_Accuracy); +/** + * @brief The LE Direct Advertising Report event indicates that directed advertisements +have been received where the advertiser is using a resolvable private address +for the InitA field in the ADV_DIRECT_IND PDU and the +Scanning_Filter_Policy is equal to 0x02 or 0x03, see HCI_LE_Set_Scan_Parameters. +Direct_Address_Type and Direct_Addres is the address the directed +advertisements are being directed to. Address_Type and Address is the +address of the advertiser sending the directed advertisements. + * @param Num_Reports Number of responses in this event. + * Values: + - 0x01 + * @param Direct_Advertising_Report See @ref Direct_Advertising_Report_t + * @retval None +*/ +void hci_le_direct_advertising_report_event(uint8_t Num_Reports, + Direct_Advertising_Report_t Direct_Advertising_Report[]); +/** + * @} + */ +/** + *@defgroup ACI_GAP_events ACI GAP events + *@brief ACI GAP events layer. + *@{ + */ +/* ACI GAP events */ +/** + * @brief This event is generated by the controller when the limited discoverable mode ends due to +timeout. The timeout is 180 seconds. + * @retval None +*/ +void aci_gap_limited_discoverable_event(void); +/** + * @brief This event is generated when the pairing process has completed successfully or a pairing +procedure timeout has occurred or the pairing has failed. This is to notify the application that +we have paired with a remote device so that it can take further actions or to notify that a +timeout has occurred so that the upper layer can decide to disconnect the link. + * @param Connection_Handle Connection handle on which the pairing procedure completed + * @param Status Pairing status + * Values: + - 0x00: Success + - 0x01: Timeout + - 0x02: Failed + * @param Reason Pairing reason error code + * Values: + - 0x00 + - 0x01: PASSKEY_ENTRY_FAILED + - 0x02: OOB_NOT_AVAILABLE + - 0x03: AUTH_REQ_CANNOT_BE_MET + - 0x04: CONFIRM_VALUE_FAILED + - 0x05: PAIRING_NOT_SUPPORTED + - 0x06: INSUFF_ENCRYPTION_KEY_SIZE + - 0x07: CMD_NOT_SUPPORTED + - 0x08: UNSPECIFIED_REASON + - 0x09: VERY_EARLY_NEXT_ATTEMPT + - 0x0A: SM_INVALID_PARAMS + - 0x0B: SMP_SC_DHKEY_CHECK_FAILED + - 0x0C: SMP_SC_NUMCOMPARISON_FAILED + * @retval None +*/ +void aci_gap_pairing_complete_event(uint16_t Connection_Handle, + uint8_t Status, + uint8_t Reason); +/** + * @brief This event is generated by the Security manager to the application when a passkey is +required for pairing. When this event is received, the application has to respond with the +@ref aci_gap_pass_key_resp command. + * @param Connection_Handle Connection handle for which the passkey has been requested. + * @retval None +*/ +void aci_gap_pass_key_req_event(uint16_t Connection_Handle); +/** + * @brief This event is generated by the Security manager to the application when the application has +set that authorization is required for reading/writing of attributes. This event will be +generated as soon as the pairing is complete. When this event is received, +@ref aci_gap_authorization_resp command should be used to respond by the application. + * @param Connection_Handle Connection handle for which authorization has been requested. + * @retval None +*/ +void aci_gap_authorization_req_event(uint16_t Connection_Handle); +/** + * @brief This event is generated when the slave security request is successfully sent to the master. + * @retval None +*/ +void aci_gap_slave_security_initiated_event(void); +/** + * @brief This event is generated on the slave when a ACI_GAP_SLAVE_SECURITY_REQUEST is called to reestablish the bond +with a master but the master has lost the bond. When this event is received, the upper layer has to issue the +ACI_GAP_ALLOW_REBOND command in order to allow the slave to continue the pairing process with the master. +On the master this event is raised when ACI_GAP_SEND_PAIRING_REQUEST is called to reestablish a bond with a slave +but the slave has lost the bond. In order to create a new bond the master has to launch ACI_GAP_SEND_PAIRING_REQUEST +with force_rebond set to 1. + * @retval None +*/ +void aci_gap_bond_lost_event(void); +/** + * @brief This event is sent by the GAP to the upper layers when a procedure previously started has +been terminated by the upper layer or has completed for any other reason + * @param Procedure_Code Terminated procedure. + * Values: + - 0x01: LIMITED_DISCOVERY_PROC + - 0x02: GENERAL_DISCOVERY_PROC + - 0x04: NAME_DISCOVERY_PROC + - 0x08: AUTO_CONNECTION_ESTABLISHMENT_PROC + - 0x10: GENERAL_CONNECTION_ESTABLISHMENT_PROC + - 0x20: SELECTIVE_CONNECTION_ESTABLISHMENT_PROC + - 0x40: DIRECT_CONNECTION_ESTABLISHMENT_PROC + - 0x80: OBSERVATION_PROC + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Data_Length Length of Data in octets + * @param Data Procedure Specific Data: +- For Name Discovery Procedure: the name of the peer device if the procedure completed successfully. + * @retval None +*/ +void aci_gap_proc_complete_event(uint8_t Procedure_Code, + uint8_t Status, + uint8_t Data_Length, + uint8_t Data[]); +/** + * @brief This event is sent only by a privacy enabled Peripheral. The event is sent to the +upper layers when the peripheral is unsuccessful in resolving the resolvable +address of the peer device after connecting to it. + * @param Connection_Handle Connection handle for which the private address could not be +resolved with any of the stored IRK's. + * @retval None +*/ +void aci_gap_addr_not_resolved_event(uint16_t Connection_Handle); +/** + * @brief This event is sent only during SC v.4.2 Pairing, when Numeric Comparison Association model is selected, in order to show the Numeric Value generated, and to ask for Confirmation to the User. When this event is received, the application has to respond with the +@ref aci_gap_numeric_comparison_value_confirm_yesno command + * @param Connection_Handle Connection handle related to the underlying Pairing + * @param Numeric_Value + * @retval None +*/ +void aci_gap_numeric_comparison_value_event(uint16_t Connection_Handle, + uint32_t Numeric_Value); +/** + * @brief This event is sent only during SC v.4.2 Pairing, when Keypress Notifications are supported, in order to show the input type signalled by the peer device, having Keyboard only I/O capabilities. When this event is received, no action is required to the User. + * @param Connection_Handle Connection handle related to the underlying Pairing + * @param Notification_Type Type of Keypress input notified/signaled by peer device (having Keyboard only I/O capabilities + * @retval None +*/ +void aci_gap_keypress_notification_event(uint16_t Connection_Handle, + uint8_t Notification_Type); +/** + * @} + */ +/** + *@defgroup ACI_GATT_ATT_events ACI GATT/ATT events + *@brief ACI GATT/ATT events layer. + *@{ + */ +/* ACI GATT/ATT events */ +/** Documentation for C struct Attribute_Group_Handle_Pair_t */ +typedef struct Attribute_Group_Handle_Pair_t_s { + /** Found Attribute handle + */ + uint16_t Found_Attribute_Handle; + /** Group End handle + */ + uint16_t Group_End_Handle; +} Attribute_Group_Handle_Pair_t; +/** Documentation for C struct Handle_Item_t */ +typedef struct Handle_Item_t_s { + /** + */ + uint16_t Handle; +} Handle_Item_t; +/** + * @brief This event is generated to the application by the GATT server when a client modifies any +attribute on the server, as consequence of one of the following GATT procedures: +- write without response +- signed write without response +- write characteristic value +- write long characteristic value +- reliable write. + * @param Connection_Handle The connection handle which modified the attribute. + * @param Attr_Handle Handle of the attribute that was modified. + * @param Offset SoC mode: the offset is never used and it is always 0. Network coprocessor mode: + - Bits 0-14: offset of the reported value inside the attribute. + - Bit 15: if the entire value of the attribute does not fit inside a single ACI_GATT_ATTRIBUTE_MODIFIED_EVENT event, this bit is set to 1 to notify that other ACI_GATT_ATTRIBUTE_MODIFIED_EVENT events will follow to report the remaining value. + * @param Attr_Data_Length Length of Attr_Data in octets + * @param Attr_Data The modified value + * @retval None +*/ +void aci_gatt_attribute_modified_event(uint16_t Connection_Handle, + uint16_t Attr_Handle, + uint16_t Offset, + uint16_t Attr_Data_Length, + uint8_t Attr_Data[]); +/** + * @brief This event is generated by the client/server to the application on a GATT timeout (30 +seconds). This is a critical event that should not happen during normal operating conditions. It is an indication of either a major disruption in the communication link or a mistake in the application which does not provide a reply to GATT procedures. After this event, the GATT channel is closed and no more GATT communication can be performed. The applications is exptected to issue an @ref aci_gap_terminate to disconnect from the peer device. It is important to leave an 100 ms blank window before sending the @ref aci_gap_terminate, since immediately after this event, system could save important information in non volatile memory. + * @param Connection_Handle Connection handle on which the GATT procedure has timed out + * @retval None +*/ +void aci_gatt_proc_timeout_event(uint16_t Connection_Handle); +/** + * @brief This event is generated in response to an Exchange MTU request. See +@ref aci_gatt_exchange_config. + * @param Connection_Handle Connection handle related to the response + * @param Server_RX_MTU ATT_MTU value agreed between server and client + * @retval None +*/ +void aci_att_exchange_mtu_resp_event(uint16_t Connection_Handle, + uint16_t Server_RX_MTU); +/** + * @brief This event is generated in response to a Find Information Request. See +@ref aci_att_find_info_req and Find Information Response in Bluetooth Core v4.1 +spec. + * @param Connection_Handle Connection handle related to the response + * @param Format Format of the hanndle-uuid pairs + * @param Event_Data_Length Length of Handle_UUID_Pair in octets + * @param Handle_UUID_Pair A sequence of handle-uuid pairs. if format=1, each pair is:[2 octets for handle, 2 octets for UUIDs], if format=2, each pair is:[2 octets for handle, 16 octets for UUIDs] + * @retval None +*/ +void aci_att_find_info_resp_event(uint16_t Connection_Handle, + uint8_t Format, + uint8_t Event_Data_Length, + uint8_t Handle_UUID_Pair[]); +/** + * @brief This event is generated in response to a @ref aci_att_find_by_type_value_req + * @param Connection_Handle Connection handle related to the response + * @param Num_of_Handle_Pair Number of attribute, group handle pairs + * @param Attribute_Group_Handle_Pair See @ref Attribute_Group_Handle_Pair_t + * @retval None +*/ +void aci_att_find_by_type_value_resp_event(uint16_t Connection_Handle, + uint8_t Num_of_Handle_Pair, + Attribute_Group_Handle_Pair_t Attribute_Group_Handle_Pair[]); +/** + * @brief This event is generated in response to a @ref aci_att_read_by_type_req. See +@ref aci_gatt_find_included_services and @ref aci_gatt_disc_all_char_desc. + * @param Connection_Handle Connection handle related to the response + * @param Handle_Value_Pair_Length The size of each attribute handle-value pair + * @param Data_Length Length of Handle_Value_Pair_Data in octets + * @param Handle_Value_Pair_Data Attribute Data List as defined in Bluetooth Core v4.1 spec. A sequence of handle-value pairs: [2 octets for Attribute Handle, (Handle_Value_Pair_Length - 2 octets) for Attribute Value] + * @retval None +*/ +void aci_att_read_by_type_resp_event(uint16_t Connection_Handle, + uint8_t Handle_Value_Pair_Length, + uint8_t Data_Length, + uint8_t Handle_Value_Pair_Data[]); +/** + * @brief This event is generated in response to a Read Request. See @ref aci_gatt_read_char_value. + * @param Connection_Handle Connection handle related to the response + * @param Event_Data_Length Length of following data + * @param Attribute_Value The value of the attribute. + * @retval None +*/ +void aci_att_read_resp_event(uint16_t Connection_Handle, + uint8_t Event_Data_Length, + uint8_t Attribute_Value[]); +/** + * @brief This event can be generated during a read long characteristic value procedure. See @ref aci_gatt_read_long_char_value. + * @param Connection_Handle Connection handle related to the response + * @param Event_Data_Length Length of following data + * @param Attribute_Value Part of the attribute value. + * @retval None +*/ +void aci_att_read_blob_resp_event(uint16_t Connection_Handle, + uint8_t Event_Data_Length, + uint8_t Attribute_Value[]); +/** + * @brief This event is generated in response to a Read Multiple Request. + * @param Connection_Handle Connection handle related to the response + * @param Event_Data_Length Length of following data + * @param Set_Of_Values A set of two or more values. +A concatenation of attribute values for each of the attribute handles in the request in the order that they were requested. + * @retval None +*/ +void aci_att_read_multiple_resp_event(uint16_t Connection_Handle, + uint8_t Event_Data_Length, + uint8_t Set_Of_Values[]); +/** + * @brief This event is generated in response to a Read By Group Type Request. See +@ref aci_gatt_disc_all_primary_services. + * @param Connection_Handle Connection handle related to the response + * @param Attribute_Data_Length The size of each attribute data + * @param Data_Length Length of Attribute_Data_List in octets + * @param Attribute_Data_List Attribute Data List as defined in Bluetooth Core v4.1 spec. A sequence of attribute handle, end group handle, attribute value tuples: [2 octets for Attribute Handle, 2 octets End Group Handle, (Attribute_Data_Length - 4 octets) for Attribute Value] + * @retval None +*/ +void aci_att_read_by_group_type_resp_event(uint16_t Connection_Handle, + uint8_t Attribute_Data_Length, + uint8_t Data_Length, + uint8_t Attribute_Data_List[]); +/** + * @brief This event is generated in response to a @ref aci_att_prepare_write_req. + * @param Connection_Handle Connection handle related to the response + * @param Attribute_Handle The handle of the attribute to be written + * @param Offset The offset of the first octet to be written. + * @param Part_Attribute_Value_Length Length of Part_Attribute_Value in octets + * @param Part_Attribute_Value The value of the attribute to be written + * @retval None +*/ +void aci_att_prepare_write_resp_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint16_t Offset, + uint8_t Part_Attribute_Value_Length, + uint8_t Part_Attribute_Value[]); +/** + * @brief This event is generated in response to an Execute Write Request. + * @param Connection_Handle Connection handle related to the response + * @retval None +*/ +void aci_att_exec_write_resp_event(uint16_t Connection_Handle); +/** + * @brief This event is generated when an indication is received from the server. + * @param Connection_Handle Connection handle related to the response + * @param Attribute_Handle The handle of the attribute + * @param Attribute_Value_Length Length of Attribute_Value in octets + * @param Attribute_Value The current value of the attribute + * @retval None +*/ +void aci_gatt_indication_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint8_t Attribute_Value_Length, + uint8_t Attribute_Value[]); +/** + * @brief This event is generated when a notification is received from the server. + * @param Connection_Handle Connection handle related to the response + * @param Attribute_Handle The handle of the attribute + * @param Attribute_Value_Length Length of Attribute_Value in octets + * @param Attribute_Value The current value of the attribute + * @retval None +*/ +void aci_gatt_notification_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint8_t Attribute_Value_Length, + uint8_t Attribute_Value[]); +/** + * @brief This event is generated when a GATT client procedure completes either with error or +successfully. + * @param Connection_Handle Connection handle related to the response + * @param Error_Code Indicates whether the procedure completed with an error or was successful + * Values: + - 0x00: Success + - 0x01: Unknown HCI Command + - 0x02: Unknown Connection Identifier + - 0x03: Hardware Failure + - 0x04: Page Timeout + - 0x05: Authentication Failure + - 0x06: PIN or Key Missing + - 0x07: Memory Capacity Exceeded + - 0x08: Connection Timeout + - 0x09: Connection Limit Exceeded + - 0x0A: Synchronous Connection Limit to a Device Exceeded + - 0x0B: ACL Connection Already Exists + - 0x0C: Command Disallowed + - 0x0D: Connection Rejected Due To Limited Resources + - 0x0E: Connection Rejected Due To Security Reasons + - 0x0F: Connection Rejected due to Unacceptable BD_ADDR + - 0x10: Connection Accept Timeout Exceeded + - 0x11: Unsupported Feature Or Parameter Value + - 0x12: Invalid HCI Command Parameters + - 0x13: Remote User Terminated Connection + - 0x14: Remote Device Terminated Connection due to Low Resources + - 0x15: Remote Device Terminated Connection due to Power Off + - 0x16: Connection Terminated By Local Host + - 0x17: Repeated Attempts + - 0x18: Pairing Not Allowed + - 0x19: Unknown LMP PDU + - 0x1A: Unsupported Remote Feature / Unsupported LMP Feature + - 0x1B: SCO Offset Rejected + - 0x1C: SCO Interval Rejected + - 0x1D: SCO Air Mode Rejected + - 0x1E: Invalid LMP Parameters + - 0x1F: Unspecified Error + - 0x20: Unsupported LMP Parameter Value + - 0x21: Role Change Not Allowed + - 0x22: LMP Response Timeout / LL Response Timeout + - 0x23: LMP Error Transaction Collision + - 0x24: LMP PDU Not Allowed + - 0x25: Encryption Mode Not Acceptable + - 0x26: Link Key cannot be Changed + - 0x27: Requested QoS Not Supported + - 0x28: Instant Passed + - 0x29: Pairing With Unit Key Not Supported + - 0x2A: Different Transaction Collision + - 0x2C: QoS Unacceptable Parameter + - 0x2D: QoS Rejected + - 0x2E: Channel Assessment Not Supported + - 0x2F: Insufficient Security + - 0x30: Parameter Out Of Mandatory Range + - 0x32: Role Switch Pending + - 0x34: Reserved Slot Violation + - 0x35: Role Switch Failed + - 0x36: Extended Inquiry Response Too Large + - 0x37: Secure Simple Pairing Not Supported by Host + - 0x38: Host Busy - Pairing + - 0x39: Connection Rejected due to No Suitable Channel Found + - 0x3A: Controller Busy + - 0x3B: Unacceptable Connection Interval + - 0x3C: Directed Advertising Timeout + - 0x3D: Connection Terminated Due to MIC Failure + - 0x3E: Connection Failed to be Established + - 0x3F: MAC of the 802.11 AMP + - 0x41: Failed + - 0x42: Invalid parameters + - 0x43: Busy + - 0x44: Invalid length + - 0x45: Pending + - 0x46: Not allowed + - 0x47: GATT error + - 0x48: Address not resolved + - 0x50: Invalid CID + - 0x5A: CSRK not found + - 0x5B: IRK not found + - 0x5C: Device not found in DB + - 0x5D: Security DB full + - 0x5E: Device not bonded + - 0x5F: Device in blacklist + - 0x60: Invalid handle + - 0x61: Invalid parameter + - 0x62: Out of handles + - 0x63: Invalid operation + - 0x64: Insufficient resources + - 0x65: Insufficient encryption key size + - 0x66: Characteristic already exist + - 0x82: No valid slot + - 0x83: Short window + - 0x84: New interval failed + - 0x85: Too large interval + - 0x86: Slot length failed + - 0xFA: Flash read failed + - 0xFB: Flash write failed + - 0xFC: Flash erase failed + * @retval None +*/ +void aci_gatt_proc_complete_event(uint16_t Connection_Handle, + uint8_t Error_Code); +/** + * @brief This event is generated when an Error Response is received from the server. The error +response can be given by the server at the end of one of the GATT discovery procedures. +This does not mean that the procedure ended with an error, but this error event is part of the +procedure itself. + * @param Connection_Handle Connection handle related to the response + * @param Req_Opcode The request that generated this error response + * @param Attribute_Handle The attribute handle that generated this error response + * @param Error_Code The reason why the request has generated an error response (ATT error codes) + * Values: + - 0x01: Invalid handle + - 0x02: Read not permitted + - 0x03: Write not permitted + - 0x04: Invalid PDU + - 0x05: Insufficient authentication + - 0x06: Request not supported + - 0x07: Invalid offset + - 0x08: Insufficient authorization + - 0x09: Prepare queue full + - 0x0A: Attribute not found + - 0x0B: Attribute not long + - 0x0C: Insufficient encryption key size + - 0x0D: Invalid attribute value length + - 0x0E: Unlikely error + - 0x0F: Insufficient encryption + - 0x10: Unsupported group type + - 0x11: Insufficient resources + * @retval None +*/ +void aci_gatt_error_resp_event(uint16_t Connection_Handle, + uint8_t Req_Opcode, + uint16_t Attribute_Handle, + uint8_t Error_Code); +/** + * @brief This event can be generated during a "Discover Characteristics By UUID" procedure or a +"Read using Characteristic UUID" procedure. +The attribute value will be a service declaration as defined in Bluetooth Core v4.1spec +(vol.3, Part G, ch. 3.3.1), when a "Discover Characteristics By UUID" has been started. It will +be the value of the Characteristic if a* "Read using Characteristic UUID" has been +performed. + * @param Connection_Handle Connection handle related to the response + * @param Attribute_Handle The handle of the attribute + * @param Attribute_Value_Length Length of Attribute_Value in octets + * @param Attribute_Value The attribute value will be a service declaration as defined in Bluetooth Core v4.0 spec + (vol.3, Part G, ch. 3.3.1), when a "Discover Characteristics By UUID" has been started. + It will be the value of the Characteristic if a "Read using Characteristic UUID" has been performed. + * @retval None +*/ +void aci_gatt_disc_read_char_by_uuid_resp_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint8_t Attribute_Value_Length, + uint8_t Attribute_Value[]); +/** + * @brief This event is given to the application when a write request, write command or signed write +command is received by the server from the client. This event will be given to the application +only if the event bit for this event generation is set when the characteristic was added. +When this event is received, the application has to check whether the value being requested +for write can be allowed to be written and respond with the command @ref aci_gatt_write_resp. +The details of the parameters of the command can be found. Based on the response from +the application, the attribute value will be modified by the stack. If the write is rejected by the +application, then the value of the attribute will not be modified. In case of a write REQ, an +error response will be sent to the client, with the error code as specified by the application. +In case of write/signed write commands, no response is sent to the client but the attribute is +not modified. + * @param Connection_Handle Handle of the connection on which there was the request to write the attribute + * @param Attribute_Handle The handle of the attribute + * @param Data_Length Length of Data field + * @param Data The data that the client has requested to write + * @retval None +*/ +void aci_gatt_write_permit_req_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint8_t Data_Length, + uint8_t Data[]); +/** + * @brief This event is given to the application when a read request or read blob request is received +by the server from the client. This event will be given to the application only if the event bit +for this event generation is set when the characteristic was added. +On receiving this event, the application can update the value of the handle if it desires and +when done, it has to send the @ref aci_gatt_allow_read command to indicate to the stack that it +can send the response to the client. + * @param Connection_Handle Connection handle related to the response + * @param Attribute_Handle The handle of the attribute + * @param Offset Contains the offset from which the read has been requested + * @retval None +*/ +void aci_gatt_read_permit_req_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint16_t Offset); +/** + * @brief This event is given to the application when a read multiple request or read by type request is +received by the server from the client. This event will be given to the application only if the +event bit for this event generation is set when the characteristic was added. +On receiving this event, the application can update the values of the handles if it desires and +when done, it has to send the @ref aci_gatt_allow_read command to indicate to the stack that it +can send the response to the client. + * @param Connection_Handle Handle of the connection which requested to read the attribute + * @param Number_of_Handles + * @param Handle_Item See @ref Handle_Item_t + * @retval None +*/ +void aci_gatt_read_multi_permit_req_event(uint16_t Connection_Handle, + uint8_t Number_of_Handles, + Handle_Item_t Handle_Item[]); +/** + * @brief Each time BLE FW stack raises the error code @ref ble_status_insufficient_resources (0x64), +the @ref aci_gatt_tx_pool_available_event event is generated as soon as the available buffer size +is greater than maximum ATT MTU (on stack versions below v2.1 this event is generated when at least 2 packets +with MTU of 23 bytes are available). + * @param Connection_Handle Connection handle related to the request + * @param Available_Buffers Not used. + * @retval None +*/ +void aci_gatt_tx_pool_available_event(uint16_t Connection_Handle, + uint16_t Available_Buffers); +/** + * @brief This event is generated when the client has sent the confirmation to a previously sent indication + * @param Connection_Handle Connection handle related to the event + * @retval None +*/ +void aci_gatt_server_confirmation_event(uint16_t Connection_Handle); +/** + * @brief This event is given to the application when a prepare write request +is received by the server from the client. This event will be given to the application +only if the event bit for this event generation is set when the characteristic was added. +When this event is received, the application has to check whether the value being requested +for write can be allowed to be written and respond with the command @ref aci_gatt_write_resp. +Based on the response from the application, the attribute value will be modified by the stack. +If the write is rejected by the application, then the value of the attribute will not be modified +and an error response will be sent to the client, with the error code as specified by the application. + * @param Connection_Handle Handle of the connection on which there was the request to write the attribute + * @param Attribute_Handle The handle of the attribute + * @param Offset The offset from which the prepare write has been requested + * @param Data_Length Length of Data field + * @param Data The data that the client has requested to write + * @retval None +*/ +void aci_gatt_prepare_write_permit_req_event(uint16_t Connection_Handle, + uint16_t Attribute_Handle, + uint16_t Offset, + uint8_t Data_Length, + uint8_t Data[]); +/** + * @} + */ +/** + *@defgroup ACI_L2CAP_events ACI L2CAP events + *@brief ACI L2CAP events layer. + *@{ + */ +/* ACI L2CAP events */ +/** + * @brief This event is generated when the master responds to the connection update request packet +with a connection update response packet. + * @param Connection_Handle Connection handle referring to the COS Channel where the Disconnection has been received. + * @param Result + * @retval None +*/ +void aci_l2cap_connection_update_resp_event(uint16_t Connection_Handle, + uint16_t Result); +/** + * @brief This event is generated when the master does not respond to the connection update +request packet with a connection update response packet or a command reject packet +within 30 seconds. + * @param Connection_Handle Handle of the connection related to this +L2CAP procedure. + * @param Data_Length Length of following data + * @param Data + * @retval None +*/ +void aci_l2cap_proc_timeout_event(uint16_t Connection_Handle, + uint8_t Data_Length, + uint8_t Data[]); +/** + * @brief The event is given by the L2CAP layer when a connection update request is received from +the slave. The upper layer which receives this event has to respond by sending a +@ref aci_l2cap_connection_parameter_update_resp command. + * @param Connection_Handle Handle of the connection related to this +L2CAP procedure. + * @param Identifier This is the identifier which associate the request to the +response. + * @param L2CAP_Length Length of the L2CAP connection update request. + * @param Interval_Min Minimum value for the connection event interval. This shall be less +than or equal to Conn_Interval_Max. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Interval_Max Maximum value for the connection event interval. This shall be +greater than or equal to Conn_Interval_Min. +Time = N * 1.25 msec. + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Slave_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Timeout_Multiplier Defines connection timeout parameter in the following manner: Timeout Multiplier * 10ms. + * @retval None +*/ +void aci_l2cap_connection_update_req_event(uint16_t Connection_Handle, + uint8_t Identifier, + uint16_t L2CAP_Length, + uint16_t Interval_Min, + uint16_t Interval_Max, + uint16_t Slave_Latency, + uint16_t Timeout_Multiplier); +/** + * @brief This event is generated when the master responds to the connection update request packet +with a command reject packet. + * @param Connection_Handle Connection handle referring to the COS Channel where the Disconnection has been received. + * @param Identifier This is the identifier which associate the request to the +response. + * @param Reason Reason + * @param Data_Length Length of following data + * @param Data Data field associated with Reason + * @retval None +*/ +void aci_l2cap_command_reject_event(uint16_t Connection_Handle, + uint8_t Identifier, + uint16_t Reason, + uint8_t Data_Length, + uint8_t Data[]); +/** + * @} + */ +/** + *@defgroup ACI_HAL_events ACI HAL events + *@brief ACI HAL events layer. + *@{ + */ +/* ACI HAL events */ +/** + * @brief 'This event is generated when the device completes a radio activity and provide information when a new radio acitivity will be performed. +Informtation provided includes type of radio activity and absolute time in system ticks when a new radio acitivity is schedule, if any. Application can use this information to schedule user activities synchronous to selected radio activitities. A command @ref aci_hal_set_radio_activity_mask is provided to enable radio activity events of user interests, by default no events are enabled. +User should take into account that enablinng radio events in application with intense radio activity could lead to a fairly high rate of events generated. +Application use cases includes synchronizing notification with connection interval, switiching antenna at the end of advertising or performing flash erase operation while radio is idle. + * @param Last_State Completed radio events + * Values: + - 0x00: Idle + - 0x01: Advertising + - 0x02: Connection event slave + - 0x03: Scanning + - 0x04: Connection request + - 0x05: Connection event master + - 0x06: TX test mode + - 0x07: RX test mode + * @param Next_State Incoming radio events + * Values: + - 0x00: Idle + - 0x01: Advertising + - 0x02: Connection event slave + - 0x03: Scanning + - 0x04: Connection request + - 0x05: Connection event master + - 0x06: TX test mode + - 0x07: RX test mode + * @param Next_State_SysTime 32bit absolute current time expressed in internal time units. + * @retval None +*/ +void aci_hal_end_of_radio_activity_event(uint8_t Last_State, + uint8_t Next_State, + uint32_t Next_State_SysTime); +/** + * @brief This event is reported to the application after a scan request is received and a scan reponse +is scheduled to be transmitted. + * @param RSSI N Size: 1 Octet (signed integer) +Units: dBm + * Values: + - 127: RSSI not available + - -127 ... 20 + * @param Peer_Address_Type 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + * @param Peer_Address Public Device Address or Random Device Address of the peer device + * @retval None +*/ +void aci_hal_scan_req_report_event(uint8_t RSSI, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6]); +/** + * @brief This event is generated to report firmware error informations. + * @param FW_Error_Type FW Error type + * Values: + - 0x01: L2CAP recombination failure + * @param Data_Length Length of Data in octets + * @param Data The error event info + * @retval None +*/ +void aci_hal_fw_error_event(uint8_t FW_Error_Type, + uint8_t Data_Length, + uint8_t Data[]); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BLUENRG1_EVENTS_H_ */ diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_stack.h b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_stack.h new file mode 100644 index 00000000000..7743dad7695 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/bluenrg1_stack.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef BLUENRG1_STACK_H +#define BLUENRG1_STACK_H + +#include +#include +#include + +#define MIN(a,b) (((a) < (b))? (a) : (b)) +#define MAX(a,b) (((a) > (b))? (a) : (b)) +#define DIV_CEIL(x, y) (((x) + (y) - 1) / (y)) + +/** + * DEFAULT_ATT_MTU: minimum mtu value that GATT must support. + * 5.2.1 ATT_MTU, BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] + */ +#define DEFAULT_ATT_MTU (23) + +#define MEM_BLOCK_SIZE (32) + +/** + * SM_SECURE_CONN_MTU: mtu size needed for Security Manager Channel Configuration + * Parameters with LE Secure Connections. + * 3.2 SECURITY MANAGER CHANNEL OVER L2CAP, BLUETOOTH SPECIFICATION Version 4.2 + * [Vol 3, Part H] + */ +#define SM_SECURE_CONN_MTU (65) + +/** + * DEFAULT_MAX_ATT_MTU: maximum supported ATT_MTU size. + */ +#define DEFAULT_MAX_ATT_MTU (251 - 4) // (4 bytes for L2CAP header) + +/** + * DEFAULT_MAX_ATT_SIZE: maximum attribute size. + */ +#define DEFAULT_MAX_ATT_SIZE (512) + +/** + * PREP_WRITE_X_ATT(max_att): compute how many Prepare Write Request are needed + * to write a characteristic with size max_att when the used ATT_MTU value is + * equal to DEFAULT_ATT_MTU (23). + */ +#define PREP_WRITE_X_ATT(max_att) (DIV_CEIL(max_att, DEFAULT_ATT_MTU - 5U) * 2) + +/** + * MEM_BLOCK_X_MTU(mtu, n_links): compute how many memory blocks are needed to + * support a maximum number (n_links)of simultaneous connections that use ATT + * packet with ATT_MTU=mtu. + * 7.2 FRAGMENTATION AND RECOMBINATION, BLUETOOTH SPECIFICATION Version 4.2 + * [Vol 3, Part A] + */ + +#define MEM_BLOCK_X_TX(mtu) (DIV_CEIL((mtu) + 4U, MEM_BLOCK_SIZE) + 1U) +#define MEM_BLOCK_X_RX(mtu, n_link) ((DIV_CEIL((mtu) + 4U, MEM_BLOCK_SIZE) + 2U) * (n_link) + 1) +#define MEM_BLOCK_X_MTU(mtu, n_link) (MEM_BLOCK_X_TX(mtu) + MEM_BLOCK_X_RX(mtu, (n_link))) + +/** + * Minimum number of blocks required for secure connections + */ +#define MBLOCKS_SECURE_CONNECTIONS (4) + +/** + * MBLOCKS_CALC(pw, mtu, n_link): minimum number of buffers needed by the stack. + * This is the minimum racomanded value and depends on: + * - pw: size of Prepare Write List + * - mtu: ATT_MTU size + * - n_link: maximum number of simultaneous connections + */ +#define MBLOCKS_CALC(pw, mtu, n_link) ((pw) + MAX(MEM_BLOCK_X_MTU(mtu, n_link), (MBLOCKS_SECURE_CONNECTIONS))) + +/** + * DEFAULT_PREP_WRITE_LIST_SIZE: default minimum Prepare Write List size. + */ +#define DEFAULT_PREP_WRITE_LIST_SIZE PREP_WRITE_X_ATT(DEFAULT_MAX_ATT_SIZE) + +/** + * DEFAULT_MBLOCKS_COUNT: default memory blocks count + */ +#define DEFAULT_MBLOCKS_COUNT MBLOCKS_CALC(DEFAULT_PREP_WRITE_LIST_SIZE, DEFAULT_MAX_ATT_MTU, NUM_LINKS) + +/** + * A part of the RAM, is dinamically allocated by initilizing all the pointers + * defined in a global context variable "mem_alloc_ctx_p". + * This initialization is made in the Dynamic_allocator functions, which + * assing a portion of RAM given by the external application to the above + * mentioned "global pointers". + * + * The size of this Dynamic RAM is made of 2 main components: + * - a part that is parameters-dependent (num of links, GATT buffers, ...), + * and which value is explicited by the following macro; + * - a part, that may be considered "fixed", i.e. independent from the above + * mentioned parameters. +*/ +#define FIXED_BUFFER_SIZE_BYTES (4948+1492+32+4+4-36-8+16) + +/** + * D_LEN_EXT_SIZE: amount of memory needed to support Data Length Extension + * feature. + */ +#define D_LEN_EXT_SIZE(ENABLED) (((ENABLED) == 1) ? (436) : (0)) + +/** + * + * This macro returns the amount of memory, in bytes, needed for the storage of GATT database elements + * and other data structures whose size depends on the number of supported connections. + * + * @param NUM_LINKS: Maximum number of simultaneous connections that the device will support. Valid values are from 1 to 8. + * @param NUM_GATT_ATTRIBUTES: Maximum number of Attributes (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services) that can be stored in the GATT database. Note that certain characteristics and relative descriptors are added automatically during device initialization so this parameters should be 9 plus the number of user Attributes + * @param NUM_GATT_SERVICES: Maximum number of Services that can be stored in the GATT database. Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services + * @param ATT_VALUE_ARRAY_SIZE: Size of the storage area for Attribute values. + * @param MBLOCKS_COUNT: Number of memory blocks allocated for packets. + * @param D_LEN_EXT_EN: Enable or disable the Extended Packet length feature. Valid values are 0 or 1. + */ +#define TOTAL_BUFFER_SIZE(NUM_LINKS,NUM_GATT_ATTRIBUTES,NUM_GATT_SERVICES,ATT_VALUE_ARRAY_SIZE,MBLOCKS_COUNT,D_LEN_EXT_EN) (\ + FIXED_BUFFER_SIZE_BYTES + \ + ((((ATT_VALUE_ARRAY_SIZE) - 1) | 3) + 1) + \ + (332 * (NUM_LINKS)) + \ + (40 * (NUM_GATT_ATTRIBUTES)) + \ + (48 * (NUM_GATT_SERVICES)) + \ + ((MEM_BLOCK_SIZE + 12) * (MBLOCKS_COUNT)) + \ + D_LEN_EXT_SIZE(D_LEN_EXT_EN) \ +) + +/** +* +* This macro returns the amount of memory, in bytes, needed for the storage of non-volatile data for bonded devices +* +* @param FLASH_SEC_DB_SIZE: Size of the database used to store security information for bonded devices. The recommended value for this parameter is 1024. +* @param FLASH_SERVER_DB_SIZE: Size of the database used for service change notification for bonded devices. The recommended value for this parameter is 1024. +* @note: the total buffer size is rounded-up to the next multiple of on flash sector size, i.e. 2048 bytes +*/ +#define TOTAL_FLASH_BUFFER_SIZE(FLASH_SEC_DB_SIZE, FLASH_SERVER_DB_SIZE) (\ + ((((FLASH_SEC_DB_SIZE+FLASH_SERVER_DB_SIZE)-1)|2047)+1)\ + ) + +/** +* This symbol defines the size of non-volatile device identification data +*/ +#define TOTAL_DEVICE_ID_DATA_SIZE (56) + +/** @defgroup Master_Sleep_Clock_Accuracy_Definitions Master Sleep Clock Accuracy Definitions + * @{ + */ +#define MASTER_SCA_500ppm 0 /*!< 251 ppm to 500 ppm */ +#define MASTER_SCA_250ppm 1 /*!< 151 ppm to 250 ppm */ +#define MASTER_SCA_150ppm 2 /*!< 101 ppm to 150 ppm */ +#define MASTER_SCA_100ppm 3 /*!< 76 ppm to 100 ppm */ +#define MASTER_SCA_75ppm 4 /*!< 51 ppm to 75 ppm */ +#define MASTER_SCA_50ppm 5 /*!< 31 ppm to 50 ppm */ +#define MASTER_SCA_30ppm 6 /*!< 21 ppm to 30 ppm */ +#define MASTER_SCA_20ppm 7 /*!< 0 ppm to 20 ppm */ +/** + * @} + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** +* +* This structure contains low level hardware configuration data for the device +*/ +typedef struct { + uint32_t *hot_ana_config_table; /**< Set to NULL */ + uint32_t max_conn_event_length; /**< Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us) */ + uint16_t slave_sca ; /**< Sleep clock accuracy in Slave mode (ppm value)*/ + uint8_t master_sca ; /**< Sleep clock accuracy in Master mode (0 to 7 corresponding to 500, 250, 150, 100, 75, 50, 30, 20 ppm)*/ + uint8_t ls_source; /**< Source for the 32 kHz slow speed clock: 1: internal RO; 0: external crystal */ + uint16_t hs_startup_time ; /**< Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)*/ +} hardware_config_table_t; + +/** +* +* This structure contains memory and low level hardware configuration data for the device +*/ +typedef struct { + uint8_t* bleStartFlashAddress; /**< Start address for the non-volatile memory area allocated according to TOTAL_FLASH_BUFFER_SIZE (Aligned to 2048 bytes flash sector boundary) */ + uint32_t secDbSize; /**< Size of the database used to store security information for bonded devices (FLASH_SEC_DB_SIZE used in the calculation of TOTAL_FLASH_BUFFER_SIZE). Current SUPPORTED VALUE is 1024 */ + uint32_t serverDbSize; /**< Size of the database used for service change notification for bonded devices (FLASH_SERVER_DB_SIZE used in the calculation of TOTAL_FLASH_BUFFER_SIZE). Current SUPPORTED VALUE is 1024 */ + uint8_t* stored_device_id_data_p; /**< Address of the const device id data vector (56 bytes, 32bit aligned FLASH area, all elements must be initialized to 0xFF) */ + uint8_t* bleStartRamAddress; /**< Start address of the RAM buffer for GATT database allocated according to TOTAL_BUFFER_SIZE (32bit aligned RAM area) */ + uint32_t total_buffer_size; /**< TOTAL_BUFFER_SIZE return value, used to check the MACRO correctness*/ + uint16_t numAttrRecord; /**< Maximum number of Attributes (i.e. the number of characteristic + the number of characteristic values + the number of descriptors, excluding the services) that can be stored in the GATT database. Note that certain characteristics and relative descriptors are added automatically during device initialization so this parameters should be 9 plus the number of user Attributes (NUM_GATT_ATTRIBUTES used in the calculation of TOTAL_BUFFER_SIZE) */ + uint16_t numAttrServ; /**< Maximum number of Services that can be stored in the GATT database. Note that the GAP and GATT services are automatically added so this parameter should be 2 plus the number of user services (NUM_GATT_SERVICES used in the calculation of TOTAL_BUFFER_SIZE)*/ + uint16_t attrValueArrSize; /**< Size of the storage area for Attribute values (ATT_VALUE_ARRAY_SIZE used in the calculation of TOTAL_BUFFER_SIZE) + This value depends on the number of attributes used by application. In particular the sum of the following quantities (in octets) should be made for each attribute: + - attribute value length + - 5, if UUID is 16 bit; 19, if UUID is 128 bit + - 2, if server configuration descriptor is used + - 2*numOfLinks, if client configuration descriptor is used + - 2, if extended properties is used + + The total amount of memory needed is the sum of the above quantities for each attribute. +*/ + uint8_t numOfLinks; /**< Maximum number of simultaneous connections that the device will support. Valid values are from 1 to 8 (NUM_LINKS used in the calculation of TOTAL_BUFFER_SIZE). */ + uint8_t extended_packet_length_enable; /**unsupported feature (reserved for future use)*/ + uint8_t prWriteListSize; /**< Prepare Write List size in terms of number of packet with ATT_MTU=23 bytes */ + uint8_t mblockCount; /**< Number of allocated memory blocks */ + uint16_t attMtu; /**< Maximum supported ATT_MTU size */ + hardware_config_table_t hardware_config; /**< Structure containing low level hardware configuration data for the device */ +} BlueNRG_Stack_Initialization_t; + + +/** + * @brief This function executes the processing of all Host Stack layers. + * + * The BTLE Stack Tick function has to be executed regularly to process incoming Link Layer packets and to process Host Layers procedures. All + * stack callbacks are called by this function. + * + * If Low Speed Ring Oscillator is used instead of the LS Crystal oscillator this function performs also the LS RO calibration and hence must + * be called at least once at every system wake-up in order to keep the 500 ppm accuracy (at least 500 ppm accuracy is mandatory if acting as a master). + * + * No BTLE stack function must be called while the BTLE_StackTick is running. For example, if a BTLE stack function may be called inside an + * interrupt routine, that interrupt must be disabled during the execution of BTLE_StackTick(). Example (if a stack function may be called inside + * UART ISR): + * @code + * NVIC_DisableIRQ(UART_IRQn); + * BTLE_StackTick(); + * NVIC_EnableIRQ(UART_IRQn); + * @endcode + + * @note The API name and parameters are subject to change in future releases. + * @return None + */ +void BTLE_StackTick(void); + + +/** + * @brief The BTLE Stack initialization routine + * + * @note The API name and parameters are subject to change in future releases. + * + * @param[in] BlueNRG_Stack_Init_params_p pointer to the const structure containing memory and low level + * hardware configuration data for the device + * + * @return Value indicating success or error code. + * + */ +tBleStatus BlueNRG_Stack_Initialization(const BlueNRG_Stack_Initialization_t *BlueNRG_Stack_Init_params_p); + + +/** + * @brief Returns the BTLE Stack matching sleep mode + * + * @note The API name and parameters are subject to change in future releases. + * + * @return + * SLEEPMODE_RUNNING = 0, + * SLEEPMODE_CPU_HALT = 1, + * SLEEPMODE_WAKETIMER = 2, + * SLEEPMODE_NOTIMER = 3, + */ +uint8_t BlueNRG_Stack_Perform_Deep_Sleep_Check(void); + +/** + * + * @brief Radio ISR routine. + * + * This is the base function called for any radio ISR. + * + * @return None + */ + + +void RAL_Isr(void); +/** + * @brief Starts a one-shot virtual timer for the given relative timeout value expressed in ms + * + * @note The API name and parameters are subject to change in future releases. + * + * @param[in] timerNum The virtual timer number [0..3] + * @param[in] msRelTimeout The relative time, from current time, expressed in ms + * Note: abs(msRelTimeout) <= 5242879 + * + * @return 0 if the timerNum virtual timer is valid. + */ +int HAL_VTimerStart_ms(uint8_t timerNum, int32_t msRelTimeout); + +/** + * @brief Stops the one-shot virtual timer specified if found + * + * @note The API name and parameters are subject to change in future releases. + * + * @param[in] timerNum The virtual timer number [0..3] + * + * @return None + */ +void HAL_VTimer_Stop(uint8_t timerNum); + +/** + * @brief Virtual timer callback + * + * This function will be called on the expiry of a one-shot virtual timer. + * HAL_VTimerTimeoutCallback will notify the virtual timer number. + * + * @note The API name and parameters are subject to change in future releases. + * + * @param[in] timerNum The virtual timer number [0..3] + * + * @return None + */ +void HAL_VTimerTimeoutCallback(uint8_t timerNum); + +/** + * @brief This function return the current reference time expressed in internal time units. + * + * The returned value can be used as absolute time parameter where needed in the other + * HAL_VTimer* APIs + * + * @note The API name and parameters are subject to change in future releases. + * + * @return 32bit absolute current time expressed in internal time units. + */ +uint32_t HAL_VTimerGetCurrentTime_sysT32(void); + +/** + * @brief This function returns the sum of an absolute time and a signed relative time. + * + * @param[in] sysTime Absolute time expressed in internal time units. + * @param[in] msTime Signed relative time expressed in ms. + * Note: abs(msTime) <= 5242879 + * + * @note The API name and parameters are subject to change in future releases. + * + * @return 32bit resulting absolute time expressed in internal time units. + */ +uint32_t HAL_VTimerAcc_sysT32_ms(uint32_t sysTime, int32_t msTime); + + +/** + * @brief Returns a time difference. + * + * This function return the difference between two absolute times: sysTime1-sysTime2. + * The resulting value is expressed in ms. + * + * @param[in] sysTime1 Absolute time expressed in internal time units. + * @param[in] sysTime2 Absolute time expressed in internal time units. + * + * @note The API name and parameters are subject to change in future releases. + * @return 32bit resulting signed relative time expressed in ms. + */ +int32_t HAL_VTimerDiff_ms_sysT32(uint32_t sysTime1, uint32_t sysTime2); + +/** + * @brief Starts a one-shot timer. + * + * Starts a one-shot virtual timer for the given absolute timeout value expressed in + * internal time units. + * + * @param[in] timerNum The virtual timer number [0..3] + * @param[in] time Absolute time expressed in internal time units. + * + * @note The API name and parameters are subject to change in future releases. + * @return 0 if the timerNum virtual timer is idle. + */ +int HAL_VTimerStart_sysT32(uint8_t timerNum, uint32_t time); + + +/** + * @brief Returns the absolute expiry time of a running timer. + * + * Returned time is expressed in internal time units. + * + * @note The API name and parameters are subject to change in future releases. + * + * @param[in] timerNum The virtual timer number [0..3] + * @param[out] sysTime Absolute time expressed in internal time units. + * + * @return 0 if the timerNum virtual timer is running. + */ +int HAL_VTimerExpiry_sysT32(uint8_t timerNum, uint32_t *sysTime); + +/** + * @brief This callback is called by the stack library to indicate the arrival of an ACL Data Packet. + * + * @note The API name and parameters are subject to change in future releases. + * + * @param[in] connHandle Connection handle for which the command is given. Range: 0x0000-0x0EFF (0x0F00 - 0x0FFF Reserved for future use) + * @param[in] pb_flag Packet boundary flag + * @param[in] bc_flag Broadcast flag + * @param[in] dataLen Length of PDU data in octets. + * @param[in] pduData PDU data pointer + * + * @return void + */ + +tBleStatus hci_rx_acl_data_event(uint16_t connHandle, uint8_t pb_flag, uint8_t bc_flag, uint16_t dataLen, uint8_t* pduData); + +/** + * @brief API used to send HCI ACL Data Packets to exchange data between the Host and Controller. + * + * @note The API name is only available in link layer only mode. + * + * @param[in] connHandle Connection handle for which the command is given. Range: 0x0000-0x0EFF (0x0F00 - 0x0FFF Reserved for future use) + * @param[in] pb_flag Packet boundary flag + * @param[in] bc_flag Broadcast flag + * @param[in] dataLen Length of PDU data in octets. + * @param[in] pduData PDU data pointer + * + * @return Error code + */ + +tBleStatus hci_tx_acl_data(uint16_t connHandle, uint8_t pb_flag, uint8_t bc_flag, uint16_t dataLen, uint8_t* pduData); + +#ifdef __cplusplus +} +#endif + +#endif // defined( BLUENRG1_STACK_H ) + diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/inc/stack_user_cfg.h b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/stack_user_cfg.h new file mode 100644 index 00000000000..904d90d2ed0 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/inc/stack_user_cfg.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef _STACK_USER_CFG_H_ +#define _STACK_USER_CFG_H_ + + +/* --------------------- BLE stack configuration options --------------------------------------------------- */ + +/** + * @brief BLE stack full configuration: all available modules are included + */ +#define BLE_STACK_FULL_CONFIGURATION (0U) + +/** + * @brief BLE stack basic configuration: no Controller Privacy, no LE Secure Connections, no Master GAP role, no Data Length Extension + */ +#define BLE_STACK_BASIC_CONFIGURATION (1U) + +/** + * @brief BLE OTA Service support, BLE stack configuration with Data Length Extension (BlueNRG-2, BLE stack v2.1) + */ +#define BLE_OTA_BASIC_CONFIGURATION (2U) + +/* Select default configuration */ +#ifndef BLE_STACK_CONFIGURATION +#error "you shall define basic configuration" +/** +* @brief BLE stack default configuration +*/ +#define BLE_STACK_CONFIGURATION BLE_STACK_FULL_CONFIGURATION +#endif + +/* --------------------- BLE stack configuration options and associated module inclusion -------------------- */ + +/** + * @brief Full BLE stack configuration + */ +#if (BLE_STACK_CONFIGURATION == BLE_STACK_FULL_CONFIGURATION) + +/* Controller Privacy module: ENABLED */ +#define CONTROLLER_PRIVACY_ENABLED (1U) + +/* LE Secure Connections module: ENABLED */ +#define SECURE_CONNECTIONS_ENABLED (1U) + +/* Master GAP role module: ENABLED */ +#define CONTROLLER_MASTER_ENABLED (1U) + +#ifdef BLUENRG2_DEVICE + + /* Data length extension module: ENABLED */ + #define CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED (1U) + +#else /* BlueNRG-1 device doesn't support Data length extension */ + + /* Data length extension module: DISABLED */ + #define CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED (0U) + +#endif + +/** + * @brief Basic BLE stack configuration + */ +#elif (BLE_STACK_CONFIGURATION == BLE_STACK_BASIC_CONFIGURATION) + +/* Controller Privacy module: DISABLED */ +#define CONTROLLER_PRIVACY_ENABLED (0U) + +/* LE Secure Connections module: DISABLED */ +#define SECURE_CONNECTIONS_ENABLED (0U) + +/* Master GAP role module: DISABLED */ +#define CONTROLLER_MASTER_ENABLED (0U) + +/* Data length extension module: DISABLED */ +#define CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED (0U) + +/** + * @brief BLE OTA Service support, BLE stack configuration with Data Length Extension (BlueNRG-2, BLE stack v2.1) + */ +#elif (BLE_STACK_CONFIGURATION == BLE_OTA_BASIC_CONFIGURATION) + +/* Controller Privacy module: DISABLED */ +#define CONTROLLER_PRIVACY_ENABLED (0U) + +/* LE Secure Connections module: DISABLED */ +#define SECURE_CONNECTIONS_ENABLED (0U) + +/* Master GAP role module: DISABLED */ +#define CONTROLLER_MASTER_ENABLED (0U) + +#ifdef BLUENRG2_DEVICE + + /* Data length extension module: ENABLED */ + #define CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED (1U) + +#else /* BlueNRG-1 device doesn't support Data length extension */ + + /* Data length extension module: DISABLED */ + #define CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED (0U) + +#endif +#endif +#endif /* _STACK_USER_CFG_H_ */ + diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/library/libbluenrg1_stack.a b/targets/TARGET_STMBLUE/Bluetooth_LE/library/libbluenrg1_stack.a new file mode 100644 index 00000000000..960b2668a9f Binary files /dev/null and b/targets/TARGET_STMBLUE/Bluetooth_LE/library/libbluenrg1_stack.a differ diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_dle_api_stubs.c b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_dle_api_stubs.c new file mode 100644 index 00000000000..ef9d8c1f8f2 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_dle_api_stubs.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "stack_user_cfg.h" + +#ifdef CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED +#if (CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED == 0) + +#include +#include "bluenrg1_api.h" + +#define ERR_UNKNOWN_HCI_COMMAND (0x01) + +/* APIs definitions */ +tBleStatus hci_le_set_data_length(uint16_t Connection_Handle, uint16_t TxOctets, uint16_t TxTime) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_read_suggested_default_data_length(uint16_t *SuggestedMaxTxOctets, uint16_t *SuggestedMaxTxTime) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_write_suggested_default_data_length(uint16_t SuggestedMaxTxOctets, uint16_t SuggestedMaxTxTime) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_read_maximum_data_length(uint16_t *supportedMaxTxOctets, uint16_t *supportedMaxTxTime, + uint16_t *supportedMaxRxOctets, uint16_t *supportedMaxRxTime) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} +#endif +#endif + diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_priv_api_stubs.c b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_priv_api_stubs.c new file mode 100644 index 00000000000..85767d551c7 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_priv_api_stubs.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "stack_user_cfg.h" + +#ifdef CONTROLLER_PRIVACY_ENABLED +#if (CONTROLLER_PRIVACY_ENABLED == 0) + +#include +#include "bluenrg1_api.h" + +#define ERR_UNKNOWN_HCI_COMMAND (0x01) + +/* APIs definitions */ +tBleStatus aci_gap_add_devices_to_resolving_list(uint8_t Num_of_Resolving_list_Entries, Whitelist_Identity_Entry_t Whitelist_Identity_Entry[], uint8_t Clear_Resolving_List) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_remove_device_from_resolving_list(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_add_device_to_resolving_list(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Peer_IRK[16], uint8_t Local_IRK[16]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_set_resolvable_private_address_timeout(uint16_t RpaTimeout) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_set_address_resolution_enable(uint8_t AddressResolutionEnable) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_read_peer_resolvable_address(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Peer_Resolvable_Address[6]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_read_local_resolvable_address(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Local_Resolvable_Address[6]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_read_resolving_list_size(uint8_t *resolving_List_Size) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +uint8_t hci_le_clear_resolving_list(void) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_set_privacy_mode(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Privacy_Mode) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} +#endif +#endif diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_sc_api_stubs.c b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_sc_api_stubs.c new file mode 100644 index 00000000000..a2f2faa3a29 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_sc_api_stubs.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "stack_user_cfg.h" + +#ifdef SECURE_CONNECTIONS_ENABLED +#if (SECURE_CONNECTIONS_ENABLED == 0) + +#include "compiler.h" +#include "bluenrg1_api.h" + +#define ERR_UNKNOWN_HCI_COMMAND (0x01) + +/* APIs definitions */ +tBleStatus aci_gap_passkey_input(uint16_t Connection_Handle, uint8_t Input_Type) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_numeric_comparison_value_confirm_yesno(uint16_t Connection_Handle, uint8_t Confirm_Yes_No) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_read_local_p256_public_key(void) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_generate_dhkey(uint8_t Remote_P256_Public_Key[64]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} +#endif +#endif diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_slvonly_api_stubs.c b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_slvonly_api_stubs.c new file mode 100644 index 00000000000..92799a5a776 --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_slvonly_api_stubs.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "stack_user_cfg.h" + +#ifdef CONTROLLER_MASTER_ENABLED +#if (CONTROLLER_MASTER_ENABLED == 0) + +#include +#include "bluenrg1_api.h" + +#define ERR_UNKNOWN_HCI_COMMAND (0x01) + +/* APIs definitions */ +tBleStatus aci_gap_start_auto_connection_establish_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_general_connection_establish_proc(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scan_Filter_Policy, + uint8_t Filter_Duplicates) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_selective_connection_establish_proc(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scan_Filter_Policy, + uint8_t Filter_Duplicates, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_terminate_gap_proc(uint8_t Procedure_Code) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_limited_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_general_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_name_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_start_observation_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t LE_Scan_Type, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates, + uint8_t scanFilterPolicy) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_gap_send_pairing_req(uint16_t Connection_Handle, uint8_t Force_Rebond) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus aci_l2cap_connection_parameter_update_resp(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Slave_latency, + uint16_t Timeout_Multiplier, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Identifier, + uint8_t Accept) + +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Initiator_Filter_Policy, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + + + +tBleStatus hci_le_create_connection_cancel(void) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_set_scan_parameters(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + + +tBleStatus hci_le_set_scan_enable(uint8_t LE_Scan_Enable, + uint8_t Filter_Duplicates) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_start_encryption(uint16_t Connection_Handle, + uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier, + uint8_t Long_Term_Key[16]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +tBleStatus hci_le_set_host_channel_classification(uint8_t LE_Channel_Map[5]) +{ + return ERR_UNKNOWN_HCI_COMMAND; +} + +#endif +#endif diff --git a/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_user_cfg.c b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_user_cfg.c new file mode 100644 index 00000000000..c451177731d --- /dev/null +++ b/targets/TARGET_STMBLUE/Bluetooth_LE/src/stack_user_cfg.c @@ -0,0 +1,963 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bluenrg1_api.h" +#include "hal_types.h" +#include "stack_user_cfg.h" + +/* ---------------------------------------------------------------------------------------------------------- */ + +#ifdef CONTROLLER_PRIVACY_ENABLED +#if (CONTROLLER_PRIVACY_ENABLED == 1) + +/* Internal APIs prototypes */ +tBleStatus aci_gap_add_devices_to_resolving_list_api(uint8_t Num_of_Resolving_list_Entries, Whitelist_Identity_Entry_t Whitelist_Identity_Entry[], uint8_t Clear_Resolving_List); +tBleStatus hci_le_remove_device_from_resolving_list_api(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6]); +tBleStatus hci_le_add_device_to_resolving_list_api(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Peer_IRK[16], uint8_t Local_IRK[16]); +tBleStatus hci_le_set_resolvable_private_address_timeout_api(uint16_t RpaTimeout); +tBleStatus hci_le_set_address_resolution_enable_api(uint8_t AddressResolutionEnable); +tBleStatus hci_le_read_peer_resolvable_address_api(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Peer_Resolvable_Address[6]); +tBleStatus hci_le_read_local_resolvable_address_api(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Local_Resolvable_Address[6]); +tBleStatus hci_le_read_resolving_list_size_api(uint8_t *resolving_List_Size); +tBleStatus hci_le_clear_resolving_list_api(void); +tBleStatus hci_le_set_privacy_mode_api(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Privacy_Mode); + +/* Internal core function prototypes */ +void PRIV_vGeneratePrivateAddress(uint8_t *IRK, uint8_t *PrivateAddress); +uint8_t LL_LE_Set_Resolvable_Private_Address_Timeout(uint32_t RpaTimeout); +uint8_t LL_SetAddressResolutionEnable(uint8_t enable); +uint8_t PRIV_u32ProcessAdvPacket(void *params); +uint8_t PRIV_u8OfflineProcessing(void); +void PRIV_vGenerate_hci_le_enhanced_connection_complete_event(uint8_t role, uint32_t *peer_addr, uint8_t status, uint16_t connHandle, + uint16_t interval, uint16_t latency, uint32_t supertimeout, uint16_t CONN_Sca); + +BOOL PRIV_vGenerate_hci_le_direct_advertising_report_event(uint8_t scanFilterPolicy, BOOL adv_direct_add_rpa, uint8_t scantype, uint8_t peer_addr_type, uint8_t* p1, uint8_t rssi, uint8_t length); +tBleStatus GAP_enable_controller_privacy(uint8_t *gapRole, uint8_t *numServiceRec); +tBleStatus LL_Encrypt_Plain_Data(uint8_t *key, uint8_t *textData, uint8_t *textDataOut, BOOL inISR); + +/* APIs definitions */ +tBleStatus aci_gap_add_devices_to_resolving_list(uint8_t Num_of_Resolving_list_Entries, Whitelist_Identity_Entry_t Whitelist_Identity_Entry[], uint8_t Clear_Resolving_List) +{ + return aci_gap_add_devices_to_resolving_list_api(Num_of_Resolving_list_Entries, Whitelist_Identity_Entry, Clear_Resolving_List); +} + +tBleStatus hci_le_remove_device_from_resolving_list(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6]) +{ + return hci_le_remove_device_from_resolving_list_api(Peer_Identity_Address_Type, Peer_Identity_Address); +} + +tBleStatus hci_le_add_device_to_resolving_list(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Peer_IRK[16], uint8_t Local_IRK[16]) +{ + return hci_le_add_device_to_resolving_list_api(Peer_Identity_Address_Type, Peer_Identity_Address, Peer_IRK, Local_IRK); +} + +tBleStatus hci_le_set_resolvable_private_address_timeout(uint16_t RpaTimeout) +{ + return hci_le_set_resolvable_private_address_timeout_api(RpaTimeout); +} + +tBleStatus hci_le_set_address_resolution_enable(uint8_t AddressResolutionEnable) +{ + return hci_le_set_address_resolution_enable_api(AddressResolutionEnable); +} + +tBleStatus hci_le_read_peer_resolvable_address(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Peer_Resolvable_Address[6]) +{ + return hci_le_read_peer_resolvable_address_api(Peer_Identity_Address_Type, Peer_Identity_Address, Peer_Resolvable_Address); +} + +tBleStatus hci_le_read_local_resolvable_address(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Local_Resolvable_Address[6]) +{ + return hci_le_read_local_resolvable_address_api(Peer_Identity_Address_Type, Peer_Identity_Address, Local_Resolvable_Address); +} + +tBleStatus hci_le_read_resolving_list_size(uint8_t *resolving_List_Size) +{ + return hci_le_read_resolving_list_size_api(resolving_List_Size); +} + +tBleStatus hci_le_clear_resolving_list(void) +{ + return hci_le_clear_resolving_list_api(); +} + +tBleStatus hci_le_set_privacy_mode(uint8_t Peer_Identity_Address_Type, uint8_t Peer_Identity_Address[6], uint8_t Privacy_Mode) +{ + return hci_le_set_privacy_mode_api(Peer_Identity_Address_Type, Peer_Identity_Address, Privacy_Mode); +} + +/* Internal core function definitions */ +void PRIV_vGeneratePrivateAddress_ucfg(uint8_t *IRK, uint8_t *PrivateAddress) +{ + PRIV_vGeneratePrivateAddress(IRK, PrivateAddress); +} + +uint8_t LL_LE_Set_Resolvable_Private_Address_Timeout_ucfg(uint32_t RpaTimeout) +{ + return LL_LE_Set_Resolvable_Private_Address_Timeout(RpaTimeout); +} + +uint8_t LL_SetAddressResolutionEnable_ucfg(uint8_t enable) +{ + return LL_SetAddressResolutionEnable(enable); +} + +uint8_t PRIV_u32ProcessAdvPacket_ucfg(void *params) +{ + return PRIV_u32ProcessAdvPacket(params); +} + +uint8_t PRIV_u8OfflineProcessing_ucfg(void) +{ + return PRIV_u8OfflineProcessing(); +} + +void PRIV_vGenerate_hci_le_enhanced_connection_complete_event_ucfg(uint8_t role, uint32_t *peer_addr, + uint8_t status, uint16_t connHandle, + uint16_t interval, uint16_t latency, + uint32_t supertimeout, uint16_t CONN_Sca) +{ + PRIV_vGenerate_hci_le_enhanced_connection_complete_event(role, + peer_addr, + status, + connHandle, + interval, + latency, + supertimeout, + CONN_Sca); +} + +BOOL PRIV_vGenerate_hci_le_direct_advertising_report_event_ucfg(uint8_t scanFilterPolicy, + BOOL adv_direct_add_rpa, + uint8_t scantype, + uint8_t peer_addr_type, + uint8_t* p1, + uint8_t rssi, + uint8_t length) +{ + return PRIV_vGenerate_hci_le_direct_advertising_report_event(scanFilterPolicy, + adv_direct_add_rpa, + scantype, + peer_addr_type, + p1, + rssi, + length); +} + +tBleStatus GAP_enable_controller_privacy_ucfg(uint8_t *gapRole, uint8_t *numServiceRec) +{ + return GAP_enable_controller_privacy(gapRole, numServiceRec); +} + +tBleStatus LL_Encrypt_Plain_Data_ucfg(uint8_t *key, uint8_t *textData, uint8_t *textDataOut, BOOL inISR) +{ + return LL_Encrypt_Plain_Data(key, textData, textDataOut, inISR); +} + +uint32_t PRIV_controller_privacy_csr_ucfg(void) +{ + return 1U; +} +#endif +#else +#warning CONTROLLER_PRIVACY_ENABLED is not defined +#endif + +/* ---------------------------------------------------------------------------------------------------------- */ +#ifdef CONTROLLER_MASTER_ENABLED +#if (CONTROLLER_MASTER_ENABLED == 1) + +/* Internal APIs prototypes */ +tBleStatus aci_gap_start_auto_connection_establish_proc_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]); + +tBleStatus aci_gap_start_general_connection_establish_proc_api(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scan_Filter_Policy, + uint8_t Filter_Duplicates); + +tBleStatus aci_gap_start_selective_connection_establish_proc_api(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scan_Filter_Policy, + uint8_t Filter_Duplicates, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]); + +tBleStatus aci_gap_create_connection_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + +tBleStatus aci_gap_start_connection_update_api(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + +tBleStatus aci_gap_terminate_gap_proc_api(uint8_t Procedure_Code); + +tBleStatus aci_gap_start_limited_discovery_proc_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates); + +tBleStatus aci_gap_start_general_discovery_proc_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates); + +tBleStatus aci_gap_start_name_discovery_proc_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + +tBleStatus aci_gap_start_observation_proc_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t LE_Scan_Type, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates, + uint8_t scanFilterPolicy); + +tBleStatus aci_gap_send_pairing_req_api(uint16_t Connection_Handle, uint8_t Force_Rebond); + +tBleStatus aci_l2cap_connection_parameter_update_resp_api(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Slave_latency, + uint16_t Timeout_Multiplier, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Identifier, + uint8_t Accept); + +tBleStatus hci_le_create_connection_api(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Initiator_Filter_Policy, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + +tBleStatus hci_le_create_connection_cancel_api(void); + +tBleStatus hci_le_connection_update_api(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + +tBleStatus hci_le_set_scan_parameters_api(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy); + +tBleStatus hci_le_set_scan_enable_api(uint8_t LE_Scan_Enable, uint8_t Filter_Duplicates); + +tBleStatus hci_le_start_encryption_api(uint16_t Connection_Handle, uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier, uint8_t Long_Term_Key[16]); + +tBleStatus hci_le_set_host_channel_classification_api(uint8_t LE_Channel_Map[5]); + +/* Internal core function prototypes */ +void GAP_DiscProcTimeoutcb(void); +void GAP_LimDiscTimeoutcb(void); +uint32_t cancel_connect_master(uint8_t slaveno); +void isr_event_handler_scan_data(void *params); +void Reclassify_All_Channels(uint8_t slot_no); +tBleStatus LL_Start_Encryption(uint16_t connHandle, uint8_t *randNum, uint8_t *ediv, uint8_t *ltk); +tBleStatus GAP_check_and_set_role(uint8_t *gapRole, uint8_t role); +void GAP_discover_peer_name(void); +void full_state_func_call_init(void); + +/* SMP_MASTER functionalities */ +tBleStatus smp_MI_Start_Encryption(void *params); +void smp_Execute_Actions_wrt_Current_State_MI_excerpt(void *params); +tBleStatus smp_Process_Rx_Packet_wrt_Current_State_MI_excerpt(void *params); +/* APIs definitions*/ +tBleStatus aci_gap_start_auto_connection_establish_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]) +{ + return aci_gap_start_auto_connection_establish_proc_api(LE_Scan_Interval, + LE_Scan_Window, + Own_Address_Type, + Conn_Interval_Min, + Conn_Interval_Max, + Conn_Latency, + Supervision_Timeout, + Minimum_CE_Length, + Maximum_CE_Length, + Num_of_Whitelist_Entries, + Whitelist_Entry); +} + +tBleStatus aci_gap_start_general_connection_establish_proc(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scan_Filter_Policy, + uint8_t Filter_Duplicates) +{ + return aci_gap_start_general_connection_establish_proc_api(LE_Scan_Type, + LE_Scan_Interval, + LE_Scan_Window, + Own_Address_Type, + Scan_Filter_Policy, + Filter_Duplicates); +} + +tBleStatus aci_gap_start_selective_connection_establish_proc(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scan_Filter_Policy, + uint8_t Filter_Duplicates, + uint8_t Num_of_Whitelist_Entries, + Whitelist_Entry_t Whitelist_Entry[]) +{ + return aci_gap_start_selective_connection_establish_proc_api(LE_Scan_Type, + LE_Scan_Interval, + LE_Scan_Window, + Own_Address_Type, + Scan_Filter_Policy, + Filter_Duplicates, + Num_of_Whitelist_Entries, + Whitelist_Entry); +} + +tBleStatus aci_gap_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return aci_gap_create_connection_api(LE_Scan_Interval, + LE_Scan_Window, + Peer_Address_Type, + Peer_Address, + Own_Address_Type, + Conn_Interval_Min, + Conn_Interval_Max, + Conn_Latency, + Supervision_Timeout, + Minimum_CE_Length, + Maximum_CE_Length); +} + +tBleStatus aci_gap_start_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return aci_gap_start_connection_update_api(Connection_Handle, + Conn_Interval_Min, + Conn_Interval_Max, + Conn_Latency, + Supervision_Timeout, + Minimum_CE_Length, + Maximum_CE_Length); +} + +tBleStatus aci_gap_terminate_gap_proc(uint8_t Procedure_Code) +{ + return aci_gap_terminate_gap_proc_api(Procedure_Code); +} + +tBleStatus aci_gap_start_limited_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates) +{ + return aci_gap_start_limited_discovery_proc_api(LE_Scan_Interval, + LE_Scan_Window, + Own_Address_Type, + Filter_Duplicates); +} + +tBleStatus aci_gap_start_general_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates) +{ + return aci_gap_start_general_discovery_proc_api(LE_Scan_Interval, + LE_Scan_Window, + Own_Address_Type, + Filter_Duplicates); +} + +tBleStatus aci_gap_start_name_discovery_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return aci_gap_start_name_discovery_proc_api(LE_Scan_Interval, + LE_Scan_Window, + Peer_Address_Type, + Peer_Address, + Own_Address_Type, + Conn_Interval_Min, + Conn_Interval_Max, + Conn_Latency, + Supervision_Timeout, + Minimum_CE_Length, + Maximum_CE_Length); +} + +tBleStatus aci_gap_start_observation_proc(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t LE_Scan_Type, + uint8_t Own_Address_Type, + uint8_t Filter_Duplicates, + uint8_t scanFilterPolicy) +{ + return aci_gap_start_observation_proc_api(LE_Scan_Interval, + LE_Scan_Window, + LE_Scan_Type, + Own_Address_Type, + Filter_Duplicates, + scanFilterPolicy); +} + +tBleStatus aci_gap_send_pairing_req(uint16_t Connection_Handle, uint8_t Force_Rebond) +{ + return aci_gap_send_pairing_req_api(Connection_Handle, Force_Rebond); +} + +tBleStatus aci_l2cap_connection_parameter_update_resp(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Slave_latency, + uint16_t Timeout_Multiplier, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length, + uint8_t Identifier, + uint8_t Accept) + +{ + return aci_l2cap_connection_parameter_update_resp_api(Connection_Handle, + Conn_Interval_Min, + Conn_Interval_Max, + Slave_latency, + Timeout_Multiplier, + Minimum_CE_Length, + Maximum_CE_Length, + Identifier, + Accept); +} + +tBleStatus hci_le_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Initiator_Filter_Policy, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return hci_le_create_connection_api(LE_Scan_Interval, + LE_Scan_Window, + Initiator_Filter_Policy, + Peer_Address_Type, + Peer_Address, + Own_Address_Type, + Conn_Interval_Min, + Conn_Interval_Max, + Conn_Latency, + Supervision_Timeout, + Minimum_CE_Length, + Maximum_CE_Length); +} + +tBleStatus hci_le_create_connection_cancel(void) +{ + return hci_le_create_connection_cancel_api(); +} + +tBleStatus hci_le_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length) +{ + return hci_le_connection_update_api(Connection_Handle, + Conn_Interval_Min, + Conn_Interval_Max, + Conn_Latency, + Supervision_Timeout, + Minimum_CE_Length, + Maximum_CE_Length); +} + +tBleStatus hci_le_set_scan_parameters(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy) +{ + return hci_le_set_scan_parameters_api(LE_Scan_Type, + LE_Scan_Interval, + LE_Scan_Window, + Own_Address_Type, + Scanning_Filter_Policy); +} + +tBleStatus hci_le_set_scan_enable(uint8_t LE_Scan_Enable, uint8_t Filter_Duplicates) +{ + return hci_le_set_scan_enable_api(LE_Scan_Enable, Filter_Duplicates); +} + +tBleStatus hci_le_start_encryption(uint16_t Connection_Handle, + uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier, + uint8_t Long_Term_Key[16]) +{ + return hci_le_start_encryption_api(Connection_Handle, + Random_Number, + Encrypted_Diversifier, + Long_Term_Key); +} + +tBleStatus hci_le_set_host_channel_classification(uint8_t LE_Channel_Map[5]) +{ + return hci_le_set_host_channel_classification_api(LE_Channel_Map); +} + +/* Internal core function definitions */ +void GAP_DiscProcTimeoutcb_ucfg(void) +{ + GAP_DiscProcTimeoutcb(); +} + +void GAP_LimDiscTimeoutcb_ucfg(void) +{ + GAP_LimDiscTimeoutcb(); +} + +uint32_t cancel_connect_master_ucfg(uint8_t slaveno) +{ + return cancel_connect_master(slaveno); +} + +void isr_event_handler_scan_data_ucfg(void *params) +{ + isr_event_handler_scan_data(params); +} + +void Reclassify_All_Channels_ucfg(uint8_t slot_no) +{ + Reclassify_All_Channels(slot_no); +} + +tBleStatus LL_Start_Encryption_ucfg(uint16_t connHandle, uint8_t *randNum, uint8_t *ediv, uint8_t *ltk) +{ + return LL_Start_Encryption(connHandle, randNum, ediv, ltk); +} + +tBleStatus GAP_check_and_set_role_ucfg(uint8_t *gapRole, uint8_t role) +{ + return GAP_check_and_set_role(gapRole, role); +} + +void GAP_discover_peer_name_ucfg(void) +{ + GAP_discover_peer_name(); +} + +void state_func_call_init_csr_ucfg(void) +{ + full_state_func_call_init(); +} + +uint32_t master_csr_ucfg(void) +{ + return 1U; +} + +/* SMP_MASTER functionalities */ +tBleStatus smp_MI_Start_Encryption_ucfg(void *params) +{ + return smp_MI_Start_Encryption(params); +} +void smp_Execute_Actions_wrt_Current_State_MI_excerpt_ucfg(void *params) +{ + smp_Execute_Actions_wrt_Current_State_MI_excerpt(params); +} +tBleStatus smp_Process_Rx_Packet_wrt_Current_State_MI_excerpt_ucfg(void *params) +{ + return smp_Process_Rx_Packet_wrt_Current_State_MI_excerpt(params); +} +#endif +#else +#warning CONTROLLER_MASTER_ENABLED is not defined +#endif + + +/* ---------------------------------------------------------------------------------------------------------- */ +#if ((CONTROLLER_MASTER_ENABLED == 1) || (SECURE_CONNECTIONS_ENABLED == 1)) +void smp_Execute_Actions_wrt_Current_State_sc_MI_excerpt_phase2as2(void *params); +void smp_Execute_Actions_wrt_Current_State_sc_MI_excerpt_phase2as2_ucfg(void *params) +{ + smp_Execute_Actions_wrt_Current_State_sc_MI_excerpt_phase2as2(params); +} +#endif + +/* ---------------------------------------------------------------------------------------------------------- */ + +#ifdef CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED +#if (CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED == 1) + +/* Internal APIs prototypes */ +tBleStatus hci_le_set_data_length_api(uint16_t Connection_Handle, uint16_t TxOctets, uint16_t TxTime); +tBleStatus hci_le_read_suggested_default_data_length_api(uint16_t *SuggestedMaxTxOctets, uint16_t *SuggestedMaxTxTime); +tBleStatus hci_le_write_suggested_default_data_length_api(uint16_t SuggestedMaxTxOctets, uint16_t SuggestedMaxTxTime); +tBleStatus hci_le_read_maximum_data_length_api(uint16_t *supportedMaxTxOctets, uint16_t *supportedMaxTxTime, + uint16_t *supportedMaxRxOctets, uint16_t *supportedMaxRxTime); +/* Internal core function prototypes */ +void Data_Len_Update_Offline_Processing(void); +BOOL Data_Length_Update_Control_ISR(BOOL is_slave_flag, uint8_t opcode_temp, uint8_t *RcvData_temp_p, volatile uint32_t *sent_event_temp_p); +tBleStatus ll_write_supported_data(uint16_t Supported_Max_Tx_Octets, uint16_t Supported_Max_Tx_Time, + uint16_t Supported_Max_Rx_Octets, uint16_t Supported_Max_Rx_Time); + +BOOL LL_Data_Length_Change_Event(void *params); +tBleStatus LL_Send_Length_Resp(uint16_t connHandle); + +/* APIs definitions */ +tBleStatus hci_le_set_data_length(uint16_t Connection_Handle, uint16_t TxOctets, uint16_t TxTime) +{ + return hci_le_set_data_length_api(Connection_Handle, TxOctets, TxTime); +} + +tBleStatus hci_le_read_suggested_default_data_length(uint16_t *SuggestedMaxTxOctets, uint16_t *SuggestedMaxTxTime) +{ + return hci_le_read_suggested_default_data_length_api(SuggestedMaxTxOctets, SuggestedMaxTxTime); +} + +tBleStatus hci_le_write_suggested_default_data_length(uint16_t SuggestedMaxTxOctets, uint16_t SuggestedMaxTxTime) +{ + return hci_le_write_suggested_default_data_length_api(SuggestedMaxTxOctets, SuggestedMaxTxTime); +} + +tBleStatus hci_le_read_maximum_data_length(uint16_t *supportedMaxTxOctets, uint16_t *supportedMaxTxTime, + uint16_t *supportedMaxRxOctets, uint16_t *supportedMaxRxTime) +{ + return hci_le_read_maximum_data_length_api(supportedMaxTxOctets, supportedMaxTxTime, + supportedMaxRxOctets, supportedMaxRxTime); +} + +/* Internal core function definitions */ +void Data_Len_Update_Offline_Processing_ucfg(void) +{ + Data_Len_Update_Offline_Processing(); +} + +BOOL Data_Length_Update_Control_ISR_ucfg(BOOL is_slave_flag, uint8_t opcode_temp, uint8_t *RcvData_temp_p, volatile uint32_t *sent_event_temp_p) +{ + return Data_Length_Update_Control_ISR(is_slave_flag, opcode_temp, RcvData_temp_p, sent_event_temp_p); +} + +tBleStatus ll_write_supported_data_ucfg(uint16_t Supported_Max_Tx_Octets, uint16_t Supported_Max_Tx_Time, + uint16_t Supported_Max_Rx_Octets, uint16_t Supported_Max_Rx_Time) +{ + return ll_write_supported_data(Supported_Max_Tx_Octets, Supported_Max_Tx_Time, + Supported_Max_Rx_Octets, Supported_Max_Rx_Time); +} + +BOOL LL_Data_Length_Change_Event_ucfg(void *params) +{ + return LL_Data_Length_Change_Event(params); +} + +tBleStatus LL_Send_Length_Resp_ucfg(uint16_t connHandle) +{ + return LL_Send_Length_Resp(connHandle); +} + +uint32_t data_length_extension_csr_ucfg(void) +{ + return 1U; +} +#endif +#else +#warning CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED is not defined +#endif + + +/* ---------------------------------------------------------------------------------------------------------- */ +#ifdef SECURE_CONNECTIONS_ENABLED +#if(SECURE_CONNECTIONS_ENABLED == 1) +/* +* ***************************************************************************** +* BLE Stack API functions +* ***************************************************************************** +*/ + +/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + * BLE Stack API functions "_api" declaration + */ +/* ------------------------------------------------ from bluenrg1_api.h ----- */ +tBleStatus aci_gap_passkey_input_api(uint16_t Connection_Handle, uint8_t Input_Type); +tBleStatus aci_gap_numeric_comparison_value_confirm_yesno_api(uint16_t Connection_Handle, uint8_t Confirm_Yes_No); +tBleStatus hci_le_read_local_p256_public_key_api(void); +tBleStatus hci_le_generate_dhkey_api(uint8_t Remote_P256_Public_Key[64]); + +/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + * BLE Stack API functions "_api" wrapping implementation + */ +/* ------------------------------------------------ from bluenrg1_api.h ----- */ +tBleStatus aci_gap_passkey_input(uint16_t Connection_Handle, uint8_t Input_Type) +{ + return aci_gap_passkey_input_api(Connection_Handle, Input_Type); +} + +tBleStatus aci_gap_numeric_comparison_value_confirm_yesno(uint16_t Connection_Handle, uint8_t Confirm_Yes_No) +{ + return aci_gap_numeric_comparison_value_confirm_yesno_api(Connection_Handle, Confirm_Yes_No); +} + +tBleStatus hci_le_read_local_p256_public_key(void) +{ + return hci_le_read_local_p256_public_key_api(); +} + +tBleStatus hci_le_generate_dhkey(uint8_t Remote_P256_Public_Key[64]) +{ + return hci_le_generate_dhkey_api(Remote_P256_Public_Key); +} + +/* +* ***************************************************************************** +* BLE Stack INTERNAL core functions +* ***************************************************************************** +*/ +/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + * BLE Stack INTERNAL core functions' prototype declaration + */ +/* --------------------------------------------------------- from hci.c ----- */ +void PKA_Offline_Processing(void); + +/* ----------------------------------------------- from smp_scv42_caf.h ----- */ +void smp_sc_init(BOOL useDebugKey); +tBleStatus smp_sc_continue_on_exclusive_sc_pairing(void *params); +void smp_sc_check_for_ecc_pk_generation_request(void); +tBleStatus smp_sc_generate_new_local_oob_data(void); +void smp_sc_update_statistics_on_pairing_complete(void *params); + + +/* ----------------------------------------------- from smp_scv42_sap.h ----- */ +void smp_sc_hci_le_read_local_p256_public_key_complete_evt_hndl(void *params); +void smp_sc_hci_le_generate_dhkey_complete_evt_hndl(void *params); + + +/* ------------------------------------------------- from securitymgr.h ----- */ +tBleStatus smp_sc_MI_PairingResponse_Receive_sc_excerpt(void *params); +void smp_sc_MI_Pairing_Phase_2AS1_Start_sc_excerpt(void *params); +void smp_sc_SR_Pairing_Phase_2AS1_Start_sc_excerpt(void *params); + +void smp_sc_MI_PairingConfirm_Send_sc_excerpt(void *params); +tBleStatus smp_sc_MI_PairingRandom_Receive_sc_excerpt1(void *params); +void smp_sc_MI_PairingRandom_Receive_sc_excerpt2(void *params); + +void smp_sc_SR_PairingConfirm_Receive_sc_excerpt(void *params); +void smp_sc_SR_PairingRandom_Receive_sc_excerpt(void *params); + +BOOL smp_Execute_Actions_wrt_Current_State_sc_excerpt_phase_1_to_2(void *params); +void smp_Execute_Actions_wrt_Current_State_sc_excerpt_phase2as2(void *params); +tBleStatus smp_Process_Rx_Packet_wrt_Current_State_sc_excerpt(void *params); +tBleStatus smp_Process_Rx_Packet_Exception_Cases_sc_excerpt(void *params); + +/* = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + * BLE Stack INTERNAL core functions' "ucfg" wrapping implementation + */ +/* ----------------------------------------------- from hci.c ----- */ +void PKA_Offline_Processing_ucfg(void) +{ + PKA_Offline_Processing(); +} + +/* ----------------------------------------------- from smp_scv42_caf.h ----- */ +void smp_sc_init_ucfg(BOOL useDebugKey) +{ + smp_sc_init(useDebugKey); +} +tBleStatus smp_sc_continue_on_exclusive_sc_pairing_ucfg(void *params) +{ + return smp_sc_continue_on_exclusive_sc_pairing(params); +} +void smp_sc_check_for_ecc_pk_generation_request_ucfg(void) +{ + smp_sc_check_for_ecc_pk_generation_request(); +} +tBleStatus smp_sc_generate_new_local_oob_data_ucfg(void) +{ + return smp_sc_generate_new_local_oob_data(); +} +void smp_sc_update_statistics_on_pairing_complete_ucfg(void *params) +{ + smp_sc_update_statistics_on_pairing_complete(params); +} + +/* ----------------------------------------------- from smp_scv42_sap.h ----- */ +uint32_t secure_connections_csr_ucfg(void) +{ + return 1U; +} + +void smp_sc_hci_le_read_local_p256_public_key_complete_evt_hndl_ucfg(void *params) +{ + smp_sc_hci_le_read_local_p256_public_key_complete_evt_hndl(params); +} +void smp_sc_hci_le_generate_dhkey_complete_evt_hndl_ucfg(void *params) +{ + smp_sc_hci_le_generate_dhkey_complete_evt_hndl(params); +} + +/* ------------------------------------------------- from securitymgr.h ----- */ +tBleStatus smp_sc_MI_PairingResponse_Receive_sc_excerpt_ucfg(void *params) +{ + return smp_sc_MI_PairingResponse_Receive_sc_excerpt(params); +} +void smp_sc_MI_Pairing_Phase_2AS1_Start_sc_excerpt_ucfg(void *params) +{ + smp_sc_MI_Pairing_Phase_2AS1_Start_sc_excerpt(params); +} +void smp_sc_SR_Pairing_Phase_2AS1_Start_sc_excerpt_ucfg(void *params) +{ + smp_sc_SR_Pairing_Phase_2AS1_Start_sc_excerpt(params); +} + +void smp_sc_MI_PairingConfirm_Send_sc_excerpt_ucfg(void *params) +{ + smp_sc_MI_PairingConfirm_Send_sc_excerpt(params); +} +tBleStatus smp_sc_MI_PairingRandom_Receive_sc_excerpt1_ucfg(void *params) +{ + return smp_sc_MI_PairingRandom_Receive_sc_excerpt1(params); +} +void smp_sc_MI_PairingRandom_Receive_sc_excerpt2_ucfg(void *params) +{ + smp_sc_MI_PairingRandom_Receive_sc_excerpt2(params); +} + +void smp_sc_SR_PairingConfirm_Receive_sc_excerpt_ucfg(void *params) +{ + smp_sc_SR_PairingConfirm_Receive_sc_excerpt(params); +} +void smp_sc_SR_PairingRandom_Receive_sc_excerpt_ucfg(void *params) +{ + smp_sc_SR_PairingRandom_Receive_sc_excerpt(params); +} + +BOOL smp_Execute_Actions_wrt_Current_State_sc_excerpt_phase_1_to_2_ucfg(void *params) +{ + return smp_Execute_Actions_wrt_Current_State_sc_excerpt_phase_1_to_2(params); +} +void smp_Execute_Actions_wrt_Current_State_sc_excerpt_phase2as2_ucfg(void *params) +{ + smp_Execute_Actions_wrt_Current_State_sc_excerpt_phase2as2(params); +} +tBleStatus smp_Process_Rx_Packet_wrt_Current_State_sc_excerpt_ucfg(void *params) +{ + return smp_Process_Rx_Packet_wrt_Current_State_sc_excerpt(params); +} +tBleStatus smp_Process_Rx_Packet_Exception_Cases_sc_excerpt_ucfg(void *params) +{ + return smp_Process_Rx_Packet_Exception_Cases_sc_excerpt(params); +} + +#ifdef __cplusplus +} +#endif + +#endif +#else +#warning "SECURE_CONNECTIONS_ENABLED is not defined" +#endif diff --git a/targets/TARGET_STMBLUE/DTM/BlueNrgHCIDriver.cpp b/targets/TARGET_STMBLUE/DTM/BlueNrgHCIDriver.cpp new file mode 100644 index 00000000000..cd243ebe130 --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/BlueNrgHCIDriver.cpp @@ -0,0 +1,370 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include +#include "CordioHCIDriver.h" +#include "CordioHCITransportDriver.h" +#include "hci_api.h" +#include "hci_cmd.h" +#include "hci_core.h" +#include "dm_api.h" +#include "bstream.h" +// +#include "DTM_boot.h" +#include "DTM_cmd_db.h" +#include "osal.h" +#include "bluenrg1_api.h" +#include "bluenrg1_stack.h" +#include "hci_defs.h" +#include "CordioBLE.h" + +#ifndef TICK_MS +#define TICK_MS 10 +#endif //TICK_MS + +//STACKTICK_CODE is used for emulating BTLE_StackTick on an HCI vendor specific command. +//This value is not used and can be assigned to this functionality. The wrapper for BTLE_StackTick +//is providen in DTM_cmd_db.h +#define STACKTICK_CODE 0xFCFF +#define TICK_US TICK_MS*1000 + +extern "C" void rcv_callback(uint8_t *data, uint16_t len){ + ble::vendor::cordio::CordioHCITransportDriver::on_data_received(data, len); +} + +#define HCI_RESET_RAND_CNT 4 +#define LL_WITHOUT_HOST_OFFSET 0x2C + +namespace ble { +namespace vendor { +namespace bluenrg { + +uint8_t test_addr[] = {0xb, 0x4d, 0x00, 0x26, 0xe1, 0x80}; + +/** + * BlueNRG HCI driver implementation. + * @see cordio::CordioHCIDriver + */ + +class HCIDriver : public cordio::CordioHCIDriver +{ +public: + /** + * Construction of the BlueNRG HCIDriver. + * @param transport: Transport of the HCI commands. + */ + HCIDriver(cordio::CordioHCITransportDriver& transport_driver) : + cordio::CordioHCIDriver(transport_driver) { } + + virtual ~HCIDriver() {}; + /** + * @see CordioHCIDriver::do_initialize + */ + virtual void do_initialize() { + + } + + /** + * @see CordioHCIDriver::start_reset_sequence + */ + virtual void start_reset_sequence() { + /* send an HCI Reset command to start the sequence */ + HciResetCmd(); + } + + /** + * @see CordioHCIDriver::do_terminate + */ + virtual void do_terminate() { + + } + + /** + * @see CordioHCIDriver::handle_reset_sequence + */ + + virtual void handle_reset_sequence(uint8_t *pMsg) { + // only accept command complete event: + if (*pMsg != HCI_CMD_CMPL_EVT) { + return; + } + + uint8_t Value_LL = 0x01; + uint16_t opcode; +// static uint8_t randCnt; + + /* parse parameters */ + pMsg += HCI_EVT_HDR_LEN; + pMsg++; /* skip num packets */ + BSTREAM_TO_UINT16(opcode, pMsg); // copy opcode + pMsg++; /* skip status */ + + /* decode opcode */ + switch (opcode) + { + case HCI_OPCODE_RESET: + /* initialize rand command count */ +// randCnt = 0; + + //manually initialization of random address (because there is no GAP init) + uint8_t Random_Address[8]; //8 bytes allocated because of ST random generation + hci_le_rand(Random_Address); + Random_Address[5] = Random_Address[5] | 0xC0; //bitwise or for 2 MSB (required by core 5.0 for Random Static Address) + DM_RAND_ADDR_SET(Random_Address, DM_RAND_ADDR_STATIC); + // note: will invoke set rand address + cordio::BLE::deviceInstance().getGap().setAddress(BLEProtocol::AddressType::RANDOM_STATIC, Random_Address); + + //Set the controller in Link Layer Only mode + aci_hal_write_config_data(LL_WITHOUT_HOST_OFFSET, 1, &Value_LL); + hci_le_set_random_address(Random_Address); + + //DO NOT SET ANY EVENT MASK, BY DEFAULT ALL EVENTS ENABLED + // Ask the Bluetooth address of the controller. + hci_read_bd_addr(hciCoreCb.bdAddr); + + // Read the size of the buffer of the controller and store the buffer parameters in the stack Cordio runtime parameters. + hci_le_read_buffer_size(&hciCoreCb.bufSize, &hciCoreCb.numBufs); ///////rivedere + /* initialize ACL buffer accounting */ + hciCoreCb.availBufs = hciCoreCb.numBufs; + + // Read the states and state combinations supported by the link layer of the controller and + // store supported state and combination in the runtime parameters of the stack Cordio. + hci_le_read_supported_states(hciCoreCb.leStates); + + // Read the total of whitelist entries that can be stored in the controller and + // store the number of whitelist entries in the stack Cordio runtime parameters. + hci_le_read_white_list_size(&hciCoreCb.whiteListSize); + + // Read the LE features supported by the controller and store the set of + // LE features supported by the controller in the Cordio Stack runtime parameters. + uint8_t features[2]; + hci_le_read_local_supported_features(features); //it is a 64 bit number, but only 16 MSB are significant (others are reserved for future use) + hciCoreCb.leSupFeat = features[1] << 8 | features[0]; + + hciCoreReadResolvingListSize(); //reset sequence could terminate here depending on controller configuration + + break; + + case HCI_OPCODE_LE_READ_RES_LIST_SIZE: + // Store the number of address translation entries in the stack runtime parameter. + BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg); + + // Read the Controller’s maximum supported payload octets and packet duration times for transmission and reception. + hciCoreReadMaxDataLen(); + break; + + case HCI_OPCODE_LE_READ_MAX_DATA_LEN: + { + // Store payload definition in the runtime stack parameters. + uint16_t maxTxOctets; + uint16_t maxTxTime; + + BSTREAM_TO_UINT16(maxTxOctets, pMsg); + BSTREAM_TO_UINT16(maxTxTime, pMsg); + + /* use Controller's maximum supported payload octets and packet duration times + * for transmission as Host's suggested values for maximum transmission number + * of payload octets and maximum packet transmission time for new connections. + */ + HciLeWriteDefDataLen(maxTxOctets, maxTxTime); + } + break; + + case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN: + if (hciCoreCb.extResetSeq) + { + /* send first extended command */ + (*hciCoreCb.extResetSeq)(pMsg, opcode); + } + else + { + /* initialize extended parameters */ + hciCoreCb.maxAdvDataLen = 0; + hciCoreCb.numSupAdvSets = 0; + hciCoreCb.perAdvListSize = 0; + + /* send next command in sequence */ + HciLeRandCmd(); + } + break; + + case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN: + case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS: + case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE: + // handle extended command + if (hciCoreCb.extResetSeq) + { + /* send next extended command in sequence */ + (*hciCoreCb.extResetSeq)(pMsg, opcode); + } + break; + + case HCI_OPCODE_LE_RAND: + /* last command in sequence; set resetting state and call callback */ + signal_reset_sequence_done(); + break; + + default: + break; + } + } + + ble::vendor::cordio::buf_pool_desc_t get_buffer_pool_description() { + return ble::vendor::cordio::CordioHCIDriver::get_default_buffer_pool_description(); + +// //minimal configuration for HRM example +// uint8_t buffer[1430]; +// +// static const wsfBufPoolDesc_t pool_desc[] = { +// { 16, 14 }, +// { 32, 10 }, +// { 64, 4 }, +// { 128, 2 }, +// { 272, 1 } +// }; +// +// return ble::vendor::cordio::buf_pool_desc_t(buffer, pool_desc); + } + +private: + + void hciCoreReadMaxDataLen(void) + { + /* if LE Data Packet Length Extensions is supported by Controller and included */ + if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) && + (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT)) + { + /* send next command in sequence */ + HciLeReadMaxDataLen(); + } + else + { + /* send next command in sequence */ + HciLeRandCmd(); + } + } + + void hciCoreReadResolvingListSize(void) + { + /* if LL Privacy is supported by Controller and included */ + if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) && + (hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY)) + { + /* send next command in sequence */ + HciLeReadResolvingListSize(); + } + else + { + hciCoreCb.resListSize = 0; + + /* send next command in sequence */ + hciCoreReadMaxDataLen(); + } + } +}; + +/** + * Virtual Transport driver, used to exchange packet between host and controller. + */ +class TransportDriver : public cordio::CordioHCITransportDriver { +public: + + TransportDriver() { } + + virtual ~TransportDriver(){ } + + /** + * @see CordioHCITransportDriver::initialize + */ + virtual void initialize() { +// tick.attach_us(mbed::callback(this, &ble::vendor::bluenrg::TransportDriver::StackTick), (uint32_t)TICK_US); + } + + /** + * @see CordioHCITransportDriver::terminate + */ + virtual void terminate() { } + + /** + * @see CordioHCITransportDriver::write + */ + virtual uint16_t write(uint8_t type, uint16_t len, uint8_t *pData) { + if(type== HCI_CMD_TYPE){ + uint8_t resp_len; + resp_len = process_command(pData, len, buffer_out, 255); + rcv_callback(buffer_out, resp_len); + } + else if(type==HCI_ACL_TYPE){ + uint16_t connHandle; + uint16_t dataLen; + uint8_t* pduData; + uint8_t pb_flag; + uint8_t bc_flag; + + connHandle = ((pData[1] & 0x0F) << 8) + pData[0]; + dataLen = (pData[3] << 8) + pData[2]; + pduData = pData+4; + pb_flag = (pData[1] >> 4) & 0x3; + bc_flag = (pData[1] >> 6) & 0x3; + hci_tx_acl_data(connHandle, pb_flag, bc_flag, dataLen, pduData); + } + + return len; + } + +private: + uint16_t process_command(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length){ + uint16_t ret_val, opCode; + + Osal_MemCpy(&opCode, buffer_in, 2); + for (int i = 0; i < (sizeof(hci_command_table)/sizeof(hci_command_table_type)); i++) { + if (opCode == hci_command_table[i].opcode) { + ret_val = hci_command_table[i].execute(buffer_in+2, buffer_in_length-2, buffer_out, buffer_out_max_length); + return ret_val; + } + } + // Unknown command length + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = 0x04; + buffer_out[3] = 0x01; ///01 unknown command <- + buffer_out[4] = 0x01; + Osal_MemCpy(&buffer_out[5], &opCode, 2); + return 7; + } + +// void StackTick(){ +// ble::vendor::cordio::BLE::deviceInstance().signalEventsToProcess(BLE::DEFAULT_INSTANCE); +// } + + uint8_t buffer_out[258]; //buffer to store hci event packets generated after an hci command +// Ticker tick; +}; + +} // namespace bluenrg +} // namespace vendor +} // namespace ble + +/** + * Cordio HCI driver factory + */ +ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() { + static ble::vendor::bluenrg::TransportDriver transport_driver; + static ble::vendor::bluenrg::HCIDriver hci_driver(transport_driver); + return hci_driver; +} diff --git a/targets/TARGET_STMBLUE/DTM/inc/BlueNRG1_conf.h b/targets/TARGET_STMBLUE/DTM/inc/BlueNRG1_conf.h new file mode 100644 index 00000000000..04070ad4995 --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/inc/BlueNRG1_conf.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BlueNRG1_CONF_H +#define BlueNRG1_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ + +#include "BlueNRG1_flash.h" +#include "BlueNRG1_gpio.h" +/*#include "BlueNRG1_i2c.h"*/ +#include "BlueNRG1_wdg.h" +#include "BlueNRG1_spi.h" +#include "BlueNRG1_uart.h" +/*#include "BlueNRG1_mft.h"*/ +/*#include "BlueNRG1_rtc.h"*/ +#include "BlueNRG1_pka.h" +#include "BlueNRG1_rng.h" +#include "BlueNRG1_dma.h" +#include "BlueNRG1_sysCtrl.h" +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* BlueNRG1_CONF_H */ + +/******************* (C) COPYRIGHT 2014 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/DTM/inc/DTM_boot.h b/targets/TARGET_STMBLUE/DTM/inc/DTM_boot.h new file mode 100644 index 00000000000..707da4da9da --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/inc/DTM_boot.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef _DTM_BOOT_H_ +#define _DTM_BOOT_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +void DTM_SystemInit(void); +void DTM_StackInit(void); + +#ifdef __cplusplus +} +#endif + +#endif //_DTM_BOOT_H_ diff --git a/targets/TARGET_STMBLUE/DTM/inc/DTM_cmd_db.h b/targets/TARGET_STMBLUE/DTM/inc/DTM_cmd_db.h new file mode 100644 index 00000000000..e332760e7a7 --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/inc/DTM_cmd_db.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef _DTM_CMD_DB_H_ +#define _DTM_CMD_DB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include "bluenrg1_api.h" + +#define HCI_MAX_PAYLOAD_SIZE 256 +//#define MIN(a, b) ((a <= b) ? (a) : (b)) + +typedef uint16_t (*hci_command_process_and_response_type)(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) ; +typedef struct hci_command_table_type_s { + uint16_t opcode; + hci_command_process_and_response_type execute; +} hci_command_table_type; + +uint16_t hci_disconnect_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_remote_version_information_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_set_event_mask_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_reset_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_transmit_power_level_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_local_version_information_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_local_supported_commands_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_local_supported_features_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_bd_addr_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_read_rssi_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_event_mask_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_buffer_size_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_local_supported_features_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_random_address_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_advertising_parameters_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_advertising_channel_tx_power_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_advertising_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_scan_response_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_advertise_enable_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_scan_parameters_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_scan_enable_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_create_connection_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_create_connection_cancel_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_white_list_size_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_clear_white_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_add_device_to_white_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_remove_device_from_white_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_connection_update_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_host_channel_classification_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_channel_map_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_remote_used_features_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_encrypt_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_rand_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_start_encryption_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_long_term_key_request_reply_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_long_term_key_requested_negative_reply_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_supported_states_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_receiver_test_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_transmitter_test_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_test_end_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_suggested_default_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_write_suggested_default_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_local_p256_public_key_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_generate_dhkey_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_add_device_to_resolving_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_remove_device_from_resolving_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_clear_resolving_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_resolving_list_size_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_peer_resolvable_address_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_local_resolvable_address_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_address_resolution_enable_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_set_resolvable_private_address_timeout_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t aci_hal_write_config_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t aci_hal_read_config_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); +uint16_t hci_le_read_maximum_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length); + +void rcv_callback(uint8_t *data, uint16_t len); + +extern const hci_command_table_type hci_command_table[56]; + +#ifdef __cplusplus +} +#endif + +#endif //_DTM_CMD_DB_H_ diff --git a/targets/TARGET_STMBLUE/DTM/inc/DTM_config.h b/targets/TARGET_STMBLUE/DTM/inc/DTM_config.h new file mode 100644 index 00000000000..fd743f80ebc --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/inc/DTM_config.h @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef _DTM_CONFIG_H_ +#define _DTM_CONFIG_H_ +#include "BlueNRG_x_device.h" +#include "bluenrg1_stack.h" +#include "stack_user_cfg.h" + +/** This file contains all the information needed to init the BlueNRG-1 stack. + * These constants and variables are used from the BlueNRG-1,2 stack to reserve RAM and FLASH + * according the application requests. + * NOTE: the current selected configuration is tuned for supporting up to 8 connections, + * 8 services, 68 attributes. + * MAX ATT_MTU size is set to 220 bytes which is the max allowed value for fitting with the + * overall DTM RAM memory requirements for all the supported configurations (SPI and UARTs), and + * use the extended packey length for OTA client FW upgrade procedure. + * This implies to reduce the PREPARE_WRITE_LIST_SIZE value. + * User can modify, tune the configuration options according to his specific application requirements. + */ + + +/* MAX numberof link for DTM */ +#define DTM_NUM_LINK 1 //8 +/* MAX numberof GATT services for DTM */ +#define DTM_NUM_GATT_SERVICES 0 //8 +/* MAX number of GAP and GATT attributes for DTM */ +#define DTM_NUM_GATT_ATTRIBUTES 0 //68 + +/* Number of links needed for the demo: 1 + * Only 1 the default + */ +#define NUM_LINKS (DTM_NUM_LINK) + +/* Number of GATT attributes needed for the DTM */ +#define NUM_GATT_ATTRIBUTES (DTM_NUM_GATT_ATTRIBUTES) + +/* Number of GATT services needed for the DTM */ +#define NUM_GATT_SERVICES (DTM_NUM_GATT_SERVICES) + +/* Set the number of prepare write request needed to write an att of 512 bytes, + using MTU default value (23 bytes): value is reduced to 9 (refer to previous added note) */ + +#define PREPARE_WRITE_LIST_SIZE (0) ////////////////////9 //(DEFAULT_PREP_WRITE_LIST_SIZE) + +/* Set supported max value for ATT_MTU */ +#define MAX_ATT_MTU (0) //220 + +/* Array size for the attribte value */ +#define ATT_VALUE_ARRAY_SIZE (0) //1344 + +/* Flash security database size */ +#define FLASH_SEC_DB_SIZE (0x400) + +/* Flash server database size */ +#define FLASH_SERVER_DB_SIZE (0x400) + +#define OPT_MBLOCKS (0) + + +/* Set the number of memory block for packet allocation */ +//#define MBLOCKS_COUNT (MBLOCKS_CALC(PREPARE_WRITE_LIST_SIZE, MAX_ATT_MTU, NUM_LINKS) + OPT_MBLOCKS) +#define MBLOCKS_COUNT 15 //minimal configuration + +/* RAM reserved to manage all the data stack according the number of links, + * number of services, number of attributes and attribute value length + */ +NO_INIT(uint32_t dyn_alloc_a[TOTAL_BUFFER_SIZE(NUM_LINKS,NUM_GATT_ATTRIBUTES,NUM_GATT_SERVICES,ATT_VALUE_ARRAY_SIZE,MBLOCKS_COUNT,CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED)>>2]); + +/* FLASH reserved to store all the security database information and + * and the server database information + */ + +NO_INIT_SECTION(uint32_t stacklib_flash_data[TOTAL_FLASH_BUFFER_SIZE(FLASH_SEC_DB_SIZE, FLASH_SERVER_DB_SIZE)>>2], ".noinit.stacklib_flash_data"); +/* FLASH reserved to store: security root keys, static random address, public address */ + + +NO_INIT_SECTION(uint8_t stacklib_stored_device_id_data[56], ".noinit.stacklib_stored_device_id_data"); + + +/* Maximum duration of the connection event */ +#define MAX_CONN_EVENT_LENGTH 0xFFFFFFFF + +/* Sleep clock accuracy: DTM is using internal RO */ + +/* Sleep clock accuracy in Slave mode */ +#define SLAVE_SLEEP_CLOCK_ACCURACY 500 + +/* Sleep clock accuracy in Master mode */ +#define MASTER_SLEEP_CLOCK_ACCURACY MASTER_SCA_500ppm + +/* Low Speed Oscillator source */ +#if (LS_SOURCE == LS_SOURCE_INTERNAL_RO) +#define LOW_SPEED_SOURCE 1 // Internal RO +#else +#define LOW_SPEED_SOURCE 0 // External 32 KHz +#endif + +/* High Speed start up time */ +#define HS_STARTUP_TIME 328 // 800 us + +/* Radio Config Hot Table */ +extern uint8_t hot_table_radio_config[]; + +/* Low level hardware configuration data for the device */ +#define CONFIG_TABLE \ +{ \ + (uint32_t*)hot_table_radio_config, \ + MAX_CONN_EVENT_LENGTH, \ + SLAVE_SLEEP_CLOCK_ACCURACY, \ + MASTER_SLEEP_CLOCK_ACCURACY, \ + LOW_SPEED_SOURCE, \ + HS_STARTUP_TIME \ +} + +/* This structure contains memory and low level hardware configuration data for the device */ +BlueNRG_Stack_Initialization_t BlueNRG_Stack_Init_params = { + (uint8_t*)stacklib_flash_data, + FLASH_SEC_DB_SIZE, + FLASH_SERVER_DB_SIZE, + (uint8_t*)stacklib_stored_device_id_data, + (uint8_t*)dyn_alloc_a, + TOTAL_BUFFER_SIZE(NUM_LINKS,NUM_GATT_ATTRIBUTES,NUM_GATT_SERVICES,ATT_VALUE_ARRAY_SIZE,MBLOCKS_COUNT,CONTROLLER_DATA_LENGTH_EXTENSION_ENABLED), + NUM_GATT_ATTRIBUTES, + NUM_GATT_SERVICES, + ATT_VALUE_ARRAY_SIZE, + NUM_LINKS, + 0, + PREPARE_WRITE_LIST_SIZE, + MBLOCKS_COUNT, + MAX_ATT_MTU, + CONFIG_TABLE, +}; + +#endif // _SENSORDEMO_CONFIG_H_ diff --git a/targets/TARGET_STMBLUE/DTM/src/DTM_boot.c b/targets/TARGET_STMBLUE/DTM/src/DTM_boot.c new file mode 100644 index 00000000000..4b6d927cd79 --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/src/DTM_boot.c @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include +#include +#include "BlueNRG1_conf.h" +#include "bluenrg1_stack.h" +#include "DTM_config.h" +#include "miscutil.h" + +/* Private typedef -----------------------------------------------------------*/ +typedef PACKED(struct) devConfigS { + uint8_t HS_crystal; + uint8_t LS_source; + uint8_t SMPS_management; + uint8_t Reserved; + uint16_t HS_startup_time; + uint16_t SlaveSCA; + uint8_t MasterSCA; + uint32_t max_conn_event_length; + uint8_t Test_mode; +} devConfig_t; + +/* Private define ------------------------------------------------------------*/ + +/** + * @name Device Configuration Registers + *@{ + */ + +/** + *@brief Analog Test Bus 0 register settings + */ +#define ATB0_ANA_ENG_REG 0x3F +/** + *@brief Analog Test Bus 1 register settings + */ +#define ATB1_ANA_ENG_REG 0x3E +/** + *@brief Rate Multiplier 1 register settings + */ +#define RM1_DIG_ENG_REG 0x3C +/** + *@brief Low Frequency Clock and SMPS register settings + */ +#define CLOCK_LOW_ENG_REG 0x3B +/** + *@brief High Frequency Clock register settings + */ +#define CLOCK_HIGH_ENG_REG 0x3A +/** + *@brief Power Management register settings + */ +#define PMU_ANA_ENG_REG 0x39 +/** + *@brief System Clock register settings + */ +#define CLOCK_ANA_USER_REG 0x34 +/** + *@brief System Power Management register settings + */ +#define PMU_ANA_USER_REG 0x35 +//@} \\Device Configuration Registers + +/** + * @name Device Configuration values + *@{ + */ + +/** + * @brief Enable the low frequency RO + */ +#define LOW_FREQ_RO 0x1B +/** + * @brief Enable the external low frequency XO + */ +#define LOW_FREQ_XO 0x5B +/** + * @brief Enable the high frequency 16 MHz + */ +#define HIGH_FREQ_16M 0x40 +/** + * @brief Enable the high frequrency 32 MHz + */ +#define HIGH_FREQ_32M 0x44 +/** + * @brief Enable the SMPS + */ +#define SMPS_ON 0x4C +/** + * @brief Disable the SMPS + */ +#define SMPS_OFF 0x6C +/** + * @brief SMPS clock frequency value for 4.7 uH inductor + */ +#define SMPS_4_7uH_RM1 0x40 +/** + * @brief Power management configuration for 4.7 uH inductor + */ +#define SMPS_4_7uH_PMU 0xBE +/** + * @brief SMPS clock frequency value for 10 uH inductor + */ +#define SMPS_10uH_RM1 0x20 +/** + * @brief Power management configuration for 10 uH inductor + */ +#define SMPS_10uH_PMU 0xB2 +/** + * @brief RCO32 trimming default values + */ +#define PMU_ANA_USER_RESET_VALUE 0x0B +/** + * @brief Analog test bus 0 settings for + * normal application mode + */ +#define USER_MODE_ATB0 0x00 +/** + * @brief Analog test bus 1 settings for + * normal application mode + */ +#define USER_MODE_ATB1 0x30 +/** + * @brief Analog test bus 0 settings for + * low speed crystal measurement + */ +#define LS_XTAL_MEAS_ATB0 0x37 +/** + * @brief Analog test bus 1 settings for + * low speed crystal measurement + */ +#define LS_XTAL_MEAS_ATB1 0x34 +/** + * @brief Analog test bus 0 settings for + * high speed crystal startup time measurement + */ +#define HS_STARTUP_TIME_MEAS_ATB0 0x04 +/** + * @brief Analog test bus 1 settings for + * high speed crystal startup time measurement + */ +#define HS_STARTUP_TIME_MEAS_ATB1 0x34 +/** + * @brief Analog test bus 0 settings for + * Tx/Rx start stop signal measurement + */ +#define TX_RX_START_STOP_MEAS_ATB0 0x38 +/** + * @brief Analog test bus 1 settings for + * Tx/Rx start stop signal measurement + */ +#define TX_RX_START_STOP_MEAS_ATB1 0x34 +//@} \\Device Configuration values + +/** + *@brief Number of configuration bytes to send over Blue SPI + */ +#define NUMBER_CONFIG_BYTE 0x02 +/** + *@brief End Configuration Tag + */ +#define END_CONFIG 0x00 + + +/* Cold Start Configuration Table */ +#define COLD_START_CONFIGURATION \ +{ \ + NUMBER_CONFIG_BYTE, ATB0_ANA_ENG_REG, USER_MODE_ATB0, \ + NUMBER_CONFIG_BYTE, ATB1_ANA_ENG_REG, USER_MODE_ATB1, \ + NUMBER_CONFIG_BYTE, RM1_DIG_ENG_REG, SMPS_10uH_RM1, \ + NUMBER_CONFIG_BYTE, CLOCK_LOW_ENG_REG, SMPS_ON, \ + NUMBER_CONFIG_BYTE, CLOCK_HIGH_ENG_REG, HIGH_FREQ_16M, \ + NUMBER_CONFIG_BYTE, PMU_ANA_ENG_REG, SMPS_10uH_PMU, \ + NUMBER_CONFIG_BYTE, CLOCK_ANA_USER_REG, LOW_FREQ_XO, \ + NUMBER_CONFIG_BYTE, PMU_ANA_USER_REG, PMU_ANA_USER_RESET_VALUE, \ + END_CONFIG \ +} + +/* Device Configuration value for struct deviceConfigS */ +#define HS_CRYSTAL_16MHZ 0xFF +#define HS_CRYSTAL_32MHZ 0x00 + +#define LS_SOURCE_RO 0xFF +#define LS_SOURCE_32KHZ 0x00 + +#define SMSP_10uH 0xFF +#define SMSPS_4_7uH 0x00 +#define SMPS_IND_OFF 0x01 + +#define USER_MODE 0xFF +#define LS_CRYSTAL_MEASURE 0x01 +#define HS_STARTUP_TIME_MEASURE 0x02 + +/* Device Configuration value for struct deviceConfigS */ +#define TX_RX_START_STOP_MEASURE 0x03 + +/** + * @brief RCO32K trimming value flash location + */ +#define RCO32K_TRIMMING_FLASH_ADDR 0x100007E8 +/** + * @brief LDO1V2 trimming value flash location + */ +#define LDO1V2_TRIMMING_FLASH_ADDR 0x100007E4 +/** + * @brief Battery Level Detector Threshold trimming value flash location + */ +#define SET_BLD_LVL_TRIMMING_FLASH_ADDR 0x100007B0 +/** + * @brief Check bytes tag + */ +#define CHECK_BYTES 0xAA55 + +/** + * @brief Max HS startup time expressed in system time (1953 us / 2.4414 us) + */ +#define MAX_HS_STARTUP_TIME 0x320 + + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +devConfig_t deviceConfig; +volatile uint8_t cold_start_config[] = COLD_START_CONFIGURATION; + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +static void coldStartConfiguration(void) +{ + uint8_t pmu_ana_user, clock_low_eng; + uint32_t Trimm_config; + PartInfoType Device_partInfo; + + /* Get partInfo */ + HAL_GetPartInfo(&Device_partInfo); + + /* High Speed Crystal Configuration */ + if (deviceConfig.HS_crystal == HS_CRYSTAL_32MHZ) { + /* 32 MHz should be set in some way. This info is retrieved from flash info */ + cold_start_config[14] = HIGH_FREQ_32M; + } else { + cold_start_config[14] = HIGH_FREQ_16M; + } + + /* Low Speed Crystal source */ + if (deviceConfig.LS_source == LS_SOURCE_32KHZ) { + cold_start_config[20] = LOW_FREQ_XO; + } else { + cold_start_config[20] = LOW_FREQ_RO; + } + + /* SMPS configuration */ + switch (deviceConfig.SMPS_management) { + case SMSPS_4_7uH: + { + cold_start_config[11] = SMPS_ON; + cold_start_config[8] = SMPS_4_7uH_RM1; + cold_start_config[17] = SMPS_4_7uH_PMU; + } + break; + case SMPS_IND_OFF: + { + cold_start_config[11] = SMPS_OFF; + } + break; + default: + { + cold_start_config[11] = SMPS_ON; + cold_start_config[8] = SMPS_10uH_RM1; + cold_start_config[17] = SMPS_10uH_PMU; + } + break; + } + + /* Test Mode */ + switch (deviceConfig.Test_mode) { + case LS_CRYSTAL_MEASURE: + { + cold_start_config[2] = LS_XTAL_MEAS_ATB0; + cold_start_config[5] = LS_XTAL_MEAS_ATB1; + } + break; + case HS_STARTUP_TIME_MEASURE: + { + cold_start_config[2] = HS_STARTUP_TIME_MEAS_ATB0; + cold_start_config[5] = HS_STARTUP_TIME_MEAS_ATB1; + } + break; + case TX_RX_START_STOP_MEASURE: + { + cold_start_config[2] = TX_RX_START_STOP_MEAS_ATB0; + cold_start_config[5] = TX_RX_START_STOP_MEAS_ATB1; + } + break; + default: + { + cold_start_config[2] = USER_MODE_ATB0; + cold_start_config[5] = USER_MODE_ATB1; + } + break; + } + + /* Setup RCO32K trimming value in PMU_ANA_USER_REG */ + Trimm_config = *(volatile uint32_t*)RCO32K_TRIMMING_FLASH_ADDR; + if ((Trimm_config >> 16) == CHECK_BYTES) { + cold_start_config[23] &= ~0x70; // Clear the register content bit 4-5-6 + cold_start_config[23] |= (Trimm_config&0x7)<<4; // Store the RCO32K trimming value in bit 4-5-6 + } + + /* Setup LDO1V2 trimming value in ATB1_ANA_ENG_REG */ + Trimm_config = *(volatile uint32_t*)LDO1V2_TRIMMING_FLASH_ADDR; + if ((Trimm_config >> 16) == CHECK_BYTES) { + cold_start_config[5] &= ~0x30; // Clear the register content of bit 4 and 5 + cold_start_config[5] |= (Trimm_config&0x3)<<4; // Store the LDO1V2 trimming value in bit 4 and 5 + } + + /* Setup Battery Level Detector Threshold value in PMU_ANA_USER_REG */ + Trimm_config = *(volatile uint32_t*)SET_BLD_LVL_TRIMMING_FLASH_ADDR; + if ((Trimm_config >> 16) == CHECK_BYTES) { + cold_start_config[23] &= ~0x03; // Clear the register content of bit 0 and 1 + cold_start_config[23] |= (Trimm_config&0x3); // Store the BLD_LVL trimming value in bit 0 and 1 + } + + /* BOR configuration. Note: this setup shall be executed after the SMPS configuration*/ +#if (BOR_CONFIG == BOR_ON) + /* Clear the 3 bit of the CLOCK_LOW_ENG_REG register */ + cold_start_config[11] &= ~(1<<2); + if (((Device_partInfo.die_major<<4)|(Device_partInfo.die_cut)) >= WA_DEVICE_VERSION) { + /* Set the 3 bit of the PMU_ANA_USER register */ + cold_start_config[23] |= (1<<2); + clock_low_eng = cold_start_config[11]; + pmu_ana_user = cold_start_config[23]; + BOR_ConfigSave(clock_low_eng, pmu_ana_user); + } +#elif (BOR_CONFIG == BOR_OFF) + /* Set the 3 bit of the CLOCK_LOW_ENG_REG register */ + cold_start_config[11] |= (1<<2); + if (((Device_partInfo.die_major<<4)|(Device_partInfo.die_cut)) >= WA_DEVICE_VERSION) { + /* Clear the 3 bit of the PMU_ANA_USER register */ + cold_start_config[23] &= ~(1<<2); + clock_low_eng = cold_start_config[11]; + pmu_ana_user = cold_start_config[23]; + BOR_ConfigSave(clock_low_eng, pmu_ana_user); + } +#else +#error "No definition for BOR Configuration" +#endif + +} + +#define FLASH_ADDRESS_STACK_DEV_ID_DATA (FLASH_END - N_BYTES_PAGE + 1) +void DTM_SystemInit(void) +{ + uint32_t current_time; + uint8_t *dev_config_addr; + PartInfoType Device_partInfo; + + /* Remap the vector table */ + FLASH->CONFIG = FLASH_PREMAP_MAIN; + + /* Load device configuration from FLASH memory */ + /* The first 256 bytes are for stacklib_stored_device_id_data */ + dev_config_addr = (uint8_t *) (FLASH_ADDRESS_STACK_DEV_ID_DATA + 0x100); + memcpy(&deviceConfig, dev_config_addr, sizeof(deviceConfig)); + +//#ifdef UART_INTERFACE +//#if (HS_SPEED_XTAL==HS_SPEED_XTAL_16MHZ) +// if(deviceConfig.HS_crystal == HS_CRYSTAL_32MHZ) { +// deviceConfig.HS_crystal = 0xFF; // Set HS_CRYSTAL_16MHZ +// FLASH_ErasePage((FLASH_ADDRESS_STACK_DEV_ID_DATA-FLASH_START)/N_BYTES_PAGE); +// uint32_t tmp32[4] = {0,0,0,0}; +// tmp32[0] = (((uint32_t)deviceConfig.Reserved)<<24) | (((uint32_t)deviceConfig.SMPS_management)<<16) | (((uint32_t)deviceConfig.LS_source)<<8) | (((uint32_t)0xFF)<<0); +// tmp32[1] = (((uint32_t)deviceConfig.SlaveSCA)<<16) | (((uint32_t)deviceConfig.HS_startup_time)<<0); +// tmp32[2] = ((((uint32_t)deviceConfig.max_conn_event_length)&0x00FFFFFF)<<8) | (((uint32_t)deviceConfig.MasterSCA)<<0); +// tmp32[3] = (((uint32_t)0xFF)<<24) | (((uint32_t)0xFF)<<16) | (((uint32_t)deviceConfig.Test_mode)<<8) | ((((uint32_t)deviceConfig.max_conn_event_length)&0xFF000000)>>24); +// FLASH_ProgramWordBurst(FLASH_ADDRESS_STACK_DEV_ID_DATA + 0x100, tmp32); +// } +//#elif (HS_SPEED_XTAL==HS_SPEED_XTAL_32MHZ) +// if(deviceConfig.HS_crystal == HS_CRYSTAL_16MHZ) { +// uint32_t tmp32 = (((uint32_t)deviceConfig.Reserved)<<24) | (((uint32_t)deviceConfig.SMPS_management)<<16) | (((uint32_t)deviceConfig.LS_source)<<8) | (((uint32_t)0x00)<<0); +// deviceConfig.HS_crystal = 0x00; // Set HS_CRYSTAL_32MHZ +// FLASH_ProgramWord(FLASH_ADDRESS_STACK_DEV_ID_DATA + 0x100, tmp32); +// } +//#endif +//#else +#if (HS_SPEED_XTAL==HS_SPEED_XTAL_16MHZ) + if(deviceConfig.HS_crystal == HS_CRYSTAL_32MHZ) { + deviceConfig.HS_crystal = 0xFF; // Set HS_CRYSTAL_16MHZ + } +#elif (HS_SPEED_XTAL==HS_SPEED_XTAL_32MHZ) + if(deviceConfig.HS_crystal == HS_CRYSTAL_16MHZ) { + deviceConfig.HS_crystal = 0x00; // Set HS_CRYSTAL_32MHZ + } +#endif +//#endif + + coldStartConfiguration(); + + if (deviceConfig.HS_crystal == HS_CRYSTAL_32MHZ) { + /* Set 32MHz_SEL bit in the System controller register */ + SYSTEM_CTRL->CTRL_b.MHZ32_SEL = 1; + } + + /* Cold start configuration device */ + BLUE_CTRL->RADIO_CONFIG = 0x10000U | (uint16_t)((uint32_t)cold_start_config & 0x0000FFFFU); + while ((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); + + /* Configure RF FrontEnd */ + HAL_GetPartInfo(&Device_partInfo); + if (((Device_partInfo.die_major<<4)|(Device_partInfo.die_cut)) >= WA_DEVICE_VERSION) { + Set_RF_FrontEnd(); + } + + /* Wait until HS is ready. The slow clock period + * measurement is done automatically each time the + * device enters in active2 state and the HS is ready. + * The interrupt signals that a measurement is done. + */ + while(CKGEN_BLE->CLK32K_IT == 0); + CKGEN_BLE->CLK32K_IT = 1; + CKGEN_BLE->CLK32K_COUNT = 23; //Restore the window length for slow clock measurement. + CKGEN_BLE->CLK32K_PERIOD = 0; + + /* Wait until the RO or 32KHz is ready */ + current_time = *(volatile uint32_t *)0x48000010; + while(((*(volatile uint32_t *)0x48000010)&0x10) == (current_time&0x10)); + + if (deviceConfig.HS_crystal == HS_CRYSTAL_32MHZ) { + /* AHB up converter command register write*/ + AHBUPCONV->COMMAND = 0x15; + } + + /* Unlock the Flash */ + flash_sw_lock = FLASH_UNLOCK_WORD; + + /* Disable all the peripherals clock except NVM, SYSCTR, PKA and RNG */ + CKGEN_SOC->CLOCK_EN = 0xE0066; + + /* Enable the IRQs */ + __enable_irq(); +} + +void DTM_StackInit(void) +{ + uint8_t ret; + + if (deviceConfig.max_conn_event_length > 1639344) { + BlueNRG_Stack_Init_params.hardware_config.max_conn_event_length = 0xFFFFFFFF; + } else { + BlueNRG_Stack_Init_params.hardware_config.max_conn_event_length = deviceConfig.max_conn_event_length; + } + if (deviceConfig.SlaveSCA == 0xFFFF) { + BlueNRG_Stack_Init_params.hardware_config.slave_sca = 500; + } else { + BlueNRG_Stack_Init_params.hardware_config.slave_sca = deviceConfig.SlaveSCA; + } + if (deviceConfig.MasterSCA == 0xFF) { + BlueNRG_Stack_Init_params.hardware_config.master_sca = 0; + } else { + BlueNRG_Stack_Init_params.hardware_config.master_sca = deviceConfig.MasterSCA; + } + BlueNRG_Stack_Init_params.hardware_config.ls_source = deviceConfig.LS_source; + if (deviceConfig.HS_startup_time > MAX_HS_STARTUP_TIME) { + BlueNRG_Stack_Init_params.hardware_config.hs_startup_time = MAX_HS_STARTUP_TIME; + } else { + BlueNRG_Stack_Init_params.hardware_config.hs_startup_time = deviceConfig.HS_startup_time; + } + + ret = BlueNRG_Stack_Initialization(&BlueNRG_Stack_Init_params); + if (ret != 0) { + while(1); + } +} + diff --git a/targets/TARGET_STMBLUE/DTM/src/DTM_cmd_db.c b/targets/TARGET_STMBLUE/DTM/src/DTM_cmd_db.c new file mode 100644 index 00000000000..bba71a887aa --- /dev/null +++ b/targets/TARGET_STMBLUE/DTM/src/DTM_cmd_db.c @@ -0,0 +1,3194 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "compiler.h" +#include "bluenrg1_events.h" +#include "osal.h" +#include "miscutil.h" +#include "DTM_cmd_db.h" +#include "bluenrg1_stack.h" + +#include + +/** Documentation for C struct Whitelist_Entry_t */ +typedef PACKED(struct) packed_Whitelist_Entry_t_s { + /** Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + */ + uint8_t Peer_Address_Type; + /** Public Device Address or Random Device Address of the device +to be added to the white list. + */ + uint8_t Peer_Address[6]; +} packed_Whitelist_Entry_t; +/** Documentation for C struct Bonded_Device_Entry_t */ +typedef PACKED(struct) packed_Bonded_Device_Entry_t_s { + /** Address type. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + */ + uint8_t Address_Type; + /** Public Device Address or Random Device Address of the device +to be added to the white list. + */ + uint8_t Address[6]; +} packed_Bonded_Device_Entry_t; +/** Documentation for C struct Whitelist_Identity_Entry_t */ +typedef PACKED(struct) packed_Whitelist_Identity_Entry_t_s { + /** Identity address type. + * Values: + - 0x00: Public Identity Address + - 0x01: Random (static) Identity Address + */ + uint8_t Peer_Identity_Address_Type; + /** Public or Random (static) Identity address of the peer device + */ + uint8_t Peer_Identity_Address[6]; +} packed_Whitelist_Identity_Entry_t; +/** Documentation for C union Service_UUID_t */ +typedef PACKED(union) packed_Service_UUID_t_s { + /** 16-bit UUID + */ + uint16_t Service_UUID_16; + /** 128-bit UUID + */ + uint8_t Service_UUID_128[16]; +} packed_Service_UUID_t; +/** Documentation for C union Include_UUID_t */ +typedef PACKED(union) packed_Include_UUID_t_s { + /** 16-bit UUID + */ + uint16_t Include_UUID_16; + /** 128-bit UUID + */ + uint8_t Include_UUID_128[16]; +} packed_Include_UUID_t; +/** Documentation for C union Char_UUID_t */ +typedef PACKED(union) packed_Char_UUID_t_s { + /** 16-bit UUID + */ + uint16_t Char_UUID_16; + /** 128-bit UUID + */ + uint8_t Char_UUID_128[16]; +} packed_Char_UUID_t; +/** Documentation for C union Char_Desc_Uuid_t */ +typedef PACKED(union) packed_Char_Desc_Uuid_t_s { + /** 16-bit UUID + */ + uint16_t Char_UUID_16; + /** 128-bit UUID + */ + uint8_t Char_UUID_128[16]; +} packed_Char_Desc_Uuid_t; +/** Documentation for C union UUID_t */ +typedef PACKED(union) packed_UUID_t_s { + /** 16-bit UUID + */ + uint16_t UUID_16; + /** 128-bit UUID + */ + uint8_t UUID_128[16]; +} packed_UUID_t; +/** Documentation for C struct Handle_Entry_t */ +typedef PACKED(struct) packed_Handle_Entry_t_s { + /** The handles for which the attribute value has to be read + */ + uint16_t Handle; +} packed_Handle_Entry_t; +/** Documentation for C struct Handle_Packets_Pair_Entry_t */ +typedef PACKED(struct) packed_Handle_Packets_Pair_Entry_t_s { + /** Connection handle + */ + uint16_t Connection_Handle; + /** The number of HCI Data Packets that have been completed (transmitted +or flushed) for the associated Connection_Handle since the previous time +the event was returned. + */ + uint16_t HC_Num_Of_Completed_Packets; +} packed_Handle_Packets_Pair_Entry_t; +/** Documentation for C struct Attribute_Group_Handle_Pair_t */ +typedef PACKED(struct) packed_Attribute_Group_Handle_Pair_t_s { + /** Found Attribute handle + */ + uint16_t Found_Attribute_Handle; + /** Group End handle + */ + uint16_t Group_End_Handle; +} packed_Attribute_Group_Handle_Pair_t; +/** Documentation for C struct Handle_Item_t */ +typedef PACKED(struct) packed_Handle_Item_t_s { + /** + */ + uint16_t Handle; +} packed_Handle_Item_t; +/** Documentation for C struct Advertising_Report_t */ +typedef PACKED(struct) packed_Advertising_Report_t_s { + /** Type of advertising report event: +ADV_IND: Connectable undirected advertising', +ADV_DIRECT_IND: Connectable directed advertising, +ADV_SCAN_IND: Scannable undirected advertising, +ADV_NONCONN_IND: Non connectable undirected advertising, +SCAN_RSP: Scan response. + * Values: + - 0x00: ADV_IND + - 0x01: ADV_DIRECT_IND + - 0x02: ADV_SCAN_IND + - 0x03: ADV_NONCONN_IND + - 0x04: SCAN_RSP + */ + uint8_t Event_Type; + /** 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + */ + uint8_t Address_Type; + /** Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising +device. + */ + uint8_t Address[6]; + /** Length of the Data[i] field for each device which responded. + * Values: + - 0 ... 31 + */ + uint8_t Length_Data; + /** Length_Data[i] octets of advertising or scan response data formatted +as defined in [Vol 3] Part C, Section 8. + */ + uint8_t Data[1]; + /** N Size: 1 Octet (signed integer) +Units: dBm + * Values: + - 127: RSSI not available + - -127 ... 20 + */ + uint8_t RSSI; +} packed_Advertising_Report_t; +/** Documentation for C struct Direct_Advertising_Report_t */ +typedef PACKED(struct) packed_Direct_Advertising_Report_t_s { + /** Advertising type + * Values: + - 0x01: Connectable directed advertising (ADV_DIRECT_IND) + */ + uint8_t Event_Type; + /** 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + */ + uint8_t Address_Type; + /** Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the advertising device. + */ + uint8_t Address[6]; + /** 0x01 Random Device Address + * Values: + - 0x01: Random Device Address + */ + uint8_t Direct_Address_Type; + /** Random Device Address + */ + uint8_t Direct_Address[6]; + /** N Size: 1 Octet (signed integer) +Units: dBm + * Values: + - 127: RSSI not available + - -127 ... 20 + */ + uint8_t RSSI; +} packed_Direct_Advertising_Report_t; +typedef PACKED(struct) hci_disconnect_cp0_s { + uint16_t Connection_Handle; + uint8_t Reason; +} hci_disconnect_cp0; + +typedef PACKED(struct) hci_disconnect_rp0_s { + uint8_t Status; +} hci_disconnect_rp0; + +typedef PACKED(struct) hci_read_remote_version_information_cp0_s { + uint16_t Connection_Handle; +} hci_read_remote_version_information_cp0; + +typedef PACKED(struct) hci_read_remote_version_information_rp0_s { + uint8_t Status; +} hci_read_remote_version_information_rp0; + +typedef PACKED(struct) hci_set_event_mask_cp0_s { + uint8_t Event_Mask[8]; +} hci_set_event_mask_cp0; + +typedef PACKED(struct) hci_set_event_mask_rp0_s { + uint8_t Status; +} hci_set_event_mask_rp0; + +typedef PACKED(struct) hci_reset_rp0_s { + uint8_t Status; +} hci_reset_rp0; + +typedef PACKED(struct) hci_read_transmit_power_level_cp0_s { + uint16_t Connection_Handle; + uint8_t Type; +} hci_read_transmit_power_level_cp0; + +typedef PACKED(struct) hci_read_transmit_power_level_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Transmit_Power_Level; +} hci_read_transmit_power_level_rp0; + +typedef PACKED(struct) hci_read_local_version_information_rp0_s { + uint8_t Status; + uint8_t HCI_Version; + uint16_t HCI_Revision; + uint8_t LMP_PAL_Version; + uint16_t Manufacturer_Name; + uint16_t LMP_PAL_Subversion; +} hci_read_local_version_information_rp0; + +typedef PACKED(struct) hci_read_local_supported_commands_rp0_s { + uint8_t Status; + uint8_t Supported_Commands[64]; +} hci_read_local_supported_commands_rp0; + +typedef PACKED(struct) hci_read_local_supported_features_rp0_s { + uint8_t Status; + uint8_t LMP_Features[8]; +} hci_read_local_supported_features_rp0; + +typedef PACKED(struct) hci_read_bd_addr_rp0_s { + uint8_t Status; + uint8_t BD_ADDR[6]; +} hci_read_bd_addr_rp0; + +typedef PACKED(struct) hci_read_rssi_cp0_s { + uint16_t Connection_Handle; +} hci_read_rssi_cp0; + +typedef PACKED(struct) hci_read_rssi_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t RSSI; +} hci_read_rssi_rp0; + +typedef PACKED(struct) hci_le_set_event_mask_cp0_s { + uint8_t LE_Event_Mask[8]; +} hci_le_set_event_mask_cp0; + +typedef PACKED(struct) hci_le_set_event_mask_rp0_s { + uint8_t Status; +} hci_le_set_event_mask_rp0; + +typedef PACKED(struct) hci_le_read_buffer_size_rp0_s { + uint8_t Status; + uint16_t HC_LE_ACL_Data_Packet_Length; + uint8_t HC_Total_Num_LE_ACL_Data_Packets; +} hci_le_read_buffer_size_rp0; + +typedef PACKED(struct) hci_le_read_local_supported_features_rp0_s { + uint8_t Status; + uint8_t LE_Features[8]; +} hci_le_read_local_supported_features_rp0; + +typedef PACKED(struct) hci_le_set_random_address_cp0_s { + uint8_t Random_Address[6]; +} hci_le_set_random_address_cp0; + +typedef PACKED(struct) hci_le_set_random_address_rp0_s { + uint8_t Status; +} hci_le_set_random_address_rp0; + +typedef PACKED(struct) hci_le_set_advertising_parameters_cp0_s { + uint16_t Advertising_Interval_Min; + uint16_t Advertising_Interval_Max; + uint8_t Advertising_Type; + uint8_t Own_Address_Type; + uint8_t Peer_Address_Type; + uint8_t Peer_Address[6]; + uint8_t Advertising_Channel_Map; + uint8_t Advertising_Filter_Policy; +} hci_le_set_advertising_parameters_cp0; + +typedef PACKED(struct) hci_le_set_advertising_parameters_rp0_s { + uint8_t Status; +} hci_le_set_advertising_parameters_rp0; + +typedef PACKED(struct) hci_le_read_advertising_channel_tx_power_rp0_s { + uint8_t Status; + uint8_t Transmit_Power_Level; +} hci_le_read_advertising_channel_tx_power_rp0; + +typedef PACKED(struct) hci_le_set_advertising_data_cp0_s { + uint8_t Advertising_Data_Length; + uint8_t Advertising_Data[31]; +} hci_le_set_advertising_data_cp0; + +typedef PACKED(struct) hci_le_set_advertising_data_rp0_s { + uint8_t Status; +} hci_le_set_advertising_data_rp0; + +typedef PACKED(struct) hci_le_set_scan_response_data_cp0_s { + uint8_t Scan_Response_Data_Length; + uint8_t Scan_Response_Data[31]; +} hci_le_set_scan_response_data_cp0; + +typedef PACKED(struct) hci_le_set_scan_response_data_rp0_s { + uint8_t Status; +} hci_le_set_scan_response_data_rp0; + +typedef PACKED(struct) hci_le_set_advertise_enable_cp0_s { + uint8_t Advertising_Enable; +} hci_le_set_advertise_enable_cp0; + +typedef PACKED(struct) hci_le_set_advertise_enable_rp0_s { + uint8_t Status; +} hci_le_set_advertise_enable_rp0; + +typedef PACKED(struct) hci_le_set_scan_parameters_cp0_s { + uint8_t LE_Scan_Type; + uint16_t LE_Scan_Interval; + uint16_t LE_Scan_Window; + uint8_t Own_Address_Type; + uint8_t Scanning_Filter_Policy; +} hci_le_set_scan_parameters_cp0; + +typedef PACKED(struct) hci_le_set_scan_parameters_rp0_s { + uint8_t Status; +} hci_le_set_scan_parameters_rp0; + +typedef PACKED(struct) hci_le_set_scan_enable_cp0_s { + uint8_t LE_Scan_Enable; + uint8_t Filter_Duplicates; +} hci_le_set_scan_enable_cp0; + +typedef PACKED(struct) hci_le_set_scan_enable_rp0_s { + uint8_t Status; +} hci_le_set_scan_enable_rp0; + +typedef PACKED(struct) hci_le_create_connection_cp0_s { + uint16_t LE_Scan_Interval; + uint16_t LE_Scan_Window; + uint8_t Initiator_Filter_Policy; + uint8_t Peer_Address_Type; + uint8_t Peer_Address[6]; + uint8_t Own_Address_Type; + uint16_t Conn_Interval_Min; + uint16_t Conn_Interval_Max; + uint16_t Conn_Latency; + uint16_t Supervision_Timeout; + uint16_t Minimum_CE_Length; + uint16_t Maximum_CE_Length; +} hci_le_create_connection_cp0; + +typedef PACKED(struct) hci_le_create_connection_rp0_s { + uint8_t Status; +} hci_le_create_connection_rp0; + +typedef PACKED(struct) hci_le_create_connection_cancel_rp0_s { + uint8_t Status; +} hci_le_create_connection_cancel_rp0; + +typedef PACKED(struct) hci_le_read_white_list_size_rp0_s { + uint8_t Status; + uint8_t White_List_Size; +} hci_le_read_white_list_size_rp0; + +typedef PACKED(struct) hci_le_clear_white_list_rp0_s { + uint8_t Status; +} hci_le_clear_white_list_rp0; + +typedef PACKED(struct) hci_le_add_device_to_white_list_cp0_s { + uint8_t Address_Type; + uint8_t Address[6]; +} hci_le_add_device_to_white_list_cp0; + +typedef PACKED(struct) hci_le_add_device_to_white_list_rp0_s { + uint8_t Status; +} hci_le_add_device_to_white_list_rp0; + +typedef PACKED(struct) hci_le_remove_device_from_white_list_cp0_s { + uint8_t Address_Type; + uint8_t Address[6]; +} hci_le_remove_device_from_white_list_cp0; + +typedef PACKED(struct) hci_le_remove_device_from_white_list_rp0_s { + uint8_t Status; +} hci_le_remove_device_from_white_list_rp0; + +typedef PACKED(struct) hci_le_connection_update_cp0_s { + uint16_t Connection_Handle; + uint16_t Conn_Interval_Min; + uint16_t Conn_Interval_Max; + uint16_t Conn_Latency; + uint16_t Supervision_Timeout; + uint16_t Minimum_CE_Length; + uint16_t Maximum_CE_Length; +} hci_le_connection_update_cp0; + +typedef PACKED(struct) hci_le_connection_update_rp0_s { + uint8_t Status; +} hci_le_connection_update_rp0; + +typedef PACKED(struct) hci_le_set_host_channel_classification_cp0_s { + uint8_t LE_Channel_Map[5]; +} hci_le_set_host_channel_classification_cp0; + +typedef PACKED(struct) hci_le_set_host_channel_classification_rp0_s { + uint8_t Status; +} hci_le_set_host_channel_classification_rp0; + +typedef PACKED(struct) hci_le_read_channel_map_cp0_s { + uint16_t Connection_Handle; +} hci_le_read_channel_map_cp0; + +typedef PACKED(struct) hci_le_read_channel_map_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t LE_Channel_Map[5]; +} hci_le_read_channel_map_rp0; + +typedef PACKED(struct) hci_le_read_remote_used_features_cp0_s { + uint16_t Connection_Handle; +} hci_le_read_remote_used_features_cp0; + +typedef PACKED(struct) hci_le_read_remote_used_features_rp0_s { + uint8_t Status; +} hci_le_read_remote_used_features_rp0; + +typedef PACKED(struct) hci_le_encrypt_cp0_s { + uint8_t Key[16]; + uint8_t Plaintext_Data[16]; +} hci_le_encrypt_cp0; + +typedef PACKED(struct) hci_le_encrypt_rp0_s { + uint8_t Status; + uint8_t Encrypted_Data[16]; +} hci_le_encrypt_rp0; + +typedef PACKED(struct) hci_le_rand_rp0_s { + uint8_t Status; + uint8_t Random_Number[8]; +} hci_le_rand_rp0; + +typedef PACKED(struct) hci_le_start_encryption_cp0_s { + uint16_t Connection_Handle; + uint8_t Random_Number[8]; + uint16_t Encrypted_Diversifier; + uint8_t Long_Term_Key[16]; +} hci_le_start_encryption_cp0; + +typedef PACKED(struct) hci_le_start_encryption_rp0_s { + uint8_t Status; +} hci_le_start_encryption_rp0; + +typedef PACKED(struct) hci_le_long_term_key_request_reply_cp0_s { + uint16_t Connection_Handle; + uint8_t Long_Term_Key[16]; +} hci_le_long_term_key_request_reply_cp0; + +typedef PACKED(struct) hci_le_long_term_key_request_reply_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_long_term_key_request_reply_rp0; + +typedef PACKED(struct) hci_le_long_term_key_requested_negative_reply_cp0_s { + uint16_t Connection_Handle; +} hci_le_long_term_key_requested_negative_reply_cp0; + +typedef PACKED(struct) hci_le_long_term_key_requested_negative_reply_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_long_term_key_requested_negative_reply_rp0; + +typedef PACKED(struct) hci_le_read_supported_states_rp0_s { + uint8_t Status; + uint8_t LE_States[8]; +} hci_le_read_supported_states_rp0; + +typedef PACKED(struct) hci_le_receiver_test_cp0_s { + uint8_t RX_Frequency; +} hci_le_receiver_test_cp0; + +typedef PACKED(struct) hci_le_receiver_test_rp0_s { + uint8_t Status; +} hci_le_receiver_test_rp0; + +typedef PACKED(struct) hci_le_transmitter_test_cp0_s { + uint8_t TX_Frequency; + uint8_t Length_Of_Test_Data; + uint8_t Packet_Payload; +} hci_le_transmitter_test_cp0; + +typedef PACKED(struct) hci_le_transmitter_test_rp0_s { + uint8_t Status; +} hci_le_transmitter_test_rp0; + +typedef PACKED(struct) hci_le_test_end_rp0_s { + uint8_t Status; + uint16_t Number_Of_Packets; +} hci_le_test_end_rp0; + +typedef PACKED(struct) hci_le_set_data_length_cp0_s { + uint16_t Connection_Handle; + uint16_t TxOctets; + uint16_t TxTime; +} hci_le_set_data_length_cp0; + +typedef PACKED(struct) hci_le_set_data_length_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; +} hci_le_set_data_length_rp0; + +typedef PACKED(struct) hci_le_read_suggested_default_data_length_rp0_s { + uint8_t Status; + uint16_t SuggestedMaxTxOctets; + uint16_t SuggestedMaxTxTime; +} hci_le_read_suggested_default_data_length_rp0; + +typedef PACKED(struct) hci_le_write_suggested_default_data_length_cp0_s { + uint16_t SuggestedMaxTxOctets; + uint16_t SuggestedMaxTxTime; +} hci_le_write_suggested_default_data_length_cp0; + +typedef PACKED(struct) hci_le_write_suggested_default_data_length_rp0_s { + uint8_t Status; +} hci_le_write_suggested_default_data_length_rp0; + +typedef PACKED(struct) hci_le_read_local_p256_public_key_rp0_s { + uint8_t Status; +} hci_le_read_local_p256_public_key_rp0; + +typedef PACKED(struct) hci_le_generate_dhkey_cp0_s { + uint8_t Remote_P256_Public_Key[64]; +} hci_le_generate_dhkey_cp0; + +typedef PACKED(struct) hci_le_generate_dhkey_rp0_s { + uint8_t Status; +} hci_le_generate_dhkey_rp0; + +typedef PACKED(struct) hci_le_add_device_to_resolving_list_cp0_s { + uint8_t Peer_Identity_Address_Type; + uint8_t Peer_Identity_Address[6]; + uint8_t Peer_IRK[16]; + uint8_t Local_IRK[16]; +} hci_le_add_device_to_resolving_list_cp0; + +typedef PACKED(struct) hci_le_add_device_to_resolving_list_rp0_s { + uint8_t Status; +} hci_le_add_device_to_resolving_list_rp0; + +typedef PACKED(struct) hci_le_remove_device_from_resolving_list_cp0_s { + uint8_t Peer_Identity_Address_Type; + uint8_t Peer_Identity_Address[6]; +} hci_le_remove_device_from_resolving_list_cp0; + +typedef PACKED(struct) hci_le_remove_device_from_resolving_list_rp0_s { + uint8_t Status; +} hci_le_remove_device_from_resolving_list_rp0; + +typedef PACKED(struct) hci_le_clear_resolving_list_rp0_s { + uint8_t Status; +} hci_le_clear_resolving_list_rp0; + +typedef PACKED(struct) hci_le_read_resolving_list_size_rp0_s { + uint8_t Status; + uint8_t Resolving_List_Size; +} hci_le_read_resolving_list_size_rp0; + +typedef PACKED(struct) hci_le_read_peer_resolvable_address_cp0_s { + uint8_t Peer_Identity_Address_Type; + uint8_t Peer_Identity_Address[6]; +} hci_le_read_peer_resolvable_address_cp0; + +typedef PACKED(struct) hci_le_read_peer_resolvable_address_rp0_s { + uint8_t Status; + uint8_t Peer_Resolvable_Address[6]; +} hci_le_read_peer_resolvable_address_rp0; + +typedef PACKED(struct) hci_le_read_local_resolvable_address_cp0_s { + uint8_t Peer_Identity_Address_Type; + uint8_t Peer_Identity_Address[6]; +} hci_le_read_local_resolvable_address_cp0; + +typedef PACKED(struct) hci_le_read_local_resolvable_address_rp0_s { + uint8_t Status; + uint8_t Local_Resolvable_Address[6]; +} hci_le_read_local_resolvable_address_rp0; + +typedef PACKED(struct) hci_le_set_address_resolution_enable_cp0_s { + uint8_t Address_Resolution_Enable; +} hci_le_set_address_resolution_enable_cp0; + +typedef PACKED(struct) hci_le_set_address_resolution_enable_rp0_s { + uint8_t Status; +} hci_le_set_address_resolution_enable_rp0; + +typedef PACKED(struct) hci_le_set_resolvable_private_address_timeout_cp0_s { + uint16_t RPA_Timeout; +} hci_le_set_resolvable_private_address_timeout_cp0; + +typedef PACKED(struct) hci_le_set_resolvable_private_address_timeout_rp0_s { + uint8_t Status; +} hci_le_set_resolvable_private_address_timeout_rp0; + +typedef PACKED(struct) hci_le_read_maximum_data_length_rp0_s { + uint8_t Status; + uint16_t supportedMaxTxOctets; + uint16_t supportedMaxTxTime; + uint16_t supportedMaxRxOctets; + uint16_t supportedMaxRxTime; +} hci_le_read_maximum_data_length_rp0; + +typedef PACKED(struct) hci_disconnection_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Reason; +} hci_disconnection_complete_event_rp0; + +typedef PACKED(struct) hci_encryption_change_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Encryption_Enabled; +} hci_encryption_change_event_rp0; + +typedef PACKED(struct) hci_read_remote_version_information_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Version; + uint16_t Manufacturer_Name; + uint16_t Subversion; +} hci_read_remote_version_information_complete_event_rp0; + +typedef PACKED(struct) hci_hardware_error_event_rp0_s { + uint8_t Hardware_Code; +} hci_hardware_error_event_rp0; + +typedef PACKED(struct) hci_number_of_completed_packets_event_rp0_s { + uint8_t Number_of_Handles; + packed_Handle_Packets_Pair_Entry_t Handle_Packets_Pair_Entry[(HCI_MAX_PAYLOAD_SIZE - 1)/sizeof(packed_Handle_Packets_Pair_Entry_t)]; +} hci_number_of_completed_packets_event_rp0; + +typedef PACKED(struct) hci_data_buffer_overflow_event_rp0_s { + uint8_t Link_Type; +} hci_data_buffer_overflow_event_rp0; + +typedef PACKED(struct) hci_encryption_key_refresh_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; +} hci_encryption_key_refresh_complete_event_rp0; + +typedef PACKED(struct) hci_le_connection_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Role; + uint8_t Peer_Address_Type; + uint8_t Peer_Address[6]; + uint16_t Conn_Interval; + uint16_t Conn_Latency; + uint16_t Supervision_Timeout; + uint8_t Master_Clock_Accuracy; +} hci_le_connection_complete_event_rp0; + +typedef PACKED(struct) hci_le_advertising_report_event_rp0_s { + uint8_t Num_Reports; + packed_Advertising_Report_t Advertising_Report[(HCI_MAX_PAYLOAD_SIZE - 1)/sizeof(packed_Advertising_Report_t)]; +} hci_le_advertising_report_event_rp0; + +typedef PACKED(struct) hci_le_connection_update_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint16_t Conn_Interval; + uint16_t Conn_Latency; + uint16_t Supervision_Timeout; +} hci_le_connection_update_complete_event_rp0; + +typedef PACKED(struct) hci_le_read_remote_used_features_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t LE_Features[8]; +} hci_le_read_remote_used_features_complete_event_rp0; + +typedef PACKED(struct) hci_le_long_term_key_request_event_rp0_s { + uint16_t Connection_Handle; + uint8_t Random_Number[8]; + uint16_t Encrypted_Diversifier; +} hci_le_long_term_key_request_event_rp0; + +typedef PACKED(struct) hci_le_data_length_change_event_rp0_s { + uint16_t Connection_Handle; + uint16_t MaxTxOctets; + uint16_t MaxTxTime; + uint16_t MaxRxOctets; + uint16_t MaxRxTime; +} hci_le_data_length_change_event_rp0; + +typedef PACKED(struct) hci_le_read_local_p256_public_key_complete_event_rp0_s { + uint8_t Status; + uint8_t Local_P256_Public_Key[64]; +} hci_le_read_local_p256_public_key_complete_event_rp0; + +typedef PACKED(struct) hci_le_generate_dhkey_complete_event_rp0_s { + uint8_t Status; + uint8_t DHKey[32]; +} hci_le_generate_dhkey_complete_event_rp0; + +typedef PACKED(struct) hci_le_enhanced_connection_complete_event_rp0_s { + uint8_t Status; + uint16_t Connection_Handle; + uint8_t Role; + uint8_t Peer_Address_Type; + uint8_t Peer_Address[6]; + uint8_t Local_Resolvable_Private_Address[6]; + uint8_t Peer_Resolvable_Private_Address[6]; + uint16_t Conn_Interval; + uint16_t Conn_Latency; + uint16_t Supervision_Timeout; + uint8_t Master_Clock_Accuracy; +} hci_le_enhanced_connection_complete_event_rp0; + +typedef PACKED(struct) hci_le_direct_advertising_report_event_rp0_s { + uint8_t Num_Reports; + packed_Direct_Advertising_Report_t Direct_Advertising_Report[(HCI_MAX_PAYLOAD_SIZE - 1)/sizeof(packed_Direct_Advertising_Report_t)]; +} hci_le_direct_advertising_report_event_rp0; + +typedef PACKED(struct) aci_hal_write_config_data_cp0_s { + uint8_t Offset; + uint8_t Length; + uint8_t Value[(HCI_MAX_PAYLOAD_SIZE - 2)/sizeof(uint8_t)]; +} aci_hal_write_config_data_cp0; + +typedef PACKED(struct) aci_hal_write_config_data_rp0_s { + uint8_t Status; +} aci_hal_write_config_data_rp0; + +typedef PACKED(struct) aci_hal_read_config_data_cp0_s { + uint8_t Offset; +} aci_hal_read_config_data_cp0; + +typedef PACKED(struct) aci_hal_read_config_data_rp0_s { + uint8_t Status; + uint8_t Data_Length; + uint8_t Data[(HCI_MAX_PAYLOAD_SIZE - 2)/sizeof(uint8_t)]; +} aci_hal_read_config_data_rp0; + +const hci_command_table_type hci_command_table[56] = { + /* hci_disconnect */ + {0x0406, hci_disconnect_process}, + /* hci_read_remote_version_information */ + {0x041d, hci_read_remote_version_information_process}, + /* hci_set_event_mask */ + {0x0c01, hci_set_event_mask_process}, + /* hci_reset */ + {0x0c03, hci_reset_process}, + /* hci_read_transmit_power_level */ + {0x0c2d, hci_read_transmit_power_level_process}, + /* hci_read_local_version_information */ + {0x1001, hci_read_local_version_information_process}, + /* hci_read_local_supported_commands */ + {0x1002, hci_read_local_supported_commands_process}, + /* hci_read_local_supported_features */ + {0x1003, hci_read_local_supported_features_process}, + /* hci_read_bd_addr */ + {0x1009, hci_read_bd_addr_process}, + /* hci_read_rssi */ + {0x1405, hci_read_rssi_process}, + /* hci_le_set_event_mask */ + {0x2001, hci_le_set_event_mask_process}, + /* hci_le_read_buffer_size */ + {0x2002, hci_le_read_buffer_size_process}, + /* hci_le_read_local_supported_features */ + {0x2003, hci_le_read_local_supported_features_process}, + /* hci_le_set_random_address */ + {0x2005, hci_le_set_random_address_process}, + /* hci_le_set_advertising_parameters */ + {0x2006, hci_le_set_advertising_parameters_process}, + /* hci_le_read_advertising_channel_tx_power */ + {0x2007, hci_le_read_advertising_channel_tx_power_process}, + /* hci_le_set_advertising_data */ + {0x2008, hci_le_set_advertising_data_process}, + /* hci_le_set_scan_response_data */ + {0x2009, hci_le_set_scan_response_data_process}, + /* hci_le_set_advertise_enable */ + {0x200a, hci_le_set_advertise_enable_process}, + /* hci_le_set_scan_parameters */ + {0x200b, hci_le_set_scan_parameters_process}, + /* hci_le_set_scan_enable */ + {0x200c, hci_le_set_scan_enable_process}, + /* hci_le_create_connection */ + {0x200d, hci_le_create_connection_process}, + /* hci_le_create_connection_cancel */ + {0x200e, hci_le_create_connection_cancel_process}, + /* hci_le_read_white_list_size */ + {0x200f, hci_le_read_white_list_size_process}, + /* hci_le_clear_white_list */ + {0x2010, hci_le_clear_white_list_process}, + /* hci_le_add_device_to_white_list */ + {0x2011, hci_le_add_device_to_white_list_process}, + /* hci_le_remove_device_from_white_list */ + {0x2012, hci_le_remove_device_from_white_list_process}, + /* hci_le_connection_update */ + {0x2013, hci_le_connection_update_process}, + /* hci_le_set_host_channel_classification */ + {0x2014, hci_le_set_host_channel_classification_process}, + /* hci_le_read_channel_map */ + {0x2015, hci_le_read_channel_map_process}, + /* hci_le_read_remote_used_features */ + {0x2016, hci_le_read_remote_used_features_process}, + /* hci_le_encrypt */ + {0x2017, hci_le_encrypt_process}, + /* hci_le_rand */ + {0x2018, hci_le_rand_process}, + /* hci_le_start_encryption */ + {0x2019, hci_le_start_encryption_process}, + /* hci_le_long_term_key_request_reply */ + {0x201a, hci_le_long_term_key_request_reply_process}, + /* hci_le_long_term_key_requested_negative_reply */ + {0x201b, hci_le_long_term_key_requested_negative_reply_process}, + /* hci_le_read_supported_states */ + {0x201c, hci_le_read_supported_states_process}, + /* hci_le_receiver_test */ + {0x201d, hci_le_receiver_test_process}, + /* hci_le_transmitter_test */ + {0x201e, hci_le_transmitter_test_process}, + /* hci_le_test_end */ + {0x201f, hci_le_test_end_process}, + /* hci_le_set_data_length */ + {0x2022, hci_le_set_data_length_process}, + /* hci_le_read_suggested_default_data_length */ + {0x2023, hci_le_read_suggested_default_data_length_process}, + /* hci_le_write_suggested_default_data_length */ + {0x2024, hci_le_write_suggested_default_data_length_process}, + /* hci_le_read_local_p256_public_key */ + {0x2025, hci_le_read_local_p256_public_key_process}, + /* hci_le_generate_dhkey */ + {0x2026, hci_le_generate_dhkey_process}, + /* hci_le_add_device_to_resolving_list */ + {0x2027, hci_le_add_device_to_resolving_list_process}, + /* hci_le_remove_device_from_resolving_list */ + {0x2028, hci_le_remove_device_from_resolving_list_process}, + /* hci_le_clear_resolving_list */ + {0x2029, hci_le_clear_resolving_list_process}, + /* hci_le_read_resolving_list_size */ + {0x202a, hci_le_read_resolving_list_size_process}, + /* hci_le_read_peer_resolvable_address */ + {0x202b, hci_le_read_peer_resolvable_address_process}, + /* hci_le_read_local_resolvable_address */ + {0x202c, hci_le_read_local_resolvable_address_process}, + /* hci_le_set_address_resolution_enable */ + {0x202d, hci_le_set_address_resolution_enable_process}, + /* hci_le_set_resolvable_private_address_timeout */ + {0x202e, hci_le_set_resolvable_private_address_timeout_process}, + /* hci_le_read_maximum_data_length */ + {0x202f, hci_le_read_maximum_data_length_process}, + /* aci_hal_write_config_data */ + {0xfc0c, aci_hal_write_config_data_process}, + /* aci_hal_read_config_data */ + {0xfc0d, aci_hal_read_config_data_process} +}; + +/* tBleStatus hci_disconnect(uint16_t Connection_Handle, + uint8_t Reason); + */ +/* Command len: 2 + 1 */ +/* Response len: 1 */ +uint16_t hci_disconnect_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_disconnect_cp0 *cp0 = (hci_disconnect_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_disconnect(cp0->Connection_Handle /* 2 */, + cp0->Reason /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x06; + buffer_out[6] = 0x04; + return (output_size + 6); +} +/* tBleStatus hci_read_remote_version_information(uint16_t Connection_Handle); + */ +/* Command len: 2 */ +/* Response len: 1 */ +uint16_t hci_read_remote_version_information_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_read_remote_version_information_cp0 *cp0 = (hci_read_remote_version_information_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + *status = hci_read_remote_version_information(cp0->Connection_Handle /* 2 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x1d; + buffer_out[6] = 0x04; + return (output_size + 6); +} +/* tBleStatus hci_set_event_mask(uint8_t Event_Mask[8]); + */ +/* Command len: 8 */ +/* Response len: 1 */ +uint16_t hci_set_event_mask_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_set_event_mask_cp0 *cp0 = (hci_set_event_mask_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_set_event_mask(cp0->Event_Mask /* 8 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x01; + buffer_out[5] = 0x0c; + return (output_size + 6); +} +/* tBleStatus hci_reset(void); + */ +/* Command len: 0 */ +/* Response len: 1 */ +uint16_t hci_reset_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + *status = hci_reset(); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x03; + buffer_out[5] = 0x0c; + return (output_size + 6); +} +/* tBleStatus hci_read_transmit_power_level(uint16_t Connection_Handle, + uint8_t Type, + uint8_t *Transmit_Power_Level); + */ +/* Command len: 2 + 1 */ +/* Response len: 1 + 2 + 1 */ +uint16_t hci_read_transmit_power_level_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_read_transmit_power_level_cp0 *cp0 = (hci_read_transmit_power_level_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 2 + 1; + /* Output params */ + hci_read_transmit_power_level_rp0 *rp0 = (hci_read_transmit_power_level_rp0 *) (buffer_out + 6); + uint8_t Transmit_Power_Level = 0; + + if (buffer_out_max_length < (1 + 2 + 1 + 6)) { return 0; } + rp0->Status = hci_read_transmit_power_level(cp0->Connection_Handle /* 2 */, + cp0->Type /* 1 */, + &Transmit_Power_Level); + rp0->Connection_Handle = cp0->Connection_Handle; + rp0->Transmit_Power_Level = Transmit_Power_Level; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2d; + buffer_out[5] = 0x0c; + return (output_size + 6); +} +/* tBleStatus hci_read_local_version_information(uint8_t *HCI_Version, + uint16_t *HCI_Revision, + uint8_t *LMP_PAL_Version, + uint16_t *Manufacturer_Name, + uint16_t *LMP_PAL_Subversion); + */ +/* Command len: 0 */ +/* Response len: 1 + 1 + 2 + 1 + 2 + 2 */ +uint16_t hci_read_local_version_information_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 1 + 2 + 1 + 2 + 2; + /* Output params */ + hci_read_local_version_information_rp0 *rp0 = (hci_read_local_version_information_rp0 *) (buffer_out + 6); + uint8_t HCI_Version = 0; + uint16_t HCI_Revision = 0; + uint8_t LMP_PAL_Version = 0; + uint16_t Manufacturer_Name = 0; + uint16_t LMP_PAL_Subversion = 0; + + if (buffer_out_max_length < (1 + 1 + 2 + 1 + 2 + 2 + 6)) { return 0; } + rp0->Status = hci_read_local_version_information(&HCI_Version, + &HCI_Revision, + &LMP_PAL_Version, + &Manufacturer_Name, + &LMP_PAL_Subversion); + { + PartInfoType partInfo; + /* get partInfo */ + HAL_GetPartInfo(&partInfo); + // H[15:12]= Hardware cut major version + // h[11:8]= Hardware cut minor version + // C[7:4]= 0: BlueNRG/BlueNRG-MS, 1: BlueNRG-1; 2: BlueNRG-2; + // S[3:0]= Library major version + /* Set HCI_Revision fields with information coming from HAL_GetPartInfo() */ + HCI_Revision = HCI_Revision & 0xF; + HCI_Revision |= ((partInfo.die_major & 0xF) <<12) | ((partInfo.die_cut & 0xF) <<8) | ((partInfo.die_id & 0xF) <<4) ; + } + rp0->HCI_Version = HCI_Version; + rp0->HCI_Revision = HCI_Revision; + rp0->LMP_PAL_Version = LMP_PAL_Version; + rp0->Manufacturer_Name = Manufacturer_Name; + rp0->LMP_PAL_Subversion = LMP_PAL_Subversion; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x01; + buffer_out[5] = 0x10; + return (output_size + 6); +} +/* tBleStatus hci_read_local_supported_commands(uint8_t Supported_Commands[64]); + */ +/* Command len: 0 */ +/* Response len: 1 + 64 */ +uint16_t hci_read_local_supported_commands_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 64; + /* Output params */ + hci_read_local_supported_commands_rp0 *rp0 = (hci_read_local_supported_commands_rp0 *) (buffer_out + 6); + uint8_t Supported_Commands[64]; + + if (buffer_out_max_length < (1 + 64 + 6)) { return 0; } + rp0->Status = hci_read_local_supported_commands(Supported_Commands); + Osal_MemCpy((void *) rp0->Supported_Commands,(const void *) Supported_Commands, 64); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x02; + buffer_out[5] = 0x10; + return (output_size + 6); +} +/* tBleStatus hci_read_local_supported_features(uint8_t LMP_Features[8]); + */ +/* Command len: 0 */ +/* Response len: 1 + 8 */ +uint16_t hci_read_local_supported_features_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 8; + /* Output params */ + hci_read_local_supported_features_rp0 *rp0 = (hci_read_local_supported_features_rp0 *) (buffer_out + 6); + uint8_t LMP_Features[8]; + + if (buffer_out_max_length < (1 + 8 + 6)) { return 0; } + rp0->Status = hci_read_local_supported_features(LMP_Features); + Osal_MemCpy((void *) rp0->LMP_Features,(const void *) LMP_Features, 8); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x03; + buffer_out[5] = 0x10; + return (output_size + 6); +} +/* tBleStatus hci_read_bd_addr(uint8_t BD_ADDR[6]); + */ +/* Command len: 0 */ +/* Response len: 1 + 6 */ +uint16_t hci_read_bd_addr_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 6; + /* Output params */ + hci_read_bd_addr_rp0 *rp0 = (hci_read_bd_addr_rp0 *) (buffer_out + 6); + uint8_t BD_ADDR[6]; + + if (buffer_out_max_length < (1 + 6 + 6)) { return 0; } + rp0->Status = hci_read_bd_addr(BD_ADDR); + Osal_MemCpy((void *) rp0->BD_ADDR,(const void *) BD_ADDR, 6); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x09; + buffer_out[5] = 0x10; + return (output_size + 6); +} +/* tBleStatus hci_read_rssi(uint16_t Connection_Handle, + uint8_t *RSSI); + */ +/* Command len: 2 */ +/* Response len: 1 + 2 + 1 */ +uint16_t hci_read_rssi_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_read_rssi_cp0 *cp0 = (hci_read_rssi_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 2 + 1; + /* Output params */ + hci_read_rssi_rp0 *rp0 = (hci_read_rssi_rp0 *) (buffer_out + 6); + uint8_t RSSI = 0; + + if (buffer_out_max_length < (1 + 2 + 1 + 6)) { return 0; } + rp0->Status = hci_read_rssi(cp0->Connection_Handle /* 2 */, + &RSSI); + rp0->Connection_Handle = cp0->Connection_Handle; + rp0->RSSI = RSSI; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x05; + buffer_out[5] = 0x14; + return (output_size + 6); +} +/* tBleStatus hci_le_set_event_mask(uint8_t LE_Event_Mask[8]); + */ +/* Command len: 8 */ +/* Response len: 1 */ +uint16_t hci_le_set_event_mask_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_event_mask_cp0 *cp0 = (hci_le_set_event_mask_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_event_mask(cp0->LE_Event_Mask /* 8 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x01; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_buffer_size(uint16_t *HC_LE_ACL_Data_Packet_Length, + uint8_t *HC_Total_Num_LE_ACL_Data_Packets); + */ +/* Command len: 0 */ +/* Response len: 1 + 2 + 1 */ +uint16_t hci_le_read_buffer_size_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 2 + 1; + /* Output params */ + hci_le_read_buffer_size_rp0 *rp0 = (hci_le_read_buffer_size_rp0 *) (buffer_out + 6); + uint16_t HC_LE_ACL_Data_Packet_Length = 0; + uint8_t HC_Total_Num_LE_ACL_Data_Packets = 0; + + if (buffer_out_max_length < (1 + 2 + 1 + 6)) { return 0; } + rp0->Status = hci_le_read_buffer_size(&HC_LE_ACL_Data_Packet_Length, + &HC_Total_Num_LE_ACL_Data_Packets); + rp0->HC_LE_ACL_Data_Packet_Length = HC_LE_ACL_Data_Packet_Length; + rp0->HC_Total_Num_LE_ACL_Data_Packets = HC_Total_Num_LE_ACL_Data_Packets; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x02; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_local_supported_features(uint8_t LE_Features[8]); + */ +/* Command len: 0 */ +/* Response len: 1 + 8 */ +uint16_t hci_le_read_local_supported_features_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 8; + /* Output params */ + hci_le_read_local_supported_features_rp0 *rp0 = (hci_le_read_local_supported_features_rp0 *) (buffer_out + 6); + uint8_t LE_Features[8]; + + if (buffer_out_max_length < (1 + 8 + 6)) { return 0; } + rp0->Status = hci_le_read_local_supported_features(LE_Features); + Osal_MemCpy((void *) rp0->LE_Features,(const void *) LE_Features, 8); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x03; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_random_address(uint8_t Random_Address[6]); + */ +/* Command len: 6 */ +/* Response len: 1 */ +uint16_t hci_le_set_random_address_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_random_address_cp0 *cp0 = (hci_le_set_random_address_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_random_address(cp0->Random_Address /* 6 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x05; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_advertising_parameters(uint16_t Advertising_Interval_Min, + uint16_t Advertising_Interval_Max, + uint8_t Advertising_Type, + uint8_t Own_Address_Type, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Advertising_Channel_Map, + uint8_t Advertising_Filter_Policy); + */ +/* Command len: 2 + 2 + 1 + 1 + 1 + 6 + 1 + 1 */ +/* Response len: 1 */ +uint16_t hci_le_set_advertising_parameters_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_advertising_parameters_cp0 *cp0 = (hci_le_set_advertising_parameters_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_advertising_parameters(cp0->Advertising_Interval_Min /* 2 */, + cp0->Advertising_Interval_Max /* 2 */, + cp0->Advertising_Type /* 1 */, + cp0->Own_Address_Type /* 1 */, + cp0->Peer_Address_Type /* 1 */, + cp0->Peer_Address /* 6 */, + cp0->Advertising_Channel_Map /* 1 */, + cp0->Advertising_Filter_Policy /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x06; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_advertising_channel_tx_power(uint8_t *Transmit_Power_Level); + */ +/* Command len: 0 */ +/* Response len: 1 + 1 */ +uint16_t hci_le_read_advertising_channel_tx_power_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 1; + /* Output params */ + hci_le_read_advertising_channel_tx_power_rp0 *rp0 = (hci_le_read_advertising_channel_tx_power_rp0 *) (buffer_out + 6); + uint8_t Transmit_Power_Level = 0; + + if (buffer_out_max_length < (1 + 1 + 6)) { return 0; } + rp0->Status = hci_le_read_advertising_channel_tx_power(&Transmit_Power_Level); + rp0->Transmit_Power_Level = Transmit_Power_Level; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x07; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_advertising_data(uint8_t Advertising_Data_Length, + uint8_t Advertising_Data[31]); + */ +/* Command len: 1 + 31 */ +/* Response len: 1 */ +uint16_t hci_le_set_advertising_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_advertising_data_cp0 *cp0 = (hci_le_set_advertising_data_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_advertising_data(cp0->Advertising_Data_Length /* 1 */, + cp0->Advertising_Data /* 31 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x08; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_scan_response_data(uint8_t Scan_Response_Data_Length, + uint8_t Scan_Response_Data[31]); + */ +/* Command len: 1 + 31 */ +/* Response len: 1 */ +uint16_t hci_le_set_scan_response_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_scan_response_data_cp0 *cp0 = (hci_le_set_scan_response_data_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_scan_response_data(cp0->Scan_Response_Data_Length /* 1 */, + cp0->Scan_Response_Data /* 31 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x09; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_advertise_enable(uint8_t Advertising_Enable); + */ +/* Command len: 1 */ +/* Response len: 1 */ +uint16_t hci_le_set_advertise_enable_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_advertise_enable_cp0 *cp0 = (hci_le_set_advertise_enable_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + *status = hci_le_set_advertise_enable(cp0->Advertising_Enable /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0a; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_scan_parameters(uint8_t LE_Scan_Type, + uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Own_Address_Type, + uint8_t Scanning_Filter_Policy); + */ +/* Command len: 1 + 2 + 2 + 1 + 1 */ +/* Response len: 1 */ +uint16_t hci_le_set_scan_parameters_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_scan_parameters_cp0 *cp0 = (hci_le_set_scan_parameters_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_scan_parameters(cp0->LE_Scan_Type /* 1 */, + cp0->LE_Scan_Interval /* 2 */, + cp0->LE_Scan_Window /* 2 */, + cp0->Own_Address_Type /* 1 */, + cp0->Scanning_Filter_Policy /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0b; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_scan_enable(uint8_t LE_Scan_Enable, + uint8_t Filter_Duplicates); + */ +/* Command len: 1 + 1 */ +/* Response len: 1 */ +uint16_t hci_le_set_scan_enable_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_scan_enable_cp0 *cp0 = (hci_le_set_scan_enable_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_scan_enable(cp0->LE_Scan_Enable /* 1 */, + cp0->Filter_Duplicates /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0c; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_create_connection(uint16_t LE_Scan_Interval, + uint16_t LE_Scan_Window, + uint8_t Initiator_Filter_Policy, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Own_Address_Type, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + */ +/* Command len: 2 + 2 + 1 + 1 + 6 + 1 + 2 + 2 + 2 + 2 + 2 + 2 */ +/* Response len: 1 */ +uint16_t hci_le_create_connection_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_create_connection_cp0 *cp0 = (hci_le_create_connection_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_create_connection(cp0->LE_Scan_Interval /* 2 */, + cp0->LE_Scan_Window /* 2 */, + cp0->Initiator_Filter_Policy /* 1 */, + cp0->Peer_Address_Type /* 1 */, + cp0->Peer_Address /* 6 */, + cp0->Own_Address_Type /* 1 */, + cp0->Conn_Interval_Min /* 2 */, + cp0->Conn_Interval_Max /* 2 */, + cp0->Conn_Latency /* 2 */, + cp0->Supervision_Timeout /* 2 */, + cp0->Minimum_CE_Length /* 2 */, + cp0->Maximum_CE_Length /* 2 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x0d; + buffer_out[6] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_create_connection_cancel(void); + */ +/* Command len: 0 */ +/* Response len: 1 */ +uint16_t hci_le_create_connection_cancel_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_create_connection_cancel(); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0e; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_white_list_size(uint8_t *White_List_Size); + */ +/* Command len: 0 */ +/* Response len: 1 + 1 */ +uint16_t hci_le_read_white_list_size_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 1; + /* Output params */ + hci_le_read_white_list_size_rp0 *rp0 = (hci_le_read_white_list_size_rp0 *) (buffer_out + 6); + uint8_t White_List_Size = 0; + + if (buffer_out_max_length < (1 + 1 + 6)) { return 0; } + rp0->Status = hci_le_read_white_list_size(&White_List_Size); + rp0->White_List_Size = White_List_Size; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0f; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_clear_white_list(void); + */ +/* Command len: 0 */ +/* Response len: 1 */ +uint16_t hci_le_clear_white_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_clear_white_list(); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x10; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_add_device_to_white_list(uint8_t Address_Type, + uint8_t Address[6]); + */ +/* Command len: 1 + 6 */ +/* Response len: 1 */ +uint16_t hci_le_add_device_to_white_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_add_device_to_white_list_cp0 *cp0 = (hci_le_add_device_to_white_list_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_add_device_to_white_list(cp0->Address_Type /* 1 */, + cp0->Address /* 6 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x11; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_remove_device_from_white_list(uint8_t Address_Type, + uint8_t Address[6]); + */ +/* Command len: 1 + 6 */ +/* Response len: 1 */ +uint16_t hci_le_remove_device_from_white_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_remove_device_from_white_list_cp0 *cp0 = (hci_le_remove_device_from_white_list_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_remove_device_from_white_list(cp0->Address_Type /* 1 */, + cp0->Address /* 6 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x12; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_connection_update(uint16_t Connection_Handle, + uint16_t Conn_Interval_Min, + uint16_t Conn_Interval_Max, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint16_t Minimum_CE_Length, + uint16_t Maximum_CE_Length); + */ +/* Command len: 2 + 2 + 2 + 2 + 2 + 2 + 2 */ +/* Response len: 1 */ +uint16_t hci_le_connection_update_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_connection_update_cp0 *cp0 = (hci_le_connection_update_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_connection_update(cp0->Connection_Handle /* 2 */, + cp0->Conn_Interval_Min /* 2 */, + cp0->Conn_Interval_Max /* 2 */, + cp0->Conn_Latency /* 2 */, + cp0->Supervision_Timeout /* 2 */, + cp0->Minimum_CE_Length /* 2 */, + cp0->Maximum_CE_Length /* 2 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x13; + buffer_out[6] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_host_channel_classification(uint8_t LE_Channel_Map[5]); + */ +/* Command len: 5 */ +/* Response len: 1 */ +uint16_t hci_le_set_host_channel_classification_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_host_channel_classification_cp0 *cp0 = (hci_le_set_host_channel_classification_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_host_channel_classification(cp0->LE_Channel_Map /* 5 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x14; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_channel_map(uint16_t Connection_Handle, + uint8_t LE_Channel_Map[5]); + */ +/* Command len: 2 */ +/* Response len: 1 + 2 + 5 */ +uint16_t hci_le_read_channel_map_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_read_channel_map_cp0 *cp0 = (hci_le_read_channel_map_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 2 + 5; + /* Output params */ + hci_le_read_channel_map_rp0 *rp0 = (hci_le_read_channel_map_rp0 *) (buffer_out + 6); + uint8_t LE_Channel_Map[5]; + + if (buffer_out_max_length < (1 + 2 + 5 + 6)) { return 0; } + rp0->Status = hci_le_read_channel_map(cp0->Connection_Handle /* 2 */, + LE_Channel_Map); + rp0->Connection_Handle = cp0->Connection_Handle; + Osal_MemCpy((void *) rp0->LE_Channel_Map,(const void *) LE_Channel_Map, 5); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x15; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_remote_used_features(uint16_t Connection_Handle); + */ +/* Command len: 2 */ +/* Response len: 1 */ +uint16_t hci_le_read_remote_used_features_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_read_remote_used_features_cp0 *cp0 = (hci_le_read_remote_used_features_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_read_remote_used_features(cp0->Connection_Handle /* 2 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x16; + buffer_out[6] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_encrypt(uint8_t Key[16], + uint8_t Plaintext_Data[16], + uint8_t Encrypted_Data[16]); + */ +/* Command len: 16 + 16 */ +/* Response len: 1 + 16 */ +uint16_t hci_le_encrypt_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_encrypt_cp0 *cp0 = (hci_le_encrypt_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 16; + /* Output params */ + hci_le_encrypt_rp0 *rp0 = (hci_le_encrypt_rp0 *) (buffer_out + 6); + uint8_t Encrypted_Data[16]; + + if (buffer_out_max_length < (1 + 16 + 6)) { return 0; } + rp0->Status = hci_le_encrypt(cp0->Key /* 16 */, + cp0->Plaintext_Data /* 16 */, + Encrypted_Data); + Osal_MemCpy((void *) rp0->Encrypted_Data,(const void *) Encrypted_Data, 16); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x17; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_rand(uint8_t Random_Number[8]); + */ +/* Command len: 0 */ +/* Response len: 1 + 8 */ +uint16_t hci_le_rand_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 8; + /* Output params */ + hci_le_rand_rp0 *rp0 = (hci_le_rand_rp0 *) (buffer_out + 6); + uint8_t Random_Number[8]; + + if (buffer_out_max_length < (1 + 8 + 6)) { return 0; } + rp0->Status = hci_le_rand(Random_Number); + Osal_MemCpy((void *) rp0->Random_Number,(const void *) Random_Number, 8); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x18; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_start_encryption(uint16_t Connection_Handle, + uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier, + uint8_t Long_Term_Key[16]); + */ +/* Command len: 2 + 8 + 2 + 16 */ +/* Response len: 1 */ +uint16_t hci_le_start_encryption_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_start_encryption_cp0 *cp0 = (hci_le_start_encryption_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_start_encryption(cp0->Connection_Handle /* 2 */, + cp0->Random_Number /* 8 */, + cp0->Encrypted_Diversifier /* 2 */, + cp0->Long_Term_Key /* 16 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x19; + buffer_out[6] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_long_term_key_request_reply(uint16_t Connection_Handle, + uint8_t Long_Term_Key[16]); + */ +/* Command len: 2 + 16 */ +/* Response len: 1 + 2 */ +uint16_t hci_le_long_term_key_request_reply_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_long_term_key_request_reply_cp0 *cp0 = (hci_le_long_term_key_request_reply_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 2; + /* Output params */ + hci_le_long_term_key_request_reply_rp0 *rp0 = (hci_le_long_term_key_request_reply_rp0 *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 2 + 6)) { return 0; } + rp0->Status = hci_le_long_term_key_request_reply(cp0->Connection_Handle /* 2 */, + cp0->Long_Term_Key /* 16 */); + rp0->Connection_Handle = cp0->Connection_Handle; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x1a; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_long_term_key_requested_negative_reply(uint16_t Connection_Handle); + */ +/* Command len: 2 */ +/* Response len: 1 + 2 */ +uint16_t hci_le_long_term_key_requested_negative_reply_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_long_term_key_requested_negative_reply_cp0 *cp0 = (hci_le_long_term_key_requested_negative_reply_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 2; + /* Output params */ + hci_le_long_term_key_requested_negative_reply_rp0 *rp0 = (hci_le_long_term_key_requested_negative_reply_rp0 *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 2 + 6)) { return 0; } + rp0->Status = hci_le_long_term_key_requested_negative_reply(cp0->Connection_Handle /* 2 */); + rp0->Connection_Handle = cp0->Connection_Handle; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x1b; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_supported_states(uint8_t LE_States[8]); + */ +/* Command len: 0 */ +/* Response len: 1 + 8 */ +uint16_t hci_le_read_supported_states_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 8; + /* Output params */ + hci_le_read_supported_states_rp0 *rp0 = (hci_le_read_supported_states_rp0 *) (buffer_out + 6); + uint8_t LE_States[8]; + + if (buffer_out_max_length < (1 + 8 + 6)) { return 0; } + rp0->Status = hci_le_read_supported_states(LE_States); + Osal_MemCpy((void *) rp0->LE_States,(const void *) LE_States, 8); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x1c; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_receiver_test(uint8_t RX_Frequency); + */ +/* Command len: 1 */ +/* Response len: 1 */ +uint16_t hci_le_receiver_test_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_receiver_test_cp0 *cp0 = (hci_le_receiver_test_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_receiver_test(cp0->RX_Frequency /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x1d; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_transmitter_test(uint8_t TX_Frequency, + uint8_t Length_Of_Test_Data, + uint8_t Packet_Payload); + */ +/* Command len: 1 + 1 + 1 */ +/* Response len: 1 */ +uint16_t hci_le_transmitter_test_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_transmitter_test_cp0 *cp0 = (hci_le_transmitter_test_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_transmitter_test(cp0->TX_Frequency /* 1 */, + cp0->Length_Of_Test_Data /* 1 */, + cp0->Packet_Payload /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x1e; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_test_end(uint16_t *Number_Of_Packets); + */ +/* Command len: 0 */ +/* Response len: 1 + 2 */ +uint16_t hci_le_test_end_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 2; + /* Output params */ + hci_le_test_end_rp0 *rp0 = (hci_le_test_end_rp0 *) (buffer_out + 6); + uint16_t Number_Of_Packets = 0; + + if (buffer_out_max_length < (1 + 2 + 6)) { return 0; } + rp0->Status = hci_le_test_end(&Number_Of_Packets); + rp0->Number_Of_Packets = Number_Of_Packets; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x1f; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_data_length(uint16_t Connection_Handle, + uint16_t TxOctets, + uint16_t TxTime); + */ +/* Command len: 2 + 2 + 2 */ +/* Response len: 1 + 2 */ +uint16_t hci_le_set_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_data_length_cp0 *cp0 = (hci_le_set_data_length_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 2; + /* Output params */ + hci_le_set_data_length_rp0 *rp0 = (hci_le_set_data_length_rp0 *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 2 + 6)) { return 0; } + rp0->Status = hci_le_set_data_length(cp0->Connection_Handle /* 2 */, + cp0->TxOctets /* 2 */, + cp0->TxTime /* 2 */); + rp0->Connection_Handle = cp0->Connection_Handle; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x22; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_suggested_default_data_length(uint16_t *SuggestedMaxTxOctets, + uint16_t *SuggestedMaxTxTime); + */ +/* Command len: 0 */ +/* Response len: 1 + 2 + 2 */ +uint16_t hci_le_read_suggested_default_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 2 + 2; + /* Output params */ + hci_le_read_suggested_default_data_length_rp0 *rp0 = (hci_le_read_suggested_default_data_length_rp0 *) (buffer_out + 6); + uint16_t SuggestedMaxTxOctets = 0; + uint16_t SuggestedMaxTxTime = 0; + + if (buffer_out_max_length < (1 + 2 + 2 + 6)) { return 0; } + rp0->Status = hci_le_read_suggested_default_data_length(&SuggestedMaxTxOctets, + &SuggestedMaxTxTime); + rp0->SuggestedMaxTxOctets = SuggestedMaxTxOctets; + rp0->SuggestedMaxTxTime = SuggestedMaxTxTime; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x23; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_write_suggested_default_data_length(uint16_t SuggestedMaxTxOctets, + uint16_t SuggestedMaxTxTime); + */ +/* Command len: 2 + 2 */ +/* Response len: 1 */ +uint16_t hci_le_write_suggested_default_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_write_suggested_default_data_length_cp0 *cp0 = (hci_le_write_suggested_default_data_length_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_write_suggested_default_data_length(cp0->SuggestedMaxTxOctets /* 2 */, + cp0->SuggestedMaxTxTime /* 2 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x24; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_local_p256_public_key(void); + */ +/* Command len: 0 */ +/* Response len: 1 */ +uint16_t hci_le_read_local_p256_public_key_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_read_local_p256_public_key(); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x25; + buffer_out[6] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_generate_dhkey(uint8_t Remote_P256_Public_Key[64]); + */ +/* Command len: 64 */ +/* Response len: 1 */ +uint16_t hci_le_generate_dhkey_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_generate_dhkey_cp0 *cp0 = (hci_le_generate_dhkey_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 3); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_generate_dhkey(cp0->Remote_P256_Public_Key /* 64 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0F; + buffer_out[2] = output_size + 3; + buffer_out[4] = 0x01; + buffer_out[5] = 0x26; + buffer_out[6] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_add_device_to_resolving_list(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6], + uint8_t Peer_IRK[16], + uint8_t Local_IRK[16]); + */ +/* Command len: 1 + 6 + 16 + 16 */ +/* Response len: 1 */ +uint16_t hci_le_add_device_to_resolving_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_add_device_to_resolving_list_cp0 *cp0 = (hci_le_add_device_to_resolving_list_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_add_device_to_resolving_list(cp0->Peer_Identity_Address_Type /* 1 */, + cp0->Peer_Identity_Address /* 6 */, + cp0->Peer_IRK /* 16 */, + cp0->Local_IRK /* 16 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x27; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_remove_device_from_resolving_list(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6]); + */ +/* Command len: 1 + 6 */ +/* Response len: 1 */ +uint16_t hci_le_remove_device_from_resolving_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_remove_device_from_resolving_list_cp0 *cp0 = (hci_le_remove_device_from_resolving_list_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_remove_device_from_resolving_list(cp0->Peer_Identity_Address_Type /* 1 */, + cp0->Peer_Identity_Address /* 6 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x28; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_clear_resolving_list(void); + */ +/* Command len: 0 */ +/* Response len: 1 */ +uint16_t hci_le_clear_resolving_list_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_clear_resolving_list(); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x29; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_resolving_list_size(uint8_t *Resolving_List_Size); + */ +/* Command len: 0 */ +/* Response len: 1 + 1 */ +uint16_t hci_le_read_resolving_list_size_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 1; + /* Output params */ + hci_le_read_resolving_list_size_rp0 *rp0 = (hci_le_read_resolving_list_size_rp0 *) (buffer_out + 6); + uint8_t Resolving_List_Size = 0; + + if (buffer_out_max_length < (1 + 1 + 6)) { return 0; } + rp0->Status = hci_le_read_resolving_list_size(&Resolving_List_Size); + rp0->Resolving_List_Size = Resolving_List_Size; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2a; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_peer_resolvable_address(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6], + uint8_t Peer_Resolvable_Address[6]); + */ +/* Command len: 1 + 6 */ +/* Response len: 1 + 6 */ +uint16_t hci_le_read_peer_resolvable_address_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_read_peer_resolvable_address_cp0 *cp0 = (hci_le_read_peer_resolvable_address_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 6; + /* Output params */ + hci_le_read_peer_resolvable_address_rp0 *rp0 = (hci_le_read_peer_resolvable_address_rp0 *) (buffer_out + 6); + uint8_t Peer_Resolvable_Address[6]; + + if (buffer_out_max_length < (1 + 6 + 6)) { return 0; } + rp0->Status = hci_le_read_peer_resolvable_address(cp0->Peer_Identity_Address_Type /* 1 */, + cp0->Peer_Identity_Address /* 6 */, + Peer_Resolvable_Address); + Osal_MemCpy((void *) rp0->Peer_Resolvable_Address,(const void *) Peer_Resolvable_Address, 6); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2b; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_local_resolvable_address(uint8_t Peer_Identity_Address_Type, + uint8_t Peer_Identity_Address[6], + uint8_t Local_Resolvable_Address[6]); + */ +/* Command len: 1 + 6 */ +/* Response len: 1 + 6 */ +uint16_t hci_le_read_local_resolvable_address_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_read_local_resolvable_address_cp0 *cp0 = (hci_le_read_local_resolvable_address_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1 + 6; + /* Output params */ + hci_le_read_local_resolvable_address_rp0 *rp0 = (hci_le_read_local_resolvable_address_rp0 *) (buffer_out + 6); + uint8_t Local_Resolvable_Address[6]; + + if (buffer_out_max_length < (1 + 6 + 6)) { return 0; } + rp0->Status = hci_le_read_local_resolvable_address(cp0->Peer_Identity_Address_Type /* 1 */, + cp0->Peer_Identity_Address /* 6 */, + Local_Resolvable_Address); + Osal_MemCpy((void *) rp0->Local_Resolvable_Address,(const void *) Local_Resolvable_Address, 6); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2c; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_address_resolution_enable(uint8_t Address_Resolution_Enable); + */ +/* Command len: 1 */ +/* Response len: 1 */ +uint16_t hci_le_set_address_resolution_enable_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_address_resolution_enable_cp0 *cp0 = (hci_le_set_address_resolution_enable_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_address_resolution_enable(cp0->Address_Resolution_Enable /* 1 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2d; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_set_resolvable_private_address_timeout(uint16_t RPA_Timeout); + */ +/* Command len: 2 */ +/* Response len: 1 */ +uint16_t hci_le_set_resolvable_private_address_timeout_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + hci_le_set_resolvable_private_address_timeout_cp0 *cp0 = (hci_le_set_resolvable_private_address_timeout_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = hci_le_set_resolvable_private_address_timeout(cp0->RPA_Timeout /* 2 */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2e; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* tBleStatus hci_le_read_maximum_data_length(uint16_t *supportedMaxTxOctets, + uint16_t *supportedMaxTxTime, + uint16_t *supportedMaxRxOctets, + uint16_t *supportedMaxRxTime); + */ +/* Command len: 0 */ +/* Response len: 1 + 2 + 2 + 2 + 2 */ +uint16_t hci_le_read_maximum_data_length_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + + int output_size = 1 + 2 + 2 + 2 + 2; + /* Output params */ + hci_le_read_maximum_data_length_rp0 *rp0 = (hci_le_read_maximum_data_length_rp0 *) (buffer_out + 6); + uint16_t supportedMaxTxOctets = 0; + uint16_t supportedMaxTxTime = 0; + uint16_t supportedMaxRxOctets = 0; + uint16_t supportedMaxRxTime = 0; + + if (buffer_out_max_length < (1 + 2 + 2 + 2 + 2 + 6)) { return 0; } + rp0->Status = hci_le_read_maximum_data_length(&supportedMaxTxOctets, + &supportedMaxTxTime, + &supportedMaxRxOctets, + &supportedMaxRxTime); + rp0->supportedMaxTxOctets = supportedMaxTxOctets; + rp0->supportedMaxTxTime = supportedMaxTxTime; + rp0->supportedMaxRxOctets = supportedMaxRxOctets; + rp0->supportedMaxRxTime = supportedMaxRxTime; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x2f; + buffer_out[5] = 0x20; + return (output_size + 6); +} +/* hci_disconnection_complete_event */ +/* Event len: 1 + 2 + 1 */ +/** + * @brief The Disconnection Complete event occurs when a connection is terminated. +The status parameter indicates if the disconnection was successful or not. The +reason parameter indicates the reason for the disconnection if the disconnection +was successful. If the disconnection was not successful, the value of the +reason parameter can be ignored by the Host. For example, this can be the +case if the Host has issued the Disconnect command and there was a parameter +error, or the command was not presently allowed, or a Connection_Handle +that didn't correspond to a connection was given. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection_Handle which was disconnected. + * Values: + - 0x0000 ... 0x0EFF + * @param Reason Reason for disconnection. + * Values: + - 0x00: Success + - 0x01: Unknown HCI Command + - 0x02: Unknown Connection Identifier + - 0x03: Hardware Failure + - 0x04: Page Timeout + - 0x05: Authentication Failure + - 0x06: PIN or Key Missing + - 0x07: Memory Capacity Exceeded + - 0x08: Connection Timeout + - 0x09: Connection Limit Exceeded + - 0x0A: Synchronous Connection Limit to a Device Exceeded + - 0x0B: ACL Connection Already Exists + - 0x0C: Command Disallowed + - 0x0D: Connection Rejected Due To Limited Resources + - 0x0E: Connection Rejected Due To Security Reasons + - 0x0F: Connection Rejected due to Unacceptable BD_ADDR + - 0x10: Connection Accept Timeout Exceeded + - 0x11: Unsupported Feature Or Parameter Value + - 0x12: Invalid HCI Command Parameters + - 0x13: Remote User Terminated Connection + - 0x14: Remote Device Terminated Connection due to Low Resources + - 0x15: Remote Device Terminated Connection due to Power Off + - 0x16: Connection Terminated By Local Host + - 0x17: Repeated Attempts + - 0x18: Pairing Not Allowed + - 0x19: Unknown LMP PDU + - 0x1A: Unsupported Remote Feature / Unsupported LMP Feature + - 0x1B: SCO Offset Rejected + - 0x1C: SCO Interval Rejected + - 0x1D: SCO Air Mode Rejected + - 0x1E: Invalid LMP Parameters + - 0x1F: Unspecified Error + - 0x20: Unsupported LMP Parameter Value + - 0x21: Role Change Not Allowed + - 0x22: LMP Response Timeout / LL Response Timeout + - 0x23: LMP Error Transaction Collision + - 0x24: LMP PDU Not Allowed + - 0x25: Encryption Mode Not Acceptable + - 0x26: Link Key cannot be Changed + - 0x27: Requested QoS Not Supported + - 0x28: Instant Passed + - 0x29: Pairing With Unit Key Not Supported + - 0x2A: Different Transaction Collision + - 0x2C: QoS Unacceptable Parameter + - 0x2D: QoS Rejected + - 0x2E: Channel Assessment Not Supported + - 0x2F: Insufficient Security + - 0x30: Parameter Out Of Mandatory Range + - 0x32: Role Switch Pending + - 0x34: Reserved Slot Violation + - 0x35: Role Switch Failed + - 0x36: Extended Inquiry Response Too Large + - 0x37: Secure Simple Pairing Not Supported by Host + - 0x38: Host Busy - Pairing + - 0x39: Connection Rejected due to No Suitable Channel Found + - 0x3A: Controller Busy + - 0x3B: Unacceptable Connection Interval + - 0x3C: Directed Advertising Timeout + - 0x3D: Connection Terminated Due to MIC Failure + - 0x3E: Connection Failed to be Established + - 0x3F: MAC of the 802.11 AMP + - 0x41: Failed + - 0x42: Invalid parameters + - 0x43: Busy + - 0x44: Invalid length + - 0x45: Pending + - 0x46: Not allowed + - 0x47: GATT error + - 0x48: Address not resolved + - 0x50: Invalid CID + - 0x5A: CSRK not found + - 0x5B: IRK not found + - 0x5C: Device not found in DB + - 0x5D: Security DB full + - 0x5E: Device not bonded + - 0x5F: Device in blacklist + - 0x60: Invalid handle + - 0x61: Invalid parameter + - 0x62: Out of handles + - 0x63: Invalid operation + - 0x64: Insufficient resources + - 0x65: Insufficient encryption key size + - 0x66: Characteristic already exist + - 0x82: No valid slot + - 0x83: Short window + - 0x84: New interval failed + - 0x85: Too large interval + - 0x86: Slot length failed + - 0xFA: Flash read failed + - 0xFB: Flash write failed + - 0xFC: Flash erase failed + * @retval None +*/ +void hci_disconnection_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Reason) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_disconnection_complete_event_rp0 *rp0 = (hci_disconnection_complete_event_rp0 *) (buffer_out + 3); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + rp0->Reason = Reason; + buffer_out[0] = 0x04; + buffer_out[1] = 0x05; + buffer_out[2] = 1 + 2 + 1; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_encryption_change_event */ +/* Event len: 1 + 2 + 1 */ +/** + * @brief The Encryption Change event is used to indicate that the change of the encryption +mode has been completed. The Connection_Handle will be a Connection_Handle +for an ACL connection. The Encryption_Enabled event parameter +specifies the new Encryption_Enabled parameter for the Connection_Handle +specified by the Connection_Handle event parameter. This event will occur on +both devices to notify the Hosts when Encryption has changed for the specified +Connection_Handle between two devices. Note: This event shall not be generated +if encryption is paused or resumed; during a role switch, for example. +The meaning of the Encryption_Enabled parameter depends on whether the +Host has indicated support for Secure Connections in the Secure_Connections_Host_Support +parameter. When Secure_Connections_Host_Support is +'disabled' or the Connection_Handle refers to an LE link, the Controller shall +only use Encryption_Enabled values 0x00 (OFF) and 0x01 (ON). +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.7.8) + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Encryption_Enabled Link Level Encryption. + * Values: + - 0x00: Link Level Encryption OFF + - 0x01: Link Level Encryption is ON with AES-CCM + * @retval None +*/ +void hci_encryption_change_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Encryption_Enabled) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_encryption_change_event_rp0 *rp0 = (hci_encryption_change_event_rp0 *) (buffer_out + 3); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + rp0->Encryption_Enabled = Encryption_Enabled; + buffer_out[0] = 0x04; + buffer_out[1] = 0x08; + buffer_out[2] = 1 + 2 + 1; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_read_remote_version_information_complete_event */ +/* Event len: 1 + 2 + 1 + 2 + 2 */ +/** + * @brief The Read Remote Version Information Complete event is used to indicate the +completion of the process obtaining the version information of the remote Controller +specified by the Connection_Handle event parameter. The Connection_Handle +shall be for an ACL connection. +The Version event parameter defines the specification version of the LE Controller. +The Manufacturer_Name event parameter indicates the manufacturer +of the remote Controller. The Subversion event parameter is controlled +by the manufacturer and is implementation dependent. The Subversion +event parameter defines the various revisions that each version of the Bluetooth +hardware will go through as design processes change and errors are +fixed. This allows the software to determine what Bluetooth hardware is being +used and, if necessary, to work around various bugs in the hardware. +When the Connection_Handle is associated with an LE-U logical link, the Version +event parameter shall be Link Layer VersNr parameter, the Manufacturer_Name +event parameter shall be the CompId parameter, and the Subversion +event parameter shall be the SubVersNr parameter. +(See Bluetooth Specification v.4.1, Vol. 2, Part E, 7.7.12) + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @param Version Version of the Current LMP in the remote Controller + * @param Manufacturer_Name Manufacturer Name of the remote Controller + * @param Subversion Subversion of the LMP in the remote Controller + * @retval None +*/ +void hci_read_remote_version_information_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Version, + uint16_t Manufacturer_Name, + uint16_t Subversion) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_read_remote_version_information_complete_event_rp0 *rp0 = (hci_read_remote_version_information_complete_event_rp0 *) (buffer_out + 3); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + rp0->Version = Version; + rp0->Manufacturer_Name = Manufacturer_Name; + rp0->Subversion = Subversion; + buffer_out[0] = 0x04; + buffer_out[1] = 0x0c; + buffer_out[2] = 1 + 2 + 1 + 2 + 2; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_hardware_error_event */ +/* Event len: 1 */ +/** + * @brief The Hardware Error event is used to indicate some implementation specific type of hardware failure for the controller. This event is used to notify the Host that a hardware failure has occurred in the Controller. + * @param Hardware_Code Hardware Error Event code. +Error code 0x01 and 0x02 are errors generally caused by hardware issue on the PCB; another possible cause is a slow crystal startup. +In the latter case, the HS_STARTUP_TIME in the device configuration needs to be tuned. +Error code 0x03 indicates an internal error of the protocol stack. +After this event is recommended to force device reset. + * Values: + - 0x01: Radio state error + - 0x02: Timer overrun error + - 0x03: Internal queue overflow error + * @retval None +*/ +void hci_hardware_error_event(uint8_t Hardware_Code) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_hardware_error_event_rp0 *rp0 = (hci_hardware_error_event_rp0 *) (buffer_out + 3); + rp0->Hardware_Code = Hardware_Code; + buffer_out[0] = 0x04; + buffer_out[1] = 0x10; + buffer_out[2] = 1; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_number_of_completed_packets_event */ +/* Event len: 1 + rp0->Number_of_Handles * (sizeof(Handle_Packets_Pair_Entry_t)) */ +/** + * @brief 'The Number Of Completed Packets event is used by the Controller to indicate +to the Host how many HCI Data Packets have been completed (transmitted or +flushed) for each Connection_Handle since the previous Number Of Completed +Packets event was sent to the Host. This means that the corresponding +buffer space has been freed in the Controller. Based on this information, and +the HC_Total_Num_ACL_Data_Packets and HC_Total_Num_Synchronous_- +Data_Packets return parameter of the Read_Buffer_Size command, the Host +can determine for which Connection_Handles the following HCI Data Packets +should be sent to the Controller. The Number Of Completed Packets event +must not be sent before the corresponding Connection Complete event. While +the Controller has HCI data packets in its buffer, it must keep sending the Number +Of Completed Packets event to the Host at least periodically, until it finally +reports that all the pending ACL Data Packets have been transmitted or +flushed. + * @param Number_of_Handles The number of Connection_Handles and Num_HCI_Data_Packets parameters pairs contained in this event + * @param Handle_Packets_Pair_Entry See @ref Handle_Packets_Pair_Entry_t + * @retval None +*/ +void hci_number_of_completed_packets_event(uint8_t Number_of_Handles, + Handle_Packets_Pair_Entry_t Handle_Packets_Pair_Entry[]) +{ + uint8_t buffer_out[258]; + int output_size = 0; + /* Output params */ + hci_number_of_completed_packets_event_rp0 *rp0 = (hci_number_of_completed_packets_event_rp0 *) (buffer_out + 3); + rp0->Number_of_Handles = Number_of_Handles; + { + int i; + for (i = 0; i < Number_of_Handles; i++) { + rp0->Handle_Packets_Pair_Entry[i].Connection_Handle = Handle_Packets_Pair_Entry[i].Connection_Handle; + output_size += sizeof(uint16_t); + rp0->Handle_Packets_Pair_Entry[i].HC_Num_Of_Completed_Packets = Handle_Packets_Pair_Entry[i].HC_Num_Of_Completed_Packets; + output_size += sizeof(uint16_t); + } + } + buffer_out[0] = 0x04; + buffer_out[1] = 0x13; + buffer_out[2] = 1 + output_size; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_data_buffer_overflow_event */ +/* Event len: 1 */ +/** + * @brief 'This event is used to indicate that the Controller's data buffers have been overflowed. +This can occur if the Host has sent more packets than allowed. The +Link_Type parameter is used to indicate that the overflow was caused by ACL data. + * @param Link_Type On wich type of channel overflow has occurred. + * Values: + - 0x01: ACL Buffer Overflow + * @retval None +*/ +void hci_data_buffer_overflow_event(uint8_t Link_Type) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_data_buffer_overflow_event_rp0 *rp0 = (hci_data_buffer_overflow_event_rp0 *) (buffer_out + 3); + rp0->Link_Type = Link_Type; + buffer_out[0] = 0x04; + buffer_out[1] = 0x1a; + buffer_out[2] = 1; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_encryption_key_refresh_complete_event */ +/* Event len: 1 + 2 */ +/** + * @brief 'The Encryption Key Refresh Complete event is used to indicate to the Host +that the encryption key was refreshed on the given Connection_Handle any +time encryption is paused and then resumed. +If the Encryption Key Refresh Complete event was generated due to an +encryption pause and resume operation embedded within a change connection +link key procedure, the Encryption Key Refresh Complete event shall be sent +prior to the Change Connection Link Key Complete event. +If the Encryption Key Refresh Complete event was generated due to an +encryption pause and resume operation embedded within a role switch procedure, +the Encryption Key Refresh Complete event shall be sent prior to the +Role Change event. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle for which the command is given. + * Values: + - 0x0000 ... 0x0EFF + * @retval None +*/ +void hci_encryption_key_refresh_complete_event(uint8_t Status, + uint16_t Connection_Handle) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_encryption_key_refresh_complete_event_rp0 *rp0 = (hci_encryption_key_refresh_complete_event_rp0 *) (buffer_out + 3); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + buffer_out[0] = 0x04; + buffer_out[1] = 0x30; + buffer_out[2] = 1 + 2; + rcv_callback(buffer_out, buffer_out[2] + 3); +} + +/* hci_le_connection_complete_event */ +/* Event len: 1 + 2 + 1 + 1 + 6 + 2 + 2 + 2 + 1 */ +/** + * @brief The LE Connection Complete event indicates to both of the Hosts forming the +connection that a new connection has been created. Upon the creation of the +connection a Connection_Handle shall be assigned by the Controller, and +passed to the Host in this event. If the connection establishment fails this event +shall be provided to the Host that had issued the LE_Create_Connection command. +This event indicates to the Host which issued a LE_Create_Connection +command and received a Command Status event if the connection +establishment failed or was successful. +The Master_Clock_Accuracy parameter is only valid for a slave. On a master, +this parameter shall be set to 0x00. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Role Role of the local device in the connection. + * Values: + - 0x00: Master + - 0x01: Slave + * @param Peer_Address_Type The address type of the peer device. + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + * @param Peer_Address Public Device Address or Random Device Address of the peer +device + * @param Conn_Interval Connection interval used on this connection. +Time = N * 1.25 msec + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Master_Clock_Accuracy Master clock accuracy. Only valid for a slave. + * Values: + - 0x00: 500 ppm + - 0x01: 250 ppm + - 0x02: 150 ppm + - 0x03: 100 ppm + - 0x04: 75 ppm + - 0x05: 50 ppm + - 0x06: 30 ppm + - 0x07: 20 ppm + * @retval None +*/ +void hci_le_connection_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Role, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint16_t Conn_Interval, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint8_t Master_Clock_Accuracy) +{ + uint8_t buffer_out[258]; + // Output params + hci_le_connection_complete_event_rp0 *rp0 = (hci_le_connection_complete_event_rp0 *) (buffer_out + 4); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + rp0->Role = Role; + rp0->Peer_Address_Type = Peer_Address_Type; + Osal_MemCpy((void *) rp0->Peer_Address,(const void *) Peer_Address, 6); + rp0->Conn_Interval = Conn_Interval; + rp0->Conn_Latency = Conn_Latency; + rp0->Supervision_Timeout = Supervision_Timeout; + rp0->Master_Clock_Accuracy = Master_Clock_Accuracy; + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + 2 + 1 + 1 + 6 + 2 + 2 + 2 + 1 + 1; + buffer_out[3] = 0x01; + rcv_callback(buffer_out, buffer_out[2] + 3); +} + +/* hci_le_advertising_report_event */ +/* Event len: 1 + rp0->Num_Reports * (sizeof(Advertising_Report_t)) */ +/** + * @brief The LE Advertising Report event indicates that a Bluetooth device or multiple +Bluetooth devices have responded to an active scan or received some information +during a passive scan. The Controller may queue these advertising reports +and send information from multiple devices in one LE Advertising Report event. + * @param Num_Reports Number of responses in this event. + * Values: + - 0x01 + * @param Advertising_Report See @ref Advertising_Report_t + * @retval None +*/ +void hci_le_advertising_report_event(uint8_t Num_Reports, + Advertising_Report_t Advertising_Report[]) +{ + uint8_t buffer_out[258]; + int output_size = 0; + /* Output params */ + hci_le_advertising_report_event_rp0 *rp0 = (hci_le_advertising_report_event_rp0 *) (buffer_out + 4); + rp0->Num_Reports = Num_Reports; + { + int i; + for (i = 0; i < Num_Reports; i++) { + hci_le_advertising_report_event_rp0 *rp0_tmp = (hci_le_advertising_report_event_rp0 *) (((uint8_t *) rp0) + output_size); + rp0_tmp->Advertising_Report[0].Event_Type = Advertising_Report[i].Event_Type; + output_size += sizeof(uint8_t); + rp0_tmp->Advertising_Report[0].Address_Type = Advertising_Report[i].Address_Type; + output_size += sizeof(uint8_t); + Osal_MemCpy((void *) &rp0_tmp->Advertising_Report[0].Address, (const void *) Advertising_Report[i].Address, 6); + output_size += 6; + rp0_tmp->Advertising_Report[0].Length_Data = Advertising_Report[i].Length_Data; + output_size += sizeof(uint8_t); + Osal_MemCpy((void *) &rp0_tmp->Advertising_Report[0].Data, (const void *) Advertising_Report[i].Data, Advertising_Report[i].Length_Data); + output_size += Advertising_Report[i].Length_Data; + Osal_MemCpy((void *) &rp0_tmp->Advertising_Report[0].Data[Advertising_Report[i].Length_Data], (const void *) &Advertising_Report[i].RSSI, 1); + output_size += 1; + } + } + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + output_size + 1; + buffer_out[3] = 0x02; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_connection_update_complete_event */ +/* Event len: 1 + 2 + 2 + 2 + 2 */ +/** + * @brief The LE Connection Update Complete event is used to indicate that the Controller +process to update the connection has completed. +On a slave, if no connection parameters are updated, then this event shall not be issued. +On a master, this event shall be issued if the Connection_Update command was sent. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Conn_Interval Connection interval used on this connection. +Time = N * 1.25 msec + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @retval None +*/ +void hci_le_connection_update_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint16_t Conn_Interval, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_connection_update_complete_event_rp0 *rp0 = (hci_le_connection_update_complete_event_rp0 *) (buffer_out + 4); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + rp0->Conn_Interval = Conn_Interval; + rp0->Conn_Latency = Conn_Latency; + rp0->Supervision_Timeout = Supervision_Timeout; + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + 2 + 2 + 2 + 2 + 1; + buffer_out[3] = 0x03; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_read_remote_used_features_complete_event */ +/* Event len: 1 + 2 + 8 */ +/** + * @brief The LE Read Remote Used Features Complete event is used to indicate the +completion of the process of the Controller obtaining the used features of the +remote Bluetooth device specified by the Connection_Handle event parameter. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param LE_Features Bit Mask List of used LE features. For details see LE Link Layer specification. + * @retval None +*/ +void hci_le_read_remote_used_features_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t LE_Features[8]) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_read_remote_used_features_complete_event_rp0 *rp0 = (hci_le_read_remote_used_features_complete_event_rp0 *) (buffer_out + 4); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + Osal_MemCpy((void *) rp0->LE_Features,(const void *) LE_Features, 8); + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + 2 + 8 + 1; + buffer_out[3] = 0x04; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_long_term_key_request_event */ +/* Event len: 2 + 8 + 2 */ +/** + * @brief The LE Long Term Key Request event indicates that the master device is +attempting to encrypt or re-encrypt the link and is requesting the Long Term +Key from the Host. (See [Vol 6] Part B, Section 5.1.3). + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Random_Number 64-bit random number + * @param Encrypted_Diversifier 16-bit encrypted diversifier + * @retval None +*/ +void hci_le_long_term_key_request_event(uint16_t Connection_Handle, + uint8_t Random_Number[8], + uint16_t Encrypted_Diversifier) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_long_term_key_request_event_rp0 *rp0 = (hci_le_long_term_key_request_event_rp0 *) (buffer_out + 4); + rp0->Connection_Handle = Connection_Handle; + Osal_MemCpy((void *) rp0->Random_Number,(const void *) Random_Number, 8); + rp0->Encrypted_Diversifier = Encrypted_Diversifier; + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 2 + 8 + 2 + 1; + buffer_out[3] = 0x05; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_data_length_change_event */ +/* Event len: 2 + 2 + 2 + 2 + 2 */ +/** + * @brief The LE Data Length Change event notifies the Host of a change to either the maximum Payload length or the maximum transmission time of Data Channel PDUs in either direction. The values reported are the maximum that will actually be used on the connection following the change. + * @param Connection_Handle Connection_Handle to be used to identify a connection. + * @param MaxTxOctets The maximum number of payload octets in a Link Layer Data Channel PDU that the local Controller will send on this connection (connEffectiveMaxTxOctets defined in [Vol 6] Part B, Section 4.5.10). +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param MaxTxTime The maximum time that the local Controller will take to send a Link Layer Data Channel PDU on this connection (connEffectiveMaxTx-Time defined in [Vol 6] Part B, Section 4.5.10). +Range 0x0148-0x0848 (0x0000 - 0x0127 and 0x0849 - 0xFFFF +Reserved for future use) + * @param MaxRxOctets The maximum number of payload octets in a Link Layer Data Channel PDU that the local controller expects to receive on this connection (connEfectiveMaxRxOctets defined in [Vol 6] Part B, Section 4.5.10). +Range 0x001B-0x00FB (0x0000 - 0x001A and 0x00FC - 0xFFFF Reserved for future use) + * @param MaxRxTime The maximum time that the local Controller expects to take to receive a Link Layer Data Channel PDU on this connection (connEffectiveMax-RxTime defined in [Vol 6] Part B, Section 4.5.10). +Range 0x0148-0x0848 (0x0000 - 0x0127 and 0x0849 - 0xFFFF Reserved for future use) + * @retval None +*/ +void hci_le_data_length_change_event(uint16_t Connection_Handle, + uint16_t MaxTxOctets, + uint16_t MaxTxTime, + uint16_t MaxRxOctets, + uint16_t MaxRxTime) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_data_length_change_event_rp0 *rp0 = (hci_le_data_length_change_event_rp0 *) (buffer_out + 4); + rp0->Connection_Handle = Connection_Handle; + rp0->MaxTxOctets = MaxTxOctets; + rp0->MaxTxTime = MaxTxTime; + rp0->MaxRxOctets = MaxRxOctets; + rp0->MaxRxTime = MaxRxTime; + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 2 + 2 + 2 + 2 + 2 + 1; + buffer_out[3] = 0x07; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_read_local_p256_public_key_complete_event */ +/* Event len: 1 + 64 */ +/** + * @brief This event is generated when local P-256 key generation is complete. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Local_P256_Public_Key Local P-256 public key. + * @retval None +*/ +void hci_le_read_local_p256_public_key_complete_event(uint8_t Status, + uint8_t Local_P256_Public_Key[64]) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_read_local_p256_public_key_complete_event_rp0 *rp0 = (hci_le_read_local_p256_public_key_complete_event_rp0 *) (buffer_out + 4); + rp0->Status = Status; + Osal_MemCpy((void *) rp0->Local_P256_Public_Key,(const void *) Local_P256_Public_Key, 64); + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + 64 + 1; + buffer_out[3] = 0x08; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_generate_dhkey_complete_event */ +/* Event len: 1 + 32 */ +/** + * @brief This event indicates that LE Diffie Hellman key generation has been completed +by the Controller. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param DHKey Diffie Hellman Key + * @retval None +*/ +void hci_le_generate_dhkey_complete_event(uint8_t Status, + uint8_t DHKey[32]) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_generate_dhkey_complete_event_rp0 *rp0 = (hci_le_generate_dhkey_complete_event_rp0 *) (buffer_out + 4); + rp0->Status = Status; + Osal_MemCpy((void *) rp0->DHKey,(const void *) DHKey, 32); + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + 32 + 1; + buffer_out[3] = 0x09; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_enhanced_connection_complete_event */ +/* Event len: 1 + 2 + 1 + 1 + 6 + 6 + 6 + 2 + 2 + 2 + 1 */ +/** + * @brief The LE Enhanced Connection Complete event indicates to both of the Hosts +forming the connection that a new connection has been created. Upon the +creation of the connection a Connection_Handle shall be assigned by the +Controller, and passed to the Host in this event. If the connection establishment +fails, this event shall be provided to the Host that had issued the +LE_Create_Connection command. +If this event is unmasked and LE Connection Complete event is unmasked, +only the LE Enhanced Connection Complete event is sent when a new +connection has been completed. +This event indicates to the Host that issued a LE_Create_Connection +command and received a Command Status event if the connection +establishment failed or was successful. +The Master_Clock_Accuracy parameter is only valid for a slave. On a master, +this parameter shall be set to 0x00. + * @param Status For standard error codes see Bluetooth specification, Vol. 2, part D. For proprietary error code refer to Error codes section + * @param Connection_Handle Connection handle to be used to identify the connection with the peer device. + * Values: + - 0x0000 ... 0x0EFF + * @param Role Role of the local device in the connection. + * Values: + - 0x00: Master + - 0x01: Slave + * @param Peer_Address_Type 0x00 Public Device Address +0x01 Random Device Address +0x02 Public Identity Address (Corresponds to Resolved Private Address) +0x03 Random (Static) Identity Address (Corresponds to Resolved Private Address) + * Values: + - 0x00: Public Device Address + - 0x01: Random Device Address + - 0x02: Public Identity Address + - 0x03: Random (Static) Identity Address + * @param Peer_Address Public Device Address, Random Device Address, Public Identity +Address or Random (static) Identity Address of the device to be connected. + * @param Local_Resolvable_Private_Address Resolvable Private Address being used by the local device for this connection. +This is only valid when the Own_Address_Type is set to 0x02 or 0x03. For other Own_Address_Type values, +the Controller shall return all zeros. + * @param Peer_Resolvable_Private_Address Resolvable Private Address being used by the peer device for this connection. +This is only valid for Peer_Address_Type 0x02 and 0x03. For +other Peer_Address_Type values, the Controller shall return all zeros. + * @param Conn_Interval Connection interval used on this connection. +Time = N * 1.25 msec + * Values: + - 0x0006 (7.50 ms) ... 0x0C80 (4000.00 ms) + * @param Conn_Latency Slave latency for the connection in number of connection events. + * Values: + - 0x0000 ... 0x01F3 + * @param Supervision_Timeout Supervision timeout for the LE Link. +It shall be a multiple of 10 ms and larger than (1 + connSlaveLatency) * connInterval * 2. +Time = N * 10 msec. + * Values: + - 0x000A (100 ms) ... 0x0C80 (32000 ms) + * @param Master_Clock_Accuracy Master clock accuracy. Only valid for a slave. + * Values: + - 0x00: 500 ppm + - 0x01: 250 ppm + - 0x02: 150 ppm + - 0x03: 100 ppm + - 0x04: 75 ppm + - 0x05: 50 ppm + - 0x06: 30 ppm + - 0x07: 20 ppm + * @retval None +*/ +void hci_le_enhanced_connection_complete_event(uint8_t Status, + uint16_t Connection_Handle, + uint8_t Role, + uint8_t Peer_Address_Type, + uint8_t Peer_Address[6], + uint8_t Local_Resolvable_Private_Address[6], + uint8_t Peer_Resolvable_Private_Address[6], + uint16_t Conn_Interval, + uint16_t Conn_Latency, + uint16_t Supervision_Timeout, + uint8_t Master_Clock_Accuracy) +{ + uint8_t buffer_out[258]; + /* Output params */ + hci_le_enhanced_connection_complete_event_rp0 *rp0 = (hci_le_enhanced_connection_complete_event_rp0 *) (buffer_out + 4); + rp0->Status = Status; + rp0->Connection_Handle = Connection_Handle; + rp0->Role = Role; + rp0->Peer_Address_Type = Peer_Address_Type; + Osal_MemCpy((void *) rp0->Peer_Address,(const void *) Peer_Address, 6); + Osal_MemCpy((void *) rp0->Local_Resolvable_Private_Address,(const void *) Local_Resolvable_Private_Address, 6); + Osal_MemCpy((void *) rp0->Peer_Resolvable_Private_Address,(const void *) Peer_Resolvable_Private_Address, 6); + rp0->Conn_Interval = Conn_Interval; + rp0->Conn_Latency = Conn_Latency; + rp0->Supervision_Timeout = Supervision_Timeout; + rp0->Master_Clock_Accuracy = Master_Clock_Accuracy; + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + 2 + 1 + 1 + 6 + 6 + 6 + 2 + 2 + 2 + 1 + 1; + buffer_out[3] = 0x0a; + rcv_callback(buffer_out, buffer_out[2] + 3); +} +/* hci_le_direct_advertising_report_event */ +/* Event len: 1 + rp0->Num_Reports * (sizeof(Direct_Advertising_Report_t)) */ +/** + * @brief The LE Direct Advertising Report event indicates that directed advertisements +have been received where the advertiser is using a resolvable private address +for the InitA field in the ADV_DIRECT_IND PDU and the +Scanning_Filter_Policy is equal to 0x02 or 0x03, see HCI_LE_Set_Scan_Parameters. +Direct_Address_Type and Direct_Addres is the address the directed +advertisements are being directed to. Address_Type and Address is the +address of the advertiser sending the directed advertisements. + * @param Num_Reports Number of responses in this event. + * Values: + - 0x01 + * @param Direct_Advertising_Report See @ref Direct_Advertising_Report_t + * @retval None +*/ +void hci_le_direct_advertising_report_event(uint8_t Num_Reports, + Direct_Advertising_Report_t Direct_Advertising_Report[]) +{ + uint8_t buffer_out[258]; + int output_size = 0; + /* Output params */ + hci_le_direct_advertising_report_event_rp0 *rp0 = (hci_le_direct_advertising_report_event_rp0 *) (buffer_out + 4); + rp0->Num_Reports = Num_Reports; + { + int i; + for (i = 0; i < Num_Reports; i++) { + rp0->Direct_Advertising_Report[i].Event_Type = Direct_Advertising_Report[i].Event_Type; + output_size += sizeof(uint8_t); + rp0->Direct_Advertising_Report[i].Address_Type = Direct_Advertising_Report[i].Address_Type; + output_size += sizeof(uint8_t); + Osal_MemCpy((void *) &rp0->Direct_Advertising_Report[i].Address, (const void *) Direct_Advertising_Report[i].Address, 6); + output_size += 6; + rp0->Direct_Advertising_Report[i].Direct_Address_Type = Direct_Advertising_Report[i].Direct_Address_Type; + output_size += sizeof(uint8_t); + Osal_MemCpy((void *) &rp0->Direct_Advertising_Report[i].Direct_Address, (const void *) Direct_Advertising_Report[i].Direct_Address, 6); + output_size += 6; + rp0->Direct_Advertising_Report[i].RSSI = Direct_Advertising_Report[i].RSSI; + output_size += sizeof(uint8_t); + } + } + buffer_out[0] = 0x04; + buffer_out[1] = 0x3E; + buffer_out[2] = 1 + output_size + 1; + buffer_out[3] = 0x0b; + rcv_callback(buffer_out, buffer_out[2] + 3); +} + +/* Command len: 1 + 1 + cp0->Length * (sizeof(uint8_t)) */ +/* Response len: 1 */ +uint16_t aci_hal_write_config_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + aci_hal_write_config_data_cp0 *cp0 = (aci_hal_write_config_data_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 1; + /* Output params */ + uint8_t *status = (uint8_t *) (buffer_out + 6); + + if (buffer_out_max_length < (1 + 6)) { return 0; } + *status = aci_hal_write_config_data(cp0->Offset /* 1 */, + cp0->Length /* 1 */, + cp0->Value /* cp0->Length * (sizeof(uint8_t)) */); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0c; + buffer_out[5] = 0xfc; + return (output_size + 6); +} + +/* Command len: 1 */ +/* Response len: 1 + 1 + rp0->Data_Length * (sizeof(uint8_t)) */ +uint16_t aci_hal_read_config_data_process(uint8_t *buffer_in, uint16_t buffer_in_length, uint8_t *buffer_out, uint16_t buffer_out_max_length) +{ + /* Input params */ + aci_hal_read_config_data_cp0 *cp0 = (aci_hal_read_config_data_cp0 *)(buffer_in + 1 + (0)); + + int output_size = 0; + /* Output params */ + aci_hal_read_config_data_rp0 *rp0 = (aci_hal_read_config_data_rp0 *) (buffer_out + 6); + uint8_t Data_Length = 0; + uint8_t Data[HCI_MAX_PAYLOAD_SIZE/sizeof(uint8_t)]; + + if (buffer_out_max_length < (1 + 6)) { return 0; } + rp0->Status = aci_hal_read_config_data(cp0->Offset /* 1 */, + &Data_Length, + Data); + output_size += 1; + if (buffer_out_max_length < (output_size + (1) + 6)) { return 0; } + rp0->Data_Length = Data_Length; + output_size += 1; + if (buffer_out_max_length < (output_size + (rp0->Data_Length * (sizeof(uint8_t))) + 6)) { return 0; } + Osal_MemCpy((void *) rp0->Data,(const void *) Data, rp0->Data_Length * (sizeof(uint8_t))); + output_size += rp0->Data_Length * (sizeof(uint8_t)); + buffer_out[0] = 0x04; + buffer_out[1] = 0x0E; + buffer_out[2] = output_size + 3; + buffer_out[3] = 0x01; + buffer_out[4] = 0x0d; + buffer_out[5] = 0xfc; + return (output_size + 6); +} + +tBleStatus hci_rx_acl_data_event(uint16_t connHandle, uint8_t pb_flag, uint8_t bc_flag, uint16_t dataLen, uint8_t* pduData) +{ + uint8_t buffer_out[251+5]; + + buffer_out[0] = 0x02; + buffer_out[1] = connHandle & 0xFF; + buffer_out[2] = (connHandle >> 8 & 0x0F) | (pb_flag << 4) | (bc_flag << 6) ; + Osal_MemCpy(buffer_out+3,&dataLen, 2); + Osal_MemCpy(buffer_out+5, pduData, dataLen); + rcv_callback(buffer_out, dataLen+2+2+1); + return 0; +} diff --git a/targets/TARGET_STMBLUE/LICENSE-SLA0068.txt b/targets/TARGET_STMBLUE/LICENSE-SLA0068.txt new file mode 100644 index 00000000000..417e03d9dd1 --- /dev/null +++ b/targets/TARGET_STMBLUE/LICENSE-SLA0068.txt @@ -0,0 +1,322 @@ +SLA0068 +Software license agreement +PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS +IMPORTANT-READ CAREFULLY: +This Production Limited License Agreement ("PLLA") for ST materials is made between you on behalf of +yourself or on behalf of any entity by which you are employed or engaged (collectively referred to in this +PLLA as "You" or “Licensee”) and STMicroelectronics International NV, a company incorporated under +the laws of the Netherlands acting for the purpose of this PLLA through its Swiss branch located at 39, +Chemin du Champ des Filles, 1228 Plan-les-Ouates, Geneva, Switzerland (hereinafter “ST”). Affiliates +shall mean any corporation, partnership, or other entity that, directly or indirectly, owns, is owned by, or +is under common ownership with ST, for so long as such ownership exists. For the purposes of the +foregoing, "own", "owned," or "ownership" shall mean ownership of more than fifty percent (50%) of the +stock or other equity interests entitled to vote for the election of directors or an equivalent governing +body. +The ST materials licensed under this PLLA shall mean the software made available by ST and/or its +Affiliates upon agreeing to this PLLA, including any associated Documentation (collectively the +“Licensed Materials”). Documentation shall mean and include any comments, annotations, instructions, +manuals, and other materials, whether in printed or electronic form, including without limitation +installation manuals, user’s guides, and programmer guides, related to any software made available +under this PLLA. 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RESTRICTIONS AND ADDITIONAL OBLIGATIONS +Unless otherwise expressly stipulated under Article 1, You shall not, and shall not permit any third party +to: (i) copy, reproduce or duplicate the Licensed Materials; (ii) translate, modify, adapt, decompile, +disassemble or reverse engineer and make derivative works of all or any portion of the Licensed +Materials; (iii) rent, disclose, publish, sell, assign, lease, lend, sublicense, market, transfer, distribute or +otherwise provide third parties access to (any portion of) the Licensed Materials for any purpose; (iv) +attempt to derive the source code, algorithmic nature or structure of any object code portions of the +Licensed Materials; (v) use the Licensed Materials to create any product that competes with the +Licensed Materials or ST Products; (vi) remove or circumvent any protection or other restrictive +technology mechanism of the Licensed Materials or ST Products; (vii) disclose the results of the +Licensed Materials’ performance benchmarks to any third party; or (viii) otherwise use (any portion of) +the Licensed Materials in any manner not expressly authorized by this PLLA. +Other than the limited expressed license granted to You under Article 1 herein, no other rights or +licenses are granted, or implied by estoppel or otherwise, under any intellectual property rights of ST +and/or its Affiliates or any intellectual property of a third-party residing in the Licensed Materials or any +other confidential information furnished by ST and its Affiliates, including (i) for the combination of such +Licensed Materials or other confidential information with one or more other items (including items +acquired from ST and/or its Affiliates) even if such items have no substantial use other than as part of +such combination (ii) with respect to any trademark, trade or brand name, a corporate name of ST +and/or its Affiliates, or any other name or mark, or contraction abbreviation or simulation thereof, (iii) +under any intellectual property rights covering any standard set by a standard setting body and any de +facto standards. + +2/7 + +DocID029125 Rev 1 + +SLA0068 + +ST and its Affiliates have no obligation to provide You with maintenance, support or updates for the +Licensed Materials. Nothing in this PLLA will be construed as: (i) a warranty or representation by ST and +its Affiliates to maintain production of any ST software or ST Product with which the Licensed Materials +may be used in any manner; and (ii) a commitment from ST and its Affiliates to bring or prosecute +actions against third-parties for infringement. +You shall limit access and use of the Licensed Materials to You and those individuals who may be +employed by You who have a need to access the Licensed Materials for the purpose of this PLLA and +provided that You shall ensure that such individuals shall comply with the provisions of this PLLA, and +except as expressly permitted under Article 1 or as otherwise expressly agreed in writing by ST, You +shall not allow any third-party to use the Licensed Materials, You shall be liable towards ST for any +damages due to a failure by such third-party(ies) to comply with the provisions of this PLLA. + +3. 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DISCLAIMER OF WARRANTY +YOU ACKNOWLEDGE THAT THE LICENSED MATERIALS AND ANY AND ALL PARTS THEREOF +ARE PROVIDED “AS IS”. ST AND ITS AFFILIATE MAKE NO REPRESENTATIONS OR WARRANTIES +WITH RESPECT TO THE LICENSED MATERIALS AND OR PARTS THEREOF WHETHER + +DocID029125 Rev 1 + +3/7 + +SLA0068 + +EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO, IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. SPECIFICALLY, WITHOUT +LIMITING THE GENERALITY OF THE FOREGOING, ST AND ITS AFFILIATES MAKE NO +REPRESENTATION OR WARRANTY THAT (I) THE USE AND DISTRIBUTION OF THE LICENSED +MATERIALS AND OR PARTS THEREOF WILL BE UNINTERRUPTED OR ERROR FREE, AND OR +(II) ANY USE AND DISTRIBUTION OF THE LICENSED MATERIALS AND OR PARTS THEREOF, +WHETHER INTEGRATED INTO OTHER EQUIPMENT OR NOT, ARE FREE FROM INFRINGEMENT +OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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Such Open Source Software is supplied to You under the applicable Open Source Terms and +is not subject to the terms of this PLLA to the extent the terms of this PLLA are in conflict with such +applicable Open Source Terms. +Except for Open Source Software, You have no rights under this PLLA to, and may not under any +circumstances use the Licensed Materials or any parts thereof such that they become subject to any +Open Source Terms. These actions include but are not limited to combining the Licensed Materials by +means of incorporation or linking or otherwise. +For the purpose of this PLLA, “Open Source Terms” shall mean any open source license which requires +as part of distribution of software that the source code of such software is distributed therewith, or open +source license that complies with the Open Source Definition specified at www.opensource.org and any +other comparable open source license such as for example GNU General Public License (GPL), Eclipse +Public License (EPL), Apache Software License, BSD license and MIT license. “Open Source Software” +shall mean any software that is licensed or distributed under Open Source Terms as specified in the +Licensed Materials. + +7. COMPLIANCE +You agree not to use the Licensed Materials in violation of any applicable law, statute, ordinance or +other regulation or any obligation by which You are bound. You agree to comply with all applicable laws +and regulations affecting the use of the Licensed Materials. Specifically but without limiting the +generality of the foregoing, You acknowledge that the Licensed Materials are subject to export controls +restrictions and You agree to comply with any applicable export control law or regulation including but +not limited to the European export regulations and US similar regulations, and to obtain any necessary +export license or other documentation prior to exportation or re-exportation of the Licensed Materials. +Some Licensed Materials may (i) require licenses from third parties claiming intellectual property rights +covering use or implementation of the Licensed Materials or (ii) be based on industry recognized +standards or software programs published by industry recognized standards bodies and certain third +parties may claim to own intellectual property rights that cover implementation or use of those +standards. You agree that You are responsible for obtaining any such license which may be needed, +and no such license is provided by ST or its Affiliates. + +4/7 + +DocID029125 Rev 1 + +SLA0068 + +You shall be responsible for the due and proper compliance with the terms and conditions of this PLLA +by your customers and shall be liable to ST for any and all damages incurred by ST, its Affiliates and its +suppliers and licensors in connection with any such customers’ non-compliance therewith. + +8. DISCLAIMER OF DAMAGES +IN NO EVENT SHALL ST AND ITS AFFILIATES BE LIABLE TO THE LICENSEE AND ITS +CUSTOMERS FOR ANY INDIRECT, INCIDENTAL, PUNITIVE, SPECIAL OR CONSEQUENTIAL +DAMAGES, LOST PROFITS OR LOST SAVINGS, LOSS OF BARGAIN OR OPPORTUNITY, +PROFESSIONAL FEES OR EXPENSES, BUSINESS INTERRUPTION, LOST REVENUES OR SALES, +DAMAGE TO PRODUCT OR EQUIPMENT OR TO FACILITIES, COSTS OF SUBSTITUTE PRODUCT, +FACILITIES OR SERVICES, REWORK CHARGES, COSTS ASSOCIATED WITH DOWN TIME, LOSS +OF GOODWILL, LOSS OF DATA OR FOR ANY DAMAGES COSTS OR EXPENSES ASSOCIATED +WITH WARRANTY OR INTELLECTUAL PROPERTY INFRINGEMENT CLAIMS, WHETHER +FORESEEABLE OR UNFORESEEABLE AND WHETHER OR NOT SUCH DAMAGES ARE BASED +ON WARRANTY, CONTRACT OR ANY OTHER LEGAL THEORY – EVEN IF LICENSEE HAS BEEN +ADVISED, OR IS AWARE, OF THE POSSIBILITY OF SUCH DAMAGES ARISING FROM OR IN +CONNECTION WITH THIS PLLA. ST AND ITS AFFILIATES AGGREGATE AND CUMULATIVE +LIABILITY UNDER THIS PLLA SHALL NOT EXCEED 100 USD (ONE HUNDRED USD). THE +LIMITATIONS SET FORTH IN THIS ARTICLE 8 SHALL ONLY APPLY TO THE MAXIMUM EXTENT +PERMITTED BY APPLICABLE LAW. + +9. TERM AND TERMINATION +This PLLA shall be valid from acceptance by You of this PLLA for an unlimited period of time until +terminated by either ST or Licensee upon one (1) month prior written notice to the other. +Notwithstanding the foregoing, Licensee may terminate this PLLA at any time by destroying all Licensed +Materials, Documentation and other Confidential Information or by returning those to ST. ST may +terminate this PLLA at any time if (i) You fail to comply with the terms and conditions of this PLLA, or (ii) +You file litigation against ST or its Affiliates, (iii) ST or its Affiliates receive notice of any claim, suit or +proceeding that alleges that the Licensed Materials or Your use or distribution of the Licensed Materials +infringes any third-party intellectual property rights or (iv) to the extent permitted by laws, a voluntary or +involuntary petition in bankruptcy or winding up is filed against Licensee, any proceedings in insolvency +or bankruptcy are instituted against Licensee, a trustee or receiver is appointed over Licensee, or any +assignment is made for the benefit of creditors of Licensee. Upon termination You shall delete, destroy, +or return to ST all Licensed Materials in your possession and You shall stop using the Licensed +Materials for any purpose whatsoever. The rights and obligations under Articles from 2 to 11 will survive +the termination of this PLLA. However the right to use the Licensed Materials incorporated in a Licensee +Product as per Article 1 will survive with respect to Licensee Products sold, licensed or distributed +before the termination of this PLLA. + +10. MISCELLANEOUS +If a court or agency of competent jurisdiction holds any term of this PLLA invalid, illegal, or +unenforceable for any reason, the remainder of this PLLA shall be valid and enforceable and You and +ST shall discuss in good faith a substitute, valid, enforceable provision which most nearly effects the +parties intent in entering into this PLLA. +The failure by ST to enforce any provisions of this PLLA or to exercise any right in respect thereto shall +not be construed as constituting a waiver of its rights thereof. +No agency, joint venture, partnership or other business organisation shall be created or be construed as +being created by reason of this PLLA. You will not have the right or authority to, and shall not, assume +or create any obligation of any nature whatsoever on behalf of ST and its Affiliates or bind ST and its +Affiliates in any respect whatsoever. You and ST are independent parties and nothing in this PLLA shall +be construed as making You an employee, agent or legal representative of ST. + +DocID029125 Rev 1 + +5/7 + +SLA0068 + +This PLLA contains the entire and sole agreement between You and ST on the subject matter of this +PLLA, and supersedes all representations, undertakings and agreements previously made between You +and ST and/or its Affiliates and shall prevail over the terms and conditions set forth in any document +from You with respect to the subject matter of this PLLA. +Any amendment to this PLLA shall be agreed in writing and duly signed by You and ST or signed solely +by You on the format proposed by ST and shall make reference to this PLLA. + +11. APPLICABLE LAW +This PLLA is governed by the laws of Switzerland, without regard to its conflict of law rules. All disputes +or questions arising out of or in connection with this PLLA shall be finally settled by the competent +courts of Geneva, Switzerland. Notwithstanding the aforesaid, nothing in this PLLA shall prevent ST +from seeking any interim or final injunctive or equitable relief by a court of competent jurisdiction. + +6/7 + +DocID029125 Rev 1 + +SLA0068 + +Revision history +Table 1: Document revision history +Date + +Version + +17-Mar-2016 + +1 + +Changes +Initial release. + +DocID029125 Rev 1 + +7/7 \ No newline at end of file diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_adc.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_adc.h new file mode 100644 index 00000000000..bd71922ff44 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_adc.h @@ -0,0 +1,248 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_ADC_H +#define BLUENRG1_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup ADC_Peripheral ADC Peripheral + * @{ + */ + +/** @defgroup ADC_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC initialization + */ +typedef struct { + uint8_t ADC_OSR; /*!< Specifies the decimation rate. + This parameter can be a value of @ref ADC_OSR */ + + uint8_t ADC_Input; /*!< Specifies the input used for the conversion. + This parameter can be a value of @ref ADC_Input */ + + uint8_t ADC_ConversionMode; /*!< Specifies the conversion mode. + This parameter can be a value of @ref ADC_ConversionMode */ + + uint8_t ADC_Attenuation; /*!< Specifies the attenuation. + This parameter can be a value of @ref ADC_Attenuation */ + + uint8_t ADC_ReferenceVoltage; /*!< Specifies the ADC reference voltage. + This parameter can be a value of @ref ADC_ReferenceVoltage */ +} ADC_InitType; + +/** + * @} + */ + + + +/** @defgroup ADC_Exported_Constants Exported Constants + * @{ + */ + + +/** @defgroup ADC_Decimation_Rate_Definitions Decimation Rate Definitions + * @{ + */ +#define ADC_OSR_200 ((uint8_t)0x00) /* Recommended value for DC signals */ +#define ADC_OSR_100 ((uint8_t)0x01) +#define ADC_OSR_64 ((uint8_t)0x02) +#define ADC_OSR_32 ((uint8_t)0x03) + +#define IS_ADC_OSR(OSR) (((OSR) == ADC_OSR_200) || \ + ((OSR) == ADC_OSR_100) || \ + ((OSR) == ADC_OSR_64) || \ + ((OSR) == ADC_OSR_32)) +/** + * @} + */ + + +/** @defgroup ADC_Input_Definitions Input Definitions + * @{ + */ +#define ADC_Input_None ((uint8_t)0x00) +#define ADC_Input_AdcPin2 ((uint8_t)0x01) /* Single ended input from ADC2 pin */ +#define ADC_Input_AdcPin1 ((uint8_t)0x02) /* Single ended input from ADC1 pin */ +#define ADC_Input_AdcPin12 ((uint8_t)0x03) /* Differential input */ +#define ADC_Input_TempSensor ((uint8_t)0x04) /* Temperature sensor */ +#define ADC_Input_BattSensor ((uint8_t)0x05) /* Internal battery detector */ +#define ADC_Input_Internal0V60V6 ((uint8_t)0x06) /* Test input */ +#define ADC_Input_Internal1V20V0 ((uint8_t)0x07) /* Test input */ +#define ADC_Input_Microphone ((uint8_t)0x0F) /* Microphone mode */ + +#define IS_ADC_INPUT(INPUT) (((INPUT) == ADC_Input_None) || \ + ((INPUT) == ADC_Input_AdcPin1) || \ + ((INPUT) == ADC_Input_AdcPin2) || \ + ((INPUT) == ADC_Input_AdcPin12) || \ + ((INPUT) == ADC_Input_TempSensor) || \ + ((INPUT) == ADC_Input_BattSensor) || \ + ((INPUT) == ADC_Input_Internal0V60V6) || \ + ((INPUT) == ADC_Input_Internal1V20V0) || \ + ((INPUT) == ADC_Input_Microphone)) + +/** + * @} + */ + + +/** @defgroup ADC_Conversion_Mode_Definitions Conversion Mode Definitions + * @{ + */ +#define ADC_ConversionMode_Single ((uint8_t)0x00) + +/* The user must discards the first 10 converted samples in continuous mode if the SKIP bit is 0. + * The user must discards the first 3 converted samples in continuous mode if the SKIP bit is 1. */ +#define ADC_ConversionMode_Continuous ((uint8_t)0x08) + +#define IS_ADC_CONVERSIONMODE(CONVERSIONMODE) (((CONVERSIONMODE) == ADC_ConversionMode_Single) || \ + ((CONVERSIONMODE) == ADC_ConversionMode_Continuous)) +/** + * @} + */ + + + +/** @defgroup ADC_Attenuation_Definitions Attenuation Definitions + * @{ + */ +#define ADC_Attenuation_0dB ((uint8_t)0x00) +#define ADC_Attenuation_6dB02 ((uint8_t)0x01) +#define ADC_Attenuation_9dB54 ((uint8_t)0x02) + +#define IS_ADC_ATTENUATION(ATTENUATION) (((ATTENUATION) == ADC_Attenuation_0dB) || \ + ((ATTENUATION) == ADC_Attenuation_6dB02) || \ + ((ATTENUATION) == ADC_Attenuation_9dB54)) +/** + * @} + */ + + +/** @defgroup ADC_Reference_Voltage_Definitions Reference Voltage Definitions + * @{ + */ + +#define ADC_ReferenceVoltage_0V6 ((uint8_t)0x02) /* Optimal setting */ +#define ADC_ReferenceVoltage_0V0 ((uint8_t)0x00) /* Default value: not recommended */ + +#define IS_ADC_REFERENCEVOLTAGE(REFERENCEVOLTAGE) (((REFERENCEVOLTAGE) == ADC_ReferenceVoltage_0V6) || \ + ((REFERENCEVOLTAGE) == ADC_ReferenceVoltage_0V0)) +/** + * @} + */ + + +/** @defgroup ADC_Mic_Frequency_Definitions Mic Frequency Definitions + * @{ + */ +#define ADC_MIC_800KHZ ((uint8_t)0x00) /*!< Enable the 800 kHz through IO0 for external MEMS microphone */ +#define ADC_MIC_1600KHZ ((uint8_t)0x01) /*!< Enable the 1.6 MHz through IO0 for external MEMS microphone */ + +#define IS_ADC_MIC_FREQ_SEL(FREQ) (((FREQ) == ADC_MIC_800KHZ) || ((FREQ) == ADC_MIC_1600KHZ)) + +/** + * @} + */ + +/** @defgroup ADC_Flags_Definitions Flags Definitions + * @{ + */ + +#define ADC_FLAG_CAL ((uint8_t)0x01) /*!< End of Calibration flag */ +#define ADC_FLAG_BUSY ((uint8_t)0x02) /*!< Busy flag */ +#define ADC_FLAG_EOC ((uint8_t)0x04) /*!< End of Conversion flag */ +#define ADC_FLAG_WDG ((uint8_t)0x08) /*!< Value within set threshold */ + +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) & 0x0F) != 0) + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup ADC_Exported_Functions Exported Functions + * @{ + */ +void ADC_Init(ADC_InitType* ADC_InitStruct); +void ADC_DeInit(void); +void ADC_StructInit(ADC_InitType* ADC_InitStruct); +void ADC_Cmd(FunctionalState NewState); +void ADC_DmaCmd(FunctionalState NewState); +void ADC_Filter(FunctionalState NewState); +void ADC_SelectInput(uint8_t AdcInput); +void ADC_Calibration(FunctionalState NewState); +void ADC_AutoOffsetUpdate(FunctionalState NewState); +void ADC_SetOffset(uint16_t Offset); +uint16_t ADC_GetOffset(void); +void ADC_ThresholdCheck(FunctionalState NewState); +void ADC_ThresholdConfig(uint32_t ThresholdLow, uint32_t ThresholdHigh); +void ADC_ConversionMode(uint8_t ConvertionMode); +void ADC_SelectFrequencyMic(uint8_t Frequency); +float ADC_GetConvertedData(uint8_t DataType, uint8_t Vref); +uint8_t ADC_GetFlags(void); +FlagStatus ADC_GetFlagStatus(uint8_t ADC_Flag); +ITStatus ADC_GetITStatus(uint8_t ADC_Flag); +void ADC_ITConfig(uint8_t ADC_Flag, FunctionalState NewState); + +float ADC_ConvertDifferentialVoltage(int16_t raw_value, uint8_t attenuation); +float ADC_ConvertSingleEndedVoltage(int16_t raw_value, uint8_t channel, uint8_t vRef, uint8_t attenuation); +float ADC_ConvertBatterySensor(int16_t raw_value, uint8_t vRef); +float ADC_ConvertTemperatureSensor(int16_t raw_value, uint8_t vRef, uint8_t attenuation); + +uint16_t ADC_GetRawData(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*BLUENRG1_ADC_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_dma.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_dma.h new file mode 100644 index 00000000000..b7df19cb8ce --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_dma.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_DMA_H +#define BLUENRG1_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup DMA_Peripheral DMA Peripheral + * @{ + */ + +/** @defgroup DMA_Exported_Types Exported Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitType; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants Exported Constants + * @{ + */ + + +/** @defgroup DMA_Data_Transfer_Direction_Definitions Data Transfer Direction Definitions + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_Incremented_Mode_Definitions Peripheral Incremented Mode Definitions + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_Memory_Incremented_Mode_Definitions Memory Incremented Mode Definitions + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_Peripheral_Data_Size_Definitions Peripheral Data Size Definitions + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_Memory_Data_Size_Definitions Memory Data Size Definitions + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_Circular_Normal_Mode_Definitions Circular Normal Mode Definitions + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_Priority_Level_Definitions Priority Level Definitions + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_Memory_To_Memory_Definitions Memory To Memory Definitions + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_Flag_Mask_Definitions Flag Mask Definitions + * @{ + */ + +#define DMA_FLAG_TC ((uint32_t)0x00000002) +#define DMA_FLAG_HT ((uint32_t)0x00000004) +#define DMA_FLAG_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_FLAG(FLAG) (((FLAG) & 0x0E) != 0) + +/** + * @} + */ + + +/** @defgroup DMA_Interrupts_Channel_Definitions Interrupts Channel Definitions + * @{ + */ + +#define DMA_FLAG_GL0 ((uint32_t)0x00000001) +#define DMA_FLAG_TC0 ((uint32_t)0x00000002) +#define DMA_FLAG_HT0 ((uint32_t)0x00000004) +#define DMA_FLAG_TE0 ((uint32_t)0x00000008) +#define DMA_FLAG_GL1 ((uint32_t)0x00000010) +#define DMA_FLAG_TC1 ((uint32_t)0x00000020) +#define DMA_FLAG_HT1 ((uint32_t)0x00000040) +#define DMA_FLAG_TE1 ((uint32_t)0x00000080) +#define DMA_FLAG_GL2 ((uint32_t)0x00000100) +#define DMA_FLAG_TC2 ((uint32_t)0x00000200) +#define DMA_FLAG_HT2 ((uint32_t)0x00000400) +#define DMA_FLAG_TE2 ((uint32_t)0x00000800) +#define DMA_FLAG_GL3 ((uint32_t)0x00001000) +#define DMA_FLAG_TC3 ((uint32_t)0x00002000) +#define DMA_FLAG_HT3 ((uint32_t)0x00004000) +#define DMA_FLAG_TE3 ((uint32_t)0x00008000) +#define DMA_FLAG_GL4 ((uint32_t)0x00010000) +#define DMA_FLAG_TC4 ((uint32_t)0x00020000) +#define DMA_FLAG_HT4 ((uint32_t)0x00040000) +#define DMA_FLAG_TE4 ((uint32_t)0x00080000) +#define DMA_FLAG_GL5 ((uint32_t)0x00100000) +#define DMA_FLAG_TC5 ((uint32_t)0x00200000) +#define DMA_FLAG_HT5 ((uint32_t)0x00400000) +#define DMA_FLAG_TE5 ((uint32_t)0x00800000) +#define DMA_FLAG_GL6 ((uint32_t)0x01000000) +#define DMA_FLAG_TC6 ((uint32_t)0x02000000) +#define DMA_FLAG_HT6 ((uint32_t)0x04000000) +#define DMA_FLAG_TE6 ((uint32_t)0x08000000) +#define DMA_FLAG_GL7 ((uint32_t)0x10000000) +#define DMA_FLAG_TC7 ((uint32_t)0x20000000) +#define DMA_FLAG_HT7 ((uint32_t)0x40000000) +#define DMA_FLAG_TE7 ((uint32_t)0x80000000) + + +#define IS_DMA_CH_FLAG(FLAG) ((FLAG) != 0x00) + + + +/** + * @} + */ + + + +/** @defgroup DMA_Interrupts_Channel_Definitions Interrupts Channel Definitions + * @{ + */ + +#define DMA_ADC_CHANNEL0 ((uint8_t)0x01) +#define DMA_ADC_CHANNEL1 ((uint8_t)0x02) +#define DMA_ADC_CHANNEL2 ((uint8_t)0x04) +#define DMA_ADC_CHANNEL3 ((uint8_t)0x08) +#define DMA_ADC_CHANNEL4 ((uint8_t)0x10) +#define DMA_ADC_CHANNEL5 ((uint8_t)0x20) +#define DMA_ADC_CHANNEL6 ((uint8_t)0x40) +#define DMA_ADC_CHANNEL7 ((uint8_t)0x80) + + +#define IS_DMA_ADC_CH(SEL) (((SEL) == DMA_ADC_CHANNEL0) || \ + ((SEL) == DMA_ADC_CHANNEL1) || \ + ((SEL) == DMA_ADC_CHANNEL2) || \ + ((SEL) == DMA_ADC_CHANNEL3) || \ + ((SEL) == DMA_ADC_CHANNEL4) || \ + ((SEL) == DMA_ADC_CHANNEL5) || \ + ((SEL) == DMA_ADC_CHANNEL6) || \ + ((SEL) == DMA_ADC_CHANNEL7)) + + + +/** + * @} + */ + + + +/** @defgroup DMA_Buffer_Size_Definitions Buffer Size Definitions + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + + +/** @defgroup DMA_Exported_Functions Exported Functions + * @{ + */ + +/* Function used to set the DMA configuration to the default reset state *****/ +void DMA_DeInit(DMA_CH_Type* DMAy_Channelx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_CH_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct); +void DMA_StructInit(DMA_InitType* DMA_InitStruct); +void DMA_Cmd(DMA_CH_Type* DMAy_Channelx, FunctionalState NewState); +void DMA_SelectAdcChannel(uint8_t DMA_AdcChannel, FunctionalState NewState); + +/* Data Counter functions *****************************************************/ +void DMA_SetCurrDataCounter(DMA_CH_Type* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_CH_Type* DMAy_Channelx); + +/* Interrupts and flags management functions **********************************/ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_Flag); +void DMA_FlagConfig(DMA_CH_Type* DMAy_Channelx, uint32_t DMA_Flag, FunctionalState NewState); +void DMA_ClearFlag(uint32_t DMA_Flag); + + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*BLUENRG1_DMA_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_flash.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_flash.h new file mode 100644 index 00000000000..206159c4f2f --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_flash.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_FLASH_H +#define BLUENRG1_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "bluenrg_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup FLASH_Peripheral FLASH Peripheral + * @{ + */ + +/** @defgroup FLASH_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Flash status enumeration + */ + +#define Flash_CMDDONE 0x01 /* Flash command done */ +#define Flash_CMDSTART 0x02 /* Flash command start */ +#define Flash_CMDERR 0x04 /* Flash command error */ +#define Flash_ILLCMD 0x08 /* Flash illegal command written */ +#define Flash_READOK 0x10 /* Flash mass read was OK */ +#define Flash_FLNREADY 0x20 /* Flash not ready (sleep) */ + +#define IS_FLASH_FLAG(FLAG) ( ((FLAG) == Flash_CMDDONE) || \ + ((FLAG) == Flash_CMDSTART) || \ + ((FLAG) == Flash_CMDERR) || \ + ((FLAG) == Flash_ILLCMD) || \ + ((FLAG) == Flash_READOK) || \ + ((FLAG) == Flash_FLNREADY) ) +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup FLASH_Size_Definitions Size Definitions + * @{ + */ + +#define FLASH_START (_MEMORY_FLASH_BEGIN_) +#define FLASH_END (_MEMORY_FLASH_END_) + +#define IS_FLASH_ADDRESS(ADDR) ( ((ADDR) >= FLASH_START) && ((ADDR) <= FLASH_END) ) + +#define N_BYTES_WORD (4) +#define N_ROWS (8) +#define N_BYTES_PAGE (_MEMORY_BYTES_PER_PAGE_) +#define N_PAGES (_MEMORY_FLASH_SIZE_/N_BYTES_PAGE) +#define N_WORDS_ROW (N_BYTES_PAGE / N_ROWS / N_BYTES_WORD) +#define N_WORDS_PAGE (N_BYTES_PAGE / N_BYTES_WORD) + +#define IS_PAGE_NUMBER(PAGE) ( (PAGE)= 1) && ((SPEED) <= 400000)) + +/** + * @} + */ + + +/** @defgroup I2C_DMA_Requests_Definition DMA Requests Definition + * @{ + */ + +#define I2C_DMAReq_Tx ((uint16_t)0x0200) +#define I2C_DMAReq_Rx ((uint16_t)0x0400) +#define IS_I2C_DMAREQ(DMAREQ) (((DMAREQ) & 0x0600) != 0) + +/** + * @} + */ + +/** @defgroup I2C_Burst_Size Burst Size + * @{ + */ + +/** This macro checks if the burst size is a valid value */ +#define IS_I2C_BURSTSIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 7)) + +/** + * @} + */ + +/** @defgroup I2C_Hold_Time Hold Time + * @{ + */ + +/** This macro checks if the hold time is a valid value */ +#define IS_I2C_HOLDTIME(TIME) ((TIME) <= 0x1FF) + +/** + * @} + */ + + +/** @defgroup I2C_Setup_Time Setup Time + * @{ + */ + +/** This macro checks if the setup time is a valid value */ +#define IS_I2C_SETUPTIME(TIME) ((TIME) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions Exported Functions + * @{ + */ +void I2C_DeInit(I2C_Type* I2Cx); +void I2C_Init(I2C_Type* I2Cx, I2C_InitType* I2C_InitStruct); +void I2C_StructInit(I2C_InitType* I2C_InitStruct); +void I2C_Cmd(I2C_Type* I2Cx, FunctionalState NewState); +void I2C_BeginTransaction(I2C_Type* I2Cx, I2C_TransactionType* tr); +void I2C_GeneralCallCmd(I2C_Type* I2Cx, FunctionalState NewState); +void I2C_FillTxFIFO(I2C_Type* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_Type* I2Cx); +void I2C_FlushTx(I2C_Type* I2Cx); +void I2C_FlushRx(I2C_Type* I2Cx); +void I2C_SetTxThreshold(I2C_Type* I2Cx, uint16_t TxThres); +void I2C_SetRxThreshold(I2C_Type* I2Cx, uint16_t RxThres); +void I2C_GenerateStopCondition(I2C_Type* I2Cx); +void I2C_SetHoldTime(I2C_Type* I2Cx, uint16_t I2C_HoldTime); +void I2C_SetHoldTimeStartCondition(I2C_Type* I2Cx, uint16_t I2C_HoldTime); +void I2C_SetSetupTimeStartCondition(I2C_Type* I2Cx, uint16_t I2C_SetupTime); +I2C_OpStatus I2C_WaitFlushRx(I2C_Type* I2Cx); +I2C_OpStatus I2C_WaitFlushTx(I2C_Type* I2Cx); + +void I2C_ITConfig(I2C_Type* I2Cx, uint32_t I2C_IT, FunctionalState NewState); +ITStatus I2C_GetITStatus(I2C_Type* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_Type* I2Cx, uint32_t I2C_IT); +ITStatus I2C_GetITPendingBit(I2C_Type* I2Cx, uint32_t I2C_IT); +I2C_OpStatus I2C_GetStatus(I2C_Type* I2Cx); +void I2C_DMACmd(I2C_Type* I2Cx, uint16_t I2C_DMAReq, FunctionalState NewState); +void I2C_DMATxBurstMode(I2C_Type* I2Cx, FunctionalState NewState); +void I2C_DMATxBurstSize(I2C_Type* I2Cx, uint8_t I2C_BurstSize); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*BLUENRG1_I2C_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_mft.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_mft.h new file mode 100644 index 00000000000..cd704cab12d --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_mft.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_MFT_H +#define BLUENRG1_MFT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup MFT_Peripheral MFT Peripheral + * @{ + */ + +/** @defgroup MFT_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Structure definition of MFT initialization + */ + typedef struct +{ + uint8_t MFT_Mode; /*!< Specifies the MFT mode. + This value can be a value of @ref MFT_Mode_Definition */ + + uint8_t MFT_Clock1; /*!< Specifies the MFT clock selection, for counter A. + This value can be a value of @ref MFT_Clock_Selector_Definition */ + + uint8_t MFT_Clock2; /*!< Specifies the MFT clock selection, for counter B. + This value can be a value of @ref MFT_Clock_Selector_Definition */ + + uint8_t MFT_Prescaler; /*!< Specifies the MFT prescaler only for MFT_PRESCALED_CLK */ + + uint16_t MFT_CRA; /*!< Specifies the MFT CRA init value. */ + + uint16_t MFT_CRB; /*!< Specifies the MFT CRB init value. */ + +} MFT_InitType; + + +/** + * @} + */ + +/** @defgroup MFT_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup MFT_Peripheral_Name_Definitions Peripheral Name Definitions + * @{ + */ + +/** This macro checks if PERIPH is a valid MFT peripheral */ +#define IS_MFT(PERIPH) (((PERIPH) == MFT1) || ((PERIPH) == MFT2)) + +/** + * @} + */ + +/** @defgroup MFT_Mode_Definitions Mode Definitions + * @{ + */ + +#define MFT_MODE_1 ((uint8_t)0x00) /*!< Mode 1 */ +#define MFT_MODE_1a ((uint8_t)0x80) /*!< Mode 1a */ +#define MFT_MODE_2 ((uint8_t)0x01) /*!< Mode 2 */ +#define MFT_MODE_3 ((uint8_t)0x02) /*!< Mode 3 */ +#define MFT_MODE_4 ((uint8_t)0x03) /*!< Mode 4 */ + +#define IS_MFT_MODE(MODE) (((MODE) == MFT_MODE_1) || \ + ((MODE) == MFT_MODE_1a) || \ + ((MODE) == MFT_MODE_2) || \ + ((MODE) == MFT_MODE_3) || \ + ((MODE) == MFT_MODE_4)) + +/** + * @} + */ + +/** @defgroup MFT_Interrupt_Definitions Interrupt Definitions + * @{ + */ + +#define MFT_IT_TNA ((uint32_t)0x1) /*!< interrupt TnAPND */ +#define MFT_IT_TNB ((uint32_t)0x2) /*!< interrupt TnBPND */ +#define MFT_IT_TNC ((uint32_t)0x4) /*!< interrupt TnCPND */ +#define MFT_IT_TND ((uint32_t)0x8) /*!< interrupt TnDPND */ + +#define IS_MFT_INTERRUPT(IT) ((((IT) & (~0xF)) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup MFT_Clock_Selector_Definitions Clock Selector Definitions + * @{ + */ + +#define MFT_NO_CLK ((uint8_t)0x00) /*!< Noclock, timer1 stopped */ +#define MFT_PRESCALED_CLK ((uint8_t)0x01) /*!< System clock with configurable prescaler */ +#define MFT_EXTERNAL_EVENT ((uint8_t)0x02) /*!< External event on TnB (mode 1 and 3 only) */ +#define MFT_PULSE_ACCUMULATE ((uint8_t)0x03) /*!< Pulse accumulate (mode 1 and 3 only) */ +#define MFT_LOW_SPEED_CLK ((uint8_t)0x04) /*!< 16 MHz clock without prescaler (only when the system clock is 32 MHz). */ + +#define IS_MFT_CLOCK_SEL(MODE) (((MODE) == MFT_NO_CLK) || \ + ((MODE) == MFT_PRESCALED_CLK) || \ + ((MODE) == MFT_EXTERNAL_EVENT) || \ + ((MODE) == MFT_PULSE_ACCUMULATE) || \ + ((MODE) == MFT_LOW_SPEED_CLK)) + +/** + * @} + */ + + +/** @defgroup MFT_Pin_Trigger_Definitions Pin Trigger Definitions + * @{ + */ + +#define MFT_FALLING ((uint32_t)0x0) /* on rising edge */ +#define MFT_RISING ((uint32_t)0x1) /* on falling edge */ + +#define IS_MFT_Tn_EDGE(REG) (((REG) == MFT_FALLING) || ((REG) == MFT_RISING) ) + +/** + * @} + */ + +/** @defgroup MFT_Mode1a_Trigger_Definitions Mode1a Trigger Definitions + * @{ + */ + +#define MFT_TnB_TRIGGER ((uint32_t)0x0) /* trigger on TnB edge */ +#define MFT_SOFTWARE_TRIGGER ((uint32_t)0x1) /* trigger software */ + +#define IS_MFT_PULSETRAIN_TRIGGER(MODE) (((MODE) == MFT_TnB_TRIGGER) || ((MODE) == MFT_SOFTWARE_TRIGGER)) + + /** + * @} + */ + +/** @defgroup MFT_Pin_Definitions Pin Definitions + * @{ + */ + +#define MFT_TnA 0 /* select internal pin TnA */ +#define MFT_TnB 1 /* select internal pin TnB */ + +#define IS_MFT_TnX(VALUE) (((VALUE) == MFT_TnA) || ((VALUE) == MFT_TnB)) + +/** +* @} +*/ + +/** @defgroup MFT_PWMX_Pin_Definitions PWMX Pins Definitions + * @{ + */ + +#define MFT_PWM0_PIN GPIO_Pin_2 /* The PWM0 pin */ +#define MFT_PWM1_PIN GPIO_Pin_3 /* The PWM1 pin */ + +#define IS_MFT_PWMX_PIN(VALUE) (((VALUE) == MFT_PWM0_PIN) || ((VALUE) == MFT_PWM1_PIN)) + +/** +* @} +*/ + + +/** @defgroup MFT_TIMERx_Definitions TIMERx Definitions + * @{ + */ + +#define MFT1_TIMERA ((uint32_t)0x0) /* Timer MFT1 and input TnA */ +#define MFT1_TIMERB ((uint32_t)0x1) /* Timer MFT1 and input TnB */ +#define MFT2_TIMERA ((uint32_t)0x2) /* Timer MFT2 and input TnA */ +#define MFT2_TIMERB ((uint32_t)0x3) /* Timer MFT2 and input TnB */ + +#define IS_MFT_TIMER(VALUE) ((VALUE) <= 3) + +#define IS_MFT_INPUT_IO(VALUE) ((VALUE) < 15) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MFT_Exported_Functions Exported Functions + * @{ + */ + +void MFT_DeInit(MFT_Type* MFTx); +void MFT_Init(MFT_Type* MFTx, MFT_InitType* MFT_InitStruct); +void MFT_Cmd(MFT_Type* MFTx, FunctionalState NewState); +void MFT_StructInit(MFT_InitType* MFT_InitStruct); +void MFT_TnEDGES(MFT_Type* MFTx, uint32_t MFT_TnA_edge, uint32_t MFT_TnB_edge); +void MFT_PulseTrainTriggerSelect(MFT_Type* MFTx, uint32_t MFT_Trigger); +void MFT_PulseTrainSoftwareTrigger(MFT_Type* MFTx); +uint8_t MFT_PulseTrainEventTriggerStatus(MFT_Type* MFTx); +void MFT_TnXEN(MFT_Type* MFTx, uint8_t TnX, FunctionalState NewState); +void MFT_SelectCapturePin( uint32_t MFT_TimerType, uint8_t MFT_Pin); +void MFT_SetCounter(MFT_Type* MFTx, uint16_t MFT_Cnt1, uint16_t MFT_Cnt2); +void MFT_SetCounter1(MFT_Type* MFTx, uint16_t MFT_Cnt); +uint16_t MFT_GetCounter1(MFT_Type* MFTx); +void MFT_SetCounter2(MFT_Type* MFTx, uint16_t MFT_Cnt); +uint16_t MFT_GetCounter2(MFT_Type* MFTx); +void MFT_EnableIT(MFT_Type* MFTx, uint8_t MFT_IrqSource, FunctionalState NewState); +void MFT_ClearIT(MFT_Type* MFTx, uint8_t MFT_IrqSource); +ITStatus MFT_StatusIT(MFT_Type* MFTx, uint8_t MFT_IrqSource); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*BLUENRG1_MFT_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_pka.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_pka.h new file mode 100644 index 00000000000..b7918e19074 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_pka.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_PKA_H +#define BLUENRG1_PKA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup PKA_Peripheral PKA Peripheral + * @{ + */ + +/** @defgroup PKA_Exported_Types Exported Types + * @{ + */ + +#define PKA_DATA_SK 0x01 /* PKA select data for K value */ +#define PKA_DATA_PCX 0x02 /* PKA select data for Point X coordinate value */ +#define PKA_DATA_PCY 0x03 /* PKA select data for Point Y coordinate value */ + +#define IS_PKA_CMD(CMD) ( ((CMD) == PKA_DATA_SK) || \ + ((CMD) == PKA_DATA_PCX) || \ + ((CMD) == PKA_DATA_PCY) ) + + +/** + * @brief PKA status enumeration + */ + +#define PKA_PROCEND 0x01 /* PKA process end */ +#define PKA_RAMERR 0x04 /* PKA RAM error */ +#define PKA_ADDERR 0x08 /* PKA address invalid */ + +#define IS_PKA_FLAG(FLAG) ( ((FLAG) == PKA_PROCEND) || \ + ((FLAG) == PKA_RAMERR) || \ + ((FLAG) == PKA_ADDERR) ) + +/** + * @} + */ + +/** @defgroup PKA_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup PKA_Size_Definitions Size Definitions + * @{ + */ + +#define PKA_RAM_BASE (PKA_BASE + 0x00000400) + +#define PKA_RAM_START (PKA_RAM_BASE) +#define PKA_RAM_END (PKA_RAM_BASE + 0x00001000) + +#define PKA_RAM_ECC_ADDR_KP_ERROR (PKA_RAM_BASE) +#define PKA_RAM_ECC_ADDR_K (PKA_RAM_BASE + 0x6C) +#define PKA_RAM_ECC_ADDR_PX (PKA_RAM_BASE + 0x90) +#define PKA_RAM_ECC_ADDR_PY (PKA_RAM_BASE + 0xB4) + + + +/* The initial Point X coordinate of the curve in hex format: + * 6b17d1f2 e12c4247 f8bce6e5 63a440f2 77037d81 2deb33a0 f4a13945 d898c296 + */ +#define INITIAL_START_POINT_X_W1 0xd898c296 +#define INITIAL_START_POINT_X_W2 0xf4a13945 +#define INITIAL_START_POINT_X_W3 0x2deb33a0 +#define INITIAL_START_POINT_X_W4 0x77037d81 +#define INITIAL_START_POINT_X_W5 0x63a440f2 +#define INITIAL_START_POINT_X_W6 0xf8bce6e5 +#define INITIAL_START_POINT_X_W7 0xe12c4247 +#define INITIAL_START_POINT_X_W8 0x6b17d1f2 + +/* The initial Point Y coordinate of the curve in hex format: + * 4fe342e2 fe1a7f9b 8ee7eb4a 7c0f9e16 2bce3357 6b315ece cbb64068 37bf51f5 + */ +#define INITIAL_START_POINT_Y_W1 0x37bf51f5 +#define INITIAL_START_POINT_Y_W2 0xcbb64068 +#define INITIAL_START_POINT_Y_W3 0x6b315ece +#define INITIAL_START_POINT_Y_W4 0x2bce3357 +#define INITIAL_START_POINT_Y_W5 0x7c0f9e16 +#define INITIAL_START_POINT_Y_W6 0x8ee7eb4a +#define INITIAL_START_POINT_Y_W7 0xfe1a7f9b +#define INITIAL_START_POINT_Y_W8 0x4fe342e2 + + +/** + * @} + */ + + +/** @defgroup PKA_Commands_Definitions Commands Definitions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PKA_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PKA_Exported_Functions Exported Functions + * @{ + */ + + +ErrorStatus PKA_SetData(uint8_t dataType, uint32_t* srcData); +ErrorStatus PKA_GetData(uint8_t dataType, uint8_t* dataTarget); + +void PKA_Reset(void); +void PKA_StartProcessing(void); +void PKA_WaitProcess(void); +FlagStatus PKA_GetProcessStatus(void); +ErrorStatus PKA_VerifyProcess(void); + +void PKA_ClearITPendingBit(uint8_t PkaFlag); +FlagStatus PKA_GetFlagStatus(uint8_t PkaFlag); +void PKA_ITConfig(uint8_t PkaFlag, FunctionalState NewState); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_PKA_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_radio.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_radio.h new file mode 100644 index 00000000000..602bd5d2909 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_radio.h @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + + /* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_RADIO_H +#define BLUENRG1_RADIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "bluenrg_x_device.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + + +/** @addtogroup Radio_Peripheral Radio Peripheral + * @{ + */ + +/** @defgroup Radio_Exported_Constants Exported Constants +* @{ + */ + +#define HEADER_LENGTH 2 +#ifdef BLUENRG2_DEVICE +#define MAX_PACKET_LENGTH (255+HEADER_LENGTH) // 255 (-4 if encryption) +#else +#define MAX_PACKET_LENGTH (38+HEADER_LENGTH) // 31 in data channel, 38 in adv. channel (-4 if encryption) +#endif +#define MIC_FIELD_LENGTH 4 +#define RECEIVE_BUFFER_LENGTH 45 +#define MAX_OUTPUT_RF_POWER 15 +#define SUCCESS_0 0 +#define INVALID_PARAMETER_C0 0xC0 +#define WAKEUP_NOTSET_C2 0xC2 +#define RADIO_BUSY_C4 0xC4 +#define COMMAND_DISALLOWED 0xC5 +#define NULL_0 0 +#define BLUE_IDLE_0 0 +#define BLUE_BUSY_NOWAKEUP_T1 1 +#define BLUE_BUSY_NOWAKEUP_T2 2 +#define BLUE_BUSY_WAKEUP 3 +#define TIMESTAMP_POSITION_ACCESSADDRESS 0x40 +#define TIMESTAMP_POSITION_LASTBIT 0x80 /*C0*/ +#define HOT_ANA_CONFIG_TABLE_LENGTH 64 +#define CONFIG_ERROR_EN 0x10 +#define SCA_DEFAULTVALUE 488 + +#define STATEMACHINE_COUNT 8 + +#define ANALOG_HW_OFFSET (86) /* subtrack 2*86 in the 1st packet for XC oscillator */ +#define TIMING_ERROR_CORRECTION (69) /* subtrack 2*69 in all packet except 1st for XC oscillator */ + + +/** @defgroup Radio_Interrupt_Status_Bits Interrupt Status bits + * @{ + */ + +#define IRQ_RCV_OK (1UL<<31) /* The packet is received, and the CRC is valid. */ +#define IRQ_CRC_ERR (1UL<<30) /* The packet is received with CRC error or timeout error. */ +#define IRQ_RCV_TRIG (1UL<<29) +#define IRQ_CMD (1UL<<28) +#define IRQ_MD (1UL<<27) +#define IRQ_TIMEOUT (1UL<<26) /* No packet received within the defined RX time window. */ +#define IRQ_RCV_FAIL (1UL<<25) +#define IRQ_DONE (1UL<<24) /* Requested action (TX or RX) has been executed. */ +#define IRQ_ERR_ENC (1UL<<23) /* A packet is received, but there is an error in the MIC field. */ +#define IRQ_TX_OK (1UL<<22) /* The packet has been sent successfully. */ +#define BIT_TX_SKIP (1UL<<20) +#define IRQ_CONFIG_ERR (1UL<<19) +#define BIT_TX_MODE (1UL<<18) /* The packet has been sent successfully. */ +#define BIT_TIME_OVERRUN (1UL<<17) +#define BIT_ACT2_ERROR (1UL<<16) +#define IRQ_WAKEUP_2 (1UL<<15) +#define BIT_AES_READY (1UL<<12) + +/** + * @} + */ + + +/** @defgroup Radio_ActionTag_BitMask ActionTag BitMask +* @{ +*/ + +/* This bit activates the radio frequency PLL calibration. + * 0: Radio frequency calibration disabled. + * 1: Radio frequency calibration enabled. + * User should set this bit only if TIMER_WAKEUP is set to 1. +*/ +#define PLL_TRIG 0x01 + +/* This bit determines if the action is an RX action or a TX action. + * 1: TX + * 0: RX +*/ +#define TXRX 0x02 + +/* The bit determines if the action (RX or TX) is going to be executed based on the back-to-back time or based on the WakeupTime. + * 0: Based on the back-to-back time (default 150 µs). + * 1: Based on the WakeupTime. +*/ +#define TIMER_WAKEUP 0x04 + +/* This bit activates automatic channel increment. The API RADIO_SetChannel sets the value of the increment. + * 0: No increment + * 1: Automatic increment +*/ +#define INC_CHAN 0x10 + +/* It determines if the WakeupTime field of the ActionPacket is considered as absolute time or relative time to the current. + * 0: Absolute + * 1: Relative +*/ +#define RELATIVE 0x20 + +/* This bit sets where the position of time stamp is taken, the beginning of the packet or the end of it. RX only. + * 0: End of the Packet + * 1: Beginning of the packet + */ +#define TIMESTAMP_POSITION 0x80 + +/** + * @} + */ + + +/** +* @} +*/ + +/** @defgroup Radio_Exported_Types Exported Types +* @{ +*/ + +typedef enum { + STATE_MACHINE_0 = 0, + STATE_MACHINE_1, + STATE_MACHINE_2, + STATE_MACHINE_3, + STATE_MACHINE_4, + STATE_MACHINE_5, + STATE_MACHINE_6, + STATE_MACHINE_7, +} StateMachine_t; + +typedef struct +{ + volatile uint16_t next; + volatile uint16_t datptr; + volatile uint8_t rcvlen[3]; + volatile uint8_t timeout[3]; + volatile uint8_t byte10; + volatile uint8_t byte11; +} BlueTransStruct; + + +typedef struct ActionPacket ActionPacket; + +typedef struct { + uint32_t *hot_ana_config_table; /**< Set to NULL */ + uint8_t ls_source; /**< Source for the 32 kHz slow speed clock: 1: internal RO; 0: external crystal */ + uint16_t hs_startup_time ; /**< Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)*/ +} config_table_t; + + +typedef struct { + int32_t freq; + int32_t period; + struct { + uint32_t Time_mT : 24; + uint32_t started_flag : 8; + } calibr; +} Clk32Context_t; + +typedef struct { + uint32_t back2backTime; + uint8_t forceRadiotoStop; + uint32_t rssiLevel[2]; + int32_t wakeupTime; + uint16_t period_slow_patch; + int32_t freq_global_debug; + int32_t period_global_debug; + int32_t hot_ana_config_table_a[HOT_ANA_CONFIG_TABLE_LENGTH>>2]; + Clk32Context_t Clk32Context; + config_table_t hardware_config; + // uint8_t tone_start_stop_flag; + ActionPacket* current_action_packet; + uint8_t powerUpfirstPacket; + +}RadioGlobalParameters_t; + +extern RadioGlobalParameters_t globalParameters; + + +struct ActionPacket +{ + uint8_t StateMachineNo ; /* This parameter indicates the state machine number for this action. From 0 to 7. */ + uint8_t ActionTag; /* The configuration of the current action. + * Action Tag: PLL_TRIG, TXRX, TIMER_WAKEUP, INC_CHAN, TIMESTAMP_POSITION, RELATIVE */ + uint32_t WakeupTime; /* Contains the wakeup time in microsecond if it is relative. + * It should not be more than 24 bits if it is absolute. + * It only applies if TIMER_WAKEUP flag is set in ActionTag. */ + uint32_t ReceiveWindowLength; /* Sets RX window size in microsecond. Applicable only for RX actions. */ + uint8_t *data; /* Pointer to the array with the data to send (header, length and data field), for TX. + * Pointer to the array where the data received are copied, for RX. + * In case of RX, the array must have the max size MAX_PACKET_LENGTH. */ + uint32_t status; /* The Status Register with the information on the action. */ + uint32_t timestamp_receive; /* This field contains the timestamp when a packet is received. + * Intended to be used in the dataRoutine() callback routine. RX only. */ + int32_t rssi; /* The rssi of the packet was received with. RX only. */ + BlueTransStruct trans_packet; /* This is a linked list, which is going to be used by Hardware. + * User does not need to do anything. */ + ActionPacket *next_true; /* Pointer to next ActionPacket if condRoutine() returns TRUE */ + ActionPacket *next_false; /* Pointer to next ActionPacket if condRoutine() returns FALSE */ + uint8_t (*condRoutine)(ActionPacket*); /* User callback that decide the next ActionPacket to use. + * It is time critical. Routine must end within 45 us. */ + uint8_t (*dataRoutine)(ActionPacket*, ActionPacket*); /* User callback for managing data. */ + uint8_t trans_config; /* This is for configuring the device for TX or RX. User does not need to do anything. */ +}; + +/** +* @} +*/ + + +/** @defgroup Radio_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup Radio_Private_Functions Private Functions +* @{ +*/ + +/** + * @} + */ + + +/** @defgroup Radio_Exported_Functions Exported Functions + * @{ + */ + +void RADIO_Init(uint16_t hs_startup_time, uint8_t low_speed_osc, uint32_t* hot_table, FunctionalState whitening); +uint8_t RADIO_GetStatus(uint32_t *time); +void RADIO_SetChannelMap(uint8_t StateMachineNo,uint8_t *chan_remap); +void RADIO_SetChannel(uint8_t StateMachineNo, uint8_t channel,uint8_t channel_increment); +void RADIO_SetTxAttributes(uint8_t StateMachineNo, uint32_t NetworkID, uint32_t crc_init, uint32_t sca); +void RADIO_SetBackToBackTime(uint32_t back_to_back_time); +void RADIO_SetTxPower(uint8_t PowerLevel); +void RADIO_IRQHandler(void); +uint8_t RADIO_StopActivity(void); +void RADIO_SetReservedArea(ActionPacket *p); +uint8_t RADIO_MakeActionPacketPending(ActionPacket *p); +void RADIO_CrystalCheck(void); +void RADIO_StartTone(uint8_t RF_channel, uint8_t powerLevel); +void RADIO_StopTone(void); +void RADIO_SetEncryptionCount(uint8_t StateMachineNo, uint8_t *count_tx, uint8_t *count_rcv); +void RADIO_SetEncryptionAttributes(uint8_t StateMachineNo, uint8_t *enc_iv, uint8_t *enc_key); +void RADIO_SetEncryptFlags(uint8_t StateMachineNo, FunctionalState EncryptFlagTx, FunctionalState EncryptFlagRcv); +void RADIO_EncryptPlainData(uint8_t *Key, uint8_t *plainData, uint8_t *cypherData); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*BLUENRG1_RADIO_H */ + +/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_rng.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_rng.h new file mode 100644 index 00000000000..bb17744f16c --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_rng.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_RNG_H +#define BLUENRG1_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup RNG_Peripheral RNG Peripheral + * @{ + */ + +/** @defgroup RNG_Exported_Types Exported Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Exported_Constants Exported Constants + * @{ + */ + +/** + * @} + */ + + +/** @defgroup RNG_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Exported_Functions Exported Functions + * @{ + */ + +void RNG_Cmd(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(void); + +/** +* @brief Get the RNG value. +* @param None +* @retval RNG value +*/ +#define RNG_GetValue() READ_REG(RNG->VAL) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_RNG_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_rtc.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_rtc.h new file mode 100644 index 00000000000..9ab08411cbe --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_rtc.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_RTC_H +#define BLUENRG1_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup RTC_Peripheral RTC Peripheral + * @{ + */ + +/** @defgroup RTC_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Structure definition of RTC initialization + */ +typedef struct +{ + uint8_t RTC_operatingMode; /*!< Specifies the operating mode. + This parameter can be a value of @ref RTC_Timer_OperatingMode */ + + uint32_t RTC_TLR1; /*!< Load TLR1 register. + 32 bit value to load */ + + uint32_t RTC_TLR2; /*!< Load TLR2 register. + 32 bit value to load */ + + uint32_t RTC_PATTERN_SIZE; /*!< Define the pattern size to use. + 7 bit pattern, 0x0 size of 1 and 0x7F size of 128 */ + + uint32_t RTC_PATTERN1; /*!< Define the pattern, '0' relaod TLR1 and '1' reload TLR2. + First 32 bit pattern */ + + uint32_t RTC_PATTERN2; /*!< Define the pattern, '0' relaod TLR1 and '1' reload TLR2. + Second 32 bit pattern */ + + uint32_t RTC_PATTERN3; /*!< Define the pattern, '0' relaod TLR1 and '1' reload TLR2. + Third 32 bit pattern */ + + uint32_t RTC_PATTERN4; /*!< Define the pattern, '0' relaod TLR1 and '1' reload TLR2. + Fourth 32 bit pattern */ +} RTC_InitType; + + +/** + * @brief Structure definition of RTC DateTime + */ +typedef struct +{ + uint8_t Second; /*!< Specify the present second to be set to RTC clockwatch. + This parameter can be integer value in range from 0 to 59 */ + + uint8_t Minute; /*!< Specify the present minute to be set to RTC clockwatch. + This parameter can be integer value in range from 0 to 59 */ + + uint8_t Hour; /*!< Specify the present hour to be set to RTC clockwatch. + This parameter can be integer value in range from 0 to 23 */ + + uint8_t WeekDay; /*!< Specify the present day in the week to be set to RTC clockwatch. + This parameter can be an integer value in range from 0 to 7 */ + + uint8_t MonthDay; /*!< Specify the present day in the month to be set to RTC clockwatch. + This parameter can be an integer value in range from 1 to 31 (depends on month) */ + + uint8_t Month; /*!< Specify the present month to be set to RTC clockwatch. + This parameter can be an integer value in range from 1 to 12 (depends on month) */ + + uint16_t Year; /*!< Specify the present year to be set to RTC clockwatch. + This parameter can be an integer value in range from 0 to 3999 (depends on month) */ + +} RTC_DateTimeType; + +/** + * @} + */ + + +/** @defgroup RTC_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup RTC_Time_and_Data_Definitions Time and Data Definitions + * @{ + */ + +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) + +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) +#define RTC_Weekday_Sunday ((uint8_t)0x07) + +#define IS_SECOND(N) ((N) < 60) +#define IS_MINUTE(N) ((N) < 60) +#define IS_HOUR(N) ((N) < 24) +#define IS_WEEKDAY(N) (((N) > 0) && ((N) < 8)) +#define IS_MONTHDAY(N) (((N) > 0) && ((N) < 32)) +#define IS_MONTH(N) (((N) > 0) && ((N) < 13)) +#define IS_YEAR(N) (((N) > 0) && ((N) < 4000)) + +#define IS_MATCH_WEEKDAY(N) ((N) < 8) +#define IS_MATCH_MONTHDAY(N) ((N) < 32) +#define IS_MATCH_MONTH(N) ((N) < 13) +#define IS_MATCH_YEAR(N) ((N) < 4000) + + +/** + * @} + */ + + + +/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions + * @{ + */ +#define RTC_IT_CLOCKWATCH ((uint8_t)1) /*!< RTC clock watch interrupt */ +#define RTC_IT_TIMER ((uint8_t)2) /*!< RTC timer interrupt */ + + +/** This macro checks if IT is a valid combination of interrupt */ +#define IS_RTC_IT(IT) (((IT) == RTC_IT_CLOCKWATCH) || \ + ((IT) == RTC_IT_TIMER)) + +/** + * @} + */ + +/** @defgroup RTC_Timer_Operating_Mode_Definitions Timer Operating Mode Definitions + * @{ + */ +#define RTC_TIMER_PERIODIC ((uint8_t)0) /*!< RTC timer periodic mode */ +#define RTC_TIMER_ONESHOT ((uint8_t)1) /*!< RTC timer one shot mode */ + + +/** This macro checks if IT is a valid combination of interrupt */ +#define IS_RTC_TIMER_MODE(IT) (((IT) == RTC_TIMER_PERIODIC) || \ + ((IT) == RTC_TIMER_ONESHOT)) + +/** + * @} + */ + +/** @defgroup RTC_Pattern_Size_Definitions Pattern Size Definitions + * @{ + */ + +#define IS_PATTERN(N) ((N) < 0x80) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions Exported Functions + * @{ + */ + +void RTC_Init(RTC_InitType* RTC_InitStruct); +void RTC_StructInit(RTC_InitType* RTC_InitStruct); +void RTC_Cmd(FunctionalState NewState); +void RTC_IT_Config(uint8_t RTC_IT, FunctionalState NewState); +ITStatus RTC_IT_Status(uint8_t RTC_IT); +void RTC_IT_Clear(uint8_t RTC_IT); + +void RTC_ClockwatchCmd(FunctionalState NewState); +void RTC_SetTimeDate(RTC_DateTimeType* RTC_DateTime); +void RTC_SetMatchTimeDate(RTC_DateTimeType* RTC_MatchDataTime); +void RTC_GetTimeDate(RTC_DateTimeType* RTC_DataTime); + +uint32_t RTC_GetTimerValue(void); +void RTC_AutoStart(FunctionalState NewState); +void RTC_SelectTrimmedClock(FunctionalState NewState); +uint32_t RTC_GetNumberIrqGenerated(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_RTC_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_spi.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_spi.h new file mode 100644 index 00000000000..274c998bebf --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_spi.h @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_SPI_H +#define BLUENRG1_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "bluenrg_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup SPI_Peripheral SPI Peripheral + * @{ + */ + +/** @defgroup SPI_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization + */ +typedef struct { + uint8_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint8_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint8_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint8_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t SPI_BaudRate; /*!< Specifies the Baud Rate value which will be + used to configure the transmit and receive SCK clock. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ +} SPI_InitType; + + +/** + * @} + */ + + +/** @defgroup SPI_Exported_Constants Exported Constants + * @{ + */ + + +/** @defgroup SPI_Clock_Speed_Definition Clock Speed Definitions + * @{ + */ + +/* This macro checks if SPI baud rate is a valid value */ +#define IS_SPI_BAUDRATE(BAUDRATE) (((BAUDRATE)>=10000) && ((BAUDRATE)<=8000000)) + +/** +* @} +*/ + +/** @defgroup SPI_Communication_Mode_Definition Communication Mode Definition + * @{ + */ +#define SPI_FULL_DUPLEX_MODE ((uint32_t)0x00000000) +#define SPI_TRANSMIT_MODE ((uint32_t)0x00000001) +#define SPI_RECEIVE_MODE ((uint32_t)0x00000002) +#define SPI_COMBINED_MODE ((uint32_t)0x00000003) + + +#define IS_SPI_COM_MODE(MODE) (((MODE) == SPI_FULL_DUPLEX_MODE) || \ + ((MODE) == SPI_TRANSMIT_MODE) || \ + ((MODE) == SPI_RECEIVE_MODE) || \ + ((MODE) == SPI_COMBINED_MODE)) + +/** + * @} + */ + +/** @defgroup SPI_Mode_Definition Mode Definition + * @{ + */ + +#define SPI_FrmFrmt_Motorola ((uint8_t)0x0) /*!< Motorola SPI frame format */ +#define SPI_FrmFrmt_Microwire ((uint8_t)0x2) /*!< MicroWire frame format */ + +/* This macro checks if frame format value is valid */ +#define IS_SPI_FRMFRMT(FRMT) (((FRMT) == SPI_FrmFrmt_Motorola) || \ + ((FRMT) == SPI_FrmFrmt_Microwire)) + +/** + * @} + */ + +/** @defgroup SPI_Mode_Definition Mode Definition + * @{ + */ + +#define SPI_Mode_Master ((uint8_t)0x00) /*!< Master mode */ +#define SPI_Mode_Slave ((uint8_t)0x01) /*!< Slave mode */ + +/* This macro checks if MODE is a valid SPI mode */ +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) + +/** + * @} + */ + + +/** @defgroup SPI_Data_Size_Definition Data Size Definition + * @{ + */ +#define SPI_DataSize_32b ((uint8_t)0x1F) /*!< 32-bit data size */ +#define SPI_DataSize_31b ((uint8_t)0x1E) /*!< 31-bit data size */ +#define SPI_DataSize_30b ((uint8_t)0x1D) /*!< 30-bit data size */ +#define SPI_DataSize_29b ((uint8_t)0x1C) /*!< 29-bit data size */ +#define SPI_DataSize_28b ((uint8_t)0x1B) /*!< 28-bit data size */ +#define SPI_DataSize_27b ((uint8_t)0x1A) /*!< 27-bit data size */ +#define SPI_DataSize_26b ((uint8_t)0x19) /*!< 26-bit data size */ +#define SPI_DataSize_25b ((uint8_t)0x18) /*!< 25-bit data size */ +#define SPI_DataSize_24b ((uint8_t)0x17) /*!< 24-bit data size */ +#define SPI_DataSize_23b ((uint8_t)0x16) /*!< 23-bit data size */ +#define SPI_DataSize_22b ((uint8_t)0x15) /*!< 22-bit data size */ +#define SPI_DataSize_21b ((uint8_t)0x14) /*!< 21-bit data size */ +#define SPI_DataSize_20b ((uint8_t)0x13) /*!< 20-bit data size */ +#define SPI_DataSize_19b ((uint8_t)0x12) /*!< 19-bit data size */ +#define SPI_DataSize_18b ((uint8_t)0x11) /*!< 18-bit data size */ +#define SPI_DataSize_17b ((uint8_t)0x10) /*!< 17-bit data size */ +#define SPI_DataSize_16b ((uint8_t)0x0F) /*!< 16-bit data size */ +#define SPI_DataSize_15b ((uint8_t)0x0E) /*!< 15-bit data size */ +#define SPI_DataSize_14b ((uint8_t)0x0D) /*!< 14-bit data size */ +#define SPI_DataSize_13b ((uint8_t)0x0C) /*!< 13-bit data size */ +#define SPI_DataSize_12b ((uint8_t)0x0B) /*!< 12-bit data size */ +#define SPI_DataSize_11b ((uint8_t)0x0A) /*!< 11-bit data size */ +#define SPI_DataSize_10b ((uint8_t)0x09) /*!< 10-bit data size */ +#define SPI_DataSize_9b ((uint8_t)0x08) /*!< 9-bit data size */ +#define SPI_DataSize_8b ((uint8_t)0x07) /*!< 8-bit data size */ +#define SPI_DataSize_7b ((uint8_t)0x06) /*!< 7-bit data size */ +#define SPI_DataSize_6b ((uint8_t)0x05) /*!< 6-bit data size */ +#define SPI_DataSize_5b ((uint8_t)0x04) /*!< 5-bit data size */ +#define SPI_DataSize_4b ((uint8_t)0x03) /*!< 4-bit data size */ + +/* This macro checks if DATASIZE is a valid SPI data size value */ +#define IS_SPI_DATASIZE(DATASIZE) ((DATASIZE) < 0x20) + +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity_Definition Clock Polarity Definition + * @{ + */ + +#define SPI_CPOL_Low ((uint8_t)0) /*!< Clock polarity low */ +#define SPI_CPOL_High ((uint8_t)1) /*!< Clock polarity high */ + +/* This macro checks if CPOL is a valid clock polarity value */ +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) + + +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase_Definition Clock Phase Definition + * @{ + */ + +#define SPI_CPHA_1Edge ((uint8_t)0) /*!< Clock phase 1st edge */ +#define SPI_CPHA_2Edge ((uint8_t)1) /*!< Clock phase 2nd edge */ + +/* This macro checks if CPHA is a valid clock phase value */ +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup SPI_Interrupts_Mask_Definition Interrupts Mask Definition + * @{ + */ +#define SPI_IT_TE ((uint8_t)0x20) /*!< Transmit FIFO empty interrupt mask */ +#define SPI_IT_TUR ((uint8_t)0x10) /*!< Transmit underrun interrupt mask */ +#define SPI_IT_TX ((uint8_t)0x08) /*!< Tx interrupt mask */ +#define SPI_IT_RX ((uint8_t)0x04) /*!< Rx interrupt mask */ +#define SPI_IT_RT ((uint8_t)0x02) /*!< Rx timeout interrupt mask */ +#define SPI_IT_ROR ((uint8_t)0x01) /*!< Rx overrun interrupt mask */ +#define SPI_IT_MSK ((uint8_t)0x3F) /*!< Interrupt mask */ + +/* This macro checks if IT is a valid combination of interrupt */ +#define IS_SPI_CONFIG_IT(IT) ((((IT) & ~SPI_IT_MSK) == 0x00) && ((IT) != 0x00)) + + +/* This macro checks if IT is a valid clearable interrupt */ +#define IS_SPI_CLEAR_IT(IT) (((IT) == SPI_IT_TUR) || \ + ((IT) == SPI_IT_RT) || ((IT) == SPI_IT_ROR)) + +/* This macro checks if IT is a valid interrupt */ +#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_TX) || ((IT) == SPI_IT_RX) || \ + ((IT) == SPI_IT_RT) || ((IT) == SPI_IT_ROR) || \ + ((IT) == SPI_IT_TUR) || ((IT) == SPI_IT_TE)) + + +/** + * @} + */ + +/** @defgroup SPI_Flags_Definition Flags Definition + * @{ + */ +#define SPI_FLAG_TFE ((uint8_t)0x01) /*!< Tx FIFO empty flag */ +#define SPI_FLAG_TNF ((uint8_t)0x02) /*!< Tx FIFO not full flag */ +#define SPI_FLAG_RNE ((uint8_t)0x04) /*!< Rx FIFO not empty flag */ +#define SPI_FLAG_RFF ((uint8_t)0x08) /*!< Rx FIFO full flag */ +#define SPI_FLAG_BSY ((uint8_t)0x10) /*!< Busy flag */ + +/* This macro checks if FLAG is a valid flag */ +#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_TFE) || ((FLAG) == SPI_FLAG_TNF) || \ + ((FLAG) == SPI_FLAG_RNE) || ((FLAG) == SPI_FLAG_RFF) || \ + ((FLAG) == SPI_FLAG_BSY)) +/** + * @} + */ + +/** @defgroup SPI_DMA_Requests_Definition DMA Requests Definition + * @{ + */ + +#define SPI_DMAReq_Tx ((uint8_t)0x04) /*!< DMA TX request */ +#define SPI_DMAReq_Rx ((uint8_t)0x01) /*!< DMA RX request */ + +/* This macro checks if DMAREQ is a valid DMA request */ +#define IS_SPI_DMAREQ(DMAREQ) (((DMAREQ)==SPI_DMAReq_Tx) || ((DMAREQ)==SPI_DMAReq_Rx) || ((DMAREQ)==(SPI_DMAReq_Rx | SPI_DMAReq_Tx))) + +/** + * @} + */ + + +/** @defgroup SPI_Fifo_Level_Definition FIFO Level Definition + * @{ + */ + +#define SPI_FIFO_LEV_1 ((uint8_t)0) /*!< Interrupt when FIFO contains 1 element or more */ +#define SPI_FIFO_LEV_4 ((uint8_t)1) /*!< Interrupt when FIFO contains 4 elements or more */ +#define SPI_FIFO_LEV_8 ((uint8_t)2) /*!< Interrupt when FIFO contains 8 elements or more */ + +/* This macro checks if IS_SPI_FIFO_LEV is a valid FIFO level */ +#define IS_SPI_FIFO_LEV(FIFO_LEV) ( ((FIFO_LEV) == SPI_FIFO_LEV_1) || \ + ((FIFO_LEV) == SPI_FIFO_LEV_4) || \ + ((FIFO_LEV) == SPI_FIFO_LEV_8)) + +/** + * @} + */ + + +/** @defgroup SPI_Endian_Format_Definition Endian Format Definition + * @{ + */ + +#define SPI_ENDIAN_MSByte_MSBit ((uint8_t)0) /*!< Endian format MSByte first and MSbit first */ +#define SPI_ENDIAN_LSByte_MSBit ((uint8_t)1) /*!< Endian format LSByte first and MSbit first */ +#define SPI_ENDIAN_MSByte_LSBit ((uint8_t)2) /*!< Endian format MSByte first and LSbit first */ +#define SPI_ENDIAN_LSByte_LSBit ((uint8_t)3) /*!< Endian format LSByte first and LSbit first */ + +/** This macro checks if IS_SPI_ENDIAN is a valid FORMAT value */ +#define IS_SPI_ENDIAN(FORMAT) ( ((FORMAT) == SPI_ENDIAN_MSByte_MSBit) || \ + ((FORMAT) == SPI_ENDIAN_LSByte_MSBit) || \ + ((FORMAT) == SPI_ENDIAN_MSByte_LSBit) || \ + ((FORMAT) == SPI_ENDIAN_LSByte_LSBit)) +/** + * @} + */ + +/** @defgroup SPI_Delay_Between_Frames_Definition Delay Between Frames Definition + * @{ + */ + +/* This macro checks if IS_WAIT_VALUE is a valid value */ +#define IS_WAIT_VALUE(VALUE) ( (VALUE) < 16) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions Exported Functions + * @{ + */ + +/* SPI initialization and configuration */ +void SPI_StructInit(SPI_InitType* SPI_InitStruct); +void SPI_DeInit(void); +void SPI_Init(SPI_InitType* SPI_InitStruct); +void SPI_Cmd(FunctionalState NewState); +void SPI_ITConfig(uint8_t SPI_IT, FunctionalState NewState); +void SPI_DataSizeConfig(uint16_t SPI_DataSize); +void SPI_CommandSizeConfig(uint16_t SPI_DataSize); +void SPI_FrameFormatConfig(uint8_t SPI_FrameFormat); + +/* SPI data register access */ +void SPI_SendData(uint32_t Data); +uint32_t SPI_ReceiveData(void); + +/* Interrupt and status management */ +FlagStatus SPI_GetFlagStatus(uint16_t SPI_FLAG); +ITStatus SPI_GetITStatus(uint8_t SPI_IT); +void SPI_ClearITPendingBit(uint8_t SPI_IT); + +/* Clear RX and TX FIFO */ +void SPI_ClearRXFIFO(void); +void SPI_ClearTXFIFO(void); + +/* Communication mode configuration in SPI master mode */ +void SPI_SetMasterCommunicationMode(uint32_t Mode); +void SPI_SetDummyCharacter(uint32_t NullCharacter); +void SPI_SetNumFramesToReceive(uint16_t Number); +void SPI_SetNumFramesToTransmit(uint16_t Number); +void SPI_EnableWaitState(FunctionalState NewState); +void SPI_SlaveSwSelection(FunctionalState NewState); +void SPI_EndianFormatReception(uint8_t Endian); +void SPI_EndianFormatTransmission(uint8_t Endian); +void SPI_DelayBetweenFrames(uint8_t Delay); +void SPI_DelayDataInput(FunctionalState NewState); + +/* Special functionality */ +void SPI_SlaveModeOutputCmd(FunctionalState NewState); + +/* DMA channel control */ +void SPI_DMACmd(uint8_t SPI_DMAReq, FunctionalState NewState); + +/* SPI FIFO interrupt level */ +void SPI_TxFifoInterruptLevelConfig(uint8_t SPI_TX_FIFO_LEV); +void SPI_RxFifoInterruptLevelConfig(uint8_t SPI_RX_FIFO_LEV); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*BLUENRG1_SPI_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_sysCtrl.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_sysCtrl.h new file mode 100644 index 00000000000..fe6047ea4f5 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_sysCtrl.h @@ -0,0 +1,189 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_SYSCTRL_H +#define BLUENRG1_SYSCTRL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup SystemControl System Control + * @{ + */ + +/** @defgroup SystemControl_Exported_Types Exported Types + * @{ + */ + + +/** + * @brief System Reset and Wakeup Sources + */ +typedef enum +{ + RESET_NONE, + RESET_SYSREQ, + RESET_WDG, + RESET_LOCKUP, + RESET_BLE_BOR, + RESET_BLE_POR, + RESET_BLE_WAKEUP_FROM_IO9, + RESET_BLE_WAKEUP_FROM_IO10, + RESET_BLE_WAKEUP_FROM_IO11, + RESET_BLE_WAKEUP_FROM_IO12, + RESET_BLE_WAKEUP_FROM_IO13, + RESET_BLE_WAKEUP_FROM_TIMER1, + RESET_BLE_WAKEUP_FROM_TIMER2, +} RESET_REASON_Type; + + +/** + * @} + */ + +/** @defgroup SystemControl_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup System_Clock_Frequency System Clock Frequency + * @{ + */ +#if (HS_SPEED_XTAL == HS_SPEED_XTAL_32MHZ) + #define SYST_CLOCK 32000000 /* System clock frequency */ +#elif (HS_SPEED_XTAL == HS_SPEED_XTAL_16MHZ) + #define SYST_CLOCK 16000000 /* System clock frequency */ +#else +#error "No definition for SYST_CLOCK" +#endif + +/** + * @} + */ + + +/** @defgroup Peripherals_Clock Peripherals Clock + * @{ + */ +#define CLOCK_PERIPH_GPIO ((uint32_t)0x00000001) +#define CLOCK_PERIPH_NVM ((uint32_t)0x00000002) +#define CLOCK_PERIPH_SYS_CONTROL ((uint32_t)0x00000004) +#define CLOCK_PERIPH_UART ((uint32_t)0x00000008) +#define CLOCK_PERIPH_SPI ((uint32_t)0x00000010) +#define CLOCK_PERIPH_WDG ((uint32_t)0x00000080) +#define CLOCK_PERIPH_ADC ((uint32_t)0x00000100) +#define CLOCK_PERIPH_I2C1 ((uint32_t)0x00000200) +#define CLOCK_PERIPH_I2C2 ((uint32_t)0x00000400) +#define CLOCK_PERIPH_MTFX1 ((uint32_t)0x00000800) +#define CLOCK_PERIPH_MTFX2 ((uint32_t)0x00001000) +#define CLOCK_PERIPH_RTC ((uint32_t)0x00002000) +#define CLOCK_PERIPH_DMA ((uint32_t)0x00010000) +#define CLOCK_PERIPH_RNG ((uint32_t)0x00020000) +#define CLOCK_PERIPH_PKA ((uint32_t)0x000C0000) + +#define IS_CLOCK_PERIPH(PERIPH) (((PERIPH) & 0x000F3F9F) != 0) +/** + * @} + */ + + + +/** @defgroup IO_sources_for_wakeup IO sources for wakeup + * @{ + */ + +#define WAKEUP_ON_IO9 ((uint8_t)0x01) /* Wakeup source is IO9 */ +#define WAKEUP_ON_IO10 ((uint8_t)0x02) /* Wakeup source is IO10 */ +#define WAKEUP_ON_IO11 ((uint8_t)0x04) /* Wakeup source is IO11 */ +#define WAKEUP_ON_IO12 ((uint8_t)0x08) /* Wakeup source is IO12 */ +#define WAKEUP_ON_IO13 ((uint8_t)0x10) /* Wakeup source is IO13 */ + +#define WAKEUP_ON_HIGH_STATE ((uint8_t)0) /* Wakeup on high state */ +#define WAKEUP_ON_LOW_STATE ((uint8_t)1) /* Wakeup on low state */ + +#define IS_WAKEUP_ON_IO(IOS) (((IOS) & 0x1F) != 0) + +#define IS_WAKEUP_ON_STATE(STATE) ( ((STATE) == WAKEUP_ON_HIGH_STATE) || ((STATE) == WAKEUP_ON_LOW_STATE) ) + +/** + * @} + */ + + +/** @defgroup External_Clock_Selection External Clock Selection + * @{ + */ + +#define XO_32MHZ ((uint8_t)1) /* The external clock XO used is a 32 MHz */ +#define XO_16MHZ ((uint8_t)0) /* The external clock XO used is a 16 MHz */ + +#define IS_XO_FREQ(XO) ( ((XO) == XO_32MHZ) || ((XO) == XO_16MHZ) ) + +/** + * @} + */ + + +/** + * @} + */ + + + +/** @defgroup SystemControl_Exported_Functions Exported Functions + * @{ + */ + +void SysCtrl_DeInit(void); +void SysCtrl_PeripheralClockCmd(uint32_t PeriphClock, FunctionalState NewState); +RESET_REASON_Type SysCtrl_GetWakeupResetReason(void); + +void SysCtrl_WakeupFromIo(uint8_t IO, uint8_t LevelState, FunctionalState NewState); +void SysCtrl_SelectXO(uint8_t XOFreq); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_SYSCTRL_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_uart.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_uart.h new file mode 100644 index 00000000000..caabf5196b0 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_uart.h @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_UART_H +#define BLUENRG1_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "bluenrg_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup UART_Peripheral UART Peripheral + * @{ + */ + +/** @defgroup UART_Exported_Types Exported Types + * @{ + */ + +/** + * @brief Structure definition of UART initialization + */ +typedef struct +{ + uint32_t UART_BaudRate; /*!< This member configures the UART communication baud rate. */ + + uint8_t UART_WordLengthTransmit; /*!< Specifies the number of data bits transmitted in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint8_t UART_WordLengthReceive; /*!< Specifies the number of data bits received in a frame. + This parameter can be a value of @ref UART_Word_Length */ + + uint8_t UART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits */ + + uint8_t UART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity */ + + uint8_t UART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode */ + + uint8_t UART_HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control */ + + FunctionalState UART_FifoEnable; /*!< Specifies whether the FIFO is enabled or disabled. + This parameter can be a value of @ref UART_Fifo_Enable */ +} UART_InitType; + + +/** + * @} + */ + +/** @defgroup UART_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup UART_Word_Length_Definition Word Length Definition + * @{ + */ + +#define UART_WordLength_5b ((uint8_t)0) /*!< 5-bit word length */ +#define UART_WordLength_6b ((uint8_t)1) /*!< 6-bit word length */ +#define UART_WordLength_7b ((uint8_t)2) /*!< 7-bit word length */ +#define UART_WordLength_8b ((uint8_t)3) /*!< 8-bit word length */ + +/* This macro checks if LENGTH is a valid UART word length value */ +#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_5b) || \ + ((LENGTH) == UART_WordLength_6b) || \ + ((LENGTH) == UART_WordLength_7b) || \ + ((LENGTH) == UART_WordLength_8b)) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits_Definition Stop Bits Definition + * @{ + */ + +#define UART_StopBits_1 ((uint8_t)0) /*!< 1 stop bit */ +#define UART_StopBits_2 ((uint8_t)1) /*!< 2 stop bits */ + +/* This macro checks if STOPBITS is a valid UART stop bits value */ +#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \ + ((STOPBITS) == UART_StopBits_2)) +/** + * @} + */ + +/** @defgroup UART_Parity_Definition Parity Definition + * @{ + */ + +#define UART_Parity_No ((uint8_t)0) /*!< No parity */ +#define UART_Parity_Even ((uint8_t)1) /*!< Even parity */ +#define UART_Parity_Odd ((uint8_t)2) /*!< Odd parity */ + +/* This macro checks if PARITY is a valid UART parity value */ +#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \ + ((PARITY) == UART_Parity_Even) || \ + ((PARITY) == UART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup UART_Mode_Definition Mode Definition + * @{ + */ + +#define UART_Mode_Rx ((uint8_t)0x01) /*!< Enables Rx */ +#define UART_Mode_Tx ((uint8_t)0x02) /*!< Enables Tx */ + +/* This macro checks if MODE is a valid UART mode value */ +#define IS_UART_MODE(MODE) ( (MODE)<= 3) + +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control_Definition Hardware Flow Control Definition + * @{ + */ +#define UART_HardwareFlowControl_None ((uint8_t)0x00) /*!< Disable the hardware flow control */ +#define UART_HardwareFlowControl_RTS ((uint8_t)0x01) /*!< Enables the RTS hardware flow control */ +#define UART_HardwareFlowControl_CTS ((uint8_t)0x02) /*!< Enables the CTS hardware flow control */ +#define UART_HardwareFlowControl_RTS_CTS ((uint8_t)0x03) /*!< Enables the RTS and CTS hardware flow control */ + +/* This macro checks if CONTROL is a valid UART hardware flow control value */ +#define IS_UART_HW_FLOW_CONTROL(CONTROL) ( (CONTROL) <= 3 ) + +/** + * @} + */ + + +/** @defgroup UART_Interrupt_Definition Interrupt Definition + * @{ + */ + +#define UART_IT_TXFE ((uint16_t)0x1000) /*!< Tx FIFO empty interrupt */ +#define UART_IT_XO ((uint16_t)0x0800) /*!< XOFF interrupt */ +#define UART_IT_OE ((uint16_t)0x0400) /*!< Overrun error interrupt */ +#define UART_IT_BE ((uint16_t)0x0200) /*!< Break error interrupt */ +#define UART_IT_PE ((uint16_t)0x0100) /*!< Parity error interrupt */ +#define UART_IT_FE ((uint16_t)0x0080) /*!< Framing error interrupt */ +#define UART_IT_RT ((uint16_t)0x0040) /*!< Receive error interrupt */ +#define UART_IT_TX ((uint16_t)0x0020) /*!< Transmit interrupt */ +#define UART_IT_RX ((uint16_t)0x0010) /*!< Receive interrupt */ +#define UART_IT_CTS ((uint16_t)0x0002) /*!< CTS interrupt */ + +/* This macro checks if IT is a valid combination of UART interrupt value */ +#define IS_UART_CONFIG_IT(IT) ((((IT) & (uint16_t)~0x1FF2) == 0x00) && ((IT) != (uint16_t)0x0000)) + + + +/** + * @} + */ + + +/** @defgroup UART_Flags_Definition Flags Definition + * @{ + */ + +#define UART_FLAG_CTS ((uint32_t)0x00000001) /*!< Clear to send flag */ +#define UART_FLAG_BUSY ((uint32_t)0x00000008) /*!< Busy flag */ +#define UART_FLAG_RXFE ((uint32_t)0x00000010) /*!< Receive FIFO empty flag */ +#define UART_FLAG_TXFF ((uint32_t)0x00000020) /*!< Transmit FIFO full flag */ +#define UART_FLAG_RXFF ((uint32_t)0x00000040) /*!< Receive FIFO full flag */ +#define UART_FLAG_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty flag */ + +#define UART_FLAG_FE ((uint32_t)0x80000001) /*!< Framing error flag */ +#define UART_FLAG_PE ((uint32_t)0x80000002) /*!< Parity error flag */ +#define UART_FLAG_BE ((uint32_t)0x80000004) /*!< Break error flag */ +#define UART_FLAG_OE ((uint32_t)0x80000008) /*!< Overrun error flag */ + +/* This macro checks if FLAG is a valid UART flag */ +#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_CTS) || ((FLAG) == UART_FLAG_BUSY) || \ + ((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_TXFF) || \ + ((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFE) || \ + ((FLAG) == UART_FLAG_OE) || ((FLAG) == UART_FLAG_FE) || \ + ((FLAG) == UART_FLAG_PE) || ((FLAG) == UART_FLAG_BE) ) + +/* This macro checks if FLAG is a valid UART clearable flag */ +#define IS_UART_CLEAR_FLAG(FLAG) (((FLAG) == UART_FLAG_FE) || ((FLAG) == UART_FLAG_PE) || \ + ((FLAG) == UART_FLAG_BE) || ((FLAG) == UART_FLAG_OE)) + +/* This macro checks if BAUDRATE is a valid UART baudrate */ +#define IS_UART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) <= 1000000)) + +/* This macro checks if DATA is a valid UART data */ +#define IS_UART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** @defgroup UART_Fifo_Level_Definition FIFO Level Definition + * @{ + */ + +#define FIFO_LEV_1_64 ((uint8_t)0) /*!< FIFO threshold 1/64 */ +#define FIFO_LEV_1_32 ((uint8_t)1) /*!< FIFO threshold 1/32 */ +#define FIFO_LEV_1_16 ((uint8_t)2) /*!< FIFO threshold 1/16 */ +#define FIFO_LEV_1_8 ((uint8_t)3) /*!< FIFO threshold 1/8 */ +#define FIFO_LEV_1_4 ((uint8_t)4) /*!< FIFO threshold 1/4 */ +#define FIFO_LEV_1_2 ((uint8_t)5) /*!< FIFO threshold 1/2 */ +#define FIFO_LEV_3_4 ((uint8_t)6) /*!< FIFO threshold 3/4 */ + +/* This macro checks if TX_FIFO_LEV is a valid Tx FIFO level */ +#define IS_FIFO_LEV(FIFO_LEV) ( ((FIFO_LEV) == FIFO_LEV_1_64) || \ + ((FIFO_LEV) == FIFO_LEV_1_32) || \ + ((FIFO_LEV) == FIFO_LEV_1_16) || \ + ((FIFO_LEV) == FIFO_LEV_1_8) || \ + ((FIFO_LEV) == FIFO_LEV_1_4) || \ + ((FIFO_LEV) == FIFO_LEV_1_2) || \ + ((FIFO_LEV) == FIFO_LEV_3_4)) + +/** + * @} + */ + +/** @defgroup UART_Software_Flow_Control_Mode_Definition Software Flow Control Mode Definition + * @{ + */ +#define NO_SW_FLOW_CTRL ((uint8_t)0) /*!< No software flow control */ +#define SW_FLOW_CTRL_XON1_XOFF1 ((uint8_t)1) /*!< Software flow control XON1 and XOFF1 */ +#define SW_FLOW_CTRL_XON2_XOFF2 ((uint8_t)2) /*!< Software flow control XON2 and XOFF2 */ +#define SW_FLOW_CTRL_ALL_CHARS ((uint8_t)3) /*!< Software flow control XON1 and XOFF1, XON2 and XOFF2 */ + +/* This macro checks if SW_FLOW_CTRL is a valid software flow control value */ +#define IS_SW_FLOW_CTRL(SW_FLOW_CTRL) ( ((SW_FLOW_CTRL) == NO_SW_FLOW_CTRL) || \ + ((SW_FLOW_CTRL) == SW_FLOW_CTRL_XON1_XOFF1) || \ + ((SW_FLOW_CTRL) == SW_FLOW_CTRL_XON2_XOFF2) || \ + ((SW_FLOW_CTRL) == SW_FLOW_CTRL_ALL_CHARS)) +/** + * @} + */ + +/** @defgroup UART_DMA_Requests_Definition DMA Requests Definition + * @{ + */ + +#define UART_DMAReq_Tx ((uint8_t)0x02) +#define UART_DMAReq_Rx ((uint8_t)0x01) + +/* This macro checks if DMAREQ is a valid DMA request value */ +#define IS_UART_DMAREQ(DMAREQ) ((DMAREQ)<(uint8_t)4 && (DMAREQ)!=(uint8_t)0 ) + +/** + * @} + */ + +/** @defgroup UART_Timeout_Definition DMA Timeout + * @{ + */ + +/* This macro checks if VAL is a valid timeout value */ +#define IS_UART_TIMEOUT(VAL) ((VAL) < 0x400000 ) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions Exported Functions + * @{ + */ + +void UART_DeInit(void); +void UART_Init(UART_InitType* UART_InitStruct); +void UART_StructInit(UART_InitType* UART_InitStruct); +void UART_Cmd(FunctionalState NewState); + +uint8_t UART_IsEnabled(void); + +void UART_ITConfig(uint16_t UART_IT, FunctionalState NewState); +void UART_SendData(uint16_t Data); +uint16_t UART_ReceiveData(void); +void UART_BreakCmd(FunctionalState NewState); +void UART_RequestToSendCmd(FunctionalState NewState); +FlagStatus UART_GetFlagStatus(uint32_t UART_FLAG); +void UART_ClearFlag(uint32_t UART_FLAG); +ITStatus UART_GetITStatus(uint16_t UART_IT); +void UART_ClearITPendingBit(uint16_t UART_IT); +void UART_TxFifoIrqLevelConfig(uint8_t UART_TxFifo_Level); +void UART_RxFifoIrqLevelConfig(uint8_t UART_RxFifo_Level); +void UART_RXTimeoutConfig(uint32_t UART_TimeoutMS); +void UART_Oversampling(FunctionalState NewState); +void UART_SwFlowControl(FunctionalState NewState); +void UART_RxSwFlowControlMode(uint8_t UART_RxSwFlowCtrlMode); +void UART_TxSwFlowControlMode(uint8_t UART_TxSwFlowCtrlMode); +void UART_XonAnyBit(FunctionalState NewState); +void UART_SpecialCharDetect(FunctionalState NewState); +void UART_Xon1Char(uint8_t UART_XonChar); +void UART_Xon2Char(uint8_t UART_XonChar); +void UART_Xoff1Char(uint8_t UART_XoffChar); +void UART_Xoff2Char(uint8_t UART_XoffChar); + +void UART_DMACmd(uint8_t UART_DMAReq, FunctionalState NewState); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_UART_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_wdg.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_wdg.h new file mode 100644 index 00000000000..b6555d8b64d --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/BlueNRG1_wdg.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/** + * @file BlueNRG1_WDG.h + * @brief BlueNRG-1,2 Watchdog header file + * + +* \section WDG How tho use the Watchdog functionality? + + In order to use this functionality the best way is to add the watchdog reload in the main loop (and not on the WDG IRQ handler: WDG_Handler()). + User should follow these steps: + + 1: Add a Watchdog initialization function to be called before entering on main loop: (WATCHDOG_TIME is a timeout defined based on the application scenario): + + void WDG_Init(void) + { + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_WDG, ENABLE); + WDG_SetReload(RELOAD_TIME(WATCHDOG_TIME)); + WDG_Enable(); + } + + 2: Just call the reload function inside the main loop: + + while(1) + { + ..... + WDG_SetReload(RELOAD_TIME(WATCHDOG_TIME)); + } + + - NOTE: The option to use the WDG_Handler() it is not mandatory at all, and it is just an implementation choice. If user wants to use this method (not mandatory), then he must clear the pending bit associated to the watchdog (WDG_ClearITPendingBit()). + +**/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_WDG_H +#define BLUENRG1_WDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup WDG_Peripheral WDG Peripheral + * @{ + */ + +/** @defgroup WDG_Exported_Types Exported Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Exported_Constants Exported Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Exported_Functions Exported Functions + * @{ + */ +void WDG_SetWriteAccess(FunctionalState NewState); +FunctionalState WDG_GetWriteAccess(void); +void WDG_SetReload(uint32_t WDG_Reload); +uint32_t WDG_GetCounter(void); +void WDG_Enable(void); +void WDG_DisableReset(void); +void WDG_ITConfig(FunctionalState NewState); +ITStatus WDG_GetITStatus(void); +void WDG_ClearITPendingBit(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_WDG_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/inc/misc.h b/targets/TARGET_STMBLUE/Periph_Driver/inc/misc.h new file mode 100644 index 00000000000..37801094a91 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/inc/misc.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG1_MISC_H +#define BLUENRG1_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "bluenrg_x_device.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup MISC_Peripheral MISC Peripheral + * @{ + */ + +/** @defgroup MISC_Exported_Types Exported Types + * @{ + */ + + +/** + * @brief Structure definition of NVIC initialization + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete BlueNRG1 Device IRQ Channels list, please + refer to BlueNRG1.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 3 */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitType; + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants Exported Constants + * @{ + */ + +/** @defgroup Preemption_Priority_Definitions Preemption Priority Group Definitions + * @{ + */ + +/* IRQ priority high */ +#define HIGH_PRIORITY 1 + +/* IRQ priority medium */ +#define MED_PRIORITY 2 + +/* IRQ priority low */ +#define LOW_PRIORITY 3 + +/* This macro checks if PRIORITY is a valid WriteAccess value */ +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) + + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros Exported Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions Exported Functions + * @{ + */ + +void NVIC_Init(NVIC_InitType* NVIC_InitStruct); +void SystemSleepCmd(FunctionalState NewState); +void SysTick_State(FunctionalState NewState); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG1_MISC_H */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_adc.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_adc.c new file mode 100644 index 00000000000..6e1049a3cb5 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_adc.c @@ -0,0 +1,828 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_adc.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup ADC_Peripheral ADC Peripheral + * @{ + */ + + +/** @defgroup ADC_Private_Types Private Types +* @{ +*/ + +/** +* @} +*/ + + +/** @defgroup ADC_Private_Constants Private Constants +* @{ +*/ +#define ADC_VREF ((float)(2.4)) +#ifdef BLUENRG2_DEVICE +#define ADC_FS_OSR_32_64 ((float)(35442.0)) +#define ADC_FS_OSR_100_200 ((float)(41260.0)) +#else +#define ADC_FS_OSR_32_64 ((float)(16708.0)) +#define ADC_FS_OSR_100_200 ((float)(19450.0)) +#endif +#define ADC_KBATT ((float)(4.36)) +#define ADC_KTEMP ((float)(401.0)) +#define ADC_CTEMP ((float)(267.0)) + +#define ADC_FS_OSR_32_64_SKIP ((float)(32768.0)) +#define ADC_FS_OSR_100_200_SKIP ((float)(38147.0)) + +/** +* @} +*/ + + +/** @defgroup ADC_Private_Macros Private Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Private_Variables Private Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup ADC_Private_Function Private Functions +* @{ +*/ + +#if (HS_SPEED_XTAL==HS_SPEED_XTAL_32MHZ) && (ADC_2411==1) + +/* x = 1: Workaround for running ADC with 32 MHz clock - Run the APB bus @ 16 MHz; + x = 0: Restore the APB bus @ 32 MHz */ + +#define ADC_2411_WORKAROUND(x) ((x == 1) ? (AHBUPCONV->COMMAND = 0x14) : (AHBUPCONV->COMMAND = 0x15)) + +#else /* do nothing: no workaround is needed */ + +#define ADC_2411_WORKAROUND(x) + +#endif + + + +/** +* @brief Convert raw ADC value in converted differential voltage value. +* @param raw_value: ADC raw value +* @retval float: converted differential voltage value +*/ +float ADC_ConvertDifferentialVoltage(int16_t raw_value, uint8_t attenuation) +{ + float pga, raw_value_f, divider; + + if( ADC->CONF_b.SKIP == 1) { + divider = ADC_FS_OSR_32_64_SKIP; + } + else { + divider = ADC_FS_OSR_32_64; + } + + pga = (float)attenuation; + raw_value_f = (float)raw_value; + + ADC_2411_WORKAROUND(1); + + if(ADC->CONF_b.OSR == ADC_OSR_100 || ADC->CONF_b.OSR == ADC_OSR_200) { + if( ADC->CONF_b.SKIP == 1) { + divider = ADC_FS_OSR_100_200_SKIP; + } + else { + divider = ADC_FS_OSR_100_200; + } + } + + ADC_2411_WORKAROUND(0); + + return ((1 + pga) * (raw_value_f / divider) * ADC_VREF); +} + +/** +* @brief Convert raw ADC value in converted single ended voltage value. +* @param raw_value ADC raw value +* @param channel: the selected single channel type +* @param vRef: the configured reference voltage +* @retval float: converted single ended voltage value +*/ +float ADC_ConvertSingleEndedVoltage(int16_t raw_value, uint8_t channel, uint8_t vRef, uint8_t attenuation) +{ + float pga, raw_value_f, divider; + + if( ADC->CONF_b.SKIP == 1) { + divider = ADC_FS_OSR_32_64_SKIP; + } + else { + divider = ADC_FS_OSR_32_64; + } + + pga = (float)attenuation; + raw_value_f = (float)raw_value; + + ADC_2411_WORKAROUND(1); + + if(ADC->CONF_b.OSR == ADC_OSR_100 || ADC->CONF_b.OSR == ADC_OSR_200) { + if( ADC->CONF_b.SKIP == 1) { + divider = ADC_FS_OSR_100_200_SKIP; + } + else { + divider = ADC_FS_OSR_100_200; + } + } + + ADC_2411_WORKAROUND(0); + + if(channel == ADC_Input_AdcPin1) + return ((1 + pga) * (0.6 + ((raw_value_f/divider) * ADC_VREF))); + else + return ((1 + pga) * (0.6 - ((raw_value_f/divider) * ADC_VREF))); +} + + +/** +* @brief Convert raw ADC value in battery level. +* @param raw_value ADC raw value +* @param vRef: the configured reference voltage +* @retval float: converted battery level +*/ +float ADC_ConvertBatterySensor(int16_t raw_value, uint8_t vRef) /* testare al variare di vref */ +{ + return (ADC_KBATT * (ADC_ConvertSingleEndedVoltage(raw_value, ADC_Input_AdcPin2, ADC_ReferenceVoltage_0V6, ADC_Attenuation_0dB))); +} + +/** +* @brief Convert raw ADC value in temperature level in Celsius degrees. +* @param raw_value ADC raw value +* @param vRef: the configured reference voltage +* @retval float: converted temperature level in Celsius degrees +*/ +float ADC_ConvertTemperatureSensor(int16_t raw_value, uint8_t vRef, uint8_t attenuation) +{ + return ((ADC_KTEMP * (ADC_ConvertSingleEndedVoltage(raw_value, ADC_Input_AdcPin2, ADC_ReferenceVoltage_0V6, ADC_Attenuation_0dB))) - ADC_CTEMP); +} +float ADC_ConvertTemperatureSensorFarenait(int16_t raw_value, uint8_t vRef, uint8_t attenuation) +{ + return ((722.0 * (ADC_ConvertSingleEndedVoltage(raw_value, ADC_Input_AdcPin2, ADC_ReferenceVoltage_0V6, ADC_Attenuation_0dB))) - 499.0); +} + +/** +* @} +*/ + + +/** @defgroup ADC_Public_Functions Public Functions +* @{ +*/ + +/** +* @brief Deinitializes ADC peripheral registers to their default reset values. +* @param None +* @retval None +*/ +void ADC_DeInit(void) +{ + ADC_2411_WORKAROUND(1); + + /* Enable ADC reset state */ + ADC->CTRL_b.RESET = SET; + + ADC_2411_WORKAROUND(0); +} + + +/** + * @brief Fills the ADC_InitStruct with default values. + * @param ADC_InitStruct: pointer to an @ref ADC_InitType structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitType* ADC_InitStruct) +{ + /* Set the decimation rate */ + ADC_InitStruct->ADC_OSR = ADC_OSR_200; + + /* Select the input source */ + ADC_InitStruct->ADC_Input = ADC_Input_None; + + /* Set the reference voltage */ + ADC_InitStruct->ADC_ReferenceVoltage = ADC_ReferenceVoltage_0V6; + + /* Set the conversion mode */ + ADC_InitStruct->ADC_ConversionMode = ADC_ConversionMode_Single; + + /* Set the attenuation */ + ADC_InitStruct->ADC_Attenuation = ADC_Attenuation_0dB; +} + + +/** +* @brief Initializes the ADC peripheral according to the specified parameters +* in the ADC_InitStruct. +* @param ADC_InitStruct: pointer to an @ref ADC_InitType structure that contains +* the configuration information for the ADC peripheral. +* @retval None +*/ +void ADC_Init(ADC_InitType* ADC_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_ADC_OSR(ADC_InitStruct->ADC_OSR)); + assert_param(IS_ADC_INPUT(ADC_InitStruct->ADC_Input)); + assert_param(IS_ADC_CONVERSIONMODE(ADC_InitStruct->ADC_ConversionMode)); + assert_param(IS_ADC_ATTENUATION(ADC_InitStruct->ADC_Attenuation)); + assert_param(IS_ADC_REFERENCEVOLTAGE(ADC_InitStruct->ADC_ReferenceVoltage)); + + ADC_2411_WORKAROUND(1); + + /* Set the decimation rate */ + ADC->CONF_b.OSR = ADC_InitStruct->ADC_OSR; + + /* Select the input source */ + if(ADC_InitStruct->ADC_Input == ADC_Input_Microphone) { + ADC->CONF_b.MIC_SEL = SET; + } + else { + ADC->CONF_b.MIC_SEL = RESET; + ADC->CONF_b.CHSEL = ADC_InitStruct->ADC_Input; + } + + /* Set the reference voltage */ + ADC->CONF_b.REFSEL = ADC_InitStruct->ADC_ReferenceVoltage; + + /* Set the conversion mode */ + if(ADC_InitStruct->ADC_ConversionMode == ADC_ConversionMode_Continuous) { + ADC->CONF_b.CONT = SET; + } + else { + ADC->CONF_b.CONT = RESET; + } + + /* Set the attenuation */ + ADC->CONF_b.PGASEL = ADC_InitStruct->ADC_Attenuation; + + ADC_2411_WORKAROUND(0); +} + + +/** +* @brief Enable disable the ADC conversion. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + ADC_2411_WORKAROUND(1); + + if(NewState==ENABLE) { + if(ADC->CONF_b.MIC_SEL) { + ADC->CTRL_b.MIC_ON = SET; + } + else { + ADC->CTRL_b.SWSTART = SET; + ADC->CTRL_b.ON = SET; + } + } + else { + ADC->CTRL_b.STOP = SET; + } + + ADC_2411_WORKAROUND(0); +} + + +/** +* @brief Enable disable the ADC DMA feature. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_DmaCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + ADC_2411_WORKAROUND(1); + + if(NewState==ENABLE) { + ADC->CTRL_b.DMA_EN = SET; + } + else { + ADC->CTRL_b.DMA_EN = RESET; + } + + ADC_2411_WORKAROUND(0); +} + + +/** +* @brief Specified the ADC input channel. +* @param adc_input: Specifies the input used for the conversion. +* This parameter can be a value of @ref ADC_Input. +* @retval None +*/ +void ADC_SelectInput(uint8_t AdcInput) +{ + /* Check the parameter */ + assert_param(IS_ADC_INPUT(AdcInput)); + + ADC_2411_WORKAROUND(1); + + ADC->CONF_b.CHSEL = AdcInput; + + ADC_2411_WORKAROUND(0); +} + +/** +* @brief Enable disable the ADC calibration procedure. +* If the automatic calibration must be enabled, +* call the following APIs: +* ADC_AutoOffsetUpdate(ENABLE); +* ADC_Calibration(ENABLE); +* If the automatic calibration must be disabled, +* call the following APIs: +* ADC_AutoOffsetUpdate(DISABLE); +* ADC_Calibration(DISABLE); +* +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_Calibration(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + ADC_2411_WORKAROUND(1); + + if(NewState==ENABLE) { + ADC->CTRL_b.CALEN = SET; + } + else { + ADC->CTRL_b.RSTCALEN = SET; + ADC->CTRL_b.CALEN = RESET; + } + + ADC_2411_WORKAROUND(0); +} + + +/** +* @brief Enable disable the ADC automatic update of the offset. +* If the automatic calibration must be enabled, +* call the following APIs: +* ADC_AutoOffsetUpdate(ENABLE); +* ADC_Calibration(ENABLE); +* If the automatic calibration must be disabled, +* call the following APIs: +* ADC_AutoOffsetUpdate(DISABLE); +* ADC_Calibration(DISABLE); +* +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_AutoOffsetUpdate(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + ADC_2411_WORKAROUND(1); + + if(NewState==ENABLE) { + ADC->CTRL_b.AUTO_OFFSET = SET; + } + else { + ADC->CTRL_b.AUTO_OFFSET = RESET; + } + + ADC_2411_WORKAROUND(0); +} + + +/** +* @brief Enable disable the ADC threshold check. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_ThresholdCheck(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + ADC_2411_WORKAROUND(1); + + if(NewState==ENABLE) { + ADC->CTRL_b.ENAB_COMP = SET; + } + else { + ADC->CTRL_b.ENAB_COMP = RESET; + } + + ADC_2411_WORKAROUND(0); +} + + +/** +* @brief Configure the ADC threshold. +* @param ThresholdLow: ADC threshold low value. +* ThresholdHigh: ADC threshold high value. +* @retval None +*/ +void ADC_ThresholdConfig(uint32_t ThresholdLow, uint32_t ThresholdHigh) +{ + ADC_2411_WORKAROUND(1); + + ADC->THRESHOLD_LO = ThresholdLow; + ADC->THRESHOLD_HI = ThresholdHigh; + + ADC_2411_WORKAROUND(0); +} + +/** +* @brief Get the ADC offset value previously calculated +* internally with the auto calibration. +* @param None +* @retval uint16_t: Offset for correction of converter data. +*/ +uint16_t ADC_GetOffset(void) +{ + uint16_t value; + + ADC_2411_WORKAROUND(1); + + /* Conversion done with filter bypassed */ + if(ADC->CONF_b.SKIP == 0) { + value = READ_REG(ADC->OFFSET_MSB); + } + /* Conversion done with filter not bypassed */ + else { + value = READ_REG(ADC->OFFSET_LSB); + } + + ADC_2411_WORKAROUND(0); + + return value; +} + + +/** +* @brief Set the ADC offset value previously calculated +* internally with the auto calibration. +* The AUTO_OFFSET will perform this operation automatically. +* @param int32_t: Offset for correction of converter data. +* @retval None +*/ +void ADC_SetOffset(uint16_t Offset) +{ + ADC_2411_WORKAROUND(1); + + /* Conversion done with filter bypassed */ + if(ADC->CONF_b.SKIP == 0) { + ADC->OFFSET_MSB = Offset; + } + /* Conversion done with filter not bypassed */ + else { + ADC->OFFSET_LSB = Offset; + } + + ADC_2411_WORKAROUND(0); +} + +/** +* @brief Configure the ADC conversion mode. +* @param cConvertionMode: the value can be +* @arg ADC_ConversionMode_Single single shot ADC conversion +* @arg ADC_ConversionMode_Continuous continuous ADC conversion +* @retval None +*/ +void ADC_ConversionMode(uint8_t ConvertionMode) +{ + /* Check the parameters */ + assert_param(IS_ADC_CONVERSIONMODE(ConvertionMode)); + + ADC_2411_WORKAROUND(1); + + if(ConvertionMode==ADC_ConversionMode_Continuous) { + ADC->CONF_b.CONT = SET; + } + else { + ADC->CONF_b.CONT = RESET; + } + + ADC_2411_WORKAROUND(0); + +} + +/** +* @brief Select the frequency of the clock signal for an external MEMS microphone (through IO0) +* @param Frequency: the value can be +* @arg ADC_MIC_800KH Enable the 800 kHz through IO0 for external MEMS microphone +* @arg ADC_MIC_1600KH Enable the 1.6 MHz through IO0 for external MEMS microphone +* @retval None +*/ +void ADC_SelectFrequencyMic(uint8_t Frequency) +{ + /* Check the parameters */ + assert_param(IS_ADC_MIC_FREQ_SEL(Frequency)); + + ADC_2411_WORKAROUND(1); + + /* Check the value of Frequency */ + if(Frequency == ADC_MIC_800KHZ) { + ADC->CONF_b.DIG_FILT_CLK = RESET; + } + else if(Frequency == ADC_MIC_1600KHZ) { + ADC->CONF_b.DIG_FILT_CLK = SET; + } + + ADC_2411_WORKAROUND(0); + +} + + +/** +* @brief Get the ADC flags. +* The read operation will clear the flags. +* @param none +* @retval uint8_t: the ADC flags as bitmask 0x0000b3b2b1b0: +* b3: ADC_FLAG_WDG +* b2: ADC_FLAG_EOC +* b1: ADC_FLAG_BUSY +* b0: ADC_FLAG_CAL. +*/ +uint8_t ADC_GetFlags(void) +{ + uint8_t flags; + + ADC_2411_WORKAROUND(1); + + flags = (ADC->IRQRAW & 0x0F); + + ADC_2411_WORKAROUND(0); + + return flags; +} + +/** +* @brief Get the status flag of ADC. +* The read operation will clear the flags. +* If more than one status flag must be read, +* then the function must be ADC_GetFlags(). +* @param ADC_Flag: the value can be +* @arg ADC_FLAG_CAL ADC End of Calibration flag +* @arg ADC_FLAG_BUSY ADC busy flag +* @arg ADC_FLAG_EOC ADC End of Conversion flag +* @arg ADC_FLAG_WDG ADC ADV value within set threshold +* @retval FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. +*/ +FlagStatus ADC_GetFlagStatus(uint8_t ADC_Flag) +{ + FlagStatus status; + + /* Check the parameters */ + assert_param(IS_ADC_GET_FLAG(ADC_Flag)); + + ADC_2411_WORKAROUND(1); + + /* Check the status of the specified SPI flag */ + if (READ_BIT(ADC->IRQRAW, ADC_Flag) != (uint16_t)RESET) { + /* SPI_FLAG is set */ + status = SET; + } + else { + /* SPI_FLAG is reset */ + status = RESET; + } + + ADC_2411_WORKAROUND(0); + + return status; +} + +/** +* @brief Get the status of the masked IT flag. +* The read operation will clear the flags. +* If more than one status flag must be read, +* then the function must be ADC_GetFlags(). +* @param ADC_Flag: the value can be +* @arg ADC_FLAG_CAL ADC End of Calibration flag +* @arg ADC_FLAG_BUSY ADC busy flag +* @arg ADC_FLAG_EOC ADC End of Conversion flag +* @arg ADC_FLAG_WDG ADC ADV value within set threshold +* @retval ITStatus: functional state @ref ITStatus +* This parameter can be: SET or RESET. +*/ +ITStatus ADC_GetITStatus(uint8_t ADC_Flag) +{ + ITStatus status; + + /* Check the parameters */ + assert_param(IS_ADC_GET_FLAG(ADC_Flag)); + + ADC_2411_WORKAROUND(1); + + /* Check the status of the specified SPI interrupt */ + if (READ_BIT(ADC->IRQSTAT, ADC_Flag) != (uint16_t)RESET) { + /* ADC_Flag is set */ + status = SET; + } + else { + /* SPI_IT is reset */ + status = RESET; + } + + ADC_2411_WORKAROUND(0); + + return status; +} + + + +/** +* @brief Enable disable the ADC IT flag. +* @param ADC_Flag: the value can be +* @arg ADC_FLAG_CAL ADC End of Calibration flag +* @arg ADC_FLAG_BUSY ADC busy flag +* @arg ADC_FLAG_EOC ADC End of Conversion flag +* @arg ADC_FLAG_WDG ADC ADV value within set threshold +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_ITConfig(uint8_t ADC_Flag, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_GET_FLAG(ADC_Flag)); + + ADC_2411_WORKAROUND(1); + + if (NewState != DISABLE) { + /* Enable the selected SPI interrupts */ + CLEAR_BIT(ADC->IRQMASK, ADC_Flag); + } + else { + /* Disable the selected SPI interrupts */ + SET_BIT(ADC->IRQMASK, ADC_Flag); + } + + ADC_2411_WORKAROUND(0); +} + +/** +* @brief Get the ADC converted value in Volt. +* @param dataType: the selected channel, this value can be +* @arg ADC_Input_AdcPin1 data from ADC pin1 +* @arg ADC_Input_AdcPin2 data from ADC pin2 +* @arg ADC_Input_AdcPin12 data from ADC pin12 +* @arg ADC_Input_Internal0V60V6 data from internal 0.6V +* @arg ADC_Input_Internal1V20V0 data from internal 1.2V +* @arg ADC_Input_BattSensor data from battery sensor +* @arg ADC_Input_TempSensor data from temperature sensor +* @param vRef: voltage reference configured, the value can be +* @arg ADC_ReferenceVoltage_0V6 Vref is 0.6 V +* @retval Converted ADC value in Volt +*/ +float ADC_GetConvertedData(uint8_t DataType, uint8_t Vref) +{ + int16_t raw_value; + uint8_t pga_reg; + + /* Check the parameters */ + assert_param(IS_ADC_INPUT(DataType)); + assert_param(IS_ADC_REFERENCEVOLTAGE(Vref)); + + ADC_2411_WORKAROUND(1); + + raw_value = (int16_t)ADC_GetRawData(); + pga_reg = ADC->CONF_b.PGASEL; + + ADC_2411_WORKAROUND(0); + + if(DataType==ADC_Input_AdcPin1) { + return ADC_ConvertSingleEndedVoltage(raw_value, (uint8_t)ADC_Input_AdcPin1, Vref, pga_reg); + } + else if(DataType==ADC_Input_AdcPin2) { + return ADC_ConvertSingleEndedVoltage(raw_value, (uint8_t)ADC_Input_AdcPin2, Vref, pga_reg); + } + else if(DataType==ADC_Input_AdcPin12 || DataType==ADC_Input_Internal0V60V6 || DataType==ADC_Input_Internal1V20V0) { + return ADC_ConvertDifferentialVoltage(raw_value, pga_reg); + } + else if(DataType==ADC_Input_BattSensor) { + return ADC_ConvertBatterySensor(raw_value, Vref); + } + else if(DataType==ADC_Input_TempSensor) { + return ADC_ConvertTemperatureSensor(raw_value, Vref, pga_reg); + } + return raw_value; +} + + +/** +* @brief Get the ADC raw value. +* @param None +* @retval ADC raw value +*/ +uint16_t ADC_GetRawData(void) +{ + uint16_t value; + + ADC_2411_WORKAROUND(1); + + /* Conversion done with filter bypassed */ + if(ADC->CONF_b.SKIP == 0) { + value = READ_REG(ADC->DATA_CONV_MSB); + } + /* Conversion done with filter not bypassed */ + else { + value = READ_REG(ADC->DATA_CONV_LSB); + } + + ADC_2411_WORKAROUND(0); + + return value; +} + + +/** +* @brief Enable/disable the COMP filter. +* This operation could be useful to speed up the conversion +* for signal at low frequency. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void ADC_Filter(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + ADC_2411_WORKAROUND(1); + + /* If ENABLE the filter, then reset the SKIP bifield */ + if(NewState==ENABLE) { + ADC->CONF_b.SKIP = RESET; + } + + /* If DISABLE the filter, then set the SKIP bifield */ + else { + ADC->CONF_b.SKIP = SET; + } + + ADC_2411_WORKAROUND(0); +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_dma.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_dma.c new file mode 100644 index 00000000000..03facf40d49 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_dma.c @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_dma.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @defgroup DMA_Peripheral DMA Peripheral + * @{ + */ + + +/** @defgroup DMA_Private_TypesDefinitions Private Type Definitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_Defines Private Defines +* @{ +*/ +/* DMA registers Masks */ +#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) + +/** +* @} +*/ + +/** @defgroup DMA_Private_Macros Private Macros +* @{ +*/ + +/* DMA Channelx interrupt pending bit masks */ +#define DMA_CHANNEL0_FLAG_MASK ((uint32_t)(DMA_FLAG_GL0 | DMA_FLAG_TC0 | DMA_FLAG_HT0 | DMA_FLAG_TE0)) +#define DMA_CHANNEL1_FLAG_MASK ((uint32_t)(DMA_FLAG_GL1 | DMA_FLAG_TC1 | DMA_FLAG_HT1 | DMA_FLAG_TE1)) +#define DMA_CHANNEL2_FLAG_MASK ((uint32_t)(DMA_FLAG_GL2 | DMA_FLAG_TC2 | DMA_FLAG_HT2 | DMA_FLAG_TE2)) +#define DMA_CHANNEL3_FLAG_MASK ((uint32_t)(DMA_FLAG_GL3 | DMA_FLAG_TC3 | DMA_FLAG_HT3 | DMA_FLAG_TE3)) +#define DMA_CHANNEL4_FLAG_MASK ((uint32_t)(DMA_FLAG_GL4 | DMA_FLAG_TC4 | DMA_FLAG_HT4 | DMA_FLAG_TE4)) +#define DMA_CHANNEL5_FLAG_MASK ((uint32_t)(DMA_FLAG_GL5 | DMA_FLAG_TC5 | DMA_FLAG_HT5 | DMA_FLAG_TE5)) +#define DMA_CHANNEL6_FLAG_MASK ((uint32_t)(DMA_FLAG_GL6 | DMA_FLAG_TC6 | DMA_FLAG_HT6 | DMA_FLAG_TE6)) +#define DMA_CHANNEL7_FLAG_MASK ((uint32_t)(DMA_FLAG_GL7 | DMA_FLAG_TC7 | DMA_FLAG_HT7 | DMA_FLAG_TE7)) + + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA_CH0) || \ + ((PERIPH) == DMA_CH1) || \ + ((PERIPH) == DMA_CH2) || \ + ((PERIPH) == DMA_CH3) || \ + ((PERIPH) == DMA_CH4) || \ + ((PERIPH) == DMA_CH5) || \ + ((PERIPH) == DMA_CH6) || \ + ((PERIPH) == DMA_CH7)) +/** +* @} +*/ + +/** @defgroup DMA_Private_Variables Private Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_FunctionPrototypes Private Function Prototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup DMA_Private_Functions Private Functions +* @{ +*/ + + + +/** +* @} +*/ + +/** @defgroup DMA_Public_Functions Public Functions +* @{ +*/ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_CH_Type* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR_b.EN = RESET; + + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA_CH1) + { + /* Reset interrupt pending bits for DMA Channel1 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL1_FLAG_MASK); + } + else if (DMAy_Channelx == DMA_CH2) + { + /* Reset interrupt pending bits for DMA Channel2 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL2_FLAG_MASK); + } + else if (DMAy_Channelx == DMA_CH3) + { + /* Reset interrupt pending bits for DMA Channel3 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL3_FLAG_MASK); + } + else if (DMAy_Channelx == DMA_CH4) + { + /* Reset interrupt pending bits for DMA Channel4 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL4_FLAG_MASK); + } + else if (DMAy_Channelx == DMA_CH5) + { + /* Reset interrupt pending bits for DMA Channel5 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL5_FLAG_MASK); + } + else if (DMAy_Channelx == DMA_CH6) + { + /* Reset interrupt pending bits for DMA Channel6 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL6_FLAG_MASK); + } + else if (DMAy_Channelx == DMA_CH7) + { + /* Reset interrupt pending bits for DMA Channel7 */ + SET_BIT(DMA->IFCR, DMA_CHANNEL7_FLAG_MASK); + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitType structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_CH_Type* DMAy_Channelx, DMA_InitType* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_MASK; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct: pointer to a DMA_InitType structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitType* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_CH_Type* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR_b.EN = SET; + } + else { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR_b.EN = RESET; + } +} + + +/** + * @brief Enables or disables the specified DMA ADC Channel. + * @param DMA_AdcChannel: ADC channel from 0 to 7. + * @param NewState: new state of the DMA ADC Channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_SelectAdcChannel(uint8_t DMA_AdcChannel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ADC_CH(DMA_AdcChannel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the selected of DMA ADC Channel */ + SET_BIT(CKGEN_SOC->DMA_CONFIG, DMA_AdcChannel); + } + else { + /* Disable the selected of DMA ADC Channel */ + CLEAR_BIT(CKGEN_SOC->DMA_CONFIG, DMA_AdcChannel); + } +} + + +/** + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA to select the DMA Channel. + * @param DataNumber: The number of data units in the current DMAy Channelx + * transfer. + * @note This function can only be used when the DMAy_Channelx is disabled. + * @retval None. + */ +void DMA_SetCurrDataCounter(DMA_CH_Type* DMAy_Channelx, uint16_t DataNumber) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = (uint32_t)DataNumber; +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_CH_Type* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 to select the DMA and + * x can be 1 to 7 for DMA to select the DMA Channel. + * @param DMA_Flag: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_Flag_TC: Transfer complete interrupt mask + * @arg DMA_Flag_HT: Half transfer interrupt mask + * @arg DMA_Flag_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_FlagConfig(DMA_CH_Type* DMAy_Channelx, uint32_t DMA_Flag, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_FLAG(DMA_Flag)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the selected DMA interrupts */ + SET_BIT(DMAy_Channelx->CCR, DMA_Flag); + } + else { + /* Disable the selected DMA interrupts */ + CLEAR_BIT(DMAy_Channelx->CCR, DMA_Flag); + } +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_Flag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA_FLAG_GL1: DMA Channel1 global flag. + * @arg DMA_FLAG_TC1: DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1: DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1: DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2: DMA Channel2 global flag. + * @arg DMA_FLAG_TC2: DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2: DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2: DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3: DMA Channel3 global flag. + * @arg DMA_FLAG_TC3: DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3: DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3: DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4: DMA Channel4 global flag. + * @arg DMA_FLAG_TC4: DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4: DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4: DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5: DMA Channel5 global flag. + * @arg DMA_FLAG_TC5: DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5: DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5: DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6: DMA Channel6 global flag. + * @arg DMA_FLAG_TC6: DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6: DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6: DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7: DMA Channel7 global flag. + * @arg DMA_FLAG_TC7: DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7: DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7: DMA Channel7 transfer error flag. + * + * @note + * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags + * relative to the same channel is set (Transfer Complete, Half-transfer + * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or + * DMAy_FLAG_TEx). + * + * @retval The new state of DMA_Flag (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_Flag) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_CH_FLAG(DMA_Flag)); + + /* Get DMA ISR register value */ + tmpreg = DMA->ISR; + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_Flag) != (uint32_t)RESET) + { + /* DMA_Flag is set */ + return SET; + } + else + { + /* DMA_Flag is reset */ + return RESET; + } + +} + + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_Flag: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA_FLAG_GL1: DMA Channel1 global flag. + * @arg DMA_FLAG_TC1: DMA Channel1 transfer complete flag. + * @arg DMA_FLAG_HT1: DMA Channel1 half transfer flag. + * @arg DMA_FLAG_TE1: DMA Channel1 transfer error flag. + * @arg DMA_FLAG_GL2: DMA Channel2 global flag. + * @arg DMA_FLAG_TC2: DMA Channel2 transfer complete flag. + * @arg DMA_FLAG_HT2: DMA Channel2 half transfer flag. + * @arg DMA_FLAG_TE2: DMA Channel2 transfer error flag. + * @arg DMA_FLAG_GL3: DMA Channel3 global flag. + * @arg DMA_FLAG_TC3: DMA Channel3 transfer complete flag. + * @arg DMA_FLAG_HT3: DMA Channel3 half transfer flag. + * @arg DMA_FLAG_TE3: DMA Channel3 transfer error flag. + * @arg DMA_FLAG_GL4: DMA Channel4 global flag. + * @arg DMA_FLAG_TC4: DMA Channel4 transfer complete flag. + * @arg DMA_FLAG_HT4: DMA Channel4 half transfer flag. + * @arg DMA_FLAG_TE4: DMA Channel4 transfer error flag. + * @arg DMA_FLAG_GL5: DMA Channel5 global flag. + * @arg DMA_FLAG_TC5: DMA Channel5 transfer complete flag. + * @arg DMA_FLAG_HT5: DMA Channel5 half transfer flag. + * @arg DMA_FLAG_TE5: DMA Channel5 transfer error flag. + * @arg DMA_FLAG_GL6: DMA Channel6 global flag. + * @arg DMA_FLAG_TC6: DMA Channel6 transfer complete flag. + * @arg DMA_FLAG_HT6: DMA Channel6 half transfer flag. + * @arg DMA_FLAG_TE6: DMA Channel6 transfer error flag. + * @arg DMA_FLAG_GL7: DMA Channel7 global flag. + * @arg DMA_FLAG_TC7: DMA Channel7 transfer complete flag. + * @arg DMA_FLAG_HT7: DMA Channel7 half transfer flag. + * @arg DMA_FLAG_TE7: DMA Channel7 transfer error flag. + * + * @note + * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags + * relative to the same channel (Transfer Complete, Half-transfer Complete and + * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). + * + * @retval None + */ +void DMA_ClearFlag(uint32_t DMA_Flag) +{ + /* Check the parameters */ + assert_param(IS_DMA_CH_FLAG(DMA_Flag)); + + /* Clear the selected DMA flags */ + DMA->IFCR = DMA_Flag; + +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_flash.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_flash.c new file mode 100644 index 00000000000..4663fa70cfd --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_flash.c @@ -0,0 +1,374 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_flash.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver +* @{ +*/ + +/** @defgroup FLASH_Peripheral FLASH Peripheral +* @{ +*/ + +/** @defgroup FLASH_Private_TypesDefinitions Private Types Definitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Defines Private Defines +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Macros Private Macros +* @{ +*/ + + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Variables Private Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Private_Functions Private Functions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup FLASH_Public_Functions Public Functions +* @{ +*/ + + + +/** +* @brief Erases a specified flash page. +* @param PageNumber: the page number. +* @retval None +*/ +void FLASH_ErasePage(uint16_t PageNumber) +{ + uint16_t pageAddress; + + assert_param(IS_PAGE_NUMBER(PageNumber)); + + /* Lock word to avoid undesired FLASH operation */ + if (flash_sw_lock != FLASH_UNLOCK_WORD) + return; + + pageAddress = (PageNumber * N_BYTES_PAGE)>>2; + + /* Clear IRQ */ + FLASH->IRQSTAT = 0x3F; + + /* Write the page address */ + FLASH->ADDRESS = pageAddress; + + /* Write the ERASE command */ + FLASH->COMMAND = FLASH_ERASE; + + FLASH_WaitCmdDone(); + + /* Verify */ + // return; +} + +/** +* @brief Erases all main Flash. +* @param None +* @retval None +*/ +void FLASH_EraseAllFlash(void) +{ + /* Lock word to avoid undesired FLASH operation */ + if (flash_sw_lock != FLASH_UNLOCK_WORD) + return; + + /* Clear IRQ */ + FLASH->IRQSTAT = 0x3F; + + /* Write the MASSERASE command */ + FLASH->COMMAND = FLASH_MASSERASE; + + FLASH_WaitCmdDone(); + +} + +/** +* @brief Flash read 32 bits. +* @param Address: address to read. + Address must be word aligned. +* @retval Data read +*/ +uint32_t FLASH_ReadWord(uint32_t Address) +{ + assert_param(IS_FLASH_ADDRESS(Address)); + + return (*((volatile uint32_t*)(Address))); +} + +/** +* @brief Flash read 8 bits. +* @param Address: address to write. +* @retval Data read +*/ +uint8_t FLASH_ReadByte(uint32_t Address) +{ + assert_param(IS_FLASH_ADDRESS(Address)); + + return (*((volatile uint8_t*)(Address))); +} + +/** +* @brief Flash write 32 bits. +* @param Address: address to write +* @param Data: word to write +* @retval None +*/ +void FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Lock word to avoid undesired FLASH operation */ + if (flash_sw_lock != FLASH_UNLOCK_WORD) + return; + + /* Clear IRQ */ + FLASH->IRQSTAT = 0x3F; + + /* Write the page address */ + FLASH->ADDRESS = Address>>2; + + /* Write the data to program */ + FLASH->DATA0 = Data; + + /* Write the WRITE command */ + FLASH->COMMAND = FLASH_WRITE; + + FLASH_WaitCmdDone(); + + /* Verify */ + // return ; +} + +/** +* @brief Flash write 32 bits. +* @param Address: address to write +* @param Data: pointer to an array of 4 words to write +* @retval None +*/ +void FLASH_ProgramWordBurst(uint32_t Address, uint32_t* Data) +{ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* Lock word to avoid undesired FLASH operation */ + if (flash_sw_lock != FLASH_UNLOCK_WORD) + return; + + /* Clear IRQ */ + FLASH->IRQSTAT = 0x3F; + + /* Write the page address */ + FLASH->ADDRESS = Address>>2; + + /* Write the data to program */ + FLASH->DATA0 = Data[0]; + FLASH->DATA1 = Data[1]; + FLASH->DATA2 = Data[2]; + FLASH->DATA3 = Data[3]; + + /* Write the BURSTWRITE command */ + FLASH->COMMAND = FLASH_BURSTWRITE; + + FLASH_WaitCmdDone(); + + /* Verify */ + // return ; +} + +/** +* @brief Flash Lock +* @param None +* @retval None +*/ +void FLASH_Lock(void) +{ + flash_sw_lock = FLASH_LOCK_WORD; +} + +/** +* @brief Flash Unlock +* @param None +* @retval None +*/ +void FLASH_Unlock(void) +{ + flash_sw_lock = FLASH_UNLOCK_WORD; +} + +/** +* @brief Wait loop for CMDDONE status +* @param None +* @retval None +*/ +void FLASH_WaitCmdDone(void) +{ + /* Waits for Command Done */ + while(FLASH->IRQRAW_b.CMDDONE != SET); +} + + +/** +* @brief Clear CMDDONE flag +* @param None +* @retval None +*/ +void FLASH_ClearCmdDone(void) +{ + /* Clear the CMDDONE flag */ + SET_BIT(FLASH->IRQSTAT, Flash_CMDDONE); +} + + + +/** +* @brief Enables or disables the specified flash interrupts. +* @param FlashFlag: the value can be +* @arg Flash_CMDDONE Flash command done +* @arg Flash_CMDSTART Flash command start +* @arg Flash_CMDERR Flash command error +* @arg Flash_ILLCMD Flash illegal command written +* @arg Flash_READOK Flash mass read was OK +* @arg Flash_FLNREADY Flash not ready (sleep) +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void FLASH_ITConfig(uint8_t FlashFlag, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_FLAG(FlashFlag)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + SET_BIT(FLASH->IRQMASK, FlashFlag); + } + else if (NewState == DISABLE) { + CLEAR_BIT(FLASH->IRQMASK, FlashFlag); + } +} + + +/** +* @brief Clears the specific flash pending IT bit. +* @param FlashFlag: the FLASH flag to clear, this can be +* @arg Flash_CMDDONE Flash command done +* @arg Flash_CMDSTART Flash command start +* @arg Flash_CMDERR Flash command error +* @arg Flash_ILLCMD Flash illegal command written +* @arg Flash_READOK Flash mass read was OK +* @arg Flash_FLNREADY Flash not ready (sleep) +* @retval None +*/ +void FLASH_ClearITPendingBit(uint8_t FlashFlag) +{ + assert_param(IS_FLASH_FLAG(FlashFlag)) ; + + /* Clear the flags */ + FLASH->IRQSTAT = FlashFlag; +} + + +/** +* @brief Checks whether the specified FLASH raw flag is set or not. +* @param FlashFlag: the FLASH flag to check, this can be +* @arg Flash_CMDDONE Flash command done +* @arg Flash_CMDSTART Flash command start +* @arg Flash_CMDERR Flash command error +* @arg Flash_ILLCMD Flash illegal command written +* @arg Flash_READOK Flash mass read was OK +* @arg Flash_FLNREADY Flash not ready (sleep) +* @retval FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. +*/ +FlagStatus FLASH_GetFlagStatus(uint8_t FlashFlag) +{ + /* Check the parameters */ + assert_param(IS_FLASH_FLAG(FlashFlag)); + + if((FLASH->IRQRAW & FlashFlag) != (uint16_t)RESET) { + return SET; + } + else { + return RESET; + } +} + +/** +* @brief Clears the specific flash pending flags. +* @param FlashFlag: the FLASH flag to clear, this can be +* @arg Flash_CMDDONE Flash command done +* @arg Flash_CMDSTART Flash command start +* @arg Flash_CMDERR Flash command error +* @arg Flash_ILLCMD Flash illegal command written +* @arg Flash_READOK Flash mass read was OK +* @arg Flash_FLNREADY Flash not ready (sleep) +* @retval None +*/ +void FLASH_ClearFlag(uint8_t FlashFlag) +{ + assert_param(IS_FLASH_FLAG(FlashFlag)) ; + + /* Clear the flags */ + FLASH->IRQSTAT = FlashFlag; +} + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_gpio.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_gpio.c new file mode 100644 index 00000000000..4dc6fefe9ee --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_gpio.c @@ -0,0 +1,522 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_gpio.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver +* @{ +*/ + +/** @addtogroup GPIO_Peripheral GPIO Peripheral +* @{ +*/ + +/** @defgroup GPIO_Private_TypesDefinitions Private Type Definitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Defines Private Defines +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Macros Private Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Variables Private Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_FunctionPrototypes Private Function Prototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup GPIO_Private_Functions Private Functions +* @{ +*/ + + + +/** +* @} +*/ + +/** @defgroup GPIO_Public_Functions Public Functions +* @{ +*/ + +/** +* @brief Deinitializes the GPIO peripheral registers to their default reset values. +* @param None +* @retval None +*/ +void GPIO_DeInit(void) +{ + /* Set all GPIO registers to default/reset configuration */ + GPIO->OEN = 0x00000000; + GPIO->PE = 0x03FFFFFF; + GPIO->DS = 0x00000000; + GPIO->IS = 0x00000000; + GPIO->IBE = 0x00000000; + GPIO->IEV = 0x00000000; + GPIO->IE = 0x00000000; + GPIO->IC = 0xFFFFFFFF; + GPIO->MODE0 = 0x00000000; + GPIO->MODE1 = 0x00000110; + GPIO->MFTX = 0x00000000; +} + + +/** +* @brief Initializes the GPIO peripheral according to the specified +* parameters in the GPIO_InitStruct. +* @param GPIO_InitStruct: pointer to a @ref GPIO_InitType structure that +* contains the configuration information for the specified GPIO peripheral. +* @retval None +*/ +void GPIO_Init(GPIO_InitType* GPIO_InitStruct) +{ + uint8_t tmp; + + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_FUNCTIONAL_STATE(GPIO_InitStruct->GPIO_Pull)); + assert_param(IS_FUNCTIONAL_STATE(GPIO_InitStruct->GPIO_HighPwr)); + + /* IO12 and IO13 cannot be programmed in output mode */ + assert_param( ((GPIO_InitStruct->GPIO_Pin & GPIO_Pin_12) != GPIO_Pin_12) || (GPIO_InitStruct->GPIO_Mode != GPIO_Output)); + assert_param( ((GPIO_InitStruct->GPIO_Pin & GPIO_Pin_13) != GPIO_Pin_13) || (GPIO_InitStruct->GPIO_Mode != GPIO_Output)); + + + /* Configure the IO mode */ + if(GPIO_InitStruct->GPIO_Mode == GPIO_Input) { + CLEAR_BIT(GPIO->OEN, GPIO_InitStruct->GPIO_Pin); + } + else if(GPIO_InitStruct->GPIO_Mode == GPIO_Output) { + GPIO_InitStruct->GPIO_Mode = GPIO_Input; + SET_BIT(GPIO->OEN, GPIO_InitStruct->GPIO_Pin); + } + + for(uint8_t i = 0; i < GPIO_PIN_COUNT; i++) { + tmp = (uint8_t)((GPIO_InitStruct->GPIO_Pin>>i) & 0x01); + if(tmp!=0) { + + if(i < 8) { + MODIFY_REG(GPIO->MODE0, (0xF<<(i*4)), (GPIO_InitStruct->GPIO_Mode << (i*4)) ); + } + else if((i > 7) && (i < 16)) { + MODIFY_REG(GPIO->MODE1, (0xF<<((i-8)*4)), (GPIO_InitStruct->GPIO_Mode << ((i-8)*4)) ); + } +#ifdef BLUENRG2_DEVICE + else if((i > 15) && (i < 24)) { + MODIFY_REG(GPIO->MODE2, (0xF<<((i-16)*4)), (GPIO_InitStruct->GPIO_Mode << ((i-16)*4)) ); + } + else if(i > 23) { + MODIFY_REG(GPIO->MODE3, (0xF<<((i-24)*4)), (GPIO_InitStruct->GPIO_Mode << ((i-24)*4)) ); + } +#endif + } + } + + /* Set the current mode */ + if(GPIO_InitStruct->GPIO_HighPwr == ENABLE) { + SET_BIT(GPIO->DS, GPIO_InitStruct->GPIO_Pin); + } + else { + CLEAR_BIT(GPIO->DS, GPIO_InitStruct->GPIO_Pin); + } + + /* Set the pull on IO */ + if(GPIO_InitStruct->GPIO_Pull == ENABLE) { + SET_BIT(GPIO->PE, GPIO_InitStruct->GPIO_Pin); + } + else { + CLEAR_BIT(GPIO->PE, GPIO_InitStruct->GPIO_Pin); + } + +} + +/** +* @brief Fills the GPIO_InitStruct member with its default value. +* @param GPIO_InitStruct : pointer to a @ref GPIO_InitType structure which will +* be initialized. +* @retval None +*/ +void GPIO_StructInit(GPIO_InitType* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = 0x00000000; + GPIO_InitStruct->GPIO_Mode = GPIO_Input; + GPIO_InitStruct->GPIO_Pull = DISABLE; + GPIO_InitStruct->GPIO_HighPwr = DISABLE; +} + + +/** +* @brief Initializes the GPIO9, GPIO10 and GPIO11 according to the specified +* parameters in the GPIO_InitStruct. This setting is applied during low power modes. +* This feature is applicable only for BlueNRG-2. +* @param GPIO_InitStruct: pointer to a @ref GPIO_InitType structure that +* contains the configuration information for the specified GPIO peripheral. +* @retval None +*/ +void GPIO_InitLowPowerModes(GPIO_InitType* GPIO_InitStruct) +{ +#ifdef BLUENRG2_DEVICE + + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_FUNCTIONAL_STATE(GPIO_InitStruct->GPIO_Pull)); + assert_param(IS_FUNCTIONAL_STATE(GPIO_InitStruct->GPIO_HighPwr)); + + if((GPIO_InitStruct->GPIO_Pin&GPIO_Pin_9) == GPIO_Pin_9 || + (GPIO_InitStruct->GPIO_Pin&GPIO_Pin_10) == GPIO_Pin_10 || + (GPIO_InitStruct->GPIO_Pin&GPIO_Pin_11) == GPIO_Pin_11) { + + /* Configure the IO mode */ + if(GPIO_InitStruct->GPIO_Mode == GPIO_Input) { + SET_BIT(SYSTEM_CTRL->SLEEPIO_OEN, (GPIO_InitStruct->GPIO_Pin>>9)); + } + else if(GPIO_InitStruct->GPIO_Mode == GPIO_Output) { + CLEAR_BIT(SYSTEM_CTRL->SLEEPIO_OEN, (GPIO_InitStruct->GPIO_Pin>>9)); + } + + /* Set the current mode */ + if(GPIO_InitStruct->GPIO_HighPwr == ENABLE) { + SET_BIT(SYSTEM_CTRL->SLEEPIO_DS, (GPIO_InitStruct->GPIO_Pin>>9)); + } + else { + CLEAR_BIT(SYSTEM_CTRL->SLEEPIO_DS, (GPIO_InitStruct->GPIO_Pin>>9)); + } + + /* Set the pull on IO */ + if(GPIO_InitStruct->GPIO_Pull == ENABLE) { + SET_BIT(SYSTEM_CTRL->SLEEPIO_PE, (GPIO_InitStruct->GPIO_Pin>>9)); + } + else { + CLEAR_BIT(SYSTEM_CTRL->SLEEPIO_PE, (GPIO_InitStruct->GPIO_Pin>>9)); + } + } +#endif +} + + +/** +* @brief Set the output state of the GIO9, GIO10, GIO11 during low power modes. +* Only for BlueNRG-2 device. +* @param GPIO_Pin: specifies the GPIO pin pins to be retained +* This parameter can be GPIO_Pin_x where x can be (9, 10, 11) @ref GPIO_Pins_Definition. +* @retval None +*/ +void GPIO_WriteBitLowPowerModes(uint32_t GPIO_Pin, BitAction BitVal) +{ +#ifdef BLUENRG2_DEVICE + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + /* Reset GPIO init structure parameters values */ + if((GPIO_Pin&GPIO_Pin_9) == GPIO_Pin_9 || + (GPIO_Pin&GPIO_Pin_10) == GPIO_Pin_10 || + (GPIO_Pin&GPIO_Pin_11) == GPIO_Pin_11) { + if (BitVal == Bit_SET) { + SET_BIT(SYSTEM_CTRL->SLEEPIO_OUT, (GPIO_Pin>>9)); + } + else { + CLEAR_BIT(SYSTEM_CTRL->SLEEPIO_OUT, (GPIO_Pin>>9)); + } + } +#endif +} + + + +/** +* @brief Reads the specified input pin value. +* @param GPIO_Pin: specifies the GPIO pin bits to read. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* @retval The input pin value @ref BitAction. +*/ +BitAction GPIO_ReadBit(uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if(READ_BIT(GPIO->DATA, GPIO_Pin)) { + return Bit_SET; + } + else { + return Bit_RESET; + } +} + + +/** +* @brief Sets the selected IO pin bit. +* @param GPIO_Pin: specifies the pins to be written. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* More than one pin can be specified in OR logic, i.e. (GPIO_Pin_0 | GPIO_Pin_1). +* @retval None +*/ +void GPIO_SetBits(uint32_t GPIO_Pins) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_Pins)); + + WRITE_REG(GPIO->DATS, GPIO_Pins); +} + +/** +* @brief Clears the selected IO pin bits. +* @param GPIO_Pin: specifies the pins to be written. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* More than one pin can be specified in OR logic, i.e. (GPIO_Pin_0 | GPIO_Pin_1). +* @retval None +*/ +void GPIO_ResetBits(uint32_t GPIO_Pins) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_Pins)); + + WRITE_REG(GPIO->DATC, GPIO_Pins); +} + +/** +* @brief Sets or clears the selected IO pin bit. +* @param GPIO_Pin: specifies the IO bits to be written. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* More than one pin can be specified in OR logic, i.e. (GPIO_Pin_0 | GPIO_Pin_1). +* @param BitVal: specifies the value to be written to the selected bit. +* This parameter can be any value of @ref BitAction. +* @retval None +*/ +void GPIO_WriteBit(uint32_t GPIO_Pins, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_Pins)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal == Bit_SET) { + WRITE_REG(GPIO->DATS, GPIO_Pins); + } + else { + WRITE_REG(GPIO->DATC, GPIO_Pins); + } +} + +/** +* @brief Toggles data to the specified IO pin. +* @param GPIO_Pin: specifies the IO bits to be toggled. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* More than one pin can be specified in OR logic, i.e. (GPIO_Pin_0 | GPIO_Pin_1). +* @retval None +*/ +void GPIO_ToggleBits(uint32_t GPIO_Pins) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_Pins)); + + GPIO->DATA ^= GPIO_Pins; +} + +/** +* @brief Fills each GPIO_EXTIStruct member with its default value. +* @param GPIO_EXTIInitStruct : pointer to a @ref GPIO_EXTIConfigType structure. +* @retval None +*/ +void GPIO_EXTIStructInit(GPIO_EXTIConfigType* GPIO_EXTIInitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_EXTIInitStruct->GPIO_Pin = 0x00000000; + GPIO_EXTIInitStruct->GPIO_IrqSense = GPIO_IrqSense_Edge; + GPIO_EXTIInitStruct->GPIO_Event = GPIO_Event_Low; +} + + +/** +* @brief Selects the GPIO pins used as EXTI Line. +* @param EXTIConfig: pointer to a @ref GPIO_EXTIConfigType structure that +* contains the configuration information for the specified GPIO pins. +* @retval None +*/ +void GPIO_EXTIConfig(GPIO_EXTIConfigType* EXTIConfig) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(EXTIConfig->GPIO_Pin)); + assert_param(IS_GPIO_IRQSENSE(EXTIConfig->GPIO_IrqSense)); + assert_param(IS_GPIO_EVENT(EXTIConfig->GPIO_Event)); + + /* Interrupt sense configuration */ + if (EXTIConfig->GPIO_IrqSense == GPIO_IrqSense_Level) { + /* Configure level detection */ + SET_BIT(GPIO->IS, EXTIConfig->GPIO_Pin); + } + else { + /* Configure edge detection */ + CLEAR_BIT(GPIO->IS, EXTIConfig->GPIO_Pin); + } + + /* Configure event */ + if (EXTIConfig->GPIO_Event == GPIO_Event_High) { + /* Configure interrupt on high level or rising edge event */ + SET_BIT(GPIO->IEV, EXTIConfig->GPIO_Pin); + CLEAR_BIT(GPIO->IBE, EXTIConfig->GPIO_Pin); + } + else if (EXTIConfig->GPIO_Event == GPIO_Event_Low) { + /* Configure interrupt on low level or falling edge event */ + CLEAR_BIT(GPIO->IEV, EXTIConfig->GPIO_Pin); + CLEAR_BIT(GPIO->IBE, EXTIConfig->GPIO_Pin); + } + else { + /* Configure interrupt on both edge */ + SET_BIT(GPIO->IBE, EXTIConfig->GPIO_Pin); + } + +} + +/** +* @brief Enables or disables interrupts on specified pins. +* @param GPIO_Pin: specifies the IO pins as an interrupt source. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* More than one pin can be specified in OR logic, i.e. (GPIO_Pin_0 | GPIO_Pin_1). +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void GPIO_EXTICmd(uint32_t GPIO_Pins, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_Pins)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + SET_BIT(GPIO->IE, GPIO_Pins); + } + else { + CLEAR_BIT(GPIO->IE, GPIO_Pins); + } +} + +/** +* @brief Clears the GPIO interrupt pending bits. +* @param GPIO_Pin: specifies the GPIO interrupt pending bit to clear. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* More than one pin can be specified in OR logic, i.e. (GPIO_Pin_0 | GPIO_Pin_1). +* @retval None +*/ +void GPIO_ClearITPendingBit(uint32_t GPIO_Pins) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PINS(GPIO_Pins)); + + SET_BIT(GPIO->IC, GPIO_Pins); +} + + +/** +* @brief Checks whether the specified enabled GPIO interrupt is active. +* @param GPIO_Pin: Specifies the GPIO interrupt to check. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* @param FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. +*/ +FlagStatus GPIO_GetITPendingBit(uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if(READ_BIT(GPIO->MIS, GPIO_Pin) != (uint32_t)RESET) { + return SET; + } + else { + return RESET; + } +} + + +/** +* @brief Checks whether the specified GPIO interrupt is active. +* @param GPIO_Pin: Specifies the GPIO interrupt to check. +* This parameter can be GPIO_Pin_x where x can be (0..25) @ref GPIO_Pins_Definition. +* QFN32 package: 15 pins, WLCSP32 package: 14 pins, QFN48 package: 26 pins. +* @param FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. +*/ +ITStatus GPIO_GetITStatusBit(uint32_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if(READ_BIT(GPIO->RIS, GPIO_Pin) != (uint32_t)RESET) { + return SET; + } + else { + return RESET; + } +} +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_i2c.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_i2c.c new file mode 100644 index 00000000000..53100dd59ec --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_i2c.c @@ -0,0 +1,742 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_i2c.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup I2C_Peripheral I2C Peripheral + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines Private Defines + * @{ + */ + +/* I2C Standard mode */ +#define I2C_CR_SM_STD (0x0) + +/* I2C Fast mode */ +#define I2C_CR_SM_FAST (0x1) + +#define I2C_CLOCK (16000000) + +#define I2C_SLAVE_ADDR_EXT10_SMK (0x03FF) + + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables Private Variables + * @{ + */ +static __I uint16_t Foncycles[4] = {1, 3, 4, 6}; + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Public_Functions Public Functions + * @{ + */ + + +/** +* @brief Deinitializes the I2C peripheral registers to their default reset values. +* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type +* @retval None +*/ +void I2C_DeInit(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Generate a stop condition */ + I2Cx->CR_b.FS_1 = SET; + + /* Disable the selected I2C peripheral / software reset */ + I2Cx->CR_b.PE = RESET; +} + + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_InitStruct: pointer to a @ref I2C_InitType structure that + * contains the configuration information for the specified I2C peripheral. +* @retval None + */ +void I2C_Init(I2C_Type* I2Cx, I2C_InitType* I2C_InitStruct) +{ + uint16_t foncycle; + uint32_t brcnt; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED_I2C(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_OPERATING_MODE(I2C_InitStruct->I2C_OperatingMode)); + assert_param(IS_I2C_FILTERING(I2C_InitStruct->I2C_Filtering)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_FUNCTIONAL_STATE(I2C_InitStruct->I2C_ExtendAddress)); + + /* Disable the selected I2C peripheral / software reset */ + I2Cx->CR_b.PE = RESET; + + /* Select the digital filtering */ + I2Cx->CR_b.FON = I2C_InitStruct->I2C_Filtering; + + /* Clock rate computation */ + foncycle = Foncycles[I2C_InitStruct->I2C_Filtering]; + brcnt = I2C_CLOCK - I2C_InitStruct->I2C_ClockSpeed * foncycle; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + brcnt /= (I2C_InitStruct->I2C_ClockSpeed << 1); + + I2Cx->CR_b.SM = I2C_CR_SM_STD; + + /* @16MHz 0x0003=>250ns */ + I2Cx->SCR_b.SLSU = 0x003; + } + /* Configure speed in fast mode */ + else if (I2C_InitStruct->I2C_ClockSpeed <= 400000) + { + brcnt /= (I2C_InitStruct->I2C_ClockSpeed * 3); + + I2Cx->CR_b.SM = I2C_CR_SM_FAST; + + /* @16MHz 0x0002=>125ns */ + I2Cx->SCR_b.SLSU = 0x0002; + } + + /* Set I2C own address */ + MODIFY_REG(I2Cx->SCR, I2C_SLAVE_ADDR_EXT10_SMK, I2C_InitStruct->I2C_OwnAddress1); + + /* Configure the baud rate */ + I2Cx->BRCR_b.BRCNT = (uint16_t)brcnt; + + /* Configure the operating mode */ + I2Cx->CR_b.OM = I2C_InitStruct->I2C_OperatingMode; + + if(I2C_InitStruct->I2C_ExtendAddress == ENABLE) { + I2Cx->CR_b.SAM = SET; + } + else { + I2Cx->CR_b.SAM = RESET; + } + + /* Enable the selected I2C peripheral */ + I2Cx->CR_b.PE = SET; +} + + +/** + * @brief Fills the I2C_InitStruct with default values. + * @param I2C_InitStruct: pointer to an @ref I2C_InitType structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitType* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + + /* initialize the I2C_OperatingMode member */ + I2C_InitStruct->I2C_OperatingMode = I2C_OperatingMode_Slave; + + /* initialize the I2C_Filtering member */ + I2C_InitStruct->I2C_Filtering = I2C_Filtering_Off; + + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + + /* Initialize the I2C_AddressingMode member */ + I2C_InitStruct->I2C_ExtendAddress = DISABLE; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_Type* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the selected I2C peripheral */ + I2Cx->CR_b.PE = SET; + } + else { + /* Disable the selected I2C peripheral */ + I2Cx->CR_b.PE = RESET; + } +} + + +/** + * @brief Start an I2C transaction sending the frame specified. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param tr: pointer to an @ref I2C_TransactionType structure used + * for this transaction. + * @retval None. + */ +void I2C_BeginTransaction(I2C_Type* I2Cx, I2C_TransactionType* tr) +{ + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_OPERATION(tr->Operation)); + assert_param(IS_I2C_STARTBYTE(tr->StartByte)); + assert_param(IS_I2C_ADDRESSTYPE(tr->AddressType)); + assert_param(IS_I2C_OWN_ADDRESS1(tr->Address)); + assert_param(IS_I2C_STOPCONDITION(tr->StopCondition)); + assert_param(IS_I2C_LENGTH(tr->Length)); + + I2Cx->MCR = ((uint32_t)(tr->Operation)) | (((uint32_t)(tr->Address)) << 1) | + ((uint32_t)(tr->StartByte)) | ((uint32_t)(tr->AddressType)) | + ((uint32_t)(tr->StopCondition)) | (((uint32_t)(tr->Length)) << 15); + +} + + +/** + * @brief Enables or disables the general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_Type* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) { + /* Enable generall call */ + I2Cx->CR_b.SGCM = SET; + } + else { + /* Disable generall call */ + I2Cx->CR_b.SGCM = RESET; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_TXFE: Tx FIFO empty + * @arg I2C_IT_TXFNE: TX FIFO nearly empty + * @arg I2C_IT_TXFF: Tx FIFO full + * @arg I2C_IT_TXFOVR: Tx FIFO overflow + * @arg I2C_IT_RXFE: Rx FIFO empty + * @arg I2C_IT_RXFNF: Rx FIFO nearly full + * @arg I2C_IT_RXFF: Rx FIFO full + * @arg I2C_IT_LBR: Length number of bytes received + * @arg I2C_IT_RFSR: Read from slave request + * @arg I2C_IT_RFSE: Read from slave empty + * @arg I2C_IT_WTSR: Write to slave request + * @arg I2C_IT_MTD: Master transaction done + * @arg I2C_IT_STD: Slave transaction done + * @arg I2C_IT_SAL: Slave arbitration lost + * @arg I2C_IT_MAL: Master arbitration lost + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_MTDWS: Master transaction done without stop + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_Type* I2Cx, uint32_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_IT(I2C_IT)); + + if (NewState != DISABLE) { + /* Enable the selected I2C interrupts */ + SET_BIT(I2Cx->IMSCR, I2C_IT); + } + else { + /* Disable the selected I2C interrupts */ + CLEAR_BIT(I2Cx->IMSCR, I2C_IT); + } +} + +/** + * @brief Fills the Tx FIFO with the specified data byte. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param Data: Byte to be transmitted. + * @retval None + */ +void I2C_FillTxFIFO(I2C_Type* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->TFR = (uint32_t)Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval uint8_t The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return I2Cx->RFR_b.RDATA; +} + + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval None + */ +void I2C_FlushTx(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Set flush tx flag */ + I2Cx->CR_b.FTX = SET; +} + + +/** + * @brief Return the status of the TX FIFO flush operation. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval I2C_OpStatus operation status @ref I2C_OpStatus + */ +I2C_OpStatus I2C_WaitFlushTx(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Wait the flush of TX FIFO is completed */ + if(I2Cx->CR_b.FTX == SET) { + return I2C_OP_ONGOING; + } + else { + return I2C_OP_OK; + } +} + + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval None + */ +void I2C_FlushRx(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Set flush rx flag */ + I2Cx->CR_b.FRX = SET; +} + + +/** + * @brief Return the status of the RX FIFO flush operation. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval I2C_OpStatus operation status @ref I2C_OpStatus + */ +I2C_OpStatus I2C_WaitFlushRx(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Wait the flush of TX FIFO is completed */ + if(I2Cx->CR_b.FRX == SET) { + return I2C_OP_ONGOING; + } + else { + return I2C_OP_OK; + } +} + +/** + * @brief Sets the transmit FIFO threshold by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param TxThres: The value of the threshold 2-byte. + * @retval None + */ +void I2C_SetTxThreshold(I2C_Type* I2Cx, uint16_t TxThres) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_TX_THRESHOLD(TxThres)); + + /* Set the Tx FIFO Threshold */ + I2Cx->TFTR_b.THRESH_TX = TxThres; +} + +/** + * @brief Sets the receive FIFO threshold by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param RxThres: The value of the threshold 2-byte. + */ +void I2C_SetRxThreshold(I2C_Type* I2Cx, uint16_t RxThres) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_RX_THRESHOLD(RxThres)); + + /* Set the Rx FIFO Threshold */ + I2Cx->RFTR_b.THRESH_RX = RxThres; +} + + +/** + * @brief Generate a stop condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval None + */ +void I2C_GenerateStopCondition(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Generate a stop condition */ + I2Cx->CR_b.FS_1 = SET; +} + +/** + * @brief Set the hold time value for data transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_HoldTime: specifies the hold time value. + * @retval None + */ +void I2C_SetHoldTime(I2C_Type* I2Cx, uint16_t I2C_HoldTime) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_HOLDTIME(I2C_HoldTime)); + + I2Cx->THDDAT = I2C_HoldTime; +} + +/** + * @brief Set the hold time value for start condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_HoldTime: specifies the hold time value. + * @retval None + */ +void I2C_SetHoldTimeStartCondition(I2C_Type* I2Cx, uint16_t I2C_HoldTime) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_HOLDTIME(I2C_HoldTime)); + + /* Standard mode */ + if(I2Cx->CR_b.SM == I2C_CR_SM_STD) { + I2Cx->THDSTA_FST_STD_b.THDSTA_STD = I2C_HoldTime; + } + else if(I2Cx->CR_b.SM == I2C_CR_SM_FAST) { + I2Cx->THDSTA_FST_STD_b.THDSTA_FST = I2C_HoldTime; + } +} + +/** + * @brief Set the setup time value for start condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_SetupTime: specifies the setup time value. + * @retval None + */ +void I2C_SetSetupTimeStartCondition(I2C_Type* I2Cx, uint16_t I2C_SetupTime) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SETUPTIME(I2C_SetupTime)); + + /* Standard mode */ + if(I2Cx->CR_b.SM == I2C_CR_SM_STD) { + I2Cx->TSUSTA_FST_STD_b.TSUSTA_STD = I2C_SetupTime; + } + else if(I2Cx->CR_b.SM == I2C_CR_SM_FAST) { + I2Cx->TSUSTA_FST_STD_b.TSUSTA_FST = I2C_SetupTime; + } +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_TXFE: Tx FIFO empty + * @arg I2C_IT_TXFNE: TX FIFO nearly empty + * @arg I2C_IT_TXFF: Tx FIFO full + * @arg I2C_IT_TXFOVR: Tx FIFO overflow + * @arg I2C_IT_RXFE: Rx FIFO empty + * @arg I2C_IT_RXFNF: Rx FIFO nearly full + * @arg I2C_IT_RXFF: Rx FIFO full + * @arg I2C_IT_LBR: Length number of bytes received + * @arg I2C_IT_RFSR: Read from slave request + * @arg I2C_IT_RFSE: Read from slave empty + * @arg I2C_IT_WTSR: Write to slave request + * @arg I2C_IT_MTD: Master transaction done + * @arg I2C_IT_STD: Slave transaction done + * @arg I2C_IT_SAL: Slave arbitration lost + * @arg I2C_IT_MAL: Master arbitration lost + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_MTDWS: Master transaction done without stop + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error + * @retval ITStatus: functional state @ref ITStatus + * This parameter can be: SET or RESET. + */ +ITStatus I2C_GetITStatus(I2C_Type* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_IT(I2C_IT)); + + /* Check the status of the specified I2C flag */ + if (READ_BIT(I2Cx->RISR, I2C_IT) != (uint32_t)RESET) { + /* I2C_IT is set */ + return SET; + } + else { + /* I2C_IT is reset */ + return RESET; + } +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_TXFE: Tx FIFO empty + * @arg I2C_IT_TXFNE: TX FIFO nearly empty + * @arg I2C_IT_TXFF: Tx FIFO full + * @arg I2C_IT_TXFOVR: Tx FIFO overflow + * @arg I2C_IT_RXFE: Rx FIFO empty + * @arg I2C_IT_RXFNF: Rx FIFO nearly full + * @arg I2C_IT_RXFF: Rx FIFO full + * @arg I2C_IT_LBR: Length number of bytes received + * @arg I2C_IT_RFSR: Read from slave request + * @arg I2C_IT_RFSE: Read from slave empty + * @arg I2C_IT_WTSR: Write to slave request + * @arg I2C_IT_MTD: Master transaction done + * @arg I2C_IT_STD: Slave transaction done + * @arg I2C_IT_SAL: Slave arbitration lost + * @arg I2C_IT_MAL: Master arbitration lost + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_MTDWS: Master transaction done without stop + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error + * @retval ITStatus: functional state @ref ITStatus + * This parameter can be: SET or RESET. + */ +ITStatus I2C_GetITPendingBit(I2C_Type* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_IT(I2C_IT)); + + /* Check the status of the specified I2C flag */ + if (READ_BIT(I2Cx->MISR, I2C_IT) != (uint32_t)RESET) { + /* I2C_IT is set */ + return SET; + } + else { + /* I2C_IT is reset */ + return RESET; + } +} + + +/** + * @brief Clears the I2Cx interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_TXFE: Tx FIFO empty + * @arg I2C_IT_TXFNE: TX FIFO nearly empty + * @arg I2C_IT_TXFF: Tx FIFO full + * @arg I2C_IT_TXFOVR: Tx FIFO overflow + * @arg I2C_IT_RXFE: Rx FIFO empty + * @arg I2C_IT_RXFNF: Rx FIFO nearly full + * @arg I2C_IT_RXFF: Rx FIFO full + * @arg I2C_IT_LBR: Length number of bytes received + * @arg I2C_IT_RFSR: Read from slave request + * @arg I2C_IT_RFSE: Read from slave empty + * @arg I2C_IT_WTSR: Write to slave request + * @arg I2C_IT_MTD: Master transaction done + * @arg I2C_IT_STD: Slave transaction done + * @arg I2C_IT_SAL: Slave arbitration lost + * @arg I2C_IT_MAL: Master arbitration lost + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_MTDWS: Master transaction done without stop + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error + * @retval None + */ +void I2C_ClearITPendingBit(I2C_Type* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_IT(I2C_IT)); + /* Clear the selected I2C flags */ + WRITE_REG(I2Cx->ICR, I2C_IT); +} + + +/** + * @brief Get the present state of the operation executed by I2C block. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @retval I2C_OpStatus: the I2C operation status @ref I2C_OpStatus + */ +I2C_OpStatus I2C_GetStatus(I2C_Type* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the OP status field of the status register */ + return (I2C_OpStatus)I2Cx->SR_b.STATUS; +} + + + +/** + * @brief Enables or disables the I2C DMA interface. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg I2C_DMAReq_Tx: I2C DMA transmit request + * @arg I2C_DMAReq_Rx: I2C DMA receive request. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_Type* I2Cx, uint16_t I2C_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DMAREQ(I2C_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer */ + I2Cx->CR |= I2C_DMAReq; + } + else + { + /* Disable the DMA transfer */ + I2Cx->CR &= ~I2C_DMAReq; + } +} + +/** + * @brief Enables or disables the I2C TX DMA burst mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMATxBurstMode(I2C_Type* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TX DMA burst mode */ + I2Cx->DMAR_b.BURST_TX = SET; + } + else + { + /* Disable the TX DMA burst mode */ + I2Cx->DMAR_b.BURST_TX = RESET; + } +} + +/** + * @brief Set the number of burst of data. + * If this number is smaller than the transaction length, only one single request are generated. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral @ref I2C_Type + * @param I2C_BurstSize: specifies the number of burst request. + * @retval None + */ +void I2C_DMATxBurstSize(I2C_Type* I2Cx, uint8_t I2C_BurstSize) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_BURSTSIZE(I2C_BurstSize)); + + I2Cx->DMAR_b.DBSIZE_TX = I2C_BurstSize; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_mft.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_mft.c new file mode 100644 index 00000000000..b6574924848 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_mft.c @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_mft.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + + +/** @defgroup MFT_Peripheral MFT Peripheral + * @{ + */ + +/** @defgroup MFT_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MFT_Private_Defines Private Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup MFT_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MFT_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MFT_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + + /** + * @} + */ + +/** @defgroup MFT_Public_Functions Public Functions + * @{ + */ + +/** + *@brief DeInit the MFTx peripheral. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@retval None + */ +void MFT_DeInit(MFT_Type* MFTx) +{ + MFTx->TNPRSC = 0x00000000; + MFTx->TNCKC = 0x00000000; + MFTx->TNMCTRL = 0x00000000; + MFTx->TNICLR = 0x0000000F; + +} + + +/** + *@brief Initializes the MFTx peripheral according to the specified + * parameters in the MFT_InitStruct. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_InitStruct: pointer to a @ref MFT_InitType structure that + * contains the configuration information for the specified MFT peripheral. + *@retval None + */ +void MFT_Init(MFT_Type* MFTx, MFT_InitType* MFT_InitStruct) +{ + + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_MODE(MFT_InitStruct->MFT_Mode)); + assert_param(IS_MFT_CLOCK_SEL(MFT_InitStruct->MFT_Clock1)); + assert_param(IS_MFT_CLOCK_SEL(MFT_InitStruct->MFT_Clock2)); + + MFTx->TNMCTRL_b.TNAEN = RESET; + MFTx->TNMCTRL_b.TNBEN = RESET; + + MFTx->TNCKC_b.TNC1CSEL = MFT_NO_CLK; + MFTx->TNCKC_b.TNC2CSEL = MFT_NO_CLK; + + if(MFT_InitStruct->MFT_Mode == MFT_MODE_1a) { + MFTx->TNMCTRL_b.TNMDSEL = MFT_MODE_1; + MFTx->TNMCTRL_b.TNPTEN = SET; + } + else { + MFTx->TNMCTRL_b.TNMDSEL = MFT_InitStruct->MFT_Mode; + MFTx->TNMCTRL_b.TNPTEN = RESET; + } + + MFTx->TNPRSC = MFT_InitStruct->MFT_Prescaler; + MFTx->TNMCTRL_b.TNEN = SET; + MFTx->TNCRA = MFT_InitStruct->MFT_CRA; + MFTx->TNCRB = MFT_InitStruct->MFT_CRB; + MFTx->TNMCTRL_b.TNEN = RESET; + + MFTx->TNCKC_b.TNC1CSEL = MFT_InitStruct->MFT_Clock1; + MFTx->TNCKC_b.TNC2CSEL = MFT_InitStruct->MFT_Clock2; +} + +/** + * @brief Fills each MFT_InitStruct member with its default value. + * @param MFT_InitStruct : pointer to a @ref MFT_InitType structure which will + * be initialized. + * @retval None + */ +void MFT_StructInit(MFT_InitType* MFT_InitStruct) +{ + /* Reset MFT init structure parameters values */ + MFT_InitStruct->MFT_Clock1 = MFT_NO_CLK; + MFT_InitStruct->MFT_Clock2 = MFT_NO_CLK; + MFT_InitStruct->MFT_CRA = 0; + MFT_InitStruct->MFT_CRB = 0; + MFT_InitStruct->MFT_Mode = MFT_MODE_1; + MFT_InitStruct->MFT_Prescaler = 0; +} + +/** + *@brief Enable/Disable the MFT + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + *@retval None + */ +void MFT_Cmd(MFT_Type* MFTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + MFTx->TNMCTRL_b.TNEN = SET; + } + else { + MFTx->TNMCTRL_b.TNEN = RESET; + } +} + + +/** + *@brief Configure edges sensibility of TnA and TnB + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_TnA_edge : falling or rising edge + *@param MFT_TnB_edge : falling or rising edge, these values can be + * @arg MFT_FALLING on rising edge + * @arg MFT_RISING on falling edge + *@retval None + */ +void MFT_TnEDGES(MFT_Type* MFTx, uint32_t MFT_TnA_edge, uint32_t MFT_TnB_edge) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_Tn_EDGE(MFT_TnA_edge)); + assert_param(IS_MFT_Tn_EDGE(MFT_TnB_edge)); + + MFTx->TNMCTRL_b.TNAEDG = MFT_TnA_edge; + MFTx->TNMCTRL_b.TNBEDG = MFT_TnB_edge; +} + +/** + *@brief Select trigger source for pulse-train generation in Mode 1a + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_Trigger : software or TnB trigger, this value can be + * @arg MFT_TnB_TRIGGER trigger on TnB edge + * @arg MFT_SOFTWARE_TRIGGER trigger software + *@retval None + */ +void MFT_PulseTrainTriggerSelect(MFT_Type* MFTx, uint32_t MFT_Trigger) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_PULSETRAIN_TRIGGER(MFT_Trigger)); + + MFTx->TNMCTRL_b.TNPTSE = MFT_Trigger; +} + +/** + *@brief Pulse-train trigger generation in Mode 1a + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@retval None + */ +void MFT_PulseTrainSoftwareTrigger(MFT_Type* MFTx) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + MFTx->TNMCTRL_b.TNPTET = SET; +} + +/** + *@brief Return the status of the Pulse-train event trigger in Mode 1a + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@retval If pule-train event trigger has occurred or not: + * Possible values are: + * RESET: No Pulse-Train Event Trigger occurred. + * SET: Pulse-Train Event Trigger occurred. Pulse-train generation not yet finished. + */ +uint8_t MFT_PulseTrainEventTriggerStatus(MFT_Type* MFTx) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + return MFTx->TNMCTRL_b.TNPTET; +} + +/** + *@brief Set or Reset TnAEN bit + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param TnX : set or reset, @ref MFT_TnAEN + * @arg MFT_TnA select internal pin TnA + * @arg MFT_TnB select internal pin TnB + *@param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + *@retval None + */ +void MFT_TnXEN(MFT_Type* MFTx, uint8_t TnX, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_TnX(TnX)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(TnX == MFT_TnA) { + MFTx->TNMCTRL_b.TNAEN = NewState; + } + else if(TnX == MFT_TnB) { + MFTx->TNMCTRL_b.TNBEN = NewState; + } +} + + +/** + *@brief Set or Reset TnAEN bit + *@param MFT_TimerType : select the timer and the pin, this value can be + * @arg MFT1_TIMERA Select Timer MFT1 and input TnA + * @arg MFT1_TIMERB Select Timer MFT1 and input TnB + * @arg MFT2_TIMERA Select Timer MFT2 and input TnA + * @arg MFT2_TIMERB Select Timer MFT2 and input TnB + *@param MFT_Pin : the IO number from IO0 to IO14 (0, 1, .. 14) + *@retval None + */ +void MFT_SelectCapturePin( uint32_t MFT_TimerType, uint8_t MFT_Pin) +{ + /* Check the parameters */ + assert_param(IS_MFT_TIMER(MFT_TimerType)); + assert_param(IS_MFT_INPUT_IO(MFT_Pin)); + + /* set counter */ + if(MFT_TimerType == MFT1_TIMERA) { + GPIO->MFTX_b.MFT1_TIMER_A = MFT_Pin; + } + else if(MFT_TimerType == MFT1_TIMERB) { + GPIO->MFTX_b.MFT1_TIMER_B = MFT_Pin; + } + else if(MFT_TimerType == MFT2_TIMERA) { + GPIO->MFTX_b.MFT2_TIMER_A = MFT_Pin; + } + else if(MFT_TimerType == MFT2_TIMERB) { + GPIO->MFTX_b.MFT2_TIMER_B = MFT_Pin; + } + +} + + +/** + *@brief Set the timer counter. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_Cnt1 : set the counter value for CNT1 + *@param MFT_Cnt2 : set the counter value for CNT2 + *@retval None + */ +void MFT_SetCounter(MFT_Type* MFTx, uint16_t MFT_Cnt1, uint16_t MFT_Cnt2) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + /* Set counters */ + MFTx->TNCNT1 = MFT_Cnt1; + MFTx->TNCNT2 = MFT_Cnt2; +} + + +/** + *@brief Set the timer counter1. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_Cnt : set the counter value for CNT1 + *@retval None + */ +void MFT_SetCounter1(MFT_Type* MFTx, uint16_t MFT_Cnt) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + /* Set counter */ + MFTx->TNCNT1 = MFT_Cnt; +} + +/** + *@brief Get the timer counter1. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param None + *@retval uint16_t the counter 1 value + */ +uint16_t MFT_GetCounter1(MFT_Type* MFTx) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + /* Return counter */ + return MFTx->TNCNT1; +} + +/** + *@brief Set the timer counter2. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_Cnt : set the counter value for CNT2 + *@retval None + */ +void MFT_SetCounter2(MFT_Type* MFTx, uint16_t MFT_Cnt) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + /* set counter */ + MFTx->TNCNT2 = MFT_Cnt; +} + +/** + *@brief Get the timer counter2. + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param None + *@retval uint16_t the counter 2 value + */ +uint16_t MFT_GetCounter2(MFT_Type* MFTx) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + + /* Return counter */ + return MFTx->TNCNT2; +} + +/** + *@brief Enable specific MFT interrupt + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_IrqSource: interrupt source to enable, this value can be + * @arg MFT_IT_TNA Select the interrupt source A + * @arg MFT_IT_TNB Select the interrupt source B + * @arg MFT_IT_TNC Select the interrupt source C + * @arg MFT_IT_TND Select the interrupt source D + *@param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + *@retval None + */ +void MFT_EnableIT(MFT_Type* MFTx, uint8_t MFT_IrqSource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_INTERRUPT(MFT_IrqSource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + SET_BIT(MFTx->TNICTRL, (MFT_IrqSource << 4)); + } + else { + CLEAR_BIT(MFTx->TNICTRL, (MFT_IrqSource << 4)); + } +} + +/** + *@brief Clear specific MFT interrupt + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_IrqSource: interrupt source to enable, this value can be + * @arg MFT_IT_TNA Select the interrupt source A + * @arg MFT_IT_TNB Select the interrupt source B + * @arg MFT_IT_TNC Select the interrupt source C + * @arg MFT_IT_TND Select the interrupt source D + *@retval None + */ +void MFT_ClearIT(MFT_Type* MFTx, uint8_t MFT_IrqSource) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_INTERRUPT(MFT_IrqSource)); + + SET_BIT(MFTx->TNICLR, MFT_IrqSource); +} + +/** + *@brief Return interrupt status + *@param MFTx: where x can be 1 or 2 to select the MFT peripheral @ref MFT_Type + *@param MFT_IrqSource: interrupt source to enable, this value can be + * @arg MFT_IT_TNA Select the interrupt source A + * @arg MFT_IT_TNB Select the interrupt source B + * @arg MFT_IT_TNC Select the interrupt source C + * @arg MFT_IT_TND Select the interrupt source D + *@retval ITStatus: functional state @ref ITStatus + * This parameter can be: SET or RESET. + */ +ITStatus MFT_StatusIT(MFT_Type* MFTx, uint8_t MFT_IrqSource) +{ + /* Check the parameters */ + assert_param(IS_MFT(MFTx)); + assert_param(IS_MFT_INTERRUPT(MFT_IrqSource)); + + if((MFTx->TNICTRL & MFT_IrqSource) != (uint32_t)RESET) { + return SET; + } + else { + return RESET; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_pka.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_pka.c new file mode 100644 index 00000000000..ab32d3be44b --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_pka.c @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_pka.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver +* @{ +*/ + +/** @defgroup PKA_Peripheral PKA Peripheral +* @{ +*/ + +/** @defgroup PKA_Private_TypesDefinitions Private Types Definitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PKA_Private_Defines Private Defines +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PKA_Private_Macros Private Macros +* @{ +*/ + + +/** +* @} +*/ + +/** @defgroup PKA_Private_Variables Private Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup PKA_Private_Functions Private Functions +* @{ +*/ + + +/** +* @} +*/ + +/** @defgroup PKA_Public_Functions Public Functions +* @{ +*/ + + +/** +* @brief PKA Software Reset. +* @param None +* @retval None +*/ +void PKA_Reset(void) +{ + /* Set Bit SFT_RST of CSR */ + PKA->CSR_b.SFT_RST = SET; + + /* the Bit SFT_RST must be reset after set */ + PKA->CSR_b.SFT_RST = RESET; +} + + +/** +* @brief PKA start processing command. +* @param None +* @retval ErrorStatus +* @note Assumes that Input Data have been already loaded into PKA memory! +*/ +void PKA_StartProcessing(void) +{ + /* Set Bit GO of CSR */ + PKA->CSR_b.GO = SET; + + /* the Bit GO must be reset before the end of calculation */ + PKA->CSR_b.GO = RESET; + +} + + +/** +* @brief Wait loop for READY status +* @param None +* @retval None +*/ +void PKA_WaitProcess(void) +{ + /* Wait PKA processing end */ + while(PKA->CSR_b.READY != SET); +} + + +/** +* @brief Return the READY status +* @param None +* @retval FlagStatus RESET if PKA is busy +*/ +FlagStatus PKA_GetProcessStatus(void) +{ + /* Wait PKA processing end */ + return (FlagStatus)(PKA->CSR_b.READY); +} + + +/** +* @brief PKA verification of process command. +* @param None +* @retval ErrorStatus +*/ +ErrorStatus PKA_VerifyProcess(void) +{ + uint32_t errorCode; + + errorCode = *(uint32_t *)(PKA_RAM_ECC_ADDR_KP_ERROR); + + if (errorCode == 0) { + return SUCCESS; + } + else { + return ERROR; + } +} + + +/** +* @brief Enables or disables the specified PKA interrupts. +* @param PkaFlag: the PKA flag to clear, this can be +* @arg PKA_PROCEND PKA process end +* @arg PKA_RAMERR PKA RAM error +* @arg PKA_ADDERR PKA address invalid +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void PKA_ITConfig(uint8_t PkaFlag, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_PKA_FLAG(PkaFlag)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + SET_BIT(PKA->IEN, PkaFlag); + } + else if (NewState == DISABLE) { + CLEAR_BIT(PKA->IEN, PkaFlag); + } +} + + +/** +* @brief Clears the specific PKA pending IT bit. +* @param PkaFlag: the PKA flag to clear, this can be +* @arg PKA_PROCEND PKA process end +* @arg PKA_RAMERR PKA RAM error +* @arg PKA_ADDERR PKA address invalid +* @retval None +*/ +void PKA_ClearITPendingBit(uint8_t PkaFlag) +{ + assert_param(IS_PKA_FLAG(PkaFlag)) ; + + /* Clear the flags */ + PKA->ISR = PkaFlag; +} + + +/** +* @brief Checks whether the specified PKA flag is set or not. +* @param PkaFlag: the PKA flag to clear, this can be +* @arg PKA_PROCEND PKA process end +* @arg PKA_RAMERR PKA RAM error +* @arg PKA_ADDERR PKA address invalid +* @retval FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. +*/ +FlagStatus PKA_GetFlagStatus(uint8_t PkaFlag) +{ + /* Check the parameters */ + assert_param(IS_PKA_FLAG(PkaFlag)); + + if((PKA->ISR & PkaFlag) != (uint16_t)RESET) { + return SET; + } + else { + return RESET; + } +} + + + +/** +* @brief Write the PKA RAM with the input data. +* @param dataType: select the region of PKA RAM to write: +* @arg PKA_DATA_SK is the K value +* @arg PKA_DATA_PCX is the point X coordinate +* @arg PKA_DATA_PCY is the point Y coordinate +* @retval ErrorStatus +*/ +ErrorStatus PKA_SetData(uint8_t dataType, uint32_t* srcData) +{ + uint32_t StartAddress; + uint8_t idx; + + /* Check the parameters */ + assert_param(IS_PKA_CMD(dataType)); + + if (dataType == PKA_DATA_SK) + StartAddress = PKA_RAM_ECC_ADDR_K; + else if (dataType == PKA_DATA_PCX) + StartAddress = PKA_RAM_ECC_ADDR_PX; + else if (dataType == PKA_DATA_PCY) + StartAddress = PKA_RAM_ECC_ADDR_PY; + else return ERROR; + + /* Write the source data to target PKA RAM address. */ + for (idx = 0; idx<8; idx++) + { + *(uint32_t *)(StartAddress + 4*idx) = srcData[idx]; + } + + /* A 9th word of zeros must be added */ + *(uint32_t *)(StartAddress + 32UL) = 0x00000000; + + return SUCCESS; +} + + +/** +* @brief Get from the PKA RAM the output data. +* @param dataType: select the region of PKA RAM to read: +* @arg PKA_DATA_SK is the K value +* @arg PKA_DATA_PCX is the point X coordinate +* @arg PKA_DATA_PCY is the point Y coordinate +* @retval ErrorStatus +*/ +ErrorStatus PKA_GetData(uint8_t dataType, uint8_t* dataTarget) +{ + uint32_t StartAddress; + + /* Check the parameters */ + assert_param(IS_PKA_CMD(dataType)); + + if (dataType == PKA_DATA_SK) + StartAddress = PKA_RAM_ECC_ADDR_K; + else if (dataType == PKA_DATA_PCX) + StartAddress = PKA_RAM_ECC_ADDR_PX; + else if (dataType == PKA_DATA_PCY) + StartAddress = PKA_RAM_ECC_ADDR_PY; + else return ERROR; + + /* Read the data to target PKA RAM address. */ + for(uint8_t i=0;i<32;i++) { + dataTarget[i] = ((uint8_t *)StartAddress)[i]; + } + + return SUCCESS; +} + + + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_radio.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_radio.c new file mode 100644 index 00000000000..5b68974feb7 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_radio.c @@ -0,0 +1,1245 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_radio.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver +* @{ +*/ + +/** @addtogroup Radio_Peripheral Radio Peripheral +* @{ +*/ + + +/** @defgroup Radio_Exported_Types Exported Types +* @{ +*/ + + + +/** +* @} +*/ + + +/** @defgroup Radio_Exported_Constants Exported Constants +* @{ +*/ + +/** @defgroup Radio_TXRX_Delay_Constants TXRX Delay Constants +* @{ +*/ + +#define TX_DELAY 0x09 +#define TX_DELAY1 0x09 +#define RX_DELAY 0x05 +#define RX_DELAY1 0x05 + +#define ANALOG_OFFSET 0x00 +/** +* @} +*/ + +#define LS_CRYSTAL_PERIOD (0X00190000) // Default period for 32768 Hz Crystal +#define LS_CRYSTAL_FREQ (0x0028F5C2) // Default frequency for 32768 Hz Crystal + +/* timeout register offsets and masks */ +#define OFF_R_DESTINATION (24) +#define OFF_R_SLEEP (28) +#define MASK_R_TIMEOUT (0X00ffffff) + +/*#define Blue_BIT_PLLTRIG 1 +#define Blue_BIT_NEXT_TX_MODE 2 +#define Blue_BIT_SLEEP (1<<2) +#define Blue_BIT_NS_EN (1<<3) +#define Blue_BIT_INC_CHAN (1<<4) +#define Blue_SHIFT_NEXT_MAS (5)*/ + +#define Blue_INT_DONE (1) +#define Blue_INT_RCV_OK (2) +#define Blue_INT_CRC_ERR (1<<2) +#define Blue_INT_RCV_TRIG (1<<3) +#define Blue_INT_CMD (1<<4) +#define Blue_INT_RCVMD (1<<5) +#define Blue_INT_TIMEOUT (1<<6) +#define Blue_INT_TX_OK (1<<7) + +#define WAKEUP_TIMER_TRIGGER 0x1000000 +#define TIMER1_TIMER_TRIGGER 0x2000000 +#define TIMER2_TIMER_TRIGGER 0x3000000 + +#define WAKEUP_TIMER_MASK 0x1 +#define TIMER1_TIMER_MASK 0x2 +#define TIMER2_TIMER_MASK 0x3 + +#define BLUE_SLEEP_ENABLE 0x10000000 +#define BLUE_STANDBY_ENABLE 0x30000000 +#define TIMER_OFF 0 +#define SLEEP_TIME_MIN (250) +#define NO_DEEP_SLEEP (0x97) + + +#define IRQSPI (SPI_IRQn) +#define IRQBLUE (BLUE_CTRL_IRQn) +#define IRQNVM (NVM_IRQn) + +#define BLE_STATUS_SUCCESS (0x00) + +/** +* @} +*/ + +/** @defgroup Radio_Exported_Macros Exported Macros +* @{ +*/ +#define DISABLE_INTERRUPT(irqNum) {NVIC_DisableIRQ(irqNum);} +#define ENABLE_INTERRUPT(irqNum) {NVIC_EnableIRQ(irqNum);} +#define BLUE_STRUCT_PTR_CAST(x) (((BlueTransBlueStrctPtr_t)(int)(x)) & 0xffff) +#define BLUE_DATA_PTR_CAST(x) (((BlueTransBlueDataPtr_t)(int)(x)) & 0xffff) +#define TIME24_DIFF(a, b) (((int32_t)((a - b) << 8)) >> 8) +#define IS_STATE_VALID(STATEMACHINE_NO) (STATEMACHINE_NO < STATEMACHINE_COUNT) +#define IS_POWERLEVEL_VALID(POWER) (POWER < 16) +#define IS_RFCHANNEL_VALID(RF_CHANNEL) (RF_CHANNEL <40) +#define GET_CUR_TIME (MASK_R_TIMEOUT & BLUE_CTRL->CURRENT_TIME) +#define IFR (&(globalParameters.hardware_config) ) + +#define IS_DELAY_VALID(TIME) ( ((us_time_translate(TIME) - (IFR->hs_startup_time + (IFR->hs_startup_time>>2)-(IFR->hs_startup_time>>4)) - ANALOG_HW_OFFSET)>10) && \ + ((us_time_translate(TIME) - (IFR->hs_startup_time + (IFR->hs_startup_time>>2)-(IFR->hs_startup_time>>4)) - ANALOG_HW_OFFSET)<(1<<24))) + + +#define MASK_INTERRUPTS() __disable_irq(); +#define UNMASK_INTERRUPTS() __enable_irq(); + + +/** +* @} +*/ + +/** @defgroup Radio_Private_Variables Private Variables +* @{ +*/ + +static volatile BlueGlob* const blueglob = &__blue_RAM.BlueGlobVar; // (BlueGlob*) BLUEGLOB_BASE; +static volatile BlueGlobPerMaster* const bluedata = __blue_RAM.BlueGlobPerMasterVar;// (BlueGlobPerMaster*) (BLUEGLOB_BASE+12); + +/* volatile uint8_t *testP;*/ + +/* glabal variables */ +RadioGlobalParameters_t globalParameters; + +/*ActionPacket dummy_action_packet; +uint8_t dummy_data[50];*/ + + +/** +* @} +*/ + + + + +/** @defgroup Radio_Private_Functions Private Functions +* @{ +*/ + +/** +* @brief Weak definition of RADIO_TimerOverrunCallback +* @param void +* @retval void +*/ +WEAK_FUNCTION(void RADIO_TimerOverrunCallback(void));; + +/** +* @brief Weak definition of RADIO_HostTimerCallback +* @param void +* @retval void +*/ +WEAK_FUNCTION(void RADIO_HostTimerCallback(void)); + +/** +* @brief This function translates the incoming time in system time units to machine time units. +* @param time: Time in system time units (625/256 us). +* @retval int32_t: time in machine time units (period slow clock/16). +*/ +static int32_t machine_time_translate(int32_t time) +{ + int32_t freq_global = globalParameters.freq_global_debug ; + int32_t time1 = (time >> 15) ; + int32_t time2 = time & 0x7fff ; + int32_t freq1 = freq_global >> 7 ; + int32_t result = freq_global*time1 + ((time2 * freq1) >> 8) ; + + return((result + 32) >> 6) ; +} + + +/** +* @brief This function translates the incoming time in 512 kHz time units to us. +* @param time: Time in system in 512 kHz unit. +* @retval uint32_t: time in micro second. +*/ +static uint32_t us_time_translate(int32_t time) +{ + + //0.68DB8BAC710CB29 + uint32_t t1 = time * 0x68; + uint32_t t2 = time * 0xDB; + + return machine_time_translate( (t1 >> 8) + (t2 >> 16) );//(time*256)/625); +} + + +/** +* @brief This function gets frequency and period and sets approprite registers of BLE. +* @param a: frequency. +* b: period. +* @retval None +*/ +static void set_freq(int32_t a, int32_t b) +{ + int32_t freq_global; + int32_t period_global; + + if(IFR->ls_source != 0) { + int32_t mult = 0x753 ; + int32_t a1 = a >> 6 ; + int32_t a2 = a1 * mult ; + + int32_t mul1 = 0x8BCF6 ; + int32_t b1 = b >> 8 ; + int32_t b2 = b & 0xff ; + period_global = ((mul1 * b1) + ((b2 * mul1)>>8) + 16 )>>5 ; + + freq_global = (a2 + 128) >> 8 ; + + globalParameters.period_slow_patch = ((b * 1365) >> 16); /* Divide by 48 */ + } + else { + freq_global = LS_CRYSTAL_FREQ ; + period_global = LS_CRYSTAL_PERIOD; + /* [EM:] Fix bug #1343 + * save the period_slow value to restore in the ISR + */ + globalParameters.period_slow_patch = ((LS_CRYSTAL_PERIOD>>6)*1250) >> 16; + } + + blueglob->period_slow = globalParameters.period_slow_patch; + globalParameters.freq_global_debug = freq_global; + globalParameters.period_global_debug = period_global; /* not used in current implementation */ + int32_t time1 = machine_time_translate(IFR->hs_startup_time) ; + if(time1 >= 1024) + time1 = 1023 ; + if (time1 < 8) + time1 = 8; + blueglob->wakeup_time_offset = time1 >> 3 ; +} + + +/** +* @brief BlueNRG Start Crystal Measurement. +* @param None +* @retval None +*/ +static void BlueNRG_Start_Crystal_Measurement(void) +{ + CKGEN_BLE->CLK32K_PERIOD = 0; + globalParameters.Clk32Context.calibr.started_flag = 1; +} + + +/** +* @brief Read RSSI +* @param None +* @retval int32_t: RSSI in dBm +*/ +static int32_t read_RSSI(void) +{ + int i = 0 ; + int rsi_dbm; + + while(i < 100 && (BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0) + { + // dump_it = i++; + rsi_dbm = i++; // use rsi_dbm instead of dump_it which is in RAM2 + } + + int rssi_int16 = ((globalParameters.rssiLevel[0] >> 16) & 0xff00) | (globalParameters.rssiLevel[1] & 0xff) ; + int reg_agc = (globalParameters.rssiLevel[0] >> 16) & 0xff ; + + if(rssi_int16 == 0 || reg_agc > 0xb) + { + rsi_dbm = 127 ; + } + else + { + rsi_dbm = reg_agc * 6 -127 ; + while(rssi_int16 > 30) + { + rsi_dbm = rsi_dbm + 6 ; + rssi_int16 = rssi_int16 >> 1 ; + } + rsi_dbm = rsi_dbm + ((417*rssi_int16 + 18080)>>10) ; + } + + return rsi_dbm ; +} + + + + +#if 0 +/** +* @brief Select which timer should be employed. +* If wakeupTime is less than 1.2 ms Timer1 will be employed, +* otherwise wakeupTime will be employed. +* @param wakeupTime +* @retval uint8_t: BLE_STATUS_SUCCESS or NO_DEEP_SLEEP +*/ +static uint8_t timerSelect(uint32_t wakeupTime) +{ + int32_t time2 = BLUE_CTRL->CURRENT_TIME ; + int32_t timediff = (wakeupTime - time2) & 0xffffff ; + + /* more than 1.2 ms in the future */ + if(timediff > (blueglob->wakeup_time_offset << 3) + machine_time_translate(SLEEP_TIME_MIN) && timediff < 0x800000) { + return BLE_STATUS_SUCCESS; + } + else { + return NO_DEEP_SLEEP; + } +} +#endif + + + +/** +* @brief write_radio_config. +* @param ptr +* @retval None +*/ +static void write_radio_config(char *ptr) +{ + /* rc_config[0] = 0x005b3402 ; // turn on X-tal */ + int var11 = ((int)ptr & 0xffff) | 0x10000 ; + BLUE_CTRL->RADIO_CONFIG = var11 ; + int i = 0 ; + while((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0) + { + i = i+1 ; + } +} + +/** +* @} +*/ + + + +/** @defgroup Radio_Exported_Functions Exported Functions +* @{ +*/ + + +/** +* @brief Radio ISR. Completed event is handled here. +* Besides, next packet is scheduled here. +* @param None +* @retval None +*/ +void RADIO_IRQHandler(void) +{ + uint32_t int_value = BLUE_CTRL->INTERRUPT; + + if ( (int_value & IRQ_DONE) != 0) { + /* Indicates that there is no scheduling for wakeup Timer */ + globalParameters.wakeupTime = 0; + + /* Restore period_slow since it is rewritten by hardware */ + blueglob->period_slow = globalParameters.period_slow_patch; + + /* if (!Is_Flash_Write_On_Going()) + { + BLUE_CTRL->RADIO_CONFIG = ((int)GVAR(rssi_level) & 0xffff) | 0x10000; + } */ + BLUE_CTRL->RADIO_CONFIG = ((int)(globalParameters.rssiLevel) & 0xffff) | 0x10000; + + + ActionPacket* next, *actionPacketBackup; + BlueTransStruct *p; + + /* Copy status in order for callback to access it. */ + globalParameters.current_action_packet->status = int_value; + + if( ( globalParameters.current_action_packet->condRoutine(globalParameters.current_action_packet) ) == TRUE) { + next = globalParameters.current_action_packet->next_true; + } + else { + next = globalParameters.current_action_packet->next_false; + } + + if(next == NULL_0) { + /* timer2 off */ + BLUE_CTRL->TIMEOUT = TIMER_OFF | BLUE_SLEEP_ENABLE; + blueglob->Config = 0; + } + else { + blueglob->Config = (blueglob->Config & 0xFFF0) | (next->StateMachineNo | 0x48); + p= &next->trans_packet; + (bluedata + next->StateMachineNo)->stat_config = next->trans_config; + (bluedata + next->StateMachineNo)->txpoint = BLUE_STRUCT_PTR_CAST(p); + (bluedata + next->StateMachineNo)->rcvpoint = BLUE_STRUCT_PTR_CAST(p); + +#ifdef BLUENRG2_DEVICE + (bluedata + next->StateMachineNo)->remap_chan = (bluedata+next->StateMachineNo)->remap_chan | 0x80; +#endif + + /* Packet will execute on time specified by WakeupTime */ + if( (next->ActionTag & TIMER_WAKEUP ) !=0 ) { + /* timer2 off */ + BLUE_CTRL->TIMEOUT = TIMER_OFF | BLUE_SLEEP_ENABLE; + + /* program timer at next->wakeuptime */ + if((next->ActionTag & RELATIVE ) !=0) { + globalParameters.wakeupTime = BLUE_CTRL->CURRENT_TIME; + globalParameters.wakeupTime = globalParameters.wakeupTime + us_time_translate(next->WakeupTime); + /* Adding the correction factor 1.1875*HS_STARTUP_TIME + HW_OFFSET for all packet except first packet for XC oscillator */ + globalParameters.wakeupTime = globalParameters.wakeupTime -((IFR->hs_startup_time) + (IFR->hs_startup_time>>2) - (IFR->hs_startup_time>>4)) - ANALOG_HW_OFFSET - TIMING_ERROR_CORRECTION; + + globalParameters.wakeupTime =(globalParameters.wakeupTime & 0x00FFFFFF); + } + else { + globalParameters.wakeupTime = next->WakeupTime; + globalParameters.wakeupTime =(globalParameters.wakeupTime & 0x00FFFFFF); + } + + BLUE_CTRL->TIMEOUT = (globalParameters.wakeupTime | WAKEUP_TIMER_TRIGGER | BLUE_SLEEP_ENABLE); + + /* if(timerSelect(next->WakeupTime) == BLE_STATUS_SUCCESS) { + blue->Timeout = (globalParameters.wakeupTime | WAKEUP_TIMER_TRIGGER | BLUE_SLEEP_ENABLE); + } + else { + blue->Timeout = globalParameters.wakeupTime | TIMER1_TIMER_TRIGGER; + }*/ + } + /* back to back */ + else { + } + } + + /* Accept the packet even with CRC Error */ + if( ( (int_value & IRQ_RCV_OK) != 0) || ( (int_value & IRQ_CRC_ERR) != 0) ) { + /* read RSSI */ + globalParameters.current_action_packet->rssi = read_RSSI(); + + /* bluedata->config = bluedata->config ^ 0x80 ; toggle NESN bit + bluedata->config = bluedata->config & 0x7F ; //reset NESN bit */ + + /* read time stamp */ + globalParameters.current_action_packet->timestamp_receive = BLUE_CTRL->TIMER_CAPTURE; + } + + actionPacketBackup = globalParameters.current_action_packet; + globalParameters.current_action_packet = next; + actionPacketBackup->dataRoutine(actionPacketBackup, next); + } + + if ( (int_value & IRQ_WAKEUP_2) != 0) { + RADIO_HostTimerCallback(); + } + if (int_value & BIT_TIME_OVERRUN) { + // Timer overrun!!! + RADIO_TimerOverrunCallback(); + } + + /* clear interrupts */ + BLUE_CTRL->INTERRUPT = int_value; + + return ; +} + +/** +* @brief This routine force the radio to be stopped. After calling this function, +* the ISR is not triggered unless, "MakeActionPacketPending" API called again. +* @param None +* @retval TRUE +*/ +uint8_t RADIO_StopActivity(void) +{ + MASK_INTERRUPTS(); + blueglob->Config = 0; + BLUE_CTRL->TIMEOUT = TIMER_OFF | BLUE_SLEEP_ENABLE; + globalParameters.current_action_packet = 0; + globalParameters.forceRadiotoStop = TRUE; + + UNMASK_INTERRUPTS(); + return TRUE; +} + + +/** +* @brief This routine sets the 40-bit receive and transmit packet count, to be used in +* encryption calculation. +* Both are pointers to char, and set the 39-bit counter + 1-bit MSB as defined in the +* Bluetooth Low Energy spec. One is for transmit packets, the other is for receive packets. +* @param StateMachineNo: state machine number in multi state. From 0 to 7. +* @param count_tx: 40-bit transmit packet count, to be used in encryption nounce calculation. +* @param count_rcv: 40-bit receive packet count, to be used in encryption nounce calculation. +* @retval None +*/ +void RADIO_SetEncryptionCount(uint8_t StateMachineNo, uint8_t *count_tx, uint8_t *count_rcv) +{ + /* Check the parameters */ + assert_param(IS_STATE_VALID(StateMachineNo)); + + for(uint8_t i = 0; i < 5; i++) { + (bluedata + StateMachineNo)->Pack_count_Rcv[i] = count_rcv[i]; + (bluedata + StateMachineNo)->Pack_count_Tx[i] = count_tx[i]; + } + return; +} + + +/** +* @brief This routines sets the 8-byte encryption initial vector, and the 16-byte encryption key. +* The definition of the encryption key and its initial value is according the Bluetooth Low Energy spec. +* @param StateMachineNo: state machine number in multi state. From 0 to 7. +* @param enc_iv: 8-byte encryption initial vector. +* @param enc_key: 16-byte encryption key. +* @retval None +*/ +void RADIO_SetEncryptionAttributes(uint8_t StateMachineNo, uint8_t *enc_iv, uint8_t *enc_key) +{ + uint8_t i = 0; + + /* Check the parameters */ + assert_param(IS_STATE_VALID(StateMachineNo)); + + for(i = 0; i < 8; i++) { + (bluedata + StateMachineNo)->enc_iv[i] = enc_iv[i]; + (bluedata + StateMachineNo)->enc_key[i] = enc_key[i]; + } + for(i = 8; i < 16; i++) { + (bluedata + StateMachineNo)->enc_key[i] = enc_key[i]; + } + + return ; +} + + +/** +* @brief This routine sets the channel map. If channel map is not in use, do not use it. The +* chan_remap constant is a 37-bit vector, one bit per channel from 0 to 36, with the +* LSB corresponding to the channel 0. If the corresponding bit is set, the channel is in use; if it is cleared, +* there is an automatic remap to another channel, as defined in the Bluetooth Low +* Energy specification. +* Setting all bits of the array to one, disables the channel remapping, and this is the mode +* that should be used if the Bluetooth channel remap is not in use. +* +* @param StateMachineNo: state machine number in multi state. From 0 to 7. +* @param chan_remap: a 37-bit vector, one bit per channel from 0 to 36, with the LSB corresponding to the channel 0 +* @retval None +*/ +void RADIO_SetChannelMap(uint8_t StateMachineNo,uint8_t *chan_remap) +{ + /* Check the parameters */ + assert_param(IS_STATE_VALID(StateMachineNo)); + + for(uint8_t i = 0; i < 5; i++) { + (bluedata + StateMachineNo)->chan_remap[i] = chan_remap[i]; + } + return ; +} + + +/** +* @brief This routine sets the channel and the channel increment. Channel and channel +* increment follows channel mapping corresponding to Bluetooth specification. +* RF channel 0: 2402 MHz -> channel 37 +* RF channel 1: 2404 MHz -> channel 0 +* RF channel 2: 2406 MHz -> channel 1 +* ... +* RF channel 11: 2424 MHz -> channel 10 +* RF channel 12: 2426 MHz -> channel 38 +* RF channel 13: 2428 MHz -> channel 11 +* RF channel 14: 2430 MHz -> channel 12 +* ... +* RF channel 38: 2478 MHz -> channel 36 +* RF channel 39: 2480 MHz -> channel 39 +* +* For the channel 37, 38 and 39 (RF channel 0, 12, 39): +* - The crc_init value should always be 0x555555. +* - There is no encryption. +* - The channel increment is dedicated, the channel sequence is: +* 37 -> 38 -> 39 -> 37 -> ... while for the other channels is: +* 0 -> 1 -> ... -> 36 -> 0 -> ... +* There is no channel map for these three channels. +* Valid values for packet length for these channels are from 6 to 37. +* @param StateMachineNo: state machine number in multi state. From 0 to 7. +* @param channel: frequency channel. From 0 to 39. +* @param channel_increment: determines the hoping value. +* @retval None +*/ +void RADIO_SetChannel(uint8_t StateMachineNo, uint8_t channel, uint8_t channel_increment) +{ + /* Check the parameters */ + assert_param(IS_STATE_VALID(StateMachineNo)); + assert_param(IS_RFCHANNEL_VALID(channel)); + + (bluedata + StateMachineNo)->unmapped_chan = channel; + (bluedata + StateMachineNo)->hop_incr = channel_increment; + + return ; +} + + +/** +* @brief This routine sets the NetworkID, the CRC init, and the SCA. +* @param StateMachineNo: state machine number in multi state. From 0 to 7. +* @param NetworkID: The NetworkID is the ID of the device. +* The user shall ensure that the NetworkID meets the following requirements: +* - It shall have no more than six consecutive zeros or ones. +* - It shall not have all four octets equal. +* - It shall have no more than 24 transitions. +* - It shall have a minimum of two transitions in the most significant six bits. +* @param crc_init: CRC initilization value. +* This value must be 0x555555 when channel frequency is one of these values: 37, 38, 39. +* @param sca: slow clock accuracy. Period duration of the 32 kHz clock (slow clock). +* "period_slow" defines the number of 16 MHz clock cycle in a 32 kHz period. +* Note: the number 16 MHz clock cycle in a 32 kHz period can be measured by the clockgen block. +* Note: If the application uses a CLK32K crystal then the value is a constant provided by the firmware. (488 = 16,000,000 / 32768) +* Note: If the application uses the 32 kHz RC clock, then its value is measured in the clock_gen. +* Note: not used here. This value should be set automatically in RADIO_CrystalCheck routine. +* @retval None +*/ +void RADIO_SetTxAttributes(uint8_t StateMachineNo, uint32_t NetworkID, uint32_t crc_init, uint32_t sca) +{ + /* Check the parameters */ + assert_param(IS_STATE_VALID(StateMachineNo)); + + (bluedata + StateMachineNo)->access_address = NetworkID; + (bluedata + StateMachineNo)->crc_init = crc_init; + + /* blueglob->period_slow = sca; */ + return; +} + + + +/** +* @brief Initializes the time between back-to-back radio transmissions. +* @param back_to_back_time: time between two packets if wakeupTimer is not used. Resolution is 1 us. +* @retval None +*/ +void RADIO_SetBackToBackTime(uint32_t back_to_back_time) +{ + globalParameters.back2backTime = back_to_back_time; + return; +} + + +/** +* @brief Configures the transmit power level. +* @param PowerLevel: power level which should set to this value: +* - 0 = -18 dBm, +* - 1 = -15 dBm, +* - 2 = -12 dBm, +* - 3 = -9 dBm, +* - 4 = -6 dBm, +* - 5 = -2 dBm, +* - 6 = 0 dBm, +* - 7 = 5 dBm. +* +* - 8 = -14 dBm, +* - 9 = -11 dBm, +* - 10 = -8 dBm, +* - 11 = -5 dBm, +* - 12 = -2 dBm, +* - 13 = 2 dBm, +* - 14 = 4 dBm, +* - 15 = 8 dBm. +* @retval None +*/ +void RADIO_SetTxPower(uint8_t PowerLevel) +{ + /* Check the parameters */ + assert_param(IS_POWERLEVEL_VALID(PowerLevel)); + + PowerLevel <<= 3; + for(int n = 0; n conf_byte5 = PowerLevel; + } + return; +} + + +/** +* @brief This routine turns encrypt ON and OFF. When the encryption is enabled, the hardware will add 4 bytes +* at the end of the packet as MIC (Message Authentication Code). So the user need to add 4 byte to the +* length of the packet. The parameters enable the encryption for both. There are two separated parameters +* for this function just compliance with previous version of the driver. +* @param StateMachineNo: state machine number in multi state. From 0 to 7. +* @param EncryptFlagTx: DISABLE: encryption is turned OFF for both TX and RX operations. +* ENABLE: encryption is turned OFF for both TX and RX operations. +* This parameter can be: ENABLE or DISABLE. +* @param EncryptFlagRcv: encryption is turned OFF for both TX and RX operations. +* ENABLE: encryption is turned OFF for both TX and RX operations. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void RADIO_SetEncryptFlags(uint8_t StateMachineNo, FunctionalState EncryptFlagTx, FunctionalState EncryptFlagRcv) +{ + /* Check the parameters */ + assert_param(IS_STATE_VALID(StateMachineNo)); + assert_param(IS_FUNCTIONAL_STATE(EncryptFlagTx)); + assert_param(IS_FUNCTIONAL_STATE(EncryptFlagRcv)); + + if(EncryptFlagTx==ENABLE || EncryptFlagRcv==ENABLE) { + (bluedata + StateMachineNo)->config = (bluedata + StateMachineNo)->config | 0x0A; + } + else { + (bluedata + StateMachineNo)->config = (bluedata + StateMachineNo)->config & 0xF5; + } + return; +} + + +/** +* @brief This routine should be called after writing/modifying an action packet, and before it +* is executed via either the API mechanism, or the next mechanism. +* @param p: pointer to action packet. +* @retval None +*/ +void RADIO_SetReservedArea(ActionPacket *p) +{ + //p->WakeupTime = (uint32_t) (p->WakeupTime * 0.525); /* convert us to appropriated value. 1000 * 1/512000 = 1953.125 */ + + /* Check the parameters */ + assert_param(IS_DELAY_VALID(p->WakeupTime)); + + p->trans_packet.datptr = BLUE_DATA_PTR_CAST(p->data); + + /* rcvlen[17:0] */ + if(p->ReceiveWindowLength < 0x40000) { + p->trans_packet.rcvlen[0] = (p->ReceiveWindowLength) & 0x000000FF ; + p->trans_packet.rcvlen[1] = (p->ReceiveWindowLength >> 8) & 0x000000FF ; + p->trans_packet.rcvlen[2] = (p->ReceiveWindowLength >> 16) & 0x00000003 ; + } + else if(p->ReceiveWindowLength < 0x100000) { + p->trans_packet.rcvlen[0] = (p->ReceiveWindowLength >> 2) & 0x000000FF ; + p->trans_packet.rcvlen[1] = (p->ReceiveWindowLength >> 10) & 0x000000FF ; + p->trans_packet.rcvlen[2] = (p->ReceiveWindowLength >> 18) & 0x00000003 ; + + p->trans_packet.rcvlen[2] |= 0x04; + } + else if(p->ReceiveWindowLength < 0x400000) { + p->trans_packet.rcvlen[0] = (p->ReceiveWindowLength >> 4) & 0x000000FF ; + p->trans_packet.rcvlen[1] = (p->ReceiveWindowLength >> 12) & 0x000000FF ; + p->trans_packet.rcvlen[2] = (p->ReceiveWindowLength >> 20) & 0x00000003 ; + + p->trans_packet.rcvlen[2] |= 0x08; + } + else if(p->ReceiveWindowLength < 0x1000000) { + p->trans_packet.rcvlen[0] = (p->ReceiveWindowLength >> 6) & 0x000000FF ; + p->trans_packet.rcvlen[1] = (p->ReceiveWindowLength >> 14) & 0x000000FF ; + p->trans_packet.rcvlen[2] = (p->ReceiveWindowLength >> 22) & 0x00000003 ; + + p->trans_packet.rcvlen[2] |= 0x0C; + } + else { + /* error */ + } + + if((p->ActionTag & TIMESTAMP_POSITION) == 0) { + p->trans_packet.rcvlen[2] |= TIMESTAMP_POSITION_LASTBIT; + } + else { + p->trans_packet.rcvlen[2] |= TIMESTAMP_POSITION_ACCESSADDRESS; + } + + /* p->trans_packet.rcvlen[2] = p->trans_packet.rcvlen[2] | 0x30 | 0x40 | TIMESTAMP_POSITION; */ + p->trans_packet.rcvlen[2] = p->trans_packet.rcvlen[2] | 0x30; + + p->trans_packet.timeout[0] = (globalParameters.back2backTime >> 0) & 0x000000FF; + p->trans_packet.timeout[1] = (globalParameters.back2backTime >> 8) & 0x000000FF; + p->trans_packet.timeout[2] = (globalParameters.back2backTime >> 16) & 0x0000000F; /* only 20 bits */ + + p->trans_packet.byte10 =0; + p->trans_packet.byte10 = (p->ActionTag & INC_CHAN) | (p->ActionTag & PLL_TRIG) | (p->ActionTag & TXRX); + + /* next state is zero */ + p->trans_packet.byte10 = p->trans_packet.byte10 & 0x1F; + + /* sleep . do not go to sleep*/ + p->trans_packet.byte10 = p->trans_packet.byte10 & 0xFB; + + /* for multi-state automatically increment the channel */ + p->trans_packet.byte10 = p->trans_packet.byte10 | ((p->StateMachineNo)<<5); + + /* enable all interrupts */ + p->trans_packet.byte11 = 0xFF; + + p->trans_config =0; + if( (p->ActionTag & TXRX) != 0) { + p->trans_config = 0x80; + } + + return ; +} + + +/** +* @brief This routine should be called for the first actionPacket that needs to be scheduled +* on the radio. For it to work OK, the WakeupTime should be valid, and the TIMER_WAKEUP flag set. +* Subsequent packets can be dispatched using the same process, or by providing non-NULL pointers +* to the next_true and next_false pointers of the ActionPacket. +* +* @param p: pointer to action packet. +* @retval uint8_t with following values: +* - 0x00 : Success. +* - 0xC4 : Radio is busy, action packet has not been executed. +*/ +uint8_t RADIO_MakeActionPacketPending(ActionPacket *p) +{ + uint8_t returnValue = SUCCESS_0; + uint32_t dummyTime ; + + if(RADIO_GetStatus(&dummyTime) == BLUE_IDLE_0) + { + globalParameters.forceRadiotoStop = FALSE; + uint16_t statemachineNo; + BlueTransStruct *p1 ; + + /* timer2 off */ + BLUE_CTRL->TIMEOUT = TIMER_OFF | BLUE_SLEEP_ENABLE; + globalParameters.rssiLevel[0] = 0x2e86 ; + globalParameters.rssiLevel[1] = 0 ; + + int32_t* temp ; + temp = globalParameters.hot_ana_config_table_a; + blueglob->RadioConfigPtr = BLUE_DATA_PTR_CAST(temp) ; /* to be discussed */ + + /* Set_Radio_Config_Data(); */ /* to be discussed */ + + /* tell the schedular which table in SRAM should be applied and activate it */ + statemachineNo = 0x0007 & p->StateMachineNo; + + blueglob->Config = (blueglob->Config & 0xFFF0) | (statemachineNo | 0x48); + + (bluedata+statemachineNo)->txpoint_prev = 0; + (bluedata+statemachineNo)->rcvpoint_prev = 0; + (bluedata+statemachineNo)->txpoint_next = 0; + + p1= &p->trans_packet; + (bluedata+statemachineNo)->txpoint = BLUE_STRUCT_PTR_CAST(p1); + (bluedata+statemachineNo)->rcvpoint = BLUE_STRUCT_PTR_CAST(p1); + +#ifdef BLUENRG2_DEVICE + (bluedata+statemachineNo)->remap_chan = (bluedata+statemachineNo)->remap_chan | 0x80; +#endif + + globalParameters.current_action_packet = p; + (bluedata+statemachineNo)->stat_config = p->trans_config; /* Transmision or reception for first packet */ + + /* program timer at next->wakeuptime */ + MASK_INTERRUPTS(); + if((p->ActionTag & RELATIVE ) !=0) { + globalParameters.wakeupTime = BLUE_CTRL->CURRENT_TIME; + /* Adding the correction factor 1.1875*HS_STARTUP_TIME + ANALOG_HW_OFFSET for the first packet */ + globalParameters.wakeupTime = globalParameters.wakeupTime + us_time_translate(p->WakeupTime) - (IFR->hs_startup_time + (IFR->hs_startup_time>>2)-(IFR->hs_startup_time>>4)) - ANALOG_HW_OFFSET; + globalParameters.wakeupTime =(globalParameters.wakeupTime & 0x00FFFFFF); + } + else { + globalParameters.wakeupTime = p->WakeupTime; + globalParameters.wakeupTime =(globalParameters.wakeupTime & 0x00FFFFFF); + } + BLUE_CTRL->TIMEOUT = (globalParameters.wakeupTime | WAKEUP_TIMER_TRIGGER | BLUE_SLEEP_ENABLE); + UNMASK_INTERRUPTS(); + } + else { + returnValue = RADIO_BUSY_C4; + } + + return returnValue; +} + + +/** +* @brief This function performs the automatic calibration procedure on the BLE period_slow hardware register when +* the value of hardware_config.ls_source variable is non-zero. In this case, also +* the internal BLE stack timing reference is tuned accordingly. +* When the hardware_config.ls_source is zero, the period_slow register value is set on the +* basis of the LS_CRYSTAL_PERIOD macro. In this case, the internal BLE stack timing reference is +* set according to the LS_CRYSTAL_FREQ and LS_CRYSTAL_PERIOD macros. +* In any cases, the resulting internal BLE stack timing reference is used to set the BLE wakeup_time_offset +* hardware register according to the hardware_config.hs_startup_time content. +* @param None +* @retval None +*/ +void RADIO_CrystalCheck(void) +{ + Clk32Context_t *Clk32Context_p = &(globalParameters.Clk32Context); + BOOL new_computation_flag = Clk32Context_p->period == -1; + if(IFR->ls_source != 0) /* using internal RO */ + { + if (new_computation_flag) + { + int32_t freq1 = 0 ; + int32_t var1 = 0; + int32_t freq2; + do{ + freq2 = freq1 ; + freq1 = CKGEN_BLE->CLK32K_FREQ; /*reading frequency from hardware */ + var1++; + }while((freq1 != freq2 || freq1 == 0) && var1 < 5000); /* repeat until two consecutive reading are equal */ + Clk32Context_p->freq = freq1; + Clk32Context_p->period = CKGEN_BLE->CLK32K_PERIOD; + Clk32Context_p->calibr.Time_mT = GET_CUR_TIME; + BlueNRG_Start_Crystal_Measurement(); + } + else{ + uint32_t current_time_mT = GET_CUR_TIME; + if ((Clk32Context_p->calibr.started_flag != 0) && (CKGEN_BLE->CLK32K_IT != 0) ) + { + Clk32Context_p->freq = CKGEN_BLE->CLK32K_FREQ; + Clk32Context_p->period = CKGEN_BLE->CLK32K_PERIOD; + Clk32Context_p->calibr.started_flag = 0; + Clk32Context_p->calibr.Time_mT = current_time_mT; + new_computation_flag = TRUE; + } + else{ + if ((Clk32Context_p->calibr.started_flag == 0) && (((uint32_t)TIME24_DIFF(current_time_mT, Clk32Context_p->calibr.Time_mT)) > (1000<<9)))/* [RG:] about 1sec +/-20% */ + { + BlueNRG_Start_Crystal_Measurement(); + } + } + } + } + else { /* using external Crystal */ + Clk32Context_p->period = 0; + } + + if (new_computation_flag == TRUE ) + { + set_freq(Clk32Context_p->freq,Clk32Context_p->period) ; + } + +} + +/** +* @brief Initializes the radio. +* @param hs_startup_time: start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us). +* @param low_speed_osc: source for the 32 kHz slow speed clock: 1: internal RO; 0: external crystal. +* @param hot_table: reserved for future use, set to NULL. +* @param whitening: DISABLE: disable whitening for TX and RX. ENABLE: enable whitening for TX and RX. +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void RADIO_Init(uint16_t hs_startup_time, uint8_t low_speed_osc, uint32_t* hot_table, FunctionalState whitening) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(whitening)); + + DISABLE_INTERRUPT(IRQBLUE); + + blueglob->TxDelay = TX_DELAY; + blueglob->TxDelay1 = TX_DELAY1; + blueglob->RcvDelay = RX_DELAY; + blueglob->RcvDelay1 = RX_DELAY1; + + if(whitening == DISABLE) { + /* disable Transmision Whitening */ + blueglob->TxDelay |= 0x80; + blueglob->TxDelay1 |= 0x80; + + /* disable Receiving Whitening */ + blueglob->RcvDelay |= 0x80; + blueglob->RcvDelay1 |= 0x80; + } + + globalParameters.hardware_config.hs_startup_time = hs_startup_time; + globalParameters.hardware_config.ls_source = low_speed_osc; + globalParameters.hardware_config.hot_ana_config_table = hot_table; + + blueglob->Config = 0; + BLUE_CTRL->TIMEOUT = TIMER_OFF | BLUE_SLEEP_ENABLE ; + BLUE_CTRL->HOST_WKUP_TIMER = TIMER_OFF | (1<INTERRUPT ; + BLUE_CTRL->INTERRUPT = int_value ; + + blueglob->period_slow = SCA_DEFAULTVALUE; + +#if BLUENRG_START_CRYSTAL_MEASUREMENT_CALLED_EXTERNALLY != 0 + if (Clk32Context.calibr.started_flag != 1){ + CKGEN_BLE->CLK32K_IT = 1; + BlueNRG_Start_Crystal_Measurement(); + } +#else + CKGEN_BLE->CLK32K_COUNT = 23 ; +#endif + + globalParameters.back2backTime = 150; /* 150 micro second */ + globalParameters.forceRadiotoStop = FALSE; + globalParameters.powerUpfirstPacket = 1; + globalParameters.Clk32Context.period = -1; + + RADIO_CrystalCheck(); + + RADIO_SetTxPower(11); + RADIO_SetEncryptFlags(0, DISABLE, DISABLE); + + //blueglob->wakeup_time_offset= 0x07; /* 30.51us */ + + ENABLE_INTERRUPT(IRQBLUE); + ENABLE_INTERRUPT(IRQNVM); + + return; +} + + +/** +* @brief This routine returns the status of the Radio whether it is busy or not. +* If it is busy, the time argument will be filled with absolute time value of next radio activity. +* User can use this value (in comparison with current time) to check that +* how long it is far to force the device to sleep or not. +* Note: when Timer2 is on schedule, time value is not absolute time. +* @param time: pointer to int value which is going to have time value. +* @retval uint8_t with following values: +* - 0 : BLUE_IDLE_0. Radio is not busy. +* - 1 : BLUE_BUSY_NOWAKEUP_T1. Radio is busy, but there is no wakeup timer on schedule but Timer1 is. +* - 2 : BLUE_BUSY_NOWAKEUP_T2. Radio is busy, but there is no wakeup timer on schedule but Timer2 is. +* - 3 : BLUE_BUSY_WAKEUP. Radio is busy and wakeup timer is on the schedule. +*/ +uint8_t RADIO_GetStatus(uint32_t *time) +{ + uint8_t retValue = BLUE_IDLE_0; + uint32_t timeOut; + if((blueglob->Config & 0x8) != 0) + { + timeOut = BLUE_CTRL->TIMEOUT; + *time = timeOut; + timeOut = (timeOut >> 24) & 0x07; + if(timeOut == TIMER2_TIMER_MASK) + { + retValue = BLUE_BUSY_NOWAKEUP_T2; + } + else if(timeOut == TIMER1_TIMER_MASK) + { + retValue = BLUE_BUSY_NOWAKEUP_T1; + } + else if(timeOut == WAKEUP_TIMER_MASK) + { + retValue = BLUE_BUSY_WAKEUP; + } + + /* *time =globalParameters.wakeupTime; */ + } + + return retValue; +} + + +/** +* @brief Starts tone transmission on selected channel. +* This API is dedicated for test and destroys context and multistate. +* So, after calling this function the radio should be re-initialized. +* @param RF_Channel: radio frequency channel number from 0 to 39. +* @param PowerLevel: power level which should set to this value: +* - 0 = -18 dBm, +* - 1 = -15 dBm, +* - 2 = -12 dBm, +* - 3 = -9 dBm, +* - 4 = -6 dBm, +* - 5 = -2 dBm, +* - 6 = 0 dBm, +* - 7 = 5 dBm. +* +* - 8 = -14 dBm, +* - 9 = -11 dBm, +* - 10 = -8 dBm, +* - 11 = -5 dBm, +* - 12 = -2 dBm, +* - 13 = 2 dBm, +* - 14 = 4 dBm, +* - 15 = 8 dBm. +* @retval None +*/ +void RADIO_StartTone(uint8_t RF_Channel, uint8_t powerLevel) +{ + /* Check the parameters */ + assert_param(IS_RFCHANNEL_VALID(RF_Channel)); + assert_param(IS_POWERLEVEL_VALID(powerLevel)); + + uint8_t channel; + uint8_t value1; + uint8_t value2; + uint32_t dummy; + char data[24]; + + if (RADIO_GetStatus(&dummy) == BLUE_IDLE_0) { + /* [EM:] Calculate the synt divide factor for 16 MHz quarts and +250 kHz offset wrt the channel center frequency + * Algorithmically MAK = F_rf*(2^20)/16 = F_rf*(2^16) + * With F_rf = (2402+2*RF_Channel)+0.25 MHz + * K corresponds to b19-b0 of MAK + * A corresponds to b22-b20 of MAK + * M corresponds to b27-b23 of MAK + */ + uint32_t kHz_250_scaled = 16384; /* = 0.250*2^20/16 */ + uint32_t MAK = ((2402+2*RF_Channel)<<16) - kHz_250_scaled; + uint8_t M = (MAK>>23)&0x1F; + uint8_t A = (MAK>>20)&0x07; + uint32_t K = (MAK&0x000FFFFF)+1; + uint8_t MOD3_DIG_TEST = (M<<3) | (A & 0x7); + uint8_t MOD2_DIG_TEST = ((K>>12) & 0xFF); + uint8_t MOD1_DIG_TEST = ((K>> 4) & 0xFF); + uint8_t MOD0_DIG_TEST = ((K&0x0F)<<4) | 0x09; + + value1 = 0x7E & 0x87; + + value1 |= (powerLevel << 3); + value2 = 0x3F & 0xF1; + powerLevel &= 0x07; + value2 |= (powerLevel << 1); + + channel = RF_Channel; + channel <<= 1; + data[0] = 0x03; + data[1] = 0x04; + data[2] = channel; // addr 0x4, value channel + data[3] = value1; // addr 0x5, value TX power + data[4] = 0x02; + data[5] = 0x1C; // addr 0x1C, value 0x73 + data[6] = 0x73; + data[7] = 0x03; + data[8] = 0x24; + data[9] = value2; // addr 0x24, value 0x3F + data[10] = 0x3F; // addr 0x25, value 0x3F + data[11] = 0x02; + data[12] = 0x23; + data[13] = 0x03; // addr 0x23, value 0x03 + data[14] = 0x02; + data[15] = 0x23; + data[16] = 0x07; // addr 0x23, value 0x07� + /*[EM:] Fix 204: force MAK values through MODx test registers */ + data[17] = 0x05; + data[18] = 0x28; + data[19] = MOD3_DIG_TEST; + data[20] = MOD2_DIG_TEST; + data[21] = MOD1_DIG_TEST; + data[22] = MOD0_DIG_TEST; + + data[23] = 0x0; + + write_radio_config(data); + } +} + + +/** +* @brief This routine starts tone transmission. +* This API is dedicated for test and destroys context and multistate. +* So, after calling this function the radio should be re-initialized. +* @param None +* @retval None +*/ +void RADIO_StopTone() +{ + char data[9]; + + data[0] = 0x04; + data[1] = 0x23; + data[2] = 0x00; // addr 0x23, value 0x00 + data[3] = 0x0E; // addr 0x24, value 0x0E + data[4] = 0x00; // addr 0x25, value 0x00 + data[5] = 0x02; //[EM:] Fix 204 + data[6] = 0x2B; // Reg MOD0_DIG_TEST@0x2B + data[7] = 0x08; // Reset to default value (disable mod test mode) + data[8] = 0x00; + write_radio_config(data); +} + + +/** +* @brief Encrypts plain text data using AES encryption with given input key and +* 128 bit block size +* @param Key: encryption key to be used. +* @param plainData: text data to be encrypted. +* @param cypherData: contains the encrypted data. +* @retval None +*/ +void RADIO_EncryptPlainData(uint8_t *Key, + uint8_t *plainData, + uint8_t *cypherData) +{ + uint32_t key[4] ; + uint32_t cleartext[4] ; + uint32_t ciphertext[4] ; + volatile uint32_t ii ; + + for(uint8_t i = 0; i < 4; i++) { + key[i] = ((uint32_t)Key[i*4]) | ((uint32_t)Key[i*4+1])<<8 | ((uint32_t)Key[i*4+2])<<16 | ((uint32_t)Key[i*4+3])<<24; + cleartext[i] = ((uint32_t)plainData[i*4]) | ((uint32_t)plainData[i*4+1])<<8 | ((uint32_t)plainData[i*4+2])<<16 | ((uint32_t)plainData[i*4+3])<<24; + } + + BLUE_CTRL->AES_KEY0 = key[3]; + BLUE_CTRL->AES_KEY1 = key[2]; + BLUE_CTRL->AES_KEY2 = key[1]; + BLUE_CTRL->AES_KEY3 = key[0]; + + BLUE_CTRL->CLEAR_TEXT0 = cleartext[3]; + BLUE_CTRL->CLEAR_TEXT1 = cleartext[2]; + BLUE_CTRL->CLEAR_TEXT2 = cleartext[1]; + BLUE_CTRL->CLEAR_TEXT3 = cleartext[0]; + + ii = 0 ; + while( ( BLUE_CTRL->STATUS & BIT_AES_READY) == 0 && ii < 100) { + ii++ ;} + + ciphertext[0] = BLUE_CTRL->AES_CYPHERTEXT3; + ciphertext[1] = BLUE_CTRL->AES_CYPHERTEXT2; + ciphertext[2] = BLUE_CTRL->AES_CYPHERTEXT1; + ciphertext[3] = BLUE_CTRL->AES_CYPHERTEXT0; + + for(uint8_t i = 0; i < 4; i++) { + cypherData[i*4] = ((uint8_t)ciphertext[i]); + cypherData[i*4+1] = (uint8_t)(ciphertext[i]>>8); + cypherData[i*4+2] = (uint8_t)(ciphertext[i]>>16); + cypherData[i*4+3] = (uint8_t)(ciphertext[i]>>24); + } + + return ; +} + + +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_rng.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_rng.c new file mode 100644 index 00000000000..e60b9a4a771 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_rng.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_rng.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @defgroup RNG_Peripheral RNG Peripheral + * @{ + */ + +/** @defgroup RNG_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Private_Defines Private Defines + * @{ + */ + + +/** + * @} + */ + +/** @defgroup RNG_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Private_Functions Private Functions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RNG_Public_Functions Public Functions +* @{ +*/ + +/** + * @brief Enables or disables the specified RNG peripheral. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RNG_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Disable RNG peripheral */ + RNG->CR_b.DIS = RESET; + } + else { + /* Enable RNG peripheral */ + RNG->CR_b.DIS = SET; + } +} + + +/** + * @brief Checks if the RNG flag is set or not. +* @retval FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. + */ +FlagStatus RNG_GetFlagStatus(void) +{ + if (RNG->SR_b.RDY == SET) { + return SET; + } + else { + return RESET; + } + +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_rtc.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_rtc.c new file mode 100644 index 00000000000..1082278bd0d --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_rtc.c @@ -0,0 +1,410 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_rtc.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @defgroup RTC_Peripheral RTC Peripheral + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Defines Private Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Public_Functions Public Functions +* @{ +*/ + +/** + * @brief Initializes the RTC peripheral according to the specified + * parameters in the RTC_InitStruct. + * @param RTC_InitStruct: pointer to a @ref RTC_InitType structure that + * contains the configuration information for the specified RTC peripheral. + * @retval None + */ +void RTC_Init(RTC_InitType* RTC_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_TIMER_MODE(RTC_InitStruct->RTC_operatingMode)); + assert_param(IS_PATTERN(RTC_InitStruct->RTC_PATTERN_SIZE)); + + RTC->TCR_b.OS = RTC_InitStruct->RTC_operatingMode; + RTC->TCR_b.SP = RTC_InitStruct->RTC_PATTERN_SIZE; + + RTC->TLR1 = RTC_InitStruct->RTC_TLR1; + RTC->TLR2 = RTC_InitStruct->RTC_TLR2; + RTC->TPR1 = RTC_InitStruct->RTC_PATTERN1; + RTC->TPR2 = RTC_InitStruct->RTC_PATTERN2; + RTC->TPR3 = RTC_InitStruct->RTC_PATTERN3; + RTC->TPR4 = RTC_InitStruct->RTC_PATTERN4; + +} + +/** +* @brief Fills the RTC_InitStruct member with its default value. +* @param RTC_InitStruct : pointer to a @ref RTC_InitType structure which will +* be initialized. +* @retval None +*/ +void RTC_StructInit(RTC_InitType* RTC_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + RTC_InitStruct->RTC_operatingMode = RTC_TIMER_PERIODIC; + RTC_InitStruct->RTC_PATTERN_SIZE = 0; + + RTC_InitStruct->RTC_TLR1 = 0; + RTC_InitStruct->RTC_TLR2 = 0; + RTC_InitStruct->RTC_PATTERN1 = 0; + RTC_InitStruct->RTC_PATTERN2 = 0; + RTC_InitStruct->RTC_PATTERN3 = 0; + RTC_InitStruct->RTC_PATTERN4 = 0; +} + + +/** + * @brief Enables or disables selected RTC peripheral. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + RTC->TCR_b.EN = SET; + } + else { + RTC->TCR_b.EN = RESET; + + } +} + +/** + * @brief Enables or disables selected RTC interrupt. + * @param RTC_IT: specifies the RTC interrupts sources, the value can be + * @arg RTC_IT_CLOCKWATCH RTC clock watch interrupt flag + * @arg RTC_IT_TIMER RTC timer interrupt flag + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_IT_Config(uint8_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_RTC_IT(RTC_IT)); + + if (RTC_IT == RTC_IT_CLOCKWATCH) { + /* Enable the selected RTC interrupts */ + RTC->IMSC_b.WIMSC = NewState; + } + else { + /* Disable the selected RTC interrupts */ + RTC->IMSC_b.TIMSC = NewState; + } +} + +/** + * @brief Return the RTC interrupt status for the specified IT. + * @param RTC_IT: specifies the RTC interrupts sources, the value can be + * @arg RTC_IT_CLOCKWATCH RTC clock watch interrupt flag + * @arg RTC_IT_TIMER RTC timer interrupt flag + * @retval ITStatus: functional state @ref ITStatus + * This parameter can be: SET or RESET. + */ +ITStatus RTC_IT_Status(uint8_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Check the status of the specified RTC flag */ + if ((RTC->RIS & RTC_IT) != RESET) { + /* RTC_IT is set */ + return SET; + } + else { + /* RTC_IT is reset */ + return RESET; + } +} + +/** + * @brief Clear selected RTC interrupt. + * @param RTC_IT: specifies the RTC interrupts sources, the value can be + * @arg RTC_IT_CLOCKWATCH RTC clock watch interrupt flag + * @arg RTC_IT_TIMER RTC timer interrupt flag + * @retval None + */ +void RTC_IT_Clear(uint8_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + RTC->ICR = RTC_IT; +} + + +/** + * @brief Enables or disables selected RTC clockwatch. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ClockwatchCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + RTC->CTCR_b.CWEN = SET; + } + else { + RTC->CTCR_b.CWEN = RESET; + } +} + +/** + * @brief Initialize the RTC clockwatch with present time and date. + * @param RTC_DateTime: pointer to a @ref RTC_DateTimeType structure that + * contains the specified time and date setting. + * @retval None + */ +void RTC_SetTimeDate(RTC_DateTimeType* RTC_DateTime) +{ + /* Check the parameters */ + assert_param(IS_SECOND(RTC_DateTime->Second)); + assert_param(IS_MINUTE(RTC_DateTime->Minute)); + assert_param(IS_HOUR(RTC_DateTime->Hour)); + assert_param(IS_WEEKDAY(RTC_DateTime->WeekDay)); + assert_param(IS_MONTHDAY(RTC_DateTime->MonthDay)); + assert_param(IS_MONTH(RTC_DateTime->Month)); + assert_param(IS_YEAR(RTC_DateTime->Year)); + + /** Select seconds from the data structure */ + RTC->CWDLR_b.CWSECL = RTC_DateTime->Second; + + /** Select minutes from the data structure */ + RTC->CWDLR_b.CWMINL = RTC_DateTime->Minute; + + /** Select hours from the data structure */ + RTC->CWDLR_b.CWHOURL = RTC_DateTime->Hour; + + /** Select week day from the data structure */ + RTC->CWDLR_b.CWDAYWL = RTC_DateTime->WeekDay; + + /** Select month day from the data structure */ + RTC->CWDLR_b.CWDAYML = RTC_DateTime->MonthDay; + + /** Select month from the data structure */ + RTC->CWDLR_b.CWMONTHL = RTC_DateTime->Month; + + /* Store data to load register */ + RTC->CWYLR_b.CWYEARL = RTC_DateTime->Year; +} + +/** + * @brief Set the RTC clockwatch match date and time registers. + * @param RTC_MatchDataTime: pointer to a @ref RTC_DateTimeType structure that + * contains the matching time and date setting. + * @retval None + */ +void RTC_SetMatchTimeDate(RTC_DateTimeType* RTC_MatchDataTime) +{ + /* Check the parameters */ + assert_param(IS_SECOND(RTC_MatchDataTime->Second)); + assert_param(IS_MINUTE(RTC_MatchDataTime->Minute)); + assert_param(IS_HOUR(RTC_MatchDataTime->Hour)); + assert_param(IS_MATCH_WEEKDAY(RTC_MatchDataTime->WeekDay)); + assert_param(IS_MATCH_MONTHDAY(RTC_MatchDataTime->MonthDay)); + assert_param(IS_MATCH_MONTH(RTC_MatchDataTime->Month)); + assert_param(IS_MATCH_YEAR(RTC_MatchDataTime->Year)); + + /* Select seconds from the data structure */ + RTC->CWDMR_b.CWSECM = RTC_MatchDataTime->Second; + + /* Select minutes from the data structure */ + RTC->CWDMR_b.CWMINM = RTC_MatchDataTime->Minute; + + /* Select hours from the data structure */ + RTC->CWDMR_b.CWHOURM = RTC_MatchDataTime->Hour; + + /* Select week day from the data structure */ + RTC->CWDMR_b.CWDAYWM = RTC_MatchDataTime->WeekDay; + + /* Select month day from the data structure */ + RTC->CWDMR_b.CWDAYMM = RTC_MatchDataTime->MonthDay; + + /* Select month from the data structure */ + RTC->CWDMR_b.CWMONTHM = RTC_MatchDataTime->Month; + +/* Select year from the data structure */ + RTC->CWYMR_b.CWYEARM = RTC_MatchDataTime->Year; +} + +/** + * @brief Set the RTC clockwatch match date and time registers. + * @param RTC_DataTime: pointer to a @ref RTC_DateTimeType structure that + * is filled with the configured values of time and date. + * @retval None + */ +void RTC_GetTimeDate(RTC_DateTimeType* RTC_DataTime) +{ + /* Select seconds from the RTC register */ + RTC_DataTime->Second = RTC->CWDR_b.CWSEC; + + /* Select minutes from the RTC register */ + RTC_DataTime->Minute= RTC->CWDR_b.CWMIN; + + /* Select hours from the RTC register */ + RTC_DataTime->Hour= RTC->CWDR_b.CWHOUR; + + /* Select week day from the RTC register */ + RTC_DataTime->WeekDay = RTC->CWDR_b.CWDAYW; + + /* Select month day from the RTC register */ + RTC_DataTime->MonthDay = RTC->CWDR_b.CWDAYM; + + /* Select month from the RTC register */ + RTC_DataTime->Month = RTC->CWDR_b.CWMONTH; + + /* Select year from the RTC register */ + RTC_DataTime->Year = RTC->CWYR_b.CWYEAR; +} + +/** + * @brief Return the actual timer counter. + * @param None + * @retval uint32_t the current counter value. + */ +uint32_t RTC_GetTimerValue(void) +{ + /* Return the current Time Data Register */ + return RTC->TDR; +} + +/** + * @brief Return the actual number of interrupt generated by RTC. + * @param None + * @retval uint32_t the actual number of interrupt generated by RTC. + */ +uint32_t RTC_GetNumberIrqGenerated(void) +{ + /* Return the current Time Data Register */ + return RTC->TIN; +} + + +/** + * @brief Enables or disables the auto start on load register or pattern register write operation. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_AutoStart(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + RTC->TCR_b.S = SET; + } + else { + RTC->TCR_b.S = RESET; + } +} + + +/** + * @brief Enables or disables the use of the trimmed 32 kHz clock. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_SelectTrimmedClock(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + RTC->TCR_b.CLK = SET; + } + else { + RTC->TCR_b.CLK = RESET; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_spi.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_spi.c new file mode 100644 index 00000000000..17a9a76dcc1 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_spi.c @@ -0,0 +1,710 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_spi.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver +* @{ +*/ + +/** @addtogroup SPI_Peripheral SPI Peripheral +* @{ +*/ + +/** @defgroup SPI_Private_TypesDefinitions Private Types Definitions +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Defines Private Defines +* @{ +*/ + +#define MAX_SCR (255) +#define MAX_CPSVDR (254) +#define MIN_DIVIDER (1) +#define MAX_DIVIDER (65024) // MAX_CPSVDR * (MAX_SCR+1) + +#define SPI_CLOCK (16000000) + +/** +* @} +*/ + +/** @defgroup SPI_Private_Macros Private Macros +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Variables Private Variables +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_FunctionPrototypes Private Function Prototypes +* @{ +*/ + +/** +* @} +*/ + +/** @defgroup SPI_Private_Functions Private Functions +* @{ +*/ + +/** +* @brief SPI set baud rate function. +* @param Baudrate: the SPI baud rate up to 8MHz for master mode +* and 1MHz for slave mode. +* @retval None +*/ +void SPI_SetBaudrate(uint32_t Baudrate) +{ + uint32_t c; + uint8_t scr = 1; + uint8_t cpsr = 2; + + /* Check the parameters */ + assert_param(IS_SPI_BAUDRATE(Baudrate)); + + /* bit rate is: 16MHz / (CPSDVR * (1+SCR)) + and CPSDVR must be an even number from 2-254. + We calculate (1/2 * CPSDVR) * (1+SCR) */ + c = SPI_CLOCK / (2 * Baudrate); + + /* if the bit rate is possible */ + if ((c >= MIN_DIVIDER) && (c <= MAX_DIVIDER)) { + /* adjust the ratio CPSDVR / (SCR+1) */ + while (c > MAX_SCR) { + cpsr <<= 1; + c >>= 1; + } + scr = c - 1; + } + /* set dividers */ + SPI1->CPSR = cpsr; + SPI1->CR0_b.SCR = scr; +} + +/** +* @} +*/ + +/** @defgroup SPI_Public_Functions Public Functions +* @{ +*/ + +/** +* @brief Deinitializes the SPI peripheral registers to their default +* reset values. +* @param None +* @retval None +*/ +void SPI_DeInit(void) +{ + SPI1->CR0 = 0x1C000000; + SPI1->CR1 = 0x00000000; + SPI1->CPSR = 0x00000000; + SPI1->IMSC = 0x00000000; + SPI1->ICR = 0x00000000; + SPI1->DMACR = 0x00000000; + SPI1->RXFRM = 0x00000000; + SPI1->CHN = 0x00000000; + SPI1->WDTXF = 0x00000000; +} + +/** +* @brief Initializes the SPI peripheral according to the specified +* parameters in the SPI_InitStruct. +* @param SPI_InitStruct: pointer to a @ref SPI_InitType structure that +* contains the configuration information for the specified SPI peripheral. +* @retval None +*/ +void SPI_Init(SPI_InitType* SPI_InitStruct) +{ + /* check the parameters */ + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + + /* Set the specified baud rate */ + SPI_SetBaudrate(SPI_InitStruct->SPI_BaudRate); + + /* Set SPI mode */ + SPI1->CR1_b.MS = SPI_InitStruct->SPI_Mode; + + /* Set CPOL */ + SPI1->CR0_b.SPO = SPI_InitStruct->SPI_CPOL; + + /* Set CPHA */ + SPI1->CR0_b.SPH = SPI_InitStruct->SPI_CPHA; + + /* Set datasize */ + SPI1->CR0_b.DSS = SPI_InitStruct->SPI_DataSize; +} + + +/** +* @brief Fills each SPI_InitStruct member with its default value. +* @param SPI_InitStruct: pointer to a @ref SPI_InitType structure which will be initialized. +* @retval None +*/ +void SPI_StructInit(SPI_InitType* SPI_InitStruct) +{ + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + + /* Initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + + /* Initialize the SPI_BaudRate member */ + SPI_InitStruct->SPI_BaudRate = 1000000; +} + +/** +* @brief Enables or disables the SPI peripheral. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SPI_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the selected SPI peripheral */ + SPI1->CR1_b.SSE = SET; + } + else { + /* Disable the selected SPI peripheral */ + SPI1->CR1_b.SSE = RESET; + } +} + +/** +* @brief Enables or disables the specified SPI interrupts. +* @param SPI_IT: specifies the SPI interrupt source to be enabled or disabled. +* This parameter can be any combination of the following values: +* @arg SPI_IT_TX: Transmit FIFO half empty or less condition interrupt mask. +* @arg SPI_IT_RX: Receive FIFO half full or less condition interrupt mask. +* @arg SPI_IT_RT: Receive FIFO not empty and no read prior to timeout period interrupt mask. +* @arg SPI_IT_ROR: Receive FIFO written to while full condition interrupt mask. +* @arg SPI_IT_TUR: Transmit underrun interrupt mask. +* @arg SPI_IT_TE: Transmit FIFO empty interrupt mask. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SPI_ITConfig(uint8_t SPI_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_CONFIG_IT(SPI_IT)); + + if (NewState != DISABLE) { + /* Enable the selected SPI interrupts */ + SET_BIT(SPI1->IMSC, SPI_IT); + } + else { + /* Disable the selected SPI interrupts */ + CLEAR_BIT(SPI1->IMSC, SPI_IT); + } +} + + +/** +* @brief Enables or disables the output if in slave mode. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SPI_SlaveModeOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the output */ + SPI1->CR1_b.SOD = RESET; + } + else { + /* Disable the output */ + SPI1->CR1_b.SOD = SET; + } +} + +/** +* @brief Transmits a Data through the SPI peripheral. +* @param Data: Data to be transmitted. +* @retval None +*/ +void SPI_SendData(uint32_t Data) +{ + /* Write in the DR register the data to be sent */ + SPI1->DR = Data; +} + +/** +* @brief Returns the most recent received data by the SPI peripheral. +* @param None +* @retval The value of the received data. +*/ +uint32_t SPI_ReceiveData(void) +{ + /* Return the data in the DR register */ + return SPI1->DR; +} + +/** +* @brief Configures the data size for the selected SPI. +* @param SPI_DataSize: specifies the SPI data size. +* This parameter can be one of the following values: +* @arg SPI_DataSize_32b: Set data frame format to 32bit +* ... +* @arg SPI_DataSize_5b: Set data frame format to 5bit +* @arg SPI_DataSize_4b: Set data frame format to 4bit +* @retval None +*/ +void SPI_DataSizeConfig(uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + + /* set the datasize */ + SPI1->CR0_b.DSS = SPI_DataSize; +} + +/** +* @brief Configures the command size for the selected SPI. +* @param SPI_DataSize: specifies the SPI command size. +* This parameter can be one of the following values: +* @arg SPI_DataSize_32b: Set data frame format to 32bit +* ... +* @arg SPI_DataSize_5b: Set data frame format to 5bit +* @arg SPI_DataSize_4b: Set data frame format to 4bit +* @retval None +*/ +void SPI_CommandSizeConfig(uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + + /* set the datasize */ + SPI1->CR0_b.CSS = SPI_DataSize; +} + +/** +* @brief Enable the wait state only for Microwire mode. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SPI_EnableWaitState(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the wait state */ + SPI1->CR1_b.MSPIWAIT = RESET; + } + else { + /* Disable the wait state */ + SPI1->CR1_b.MSPIWAIT = SET; + } +} + + +/** +* @brief Configures the frame format for the selected SPI. +* @param SPI_FrameFormat: specifies the SPI frame format. +* This parameter can be one of the following values: +* @arg SPI_FrmFrmt_Motorola: Set the Motorola SPI frame format +* @arg SPI_FrmFrmt_Microwire: Set the MicroWire frame format +* @retval None +*/ +void SPI_FrameFormatConfig(uint8_t SPI_FrameFormat) +{ + /* Check the parameters */ + assert_param(IS_SPI_FRMFRMT(SPI_FrameFormat)); + + /* set the datasize */ + SPI1->CR0_b.FRF = SPI_FrameFormat; +} + + +/** +* @brief Checks whether the specified SPI flag is set or not. +* @param SPI_FLAG: specifies the SPI flag to check. +* This parameter can be any combination of the following values: +* @arg SPI_IT_TX: Transmit FIFO half empty or less condition interrupt mask. +* @arg SPI_IT_RX: Receive FIFO half full or less condition interrupt mask. +* @arg SPI_IT_RT: Receive FIFO not empty and no read prior to timeout period interrupt mask. +* @arg SPI_IT_ROR: Receive FIFO written to while full condition interrupt mask. +* @arg SPI_IT_TUR: Transmit underrun interrupt mask. +* @arg SPI_IT_TE: Transmit FIFO empty interrupt mask. +* @retval FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. +*/ +FlagStatus SPI_GetFlagStatus(uint16_t SPI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_GET_FLAG(SPI_FLAG)); + + /* Check the status of the specified SPI flag */ + if (READ_BIT(SPI1->SR, SPI_FLAG) != (uint16_t)RESET) { + /* SPI_FLAG is set */ + return SET; + } + else { + /* SPI_FLAG is reset */ + return RESET; + } + +} + +/** +* @brief Checks whether the specified SPI interrupt has occurred or not. +* @param SPI_IT: specifies the SPI interrupt source to check. +* This parameter can be one of the following values: +* @arg SPI_IT_TX: Transmit FIFO half empty or less condition interrupt mask. +* @arg SPI_IT_RX: Receive FIFO half full or less condition interrupt mask. +* @arg SPI_IT_RT: Receive FIFO not empty and no read prior to timeout period interrupt mask. +* @arg SPI_IT_ROR: Receive FIFO written to while full condition interrupt mask. +* @arg SPI_IT_TUR: Transmit underrun interrupt mask. +* @arg SPI_IT_TE: Transmit FIFO empty interrupt mask. +* @retval ITStatus: functional state @ref ITStatus +* This parameter can be: SET or RESET. +*/ +ITStatus SPI_GetITStatus(uint8_t SPI_IT) +{ + /* Check the parameters */ + assert_param(IS_SPI_GET_IT(SPI_IT)); + + /* Check the status of the specified SPI interrupt */ + if (READ_BIT(SPI1->RIS, SPI_IT) != (uint16_t)RESET) { + /* SPI_IT is set */ + return SET; + } + else { + /* SPI_IT is reset */ + return RESET; + } + +} + +/** +* @brief Clears the SPI interrupt pending bits. +* @param SPI_IT: specifies the SPI interrupt pending bit to clear. +* This parameter can be one of the following values: +* @arg SPI_IT_TX: Transmit FIFO half empty or less condition interrupt mask. +* @arg SPI_IT_RX: Receive FIFO half full or less condition interrupt mask. +* @arg SPI_IT_RT: Receive FIFO not empty and no read prior to timeout period interrupt mask. +* @arg SPI_IT_ROR: Receive FIFO written to while full condition interrupt mask. +* @arg SPI_IT_TUR: Transmit underrun interrupt mask. +* @arg SPI_IT_TE: Transmit FIFO empty interrupt mask. +* @retval None +*/ +void SPI_ClearITPendingBit(uint8_t SPI_IT) +{ + /* Check the parameters */ + assert_param(IS_SPI_CLEAR_IT(SPI_IT)); + + /* Clear the selected SPI interrupt pending bit */ + CLEAR_BIT(SPI1->ICR, SPI_IT); +} + +/** +* @brief Clear all data present within the RX FIFO of the SPI peripherial. +* SPI peripherial clocks have to be enabled first before the use. +* @param None +* @retval None +*/ +void SPI_ClearRXFIFO(void) +{ + /* Flush the data from SPI RX FIFO */ + while(SET == SPI_GetFlagStatus(SPI_FLAG_RNE) ) { + SPI_ReceiveData(); + } +} + +/** +* @brief Clear all data present within the TX FIFO of the SPI peripherial. +* SPI peripherial clocks have to be enabled first before the use. +* @param None +* @retval None +*/ +void SPI_ClearTXFIFO(void) +{ + uint32_t tmp; + + /* Enable read from the TX FIFO */ + SPI1->ITCR_b.SWAPFIFO = SET; + + /* Flush the data from the TX FIFO till it is not empty. */ + while(0 == SPI1->SR_b.TFE) { + tmp |= SPI1->TDR; + } + + /* Disable the read from the TX FIFO */ + SPI1->ITCR_b.SWAPFIFO = RESET; + +} + +/** +* @brief Set the SPI communication mode. +* @param Mode: specifies the SPI communication mode. +* This parameter can be one of the following values: +* @arg SPI_FULL_DUPLEX_MODE: SPI full duplex communication mode. +* @arg SPI_TRANSMIT_MODE: SPI transmit communication mode. +* @arg SPI_RECEIVE_MODE: SPI receive communication mode. +* @arg SPI_COMBINED_MODE: SPI combined communication mode. +* @retval None +*/ +void SPI_SetMasterCommunicationMode(uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_SPI_COM_MODE(Mode)); + + /* Set the communication mode */ + SPI1->CR0_b.SPIM = Mode; +} + +/** +* @brief Set the dummy character used for the SPI master communication. +* @param NullCharacter: Dummy character to be used. +* @retval None +*/ +void SPI_SetDummyCharacter(uint32_t NullCharacter) +{ + /* Set the dummy character */ + SPI1->CHN = NullCharacter; +} + +/** +* @brief Set the number of frames to receive from slave. +* @param Number: Number of frames to receive. +* @retval None +*/ +void SPI_SetNumFramesToReceive(uint16_t Number) +{ + /* Set the number of frames to receive */ + SPI1->RXFRM = Number; +} + +/** +* @brief Set the number of frames to transmit to slave +* @param Number: Number of frames to transmit. +* @retval None +*/ +void SPI_SetNumFramesToTransmit(uint16_t Number) +{ + /* Set the number of frames to transmit */ + SPI1->WDTXF = Number; +} + + +/** +* @brief Master can select the slave by driving the CS pin by software. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SPI_SlaveSwSelection(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the output */ + SPI1->CR0_b.CS1 = RESET; + } + else { + /* Disable the output */ + SPI1->CR0_b.CS1 = SET; + } +} + +/** +* @brief Master can select the slave by driving the CS pin by software. +* @param Endian: the endian format @ref SPI_Endian_Format_Definition +* @retval None +*/ +void SPI_EndianFormatReception(uint8_t Endian) +{ + /* Check the parameters */ + assert_param(IS_SPI_ENDIAN(Endian)); + + SPI1->CR1_b.RENDN = Endian; +} + +/** +* @brief Master can select the slave by driving the CS pin by software. +* @param Endian: the endian format @ref SPI_Endian_Format_Definition +* @retval None +*/ +void SPI_EndianFormatTransmission(uint8_t Endian) +{ + /* Check the parameters */ + assert_param(IS_SPI_ENDIAN(Endian)); + + SPI1->CR1_b.TENDN = Endian; +} + + +/** +* @brief Configure the delay between the frames. +* The MSPIWAIT value is used to insert a wait state between frames. +* The SSPFRM pulse duration is given by the equation: +* SSPCLKOUT x {MSPIWAIT - (SCR-1) / [2x(SCR+1)]}. +* When SCR=1, MSPIWAIT indicates the number of SSPCLKO cycle that +* the SSPFRM pulse duration should have between frames. +* @param Delay: this value must be less than or equal to 15. +* 0 means no delay (default). +* @retval None +*/ +void SPI_DelayBetweenFrames(uint8_t Delay) +{ + /* Check the parameters */ + assert_param(IS_SPI_ENDIAN(Delay)); + + SPI1->CR1_b.MSPIWAIT = Delay; +} + + +/** +* @brief Master insert a delay of two clock cycle if enabled. +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SPI_DelayDataInput(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the output */ + SPI1->CR1_b.DATAINDEL = RESET; + } + else { + /* Disable the output */ + SPI1->CR1_b.DATAINDEL = SET; + } +} + + +/** + * @brief Sets the SPI interrupt FIFO level. + * @param SPI_TX_FIFO_LEV: specifies the transmit interrupt FIFO level. + * This parameter can be one of the following values: + * @arg FIFO_TX_LEV_1: interrupt when TX FIFO contains 1 element or more + * @arg FIFO_TX_LEV_4: interrupt when TX FIFO contains 4 elements or more + * @arg FIFO_TX_LEV_8: interrupt when TX FIFO contains 8 elements or more + * @retval None + */ +void SPI_TxFifoInterruptLevelConfig(uint8_t SPI_TX_FIFO_LEV) +{ + /* Check the parameters */ + assert_param(IS_SPI_FIFO_LEV(SPI_TX_FIFO_LEV)); + + SPI1->CR1_b.TXIFLSEL = SPI_TX_FIFO_LEV; +} + +/** + * @brief Sets the SPI interrupt FIFO level. + * @param SPI_RX_FIFO_LEV: specifies the receive interrupt FIFO level. + * This parameter can be one of the following values: + * @arg FIFO_RX_LEV_1: interrupt when RX FIFO contains 1 element or more + * @arg FIFO_RX_LEV_4: interrupt when RX FIFO contains 4 elements or more + * @arg FIFO_RX_LEV_8: interrupt when RX FIFO contains 8 elements or more + * + * @retval None + */ +void SPI_RxFifoInterruptLevelConfig(uint8_t SPI_RX_FIFO_LEV) +{ + /* Check the parameters */ + assert_param(IS_SPI_FIFO_LEV(SPI_RX_FIFO_LEV)); + + SPI1->CR1_b.RXIFLSEL = SPI_RX_FIFO_LEV; +} + +/** + * @brief Enables or disables the SPI DMA interface. + * @param SPI_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg SPI_DMAReq_Tx: SPI DMA transmit request + * @arg SPI_DMAReq_Rx: SPI DMA receive request. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_DMACmd(uint8_t SPI_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_DMAREQ(SPI_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transfer */ + SPI1->DMACR |= SPI_DMAReq; + } + else + { + /* Disable the DMA transfer */ + SPI1->DMACR &= (uint8_t)~SPI_DMAReq; + } +} + +#pragma message("SPI1 modificato") +/** +* @} +*/ + +/** +* @} +*/ + +/** +* @} +*/ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_sysCtrl.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_sysCtrl.c new file mode 100644 index 00000000000..af8437eb403 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_sysCtrl.c @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_sysCtrl.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @defgroup SysCtrl System Controller Driver + * @{ + */ + +/** @defgroup SysCtrl_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup SysCtrl_Private_Defines Private Defines + * @{ + */ + + +#define SOC_REASON_SYSREQ (0x00000002) +#define SOC_REASON_WDG (0x00000004) +#define SOC_REASON_LOCKUP (0x00000008) + +#define BLE_REASON_WAKEUP_RST (0x00000001) +#define BLE_REASON_BOR_RST (0x00000002 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_POR_RST (0x00000004 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_IO9 (0x00000008 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_IO10 (0x00000010 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_IO11 (0x00000020 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_IO12 (0x00000040 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_IO13 (0x00000080 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_TIMER1 (0x00000100 | BLE_REASON_WAKEUP_RST) +#define BLE_REASON_FROM_TIMER2 (0x00000400 | BLE_REASON_WAKEUP_RST) + + +/** + * @} + */ + +/** @defgroup SysCtrl_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SysCtrl_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SysCtrl_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SysCtrl_Public_Functions Public Functions + * @{ + */ + + +/** + * @brief De init function + * @param None + * @retval None + */ +void SysCtrl_DeInit(void) +{ + SYSTEM_CTRL->WKP_IO_IS = 0x00; + SYSTEM_CTRL->WKP_IO_IE = 0x03; + CKGEN_SOC->CLOCK_EN = 0x0003FFFF; + CKGEN_BLE->CLK32K_COUNT = 0x0000000F; + CKGEN_BLE->CLK32K_IT = 0x00000000; +} + + +/** + * @brief Enables the clock for the specified peripheral. + * @param PeriphClock: Peripheral to be enabled, this value can be + * @arg CLOCK_PERIPH_GPIO Clock of GPIO peripheral + * @arg CLOCK_PERIPH_NVM Clock of NVM peripheral + * @arg CLOCK_PERIPH_SYS_CONTROL Clock of SYSTEM CONTROL peripheral + * @arg CLOCK_PERIPH_UART Clock of UART peripheral + * @arg CLOCK_PERIPH_SPI Clock of SPI peripheral + * @arg CLOCK_PERIPH_WDG Clock of WATCHDOG peripheral + * @arg CLOCK_PERIPH_ADC Clock of ADC peripheral + * @arg CLOCK_PERIPH_I2C1 Clock of I2C1 peripheral + * @arg CLOCK_PERIPH_I2C2 Clock of I2C2 peripheral + * @arg CLOCK_PERIPH_MTFX1 Clock of MFTX1 peripheral + * @arg CLOCK_PERIPH_MTFX2 Clock of MFTX2 peripheral + * @arg CLOCK_PERIPH_RTC Clock of RTC peripheral + * @arg CLOCK_PERIPH_DMA Clock of DMA peripheral + * @arg CLOCK_PERIPH_RNG Clock of RNG peripheral + * @arg CLOCK_PERIPH_PKA Clock of PKA peripheral + * @param NewState: New state of the peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SysCtrl_PeripheralClockCmd(uint32_t PeriphClock, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CLOCK_PERIPH(PeriphClock)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) { + SET_BIT(CKGEN_SOC->CLOCK_EN, PeriphClock); + } + else { + CLEAR_BIT(CKGEN_SOC->CLOCK_EN, PeriphClock); + } +} + +/** + * @brief Get the wakeup reason. + * @param None + * @retval RESET_REASON_Type: wakeup reason @ref RESET_REASON_Type + */ +RESET_REASON_Type SysCtrl_GetWakeupResetReason(void) +{ + uint32_t tmpSoc, tmpBle; + + tmpSoc = CKGEN_SOC->REASON_RST; + tmpBle = CKGEN_BLE->REASON_RST; + + if ((tmpSoc == 0) && + (tmpBle >= BLE_REASON_FROM_IO9) && + (tmpBle <= BLE_REASON_FROM_IO13)) { + if ((tmpBle & BLE_REASON_FROM_IO9) == BLE_REASON_FROM_IO9) { + return RESET_BLE_WAKEUP_FROM_IO9; + } + if ((tmpBle & BLE_REASON_FROM_IO10) == BLE_REASON_FROM_IO10) { + return RESET_BLE_WAKEUP_FROM_IO10; + } + if ((tmpBle & BLE_REASON_FROM_IO11) == BLE_REASON_FROM_IO11) { + return RESET_BLE_WAKEUP_FROM_IO11; + } + if ((tmpBle & BLE_REASON_FROM_IO12) == BLE_REASON_FROM_IO12) { + return RESET_BLE_WAKEUP_FROM_IO12; + } + if ((tmpBle & BLE_REASON_FROM_IO13) == BLE_REASON_FROM_IO13) { + return RESET_BLE_WAKEUP_FROM_IO13; + } + } + + if ((tmpSoc == 0) && + ((tmpBle & BLE_REASON_FROM_TIMER1) == BLE_REASON_FROM_TIMER1)) { + return RESET_BLE_WAKEUP_FROM_TIMER1; + } + if ((tmpSoc == 0) && + ((tmpBle & BLE_REASON_FROM_TIMER2) == BLE_REASON_FROM_TIMER2)) { + return RESET_BLE_WAKEUP_FROM_TIMER2; + } + if ((tmpSoc == 0) && + ((tmpBle & BLE_REASON_POR_RST) == BLE_REASON_POR_RST)) { + return RESET_BLE_POR; + } + if ((tmpSoc == 0) && + ((tmpBle & BLE_REASON_BOR_RST) == BLE_REASON_BOR_RST)) { + return RESET_BLE_BOR; + } + if (tmpSoc == SOC_REASON_SYSREQ) { + return RESET_SYSREQ; + } + if (tmpSoc == SOC_REASON_WDG) { + return RESET_WDG; + } + if((tmpSoc == SOC_REASON_LOCKUP)) { + return RESET_LOCKUP; + } + + return RESET_NONE; +} + + +/** +* @brief Configure the wakeup source from IO. +* @param IO: the IO selected as wakeup source, the value can be +* @arg WAKEUP_ON_IO9 Wakeup source is IO9 +* @arg WAKEUP_ON_IO10 Wakeup source is IO10 +* @arg WAKEUP_ON_IO11 Wakeup source is IO11 +* @arg WAKEUP_ON_IO12 Wakeup source is IO12 +* @arg WAKEUP_ON_IO13 Wakeup source is IO13 +* @param LevelState: select the level of the wakeup source, the value can be +* @arg WAKEUP_ON_HIGH_STATE Wakeup on high state +* @arg WAKEUP_ON_LOW_STATE Wakeup on low state +* @param NewState: functional state @ref FunctionalState +* This parameter can be: ENABLE or DISABLE. +* @retval None +*/ +void SysCtrl_WakeupFromIo(uint8_t IO, uint8_t LevelState, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_WAKEUP_ON_IO(IO)); + assert_param(IS_WAKEUP_ON_STATE(LevelState)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(LevelState == WAKEUP_ON_HIGH_STATE) { + SET_BIT(SYSTEM_CTRL->WKP_IO_IS, IO); + } + else { + CLEAR_BIT(SYSTEM_CTRL->WKP_IO_IS, IO); + } + + if(NewState == ENABLE) { + SET_BIT(SYSTEM_CTRL->WKP_IO_IE, IO); + } + else { + CLEAR_BIT(SYSTEM_CTRL->WKP_IO_IE, IO); + } + +} + +/** + * @brief Enable disable the XO clock divider for the system control. + * @param XOFreq: configure the system for the correct XO external clock used, the value can be +* @arg XO_32MHz enable the XO divider and expect a 32 MHz external clock. +* @arg XO_16MHz disable the XO divider and expect a 16 MHz external clock. + * @retval None + */ +void SysCtrl_SelectXO(uint8_t XOFreq) +{ + /* Check the parameters */ + assert_param(IS_XO_FREQ(XOFreq)); + + if(XOFreq == XO_32MHZ) { + SYSTEM_CTRL->CTRL_b.MHZ32_SEL = SET; + } + else if(XOFreq == XO_16MHZ) { + SYSTEM_CTRL->CTRL_b.MHZ32_SEL = RESET; + } +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_uart.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_uart.c new file mode 100644 index 00000000000..eb57d84adf8 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_uart.c @@ -0,0 +1,733 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_uart.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup UART_Peripheral UART Peripheral + * @{ + */ + +/** @defgroup UART_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Defines Private Defines + * @{ + */ +#define UART_CLOCK (16000000) + +/* UART clock cycle for oversampling factor */ +#define UART_CLOCK_CYCLE16 (16) +#define UART_CLOCK_CYCLE8 (8) + +/* Max UART RX timeout value */ +#define UART_MAX_RX_TIMEOUT (0x3FFFFF) + +/** + * @} + */ + +/** @defgroup UART_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup UART_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup UART_Public_Functions Public Functions + * @{ + */ + + +/** + * @brief Enables or disables the UART peripheral. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the selected UART by setting the UARTEN bit in the UARTCR register */ + UART->CR_b.EN = SET; + } + else { + /* Disable the selected UART by clearing the UARTEN bit in the UARTCR register */ + UART->CR_b.EN = RESET; + } +} + + +uint8_t UART_IsEnabled(void){ + return (uint8_t)UART->CR_b.EN; +} + + + +/** +* @brief Deinitializes the UART peripheral registers to their default +* reset values. +* @param None +* @retval None +*/ +void UART_DeInit(void) +{ + UART->TIMEOUT = 0x000001FF; + UART->LCRH_RX = 0x00000000; + UART->IBRD = 0x00000000; + UART->FBRD = 0x00000000; + UART->LCRH_TX = 0x00000000; + UART->CR = 0x00040300; + UART->IFLS = 0x00000012; + UART->IMSC = 0x00000000; + UART->ICR = 0x00000000; + UART->DMACR = 0x00000000; + UART->XFCR = 0x00000000; + UART->XON1 = 0x00000000; + UART->XON2 = 0x00000000; + UART->XOFF1 = 0x00000000; + UART->XOFF2 = 0x00000000; +} + + +/** + * @brief Initializes the UART peripheral according to the specified + * parameters in the UART_InitStruct. + * @param UART_InitStruct: pointer to a @ref UART_InitType structure + * that contains the configuration information for the specified UART. + * @retval None + */ +void UART_Init(UART_InitType* UART_InitStruct) +{ + uint32_t divider; + uint16_t ibrd, fbrd; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate)); + assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLengthTransmit)); + assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLengthReceive)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + assert_param(IS_UART_HW_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl)); + assert_param(IS_FUNCTIONAL_STATE(UART_InitStruct->UART_FifoEnable)); + + /*---------------------------- UART BaudRate Configuration -----------------------*/ + + if (UART->CR_b.OVSFACT == 0) + divider = (UART_CLOCK<<7) / (UART_CLOCK_CYCLE16 * UART_InitStruct->UART_BaudRate); + else + divider = (UART_CLOCK<<7) / (UART_CLOCK_CYCLE8 * UART_InitStruct->UART_BaudRate); + + ibrd = divider >> 7; + UART->IBRD = ibrd; + fbrd = ((divider - (ibrd <<7) + 1) >> 1); + if (fbrd > 0x3f) { + ibrd++; + fbrd = (fbrd - 0x3F) & 0x3F; + } + UART->FBRD = fbrd; + + /*---------------------------- UART Word Length Configuration -----------------------*/ + UART->LCRH_TX_b.WLEN_TX = UART_InitStruct->UART_WordLengthTransmit; + UART->LCRH_RX_b.WLEN_RX = UART_InitStruct->UART_WordLengthReceive; + + /*---------------------------- UART Stop Bits Configuration -----------------------*/ + UART->LCRH_TX_b.STP2_TX = UART_InitStruct->UART_StopBits; + UART->LCRH_RX_b.STP2_RX = UART_InitStruct->UART_StopBits; + + /*---------------------------- UART Parity Configuration -----------------------*/ + if(UART_InitStruct->UART_Parity == UART_Parity_No) { + UART->LCRH_TX_b.PEN_TX = RESET; + UART->LCRH_RX_b.PEN_RX = RESET; + } + else if(UART_InitStruct->UART_Parity == UART_Parity_Odd) { + UART->LCRH_TX_b.PEN_TX = SET; + UART->LCRH_TX_b.EPS_TX = RESET; + UART->LCRH_RX_b.PEN_RX = SET; + UART->LCRH_RX_b.EPS_RX = RESET; + } + else { + UART->LCRH_TX_b.PEN_TX = SET; + UART->LCRH_TX_b.EPS_TX = SET; + UART->LCRH_RX_b.PEN_RX = SET; + UART->LCRH_RX_b.EPS_RX = SET; + } + + /*---------------------------- UART Mode Configuration -----------------------*/ + UART->CR_b.RXE = UART_InitStruct->UART_Mode&1; + UART->CR_b.TXE = (UART_InitStruct->UART_Mode>>1)&1; + + /*---------------------------- UART Hardware flow control Configuration -----------------------*/ + UART->CR_b.RTSEN = UART_InitStruct->UART_HardwareFlowControl&1; + UART->CR_b.CTSEN = (UART_InitStruct->UART_HardwareFlowControl>>1)&1; + + /*---------------------------- UART Fifo Configuration -----------------------*/ + UART->LCRH_TX_b.FEN_TX = (uint8_t)UART_InitStruct->UART_FifoEnable; + UART->LCRH_RX_b.FEN_RX = (uint8_t)UART_InitStruct->UART_FifoEnable; + +} + +/** + * @brief Fills each UART_InitStruct member with its default value. + * @param UART_InitStruct: pointer to a @ref UART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitType* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 115200; + UART_InitStruct->UART_WordLengthTransmit = UART_WordLength_8b; + UART_InitStruct->UART_WordLengthReceive = UART_WordLength_8b; + UART_InitStruct->UART_StopBits = UART_StopBits_1; + UART_InitStruct->UART_Parity = UART_Parity_No; + UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx; + UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None; + UART_InitStruct->UART_FifoEnable = DISABLE; +} + +/** + * @brief Enables or disables the specified UART interrupts. + * @param UART_IT: specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be a any combination of the following values: + * @arg UART_IT_TXFE: Tx FIFO empty interrupt + * @arg UART_IT_XO: XOFF interrupt + * @arg UART_IT_OE: Overrun error interrupt + * @arg UART_IT_BE: Break error interrupt + * @arg UART_IT_PE: Parity error interrupt + * @arg UART_IT_FE: Framing error interrupt + * @arg UART_IT_RT: Receive timeout interrupt + * @arg UART_IT_TX: Transmit interrupt + * @arg UART_IT_RX: Receive interrupt + * @arg UART_IT_CTS: CTS interrupt. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_ITConfig(uint16_t UART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_CONFIG_IT(UART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable specified interrupts */ + SET_BIT(UART->IMSC, UART_IT); + } + else { + /* Disable specified interrupts */ + CLEAR_BIT(UART->IMSC, UART_IT); + } +} + +/** + * @brief Transmits single data through the UART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void UART_SendData(uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_UART_DATA(Data)); + + /* Transmit Data */ + UART->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the UART peripheral. + * @param None + * @retval uint16_t: The received data. + */ +uint16_t UART_ReceiveData(void) +{ + /* Check the parameters */ + + /* Receive Data */ + return (uint16_t)(UART->DR & 0x00FF); +} + +/** + * @brief Enables or disables the break command. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_BreakCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + UART->LCRH_TX_b.BRK = (uint8_t)NewState; +} + +/** + * @brief Enables or disables the request to send command. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_RequestToSendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + UART->CR_b.RTS = (uint8_t)NewState; +} + + +/** + * @brief Checks whether the specified UART flag is set or not. + * @param UART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_CTS: Clear to send + * @arg UART_FLAG_BUSY: UART busy + * @arg UART_FLAG_RXFE: Receive FIFO empty + * @arg UART_FLAG_TXFF: Transmit FIFO full + * @arg UART_FLAG_RXFF: Receive FIFO full + * @arg UART_FLAG_TXFE: Transmit FIFO empty + * @arg UART_FLAG_FE: Framing error + * @arg UART_FLAG_PE: Parity error + * @arg UART_FLAG_BE: Break error + * @arg UART_FLAG_OE: Overrun error. +* @retval FlagStatus: functional state @ref FlagStatus +* This parameter can be: SET or RESET. + */ +FlagStatus UART_GetFlagStatus(uint32_t UART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_UART_FLAG(UART_FLAG)); + + if (UART_FLAG & 0x80000000) { + if (UART->RSR & UART_FLAG) { + return SET; + } + else { + return RESET; + } + } + else { + if (UART->FR & UART_FLAG) { + return SET; + } + else { + return RESET; + } + } + +} + +/** + * @brief Clears the UART pending flags. + * @param UART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg UART_FLAG_FE: Framing error + * @arg UART_FLAG_PE: Parity error + * @arg UART_FLAG_BE: Break error + * @arg UART_FLAG_OE: Overrun error + * @retval None + */ +void UART_ClearFlag(uint32_t UART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_UART_CLEAR_FLAG(UART_FLAG)); + + UART->ECR = UART_FLAG; +} + +/** + * @brief Checks whether the specified UART interrupt has occurred or not. + * @param UART_IT: specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_IT_TXFE: Tx FIFO empty interrupt + * @arg UART_IT_XO: XOFF interrupt + * @arg UART_IT_OE: Overrun error interrupt + * @arg UART_IT_BE: Break error interrupt + * @arg UART_IT_PE: Parity error interrupt + * @arg UART_IT_FE: Framing error interrupt + * @arg UART_IT_RT: Receive timeout interrupt + * @arg UART_IT_TX: Transmit interrupt + * @arg UART_IT_RX: Receive interrupt + * @arg UART_IT_CTS: CTS interrupt + * @retval ITStatus: functional state @ref ITStatus + * This parameter can be: SET or RESET. + */ +ITStatus UART_GetITStatus(uint16_t UART_IT) +{ + /* Check the parameters */ + assert_param(IS_UART_CONFIG_IT(UART_IT)); + + if ((UART->RIS & UART_IT) != (uint16_t)RESET) { + return SET; + } + else { + return RESET; + } +} + +/** + * @brief Clears the UART interrupt pending bits. + * @param UART_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg UART_IT_TXFE: Tx FIFO empty interrupt + * @arg UART_IT_XO: XOFF interrupt + * @arg UART_IT_OE: Overrun error interrupt + * @arg UART_IT_BE: Break error interrupt + * @arg UART_IT_PE: Parity error interrupt + * @arg UART_IT_FE: Framing error interrupt + * @arg UART_IT_RT: Receive timeout interrupt + * @arg UART_IT_TX: Transmit interrupt + * @arg UART_IT_RX: Receive interrupt + * @arg UART_IT_CTS: CTS interrupt + * + * @retval None + */ +void UART_ClearITPendingBit(uint16_t UART_IT) +{ + /* Check the parameters */ + assert_param(IS_UART_CONFIG_IT(UART_IT)); + + UART->ICR = UART_IT; +} + + +/** + * @brief Sets the UART interrupt FIFO level. + * @param UART_TxFifo_Level: specifies the transmit interrupt FIFO level. + * This parameter can be one of the following values: + * @arg FIFO_LEV_1_64: interrupt when Tx FIFO becomes <= 1/64 full = 1 + * @arg FIFO_LEV_1_32: interrupt when Tx FIFO becomes <= 1/32 full = 2 + * @arg FIFO_LEV_1_16: interrupt when Tx FIFO becomes <= 1/16 full = 4 + * @arg FIFO_LEV_1_8: interrupt when Tx FIFO becomes <= 1/8 full = 8 + * @arg FIFO_LEV_1_4: interrupt when Tx FIFO becomes <= 1/4 full = 16 + * @arg FIFO_LEV_1_2: interrupt when Tx FIFO becomes <= 1/2 full = 32 + * @arg FIFO_LEV_3_4: interrupt when Tx FIFO becomes <= 3/4 full = 48 + * @retval None + */ +void UART_TxFifoIrqLevelConfig(uint8_t UART_TxFifo_Level) +{ + /* Check the parameters */ + assert_param(IS_FIFO_LEV(UART_TxFifo_Level)); + + UART->IFLS_b.TXIFLSEL = UART_TxFifo_Level; +} + +/** + * @brief Sets the UART interrupt FIFO level. + * @param UART_RxFifo_Level: specifies the receive interrupt FIFO level. + * This parameter can be one of the following values: + * @arg FIFO_LEV_1_64: interrupt when Rx FIFO becomes >= 1/64 full = 1 + * @arg FIFO_LEV_1_32: interrupt when Rx FIFO becomes >= 1/32 full = 2 + * @arg FIFO_LEV_1_16: interrupt when Rx FIFO becomes >= 1/16 full = 4 + * @arg FIFO_LEV_1_8: interrupt when Rx FIFO becomes >= 1/8 full = 8 + * @arg FIFO_LEV_1_4: interrupt when Rx FIFO becomes >= 1/4 full = 16 + * @arg FIFO_LEV_1_2: interrupt when Rx FIFO becomes >= 1/2 full = 32 + * @arg FIFO_LEV_3_4: interrupt when Rx FIFO becomes >= 3/4 full = 48 + * @retval None + */ +void UART_RxFifoIrqLevelConfig(uint8_t UART_RxFifo_Level) +{ + /* Check the parameters */ + assert_param(IS_FIFO_LEV(UART_RxFifo_Level)); + + UART->IFLS_b.RXIFLSEL = UART_RxFifo_Level; +} + +/** + * @brief UART RX timeout. + * The RX timeout interrupt is asserted when + * the RX FIFO is not empty and no further data is received + * over a programmed timeout period. + * @param UART_TimeoutMS: is the timeout in milliseconds. + * @retval None + */ +void UART_RXTimeoutConfig(uint32_t UART_TimeoutMS) +{ + uint32_t timeout_val; + uint32_t tmp32; + + tmp32 = (UART->IBRD)<<4; + if (UART->CR_b.OVSFACT == 0) + timeout_val = (UART_TimeoutMS * 16 * 16000) / (((UART->FBRD)>>2) + tmp32); + else + timeout_val = (UART_TimeoutMS * 8 * 16000) / (((UART->FBRD)>>3) + tmp32); + + /* Set the timeout value */ + if(IS_UART_TIMEOUT(timeout_val)) { + UART->TIMEOUT = timeout_val; + } + else { + UART->TIMEOUT = UART_MAX_RX_TIMEOUT; + } +} + +/** + * @brief Enables or disables the UART oversampling. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_Oversampling(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + /* Enable the UART oversampling factor */ + UART->CR_b.OVSFACT = 1; + } + else + { + /* Disable the UART oversampling factor */ + UART->CR_b.OVSFACT = 0; + } +} + +/** + * @brief Enables or disables the UART DMA interface. + * @param UART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg UART_DMAReq_Tx: UART DMA transmit request. + * @arg UART_DMAReq_Rx: UART DMA receive request. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_DMACmd(uint8_t UART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_DMAREQ(UART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState == ENABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the UART CR3 register */ + UART->DMACR |= UART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the UART CR3 register */ + UART->DMACR &= (uint8_t)~UART_DMAReq; + } +} + + + +/** + * @brief Enables or disables the UART software flow control. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_SwFlowControl(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable UART software flow control */ + UART->XFCR_b.SFEN = SET; + } + else { + /* Disable UART software flow control */ + UART->XFCR_b.SFEN = RESET; + } +} + + +/** + * @brief Sets the UART flow control mode for reception. + * @param UART_RxSwFlowCtrlMode: specifies the software flow control used for RX. + * This parameter can be one of the following values: + * @arg NO_SW_FLOW_CTRL: No software flow control + * @arg SW_FLOW_CTRL_XON1_XOFF1: Software flow control XON1 and XOFF1 + * @arg SW_FLOW_CTRL_XON2_XOFF2: Software flow control XON2 and XOFF2 + * @arg SW_FLOW_CTRL_ALL_CHARS: Software flow control XON1 and XOFF1, XON2 and XOFF2 + * @retval None + */ +void UART_RxSwFlowControlMode(uint8_t UART_RxSwFlowCtrlMode) +{ + /* Check the parameters */ + assert_param(IS_SW_FLOW_CTRL(UART_RxSwFlowCtrlMode)); + + UART->XFCR_b.SFRMOD = UART_RxSwFlowCtrlMode; +} + +/** + * @brief Sets the UART flow control mode for transmission. + * @param UART_TxSwFlowCtrlMode: specifies the software flow control used for TX. + * This parameter can be one of the following values: + * @arg NO_SW_FLOW_CTRL: No software flow control + * @arg SW_FLOW_CTRL_XON1_XOFF1: Software flow control XON1 and XOFF1 + * @arg SW_FLOW_CTRL_XON2_XOFF2: Software flow control XON2 and XOFF2 + * @arg SW_FLOW_CTRL_ALL_CHARS: Software flow control XON1 and XOFF1, XON2 and XOFF2 + * @retval None + */ +void UART_TxSwFlowControlMode(uint8_t UART_TxSwFlowCtrlMode) +{ + /* Check the parameters */ + assert_param(IS_SW_FLOW_CTRL(UART_TxSwFlowCtrlMode)); + + UART->XFCR_b.SFTMOD = UART_TxSwFlowCtrlMode; +} + + +/** + * @brief Enables or disables the UART XON any bit. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_XonAnyBit(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the UART XON any bit */ + UART->XFCR_b.XONANY = SET; + } + else { + /* Disable the UART XON any bit */ + UART->XFCR_b.XONANY = RESET; + } +} + + +/** + * @brief Enables or disables the UART special character detection. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_SpecialCharDetect(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /* Enable the UART special character detection */ + UART->XFCR_b.SPECHAR = SET; + } + else { + /* Disable the UART special character detection */ + UART->XFCR_b.SPECHAR = RESET; + } +} + + +/** + * @brief Sets the UART flow control mode for transmission. + * @param uint8_t: specifies the flow control character. + * @retval None + */ +void UART_Xon1Char(uint8_t UART_XonChar) +{ + /* Check the parameters */ + assert_param(IS_SW_FLOW_CTRL(UART_XonChar)); + + UART->XON1 = UART_XonChar; +} + +/** + * @brief Sets the UART flow control mode for transmission. + * @param uint8_t: specifies the flow control character. + * @retval None + */ +void UART_Xon2Char(uint8_t UART_XonChar) +{ + /* Check the parameters */ + assert_param(IS_SW_FLOW_CTRL(UART_XonChar)); + + UART->XON2 = UART_XonChar; +} + +/** + * @brief Sets the UART flow control mode for transmission. + * @param uint8_t: specifies the flow control character. + * @retval None + */ +void UART_Xoff1Char(uint8_t UART_XoffChar) +{ + /* Check the parameters */ + assert_param(IS_SW_FLOW_CTRL(UART_XoffChar)); + + UART->XOFF1 = UART_XoffChar; +} + +/** + * @brief Sets the UART flow control mode for transmission. + * @param uint8_t: specifies the flow control character. + * @retval None + */ +void UART_Xoff2Char(uint8_t UART_XoffChar) +{ + /* Check the parameters */ + assert_param(IS_SW_FLOW_CTRL(UART_XoffChar)); + + UART->XOFF2 = UART_XoffChar; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_wdg.c b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_wdg.c new file mode 100644 index 00000000000..15bf866c900 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/BlueNRG1_wdg.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/BlueNRG1_wdg.h" + + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @defgroup WDG_Peripheral WDG Peripheral + * @{ + */ + +/** @defgroup WDG_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Private_Defines Private Defines + * @{ + */ + +#define WDG_WRITE_ACCESS_UNLOCK ((uint32_t)0x1ACCE551) /*!< Enables WDG write access */ +#define WDG_WRITE_ACCESS_LOCK ((uint32_t)0x00000000) /*!< Disables WDG write access */ + +/** + * @} + */ + +/** @defgroup WDG_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Private_Functions Private Functions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WDG_Public_Functions Public Functions +* @{ +*/ + +/** + * @brief Enables or disables write access to all the other WDG registers. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void WDG_SetWriteAccess(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + WDG->LOCK = WDG_WRITE_ACCESS_UNLOCK; + } + else { + WDG->LOCK = WDG_WRITE_ACCESS_LOCK; + } +} + + +/** + * @brief Get the write access state. + * @param None + * @retval NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + */ +FunctionalState WDG_GetWriteAccess(void) +{ + return (FunctionalState)!WDG->LOCK; + +} + +/** + * @brief Sets WDG reload value. + * @param WDG_Reload: specifies the WDG reload value. + * This parameter must be a number greater than 0. + * @retval None + */ +void WDG_SetReload(uint32_t WDG_Reload) +{ + /* Check the parameters */ + assert_param(WDG_Reload > 0); + WDG->LR = WDG_Reload; +} + +/** + * @brief Enables WDG reset. + * @param None + * @retval None + */ +void WDG_Enable(void) +{ + WDG->CR_b.INTEN = SET; + WDG->CR_b.RESEN = SET; +} + +/** + * @brief Disable WDG reset. + * @param None + * @retval None + */ +void WDG_DisableReset(void) +{ + WDG->CR_b.RESEN = RESET; +} + + +/** + * @brief Gets the WDG counter value. + * @param None + * @retval WDG counter value. + */ +uint32_t WDG_GetCounter(void) +{ + return WDG->VAL; +} + +/** + * @brief Enables or disables the WDG interrupt. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void WDG_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + WDG->CR_b.INTEN = SET; + } + else { + WDG->CR_b.INTEN = RESET; + } +} + +/** + * @brief Checks whether the WDG interrupt has occurred or not. + * @param None + * @retval ITStatus: functional state @ref ITStatus + * This parameter can be: SET or RESET. + */ +ITStatus WDG_GetITStatus(void) +{ + FlagStatus bitstatus = RESET; + + /* Check the status of the WDG interrupt */ + if (WDG->RIS != (uint32_t)RESET) { + bitstatus = SET; + } + + return bitstatus; +} + +/** + * @brief Clears the WDG's interrupt pending bit. + * @param None + * @retval None + */ +void WDG_ClearITPendingBit(void) +{ + WDG->ICR = 0xFFFFFFFF; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/Periph_Driver/src/misc.c b/targets/TARGET_STMBLUE/Periph_Driver/src/misc.c new file mode 100644 index 00000000000..7b6065e22b4 --- /dev/null +++ b/targets/TARGET_STMBLUE/Periph_Driver/src/misc.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "../../Periph_Driver/inc/misc.h" + +/** @addtogroup BLUENRG1_Peripheral_Driver BLUENRG1 Peripheral Driver + * @{ + */ + +/** @addtogroup MISC_Peripheral MISC Peripheral + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions Private Types Definitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines Provate Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/** + * @} + */ + +/** @defgroup MISC_Private_Macros Private Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables Private Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes Private Function Prototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Public_Functions Public Function + * @{ + */ + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a @ref NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitType* NVIC_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + NVIC_SetPriority((IRQn_Type)NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Enables or disables sleep/stop mode on system level. + * @param NewState: functional state @ref FunctionalState + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SystemSleepCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) { + /** Enable Sleep/Stop mode entry on system level */ + SCB->SCR |= 1<SCR &= ~(1<CTRL |= SysTick_CTRL_ENABLE_Msk; + } + else { + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; + } +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2016 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/PeripheralNames.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/PeripheralNames.h new file mode 100644 index 00000000000..8b8afa43ed1 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/PeripheralNames.h @@ -0,0 +1,63 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC_BASE +} ADCName; + +typedef enum { + UART_1 = (int)UART_BASE, +} UARTName; +/* +#define STDIO_UART_TX IO_8 +#define STDIO_UART_RX IO_11 +#define STDIO_UART UART_1 +*/ +typedef enum { + SPI_1 = (int)SPI_BASE, +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE +} I2CName; + +//typedef enum { +// PWM_1 = (int)TIM1_BASE, +// PWM_3 = (int)TIM3_BASE, +// PWM_14 = (int)TIM14_BASE, +// PWM_15 = (int)TIM15_BASE, +// PWM_16 = (int)TIM16_BASE, +// PWM_17 = (int)TIM17_BASE +//} PWMName; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/PinNames.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/PinNames.h new file mode 100644 index 00000000000..a15f3fc34b3 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/PinNames.h @@ -0,0 +1,185 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "BlueNRG1_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + IO_0 = GPIO_Pin_0, + IO_1 = GPIO_Pin_1, + IO_2 = GPIO_Pin_2, + IO_3 = GPIO_Pin_3, + IO_4 = GPIO_Pin_4, + IO_5 = GPIO_Pin_5, + IO_6 = GPIO_Pin_6, + IO_7 = GPIO_Pin_7, + IO_8 = GPIO_Pin_8, + IO_9 = GPIO_Pin_9, + IO_10 = GPIO_Pin_10, + IO_11 = GPIO_Pin_11, + IO_12 = GPIO_Pin_12, + IO_13 = GPIO_Pin_13, + IO_14 = GPIO_Pin_14, + IO_15 = GPIO_Pin_15, + + IO_16 = GPIO_Pin_16, + IO_17 = GPIO_Pin_17, + IO_18 = GPIO_Pin_18, + IO_19 = GPIO_Pin_19, + IO_20 = GPIO_Pin_20, + IO_21 = GPIO_Pin_21, + IO_22 = GPIO_Pin_22, + IO_23 = GPIO_Pin_23, + IO_24 = GPIO_Pin_24, + IO_25 = GPIO_Pin_25, + + // ADC internal channels + ADC_OPEN = 0x10, + ADC2 = 0x11, + ADC1 = 0x12, /////////////cambiare!!!!!!!!! + ADC_DIFF = 0x13, + ADC_TEMP = 0x14, + ADC_VBAT = 0x15, + ADC_VREF = 0x16, + + + // STEVAL_IDB008V2 signals namings + // DIO + DIO0 = IO_0, + DIO1 = IO_1, + DIO2 = IO_2, + DIO3 = IO_3, + DIO4 = IO_4, + DIO5 = IO_5, + DIO6 = IO_6, + DIO7 = IO_7, + DIO8 = IO_8, + DIO11 = IO_11, + DIO12 = IO_12, + DIO13 = IO_13, + DIO14 = IO_14, + // LEDS + DL1 = DIO6, + DL2 = DIO7, + DL3 = DIO14, + // PUSH BUTTONS + PUSH1 = DIO13, + PUSH2 = DIO5, + + + // Arduino connector namings + A0 = DIO12, + //A1 = TEST1, + A2 = DIO13, + A3 = DIO14, + A4 = ADC1, + A5 = ADC2, + D0 = DIO11, + D1 = DIO8, + D2 = DIO11, + D3 = DIO0, + D4 = DIO2, + D5 = DIO3, + D6 = DIO6, + //D7 = RESET, + D8 = DIO8, + D9 = DIO7, + D10 = DIO1, + D11 = DIO2, + D12 = DIO3, + D13 = DIO0, + D14 = DIO5, + D15 = DIO4, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = IO_8, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = IO_11, +#endif + + + // Generic signals namings + LED1 = DL1, + LED2 = DL2, + LED3 = DL3, + USER_BUTTON = PUSH1, + USER_BUTTON_1 = PUSH1, + USER_BUTTON_2 = PUSH2, + + // Standardized button names + BUTTON = USER_BUTTON_1, + BUTTON1 = USER_BUTTON_1, + BUTTON2 = USER_BUTTON_2, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + I2C_SCL = DIO5, + I2C_SDA = DIO4, + SPI_MOSI = DIO2, + SPI_MISO = DIO3, + SPI_SCK = DIO0, + SPI_CS = DIO1, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; +/* +typedef enum { + PullNone = 0, + PullEnable = 1, + PullDefault = PullNone, + PullUp = PullEnable, + PullDown = PullNone, + NoPull = PullNone +} PinMode; +*/ +typedef enum { + PIN_INPUT = 0, + PIN_OUTPUT = 6 +} PinDirection; + +typedef enum { + PortA = 0 +} PortName; + +typedef enum { + PullNone = 0, + PullEnable = 1, + PullDefault = PullNone +} PinMode; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device.h new file mode 100644 index 00000000000..c7b4f443889 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device.h @@ -0,0 +1,27 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +//======================================= +#define DEVICE_ID_LENGTH 24 + +#include "objects.h" + +#endif diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/BlueNRG2.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/BlueNRG2.h new file mode 100644 index 00000000000..e613c488425 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/BlueNRG2.h @@ -0,0 +1,3278 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/** @addtogroup STMicroelectronics + * @{ + */ + +/** @addtogroup BlueNRG2 + * @{ + */ + +#ifndef BLUENRG2_H +#define BLUENRG2_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* --------------------- BlueNRG2 Specific Interrupt Numbers -------------------- */ + GPIO_IRQn = 0, /*!< 0 GPIO bus interrupt */ + NVM_IRQn = 1, /*!< 1 Non-volatile memory (Flash) controller interrupt */ + UART_IRQn = 4, /*!< 4 UART interrupt */ + SPI_IRQn = 5, /*!< 5 SPI interrupt */ + BLUE_CTRL_IRQn = 6, /*!< 6 BLUE controller interrupt */ + WDG_IRQn = 7, /*!< 7 Watchdog interrupt */ + ADC_IRQn = 13, /*!< 13 ADC interrupt */ + I2C2_IRQn = 14, /*!< 14 I2C 2 interrupt */ + I2C1_IRQn = 15, /*!< 15 I2C 1 interrupt */ + MFT1A_IRQn = 17, /*!< 17 Multi functional timer MFT1 interrupt A */ + MFT1B_IRQn = 18, /*!< 18 Multi functional timer MFT1 interrupt B */ + MFT2A_IRQn = 19, /*!< 19 Multi functional timer MFT2 interrupt A */ + MFT2B_IRQn = 20, /*!< 20 Multi functional timer MFT2 interrupt B */ + RTC_IRQn = 21, /*!< 21 RTC interrupt */ + PKA_IRQn = 22, /*!< 22 PKA interrupt */ + DMA_IRQn = 23 /*!< 23 DMA interrupt */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ +#define __CM0_REV 0x0000 /*!< Cortex-M0 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ +#include "system_bluenrg2.h" /*!< BlueNRG2 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO Controller (GPIO) + */ + +typedef struct { /*!< (@ 0x40000000) GPIO Structure */ + __IO uint32_t DATA; /*!< (@ 0x40000000) IO0 to IO14 data value.

Writing to a bit will + drive the written value on the corresponding IO when it is configured + in GPIO mode and the output direction. Reading a bit indicates + the pin value

*/ + __IO uint32_t OEN; /*!< (@ 0x40000004) GPIO output enable register (1 bit per GPIO).
  • 0: + input mode.
  • 1: output mode
*/ + __IO uint32_t PE; /*!< (@ 0x40000008) Pull enable (1 bit per IO).
  • 0: pull disabled.
    • 1: pull enabled
*/ + __IO uint32_t DS; /*!< (@ 0x4000000C) IO driver strength (1 bit per IO).
  • 0: + 2mA.
  • 1: 4 mA
*/ + __IO uint32_t IS; /*!< (@ 0x40000010) Interrupt sense register (1 bit per IO).
  • 0: + edge detection.
  • 1: level detection
*/ + __IO uint32_t IBE; /*!< (@ 0x40000014) Interrupt edge register (1 bit per IO).
  • 0: + single edge.
  • 1: both edges
*/ + __IO uint32_t IEV; /*!< (@ 0x40000018) Interrupt event register (1 bit per IO).
  • 0: + falling edge or low level.
  • 1: rising edge or high level
*/ + __IO uint32_t IE; /*!< (@ 0x4000001C) Interrupt mask register (1 bit per IO).
  • 0: + interrupt disabled.
  • 1: interrupt enabled.
*/ + __I uint32_t RIS; /*!< (@ 0x40000020) Raw interrupt status register (1 bit per IO) */ + __I uint32_t MIS; /*!< (@ 0x40000024) Masked interrupt status register (1 bit per IO) */ + __O uint32_t IC; /*!< (@ 0x40000028) Interrupt clear register (1 bit per IO).
  • 0: + no effect.
  • 1: clear interrupt
*/ + + union { + __IO uint32_t MODE0; /*!< (@ 0x4000002C) Select mode for IO0 to IO7.
  • 000b: GPIO + mode.
  • 001b: Serial1 mode.
  • 100b: Serial0 mode.
  • 101b + : Microphone/ADC mode.
*/ + + struct { + __IO uint32_t IO0 : 3; /*!< [0..2] IO0 mode */ + uint32_t : 1; + __IO uint32_t IO1 : 3; /*!< [4..6] IO1 mode */ + uint32_t : 1; + __IO uint32_t IO2 : 3; /*!< [8..10] IO2 mode */ + uint32_t : 1; + __IO uint32_t IO3 : 3; /*!< [12..14] IO3 mode */ + uint32_t : 1; + __IO uint32_t IO4 : 3; /*!< [16..18] IO4 mode */ + uint32_t : 1; + __IO uint32_t IO5 : 3; /*!< [20..22] IO5 mode */ + uint32_t : 1; + __IO uint32_t IO6 : 3; /*!< [24..26] IO6 mode */ + uint32_t : 1; + __IO uint32_t IO7 : 3; /*!< [28..30] IO7 mode */ + } MODE0_b; /*!< [31] BitSize */ + }; + + union { + __IO uint32_t MODE1; /*!< (@ 0x40000030) Select mode for IO8 to IO15.
  • 000b: GPIO + mode.
  • 001b: Serial1 mode.
  • 100b: Serial0 mode.
  • 101b + : Microphone/ADC mode.
*/ + + struct { + __IO uint32_t IO8 : 3; /*!< [0..2] IO8 mode */ + uint32_t : 1; + __IO uint32_t IO9 : 3; /*!< [4..6] IO9 mode */ + uint32_t : 1; + __IO uint32_t IO10 : 3; /*!< [8..10] IO10 mode */ + uint32_t : 1; + __IO uint32_t IO11 : 3; /*!< [12..14] IO11 mode */ + uint32_t : 1; + __IO uint32_t IO12 : 3; /*!< [16..18] IO12 mode */ + uint32_t : 1; + __IO uint32_t IO13 : 3; /*!< [20..22] IO13 mode */ + uint32_t : 1; + __IO uint32_t IO14 : 3; /*!< [24..26] IO14 mode */ + uint32_t : 1; + __IO uint32_t IO15 : 3; /*!< [28..30] IO15 mode */ + } MODE1_b; /*!< [31] BitSize */ + }; + + union { + __IO uint32_t MODE2; /*!< (@ 0x40000034) Select mode for IO16 to IO23 */ + + struct { + __IO uint32_t IO16 : 3; /*!< [0..2] IO16 mode */ + uint32_t : 1; + __IO uint32_t IO17 : 3; /*!< [4..6] IO17 mode */ + uint32_t : 1; + __IO uint32_t IO18 : 3; /*!< [8..10] IO18 mode */ + uint32_t : 1; + __IO uint32_t IO19 : 3; /*!< [12..14] IO19 mode */ + uint32_t : 1; + __IO uint32_t IO20 : 3; /*!< [16..18] IO20 mode */ + uint32_t : 1; + __IO uint32_t IO21 : 3; /*!< [20..22] IO21 mode */ + uint32_t : 1; + __IO uint32_t IO22 : 3; /*!< [24..26] IO22 mode */ + uint32_t : 1; + __IO uint32_t IO23 : 3; /*!< [28..30] IO23 mode */ + } MODE2_b; /*!< [31] BitSize */ + }; + + union { + __IO uint16_t MODE3; /*!< (@ 0x40000038) Select mode for IO24 to IO25 */ + + struct { + __IO uint16_t IO24 : 3; /*!< [0..2] IO24 mode */ + uint16_t : 1; + __IO uint16_t IO25 : 3; /*!< [4..6] IO25 mode */ + } MODE3_b; /*!< [7] BitSize */ + }; + __I uint16_t RESERVED; + __IO uint32_t DATS; /*!< (@ 0x4000003C) Set some bits of DATA when in GPIO mode without + affecting the others (1 bit per IO).
  • 0: no effect.
  • 1: + set at 1 the bit
*/ + __IO uint32_t DATC; /*!< (@ 0x40000040) Clear some bits of DATA when in GPIO mode without + affecting the others (1 bit per IO).
  • 0: no effect.
  • 1: + clear at 0 the bit
*/ + + union { + __IO uint32_t MFTX; /*!< (@ 0x40000044) Select the IO to be used as capture input for + the MFTX timers */ + + struct { + __IO uint32_t MFT1_TIMER_A: 8; /*!< [0..7] Selects which IO must be used as input pin TnA for the + MFT1 peripheral. Only mode 2 and mode 4.
  • 0x00: IO0.
  • 0x01: + IO1
  • 0x02: IO2
  • ...
  • 0x0E: IO14
*/ + __IO uint32_t MFT1_TIMER_B: 8; /*!< [8..15] Selects which IO must be used as input pin TnB for the + MFT1 peripheral. Only mode 2 and mode 4.
  • 0x00: IO0.
  • 0x01: + IO1
  • 0x02: IO2
  • ...
  • 0x0E: IO14
*/ + __IO uint32_t MFT2_TIMER_A: 8; /*!< [16..23] Selects which IO must be used as input pin TnA for + the MFT2 peripheral. Only mode 2 and mode 4.
  • 0x00: IO0.
  • 0x0 + 1: IO1
  • 0x02: IO2
  • ...
  • 0x0E: IO14
*/ + __IO uint32_t MFT2_TIMER_B: 8; /*!< [24..31] Selects which IO must be used as input pin TnB for + the MFT2 peripheral. Only mode 2 and mode 4.
  • 0x00: IO0.
  • 0x0 + 1: IO1
  • 0x02: IO2
  • ...
  • 0x0E: IO14
*/ + } MFTX_b; /*!< [32] BitSize */ + }; +} GPIO_Type; + + +/* ================================================================================ */ +/* ================ FLASH ================ */ +/* ================================================================================ */ + + +/** + * @brief Flash Controller (FLASH) + */ + +typedef struct { /*!< (@ 0x40100000) FLASH Structure */ + __IO uint16_t COMMAND; /*!< (@ 0x40100000) Commands for the module */ + __I uint16_t RESERVED; + __IO uint16_t CONFIG; /*!< (@ 0x40100004) Configure the wrapper */ + __I uint16_t RESERVED1; + + union { + __IO uint16_t IRQSTAT; /*!< (@ 0x40100008) Flash status interrupt (masked) */ + + struct { + __IO uint16_t CMDDONE : 1; /*!< [0..0] Command is done. 1: clear the interrupt pending bit. */ + __IO uint16_t CMDSTART : 1; /*!< [1..1] Command is started. 1: clear the interrupt pending bit. */ + __IO uint16_t CMDERR : 1; /*!< [2..2] Command written while BUSY. 1: clear the interrupt pending + bit. */ + __IO uint16_t ILLCMD : 1; /*!< [3..3] Illegal command written. 1: clear the interrupt pending + bit. */ + __IO uint16_t READOK : 1; /*!< [4..4] Mass read was OK. 1: clear the interrupt pending bit. */ + __IO uint16_t FLNREADY : 1; /*!< [5..5] Flash not ready (sleep). 1: clear the interrupt pending + bit. */ + } IRQSTAT_b; /*!< [6] BitSize */ + }; + __I uint16_t RESERVED2; + + union { + __IO uint16_t IRQMASK; /*!< (@ 0x4010000C) Mask for interrupts */ + + struct { + __IO uint16_t CMDDONE : 1; /*!< [0..0] Command is done. */ + __IO uint16_t CMDSTART : 1; /*!< [1..1] Command is started. */ + __IO uint16_t CMDERR : 1; /*!< [2..2] Command written while BUSY */ + __IO uint16_t ILLCMD : 1; /*!< [3..3] Illegal command written */ + __IO uint16_t READOK : 1; /*!< [4..4] Mass read was OK. */ + __IO uint16_t FLNREADY : 1; /*!< [5..5] Flash not ready (sleep). */ + } IRQMASK_b; /*!< [6] BitSize */ + }; + __I uint16_t RESERVED3; + + union { + __IO uint16_t IRQRAW; /*!< (@ 0x40100010) Status interrupts (unmasked) */ + + struct { + __IO uint16_t CMDDONE : 1; /*!< [0..0] Command is done. */ + __IO uint16_t CMDSTART : 1; /*!< [1..1] Command is started. */ + __IO uint16_t CMDERR : 1; /*!< [2..2] Command written while BUSY */ + __IO uint16_t ILLCMD : 1; /*!< [3..3] Illegal command written */ + __IO uint16_t READOK : 1; /*!< [4..4] Mass read was OK. */ + __IO uint16_t FLNREADY : 1; /*!< [5..5] Flash not ready (sleep). */ + } IRQRAW_b; /*!< [6] BitSize */ + }; + __I uint16_t RESERVED4; + __I uint16_t SIZE; /*!< (@ 0x40100014) Indicates the size of the main Flash */ + __I uint16_t RESERVED5; + __IO uint32_t ADDRESS; /*!< (@ 0x40100018) Address for programming Flash, will auto-increment */ + __I uint32_t RESERVED6[9]; + __IO uint32_t DATA0; /*!< (@ 0x40100040) Program cycle data */ + __IO uint32_t DATA1; /*!< (@ 0x40100044) Program cycle data */ + __IO uint32_t DATA2; /*!< (@ 0x40100048) Program cycle data */ + __IO uint32_t DATA3; /*!< (@ 0x4010004C) Program cycle data */ +} FLASH_Type; + + +/* ================================================================================ */ +/* ================ SYSTEM_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief System controller (SYSTEM_CTRL) + */ + +typedef struct { /*!< (@ 0x40200000) SYSTEM_CTRL Structure */ + __IO uint8_t WKP_IO_IS; /*!< (@ 0x40200000) Level selection for wakeup IO (1 bit for IO) + IO[13:9].
  • 0: The system wakes up when IO is low.
  • 1: + The system wakes up when IO is high.
*/ + __I uint8_t RESERVED[3]; + __IO uint8_t WKP_IO_IE; /*!< (@ 0x40200004) Enables the IO that wakes up the device (1 bit + for IO) IO[13:9].
  • 0: The wakes up feature on the IO is + disabled.
  • 1: The wakes up feature on the IO is enabled.
*/ + __I uint8_t RESERVED1[3]; + + union { + __IO uint8_t CTRL; /*!< (@ 0x40200008) XO frequency indication to provide by the application */ + + struct { + __IO uint8_t MHZ32_SEL : 1; /*!< [0..0] Indicates the crystal frequency used in the application.
  • 0: + The 16 MHz is selected.
  • 1: The 32 MHz is selected.
*/ + } CTRL_b; /*!< [1] BitSize */ + }; + __I uint8_t RESERVED2[3]; + __IO uint8_t SLEEPIO_OEN; /*!< (@ 0x4020000C) IO output enable register for low power modes. + It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.
  • 0: + IO output disabled.
  • 1: IO output is enabled.
*/ + __I uint8_t RESERVED3[3]; + __IO uint8_t SLEEPIO_OUT; /*!< (@ 0x40200010) IO data output value register for low power modes. + It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.
  • 0: + put the IO low.
  • 1: put the IO high.
*/ + __I uint8_t RESERVED4[3]; + __IO uint8_t SLEEPIO_DS; /*!< (@ 0x40200014) IO drive strength control register for low power + modes. It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 + for IO9.
  • 0: drive up to 2 mA.
  • 1: drive up to + 4 mA.
*/ + __I uint8_t RESERVED5[3]; + __IO uint8_t SLEEPIO_PE; /*!< (@ 0x40200018) IO pull enable register for low power modes. + It is 1 bit for IO: bit0 for IO9, bit1 for IO10, bit2 for IO9.
  • 0: + pull disabled.
  • 1: pull enabled.
*/ +} SYSTEM_CTRL_Type; + + +/* ================================================================================ */ +/* ================ UART ================ */ +/* ================================================================================ */ + + +/** + * @brief UART (UART) + */ + +typedef struct { /*!< (@ 0x40300000) UART Structure */ + + union { + __IO uint16_t DR; /*!< (@ 0x40300000) Data Register */ + + struct { + __IO uint16_t DATA : 8; /*!< [0..7] UART data register:
  • Receive: read data character.
  • T + ransmit: write data character.
*/ + __I uint16_t FE : 1; /*!< [8..8] Frame error. This bit is set to 1 if the received character + did not have a valid stop bit. In FIFO mode, this error is associated + with the character at the top of the FIFO. */ + __I uint16_t PE : 1; /*!< [9..9] Parity error. This bit is set to 1 if the parity of the + received data character does not match the parity selected as + defined by bits 2 and 7 of the LCRH_RX register. In FIFO mode, + this error is associated with the character at the top of the + FIFO. */ + __I uint16_t BE : 1; /*!< [10..10] Break error. This bit is set to 1 if a break condition + was detected, indicating that the received data input was held + low for longer than a full-word transmission time (defined as + start, data, parity and stop bits). In FIFO mode, this error + is associated with the character at the top of the FIFO. When + a break occurs, only one 0 character is loaded into the FIFO. + The next character is only enabled after the receive data input + goes to HIGH (marking state), and the next valid start bit is + received */ + __I uint16_t OE : 1; /*!< [11..11] Overrun error. This bit is set to 1 if data is received + and the receive FIFO is already full. This is cleared to 0b + once there is an empty space in the FIFO and a new character + can be written to it. The FIFO content remains valid since no + further data is written when the FIFO is full, only the content + of the shift register is overwritten. */ + } DR_b; /*!< [12] BitSize */ + }; + __I uint16_t RESERVED; + + union { + __IO uint32_t ECR; /*!< (@ 0x40300004) Error Clear Register. A write to this register + clears the framing (FE), parity (PE), break (BE), and overrun + (OE) errors. */ + + union { + __I uint32_t RSR; /*!< (@ 0x40300004) Receive Status Register */ + + struct { + __I uint32_t FE : 1; /*!< [0..0] Frame error. This bit is set to 1 if the received character + did not have a valid stop bit (a valid stop bit is 1).This bit + is cleared to 0b after a write to ECR. In FIFO mode, this error + is associated with the character at the top of the FIFO. */ + __I uint32_t PE : 1; /*!< [1..1] Parity error. This bit is set to 1 if the parity of the + received data character does not match the parity selected as + defined by bits 2 and 7 of the LCRH_RX register.This bit is + cleared to 0b after a write to ECR. In FIFO mode, this error + is associated with the character at the top of the FIFO. */ + __I uint32_t BE : 1; /*!< [2..2] Break error. This bit is set to 1 if a break condition + was detected, indicating that the received data input was held + low for longer than a full-word transmission time (defined as + start, data, parity and stop bits). This bit is cleared to 0b + after a write to ECR. In FIFO mode, this error is associated + with the character at the top of the FIFO. When a break occurs, + only one 0 character is loaded into the FIFO. The next character + is only enabled after the receive data input goes to HIGH (marking + state), and */ + __I uint32_t OE : 1; /*!< [3..3] Overrun error. This bit is set to 1 if data is received + and the receive FIFO is already full. This is cleared to 0 by + a write to ECR (data value is not important). The FIFO contents + remain valid since no further data is written when the FIFO + is full, only the content of the shift register are overwritten. + The CPU or DMA must now read the data in order to empty the + FIFO. */ + } RSR_b; /*!< [4] BitSize */ + }; + }; + __I uint32_t RESERVED1; + + union { + __IO uint32_t TIMEOUT; /*!< (@ 0x4030000C) Timeout Register */ + + struct { + __IO uint32_t PERIOD : 22; /*!< [0..21] Timeout period configuration. This bit field contains + the timeout period for the UART timeout interrupt assertion. + The receive timeout interrupt is asserted when the receive FIFO + is not empty and no further data is received over a programmed + timeout period. The duration before the timeout interrupt will + assert is calculated by the following formula:

Timeout_Duration + = (TIMEOUT_PERIOD) / (OVSP * Baud_Rate)

or

Timeout_Duration + = (TIMEOUT_PERIOD) * Baud_Divisor * Tuartclk

*/ + } TIMEOUT_b; /*!< [22] BitSize */ + }; + __I uint32_t RESERVED2[2]; + + union { + __I uint16_t FR; /*!< (@ 0x40300018) Flag Register */ + + struct { + __I uint16_t CTS : 1; /*!< [0..0] Clear to send. */ + uint16_t : 2; + __I uint16_t BUSY : 1; /*!< [3..3] UART Busy. If this bit is set to 1, the UART is busy + transmitting data. This bit remains set until the complete byte, + including all the stop bits, has been sent from the shift register. + However, if the transmit section of the UART is disabled in + the middle of a transmission, the BUSY bit gets cleared. This + bit is set again once the transmit section is re-enabled to + complete the remaining transmission.This bit is set as soon + as the transmit FIFO becomes nonempty (regardless of whether + the UART is enabled or */ + __I uint16_t RXFE : 1; /*!< [4..4] Receive FIFO empty. If the FIFO is disabled (bit FEN + = 0b), this bit is set when the receive holding register is + empty. If the FIFO is enabled (FEN = 1b), the RXFE bit is set + when the receive FIFO is empty. */ + __I uint16_t TXFF : 1; /*!< [5..5] Transmit FIFO full. If the FIFO is disabled (bit FEN + = 0b), this bit is set when the transmit holding register is + full. If the FIFO is enabled (FEN = 1b), the TXFF bit is set + when the transmit FIFO is full. */ + __I uint16_t RXFF : 1; /*!< [6..6] Receive FIFO full. If the FIFO is disabled (bit FEN = + 0b), this bit is set when the receive holding register is full. + If the FIFO is enabled (FEN = 1b), the RXFF bit is set when + the receive FIFO is full. */ + __I uint16_t TXFE : 1; /*!< [7..7] Transmit FIFO empty. If the FIFO is disabled (bit FEN + = 0b), this bit is set when the transmit holding register is + empty. If the FIFO is enabled (FEN = 1b), the TXFE bit is set + when the transmit FIFO is empty. */ + uint16_t : 1; + __I uint16_t DCTS : 1; /*!< [9..9] Delta Clear To Send. This bit is set CTS changes since + the last read of the FR register. */ + uint16_t : 3; + __I uint16_t RTXDIS : 1; /*!< [13..13] Remote Transmitter Disabled (software flow control). + This bit indicates an Xoff character was sent to the remote + transmitter to stop it after the received FIFO has passed over + its trigger limit. This bit is cleared when a Xon character + is sent to the remote transmitter. */ + } FR_b; /*!< [14] BitSize */ + }; + __I uint16_t RESERVED3; + + union { + __IO uint8_t LCRH_RX; /*!< (@ 0x4030001C) Receive Line Control Register */ + + struct { + uint8_t : 1; + __IO uint8_t PEN_RX : 1; /*!< [1..1] RX parity enable:
  • 0: Parity disabled.
  • 1: + Parity enabled.
*/ + __IO uint8_t EPS_RX : 1; /*!< [2..2] RX even parity selection, when the parity is enabled.
  • 0: + Odd parity generation and checking is performed during reception, + which check for an odd number of 1s in data and parity bits.
  • 1: + Even parity generation and checking is performed during reception, + which check for an even number of 1s in data and parity bits.
*/ + __IO uint8_t STP2_RX : 1; /*!< [3..3] RX two stop bits select. This bit enables the check for + two stop bits being received:
  • 0: 1 stop bit received.
  • 1: + 2 stop bits received.
*/ + __IO uint8_t FEN_RX : 1; /*!< [4..4] RX enable FIFOs. This bit enables/disables the receive + RX FIFO buffer:
  • 0: RX FIFO is disabled (character mode).
  • 1: + RX FIFO is enabled.
*/ + __IO uint8_t WLEN_RX : 2; /*!< [5..6] RX Word length. This bit field indicates the number of + data bits received in a frame as follows:
  • 00b: 5 bits.
  • 01b: + 6 bits.
  • 10b: 7 bits.
  • 11b: 8 bits.
*/ + __IO uint8_t SPS_RX : 1; /*!< [7..7] RX stick parity select:
  • 0: stick parity is disabled.
  • 1: when PEN_RX = 1b (parity enabled) and EPS_RX = 1b (even parity), + the parity is checked as a 0. When PEN_RX = 1b and EPS_RX = + 0b (odd parity), the parity bit is checked as a 1.
*/ + } LCRH_RX_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED4[7]; + + union { + __IO uint16_t IBRD; /*!< (@ 0x40300024) Integer Baud Rate Register */ + + struct { + __IO uint16_t DIVINT : 16; /*!< [0..15] Baud rate integer. The baud rate divisor is calculated + as follows:

When OVSFACT = 0b in the CR register: Baud rate + divisor = (Frequency (UARTCLK)/(16*Baud rate))

When OVSFACT + = 1b in CR register: Baud rate divisor = (Frequency (UARTCLK)/(8*Baud + rate))

where Frequency (UARTCLK) is the UART reference clock + frequency. The baud rate divisor comprises the integer value + (DIVINT) and the fractional value (DIVFRAC). The contents of + the IBRD and FBRD registers are not updated until transmission + or recept */ + } IBRD_b; /*!< [16] BitSize */ + }; + __I uint16_t RESERVED5; + + union { + __IO uint8_t FBRD; /*!< (@ 0x40300028) Fractional Baud Rate Register */ + + struct { + __IO uint8_t DIVFRAC : 6; /*!< [0..5] Baud rate fraction. Baud rate integer. The baud rate + divisor is calculated as follows:

When OVSFACT = 0b in the + CR register: Baud rate divisor = (Frequency (UARTCLK)/(16*Baud + rate))

When OVSFACT = 1b in CR register: Baud rate divisor + = (Frequency (UARTCLK)/(8*Baud rate))

where Frequency (UARTCLK) + is the UART reference clock frequency. The baud rate divisor + comprises the integer value (DIVINT) and the fractional value + (DIVFRAC). The contents of the IBRD and FBRD registers are not + updated until tr */ + } FBRD_b; /*!< [6] BitSize */ + }; + __I uint8_t RESERVED6[3]; + + union { + __IO uint8_t LCRH_TX; /*!< (@ 0x4030002C) Transmit Line Control Register */ + + struct { + __IO uint8_t BRK : 1; /*!< [0..0] Send break. This bit allows a continuous low-level to + be forced on TX output, after completion of the current character. + This bit must be asserted for at least one complete frame transmission + time in order to generate a break condition. The transmit FIFO + contents remain unaffected during a break condition.
  • 0: + Normal transmission.
  • 1: Break condition transmission.
*/ + __IO uint8_t PEN_TX : 1; /*!< [1..1] TX parity enable:
  • 0: Parity disabled.
  • 1: + Parity Enable.
*/ + __IO uint8_t EPS_TX : 1; /*!< [2..2] TX even parity select. This bit selects the parity generation, + when the parity is enabled (PEN_TX =1b). This bit has no effect + when parity is disabled (PEN_TX = 0b).
  • 0: Odd parity + generation and checking is performed during transmission, which + check for an odd number of 1s in data and parity bits.
  • 1: + Even parity generation and checking is performed during transmission, + which check for an even number of 1s in data and parity bits.
*/ + __IO uint8_t STP2_TX : 1; /*!< [3..3] TX two stop bits select. This bit enables the check for + two stop bits being received:
  • 0: 1 stop bit received.
  • 1: + 2 stop bits received.
*/ + __IO uint8_t FEN_TX : 1; /*!< [4..4] TX Enable FIFO. This bit enables/disables the transmit + TX FIFO buffer:
  • 0: TX FIFO is disabled (character mode), + i.e. the TX FIFO becomes a 1-byte deep holding register.
  • 1: + TX FIFO is enabled.
*/ + __IO uint8_t WLEN_TX : 2; /*!< [5..6] TX word length. This bit field indicates the number of + data bits transmitted in a frame as follows:
  • 00b: 5 bits.
  • 0 + 1b: 6 bits.
  • 10b: 7 bits.
  • 11b: 8 bits.
*/ + __IO uint8_t SPS_TX : 1; /*!< [7..7] TX Stick parity check:
  • 0: stick parity disable.
  • 1: + when PEN_TX = 1b (parity enabled) and EPS_TX = 1b (even parity), + the parity is transmitted as a 0. When PEN_TX = 1b and EPS_TX + = 0b (odd parity), the parity bit is transmitted as a 1.
*/ + } LCRH_TX_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED7[3]; + + union { + __IO uint32_t CR; /*!< (@ 0x40300030) Control Register */ + + struct { + __IO uint32_t EN : 1; /*!< [0..0] UART enable. This bit enables the UART.
  • 0: UART + is disabled.
  • 1: UART is enabled. Data transmission and + reception can occur. When the UART is disabled in the middle + of transmission or reception, it completes the current character + before stopping.
*/ + uint32_t : 2; + __IO uint32_t OVSFACT : 1; /*!< [3..3] UART oversampling factor.This bit enables the UART oversampling + factor. If UARTCLK is 16 MHz thus max. baud-rate is 1 Mbaud + when OVSFACT = 0b, and 2 Mbaud when OVSFACT = 1b.
  • 0: + UART it is 16 UARTCLK clock cycles.
  • 1: UART it is 8 + UARTCLK clock cycles.
*/ + uint32_t : 4; + __IO uint32_t TXE : 1; /*!< [8..8] Transmit enable.
  • 0b: UART TX disabled.
  • 1b: + UART TX enabled.
*/ + __IO uint32_t RXE : 1; /*!< [9..9] Receive enable.
  • 0b: UART RX disabled.
  • 1b: + UART RX enabled.
*/ + uint32_t : 1; + __IO uint32_t RTS : 1; /*!< [11..11] Request to send.
  • 0: RTS is high.
  • 1: + RTS is low.
*/ + uint32_t : 2; + __IO uint32_t RTSEN : 1; /*!< [14..14] RTS hardware flow control enable.
  • 0b: RTS disabled.
    • 1b: RTS enabled. Data is only requested when there is space + in the receive FIFO for it to be received.
*/ + __IO uint32_t CTSEN : 1; /*!< [15..15] CTS hardware flow control enable.
  • 0b: CTS disabled.
    • 1b: CTS enabled. Data is only transmitted when the CTS is asserted.< + /ul> */ + __IO uint32_t STA_B_DURATION: 4; /*!< [16..19] START bit duration Receiver state. These bits can be + used to configure the START bit duration (in clock cycles) to + get the bit sampled in the middle of the UART receiver. These + bits can be used only when using high baud rates (IBRD = 1, + FBRD >= 0 and OVSFACT = 1). Below the formula to calculate the + START bit duration receiver state:

    STA_B_DURATION = Integer(Fuartclk/(2* + BAUD RATE)) - 1

    Example: when UARTCLK = 16 MHz and BAUD RATE + = 2.0 Mbps then STA_B_DURATION = 4 - 1 = 3. STA_B_DURATION field + should */ + } CR_b; /*!< [20] BitSize */ + }; + + union { + __IO uint8_t IFLS; /*!< (@ 0x40300034) Interrupt FIFO level select register */ + + struct { + __IO uint8_t TXIFLSEL : 3; /*!< [0..2] Transmit interrupt FIFO level select. This bit field + selects the trigger points for TX FIFO interrupt:
    • 000b: + Interrupt when FIFO >= 1/64 empty.
    • 001b: Interrupt when + FIFO >= 1/32 empty.
    • 010b: Interrupt when FIFO >= 1/16 + empty.
    • 011b: Interrupt when FIFO >= 1/8 empty.
    • 100b: + Interrupt when FIFO >= 1/4 empty.
    • 101b: Interrupt when + FIFO >= 1/2 empty.
    • 110b: Interrupt when FIFO >= 3/4 + empty.
    */ + __IO uint8_t RXIFLSEL : 3; /*!< [3..5] Receive interrupt FIFO level select. This bit field selects + the trigger points for RX FIFO interrupt:
    • 000b: Interrupt + when FIFO >= 1/64 full.
    • 001b: Interrupt when FIFO >= + 1/32 full.
    • 010b: Interrupt when FIFO >= 1/16 full.
    • 011b: + Interrupt when FIFO >= 1/8 full.
    • 100b: Interrupt when + FIFO >= 1/4 full.
    • 101b: Interrupt when FIFO >= 1/2 full.
    • 1 + 10b: Interrupt when FIFO >= 3/4 full.
    */ + } IFLS_b; /*!< [6] BitSize */ + }; + __I uint8_t RESERVED8[3]; + + union { + __IO uint16_t IMSC; /*!< (@ 0x40300038) Interrupt Mask Set/Clear Register */ + + struct { + uint16_t : 1; + __IO uint16_t CTSMIM : 1; /*!< [1..1] Clear to send modem interrupt mask. On a read, the current + mask for the CTSMIM interrupt is returned.
    • 0: Clears + the mask (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + uint16_t : 2; + __IO uint16_t RXIM : 1; /*!< [4..4] Receive interrupt mask. On a read, the current mask for + the RXIM interrupt is returned.
    • 0: Clears the mask (interrupt + is disabled).
    • 1: Sets the mask (interrupt is enabled).
    */ + __IO uint16_t TXIM : 1; /*!< [5..5] Transmit interrupt mask. On a read, the current mask + for the TXIM interrupt is returned.
    • 0: Clears the mask + (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t RTIM : 1; /*!< [6..6] Receive timeout interrupt mask. On a read, the current + mask for the RTIM interrupt is returned.
    • 0: Clears the + mask (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t FEIM : 1; /*!< [7..7] Framing error interrupt mask. On a read, the current + mask for the FEIM interrupt is returned.
    • 0: Clears the + mask (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t PEIM : 1; /*!< [8..8] Parity error interrupt mask. On a read, the current mask + for the PEIM interrupt is returned.
    • 0: Clears the mask + (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t BEIM : 1; /*!< [9..9] Break error interrupt mask. On a read, the current mask + for the BEIM interrupt is returned.
    • 0: Clears the mask + (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t OEIM : 1; /*!< [10..10] Overrun error interrupt mask. On a read, the current + mask for the OEIM interrupt is returned.
    • 0: Clears the + mask (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t XOFFIM : 1; /*!< [11..11] XOFF interrupt mask. On a read, the current mask for + the XOFFIM interrupt is returned.
    • 0: Clears the mask + (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + __IO uint16_t TXFEIM : 1; /*!< [12..12] TX FIFO empty interrupt mask. On a read, the current + mask for the TXFEIM interrupt is returned.
    • 0: Clears + the mask (interrupt is disabled).
    • 1: Sets the mask (interrupt + is enabled).
    */ + } IMSC_b; /*!< [13] BitSize */ + }; + __I uint16_t RESERVED9; + + union { + __I uint16_t RIS; /*!< (@ 0x4030003C) Raw Interrupt Status Register */ + + struct { + uint16_t : 1; + __I uint16_t CTSMIS : 1; /*!< [1..1] Clear to send interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + uint16_t : 2; + __I uint16_t RXIS : 1; /*!< [4..4] Receive interrupt status.
    • 0: The interrupt is + not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t TXIM : 1; /*!< [5..5] Transmit interrupt status.
    • 0: The interrupt is + not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t RTIS : 1; /*!< [6..6] Receive timeout interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t FEIS : 1; /*!< [7..7] Framing error interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t PEIS : 1; /*!< [8..8] Parity error interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t BEIS : 1; /*!< [9..9] Break error interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t OEIS : 1; /*!< [10..10] Overrun error interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t XOFFIS : 1; /*!< [11..11] XOFF interrupt status.
    • 0: The interrupt is not + pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t TXFEIS : 1; /*!< [12..12] TX FIFO empty interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + } RIS_b; /*!< [13] BitSize */ + }; + __I uint16_t RESERVED10; + + union { + __I uint16_t MIS; /*!< (@ 0x40300040) Masked Interrupt Status Register */ + + struct { + uint16_t : 1; + __I uint16_t CTSMMIS : 1; /*!< [1..1] Clear to send masked interrupt status.
    • 0: The + interrupt is not pending.
    • 1: The interrupt is pending.
    */ + uint16_t : 2; + __I uint16_t RXMIS : 1; /*!< [4..4] Receive masked interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t TXMIS : 1; /*!< [5..5] Transmit masked interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t RTMIS : 1; /*!< [6..6] Receive timeout masked interrupt status.
    • 0: The + interrupt is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t FEMIS : 1; /*!< [7..7] Framing error masked interrupt status.
    • 0: The + interrupt is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t PEMIS : 1; /*!< [8..8] Parity error masked interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t BEMIS : 1; /*!< [9..9] Break error masked interrupt status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t OEMIS : 1; /*!< [10..10] Overrun error masked interrupt status.
    • 0: The + interrupt is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t XOFFMIS : 1; /*!< [11..11] XOFF interrupt masked status.
    • 0: The interrupt + is not pending.
    • 1: The interrupt is pending.
    */ + __I uint16_t TXFEMIS : 1; /*!< [12..12] TX FIFO empty masked interrupt status.
    • 0: The + interrupt is not pending.
    • 1: The interrupt is pending.
    */ + } MIS_b; /*!< [13] BitSize */ + }; + __I uint16_t RESERVED11; + + union { + __O uint16_t ICR; /*!< (@ 0x40300044) Interrupt Clear Register */ + + struct { + uint16_t : 1; + __O uint16_t CTSMIC : 1; /*!< [1..1] Clear to send modem interrupt clear.
    • 0: No effect.
    • 1 + : Clears the interrupt.
    */ + uint16_t : 2; + __O uint16_t RXIC : 1; /*!< [4..4] Receive interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t TXIC : 1; /*!< [5..5] Transmit interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t RTIC : 1; /*!< [6..6] Receive timeout interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t FEIC : 1; /*!< [7..7] Framing error interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t PEIC : 1; /*!< [8..8] Parity error interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t BEIC : 1; /*!< [9..9] Break error interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t OEIC : 1; /*!< [10..10] Overrun error interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t XOFFIC : 1; /*!< [11..11] XOFF interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + __O uint16_t TXFEIC : 1; /*!< [12..12] TX FIFO empty interrupt clear.
    • 0: No effect.
    • 1: + Clears the interrupt.
    */ + } ICR_b; /*!< [13] BitSize */ + }; + __I uint16_t RESERVED12; + + union { + __IO uint8_t DMACR; /*!< (@ 0x40300048) DMA control register */ + + struct { + __IO uint8_t RXDMAE : 1; /*!< [0..0] Receive DMA enable bit.
    • 0: DMA mode is disabled + for reception.
    • 1: DMA mode is enabled for reception.
    */ + __IO uint8_t TXDMAE : 1; /*!< [1..1] Transmit DMA enable bit.
    • 0: DMA mode is disabled + for transmit.
    • 1: DMA mode is enabled for transmit.
    */ + uint8_t : 1; + __IO uint8_t DMAONERR : 1; /*!< [3..3] DMA on error.
    • 0: UART error interrupt status has + no impact in receive DMA mode.
    • 1: DMA receive requests + are disabled when the UART error interrupt is asserted.
    */ + } DMACR_b; /*!< [4] BitSize */ + }; + __I uint8_t RESERVED13[7]; + + union { + __IO uint8_t XFCR; /*!< (@ 0x40300050) XON/XOFF Control Register */ + + struct { + __IO uint8_t SFEN : 1; /*!< [0..0] Software flow control enable.
    • 0: Software flow + control disable.
    • 1: software flow control enable.
    */ + __IO uint8_t SFRMOD : 2; /*!< [1..2] Software receive flow control mode:
    • 00b: Receive + flow control is disabled.
    • 01b: Xon1, Xoff1 characters + are used in receiving software flow control.
    • 10b: Xon2, + Xoff2 characters are used in receiving software flow control.
    • 11b: + Xon1 and Xon2, Xoff1 and Xoff2 characters are used in receiving + software flow control.
    */ + __IO uint8_t SFTMOD : 2; /*!< [3..4] Software transmit flow control mode:
    • 00b: Transmit + flow control is disabled.
    • 01b: Xon1, Xoff1 characters + are used in transmitting software flow control.
    • 10b: + Xon2, Xoff2 characters are used in transmitting software flow + control.
    • 11b: Xon1 and Xon2, Xoff1 and Xoff2 characters + are used in transmitting software flow control.
    */ + __IO uint8_t XONANY : 1; /*!< [5..5] Xon-any bit:
    • 0: Incoming character must match + Xon programmed value(s) to be a valid Xon.
    • 1: Any incoming + character is considered as a valid Xon.
    */ + __IO uint8_t SPECHAR : 1; /*!< [6..6] Special character detection bit.
    • 0: Special character + detection disabled.
    • 1: Special character detection enabled.
      • */ + } XFCR_b; /*!< [7] BitSize */ + }; + __I uint8_t RESERVED14[3]; + + union { + __IO uint8_t XON1; /*!< (@ 0x40300054) Register used to store the Xon1 character used + for software flow control */ + + struct { + __IO uint8_t XON1 : 8; /*!< [0..7] Value of Xon1 character used in the software flow control */ + } XON1_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED15[3]; + + union { + __IO uint8_t XON2; /*!< (@ 0x40300058) Register used to store the Xon2 character used + for software flow control */ + + struct { + __IO uint8_t XON2 : 8; /*!< [0..7] Value of Xon2 character used in the software flow control */ + } XON2_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED16[3]; + + union { + __IO uint8_t XOFF1; /*!< (@ 0x4030005C) Register used to store the Xoff1 character used + for software flow control */ + + struct { + __IO uint8_t XOFF1 : 8; /*!< [0..7] Value of Xoff1 character used in the software flow control */ + } XOFF1_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED17[3]; + + union { + __IO uint8_t XOFF2; /*!< (@ 0x40300060) Register used to store the Xoff2 character used + for software flow control */ + + struct { + __IO uint8_t XOFF2 : 8; /*!< [0..7] Value of Xoff2 character used in the software flow control */ + } XOFF2_b; /*!< [8] BitSize */ + }; +} UART_Type; + + +/* ================================================================================ */ +/* ================ SPI ================ */ +/* ================================================================================ */ + + +/** + * @brief Serial peripheral interface (SPI) + */ + +typedef struct { /*!< (@ 0x40400000) SPI Structure */ + + union { + __IO uint32_t CR0; /*!< (@ 0x40400000) Control Register 0 */ + + struct { + __IO uint32_t DSS : 5; /*!< [0..4] Data size select. (DSS+1) defines the number of bits:
      • 0x00: + Reserved.
      • 0x01: Reserved.
      • 0x02: Reserved.
      • 0x03: + 4-bit data.
      • 0x04: 5-bit data.
      • ...
      • 0x1F: + 32-bit data.
      */ + uint32_t : 1; + __IO uint32_t SPO : 1; /*!< [6..6] Clock polarity.
      • 0: Steady state of clock polarity + is low.
      • 1: Steady state of clock polarity is high.
      */ + __IO uint32_t SPH : 1; /*!< [7..7] Clock phase.
      • 0: Steady state of clock phase is + low.
      • 1: Steady state of clock phase is high.
      */ + __IO uint32_t SCR : 8; /*!< [8..15] Serial Clock Rate.

      The SRC value is used to generate + the transmit and receive bit rate of the SPI. The bit rate is: + f_SPICLK / (CPSDVR * (1 + SCR)), where CPSDVR is an even value + from 2 to 254 and SCR is a value from 0 to 255.

      */ + __IO uint32_t CSS : 5; /*!< [16..20] Command Size Select (in MicroWire mode). (CSS+1) defines + the number of bits:
      • 0x00: Reserved.
      • 0x01: Reserved.
      • 0x02: Reserved.
      • 0x03: 4-bit data.
      • 0x04: 5-bit + data.
      • ...
      • 0x1F: 32-bit data.
      */ + __IO uint32_t FRF : 2; /*!< [21..22] Frame format.
      • 00b: Motorola SPI frame format.
      • 10b: + National MicroWire frame format.
      */ + __IO uint32_t SPIM : 2; /*!< [23..24] SPI transmission mode.
      • 00b: Full duplex mode.
      • 01b: + Transmit mode.
      • 10b: Receive mode.
      • 11b: Combined + mode.
      */ + uint32_t : 1; + __IO uint32_t CS1 : 1; /*!< [26..26] Chip Selection for slave one
      • 0: the slave 1 + is selected.
      • 1: the slave 1 is not selected.
      */ + } CR0_b; /*!< [27] BitSize */ + }; + + union { + __IO uint32_t CR1; /*!< (@ 0x40400004) Control Register 1 */ + + struct { + uint32_t : 1; + __IO uint32_t SSE : 1; /*!< [1..1] SPI enable.
      • 0: SPI disable.
      • 1: SPI enable.
      */ + __IO uint32_t MS : 1; /*!< [2..2] Master or slave mode select.
      • 0: Master mode.
      • 1: + Slave mode.
      */ + __IO uint32_t SOD : 1; /*!< [3..3] Slave mode output disable (slave mode only).
      • 0: + SPI can drive the MISO signal in slave mode.
      • 1: SPI + must not drive the MISO signal in slave mode.
      In multiple + slave system, it is possible for a SPI master to broadcast a + message to all slaves in the system while ensuring only one + slave drives data onto the serial output line MISO. */ + __IO uint32_t RENDN : 2; /*!< [4..5] Receive endian format.
      • 00b: The element is received + MSByte-first and MSbit-first.
      • 01b: The element is received + LSByte-first and MSbit-first.
      • 10b: The element is received + MSByte-first and LSbit-first.
      • 11b: The element is received + LSByte-first and LSbit-first.
      The cases 00b and 11b + are set for data frame size from 4 to 32 bits. The cases 01b + and 10b are set only for data frame size 16, 24 and 32 bits. */ + __IO uint32_t MWAIT : 1; /*!< [6..6] MicroWire Wait Sate Bit Enable */ + __IO uint32_t RXIFLSEL : 3; /*!< [7..9] Receive interrupt FIFO level select. This bit field selects + the trigger points to receive FIFO interrupt:
      • 000b: RX + FIFO contains 1 element or more.
      • 001b: RX FIFO contains + 4 elements or more.
      • 010b: RX FIFO contains 8 elements + or more.
      • Others: Reserved.
      */ + __IO uint32_t TXIFLSEL : 3; /*!< [10..12] Transmit interrupt FIFO level select. This bit field + selects the trigger points to transmit FIFO interrupt:
      • 000b: + TX FIFO contains 1 element or more.
      • 001b: TX FIFO contains + 4 elements or more.
      • 010b: TX FIFO contains 8 elements + or more.
      • Others: Reserved.
      */ + uint32_t : 1; + __IO uint32_t MSPIWAIT : 4; /*!< [14..17] SPI Wait mode. This value is used to insert a wait + state between frames. */ + __IO uint32_t TENDN : 2; /*!< [18..19] Transmit endian format.
      • 00b: The element is + transmitted MSByte-first and MSbit-first.
      • 01b: The element + is transmitted LSByte-first and MSbit-first.
      • 10b: The + element is transmitted MSByte-first and LSbit-first.
      • 11b: + The element is transmitted LSByte-first and LSbit-first.
      The + cases 00b and 11b are set for data frame size from 4 to 32 bits. + The cases 01b and 10b are set only for data frame size 16, 24 + and 32 bits. */ + uint32_t : 1; + __IO uint32_t DATAINDEL : 1; /*!< [21..21] Data input delay.
      • 0: No delay is inserted in + data input.
      • 1: A delay of 2 clock cycles is inserted + in the data input path.
      */ + } CR1_b; /*!< [22] BitSize */ + }; + + union { + __IO uint32_t DR; /*!< (@ 0x40400008) Data Register */ + + struct { + __IO uint32_t DATA : 32; /*!< [0..31] Transmit/Receive data:
      • Read: RX FIFO is read.
      • Write + : TX FIFO is written.
      Data must be right-justified when + a data size of less than 32-bit is programmed. Unused bits are + ignored by the transmit logic. The receive logic automatically + right-justifies data. */ + } DR_b; /*!< [32] BitSize */ + }; + + union { + __I uint8_t SR; /*!< (@ 0x4040000C) Status Register */ + + struct { + __I uint8_t TFE : 1; /*!< [0..0] Transmit FIFO empty:
      • 0: TX FIFO is not empty.
      • 1: + TX FIFO is empty.
      */ + __I uint8_t TNF : 1; /*!< [1..1] Transmit FIFO not full:
      • 0: TX FIFO is full.
      • 1: + TX FIFO is not full.
      */ + __I uint8_t RNE : 1; /*!< [2..2] Receive FIFO not empty:
      • 0: RX FIFO is empty.
      • 1: + RX FIFO is not empty.
      */ + __I uint8_t RFF : 1; /*!< [3..3] Receive FIFO full:
      • 0: RX FIFO is not full.
      • 1: + RX FIFO is full.
      */ + __I uint8_t BSY : 1; /*!< [4..4] SPI busy flag:
      • 0: SPI is idle.
      • 1: SPI + is currently transmitting and/or receiving a frame or the TX + FIFO is not empty.
      */ + } SR_b; /*!< [5] BitSize */ + }; + __I uint8_t RESERVED[3]; + + union { + __IO uint8_t CPSR; /*!< (@ 0x40400010) Clock prescale register */ + + struct { + __IO uint8_t CPSDVSR : 8; /*!< [0..7] Clock prescale divisor.It must be an even number from + 2 to 254. The value is used to generate the transmit and receive + bit rate of the SPI. The bit rate is:

      FSSPCLK / [CPSDVR x + (1+SCR)]

      where SCR is a value from 0 to 255, programmed through + the SSP_CR0 register. */ + } CPSR_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED1[3]; + + union { + __IO uint8_t IMSC; /*!< (@ 0x40400014) Interrupt mask set or clear register */ + + struct { + __IO uint8_t RORIM : 1; /*!< [0..0] Receive overrun interrupt mask:
      • 0: RX FIFO written + to while full condition interrupt is masked (irq disabled).
      • 1: + RX FIFO written to while full condition interrupt is not masked + (irq enabled).
      */ + __IO uint8_t RTIM : 1; /*!< [1..1] Receive timeout interrupt mask:
      • 0: RX FIFO not + empty or no read prior to the timeout period interrupt is masked + (irq disabled).
      • 1: RX FIFO not empty or no read prior + to the timeout period interrupt is not masked (irq enabled).
      */ + __IO uint8_t RXIM : 1; /*!< [2..2] Receive FIFO interrupt mask:
      • 0: Receive interrupt + is masked (irq disabled).
      • 1: Receive interrupt is not + masked (irq enabled).
      */ + __IO uint8_t TXIM : 1; /*!< [3..3] Transmit FIFO interrupt mask:
      • 0: Transmit interrupt + is masked (irq disabled).
      • 1: Transmit interrupt is not + masked (irq enabled).
      */ + __IO uint8_t TURIM : 1; /*!< [4..4] Transmit underrun interrupt mask:
      • 0: Transmit + underrun interrupt is masked (irq disabled).
      • 1: Transmit + underrun interrupt is not masked (irq enabled).
      */ + __IO uint8_t TEIM : 1; /*!< [5..5] Transmit FIFO empty interrupt mask:
      • 0: TX FIFO + empty interrupt is masked (irq disabled).
      • 1: TX FIFO + empty interrupt is not masked (irq enabled).
      */ + } IMSC_b; /*!< [6] BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __I uint8_t RIS; /*!< (@ 0x40400018) Raw interrupt status register */ + + struct { + __I uint8_t RORRIS : 1; /*!< [0..0] Receive overrun raw interrupt status */ + __I uint8_t RTRIS : 1; /*!< [1..1] Receive time out raw interrupt status */ + __I uint8_t RXRIS : 1; /*!< [2..2] Receive raw interrupt status */ + __I uint8_t TXRIS : 1; /*!< [3..3] Transmit raw interrupt status */ + __I uint8_t TURRIS : 1; /*!< [4..4] Transmit underrun raw interrupt Status */ + __I uint8_t TERIS : 1; /*!< [5..5] Transmit FIFO Empty Raw Interrupt Status */ + } RIS_b; /*!< [6] BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __I uint8_t MIS; /*!< (@ 0x4040001C) Masked Interrupt Status Register */ + + struct { + __I uint8_t RORMIS : 1; /*!< [0..0] Receive Overrun Masked Interrupt Status: gives the interrupt + status after masking of the receive overrun interrupt. */ + __I uint8_t RTMIS : 1; /*!< [1..1] Receive Time Out Masked Interrupt Status: gives the interrupt + status after masking of receive timeout interrupt. */ + __I uint8_t RXMIS : 1; /*!< [2..2] Receive Masked Interrupt Status: gives the interrupt + status after masking of the receive interrupt. */ + __I uint8_t TXMIS : 1; /*!< [3..3] Transmit Masked Interrupt Status: gives the interrupt + status after masking of the transmit interrupt. */ + __I uint8_t TURMIS : 1; /*!< [4..4] Transmit Underrun Masked Interrupt Status: gives the + interrupt status after masking of the transmit underrun interrupt. */ + __I uint8_t TEMIS : 1; /*!< [5..5] Transmit FIFO Empty Masked Interrupt Status: gives the + interrupt status after masking of the transmit FIFO empty interrupt. */ + } MIS_b; /*!< [6] BitSize */ + }; + __I uint8_t RESERVED4[3]; + + union { + __O uint8_t ICR; /*!< (@ 0x40400020) Interrupt clear register */ + + struct { + __O uint8_t RORIC : 1; /*!< [0..0] Receive Overrun Clear Interrupt: writing 1 clears the + receive overrun interrupt. */ + __O uint8_t RTIC : 1; /*!< [1..1] Receive Time Out Clear Interrupt: writing 1 clears the + receive timeout interrupt. */ + __O uint8_t TURIC : 1; /*!< [2..2] Transmit Underrun Clear Interrupt: writing 1 clears the + transmit overrun interrupt. */ + } ICR_b; /*!< [3] BitSize */ + }; + __I uint8_t RESERVED5[3]; + + union { + __IO uint8_t DMACR; /*!< (@ 0x40400024) SPI DMA control register */ + + struct { + __IO uint8_t RXDMASE : 1; /*!< [0..0] Single receive DMA request.
      • 0: Single transfer + DMA in receive disable.
      • 1: Single transfer DMA in receive + enable.
      */ + uint8_t : 1; + __IO uint8_t TXDMASE : 1; /*!< [2..2] Signle transmit DMA request.
      • 0: Single transfer + DMA in transmit disable.
      • 1: Single transfer DMA in transmit + enable.
      */ + } DMACR_b; /*!< [3] BitSize */ + }; + __I uint8_t RESERVED6[3]; + __IO uint16_t RXFRM; /*!< (@ 0x40400028) SPI Receive Frame register. Indicates the number + of frames to receive from the slave. */ + __I uint16_t RESERVED7; + __IO uint32_t CHN; /*!< (@ 0x4040002C) Dummy character register */ + __IO uint16_t WDTXF; /*!< (@ 0x40400030) SPI transmit FIFO receive frame number. Indicates + the number of frames to receive from the transmit FIFO. */ + __I uint16_t RESERVED8[39]; + + union { + __IO uint8_t ITCR; /*!< (@ 0x40400080) Integration test control register */ + + struct { + uint8_t : 1; + __IO uint8_t SWAPFIFO : 1; /*!< [1..1] FIFO control mode:
      • 0: FIFO normal mode. Write + in TDR register puts data in TX FIFO and read from TDR register + read data from RX FIFO.
      • 1: FIFO swapped mode. Write + in TDR register puts data in RX FIFO and read from TDR register + read data from TX FIFO.
      */ + } ITCR_b; /*!< [2] BitSize */ + }; + __I uint8_t RESERVED9[11]; + __IO uint32_t TDR; /*!< (@ 0x4040008C) FIFO Test Data Register */ +} SPI_Type; + + +/* ================================================================================ */ +/* ================ WDG ================ */ +/* ================================================================================ */ + + +/** + * @brief Watchdog (WDG) + */ + +typedef struct { /*!< (@ 0x40700000) WDG Structure */ + + union { + __IO uint32_t LR; /*!< (@ 0x40700000) Watchdog Load Register */ + + struct { + __IO uint32_t LOAD : 32; /*!< [0..31] Watchdog load value. Value from which the counter is + to decrement. When this register is written to, the count is + immediately restarted from the new value. */ + } LR_b; /*!< [32] BitSize */ + }; + + union { + __I uint32_t VAL; /*!< (@ 0x40700004) Watchdog Value Register */ + + struct { + __I uint32_t WDTVAL : 32; /*!< [0..31] Watchdog load value. When read, returns the current + value of the decrementing watchdog counter. A write has no effect. */ + } VAL_b; /*!< [32] BitSize */ + }; + + union { + __IO uint8_t CR; /*!< (@ 0x40700008) Watchdog Control Register */ + + struct { + __IO uint8_t INTEN : 1; /*!< [0..0] Watchdog interrupt enable. Enable the interrupt event:
      • 0: + watchdog interrupt is disabled.
      • 1: watchdog interrupt + is enabled.
      */ + __IO uint8_t RESEN : 1; /*!< [1..1] Watchdog reset enable. Enable the watchdog reset output:
      • 0: + watchdog reset is disabled.
      • 1: watchdog reset is enabled.
      */ + } CR_b; /*!< [2] BitSize */ + }; + __I uint8_t RESERVED[3]; + + union { + __IO uint32_t ICR; /*!< (@ 0x4070000C) Watchdog Interrupt Clear Register */ + + struct { + __IO uint32_t WDTICLR : 32; /*!< [0..31] Watchdog interrupt enable:
      • Writing any value + will clear the watchdog interrupt and reloads the counter from + the LR register.
      • A read returns zero.
      */ + } ICR_b; /*!< [32] BitSize */ + }; + + union { + __I uint8_t RIS; /*!< (@ 0x40700010) Watchdog Raw Interrupt Status Register */ + + struct { + __I uint8_t RIS : 1; /*!< [0..0] Watchdog raw interrupt status bit. Reflects the status + of the interrupt status from the watchdog:
      • 0: watchdog + interrupt is not active.
      • 1: watchdog interrupt is active.
      Read-only bit. A write has no effect. */ + } RIS_b; /*!< [1] BitSize */ + }; + __I uint8_t RESERVED1[3]; + + union { + __I uint8_t MIS; /*!< (@ 0x40700014) Watchdog Masked Interrupt Status Register */ + + struct { + __I uint8_t MIS : 1; /*!< [0..0] Watchdog masked interrupt status bit. Masked value of + watchdog interrupt status:
      • 0: watchdog interrupt is not + active.
      • 1: watchdog interrupt is active.
      Read-only + bit. A write has no effect. */ + } MIS_b; /*!< [1] BitSize */ + }; + __I uint8_t RESERVED2[3051]; + + union { + __IO uint32_t LOCK; /*!< (@ 0x40700C00) Watchdog Lock Register */ + + struct { + __IO uint32_t LOCKVAL : 32; /*!< [0..31] Watchdog lock value. When read, returns the lock status:
      • 0: + Write access to all watchdog other registers is enabled.
      • 1: + Write access to all watchdog other registers is disabled.
      When + written, allows enabling or disabling write access to all other + watchdog registers:
      • Writing 0x1ACCE551: Write access + to all other registers is enabled.
      • Writing any other + value: Write access to all other registers is disabled.
      */ + } LOCK_b; /*!< [32] BitSize */ + }; +} WDG_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + + +/** + * @brief ADC (ADC) + */ + +typedef struct { /*!< (@ 0x40800000) ADC Structure */ + + union { + __IO uint16_t CTRL; /*!< (@ 0x40800000) ADC control register */ + + struct { + __IO uint16_t ON : 1; /*!< [0..0] Starts ADC analog subsystem. This bit must be set before + starting a conversion.
      • 0: ADC is OFF.
      • 1: ADC + is ON.
      This bit works for all the mode except the microphone + mode. */ + __IO uint16_t CALEN : 1; /*!< [1..1] The automatic calibration routine is enabled if both + AUTO_OFFSET and CALEN bitfields are set. The result of the calibration + is placed in the OFFSET register according to the SKIP bitfield + value.
      • 0: disable the automatic calibration.
      • 1: + enable the automatic calibration.
      This bitfield can + be set to 0 only by setting to 1 the bitfield RSTCALEN. */ + __IO uint16_t SWSTART : 1; /*!< [2..2] Starts the ADC conversion phase when set. This bit works + for all the mode except the microphone mode. */ + __IO uint16_t RESET : 1; /*!< [3..3] Reset all the ADC APB registers when set (CTRL, CONF, + DATA_CONV_THRESHOLD_HI, THRESHOLD_LO). */ + __IO uint16_t STOP : 1; /*!< [4..4] Permits to stop the continuous conversion. 1: stop the + continuous conversion and switch off the ADC. The bitfields + SWSTART, ON, DMA_EN and MIC_ON are auto-cleared if set. This + bit is auto-cleared by the hardware so it is always read at + 0. */ + __IO uint16_t ENAB_COMP : 1; /*!< [5..5] Enables the window comparator when set to 1. WDOG flag + is ADC_SR register is set if the converted value is between + ADCTHRESHOLD_HI and ADCTHRESHOLD_LO value. */ + __IO uint16_t RSTCALEN : 1; /*!< [6..6] Disable the calibration phase when set to 1. This bit + has to be set to disable the calibration each time calibration + is enabled. */ + __IO uint16_t AUTO_OFFSET: 1; /*!< [7..7] The automatic calibration routine is enabled if both + AUTO_OFFSET and CALEN bitfields are set. The result of the calibration + is placed in the OFFSET register according to the SKIP bitfield + value.
      • 0: disable the automatic calibration.
      • 1: + enable the automatic calibration.
      This bitfield can + be set to 0 only by setting to 1 the bitfield RSTCALEN. */ + __IO uint16_t MIC_ON : 1; /*!< [8..8] Starts ADC analog subsystem only for microphone mode.
      • 0: + ADC is OFF.
      • 1: ADC is ON.
      */ + __IO uint16_t DMA_EN : 1; /*!< [9..9] Enables the DMA.
      • 0: DMA is disabled.
      • 1: + DMA is enabled.
      */ + } CTRL_b; /*!< [10] BitSize */ + }; + __I uint16_t RESERVED; + + union { + __IO uint32_t CONF; /*!< (@ 0x40800004) ADC configuration register */ + + struct { + uint32_t : 1; + __IO uint32_t CHSEL : 3; /*!< [1..3] Select the input channel:
      • 000b: All switches open.
      • 0 + 01b: Single ended through ADC2 pin. InP=VREF (internal), InN=ADC2 + pin.
      • 010b: Single ended through ADC1 pin. InP=ADC1 pin, + InN=VREF (internal).
      • 011b: Differential ADC1 pin - ADC2 + pin, InP=ADC1 pin, InN=ADC2 pin.
      • 101b: Battery level + detector. InP=0.6V (internal), InN=VBATSENS.
      • 110b: Short + InN=InP=0.6V (internal).
      */ + __IO uint32_t REFSEL : 2; /*!< [4..5] Set the VREF for single ended conversion:
      • 00b: + 0.0V.
      • 10b: 0.6V.
      */ + __IO uint32_t OSR : 2; /*!< [6..7] Set the ADC resolution:
      • 00b: Set the oversampling + ratio to 200.
      • 01b: Set the oversampling ratio to 100.
      • 10b: + Set the oversampling ratio to 64.
      • 11b: Set the oversampling + ratio to 32.
      */ + __IO uint32_t PGASEL : 2; /*!< [8..9] Set the input attenuator value:
      • 000b: Input attenuator + at 0 dB.
      • 001b: Input attenuator at 6.02 dB.
      • 010b: + Input attenuator at 9.54 dB.
      */ + uint32_t : 1; + __IO uint32_t CONT : 1; /*!< [11..11] Enable the continuous conversion mode:
      • 0: Single + conversion.
      • 1: Continuous conversion.
      */ + uint32_t : 6; + __IO uint32_t SKIP : 1; /*!< [18..18] It permits to bypass the filter COMP to speed up the + conversion for signal at low frequency:
      • 0: Filter not + bypassed.
      • 1: Filter bypassed.
      According to + the value of this bitfield, the behaviour of the ADC changes + as follows: if SKIP is 0: the first 10 converted samples in + ADC mode continuous should be discarded by the user (3 if SKIP + is 1). The converted date are in DATA_CONV_MSB (DATA_CONV_LSB + if SKIP is 1). The calibration result is in OFFSET_MSB (OFFSET_LSB + if SKIP is 1). */ + uint32_t : 1; + __IO uint32_t DIG_FILT_CLK: 1; /*!< [20..20] Frequency clock selection value on GPIO0 when MIC_SEL=1:
      • 0 + : 0.8 MHz.
      • 1: 1.6 MHz.
      */ + uint32_t : 1; + __IO uint32_t MIC_SEL : 1; /*!< [22..22] Provides the clock on GPIO:
      • 0: Do not provided + any external clock source.
      • 1: Provide clock source from + GPIO.
      */ + } CONF_b; /*!< [23] BitSize */ + }; + + union { + __I uint8_t IRQSTAT; /*!< (@ 0x40800008) IRQ masked status register */ + + struct { + __I uint8_t ENDCAL : 1; /*!< [0..0] 1: when the calibration is completed. Clear on register + read. */ + uint8_t : 1; + __I uint8_t EOC : 1; /*!< [2..2] 1: when the conversion is completed. Clear on register + read. */ + __I uint8_t WDOG : 1; /*!< [3..3] 1: when the data is within the thresholds. Clear on register + read. */ + } IRQSTAT_b; /*!< [4] BitSize */ + }; + __I uint8_t RESERVED1[3]; + + union { + __IO uint8_t IRQMASK; /*!< (@ 0x4080000C) It sets the mask for ADC interrupt */ + + struct { + __IO uint8_t ENDCAL : 1; /*!< [0..0] Interrupt mask for the end of calibration event:
      • 0: + Interrupt is enabled.
      • 1: Interrupt is disabled.
      */ + uint8_t : 1; + __IO uint8_t EOC : 1; /*!< [2..2] Interrupt mask for the end of conversion event:
      • 0: + Interrupt is enabled.
      • 1: Interrupt is disabled.
      */ + __IO uint8_t WDOG : 1; /*!< [3..3] Interrupt mask for the within the threhsold event:
      • 0: + Interrupt is enabled.
      • 1: Interrupt is disabled.
      */ + } IRQMASK_b; /*!< [4] BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __I uint8_t IRQRAW; /*!< (@ 0x40800010) IRQ status raw register */ + + struct { + __I uint8_t ENDCAL : 1; /*!< [0..0] 1: when the calibration is completed. Clear on register + read. */ + uint8_t : 1; + __I uint8_t EOC : 1; /*!< [2..2] 1: when the conversion is completed. Clear on register + read. */ + __I uint8_t WDOG : 1; /*!< [3..3] 1: when the data is inside the thresholds. Clear on register + read. */ + } IRQRAW_b; /*!< [4] BitSize */ + }; + __I uint8_t RESERVED3[3]; + __I uint16_t DATA_CONV_LSB; /*!< (@ 0x40800014) Result of the conversion LSB in two complement + format. If the filter is bypassed, the bitfield SKIP is 1, the + DATA_CONV_MSB is negligible and the ADC converted data is the + DATA_CONV_LSB * 1.08 (corrective factor). If the filter is not + bypassed, the bitfield SKIP is 0, the DATA_CONV_LSB is negligeble. */ + __I uint16_t DATA_CONV_MSB; /*!< (@ 0x40800016) Result of the conversion MSB in two complement + format. If the filter is not bypassed, the bitfield SKIP is + 0, the DATA_CONV_LSB is negligible and the ADC converted data + is the DATA_CONV_MSB. If the filter is bypassed, the bitfield + SKIP is 1, the DATA_CONV_MSB is negligeble. */ + __IO uint16_t OFFSET_LSB; /*!< (@ 0x40800018) Offset for correction of converted data. If the + bitfield SKIP is 0, the 16-bit offset is in OFFSET_MSB, while + if the bitfield SKIP is 1, the 16-bit offset is in OFFSET_LSB. */ + __IO uint16_t OFFSET_MSB; /*!< (@ 0x4080001A) Offset for correction of converted data. If the + bitfield SKIP is 0, the 16-bit offset is in OFFSET_MSB, while + if the bitfield SKIP is 1, the 16-bit offset is in OFFSET_LSB. */ + __I uint32_t RESERVED4; + + union { + __IO uint8_t SR_REG; /*!< (@ 0x40800020) ADC status register */ + + struct { + uint8_t : 1; + __IO uint8_t BUSY : 1; /*!< [1..1] 1: during conversion. */ + uint8_t : 1; + __IO uint8_t WDOG : 1; /*!< [3..3] If ENAB_COMP=1, this bit indicates the result of the + conversion is between high and low threshold:
      • 0: DATAOUT[31:0] + is NOT between THRESHOLD_HI and THRESHOLD_LO values.
      • 1: + DATAOUT[31:0] is between THRESHOLD_HI and THRESHOLD_LO values.
      */ + } SR_REG_b; /*!< [4] BitSize */ + }; + __I uint8_t RESERVED5[3]; + __IO uint32_t THRESHOLD_HI; /*!< (@ 0x40800024) High threshold for window comparator */ + __IO uint32_t THRESHOLD_LO; /*!< (@ 0x40800028) Low threshold for window comparator */ +} ADC_Type; + + +/* ================================================================================ */ +/* ================ CKGEN_SOC ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock Gen SOC (CKGEN_SOC) + */ + +typedef struct { /*!< (@ 0x40900000) CKGEN_SOC Structure */ + __I uint32_t RESERVED[2]; + + union { + __I uint8_t REASON_RST; /*!< (@ 0x40900008) Indicates the reset reason from Cortex-M0 */ + + struct { + uint8_t : 1; + __I uint8_t SYSREQ : 1; /*!< [1..1] Reset caused by Cortex-M0 debug asserting SYSRESETREQ */ + __I uint8_t WDG : 1; /*!< [2..2] Reset caused by assertion of watchdog reset */ + __I uint8_t LOCKUP : 1; /*!< [3..3] Reset caused by Cortex-M0 asserting LOCKUP signal */ + } REASON_RST_b; /*!< [4] BitSize */ + }; + __I uint8_t RESERVED1[19]; + + union { + __I uint32_t DIE_ID; /*!< (@ 0x4090001C) Identification information of the device */ + + struct { + __I uint32_t REV : 4; /*!< [0..3] Cut revision */ + __I uint32_t VERSION : 4; /*!< [4..7] Cut version */ + __I uint32_t PRODUCT : 4; /*!< [8..11] Product */ + } DIE_ID_b; /*!< [12] BitSize */ + }; + + union { + __IO uint32_t CLOCK_EN; /*!< (@ 0x40900020) Enable or gates the APB clock of the peripherals */ + + struct { + __IO uint32_t GPIO : 1; /*!< [0..0] GPIO clock */ + __IO uint32_t NVM : 1; /*!< [1..1] Flash controller clock */ + __IO uint32_t SYSCTRL : 1; /*!< [2..2] System controller clock */ + __IO uint32_t UART : 1; /*!< [3..3] UART clock */ + __IO uint32_t SPI : 1; /*!< [4..4] SPI clock */ + uint32_t : 2; + __IO uint32_t WDOG : 1; /*!< [7..7] Watchdog clock */ + __IO uint32_t ADC : 1; /*!< [8..8] ADC clock */ + __IO uint32_t I2C1 : 1; /*!< [9..9] I2C1 clock */ + __IO uint32_t I2C2 : 1; /*!< [10..10] I2C2 clock */ + __IO uint32_t MFT1 : 1; /*!< [11..11] MFT1 clock */ + __IO uint32_t MFT2 : 1; /*!< [12..12] MFT2 clock */ + __IO uint32_t RTC : 1; /*!< [13..13] RTC clock */ + uint32_t : 2; + __IO uint32_t DMA : 1; /*!< [16..16] DMA AHB clock */ + __IO uint32_t RNG : 1; /*!< [17..17] RNG AHB clock */ + __IO uint32_t PKA : 2; /*!< [18..19] PKA AHB clock and RAM */ + } CLOCK_EN_b; /*!< [20] BitSize */ + }; + + union { + __IO uint8_t DMA_CONFIG; /*!< (@ 0x40900024) DMA config */ + + struct { + __IO uint8_t ADC_CH0 : 1; /*!< [0..0] Select ADC on DMA channel 0 instead of peripheral */ + __IO uint8_t ADC_CH1 : 1; /*!< [1..1] Select ADC on DMA channel 1 instead of peripheral */ + __IO uint8_t ADC_CH2 : 1; /*!< [2..2] Select ADC on DMA channel 2 instead of peripheral */ + __IO uint8_t ADC_CH3 : 1; /*!< [3..3] Select ADC on DMA channel 3 instead of peripheral */ + __IO uint8_t ADC_CH4 : 1; /*!< [4..4] Select ADC on DMA channel 4 instead of peripheral */ + __IO uint8_t ADC_CH5 : 1; /*!< [5..5] Select ADC on DMA channel 5 instead of peripheral */ + __IO uint8_t ADC_CH6 : 1; /*!< [6..6] Select ADC on DMA channel 6 instead of peripheral */ + __IO uint8_t ADC_CH7 : 1; /*!< [7..7] Select ADC on DMA channel 7 instead of peripheral */ + } DMA_CONFIG_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __I uint32_t JTAG_IDCODE; /*!< (@ 0x40900028) JTAG ID code */ + + struct { + uint32_t : 1; + __I uint32_t MANUF_ID : 11; /*!< [1..11] Manufacturer ID */ + __I uint32_t PART_NUMBER: 16; /*!< [12..27] Part number */ + __I uint32_t VERSION_NUM: 4; /*!< [28..31] Version */ + } JTAG_IDCODE_b; /*!< [32] BitSize */ + }; +} CKGEN_SOC_Type; + + +/* ================================================================================ */ +/* ================ I2C [I2C2] ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C2 (I2C) + */ + +typedef struct { /*!< (@ 0x40A00000) I2C Structure */ + + union { + __IO uint32_t CR; /*!< (@ 0x40A00000) I2C Control register */ + + struct { + __IO uint32_t PE : 1; /*!< [0..0] I2C enable disable:
      • 0: I2C disable.
      • 1: + I2C enable.
      This bit when deasserted works as software + reset for I2C peripheral. */ + __IO uint32_t OM : 2; /*!< [1..2] Select the operating mode:
      • 00b: Slave mode. The + peripheral can only respond (transmit/receive) when addressed + by a master device
      • 01b: Master mode. The peripheral + works in a multi-master system where itself cannot be addressed + by another master device. It can only initiate a new transfer + as master device.
      • 10b: Master/slave mode. The peripheral + works in a multi-master system where itself can be addressed + by another master device, besides to initiate a transfer as + master device.
      • 0: 7-bit addressing mode.
      • 1: 10-bit addressing + mode.
      */ + __IO uint32_t SM : 2; /*!< [4..5] Speed mode. SM defines the speed mode related to the + serial bit rate:
      • 0: Standard mode (up to 100 K/s).
      • 1: + Fast mode (up to 400 K/s).
      */ + __IO uint32_t SGCM : 1; /*!< [6..6] Slave general call mode defines the operating mode of + the slave controller when a general call is received. This setting + does not affect the hardware general call that is always managed + in transparent mode.
      • 0: transparent mode, the slave receiver + recognizes the general call but any action is taken by the hardware + after the decoding of the message included in the Rx FIFO.
      • 1: + direct mode, the slave receiver recognizes the general call + and executes directly (without software intervention) the r */ + __IO uint32_t FTX : 1; /*!< [7..7] FTX flushes the transmit circuitry (FIFO, fsm). The configuration + of the I2C node (register setting) is not affected by the flushing + operation. The flushing operation is performed on modules working + on different clock domains (system and I2C clocks) and needs + several system clock cycles before being completed. Upon completion, + the I2C node (internal logic) clears this bit. The application + must not access the Tx FIFO during the flushing operation and + should poll on this bit waiting for completion.
        • 0: */ + __IO uint32_t FRX : 1; /*!< [8..8] FRX flushes the receive circuitry (FIFO, fsm).The configuration + of the I2C node (register setting) is not affected by the flushing + operation. The flushing operation is performed on modules working + on different clock domains (system and I2C clocks) and needs + several system clock cycles before to be completed. Upon completion, + the I2C node (internal logic) clears this bit. The application + must not access the Rx FIFO during the flushing operation and + should poll on this bit waiting for the completion.
          • */ + __IO uint32_t DMA_TX_EN : 1; /*!< [9..9] Enables the DMA TX interface.
            • 0: Idle state, the + DMA TX interface is disabled.
            • 1: Run state, the DMA + TX interface is enabled.
            On the completion of the DMA + transfer, the DMA TX interface is automatically turned off clearing + this bit when the end of transfer signal coming from the DMA + is raised. DMA_TX_EN and DMA_RX_EN must not enabled at the same + time. */ + __IO uint32_t DMA_RX_EN : 1; /*!< [10..10] Enables the DMA RX interface.
            • 0: Idle state, + the DMA RX interface is disabled.
            • 1: Run state, the + DMA RX interface is enabled.
            On the completion of the + DMA transfer, the DMA RX interface is automatically turned off + clearing this bit when the end of transfer signal coming from + the DMA is raised. DMA_TX_EN and DMA_RX_EN must not enabled + at the same time. */ + uint32_t : 2; + __IO uint32_t FON : 2; /*!< [13..14] Filtering on sets the digital filters on the SDA, SCL + line, according to the I2C bus requirements, when standard open-drain + pads are used:
            • 00b: No digital filters are inserted.
            • 01b: + Digital filters (filter 1 ck wide spikes) are inserted.
            • 10b: + Digital filters (filter 2 ck wide spikes) are inserted.
            • 11b: + Digital filters (filter 4 ck wide spikes) are inserted.
            */ + __IO uint32_t FS_1 : 1; /*!< [15..15] Force stop enable bit. When set to 1b, the STOP condition + is generated.
            • 0: Force stop disabled.
            • 1: Enable + force stop.
            */ + } CR_b; /*!< [16] BitSize */ + }; + + union { + __IO uint32_t SCR; /*!< (@ 0x40A00004) I2C Slave Control register */ + + struct { + __IO uint32_t SA7 : 7; /*!< [0..6] Slave address 7-bit. SA7 includes the slave address 7-bit + or the LSB bits of the slave address 10-bit */ + __IO uint32_t ESA10 : 3; /*!< [7..9] Extended slave address 10-bit. ESA10 includes the extension + (MSB bits) to the SA7 register field in case of slave addressing + mode set to 10-bit */ + uint32_t : 6; + __IO uint32_t SLSU : 16; /*!< [16..31] Slave data setup time. SLSU defines the data setup + time after SCL clock stretching in terms of i2c_clk cycles. + Data setup time is actually equal to SLSU-1 clock cycles. The + typical values for i2c_clk of 16 MHz are SLSU = 5 in standard + mode and SLSU = 3 in fast modes. */ + } SCR_b; /*!< [32] BitSize */ + }; + __I uint32_t RESERVED; + + union { + __IO uint32_t MCR; /*!< (@ 0x40A0000C) I2C master control register */ + + struct { + __IO uint32_t OP : 1; /*!< [0..0] Operation
            • 0: Indicates a master write operation.
            • 1: + Indicates a master read operation.
            */ + __IO uint32_t A7 : 7; /*!< [1..7] Address. Includes the 7-bit address or the LSB bits of + the10-bit address used to initiate the current transaction */ + __IO uint32_t EA10 : 3; /*!< [8..10] Extended address. Includes the extension (MSB bits) + of the field A7 used to initiate the current transaction */ + __IO uint32_t SB : 1; /*!< [11..11] Start byte:
            • 0: The start byte procedure is not + applied to the current transaction.
            • 1: The start byte + procedure is prefixed to the current transaction.
            */ + __IO uint32_t AM : 2; /*!< [12..13] Address type:
            • 00b: The transaction is initiated + by a general call command. In this case the fields OP, A7, EA10 + are "don't care".
            • 01b: The transaction is initiated + by the 7-bit address included in the A7 field.
            • 10b: + The transaction is initiated by the 10-bit address included + in the EA10 and A7 fields.
            */ + __IO uint32_t P : 1; /*!< [14..14] Stop condition:
            • 0: The current transaction is + not terminated by a STOP condition. A repeated START condition + is generated on the next operation which is required to avoid + to stall the I2C line.
            • 1: The current transaction is + terminated by a STOP condition.
            */ + __IO uint32_t LENGTH : 11; /*!< [15..25] Transaction length. Defines the length, in terms of + the number of bytes to be transmitted (MW) or received (MR). + In case of write operation, the payload is stored in the Tx + FIFO. A transaction can be larger than the Tx FIFO size. In + case of read operation the length refers to the number of bytes + to be received before generating a not-acknowledge response. + A transaction can be larger than the Rx FIFO size. The I2C clock + line is stretched low until the data in Rx FIFO are consumed. */ + } MCR_b; /*!< [26] BitSize */ + }; + + union { + __IO uint8_t TFR; /*!< (@ 0x40A00010) I2C transmit FIFO register */ + + struct { + __IO uint8_t TDATA : 8; /*!< [0..7] Transmission Data. TDATA contains the payload related + to a master write or read-from-slave operation to be written + in the Tx FIFO. TDATA(0) is the first LSB bit transmitted over + the I2C line.

            In case of master write operation, the Tx FIFO + shall be preloaded otherwise the I2C controller cannot start + the operation until data are available.

            In case of read-from-slave + operation, when the slave is addressed, the interrupt RISR:RFSR + bit is asserted and the CPU shall download the data in the FIFO. + If the */ + } TFR_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED1[3]; + + union { + __I uint32_t SR; /*!< (@ 0x40A00014) I2C status register */ + + struct { + __I uint32_t OP : 2; /*!< [0..1] Operation:

            • 00b: MW: master write operation.
            • 01b: + MR: master read operation.
            • 10b: WTS: write-to-slave + operation.
            • 11b: RFS: read-from-slave operation.
            */ + __I uint32_t STATUS : 2; /*!< [2..3] Controller status. Valid for the operations MW, MR, WTS + RFS:
            • 00b: NOP: No operation is in progress.
            • 01b: + ON_GOING: An operation is ongoing.
            • 10b: OK: The operation + (OP field) has been completed successfully.
            • 11b: ABORT: + The operation (OP field) has been aborted due to the occurrence + of the event described in the CAUSE field.
            */ + __I uint32_t CAUSE : 3; /*!< [4..6] Abort cause. This field is valid only when the STATUS + field contains the ABORT tag. Others: RESERVED.
            • 000b: + NACK_ADDR: The master receives a not-acknowledge after the transmission + of the address. Valid for the operation MW, MR.
            • 001b: + NACK_DATA: The master receives a not-acknowledge during the + data phase of a MW operation. Valid for the operation MW.
            • 011b: + ARB_LOST: The master loses the arbitration during a MW or MR + operation. Valid for the operation MW, MR.
            • 100b: BERR_START: */ + __I uint32_t TYPE : 2; /*!< [7..8] Receive type. Valid only for the operation WTS:
              • 00b: + FRAME: The slave has received a normal frame.
              • 01b: GCALL: + The slave has received a general call. If the it I2C_CR:SGCM + is set to 1, the general call is directly executed without software + intervention and only the control code word is reported in FIFO + (LENGTH =0).
              • 10b: HW_GCALL: The slave has received a + hardware general call.
              */ + __I uint32_t LENGTH : 10; /*!< [9..18] Transfer length. For an MR, WTS operation the LENGTH + field defines the actual size of the subsequent payload, in + terms of number of bytes. For an MW, RFS operation the LENGTH + field defines the actual number of bytes transferred by the + master/slave device. For a WTS operation if the transfer length + exceeds 2047 bytes, the operation is stopped by the slave returning + a NACK handshake and the flag OVFL is set. For an RFS operation + if the transfer length exceeds 2047 bytes, the operation continues + normally but */ + uint32_t : 10; + __I uint32_t DUALF : 1; /*!< [29..29] Dual flag (slave mode):
              • 0: Received address + matched with slave address (SA7).
              • 1: Received address + matched with dual slave address (DSA7).
              Cleared by + hardware after a Stop condition or repeated Start condition, + bus error or when PE=0. */ + } SR_b; /*!< [30] BitSize */ + }; + + union { + __I uint8_t RFR; /*!< (@ 0x40A00018) I2C receive FIFO register */ + + struct { + __I uint8_t RDATA : 8; /*!< [0..7] Receive data. RDATA contains the received payload, related + to a master read or write-to-slave operation, to be read from + the Rx FIFO. The RDATA(0) is the first LSB bit received over + the I2C line. In case the FIFO is full, the I2C controller stretches + automatically the I2C clock line until a new entry is available.

              For + a write-to-slave operation, when the slave is addressed, the + interrupt I2C_RISR:WTSR bit is asserted for notification to + the CPU. In CPU mode the FIFO management shall be based on the + asser */ + } RFR_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __IO uint16_t TFTR; /*!< (@ 0x40A0001C) I2C transmit FIFO threshold register */ + + struct { + __IO uint16_t THRESH_TX : 10; /*!< [0..9] Threshold TX, contains the threshold value, in terms + of number of bytes, of the Tx FIFO.

              When the number of entries + of the Tx FIFO is less or equal than the threshold value, the + interrupt bit I2C_RISR:TXFNE is set in order to request the + loading of data to the application.

              */ + } TFTR_b; /*!< [10] BitSize */ + }; + __I uint16_t RESERVED3; + + union { + __IO uint16_t RFTR; /*!< (@ 0x40A00020) I2C receive FIFO threshold register */ + + struct { + __IO uint16_t THRESH_RX : 10; /*!< [0..9] Threshold RX, contains the threshold value, in terms + of number of bytes, of the Rx FIFO.

              When the number of entries + of the RX FIFO is greater than or equal to the threshold value, + the interrupt bit RISR:RXFNF is set in order to request the + download of received data to the application. The application + shall download the received data based on the threshold. (RISR:RXFNF).

              */ + } RFTR_b; /*!< [10] BitSize */ + }; + __I uint16_t RESERVED4; + + union { + __IO uint16_t DMAR; /*!< (@ 0x40A00024) I2C DMA register */ + + struct { + uint16_t : 8; + __IO uint16_t DBSIZE_TX : 3; /*!< [8..10] Destination burst size. This register field is valid + only if the BURST_TX bit is set to '1'. If burst size is smaller + than the transaction length, only single request are generated. */ + __IO uint16_t BURST_TX : 1; /*!< [11..11] Defines the type of DMA request generated by the DMA + TX interface.
              • 0: Single request mode. Transfers a single + data (one byte) in the TX FIFO.
              • 1: Burst request mode. + Transfers a programmed burst of data according to DBSIZE_TX + field.
              When the burst mode is programmed, the DMA transfer + can be completed by one or more single requests as required. */ + } DMAR_b; /*!< [12] BitSize */ + }; + __I uint16_t RESERVED5; + + union { + __IO uint16_t BRCR; /*!< (@ 0x40A00028) I2C Baud-rate counter register */ + + struct { + __IO uint16_t BRCNT : 16; /*!< [0..15] Baud rate counter. BRCNT defines the counter value used + to set up the I2C baud rate in standard and fast mode, when + the peripheral is operating in master mode. */ + } BRCR_b; /*!< [16] BitSize */ + }; + __I uint16_t RESERVED6; + + union { + __IO uint32_t IMSCR; /*!< (@ 0x40A0002C) I2C interrupt mask set/clear register */ + + struct { + __IO uint32_t TXFEM : 1; /*!< [0..0] TX FIFO empty mask. TXFEM enables the interrupt bit TXFE:
              • 0: + TXFE interrupt is disabled.
              • 1: TXFE interrupt is enabled.
              */ + __IO uint32_t TXFNEM : 1; /*!< [1..1] TX FIFO nearly empty mask. TXFNEM enables the interrupt + bit TXFNE:
              • 0: TXFNE interrupt is disabled.
              • 1: + TXFNE interrupt is enabled.
              */ + __IO uint32_t TXFFM : 1; /*!< [2..2] TX FIFO full mask. TXFFM enables the interrupt bit TXFF:
              • 0: + TXFF interrupt is disabled.
              • 1: TXFF interrupt is enabled.
              */ + __IO uint32_t TXFOVRM : 1; /*!< [3..3] TX FIFO overrun mask. TXOVRM enables the interrupt bit + TXOVR:
              • 0: TXOVR interrupt is disabled.
              • 1: TXOVR + interrupt is enabled.
              */ + __IO uint32_t RXFEM : 1; /*!< [4..4] RX FIFO empty mask. RXFEM enables the interrupt bit RXFE:
              • 0: + RXFE interrupt is disabled.
              • 1: RXFE interrupt is enabled.
              */ + __IO uint32_t RXFNFM : 1; /*!< [5..5] RX FIFO nearly full mask. RXNFM enables the interrupt + bit RXNF:
              • 0: RXNF interrupt is disabled.
              • 1: RXNF + interrupt is enabled
              */ + __IO uint32_t RXFFM : 1; /*!< [6..6] RX FIFO full mask. RXFFM enables the interrupt bit RXFF:
              • 0: + RXFF interrupt is disabled.
              • 1: RXFF interrupt is enabled.
              */ + uint32_t : 9; + __IO uint32_t RFSRM : 1; /*!< [16..16] Read-from-Slave request mask. RFSRM enables the interrupt + bit RFSR:
              • 0: RFSR interrupt is disabled.
              • 1: RFSR + interrupt is enabled.
              */ + __IO uint32_t RFSEM : 1; /*!< [17..17] Read-from-Slave empty mask. RFSEM enables the interrupt + bit RFSE:
              • 0: RFSE interrupt is disabled.
              • 1: RFSE + interrupt is enabled.
              */ + __IO uint32_t WTSRM : 1; /*!< [18..18] Write-to-Slave request mask. WTSRM enables the interrupt + bit WTSR:
              • 0: WTSR interrupt is disabled.
              • 1: WTSR + interrupt is enabled.
              */ + __IO uint32_t MTDM : 1; /*!< [19..19] Master Transaction done mask. MTDM enables the interrupt + bit MTD:
              • 0: MTD interrupt is disabled.
              • 1: MTD + interrupt is enabled.
              */ + __IO uint32_t STDM : 1; /*!< [20..20] Slave Transaction done mask. STDM enables the interrupt + bit STD:
              • 0: STDM interrupt is disabled.
              • 1: STDM + interrupt is enabled.
              */ + uint32_t : 3; + __IO uint32_t MALM : 1; /*!< [24..24] Master Arbitration lost mask. MALM enables the interrupt + bit MAL:
              • 0: MAL interrupt is disabled.
              • 1: MAL + interrupt is enabled.
              */ + __IO uint32_t BERRM : 1; /*!< [25..25] Bus Error mask. BERRM enables the interrupt bit BERR:
              • 0: + BERR interrupt is disabled.
              • 1: BERR interrupt is enabled.
              */ + uint32_t : 2; + __IO uint32_t MTDWSM : 1; /*!< [28..28] Master Transaction done without stop mask. MTDWSM enables + the interrupt bit MTDWS:
              • 0: MTDWS interrupt is disabled.
              • 1: + MTDWS interrupt is enabled.
              */ + } IMSCR_b; /*!< [29] BitSize */ + }; + + union { + __I uint32_t RISR; /*!< (@ 0x40A00030) I2C raw interrupt status register */ + + struct { + __I uint32_t TXFE : 1; /*!< [0..0] TX FIFO empty. TXFE is set when TX FIFO is empty. This + bit is self-cleared by writing in TX FIFO.
              • 0: TX FIFO + is not empty.
              • 1: TX FIFO is empty.
              */ + __I uint32_t TXFNE : 1; /*!< [1..1] TX FIFO nearly empty. TXFNE is set when the number of + entries in TX FIFO is less than or equal to the threshold value + programmed in the I2C_TFTR:THRESHOLD_TX register. It is self-cleared + when the threshold level is over the programmed threshold.
              • 0: + Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX + register.
              • 1: Number of entries in TX FIFO less than + or equal to the TFTR:THRESHOLD_TX register.
              */ + __I uint32_t TXFF : 1; /*!< [2..2] TX FIFO full. TXFF is set when a full condition occurs + in TX FIFO. This bit is self-cleared when the TX FIFO is not + full:
              • 0: TX FIFO is not full.
              • 1: TX FIFO is full.
              */ + __I uint32_t TXFOVR : 1; /*!< [3..3] TX FIFO overrun. TXFOVR is set when a write operation + in TX FIFO is performed and TX FIFO is full. The application + must avoid an overflow condition by a proper data flow control. + Anyway in case of overrun, the application shall flush the transmitter + (CR:FTX bit to set) because the TX FIFO content is corrupted + (at least one word has been lost in FIFO). This interrupt is + cleared by setting the related bit of the ICR register:
              • 0: + No overrun condition occurred in TX FIFO.
              • 1: Overrun + condition oc */ + __I uint32_t RXFE : 1; /*!< [4..4] RX FIFO empty. RXFE is set when the RX FIFO is empty. + This bit is self-cleared when the slave RX FIFO is not empty:
                • 0: + RX FIFO is not empty..
                • 1: RX FIFO is empty..
                */ + __I uint32_t RXFNF : 1; /*!< [5..5] RX FIFO nearly full. RXFNF is set when the number of + entries in RX FIFO is greater than or equal to the threshold + value programmed in the RFTR:THRESHOLD_RX register. Its self-cleared + when the threshold level is under the programmed threshold:
                • 0: + Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX + register.
                • 1: Number of entries in the RX FIFO greater + than or equal to the RFTR:THRESHOLD_RX register.
                */ + __I uint32_t RXFF : 1; /*!< [6..6] RX FIFO full. RXFF is set when a full condition occurs + in RX FIFO. This bit is self-cleared when the data are read + from the RX FIFO.
                • 0: RX FIFO is not full.
                • 1: + RX FIFO is full.
                */ + uint32_t : 8; + __I uint32_t LBR : 1; /*!< [15..15] Length number of bytes received. LBR is set in case + of MR or WTS and when the number of bytes received is equal + to the transaction length programmed in the MCR:LENGTH (master + mode) or SMB_SCR:LENGTH (slave mode). On the assertion of this + interrupt and when the bit CR:FRC_STRTCH is set, the hardware + starts clock stretching, the CPU shall download the data byte + (Command code, Byte Count, Data...) from RX FIFO, re-set the + expected length of the transaction in SMB_SCR:LENGTH and clear + the interrupt. When clear */ + __I uint32_t RFSR : 1; /*!< [16..16] Read-from-slave request. RFSR is set when a read-from-slave + "Slavetransmitter" request is received (I2C slave is addressed) + from the I2C line. On the assertion of this interrupt the TX + FIFO is flushed (pending data are cleared) and the CPU shall + put the data in TX FIFO. This bit is self-cleared by writing + data in FIFO. In case the FIFO is empty before the completion + of the read operation, the RISR:RFSE interrupt bit is set.This + interrupt is cleared by setting the related bit of the ICR register.
                  0: */ + __I uint32_t RFSE : 1; /*!< [17..17] Read-from-Slave empty. RFSE is set when a read-from-slave + operation is in progress and TX FIFO is empty. On the assertion + of this interrupt, the CPU shall download in TX FIFO the data + required for the slave operation. This bit is self-cleared by + writing in TX FIFO. At the end of the read-from-slave operation + this bit is cleared although the TX FIFO is empty.
                  • 0: + TX FIFO is not empty.
                  • 1: TX FIFO is empty with the read-from-slave + operation in progress.
                  */ + __I uint32_t WTSR : 1; /*!< [18..18] Write-to-Slave request. WTSR is set when a write-to-slave + operation is received (I2C slave is addressed) from the I2C + line. This notification can be used by the application to program + the DMA descriptor when required. This interrupt is cleared + by setting the related bit of the ICR register:
                  • 0: No + write-to-slave request pending.
                  • 1: Write-to-slave request + is pending.
                  */ + __I uint32_t MTD : 1; /*!< [19..19] Master Transaction done. MTD is set when a master operation + (master write or master read) has been executed after a stop + condition. The application shall read the related transaction + status (SR register), the pending data in the RX FIFO (only + for a master read operation) and clear this interrupt (transaction + acknowledgment). A subsequent master operation can be issued + (writing the MCR register) after the clearing of this interrupt. + A subsequent slave operation will be notified (RISR:WTSR and + RISR:RFSR inte */ + __I uint32_t STD : 1; /*!< [20..20] Slave Transaction done. STD is set when a slave operation + (write-to-slave or read-from-slave) has been executed. The application + shall read the related transaction status (SR register), the + pending data in the RX FIFO (only for a write-to-slave operation) + and clear this interrupt (transaction acknowledgment). A subsequent + slave operation will be notified (RISR:WTSR and RISR:RFSR interrupt + bits assertion) after clearing this interrupt, meanwhile the + I2C clock line will be stretched low. A subsequent master */ + uint32_t : 2; + __I uint32_t SAL : 1; /*!< [23..23] Slave Arbitration lost. SAL is set when the slave loses + the arbitration during the data phase. A collision occurs when + 2 devices transmit simultaneously 2 opposite values on the serial + data line. The device that is pulling up the line, identifies + the collision reading a 0 value on the sda_in signal, stops + the transmission, releases the bus and waits for the idle state + (STOP condition received) on the bus line. The device which + transmits the first unique zero wins the bus arbitration. This + interrupt is clea */ + __I uint32_t MAL : 1; /*!< [24..24] Master arbitration lost. MAL is set when the master + loses the arbitration. The status code word in the SR contains + a specific error tag (CAUSE field) for this error condition. + A collision occurs when 2 stations transmit simultaneously 2 + opposite values on the serial line. The station that is pulling + up the line, identifies the collision reading a 0 value on the + sda_in signal, stops the transmission, leaves the bus and waits + for the idle state (STOP condition received) on the bus line + before retrying the sa */ + __I uint32_t BERR : 1; /*!< [25..25] Bus Error. BERR is set when an unexpected Start/Stop + condition occurs during a transaction. The related actions are + different, depending on the type of operation in progress.The + status code word in the SR contains a specific error tag (CAUSE + field) for this error condition. This interrupt is cleared by + setting the related bit of the ICR register.
                  • 0: No bus + error detection.
                  • 1: Bus error detection.
                  */ + uint32_t : 2; + __I uint32_t MTDWS : 1; /*!< [28..28] Master transaction done without stop. MTDWS is set + when a master operation (write or read) has been executed and + a stop (MCR:P field) is not programmed. The application shall + read the related transaction status (SR register), the pending + data in the RX FIFO (only for a master read operation) and clear + this interrupt (transaction acknowledgment). A subsequent master + operation can be issued (by writing the MCR register) after + clearing this interrupt. A subsequent slave operation will be + notified (RISR:WTSR a */ + } RISR_b; /*!< [29] BitSize */ + }; + + union { + __I uint32_t MISR; /*!< (@ 0x40A00034) I2C masked interrupt status register */ + + struct { + __I uint32_t TXFEMIS : 1; /*!< [0..0] TX FIFO empty masked interrupt status.
                  • 0: TX FIFO + is not empty.
                  • 1: TX FIFO is empty.
                  */ + __I uint32_t TXFNEMIS : 1; /*!< [1..1] TX FIFO nearly empty masked interrupt status.
                  • 0: + Number of entries in TX FIFO greater than the TFTR:THRESHOLD_TX + register.
                  • 1: Number of entries in TX FIFO less than + or equal to the TFTR:THRESHOLD_TX register.
                  */ + __I uint32_t TXFFMIS : 1; /*!< [2..2] Tx FIFO full masked interrupt status.
                  • 0: TX FIFO + is not full.
                  • 1: TX FIFO is full.
                  */ + __I uint32_t TXFOVRMIS : 1; /*!< [3..3] Tx FIFO overrun masked interrupt status.
                  • 0: No + overrun condition occurred in TX FIFO.
                  • 1: Overrun condition + occurred in TX FIFO.
                  */ + __I uint32_t RXFEMIS : 1; /*!< [4..4] RX FIFO empty masked interrupt status.
                  • 0: RX FIFO + is not empty.
                  • 1: RX FIFO is empty..
                  */ + __I uint32_t RXFNFMIS : 1; /*!< [5..5] RX FIFO nearly full masked interrupt status.
                  • 0: + Number of entries in the RX FIFO less than the RFTR:THRESHOLD_RX + register.
                  • 1: Number of entries in the RX FIFO greater + than or equal to the RFTR:THRESHOLD_RX register.
                  */ + __I uint32_t RXFFMIS : 1; /*!< [6..6] RX FIFO full masked interrupt status.
                  • 0: RX FIFO + is not full.
                  • 1: RX FIFO is full.
                  */ + uint32_t : 9; + __I uint32_t RFSRMIS : 1; /*!< [16..16] Read-from-Slave request masked interrupt status.
                  • 0: + Read-from-slave request has been served.
                  • 1: Read-from-slave + request is pending.
                  */ + __I uint32_t RFSEMIS : 1; /*!< [17..17] Read-from-Slave empty masked interrupt status.
                  • 0: + TX FIFO is not empty.
                  • 1: TX FIFO is empty with the read-from-slave + operation in progress.
                  */ + __I uint32_t WTSRMIS : 1; /*!< [18..18] Write-to-Slave request masked interrupt status.
                  • 0: + No write-to-slave request pending.
                  • 1: Write-to-slave + request is pending.
                  */ + __I uint32_t MTDMIS : 1; /*!< [19..19] Master Transaction done masked interrupt status.
                  • 0: + Master transaction acknowledged.
                  • 1: Master transaction + done (ready for acknowledgment).
                  */ + __I uint32_t STDMIS : 1; /*!< [20..20] Slave Transaction done masked interrupt status.
                  • 0: + Slave transaction acknowledged.
                  • 1: Slave transaction + done (ready for acknowledgment).
                  */ + uint32_t : 3; + __I uint32_t MALMIS : 1; /*!< [24..24] Master Arbitration lost masked interrupt status.
                  • 0: + No master arbitration lost.
                  • 1: Master arbitration lost.
                  */ + __I uint32_t BERRMIS : 1; /*!< [25..25] Bus Error masked interrupt status.
                  • 0: No bus + error detection.
                  • 1: Bus error detection.
                  */ + uint32_t : 2; + __I uint32_t MTDWSMIS : 1; /*!< [28..28] Master Transaction done without stop masked interrupt + status.
                  • 0: Master transaction acknowledged.
                  • 1: + Master transaction done (ready for acknowledgment) and stop + is not applied into the I2C bus.
                  */ + } MISR_b; /*!< [29] BitSize */ + }; + + union { + __IO uint32_t ICR; /*!< (@ 0x40A00038) I2C interrupt clear register */ + + struct { + uint32_t : 3; + __IO uint32_t TXFOVRIC : 1; /*!< [3..3] Tx FIFO overrun interrupt clear.
                  • 0: Has no effect.
                  • 1 + : Clears interrupt pending.
                  */ + uint32_t : 12; + __IO uint32_t RFSRIC : 1; /*!< [16..16] Read-from-Slave request interrupt clear.
                  • 0: + Has no effect.
                  • 1: Clears interrupt pending.
                  */ + __IO uint32_t RFSEIC : 1; /*!< [17..17] Read-from-Slave empty interrupt clear.
                  • 0: Has + no effect.
                  • 1: Clears interrupt pending.
                  */ + __IO uint32_t WTSRIC : 1; /*!< [18..18] Write-to-Slave request interrupt clear.
                  • 0: Has + no effect.
                  • 1: Clears interrupt pending.
                  */ + __IO uint32_t MTDIC : 1; /*!< [19..19] Master Transaction done interrupt clear.
                  • 0: + Has no effect.
                  • 1: Clears interrupt pending.
                  */ + __IO uint32_t STDIC : 1; /*!< [20..20] Slave Transaction done interrupt clear.
                  • 0: Has + no effect.
                  • 1: Clears interrupt pending.
                  */ + uint32_t : 3; + __IO uint32_t MALIC : 1; /*!< [24..24] Master Arbitration lost interrupt clear.
                  • 0: + Has no effect.
                  • 1: Clears interrupt pending.
                  */ + __IO uint32_t BERRIC : 1; /*!< [25..25] Bus Error interrupt clear.
                  • 0: Has no effect.
                  • 1: + Clears interrupt pending.
                  */ + uint32_t : 2; + __IO uint32_t MTDWSIC : 1; /*!< [28..28] Master Transaction done without stop interrupt clear.
                  • 0: + Has no effect.
                  • 1: Clears interrupt pending.
                  */ + uint32_t : 1; + __IO uint32_t TIMEOUTIC : 1; /*!< [30..30] Timeout or Tlow error interrupt clear.
                  • 0: Has + no effect.
                  • 1: Clears interrupt pending.
                  */ + } ICR_b; /*!< [31] BitSize */ + }; + __I uint32_t RESERVED7[4]; + + union { + __IO uint16_t THDDAT; /*!< (@ 0x40A0004C) I2C hold time data */ + + struct { + __IO uint16_t THDDAT : 9; /*!< [0..8] Hold time data value. In master or slave mode, when the + I2C controller detects a falling edge in the SCL line, the counter, + which is loaded by the THDDAT, is launched. Once the THDDAT + value is reached, the data is transferred. */ + } THDDAT_b; /*!< [9] BitSize */ + }; + __I uint16_t RESERVED8; + + union { + __IO uint32_t THDSTA_FST_STD; /*!< (@ 0x40A00050) I2C hold time start condition F/S */ + + struct { + __IO uint32_t THDSTA_STD : 9; /*!< [0..8] Hold time start condition value for standard mode. When + the start condition is asserted, the decimeter loads the value + of THDSTA_STD for standard mode, once the THDSTA_STD value is + reached, the SCL line asserts low. */ + uint32_t : 7; + __IO uint32_t THDSTA_FST : 9; /*!< [16..24] Hold time start condition value for fast mode. When + the start condition is asserted, the decimeter loads the value + of THDSTA_FST for fast mode, once the THDSTA_FST value is reached, + the SCL line assert slow. */ + } THDSTA_FST_STD_b; /*!< [25] BitSize */ + }; + __I uint32_t RESERVED9; + + union { + __IO uint32_t TSUSTA_FST_STD; /*!< (@ 0x40A00058) I2C setup time start condition F/S */ + + struct { + __IO uint32_t TSUSTA_STD : 9; /*!< [0..8] Setup time start condition value for standard mode. After + a non-stop on the SCL line the decimeter loads the value of + TSUSTA_STD according to standard mode. Once the counter is expired, + the start condition is generated. */ + uint32_t : 7; + __IO uint32_t TSUSTA_FST : 9; /*!< [16..24] Setup time start condition value for fast mode. After + a non-stop on the SCL line the decimeter loads the value of + TSUSTA_FST according to fast mode. Once the counter is expired + the start condition is generated. */ + } TSUSTA_FST_STD_b; /*!< [25] BitSize */ + }; +} I2C_Type; + + +/* ================================================================================ */ +/* ================ AHBUPCONV ================ */ +/* ================================================================================ */ + + +/** + * @brief AHB up/down converter converter (AHBUPCONV) + */ + +typedef struct { /*!< (@ 0x40C00000) AHBUPCONV Structure */ + __IO uint8_t COMMAND; /*!< (@ 0x40C00000) AHB up/down converter command register */ +} AHBUPCONV_Type; + + +/* ================================================================================ */ +/* ================ MFT [MFT1] ================ */ +/* ================================================================================ */ + + +/** + * @brief MFT1 (MFT) + */ + +typedef struct { /*!< (@ 0x40D00000) MFT Structure */ + __IO uint16_t TNCNT1; /*!< (@ 0x40D00000) The Timer/Counter 1 register is a 16-bit RW register + that is not altered by reset and thus contains random data upon + power-up. Reading the register returns the current value of + the Timer/Counter 1. TnCNT1 can only be written by the software + when MFT is enabled (TnEN = 1). When MFT is disabled (TnEN = + 0), write operations on TnCNT1 register are ignored. */ + __I uint16_t RESERVED; + __IO uint16_t TNCRA; /*!< (@ 0x40D00004) The Capture/Reload A register is a 16-bit RW + register that is not affected by reset and thus contains random + data upon power-up. The software may read the register at any + time. However, the register can only be written by the software + when MFT is enabled (TnEN = 1). When MFT is disabled (TnEN = + 0), write operations on TnCRA register are ignored. */ + __I uint16_t RESERVED1; + __IO uint16_t TNCRB; /*!< (@ 0x40D00008) The Capture/Reload B register is a 16-bit RW + register that is not affected by reset and thus contains random + data upon power-up. The software may read the register at any + time. However, the register can only be written by the software + when MFT is enabled (TnEN = 1). When MFT is disabled (TnEN = + 0), write operations on TnCRB register are ignored. */ + __I uint16_t RESERVED2; + __IO uint16_t TNCNT2; /*!< (@ 0x40D0000C) The Timer/Counter 2 register is a 16-bit RW register + that is not altered by reset and thus contains random data upon + power-up. Reading the register returns the current value of + the Timer/Counter 2. TnCNT2 can only be written by the software + when MFT is enabled (TnEN = 1). When MFT is disabled (TnEN = + 0), write operations on TnCNT2 register are ignored. */ + __I uint16_t RESERVED3; + __IO uint8_t TNPRSC; /*!< (@ 0x40D00010) It contains the current value of the clock prescaler, + which determines the timer clock prescaler ratio. The register + value can be changed at any time. The timer clock is generated + by dividing the system clock by TnPRSC + 1. Therefore, the maximum + timer clock frequency is equal to the frequency of the system + clock (TnPRSC = 0x00), and the minimum timer clock is the frequency + of the system clock divided by 256 (TnPRSC = 0xFF). */ + __I uint8_t RESERVED4[3]; + + union { + __IO uint8_t TNCKC; /*!< (@ 0x40D00014) Clock unit control register */ + + struct { + __IO uint8_t TNC1CSEL : 3; /*!< [0..2] Define the clock mode for Timer/Counter 1:
                  • 000b: + No clock (Timer/Counter 1 stopped).
                  • 001b: System clock + with configurable prescaler (register TnPRSC).
                  • 010b: + External event on TnB (mode 1 and 3 only).
                  • 011b: Pulse + accumulate (mode 1 and 3 only).
                  • 100b: 16 MHz clock without + prescaler (only when the system clock is 32 MHz).
                  */ + __IO uint8_t TNC2CSEL : 3; /*!< [3..5] Define the clock mode for Timer/Counter 2:
                  • 000b: + No clock (Timer/Counter 2 stopped).
                  • 001b: System clock + with configurable prescaler (register TnPRSC).
                  • 010b: + External event on TnB (mode 1 and 3 only).
                  • 011b: Pulse + accumulate (mode 1 and 3 only).
                  • 100b: 16 MHz clock without + prescaler (only when the system clock is 32 MHz).
                  */ + } TNCKC_b; /*!< [6] BitSize */ + }; + __I uint8_t RESERVED5[3]; + + union { + __IO uint16_t TNMCTRL; /*!< (@ 0x40D00018) Timer mode control register */ + + struct { + __IO uint16_t TNMDSEL : 2; /*!< [0..1] MFTX mode select:
                  • 00b: Mode 1 or 1a: PWM mode + and system timer or pulse train.
                  • 01b: Mode 2: Dual-input + capture and system timer.
                  • 10b: Mode 3: Dual independent + Timer/Counter.
                  • 11b: Mode 4: Single timer and single + input capture.
                  */ + __IO uint16_t TNAEDG : 1; /*!< [2..2] Configure the TnA edge polarity for trigging an action:
                  • 0: + Input is sensitive to falling edges.
                  • 1: Input is sensitive + to rising edges.
                  */ + __IO uint16_t TNBEDG : 1; /*!< [3..3] Configure the TnB edge polarity for trigging an action:
                  • 0: + Input is sensitive to falling edges.
                  • 1: Input is sensitive + to rising edges.
                  */ + __IO uint16_t TNAEN : 1; /*!< [4..4] Enables TnA to either function as a preset input or as + a PWM output depending on the mode of operation. If the bit + is set (1) while operating in the dual-input capture mode (mode + 2), a transition on TnA causes TnCNT1 to be preset to 0xFFFF. + In the remaining modes of operation, setting TnAEN enables TnA + to function as a PWM output:
                  • 0: TnA input disable.
                  • 1: + TnA input enable.
                  */ + __IO uint16_t TNBEN : 1; /*!< [5..5] TnB Enable: If set (1) and while operating in dual-input + capture mode (mode 2) or input capture and timer mode (mode + 4), a transition on TnB will cause the corresponding Timer/Counter + to be preset to 0xFFFF. In mode 2, TnCNT1 will be preset to + 0xFFFF, while in mode 4, TnCNT2 is preset to 0xFFFF. The bit + has no effect while operating in any other modes than mode 2 + or mode 4:
                  • 0: TnB input disable.
                  • 1: TnB input + enable.
                  */ + __IO uint16_t TNAOUT : 1; /*!< [6..6] It contains the value of the TnA when used as PWM output. + The bit will be set and cleared by the hardware and thus reflects + the status of TnA. The bit can be read or written by software + at any time. If the hardware is attempting to toggle the bit + at the same time that software writes to the bit, the software + write will take precedence over the hardware update. The bit + has no effect when TnA is used as an input or when the module + is disabled:
                  • 0: TnA pin is low.
                  • 1: TnA pin is + high.
                  */ + __IO uint16_t TNEN : 1; /*!< [7..7] MFT is enabled if the bit is set (1), otherwise it is + disabled. When MFT is disabled, all clocks to the counter unit + are stopped, thus decreasing power consumption to a minimum. + For that reason, the Timer/Counter registers (TnCNT1, TnCNT2), + the Capture/Reload registers (TnCRA, TnCRB) and the interrupt-pending + bits (TnXPND) cannot be written by software. Furthermore, the + 8-bit clock prescaler and the interrupt-pending bits are reset + and the TnA I/O pin becomes an input. */ + __IO uint16_t TNPTEN : 1; /*!< [8..8] This bitfield enable the mode 1a. If set (1) while TnMDSEL + is set to 00b, the Timer/Counter 1 operates in PWM pulse-train + mode (mode 1a). The bit has no effect while TnMDSEL is set to + any value other than 00b:
                  • 0: Mode 1a not selected.
                  • 1: + Mode 1a selected (if TnMDSEL = 00b).
                  */ + __IO uint16_t TNPTSE : 1; /*!< [9..9] Tn Pulse-Train software trigger enable: if set (1) while + operating in PWM pulse-train mode (mode 1a), the pulse-train + generation can only be triggered by setting the TnPTET to 1. + If the TnPTSE bit is reset (0), pulses are generated only if + a transition occurs on TnB. The bit has no effect while operating + in any other modes than timer mode 1a:
                  • 0: No effect.
                  • 1: + Pulse-train generation trigger (in mode 1a)
                  */ + __IO uint16_t TNPTET : 1; /*!< [10..10] Tn Pulse-Train event trigger: if set (1) while operating + in pulse-train mode (mode 1a) and the TnPTSE bit is set (1), + pulse-train generation is triggered. When Timer/Counter 2 (TnCNT2) + reaches its underflow condition, this bit is reset (0). If the + TnPTSE bit is not set (0) while operating in mode 1a, the TnPTET + bit cannot be written.
                  • 0: No pulse-train event trigger + occurred.
                  • 1: Pulse-train event trigger occurred (in + mode 1a).
                  */ + } TNMCTRL_b; /*!< [11] BitSize */ + }; + __I uint16_t RESERVED6; + + union { + __IO uint8_t TNICTRL; /*!< (@ 0x40D0001C) Timer interrupt control register */ + + struct { + __I uint8_t TNAPND : 1; /*!< [0..0] Timer interrupt A pending:
                  • 0: No interrupt source + pending.
                  • 1: Interrupt source pending.
                  */ + __I uint8_t TNBPND : 1; /*!< [1..1] Timer interrupt B pending:
                  • 0: No interrupt source + pending.
                  • 1: Interrupt source pending.
                  */ + __I uint8_t TNCPND : 1; /*!< [2..2] Timer interrupt C pending:
                  • 0: No interrupt source + pending.
                  • 1: Interrupt source pending.
                  */ + __I uint8_t TNDPND : 1; /*!< [3..3] Timer interrupt D pending:
                  • 0: No interrupt source + pending.
                  • 1: Interrupt source pending.
                  */ + __IO uint8_t TNAIEN : 1; /*!< [4..4] Timer interrupt A enable:
                  • 0: Interrupt disabled.
                  • 1: + Interrupt enabled.
                  */ + __IO uint8_t TNBIEN : 1; /*!< [5..5] Timer interrupt B enable:
                  • 0: Interrupt disabled.
                  • 1: + Interrupt enabled.
                  */ + __IO uint8_t TNCIEN : 1; /*!< [6..6] Timer interrupt C enable:
                  • 0: Interrupt disabled.
                  • 1: + Interrupt enabled.
                  */ + __IO uint8_t TNDIEN : 1; /*!< [7..7] Timer interrupt D enable:
                  • 0: Interrupt disabled.
                  • 1: + Interrupt enabled.
                  */ + } TNICTRL_b; /*!< [8] BitSize */ + }; + __I uint8_t RESERVED7[3]; + + union { + __O uint8_t TNICLR; /*!< (@ 0x40D00020) Timer interrupt clear register */ + + struct { + __O uint8_t TNACLR : 1; /*!< [0..0] 1: clear the timer pending flag A. */ + __O uint8_t TNBCLR : 1; /*!< [1..1] 1: clear the timer pending flag B. */ + __O uint8_t TNCCLR : 1; /*!< [2..2] 1: clear the timer pending flag C. */ + __O uint8_t TNDCLR : 1; /*!< [3..3] 1: clear the timer pending flag D. */ + } TNICLR_b; /*!< [4] BitSize */ + }; +} MFT_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief Real-Time Counter (RTC) + */ + +typedef struct { /*!< (@ 0x40F00000) RTC Structure */ + + union { + __I uint32_t CWDR; /*!< (@ 0x40F00000) Clockwatch Data Register */ + + struct { + __I uint32_t CWSEC : 6; /*!< [0..5] RTC clockwatch second value. Clockwatch seconds: 0 to + 59 (max 0x3B). */ + __I uint32_t CWMIN : 6; /*!< [6..11] RTC clockwatch minute value. Clockwatch seconds: 0 to + 59 (max 0x3B). */ + __I uint32_t CWHOUR : 5; /*!< [12..16] RTC clockwatch hour value. Clockwatch seconds: 0 to + 23 (max 0x17). */ + __I uint32_t CWDAYW : 3; /*!< [17..19] RTC clockwatch day of week value. Clockwatch day of + week:
                  • 001b: Sunday.
                  • 010b: Monday.
                  • 011b: + Tuesday.
                  • 100b: Wednesday.
                  • 101b: Thursday.
                  • 110b: + Friday.
                  • 111b: Saturday.
                  */ + __I uint32_t CWDAYM : 5; /*!< [20..24] RTC clockwatch day of month value: 1 to 28/29/30 or + 31. Range of value to program depends on the month:
                  • 1 + to 28: February month, non-leap year.
                  • 1 to 29: February + month, leap year.
                  • 1 to 30: April, June, September, November + month.
                  • 1 to 31: January, March, May, August, October, + December month.
                  */ + __I uint32_t CWMONTH : 4; /*!< [25..28] RTC clockwatch month value:
                  • 0001b: January.
                  • ...
                  • 1100: December.
                  */ + } CWDR_b; /*!< [29] BitSize */ + }; + + union { + __IO uint32_t CWDMR; /*!< (@ 0x40F00004) Clockwatch Data Match Register */ + + struct { + __IO uint32_t CWSECM : 6; /*!< [0..5] RTC clockwatch second match value:
                  • 00 0000 to + 11 1011: (0 to 59 or 0x00 to 0x3B) clockwatch seconds.
                  • 11 + 1100 to 11 1111 - (60 to 63 or 0x3C to 0x3F).
                  Non-valid + data, match never occurs. */ + __IO uint32_t CWMINM : 6; /*!< [6..11] RTC clockwatch minute match value:
                  • 00 0000 to + 11 1011: (0 to 59 or 0x00 to 0x3B) clockwatch minutes.
                  • 11 + 1100 to 11 1111 - (60 to 63 or 0x3C to 0x3F).
                  Non-valid + data, match never occurs. */ + __IO uint32_t CWHOURM : 5; /*!< [12..16] RTC clockwatch hour match value:
                  • 00000b to 10111b: + (0 to 23 or 0x00 to 0x17) hour match value.
                  • 11000b to + 11111b - (24 to 31 or 0x18 to 0x1F).
                  Non-valid data, + match never occurs. */ + __IO uint32_t CWDAYWM : 3; /*!< [17..19] RTC clockwatch day of week match value:
                  • 000b: + day of week is don't care in the comparison. (Default value + after PORn).
                  • 001b to 111b: (1 to 7) day of week match + value.
                  */ + __IO uint32_t CWDAYMM : 5; /*!< [20..24] RTC clockwatch day of month match value:
                  • 0000b: + (month is don't care in the comparison. Default value after + PORn).
                  • 1 to 31: day of month match value.
                  */ + __IO uint32_t CWMONTHM : 4; /*!< [25..28] RTC clockwatch month match value:
                  • 0000b: (day + of month is don't care in the comparison. Default value after + PORn).
                  • 0001b to 1100b: (1 to 12) month match value.
                  • 1101b + (13, 0xD) to 1111b (0xF) non-valid data, match never occurs.
                  */ + } CWDMR_b; /*!< [29] BitSize */ + }; + + union { + __IO uint32_t CWDLR; /*!< (@ 0x40F00008) Clockwatch Data Load Register */ + + struct { + __IO uint32_t CWSECL : 6; /*!< [0..5] RTC clockwatch second load value. Clockwatch seconds + from 0 to 59 (0x3B). Other values must not be used. */ + __IO uint32_t CWMINL : 6; /*!< [6..11] RTC clockwatch minute load value. Clockwatch minutes + from 0 to 59 (0x3B). Other values must not be used. */ + __IO uint32_t CWHOURL : 5; /*!< [12..16] RTC clockwatch hour load value. Clockwatch hours from + 0 to 23 (0x17). Other values must not be used. */ + __IO uint32_t CWDAYWL : 3; /*!< [17..19] RTC clockwatch day of week load value. Clockwatch day + of week:
                  • 000b: Must not be used.
                  • 001b: Sunday.
                  • 010b + : Monday.
                  • 011b: Tuesday.
                  • 100b: Wednesday.
                  • 101b: + Thursday.
                  • 110b: Friday.
                  • 111b: Saturday.
                  */ + __IO uint32_t CWDAYML : 5; /*!< [20..24] RTC clockwatch day of month load value. 1 to 28/29/30 + or 31 depending on month:
                  • 1 to 28: February month, non-leap + year.
                  • 1 to 29: February month, leap year.
                  • 1 + to 30: April, June, September, November month.
                  • 1 to + 31: January, March, May, August, October, December month.
                  • Other + values must not be used.
                  */ + __IO uint32_t CWMONTHL : 4; /*!< [25..28] RTC clockwatch month load value:
                  • 0001b: January.
                  • . + ..
                  • 1100: December.
                  Other values must not be + used. */ + } CWDLR_b; /*!< [29] BitSize */ + }; + + union { + __I uint16_t CWYR; /*!< (@ 0x40F0000C) Clockwatch Year Register */ + + struct { + __I uint16_t CWYEAR : 14; /*!< [0..13] RTC clockwatch year value. Clockwatch year, in BCD format + is from 0 to 3999. */ + } CWYR_b; /*!< [14] BitSize */ + }; + __I uint16_t RESERVED; + + union { + __IO uint16_t CWYMR; /*!< (@ 0x40F00010) Clockwatch Year Match Register */ + + struct { + __IO uint16_t CWYEARM : 14; /*!< [0..13] RTC clockwatch year match value. Clockwatch year match + value is in BCD format from 0 to 3999. */ + } CWYMR_b; /*!< [14] BitSize */ + }; + __I uint16_t RESERVED1; + + union { + __IO uint16_t CWYLR; /*!< (@ 0x40F00014) Clockwatch Year Load Register */ + + struct { + __IO uint16_t CWYEARL : 14; /*!< [0..13] RTC clockwatch year load value. Clockwatch year load + value is in BCD format from 0 to 3999. */ + } CWYLR_b; /*!< [14] BitSize */ + }; + __I uint16_t RESERVED2; + + union { + __IO uint32_t CTCR; /*!< (@ 0x40F00018) Control Trim and Counter Register */ + + struct { + __IO uint32_t CKDIV : 15; /*!< [0..14] Clock divider factor. This value plus one represents + the integer part of the CLK32K clock divider used to produce + the reference 1 Hz clock.
                  • 0x000: CLK1HZ clock is similar + to CLK32K for RTC timer and stopped for RTC clockwatch.
                  • 0x0001: + 2 CLK32K clock cycles per CLK1HZ clock cycle.
                  • ...
                  • 0x7FFF: + 32768 CLK32K clock cycles per CLK1HZ clock cycle (default value + after PORn reset).
                  • ...
                  • 0xFFFF: CLK32K clock + cycles per CLK1HZ clock cycle.
                  Writing to this bit-fie */ + uint32_t : 1; + __IO uint32_t CKDEL : 10; /*!< [16..25] Trim delete count. This value represents the number + of CLK32K clock pulses to delete every 1023 CLK32K clock cycles + to get a better reference 1 Hz clock for incrementing the RTC + counter.
                  • 0x000: No CLK32K clock cycle is deleted every + 1023 CLK1HZ clock cycles (default value after PORn reset).
                  • 0x001: + 1 CLK32K clock cycle is deleted every 1023 CLK1HZ clock cycles.
                  • .. + .
                  • 0x3FF: 1023 CLK32K clock cycles are deleted every 1023 + CLK1HZ clock cycles.
                  Writing to this bit-field wi */ + __IO uint32_t CWEN : 1; /*!< [26..26] Clockwatch enable bit. When set to 1, the clockwatch + is enabled. Once it is enabled, any write to this register has + no effect until a power-on reset. A read returns the value of + the CWEN bit value. */ + } CTCR_b; /*!< [27] BitSize */ + }; + + union { + __IO uint8_t IMSC; /*!< (@ 0x40F0001C) RTC interrupt mask register */ + + struct { + __IO uint8_t WIMSC : 1; /*!< [0..0] RTC clock watch interrupt enable bit:
                  • When set + to 0, clears the interrupt mask (default after PORn reset). + The interrupt is disabled.
                  • When set to 1, the interrupt + for RTC clockwatch interrupt is enabled.
                  */ + __IO uint8_t TIMSC : 1; /*!< [1..1] RTC timer interrupt enable bit:
                  • When set to 0, + sets the mask for RTC timer interrupt (default after PORn reset). + The interrupt is disabled.
                  • When set to 1, clears this + mask and enables the interrupt.
                  */ + } IMSC_b; /*!< [2] BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __I uint8_t RIS; /*!< (@ 0x40F00020) RTC raw interrupt status register */ + + struct { + __I uint8_t WRIS : 1; /*!< [0..0] RTC clock watch raw interrupt status bit. Gives the raw + interrupt state (prior to masking) of the RTC clock watch interrupt. */ + __I uint8_t TRIS : 1; /*!< [1..1] RTC timer raw interrupt status bit. Gives the raw interrupt + state (prior to masking) of the RTC timer interrupt. */ + } RIS_b; /*!< [2] BitSize */ + }; + __I uint8_t RESERVED4[3]; + + union { + __I uint8_t MIS; /*!< (@ 0x40F00024) RTC masked interrupt status register */ + + struct { + __I uint8_t WMIS : 1; /*!< [0..0] RTC clock watch interrupt status bit. Gives the masked + interrupt status (after masking) of the RTC clock watch interrupt + WINTR. */ + __I uint8_t TMIS : 1; /*!< [1..1] RTC timer interrupt status bit. Gives the masked interrupt + status (after masking) of the RTC timer interrupt TINTR. */ + } MIS_b; /*!< [2] BitSize */ + }; + __I uint8_t RESERVED5[3]; + + union { + __O uint8_t ICR; /*!< (@ 0x40F00028) RTC interrupt clear register */ + + struct { + __O uint8_t WIC : 1; /*!< [0..0] RTC clock watch interrupt clear register bit. Clears + the RTC clock watch interrupt WINTR.
                  • 0: No effect.
                  • 1: + Clears the interrupt.
                  */ + __O uint8_t TIC : 1; /*!< [1..1] RTC timer interrupt clear register bit. Clears the RTC + timer interrupt TINTR.
                  • 0: No effect.
                  • 1: Clears + the interrupt.
                  */ + } ICR_b; /*!< [2] BitSize */ + }; + __I uint8_t RESERVED6[3]; + __I uint32_t TDR; /*!< (@ 0x40F0002C) RTC timer load value */ + + union { + __IO uint16_t TCR; /*!< (@ 0x40F00030) RTC timer control register */ + + struct { + __IO uint16_t OS : 1; /*!< [0..0] RTC Timer one shot count.
                  • 0: Periodic mode (default). + When reaching zero, the RTC timer raises its interrupt and is + reloaded from the LD content.
                  • 1: One-shot mode. When + reaching zero, the RTC timer raise its interrupt and stops.
                  */ + __IO uint16_t EN : 1; /*!< [1..1] RTC Timer enable bit.
                  • 0: The RTC timer is stopped + on the next CLK32K cycle.
                  • 1: The RTC timer is enabled + on the next CLK32K cycle.
                  When the RTC timer is stopped, + the content of the counter is frozen. A read returns the value + of the EN bit. This bit set by hardware when the TLR register + is written to while the counter is stopped. When the device + is active, this bit is cleared by hardware when the counter + reaches zero in one-shot mode. */ + __IO uint16_t S : 1; /*!< [2..2] RTC Timer self start bit. When written to 1b, each write + in a load register or a pattern will set EN to 1b, so, start + the counter in the next CLK32K cycle. */ + uint16_t : 1; + __IO uint16_t SP : 7; /*!< [4..10] RTC Timer Pattern size. Number of pattern bits crossed + by the pointer. It defines the useful pattern size. */ + __IO uint16_t CLK : 1; /*!< [11..11] RTC Timer clock.
                  • 0: The RTC timer is clocked + by CLK32K.
                  • 1: The RTC timer is clocked by the trimmed + clock.
                  */ + __IO uint16_t BYPASS_GATED: 1; /*!< [12..12] Enable or disable the internal clock gating:
                  • 0: + The internal clock gating is activated.
                  • 1: No clock + gating, clock is always enabled.
                  */ + } TCR_b; /*!< [13] BitSize */ + }; + __I uint16_t RESERVED7; + __IO uint32_t TLR1; /*!< (@ 0x40F00034) RTC Timer first Load Register */ + __IO uint32_t TLR2; /*!< (@ 0x40F00038) RTC Timer second Load Register */ + __IO uint32_t TPR1; /*!< (@ 0x40F0003C) RTC Timer Pattern Register (pattern[31:0]) */ + __IO uint32_t TPR2; /*!< (@ 0x40F00040) RTC Timer Pattern Register (pattern[63:32]) */ + __IO uint32_t TPR3; /*!< (@ 0x40F00044) RTC Timer Pattern Register (pattern[95:64]) */ + __IO uint32_t TPR4; /*!< (@ 0x40F00048) RTC Timer Pattern Register (pattern[127:96]) */ + __IO uint32_t TIN; /*!< (@ 0x40F0004C) RTC Timer Interrupt Number Register */ +} RTC_Type; + + +/* ================================================================================ */ +/* ================ BLUE_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief BLUE Controller (BLUE_CTRL) + */ + +typedef struct { /*!< (@ 0x48000000) BLUE_CTRL Structure */ + __IO uint32_t INTERRUPT; /*!< (@ 0x48000000) Interrupt status and clear register */ + __IO uint32_t TIMEOUT; /*!< (@ 0x48000004) Timeout programming register */ + __I uint32_t TIMER_CAPTURE; /*!< (@ 0x48000008) Captured timer value register */ + __IO uint32_t RADIO_CONFIG; /*!< (@ 0x4800000C) Radio configuration register */ + __I uint32_t CURRENT_TIME; /*!< (@ 0x48000010) Timer current value register */ + __I uint32_t STATUS; /*!< (@ 0x48000014) Status register */ + __IO uint32_t AES_KEY0; /*!< (@ 0x48000018) AES key bit [127:96] */ + __IO uint32_t AES_KEY1; /*!< (@ 0x4800001C) AES key bit [95:64] */ + __IO uint32_t AES_KEY2; /*!< (@ 0x48000020) AES key bit [63:32] */ + __IO uint32_t AES_KEY3; /*!< (@ 0x48000024) AES key bit [31:0] */ + __IO uint32_t CLEAR_TEXT0; /*!< (@ 0x48000028) AES clear text bit [127:96] */ + __IO uint32_t CLEAR_TEXT1; /*!< (@ 0x4800002C) AES clear text bit [95:64] */ + __IO uint32_t CLEAR_TEXT2; /*!< (@ 0x48000030) AES clear text bit [63:32] */ + __IO uint32_t CLEAR_TEXT3; /*!< (@ 0x48000034) AES clear text bit [31:0]. Writing in this register + starts an encryption */ + __I uint32_t AES_CYPHERTEXT0; /*!< (@ 0x48000038) AES cypher text bit [127:96] */ + __I uint32_t AES_CYPHERTEXT1; /*!< (@ 0x4800003C) AES cypher text bit [95:64] */ + __I uint32_t AES_CYPHERTEXT2; /*!< (@ 0x48000040) AES cypher text bit [63:32] */ + __I uint32_t AES_CYPHERTEXT3; /*!< (@ 0x48000044) AES cypher text bit [31:0] */ + __IO uint32_t HOST_WKUP_TIMER; /*!< (@ 0x48000048) Host wakeup timer register */ +} BLUE_CTRL_Type; + + +/* ================================================================================ */ +/* ================ CKGEN_BLE ================ */ +/* ================================================================================ */ + + +/** + * @brief Clock Gen BLE (CKGEN_BLE) + */ + +typedef struct { /*!< (@ 0x48100000) CKGEN_BLE Structure */ + __I uint32_t RESERVED[2]; + + union { + __I uint16_t REASON_RST; /*!< (@ 0x48100008) Indicates the reset reason from BLE */ + + struct { + uint16_t : 1; + __I uint16_t BOR : 1; /*!< [1..1] Reset from BOR */ + __I uint16_t POR : 1; /*!< [2..2] Reset from POR */ + __I uint16_t WKP_IO9 : 1; /*!< [3..3] Wakeup from external IO9 */ + __I uint16_t WKP_IO10 : 1; /*!< [4..4] Wakeup from external IO10 */ + __I uint16_t WKP_IO11 : 1; /*!< [5..5] Wakeup from external IO11 */ + __I uint16_t WKP_IO12 : 1; /*!< [6..6] Wakeup from external IO12 */ + __I uint16_t WKP_IO13 : 1; /*!< [7..7] Wakeup from external IO13 */ + __I uint16_t WKP_BLUE : 1; /*!< [8..8] Wakeup coms from the timer 1 expiration in the wakeup + control block of the BLE radio */ + uint16_t : 1; + __I uint16_t WKP2_BLUE : 1; /*!< [10..10] Wakeup coms from the timer 2 expiration in the wakeup + control block of the BLE radio */ + } REASON_RST_b; /*!< [11] BitSize */ + }; + __I uint16_t RESERVED1; + + union { + __IO uint16_t CLK32K_COUNT; /*!< (@ 0x4810000C) Counter of 32 kHz clock */ + + struct { + __IO uint16_t SLOW_COUNT : 9; /*!< [0..8] Program the window length (in slow clock period unit) + for slow clock measurement */ + } CLK32K_COUNT_b; /*!< [9] BitSize */ + }; + __I uint16_t RESERVED2; + + union { + __IO uint32_t CLK32K_PERIOD; /*!< (@ 0x48100010) Period of 32 kHz clock */ + + struct { + __I uint32_t SLOW_PERIOD: 19; /*!< [0..18] Indicates slow clock period information. The result + provided in this field corresponds to the length of SLOW_COUNT + periods of the slow clock (32 kHz) measured in 16 MHz half-period + unit. The measurement is done automatically each time the device + enters in active2 mode using SLOW_COUNT = 16. A new calculation + can be launched by writing zero in CLK32K_PERIOD register. In + this case, the time window uses the value programmed in SLOW_COUNT + field. */ + } CLK32K_PERIOD_b; /*!< [19] BitSize */ + }; + + union { + __I uint32_t CLK32K_FREQ; /*!< (@ 0x48100014) Measurement of frequency of 32 kHz clock */ + + struct { + __I uint32_t SLOW_FREQ : 27; /*!< [0..26] Value equal to 2^33 / SLOW_PERIOD */ + } CLK32K_FREQ_b; /*!< [27] BitSize */ + }; + + union { + __IO uint16_t CLK32K_IT; /*!< (@ 0x48100018) Interrupt event for 32 kHz clock measurement */ + + struct { + __IO uint16_t CLK32K_MEAS_IRQ: 1; /*!< [0..0] When read, provides the status of the interrupt indicating + slow lock measurement is finished:
                  • 0: No pending interrupt.
                  • 1: Pending interrupt.
                  When written, clears the interrupt:
                  • + 0: No effect.
                  • 1: Clear the interrupt.
                  */ + } CLK32K_IT_b; /*!< [1] BitSize */ + }; +} CKGEN_BLE_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + + +/** + * @brief DMA (DMA) + */ + +typedef struct { /*!< (@ 0xA0000000) DMA Structure */ + + union { + __I uint32_t ISR; /*!< (@ 0xA0000000) DMA interrupt status register */ + + struct { + __I uint32_t GIF0 : 1; /*!< [0..0] Channel 0 global interrupt flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No TE, HT or TC event on channel + 0.
                  • 1: A TE, HT or TC event occurred on channel 0.
                  */ + __I uint32_t TCIF0 : 1; /*!< [1..1] Channel 0 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 0.
                  • 1: A transfer complete (TC) occurred on + channel 0.
                  */ + __I uint32_t HTIF0 : 1; /*!< [2..2] Channel 0 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 0.
                  • 1: A half transfer (HT) event occurred + on channel 0.
                  */ + __I uint32_t TEIF0 : 1; /*!< [3..3] Channel 0 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 0.
                  • 1: A transfer error (TE) occurred on channel + 0.
                  */ + __I uint32_t GIF1 : 1; /*!< [4..4] Channel 1 global interrupt flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No TE, HT or TC event on channel + 1.
                  • 1: A TE, HT or TC event occurred on channel 1.
                  */ + __I uint32_t TCIF1 : 1; /*!< [5..5] Channel 1 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 1.
                  • 1: A transfer complete (TC) occurred on + channel 1.
                  */ + __I uint32_t HTIF1 : 1; /*!< [6..6] Channel 1 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 1.
                  • 1: A half transfer (HT) event occurred + on channel 1.
                  */ + __I uint32_t TEIF1 : 1; /*!< [7..7] Channel 1 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 1.
                  • 1: A transfer error (TE) occurred on channel + 1.
                  */ + __I uint32_t GIF2 : 1; /*!< [8..8] Channel 2 global interrupt flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No TE, HT or TC event on channel + 2.
                  • 1: A TE, HT or TC event occurred on channel 2.
                  */ + __I uint32_t TCIF2 : 1; /*!< [9..9] Channel 2 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 2.
                  • 1: A transfer complete (TC) occurred on + channel 2.
                  */ + __I uint32_t HTIF2 : 1; /*!< [10..10] Channel 2 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 2.
                  • 1: A half transfer (HT) event occurred + on channel 2.
                  */ + __I uint32_t TEIF2 : 1; /*!< [11..11] Channel 2 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 2.
                  • 1: A transfer error (TE) occurred on channel + 2.
                  */ + __I uint32_t GIF3 : 1; /*!< [12..12] Channel 3 global interrupt flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No TE, HT or TC event on + channel 3.
                  • 1: A TE, HT or TC event occurred on channel + 3.
                  */ + __I uint32_t TCIF3 : 1; /*!< [13..13] Channel 3 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 3.
                  • 1: A transfer complete (TC) occurred on + channel 3.
                  */ + __I uint32_t HTIF3 : 1; /*!< [14..14] Channel 3 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 3.
                  • 1: A half transfer (HT) event occurred + on channel 3.
                  */ + __I uint32_t TEIF3 : 1; /*!< [15..15] Channel 3 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 3.
                  • 1: A transfer error (TE) occurred on channel + 3.
                  */ + __I uint32_t GIF4 : 1; /*!< [16..16] Channel 4 global interrupt flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No TE, HT or TC event on + channel 4.
                  • 1: A TE, HT or TC event occurred on channel + 4.
                  */ + __I uint32_t TCIF4 : 1; /*!< [17..17] Channel 4 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 4.
                  • 1: A transfer complete (TC) occurred on + channel 4.
                  */ + __I uint32_t HTIF4 : 1; /*!< [18..18] Channel 4 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 4.
                  • 1: A half transfer (HT) event occurred + on channel 4.
                  */ + __I uint32_t TEIF4 : 1; /*!< [19..19] Channel 4 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 4.
                  • 1: A transfer error (TE) occurred on channel + 4.
                  */ + __I uint32_t GIF5 : 1; /*!< [20..20] Channel 5 global interrupt flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No TE, HT or TC event on + channel 5.
                  • 1: A TE, HT or TC event occurred on channel + 5.
                  */ + __I uint32_t TCIF5 : 1; /*!< [21..21] Channel 5 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 5.
                  • 1: A transfer complete (TC) occurred on + channel 5.
                  */ + __I uint32_t HTIF5 : 1; /*!< [22..22] Channel 5 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 5.
                  • 1: A half transfer (HT) event occurred + on channel 5.
                  */ + __I uint32_t TEIF5 : 1; /*!< [23..23] Channel 5 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 5.
                  • 1: A transfer error (TE) occurred on channel + 5.
                  */ + __I uint32_t GIF6 : 1; /*!< [24..24] Channel 6 global interrupt flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No TE, HT or TC event on + channel 6.
                  • 1: A TE, HT or TC event occurred on channel + 6.
                  */ + __I uint32_t TCIF6 : 1; /*!< [25..25] Channel 6 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 6.
                  • 1: A transfer complete (TC) occurred on + channel 6.
                  */ + __I uint32_t HTIF6 : 1; /*!< [26..26] Channel 6 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 6.
                  • 1: A half transfer (HT) event occurred + on channel 6.
                  */ + __I uint32_t TEIF6 : 1; /*!< [27..27] Channel 6 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 6.
                  • 1: A transfer error (TE) occurred on channel + 6.
                  */ + __I uint32_t GIF7 : 1; /*!< [28..28] Channel 7 global interrupt flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No TE, HT or TC event on + channel 7.
                  • 1: A TE, HT or TC event occurred on channel + 7.
                  */ + __I uint32_t TCIF7 : 1; /*!< [29..29] Channel 7 transfer complete flag. This bit is set by + hardware. It is cleared by software writing 1 to the corresponding + bit in the IFCR register.
                  • 0: No transfer complete (TC) + on channel 7.
                  • 1: A transfer complete (TC) occurred on + channel 7.
                  */ + __I uint32_t HTIF7 : 1; /*!< [30..30] Channel 7 half transfer flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No half transfer (HT) event + on channel 7.
                  • 1: A half transfer (HT) event occurred + on channel 7.
                  */ + __I uint32_t TEIF7 : 1; /*!< [31..31] Channel 7 transfer error flag. This bit is set by hardware. + It is cleared by software writing 1 to the corresponding bit + in the IFCR register.
                  • 0: No transfer error (TE) event + on channel 7.
                  • 1: A transfer error (TE) occurred on channel + 7.
                  */ + } ISR_b; /*!< [32] BitSize */ + }; + + union { + __O uint32_t IFCR; /*!< (@ 0xA0000004) DMA interrupt flag clear register */ + + struct { + __O uint32_t CGIF0 : 1; /*!< [0..0] Channel 0 global interrupt flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the GIF, TEIF, HTIF and TCIF + flags in the ISR register.
                  */ + __O uint32_t CTCIF0 : 1; /*!< [1..1] Channel 0 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF0 : 1; /*!< [2..2] Channel 0 half transfer flag. This bit is set by software.
                  • 0 + : No effect.
                  • 1: Clears the corresponding HTIF flag in + the ISR register.
                  */ + __O uint32_t CTEIF0 : 1; /*!< [3..3] Channel 0 transfer error flag. This bit is set by software.
                  • + 0: No effect.
                  • 1: Clears the corresponding TEIF flag in + the ISR register.
                  */ + __O uint32_t CGIF1 : 1; /*!< [4..4] Channel 1 global interrupt flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the GIF, TEIF, HTIF and TCIF + flags in the ISR register.
                  */ + __O uint32_t CTCIF1 : 1; /*!< [5..5] Channel 1 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF1 : 1; /*!< [6..6] Channel 1 half transfer flag. This bit is set by software.
                  • 0 + : No effect.
                  • 1: Clears the corresponding HTIF flag in + the ISR register.
                  */ + __O uint32_t CTEIF1 : 1; /*!< [7..7] Channel 1 transfer error flag. This bit is set by software.
                  • + 0: No effect.
                  • 1: Clears the corresponding TEIF flag in + the ISR register.
                  */ + __O uint32_t CGIF2 : 1; /*!< [8..8] Channel 2 global interrupt flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the GIF, TEIF, HTIF and TCIF + flags in the ISR register.
                  */ + __O uint32_t CTCIF2 : 1; /*!< [9..9] Channel 2 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF2 : 1; /*!< [10..10] Channel 2 half transfer flag. This bit is set by software.
                  • 0: No effect.
                  • 1: Clears the corresponding HTIF flag + in the ISR register.
                  */ + __O uint32_t CTEIF2 : 1; /*!< [11..11] Channel 2 transfer error flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the corresponding TEIF flag + in the ISR register.
                  */ + __O uint32_t CGIF3 : 1; /*!< [12..12] Channel 3 global interrupt flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the GIF, TEIF, + HTIF and TCIF flags in the ISR register.
                  */ + __O uint32_t CTCIF3 : 1; /*!< [13..13] Channel 3 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF3 : 1; /*!< [14..14] Channel 3 half transfer flag. This bit is set by software.
                  • 0: No effect.
                  • 1: Clears the corresponding HTIF flag + in the ISR register.
                  */ + __O uint32_t CTEIF3 : 1; /*!< [15..15] Channel 3 transfer error flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the corresponding TEIF flag + in the ISR register.
                  */ + __O uint32_t CGIF4 : 1; /*!< [16..16] Channel 4 global interrupt flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the GIF, TEIF, + HTIF and TCIF flags in the ISR register.
                  */ + __O uint32_t CTCIF4 : 1; /*!< [17..17] Channel 4 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF4 : 1; /*!< [18..18] Channel 4 half transfer flag. This bit is set by software.
                  • 0: No effect.
                  • 1: Clears the corresponding HTIF flag + in the ISR register.
                  */ + __O uint32_t CTEIF4 : 1; /*!< [19..19] Channel 4 transfer error flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the corresponding TEIF flag + in the ISR register.
                  */ + __O uint32_t CGIF5 : 1; /*!< [20..20] Channel 5 global interrupt flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the GIF, TEIF, + HTIF and TCIF flags in the ISR register.
                  */ + __O uint32_t CTCIF5 : 1; /*!< [21..21] Channel 5 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF5 : 1; /*!< [22..22] Channel 5 half transfer flag. This bit is set by software.
                  • 0: No effect.
                  • 1: Clears the corresponding HTIF flag + in the ISR register.
                  */ + __O uint32_t CTEIF5 : 1; /*!< [23..23] Channel 5 transfer error flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the corresponding TEIF flag + in the ISR register.
                  */ + __O uint32_t CGIF6 : 1; /*!< [24..24] Channel 6 global interrupt flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the GIF, TEIF, + HTIF and TCIF flags in the ISR register.
                  */ + __O uint32_t CTCIF6 : 1; /*!< [25..25] Channel 6 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF6 : 1; /*!< [26..26] Channel 6 half transfer flag. This bit is set by software.
                  • 0: No effect.
                  • 1: Clears the corresponding HTIF flag + in the ISR register.
                  */ + __O uint32_t CTEIF6 : 1; /*!< [27..27] Channel 6 transfer error flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the corresponding TEIF flag + in the ISR register.
                  */ + __O uint32_t CGIF7 : 1; /*!< [28..28] Channel 7 global interrupt flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the GIF, TEIF, + HTIF and TCIF flags in the ISR register.
                  */ + __O uint32_t CTCIF7 : 1; /*!< [29..29] Channel 7 transfer complete flag. This bit is set by + software.
                  • 0: No effect.
                  • 1: Clears the corresponding + TCIF flag in the ISR register.
                  */ + __O uint32_t CHTIF7 : 1; /*!< [30..30] Channel 7 half transfer flag. This bit is set by software.
                  • 0: No effect.
                  • 1: Clears the corresponding HTIF flag + in the ISR register.
                  */ + __O uint32_t CTEIF7 : 1; /*!< [31..31] Channel 7 transfer error flag. This bit is set by software.
                    0: No effect.
                  • 1: Clears the corresponding TEIF flag + in the ISR register.
                  */ + } IFCR_b; /*!< [32] BitSize */ + }; +} DMA_Type; + + +/* ================================================================================ */ +/* ================ DMA_CH [DMA_CH0] ================ */ +/* ================================================================================ */ + + +/** + * @brief DMA channel (DMA_CH) + */ + +typedef struct { /*!< (@ 0xA0000008) DMA_CH Structure */ + + union { + __IO uint32_t CCR; /*!< (@ 0xA0000008) DMA channel configuration register */ + + struct { + __IO uint32_t EN : 1; /*!< [0..0] DMA channel enable.
                  • 0: DMA channel disabled.
                  • 1: + DMA channel enabled.
                  */ + __IO uint32_t TCIE : 1; /*!< [1..1] Transfer complete interrupt enable.
                  • 0: TC interrupt + disabled.
                  • 1: TC interrupt enabled.
                  */ + __IO uint32_t HTIE : 1; /*!< [2..2] Half transfer interrupt enable.
                  • 0: HT interrupt + disabled.
                  • 1: HT interrupt enabled.
                  */ + __IO uint32_t TEIE : 1; /*!< [3..3] Transfer error interrupt enable.
                  • 0: TE interrupt + disabled.
                  • 1: TE interrupt enabled.
                  */ + __IO uint32_t DIR : 1; /*!< [4..4] Data transfer direction.
                  • 0: Read from peripheral.
                  • 1: + Read from memory.
                  */ + __IO uint32_t CIRC : 1; /*!< [5..5] Circular mode.
                  • 0: Circular mode disabled.
                  • 1: + Circular mode enabled.
                  */ + __IO uint32_t PINC : 1; /*!< [6..6] Peripheral increment mode.
                  • 0: Peripheral increment + disabled.
                  • 1: Peripheral increment enabled.
                  */ + __IO uint32_t MINC : 1; /*!< [7..7] Memory increment mode.
                  • 0: Memory increment disabled.
                  • 1: Memory increment enabled.
                  */ + __IO uint32_t PSIZE : 2; /*!< [8..9] Peripheral size.
                  • 00b: Size 8 bits.
                  • 01b: + Size 16 bits.
                  • 10b: Size 32 bits.
                  */ + __IO uint32_t MSIZE : 2; /*!< [10..11] Memory size.
                  • 00b: Size 8 bits.
                  • 01b: + Size 16 bits.
                  • 10b: Size 32 bits.
                  */ + __IO uint32_t PL : 2; /*!< [12..13] Channel priority level.
                  • 00b: Low priority.
                  • 01b: + Medium priority.
                  • 10b: High priority.
                  • 11b: Very + high priority.
                  */ + __IO uint32_t MEM2MEM : 1; /*!< [14..14] Memory to memory mode.
                  • 0: Memory to memory mode + disabled.
                  • 0: Memory to memory mode enabled.
                  */ + __I uint32_t RESERVED1 : 17; /*!< [15..31] Reserved */ + } CCR_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t CNDTR; /*!< (@ 0xA000000C) DMA channel number of data register. */ + + struct { + __IO uint32_t NDT : 16; /*!< [0..15] Number of data to be transferred (0 up to 65535). This + register can only be written when the channel is disabled. Once + the channel is enabled, this register is read-only, indicating + the remaining bytes to be transmitted. This register decrements + after each DMA transfer. Once the transfer is completed, this + register can either stay at zero or be reloaded automatically + by the value previously programmed if the channel is configured + in auto-reload mode. If this register is zero, no transaction + can be served w */ + __I uint32_t RESERVED1 : 16; /*!< [16..31] Reserved */ + } CNDTR_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t CPAR; /*!< (@ 0xA0000010) DMA channel peripheral address register */ + + struct { + __IO uint32_t PA : 32; /*!< [0..31] Base address of the peripheral data register from/to + which the data will be read/written. When PSIZE is 01 (16-bit), + the PA[0] bit is ignored. Access is automatically aligned to + a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. + Access is automatically aligned to a word address. */ + } CPAR_b; /*!< [32] BitSize */ + }; + + union { + __IO uint32_t CMAR; /*!< (@ 0xA0000014) DMA channel memory address register */ + + struct { + __IO uint32_t MA : 32; /*!< [0..31] Base address of the memory area from/to which the data + will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit + is ignored. Access is automatically aligned to a halfword address. + When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically + aligned to a word address. */ + } CMAR_b; /*!< [32] BitSize */ + }; +} DMA_CH_Type; + + +/* ================================================================================ */ +/* ================ RNG ================ */ +/* ================================================================================ */ + + +/** + * @brief RNG (RNG) + */ + +typedef struct { /*!< (@ 0xB0000000) RNG Structure */ + + union { + __IO uint32_t CR; /*!< (@ 0xB0000000) RNG configuration register */ + + struct { + uint32_t : 2; + __IO uint32_t DIS : 1; /*!< [2..2] Set the state of the random number generator.
                  • 0: + RNG is enable.
                  • 1: RNG is disabled. The internal free-running + oscillators are put in power-down mode and the RNG clock is + stopped at the input of the block.
                  */ + } CR_b; /*!< [3] BitSize */ + }; + + union { + __I uint32_t SR; /*!< (@ 0xB0000004) RNG status register */ + + struct { + __I uint32_t RDY : 1; /*!< [0..0] New random value ready.
                  • 0: The RNG_VAL register + value is not yet valid. If performing a read access to VAL, + the host will be put on hold (by wait-states insertion on the + AHB bus) until a random value is available.
                  • 1: The VAL + register contains a valid random number.
                  This bit remains + at 0 when the RNG is disabled (RNGDIS bit = 1b in CR) */ + } SR_b; /*!< [1] BitSize */ + }; + __I uint32_t VAL; /*!< (@ 0xB0000008) RNG 16 bit random value */ +} RNG_Type; + + +/* ================================================================================ */ +/* ================ PKA ================ */ +/* ================================================================================ */ + + +/** + * @brief PKA (PKA) + */ + +typedef struct { /*!< (@ 0xC0000000) PKA Structure */ + + union { + __IO uint32_t CSR; /*!< (@ 0xC0000000) Command and status register */ + + struct { + __O uint32_t GO : 1; /*!< [0..0] PKA start processing command:
                  • 0: has no effect.
                  • 1: + starts the processing.
                  After this bitfield is written + to 1, it must be written back to zero manually. */ + __I uint32_t READY : 1; /*!< [1..1] PKA readiness status:
                  • 0: the PKA is computing. + It is not ready.
                  • 1: the PKA is ready to start a new + processing.
                  The rising edge of the READY bit set the + PROC_END flag in the ISR register. */ + uint32_t : 5; + __O uint32_t SFT_RST : 1; /*!< [7..7] PKA software reset:
                  • 0: has no effect.
                  • 1: + reset the PKA peripheral.
                  After this bitfield is written + to 1, it must be written back to zero manually. */ + } CSR_b; /*!< [8] BitSize */ + }; + + union { + __IO uint32_t ISR; /*!< (@ 0xC0000004) Interrupt status register */ + + struct { + __IO uint32_t PROC_END : 1; /*!< [0..0] PKA process ending interrupt. When read:
                  • 0: no + event.
                  • 1: PKA process is ended.
                  When written:
                  • 0: + no effect.
                  • 1: clears the PKA process ending interrupt.
                  */ + uint32_t : 1; + __IO uint32_t RAM_ERR : 1; /*!< [2..2] RAM read / write access error interrupt. When read:
                  • 0: + All AHB read or write access to the PKA RAM occurred while the + PKA was stopped.
                  • 1: All the AHB read or write access + to the PKA RAM occurred while the PKA was operating and using + the internal RAM. Those read or write could not succeed as the + PKA internal RAM is disconnected from the AHB bus when the PKA + is operating (READY bit low).
                  When written:
                  • 0: + no effect.
                  • 1: clears the RAM access error interrupt.
                  */ + __IO uint32_t ADD_ERR : 1; /*!< [3..3] AHB address error interrupt. When read:
                  • 0: All + AHB read or write access to the PKA RAM occurred in a mapped + address range.
                  • 1: All AHB read or write access to the + PKA RAM occurred in an unmapped address range.
                  When + written:
                  • 0: no effect.
                  • 1: clears the AHB Address + error interrupt.
                  */ + } ISR_b; /*!< [4] BitSize */ + }; + + union { + __IO uint32_t IEN; /*!< (@ 0xC0000008) Interrupt enable register */ + + struct { + __IO uint32_t PROCEND_EN : 1; /*!< [0..0] Process ended interrupt enable.
                  • 0: interrupt disabled.
                    • < + li>1: interrupt enabled.
                  */ + uint32_t : 1; + __IO uint32_t RAMERR_EN : 1; /*!< [2..2] RAM access error interrupt enable.
                  • 0: interrupt + disabled.
                  • 1: interrupt enabled.
                  */ + __IO uint32_t ADDERR_EN : 1; /*!< [3..3] AHB address error interrupt enable.
                  • 0: interrupt + disabled.
                  • 1: interrupt enabled.
                  */ + } IEN_b; /*!< [4] BitSize */ + }; +} PKA_Type; + + +/* ================================================================================ */ +/* ================ ROM_INFO ================ */ +/* ================================================================================ */ + + +/** + * @brief ROM information (ROM_INFO) + */ + +typedef struct { /*!< (@ 0x10000000) ROM_INFO Structure */ + __I uint32_t RESERVED[4]; + __I uint32_t BOOTLOADER_VERSION; /*!< (@ 0x10000010) Bootloader Version */ + __I uint32_t RESERVED1; + __I uint32_t FLASH_WRITE; /*!< (@ 0x10000018) FLASH write function */ + __I uint32_t FLASH_ERASE; /*!< (@ 0x1000001C) FLASH erase function */ + __I uint32_t BOOTLOADER; /*!< (@ 0x10000020) Bootloader entry point */ + __I uint32_t RESERVED2[483]; + __I uint32_t BLD_TRIM; /*!< (@ 0x100007B0) BLD trimming value */ + __I uint32_t ADC_BLD_1V8_OFFSET; /*!< (@ 0x100007B4) ADC BLD 1V8 OFFSET */ + __I uint32_t ADC_BLD_1V8_VALUE; /*!< (@ 0x100007B8) ADC BLD 1V8 VALUE */ + __I uint32_t ADC_BLD_2V7_OFFSET; /*!< (@ 0x100007BC) ADC BLD 2V7 OFFSET */ + __I uint32_t ADC_BLD_2V7_VALUE; /*!< (@ 0x100007C0) ADC BLD 2V7 VALUE */ + __I uint32_t ADC_BLD_3V6_OFFSET; /*!< (@ 0x100007C4) ADC BLD 3V6 OFFSET */ + __I uint32_t ADC_BLD_3V6_VALUE; /*!< (@ 0x100007C8) ADC BLD 3V6 VALUE */ + __I uint32_t ADC_SE2_0V_OFFSET; /*!< (@ 0x100007CC) ADC SE2 0V OFFSET */ + __I uint32_t ADC_SE2_0V_VALUE; /*!< (@ 0x100007D0) ADC SE2 0V VALUE */ + __I uint32_t ADC_SE2_1V8_OFFSET; /*!< (@ 0x100007D4) ADC SE2 1V8 OFFSET */ + __I uint32_t ADC_SE2_1V8_VALUE; /*!< (@ 0x100007D8) ADC SE2 1V8 VALUE */ + __I uint32_t ADC_SE2_3V6_OFFSET; /*!< (@ 0x100007DC) ADC SE2 3V6 OFFSET */ + __I uint32_t ADC_SE2_3V6_VALUE; /*!< (@ 0x100007E0) ADC SE2 3V6 VALUE */ + __I uint16_t LDO1V2_TRIMM_CODE; /*!< (@ 0x100007E4) LDO 1V2 trimming code */ + __I uint16_t LDO1V2_TRIMMING_CODE_CHECK_BYTES; /*!< (@ 0x100007E6) LDO 1V2 trimming code check bytes */ + __I uint16_t RCO_TRIMMING_CODE; /*!< (@ 0x100007E8) RCO trimming code */ + __I uint16_t RCO_TRIMMING_CODE_CHECK_BYTES; /*!< (@ 0x100007EA) RCO trimming code check bytes */ + __I uint32_t RESERVED3[2]; + __I uint8_t UNIQUE_ID_1; /*!< (@ 0x100007F4) Unique ID 1st byte */ + __I uint8_t UNIQUE_ID_2; /*!< (@ 0x100007F5) Unique ID 2nd byte */ + __I uint8_t UNIQUE_ID_3; /*!< (@ 0x100007F6) Unique ID 3rd byte */ + __I uint8_t UNIQUE_ID_4; /*!< (@ 0x100007F7) Unique ID 4th byte */ + __I uint8_t UNIQUE_ID_5; /*!< (@ 0x100007F8) Unique ID 5th byte */ + __I uint8_t UNIQUE_ID_6; /*!< (@ 0x100007F9) Unique ID 6th byte */ + __I uint16_t UNIQUE_ID_CHECK_CODE; /*!< (@ 0x100007FA) Unique ID check code */ + __I uint32_t FLASH_PROTECTION_DISABLED; /*!< (@ 0x100007FC) ROM Lock Protection (not locked) */ +} ROM_INFO_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define GPIO_BASE 0x40000000UL +#define FLASH_BASE 0x40100000UL +#define SYSTEM_CTRL_BASE 0x40200000UL +#define UART_BASE 0x40300000UL +#define SPI_BASE 0x40400000UL +#define WDG_BASE 0x40700000UL +#define ADC_BASE 0x40800000UL +#define CKGEN_SOC_BASE 0x40900000UL +#define I2C2_BASE 0x40A00000UL +#define I2C1_BASE 0x40B00000UL +#define AHBUPCONV_BASE 0x40C00000UL +#define MFT1_BASE 0x40D00000UL +#define MFT2_BASE 0x40E00000UL +#define RTC_BASE 0x40F00000UL +#define BLUE_CTRL_BASE 0x48000000UL +#define CKGEN_BLE_BASE 0x48100000UL +#define DMA_BASE 0xA0000000UL +#define DMA_CH0_BASE 0xA0000008UL +#define DMA_CH1_BASE 0xA000001CUL +#define DMA_CH2_BASE 0xA0000030UL +#define DMA_CH3_BASE 0xA0000044UL +#define DMA_CH4_BASE 0xA0000058UL +#define DMA_CH5_BASE 0xA000006CUL +#define DMA_CH6_BASE 0xA0000080UL +#define DMA_CH7_BASE 0xA0000094UL +#define RNG_BASE 0xB0000000UL +#define PKA_BASE 0xC0000000UL +#define ROM_INFO_BASE 0x10000000UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define GPIO ((GPIO_Type *) GPIO_BASE) +#define FLASH ((FLASH_Type *) FLASH_BASE) +#define SYSTEM_CTRL ((SYSTEM_CTRL_Type *) SYSTEM_CTRL_BASE) +#define UART ((UART_Type *) UART_BASE) +#define SPI1 ((SPI_Type *) SPI_BASE) +#define WDG ((WDG_Type *) WDG_BASE) +#define ADC ((ADC_Type *) ADC_BASE) +#define CKGEN_SOC ((CKGEN_SOC_Type *) CKGEN_SOC_BASE) +#define I2C2 ((I2C_Type *) I2C2_BASE) +#define I2C1 ((I2C_Type *) I2C1_BASE) +#define AHBUPCONV ((AHBUPCONV_Type *) AHBUPCONV_BASE) +#define MFT1 ((MFT_Type *) MFT1_BASE) +#define MFT2 ((MFT_Type *) MFT2_BASE) +#define RTC ((RTC_Type *) RTC_BASE) +#define BLUE_CTRL ((BLUE_CTRL_Type *) BLUE_CTRL_BASE) +#define CKGEN_BLE ((CKGEN_BLE_Type *) CKGEN_BLE_BASE) +#define DMA ((DMA_Type *) DMA_BASE) +#define DMA_CH0 ((DMA_CH_Type *) DMA_CH0_BASE) +#define DMA_CH1 ((DMA_CH_Type *) DMA_CH1_BASE) +#define DMA_CH2 ((DMA_CH_Type *) DMA_CH2_BASE) +#define DMA_CH3 ((DMA_CH_Type *) DMA_CH3_BASE) +#define DMA_CH4 ((DMA_CH_Type *) DMA_CH4_BASE) +#define DMA_CH5 ((DMA_CH_Type *) DMA_CH5_BASE) +#define DMA_CH6 ((DMA_CH_Type *) DMA_CH6_BASE) +#define DMA_CH7 ((DMA_CH_Type *) DMA_CH7_BASE) +#define RNG ((RNG_Type *) RNG_BASE) +#define PKA ((PKA_Type *) PKA_BASE) +#define ROM_INFO ((ROM_INFO_Type *) ROM_INFO_BASE) + +#pragma message("SPI1 modificato") +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group BlueNRG2 */ +/** @} */ /* End of group STMicroelectronics */ + +#ifdef __cplusplus +} +#endif + + +#endif /* BlueNRG2_H */ + diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_ARMC6/BlueNRG2.sct b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_ARMC6/BlueNRG2.sct new file mode 100644 index 00000000000..0b72e135d56 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_ARMC6/BlueNRG2.sct @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#! armcc -E + +/* Device specific values */ +/* +BlueNRG-2 memory map ++-----------------------+ 0x20005FFF +| RAM (24K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1007FFFF +| | +| FLASH (256K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100007FF +| ROM (2K) | ++-----------------------+ 0x10000000 +*/ + +#define _RAM_START_ 0x20000000 +#define _RAM_SIZE_ 0x6000 /* 24KB */ +//#define _MEMORY_RAM_END_ 0x20005FFF + +#define _FLASH_START_ 0x10040000 +#define _FLASH_SIZE_ 0x40000 /* 256KB */ +//#define _MEMORY_FLASH_END_ 0x1007FFFF + +#define _ROM_START_ 0x10000000 +#define _ROM_SIZE_ 0x800 /* 2KB */ +//#define _MEMORY_ROM_END_ 0x100007FF + +/* Reserved for BTLE stack non volatile memory */ +#define _FLASH_NVM_DATASIZE_ (4*1024) + +#ifndef FLASH_APP_OFFSET +#define FLASH_APP_OFFSET (0) +#endif + +#ifndef FLASH_APP_SIZE +#define FLASH_APP_SIZE (_FLASH_SIZE_ - _FLASH_NVM_DATASIZE_ - FLASH_APP_OFFSET) +#endif + +#ifndef RAM_APP_OFFSET +#define RAM_APP_OFFSET (0x02CC) +#endif + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +#define VECTORS 48 /* This value must match NVIC_NUM_VECTORS */ + +/* Common - Do not change */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START _FLASH_START_ + FLASH_APP_OFFSET +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE _FLASH_SIZE_ - _FLASH_NVM_DATASIZE_ - FLASH_APP_OFFSET +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) +/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */ + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +//#define VECTORS_SIZE (((VECTORS * 4) + 7) AND ~7) +#define VECTORS_SIZE (VECTORS * 4) + +LR_IROM2 (_FLASH_START_) FLASH_APP_OFFSET { ; load region size_region + REGION_FLASH_BOOTLOADER (_FLASH_START_) (FLASH_APP_OFFSET) { ; load address = execution address + *.o (.bootloader) + } +} + +LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region + + ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address + *.o (.intvec, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + BLOCK_STACKLIB_FLASH_DATA (_FLASH_START_ + _FLASH_SIZE_ - _FLASH_NVM_DATASIZE_) UNINIT _FLASH_NVM_DATASIZE_ { + *.o (.noinit.stacklib_flash_data) + *.o (.noinit.stacklib_stored_device_id_data) + } + ota_sw_activation_block 0x20000004 UNINIT 4 { + *.o (.ota_sw_activation) + } + savedMSP_block 0x20000008 4 { + *.o (.savedMSP) + } + wakeupFromSleepFlag_block 0x2000000C 4 { + *.o (.wakeupFromSleepFlag) + } + app_base_block 0x20000010 4 { + *.o (.app_base) + } + flash_sw_lock_block 0x20000014 4 { + *.o (.flash_sw_lock) + } + Blue_Flag_Ram_block 0x20000030 4 { + *.o (.__blueflag_RAM) + } + Crash_Info_block 0x20000034 UNINIT 40 { + *.o (.__crash_RAM) + } + BLUE 0x200000C0 0x20C { + *.o (.bss.__blue_RAM) + } + REGION_RAM2 (_RAM_START_ + RAM_APP_OFFSET) (_RAM_SIZE_ - RAM_APP_OFFSET) { ; RW data + .ANY (+RW, +BSS) + } + REGION_RAM3 +0 UNINIT (_RAM_SIZE_ - RAM_APP_OFFSET) { ; RW data not initialized + *.o (.noinit.data) + } + + RW_IRAM1 (_RAM_START_ + VECTORS_SIZE + RAM_APP_OFFSET) { ; RW data + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (_RAM_START_ + _RAM_SIZE_ - 0XC00 - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + } + + ARM_LIB_STACK (_RAM_START_ + _RAM_SIZE_) EMPTY -0x00 { ; Stack region growing down + } + + REGION_ROM _ROM_START_ EMPTY _ROM_SIZE_ { } + ARM_LIB_STACKHEAP (_RAM_START_ + _RAM_SIZE_) EMPTY -0xC00 { } +} \ No newline at end of file diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_GCC_ARM/BlueNRG2.ld b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_GCC_ARM/BlueNRG2.ld new file mode 100644 index 00000000000..440067452b6 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_GCC_ARM/BlueNRG2.ld @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/******************************************************************************* +* Memory Definitions +* +* NOTE: The RAM region definition for mbed OS is intended starting with an offset +* of VECTORS_SIZE with respect to the RAM base address (to copy the vector +* table from the flash to the RAM in the M0 case, that doesn't have VTOR +* register). In this linker script implementation the RAM region address +* starts from the base address, to keep compatibility with the routines of +* BLUENRGx, that requires some definitions in the vector table region. +* +*******************************************************************************/ +/* +BlueNRG-2 memory map ++-----------------------+ 0x20005FFF +| RAM (24K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1003FFFF +| | +| FLASH (256K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100007FF +| ROM (2K) | ++-----------------------+ 0x10000000 +*/ + +/* Device specific values */ + +#define FLASH_START 0x10040000 +#define FLASH_SIZE 0x3FFFF //256KB +//#define FLASH_END 0x1007FFFF +#define RAM_START 0x20000000 +#define RAM_SIZE 0x6000 //24KB +//#define RAM_END 0x20005FFF +#define ROM_START 0x10000000 +#define ROM_SIZE 0x800 //2KB +//#define ROM_END 0x100007FF + +#define FLASH_APP_OFFSET 0 +#define FLASH_NVM_DATASIZE (4*1024) +#define MEMORY_RAM_APP_OFFSET 0x2cc + +#define VECTORS 48 /* This value must match NVIC_NUM_VECTORS */ + +/* Common - Do not change */ + +#if !defined(MBED_APP_START) + #define MBED_APP_START (FLASH_START + FLASH_APP_OFFSET) +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (FLASH_SIZE - FLASH_NVM_DATASIZE - FLASH_APP_OFFSET) +#endif + +/* Round up VECTORS_SIZE to 8 bytes */ +//#define VECTORS_SIZE (((VECTORS * 4) + 7) & 0xFFFFFFF8) +#define VECTORS_SIZE (VECTORS*4) + +MEMORY +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_SIZE + ROM(rx) : ORIGIN = ROM_START, LENGTH = ROM_SIZE + NVM (rx) : ORIGIN = FLASH_START + FLASH_SIZE + 1 - FLASH_NVM_DATASIZE, LENGTH = FLASH_NVM_DATASIZE + BOOTLOADER (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_APP_OFFSET +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(RESET_HANDLER) + +SECTIONS +{ + + /* The startup code goes first into FLASH */ + .bootloader (ORIGIN(BOOTLOADER)) : + { + . = ALIGN(4); + KEEP(*(.bootloader)) /* Startup code */ + . = ALIGN(4); + } > BOOTLOADER + + .rom_info (NOLOAD) : + { + . = ALIGN(4); + KEEP(*(.rom_info)) + . = ALIGN(4); + } > ROM + + /* The startup code goes first into FLASH */ +/* + .intvec (ORIGIN(FLASH)) : + { + . = ALIGN(4); + KEEP(*(.intvec)) // Startup code + . = ALIGN(4); + } > FLASH + */ + + .text : + { + . = ALIGN(4); + KEEP(*(.intvec)) /* Startup code */ + KEEP(*(.cmd_call_table)) + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(i.*) /* i.* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.constdata) + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + +///////////////--BLUENRG2 requirements memory section start--/////////////// + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + /* used by the startup to initialize data */ + _sidata2 = LOADADDR(.ram_preamble); + + /* RAM preamble no init */ + .ram_preamble_noinit 0x20000000 (NOLOAD) : + { + . = ALIGN(4); + . = 0x04 ; //There is a waste of RAM here + KEEP(*(.ota_sw_activation)) + } > RAM + +/* RAM preamble initialized */ + .ram_preamble 0x20000008 /*(NOLOAD)*/ : + { + _sdata2 = .; /* create a global symbol at data start */ + /* This is used by the startup in order to initialize the .bss section */ + KEEP(*(.savedMSP)) + . = 0x04 ; + KEEP(*(.wakeupFromSleepFlag)) + . = 0x08 ; + KEEP(*(.app_base)) + . = 0x0C ; + KEEP(*(.flash_sw_lock)) + . = 0x28 ; + KEEP(*(.__blueflag_RAM)) + _edata2 = .; /* create a global symbol at data end (.__crash_RAM is skipped since it must not be initialized) */ + } > RAM AT> FLASH + + /* Location counter can end up 2byte aligned with narrow Thumb code but + __etext is assumed by startup code to be the LMA of a section in RAM + which must be 4byte aligned */ + __etext = ALIGN (4); + + /* RAM preamble no init */ + .ram_preamble_noinit2 0x20000034 (NOLOAD) : + { + KEEP(*(.__crash_RAM)) + } > RAM + /* Uninitialized data section */ + + .bss.blueRAM 0x200000C0 : + { + . = ALIGN(4); + _sbssblue = .; // define a global symbol at .bss.blueRAM start + KEEP(*(.bss.__blue_RAM)) + . = ALIGN(4); + _ebssblue = .; // define a global symbol at .bss.blueRAM end + + . = 0x20c + MEMORY_RAM_APP_OFFSET - 0x2cc; + + } > RAM +///////////////--BLUENRG2 requirements memory section end--/////////////// + + .data : //AT (__etext) + { + _sdata = .; /* create a global symbol at data start */ + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + _edata = .; /* create a global symbol at data end */ + + } > RAM AT> FLASH + + .bss : + { + . = ALIGN(4); + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = .; + *(.bss.ev_call_table) + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; /* define a global symbol at bss end */ + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*); + . = ORIGIN(RAM) + LENGTH(RAM); //antonio + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + +///////////////--BLUENRG2 requirements memory section start--/////////////// + BLOCK_STACKLIB_FLASH_DATA (FLASH_START + FLASH_SIZE - FLASH_NVM_DATASIZE + 1) (NOLOAD) : + { + . = ALIGN(2048); + + KEEP(*(.noinit.stacklib_flash_data)) + KEEP(*(.noinit.stacklib_stored_device_id_data)) + + } > NVM +///////////////BLUENRG2 requirements memory section end--/////////////// + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop; //antonio - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + // Remove information from the standard libraries + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} \ No newline at end of file diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_IAR/BlueNRG2.icf b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_IAR/BlueNRG2.icf new file mode 100644 index 00000000000..55b1e703b89 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/TOOLCHAIN_IAR/BlueNRG2.icf @@ -0,0 +1,185 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +/******************************************************************************* +* Memory Definitions +*******************************************************************************/ +/* +BlueNRG-2 memory map ++-----------------------+ 0x20005FFF +| RAM (24K) | ++-----------------------+ 0x20000000 +| | +| | ++-----------------------+ 0x1007FFFF +| | +| FLASH (256K) | ++-----------------------+ 0x10040000 +| | ++-----------------------| 0x100007FF +| ROM (2K) | ++-----------------------+ 0x10000000 +*/ + +define symbol _RAM_START = 0x20000000; +define symbol _RAM_SIZE = 0x6000; /* 24KB */ +//define symbol _RAM_END_ = 0x20005FFF; + +define symbol _FLASH_START = 0x10040000; +define symbol _FLASH_SIZE = 0x40000; /* 256KB */ +//define symbol _FLASH_END_ = 0x1007FFFF; + +define symbol _ROM_START = 0x10000000; +define symbol _ROM_SIZE = 0x800; /* 2KB */ +//define symbol _ROM_END_ = 0x100007FF; + +/* Reserved for BTLE stack non volatile memory */ +define symbol _FLASH_NVM_DATASIZE = 4*1024; + +if( !isdefinedsymbol( _RAM_APP_OFFSET) ) { + define symbol _RAM_APP_OFFSET = 0x00; +} + +if( !isdefinedsymbol( _FLASH_APP_OFFSET) ) { + define symbol _FLASH_APP_OFFSET = 0; +} + +if( !isdefinedsymbol( _FLASH_APP_SIZE) ) { + define symbol _FLASH_APP_SIZE = _FLASH_SIZE - _FLASH_NVM_DATASIZE - _FLASH_APP_OFFSET; +} + +/* Device specific values */ + +/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ + +define symbol VECTORS = 48; /* This value must match NVIC_NUM_VECTORS */ +define symbol HEAP_SIZE = 0xC00 ; + +/* Common - Do not change */ + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = _FLASH_START + _FLASH_APP_OFFSET; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = _FLASH_SIZE - _FLASH_NVM_DATASIZE - _FLASH_APP_OFFSET; +} + +/* Round up VECTORS_SIZE to 8 bytes */ +//define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; +define symbol VECTORS_SIZE = (VECTORS * 4); + +define symbol RAM_REGION_START = _RAM_START + _RAM_APP_OFFSET + VECTORS_SIZE; +define symbol RAM_REGION_SIZE = _RAM_SIZE - VECTORS_SIZE; + +define memory mem with size = 4G; +define region FLASH_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; +define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; +define region REGION_FLASH_BOOTLOADER = mem:[from _FLASH_START to _FLASH_START + _FLASH_APP_OFFSET]; +define region REGION_FLASH_NVM = mem:[from _FLASH_START + _FLASH_SIZE - _FLASH_NVM_DATASIZE to _FLASH_START + _FLASH_SIZE -1]; +define region REGION_ROM = mem:[from _ROM_START to _ROM_START + _ROM_SIZE -1]; + +/******************************************************************************* +* ROM Sections +*******************************************************************************/ +define block ROM_INFO with alignment = 8, size = 0x800 { section .rom_info}; +keep {section .rom_info}; +place in REGION_ROM { block ROM_INFO, }; + +/******************************************************************************* +* BlueNRG-1 STACK Sections +*******************************************************************************/ +/** +* The last 2KB sector of FLASH is reserved for firmware to use. The BLE Host +* stores its security database in this area. The linker needs to make sure this +* 2KB sector is left empty. +*/ +define block BLOCK_STACKLIB_FLASH_DATA with alignment = 2048, fixed order +{ + section .noinit.stacklib_flash_data, + section .noinit.stacklib_stored_device_id_data +}; +place at start of REGION_FLASH_NVM {block BLOCK_STACKLIB_FLASH_DATA}; +do not initialize { section .noinit.stacklib_flash_data, + section .noinit.stacklib_stored_device_id_data}; + + +define block BLUE with alignment = 8, size = 0x20C { section .bss.__blue_RAM}; // Radio Global configuration data +keep {section .bss.__blue_RAM}; +place at address mem: 0x200000C0 { block BLUE, }; + +/******************************************************************************* +* FLASH Sections +*******************************************************************************/ + +place at start of REGION_FLASH_BOOTLOADER { readonly section .bootloader}; +place at start of FLASH_region { readonly section .intvec }; +keep {section .intvec}; + +/******************************************************************************* +* RAM Sections +*******************************************************************************/ +define block HEAP with alignment = 8, size = HEAP_SIZE { }; +define block CSTACK with alignment = 8, size = 0x400 { }; +//do not initialize { section CSTACK }; + +initialize by copy { readwrite }; +do not initialize {section .noinit}; + +/* OTA SW activation Block */ +define block ota_sw_activation_block with alignment = 4, size = 4 { section .ota_sw_activation}; +keep {section .ota_sw_activation}; +do not initialize {section .ota_sw_activation}; +place at address mem: 0x20000004 { block ota_sw_activation_block, }; + +/* savedMSP Block */ +define block savedMSP_block with alignment = 4, size = 4 { section .savedMSP}; +keep {section .savedMSP}; +place at address mem: 0x20000008 { block savedMSP_block, }; + +/* wakeupFromSleepFlag Block */ +define block wakeupFromSleepFlag_block with alignment = 4, size = 4 { section .wakeupFromSleepFlag}; +keep {section .wakeupFromSleepFlag}; +place at address mem: 0x2000000C { block wakeupFromSleepFlag_block, }; + +/* app_base Block - Software activation */ +define block app_base_block with alignment = 4, size = 4 { section .app_base}; +keep {section .app_base}; +place at address mem: 0x20000010 { block app_base_block, }; + +/* flash_sw_lock Block */ +define block flash_sw_lock_block with alignment = 4, size = 4 { section .flash_sw_lock}; +keep {section .flash_sw_lock}; +place at address mem: 0x20000014 { block flash_sw_lock_block, }; + +/* BLUE flag Ram Block - Software activation */ +define block Blue_Flag_Ram_block with alignment = 4, size = 4 { section .__blueflag_RAM}; +keep {section .__blueflag_RAM}; +place at address mem: 0x20000030 { block Blue_Flag_Ram_block, }; + + +/* Crash Handler Storage Information Block */ +define symbol CRASH_RAM_SIZE = 40; +define block Crash_Info_block with alignment = 4, size = CRASH_RAM_SIZE { section .__crash_RAM}; +keep {section .__crash_RAM}; +do not initialize {section .__crash_RAM}; +place at address mem: 0x20000034 { block Crash_Info_block, }; + +place in FLASH_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis.h new file mode 100644 index 00000000000..e2e06230f07 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis.h @@ -0,0 +1,25 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "bluenrg_x_device.h" +#include "cmsis_nvic.h" + +#endif diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis_nvic.c b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis_nvic.c new file mode 100644 index 00000000000..2bf282562e2 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis_nvic.c @@ -0,0 +1,40 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include "cmsis_nvic.h" +#include "BlueNRG1_flash.h" + +inline void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { + + // Copy from flash and switch to dynamic vectors if first time called + if(FLASH->CONFIG == FLASH_PREMAP_MAIN){ + volatile uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; + for (int i = 0; i < NVIC_NUM_VECTORS; i++) { + *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i*4))) = old_vectors[i]; + } + FLASH->CONFIG = FLASH_REMAP_RAM; + } + // Set the vector + *(uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn*4) + (NVIC_USER_IRQ_OFFSET*4)) = vector; +} + +uint32_t NVIC_GetVector(IRQn_Type IRQn) { + uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; + // Return the vector + return vectors[(uint32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis_nvic.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis_nvic.h new file mode 100644 index 00000000000..9c6234193db --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/cmsis_nvic.h @@ -0,0 +1,54 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F +// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF +// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM +#define NVIC_NUM_VECTORS 48 +//#define NVIC_USER_IRQ_OFFSET 16 + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NVIC_RAM_VECTOR_ADDRESS _MEMORY_RAM_BEGIN_ // Vectors positioned at start of RAM 0X20000000 +#define NVIC_FLASH_VECTOR_ADDRESS _MEMORY_FLASH_BEGIN_ // Initial vector position in flash 0X10000000 +/* +#ifndef FLASH_REMAP_RAM +#define FLASH_REMAP_RAM 0x0002U +#endif //flash_remap_ram + +#ifndef FLASH_PREMAP_MAIN +#define FLASH_PREMAP_MAIN 0x0008U +#endif //flash_premap_main +*/ +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +//#include "../../../Periph_Driver/inc/misc.h" + +#ifdef __cplusplus +} +#endif + +#endif //MBED_CMSIS_NVIC_H diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/system_bluenrg2.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/system_bluenrg2.h new file mode 100644 index 00000000000..ae75a8395cd --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/device/system_bluenrg2.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef SYSTEM_BLUENRG2_H +#define SYSTEM_BLUENRG2_H + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup system_bluenrg2 system bluenrg2 + * @{ + */ + +#include "compiler.h" +#include "hal_types.h" +#include +#include "system_bluenrg.h" + +/** @addtogroup system_bluenrg2_Exported_Constants Exported Constants + * @{ + */ + + +/** + * @brief RAM base address + */ +#define _MEMORY_RAM_BEGIN_ 0x20000000 +#define _MEMORY_RAM_SIZE_ 0x6000 /* 24KB */ +#define _MEMORY_RAM_END_ 0x20005FFF + +/** + * @brief User FLASH base address + */ +#define _MEMORY_FLASH_BEGIN_ 0x10040000 +#define _MEMORY_FLASH_SIZE_ 0x40000 /* 256KB */ +#define _MEMORY_FLASH_END_ 0x1007FFFF +#define _MEMORY_BYTES_PER_PAGE_ (2048) + +/** + * @brief ROM base address + */ +#define _MEMORY_ROM_BEGIN_ 0x10000000 +#define _MEMORY_ROM_SIZE_ 0x800 /* 2KB */ +#define _MEMORY_ROM_END_ 0x100007FF + +#define SystemCoreClock 32000000 // for IDB008V2 board +/** + * @} + */ + + +#endif /* SYSTEM_BLUENRG2_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/objects.h b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/objects.h new file mode 100644 index 00000000000..b796c2e9e07 --- /dev/null +++ b/targets/TARGET_STMBLUE/TARGET_BLUENRG2/TARGET_STEVAL_IDB008V2/objects.h @@ -0,0 +1,88 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "BlueNRG1_spi.h" +#include "BlueNRG1_uart.h" +#include "BlueNRG1_gpio.h" +#include "BlueNRG1_i2c.h" +#include "cmsis.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct{ + GPIO_InitType gpio; + PinName pin; +} gpio_t; + +struct gpio_irq_s{ + GPIO_EXTIConfigType exti; + uint32_t id; +}; + +struct serial_s{ + UARTName uart; + uint32_t index_irq; // Used by irq + UART_InitType init; //bluenrg struct + PinName pin_tx; + PinName pin_rx; +}; + +struct spi_s{ + SPI_InitType init; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; + char dummy_char; +}; + +struct i2c_s { + I2CName i2c; + I2C_InitType init; +// I2C_TransactionType t; + PinName sda; + PinName scl; +// IRQn_Type event_i2cIRQ; +// IRQn_Type error_i2cIRQ; +// uint32_t XferOperation; +// volatile uint8_t event; +// volatile int pending_start; +#if DEVICE_I2CSLAVE + uint8_t slave; + volatile uint8_t pending_slave_tx_master_rx; + volatile uint8_t pending_slave_rx_maxter_tx; +#endif +#if DEVICE_I2C_ASYNCH + uint32_t address; + uint8_t stop; + uint8_t available_events; +#endif +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STMBLUE/gpio_api.c b/targets/TARGET_STMBLUE/gpio_api.c new file mode 100644 index 00000000000..7da7eecd8a9 --- /dev/null +++ b/targets/TARGET_STMBLUE/gpio_api.c @@ -0,0 +1,81 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include "mbed_assert.h" // arm +#include "gpio_api.h" // arm +//#include "pinmap.h" // arm +#include "mbed_error.h" // arm +#include "device.h" +#include "BlueNRG1_gpio.h" +#include "BlueNRG1_sysCtrl.h" +//#include "objects.h" + +#define GPIOA_BASE GPIO_BASE + +uint32_t gpio_set(PinName pin) { + GPIO_InitInputPinx((uint32_t)pin); //cambiato + return (uint32_t)pin; //cambiato +} + +int gpio_is_connected(const gpio_t *obj){ + + if(obj->pin == NC) + return 0; + else + return 1; +} + +void gpio_init(gpio_t *obj, PinName pin) { + + if(pin==NC){ + obj->pin = NC; + return; + } + + obj->gpio.GPIO_Pin = (uint32_t)pin; + // preset + obj->gpio.GPIO_Mode = GPIO_Output; + obj->gpio.GPIO_Pull = ENABLE; + obj->gpio.GPIO_HighPwr = ENABLE; + /* Enable the GPIO Clock */ + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_GPIO, ENABLE); + + GPIO_Init(&(obj->gpio)); + obj->gpio.GPIO_Mode = GPIO_Output; +} + +void gpio_mode(gpio_t *obj, PinMode mode) { + uint8_t current_mode = obj->gpio.GPIO_Mode; + obj->gpio.GPIO_Pull = (FunctionalState)mode; + GPIO_Init(&(obj->gpio)); + obj->gpio.GPIO_Mode = current_mode; +} + +inline void gpio_dir(gpio_t *obj, PinDirection direction) { + obj->gpio.GPIO_Mode = (uint8_t)direction; + GPIO_Init(&(obj->gpio)); + obj->gpio.GPIO_Mode = direction; +} + +inline void gpio_write(gpio_t *obj, int value){ + value ? GPIO_WriteBit(obj->gpio.GPIO_Pin, Bit_SET) : GPIO_WriteBit(obj->gpio.GPIO_Pin, Bit_RESET); +} + +int gpio_read(gpio_t *obj){ + return GPIO_ReadBit(obj->gpio.GPIO_Pin) ? 1 : 0; +} diff --git a/targets/TARGET_STMBLUE/gpio_irq_api.c b/targets/TARGET_STMBLUE/gpio_irq_api.c new file mode 100644 index 00000000000..b24122f4646 --- /dev/null +++ b/targets/TARGET_STMBLUE/gpio_irq_api.c @@ -0,0 +1,105 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include "cmsis.h" +#include "gpio_irq_api.h" +#include "pinmap.h" +#include "BlueNRG1_gpio.h" + +static gpio_irq_handler irq_handler; +static gpio_irq_t *obj_ptr; + +void GPIO_Handler(void){ + //clear interrupt flag + if(GPIO_GetITStatusBit(obj_ptr->exti.GPIO_Pin) && GPIO_GetITPendingBit(obj_ptr->exti.GPIO_Pin)) + GPIO_ClearITPendingBit(obj_ptr->exti.GPIO_Pin); + irq_handler(obj_ptr->id, obj_ptr->exti.GPIO_Event); +} + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + if(pin == NC) + return -1; + NVIC_DisableIRQ(GPIO_IRQn); + obj_ptr = obj; + + obj->id = id; + GPIO_EXTIStructInit(&obj->exti); //default values + obj->exti.GPIO_IrqSense = GPIO_IrqSense_Edge; //fixed, mbed api does not support sense level interrupts + obj->exti.GPIO_Event = GPIO_Event_Both; //default value at initialization, used as control when fall and rise interrupts are required at the same time on the same pin + obj->exti.GPIO_Pin = (uint32_t)pin; + GPIO_EXTIConfig(&obj->exti); + + irq_handler = handler; + + NVIC_SetVector(GPIO_IRQn, (uint32_t)&GPIO_Handler); + + //GPIO_EXTICmd((uint32_t)pin, (FunctionalState)1); //////da rivedere + + NVIC_EnableIRQ(GPIO_IRQn); + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + GPIO_ClearITPendingBit(obj->exti.GPIO_Pin); + GPIO_EXTICmd(obj->exti.GPIO_Pin, DISABLE); +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + ///there is a mismatch between MBED enum gpio_irq_event and DK defines in BlueNRG1_gpio.h + ///mbed API : none=0, rise=1, fall=2 + ///DK defines: fall=0, rise=1, both=2 + /// + ///A lookup table is defined + gpio_irq_event event_new; + FunctionalState enable_new; + switch(event){ + case IRQ_NONE: + event_new = (gpio_irq_event)GPIO_Event_Both; //its initialize value + enable_new = DISABLE; + break; + case IRQ_RISE: + event_new = (gpio_irq_event)GPIO_Event_High; + enable_new = ENABLE; + break; + case IRQ_FALL: + event_new = (gpio_irq_event)GPIO_Event_Low; + enable_new = ENABLE; + break; + } + if(obj->exti.GPIO_Event != GPIO_Event_Both) + event_new = GPIO_Event_Both; + ///end of lut + obj->exti.GPIO_Event = event_new; + GPIO_EXTIConfig(&obj->exti); + obj->exti.GPIO_Event = event; //to avoid the IRQ_FALL to be mapped into IRQ_none + GPIO_EXTICmd(obj->exti.GPIO_Pin, (FunctionalState)enable_new); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + NVIC_EnableIRQ(GPIO_IRQn); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + NVIC_DisableIRQ(GPIO_IRQn); + NVIC_ClearPendingIRQ(GPIO_IRQn); +} diff --git a/targets/TARGET_STMBLUE/hal/inc/asm.h b/targets/TARGET_STMBLUE/hal/inc/asm.h new file mode 100644 index 00000000000..529ef07ec43 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/asm.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __ASM_H__ +#define __ASM_H__ + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +#if defined(__ICCARM__) || defined(__IAR_SYSTEMS_ASM__) +#define __CODE__ SECTION .text:CODE:REORDER:NOROOT(2) +#define __BSS__ SECTION .bss:DATA:NOROOT(2) +#define __EXPORT__ EXPORT +#define __IMPORT__ IMPORT +#define __THUMB__ THUMB +#define EXPORT_FUNC(f) f: +#define __END__ END +#define __SPACE__ DS8 +#define GLOBAL_VAR(val) val: +#define ENDFUNC +#define ALIGN_MEM(n) + +#else +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define __CODE__ AREA |.text|, CODE, READONLY +#define __THUMB__ +#define EXPORT_FUNC(f) f PROC +#define __BSS__ AREA |.bss|, DATA, READWRITE, NOINIT +#define __EXPORT__ EXPORT +#define __IMPORT__ IMPORT +#define __SPACE__ SPACE +#define GLOBAL_VAR(val) val +#define __END__ END +#define ENDFUNC ENDP +#define ALIGN_MEM(n) ALIGN n + +#else +#ifdef __GNUC__ +.syntax unified +.cpu cortex-m0 +.fpu softvfp +.thumb +#define __CODE__ .text +#define __BSS__ .bss +#define __EXPORT__ .global +#define __IMPORT__ .extern +#define __THUMB__ .thumb_func +#define __END__ .end +#define __SPACE__ .space +#define EXPORT_FUNC(f) f: +#define GLOBAL_VAR(val) val: +#define ENDFUNC +#define ALIGN_MEM(n) .align n>>1 + +#else + +#endif +#endif +#endif + +/* Change this define to 1 if zero-length arrays are not supported by your compiler. */ +//#ifndef __CC_ARM +//#define VARIABLE_SIZE 0 +//#else +//#define VARIABLE_SIZE 1 +//#endif + +#endif /* DOXYGEN_SHOULD_SKIP_THIS */ +#endif /* __ASM_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/bluenrg_x_device.h b/targets/TARGET_STMBLUE/hal/inc/bluenrg_x_device.h new file mode 100644 index 00000000000..62c272eb000 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/bluenrg_x_device.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef BLUENRG_X_DEVICE_H +#define BLUENRG_X_DEVICE_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup BlueNRG_x_device BlueNRG_x_device + * @{ + */ + +#ifdef BLUENRG2_DEVICE /* Reserved for Future Use: Do Not Enable it */ +#include "BlueNRG2.h" +#else +#include "BlueNRG1.h" +#endif + +/** @addtogroup BlueNRG_x_device_configuration Configuration + * @{ + */ + +/** + * @} + */ + +/** @addtogroup BlueNRG_x_device_Exported_Constants Exported Constants + * @{ + */ + + + + +/** + * @} + */ + +/** @addtogroup BlueNRG_x_device_Exported_Macros Exported Macros + * @{ + */ + + + +/** + * @} + */ + +/** @addtogroup BlueNRG_x_device_Exported_Typedefs Exported Typedefs + * @{ + */ + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* BLUENRG_X_DEVICE_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/targets/TARGET_STMBLUE/hal/inc/clock.h b/targets/TARGET_STMBLUE/hal/inc/clock.h new file mode 100644 index 00000000000..f1d5c36088f --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/clock.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __CLOCK_H__ +#define __CLOCK_H__ + +#include "BlueNRG_x_device.h" + +/** + * @brief Number of clocks in one seconds. + */ +extern const uint32_t CLOCK_SECOND; + +typedef uint32_t tClockTime; + +/** + * @brief This function initializes the clock library based on SysTick. + * + * @param None + * + * @retval None + */ +void Clock_Init(void); + +/** + * @brief This function returns the current system clock time. + * + * @param None + * + * @retval It returns current clock time, measured in system ticks. + */ +tClockTime Clock_Time(void); + + +/** + * @brief This function waits for a given number of milliseconds. + * + * @param i delay in milliseconds + * + * @retval None + */ +void Clock_Wait(uint32_t i); + +/** + * @brief This function is called on SysTick_Handler() + * + */ +void SysCount_Handler(void); + +#endif /* __CLOCK_H__ */ + diff --git a/targets/TARGET_STMBLUE/hal/inc/compiler.h b/targets/TARGET_STMBLUE/hal/inc/compiler.h new file mode 100644 index 00000000000..15fe54cce9f --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/compiler.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __COMPILER_H__ +#define __COMPILER_H__ + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +#define QUOTEME(a) #a + +/** @addtogroup compiler_macros compiler macros + * @{ + */ + + +/** @addtogroup IAR_toolchain_macros IAR toolchain macros + * @{ + */ + +/** + * @brief This is the section dedicated to IAR toolchain + */ +#if defined(__ICCARM__) || defined(__IAR_SYSTEMS_ASM__) + +/** + * @brief PACKED + * Use the PACKED macro for variables that needs to be packed. + * Usage: PACKED(struct) myStruct_s + * PACKED(union) myStruct_s + */ +#define PACKED(decl) __packed decl + +/** + * @brief REQUIRED + * Use the REQUIRED macro for variables that must be always included. + * Usage: REQUIRED(static uint8_t my_array[16]) + * REQUIRED(static int my_int) + */ +#define REQUIRED(decl) __root decl + +/** + * @brief NORETURN_FUNCTION + * Use the NORETURN_FUNCTION macro to declare a no return function. + * Usage: NORETURN_FUNCTION(void my_noretrun_function(void)) + */ +#define NORETURN_FUNCTION(function) __noreturn function + +/** + * @brief NOSTACK_FUNCTION + * Use the NOSTACK_FUNCTION macro to indicate that function should not use any stack. + * Typical usage is for hard fault handler, to avoid altering the value of the stack pointer. + * Usage: NOSTACK_FUNCTION(void my_noretrun_function(void)) + */ +#define NOSTACK_FUNCTION(function) __stackless function + +/** + * @brief SECTION + * Use the SECTION macro to assign data or code in a specific section. + * Usage: SECTION(".my_section") + */ +#define SECTION(name) _Pragma(QUOTEME(location=name)) + +/** + * @brief ALIGN + * Use the ALIGN macro to specify the alignment of a variable. + * Usage: ALIGN(4) + */ +#define ALIGN(v) _Pragma(QUOTEME(data_alignment=v)) + +/** + * @brief WEAK_FUNCTION + * Use the WEAK_FUNCTION macro to declare a weak function. + * Usage: WEAK_FUNCTION(int my_weak_function(void)) + */ +#define WEAK_FUNCTION(function) __weak function + +/** + * @brief NO_INIT + * Use the NO_INIT macro to declare a not initialized variable. + * Usage: NO_INIT(int my_no_init_var) + * Usage: NO_INIT(uint16_t my_no_init_array[10]) + */ +#define NO_INIT(var) __no_init var + +/** + * @brief NOLOAD + * Use the NOLOAD macro to declare a not initialized variable that + * must be placed in a specific section in Flash. + * Before the NOLOAD declaration, the SECTION declaration must be used. + * + * SECTION(".noinit.ro_section_my_noload_var") + * Usage: NOLOAD(int my_noload_var) + */ +#define NOLOAD(var) NO_INIT(var) + +/** + * @brief NO_INIT_ZERO + * Use the NO_INIT macro to declare a not initialized variable. + * Usage: NO_INIT(int my_no_init_var) + * Usage: NO_INIT(uint16_t my_no_init_array[10]) + */ +#define NO_INIT_ZERO(var, sect) __no_init var + +/** + * @brief NO_INIT_SECTION + * Use the NO_INIT_SECTION macro to declare a not initialized variable in RAM in + * in a specific section. + * Usage: NO_INIT_SECTION(int my_no_init_var, "MySection") + * Usage: NO_INIT_SECTION(uint16_t my_no_init_array[10], "MySection") + */ +#define NO_INIT_SECTION(var, sect) SECTION(sect) __no_init var + +#define VARIABLE_SIZE 0 +#pragma segment = "CSTACK" +#define _INITIAL_SP __sfe( "CSTACK" ) /* Stack address */ +extern void __iar_program_start(void); +#define RESET_HANDLER __iar_program_start + +/** @addtogroup Keil_toolchain_macros Keil toolchain macros + * @{ + */ + +/** + * @brief This is the section dedicated to Keil toolchain + */ +#else +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + +/** + * @brief PACKED + * Use the PACKED macro for variables that needs to be packed. + * Usage: PACKED(struct) myStruct_s + * PACKED(union) myStruct_s + */ +#define PACKED(decl) decl __attribute__((packed)) + +/** + * @brief REQUIRED + * Use the REQUIRED macro for variables that must be always included. + * Usage: REQUIRED(static uint8_t my_array[16]) + * REQUIRED(static int my_int) + */ +#define REQUIRED(decl) decl __attribute__((used)) + +/** + * @brief SECTION + * Use the SECTION macro to assign data or code in a specific section. + * Usage: SECTION(".my_section") + */ +#define SECTION(name) __attribute__((section(name))) + +/** + * @brief ALIGN + * Use the ALIGN macro to specify the alignment of a variable. + * Usage: ALIGN(4) + */ +#define ALIGN(N) __attribute__((aligned(N))) + +/** + * @brief WEAK_FUNCTION + * Use the WEAK_FUNCTION macro to declare a weak function. + * Usage: WEAK_FUNCTION(int my_weak_function(void)) + */ +#if defined(__CC_ARM) //armc5 +#define WEAK_FUNCTION(function) __weak function +#else //armc6 +#define WEAK_FUNCTION(function) __attribute__((weak)) function +#endif + +/** + * @brief NORETURN_FUNCTION + * Use the NORETURN_FUNCTION macro to declare a no return function. + * Usage: NORETURN_FUNCTION(void my_noretrun_function(void)) + */ +#define NORETURN_FUNCTION(function) __attribute__((noreturn)) function + +/** + * @brief NOSTACK_FUNCTION + * Use the NOSTACK_FUNCTION macro to indicate that function should not use any stack. + * Typical usage is for hard fault handler, to avoid altering the value of the stack pointer. + * In keil this is a dummy implementation since no equivalent function is available + * Usage: NOSTACK_FUNCTION(void my_noretrun_function(void)) + */ +#define NOSTACK_FUNCTION(function) function + +/** + * @brief NO_INIT + * Use the NO_INIT macro to declare a not initialized variable. + * Usage: NO_INIT(int my_no_init_var) + * Usage: NO_INIT(uint16_t my_no_init_array[10]) + */ +#define NO_INIT(var) var __attribute__((section("NoInit"))) + +/** + * @brief NOLOAD + * Use the NOLOAD macro to declare a not initialized variable that + * must be placed in a specific section in Flash. + * Before the NOLOAD declaration, the SECTION declaration must be used. + * Then, this section must be placed correctly in the linker file. + * + * SECTION(".noinit.ro_section_my_noload_var") + * Usage: NOLOAD(int my_noload_var) + */ +#define NOLOAD(var) var + +/** + * @brief NO_INIT_ZERO + * Use the NO_INIT macro to declare a not initialized variable. + * Usage: NO_INIT(int my_no_init_var) + * Usage: NO_INIT(uint16_t my_no_init_array[10]) + */ +#define NO_INIT_ZERO(var, sect) var __attribute__((section( sect ), zero_init)) + +/** + * @brief NO_INIT_SECTION + * Use the NO_INIT_SECTION macro to declare a not initialized variable that should be placed in a specific section. + * Linker script is in charge of placing that section in RAM. + * Usage: NO_INIT_SECTION(int my_no_init_var, "MySection") + * Usage: NO_INIT_SECTION(uint16_t my_no_init_array[10], "MySection") + */ +#define NO_INIT_SECTION(var, sect) var __attribute__((section( sect ), zero_init)) + + +extern void __main(void); +extern int main(void); +extern unsigned int Image$$ARM_LIB_STACKHEAP$$ZI$$Limit; +#define _INITIAL_SP (void(*)(void))&Image$$ARM_LIB_STACKHEAP$$ZI$$Limit /* Stack address */ +#define VARIABLE_SIZE 1 + +/** + * @} + */ + +/** @addtogroup Atollic_toolchain_macros Atollic toolchain macros + * @{ + */ + +/** + * @brief This is the section dedicated to Atollic toolchain + */ +#else +#ifdef __GNUC__ + +/** + * @brief PACKED + * Use the PACKED macro for variables that needs to be packed. + * Usage: PACKED(struct) myStruct_s + * PACKED(union) myStruct_s + */ +#ifndef PACKED +#define PACKED(decl) decl __attribute__((packed)) +#endif +/** + * @brief REQUIRED + * Use the REQUIRED macro for variables that must be always included. + * Usage: REQUIRED(static uint8_t my_array[16]) + * REQUIRED(static int my_int) + */ +#define REQUIRED(var) var __attribute__((used)) + +/** + * @brief SECTION + * Use the SECTION macro to assign data or code in a specific section. + * Usage: SECTION(".my_section") + */ +#define SECTION(name) __attribute__((section(name))) + +/** + * @brief ALIGN + * Use the ALIGN macro to specify the alignment of a variable. + * Usage: ALIGN(4) + */ +#define ALIGN(N) __attribute__((aligned(N))) + +/** + * @brief WEAK_FUNCTION + * Use the WEAK_FUNCTION macro to declare a weak function. + * Usage: WEAK_FUNCTION(int my_weak_function(void)) + */ +#define WEAK_FUNCTION(function) __attribute__((weak)) function + +/** + * @brief NORETURN_FUNCTION + * Use the NORETURN_FUNCTION macro to declare a no return function. + * Usage: NORETURN_FUNCTION(void my_noretrun_function(void)) + */ +#define NORETURN_FUNCTION(function) __attribute__((noreturn)) function + +/** + * @brief NOSTACK_FUNCTION + * Use the NOSTACK_FUNCTION macro to indicate that function should not use any stack. + * Typical usage is for hard fault handler, to avoid altering the value of the stack pointer. + * Usage: NOSTACK_FUNCTION(void my_noretrun_function(void)) + */ +#define NOSTACK_FUNCTION(function) __attribute__((naked)) function + +/** + * @brief NO_INIT + * Use the NO_INIT macro to declare a not initialized variable. + * Usage: NO_INIT(int my_no_init_var) + * Usage: NO_INIT(uint16_t my_no_init_array[10]) + */ +#define NO_INIT(var) var __attribute__((section(".noinit"))) + +/** + * @brief NOLOAD + * Use the NOLOAD macro to declare a not initialized variable that + * must be placed in a specific section in Flash. + * Before the NOLOAD declaration, the SECTION declaration must be used. + * Then, this section must be placed correctly in the linker file. + * + * SECTION(".noinit.ro_section_my_noload_var") + * Usage: NOLOAD(int my_noload_var) + */ +#define NOLOAD(var) var + +/** + * @brief NO_INIT_ZERO + * Use the NO_INIT macro to declare a not initialized variable. + * Usage: NO_INIT(int my_no_init_var) + * Usage: NO_INIT(uint16_t my_no_init_array[10]) + */ +#define NO_INIT_ZERO(var, sect) var// __attribute__((section(".noinit"))) + +/** + * @brief NO_INIT_SECTION + * Use the NO_INIT_SECTION macro to declare a not initialized variable. + * In order to work properly this macro should be aligned with the linker file. + * Usage: NO_INIT_SECTION(int my_no_init_var, "MySection") + * Usage: NO_INIT_SECTION(uint16_t my_no_init_array[10], "MySection") + */ +#define NO_INIT_SECTION(var, sect) var __attribute__((section(sect))) + +#define _INITIAL_SP (void(*)(void))(&_estack) +#define VARIABLE_SIZE 0 + +/** + * @} + */ + +#else + +#error Neither ICCARM, CC ARM nor GNUC C detected. Define your macros. + +#endif +#endif +#endif + +/** + * @} + */ + +#endif /* DOXYGEN_SHOULD_SKIP_THIS */ +#endif /* __COMPILER_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/crash_handler.h b/targets/TARGET_STMBLUE/hal/inc/crash_handler.h new file mode 100644 index 00000000000..bc5dd7d22b9 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/crash_handler.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __CRASH_HANDLER_H_ +#define __CRASH_HANDLER_H_ + +#include +#include + +/** + * @brief Number of word for the Exception RAM Locations + */ +#define NMB_OF_EXCEP_RAM_WORD 10 + +/** + * @brief Base address to store the Crash Information + */ +#define CRASH_RAM_SIZE 40 + +/** + * @brief Signature Information: CRASH_SIGNATURE_BASE + */ +#define CRASH_SIGNATURE_BASE 0xBCEC0000 +/** + * @brief Signature Information: ASSERT_SIGNATURE + */ +#define ASSERT_SIGNATURE (CRASH_SIGNATURE_BASE + 0) +/** + * @brief Signature Information: NMI_SIGNATURE + */ +#define NMI_SIGNATURE (CRASH_SIGNATURE_BASE + 1) +/** + * @brief Signature Information: HARD_FAULT_SIGNATURE + */ +#define HARD_FAULT_SIGNATURE (CRASH_SIGNATURE_BASE + 2) +/** + * @brief Signature Information: WATCHDOG_SIGNATURE + */ +#define WATCHDOG_SIGNATURE (CRASH_SIGNATURE_BASE +3) + +/** + * @brief Typedef for the overall crash information (stack pointer, programm counter, registers, ...) + */ +typedef PACKED(struct) crash_infoS { + uint32_t signature; + uint32_t SP; + uint32_t R0; + uint32_t R1; + uint32_t R2; + uint32_t R3; + uint32_t R12; + uint32_t LR; + uint32_t PC; + uint32_t xPSR; +} crash_info_t; + + +extern crash_info_t crash_info_ram; + +/** + * @brief Macro to store in RAM the register information where an assert is verified. + * + * All the information stored are words (32 bit): + * - Assert Signature + * - SP + * - R0 + * - R1 + * - R2 + * - R3 + * - R12 + * - LR + * - PC + * - xPSR + */ +#define ASSERT_HANDLER(expression) { \ + volatile uint32_t * crash_info = (volatile uint32_t *)&crash_info_ram; \ + register uint32_t reg_content; \ + if (!(expression)) { \ + /* Init to zero the crash_info RAM locations */ \ + for (reg_content=0; reg_content +#ifndef __FIFO_H__ +#define __FIFO_H__ + +typedef struct circular_fifo_s { + uint16_t tail; + uint16_t head; + uint16_t max_size; + uint8_t *buffer; + uint8_t alignment; +} circular_fifo_t; + +void fifo_init(circular_fifo_t *fifo, uint16_t max_size, uint8_t *buffer, uint8_t alignment); +uint16_t fifo_size(circular_fifo_t *fifo); +uint8_t fifo_put(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer); +uint8_t fifo_put_var_len_item(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer); +uint8_t fifo_get(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer); +uint8_t fifo_discard(circular_fifo_t *fifo, uint16_t size); +uint8_t fifo_get_ptr(circular_fifo_t *fifo, uint16_t size, uint8_t **ptr); +uint8_t fifo_get_var_len_item(circular_fifo_t *fifo, uint16_t *size, uint8_t *buffer); +uint8_t fifo_get_ptr_var_len_item(circular_fifo_t *fifo, uint16_t *size, uint8_t **ptr); +uint8_t fifo_discard_var_len_item(circular_fifo_t *fifo); +void fifo_flush(circular_fifo_t *fifo); +#endif /* __FIFO_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/gp_timer.h b/targets/TARGET_STMBLUE/hal/inc/gp_timer.h new file mode 100644 index 00000000000..bea1e46a5e4 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/gp_timer.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __GP_TIMER_H__ +#define __GP_TIMER_H__ + +#include "clock.h" + +/** + * @brief Timer structure. Use Timer_Set() to set the timer. + * + */ +struct timer { + tClockTime start; + tClockTime interval; +}; + +/** + * @brief This function sets a timer for a specific time. + * The function Timer_Expired() returns true if + * the timer has expired. + * + * @param[in] t Pointer to timer + * @param[in] interval The interval before the timer expires. + * + * @retval None + */ +void Timer_Set(struct timer *t, tClockTime interval); + +/** + * @brief This function resets the same interval that was + * given to the Timer_Set() function. The starting point of the interval is + * the last timer value when timer expired. Using this function + * makes the timer being stable over time. + * + * @param[in] t Pointer to timer + * + * @retval None + */ +void Timer_Reset(struct timer *t); + +/** + * @brief This function resets the same interval that was + * given to the Timer_Set() function. The starting point of the interval is + * the current time. For a stable timer over time, it is recommended to use + * the Timer_Reset() function. + * + * @param[in] t Pointer to timer + * + * @retval None + */ +void Timer_Restart(struct timer *t); + +/** + * @brief This function verifies if a timer has expired. + * + * @param[in] t Pointer to timer + * + * @retval 1 if the timer has expired, 0 if not expired. + */ +uint8_t Timer_Expired(struct timer *t); + +/** + * @brief This function returns the remaining time before the timer expires. + * + * @param[in] t Pointer to timer + * + * @retval The remaining time. + */ +tClockTime Timer_Remaining(struct timer *t); + +#endif /* __GP_TIMER_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/hal_radio.h b/targets/TARGET_STMBLUE/hal/inc/hal_radio.h new file mode 100644 index 00000000000..67278cd6d69 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/hal_radio.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __HAL_RADIO_H_ +#define __HAL_RADIO_H_ + +#include "../../Periph_Driver/inc/BlueNRG1_radio.h" + + +uint8_t HAL_RADIO_SendPacket(uint8_t channel, + uint32_t wakeup_time, + uint8_t* txBuffer, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) ); + +uint8_t HAL_RADIO_SendPacketWithAck(uint8_t channel, + uint32_t wakeup_time, + uint8_t* txBuffer, + uint8_t* rxBuffer, + uint32_t receive_timeout, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) + ); + +uint8_t HAL_RADIO_ReceivePacket(uint8_t channel, + uint32_t wakeup_time, + uint8_t* rxBuffer, + uint32_t receive_timeout, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) ); + +uint8_t HAL_RADIO_ReceivePacketWithAck(uint8_t channel, + uint32_t wakeup_time, + uint8_t* rxBuffer, + uint8_t* txBuffer, + uint32_t receive_timeout, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) + ); + +uint8_t HAL_RADIO_SetNetworkID(uint32_t ID); + + +#endif /* __HAL_RADIO_H_ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/hal_types.h b/targets/TARGET_STMBLUE/hal/inc/hal_types.h new file mode 100644 index 00000000000..f1496f53a26 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/hal_types.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __HAL_TYPES_H__ +#define __HAL_TYPES_H__ + +#include + +/**@brief RESET,SET definition */ +typedef enum {RESET = 0, SET} FlagStatus, ITStatus; +/**@brief Macro that checks if STATE is a FlagStatus / ITStatus */ +#define IS_FLAGSTATUS(STATE) (((STATE) == RESET) || ((STATE) == SET)) +#define IS_ITSTATUS(STATE) IS_FLAGSTATUS(STATE) + +/**@brief DISABLE, ENABLE definition */ +typedef enum {DISABLE = 0, ENABLE} FunctionalState; +/** @brief Macro that checks if STATE is a FunctionalState */ +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {SUCCESS = 0, ERROR} ErrorStatus; +/** @brief Macro that checks if STATE is a ErrorStatus */ +#define IS_ERROR_STATE(STATE) (((STATE) == SUCCESS) || ((STATE) == ERROR)) + + +/** @brief Macro that stores Value into a buffer in Little Endian Format (2 bytes)*/ +#define HOST_TO_LE_16(buf, val) ( ((buf)[0] = (uint8_t) (val) ) , \ + ((buf)[1] = (uint8_t) (val>>8) ) ) + +/** @brief Macro that stores Little Endian Format into a buffer value */ +#define LE_TO_HOST_32(ptr) (uint32_t) ( ((uint32_t) \ + *((uint8_t *)ptr)) | \ + ((uint32_t) \ + *((uint8_t *)ptr + 1) << 8) | \ + ((uint32_t) \ + *((uint8_t *)ptr + 2) << 16) | \ + ((uint32_t) \ + *((uint8_t *)ptr + 3) << 24) ) + +/** @brief Macro that stores Value into a buffer in Little Endian Format (4 bytes) */ +#define HOST_TO_LE_32(buf, val) ( ((buf)[0] = (uint8_t) (val) ) , \ + ((buf)[1] = (uint8_t) (val>>8) ) , \ + ((buf)[2] = (uint8_t) (val>>16) ) , \ + ((buf)[3] = (uint8_t) (val>>24) ) ) + +/** @brief Booelan definition */ +typedef uint8_t BOOL; + +/**@brief TRUE, FALSE definition */ +//#define TRUE ((BOOL)1U) +//#define FALSE ((BOOL)0U) + +#define TRUE 1 +#define FALSE 0 + +#endif /* __HAL_TYPES_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/miscutil.h b/targets/TARGET_STMBLUE/hal/inc/miscutil.h new file mode 100644 index 00000000000..40f5d7ac5aa --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/miscutil.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __MISCUTIL_H__ +#define __MISCUTIL_H__ + +#include +#include "crash_handler.h" +#include "compiler.h" + + +#define DIE_ID_BLUENRG2 ((uint8_t)2) +#define DIE_ID_BLUENRG1 ((uint8_t)1) + + +/** + * @brief A structure that represents part information details + * + */ +typedef struct PartInfoS { + /** DIE ID number */ + uint8_t die_id; + /** Die major number */ + uint8_t die_major; + /** Die cut number */ + uint8_t die_cut; + /** JTAG ID */ + uint32_t jtag_id_code; + /** Flash size in bytes */ + uint32_t flash_size; +} PartInfoType; + +/** + * @brief This function return a structure with information about the device + * + * @param[out] partInfo Pointer to a PartInfoType structure + * + * @retval None + */ +void HAL_GetPartInfo(PartInfoType *partInfo); +/** + * @brief Get Crash Information utility + * + * This function return the crash information that are stored in RAM, by hard + * handler, nmi handler and assert handler. + * This function reset the crash information stored in RAM before it returns. + * So it avoid to report the same crash information after a normal reboot. + * + * @param[out] crashInfo Pointer to a crash_info_t structure + * + * @retval None + */ +void HAL_GetCrashInfo(crash_info_t *crashInfo); +/** + * @brief Set Crash Information utility + * + * This function stores crash information in RAM and reset the device + * Crash information can be retrieved by using API HAL_GetCrashInfo + * + * @param[in] msp Stack pointer containg crash info + * @param[out] signature CRash reason signature + * + * @retval None + */ +void HAL_CrashHandler(uint32_t msp, uint32_t signature); + +/** + * @brief Get Device ID, Version and Revision numbers + * + * This function returns the device ID, version and revision numbers. + * To be called by the BLE Stack for ensuring platform independence. + * + * @param[out] device_id Device ID (1 = BlueNRG-1; 2 = BlueNRG-2) + * @param[out] major_cut Device cut version/major number + * @param[out] minor_cut Device cut revision/minor number + * + * @retval None + */ +void BLEPLAT_get_part_info(uint8_t *device_id, uint8_t *major_cut, uint8_t *minor_cut); + +#endif /* __MISCUTIL_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/osal.h b/targets/TARGET_STMBLUE/hal/inc/osal.h new file mode 100644 index 00000000000..ac828a30d70 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/osal.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#ifndef __OSAL_H__ +#define __OSAL_H__ + +/****************************************************************************** + * Includes + *****************************************************************************/ + +/****************************************************************************** + * Macros + *****************************************************************************/ + + +/****************************************************************************** + * Function Prototypes + *****************************************************************************/ + +/** + * @brief This function copies size number of bytes from a + * memory location pointed by src to a destination + * memory location pointed by dest + * + * @param[in] dest Destination address + * @param[in] src Source address + * @param[in] size size in the bytes + * + * @return Address of the destination + */ + +#ifdef __cplusplus +extern "C" { +#endif + +extern void* Osal_MemCpy(void *dest,const void *src, unsigned int size); + + +/** + * @brief This function sets first number of bytes, specified + * by size, to the destination memory pointed by ptr + * to the specified value + * + * @param[in] ptr Destination address + * @param[in] value Value to be set + * @param[in] size Size in the bytes + * + * @return Address of the destination + */ + +extern void* Osal_MemSet(void *ptr, int value, unsigned int size); + +/** + * @brief This function compares n bytes of two regions of memory + * + * @param[in] s1 First buffer to compare. + * @param[in] s2 Second buffer to compare. + * @param[in] size Number of bytes to compare. + * + * @return 0 if the two buffers are equal, 1 otherwise + */ +extern int Osal_MemCmp(void *s1,void *s2,unsigned int size); + +#ifdef __cplusplus +} +#endif + +#endif /* __OSAL_H__ */ diff --git a/targets/TARGET_STMBLUE/hal/inc/system_bluenrg.h b/targets/TARGET_STMBLUE/hal/inc/system_bluenrg.h new file mode 100644 index 00000000000..6b6f7307be0 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/inc/system_bluenrg.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef SYSTEM_BLUENRG_H +#define SYSTEM_BLUENRG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup system_bluenrg system bluenrg + * @{ + */ + +/** @addtogroup system_bluenrg_device_configuration Device Configuration Constants + * @{ + */ + +/** + * @brief High Speed crystal 32 MHz + */ +#define HS_SPEED_XTAL_32MHZ 1 + +/** + * @brief High Speed crystal 16 MHz + */ +#define HS_SPEED_XTAL_16MHZ 2 + +/** + * @brief High Speed Internal RO + * Not useful when radio operation are needed + * or in any case when accurate ref clock is needed. + */ +#define HS_SPEED_XTAL_INTERNAL_RO 3 + + +/** + * @brief Low Speed Internal RO + */ +#define LS_SOURCE_INTERNAL_RO 1 + +/** + * @brief Low Speed External 32 KHz + */ +#define LS_SOURCE_EXTERNAL_32KHZ 2 + +/** + * @brief SMPS Inductor 10 uH + */ +#define SMPS_INDUCTOR_10uH 1 + +/** + * @brief SMPS Inductor 4.7 uH + */ +#define SMPS_INDUCTOR_4_7uH 2 + +/** + * @brief SMPS Inductor None + */ +#define SMPS_INDUCTOR_NONE 3 + +/** + * @brief BOR OFF + */ +#define BOR_OFF 1 + +/** + * @brief BOR ON + */ +#define BOR_ON 2 + +/*Device version to apply the BOR/BLD settings*/ +#define WA_DEVICE_VERSION 0x12 + +/** + * @brief Word to unlock the flash operation + */ +#define FLASH_UNLOCK_WORD 0xFCECBCCC + +/** + * @brief Word to lock the flash operation + */ +#define FLASH_LOCK_WORD 0 + + /** + * @brief High Speed Crystal default configuration + */ +#ifndef HS_SPEED_XTAL +#define HS_SPEED_XTAL HS_SPEED_XTAL_16MHZ +#endif + +/** + * @brief Low Speed Crystal default source + */ +#ifndef LS_SOURCE +#define LS_SOURCE LS_SOURCE_EXTERNAL_32KHZ +#endif + +/** + * @brief SMPS default configuration + */ +#ifndef SMPS_INDUCTOR +#define SMPS_INDUCTOR SMPS_INDUCTOR_10uH +#endif + +/** + * @brief BOR default configuration + */ +#ifndef BOR_CONFIG +#define BOR_CONFIG BOR_ON +#endif + +/** + * @} + */ + + +/** @addtogroup system_bluenrg_Exported_Macros Exported Macros + * @{ + */ + + + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function which reports + * the name of the source file and the source line number of the call + * that failed. If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +/** + * @} + */ + +/** @addtogroup system_bluenrg_Exported_Typedefs Exported Typedefs + * @{ + */ + +typedef void( *intfunc )( void ); +typedef union { intfunc __fun; void * __ptr; } intvec_elem; + + +typedef uint16_t BlueTransBlueStrctPtr_t; +typedef uint16_t BlueTransBlueDataPtr_t; + +typedef struct +{ + volatile uint16_t Config; // 1:0 + volatile uint16_t period_slow; // 3:2 + volatile uint8_t unused; // 4 + volatile uint8_t TxDelay; // 5 + volatile uint8_t RcvDelay; // 6 + volatile uint8_t TxDelay1; // 7 + volatile uint8_t RcvDelay1; // 8 + volatile uint8_t wakeup_time_offset; // 9 + volatile BlueTransBlueDataPtr_t RadioConfigPtr; // 10:11 +} BlueGlob; + +typedef struct +{ + volatile uint8_t Pack_count_Tx[5]; // 4:0 + volatile uint8_t Pack_count_Rcv[5]; // 9:5 + volatile uint8_t stat_config; // 10 + /*volatile uint8_t rcv_fail_count;*/ + volatile uint8_t unmapped_chan; // 11 + volatile BlueTransBlueStrctPtr_t txpoint_prev; // 13:12 + volatile BlueTransBlueStrctPtr_t rcvpoint_prev; // 15:14 + volatile BlueTransBlueStrctPtr_t txpoint; // 17:16 + volatile BlueTransBlueStrctPtr_t rcvpoint; // 19:18 + volatile BlueTransBlueStrctPtr_t txpoint_next; // 21:20 + volatile uint8_t remap_chan; // 22 + volatile uint8_t config; // 23 + volatile uint32_t access_address; // 27:24 + volatile uint32_t crc_init; // 31:28 + /* volatile uint8_t rcv_fail_trig;*/ + volatile uint8_t hop_incr; // 32 + volatile uint8_t chan_remap[5]; // 37:33 + volatile uint8_t enc_iv[8]; // 45:38 + volatile uint8_t enc_key[16]; // 61:46 + volatile uint8_t conf_byte5; // 62 + volatile uint8_t unused; // 63 +} BlueGlobPerMaster; + + +typedef struct +{ + BlueGlob BlueGlobVar; + BlueGlobPerMaster BlueGlobPerMasterVar[8]; + +} __blue_RAM_struct; + + +/** + * @} + */ + + +/** @addtogroup system_bluenrg_Exported_Variables Exported Variables + * @{ + */ + + +extern __blue_RAM_struct __blue_RAM; +extern const intvec_elem __vector_table[]; +extern uint32_t savedICSR; +extern uint32_t savedSHCSR; +extern uint32_t savedNVIC_ISPR; +extern volatile uint8_t wakeupFromSleepFlag; +extern volatile uint32_t ota_sw_activation; +extern volatile uint32_t flash_sw_lock; + +/** + * @} + */ + + +/** @addtogroup system_bluenrg_Exported_Functions Exported Functions + * @{ + */ + +/* Important note: The __low_level_init_CS() function is critical for waking up from + deep sleep and it should not use more that 10 stack positions + otherwise a stack corruption will occur when waking up from deep sleep. + For this reason we are saving and restoring the first 10 words of the stack that + will be corrupted during the wake-up procedure from deep sleep. + If the __low_level_init_CS() will be modified, this define shall be modifed according + the new function implementation +*/ +#define CSTACK_PREAMBLE_NUMBER 10 + + +void SystemInit(void); +void DeviceConfiguration(BOOL coldStart, BOOL waitLS_Ready); +void BOR_ConfigSave(uint8_t clock_low_eng_conf, uint8_t pmu_ana_user_conf); +void SET_BORconfigStatus(uint8_t enabled); +void Set_RF_FrontEnd(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_BLUENRG_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/targets/TARGET_STMBLUE/hal/src/clock.c b/targets/TARGET_STMBLUE/hal/src/clock.c new file mode 100644 index 00000000000..41ec585ce25 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/clock.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" +//#include "BlueNRG1_conf.h" +#include "clock.h" + +/** @addtogroup BlueNRG1_StdPeriph_Examples +* @{ +*/ + +/** @addtogroup UART Interrupt Example +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +#if ((HS_SPEED_XTAL == HS_SPEED_XTAL_32MHZ)&&(FORCE_CORE_TO_16MHZ != 1)) + #define SYSCLK_FREQ 32000000 /* System clock frequency */ +#elif (HS_SPEED_XTAL == HS_SPEED_XTAL_16MHZ)||(FORCE_CORE_TO_16MHZ == 1) + #define SYSCLK_FREQ 16000000 /* System clock frequency */ +#else +#error "No definition for SYSCLK_FREQ" +#endif + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +static volatile tClockTime sys_tick_count; +const tClockTime CLOCK_SECOND = 1000; + +/*---------------------------------------------------------------------------*/ +void SysCount_Handler(void) +{ + sys_tick_count++; +} + +/*---------------------------------------------------------------------------*/ + +void Clock_Init(void) +{ + /** Configure SysTick to generate Interrupt with 1ms period */ + SysTick_Config(SYSCLK_FREQ/1000 - 1); +} + +/*---------------------------------------------------------------------------*/ + +tClockTime Clock_Time(void) +{ + return sys_tick_count; +} + +/*---------------------------------------------------------------------------*/ +/** + * Wait for a multiple of 1 ms. + * + */ +void Clock_Wait(uint32_t i) +{ + tClockTime start; + + start = Clock_Time(); + while(Clock_Time() - start < (tClockTime)i); +} +/*---------------------------------------------------------------------------*/ + diff --git a/targets/TARGET_STMBLUE/hal/src/context_switch.S b/targets/TARGET_STMBLUE/hal/src/context_switch.S new file mode 100644 index 00000000000..ba134eaf4e3 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/context_switch.S @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "../inc/asm.h" + + +//------------------------------------------------------------------------------ +// void CS_contextSave(void) +// void CS_contextRestore(void) +// +// These two functions are needed for the context switch during the power +// save procedure. The purpose of the CS_contextSave() function is to +// either save the current context and trigger sleeping through the 'WFI' +// instruction. +// The CS_contextRestore() function restores the context saved before +// to go in deep sleep. +// All the Cortex M0 registers are saved and restored plus after wakeup +// ----------------------------------------------------------------------------- + __CODE__ + __THUMB__ + __EXPORT__ CS_contextSave + __EXPORT__ CS_contextRestore + __IMPORT__ savedMSP + __IMPORT__ savedICSR + __IMPORT__ savedSHCSR + __IMPORT__ savedNVIC_ISPR +EXPORT_FUNC(CS_contextSave) + PUSH { r4 - r7, lr } /* store R4-R7 and LR (5 words) onto the stack */ + MOV R3, R8 /* mov thread {r8 - r12} to {r3 - r7} */ + MOV R4, R9 + MOV R5, R10 + MOV R6, R11 + MOV R7, R12 + PUSH {R3-R7} /* store R8-R12 (5 words) onto the stack */ + LDR R4, =savedMSP /* load address of savedMSP into R4 */ + MOV R3, SP /* load the stack pointer into R3 */ + STR R3, [R4] /* store the MSP into savedMSP */ + + LDR R4, =0xE000ED04 /* load address of ICSR register into R4 */ + LDR R0, [R4] /* load the ICSR register value into R0 */ + LDR R4, =savedICSR /* load address of savedICSR into R4 */ + STR R0, [R4] /* store the ICSR register value into savedICSR */ + + LDR R4, =0xE000ED24 /* load address of SHCSR register into R4 */ + LDR R0, [R4] /* load the SHCSR register value into R0 */ + LDR R4, =savedSHCSR /* load address of savedSHCSR into R4 */ + STR R0, [R4] /* store the SHCSR register value into savedSHCSR */ + + LDR R4, =0xE000E200 /* load address of NVIC_ISPR register into R4 */ + LDR R0, [R4] /* load the NVIC_ISPR register value into R0 */ + LDR R4, =savedNVIC_ISPR /* load address of savedNVIC_ISPR into R4 */ + STR R0, [R4] /* store the NVIC_ISPR register value into savedNVIC_ISPR */ + + DSB + WFI /* all saved, trigger deep sleep */ + ENDFUNC +EXPORT_FUNC(CS_contextRestore) + /* Even if we fall through the WFI instruction, we will immediately + * execute a context restore and end up where we left off with no + * ill effects. Normally at this point the core will either be + * powered off or reset (depending on the deep sleep level). */ + LDR R4, =savedMSP /* load address of savedMSP into R4 */ + LDR R4, [R4] /* load the SP from savedMSP */ + MOV SP, R4 /* restore the SP from R4 */ + POP {R3-R7} /* load R8-R12 (5 words) from the stack */ + MOV R8, R3 /* mov {r3 - r7} to {r8 - r12} */ + MOV R9, R4 + MOV R10, R5 + MOV R11, R6 + MOV R12, R7 + POP { R4 - R7, PC } /*load R4-R7 and PC (5 words) from the stack */ + ENDFUNC + + + ALIGN_MEM(4) + __END__ diff --git a/targets/TARGET_STMBLUE/hal/src/fifo.c b/targets/TARGET_STMBLUE/hal/src/fifo.c new file mode 100644 index 00000000000..9254fad40c1 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/fifo.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "fifo.h" +#include "osal.h" + +#define MIN(a, b) ((a <= b) ? (a) : (b)) +#define MAX(a, b) ((a < b) ? (b) : (a)) +#define FIFO_ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) +#define ADVANCE_QUEUE(index, size, max_size) ((index + size) % max_size) /* (((index + size) >= max_size) ? 0 : (index + size))*/ +#define FIFO_ALIGNMENT fifo->alignment +#define FIFO_GET_SIZE(fifo) ((fifo->tail>=fifo->head) ? (fifo->tail - fifo->head) : (fifo->max_size - (fifo->head - fifo->tail))) +#define VAR_LEN_ITEM_SIZE_LENGTH 2 + +/** +* @brief Initiliaze a circular fifo specfiyng also elements alignment +* The buffer allocated memory should max_size+maximum length of element, +* so that no wrapping occurs and each element is made of only linear buffer segments. +* @retval None +*/ + +void fifo_init(circular_fifo_t *fifo, uint16_t max_size, uint8_t *buffer, uint8_t alignment) +{ + fifo->tail = fifo->head = 0; + fifo->max_size = max_size; + fifo->buffer = buffer; + fifo->alignment = alignment; +} +/** +* @brief Return number of bytes held in the FIFO +* @retval None +*/ + +uint16_t fifo_size(circular_fifo_t *fifo) +{ + return FIFO_GET_SIZE(fifo); +} +void fifo_flush(circular_fifo_t *fifo) +{ + fifo->tail = fifo->head = 0; +} + + + +static uint8_t _fifo_put(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer, uint16_t index) +{ + uint16_t size_aligned = FIFO_ALIGN(size, FIFO_ALIGNMENT); + if ((FIFO_GET_SIZE(fifo) + size_aligned) < fifo->max_size) { /* <= */ + Osal_MemCpy(&fifo->buffer[index], buffer, size); + fifo->tail = ADVANCE_QUEUE(fifo->tail, size_aligned, fifo->max_size); + return 0; + } + return 1; +} + +//static uint8_t fifo_put_no_wrap(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer) +//{ +// uint16_t index = (fifo->tail == 0) ? fifo->max_size : fifo->tail; +// return (_fifo_put(fifo, size, buffer, index)); +//} + +/** +* @brief Put the buffer in the fifo (no wrapping) +* @retval None +*/ +uint8_t fifo_put(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer) +{ + return (_fifo_put(fifo, size, buffer, fifo->tail)); +} + +static uint8_t _fifo_get(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer, uint16_t index) +{ + uint16_t size_aligned = FIFO_ALIGN(size, FIFO_ALIGNMENT); + if (FIFO_GET_SIZE(fifo) >= size_aligned) { + Osal_MemCpy(buffer, &fifo->buffer[index], size); + fifo->head = ADVANCE_QUEUE(fifo->head, size_aligned, fifo->max_size); + + return 0; + } + return 1; +} + +static uint8_t fifo_get_no_wrap(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer) +{ + uint16_t index = (fifo->head == 0) ? fifo->max_size : fifo->head; + return (_fifo_get(fifo, size, buffer, index)); +} + +uint8_t fifo_get(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer) +{ + return (_fifo_get(fifo, size, buffer, fifo->head)); +} + +uint8_t fifo_put_var_len_item(circular_fifo_t *fifo, uint16_t size, uint8_t *buffer) +{ + uint8_t ret_val = 0; + uint16_t size_aligned = FIFO_ALIGN(size, FIFO_ALIGNMENT); + uint8_t length_size_aligned = FIFO_ALIGN(VAR_LEN_ITEM_SIZE_LENGTH, FIFO_ALIGNMENT); + + if ((FIFO_GET_SIZE(fifo) + size_aligned + length_size_aligned) < fifo->max_size) { + Osal_MemCpy(&fifo->buffer[fifo->tail], &size, VAR_LEN_ITEM_SIZE_LENGTH); + Osal_MemCpy(&fifo->buffer[fifo->tail + length_size_aligned], buffer, size); + + fifo->tail = ADVANCE_QUEUE(fifo->tail, size_aligned + length_size_aligned, fifo->max_size); + + } else { + ret_val = 1; + } + return ret_val; +} + + +uint8_t fifo_discard(circular_fifo_t *fifo, uint16_t size) +{ + uint16_t size_aligned = FIFO_ALIGN(size, FIFO_ALIGNMENT); + if (FIFO_GET_SIZE(fifo) >= size_aligned) { + fifo->head = ADVANCE_QUEUE(fifo->head, size_aligned, fifo->max_size); + return 0; + } + return 1; +} + +uint8_t fifo_get_ptr(circular_fifo_t *fifo, uint16_t size, uint8_t **ptr) +{ + uint16_t size_aligned = FIFO_ALIGN(size, FIFO_ALIGNMENT); + if (FIFO_GET_SIZE(fifo) >= size_aligned) { + *ptr = &fifo->buffer[fifo->head]; + return 0; + } + return 1; +} + +uint8_t fifo_get_var_len_item(circular_fifo_t *fifo, uint16_t *size, uint8_t *buffer) +{ + uint8_t ret_val = fifo_get(fifo, VAR_LEN_ITEM_SIZE_LENGTH, (uint8_t *) size); + if (ret_val == 0) { + ret_val = fifo_get_no_wrap(fifo, *size, buffer); + } + return ret_val; +} + +uint8_t fifo_get_ptr_var_len_item(circular_fifo_t *fifo, uint16_t *size, uint8_t **ptr) +{ + uint8_t ret_val = fifo_get_ptr(fifo, VAR_LEN_ITEM_SIZE_LENGTH, ptr); + if (ret_val == 0) { + *size = *((uint16_t *) *ptr); + } + return ret_val; +} +uint8_t fifo_discard_var_len_item(circular_fifo_t *fifo) +{ + uint16_t size; + uint8_t ret_val = fifo_get(fifo, VAR_LEN_ITEM_SIZE_LENGTH, (uint8_t *) &size); + if (ret_val == 0) { + ret_val = fifo_discard(fifo, size); + } + return ret_val; +} diff --git a/targets/TARGET_STMBLUE/hal/src/gp_timer.c b/targets/TARGET_STMBLUE/hal/src/gp_timer.c new file mode 100644 index 00000000000..47794e06b76 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/gp_timer.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ + +#include "clock.h" +#include "gp_timer.h" + +/*---------------------------------------------------------------------------*/ + +void Timer_Set(struct timer *t, tClockTime interval) +{ + t->interval = interval; + t->start = Clock_Time(); +} + +void Timer_Reset(struct timer *t) +{ + t->start += t->interval; +} + +void Timer_Restart(struct timer *t) +{ + t->start = Clock_Time(); +} + +uint8_t Timer_Expired(struct timer *t) +{ + tClockTime diff = (Clock_Time() - t->start) + 1; + return (t->interval < diff); + +} + +tClockTime Timer_Remaining(struct timer *t) +{ + return (t->start + t->interval - Clock_Time()); +} + + + diff --git a/targets/TARGET_STMBLUE/hal/src/hal_radio.c b/targets/TARGET_STMBLUE/hal/src/hal_radio.c new file mode 100644 index 00000000000..aaf699ec0d1 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/hal_radio.c @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#include "hal_radio.h" + +static ActionPacket aPacket[2]; +static uint32_t networkID = 0x88DF88DF; + +static uint8_t CondRoutineTrue(ActionPacket* p) +{ + return TRUE; +} + +static uint8_t dataRoutineNull(ActionPacket* current_action_packet, ActionPacket* next) +{ + return TRUE; +} + +static uint8_t CondRoutineRxTrue(ActionPacket* p) +{ + /* received a packet */ + if( ((p->status & BIT_TX_MODE) == 0) && ((p->status & IRQ_RCV_OK) != 0) ) { + /* packet received without CRC error */ + return TRUE; + } + return FALSE; +} + + +/** +* @brief This routine sets the network ID field for packet transmission and filtering for the receiving. +* Only two devices with same networkID can communicate with each other. +* @param ID: network ID based on bluetooth specification: +* 1. It shall have no more than six consecutive zeros or ones. +* 2. It shall not have all four octets equal. +* 3. It shall have no more than 24 transitions. +* 4. It shall have a minimum of two transitions in the most significant six bits. +* +* @retval uint8_t: return value +* - 0x00 : Success. +* - 0xC0 : Invalid parameter. +*/ +uint8_t HAL_RADIO_SetNetworkID(uint32_t ID) +{ + networkID = ID; + return 0; +} + + +/** +* @brief This routine sends a packet on a specific channel and at a specific time. +* @param channel: Frequency channel between 0 to 39. +* @param wakeup_time: Time of transmission in us. This is relative time regarding now. +* The relative time cannot be less than 100 us otherwise it might wrap around after 32.7 second. +* @param txBuffer: Pointer to TX data buffer. Second byte of this buffer must be the length of the data. +* @param Callback: This function is being called as data routine. +* First ActionPacket is current action packet and the second one is next action packet. +* @retval uint8_t return value +* - 0x00 : Success. +* - 0xC0 : Invalid parameter. +* - 0xC4 : Radio is busy, receiving has not been triggered. +*/ +uint8_t HAL_RADIO_SendPacket(uint8_t channel, + uint32_t wakeup_time, + uint8_t* txBuffer, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) ) +{ + uint8_t returnValue = SUCCESS_0; + uint32_t dummy; + + if(channel > 39) { + returnValue = INVALID_PARAMETER_C0; + } + + if(RADIO_GetStatus(&dummy) != BLUE_IDLE_0) { + returnValue = RADIO_BUSY_C4; + } + + if(returnValue == SUCCESS_0) { + uint8_t map[5]= {0xFF,0xFF,0xFF,0xFF,0xFF}; + RADIO_SetChannelMap(0, &map[0]); + RADIO_SetChannel(0, channel, 0); + RADIO_SetTxAttributes(0, networkID, 0x555555, SCA_DEFAULTVALUE); + + aPacket[0].StateMachineNo = STATE_MACHINE_0; + aPacket[0].ActionTag = TXRX | PLL_TRIG | TIMER_WAKEUP | RELATIVE; + aPacket[0].WakeupTime = wakeup_time; + aPacket[0].ReceiveWindowLength = 0; /* does not affect for Tx */ + aPacket[0].data = txBuffer; + aPacket[0].next_true = NULL_0; + aPacket[0].next_false = NULL_0; + aPacket[0].condRoutine = CondRoutineTrue; + aPacket[0].dataRoutine = Callback; + + RADIO_SetReservedArea(&aPacket[0]); + returnValue = RADIO_MakeActionPacketPending(&aPacket[0]); + } + + return returnValue; +} + + +/** +* @brief This routine sends a packet on a specific channel and at a certain time then wait for receiving acknowledge. +* @param channel: Frequency channel between 0 to 39. +* @param wakeup_time: Time of transmission based on us. This is relative time regarding now. +* The relative time cannot be less than 100 us otherwise it might wrap around after 32.7 second. +* @param txBuffer: Pointer to TX data buffer. Secound byte of this buffer must be the length of the data. +* @param rxBuffer: Pointer to RX data buffer. Secound byte of this buffer must be the length of the data. +* @param receive_timeout: Time of RX window used to wait for the packet on us. +* @param callback: This function is being called as data routine. +* First ActionPacket is current action packet and the second one is next action packet. +* @retval uint8_t return value +* - 0x00 : Success. +* - 0xC0 : Invalid parameter. +* - 0xC4 : Radio is busy, receiving has not been triggered. +*/ +uint8_t HAL_RADIO_SendPacketWithAck(uint8_t channel, + uint32_t wakeup_time, + uint8_t* txBuffer, + uint8_t* rxBuffer, + uint32_t receive_timeout, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) ) +{ + uint8_t returnValue = SUCCESS_0; + uint32_t dummy; + + if(channel > 39) { + returnValue = INVALID_PARAMETER_C0; + } + + if(RADIO_GetStatus(&dummy) != BLUE_IDLE_0) { + returnValue = RADIO_BUSY_C4; + } + + if(returnValue == SUCCESS_0) { + uint8_t map[5]= {0xFF,0xFF,0xFF,0xFF,0xFF}; + RADIO_SetChannelMap(0, &map[0]); + RADIO_SetChannel(0, channel, 0); + + RADIO_SetTxAttributes(0, networkID, 0x555555, SCA_DEFAULTVALUE); + + aPacket[0].StateMachineNo = STATE_MACHINE_0; + aPacket[0].ActionTag = TXRX | PLL_TRIG | TIMER_WAKEUP | RELATIVE; + aPacket[0].WakeupTime = wakeup_time; + aPacket[0].ReceiveWindowLength = 0; /* does not affect for Tx */ + aPacket[0].data = txBuffer; + aPacket[0].next_true = &aPacket[1]; + aPacket[0].next_false = &aPacket[1]; + aPacket[0].condRoutine = CondRoutineTrue; + aPacket[0].dataRoutine = dataRoutineNull; + + aPacket[1].StateMachineNo = STATE_MACHINE_0; + aPacket[1].ActionTag = 0; + aPacket[1].WakeupTime = wakeup_time; + aPacket[1].ReceiveWindowLength = receive_timeout; + aPacket[1].data = rxBuffer; + aPacket[1].next_true = NULL_0; + aPacket[1].next_false = NULL_0; + aPacket[1].condRoutine = CondRoutineTrue; + aPacket[1].dataRoutine = Callback; + + RADIO_SetReservedArea(&aPacket[0]); + RADIO_SetReservedArea(&aPacket[1]); + returnValue = RADIO_MakeActionPacketPending(&aPacket[0]); + } + + return returnValue; +} + + +/** +* @brief This routine receives a packet on a specific channel and at a certain time. +* @param channel: Frequency channel between 0 to 39. +* @param wakeup_time: Time of transmission based on us. This is relative time regarding now. +* The relative time cannot be less than 100 us otherwise it might wrap around after 32.7 second. +* @param rxBuffer: Pointer to RX data buffer. Secound byte of this buffer must be the length of the data. +* @param receive_timeout: Time of RX window used to wait for the packet on us. +* @param callback: This function is being called as data routine. +* First ActionPacket is current action packet and the second one is next action packet. +* @retval uint8_t return value +* - 0x00 : Success. +* - 0xC0 : Invalid parameter. +* - 0xC4 : Radio is busy, receiving has not been triggered. +*/ +uint8_t HAL_RADIO_ReceivePacket(uint8_t channel, + uint32_t wakeup_time, + uint8_t* rxBuffer, + uint32_t receive_timeout, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) ) +{ + uint8_t returnValue = SUCCESS_0; + uint32_t dummy; + + if(channel > 39) { + returnValue = INVALID_PARAMETER_C0; + } + + if(RADIO_GetStatus(&dummy) != BLUE_IDLE_0) { + returnValue = RADIO_BUSY_C4; + } + + if(returnValue == SUCCESS_0) { + uint8_t map[5]= {0xFF,0xFF,0xFF,0xFF,0xFF}; + RADIO_SetChannelMap(0, &map[0]); + RADIO_SetChannel(0, channel, 0); + + RADIO_SetTxAttributes(0, networkID, 0x555555, SCA_DEFAULTVALUE); + + aPacket[0].StateMachineNo = STATE_MACHINE_0; + aPacket[0].ActionTag = PLL_TRIG | TIMER_WAKEUP | RELATIVE; + aPacket[0].WakeupTime = wakeup_time; + aPacket[0].ReceiveWindowLength = receive_timeout; + aPacket[0].data = rxBuffer; + aPacket[0].next_true = NULL_0; + aPacket[0].next_false = NULL_0; + aPacket[0].condRoutine = CondRoutineTrue; + aPacket[0].dataRoutine = Callback; + + RADIO_SetReservedArea(&aPacket[0]); + returnValue = RADIO_MakeActionPacketPending(&aPacket[0]); + } + + return returnValue; +} + + +/** +* @brief This routine receives a packet on a specific channel and at a certain time. +* Then sends a packet as an acknowledgment. +* @param channel: frequency channel between 0 to 39. +* @param wakeup_time: time of transmission based on us. This is relative time regarding now. +* The relative time cannot be less than 100 us otherwise it might wrap around after 32.7 second. +* @param rxBuffer: points to received data buffer. second byte of this buffer determines the length of the data. +* @param txBuffer: points to data buffer to send. secound byte of this buffer must be the length of the buffer. +* @param receive_timeout: Time of RX window used to wait for the packet on us. +* @param callback: This function is being called as data routine. +* First ActionPacket is current action packet and the second one is next action packet. +* @retval uint8_t return value +* - 0x00 : Success. +* - 0xC0 : Invalid parameter. +* - 0xC4 : Radio is busy, receiving has not been triggered. +*/ +uint8_t HAL_RADIO_ReceivePacketWithAck(uint8_t channel, + uint32_t wakeup_time, + uint8_t* rxBuffer, + uint8_t* txBuffer, + uint32_t receive_timeout, + uint8_t (*Callback)(ActionPacket*, ActionPacket*) ) +{ + uint8_t returnValue = SUCCESS_0; + uint32_t dummy; + + if(channel > 39) { + returnValue = INVALID_PARAMETER_C0; + } + + if(RADIO_GetStatus(&dummy) != BLUE_IDLE_0) { + returnValue = RADIO_BUSY_C4; + } + + if(returnValue == SUCCESS_0) { + uint8_t map[5]= {0xFF,0xFF,0xFF,0xFF,0xFF}; + RADIO_SetChannelMap(0, &map[0]); + RADIO_SetChannel(0,channel,0); + RADIO_SetTxAttributes(0, networkID,0x555555,SCA_DEFAULTVALUE); + + aPacket[0].StateMachineNo = STATE_MACHINE_0; + aPacket[0].ActionTag = PLL_TRIG | TIMER_WAKEUP | RELATIVE; + aPacket[0].WakeupTime = wakeup_time; + aPacket[0].ReceiveWindowLength = receive_timeout; + aPacket[0].data = rxBuffer; + aPacket[0].next_true = &aPacket[1]; + aPacket[0].next_false = NULL_0; + aPacket[0].condRoutine = CondRoutineRxTrue; + aPacket[0].dataRoutine = Callback; + + aPacket[1].StateMachineNo = STATE_MACHINE_0; + aPacket[1].ActionTag = TXRX; + aPacket[1].WakeupTime = wakeup_time; + aPacket[1].ReceiveWindowLength = 0; /* does not affect for Tx */ + aPacket[1].data = txBuffer; + aPacket[1].next_true = NULL_0; + aPacket[1].next_false = NULL_0; + aPacket[1].condRoutine = CondRoutineTrue; + aPacket[1].dataRoutine = Callback; + + RADIO_SetReservedArea(&aPacket[0]); + RADIO_SetReservedArea(&aPacket[1]); + returnValue = RADIO_MakeActionPacketPending(&aPacket[0]); + } + + return returnValue; +} + + +/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/hal/src/miscutil.c b/targets/TARGET_STMBLUE/hal/src/miscutil.c new file mode 100644 index 00000000000..ec0428915a4 --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/miscutil.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include "BlueNRG_x_device.h" +#include "miscutil.h" + +NO_INIT_SECTION(crash_info_t crash_info_ram, ".__crash_RAM"); + +/** @addtogroup BlueNRG1_Miscellaneous_Utilities +* @{ +*/ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define BLUENRG2_IDCODE (0x0200A041) +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +void HAL_GetPartInfo(PartInfoType *partInfo) +{ + volatile uint32_t *ptr = (volatile uint32_t *)(CKGEN_SOC_BASE + 0x28); + + partInfo->die_major = CKGEN_SOC->DIE_ID_b.VERSION; + partInfo->die_cut = CKGEN_SOC->DIE_ID_b.REV; + + partInfo->jtag_id_code = *ptr; + if (partInfo->jtag_id_code == BLUENRG2_IDCODE) { + /* BlueNRG-2 id is conventionally 2 */ + partInfo->die_id = DIE_ID_BLUENRG2; + } else { + /* BlueNRG-1 id is conventionally 1 */ + partInfo->die_id = DIE_ID_BLUENRG1; + } + + /* Patch for early samples */ + if (partInfo->die_major == 0) + partInfo->die_major = 1; + + partInfo->flash_size = (FLASH->SIZE + 1) * 4; +} + +/** + * @brief Get Crash Information utility + */ +void HAL_GetCrashInfo(crash_info_t *crashInfo) +{ + *crashInfo = crash_info_ram; + /* Reset crash info value */ + crash_info_ram.signature = 0; +} +void HAL_CrashHandler(uint32_t msp, uint32_t signature) +{ + volatile uint32_t * crash_info = (volatile uint32_t *)&crash_info_ram; + register uint32_t reg_content; + /* Init to zero the crash_info RAM locations */ + for (reg_content=0; reg_content= ((uint32_t *) _MEMORY_RAM_BEGIN_)) && + (ptr <= ((uint32_t *) _MEMORY_RAM_END_))) + crash_info[reg_content] = *ptr; + } + NVIC_SystemReset(); + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + {} +} + +/** + * @brief Get Device ID, Version and Revision numbers + */ +void BLEPLAT_get_part_info(uint8_t *device_id, uint8_t *major_cut, uint8_t *minor_cut) +{ + PartInfoType partInfo; + + /* get partInfo */ + HAL_GetPartInfo(&partInfo); + + /* Set device ID */ + *device_id = partInfo.die_id; + + /* Set major cut */ + *major_cut = partInfo.die_major; + + /* Set minor cut */ + *minor_cut = partInfo.die_cut; +} + +/** + *@ +} */ /* End of group BlueNRG1_Miscellaneous_Utilities */ diff --git a/targets/TARGET_STMBLUE/hal/src/osal.c b/targets/TARGET_STMBLUE/hal/src/osal.c new file mode 100644 index 00000000000..630adbfc10f --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/osal.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/* Includes ------------------------------------------------------------------*/ +#include +#include "osal.h" + +/** + * Osal_MemCpy + * + */ + +void* Osal_MemCpy(void *dest,const void *src,unsigned int size) +{ + return(memcpy(dest,src,size)); +} + +/** + * Osal_MemSet + * + */ + +void* Osal_MemSet(void *ptr, int value,unsigned int size) +{ + return(memset(ptr,value,size)); +} + +/** + * Osal_MemCmp + * + */ +int Osal_MemCmp(void *s1,void *s2,unsigned int size) +{ + return(memcmp(s1,s2,size)); +} + diff --git a/targets/TARGET_STMBLUE/hal/src/system_bluenrg1.c b/targets/TARGET_STMBLUE/hal/src/system_bluenrg1.c new file mode 100644 index 00000000000..12a75f1297c --- /dev/null +++ b/targets/TARGET_STMBLUE/hal/src/system_bluenrg1.c @@ -0,0 +1,942 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +/** + * @file system_bluenrg1.c + * @brief BlueNRG-1,2 Low Level Init functions + * + +* \section SystemInit System Initialization + + - The SystemInit() function is called on BlueNRG-1, BlueNRG-2 main application as first operation required for properly initialize the device: + - It remaps the vector table and it configures all the device interrrupt priorities giving the + highest one to the Pendable request for system service and to the BLE radio BLUE Controller ones. + - It calls the DeviceConfiguration(TRUE,TRUE) function for performing the proper application configuration steps. + - It disables all the peripherals clock except NVM, SYSCTR, PKA and RNG + - It's up to user application to enables the other peripherals clock according to his needs. + - It clear PRIMASK to reenable global interrupt operations. + +* \section DeviceConfiguration_Cold Define Application Configurations + + - During the device initialization phase, some specific parameters must be set + on BLE device controller registers, in order to define the following configurations: + - Application mode: user or test mode + - High speed crystal configuration: 32 or 16 MHz + - Low speed crystal source: external 32 kHz oscillator, internal RO + - SMPS: on or off (if on: 4.7 uH or 10 uH SMPS inductor) + - BOR configuration + - The BlueNRG-1, BlueNRG-2 controller registers values are defined on file system_bluenrg1.c through the configuration table: + - COLD_START_CONFIGURATION. + - This table defines the default configurations as follows: + - User mode: ATB0_ANA_ENG_REG = USER_MODE_ATB0 (0x00), ATB1_ANA_ENG_REG = USER_MODE_ATB (0x30) + - SMPS ON, 10 uH inductor: CLOCK_LOW_ENG_REG = SMPS_ON, RM1_DIG_ENG_REG = SMPS_10uH_RM1 + - 16 MHz high speed crystal: CLOCK_HIGH_ENG_REG = HIGH_FREQ_16M + - External 32 kHz oscillator: CLOCK_ANA_USER_REG = LOW_FREQ_XO + - BOR (brown-out threshold): it is enabled by default + - At device initialization, on reset/power-on, the function SystemInit() sets the + default starting parameters defined on the COLD_START_CONFIGURATION table within + the cold_start_config[] array by calling the DeviceConfiguration(BOOL coldStart, BOOL waitLS_Ready) function with coldStart = TRUE and waitLS_Ready = TRUE. + User application can define its specific application starting settings, based on its application scenario, by setting some preprocessor options which act on specific fields of the cold_start_config[] array: + - HS_SPEED_XTAL (high speed cystal: HS_SPEED_XTAL_16MHZ or HS_SPEED_XTAL_32MHZ) + - LS_SOURCE (Low speed crystal source: LS_SOURCE_EXTERNAL_32kHZ, LS_SOURCE_INTERNAL_RO) + - SMPS_INDUCTOR (SPMS inductor disabled: SMPS_INDUCTOR_NONE or SPMS inductor enabled with 10uH: SMPS_INDUCTOR_10uH or SPMS inductor enabled with 4.7uH: SMPS_INDUCTOR_4_7uH) + - BOR_CONFIG (BOR enabled: BOR_ON; BOR disabled: BOR_OFF. Default setting: BOR_ON) + + - Regarding the ATB0_ANA_ENG_REG, ATB1_ANA_ENG_REG registers settings, some test modes are also available in order to address some test scenarios. + User should sets such registers as follows: + + - Low speed crystal oscillator test mode: + + - cold_start_config[2] = LS_XTAL_MEAS_ATB0 (0x37) + - cold_start_config[5] = LS_XTAL_MEAS_ATB1 (0x34) + + - High speed start-up time test mode: + + - cold_start_config[2] = HS_STARTUP_TIME_MEAS_ATB0 (0x04) + - cold_start_config[5] = HS_STARTUP_TIME_MEAS_ATB1 (0x34) + + - TX/RX event alert enabling: + + - cold_start_config[2] = TX_RX_START_STOP_MEAS_ATB0 (0x38) + - cold_start_config[5] = TX_RX_START_STOP_MEAS_ATB1 (0x34) + + - Internal RO time test mode: + + - cold_start_config[2] = RO_XTAL_MEAS_ATB0 (0x36) + - cold_start_config[5] = RO_XTAL_MEAS_ATB1 (0x34) + + - Please notice that the default user mode register setting must be restored for typical user mode application scenarios: + + - cold_start_config[2] = USER_MODE_ATB0 (0x00) + - cold_start_config[5] = USER_MODE_ATB1 (0x30) + +* \section General_Configuration General Device Configuration + + - Beyond the application configuration performed only at device reset/power-on by calling the DeviceConfiguration() function with + coldStart = TRUE, this function performs the following general configuration operations: + + - Setup RCO32K trimming value in PMU_ANA_USER_REG + - Setup LDO1V2 trimming value in ATB1_ANA_ENG_REG + +* \section DeviceConfiguration_ALL How to set Device Configuration Parameters? + + - The selected device configuration parameters are set within the BLE device controller, Radio configuration register, through the + following instructions executed on DeviceConfiguration() function: + + BLUE_CTRL->RADIO_CONFIG = 0x10000U | (uint16_t)((uint32_t)cold_start_config + & 0x0000FFFFU); + while ((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); + + - Once the device configuration parameters are set, the DeviceConfiguration() function must wait until the High Speed (HS) crystal is ready. + Since the slow clock period measurement is done automatically each time the device enters in active2 state and the HS cystal is ready, the + related Clock Gen interrupt signals that a slow clock period measurement has been done: + + while(CKGEN_BLE->CLK32K_IT == 0); //Interrupt event for 32 kHz clock measurement + +**/ + +#include "BlueNRG1_flash.h" +#include "misc.h" +#include "bluenrg_x_device.h" +#include "miscutil.h" +#include "hal_types.h" + +#define RESET_WAKE_DEEPSLEEP_REASONS 0x05 +#define CRITICAL_PRIORITY 0 +/* OTA tag used to tag a valid application on interrupt vector table*/ +#if ST_OTA_SERVICE_MANAGER_APPLICATION +#define OTA_VALID_APP_TAG (0xAABBCCDD) /* OTA Service Manager has a special valid tag */ +#else +#define OTA_VALID_APP_TAG (0xAA5555AA) +#endif + +#define BLUE_FLAG_TAG (0x424C5545) + +#define HOT_TABLE_RADIO_SIZE 32 + +WEAK_FUNCTION(void NMI_Handler(void) {}); +WEAK_FUNCTION(void HardFault_Handler(void) {}); +WEAK_FUNCTION(void SVC_Handler(void) {}); +WEAK_FUNCTION(void PendSV_Handler(void) {}); +WEAK_FUNCTION(void SysTick_Handler(void) {}); +WEAK_FUNCTION(void GPIO_Handler(void) {}); +WEAK_FUNCTION(void NVM_Handler(void) {}); +WEAK_FUNCTION(void UART_Handler(void) {}); +WEAK_FUNCTION(void SPI_Handler(void) {}); +WEAK_FUNCTION(void Blue_Handler(void) {}); +WEAK_FUNCTION(void MFT1A_Handler(void) {}); +WEAK_FUNCTION(void MFT1B_Handler(void) {}); +WEAK_FUNCTION(void MFT2A_Handler(void) {}); +WEAK_FUNCTION(void MFT2B_Handler(void) {}); +WEAK_FUNCTION(void RTC_Handler(void) {}); +WEAK_FUNCTION(void WDG_Handler(void) {}); +WEAK_FUNCTION(void ADC_Handler(void) {}); +WEAK_FUNCTION(void I2C2_Handler(void) {}); +WEAK_FUNCTION(void I2C1_Handler(void) {}); +WEAK_FUNCTION(void DMA_Handler(void) {}); +WEAK_FUNCTION(void PKA_Handler(void) {}); + + + +/* ------------------------------------------------------------------------------ +* uint32_t ota_sw_activation +* +* OTA SW activation +* +* ------------------------------------------------------------------------------ */ +NO_INIT_SECTION(volatile uint32_t ota_sw_activation, ".ota_sw_activation"); + +/* ------------------------------------------------------------------------------ +* uint32_t savedMSP +* +* Private storage to hold the saved stack pointer. This variable is only used +* in this file and should not be extern'ed. In our current design we +* do not use real context switching, but only context saving and restoring. +* As such, we only need to keep track of the Main Stack Pointer (MSP). This +* variable is used to hold the MSP between a save and a restore. +* ------------------------------------------------------------------------------ */ +SECTION(".savedMSP") +REQUIRED(uint32_t savedMSP); + + +/* ------------------------------------------------------------------------------ +* uint8_t wakeupFromSleepFlag +* +* A simple flag used to indicate if the wakeup occurred from Sleep or Standby +* condition. +* If this flag is zero, an interrupt has affected the WFI instruction and the +* BlueNRG-1 doesn't enter in deep sleep state. So, no context restore is +* necessary. +* If this flag is non-zero, the WFI instruction puts the BlueNRG-1 in deep sleep. +* So, at wakeup time a context restore is necessary. +* Note: The smallest unit of storage is a single byte. +* +* NOTE: This flag must be cleared before the context restore is called +* ------------------------------------------------------------------------------ */ +SECTION(".wakeupFromSleepFlag") +REQUIRED(uint8_t volatile wakeupFromSleepFlag); + + +/* ------------------------------------------------------------------------------ +* uint32_t __blueflag_RAM +* +* __blueflag_RAM +* +* ------------------------------------------------------------------------------ */ +SECTION(".__blueflag_RAM") +REQUIRED(uint32_t __blueflag_RAM); + + +/* ------------------------------------------------------------------------------ +* volatile uint32_t flash_sw_lock; +* +* This is used to lock/unlock the flash operations in software. +* The unlock word is 0xFCECBCCC +* ------------------------------------------------------------------------------ */ +SECTION(".flash_sw_lock") +REQUIRED(uint32_t volatile flash_sw_lock); + +/* ------------------------------------------------------------------------------ +* uint32_t savedICSR +* +* Private storage to save the Interrupt Control State register, to check the +* SysTick and PendSV interrupt status +* This variable is only used during the samrt power management +* procedure +* ------------------------------------------------------------------------------ */ +uint32_t savedICSR; + +/* ------------------------------------------------------------------------------ +* uint32_t savedSHCSR +* +* Private storage to save the System Handler Control and State register, +* to check the SVCall interrupt status +* This variable is only used during the samrt power management +* procedure +* ------------------------------------------------------------------------------ */ +uint32_t savedSHCSR; + +/* ------------------------------------------------------------------------------ +* uint32_t savedNVIC_ISPR +* +* Private storage to save the Interrupt Set Pending register, +* to check the NVIC interrupt status +* This variable is only used during the smart power management +* procedure +* ------------------------------------------------------------------------------ */ +uint32_t savedNVIC_ISPR; + +/* ------------------------------------------------------------------------------ +* volatile uint8_t hot_table_radio_config[HOT_TABLE_RADIO_SIZE] +* +* Hot table radio configuration storage. +* This variable is only used during the smart power management +* procedure +* ------------------------------------------------------------------------------ */ +volatile uint8_t hot_table_radio_config[HOT_TABLE_RADIO_SIZE]={0x00}; + +/* ------------------------------------------------------------------------------ +* volatile uint8_t BOR_config[7] +* +* BOR configuration storage. +* This variable is only used during the smart power management +* procedure +* ------------------------------------------------------------------------------ */ +volatile uint8_t BOR_config[7]; + + +int __low_level_init_CS(void) +{ + /* Lock the flash */ + flash_sw_lock = FLASH_LOCK_WORD; + + /* If the reset reason is a wakeup from sleep restore the context */ + if ((CKGEN_SOC->REASON_RST == 0) && (CKGEN_BLE->REASON_RST > RESET_WAKE_DEEPSLEEP_REASONS)) { +#ifndef NO_SMART_POWER_MANAGEMENT + + void CS_contextRestore(void); + wakeupFromSleepFlag = 1; /* A wakeup from Standby or Sleep occurred */ + CS_contextRestore(); /* Restore the context */ + /* if the context restore worked properly, we should never return here */ + while(1) { ; } +#else + return 0; +#endif + } + return 1; +} + +#if defined(__ICCARM__) + +void RESET_HANDLER(void) +{ + if(__low_level_init_CS()==1) + __cmain(); + else { + while(1){;} //code should never reach this point + } +} + +#else //ARMc5 or ARMc6 +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + +void RESET_HANDLER(void) +{ + if(__low_level_init_CS()==1) + __main(); + else { + __set_MSP((uint32_t)_INITIAL_SP); + main(); + } +} + + +#else /* __CC_ARM */ +#ifdef __GNUC__ + +extern unsigned long _etext; +extern unsigned long _sidata; /* start address for the initialization values of the .data section. Defined in linker script */ +extern unsigned long _sdata; /* start address for the .data section. Defined in linker script */ +extern unsigned long _edata; /* end address for the .data section. Defined in linker script */ +extern unsigned long _sbss; /* start address for the .bss section. Defined in linker script */ +extern unsigned long _ebss; /* end address for the .bss section. Defined in linker script */ +extern unsigned long _sbssblue; /* start address for the section reserved for the Blue controller. Defined in linker script */ +extern unsigned long _ebssblue; /* end address for the section reserved for the Blue controller. Defined in linker script */ +extern unsigned long _estack; /* init value for the stack pointer. Defined in linker script */ +extern unsigned long _sidata2; /* start address for the initialization values of the special ram_preamble */ +extern unsigned long _sdata2; /* start address the special ram_preamble defined in linker script */ +extern unsigned long _edata2; /* end address the special ram_preamble defined in linker script */ + +extern int main(void); + +void RESET_HANDLER(void) +{ + if(__low_level_init_CS()==1) { + unsigned long *pulSrc, *pulDest; + + // Copy the data segment initializers from flash to SRAM. + pulSrc = &_sidata; + for(pulDest = &_sdata; pulDest < &_edata; ) + { + *(pulDest++) = *(pulSrc++); + } + + pulSrc = &_sidata2; + for(pulDest = &_sdata2; pulDest < &_edata2; ) + { + *(pulDest++) = *(pulSrc++); + } + + // Zero fill the bss segment. + for(pulDest = &_sbssblue; pulDest < &_ebssblue; ) + { + *(pulDest++) = 0; + } + + for(pulDest = &_sbss; pulDest < &_ebss; ) + { + *(pulDest++) = 0; + } + } + // Call the application's entry point. + __set_MSP((uint32_t)_INITIAL_SP); + //main(); + _start(); +} + +#endif /* __GNUC__ */ +#endif /* __CC_ARM */ +#endif /* __ICCARM__ */ + +SECTION(".intvec") +REQUIRED(const intvec_elem __vector_table[]) = { + {.__ptr = _INITIAL_SP}, /* Stack address */ + {RESET_HANDLER}, /* Reset handler is C initialization. */ + {NMI_Handler}, /* The NMI handler */ + {HardFault_Handler}, /* The hard fault handler */ + {(intfunc) OTA_VALID_APP_TAG}, /* OTA Application */ + {(intfunc) BLUE_FLAG_TAG}, /* Reserved for blue flag DTM updater */ + {0x00000000}, /* Reserved */ + {0x00000000}, /* Reserved */ + {0x00000000}, /* Reserved */ + {0x00000000}, /* Reserved */ + {0x00000000}, /* Reserved */ + {SVC_Handler}, /* SVCall */ + {0x00000000}, /* Reserved */ + {0x00000000}, /* Reserved */ + {PendSV_Handler}, /* PendSV */ + {SysTick_Handler}, /* SysTick_Handler */ + {GPIO_Handler}, /* IRQ0: GPIO */ + {NVM_Handler}, /* IRQ1: NVM */ + {0x00000000}, /* IRQ2: */ + {0x00000000}, /* IRQ3: */ + {UART_Handler}, /* IRQ4: UART */ + {SPI_Handler}, /* IRQ5: SPI */ + {Blue_Handler}, /* IRQ6: Blue */ + {WDG_Handler}, /* IRQ7: Watchdog */ + {0x00000000}, /* IRQ8: */ + {0x00000000}, /* IRQ9: */ + {0x00000000}, /* IRQ10: */ + {0x00000000}, /* IRQ11: */ + {0x00000000}, /* IRQ12: */ + {ADC_Handler}, /* IRQ13 ADC */ + {I2C2_Handler}, /* IRQ14 I2C2 */ + {I2C1_Handler}, /* IRQ15 I2C1 */ + {0x00000000}, /* IRQ16 */ + {MFT1A_Handler}, /* IRQ17 MFT1 irq1 */ + {MFT1B_Handler}, /* IRQ18 MFT1 irq2 */ + {MFT2A_Handler}, /* IRQ19 MFT2 irq1 */ + {MFT2B_Handler}, /* IRQ20 MFT2 irq2 */ + {RTC_Handler}, /* IRQ21 RTC */ + {PKA_Handler}, /* IRQ22 PKA */ + {DMA_Handler}, /* IRQ23 DMA */ + {0x00000000}, /* IRQ24 */ + {0x00000000}, /* IRQ25 */ + {0x00000000}, /* IRQ26 */ + {0x00000000}, /* IRQ27 */ + {0x00000000}, /* IRQ28 */ + {0x00000000}, /* IRQ29 */ + {0x00000000}, /* IRQ30 */ + {0x00000000} /* IRQ31 */ +}; + + + +//------------------------------------------------------------------------------ +// uint32_t *app_base +// +// The application base address. Used by OTA IRQ stub file to determine the +// effective application base address and jump to the proper IRQ handler. +// +//------------------------------------------------------------------------------ +SECTION(".app_base") +REQUIRED(uint32_t *app_base) = (uint32_t *) __vector_table; + + + +SECTION(".bss.__blue_RAM") +REQUIRED(__blue_RAM_struct __blue_RAM) = {0,}; + +/** + * @name Device Configuration Registers + *@{ + */ + +/** + *@brief Analog Test Bus 0 register + */ +#define ATB0_ANA_ENG_REG 0x3F +/** + *@brief Analog Test Bus 1 register + */ +#define ATB1_ANA_ENG_REG 0x3E +/** + *@brief Rate Multiplier 1 register + */ +#define RM1_DIG_ENG_REG 0x3C +/** + *@brief Low Frequency Clock and SMPS register + */ +#define CLOCK_LOW_ENG_REG 0x3B +/** + *@brief High Frequency Clock register + */ +#define CLOCK_HIGH_ENG_REG 0x3A +/** + *@brief Power Management register + */ +#define PMU_ANA_ENG_REG 0x39 +/** + *@brief System Clock register + */ +#define CLOCK_ANA_USER_REG 0x34 +/** + *@brief System Power Management register + */ +#define PMU_ANA_USER_REG 0x35 +/** + *@brief Modulator register + */ +#define MOD_ANA_ENG_REG 0x21 +//@} \\Device Configuration Registers + +/** + * @name Device Configuration values + *@{ + */ + +/** + * @brief Enable the low frequency RO + */ +#define LOW_FREQ_RO 0x1B +/** + * @brief Enable the external low frequency XO + */ +#define LOW_FREQ_XO 0x5B +/** + * @brief Enable the high frequency 16 MHz + */ +#define HIGH_FREQ_16M 0x40 +/** + * @brief Enable the high frequrency 32 MHz + */ +#define HIGH_FREQ_32M 0x44 +/** + * @brief Enable the SMPS + */ +#define SMPS_ON 0x4C +/** + * @brief Disable the SMPS + */ +#define SMPS_OFF 0x6C +/** + * @brief SMPS clock frequency value for 4.7 uH inductor + */ +#define SMPS_4_7uH_RM1 0x40 +/** + * @brief Power management configuration for 4.7 uH inductor + */ +#define SMPS_4_7uH_PMU 0xBE +/** + * @brief SMPS clock frequency value for 10 uH inductor + */ +#define SMPS_10uH_RM1 0x20 +/** + * @brief Power management configuration for 10 uH inductor + */ +#define SMPS_10uH_PMU 0xB2 +/** + * @brief RCO32 trimming default values + */ +#define PMU_ANA_USER_RESET_VALUE 0x0B +/** + * @brief Analog test bus 0 settings for + * normal application mode + */ +#define USER_MODE_ATB0 0x00 +/** + * @brief Analog test bus 1 settings for + * normal application mode + */ +#define USER_MODE_ATB1 0x30 +/** + * @brief Analog test bus 0 settings for + * low speed crystal measurement + */ +#define LS_XTAL_MEAS_ATB0 0x37 +/** + * @brief Analog test bus 1 settings for + * low speed crystal measurement + */ +#define LS_XTAL_MEAS_ATB1 0x34 +/** + * @brief Analog test bus 0 settings for + * high speed crystal startup time measurement + */ +#define HS_STARTUP_TIME_MEAS_ATB0 0x04 +/** + * @brief Analog test bus 1 settings for + * high speed crystal startup time measurement + */ +#define HS_STARTUP_TIME_MEAS_ATB1 0x34 +/** + * @brief Analog test bus 0 settings for + * Tx/Rx start stop signal measurement + */ +#define TX_RX_START_STOP_MEAS_ATB0 0x38 +/** + * @brief Analog test bus 1 settings for + * Tx/Rx start stop signal measurement + */ +#define TX_RX_START_STOP_MEAS_ATB1 0x34 +/** + * @brief Analog test bus 0 settings for + * internal RO crystal measurement + */ +#define RO_XTAL_MEAS_ATB0 0x36 +/** + * @brief Analog test bus 1 settings for + * internal RO crystal measurement + */ +#define RO_XTAL_MEAS_ATB1 0x34 +/** + * @brief Central frequency + */ +#define CENTRAL_FREQ_MOD 0x08 +//@} \\Device Configuration values + +/** + *@brief Number of configuration bytes to send over Blue SPI + */ +#define NUMBER_CONFIG_BYTE 0x02 +/** + *@brief End Configuration Tag + */ +#define END_CONFIG 0x00 + +/** + * @brief Cold start configuration register table + */ +#define COLD_START_CONFIGURATION \ +{ \ + NUMBER_CONFIG_BYTE, ATB0_ANA_ENG_REG, USER_MODE_ATB0, \ + NUMBER_CONFIG_BYTE, ATB1_ANA_ENG_REG, USER_MODE_ATB1, \ + NUMBER_CONFIG_BYTE, RM1_DIG_ENG_REG, SMPS_10uH_RM1, \ + NUMBER_CONFIG_BYTE, CLOCK_LOW_ENG_REG, SMPS_ON, \ + NUMBER_CONFIG_BYTE, CLOCK_HIGH_ENG_REG, HIGH_FREQ_16M, \ + NUMBER_CONFIG_BYTE, PMU_ANA_ENG_REG, SMPS_10uH_PMU, \ + NUMBER_CONFIG_BYTE, CLOCK_ANA_USER_REG, LOW_FREQ_XO, \ + NUMBER_CONFIG_BYTE, PMU_ANA_USER_REG, PMU_ANA_USER_RESET_VALUE, \ + END_CONFIG \ +} + +/** + * @brief RCO32K trimming value flash location + */ +#define RCO32K_TRIMMING_FLASH_ADDR 0x100007E8 +/** + * @brief LDO1V2 trimming value flash location + */ +#define LDO1V2_TRIMMING_FLASH_ADDR 0x100007E4 +/** + * @brief Battery Level Detector Threshold trimming value flash location + */ +#define SET_BLD_LVL_TRIMMING_FLASH_ADDR 0x100007B0 +/** + * @brief Check bytes tag + */ +#define CHECK_BYTES 0xAA55 + + +/* LS Stabilization state machine defines */ +#define WAIT_FREQ_MIN_STATE 0 +#define WAIT_FREQ_STABILIZATION_STATE 1 +#define LS_STABILIZATION_ENDED 2 + +/* Min Clock Period to wait. Clock period value for 20 KHz */ +#define MIN_CLOCK_PERIOD 38400 +/* Max number of iteration to wait before to exit if the clock is not stabilized */ +#define MAX_NUMBER_ITERATION 500 +/* Default slow count */ +#define SLOW_COUNT 23 + +/* Wait the Low speed oscillator stabilization */ +void Wait_LS_Stabilization(void) +{ + uint8_t ls_state; + uint16_t number_iteration; + volatile uint32_t period1; + uint32_t period2, tick_result; + + number_iteration = 0; + ls_state = WAIT_FREQ_MIN_STATE; + CKGEN_BLE->CLK32K_COUNT = SLOW_COUNT; + + while ((ls_state != LS_STABILIZATION_ENDED) && (number_iteration <= MAX_NUMBER_ITERATION)) { + + /* Stabilization State machine */ + switch(ls_state) + { + case WAIT_FREQ_MIN_STATE: + { + /* Wait until the LS freq is minor of 20 KHz */ + CKGEN_BLE->CLK32K_IT = 1; + CKGEN_BLE->CLK32K_PERIOD = 0; + while(CKGEN_BLE->CLK32K_IT == 0); + period1 = CKGEN_BLE->CLK32K_PERIOD; + if (period1 <= MIN_CLOCK_PERIOD) { + ls_state = WAIT_FREQ_STABILIZATION_STATE; + } + } + break; + case WAIT_FREQ_STABILIZATION_STATE: + { + CKGEN_BLE->CLK32K_IT = 1; + CKGEN_BLE->CLK32K_PERIOD = 0; + while(CKGEN_BLE->CLK32K_IT == 0); + period2 = CKGEN_BLE->CLK32K_PERIOD; + if (period2 > period1) + tick_result = period2 - period1; + else + tick_result = period1 - period2; + if (tick_result <= (period1>>10)) { + ls_state = LS_STABILIZATION_ENDED; + } + period1 = period2; + } + break; + default: + /* Nothing to do */ + break; + } + number_iteration++; + } +} + +/* Configure RF FrontEnd */ +void Set_RF_FrontEnd(void) +{ + uint8_t i=0; + + /* Hot table already populated, search the first free location */ + while (hot_table_radio_config[i] != 0) + i += (hot_table_radio_config[i] + 1); + + if ((i+3) < HOT_TABLE_RADIO_SIZE) { + /* Hot table configuraiton used only for smart power management */ + hot_table_radio_config[i] = NUMBER_CONFIG_BYTE; + hot_table_radio_config[i+1] = MOD_ANA_ENG_REG; + hot_table_radio_config[i+2] = CENTRAL_FREQ_MOD; + hot_table_radio_config[i+6] = END_CONFIG; + + BLUE_CTRL->RADIO_CONFIG = 0x10000U | (uint16_t)((uint32_t)(&hot_table_radio_config[i]) & 0x0000FFFFU); + while ((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); + } +} + +/* Function to store the BOR configuration and to populate the hot radio configuration table */ +void BOR_ConfigSave(uint8_t clock_low_eng_conf, uint8_t pmu_ana_user_conf) +{ + uint8_t i=0; + + /* Hot table already populated, search the first free location */ + while (hot_table_radio_config[i] != 0) + i += (hot_table_radio_config[i] + 1); + + if ((i+6) < HOT_TABLE_RADIO_SIZE) { + /* BOR configuration storage inside hot table used only for smart power managment */ + hot_table_radio_config[i] = NUMBER_CONFIG_BYTE; + hot_table_radio_config[i+1] = CLOCK_LOW_ENG_REG; + hot_table_radio_config[i+2] = clock_low_eng_conf; + hot_table_radio_config[i+3] = NUMBER_CONFIG_BYTE; + hot_table_radio_config[i+4] = PMU_ANA_USER_REG; + hot_table_radio_config[i+5] = pmu_ana_user_conf; + hot_table_radio_config[i+6] = END_CONFIG; + } + + /* BOR configuration storage used only for smart power managment */ + BOR_config[0] = NUMBER_CONFIG_BYTE; + BOR_config[1] = CLOCK_LOW_ENG_REG; + BOR_config[2] = clock_low_eng_conf; + BOR_config[3] = NUMBER_CONFIG_BYTE; + BOR_config[4] = PMU_ANA_USER_REG; + BOR_config[5] = pmu_ana_user_conf; + BOR_config[6] = END_CONFIG; +} + +/* Function to access the BLUE SPI registers to disable and restore the BOR configuration */ +void SET_BORconfigStatus(uint8_t enabled) +{ + uint8_t clock_conf, pmu_ana_conf; + + if (enabled) { + BLUE_CTRL->RADIO_CONFIG = 0x10000U | (uint16_t)((uint32_t)BOR_config & 0x0000FFFFU); + while ((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); + }else { + clock_conf = BOR_config[2]; + pmu_ana_conf = BOR_config[5]; + BOR_config[2] |= (1<<2); + BOR_config[5] &= ~(1<<2); + BLUE_CTRL->RADIO_CONFIG = 0x10000U | (uint16_t)((uint32_t)BOR_config & 0x0000FFFFU); + while ((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); + BOR_config[2] = clock_conf; + BOR_config[5] = pmu_ana_conf; + } +} + +void DeviceConfiguration(BOOL coldStart, BOOL waitLS_Ready) +{ + uint32_t current_time; + uint32_t Trimm_config; + uint8_t pmu_ana_user, clock_low_eng; + PartInfoType Device_partInfo; + volatile uint8_t cold_start_config[] = COLD_START_CONFIGURATION; + + /* Get partInfo */ + HAL_GetPartInfo(&Device_partInfo); + + if (coldStart) { + /* High Speed Crystal Configuration */ +#if (HS_SPEED_XTAL == HS_SPEED_XTAL_32MHZ) + cold_start_config[14] = HIGH_FREQ_32M; + /* Set 32MHz_SEL bit in the System controller register */ + SYSTEM_CTRL->CTRL_b.MHZ32_SEL = 1; +#elif (HS_SPEED_XTAL == HS_SPEED_XTAL_16MHZ) + cold_start_config[14] = HIGH_FREQ_16M; +#else +#error "No definition for High Speed Crystal" +#endif + + /* SMPS configuration */ +#if (SMPS_INDUCTOR == SMPS_INDUCTOR_10uH) + cold_start_config[11] = SMPS_ON; + cold_start_config[8] = SMPS_10uH_RM1; + cold_start_config[17] = SMPS_10uH_PMU; +#elif (SMPS_INDUCTOR == SMPS_INDUCTOR_4_7uH) + cold_start_config[11] = SMPS_ON; + cold_start_config[8] = SMPS_4_7uH_RM1; + cold_start_config[17] = SMPS_4_7uH_PMU; +#elif (SMPS_INDUCTOR == SMPS_INDUCTOR_NONE) + cold_start_config[11] = SMPS_OFF; +#else +#error "No definition for SMPS Configuration" +#endif + + /* Low Speed Crystal Source */ +#if (LS_SOURCE == LS_SOURCE_EXTERNAL_32KHZ) + cold_start_config[20] = LOW_FREQ_XO; +#elif (LS_SOURCE == LS_SOURCE_INTERNAL_RO) + cold_start_config[20] = LOW_FREQ_RO; +#else +#error "No definition for Low Speed Crystal Source" +#endif + + /* Setup RCO32K trimming value in PMU_ANA_USER_REG */ + Trimm_config = *(volatile uint32_t*)RCO32K_TRIMMING_FLASH_ADDR; + if ((Trimm_config >> 16) == CHECK_BYTES) { + cold_start_config[23] &= ~0x70; // Clear the register content bit 4-5-6 + cold_start_config[23] |= (Trimm_config&0x7)<<4; // Store the RCO32K trimming value in bit 4-5-6 + } + + /* Setup LDO1V2 trimming value in ATB1_ANA_ENG_REG */ + Trimm_config = *(volatile uint32_t*)LDO1V2_TRIMMING_FLASH_ADDR; + if ((Trimm_config >> 16) == CHECK_BYTES) { + cold_start_config[5] &= ~0x30; // Clear the register content of bit 4 and 5 + cold_start_config[5] |= (Trimm_config&0x3)<<4; // Store the LDO1V2 trimming value in bit 4 and 5 + } + + /* Setup Battery Level Detector Threshold value in PMU_ANA_USER_REG */ + Trimm_config = *(volatile uint32_t*)SET_BLD_LVL_TRIMMING_FLASH_ADDR; + if ((Trimm_config >> 16) == CHECK_BYTES) { + cold_start_config[23] &= ~0x03; // Clear the register content of bit 0 and 1 + cold_start_config[23] |= (Trimm_config&0x3); // Store the BLD_LVL trimming value in bit 0 and 1 + } + + /* BOR configuration. Note: this setup shall be executed after the SMPS configuration*/ +#if (BOR_CONFIG == BOR_ON) + /* Clear the 3 bit of the CLOCK_LOW_ENG_REG register */ + cold_start_config[11] &= ~(1<<2); + if (((Device_partInfo.die_major<<4)|(Device_partInfo.die_cut)) >= WA_DEVICE_VERSION) { + /* Set the 3 bit of the PMU_ANA_USER register */ + cold_start_config[23] |= (1<<2); + clock_low_eng = cold_start_config[11]; + pmu_ana_user = cold_start_config[23]; + BOR_ConfigSave(clock_low_eng, pmu_ana_user); + } +#elif (BOR_CONFIG == BOR_OFF) + /* Set the 3 bit of the CLOCK_LOW_ENG_REG register */ + cold_start_config[11] |= (1<<2); + if (((Device_partInfo.die_major<<4)|(Device_partInfo.die_cut)) >= WA_DEVICE_VERSION) { + /* Clear the 3 bit of the PMU_ANA_USER register */ + cold_start_config[23] &= ~(1<<2); + clock_low_eng = cold_start_config[11]; + pmu_ana_user = cold_start_config[23]; + BOR_ConfigSave(clock_low_eng, pmu_ana_user); + } +#else +#error "No definition for BOR Configuration" +#endif + + /* Cold start configuration device */ + BLUE_CTRL->RADIO_CONFIG = 0x10000U | (uint16_t)((uint32_t)cold_start_config & 0x0000FFFFU); + while ((BLUE_CTRL->RADIO_CONFIG & 0x10000) != 0); + + /* Configure RF FrontEnd */ + if (((Device_partInfo.die_major<<4)|(Device_partInfo.die_cut)) >= WA_DEVICE_VERSION) { + Set_RF_FrontEnd(); + } + + } + + /* Wait until HS is ready. The slow clock period + * measurement is done automatically each time the + * device enters in active2 state and the HS is ready. + * The interrupt signals that a measurement is done. + */ + while(CKGEN_BLE->CLK32K_IT == 0); + CKGEN_BLE->CLK32K_IT = 1; + CKGEN_BLE->CLK32K_COUNT = 23; //Restore the window length for slow clock measurement. + CKGEN_BLE->CLK32K_PERIOD = 0; + + + /* Wait until the RO or 32KHz is ready */ + if (waitLS_Ready) { + current_time = BLUE_CTRL->CURRENT_TIME; + while(((BLUE_CTRL->CURRENT_TIME)&0x10) == (current_time&0x10)); +#if (LS_SOURCE == LS_SOURCE_INTERNAL_RO) + /* Wait the LS stabilization */ + Wait_LS_Stabilization(); +#endif + } + + if (coldStart) { +#if (HS_SPEED_XTAL == HS_SPEED_XTAL_32MHZ) +#if (FORCE_CORE_TO_16MHZ == 1) + /* AHB up converter command register write*/ + AHBUPCONV->COMMAND = 0x14; +#else + /* AHB up converter command register write*/ + AHBUPCONV->COMMAND = 0x15; +#endif +#endif + } + + /* Unlock the Flash */ + flash_sw_lock = FLASH_UNLOCK_WORD; +} + +void SystemInit(void) +{ + /* Remap the vector table */ + FLASH->CONFIG = FLASH_PREMAP_MAIN; + + /* Configure all the interrupts priority. + * The application can modify the interrupts priority. + * The PendSV_IRQn and BLUE_CTRL_IRQn SHALL maintain the highest priority + */ + NVIC_SetPriority(PendSV_IRQn, LOW_PRIORITY); + NVIC_SetPriority(SysTick_IRQn, LOW_PRIORITY); + NVIC_SetPriority(GPIO_IRQn, LOW_PRIORITY); + NVIC_SetPriority(NVM_IRQn, LOW_PRIORITY); + NVIC_SetPriority(UART_IRQn, LOW_PRIORITY); + NVIC_SetPriority(SPI_IRQn, LOW_PRIORITY); + NVIC_SetPriority(BLUE_CTRL_IRQn, CRITICAL_PRIORITY); + NVIC_SetPriority(WDG_IRQn, LOW_PRIORITY); + NVIC_SetPriority(ADC_IRQn, LOW_PRIORITY); + NVIC_SetPriority(I2C2_IRQn, LOW_PRIORITY); + NVIC_SetPriority(I2C1_IRQn, LOW_PRIORITY); + NVIC_SetPriority(MFT1A_IRQn, LOW_PRIORITY); + NVIC_SetPriority(MFT1B_IRQn, LOW_PRIORITY); + NVIC_SetPriority(MFT2A_IRQn, LOW_PRIORITY); + NVIC_SetPriority(MFT2B_IRQn, LOW_PRIORITY); + NVIC_SetPriority(RTC_IRQn, LOW_PRIORITY); + NVIC_SetPriority(PKA_IRQn, LOW_PRIORITY); + NVIC_SetPriority(DMA_IRQn, LOW_PRIORITY); + + /* Device Configuration */ + DeviceConfiguration(TRUE, TRUE); + /* Disable all the peripherals clock except NVM, SYSCTR, PKA and RNG */ + CKGEN_SOC->CLOCK_EN = 0xE0066; + __enable_irq(); +} + + +/******************* (C) COPYRIGHT 2017 STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STMBLUE/i2c_api.c b/targets/TARGET_STMBLUE/i2c_api.c new file mode 100644 index 00000000000..197d7c4cffd --- /dev/null +++ b/targets/TARGET_STMBLUE/i2c_api.c @@ -0,0 +1,51 @@ + + +#include "i2c_api.h" +#include "BlueNRG1_sysCtrl.h" +#include "BlueNRG1_i2c.h" + +#if DEVICE_I2C + +void i2c_init(i2c_t *obj, PinName sda, PinName scl){} + +void i2c_frequency(i2c_t *obj, int hz){} + +int i2c_start(i2c_t *obj){} + +int i2c_stop(i2c_t *obj){} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop){} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop){} + +void i2c_reset(i2c_t *obj){} + +int i2c_byte_read(i2c_t *obj, int last){} + +int i2c_byte_write(i2c_t *obj, int data){} + +#ifdef ANTONIO_armclang +const PinMap *i2c_master_sda_pinmap(void){} + +const PinMap *i2c_master_scl_pinmap(void){} + +const PinMap *i2c_slave_sda_pinmap(void){} + +const PinMap *i2c_slave_scl_pinmap(void){} +#endif //ANTONIO_armclang + + +#if DEVICE_I2CSLAVE + +void i2c_slave_mode(i2c_t *obj, int enable_slave){} + +int i2c_slave_receive(i2c_t *obj){} + +int i2c_slave_read(i2c_t *obj, char *data, int length){} + +int i2c_slave_write(i2c_t *obj, const char *data, int length){} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask){} + +#endif //DEVICE_I2CSLAVE +#endif //DEVICE_I2C diff --git a/targets/TARGET_STMBLUE/mbed_overrides.c b/targets/TARGET_STMBLUE/mbed_overrides.c new file mode 100644 index 00000000000..1ab21b35a6c --- /dev/null +++ b/targets/TARGET_STMBLUE/mbed_overrides.c @@ -0,0 +1,42 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include "cmsis.h" +#include "Periph_Driver/inc/BlueNRG1_sysCtrl.h" +#include "system_bluenrg.h" +#include "cmsis_nvic.h" +#include "bluenrg1_stack.h" +#include "DTM_boot.h" + +// This function is called after RAM initialization and before main. + +int mbed_sdk_inited =0; +void mbed_sdk_init() +{ + DTM_SystemInit(); + DTM_StackInit(); + + //Map RAL_Isr() for Blue_Handler into RAM, and remap the whole ISR vector + //and set CRITICAL PRIORITY to BLUE_CTRL_IRQn + core_util_critical_section_enter(); + NVIC_SetVector(BLUE_CTRL_IRQn, (uint32_t)&RAL_Isr); + NVIC_SetPriority(BLUE_CTRL_IRQn, 0); //0 = CRITICAL_PRIORITY + core_util_critical_section_exit(); + + mbed_sdk_inited = 1; +} diff --git a/targets/TARGET_STMBLUE/mbed_rtx.h b/targets/TARGET_STMBLUE/mbed_rtx.h new file mode 100644 index 00000000000..0ccec3f8142 --- /dev/null +++ b/targets/TARGET_STMBLUE/mbed_rtx.h @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#if MBED_MBED_RTX_H + +#include + +#ifndef INITIAL_SP + +#if (defined(TARGET_BLUENRG1)) +#define INITIAL_SP (0x20006000UL) + +#elif (defined(TARGET_BLUENRG2)) +#define INITIAL_SP (0x20006000UL) //TBC + +#else +#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file" +#endif + +#endif // INITIAL_SP + +#if (defined(TARGET_BLUENRG2)) +#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION)) +extern uint32_t __StackLimit; +extern uint32_t __StackTop; +extern uint32_t __end__; +extern uint32_t __HeapLimit; +#define HEAP_START ((unsigned char*) &__end__) +#define HEAP_SIZE ((uint32_t)((uint32_t) &__HeapLimit - (uint32_t) HEAP_START)) +#define ISR_STACK_START ((unsigned char*) &__StackLimit) +#define ISR_STACK_SIZE ((uint32_t)((uint32_t) &__StackTop - (uint32_t) &__StackLimit)) +#endif + +#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE +#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE +#endif +#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072 //da rivedere + +#endif + +#endif // MBED_MBED_RTX_H diff --git a/targets/TARGET_STMBLUE/pinmap.c b/targets/TARGET_STMBLUE/pinmap.c new file mode 100644 index 00000000000..e8bd7a7a084 --- /dev/null +++ b/targets/TARGET_STMBLUE/pinmap.c @@ -0,0 +1,23 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include "pinmap.h" + +void pin_function(PinName pin, int data){} + +void pin_mode(PinName pin, PinMode mode){} diff --git a/targets/TARGET_STMBLUE/serial_api.c b/targets/TARGET_STMBLUE/serial_api.c new file mode 100644 index 00000000000..3d593b30ddd --- /dev/null +++ b/targets/TARGET_STMBLUE/serial_api.c @@ -0,0 +1,212 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#if DEVICE_SERIAL + +#include "serial_api.h" +#include "device.h" +#include "BlueNRG1_sysCtrl.h" +#include "misc.h" + + +int stdio_uart_inited = 0;// used in platform/mbed_board.c and platform/mbed_retarget.cpp +serial_t stdio_uart; + +static uart_irq_handler irq_handler; +static uint32_t serial_irq_ids = 0; + +void serial_init(serial_t *obj, PinName tx, PinName rx){ + + //GPIO and UART Peripherals clock enable + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_UART | CLOCK_PERIPH_GPIO, ENABLE); + + //This statement is valid for both BlueNRG1-2, developed under DK 3.0.0 + //GPIO TX config + switch(tx){ + case USBTX: + GPIO_InitUartTxPin8(); + break; + case IO_5: + GPIO_InitUartTxPin5(); + break; + default: + error("The selected is not UART_TX capable. Choose the correct pin."); + break; + } + //GPIO RX config + switch(rx){ + case USBRX: + GPIO_InitUartRxPin11(); + break; + case IO_4: + GPIO_InitUartRxPin4(); + break; + default: + error("The selected is not UART_RX capable. Choose the correct pin."); + break; + } + /* + ------------ UART configuration ------------------- + - BaudRate = 115200 baud + - Word Length = 8 Bits + - One Stop Bit + - No parity + - Hardware flow control disabled (RTS and CTS signals) + - Receive and transmit enabled + */ + UART_StructInit(&obj->serial.init); + UART_Init(&obj->serial.init); + + obj->serial.uart = UART_1; + + //obj->init = &UART_InitStructure; + obj->serial.pin_tx = tx; + obj->serial.pin_rx = rx; + + /* Interrupt as soon as data is received. */ + UART_RxFifoIrqLevelConfig(FIFO_LEV_1_64); + + /* Enable UART */ + UART_Cmd(ENABLE); + + // For stdio management in platform/mbed_board.c and platform/mbed_retarget.cpp + if (tx==USBTX && rx==USBRX) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj){ + UART_DeInit(); + UART_Cmd(DISABLE); + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_UART, DISABLE); + obj->serial.index_irq = 0; + obj->serial.init.UART_BaudRate = 0; + /** + * One has to release also the GPIO assigned to the UART. In this case the + * GPIO release is not performed since it has been initialized with pull and + * high power mode disable. + */ +} + +void serial_baud(serial_t *obj, int baudrate){ + obj->serial.init.UART_BaudRate = baudrate; + UART_Init(&obj->serial.init); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits){ + obj->serial.init.UART_WordLengthTransmit = (uint8_t)data_bits; + obj->serial.init.UART_WordLengthReceive = (uint8_t)data_bits; + obj->serial.init.UART_Parity = (uint8_t)parity; + obj->serial.init.UART_StopBits= (uint8_t)stop_bits; + UART_Init(&obj->serial.init); +} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id){ + irq_handler = handler; + serial_irq_ids = id; + //obj->index_irq = id; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable){ + /* NVIC configuration */ + NVIC_InitType NVIC_InitStructure; + /* Enable the UART Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = UART_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = LOW_PRIORITY; + NVIC_InitStructure.NVIC_IRQChannelCmd = enable; + NVIC_Init(&NVIC_InitStructure); + //UART_ITConfig(UART_IT_RX, enable); + if (irq == RxIrq) + UART_ITConfig(UART_IT_RX, enable); + else// TxIrq + UART_ITConfig(UART_IT_TX, enable); +} + +int serial_getc(serial_t *obj){ + /* Loop until the UART Receive Data Register is not empty */ + while (UART_GetFlagStatus(UART_FLAG_RXFE) == SET); + /* Store the received byte in RxBuffer */ + return (int) UART_ReceiveData(); +} + +void serial_putc(serial_t *obj, int c){ + /* Wait if TX fifo is full. */ + while (UART_GetFlagStatus(UART_FLAG_TXFF) == SET); + /* send the data */ + UART_SendData((uint16_t)c); +} + +int serial_readable(serial_t *obj){ + // To avoid a target blocking case, let's check for possible OVERRUN error and discard it + if(UART_GetFlagStatus(UART_FLAG_OE)){ + UART_ClearFlag(UART_FLAG_OE); + } + return !UART_GetFlagStatus(UART_FLAG_RXFE); +} + +int serial_writable(serial_t *obj){ + return UART_GetFlagStatus(UART_FLAG_TXFF); +} + +void serial_clear(serial_t *obj){} + +void serial_break_set(serial_t *obj){} + +void serial_break_clear(serial_t *obj){} + +void serial_pinout_tx(PinName tx){} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow){} + +const PinMap *serial_tx_pinmap(void){} + +const PinMap *serial_rx_pinmap(void){} + +const PinMap *serial_cts_pinmap(void){} + +const PinMap *serial_rts_pinmap(void){} + +#if DEVICE_SERIAL_ASYNCH + +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint){} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint){} + +uint8_t serial_tx_active(serial_t *obj){} + +uint8_t serial_rx_active(serial_t *obj){} + +int serial_irq_handler_asynch(serial_t *obj){} + +void serial_tx_abort_asynch(serial_t *obj){} + +void serial_rx_abort_asynch(serial_t *obj){} + +#endif + +/* Function used to protect deep sleep while a serial transmission is on-going. + * Returns 1 if there is at least 1 serial instance with an on-going transfer + * and 0 otherwise. + * HANDLED IN sleep_api.c +*/ +uint8_t serialTxActive(void) { + return(UART_GetFlagStatus(UART_FLAG_TXFE) == RESET); +} + +#endif //DEVICE_SERIAL diff --git a/targets/TARGET_STMBLUE/sleep_api.c b/targets/TARGET_STMBLUE/sleep_api.c new file mode 100644 index 00000000000..25d9fee68f6 --- /dev/null +++ b/targets/TARGET_STMBLUE/sleep_api.c @@ -0,0 +1,572 @@ +/* + * Copyright (c) 2019 STMicroelectronics. All Rights Reserved. + * + * The information contained herein is property of STMicroelectronics. + * Terms and conditions of usage are described in detail in SOFTWARE + * LICENSE AGREEMENT: + * + * (SLA0068 - PRODUCTION LIMITED LICENSE AGREEMENT FOR ST MATERIALS) + * + * You may obtain a copy of the License here: + * LICENSE-SLA0068.txt and at STMicroelectronics website. + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + */ + +#if DEVICE_SLEEP + +#define GPIO_WAKE_BIT_MASK 31 // IO13 | IO12 | IO11 | IO10 | IO9 +#define GPIO_WAKE_LEVEL_MASK 0 // asserted pin in GPIO_WAKE_BIT_MASK are asserted at the value in the same position of this mask + +#define SHPR3_REG 0xE000ED20 + +#define WAKENED_FROM_IO9 0x09 +#define WAKENED_FROM_IO10 0x11 +#define WAKENED_FROM_IO11 0x21 +#define WAKENED_FROM_IO12 0x41 +#define WAKENED_FROM_IO13 0x81 +#define WAKENED_FROM_BLUE_TIMER1 0x101 +#define WAKENED_FROM_BLUE_TIMER2 0x401 + +#define LOW_POWER_STANDBY 0x03 + +#define BLUE_CURRENT_TIME_REG 0x48000010 + +#include "sleep_api.h" +#include "bluenrg1_stack.h" +#include "misc.h" +#include "miscutil.h" + + +//BlueNRG2 sleepmodes types +typedef enum { + SLEEPMODE_RUNNING = 0, + SLEEPMODE_CPU_HALT = 1, + SLEEPMODE_WAKETIMER = 2, + SLEEPMODE_NOTIMER = 3, +} SleepModes; + +uint32_t cStackPreamble[CSTACK_PREAMBLE_NUMBER]; +volatile uint32_t* ptr ; + +static void BlueNRG_HaltCPU(void){ + // Store the watchdog configuration and the disable it to avoid reset during CPU halt. + uint32_t WDG_CR_saved = WDG->CR; + WDG->CR = 0; + + // Wait for interrupt is called: the core execution is halted until an event occurs. + __WFI(); + + // Restore the watchdog functionality. + WDG->CR= WDG_CR_saved; +} + +static void BlueNRG_DeepSleep(SleepModes sleepMode, uint8_t gpioWakeBitMask) +{ + uint32_t savedCurrentTime, nvicPendingMask; + PartInfoType partInfo; + uint8_t i; + /* System Control saved */ + uint32_t SYS_Ctrl_saved; + /* NVIC Information Saved */ + uint32_t NVIC_ISER_saved, NVIC_IPR_saved[8], PENDSV_SYSTICK_IPR_saved; + /* CKGEN SOC Enabled */ + uint32_t CLOCK_EN_saved; + /* GPIO Information saved */ + uint32_t GPIO_DATA_saved, GPIO_OEN_saved, GPIO_PE_saved, GPIO_DS_saved, GPIO_IS_saved, GPIO_IBE_saved; + uint32_t GPIO_IEV_saved, GPIO_IE_saved, GPIO_MODE0_saved, GPIO_MODE1_saved, GPIO_IOSEL_MFTX_saved; +#ifdef BLUENRG2_DEVICE + uint32_t GPIO_MODE2_saved, GPIO_MODE3_saved; +#endif + /* UART Information saved */ + uint32_t UART_TIMEOUT_saved, UART_LCRH_RX_saved, UART_IBRD_saved, UART_FBRD_saved; + uint32_t UART_LCRH_TX_saved, UART_CR_saved, UART_IFLS_saved, UART_IMSC_saved; + uint32_t UART_DMACR_saved, UART_XFCR_saved, UART_XON1_saved, UART_XON2_saved; + uint32_t UART_XOFF1_saved, UART_XOFF2_saved; + /* SPI Information saved */ + uint32_t SPI_CR0_saved, SPI_CR1_saved, SPI_CPSR_saved, SPI_IMSC_saved, SPI_DMACR_saved; + uint32_t SPI_RXFRM_saved, SPI_CHN_saved, SPI_WDTXF_saved; + /* I2C Information saved */ + uint32_t I2C_CR_saved[2], I2C_SCR_saved[2], I2C_TFTR_saved[2], I2C_RFTR_saved[2]; + uint32_t I2C_DMAR_saved[2], I2C_BRCR_saved[2], I2C_IMSCR_saved[2], I2C_THDDAT_saved[2]; + uint32_t I2C_THDSTA_FST_STD_saved[2], I2C_TSUSTA_FST_STD_saved[2]; + /* RNG Information saved */ + uint32_t RNG_CR_saved; + /* SysTick Information saved */ + uint32_t SYST_CSR_saved, SYST_RVR_saved; + /* RTC Information saved */ + uint32_t RTC_CWDMR_saved, RTC_CWDLR_saved, RTC_CWYMR_saved, RTC_CWYLR_saved, RTC_CTCR_saved; + uint32_t RTC_IMSC_saved, RTC_TCR_saved, RTC_TLR1_saved, RTC_TLR2_saved, RTC_TPR1_saved; + uint32_t RTC_TPR2_saved, RTC_TPR3_saved, RTC_TPR4_saved; + /* MFTX Information saved */ + uint32_t T1CRA_saved, T1CRB_saved, T1PRSC_saved, T1CKC_saved, T1MCTRL_saved, T1ICTRL_saved; + uint32_t T2CRA_saved, T2CRB_saved, T2PRSC_saved, T2CKC_saved, T2MCTRL_saved, T2ICTRL_saved; + /* WDT Information saved */ + uint32_t WDG_LR_saved, WDG_CR_saved, WDG_LOCK_saved; + /* DMA channel [0..7] Information saved */ + uint32_t DMA_CCR_saved[8], DMA_CNDTR_saved[8], DMA_CPAR_saved[8], DMA_CMAR[8]; + /* ADC Information saved */ + uint32_t ADC_CTRL_saved, ADC_CONF_saved, ADC_IRQMASK_saved, ADC_OFFSET_LSB_saved, ADC_OFFSET_MSB_saved; + uint32_t ADC_THRESHOLD_HI_saved, ADC_THRESHOLD_LO_saved; + /* FlASH Config saved */ + uint32_t FLASH_CONFIG_saved; + /* PKA Information saved */ + uint32_t PKA_IEN_saved; + + /* Get partInfo */ + HAL_GetPartInfo(&partInfo); + + /* Save the peripherals configuration */ + /* System Control */ + SYS_Ctrl_saved = SYSTEM_CTRL->CTRL; + /* FLASH CONFIG */ + FLASH_CONFIG_saved = FLASH->CONFIG; + /* NVIC */ + NVIC_ISER_saved = NVIC->ISER[0]; + + // Issue with Atollic compiler +// memcpy(NVIC_IPR_saved, (void const *)NVIC->IP, sizeof(NVIC_IPR_saved)); + for (i=0; i<8; i++) { + NVIC_IPR_saved[i] = NVIC->IP[i]; + } + + + PENDSV_SYSTICK_IPR_saved = *(volatile uint32_t *)SHPR3_REG; + /* CKGEN SOC Enabled */ + CLOCK_EN_saved = CKGEN_SOC->CLOCK_EN; + /* GPIO */ + GPIO_DATA_saved = GPIO->DATA; + GPIO_OEN_saved = GPIO->OEN; + GPIO_PE_saved = GPIO->PE; + GPIO_DS_saved = GPIO->DS; + GPIO_IS_saved = GPIO->IS; + GPIO_IBE_saved = GPIO->IBE; + GPIO_IEV_saved = GPIO->IEV; + GPIO_IE_saved = GPIO->IE; + GPIO_MODE0_saved = GPIO->MODE0; + GPIO_MODE1_saved = GPIO->MODE1; +#ifdef BLUENRG2_DEVICE + GPIO_MODE2_saved = GPIO->MODE2; + GPIO_MODE3_saved = GPIO->MODE3; +#endif + GPIO_IOSEL_MFTX_saved = GPIO->MFTX; + /* UART */ + UART_TIMEOUT_saved = UART->TIMEOUT; + UART_LCRH_RX_saved = UART->LCRH_RX; + UART_IBRD_saved = UART->IBRD; + UART_FBRD_saved = UART->FBRD; + UART_LCRH_TX_saved = UART->LCRH_TX; + UART_CR_saved = UART->CR; + UART_IFLS_saved = UART->IFLS; + UART_IMSC_saved = UART->IMSC; + UART_DMACR_saved = UART->DMACR; + UART_XFCR_saved = UART->XFCR; + UART_XON1_saved = UART->XON1; + UART_XON2_saved = UART->XON2; + UART_XOFF1_saved = UART->XOFF1; + UART_XOFF2_saved = UART->XOFF2; + /* SPI */ + SPI_CR0_saved = SPI1->CR0; + SPI_CR1_saved = SPI1->CR1; + SPI_CPSR_saved = SPI1->CPSR; + SPI_IMSC_saved = SPI1->IMSC; + SPI_DMACR_saved = SPI1->DMACR; + SPI_RXFRM_saved = SPI1->RXFRM; + SPI_CHN_saved = SPI1->CHN; + SPI_WDTXF_saved = SPI1->WDTXF; + /* I2C */ + for (i=0; i<2; i++) { + I2C_Type *I2Cx = (I2C_Type*)(I2C2_BASE+ 0x100000*i); + I2C_CR_saved[i] = I2Cx->CR; + I2C_SCR_saved[i] = I2Cx->SCR; + I2C_TFTR_saved[i] = I2Cx->TFTR; + I2C_RFTR_saved[i] = I2Cx->RFTR; + I2C_DMAR_saved[i] = I2Cx->DMAR; + I2C_BRCR_saved[i] = I2Cx->BRCR; + I2C_IMSCR_saved[i] = I2Cx->IMSCR; + I2C_THDDAT_saved[i] = I2Cx->THDDAT; + I2C_THDSTA_FST_STD_saved[i] = I2Cx->THDSTA_FST_STD; + I2C_TSUSTA_FST_STD_saved[i] = I2Cx->TSUSTA_FST_STD; + } + /* RNG */ + RNG_CR_saved = RNG->CR; + /* RTC */ + RTC_CWDMR_saved = RTC->CWDMR; + RTC_CWDLR_saved = RTC->CWDLR; + RTC_CWYMR_saved = RTC->CWYMR; + RTC_CWYLR_saved = RTC->CWYLR; + RTC_CTCR_saved = RTC->CTCR; + RTC_IMSC_saved = RTC->IMSC; + RTC_TCR_saved = RTC->TCR; + RTC_TLR1_saved = RTC->TLR1; + RTC_TLR2_saved = RTC->TLR2; + RTC_TPR1_saved = RTC->TPR1; + RTC_TPR2_saved = RTC->TPR2; + RTC_TPR3_saved = RTC->TPR3; + RTC_TPR4_saved = RTC->TPR4; + /* MFTX */ + T1CRA_saved = MFT1->TNCRA; + T1CRB_saved = MFT1->TNCRB; + T1PRSC_saved = MFT1->TNPRSC; + T1CKC_saved = MFT1->TNCKC; + T1MCTRL_saved = MFT1->TNMCTRL; + T1ICTRL_saved = MFT1->TNICTRL; + T2CRA_saved = MFT2->TNCRA; + T2CRB_saved = MFT2->TNCRB; + T2PRSC_saved = MFT2->TNPRSC; + T2CKC_saved = MFT2->TNCKC; + T2MCTRL_saved = MFT2->TNMCTRL; + T2ICTRL_saved = MFT2->TNICTRL; + /* SysTick */ + SYST_CSR_saved = SysTick->CTRL; + SYST_RVR_saved = SysTick->LOAD; + /* WDT */ + WDG_LR_saved = WDG->LR; + WDG_CR_saved = WDG->CR; + if(WDG->LOCK == 0) { + WDG_LOCK_saved = 0x1ACCE551; + } else { + WDG_LOCK_saved = 0; + } + /* DMA */ + for (i=0; i<8; i++) { + DMA_CH_Type *DMAx = (DMA_CH_Type*)(DMA_CH0_BASE+ 0x14*i); + DMA_CNDTR_saved[i] = DMAx->CNDTR; + DMA_CCR_saved[i] = DMAx->CCR; + DMA_CPAR_saved[i] = DMAx->CPAR; + DMA_CMAR[i] = DMAx->CMAR; + } + /* ADC */ + ADC_CONF_saved = ADC->CONF; + ADC_IRQMASK_saved = ADC->IRQMASK; + ADC_OFFSET_MSB_saved = ADC->OFFSET_MSB; + ADC_OFFSET_LSB_saved = ADC->OFFSET_LSB; + ADC_THRESHOLD_HI_saved = ADC->THRESHOLD_HI; + ADC_THRESHOLD_LO_saved = ADC->THRESHOLD_LO; + ADC_CTRL_saved = ADC->CTRL; + + /* PKA */ + PKA_IEN_saved = PKA->IEN; + + // Enable the STANDBY mode + if (sleepMode == SLEEPMODE_NOTIMER) { + BLUE_CTRL->TIMEOUT |= LOW_POWER_STANDBY<<28; + } + + //Save the CSTACK number of words that will be restored at wakeup reset + i = 0; + ptr = __vector_table[0].__ptr ; + ptr -= CSTACK_PREAMBLE_NUMBER; + do { + cStackPreamble[i] = *ptr; + i++; + ptr++; + } while (i < CSTACK_PREAMBLE_NUMBER); + + if (((partInfo.die_major<<4)|(partInfo.die_cut)) >= WA_DEVICE_VERSION) { + /* Lock the flash */ + flash_sw_lock = FLASH_LOCK_WORD; + /* Disable BOR */ + SET_BORconfigStatus(FALSE); + } + + //Enable deep sleep + SystemSleepCmd(ENABLE); + //The __disable_irq() used at the beginning of the BlueNRG_Sleep() function + //masks all the interrupts. The interrupts will be enabled at the end of the + //context restore. Now induce a context save. + void CS_contextSave(void); + CS_contextSave(); + + //Disable deep sleep, because if no reset occours for an interrrupt pending, + //the register value remain set and if a simple CPU_HALT command is called from the + //application the BlueNRG-1 enters in deep sleep without make a context save. + //So, exiting from the deep sleep the context is restored with wrong random value. + SystemSleepCmd(DISABLE); + + if (!wakeupFromSleepFlag) { + if((NVIC->ISPR[0]&(1<ISPR[0]; + if ((savedSHCSR != SCB->SHCSR) || //Verified if a SVCall Interrupt is pending + ((savedNVIC_ISPR != NVIC->ISPR[0]) && (nvicPendingMask & NVIC->ISER[0])) || //Verified if a NVIC Interrupt is pending + ((savedICSR & 0x10000000) != (SCB->ICSR & 0x10000000)) || // Verified if a PendSV interrupt is pending + (((savedICSR & 0x4000000) != (SCB->ICSR & 0x4000000)) && (SysTick->CTRL & 0x02))) { // Verified if a SysTick interrupt is pending + savedCurrentTime = (*(volatile uint32_t *)BLUE_CURRENT_TIME_REG) >> 4; + if (0xFFFFF >= (savedCurrentTime+3)) { //Check if the counter are wrapping + while ((savedCurrentTime+3) > ((*(volatile uint32_t *)BLUE_CURRENT_TIME_REG) >> 4)); //Not Wrap + } else { + while (((*(volatile uint32_t *)BLUE_CURRENT_TIME_REG) >> 4) != (savedCurrentTime + 3 - 0xFFFFF)); //Wrap + } + } + } + + if (((partInfo.die_major<<4)|(partInfo.die_cut)) >= WA_DEVICE_VERSION) { + /* Restore BOR configuration */ + SET_BORconfigStatus(TRUE); + /* Unlock the flash */ + flash_sw_lock = FLASH_UNLOCK_WORD; + } + + // Disable the STANDBY mode + if (sleepMode == SLEEPMODE_NOTIMER) { + BLUE_CTRL->TIMEOUT &= ~(LOW_POWER_STANDBY<<28); + } + + } else { + + /* Start a new calibration, needed to signal if the HS is ready */ + CKGEN_BLE->CLK32K_IT = 1; + CKGEN_BLE->CLK32K_COUNT = 0; + CKGEN_BLE->CLK32K_PERIOD = 0; + + /* Restore the CSTACK number of words that will be saved before the sleep */ + i = 0; + ptr = __vector_table[0].__ptr ; + ptr -= CSTACK_PREAMBLE_NUMBER; + do { + *ptr = cStackPreamble[i]; + i++; + ptr++; + } while (i < CSTACK_PREAMBLE_NUMBER); + + + /* Restore the peripherals configuration */ + /* FLASH CONFIG */ + FLASH->CONFIG = FLASH_CONFIG_saved; + /* NVIC */ + NVIC->ISER[0] = NVIC_ISER_saved; + + for (i=0; i<8; i++) { + NVIC->IP[i] = NVIC_IPR_saved[i]; + } + + *(volatile uint32_t *)SHPR3_REG = PENDSV_SYSTICK_IPR_saved; + /* CKGEN SOC Enabled */ + CKGEN_SOC->CLOCK_EN = CLOCK_EN_saved; + /* GPIO */ + GPIO->DATA = GPIO_DATA_saved; + GPIO->OEN = GPIO_OEN_saved; + GPIO->PE = GPIO_PE_saved; + GPIO->DS = GPIO_DS_saved; + GPIO->IEV = GPIO_IEV_saved; + GPIO->IBE = GPIO_IBE_saved; + GPIO->IS = GPIO_IS_saved; + GPIO->IC = GPIO_IE_saved; + GPIO->IE = GPIO_IE_saved; + GPIO->MODE0 = GPIO_MODE0_saved; + GPIO->MODE1 = GPIO_MODE1_saved; +#ifdef BLUENRG2_DEVICE + GPIO->MODE2 = GPIO_MODE2_saved; + GPIO->MODE3 = GPIO_MODE3_saved; +#endif + GPIO->MFTX = GPIO_IOSEL_MFTX_saved; + /* UART */ + UART->TIMEOUT = UART_TIMEOUT_saved; + UART->LCRH_RX = UART_LCRH_RX_saved; + UART->IBRD = UART_IBRD_saved; + UART->FBRD = UART_FBRD_saved; + UART->LCRH_TX = UART_LCRH_TX_saved; + UART->CR = UART_CR_saved; + UART->IFLS = UART_IFLS_saved; + UART->IMSC = UART_IMSC_saved; + UART->DMACR = UART_DMACR_saved; + UART->XFCR = UART_XFCR_saved; + UART->XON1 = UART_XON1_saved; + UART->XON2 = UART_XON2_saved; + UART->XOFF1 = UART_XOFF1_saved; + UART->XOFF2 = UART_XOFF2_saved; + /* SPI */ + SPI1->CR0 = SPI_CR0_saved; + SPI1->CR1 = SPI_CR1_saved; + SPI1->CPSR = SPI_CPSR_saved; + SPI1->IMSC = SPI_IMSC_saved; + SPI1->DMACR = SPI_DMACR_saved; + SPI1->RXFRM = SPI_RXFRM_saved; + SPI1->CHN = SPI_CHN_saved; + SPI1->WDTXF = SPI_WDTXF_saved; + /* I2C */ + for (i=0; i<2; i++) { + I2C_Type *I2Cx = (I2C_Type*)(I2C2_BASE+ 0x100000*i); + I2Cx->CR = I2C_CR_saved[i]; + I2Cx->SCR = I2C_SCR_saved[i]; + I2Cx->TFTR = I2C_TFTR_saved[i]; + I2Cx->RFTR = I2C_RFTR_saved[i]; + I2Cx->DMAR = I2C_DMAR_saved[i]; + I2Cx->BRCR = I2C_BRCR_saved[i]; + I2Cx->IMSCR = I2C_IMSCR_saved[i]; + I2Cx->THDDAT = I2C_THDDAT_saved[i]; + I2Cx->THDSTA_FST_STD = I2C_THDSTA_FST_STD_saved[i]; + I2Cx->TSUSTA_FST_STD = I2C_TSUSTA_FST_STD_saved[i]; + } + /* RNG */ + RNG->CR = RNG_CR_saved; + /* SysTick */ + SysTick->LOAD = SYST_RVR_saved; + SysTick->VAL = 0; + SysTick->CTRL = SYST_CSR_saved; + /* RTC */ + RTC->CWDMR = RTC_CWDMR_saved; + RTC->CWDLR = RTC_CWDLR_saved; + RTC->CWYMR = RTC_CWYMR_saved; + RTC->CWYLR = RTC_CWYLR_saved; + RTC->CTCR = RTC_CTCR_saved; + RTC->IMSC = RTC_IMSC_saved; + RTC->TLR1 = RTC_TLR1_saved; + RTC->TLR2 = RTC_TLR2_saved; + RTC->TPR1 = RTC_TPR1_saved; + RTC->TPR2 = RTC_TPR2_saved; + RTC->TPR3 = RTC_TPR3_saved; + RTC->TPR4 = RTC_TPR4_saved; + RTC->TCR = RTC_TCR_saved; /* Enable moved at the end of RTC configuration */ + /* MFTX */ + MFT1->TNCRA = T1CRA_saved; + MFT1->TNCRB = T1CRB_saved; + MFT1->TNPRSC = T1PRSC_saved; + MFT1->TNCKC = T1CKC_saved; + MFT1->TNMCTRL = T1MCTRL_saved; + MFT1->TNICTRL = T1ICTRL_saved; + MFT2->TNCRA = T2CRA_saved; + MFT2->TNCRB = T2CRB_saved; + MFT2->TNPRSC = T2PRSC_saved; + MFT2->TNCKC = T2CKC_saved; + MFT2->TNMCTRL = T2MCTRL_saved; + MFT2->TNICTRL = T2ICTRL_saved; + /* WDT */ + WDG->LR = WDG_LR_saved; + WDG->CR = WDG_CR_saved; + WDG->LOCK = WDG_LOCK_saved; + /* DMA */ + for (i=0; i<8; i++) { + DMA_CH_Type *DMAx = (DMA_CH_Type*)(DMA_CH0_BASE+ 0x14*i); + DMAx->CNDTR = DMA_CNDTR_saved[i]; + DMAx->CCR = DMA_CCR_saved[i] ; + DMAx->CPAR = DMA_CPAR_saved[i]; + DMAx->CMAR = DMA_CMAR[i]; + } + /* ADC */ + ADC->CONF = ADC_CONF_saved; + ADC->IRQMASK = ADC_IRQMASK_saved; + ADC->OFFSET_MSB = ADC_OFFSET_MSB_saved; + ADC->OFFSET_LSB = ADC_OFFSET_LSB_saved; + ADC->THRESHOLD_HI = ADC_THRESHOLD_HI_saved; + ADC->THRESHOLD_LO = ADC_THRESHOLD_LO_saved; + ADC->CTRL = ADC_CTRL_saved; + + /* PKA */ + PKA->IEN = PKA_IEN_saved; + //The five IRQs are linked to a real ISR. If any of the five IRQs + //triggered, then pend their ISR + //Capture the wake source from the BLE_REASON_RESET register + if ((CKGEN_SOC->REASON_RST == 0) && + (CKGEN_BLE->REASON_RST >= WAKENED_FROM_IO9) && + (CKGEN_BLE->REASON_RST <= WAKENED_FROM_IO13) && + gpioWakeBitMask) { + if ((((CKGEN_BLE->REASON_RST & WAKENED_FROM_IO9) == WAKENED_FROM_IO9) && (GPIO->IE & GPIO_Pin_9)) || + (((CKGEN_BLE->REASON_RST & WAKENED_FROM_IO10) == WAKENED_FROM_IO10) && (GPIO->IE & GPIO_Pin_10)) || + (((CKGEN_BLE->REASON_RST & WAKENED_FROM_IO11) == WAKENED_FROM_IO11) && (GPIO->IE & GPIO_Pin_11)) || + (((CKGEN_BLE->REASON_RST & WAKENED_FROM_IO12) == WAKENED_FROM_IO12) && (GPIO->IE & GPIO_Pin_12)) || + (((CKGEN_BLE->REASON_RST & WAKENED_FROM_IO13) == WAKENED_FROM_IO13) && (GPIO->IE & GPIO_Pin_13))) { + NVIC->ISPR[0] = 1<TIMEOUT &= ~(LOW_POWER_STANDBY<<28); + } + + /* Restore the System Control register to indicate which HS crystal is used */ + SYSTEM_CTRL->CTRL = SYS_Ctrl_saved; + + // Wait until the HS clock is ready. + // If SLEEPMODE_NOTIMER is set, wait the LS clock is ready. + if (sleepMode == SLEEPMODE_NOTIMER) { + DeviceConfiguration(FALSE, TRUE); + } else { + DeviceConfiguration(FALSE, FALSE); + } + + /* If the HS is a 32 MHz */ + if (SYS_Ctrl_saved & 1) { +#if (FORCE_CORE_TO_16MHZ == 1) + /* AHB up converter command register write*/ + AHBUPCONV->COMMAND = 0x14; +#else + /* AHB up converter command register write*/ + AHBUPCONV->COMMAND = 0x15; +#endif + } + } + + //We can clear PRIMASK to reenable global interrupt operation. + //__enable_irq(); //done in hal_deepsleep +} + +void hal_sleep(void){ + //only CPU halt, wakeup from any interrupt source + //wakeup timer is not available + + // Disable IRQs + core_util_critical_section_enter(); + + //Flag to signal if a wakeup from standby or sleep occurred + wakeupFromSleepFlag = 0; + + //ask the BLE controller if link layer termination is ongoing, + //to go sleep at least it shall return at least SLEEPMODE_CPU_HALT + SleepModes sleepMode_allowed = (SleepModes)BlueNRG_Stack_Perform_Deep_Sleep_Check(); + + if(sleepMode_allowed >= SLEEPMODE_CPU_HALT){ + BlueNRG_HaltCPU(); + } + // Unmask all the interrupt + core_util_critical_section_exit(); +} + +void hal_deepsleep(void){ + //check no active UART RX - when tx ongoing fifo empty flag is 0 (RESET) +#if DEVICE_SERIAL && DEVICE_SERIAL_ASYNCH + if(serialTxActive()) return; +#endif + + // Disable IRQs + core_util_critical_section_enter(); + + + //Flag to signal if a wakeup from standby or sleep occurred + wakeupFromSleepFlag = 0; + + //ask the BLE controller if link layer termination is ongoing, + //to go sleep at least it shall return at least SLEEPMODE_WAKETIMER - only GPIO wakeup available + volatile SleepModes sleepMode_allowed = (SleepModes)BlueNRG_Stack_Perform_Deep_Sleep_Check(); + + switch(sleepMode_allowed){ + case SLEEPMODE_CPU_HALT: + BlueNRG_HaltCPU(); + break; + case SLEEPMODE_WAKETIMER: + case SLEEPMODE_NOTIMER: + //Setup the GPIO Wakeup Source + //sleepMode_allowed = SLEEPMODE_WAKETIMER; + SYSTEM_CTRL->WKP_IO_IS = GPIO_WAKE_LEVEL_MASK; + SYSTEM_CTRL->WKP_IO_IE = GPIO_WAKE_BIT_MASK; + BlueNRG_DeepSleep(sleepMode_allowed,GPIO_WAKE_BIT_MASK); + break; + default: + break; + } + // Unmask all the interrupt + core_util_critical_section_exit(); +} + +#endif //DEVICE_SLEEP diff --git a/targets/TARGET_STMBLUE/spi_api.c b/targets/TARGET_STMBLUE/spi_api.c new file mode 100644 index 00000000000..5b0818ba04a --- /dev/null +++ b/targets/TARGET_STMBLUE/spi_api.c @@ -0,0 +1,285 @@ + +#include "mbed_assert.h" +#include "mbed_error.h" +#include "spi_api.h" + + + +#if DEVICE_SPI +#include "cmsis.h" +#include "pinmap.h" +#include "objects.h" +//#include "pin_device.h" + +#include "BlueNRG1_sysCtrl.h" +#include "hal_types.h" + +//assertations + +/* Consider 10ms as the default timeout for sending/receving 1 byte */ +#define TIMEOUT_1_BYTE 10 + +#define SPI_SPEED 1000000 + +#define SPI_DUMMY_CHAR 0xFF + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel){ + + GPIO_InitType GPIO_InitStructure; + + /* Enable SPI and GPIO clocks */ + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_GPIO | CLOCK_PERIPH_SPI, ENABLE); + + /* Configure SPI pins */ + GPIO_StructInit(&GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = mosi; //SDK_EVAL_SPI_PERIPH_OUT_PIN = GPIO_Pin_2 = mosi; + GPIO_InitStructure.GPIO_Mode = Serial0_Mode;//SDK_EVAL_SPI_PERIPH_OUT_MODE; + GPIO_InitStructure.GPIO_Pull = ENABLE; + GPIO_InitStructure.GPIO_HighPwr = DISABLE; + GPIO_Init(&GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = miso; //SDK_EVAL_SPI_PERIPH_IN_PIN = GPIO_Pin_3 = miso; + GPIO_InitStructure.GPIO_Mode = Serial0_Mode;//SDK_EVAL_SPI_PERIPH_IN_MODE; + GPIO_Init(&GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = sclk; //SDK_EVAL_SPI_PERIPH_SCLK_PIN = GPIO_Pin_0 = ck; + GPIO_InitStructure.GPIO_Mode = Serial0_Mode;//SDK_EVAL_SPI_PERIPH_SCLK_MODE; + GPIO_Init(&GPIO_InitStructure); + if(ssel != NC){ + GPIO_InitStructure.GPIO_Pin = ssel; //SPI_CS_MS_DEMO_PIN; + GPIO_InitStructure.GPIO_Mode = GPIO_Output; + GPIO_InitStructure.GPIO_HighPwr = ENABLE; + GPIO_Init(&GPIO_InitStructure); + GPIO_WriteBit(ssel, 1); + } + obj->pin_miso = miso; + obj->pin_mosi = mosi; + obj->pin_sclk = sclk; + obj->pin_ssel = ssel; + + obj->init.SPI_Mode = SPI_Mode_Master; + obj->init.SPI_DataSize = SPI_DataSize_8b ; + obj->init.SPI_CPOL = SPI_CPOL_Low; + obj->init.SPI_CPHA = SPI_CPHA_1Edge; + obj->init.SPI_BaudRate = SPI_SPEED; + SPI_Init(&(obj->init)); + + // Clear RX and TX FIFO // + SPI_ClearTXFIFO(); + SPI_ClearRXFIFO(); + + // Set null character // + obj->dummy_char = SPI_DUMMY_CHAR; + SPI_SetDummyCharacter(obj->dummy_char); + + // Set communication mode // + SPI_SetMasterCommunicationMode(SPI_FULL_DUPLEX_MODE); + + // Enable SPI functionality // + SPI_Cmd(ENABLE); +} + +void spi_free(spi_t *obj){ + obj->dummy_char = 0; + obj->pin_miso = NC; + obj->pin_mosi = NC; + obj->pin_sclk = NC; + obj->pin_ssel = NC; + obj->init.SPI_BaudRate = 0; + obj->init.SPI_CPHA = 0; + obj->init.SPI_CPOL = 0; + obj->init.SPI_DataSize = 0; + obj->init.SPI_Mode = 0; + SPI_DeInit(); +} + +void spi_format(spi_t *obj, int bits, int mode, int slave){ + + /* Configure SPI in master mode */ + obj->init.SPI_Mode = (slave) ? SPI_Mode_Slave : SPI_Mode_Master; + obj->init.SPI_DataSize = (uint8_t) bits-1; + + switch (mode) { + case 0: + obj->init.SPI_CPOL = SPI_CPOL_Low; + obj->init.SPI_CPHA = SPI_CPHA_1Edge; + break; + case 1: + obj->init.SPI_CPOL = SPI_CPOL_Low; + obj->init.SPI_CPHA = SPI_CPHA_2Edge; + break; + case 2: + obj->init.SPI_CPOL = SPI_CPOL_High; + obj->init.SPI_CPHA = SPI_CPHA_1Edge; + break; + case 3: + obj->init.SPI_CPOL = SPI_CPOL_High; + obj->init.SPI_CPHA = SPI_CPHA_2Edge; + break; + default : + break; + + } + obj->init.SPI_CPOL ? GPIO_SetBits(obj->pin_sclk) : GPIO_ResetBits(obj->pin_sclk); + SPI_Init(&(obj->init)); + +} + + + +void spi_frequency(spi_t *obj, int hz) { + obj->init.SPI_BaudRate = hz; + SPI_Init(&(obj->init)); +} + +int spi_master_write(spi_t *obj, int value){ + + int received_data; + + // Set communication mode // + SPI_SetMasterCommunicationMode(SPI_FULL_DUPLEX_MODE); + + // start write: CS=0 + //GPIO_WriteBit(obj->pin_ssel, 0); + + // Write data to send to TX FIFO // + while(RESET == SPI_GetFlagStatus(SPI_FLAG_TFE)); + + SPI_SendData(value); + + // read RX FIFO data // + while(RESET == SPI_GetFlagStatus(SPI_FLAG_RNE)); + received_data = SPI_ReceiveData(); + + // wait busy + while (SET == SPI_GetFlagStatus(SPI_FLAG_BSY)); + + // stop write: CS=1 + //GPIO_WriteBit(obj->pin_ssel, 1); + return received_data; +} + + + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill){ + + obj->dummy_char = write_fill; + SPI_SetDummyCharacter(write_fill); + + // Set communication mode // + //SPI_SetMasterCommunicationMode(SPI_FULL_DUPLEX_MODE); + + // start write: CS=0 + //GPIO_WriteBit(obj->pin_ssel, 0); + // TX BUFFER // + + for (int i=0; ipin_ssel, 1); + + return tx_length > rx_length ? tx_length : rx_length; +} + +int spi_slave_receive(spi_t *obj){ + return SPI_GetFlagStatus(SPI_FLAG_RNE); // != 0) ? 1: 0; +} + +int spi_slave_read(spi_t *obj){ + while(RESET == SPI_GetFlagStatus(SPI_FLAG_RNE)); + return SPI_ReceiveData(); +} + +void spi_slave_write(spi_t *obj, int value){ + while(RESET == SPI_GetFlagStatus(SPI_FLAG_TFE)); + SPI_SendData(value); +} + +int spi_busy(spi_t *obj){ + return SPI_GetFlagStatus(SPI_FLAG_BSY); +} + +#ifdef ANTONIO_armclang +uint8_t spi_get_module(spi_t *obj){ + return 1; +} + +const PinMap *spi_master_mosi_pinmap(void){ + return 0; +} + +const PinMap *spi_master_miso_pinmap(void){ + return 0; +} + +const PinMap *spi_master_clk_pinmap(void){ + return 0; +} + +const PinMap *spi_master_cs_pinmap(void){ + return 0; +} + +const PinMap *spi_slave_mosi_pinmap(void){ + return 0; +} + +const PinMap *spi_slave_miso_pinmap(void){ + return 0; +} + +const PinMap *spi_slave_clk_pinmap(void){ + return 0; +} + +const PinMap *spi_slave_cs_pinmap(void){ + return 0; +} +#endif //antonio_armclang + + +#ifdef DEVICE_SPI_ASYNCH + +/// @returns the number of bytes transferred, or `0` if nothing transferred +static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length){ + +} + +// asynchronous API +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint){} + +inline uint32_t spi_irq_handler_asynch(spi_t *obj){} + +uint8_t spi_active(spi_t *obj){} + +void spi_abort_asynch(spi_t *obj){} + +#endif //DEVICE_SPI_ASYNCH + +#endif //DEVICE_SPI diff --git a/targets/TARGET_STMBLUE/us_ticker_api.c b/targets/TARGET_STMBLUE/us_ticker_api.c new file mode 100644 index 00000000000..75563a60c50 --- /dev/null +++ b/targets/TARGET_STMBLUE/us_ticker_api.c @@ -0,0 +1,148 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2019, STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * + * You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + * + * either express or implied. + * + * See the License for the specific language governing permissions and limitations under the License. + */ + +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "hal_types.h" +#include "BlueNRG1_mft.h" +#include "BlueNRG1_sysCtrl.h" +#include "misc.h" + +#define FREQ_TICK 1000000 +#define NUMBITS 16 + +enum InitStatus{ + noinit = 0, + init = 1, +}status; + +const ticker_info_t *us_ticker_get_info() +{ + static const ticker_info_t info = { + FREQ_TICK, + NUMBITS + }; + return &info; +} + +void us_ticker_isr(void){ + //clear interrupt flag and call the us ticker handler + MFT_ClearIT(MFT2, MFT_IT_TND); + us_ticker_irq_handler(); +} + +void us_ticker_init(void){ + if(status == init) return; + + status = init; + + MFT_InitType timer_init; + NVIC_InitType NVIC_InitStructure; + //tick_count = 0; + + NVIC_SetVector(MFT2B_IRQn, (uint32_t)&us_ticker_isr); + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_MTFX2, ENABLE); //timer 2 is used as timebase, maybe mtfx1 is useless in this context + MFT_StructInit(&timer_init); + + timer_init.MFT_Mode = MFT_MODE_3; + timer_init.MFT_Prescaler = SYST_CLOCK/FREQ_TICK - 1; + timer_init.MFT_Clock1 = MFT_NO_CLK; + timer_init.MFT_Clock2 = MFT_PRESCALED_CLK; + timer_init.MFT_CRA = 0x0000; + timer_init.MFT_CRB = 0xFFFF; + + MFT_Init(MFT2, &timer_init); + + //Set counter for timer2 + MFT_SetCounter2(MFT2, 0xFFFF); + + //Enable MFT2B Interrupt + NVIC_InitStructure.NVIC_IRQChannel = MFT2B_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = HIGH_PRIORITY; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + //Enable the MFT2 interrupt + MFT_EnableIT(MFT2, MFT_IT_TND, ENABLE); + + //Start MTF2B + MFT_Cmd(MFT2, ENABLE); +} + +void us_ticker_free(){ + if(status == init){ + MFT_Cmd(MFT2, DISABLE); //Disable MTF2B + MFT_DeInit(MFT2); //Deinit peripheral + NVIC_DisableIRQ(MFT2B_IRQn); //Disable IRQ + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_MTFX2, DISABLE); //Disable Clock Gate peripheral + status = noinit; + } +} + +uint32_t us_ticker_read(){ + if(!status) + us_ticker_init(); + + return ~MFT_GetCounter2(MFT2); //bitwise complement, MFT2 is a backward counter +} + +/* We get here absolute interrupt time which takes into account counter overflow. + * Since we use additional count-DOWN timer to generate interrupt we need to calculate + * load value based on timestamp. + * If the timestamp value is higher than the actual count, then the interrupt will be + * triggered after "timestamp - actual_ticks". + * If the timestamp value is lower than the actual count, then the interrupt is triggered + * at the next count cycle after the overflow, i.e. + * "timestamp + 1 x overflow_count (0xFFFF) - actual_count". + */ +void us_ticker_set_interrupt(timestamp_t timestamp){ + if(!status) + us_ticker_init(); + +// const uint16_t actual_ticks = (uint16_t)us_ticker_read(); +// uint16_t delta_ticks = +// (uint16_t)timestamp >= actual_ticks ? (uint16_t)timestamp - actual_ticks : (uint16_t)((uint32_t)timestamp + 0xFFFF - actual_ticks); + + uint16_t delta_ticks = (uint16_t)(timestamp - us_ticker_read()); //back counter + if (delta_ticks == 0) { + // The requested delay is less than the minimum resolution of this counter. + delta_ticks = 1; + } + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_MTFX2, DISABLE); //Clock Gate peripheral, safe since IRQ is disabled by high level API + MFT2->TNCRB = delta_ticks; + MFT_EnableIT(MFT2, MFT_IT_TND, ENABLE); + SysCtrl_PeripheralClockCmd(CLOCK_PERIPH_MTFX2, ENABLE); //Disable Clock Gate peripheral +} + +/* NOTE: must be called with interrupts disabled! */ +void us_ticker_disable_interrupt(void){ + if(!status) + us_ticker_init(); + MFT_EnableIT(MFT2, MFT_IT_TND, DISABLE); + +} + +/* NOTE: must be called with interrupts disabled! */ +void us_ticker_clear_interrupt(void){ + MFT_ClearIT(MFT2, MFT_IT_TND); +} + +/* NOTE: must be called with interrupts disabled! */ +void us_ticker_fire_interrupt(void){ + NVIC_SetPendingIRQ(MFT2B_IRQn); +} diff --git a/targets/targets.json b/targets/targets.json index 83340a7c461..924f7822a24 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8266,6 +8266,34 @@ "detect_code": ["1703"], "macros_add": ["GD32E10X"], "release_versions": ["5"] + }, + "BLUENRG2": { + "inherits": ["Target"], + "core": "Cortex-M0", + "supported_toolchains": ["GCC_ARM", "ARM", "IAR"], + "release_versions": ["5"], + "default_lib": ["std"], + "public": false, + "extra_labels": ["STMBLUE","CORDIO","BlueNRG-2"], + "device_has": ["SERIAL","SERIAL_ASYNCH","SERIAL_FC","INTERRUPTIN","SLEEP","STDIO_MESSAGES","USTICKER","SPI","SPISLAVE"], + "macros": ["BLUENRG2_DEVICE","LS_SOURCE=LS_SOURCE_EXTERNAL_32KHZ","SMPS_INDUCTOR=SMPS_INDUCTOR_10uH","BLE_STACK_CONFIGURATION=BLE_STACK_BASIC_CONFIGURATION","CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""], + "features": ["BLE"], + "device_name": "BlueNRG-2" + }, + "STEVAL_IDB008V2": { + "inherits": ["BLUENRG2"], + "config": { + "clock_source": { + "help": "Crystal oscillator frequency", + "value": "HS_SPEED_XTAL_32MHZ", + "macro_name": "HS_SPEED_XTAL" + }, + "tick_linklayer_fsm_ms": { + "help": "Link Layer FSM tick signal", + "value": "10", + "macro_name": "TICK_MS" + } + } }, "TT_M4G9": { "inherits": ["Target"], @@ -8301,4 +8329,4 @@ "version": "1", "public": false } -} +} \ No newline at end of file diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index cb288feadd8..d22a0e27d91 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -342,5 +342,8 @@ "M2351KIAAEES": { "OGChipSelectEditMenu": "M2351 series\tNuvoton M2351 series", "TrustZone": 1 - } + }, + "BlueNRG-2": { + "OGChipSelectEditMenu": "BLUENRG-2\tST BLUENRG-2" + } }