@@ -228,7 +228,7 @@ pub fn generateSymbol(
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.fail = try ErrorMsg .create (
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bin_file .allocator ,
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src ,
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- "TODO implement generateSymbol for type '{}'" ,
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+ "TODO implement generateSymbol for type '{s }'" ,
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.{@tagName (t )},
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),
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};
@@ -2029,7 +2029,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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});
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break :blk 0x84 ;
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},
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- else = > return self .fail (inst .base .src , "TODO implement condbr {} when condition is {}" , .{ self .target .cpu .arch , @tagName (cond ) }),
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+ else = > return self .fail (inst .base .src , "TODO implement condbr {s } when condition is {s }" , .{ self .target .cpu .arch , @tagName (cond ) }),
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};
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self .code .appendSliceAssumeCapacity (&[_ ]u8 { 0x0f , opcode });
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const reloc = Reloc { .rel32 = self .code .items .len };
@@ -2376,11 +2376,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.arm , .armeb = > {
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for (inst .inputs ) | input , i | {
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if (input .len < 3 or input [0 ] != '{' or input [input .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm input constraint: '{}'" , .{input });
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+ return self .fail (inst .base .src , "unrecognized asm input constraint: '{s }'" , .{input });
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}
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const reg_name = input [1 .. input .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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const arg = try self .resolveInst (inst .args [i ]);
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try self .genSetReg (inst .base .src , reg , arg );
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}
@@ -2393,11 +2393,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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if (inst .output ) | output | {
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if (output .len < 4 or output [0 ] != '=' or output [1 ] != '{' or output [output .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm output constraint: '{}'" , .{output });
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+ return self .fail (inst .base .src , "unrecognized asm output constraint: '{s }'" , .{output });
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}
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const reg_name = output [2 .. output .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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return MCValue { .register = reg };
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} else {
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return MCValue .none ;
@@ -2406,11 +2406,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.aarch64 = > {
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for (inst .inputs ) | input , i | {
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if (input .len < 3 or input [0 ] != '{' or input [input .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm input constraint: '{}'" , .{input });
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+ return self .fail (inst .base .src , "unrecognized asm input constraint: '{s }'" , .{input });
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}
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const reg_name = input [1 .. input .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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const arg = try self .resolveInst (inst .args [i ]);
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try self .genSetReg (inst .base .src , reg , arg );
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}
@@ -2425,11 +2425,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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if (inst .output ) | output | {
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if (output .len < 4 or output [0 ] != '=' or output [1 ] != '{' or output [output .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm output constraint: '{}'" , .{output });
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+ return self .fail (inst .base .src , "unrecognized asm output constraint: '{s }'" , .{output });
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}
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const reg_name = output [2 .. output .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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return MCValue { .register = reg };
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} else {
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return MCValue .none ;
@@ -2438,11 +2438,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.riscv64 = > {
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for (inst .inputs ) | input , i | {
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if (input .len < 3 or input [0 ] != '{' or input [input .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm input constraint: '{}'" , .{input });
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+ return self .fail (inst .base .src , "unrecognized asm input constraint: '{s }'" , .{input });
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}
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const reg_name = input [1 .. input .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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const arg = try self .resolveInst (inst .args [i ]);
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try self .genSetReg (inst .base .src , reg , arg );
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}
@@ -2455,11 +2455,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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if (inst .output ) | output | {
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if (output .len < 4 or output [0 ] != '=' or output [1 ] != '{' or output [output .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm output constraint: '{}'" , .{output });
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+ return self .fail (inst .base .src , "unrecognized asm output constraint: '{s }'" , .{output });
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}
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const reg_name = output [2 .. output .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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return MCValue { .register = reg };
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} else {
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return MCValue .none ;
@@ -2468,11 +2468,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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.x86_64 , .i386 = > {
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for (inst .inputs ) | input , i | {
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if (input .len < 3 or input [0 ] != '{' or input [input .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm input constraint: '{}'" , .{input });
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+ return self .fail (inst .base .src , "unrecognized asm input constraint: '{s }'" , .{input });
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}
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const reg_name = input [1 .. input .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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const arg = try self .resolveInst (inst .args [i ]);
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try self .genSetReg (inst .base .src , reg , arg );
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}
@@ -2485,11 +2485,11 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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if (inst .output ) | output | {
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if (output .len < 4 or output [0 ] != '=' or output [1 ] != '{' or output [output .len - 1 ] != '}' ) {
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- return self .fail (inst .base .src , "unrecognized asm output constraint: '{}'" , .{output });
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+ return self .fail (inst .base .src , "unrecognized asm output constraint: '{s }'" , .{output });
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}
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const reg_name = output [2 .. output .len - 1 ];
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const reg = parseRegName (reg_name ) orelse
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- return self .fail (inst .base .src , "unrecognized register: '{}'" , .{reg_name });
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+ return self .fail (inst .base .src , "unrecognized register: '{s }'" , .{reg_name });
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return MCValue { .register = reg };
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} else {
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return MCValue .none ;
@@ -3417,7 +3417,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
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next_int_reg += 1 ;
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}
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},
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- else = > return self .fail (src , "TODO implement function parameters of type {}" , .{@tagName (ty .zigTypeTag ())}),
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+ else = > return self .fail (src , "TODO implement function parameters of type {s }" , .{@tagName (ty .zigTypeTag ())}),
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}
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}
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result .stack_byte_count = next_stack_offset ;
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