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jacobly0adriweb
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Fix #1.
1 parent f13c037 commit 10a0c08

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6 files changed

+26
-22
lines changed

6 files changed

+26
-22
lines changed

llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ const TargetRegisterClass *
176176
Z80InstructionSelector::getRegClass(Register Reg,
177177
MachineRegisterInfo &MRI) const {
178178
if (Reg.isPhysical()) {
179-
for (auto *RC : {&Z80::R8RegClass, &Z80::F8RegClass, &Z80::R16RegClass,
179+
for (auto *RC : {&Z80::R8RegClass, &Z80::Z8RegClass, &Z80::R16RegClass,
180180
&Z80::Z16RegClass, &Z80::R24RegClass, &Z80::Z24RegClass})
181181
if (RC->contains(Reg))
182182
return RC;
@@ -226,8 +226,9 @@ bool Z80InstructionSelector::selectCopy(MachineInstr &I,
226226
if (DstReg.isPhysical()) {
227227
assert(I.isCopy() && "Generic operators do not allow physical registers");
228228

229-
if (DstReg == Z80::F &&
230-
!RBI.constrainGenericRegister(SrcReg, Z80::F8RegClass, MRI))
229+
if ((DstReg == Z80::F || DstReg == Z80::I || DstReg == Z80::R ||
230+
DstReg == Z80::MB) &&
231+
!RBI.constrainGenericRegister(SrcReg, Z80::Z8RegClass, MRI))
231232
return false;
232233

233234
if (DstSize > SrcSize && SrcRegBank.getID() == Z80::GPRRegBankID &&
@@ -1226,8 +1227,8 @@ Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
12261227
CallLowering::ArgInfo::NoArgIndex);
12271228
createLibcall(MIB, RTLIB::SCMP, SignedFlagsArg, FlagsArg);
12281229
MIB.buildCopy(Register(Z80::F), SignedFlagsReg);
1229-
if (!RBI.constrainGenericRegister(FlagsReg, Z80::F8RegClass, MRI) ||
1230-
!RBI.constrainGenericRegister(SignedFlagsReg, Z80::F8RegClass, MRI))
1230+
if (!RBI.constrainGenericRegister(FlagsReg, Z80::Z8RegClass, MRI) ||
1231+
!RBI.constrainGenericRegister(SignedFlagsReg, Z80::Z8RegClass, MRI))
12311232
return Z80::COND_INVALID;
12321233
}
12331234
return CC;

llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ Z80RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
4646
if (Z80::R8RegClass.hasSubClassEq(&RC) ||
4747
Z80::R16RegClass.hasSubClassEq(&RC) ||
4848
Z80::R24RegClass.hasSubClassEq(&RC) ||
49-
Z80::F8RegClass.hasSubClassEq(&RC) ||
49+
Z80::Z8RegClass.hasSubClassEq(&RC) ||
5050
Z80::Z16RegClass.hasSubClassEq(&RC) ||
5151
Z80::Z24RegClass.hasSubClassEq(&RC))
5252
return getRegBank(Z80::GPRRegBankID);

llvm/lib/Target/Z80/Z80ISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -632,15 +632,15 @@ Z80TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
632632
}
633633

634634
if (Z80::parseConstraintCode(Constraint) != Z80::COND_INVALID)
635-
return std::make_pair(Z80::F, &Z80::F8RegClass);
635+
return std::make_pair(Z80::F, &Z80::Z8RegClass);
636636

637637
// Use the default implementation in TargetLowering to convert the register
638638
// constraint into a member of a register class.
639639
auto Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
640640

641641
if (!Res.second) {
642642
if (Constraint.equals_insensitive("{f}"))
643-
return std::make_pair(Z80::F, &Z80::F8RegClass);
643+
return std::make_pair(Z80::F, &Z80::Z8RegClass);
644644

645645
return Res;
646646
}

llvm/lib/Target/Z80/Z80MachineEarlyOptimization.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ bool Z80MachineEarlyOptimization::runOnMachineFunction(MachineFunction &MF) {
154154
}
155155
}
156156
if (CallMI && Cost < CondCallThreshold) {
157-
Register TempReg = MRI.createVirtualRegister(&Z80::F8RegClass);
157+
Register TempReg = MRI.createVirtualRegister(&Z80::Z8RegClass);
158158
DebugLoc DL = MBB.findBranchDebugLoc();
159159
MBB.removeSuccessor(FalseMBB);
160160
TII.removeBranch(MBB);

llvm/lib/Target/Z80/Z80RegisterBanks.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,4 +10,4 @@
1010
//===----------------------------------------------------------------------===//
1111

1212
/// General Purpose Registers
13-
def GPRRegBank : RegisterBank<"GPR", [R24, Z24, Z16, F8]>;
13+
def GPRRegBank : RegisterBank<"GPR", [R24, Z24, Z16, Z8]>;

llvm/lib/Target/Z80/Z80RegisterInfo.td

Lines changed: 15 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ let Namespace = "Z80" in {
5353
//===----------------------------------------------------------------------===//
5454
// Register definitions...
5555
//
56-
let Namespace = "Z80" in {
56+
5757
// 8-bit registers
5858
def A : Z80Reg<"a", 7>;
5959
def F : Z80Reg<"f">;
@@ -64,11 +64,6 @@ def E : Z80Reg<"e", 3>;
6464
def H : Z80Reg<"h", 4>;
6565
def L : Z80Reg<"l", 5>;
6666

67-
// special registers
68-
def I : Z80Reg<"i", 8>;
69-
def R : Z80Reg<"r", 9>;
70-
def MB : Z80Reg<"mb", 10>;
71-
7267
// 8-bit index registers
7368
let CostPerUse = [1] in {
7469
def IXH : Z80Reg<"ixh", 4>;
@@ -101,10 +96,18 @@ let CostPerUse = [1] in {
10196
def UIX : EZ80ExtReg<IX>;
10297
def UIY : EZ80ExtReg<IY>;
10398
}
104-
}
105-
def SPL : Z80Reg<"sp", 3>;
106-
def PC : Z80Reg<"pc">;
107-
}
99+
100+
// 24-bit misc registers
101+
def SPL : Z80Reg<"sp", 3>, DwarfRegNum<[7]>;
102+
103+
// misc registers
104+
def PC : Z80Reg<"pc">, DwarfRegNum<[8]>;
105+
def I : Z80Reg<"i">;
106+
let SubRegs = [I], SubRegIndices = [sub_low] in
107+
def UI : Z80Reg<"i">;
108+
def R : Z80Reg<"r">;
109+
def MB : Z80Reg<"mb">;
110+
108111
//===----------------------------------------------------------------------===//
109112
// Register Class Definitions...
110113
//
@@ -120,7 +123,7 @@ def X8 : Z80RC8 <(add O8, IXL, IXH)>;
120123
def I8 : Z80RC8 <(add IYL, IYH, IXL, IXH)>;
121124
def R8 : Z80RC8 <(add G8, I8)>;
122125
let CopyCost = -1 in
123-
def F8 : Z80RC8 <(add F)>;
126+
def Z8 : Z80RC8 <(add F, I, R, MB)>;
124127

125128
def O16 : Z80RC16<(add DE, BC)>;
126129
def G16 : Z80RC16<(add HL, O16)>;
@@ -130,7 +133,7 @@ def I16 : Z80RC16<(add IY, IX)>;
130133
def A16 : Z80RC16<(add HL, I16)>;
131134
def R16 : Z80RC16<(add G16, I16)>;
132135
let CopyCost = -1 in
133-
def Z16 : Z80RC16<(add SPS, AF)>;
136+
def Z16 : Z80RC16<(add SPS, AF, UI)>;
134137

135138
def O24 : Z80RC24<(add UDE, UBC)>;
136139
def G24 : Z80RC24<(add UHL, O24)>;

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