@@ -53,7 +53,7 @@ let Namespace = "Z80" in {
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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- let Namespace = "Z80" in {
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+
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// 8-bit registers
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def A : Z80Reg<"a", 7>;
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def F : Z80Reg<"f">;
@@ -64,11 +64,6 @@ def E : Z80Reg<"e", 3>;
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def H : Z80Reg<"h", 4>;
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def L : Z80Reg<"l", 5>;
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- // special registers
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- def I : Z80Reg<"i", 8>;
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- def R : Z80Reg<"r", 9>;
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- def MB : Z80Reg<"mb", 10>;
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-
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// 8-bit index registers
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let CostPerUse = [1] in {
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def IXH : Z80Reg<"ixh", 4>;
@@ -101,10 +96,18 @@ let CostPerUse = [1] in {
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def UIX : EZ80ExtReg<IX>;
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def UIY : EZ80ExtReg<IY>;
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}
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- }
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- def SPL : Z80Reg<"sp", 3>;
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- def PC : Z80Reg<"pc">;
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- }
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+
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+ // 24-bit misc registers
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+ def SPL : Z80Reg<"sp", 3>, DwarfRegNum<[7]>;
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+
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+ // misc registers
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+ def PC : Z80Reg<"pc">, DwarfRegNum<[8]>;
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+ def I : Z80Reg<"i">;
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+ let SubRegs = [I], SubRegIndices = [sub_low] in
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+ def UI : Z80Reg<"i">;
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+ def R : Z80Reg<"r">;
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+ def MB : Z80Reg<"mb">;
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+
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//===----------------------------------------------------------------------===//
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// Register Class Definitions...
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//
@@ -120,7 +123,7 @@ def X8 : Z80RC8 <(add O8, IXL, IXH)>;
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def I8 : Z80RC8 <(add IYL, IYH, IXL, IXH)>;
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def R8 : Z80RC8 <(add G8, I8)>;
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let CopyCost = -1 in
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- def F8 : Z80RC8 <(add F)>;
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+ def Z8 : Z80RC8 <(add F, I, R, MB )>;
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def O16 : Z80RC16<(add DE, BC)>;
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def G16 : Z80RC16<(add HL, O16)>;
@@ -130,7 +133,7 @@ def I16 : Z80RC16<(add IY, IX)>;
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def A16 : Z80RC16<(add HL, I16)>;
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def R16 : Z80RC16<(add G16, I16)>;
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let CopyCost = -1 in
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- def Z16 : Z80RC16<(add SPS, AF)>;
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+ def Z16 : Z80RC16<(add SPS, AF, UI )>;
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def O24 : Z80RC24<(add UDE, UBC)>;
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def G24 : Z80RC24<(add UHL, O24)>;
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