Revert "[AMDGPU] Serialize WWM_REG vreg flag (llvm#110229)"

This reverts commit bec839d.

Caused buildbot failures, e.g.
https://lab.llvm.org/buildbot/#/builders/52/builds/2928

Author: pcc

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -1718,17 +1718,6 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
     MFI->reserveWWMRegister(ParsedReg);
   }
 
-  for (const auto &[_, Info] : PFS.VRegInfosNamed) {
-    for (uint8_t Flag : Info->Flags) {
-      MFI->setFlag(Info->VReg, Flag);
-    }
-  }
-  for (const auto &[_, Info] : PFS.VRegInfos) {
-    for (uint8_t Flag : Info->Flags) {
-      MFI->setFlag(Info->VReg, Flag);
-    }
-  }
-
   auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
                                    const TargetRegisterClass &RC,
                                    ArgDescriptor &Arg, unsigned UserSGPRs,

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -3851,13 +3851,3 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
   }
   return 0;
 }
-
-SmallVector<StringLiteral>
-SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
-                                  const MachineFunction &MF) const {
-  SmallVector<StringLiteral> RegFlags;
-  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
-  if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG))
-    RegFlags.push_back("WWM_REG");
-  return RegFlags;
-}

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

@@ -457,14 +457,6 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
   // No check if the subreg is supported by the current RC is made.
   unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
                                      unsigned SubReg) const;
-
-  std::optional<uint8_t> getVRegFlagValue(StringRef Name) const override {
-    return Name == "WWM_REG" ? AMDGPU::VirtRegFlag::WWM_REG
-                             : std::optional<uint8_t>{};
-  }
-
-  SmallVector<StringLiteral>
-  getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
 };
 
 namespace AMDGPU {

llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir

@@ -578,18 +578,3 @@ body:             |
     SI_RETURN
 
 ...
----
-name: vregs
-# FULL: registers:
-# FULL-NEXT:   - { id: 0, class: vgpr_32, preferred-register: '$vgpr1', flags: [ WWM_REG ] }
-# FULL-NEXT:   - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1', flags: [  ] }
-# FULL-NEXT:   - { id: 2, class: sgpr_64, preferred-register: '', flags: [  ] }
-registers:
-  - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
-  - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
-  - { id: 2, class: sgpr_64, flags: [ ] }
-body: |
-  bb.0:
-    %2:sgpr_64 = COPY %1
-    %1:sgpr_64 = COPY %0
-...