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Revert "[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction (llvm#75582)"
This reverts commit 037c220.
1 parent f1bdd62 commit a11eef4

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5 files changed

+32
-85
lines changed

5 files changed

+32
-85
lines changed

‎llvm/lib/Target/X86/X86InstrAsmAlias.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -894,11 +894,3 @@ def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
894894
def : InstAlias<"invlpga\t{%eax, %ecx|eax, ecx}", (INVLPGA32), 0>, Requires<[Not64BitMode]>;
895895
def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
896896

897-
// Aliases with explicit %xmm0
898-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
899-
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
900-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
901-
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
902-
903-
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
904-
(SHA256RNDS2rm_EVEX VR128:$dst, i128mem:$src2), 0>;

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 29 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -6689,31 +6689,31 @@ let Predicates = [HasCRC32, HasEGPR, In64BitMode], OpMap = T_MAP4, OpEnc = EncEV
66896689

66906690
// FIXME: Is there a better scheduler class for SHA than WriteVecIMul?
66916691
multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
6692-
X86FoldableSchedWrite sched, string Suffix = "", bit UsesXMM0 = 0> {
6693-
def rr#Suffix : I<Opc, MRMSrcReg, (outs VR128:$dst),
6694-
(ins VR128:$src1, VR128:$src2),
6695-
!if(UsesXMM0,
6696-
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6697-
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6698-
[!if(UsesXMM0,
6699-
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
6700-
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
6701-
T8, Sched<[sched]>;
6702-
6703-
def rm#Suffix : I<Opc, MRMSrcMem, (outs VR128:$dst),
6704-
(ins VR128:$src1, i128mem:$src2),
6705-
!if(UsesXMM0,
6706-
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6707-
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6708-
[!if(UsesXMM0,
6709-
(set VR128:$dst, (IntId VR128:$src1,
6710-
(memop addr:$src2), XMM0)),
6711-
(set VR128:$dst, (IntId VR128:$src1,
6712-
(memop addr:$src2))))]>, T8,
6713-
Sched<[sched.Folded, sched.ReadAfterFold]>;
6692+
X86FoldableSchedWrite sched, bit UsesXMM0 = 0> {
6693+
def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
6694+
(ins VR128:$src1, VR128:$src2),
6695+
!if(UsesXMM0,
6696+
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6697+
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6698+
[!if(UsesXMM0,
6699+
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
6700+
(set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>,
6701+
T8, Sched<[sched]>;
6702+
6703+
def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
6704+
(ins VR128:$src1, i128mem:$src2),
6705+
!if(UsesXMM0,
6706+
!strconcat(OpcodeStr, "\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}"),
6707+
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")),
6708+
[!if(UsesXMM0,
6709+
(set VR128:$dst, (IntId VR128:$src1,
6710+
(memop addr:$src2), XMM0)),
6711+
(set VR128:$dst, (IntId VR128:$src1,
6712+
(memop addr:$src2))))]>, T8,
6713+
Sched<[sched.Folded, sched.ReadAfterFold]>;
67146714
}
67156715

6716-
let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
6716+
let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
67176717
def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
67186718
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
67196719
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -6740,55 +6740,19 @@ let Constraints = "$src1 = $dst", Predicates = [HasSHA, NoEGPR] in {
67406740

67416741
let Uses=[XMM0] in
67426742
defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2,
6743-
SchedWriteVecIMul.XMM, "", 1>;
6743+
SchedWriteVecIMul.XMM, 1>;
67446744

67456745
defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1,
67466746
SchedWriteVecIMul.XMM>;
67476747
defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2,
67486748
SchedWriteVecIMul.XMM>;
67496749
}
67506750

6751-
let Constraints = "$src1 = $dst", Predicates = [HasSHA, HasEGPR, In64BitMode] in {
6752-
def SHA1RNDS4rri_EVEX: Ii8<0xD4, MRMSrcReg, (outs VR128:$dst),
6753-
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
6754-
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6755-
[(set VR128:$dst,
6756-
(int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
6757-
(i8 timm:$src3)))]>,
6758-
EVEX, NoCD8, T_MAP4, Sched<[SchedWriteVecIMul.XMM]>;
6759-
def SHA1RNDS4rmi_EVEX: Ii8<0xD4, MRMSrcMem, (outs VR128:$dst),
6760-
(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
6761-
"sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6762-
[(set VR128:$dst,
6763-
(int_x86_sha1rnds4 VR128:$src1,
6764-
(memop addr:$src2),
6765-
(i8 timm:$src3)))]>,
6766-
EVEX, NoCD8, T_MAP4,
6767-
Sched<[SchedWriteVecIMul.XMM.Folded,
6768-
SchedWriteVecIMul.XMM.ReadAfterFold]>;
6769-
6770-
defm SHA1NEXTE : SHAI_binop<0xD8, "sha1nexte", int_x86_sha1nexte,
6771-
SchedWriteVecIMul.XMM, "_EVEX">,
6772-
EVEX, NoCD8, T_MAP4;
6773-
defm SHA1MSG1 : SHAI_binop<0xD9, "sha1msg1", int_x86_sha1msg1,
6774-
SchedWriteVecIMul.XMM, "_EVEX">,
6775-
EVEX, NoCD8, T_MAP4;
6776-
defm SHA1MSG2 : SHAI_binop<0xDA, "sha1msg2", int_x86_sha1msg2,
6777-
SchedWriteVecIMul.XMM, "_EVEX">,
6778-
EVEX, NoCD8, T_MAP4;
6779-
6780-
let Uses=[XMM0] in
6781-
defm SHA256RNDS2 : SHAI_binop<0xDB, "sha256rnds2", int_x86_sha256rnds2,
6782-
SchedWriteVecIMul.XMM, "_EVEX", 1>,
6783-
EVEX, NoCD8, T_MAP4;
6784-
6785-
defm SHA256MSG1 : SHAI_binop<0xDC, "sha256msg1", int_x86_sha256msg1,
6786-
SchedWriteVecIMul.XMM, "_EVEX">,
6787-
EVEX, NoCD8, T_MAP4;
6788-
defm SHA256MSG2 : SHAI_binop<0xDD, "sha256msg2", int_x86_sha256msg2,
6789-
SchedWriteVecIMul.XMM, "_EVEX">,
6790-
EVEX, NoCD8, T_MAP4;
6791-
}
6751+
// Aliases with explicit %xmm0
6752+
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
6753+
(SHA256RNDS2rr VR128:$dst, VR128:$src2), 0>;
6754+
def : InstAlias<"sha256rnds2\t{$src2, $dst|$dst, $src2}",
6755+
(SHA256RNDS2rm VR128:$dst, i128mem:$src2), 0>;
67926756

67936757
//===----------------------------------------------------------------------===//
67946758
// AES-NI Instructions

‎llvm/test/MC/X86/x86_64-asm-match.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher
1212
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range
1313
// CHECK: Opcode result: complete match, selecting this opcode
14-
// CHECK: AsmMatcher: found 4 encodings with mnemonic 'sha1rnds4'
14+
// CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
1515
// CHECK: Trying to match opcode SHA1RNDS4rri
1616
// CHECK: Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher
1717
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 2 (Reg:xmm1): match success using generic matcher

‎llvm/test/TableGen/x86-fold-tables.inc

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2247,19 +2247,12 @@ static const X86FoldTableEntry Table2[] = {
22472247
{X86::SBB8rr, X86::SBB8rm, 0},
22482248
{X86::SBB8rr_ND, X86::SBB8rm_ND, 0},
22492249
{X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16},
2250-
{X86::SHA1MSG1rr_EVEX, X86::SHA1MSG1rm_EVEX, TB_ALIGN_16},
22512250
{X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16},
2252-
{X86::SHA1MSG2rr_EVEX, X86::SHA1MSG2rm_EVEX, TB_ALIGN_16},
22532251
{X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16},
2254-
{X86::SHA1NEXTErr_EVEX, X86::SHA1NEXTErm_EVEX, TB_ALIGN_16},
22552252
{X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16},
2256-
{X86::SHA1RNDS4rri_EVEX, X86::SHA1RNDS4rmi_EVEX, TB_ALIGN_16},
22572253
{X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16},
2258-
{X86::SHA256MSG1rr_EVEX, X86::SHA256MSG1rm_EVEX, TB_ALIGN_16},
22592254
{X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16},
2260-
{X86::SHA256MSG2rr_EVEX, X86::SHA256MSG2rm_EVEX, TB_ALIGN_16},
22612255
{X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16},
2262-
{X86::SHA256RNDS2rr_EVEX, X86::SHA256RNDS2rm_EVEX, TB_ALIGN_16},
22632256
{X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16},
22642257
{X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16},
22652258
{X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE},

‎llvm/utils/TableGen/X86FoldTablesEmitter.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,8 @@ struct ManualMapEntry {
3333
};
3434

3535
// List of instructions requiring explicitly aligned memory.
36-
const char *ExplicitAlign[] = {
37-
"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS", "MOVNTPD",
38-
"MOVNTDQ", "MOVNTDQA", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE",
39-
"SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2"};
36+
const char *ExplicitAlign[] = {"MOVDQA", "MOVAPS", "MOVAPD", "MOVNTPS",
37+
"MOVNTPD", "MOVNTDQ", "MOVNTDQA"};
4038

4139
// List of instructions NOT requiring explicit memory alignment.
4240
const char *ExplicitUnalign[] = {"MOVDQU", "MOVUPS", "MOVUPD",

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