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RP2040 updates for SMP
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‎portable/ThirdParty/GCC/RP2040/README.md

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## Overview
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This directory provides a FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports:
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This directory provides an SMP FreeRTOS-Kernel port that can be used with the Raspberry Pi Pico SDK. It supports:
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* Simple CMake INTERFACE libraries, to provide the FreeRTOS-Kernel and also the individual allocator types, without copying code into the user's project.
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* Running the FreeRTOS-Kernel and tasks on either core 0 or core 1
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* Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on the other core, or in IRQ handlers.
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* Running the FreeRTOS-Kernel and tasks on either core 0 or core 1, or both.
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* Use of SDK synchronization primitives (such as mutexes, semaphores, queues from pico_sync) between FreeRTOS tasks and code executing on a non FreeRTOS core, or in IRQ handlers.
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Note that a FreeRTOS SMP version of this port is also available in the FreeRTOS-Kernel smp branch, which additionally supports utilizing both RP2040 CPU cores for FreeRTOS tasks simultaneously.
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Note that whilst this SMP version can be run on just a single (either) core, it is probably
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more efficient to use the non SMP version in the main FreeRTOS-Kernel branch in that case.
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## Using this port
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‎portable/ThirdParty/GCC/RP2040/include/portmacro.h

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#endif
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#include "pico.h"
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#include "hardware/sync.h"
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* as our FreeRTOSConfig.h header cannot be included by ASM code - which is what this affects in the SDK */
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#define portUSE_DIVIDER_SAVE_RESTORE !PICO_DIVIDER_DISABLE_INTERRUPTS
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#if portUSE_DIVIDER_SAVE_RESTORE
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#define portSTACK_LIMIT_PADDING 4
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#define portSTACK_LIMIT_PADDING 4
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#endif
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/*-----------------------------------------------------------*/
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#define xPortSysTickHandler isr_systick
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#endif
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/*-----------------------------------------------------------*/
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/* Multi-core */
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#define portSUPPORT_SMP 1 /* this is an SMP build which means configNUM_CORES is relevant */
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#define portMAX_CORE_COUNT 2
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#ifndef configNUM_CORES
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#define configNUM_CORES 2
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#endif
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/* Requires for SMP */
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#define portCRITICAL_NESTING_IN_TCB 1
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/*-----------------------------------------------------------*/
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/* Check validity of number of cores specified in config */
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#if ( configNUM_CORES < 1 || portMAX_CORE_COUNT < configNUM_CORES )
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#error "Invalid number of cores specified in config!"
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#endif
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#if ( configTICK_CORE < 0 || configTICK_CORE > configNUM_CORES )
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#error "Invalid tick core specified in config!"
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#endif
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/* FreeRTOS core id is always zero based, so always 0 if we're running on only one core */
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#if configNUM_CORES == portMAX_CORE_COUNT
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#define portGET_CORE_ID() get_core_num()
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#else
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#define portGET_CORE_ID() 0
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#endif
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#define portCHECK_IF_IN_ISR() ({ \
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uint32_t ulIPSR; \
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__asm volatile ("mrs %0, IPSR" : "=r" (ulIPSR)::); \
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((uint8_t)ulIPSR)>0;})
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void vYieldCore(int xCoreID);
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#define portYIELD_CORE(a) vYieldCore(a)
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#define portRESTORE_INTERRUPTS(ulState) __asm volatile ("msr PRIMASK,%0"::"r" (ulState) : )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
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extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__( ( naked ) );
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#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) vClearInterruptMaskFromISR( x )
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#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
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#define portSET_INTERRUPT_MASK_FROM_ISR() ({ uint32_t ulStateISR = portDISABLE_INTERRUPTS(); vTaskEnterCritical(); ulStateISR; })
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x ) do { vTaskExitCritical(); portRESTORE_INTERRUPTS( x ); } while (0)
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#define portDISABLE_INTERRUPTS() ({ \
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uint32_t ulState; \
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__asm volatile ("mrs %0, PRIMASK" : "=r" (ulState)::); \
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__asm volatile ( " cpsid i " ::: "memory" ); \
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ulState;})
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extern void vPortEnableInterrupts();
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#define portENABLE_INTERRUPTS() vPortEnableInterrupts()
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical()
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#define portEXIT_CRITICAL() vPortExitCritical()
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void vTaskEnterCritical(void);
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void vTaskExitCritical(void);
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#define portENTER_CRITICAL() vTaskEnterCritical()
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#define portEXIT_CRITICAL() vTaskExitCritical()
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#define portSIO_SPINLOCK_ISR portSIO_SPINLOCK0
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#define portSIO_SPINLOCK_TASK portSIO_SPINLOCK1
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#define portRTOS_SPINLOCK_COUNT 2
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/* Note this is a single method with uxAcquire parameter since we have
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* static vars, the method is always called with a compile time constant for
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* uxAcquire, and the compiler should dothe right thing! */
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static inline void vPortRecursiveLock(uint32_t ulLockNum, spin_lock_t *pxSpinLock, BaseType_t uxAcquire) {
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static uint8_t ucOwnedByCore[ portMAX_CORE_COUNT ];
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static uint8_t ucRecursionCountByLock[ portRTOS_SPINLOCK_COUNT ];
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configASSERT(ulLockNum >= 0 && ulLockNum < portRTOS_SPINLOCK_COUNT );
184+
uint32_t ulCoreNum = get_core_num();
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uint32_t ulLockBit = 1u << ulLockNum;
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configASSERT(ulLockBit < 256u );
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if( uxAcquire )
188+
{
189+
if( __builtin_expect( !*pxSpinLock, 0 ) )
190+
{
191+
if( ucOwnedByCore[ulCoreNum] & ulLockBit )
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{
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configASSERT(ucRecursionCountByLock[ulLockNum] != 255u );
194+
ucRecursionCountByLock[ulLockNum]++;
195+
return;
196+
}
197+
while ( __builtin_expect( !*pxSpinLock, 0 ) );
198+
}
199+
__mem_fence_acquire();
200+
configASSERT(ucRecursionCountByLock[ulLockNum] == 0 );
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ucRecursionCountByLock[ulLockNum] = 1;
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ucOwnedByCore[ulCoreNum] |= ulLockBit;
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} else {
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configASSERT((ucOwnedByCore[ulCoreNum] & ulLockBit) != 0 );
205+
configASSERT(ucRecursionCountByLock[ulLockNum] != 0 );
206+
if( !--ucRecursionCountByLock[ulLockNum] )
207+
{
208+
ucOwnedByCore[ulCoreNum] &= ~ulLockBit;
209+
__mem_fence_release();
210+
*pxSpinLock = 1;
211+
}
212+
}
213+
}
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215+
#define portGET_ISR_LOCK() vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdTRUE)
216+
#define portRELEASE_ISR_LOCK() vPortRecursiveLock(0, spin_lock_instance(configSMP_SPINLOCK_0), pdFALSE)
217+
#define portGET_TASK_LOCK() vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdTRUE)
218+
#define portRELEASE_TASK_LOCK() vPortRecursiveLock(1, spin_lock_instance(configSMP_SPINLOCK_1), pdFALSE)
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/*-----------------------------------------------------------*/
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‎portable/ThirdParty/GCC/RP2040/include/rp2040_config.h

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@@ -66,6 +66,24 @@ extern "C" {
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#endif
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#endif
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69+
#if (configNUM_CORES > 1)
70+
/* configTICK_CORE indicates which core should handle the SysTick
71+
* interrupts */
72+
#ifndef configTICK_CORE
73+
#define configTICK_CORE 0
74+
#endif
75+
#endif
76+
77+
/* This SMP port requires two spin locks, which are claimed from the SDK.
78+
* the spin lock numbers to be used are defined statically and defaulted here */
79+
#ifndef configSMP_SPINLOCK_0
80+
#define configSMP_SPINLOCK_0 30
81+
#endif
82+
83+
#ifndef configSMP_SPINLOCK_1
84+
#define configSMP_SPINLOCK_1 31
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#endif
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#ifdef __cplusplus
7088
};
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#endif

‎portable/ThirdParty/GCC/RP2040/library.cmake

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@@ -32,11 +32,14 @@ target_include_directories(FreeRTOS-Kernel INTERFACE
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target_link_libraries(FreeRTOS-Kernel INTERFACE
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FreeRTOS-Kernel-Core
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pico_base_headers
35-
hardware_exception)
35+
hardware_clocks
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hardware_exception
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pico_multicore
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)
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target_compile_definitions(FreeRTOS-Kernel INTERFACE
3841
LIB_FREERTOS_KERNEL=1
39-
FREE_RTOS_KERNEL_SMP=0
42+
FREE_RTOS_KERNEL_SMP=1
4043
)
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add_library(FreeRTOS-Kernel-Static INTERFACE)

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