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Use highest numbered MPU regions for kernel
ARMv7-M allows overlapping MPU regions. When 2 MPU regions overlap, the MPU configuration of the higher numbered MPU region is applied. For example, if a memory area is covered by 2 MPU regions 0 and 1, the memory permissions for MPU region 1 are applied. We use 5 MPU regions for kernel code and kernel data protections and leave the remaining for the application writer. We were using lowest numbered MPU regions (0-4) for kernel protections and leaving the remaining for the application writer. The application writer could configure those higher numbered MPU regions to override kernel protections. This commit changes the code to use highest numbered MPU regions for kernel protections and leave the remaining for the application writer. This ensures that the application writer cannot override kernel protections. We thank the SecLab team at Northeastern University for reporting this issue. Signed-off-by: Gaurav Aggarwal <[email protected]>
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8 files changed

+79
-134
lines changed

8 files changed

+79
-134
lines changed

‎portable/GCC/ARM_CM3_MPU/port.c

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -756,31 +756,18 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
756756
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
757757
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
758758
( portMPU_REGION_VALID ) |
759-
( portSTACK_REGION );
759+
( portSTACK_REGION ); /* Region number. */
760760

761761
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
762762
( portMPU_REGION_READ_WRITE ) |
763763
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
764764
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
765765
( portMPU_REGION_ENABLE );
766766

767-
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
768-
* just removed the privileged only parameters. */
769-
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
770-
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
771-
( portMPU_REGION_VALID ) |
772-
( portSTACK_REGION + 1 );
773-
774-
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
775-
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
776-
( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
777-
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
778-
( portMPU_REGION_ENABLE );
779-
780-
/* Invalidate all other regions. */
781-
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
767+
/* Invalidate user configurable regions. */
768+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
782769
{
783-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
770+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
784771
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
785772
}
786773
}
@@ -807,7 +794,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
807794

808795
lIndex = 0;
809796

810-
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
797+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
811798
{
812799
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
813800
{
@@ -817,7 +804,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
817804
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
818805
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
819806
( portMPU_REGION_VALID ) |
820-
( portSTACK_REGION + ul ); /* Region number. */
807+
( ul - 1UL ); /* Region number. */
821808

822809
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
823810
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -827,7 +814,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
827814
else
828815
{
829816
/* Invalidate the region. */
830-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
817+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
831818
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
832819
}
833820

‎portable/GCC/ARM_CM3_MPU/portmacro.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -82,15 +82,15 @@
8282
#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x07UL << 16UL )
8383
#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 28UL )
8484

85-
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
86-
#define portPRIVILEGED_FLASH_REGION ( 1UL )
87-
#define portPRIVILEGED_RAM_REGION ( 2UL )
8885
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
8986
#define portSTACK_REGION ( 4UL )
90-
#define portFIRST_CONFIGURABLE_REGION ( 5UL )
91-
#define portLAST_CONFIGURABLE_REGION ( 7UL )
87+
#define portUNPRIVILEGED_FLASH_REGION ( 5UL )
88+
#define portPRIVILEGED_FLASH_REGION ( 6UL )
89+
#define portPRIVILEGED_RAM_REGION ( 7UL )
90+
#define portFIRST_CONFIGURABLE_REGION ( 0UL )
91+
#define portLAST_CONFIGURABLE_REGION ( 2UL )
9292
#define portNUM_CONFIGURABLE_REGIONS ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
93-
#define portTOTAL_NUM_REGIONS ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
93+
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
9494

9595
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
9696

@@ -103,7 +103,7 @@
103103
/* Plus 1 to create space for the stack region. */
104104
typedef struct MPU_SETTINGS
105105
{
106-
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
106+
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
107107
} xMPU_SETTINGS;
108108

109109
/* Architecture specifics. */

‎portable/GCC/ARM_CM4_MPU/port.c

Lines changed: 13 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@
8181
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
8282
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
8383
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
84-
#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
84+
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
8585
#define portMPU_ENABLE ( 0x01UL )
8686
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
8787
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -380,12 +380,12 @@ static void prvRestoreContextOfFirstTask( void )
380380
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
381381
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
382382
" \n"
383-
#if ( portTOTAL_NUM_REGIONS == 16 )
383+
#if ( configTOTAL_MPU_REGIONS == 16 )
384384
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
385385
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
386386
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
387387
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
388-
#endif /* portTOTAL_NUM_REGIONS == 16. */
388+
#endif /* configTOTAL_MPU_REGIONS == 16. */
389389
" \n"
390390
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
391391
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@@ -633,12 +633,12 @@ void xPortPendSVHandler( void )
633633
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
634634
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
635635
" \n"
636-
#if ( portTOTAL_NUM_REGIONS == 16 )
636+
#if ( configTOTAL_MPU_REGIONS == 16 )
637637
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
638638
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
639639
" ldmia r1!, {r4-r11} \n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
640640
" stmia r2, {r4-r11} \n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
641-
#endif /* portTOTAL_NUM_REGIONS == 16. */
641+
#endif /* configTOTAL_MPU_REGIONS == 16. */
642642
" \n"
643643
" ldr r2, =0xe000ed94 \n"/* MPU_CTRL register. */
644644
" ldr r3, [r2] \n"/* Read the value of MPU_CTRL. */
@@ -736,7 +736,7 @@ static void prvSetupMPU( void )
736736
#endif /* if defined( __ARMCC_VERSION ) */
737737

738738
/* The only permitted number of regions are 8 or 16. */
739-
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
739+
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
740740

741741
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
742742
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -879,31 +879,18 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
879879
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
880880
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
881881
( portMPU_REGION_VALID ) |
882-
( portSTACK_REGION );
882+
( portSTACK_REGION ); /* Region number. */
883883

884884
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
885885
( portMPU_REGION_READ_WRITE ) |
886886
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
887887
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
888888
( portMPU_REGION_ENABLE );
889889

890-
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
891-
* just removed the privileged only parameters. */
892-
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
893-
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
894-
( portMPU_REGION_VALID ) |
895-
( portSTACK_REGION + 1 );
896-
897-
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
898-
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
899-
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
900-
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
901-
( portMPU_REGION_ENABLE );
902-
903-
/* Invalidate all other regions. */
904-
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
890+
/* Invalidate user configurable regions. */
891+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
905892
{
906-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
893+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
907894
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
908895
}
909896
}
@@ -930,7 +917,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
930917

931918
lIndex = 0;
932919

933-
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
920+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
934921
{
935922
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
936923
{
@@ -940,7 +927,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
940927
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
941928
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
942929
( portMPU_REGION_VALID ) |
943-
( portSTACK_REGION + ul ); /* Region number. */
930+
( ul - 1UL ); /* Region number. */
944931

945932
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
946933
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -950,7 +937,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
950937
else
951938
{
952939
/* Invalidate the region. */
953-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
940+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
954941
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
955942
}
956943

‎portable/GCC/ARM_CM4_MPU/portmacro.h

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -173,15 +173,15 @@ typedef unsigned long UBaseType_t;
173173
#define configTEX_S_C_B_SRAM ( 0x07UL )
174174
#endif
175175

176-
#define portUNPRIVILEGED_FLASH_REGION ( 0UL )
177-
#define portPRIVILEGED_FLASH_REGION ( 1UL )
178-
#define portPRIVILEGED_RAM_REGION ( 2UL )
179-
#define portGENERAL_PERIPHERALS_REGION ( 3UL )
180-
#define portSTACK_REGION ( 4UL )
181-
#define portFIRST_CONFIGURABLE_REGION ( 5UL )
182-
#define portTOTAL_NUM_REGIONS ( configTOTAL_MPU_REGIONS )
183-
#define portNUM_CONFIGURABLE_REGIONS ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
184-
#define portLAST_CONFIGURABLE_REGION ( portTOTAL_NUM_REGIONS - 1 )
176+
#define portGENERAL_PERIPHERALS_REGION ( configTOTAL_MPU_REGIONS - 5UL )
177+
#define portSTACK_REGION ( configTOTAL_MPU_REGIONS - 4UL )
178+
#define portUNPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 3UL )
179+
#define portPRIVILEGED_FLASH_REGION ( configTOTAL_MPU_REGIONS - 2UL )
180+
#define portPRIVILEGED_RAM_REGION ( configTOTAL_MPU_REGIONS - 1UL )
181+
#define portFIRST_CONFIGURABLE_REGION ( 0UL )
182+
#define portLAST_CONFIGURABLE_REGION ( configTOTAL_MPU_REGIONS - 6UL )
183+
#define portNUM_CONFIGURABLE_REGIONS ( configTOTAL_MPU_REGIONS - 5UL )
184+
#define portTOTAL_NUM_REGIONS_IN_TCB ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus 1 to create space for the stack region. */
185185

186186
#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
187187

@@ -191,10 +191,9 @@ typedef struct MPU_REGION_REGISTERS
191191
uint32_t ulRegionAttribute;
192192
} xMPU_REGION_REGISTERS;
193193

194-
/* Plus 1 to create space for the stack region. */
195194
typedef struct MPU_SETTINGS
196195
{
197-
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
196+
xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS_IN_TCB ];
198197
} xMPU_SETTINGS;
199198

200199
/* Architecture specifics. */

‎portable/IAR/ARM_CM4F_MPU/port.c

Lines changed: 9 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@
8282
#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
8383
#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
8484
#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
85-
#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
85+
#define portEXPECTED_MPU_TYPE_VALUE ( configTOTAL_MPU_REGIONS << 8UL )
8686
#define portMPU_ENABLE ( 0x01UL )
8787
#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
8888
#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
@@ -555,7 +555,7 @@ static void prvSetupMPU( void )
555555
extern uint32_t __privileged_data_end__[];
556556

557557
/* The only permitted number of regions are 8 or 16. */
558-
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
558+
configASSERT( ( configTOTAL_MPU_REGIONS == 8 ) || ( configTOTAL_MPU_REGIONS == 16 ) );
559559

560560
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
561561
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
@@ -656,31 +656,18 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
656656
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
657657
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
658658
( portMPU_REGION_VALID ) |
659-
( portSTACK_REGION );
659+
( portSTACK_REGION ); /* Region number. */
660660

661661
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
662662
( portMPU_REGION_READ_WRITE ) |
663663
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
664664
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
665665
( portMPU_REGION_ENABLE );
666666

667-
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
668-
* just removed the privileged only parameters. */
669-
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
670-
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
671-
( portMPU_REGION_VALID ) |
672-
( portSTACK_REGION + 1 );
673-
674-
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
675-
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
676-
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
677-
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
678-
( portMPU_REGION_ENABLE );
679-
680-
/* Invalidate all other regions. */
681-
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
667+
/* Invalidate user configurable regions. */
668+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
682669
{
683-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
670+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
684671
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
685672
}
686673
}
@@ -707,7 +694,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
707694

708695
lIndex = 0;
709696

710-
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
697+
for( ul = 1UL; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
711698
{
712699
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
713700
{
@@ -717,7 +704,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
717704
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
718705
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
719706
( portMPU_REGION_VALID ) |
720-
( portSTACK_REGION + ul ); /* Region number. */
707+
( ul - 1UL ); /* Region number. */
721708

722709
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
723710
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
@@ -727,7 +714,7 @@ void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
727714
else
728715
{
729716
/* Invalidate the region. */
730-
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
717+
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( ( ul - 1UL ) | portMPU_REGION_VALID );
731718
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
732719
}
733720

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