Update ESP32 port to ESP-IDF release v4.2 and add ESP-IDF version check (#231)

* Revert "Reintroduce Espressif's IDF v4.2 changes to ESP32 port (#193)"

This reverts commit 3d4d171.

* Update ESP32 port files to work with ESP-IDF v4.2 as well as ESP-IDF v3.3

Add changes required to support ESP32-S2

* portmacro.h: Change return type of vApplicationSleep to void

This fixes build failure when automatic light sleep is enabled

* prevent header checks for files with different licensing

Co-authored-by: David Chalco <[email protected]>

Author: shubhamkulkarni97

.github/scripts/kernel_checker.py

@@ -6,6 +6,10 @@
 #--------------------------------------------------------------------------------------------------
 #                                            CONFIG
 #--------------------------------------------------------------------------------------------------
+KERNEL_IGNORED_FILES = [
+    'FreeRTOS-openocd.c'
+]
+
 KERNEL_IGNORED_EXTENSIONS = [
     '.yml',
     '.css',
@@ -30,7 +34,13 @@
 ]
 
 KERNEL_IGNORED_PATTERNS = [
-    r'.*\.git.*'
+    r'.*\.git.*',
+    r'.*portable.*Xtensa_ESP32\/include\/portmacro\.h',
+    r'.*portable.*Xtensa_ESP32.*port\.c',
+    r'.*portable.*Xtensa_ESP32.*portasm\.S',
+    r'.*portable.*Xtensa_ESP32.*xtensa_.*',
+    r'.*portable.*Xtensa_ESP32.*portmux_impl.*',
+    r'.*portable.*Xtensa_ESP32.*xt_asm_utils\.h'
 ]
 
 KERNEL_HEADER = [
@@ -70,6 +80,7 @@ def main():
     checker = HeaderChecker(KERNEL_HEADER)
     checker.ignoreExtension(*KERNEL_IGNORED_EXTENSIONS)
     checker.ignorePattern(*KERNEL_IGNORED_PATTERNS)
+    checker.ignoreFile(*KERNEL_IGNORED_FILES)
     checker.ignoreFile(os.path.split(__file__)[-1])
 
     return checker.processArgs(args)

portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h

@@ -82,6 +82,7 @@
     #include <xtensa/xtruntime.h>
     #include "esp_timer.h"            /* required for FreeRTOS run time stats */
     #include "esp_system.h"
+    #include "esp_idf_version.h"
 
 
     #include <esp_heap_caps.h>
@@ -134,9 +135,9 @@
         /* owner field values:
          * 0                - Uninitialized (invalid)
          * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
-         * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
+         * CORE_ID_REGVAL_PRO / CORE_ID_REGVAL_APP - Mux is locked to the particular core
          *
-         * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
+         * Any value other than portMUX_FREE_VAL, CORE_ID_REGVAL_PRO, CORE_ID_REGVAL_APP indicates corruption
          */
         uint32_t owner;
 
@@ -283,8 +284,11 @@
 
 /*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
 /*the stack memory to always be internal. */
-    #define pvPortMallocTcbMem( size )        heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
-    #define pvPortMallocStackMem( size )      heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+    #define portTcbMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
+    #define portStackMemoryCaps (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
+
+    #define pvPortMallocTcbMem(size) heap_caps_malloc(size, portTcbMemoryCaps)
+    #define pvPortMallocStackMem(size)  heap_caps_malloc(size, portStackMemoryCaps)
 
 /*xTaskCreateStatic uses these functions to check incoming memory. */
     #define portVALID_TCB_MEM( ptr )          ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
@@ -307,6 +311,14 @@
                                              uint32_t compare,
                                              uint32_t * set )
         {
+            #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+            __asm__ __volatile__ (
+                "WSR       %2,SCOMPARE1 \n"
+                "S32C1I     %0, %1, 0   \n"
+                : "=r" ( *set )
+                : "r" ( addr ), "r" ( compare ), "0" ( *set )
+                );
+            #else
             #if ( XCHAL_HAVE_S32C1I > 0 )
                 __asm__ __volatile__ (
                     "WSR 	    %2,SCOMPARE1 \n"
@@ -333,11 +345,21 @@
 
                 *set = old_value;
             #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
+            #endif /* #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0)) */
         }
 
+        #if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
         void uxPortCompareSetExtram( volatile uint32_t * addr,
                                      uint32_t compare,
                                      uint32_t * set );
+        #else
+        static inline void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set) 
+        {
+        #if defined(CONFIG_ESP32_SPIRAM_SUPPORT)    
+            compare_and_set_extram(addr, compare, set);
+        #endif    
+        }
+        #endif
 
 /*-----------------------------------------------------------*/
 
@@ -408,11 +430,37 @@
         #define PRIVILEGED_DATA
     #endif
 
-    bool vApplicationSleep( TickType_t xExpectedIdleTime );
+    void vApplicationSleep( TickType_t xExpectedIdleTime );
+    void vPortSetStackWatchpoint( void* pxStackStart );
 
     #define portSUPPRESS_TICKS_AND_SLEEP( idleTime )    vApplicationSleep( idleTime )
 
+    /*-----------------------------------------------------------*/
 
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))    
+    /* Architecture specific optimisations. */
+    
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+    
+    /* Check the configuration. */
+    #if( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 different priorities as tasks that share a priority will time slice.
+    #endif
+    
+    /* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+    
+    /*-----------------------------------------------------------*/
+    
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
+    
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
+    
+    /*-----------------------------------------------------------*/
+    
 
     void _xt_coproc_release( volatile void * coproc_sa_base );
 
@@ -429,6 +477,15 @@
     #define xPortGetFreeHeapSize               esp_get_free_heap_size
     #define xPortGetMinimumEverFreeHeapSize    esp_get_minimum_free_heap_size
 
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+/*
+ * Send an interrupt to another core in order to make the task running
+ * on it yield for a higher-priority task.
+ */
+
+        void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION;
+
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
 
 /*
  * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
@@ -442,6 +499,7 @@
  */
     BaseType_t xPortInIsrContext();
 
+
 /*
  * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
  * before calling into high prio ISR context.

portable/ThirdParty/GCC/Xtensa_ESP32/include/xt_asm_utils.h

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* File adapted to use on IDF FreeRTOS component, extracted 
+ * originally from zephyr RTOS code base:
+ * https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
+ */
+
+#ifndef __XT_ASM_UTILS_H
+#define __XT_ASM_UTILS_H
+
+/*
+ * SPILL_ALL_WINDOWS
+ *
+ * Spills all windowed registers (i.e. registers not visible as
+ * A0-A15) to their ABI-defined spill regions on the stack.
+ *
+ * Unlike the Xtensa HAL implementation, this code requires that the
+ * EXCM and WOE bit be enabled in PS, and relies on repeated hardware
+ * exception handling to do the register spills.  The trick is to do a
+ * noop write to the high registers, which the hardware will trap
+ * (into an overflow exception) in the case where those registers are
+ * already used by an existing call frame.  Then it rotates the window
+ * and repeats until all but the A0-A3 registers of the original frame
+ * are guaranteed to be spilled, eventually rotating back around into
+ * the original frame.  Advantages:
+ *
+ * - Vastly smaller code size
+ *
+ * - More easily maintained if changes are needed to window over/underflow
+ *   exception handling.
+ *
+ * - Requires no scratch registers to do its work, so can be used safely in any
+ *   context.
+ *
+ * - If the WOE bit is not enabled (for example, in code written for
+ *   the CALL0 ABI), this becomes a silent noop and operates compatbily.
+ *
+ * - Hilariously it's ACTUALLY FASTER than the HAL routine.  And not
+ *   just a little bit, it's MUCH faster.  With a mostly full register
+ *   file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
+ *   registers with this vs. 279 (!) to do it with
+ *   xthal_spill_windows().  
+ */
+
+.macro SPILL_ALL_WINDOWS
+#if XCHAL_NUM_AREGS == 64
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 4
+#elif XCHAL_NUM_AREGS == 32
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a4, a4, a4
+	rotw 2
+#else
+#error Unrecognized XCHAL_NUM_AREGS
+#endif
+.endm
+
+#endif

portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h

@@ -45,6 +45,7 @@ NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
 #include    <xtensa/corebits.h>
 #include    <xtensa/config/system.h>
 #include <xtensa/xtruntime-frames.h>
+#include    <esp_idf_version.h>
 
 
 /* Align a value up to nearest n-byte boundary, where n is a power of 2. */
@@ -325,8 +326,19 @@ STRUCT_END(XtSolFrame)
 	.endm
 #endif
 
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
 #define CORE_ID_PRO 0xCDCD
 #define CORE_ID_APP 0xABAB
+#else
+#define CORE_ID_REGVAL_PRO 0xCDCD
+#define CORE_ID_REGVAL_APP 0xABAB
+
+/* Included for compatibility, recommend using CORE_ID_REGVAL_PRO instead */
+#define CORE_ID_PRO CORE_ID_REGVAL_PRO
+
+/* Included for compatibility, recommend using CORE_ID_REGVAL_APP instead */
+#define CORE_ID_APP CORE_ID_REGVAL_APP
+#endif
 
 /*
 -------------------------------------------------------------------------------

portable/ThirdParty/GCC/Xtensa_ESP32/port.c

@@ -96,24 +96,31 @@
 #include <xtensa/config/core.h>
 
 #include "xtensa_rtos.h"
+#include "esp_idf_version.h"
 
+#if (ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0))
+#include "rom/ets_sys.h"
+#include "esp_panic.h"
+#include "esp_crosscore_int.h"
+#else
 #if CONFIG_IDF_TARGET_ESP32S2
     #include "esp32s2/rom/ets_sys.h"
 #elif CONFIG_IDF_TARGET_ESP32
     #include "esp32/rom/ets_sys.h"
 #endif
+#include "esp_private/panic_reason.h"
+#include "esp_debug_helpers.h"
+#include "esp_private/crosscore_int.h"
+#include "esp_log.h"
+#endif /* ESP_IDF_VERSION < ESP_IDF_VERSION_VAL(4, 2, 0) */
 #include "soc/cpu.h"
 
 #include "FreeRTOS.h"
 #include "task.h"
 
-#include "esp_private/panic_reason.h"
-#include "esp_debug_helpers.h"
 #include "esp_heap_caps.h"
-#include "esp_private/crosscore_int.h"
 
 #include "esp_intr_alloc.h"
-#include "esp_log.h"
 
 /* Defined in portasm.h */
 extern void _frxt_tick_timer_init( void );
@@ -488,6 +495,8 @@ void vPortSetStackWatchpoint( void * pxStackStart )
     {
         uint32_t prev;
 
+        uint32_t oldlevel = portENTER_CRITICAL_NESTED();
+
         #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
             vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
         #else
@@ -506,6 +515,8 @@ void vPortSetStackWatchpoint( void * pxStackStart )
         #else
             vPortCPUReleaseMutexIntsDisabled( &extram_mux );
         #endif
+
+        portEXIT_CRITICAL_NESTED(oldlevel);
     }
 #endif //defined(CONFIG_SPIRAM_SUPPORT)
 

portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S

@@ -25,6 +25,7 @@
 
 #include "xtensa_rtos.h"
 #include "sdkconfig.h"
+#include "esp_idf_version.h"
 
 #define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
 #define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
@@ -138,23 +139,27 @@ _frxt_int_enter:
 	mull	a2,  a4, a2
 	add     a1,  a1, a2					/* for current proc */
 
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
     #ifdef CONFIG_FREERTOS_FPU_IN_ISR
     #if XCHAL_CP_NUM > 0
     rsr     a3, CPENABLE                /* Restore thread scope CPENABLE */
     addi    sp, sp,-4                   /* ISR will manage FPU coprocessor by forcing */
     s32i    a3, a1, 0                   /* its trigger */
     #endif
     #endif
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
 
 .Lnested:
 1:
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
     #ifdef CONFIG_FREERTOS_FPU_IN_ISR
     #if XCHAL_CP_NUM > 0
     movi    a3,  0              /* whilst ISRs pending keep CPENABLE exception active */
     wsr     a3,  CPENABLE
     rsync
     #endif
     #endif
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
 
     mov     a0,  a12                    /* restore return addr and return  */
     ret
@@ -192,6 +197,7 @@ _frxt_int_exit:
     s32i    a2,  a3, 0                  /* save nesting count              */
     bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
 
+    #if (ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0))
     #ifdef CONFIG_FREERTOS_FPU_IN_ISR 
     #if XCHAL_CP_NUM > 0
     l32i    a3,  sp, 0                  /* Grab last CPENABLE before leave ISR */
@@ -200,6 +206,7 @@ _frxt_int_exit:
     rsync                               /* ensure CPENABLE was modified */
     #endif
     #endif
+    #endif /* ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(4, 2, 0) */
 
     movi    a2,  pxCurrentTCB
 	addx4	a2,  a4, a2