From 79eaf665b9df8636076e720e9abd83225f42b321 Mon Sep 17 00:00:00 2001 From: Ching-Hsin Lee Date: Tue, 30 May 2023 17:25:08 +0800 Subject: [PATCH 1/4] Add config to disable prio bits check * Add configDISABLE_INTERRUPT_PRIO_BITS_CHECK to disable cortex-M PRIO bits check. --- portable/CCS/ARM_CM3/port.c | 43 ++++++++++++++++------------- portable/CCS/ARM_CM4F/port.c | 43 ++++++++++++++++------------- portable/GCC/ARM_CM3/port.c | 43 ++++++++++++++++------------- portable/GCC/ARM_CM3_MPU/port.c | 45 ++++++++++++++++++------------- portable/GCC/ARM_CM4F/port.c | 43 ++++++++++++++++------------- portable/GCC/ARM_CM4_MPU/port.c | 45 ++++++++++++++++++------------- portable/GCC/ARM_CM7/r0p1/port.c | 43 ++++++++++++++++------------- portable/IAR/ARM_CM3/port.c | 43 ++++++++++++++++------------- portable/IAR/ARM_CM4F/port.c | 43 ++++++++++++++++------------- portable/IAR/ARM_CM4F_MPU/port.c | 43 ++++++++++++++++------------- portable/IAR/ARM_CM7/r0p1/port.c | 43 ++++++++++++++++------------- portable/MikroC/ARM_CM4F/port.c | 43 ++++++++++++++++------------- portable/RVDS/ARM_CM3/port.c | 43 ++++++++++++++++------------- portable/RVDS/ARM_CM4F/port.c | 43 ++++++++++++++++------------- portable/RVDS/ARM_CM4_MPU/port.c | 43 ++++++++++++++++------------- portable/RVDS/ARM_CM7/r0p1/port.c | 43 ++++++++++++++++------------- 16 files changed, 402 insertions(+), 290 deletions(-) diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c index f3c4e5add03..bfdcc728f4a 100755 --- a/portable/CCS/ARM_CM3/port.c +++ b/portable/CCS/ARM_CM3/port.c @@ -285,27 +285,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c index c675afe67b4..fcfaa352512 100755 --- a/portable/CCS/ARM_CM4F/port.c +++ b/portable/CCS/ARM_CM4F/port.c @@ -304,27 +304,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c index 9b42eac5a4e..9af95e46c6c 100755 --- a/portable/GCC/ARM_CM3/port.c +++ b/portable/GCC/ARM_CM3/port.c @@ -328,27 +328,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c index 619f2b0c8be..b94c700e09a 100755 --- a/portable/GCC/ARM_CM3_MPU/port.c +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -451,27 +451,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ + + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c index 88fc76db894..f5386b4db56 100755 --- a/portable/GCC/ARM_CM4F/port.c +++ b/portable/GCC/ARM_CM4F/port.c @@ -371,27 +371,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index ab76ee84204..855a15688fc 100755 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -494,27 +494,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried - * from hardware is at least as many as specified in the - * CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ + + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried - * from hardware is at least as many as specified in the - * FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); - } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c index 2be4f27704d..258345516cb 100755 --- a/portable/GCC/ARM_CM7/r0p1/port.c +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -359,27 +359,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c index d54c3aceb4a..a178b6b927f 100755 --- a/portable/IAR/ARM_CM3/port.c +++ b/portable/IAR/ARM_CM3/port.c @@ -277,27 +277,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c index e0deaf12840..c0042188bde 100755 --- a/portable/IAR/ARM_CM4F/port.c +++ b/portable/IAR/ARM_CM4F/port.c @@ -315,27 +315,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c index 1b7cca65c86..456858aef99 100755 --- a/portable/IAR/ARM_CM4F_MPU/port.c +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -429,27 +429,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c index 63f83993db9..19a713cc440 100755 --- a/portable/IAR/ARM_CM7/r0p1/port.c +++ b/portable/IAR/ARM_CM7/r0p1/port.c @@ -303,27 +303,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index 8ef593f5523..8a251c67a15 100755 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -365,27 +365,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index ae7ce37f37b..c8354fb5a69 100755 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -330,27 +330,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c index cb003aa38f9..e7c618d2f89 100755 --- a/portable/RVDS/ARM_CM4F/port.c +++ b/portable/RVDS/ARM_CM4F/port.c @@ -396,27 +396,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index 13e2f8a8ed1..2d6e5c33256 100755 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -489,27 +489,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c index 1df54ab2802..d71984d55ba 100755 --- a/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -380,27 +380,34 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - #ifdef __NVIC_PRIO_BITS + /* The interrupt priority bits are not modelled in QEMU and the assert that + * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. + * Therefore, this assert is not adding any value for QEMU targets. The config + * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the + * `FreeRTOSConfig.h` for QEMU targets. */ + #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the CMSIS - * __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS ); - } - #endif + #ifdef __NVIC_PRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); + } + #endif /* __NVIC_PRIO_BITS */ - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is at least as many as specified in the FreeRTOS - * configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits >= configPRIO_BITS ); + #ifdef configPRIO_BITS + { + /* + * Check that the number of implemented priority bits queried from + * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. + */ + configASSERT( ulImplementedPrioBits == configPRIO_BITS ); + } + #endif /* configPRIO_BITS */ } - #endif + #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ /* Shift the priority group value back to its position within the AIRCR * register. */ From 13f418ee520cf30c03f7a4968feb72052e09dc6b Mon Sep 17 00:00:00 2001 From: Ching-Hsin Lee Date: Wed, 31 May 2023 20:04:48 +0800 Subject: [PATCH 2/4] Remove __NVIC_PRIO_BITS and configPRIO_BITS check * Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3 and CM4 * Add hardware not implemented bits check. These bits should be zero. --- portable/CCS/ARM_CM3/port.c | 36 ++++++------------------------- portable/CCS/ARM_CM4F/port.c | 36 ++++++------------------------- portable/GCC/ARM_CM3/port.c | 36 ++++++------------------------- portable/GCC/ARM_CM3_MPU/port.c | 36 ++++++------------------------- portable/GCC/ARM_CM4F/port.c | 36 ++++++------------------------- portable/GCC/ARM_CM4_MPU/port.c | 36 ++++++------------------------- portable/GCC/ARM_CM7/r0p1/port.c | 36 ++++++------------------------- portable/IAR/ARM_CM3/port.c | 36 ++++++------------------------- portable/IAR/ARM_CM4F/port.c | 36 ++++++------------------------- portable/IAR/ARM_CM4F_MPU/port.c | 36 ++++++------------------------- portable/IAR/ARM_CM7/r0p1/port.c | 36 ++++++------------------------- portable/MikroC/ARM_CM4F/port.c | 36 ++++++------------------------- portable/RVDS/ARM_CM3/port.c | 36 ++++++------------------------- portable/RVDS/ARM_CM4F/port.c | 36 ++++++------------------------- portable/RVDS/ARM_CM4_MPU/port.c | 36 ++++++------------------------- portable/RVDS/ARM_CM7/r0p1/port.c | 36 ++++++------------------------- 16 files changed, 112 insertions(+), 464 deletions(-) diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c index bfdcc728f4a..75ae9155d8f 100755 --- a/portable/CCS/ARM_CM3/port.c +++ b/portable/CCS/ARM_CM3/port.c @@ -249,6 +249,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -285,35 +292,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c index fcfaa352512..7021689e0ec 100755 --- a/portable/CCS/ARM_CM4F/port.c +++ b/portable/CCS/ARM_CM4F/port.c @@ -268,6 +268,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -304,35 +311,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c index 9af95e46c6c..7af43f41e07 100755 --- a/portable/GCC/ARM_CM3/port.c +++ b/portable/GCC/ARM_CM3/port.c @@ -292,6 +292,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -328,35 +335,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c index b94c700e09a..3ba55eeef62 100755 --- a/portable/GCC/ARM_CM3_MPU/port.c +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -415,6 +415,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -451,35 +458,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c index f5386b4db56..9ed0afe30de 100755 --- a/portable/GCC/ARM_CM4F/port.c +++ b/portable/GCC/ARM_CM4F/port.c @@ -335,6 +335,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -371,35 +378,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index 855a15688fc..bc5cd959b9d 100755 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -458,6 +458,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -494,35 +501,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c index 258345516cb..8c9ba1141ee 100755 --- a/portable/GCC/ARM_CM7/r0p1/port.c +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -323,6 +323,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -359,35 +366,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c index a178b6b927f..3194104136d 100755 --- a/portable/IAR/ARM_CM3/port.c +++ b/portable/IAR/ARM_CM3/port.c @@ -241,6 +241,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -277,35 +284,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c index c0042188bde..cb09de280b7 100755 --- a/portable/IAR/ARM_CM4F/port.c +++ b/portable/IAR/ARM_CM4F/port.c @@ -279,6 +279,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -315,35 +322,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c index 456858aef99..02fc594faf6 100755 --- a/portable/IAR/ARM_CM4F_MPU/port.c +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -393,6 +393,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -429,35 +436,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c index 19a713cc440..75954a6e3a9 100755 --- a/portable/IAR/ARM_CM7/r0p1/port.c +++ b/portable/IAR/ARM_CM7/r0p1/port.c @@ -267,6 +267,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -303,35 +310,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index 8a251c67a15..ea76b04840c 100755 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -329,6 +329,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -365,35 +372,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index c8354fb5a69..fc1d48c3745 100755 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -294,6 +294,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -330,35 +337,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c index e7c618d2f89..5649cba7e37 100755 --- a/portable/RVDS/ARM_CM4F/port.c +++ b/portable/RVDS/ARM_CM4F/port.c @@ -360,6 +360,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -396,35 +403,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index 2d6e5c33256..c3ff75e97f9 100755 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -453,6 +453,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -489,35 +496,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c index d71984d55ba..a3323a7d1eb 100755 --- a/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -344,6 +344,13 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -380,35 +387,6 @@ BaseType_t xPortStartScheduler( void ) ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; From c9332f88520fbeea5ea2919c0b23b39cdf015197 Mon Sep 17 00:00:00 2001 From: Ching-Hsin Lee Date: Wed, 31 May 2023 20:06:48 +0800 Subject: [PATCH 3/4] Remove __NVIC_PRIO_BITS and configPRIO_BITS check in ARMv8 * Remove __NVIC_PRIO_BITS and configPRIO_BITS check in ARMv8. * Add hardware not implemented bits check. These bits should be zero. --- portable/ARMv8M/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM23/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM33/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM35P/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM55/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM55_NTZ/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM85/non_secure/port.c | 36 ++++---------------- portable/GCC/ARM_CM85_NTZ/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM23/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM33/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM35P/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM55/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM55_NTZ/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM85/non_secure/port.c | 36 ++++---------------- portable/IAR/ARM_CM85_NTZ/non_secure/port.c | 36 ++++---------------- 21 files changed, 147 insertions(+), 609 deletions(-) diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM35P/non_secure/port.c +++ b/portable/GCC/ARM_CM35P/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM55/non_secure/port.c +++ b/portable/GCC/ARM_CM55/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM85/non_secure/port.c +++ b/portable/GCC/ARM_CM85/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM35P/non_secure/port.c +++ b/portable/IAR/ARM_CM35P/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM55/non_secure/port.c +++ b/portable/IAR/ARM_CM55/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM85/non_secure/port.c +++ b/portable/IAR/ARM_CM85/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 7bbe1b7bc53..0f9b7337d64 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -1128,6 +1128,13 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); + /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. + * Assertion here helps inform that the configuration is not set to hardware + * as expected, although hardware ignores these bits. Possible reason here is + * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware + * implemented bits. */ + configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); + /* Calculate the maximum acceptable priority group value for the number * of bits read back. */ @@ -1164,35 +1171,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits; } - /* The interrupt priority bits are not modelled in QEMU and the assert that - * checks the number of implemented bits and __NVIC_PRIO_BITS will always fail. - * Therefore, this assert is not adding any value for QEMU targets. The config - * option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the - * `FreeRTOSConfig.h` for QEMU targets. */ - #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK - { - #ifdef __NVIC_PRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS ); - } - #endif /* __NVIC_PRIO_BITS */ - - #ifdef configPRIO_BITS - { - /* - * Check that the number of implemented priority bits queried from - * hardware is equal to the FreeRTOS configPRIO_BITS configuration macro. - */ - configASSERT( ulImplementedPrioBits == configPRIO_BITS ); - } - #endif /* configPRIO_BITS */ - } - #endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */ - /* Shift the priority group value back to its position within the AIRCR * register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; From fad6fc8d1792df7c0f5a676f1177b4fdf75c2423 Mon Sep 17 00:00:00 2001 From: Ching-Hsin Lee Date: Thu, 1 Jun 2023 14:08:25 +0800 Subject: [PATCH 4/4] Update comment --- portable/ARMv8M/non_secure/port.c | 7 ++----- portable/CCS/ARM_CM3/port.c | 7 ++----- portable/CCS/ARM_CM4F/port.c | 7 ++----- portable/GCC/ARM_CM23/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM23_NTZ/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM3/port.c | 7 ++----- portable/GCC/ARM_CM33/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM33_NTZ/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM35P/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM35P_NTZ/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM3_MPU/port.c | 7 ++----- portable/GCC/ARM_CM4F/port.c | 7 ++----- portable/GCC/ARM_CM4_MPU/port.c | 7 ++----- portable/GCC/ARM_CM55/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM55_NTZ/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM7/r0p1/port.c | 7 ++----- portable/GCC/ARM_CM85/non_secure/port.c | 7 ++----- portable/GCC/ARM_CM85_NTZ/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM23/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM23_NTZ/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM3/port.c | 7 ++----- portable/IAR/ARM_CM33/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM33_NTZ/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM35P/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM35P_NTZ/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM4F/port.c | 7 ++----- portable/IAR/ARM_CM4F_MPU/port.c | 7 ++----- portable/IAR/ARM_CM55/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM55_NTZ/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM7/r0p1/port.c | 7 ++----- portable/IAR/ARM_CM85/non_secure/port.c | 7 ++----- portable/IAR/ARM_CM85_NTZ/non_secure/port.c | 7 ++----- portable/MikroC/ARM_CM4F/port.c | 7 ++----- portable/RVDS/ARM_CM3/port.c | 7 ++----- portable/RVDS/ARM_CM4F/port.c | 7 ++----- portable/RVDS/ARM_CM4_MPU/port.c | 7 ++----- portable/RVDS/ARM_CM7/r0p1/port.c | 7 ++----- 37 files changed, 74 insertions(+), 185 deletions(-) diff --git a/portable/ARMv8M/non_secure/port.c b/portable/ARMv8M/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/ARMv8M/non_secure/port.c +++ b/portable/ARMv8M/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/CCS/ARM_CM3/port.c b/portable/CCS/ARM_CM3/port.c index 75ae9155d8f..a04efc9115a 100755 --- a/portable/CCS/ARM_CM3/port.c +++ b/portable/CCS/ARM_CM3/port.c @@ -249,11 +249,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/CCS/ARM_CM4F/port.c b/portable/CCS/ARM_CM4F/port.c index 7021689e0ec..1aff18b584a 100755 --- a/portable/CCS/ARM_CM4F/port.c +++ b/portable/CCS/ARM_CM4F/port.c @@ -268,11 +268,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM23/non_secure/port.c b/portable/GCC/ARM_CM23/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM23/non_secure/port.c +++ b/portable/GCC/ARM_CM23/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM23_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM3/port.c b/portable/GCC/ARM_CM3/port.c index 7af43f41e07..198793bd52b 100755 --- a/portable/GCC/ARM_CM3/port.c +++ b/portable/GCC/ARM_CM3/port.c @@ -292,11 +292,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM33/non_secure/port.c b/portable/GCC/ARM_CM33/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM33/non_secure/port.c +++ b/portable/GCC/ARM_CM33/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM33_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM35P/non_secure/port.c b/portable/GCC/ARM_CM35P/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM35P/non_secure/port.c +++ b/portable/GCC/ARM_CM35P/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM3_MPU/port.c b/portable/GCC/ARM_CM3_MPU/port.c index 3ba55eeef62..e9e4b57723f 100755 --- a/portable/GCC/ARM_CM3_MPU/port.c +++ b/portable/GCC/ARM_CM3_MPU/port.c @@ -415,11 +415,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM4F/port.c b/portable/GCC/ARM_CM4F/port.c index 9ed0afe30de..c59995f1a27 100755 --- a/portable/GCC/ARM_CM4F/port.c +++ b/portable/GCC/ARM_CM4F/port.c @@ -335,11 +335,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM4_MPU/port.c b/portable/GCC/ARM_CM4_MPU/port.c index bc5cd959b9d..17b3aa93486 100755 --- a/portable/GCC/ARM_CM4_MPU/port.c +++ b/portable/GCC/ARM_CM4_MPU/port.c @@ -458,11 +458,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM55/non_secure/port.c b/portable/GCC/ARM_CM55/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM55/non_secure/port.c +++ b/portable/GCC/ARM_CM55/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM55_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM7/r0p1/port.c b/portable/GCC/ARM_CM7/r0p1/port.c index 8c9ba1141ee..0fcbf5048ff 100755 --- a/portable/GCC/ARM_CM7/r0p1/port.c +++ b/portable/GCC/ARM_CM7/r0p1/port.c @@ -323,11 +323,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM85/non_secure/port.c b/portable/GCC/ARM_CM85/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM85/non_secure/port.c +++ b/portable/GCC/ARM_CM85/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/GCC/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/GCC/ARM_CM85_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM23/non_secure/port.c b/portable/IAR/ARM_CM23/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM23/non_secure/port.c +++ b/portable/IAR/ARM_CM23/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM23_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM23_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM3/port.c b/portable/IAR/ARM_CM3/port.c index 3194104136d..21b69bdd04a 100755 --- a/portable/IAR/ARM_CM3/port.c +++ b/portable/IAR/ARM_CM3/port.c @@ -241,11 +241,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM33/non_secure/port.c b/portable/IAR/ARM_CM33/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM33/non_secure/port.c +++ b/portable/IAR/ARM_CM33/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM33_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM33_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM35P/non_secure/port.c b/portable/IAR/ARM_CM35P/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM35P/non_secure/port.c +++ b/portable/IAR/ARM_CM35P/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM4F/port.c b/portable/IAR/ARM_CM4F/port.c index cb09de280b7..0352fc3bdb4 100755 --- a/portable/IAR/ARM_CM4F/port.c +++ b/portable/IAR/ARM_CM4F/port.c @@ -279,11 +279,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM4F_MPU/port.c b/portable/IAR/ARM_CM4F_MPU/port.c index 02fc594faf6..742518be5bf 100755 --- a/portable/IAR/ARM_CM4F_MPU/port.c +++ b/portable/IAR/ARM_CM4F_MPU/port.c @@ -393,11 +393,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM55/non_secure/port.c b/portable/IAR/ARM_CM55/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM55/non_secure/port.c +++ b/portable/IAR/ARM_CM55/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM55_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM55_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM7/r0p1/port.c b/portable/IAR/ARM_CM7/r0p1/port.c index 75954a6e3a9..3baf38aaaed 100755 --- a/portable/IAR/ARM_CM7/r0p1/port.c +++ b/portable/IAR/ARM_CM7/r0p1/port.c @@ -267,11 +267,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM85/non_secure/port.c b/portable/IAR/ARM_CM85/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM85/non_secure/port.c +++ b/portable/IAR/ARM_CM85/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c index 0f9b7337d64..dbbb99507ef 100644 --- a/portable/IAR/ARM_CM85_NTZ/non_secure/port.c +++ b/portable/IAR/ARM_CM85_NTZ/non_secure/port.c @@ -1128,11 +1128,8 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */ * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/MikroC/ARM_CM4F/port.c b/portable/MikroC/ARM_CM4F/port.c index ea76b04840c..2fef250a1c8 100755 --- a/portable/MikroC/ARM_CM4F/port.c +++ b/portable/MikroC/ARM_CM4F/port.c @@ -329,11 +329,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/RVDS/ARM_CM3/port.c b/portable/RVDS/ARM_CM3/port.c index fc1d48c3745..054ab02eedc 100755 --- a/portable/RVDS/ARM_CM3/port.c +++ b/portable/RVDS/ARM_CM3/port.c @@ -294,11 +294,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/RVDS/ARM_CM4F/port.c b/portable/RVDS/ARM_CM4F/port.c index 5649cba7e37..de48443bbe8 100755 --- a/portable/RVDS/ARM_CM4F/port.c +++ b/portable/RVDS/ARM_CM4F/port.c @@ -360,11 +360,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/RVDS/ARM_CM4_MPU/port.c b/portable/RVDS/ARM_CM4_MPU/port.c index c3ff75e97f9..fdf1ff95b02 100755 --- a/portable/RVDS/ARM_CM4_MPU/port.c +++ b/portable/RVDS/ARM_CM4_MPU/port.c @@ -453,11 +453,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number diff --git a/portable/RVDS/ARM_CM7/r0p1/port.c b/portable/RVDS/ARM_CM7/r0p1/port.c index a3323a7d1eb..ad9971c8d82 100755 --- a/portable/RVDS/ARM_CM7/r0p1/port.c +++ b/portable/RVDS/ARM_CM7/r0p1/port.c @@ -344,11 +344,8 @@ BaseType_t xPortStartScheduler( void ) * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */ configASSERT( ucMaxSysCallPriority ); - /* Check if the bits hardware does not implement are zero in configMAX_SYSCALL_INTERRUPT_PRIORITY. - * Assertion here helps inform that the configuration is not set to hardware - * as expected, although hardware ignores these bits. Possible reason here is - * that __NVIC_PRIO_BITS or configPRIO_BITS is set greater than hardware - * implemented bits. */ + /* Check that the bits not implemented bits in hardware are zero in + * configMAX_SYSCALL_INTERRUPT_PRIORITY. */ configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U ); /* Calculate the maximum acceptable priority group value for the number