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kmitropoulouKonstantina Mitropoulou
kmitropoulou
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Konstantina Mitropoulou
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[AMDGPU] Emit S_CBRANCH_SCC for floating-point conditions. (llvm#120588)
- **[AMDGPU] Add new test.** - **[AMDGPU] Emit S_CBRANCH_SCC for floating-point conditions.** --------- Co-authored-by: Konstantina Mitropoulou <[email protected]>
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lines changed

3 files changed

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‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

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@@ -2394,6 +2394,9 @@ bool AMDGPUDAGToDAGISel::isCBranchSCC(const SDNode *N) const {
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Subtarget->hasScalarCompareEq64();
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}
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if ((VT == MVT::f16 || VT == MVT::f32) && Subtarget->hasSALUFloatInsts())
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return true;
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return false;
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}
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‎llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -297,10 +297,7 @@ define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(ptr
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; GFX12-NEXT: s_load_b32 s0, s[4:5], 0x2c
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_cmp_eq_f32 s0, 0
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; GFX12-NEXT: s_cselect_b32 s1, -1, 0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: s_and_b32 vcc_lo, exec_lo, s1
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; GFX12-NEXT: s_cbranch_vccz .LBB2_1
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; GFX12-NEXT: s_cbranch_scc0 .LBB2_1
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; GFX12-NEXT: ; %bb.3: ; %bb0
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; GFX12-NEXT: s_getpc_b64 s[2:3]
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; GFX12-NEXT: .Lpost_getpc2:

‎llvm/test/CodeGen/AMDGPU/uniform_branch_with_floating_point_cond.ll

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -stop-after=amdgpu-isel < %s | FileCheck %s
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@external_constant1 = external addrspace(4) constant float, align 4
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@external_constant2 = external addrspace(1) constant float, align 4
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@const.ptr = external addrspace(4) constant ptr, align 4
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define void @test() {
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; CHECK-LABEL: name: test
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x30000000), %bb.3(0x50000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant1, target-flags(amdgpu-gotprel32-hi) @external_constant1, implicit-def dead $scc
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; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
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; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[S_LOAD_DWORDX2_IMM]], 0, 0 :: (dereferenceable invariant load (s32) from @external_constant1, addrspace 4)
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: nofpexcept S_CMP_LG_F32 killed [[S_LOAD_DWORD_IMM]], killed [[S_MOV_B32_]], implicit-def $scc, implicit $mode
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc
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; CHECK-NEXT: S_BRANCH %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.bb1:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET1:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @const.ptr, target-flags(amdgpu-gotprel32-hi) @const.ptr, implicit-def dead $scc
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; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET1]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
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; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM killed [[S_LOAD_DWORDX2_IMM1]], 0, 0 :: (invariant load (s64) from @const.ptr, addrspace 4)
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR killed [[S_LOAD_DWORDX2_IMM2]], killed [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load (s32) from %ir.0, addrspace 1)
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; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sgpr_32 = S_MOV_B32 1092616192
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; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sgpr_32 = S_MOV_B32 1065353216
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[GLOBAL_LOAD_DWORD_SADDR]]
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; CHECK-NEXT: nofpexcept S_CMP_LT_F32 killed [[COPY]], killed [[S_MOV_B32_2]], implicit-def $scc, implicit $mode
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.4, implicit $scc
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.bb2:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: S_BRANCH %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.Flow1:
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; CHECK-NEXT: successors: %bb.7(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_BRANCH %bb.7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4.bb3:
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; CHECK-NEXT: successors: %bb.5(0x50000000), %bb.6(0x30000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:sgpr_32 = PHI [[S_MOV_B32_1]], %bb.1, [[S_MOV_B32_3]], %bb.2
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; CHECK-NEXT: [[S_MOV_B32_4:%[0-9]+]]:sgpr_32 = S_MOV_B32 0
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; CHECK-NEXT: nofpexcept S_CMP_NEQ_F32 [[PHI]], killed [[S_MOV_B32_4]], implicit-def $scc, implicit $mode
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.6, implicit $scc
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; CHECK-NEXT: S_BRANCH %bb.5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5.bb4:
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; CHECK-NEXT: successors: %bb.6(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_PC_ADD_REL_OFFSET2:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant2, target-flags(amdgpu-gotprel32-hi) @external_constant2, implicit-def dead $scc
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; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM3:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM killed [[SI_PC_ADD_REL_OFFSET2]], 0, 0 :: (dereferenceable invariant load (s64) from got, addrspace 4)
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; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec
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; CHECK-NEXT: GLOBAL_STORE_DWORD_SADDR killed [[V_MOV_B32_e32_1]], killed [[V_MOV_B32_e32_2]], killed [[S_LOAD_DWORDX2_IMM3]], 0, 0, implicit $exec :: (store (s32) into @external_constant2, addrspace 1)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6.Flow:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7.bb5:
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; CHECK-NEXT: SI_RETURN
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entry:
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%ld1 = load float, ptr addrspace(4) @external_constant1
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%cmp1 = fcmp one float %ld1, 0.0
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br i1 %cmp1, label %bb5, label %bb1, !amdgpu.uniform !0
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bb1:
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%ptr = load ptr, ptr addrspace(4) @const.ptr
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%ld2 = load float, ptr %ptr, align 4
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%cmp2 = fcmp olt float %ld2, 1.0
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%or = or i1 %cmp2, false
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br i1 %or, label %bb3, label %bb2, !amdgpu.uniform !0
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bb2:
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br label %bb3
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bb3:
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%phi = phi float [ 10.0, %bb1 ], [ 0.0, %bb2 ]
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%cmp3 = fcmp oeq float %phi, 0.0
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br i1 %cmp3, label %bb4, label %bb5, !amdgpu.uniform !0
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bb4:
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store float 4.0, ptr addrspace(1) @external_constant2
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br label %bb5
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bb5:
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ret void
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}
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!0 = !{}

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