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[CPUID] Add ISA entries for A64FX and M1 (#44194)
* [CPUID] Rework how current ISA is determined * [CPUID] Add ISA entry for A64FX * [CPUID] Add ISA entry for Apple Silicon M1 * [CPUID] Simplify collection of full set of features for architecture * [CPUID] Remove AES from A64FX ISA, not all chips appear to have it
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3 files changed

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base/Base.jl

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -276,9 +276,6 @@ include("weakkeydict.jl")
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include("env.jl")
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# BinaryPlatforms, used by Artifacts
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include("binaryplatforms.jl")
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# functions defined in Random
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function rand end
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function randn end
@@ -336,6 +333,9 @@ using .Order
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include("sort.jl")
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using .Sort
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# BinaryPlatforms, used by Artifacts. Needs `Sort`.
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include("binaryplatforms.jl")
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# Fast math
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include("fastmath.jl")
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using .FastMath

base/binaryplatforms.jl

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -608,7 +608,8 @@ const arch_march_isa_mapping = let
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"armv8_0" => get_set("aarch64", "armv8.0-a"),
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"armv8_1" => get_set("aarch64", "armv8.1-a"),
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"armv8_2_crypto" => get_set("aarch64", "armv8.2-a+crypto"),
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"armv8_4_crypto_sve" => get_set("aarch64", "armv8.4-a+crypto+sve"),
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"a64fx" => get_set("aarch64", "a64fx"),
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"apple_m1" => get_set("aarch64", "apple_m1"),
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],
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"powerpc64le" => [
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"power8" => get_set("powerpc64le", "power8"),

base/cpuid.jl

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,10 @@ const ISAs_by_family = Dict(
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"aarch64" => [
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# Implicit in all sets, because always required: fp, asimd
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"armv8.0-a" => ISA(Set{UInt32}()),
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"armv8.1-a" => ISA(Set((JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))),
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"armv8.2-a+crypto" => ISA(Set((JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))),
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"armv8.4-a+crypto+sve" => ISA(Set((JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_fp16fml, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_dotprod, JL_AArch64_sve))),
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"armv8.1-a" => ISA(Set((JL_AArch64_v8_1a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm))),
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"armv8.2-a+crypto" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2))),
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"a64fx" => ISA(Set((JL_AArch64_v8_2a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_sha2, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fullfp16, JL_AArch64_sve))),
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"apple_m1" => ISA(Set((JL_AArch64_v8_5a, JL_AArch64_lse, JL_AArch64_crc, JL_AArch64_rdm, JL_AArch64_aes, JL_AArch64_sha2, JL_AArch64_sha3, JL_AArch64_ccpp, JL_AArch64_complxnum, JL_AArch64_fp16fml, JL_AArch64_fullfp16, JL_AArch64_dotprod, JL_AArch64_rcpc, JL_AArch64_altnzcv))),
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],
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"powerpc64le" => [
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# We have no way to test powerpc64le features yet, so we're only going to declare the lowest ISA:
@@ -88,14 +89,27 @@ function normalize_arch(arch::String)
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return arch
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end
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let
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# Collect all relevant features for the current architecture, if any.
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FEATURES = UInt32[]
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arch = normalize_arch(String(Sys.ARCH))
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if arch in keys(ISAs_by_family)
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for isa in ISAs_by_family[arch]
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unique!(append!(FEATURES, last(isa).features))
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end
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end
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# Use `@eval` to inline the list of features.
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@eval function cpu_isa()
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return ISA(Set{UInt32}(feat for feat in $(FEATURES) if test_cpu_feature(feat)))
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end
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end
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"""
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cpu_isa()
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Return the [`ISA`](@ref) (instruction set architecture) of the current CPU.
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"""
96-
function cpu_isa()
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all_features = last(last(get(ISAs_by_family, normalize_arch(String(Sys.ARCH)), "" => [ISA(Set{UInt32}())]))).features
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return ISA(Set{UInt32}(feat for feat in all_features if test_cpu_feature(feat)))
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end
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cpu_isa
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end # module CPUID

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