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52 | 52 | input RST
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53 | 53 | );
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54 | 54 |
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55 |
| - reg [14-1:0] myram_0_addr; |
| 55 | + wire [14-1:0] myram_0_addr; |
56 | 56 | wire [32-1:0] myram_0_rdata;
|
57 |
| - reg [32-1:0] myram_0_wdata; |
58 |
| - reg myram_0_wenable; |
| 57 | + wire [32-1:0] myram_0_wdata; |
| 58 | + wire myram_0_wenable; |
| 59 | + wire myram_0_enable; |
59 | 60 |
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60 | 61 | myram
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61 | 62 | inst_myram
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64 | 65 | .myram_0_addr(myram_0_addr),
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65 | 66 | .myram_0_rdata(myram_0_rdata),
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66 | 67 | .myram_0_wdata(myram_0_wdata),
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67 |
| - .myram_0_wenable(myram_0_wenable) |
| 68 | + .myram_0_wenable(myram_0_wenable), |
| 69 | + .myram_0_enable(myram_0_enable) |
68 | 70 | );
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69 | 71 |
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70 | 72 | reg [32-1:0] count;
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71 | 73 | reg [32-1:0] sum;
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72 | 74 | reg [32-1:0] addr;
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73 | 75 | reg [32-1:0] fsm;
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74 | 76 | localparam fsm_init = 0;
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75 |
| - reg _myram_cond_0_1; |
76 |
| - reg _tmp_0; |
77 |
| - reg _myram_cond_1_1; |
78 |
| - reg _myram_cond_2_1; |
79 |
| - reg _myram_cond_2_2; |
| 77 | + assign myram_0_wdata = (fsm == 1)? count : 'hx; |
| 78 | + assign myram_0_wenable = (fsm == 1)? 1'd1 : 0; |
| 79 | + assign myram_0_addr = (fsm == 2)? addr : |
| 80 | + (fsm == 1)? addr : 'hx; |
| 81 | + assign myram_0_enable = (fsm == 2)? 1'd1 : |
| 82 | + (fsm == 1)? 1'd1 : 0; |
| 83 | + localparam _tmp_0 = 1; |
| 84 | + wire [_tmp_0-1:0] _tmp_1; |
| 85 | + assign _tmp_1 = fsm == 2; |
| 86 | + reg [_tmp_0-1:0] __tmp_1_1; |
80 | 87 | reg [32-1:0] _d1_fsm;
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81 | 88 | reg _fsm_cond_2_0_1;
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82 | 89 | reg _fsm_cond_3_1_1;
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83 | 90 | localparam fsm_1 = 1;
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84 | 91 | localparam fsm_2 = 2;
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85 | 92 | localparam fsm_3 = 3;
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| 93 | + localparam fsm_4 = 4; |
| 94 | + localparam fsm_5 = 5; |
86 | 95 |
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87 | 96 | always @(posedge CLK) begin
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88 | 97 | if(RST) begin
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|
128 | 137 | fsm_2: begin
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129 | 138 | addr <= addr + 1;
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130 | 139 | count <= count + 1;
|
131 |
| - if(_tmp_0) begin |
| 140 | + if(__tmp_1_1) begin |
132 | 141 | sum <= sum + myram_0_rdata;
|
133 | 142 | end
|
134 |
| - _fsm_cond_2_0_1 <= _tmp_0; |
| 143 | + _fsm_cond_2_0_1 <= __tmp_1_1; |
135 | 144 | if(count == 15) begin
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136 | 145 | addr <= 0;
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137 | 146 | count <= 0;
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|
141 | 150 | end
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142 | 151 | end
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143 | 152 | fsm_3: begin
|
144 |
| - if(_tmp_0) begin |
| 153 | + if(__tmp_1_1) begin |
145 | 154 | sum <= sum + myram_0_rdata;
|
146 | 155 | end
|
147 |
| - _fsm_cond_3_1_1 <= _tmp_0; |
| 156 | + _fsm_cond_3_1_1 <= __tmp_1_1; |
| 157 | + fsm <= fsm_4; |
| 158 | + end |
| 159 | + fsm_4: begin |
| 160 | + $display("expected_sum=%d", 120); |
| 161 | + fsm <= fsm_5; |
148 | 162 | end
|
149 | 163 | endcase
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150 | 164 | end
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|
153 | 167 |
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154 | 168 | always @(posedge CLK) begin
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155 | 169 | if(RST) begin
|
156 |
| - myram_0_addr <= 0; |
157 |
| - myram_0_wdata <= 0; |
158 |
| - myram_0_wenable <= 0; |
159 |
| - _myram_cond_0_1 <= 0; |
160 |
| - _myram_cond_1_1 <= 0; |
161 |
| - _tmp_0 <= 0; |
162 |
| - _myram_cond_2_1 <= 0; |
163 |
| - _myram_cond_2_2 <= 0; |
| 170 | + __tmp_1_1 <= 0; |
164 | 171 | end else begin
|
165 |
| - if(_myram_cond_2_2) begin |
166 |
| - _tmp_0 <= 0; |
167 |
| - end |
168 |
| - if(_myram_cond_0_1) begin |
169 |
| - myram_0_wenable <= 0; |
170 |
| - end |
171 |
| - if(_myram_cond_1_1) begin |
172 |
| - _tmp_0 <= 1; |
173 |
| - end |
174 |
| - _myram_cond_2_2 <= _myram_cond_2_1; |
175 |
| - if(fsm == 1) begin |
176 |
| - myram_0_addr <= addr; |
177 |
| - myram_0_wdata <= count; |
178 |
| - myram_0_wenable <= 1; |
179 |
| - end |
180 |
| - _myram_cond_0_1 <= fsm == 1; |
181 |
| - if(fsm == 2) begin |
182 |
| - myram_0_addr <= addr; |
183 |
| - end |
184 |
| - _myram_cond_1_1 <= fsm == 2; |
185 |
| - _myram_cond_2_1 <= fsm == 2; |
| 172 | + __tmp_1_1 <= _tmp_1; |
186 | 173 | end
|
187 | 174 | end
|
188 | 175 |
|
|
197 | 184 | input [14-1:0] myram_0_addr,
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198 | 185 | output [32-1:0] myram_0_rdata,
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199 | 186 | input [32-1:0] myram_0_wdata,
|
200 |
| - input myram_0_wenable |
| 187 | + input myram_0_wenable, |
| 188 | + input myram_0_enable |
201 | 189 | );
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202 | 190 |
|
203 |
| - reg [14-1:0] myram_0_daddr; |
| 191 | + reg [32-1:0] myram_0_rdata_out; |
| 192 | + assign myram_0_rdata = myram_0_rdata_out; |
204 | 193 | reg [32-1:0] mem [0:16384-1];
|
205 | 194 |
|
206 | 195 | always @(posedge CLK) begin
|
207 |
| - if(myram_0_wenable) begin |
208 |
| - mem[myram_0_addr] <= myram_0_wdata; |
| 196 | + if(myram_0_enable) begin |
| 197 | + if(myram_0_wenable) begin |
| 198 | + mem[myram_0_addr] <= myram_0_wdata; |
| 199 | + myram_0_rdata_out <= myram_0_wdata; |
| 200 | + end else begin |
| 201 | + myram_0_rdata_out <= mem[myram_0_addr]; |
| 202 | + end |
209 | 203 | end
|
210 |
| - myram_0_daddr <= myram_0_addr; |
211 | 204 | end
|
212 | 205 |
|
213 |
| - assign myram_0_rdata = mem[myram_0_daddr]; |
214 | 206 |
|
215 | 207 | endmodule
|
216 | 208 | """
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