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64 | 64 | /* Default value */
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65 | 65 | #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
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66 | 66 |
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67 |
| -/* IMX I2C registers */ |
| 67 | +/* IMX I2C registers: |
| 68 | + * the I2C register offset is different between SoCs, |
| 69 | + * to provid support for all these chips, split the |
| 70 | + * register offset into a fixed base address and a |
| 71 | + * variable shift value, then the full register offset |
| 72 | + * will be calculated by |
| 73 | + * reg_off = ( reg_base_addr << reg_shift) |
| 74 | + */ |
68 | 75 | #define IMX_I2C_IADR 0x00 /* i2c slave address */
|
69 |
| -#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ |
70 |
| -#define IMX_I2C_I2CR 0x08 /* i2c control */ |
71 |
| -#define IMX_I2C_I2SR 0x0C /* i2c status */ |
72 |
| -#define IMX_I2C_I2DR 0x10 /* i2c transfer data */ |
| 76 | +#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ |
| 77 | +#define IMX_I2C_I2CR 0x02 /* i2c control */ |
| 78 | +#define IMX_I2C_I2SR 0x03 /* i2c status */ |
| 79 | +#define IMX_I2C_I2DR 0x04 /* i2c transfer data */ |
| 80 | + |
| 81 | +#define IMX_I2C_REGSHIFT 2 |
73 | 82 |
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74 | 83 | /* Bits of IMX I2C registers */
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75 | 84 | #define I2SR_RXAK 0x01
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@@ -163,13 +172,13 @@ static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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163 | 172 | static inline void imx_i2c_write_reg(unsigned int val,
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164 | 173 | struct imx_i2c_struct *i2c_imx, unsigned int reg)
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165 | 174 | {
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166 |
| - writeb(val, i2c_imx->base + reg); |
| 175 | + writeb(val, i2c_imx->base + (reg << IMX_I2C_REGSHIFT)); |
167 | 176 | }
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168 | 177 |
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169 | 178 | static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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170 | 179 | unsigned int reg)
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171 | 180 | {
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172 |
| - return readb(i2c_imx->base + reg); |
| 181 | + return readb(i2c_imx->base + (reg << IMX_I2C_REGSHIFT)); |
173 | 182 | }
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174 | 183 |
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175 | 184 | /** Functions for IMX I2C adapter driver ***************************************
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