Use LLD for linking and reorganize assembly stages

Author: phil-opp

linker.ld

@@ -28,17 +28,17 @@ SECTIONS {
     .bootloader :
     {
         /* first stage */
-        *(.boot)
+        *(.boot-first-stage)
 
-        /* second stage */
-        _second_stage_start_addr = .;
-        *(.second_stage)
+        /* rest of bootloader */
+        _rest_of_bootloader_start_addr = .;
+        *(.boot)
         *(.context_switch)
         *(.text .text.*)
         *(.rodata .rodata.*)
         *(.data .data.*)
         . = ALIGN(512);
-        _second_stage_end_addr = .;
+        _rest_of_bootloader_end_addr = .;
     }
 
     _kernel_info_block_start = .;

src/memory_map.s renamed to src/e820.s

@@ -1,4 +1,4 @@
-.section .second_stage, "awx"
+.section .boot, "awx"
 .intel_syntax noprefix
 .code16
 

src/main.rs

@@ -25,9 +25,11 @@ use x86_64::ux::u9;
 pub use x86_64::PhysAddr;
 use x86_64::VirtAddr;
 
-global_asm!(include_str!("boot.s"));
-global_asm!(include_str!("second_stage.s"));
-global_asm!(include_str!("memory_map.s"));
+global_asm!(include_str!("stage_1.s"));
+global_asm!(include_str!("stage_2.s"));
+global_asm!(include_str!("e820.s"));
+global_asm!(include_str!("stage_3.s"));
+global_asm!(include_str!("stage_4.s"));
 global_asm!(include_str!("context_switch.s"));
 
 extern "C" {

src/boot.s renamed to src/stage_1.s

@@ -1,4 +1,4 @@
-.section .boot, "awx"
+.section .boot-first-stage, "awx"
 .global _start
 .intel_syntax noprefix
 .code16
@@ -16,7 +16,6 @@ _start:
     # instructions like lodsb)
     cld
 
-
     # initialize stack
     mov sp, 0x7c00
 
@@ -70,15 +69,15 @@ check_int13h_extensions:
     int 0x13
     jc no_int13h_extensions
 
-load_second_stage_from_disk:
-    lea eax, _second_stage_start_addr
+load_rest_of_bootloader_from_disk:
+    lea eax, _rest_of_bootloader_start_addr
 
     # start of memory buffer
     mov [dap_buffer_addr], ax
 
     # number of disk blocks to load
     lea ebx, _kernel_info_block_end
-    sub ebx, eax # second stage end - second stage start
+    sub ebx, eax # end - start
     shr ebx, 9 # divide by 512 (block size)
     mov [dap_blocks], bx
 
@@ -91,10 +90,10 @@ load_second_stage_from_disk:
     lea si, dap
     mov ah, 0x42
     int 0x13
-    jc second_stage_load_failed
+    jc rest_of_bootloader_load_failed
 
 jump_to_second_stage:
-    lea eax, second_stage
+    lea eax, [stage_2]
     jmp eax
 
 spin:
@@ -174,20 +173,15 @@ no_int13h_extensions:
     lea si, no_int13h_extensions_str
     jmp error
 
-second_stage_load_failed:
-    lea si, second_stage_load_failed_str
-    jmp error
-
-kernel_load_failed:
-    lea si, kernel_load_failed_str
+rest_of_bootloader_load_failed:
+    lea si, rest_of_bootloader_load_failed_str
     jmp error
 
 boot_start_str: .asciz "Booting (first stage)..."
-second_stage_start_str: .asciz "Booting (second stage)..."
 error_str: .asciz "Error: "
 no_cpuid_str: .asciz "No CPUID support"
 no_int13h_extensions_str: .asciz "No support for int13h extensions"
-second_stage_load_failed_str: .asciz "Failed to load second stage of bootloader"
+rest_of_bootloader_load_failed_str: .asciz "Failed to load rest of bootloader"
 
 gdtinfo:
    .word gdt_end - gdt - 1  # last byte in table

src/stage_2.s

@@ -0,0 +1,86 @@
+.section .boot, "awx"
+.intel_syntax noprefix
+.code16
+
+second_stage_start_str: .asciz "Booting (second stage)..."
+loading_kernel_block_str: .asciz "loading kernel block..."
+kernel_load_failed_str: .asciz "Failed to load kernel"
+
+kernel_load_failed:
+jmp kernel_load_failed
+
+stage_2:
+set_target_operating_mode:
+    # Some BIOSs assume the processor will only operate in Legacy Mode. We change the Target
+    # Operating Mode to "Long Mode Target Only", so the firmware expects each CPU to enter Long Mode
+    # once and then stay in it. This allows the firmware to enable mode-specifc optimizations.
+    # We save the flags, because CF is set if the callback is not supported (in which case, this is
+    # a NOP)
+    pushf
+    mov ax, 0xec00
+    mov bl, 0x2
+    int 0x15
+    popf
+
+load_kernel_from_disk:
+    # start of memory buffer
+    lea eax, _kernel_buffer
+    mov [dap_buffer_addr], ax
+
+    # number of disk blocks to load
+    mov word ptr [dap_blocks], 1
+
+    # number of start block
+    lea eax, _kernel_start_addr
+    lea ebx, _start
+    sub eax, ebx
+    shr eax, 9 # divide by 512 (block size)
+    mov [dap_start_lba], eax
+
+    # destination address
+    mov edi, 0x400000
+
+    # block count
+    mov ecx, _kib_kernel_size
+    add ecx, 511 # align up
+    shr ecx, 9
+
+load_next_kernel_block_from_disk:
+    # load block from disk
+    lea si, dap
+    mov ah, 0x42
+    int 0x13
+    jc kernel_load_failed
+
+    # copy block to 2MiB
+    push ecx
+    push esi
+    mov ecx, 512 / 4
+    # move with zero extension
+    # because we are moving a word ptr
+    # to esi, a 32-bit register.
+    movzx esi, word ptr [dap_buffer_addr]
+    # move from esi to edi ecx times.
+    rep movsd [edi], [esi]
+    pop esi
+    pop ecx
+
+    # next block
+    mov eax, [dap_start_lba]
+    add eax, 1
+    mov [dap_start_lba], eax
+
+    sub ecx, 1
+    jnz load_next_kernel_block_from_disk
+
+create_memory_map:
+    lea di, es:[_memory_map]
+    call do_e820
+
+enter_protected_mode_again:
+jmp enter_protected_mode_again
+
+    lea eax, [stage_3]
+    jmp eax
+spin32:
+    jmp spin32

src/second_stage.s renamed to src/stage_3.s

@@ -1,82 +1,10 @@
-.section .second_stage, "awx"
+.section .boot, "awx"
 .intel_syntax noprefix
-.code16
+.code32
 
-loading_kernel_block_str: .asciz "loading kernel block..."
-kernel_load_failed_str: .asciz "Failed to load kernel"
 no_long_mode_str: .asciz "No long mode support"
 
-second_stage:
-    lea si, second_stage_start_str
-    call println
-
-set_target_operating_mode:
-    # Some BIOSs assume the processor will only operate in Legacy Mode. We change the Target
-    # Operating Mode to "Long Mode Target Only", so the firmware expects each CPU to enter Long Mode
-    # once and then stay in it. This allows the firmware to enable mode-specifc optimizations.
-    # We save the flags, because CF is set if the callback is not supported (in which case, this is
-    # a NOP)
-    pushf
-    mov ax, 0xec00
-    mov bl, 0x2
-    int 0x15
-    popf
-
-load_kernel_from_disk:
-    # start of memory buffer
-    lea eax, _kernel_buffer
-    mov [dap_buffer_addr], ax
-
-    # number of disk blocks to load
-    mov word ptr [dap_blocks], 1
-
-    # number of start block
-    lea eax, _kernel_start_addr
-    lea ebx, _start
-    sub eax, ebx
-    shr eax, 9 # divide by 512 (block size)
-    mov [dap_start_lba], eax
-
-    # destination address
-    mov edi, 0x400000
-
-    # block count
-    mov ecx, _kib_kernel_size
-    add ecx, 511 # align up
-    shr ecx, 9
-
-load_next_kernel_block_from_disk:
-    # load block from disk
-    lea si, dap
-    mov ah, 0x42
-    int 0x13
-    jc kernel_load_failed
-
-    # copy block to 2MiB
-    push ecx
-    push esi
-    mov ecx, 512 / 4
-    # move with zero extension
-    # because we are moving a word ptr
-    # to esi, a 32-bit register.
-    movzx esi, word ptr [dap_buffer_addr]
-    # move from esi to edi ecx times.
-    rep movsd [edi], [esi]
-    pop esi
-    pop ecx
-
-    # next block
-    mov eax, [dap_start_lba]
-    add eax, 1
-    mov [dap_start_lba], eax
-
-    sub ecx, 1
-    jnz load_next_kernel_block_from_disk
-
-create_memory_map:
-    lea di, es:[_memory_map]
-    call do_e820
-
+stage_3:
 check_cpu:
     call check_cpuid
     call check_long_mode
@@ -144,7 +72,6 @@ set_up_page_tables:
     shr ecx, 12
     mov [_p1 + ecx * 8], eax
 
-
 enable_paging:
     # load P4 to cr3 register (cpu uses this to access the P4 table)
     lea eax, [_p4]
@@ -171,12 +98,12 @@ load_64bit_gdt:
 
 jump_to_long_mode:
     push 0x8
-    lea eax, [long_mode]
+    lea eax, [stage_4]
     push eax
     retf # Load CS with 64 bit segment and flush the instruction cache
 
-    jmp spin
-
+spin_here:
+    jmp spin_here
 
 check_cpuid:
     # Check if CPUID is supported by attempting to flip the ID bit (bit 21)
@@ -212,7 +139,7 @@ check_cpuid:
     ret
 no_cpuid:
     lea si, no_cpuid_str
-    jmp error
+    jmp no_cpuid
 
 check_long_mode:
     # test if extended processor info in available
@@ -229,7 +156,7 @@ check_long_mode:
     ret
 no_long_mode:
     lea si, no_long_mode_str
-    jmp error
+    jmp no_long_mode
 
 
 .align 4
@@ -248,22 +175,3 @@ gdt_64:
 gdt_64_pointer:
     .word gdt_64_pointer - gdt_64 - 1    # 16-bit Size (Limit) of GDT.
     .long gdt_64                            # 32-bit Base Address of GDT. (CPU will zero extend to 64-bit)
-
-
-.code64
-
-long_mode:
-    # call load_elf with kernel start address, size, and memory map as arguments
-    movabs rdi, 0x400000 # move absolute 64-bit to register
-    mov rsi, _kib_kernel_size
-    lea rdx, _memory_map
-    movzx rcx, word ptr mmap_ent
-    lea r8, __page_table_start
-    lea r9, __page_table_end
-    lea rax, __bootloader_end
-    push rax
-    lea rax, __bootloader_start
-    push rax
-    call load_elf
-spin64:
-    jmp spin64

src/stage_4.s

@@ -0,0 +1,19 @@
+.section .boot, "awx"
+.intel_syntax noprefix
+.code64
+
+stage_4:
+    # call load_elf with kernel start address, size, and memory map as arguments
+    movabs rdi, 0x400000 # move absolute 64-bit to register
+    mov rsi, _kib_kernel_size
+    lea rdx, _memory_map
+    movzx rcx, word ptr mmap_ent
+    lea r8, __page_table_start
+    lea r9, __page_table_end
+    lea rax, __bootloader_end
+    push rax
+    lea rax, __bootloader_start
+    push rax
+    call load_elf
+spin64:
+    jmp spin64

x86_64-bootloader.json

@@ -1,10 +1,10 @@
 {
     "llvm-target": "x86_64-unknown-none-gnu",
     "data-layout": "e-m:e-i64:64-f80:128-n8:16:32:64-S128",
-    "linker-flavor": "ld",
-    "linker": "ld.bfd",
+    "linker-flavor": "ld.lld",
+    "linker": "rust-lld",
     "pre-link-args": {
-        "ld": [
+        "ld.lld": [
 	    "--script=linker.ld"
 	]
     },