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Replaced TbUtilPkg.Create... with ClockResetPkg.Create...
1 parent 9c42dde commit 0baf9b1

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4 files changed

+8
-8
lines changed

4 files changed

+8
-8
lines changed

GHDL_Debug/TbUart.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,15 +98,15 @@ begin
9898

9999
------------------------------------------------------------
100100
-- create Clock
101-
Osvvm.TbUtilPkg.CreateClock (
101+
Osvvm.ClockResetPkg.CreateClock (
102102
------------------------------------------------------------
103103
Clk => Clk,
104104
Period => tperiod_Clk
105105
) ;
106106

107107
------------------------------------------------------------
108108
-- create nReset
109-
Osvvm.TbUtilPkg.CreateReset (
109+
Osvvm.ClockResetPkg.CreateReset (
110110
------------------------------------------------------------
111111
Reset => nReset,
112112
ResetActive => '0',

testbench/TbUart.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,15 +91,15 @@ begin
9191

9292
------------------------------------------------------------
9393
-- create Clock
94-
Osvvm.TbUtilPkg.CreateClock (
94+
Osvvm.ClockResetPkg.CreateClock (
9595
------------------------------------------------------------
9696
Clk => Clk,
9797
Period => tperiod_Clk
9898
) ;
9999

100100
------------------------------------------------------------
101101
-- create nReset
102-
Osvvm.TbUtilPkg.CreateReset (
102+
Osvvm.ClockResetPkg.CreateReset (
103103
------------------------------------------------------------
104104
Reset => nReset,
105105
ResetActive => '0',

testbench_multiple_uarts/TbUart.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,15 +98,15 @@ begin
9898

9999
------------------------------------------------------------
100100
-- create Clock
101-
Osvvm.TbUtilPkg.CreateClock (
101+
Osvvm.ClockResetPkg.CreateClock (
102102
------------------------------------------------------------
103103
Clk => Clk,
104104
Period => tperiod_Clk
105105
) ;
106106

107107
------------------------------------------------------------
108108
-- create nReset
109-
Osvvm.TbUtilPkg.CreateReset (
109+
Osvvm.ClockResetPkg.CreateReset (
110110
------------------------------------------------------------
111111
Reset => nReset,
112112
ResetActive => '0',

testbench_xilinx/TbUart.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -97,15 +97,15 @@ begin
9797

9898
------------------------------------------------------------
9999
-- create Clock
100-
Osvvm.TbUtilPkg.CreateClock (
100+
Osvvm.ClockResetPkg.CreateClock (
101101
------------------------------------------------------------
102102
Clk => Clk,
103103
Period => tperiod_Clk
104104
) ;
105105

106106
------------------------------------------------------------
107107
-- create nReset
108-
Osvvm.TbUtilPkg.CreateReset (
108+
Osvvm.ClockResetPkg.CreateReset (
109109
------------------------------------------------------------
110110
Reset => nReset,
111111
ResetActive => '0',

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