@@ -30,6 +30,7 @@ In the description below, `ImmLaneIdx{I}` indicates the maximum value of the byt
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For example, ` ImmLaneIdx16 ` is a byte with values in the range 0-15 (inclusive).
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+ <<<<<<< HEAD
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| Instruction | ` simdop ` | Immediate operands |
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| --------------------------------| ---------:| --------------------------|
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| ` v128.load ` | ` 0x00 ` | m: memarg |
@@ -262,4 +263,232 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
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| ` i16x8.extadd_pairwise_i8x16_s ` | ` TBD ` | - |
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| ` i16x8.extadd_pairwise_i8x16_u ` | ` TBD ` | - |
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| ` i32x4.extadd_pairwise_i16x8_s ` | ` TBD ` | - |
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- | ` i32x4.extadd_pairwise_i16x8_u ` | ` TBD ` | - |
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+ | ` i32x4.extadd_pairwise_i16x8_u ` | ` TBD ` | - |
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+ =======
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+ | Instruction | ` simdop ` | Immediate operands |
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+ | ----------------------------| ---------:| --------------------------|
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+ | ` v128.load ` | ` 0x00 ` | m: memarg |
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+ | ` v128.load8x8_s ` | ` 0x01 ` | m: memarg |
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+ | ` v128.load8x8_u ` | ` 0x02 ` | m: memarg |
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+ | ` v128.load16x4_s ` | ` 0x03 ` | m: memarg |
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+ | ` v128.load16x4_u ` | ` 0x04 ` | m: memarg |
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+ | ` v128.load32x2_s ` | ` 0x05 ` | m: memarg |
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+ | ` v128.load32x2_u ` | ` 0x06 ` | m: memarg |
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+ | ` v128.load8_splat ` | ` 0x07 ` | m: memarg |
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+ | ` v128.load16_splat ` | ` 0x08 ` | m: memarg |
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+ | ` v128.load32_splat ` | ` 0x09 ` | m: memarg |
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+ | ` v128.load64_splat ` | ` 0x0a ` | m: memarg |
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+ | ` v128.store ` | ` 0x0b ` | m: memarg |
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+ | ` v128.const ` | ` 0x0c ` | i: ImmByte [ 16] |
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+ | ` i8x16.shuffle ` | ` 0x0d ` | s: ImmLaneIdx32 [ 16] |
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+ | ` i8x16.swizzle ` | ` 0x0e ` | - |
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+ | ` i8x16.splat ` | ` 0x0f ` | - |
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+ | ` i16x8.splat ` | ` 0x10 ` | - |
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+ | ` i32x4.splat ` | ` 0x11 ` | - |
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+ | ` i64x2.splat ` | ` 0x12 ` | - |
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+ | ` f32x4.splat ` | ` 0x13 ` | - |
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+ | ` f64x2.splat ` | ` 0x14 ` | - |
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+ | ` i8x16.extract_lane_s ` | ` 0x15 ` | i: ImmLaneIdx16 |
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+ | ` i8x16.extract_lane_u ` | ` 0x16 ` | i: ImmLaneIdx16 |
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+ | ` i8x16.replace_lane ` | ` 0x17 ` | i: ImmLaneIdx16 |
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+ | ` i16x8.extract_lane_s ` | ` 0x18 ` | i: ImmLaneIdx8 |
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+ | ` i16x8.extract_lane_u ` | ` 0x19 ` | i: ImmLaneIdx8 |
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+ | ` i16x8.replace_lane ` | ` 0x1a ` | i: ImmLaneIdx8 |
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+ | ` i32x4.extract_lane ` | ` 0x1b ` | i: ImmLaneIdx4 |
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+ | ` i32x4.replace_lane ` | ` 0x1c ` | i: ImmLaneIdx4 |
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+ | ` i64x2.extract_lane ` | ` 0x1d ` | i: ImmLaneIdx2 |
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+ | ` i64x2.replace_lane ` | ` 0x1e ` | i: ImmLaneIdx2 |
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+ | ` f32x4.extract_lane ` | ` 0x1f ` | i: ImmLaneIdx4 |
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+ | ` f32x4.replace_lane ` | ` 0x20 ` | i: ImmLaneIdx4 |
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+ | ` f64x2.extract_lane ` | ` 0x21 ` | i: ImmLaneIdx2 |
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+ | ` f64x2.replace_lane ` | ` 0x22 ` | i: ImmLaneIdx2 |
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+ | ` i8x16.eq ` | ` 0x23 ` | - |
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+ | ` i8x16.ne ` | ` 0x24 ` | - |
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+ | ` i8x16.lt_s ` | ` 0x25 ` | - |
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+ | ` i8x16.lt_u ` | ` 0x26 ` | - |
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+ | ` i8x16.gt_s ` | ` 0x27 ` | - |
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+ | ` i8x16.gt_u ` | ` 0x28 ` | - |
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+ | ` i8x16.le_s ` | ` 0x29 ` | - |
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+ | ` i8x16.le_u ` | ` 0x2a ` | - |
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+ | ` i8x16.ge_s ` | ` 0x2b ` | - |
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+ | ` i8x16.ge_u ` | ` 0x2c ` | - |
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+ | ` i16x8.eq ` | ` 0x2d ` | - |
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+ | ` i16x8.ne ` | ` 0x2e ` | - |
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+ | ` i16x8.lt_s ` | ` 0x2f ` | - |
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+ | ` i16x8.lt_u ` | ` 0x30 ` | - |
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+ | ` i16x8.gt_s ` | ` 0x31 ` | - |
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+ | ` i16x8.gt_u ` | ` 0x32 ` | - |
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+ | ` i16x8.le_s ` | ` 0x33 ` | - |
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+ | ` i16x8.le_u ` | ` 0x34 ` | - |
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+ | ` i16x8.ge_s ` | ` 0x35 ` | - |
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+ | ` i16x8.ge_u ` | ` 0x36 ` | - |
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+ | ` i32x4.eq ` | ` 0x37 ` | - |
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+ | ` i32x4.ne ` | ` 0x38 ` | - |
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+ | ` i32x4.lt_s ` | ` 0x39 ` | - |
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+ | ` i32x4.lt_u ` | ` 0x3a ` | - |
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+ | ` i32x4.gt_s ` | ` 0x3b ` | - |
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+ | ` i32x4.gt_u ` | ` 0x3c ` | - |
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+ | ` i32x4.le_s ` | ` 0x3d ` | - |
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+ | ` i32x4.le_u ` | ` 0x3e ` | - |
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+ | ` i32x4.ge_s ` | ` 0x3f ` | - |
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+ | ` i32x4.ge_u ` | ` 0x40 ` | - |
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+ | ` f32x4.eq ` | ` 0x41 ` | - |
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+ | ` f32x4.ne ` | ` 0x42 ` | - |
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+ | ` f32x4.lt ` | ` 0x43 ` | - |
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+ | ` f32x4.gt ` | ` 0x44 ` | - |
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+ | ` f32x4.le ` | ` 0x45 ` | - |
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+ | ` f32x4.ge ` | ` 0x46 ` | - |
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+ | ` f64x2.eq ` | ` 0x47 ` | - |
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+ | ` f64x2.ne ` | ` 0x48 ` | - |
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+ | ` f64x2.lt ` | ` 0x49 ` | - |
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+ | ` f64x2.gt ` | ` 0x4a ` | - |
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+ | ` f64x2.le ` | ` 0x4b ` | - |
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+ | ` f64x2.ge ` | ` 0x4c ` | - |
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+ | ` v128.not ` | ` 0x4d ` | - |
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+ | ` v128.and ` | ` 0x4e ` | - |
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+ | ` v128.andnot ` | ` 0x4f ` | - |
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+ | ` v128.or ` | ` 0x50 ` | - |
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+ | ` v128.xor ` | ` 0x51 ` | - |
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+ | ` v128.bitselect ` | ` 0x52 ` | - |
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+ | ` i8x16.abs ` | ` 0x60 ` | - |
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+ | ` i8x16.neg ` | ` 0x61 ` | - |
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+ | ` i8x16.all_true ` | ` 0x63 ` | - |
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+ | ` i8x16.bitmask ` | ` 0x64 ` | - |
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+ | ` i8x16.narrow_i16x8_s ` | ` 0x65 ` | - |
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+ | ` i8x16.narrow_i16x8_u ` | ` 0x66 ` | - |
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+ | ` i8x16.shl ` | ` 0x6b ` | - |
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+ | ` i8x16.shr_s ` | ` 0x6c ` | - |
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+ | ` i8x16.shr_u ` | ` 0x6d ` | - |
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+ | ` i8x16.add ` | ` 0x6e ` | - |
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+ | ` i8x16.add_sat_s ` | ` 0x6f ` | - |
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+ | ` i8x16.add_sat_u ` | ` 0x70 ` | - |
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+ | ` i8x16.sub ` | ` 0x71 ` | - |
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+ | ` i8x16.sub_sat_s ` | ` 0x72 ` | - |
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+ | ` i8x16.sub_sat_u ` | ` 0x73 ` | - |
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+ | ` i8x16.min_s ` | ` 0x76 ` | - |
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+ | ` i8x16.min_u ` | ` 0x77 ` | - |
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+ | ` i8x16.max_s ` | ` 0x78 ` | - |
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+ | ` i8x16.max_u ` | ` 0x79 ` | - |
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+ | ` i8x16.avgr_u ` | ` 0x7b ` | - |
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+ | ` i16x8.abs ` | ` 0x80 ` | - |
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+ | ` i16x8.neg ` | ` 0x81 ` | - |
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+ | ` i16x8.all_true ` | ` 0x83 ` | - |
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+ | ` i16x8.bitmask ` | ` 0x84 ` | - |
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+ | ` i16x8.narrow_i32x4_s ` | ` 0x85 ` | - |
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+ | ` i16x8.narrow_i32x4_u ` | ` 0x86 ` | - |
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+ | ` i16x8.widen_low_i8x16_s ` | ` 0x87 ` | - |
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+ | ` i16x8.widen_high_i8x16_s ` | ` 0x88 ` | - |
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+ | ` i16x8.widen_low_i8x16_u ` | ` 0x89 ` | - |
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+ | ` i16x8.widen_high_i8x16_u ` | ` 0x8a ` | - |
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+ | ` i16x8.shl ` | ` 0x8b ` | - |
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+ | ` i16x8.shr_s ` | ` 0x8c ` | - |
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+ | ` i16x8.shr_u ` | ` 0x8d ` | - |
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+ | ` i16x8.add ` | ` 0x8e ` | - |
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+ | ` i16x8.add_sat_s ` | ` 0x8f ` | - |
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+ | ` i16x8.add_sat_u ` | ` 0x90 ` | - |
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+ | ` i16x8.sub ` | ` 0x91 ` | - |
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+ | ` i16x8.sub_sat_s ` | ` 0x92 ` | - |
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+ | ` i16x8.sub_sat_u ` | ` 0x93 ` | - |
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+ | ` i16x8.mul ` | ` 0x95 ` | - |
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+ | ` i16x8.min_s ` | ` 0x96 ` | - |
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+ | ` i16x8.min_u ` | ` 0x97 ` | - |
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+ | ` i16x8.max_s ` | ` 0x98 ` | - |
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+ | ` i16x8.max_u ` | ` 0x99 ` | - |
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+ | ` i16x8.avgr_u ` | ` 0x9b ` | - |
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+ | ` i32x4.abs ` | ` 0xa0 ` | - |
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+ | ` i32x4.neg ` | ` 0xa1 ` | - |
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+ | ` i32x4.all_true ` | ` 0xa3 ` | - |
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+ | ` i32x4.bitmask ` | ` 0xa4 ` | - |
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+ | ` i32x4.widen_low_i16x8_s ` | ` 0xa7 ` | - |
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+ | ` i32x4.widen_high_i16x8_s ` | ` 0xa8 ` | - |
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+ | ` i32x4.widen_low_i16x8_u ` | ` 0xa9 ` | - |
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+ | ` i32x4.widen_high_i16x8_u ` | ` 0xaa ` | - |
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+ | ` i32x4.shl ` | ` 0xab ` | - |
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+ | ` i32x4.shr_s ` | ` 0xac ` | - |
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+ | ` i32x4.shr_u ` | ` 0xad ` | - |
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+ | ` i32x4.add ` | ` 0xae ` | - |
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+ | ` i32x4.sub ` | ` 0xb1 ` | - |
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+ | ` i32x4.mul ` | ` 0xb5 ` | - |
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+ | ` i32x4.min_s ` | ` 0xb6 ` | - |
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+ | ` i32x4.min_u ` | ` 0xb7 ` | - |
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+ | ` i32x4.max_s ` | ` 0xb8 ` | - |
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+ | ` i32x4.max_u ` | ` 0xb9 ` | - |
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+ | ` i32x4.dot_i16x8_s ` | ` 0xba ` | - |
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+ | ` i64x2.neg ` | ` 0xc1 ` | - |
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+ | ` i64x2.bitmask ` | ` 0xc4 ` | - |
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+ | ` i64x2.widen_low_i32x4_s ` | ` 0xc7 ` | - |
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+ | ` i64x2.widen_high_i32x4_s ` | ` 0xc8 ` | - |
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+ | ` i64x2.widen_low_i32x4_u ` | ` 0xc9 ` | - |
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+ | ` i64x2.widen_high_i32x4_u ` | ` 0xca ` | - |
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+ | ` i64x2.shl ` | ` 0xcb ` | - |
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+ | ` i64x2.shr_s ` | ` 0xcc ` | - |
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+ | ` i64x2.shr_u ` | ` 0xcd ` | - |
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+ | ` i64x2.add ` | ` 0xce ` | - |
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+ | ` i64x2.sub ` | ` 0xd1 ` | - |
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+ | ` i64x2.mul ` | ` 0xd5 ` | - |
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+ | ` f32x4.ceil ` | ` 0xd8 ` | - |
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+ | ` f32x4.floor ` | ` 0xd9 ` | - |
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+ | ` f32x4.trunc ` | ` 0xda ` | - |
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+ | ` f32x4.nearest ` | ` 0xdb ` | - |
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+ | ` f64x2.ceil ` | ` 0xdc ` | - |
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+ | ` f64x2.floor ` | ` 0xdd ` | - |
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+ | ` f64x2.trunc ` | ` 0xde ` | - |
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+ | ` f64x2.nearest ` | ` 0xdf ` | - |
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+ | ` f32x4.abs ` | ` 0xe0 ` | - |
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+ | ` f32x4.neg ` | ` 0xe1 ` | - |
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+ | ` f32x4.sqrt ` | ` 0xe3 ` | - |
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+ | ` f32x4.add ` | ` 0xe4 ` | - |
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+ | ` f32x4.sub ` | ` 0xe5 ` | - |
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+ | ` f32x4.mul ` | ` 0xe6 ` | - |
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+ | ` f32x4.div ` | ` 0xe7 ` | - |
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+ | ` f32x4.min ` | ` 0xe8 ` | - |
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+ | ` f32x4.max ` | ` 0xe9 ` | - |
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+ | ` f32x4.pmin ` | ` 0xea ` | - |
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+ | ` f32x4.pmax ` | ` 0xeb ` | - |
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+ | ` f64x2.abs ` | ` 0xec ` | - |
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+ | ` f64x2.neg ` | ` 0xed ` | - |
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+ | ` f64x2.sqrt ` | ` 0xef ` | - |
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+ | ` f64x2.add ` | ` 0xf0 ` | - |
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+ | ` f64x2.sub ` | ` 0xf1 ` | - |
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+ | ` f64x2.mul ` | ` 0xf2 ` | - |
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+ | ` f64x2.div ` | ` 0xf3 ` | - |
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+ | ` f64x2.min ` | ` 0xf4 ` | - |
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+ | ` f64x2.max ` | ` 0xf5 ` | - |
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+ | ` f64x2.pmin ` | ` 0xf6 ` | - |
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+ | ` f64x2.pmax ` | ` 0xf7 ` | - |
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+ | ` i32x4.trunc_sat_f32x4_s ` | ` 0xf8 ` | - |
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+ | ` i32x4.trunc_sat_f32x4_u ` | ` 0xf9 ` | - |
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+ | ` f32x4.convert_i32x4_s ` | ` 0xfa ` | - |
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+ | ` f32x4.convert_i32x4_u ` | ` 0xfb ` | - |
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+ | ` v128.load32_zero ` | ` 0xfc ` | - |
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+ | ` v128.load64_zero ` | ` 0xfd ` | - |
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+ | ` i16x8.extmul_low_i8x16_s ` | ` 0x110 ` | - |
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+ | ` i16x8.extmul_high_i8x16_s ` | ` 0x111 ` | - |
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+ | ` i16x8.extmul_low_i8x16_u ` | ` 0x112 ` | - |
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+ | ` i16x8.extmul_high_i8x16_u ` | ` 0x113 ` | - |
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+ | ` i32x4.extmul_low_i16x8_s ` | ` 0x114 ` | - |
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+ | ` i32x4.extmul_high_i16x8_s ` | ` 0x115 ` | - |
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+ | ` i32x4.extmul_low_i16x8_u ` | ` 0x116 ` | - |
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+ | ` i32x4.extmul_high_i16x8_u ` | ` 0x117 ` | - |
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+ | ` i64x2.extmul_low_i32x4_s ` | ` 0x118 ` | - |
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+ | ` i64x2.extmul_high_i32x4_s ` | ` 0x119 ` | - |
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+ | ` i64x2.extmul_low_i32x4_u ` | ` 0x11a ` | - |
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+ | ` i64x2.extmul_high_i32x4_u ` | ` 0x11b ` | - |
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+ | ` i16x8.q15mulr_sat_s ` | ` TBD ` | - |
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+ | ` v128.any_true ` | ` TBD ` | - |
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+ | ` v128.load8_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx16 |
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+ | ` v128.load16_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx8 |
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+ | ` v128.load32_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx4 |
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+ | ` v128.load64_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx2 |
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+ | ` v128.store8_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx16 |
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+ | ` v128.store16_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx8 |
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+ | ` v128.store32_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx4 |
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+ | ` v128.store64_lane ` | ` TBD ` | m: memarg , i: ImmLaneIdx2 |
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+ | ` i64x2.eq ` | ` TBD ` | - |
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+ | ` i64x2.ne ` | ` TBD ` | - |
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+ | ` i64x2.all_true ` | ` TBD ` | - |
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+ | ` i64x2.lt_s ` | ` TBD ` | - |
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+ | ` i64x2.gt_s ` | ` TBD ` | - |
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+ | ` i64x2.le_s ` | ` TBD ` | - |
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+ | ` i64x2.ge_s ` | ` TBD ` | - |
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+ >>>>>>> 12d1340 (i64x2.gt_s, i64x2.lt_s, i64x2.ge_s, and i64x2.le_s instructions)
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