From 4b303eb892c00d0859dd3b6ef84b9b030c65c8b8 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Thu, 18 Feb 2021 17:40:15 -0800 Subject: [PATCH 1/2] [spectext] Add extended pairwise add instructions This was merged in #380. --- .../core/appendix/gen-index-instructions.py | 4 +++ document/core/binary/instructions.rst | 6 +++- document/core/exec/instructions.rst | 35 +++++++++++++++++-- document/core/syntax/instructions.rst | 2 ++ document/core/text/instructions.rst | 13 ++++--- document/core/util/macros.def | 1 + document/core/valid/instructions.rst | 14 ++++++++ 7 files changed, 67 insertions(+), 8 deletions(-) diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py index 75e25e804..835ef2a3c 100755 --- a/document/core/appendix/gen-index-instructions.py +++ b/document/core/appendix/gen-index-instructions.py @@ -470,10 +470,14 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat Instruction(r'\I16X8.\EXTMUL\K{\_high\_i8x16\_s}', r'\hex{FD}~~157', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I16X8.\EXTMUL\K{\_low\_i8x16\_u}', r'\hex{FD}~~158', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), Instruction(r'\I16X8.\EXTMUL\K{\_high\_i8x16\_u}', r'\hex{FD}~~159', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'), + Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}', r'\hex{FD}~~194', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), + Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}', r'\hex{FD}~~195', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), Instruction(r'\I32X4.\VABS', r'\hex{FD}~~160', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'), Instruction(r'\I32X4.\VNEG', r'\hex{FD}~~161', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'), Instruction(r'\I32X4.\ALLTRUE', r'\hex{FD}~~163', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'), Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'), + Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}', r'\hex{FD}~~165', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), + Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}', r'\hex{FD}~~166', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'), Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'), Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'), Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'), diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst index 0ed683e3f..456d29b98 100644 --- a/document/core/binary/instructions.rst +++ b/document/core/binary/instructions.rst @@ -663,7 +663,9 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~156{:}\Bu32 &\Rightarrow& \I16X8.\Q15MULRSAT\K{\_s} \\ &&|& \hex{FD}~~157{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_s}\\ &&|& \hex{FD}~~158{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_u}\\ &&|& - \hex{FD}~~159{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ + \hex{FD}~~159{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ &&|& + \hex{FD}~~194{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|& + \hex{FD}~~195{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\ \end{array} .. math:: @@ -673,6 +675,8 @@ All other SIMD instructions are plain opcodes without any immediates. \hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|& \hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|& \hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|& + \hex{FD}~~165{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|& + \hex{FD}~~166{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}\\ &&|& \hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s} \\ &&|& \hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s} \\ &&|& \hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u} \\ &&|& diff --git a/document/core/exec/instructions.rst b/document/core/exec/instructions.rst index c542c6c87..5a0ecbad0 100644 --- a/document/core/exec/instructions.rst +++ b/document/core/exec/instructions.rst @@ -674,7 +674,7 @@ SIMD instructions are defined in terms of generic numeric operators applied lane .. _exec-simd-extend: :math:`t_2\K{x}N\K{.}\VEXTEND\_\K{low}\_t_1\K{x}M\_\sx` -..................................................... +....................................................... 1. Assert: due to :ref:`validation `, a value of :ref:`value type ` |V128| is on the top of the stack. @@ -700,7 +700,7 @@ SIMD instructions are defined in terms of generic numeric operators applied lane :math:`t_2\K{x}N\K{.}\VEXTEND\_\K{high}\_t_1\K{x}M\_\sx` -...................................................... +........................................................ 1. Assert: due to :ref:`validation `, a value of :ref:`value type ` |V128| is on the top of the stack. @@ -809,6 +809,37 @@ SIMD instructions are defined in terms of generic numeric operators applied lane \end{array} +.. _exec-simd-extaddpairwise: + +:math:`t_2\K{x}N\K{.}\EXTADDPAIRWISE\_t_1\K{x}M\_\sx` +..................................................... + +1. Assert: due to :ref:`validation `, a value of :ref:`value type ` |V128| is on the top of the stack. + +2. Pop the value :math:`\V128.\VCONST~c_1` from the stack. + +3. Let :math:`(i_1~i_2)^\ast` be the sequence :math:`\extend^{\sx}_{M,N}(\lanes_{t_1\K{x}M}(c_1))`. + +4. Let :math:`j^\ast` be the result of computing :math:`\iadd_{N}(i_1, i_2)^\ast`. + +5. Let `c` be the result of computing :math:`\lanes^{-1}_{t_2\K{x}N}(j^\ast)`. + +6. Push the value :math:`\V128.\VCONST~c` to the stack. + +.. math:: + \begin{array}{l} + \begin{array}{lcl@{\qquad}l} + (\V128\K{.}\VCONST~c_1)~t_2\K{x}N\K{.}\EXTADDPAIRWISE\_t_1\K{x}M\_\sx &\stepto& (\V128\K{.}\VCONST~c) \\ + \end{array} + \\ \qquad + \begin{array}[t]{@{}r@{~}l@{}} + (\iff & (i_1~i_2)^\ast = \extend^{\sx}_{M,N}(\lanes_{t_1\K{x}M}(c_1)) \\ + \wedge & j^\ast = \iadd_{N}(i_1, i_2)^\ast \\ + \wedge & c = \lanes^{-1}_{t_2\K{x}N}(j^\ast) + \end{array} + \end{array} + + .. index:: parametric instructions, value pair: execution; instruction single: abstract syntax; instruction diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index 0d97c76e2..ad1d6f78a 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -267,6 +267,8 @@ SIMD instructions provide basic operations over :ref:`values ` of \K{i32x4.}\EXTMUL\K{\_high}\K{\_i16x8\_}\sx \\&&|& \K{i64x2.}\EXTMUL\K{\_low}\K{\_i32x4\_}\sx ~|~ \K{i64x2.}\EXTMUL\K{\_high}\K{\_i32x4\_}\sx \\&&|& + \K{i16x8.}\EXTADDPAIRWISE\K{\_i8x16\_}\sx ~|~ + \K{i32x4.}\EXTADDPAIRWISE\K{\_i16x8\_}\sx \\ &&|& \fshape\K{.}\vfbinop \\&&|& \K{i32x4.}\VTRUNC\K{\_sat\_f32x4\_}\sx \\ &&|& \K{f32x4.}\VCONVERT\K{\_i32x4\_}\sx \\&&|& diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index 36c276360..d1f5948e4 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -696,7 +696,9 @@ SIMD const instructions have a mandatory :ref:`shape ` descri \text{i16x8.extmul\_low\_i8x16\_s} &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_s}\\ &&|& \text{i16x8.extmul\_high\_i8x16\_s} &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_s}\\ &&|& \text{i16x8.extmul\_low\_i8x16\_u} &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_u}\\ &&|& - \text{i16x8.extmul\_high\_i8x16\_u} &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ + \text{i16x8.extmul\_high\_i8x16\_u} &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ &&|& + \text{i16x8.extadd\_pairwise\_i8x16\_s} &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|& + \text{i16x8.extadd\_pairwise\_i8x16\_u} &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\ \end{array} .. math:: @@ -706,10 +708,11 @@ SIMD const instructions have a mandatory :ref:`shape ` descri \text{i32x4.neg} &\Rightarrow& \I32X4.\VNEG\\ &&|& \text{i32x4.all\_true} &\Rightarrow& \I32X4.\ALLTRUE\\ &&|& \text{i32x4.bitmask} &\Rightarrow& \I32X4.\BITMASK\\ &&|& - \text{i32x4.extend\_low\_i16x8\_s} &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s}\\ &&|& - \text{i32x4.extend\_high\_i16x8\_s} &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s}\\ &&|& - \text{i32x4.extend\_low\_i16x8\_u} &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u}\\ &&|& - \text{i32x4.extend\_high\_i16x8\_u} &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_u}\\ &&|& + \text{i32x4.extadd\_pairwise\_i16x8\_s} &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|& + \text{i32x4.widen\_low\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s}\\ &&|& + \text{i32x4.widen\_high\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s}\\ &&|& + \text{i32x4.widen\_low\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u}\\ &&|& + \text{i32x4.widen\_high\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u}\\ &&|& \text{i32x4.shl} &\Rightarrow& \I32X4.\VSHL\\ &&|& \text{i32x4.shr\_s} &\Rightarrow& \I32X4.\VSHR\K{\_s}\\ &&|& \text{i32x4.shr\_u} &\Rightarrow& \I32X4.\VSHR\K{\_u}\\ &&|& diff --git a/document/core/util/macros.def b/document/core/util/macros.def index 1007fd508..a2521edce 100644 --- a/document/core/util/macros.def +++ b/document/core/util/macros.def @@ -430,6 +430,7 @@ .. |VTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{trunc}} .. |VCONVERT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{convert}} .. |Q15MULRSAT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{q15mulr\_sat}} +.. |EXTADDPAIRWISE| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{extadd\_pairwise}} .. Instructions, non-terminals diff --git a/document/core/valid/instructions.rst b/document/core/valid/instructions.rst index ccdb506fe..a6b4347fb 100644 --- a/document/core/valid/instructions.rst +++ b/document/core/valid/instructions.rst @@ -478,6 +478,20 @@ We also define an auxiliary function to get number of packed numeric types in a } +.. _valid-simd-extaddpairwise: + +:math:`\ishape\K{.}\EXTADDPAIRWISE\K{\_}\ishape\K{\_}\sx` +......................................................... + +* The instruction is valid with type :math:`[\V128] \to [\V128]`. + +.. math:: + \frac{ + }{ + C \vdashinstr \ishape\K{.}\EXTADDPAIRWISE\K{\_}\ishape\K{\_}\sx : [\V128] \to [\V128] + } + + .. index:: parametric instructions, value type, polymorphism pair: validation; instruction single: abstract syntax; instruction From 6f0d95615102366eca2bc2232a532d9871a1c517 Mon Sep 17 00:00:00 2001 From: Ng Zhi An Date: Tue, 23 Feb 2021 13:28:00 -0800 Subject: [PATCH 2/2] Fix bad merge --- document/core/syntax/instructions.rst | 1 + document/core/text/instructions.rst | 8 ++++---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst index ad1d6f78a..48b27b93a 100644 --- a/document/core/syntax/instructions.rst +++ b/document/core/syntax/instructions.rst @@ -376,6 +376,7 @@ For the other SIMD instructions, the use of two's complement for the signed inte .. _syntax-vbinop: .. _syntax-vextend: .. _syntax-vextmul: +.. _syntax-vcvtop: Conventions ........... diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst index d1f5948e4..5bae20ba9 100644 --- a/document/core/text/instructions.rst +++ b/document/core/text/instructions.rst @@ -709,10 +709,10 @@ SIMD const instructions have a mandatory :ref:`shape ` descri \text{i32x4.all\_true} &\Rightarrow& \I32X4.\ALLTRUE\\ &&|& \text{i32x4.bitmask} &\Rightarrow& \I32X4.\BITMASK\\ &&|& \text{i32x4.extadd\_pairwise\_i16x8\_s} &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|& - \text{i32x4.widen\_low\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s}\\ &&|& - \text{i32x4.widen\_high\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s}\\ &&|& - \text{i32x4.widen\_low\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u}\\ &&|& - \text{i32x4.widen\_high\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u}\\ &&|& + \text{i32x4.extend\_low\_i16x8\_s} &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s}\\ &&|& + \text{i32x4.extend\_high\_i16x8\_s} &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s}\\ &&|& + \text{i32x4.extend\_low\_i16x8\_u} &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u}\\ &&|& + \text{i32x4.extend\_high\_i16x8\_u} &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_u}\\ &&|& \text{i32x4.shl} &\Rightarrow& \I32X4.\VSHL\\ &&|& \text{i32x4.shr\_s} &\Rightarrow& \I32X4.\VSHR\K{\_s}\\ &&|& \text{i32x4.shr\_u} &\Rightarrow& \I32X4.\VSHR\K{\_u}\\ &&|&