Add Load-And-Splat instructions (WebAssembly#82)

Author: Maratyszcza

proposals/simd/BinarySIMD.md

@@ -167,4 +167,8 @@ The `v8x16.shuffle2_imm` instruction has 16 bytes after `simdop`.
 | `f64x2.convert_s/i64x2`   |    `0xb1`| -                  |
 | `f64x2.convert_u/i64x2`   |    `0xb2`| -                  |
 | `v8x16.shuffle1`          |    `0xc0`| -                  |
-| `v8x16.shuffle2_imm`      |    `0xc1`| s:LaneIdx32[16]    |
+| `v8x16.shuffle2_imm`      |    `0xc1`| s:LaneIdx32[16]    |
+| `i8x16.load_splat`        |    `0xc2`| -                  |
+| `i16x8.load_splat`        |    `0xc3`| -                  |
+| `i32x4.load_splat`        |    `0xc4`| -                  |
+| `i64x2.load_splat`        |    `0xc5`| -                  |

proposals/simd/ImplementationStatus.md

@@ -4,14 +4,17 @@
 | `v128.store`              |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `v128.const`              | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
 | `i8x16.splat`             |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| `i8x16.load_splat`        |                           |                    |                    |                    |
 | `i8x16.extract_lane_s`    |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `i8x16.extract_lane_u`    | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
 | `i8x16.replace_lane`      |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `i16x8.splat`             |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| `i16x8.load_splat`        |                           |                    |                    |                    |
 | `i16x8.extract_lane_s`    |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `i16x8.extract_lane_u`    | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
 | `i16x8.replace_lane`      |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `i32x4.splat`             |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
+| `i32x4.load_splat`        |                           |                    |                    |                    |
 | `i32x4.extract_lane`      |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `i32x4.replace_lane`      |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `i64x2.splat`             | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
@@ -21,6 +24,7 @@
 | `f32x4.extract_lane`      |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `f32x4.replace_lane`      |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |
 | `f64x2.splat`             | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
+| `i64x2.load_splat`        |                           |                    |                    |                    |
 | `f64x2.extract_lane`      | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
 | `f64x2.replace_lane`      | `-munimplemented-simd128` |                    | :heavy_check_mark: | :heavy_check_mark: |
 | `i8x16.eq`                |               `-msimd128` | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |

proposals/simd/SIMD.md

@@ -666,6 +666,15 @@ natural alignment.
 
 Load a `v128` vector from the given heap address.
 
+### Load and Splat
+
+* `i8x16.load_splat(memarg) -> v128`
+* `i16x8.load_splat(memarg) -> v128`
+* `i32x4.load_splat(memarg) -> v128`
+* `i64x2.load_splat(memarg) -> v128`
+
+Load a single element and splat to all lanes of a `v128` vector.
+
 ### Store
 
 * `v128.store(memarg, data: v128)`