wip

Author: whitequark

nmigen/sim/_cxxrtl_ctypes.py

@@ -1,7 +1,7 @@
 from enum import IntEnum
 from ctypes import (cdll, Structure, POINTER, CFUNCTYPE,
                     c_int, c_size_t, c_uint32, c_uint64, c_void_p, c_char_p,
-                    byref)
+                    byref, string_at)
 
 
 __all__ = []
@@ -140,8 +140,12 @@ def get_parts(handle, name):
         self.vcd_destroy.argtypes = [cxxrtl_vcd]
         self.vcd_destroy.restype = None
 
+        self.vcd_timescale = library.cxxrtl_vcd_timescale
+        self.vcd_timescale.argtypes = [cxxrtl_vcd, c_int, c_char_p]
+        self.vcd_timescale.restype = None
+
         self.vcd_add = library.cxxrtl_vcd_add
-        self.vcd_add.argtypes = [cxxrtl_vcd, c_int, c_char_p]
+        self.vcd_add.argtypes = [cxxrtl_vcd, c_char_p, cxxrtl_object_p]
         self.vcd_add.restype = None
 
         self.vcd_add_from = library.cxxrtl_vcd_add_from
@@ -160,6 +164,12 @@ def get_parts(handle, name):
         self.vcd_sample.argtypes = [cxxrtl_vcd, c_uint64]
         self.vcd_sample.restype = None
 
-        self.vcd_read = library.cxxrtl_vcd_read
-        self.vcd_read.argtypes = [cxxrtl_vcd, POINTER(c_char_p), POINTER(c_size_t)]
-        self.vcd_read.restype = None
+        _vcd_read = library.cxxrtl_vcd_read
+        _vcd_read.argtypes = [cxxrtl_vcd, POINTER(c_char_p), POINTER(c_size_t)]
+        _vcd_read.restype = None
+        def vcd_read(vcd):
+            data = c_char_p()
+            size = c_size_t()
+            _vcd_read(vcd, byref(data), byref(size))
+            return string_at(data.value, size.value)
+        self.vcd_read = vcd_read

nmigen/sim/cxxsim.py

@@ -1,4 +1,5 @@
 import os
+from contextlib import contextmanager
 
 from ..hdl import *
 from ..hdl.ast import SignalDict
@@ -101,6 +102,7 @@ def __init__(self, fragment):
         # cxxlib = cxxrtl_library("./sim.so")
 
         self._state = _SimulatorState(cxxlib, name_map)
+        self._vcd_writers = []
 
     def _add_coroutine_process(self, process, *, default_cmd):
         self._processes.add(PyCoroProcess(self._state, self._timeline,
@@ -109,6 +111,7 @@ def _add_coroutine_process(self, process, *, default_cmd):
 
     def reset(self):
         self._state.reset()
+        self._timeline.reset()
         for process in self._processes:
             process.reset()
 
@@ -122,3 +125,22 @@ def _real_step(self):
             self._state.eval()
             if not self._state.commit():
                 break
+
+        for vcd_writer, vcd_file in self._vcd_writers:
+            self._state.cxxlib.vcd_sample(vcd_writer, int(self._timeline.now * 10 ** 10))
+            vcd_file.write(self._state.cxxlib.vcd_read(vcd_writer))
+
+    @contextmanager
+    def write_vcd(self, vcd_file):
+        if self._timeline.now != 0.0:
+            raise ValueError("Cannot start writing waveforms after advancing simulation time")
+        with open(vcd_file, "wb") as vcd_file:
+            try:
+                vcd_writer = self._state.cxxlib.vcd_create()
+                self._vcd_writers.append((vcd_writer, vcd_file))
+                self._state.cxxlib.vcd_timescale(vcd_writer, 100, b"ps")
+                self._state.cxxlib.vcd_add_from(vcd_writer, self._state.handle)
+                yield
+            finally:
+                self._vcd_writers.remove((vcd_writer, vcd_file))
+                self._state.cxxlib.vcd_destroy(vcd_writer)

nmigen/sim/pysim.py

@@ -255,7 +255,7 @@ def _real_step(self):
 
             for waveform_writer in self._waveform_writers:
                 for signal_state in self._state.pending:
-                    waveform_writer.update(self._state.timeline.now,
+                    waveform_writer.update(self._timeline.now,
                         signal_state.signal, signal_state.next)
 
             # 2. commit: apply every queued signal change, waking up any waiting processes