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add_clock_constraint(ClockSignal)
1 parent 6fb5f3f commit bdd0ebfCopy full SHA for bdd0ebf
amaranth/build/res.py
@@ -242,7 +242,11 @@ def iter_port_constraints_bits(self):
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yield f"{port_name}[{bit}]", pin_name, attrs
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def add_clock_constraint(self, clock, frequency):
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- if not isinstance(clock, Signal):
+ if isinstance(clock, ClockSignal):
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+ raise TypeError(f"A clock constraint can only be applied to a Signal, but a "
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+ f"ClockSignal is provided; assign the ClockSignal to an "
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+ f"intermediate signal and constrain the latter instead.")
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+ elif not isinstance(clock, Signal):
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raise TypeError(f"Object {clock!r} is not a Signal")
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if not isinstance(frequency, (int, float)):
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raise TypeError(f"Frequency must be a number, not {frequency!r}")
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