Skip to content

Commit bdd0ebf

Browse files
committed
build.res: give a more specific error for add_clock_constraint(ClockSignal).
Fixes #542.
1 parent 6fb5f3f commit bdd0ebf

File tree

1 file changed

+5
-1
lines changed

1 file changed

+5
-1
lines changed

amaranth/build/res.py

+5-1
Original file line numberDiff line numberDiff line change
@@ -242,7 +242,11 @@ def iter_port_constraints_bits(self):
242242
yield f"{port_name}[{bit}]", pin_name, attrs
243243

244244
def add_clock_constraint(self, clock, frequency):
245-
if not isinstance(clock, Signal):
245+
if isinstance(clock, ClockSignal):
246+
raise TypeError(f"A clock constraint can only be applied to a Signal, but a "
247+
f"ClockSignal is provided; assign the ClockSignal to an "
248+
f"intermediate signal and constrain the latter instead.")
249+
elif not isinstance(clock, Signal):
246250
raise TypeError(f"Object {clock!r} is not a Signal")
247251
if not isinstance(frequency, (int, float)):
248252
raise TypeError(f"Frequency must be a number, not {frequency!r}")

0 commit comments

Comments
 (0)