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msperlanholt
msperl
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clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driver
As the use of BCM2835_CLOCK_COUNT in include/dt-bindings/clock/bcm2835.h is frowned upon as it needs to get modified every time a new clock gets introduced this patch changes the clk-bcm2835 driver to use a different scheme for registration of clocks and pll, so that there is no more need for BCM2835_CLOCK_COUNT to be defined. Signed-off-by: Martin Sperl <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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‎drivers/clk/bcm/clk-bcm2835.c

Lines changed: 94 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -301,7 +301,7 @@ struct bcm2835_cprman {
301301
const char *osc_name;
302302

303303
struct clk_onecell_data onecell;
304-
struct clk *clks[BCM2835_CLOCK_COUNT];
304+
struct clk *clks[];
305305
};
306306

307307
static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
@@ -850,6 +850,25 @@ static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
850850
.is_mash_clock = true,
851851
};
852852

853+
struct bcm2835_gate_data {
854+
const char *name;
855+
const char *parent;
856+
857+
u32 ctl_reg;
858+
};
859+
860+
/*
861+
* CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
862+
* you have the debug bit set in the power manager, which we
863+
* don't bother exposing) are individual gates off of the
864+
* non-stop vpu clock.
865+
*/
866+
static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
867+
.name = "peri_image",
868+
.parent = "vpu",
869+
.ctl_reg = CM_PERIICTL,
870+
};
871+
853872
struct bcm2835_pll {
854873
struct clk_hw hw;
855874
struct bcm2835_cprman *cprman;
@@ -1642,14 +1661,81 @@ static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman,
16421661
return devm_clk_register(cprman->dev, &clock->hw);
16431662
}
16441663

1664+
static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1665+
const struct bcm2835_gate_data *data)
1666+
{
1667+
return clk_register_gate(cprman->dev, data->name, data->parent,
1668+
CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1669+
cprman->regs + data->ctl_reg,
1670+
CM_GATE_BIT, 0, &cprman->regs_lock);
1671+
}
1672+
1673+
typedef struct clk *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1674+
const void *data);
1675+
struct bcm2835_clk_desc {
1676+
bcm2835_clk_register clk_register;
1677+
const void *data;
1678+
};
1679+
1680+
#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
1681+
.data = d }
1682+
#define REGISTER_PLL(d) _REGISTER(&bcm2835_register_pll, d)
1683+
#define REGISTER_PLL_DIV(d) _REGISTER(&bcm2835_register_pll_divider, d)
1684+
#define REGISTER_CLK(d) _REGISTER(&bcm2835_register_clock, d)
1685+
#define REGISTER_GATE(d) _REGISTER(&bcm2835_register_gate, d)
1686+
1687+
static const struct bcm2835_clk_desc clk_desc_array[] = {
1688+
/* register PLL */
1689+
[BCM2835_PLLA] = REGISTER_PLL(&bcm2835_plla_data),
1690+
[BCM2835_PLLB] = REGISTER_PLL(&bcm2835_pllb_data),
1691+
[BCM2835_PLLC] = REGISTER_PLL(&bcm2835_pllc_data),
1692+
[BCM2835_PLLD] = REGISTER_PLL(&bcm2835_plld_data),
1693+
[BCM2835_PLLH] = REGISTER_PLL(&bcm2835_pllh_data),
1694+
/* the PLL dividers */
1695+
[BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
1696+
[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
1697+
[BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
1698+
[BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
1699+
[BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
1700+
[BCM2835_PLLC_PER] = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
1701+
[BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
1702+
[BCM2835_PLLD_PER] = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
1703+
[BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
1704+
[BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
1705+
[BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
1706+
/* the clocks */
1707+
[BCM2835_CLOCK_TIMER] = REGISTER_CLK(&bcm2835_clock_timer_data),
1708+
[BCM2835_CLOCK_OTP] = REGISTER_CLK(&bcm2835_clock_otp_data),
1709+
[BCM2835_CLOCK_TSENS] = REGISTER_CLK(&bcm2835_clock_tsens_data),
1710+
[BCM2835_CLOCK_VPU] = REGISTER_CLK(&bcm2835_clock_vpu_data),
1711+
[BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
1712+
[BCM2835_CLOCK_ISP] = REGISTER_CLK(&bcm2835_clock_isp_data),
1713+
[BCM2835_CLOCK_H264] = REGISTER_CLK(&bcm2835_clock_h264_data),
1714+
[BCM2835_CLOCK_V3D] = REGISTER_CLK(&bcm2835_clock_v3d_data),
1715+
[BCM2835_CLOCK_SDRAM] = REGISTER_CLK(&bcm2835_clock_sdram_data),
1716+
[BCM2835_CLOCK_UART] = REGISTER_CLK(&bcm2835_clock_uart_data),
1717+
[BCM2835_CLOCK_VEC] = REGISTER_CLK(&bcm2835_clock_vec_data),
1718+
[BCM2835_CLOCK_HSM] = REGISTER_CLK(&bcm2835_clock_hsm_data),
1719+
[BCM2835_CLOCK_EMMC] = REGISTER_CLK(&bcm2835_clock_emmc_data),
1720+
[BCM2835_CLOCK_PWM] = REGISTER_CLK(&bcm2835_clock_pwm_data),
1721+
/* the gates */
1722+
[BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
1723+
&bcm2835_clock_peri_image_data),
1724+
};
1725+
16451726
static int bcm2835_clk_probe(struct platform_device *pdev)
16461727
{
16471728
struct device *dev = &pdev->dev;
16481729
struct clk **clks;
16491730
struct bcm2835_cprman *cprman;
16501731
struct resource *res;
1732+
const struct bcm2835_clk_desc *desc;
1733+
const size_t asize = ARRAY_SIZE(clk_desc_array);
1734+
size_t i;
16511735

1652-
cprman = devm_kzalloc(dev, sizeof(*cprman), GFP_KERNEL);
1736+
cprman = devm_kzalloc(dev,
1737+
sizeof(*cprman) + asize * sizeof(*clks),
1738+
GFP_KERNEL);
16531739
if (!cprman)
16541740
return -ENOMEM;
16551741

@@ -1666,80 +1752,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
16661752

16671753
platform_set_drvdata(pdev, cprman);
16681754

1669-
cprman->onecell.clk_num = BCM2835_CLOCK_COUNT;
1755+
cprman->onecell.clk_num = asize;
16701756
cprman->onecell.clks = cprman->clks;
16711757
clks = cprman->clks;
16721758

1673-
clks[BCM2835_PLLA] = bcm2835_register_pll(cprman, &bcm2835_plla_data);
1674-
clks[BCM2835_PLLB] = bcm2835_register_pll(cprman, &bcm2835_pllb_data);
1675-
clks[BCM2835_PLLC] = bcm2835_register_pll(cprman, &bcm2835_pllc_data);
1676-
clks[BCM2835_PLLD] = bcm2835_register_pll(cprman, &bcm2835_plld_data);
1677-
clks[BCM2835_PLLH] = bcm2835_register_pll(cprman, &bcm2835_pllh_data);
1678-
1679-
clks[BCM2835_PLLA_CORE] =
1680-
bcm2835_register_pll_divider(cprman, &bcm2835_plla_core_data);
1681-
clks[BCM2835_PLLA_PER] =
1682-
bcm2835_register_pll_divider(cprman, &bcm2835_plla_per_data);
1683-
clks[BCM2835_PLLC_CORE0] =
1684-
bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core0_data);
1685-
clks[BCM2835_PLLC_CORE1] =
1686-
bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core1_data);
1687-
clks[BCM2835_PLLC_CORE2] =
1688-
bcm2835_register_pll_divider(cprman, &bcm2835_pllc_core2_data);
1689-
clks[BCM2835_PLLC_PER] =
1690-
bcm2835_register_pll_divider(cprman, &bcm2835_pllc_per_data);
1691-
clks[BCM2835_PLLD_CORE] =
1692-
bcm2835_register_pll_divider(cprman, &bcm2835_plld_core_data);
1693-
clks[BCM2835_PLLD_PER] =
1694-
bcm2835_register_pll_divider(cprman, &bcm2835_plld_per_data);
1695-
clks[BCM2835_PLLH_RCAL] =
1696-
bcm2835_register_pll_divider(cprman, &bcm2835_pllh_rcal_data);
1697-
clks[BCM2835_PLLH_AUX] =
1698-
bcm2835_register_pll_divider(cprman, &bcm2835_pllh_aux_data);
1699-
clks[BCM2835_PLLH_PIX] =
1700-
bcm2835_register_pll_divider(cprman, &bcm2835_pllh_pix_data);
1701-
1702-
clks[BCM2835_CLOCK_TIMER] =
1703-
bcm2835_register_clock(cprman, &bcm2835_clock_timer_data);
1704-
clks[BCM2835_CLOCK_OTP] =
1705-
bcm2835_register_clock(cprman, &bcm2835_clock_otp_data);
1706-
clks[BCM2835_CLOCK_TSENS] =
1707-
bcm2835_register_clock(cprman, &bcm2835_clock_tsens_data);
1708-
clks[BCM2835_CLOCK_VPU] =
1709-
bcm2835_register_clock(cprman, &bcm2835_clock_vpu_data);
1710-
clks[BCM2835_CLOCK_V3D] =
1711-
bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1712-
clks[BCM2835_CLOCK_ISP] =
1713-
bcm2835_register_clock(cprman, &bcm2835_clock_isp_data);
1714-
clks[BCM2835_CLOCK_H264] =
1715-
bcm2835_register_clock(cprman, &bcm2835_clock_h264_data);
1716-
clks[BCM2835_CLOCK_V3D] =
1717-
bcm2835_register_clock(cprman, &bcm2835_clock_v3d_data);
1718-
clks[BCM2835_CLOCK_SDRAM] =
1719-
bcm2835_register_clock(cprman, &bcm2835_clock_sdram_data);
1720-
clks[BCM2835_CLOCK_UART] =
1721-
bcm2835_register_clock(cprman, &bcm2835_clock_uart_data);
1722-
clks[BCM2835_CLOCK_VEC] =
1723-
bcm2835_register_clock(cprman, &bcm2835_clock_vec_data);
1724-
clks[BCM2835_CLOCK_HSM] =
1725-
bcm2835_register_clock(cprman, &bcm2835_clock_hsm_data);
1726-
clks[BCM2835_CLOCK_EMMC] =
1727-
bcm2835_register_clock(cprman, &bcm2835_clock_emmc_data);
1728-
1729-
/*
1730-
* CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1731-
* you have the debug bit set in the power manager, which we
1732-
* don't bother exposing) are individual gates off of the
1733-
* non-stop vpu clock.
1734-
*/
1735-
clks[BCM2835_CLOCK_PERI_IMAGE] =
1736-
clk_register_gate(dev, "peri_image", "vpu",
1737-
CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1738-
cprman->regs + CM_PERIICTL, CM_GATE_BIT,
1739-
0, &cprman->regs_lock);
1740-
1741-
clks[BCM2835_CLOCK_PWM] =
1742-
bcm2835_register_clock(cprman, &bcm2835_clock_pwm_data);
1759+
for (i = 0; i < asize; i++) {
1760+
desc = &clk_desc_array[i];
1761+
if (desc->clk_register && desc->data)
1762+
clks[i] = desc->clk_register(cprman, desc->data);
1763+
}
17431764

17441765
return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
17451766
&cprman->onecell);

‎include/dt-bindings/clock/bcm2835.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -44,5 +44,3 @@
4444
#define BCM2835_CLOCK_EMMC 28
4545
#define BCM2835_CLOCK_PERI_IMAGE 29
4646
#define BCM2835_CLOCK_PWM 30
47-
48-
#define BCM2835_CLOCK_COUNT 31

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