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Commit 3539d69

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author
Dylan McKay
committed
[AVR] Added override qualifiers to methods
This uncovered a few bugs wherein methods which were supposed to be overrided were not being overriden. I also cleaned up a few comments in the process. Closes #75.
1 parent fad5f5c commit 3539d69

17 files changed

+139
-128
lines changed

‎lib/Target/AVR/AVRAsmPrinter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ class AVRAsmPrinter : public AsmPrinter
4141
explicit AVRAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) :
4242
AsmPrinter(TM, std::move(Streamer)) {}
4343

44-
const char *getPassName() const
44+
const char *getPassName() const override
4545
{
4646
return "AVR Assembly Printer";
4747
}

‎lib/Target/AVR/AVRBranchSelector.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,12 +37,13 @@ class AVRBSel : public MachineFunctionPass
3737
static char ID;
3838
AVRBSel() : MachineFunctionPass(ID) {}
3939

40-
bool runOnMachineFunction(MachineFunction &Fn);
40+
bool runOnMachineFunction(MachineFunction &Fn) override;
4141

42-
const char *getPassName() const
42+
const char *getPassName() const override
4343
{
4444
return "AVR Branch Selector";
4545
}
46+
4647
private:
4748
/// BlockSizes - The sizes of the basic blocks in the function.
4849
std::vector<unsigned> BlockSizes;

‎lib/Target/AVR/AVRExpandPseudoInsts.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,9 +35,9 @@ class AVRExpandPseudo : public MachineFunctionPass
3535
const TargetInstrInfo *TII;
3636
AVRExpandPseudo() : MachineFunctionPass(ID) {}
3737

38-
bool runOnMachineFunction(MachineFunction &MF);
38+
bool runOnMachineFunction(MachineFunction &MF) override;
3939

40-
const char *getPassName() const
40+
const char *getPassName() const override
4141
{
4242
return "AVR pseudo instruction expansion pass";
4343
}

‎lib/Target/AVR/AVRFrameLowering.h‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -24,24 +24,24 @@ class AVRFrameLowering : public TargetFrameLowering
2424
public:
2525
explicit AVRFrameLowering();
2626
public: // TargetFrameLowering
27-
void emitPrologue(MachineFunction &MF) const;
28-
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
29-
bool hasFP(const MachineFunction &MF) const;
27+
void emitPrologue(MachineFunction &MF) const override;
28+
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
29+
bool hasFP(const MachineFunction &MF) const override;
3030
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
3131
MachineBasicBlock::iterator MI,
3232
const std::vector<CalleeSavedInfo> &CSI,
33-
const TargetRegisterInfo *TRI) const;
33+
const TargetRegisterInfo *TRI) const override;
3434
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
3535
MachineBasicBlock::iterator MI,
3636
const std::vector<CalleeSavedInfo> &CSI,
37-
const TargetRegisterInfo *TRI) const;
38-
bool hasReservedCallFrame(const MachineFunction &MF) const;
39-
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
37+
const TargetRegisterInfo *TRI) const override;
38+
bool hasReservedCallFrame(const MachineFunction &MF) const override;
39+
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
4040
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
41-
RegScavenger *RS = NULL) const;
41+
RegScavenger *RS = NULL) const override;
4242
void eliminateCallFramePseudoInstr(MachineFunction &MF,
4343
MachineBasicBlock &MBB,
44-
MachineBasicBlock::iterator MI) const;
44+
MachineBasicBlock::iterator MI) const override;
4545
};
4646

4747
} // end namespace llvm

‎lib/Target/AVR/AVRISelDAGToDAG.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ class AVRDAGToDAGISel : public SelectionDAGISel
3535
explicit AVRDAGToDAGISel(AVRTargetMachine &tm, CodeGenOpt::Level OptLevel) :
3636
SelectionDAGISel(tm, OptLevel), Subtarget(nullptr) {}
3737

38-
const char *getPassName() const
38+
const char *getPassName() const override
3939
{
4040
return "AVR DAG->DAG Instruction Selection";
4141
}
@@ -49,14 +49,14 @@ class AVRDAGToDAGISel : public SelectionDAGISel
4949
// Indexed progmem load (only postinc) matching code.
5050
unsigned SelectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT);
5151

52-
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
53-
std::vector<SDValue> &OutOps);
52+
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintCode,
53+
std::vector<SDValue> &OutOps) override;
5454

5555
// Include the pieces autogenerated from the target description.
5656
#include "AVRGenDAGISel.inc"
5757

5858
private:
59-
SDNode *Select(SDNode *N);
59+
SDNode *Select(SDNode *N) override;
6060

6161
const AVRSubtarget *Subtarget;
6262
};
@@ -212,7 +212,7 @@ unsigned AVRDAGToDAGISel::SelectIndexedProgMemLoad(const LoadSDNode *LD, MVT VT)
212212
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
213213
/// inline asm expressions.
214214
bool AVRDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
215-
char ConstraintCode,
215+
unsigned ConstraintCode,
216216
std::vector<SDValue> &OutOps)
217217
{
218218
// Yes hardcoded 'm' symbol. Just because it also has been hardcoded in

‎lib/Target/AVR/AVRISelLowering.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1641,7 +1641,8 @@ AVRTargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &info,
16411641
}
16421642

16431643
std::pair<unsigned, const TargetRegisterClass *>
1644-
AVRTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1644+
AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1645+
const std::string &Constraint,
16451646
MVT VT) const
16461647
{
16471648
auto STI = static_cast<const AVRTargetMachine&>(this->getTargetMachine()).getSubtargetImpl();

‎lib/Target/AVR/AVRISelLowering.h‎

Lines changed: 65 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -22,44 +22,44 @@ namespace llvm
2222

2323
namespace AVRISD
2424
{
25-
/// AVR Specific DAG Nodes
25+
//! \brief AVR Specific DAG Nodes
2626
enum NodeType
2727
{
28-
/// Start the numbering where the builtin ops leave off.
28+
//! Start the numbering where the builtin ops leave off.
2929
FIRST_NUMBER = ISD::BUILTIN_OP_END,
30-
/// Return from subroutine.
30+
//! Return from subroutine.
3131
RET_FLAG,
32-
/// Return from ISR.
32+
//! Return from ISR.
3333
RETI_FLAG,
34-
/// CALL - These operations represent an abstract call
35-
/// instruction, which includes a bunch of information.
34+
//! These operations represent an abstract call
35+
//! instruction, which includes a bunch of information.
3636
CALL,
37-
/// Wrapper - A wrapper node for TargetConstantPool,
38-
/// TargetExternalSymbol, and TargetGlobalAddress.
37+
//! A wrapper node for TargetConstantPool,
38+
//! TargetExternalSymbol, and TargetGlobalAddress.
3939
Wrapper,
40-
/// Bit shifting and rotation.
40+
//! Bit shifting and rotation.
4141
LSL,
4242
LSR,
4343
ASR,
4444
ROR,
4545
ROL,
46-
/// Non-constant shifts.
46+
//! Non-constant shifts.
4747
LSLLOOP,
4848
LSRLOOP,
4949
ASRLOOP,
50-
/// AVR conditional branches. Operand 0 is the chain operand, operand 1
51-
/// is the block to branch if condition is true, operand 2 is the
52-
/// condition code, and operand 3 is the flag operand produced by a CMP
53-
/// or TEST instruction.
50+
//! AVR conditional branches. Operand 0 is the chain operand, operand 1
51+
//! is the block to branch if condition is true, operand 2 is the
52+
//! condition code, and operand 3 is the flag operand produced by a CMP
53+
//! or TEST instruction.
5454
BRCOND,
55-
/// CMP - Compare instruction.
55+
//! Compare instruction.
5656
CMP,
57-
/// CMPC - Compare with carry instruction.
57+
//! Compare with carry instruction.
5858
CMPC,
59-
/// TST - Test for zero or minus instruction.
59+
//! Test for zero or minus instruction.
6060
TST,
61-
/// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 2
62-
/// is condition code and operand 3 is flag operand.
61+
//! Operand 0 and operand 1 are selection variable, operand 2
62+
//! is condition code and operand 3 is flag operand.
6363
SELECT_CC
6464
};
6565
}
@@ -70,63 +70,73 @@ class AVRTargetLowering : public TargetLowering
7070
{
7171
public:
7272
explicit AVRTargetLowering(AVRTargetMachine &TM);
73-
public: // TargetLowering
73+
public:
7474
MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
75-
const char *getTargetNodeName(unsigned Opcode) const;
75+
const char *getTargetNodeName(unsigned Opcode) const override;
7676

77-
/// LowerOperation - Provide custom lowering hooks for some operations.
78-
///
79-
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
77+
/*!
78+
* \brief Provide custom lowering hooks for some operations.
79+
*/
80+
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
8081

81-
/// ReplaceNodeResults - Replace the results of node with an illegal result
82-
/// type with new values built out of custom code.
83-
///
82+
/*!
83+
* \brief Replace the results of node with an illegal result
84+
* type with new values built out of custom code.
85+
*/
8486
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
85-
SelectionDAG &DAG) const;
86-
87-
/// isLegalAddressingMode - Return true if the addressing mode represented
88-
/// by AM is legal for this target, for a load/store of the specified type.
89-
///
90-
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
91-
92-
/// getPreIndexedAddressParts - returns true by value, base pointer and
93-
/// offset pointer and addressing mode by reference if the node's address
94-
/// can be legally represented as pre-indexed load / store address.
87+
SelectionDAG &DAG) const override;
88+
89+
/*!
90+
* \brief Return true if the addressing mode represented
91+
* by AM is legal for this target, for a load/store
92+
* of the specified type.
93+
*/
94+
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
95+
96+
/*!
97+
* \brief Returns true by value, base pointer and
98+
* offset pointer and addressing mode by reference if the node's address
99+
* can be legally represented as pre-indexed load / store address.
100+
*/
95101
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
96102
ISD::MemIndexedMode &AM,
97-
SelectionDAG &DAG) const;
103+
SelectionDAG &DAG) const override;
98104

99-
/// getPostIndexedAddressParts - returns true by value, base pointer and
100-
/// offset pointer and addressing mode by reference if this node can be
101-
/// combined with a load / store to form a post-indexed load / store.
105+
/*!
106+
* \brief Returns true by value, base pointer and
107+
* offset pointer and addressing mode by reference if this node can be
108+
* combined with a load / store to form a post-indexed load / store.
109+
*/
102110
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
103111
SDValue &Offset, ISD::MemIndexedMode &AM,
104-
SelectionDAG &DAG) const;
112+
SelectionDAG &DAG) const override;
105113

106-
/// isOffsetFoldingLegal - Return true if folding a constant offset
107-
/// with the given GlobalAddress is legal. It is frequently not legal in
108-
/// PIC relocation models.
109-
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
114+
/*!
115+
* \brief Return true if folding a constant offset
116+
* with the given GlobalAddress is legal. It is frequently not legal in
117+
* PIC relocation models.
118+
*/
119+
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
110120

111121
MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
112-
MachineBasicBlock *MBB) const;
113-
MachineBasicBlock *EmitShiftInstr(MachineInstr *MI,
114-
MachineBasicBlock *BB) const;
122+
MachineBasicBlock *MBB) const override;
115123

116124
/// Inline Asm support.
117125
/// Implementation of TargetLowering hooks.
118-
ConstraintType getConstraintType(const std::string &Constraint) const;
126+
ConstraintType getConstraintType(const std::string &Constraint) const override;
119127

120128
ConstraintWeight
121129
getSingleConstraintMatchWeight(AsmOperandInfo &info,
122-
const char *constraint) const;
130+
const char *constraint) const override;
123131

124132
std::pair<unsigned, const TargetRegisterClass *>
125-
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
133+
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
134+
const std::string &Constraint,
135+
MVT VT) const override;
126136

127137
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
128138
std::vector<SDValue> &Ops,
129-
SelectionDAG &DAG) const;
139+
SelectionDAG &DAG) const override;
130140

131141
private:
132142
SDValue getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AVRcc,
@@ -156,6 +166,8 @@ class AVRTargetLowering : public TargetLowering
156166
const SmallVectorImpl<ISD::InputArg> &Ins,
157167
SDLoc dl, SelectionDAG &DAG,
158168
SmallVectorImpl<SDValue> &InVals) const;
169+
MachineBasicBlock *EmitShiftInstr(MachineInstr *MI,
170+
MachineBasicBlock *BB) const;
159171
};
160172

161173
} // end namespace llvm

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