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gergoerdidylanmckay
gergoerdi
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[AVR] Elaborate LDWRdPtr into ld r, X++; ld r+1, X
Patch by Gergo Erdi. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314896 91177308-0d34-0410-b5e6-96231b3b80d8
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8 files changed

+33
-33
lines changed

8 files changed

+33
-33
lines changed

‎lib/Target/AVR/AVRExpandPseudoInsts.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -583,8 +583,8 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
583583
unsigned TmpReg = 0; // 0 for no temporary register
584584
unsigned SrcReg = MI.getOperand(1).getReg();
585585
bool SrcIsKill = MI.getOperand(1).isKill();
586-
OpLo = AVR::LDRdPtr;
587-
OpHi = AVR::LDDRdPtrQ;
586+
OpLo = AVR::LDRdPtrPi;
587+
OpHi = AVR::LDRdPtr;
588588
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
589589

590590
// Use a temporary register if src and dst registers are the same.
@@ -597,6 +597,7 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
597597
// Load low byte.
598598
auto MIBLO = buildMI(MBB, MBBI, OpLo)
599599
.addReg(CurDstLoReg, RegState::Define)
600+
.addReg(SrcReg, RegState::Define)
600601
.addReg(SrcReg);
601602

602603
// Push low byte onto stack if necessary.
@@ -606,8 +607,7 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
606607
// Load high byte.
607608
auto MIBHI = buildMI(MBB, MBBI, OpHi)
608609
.addReg(CurDstHiReg, RegState::Define)
609-
.addReg(SrcReg, getKillRegState(SrcIsKill))
610-
.addImm(1);
610+
.addReg(SrcReg, getKillRegState(SrcIsKill));
611611

612612
if (TmpReg) {
613613
// Move the high byte into the final destination.

‎lib/Target/AVR/AVRInstrInfo.td

+3-3
Original file line numberDiff line numberDiff line change
@@ -1152,10 +1152,10 @@ isReMaterializable = 1 in
11521152
//
11531153
// Expands to:
11541154
// ld Rd, P+
1155-
// ld Rd+1, P+
1155+
// ld Rd+1, P
11561156
let Constraints = "@earlyclobber $reg" in
11571157
def LDWRdPtr : Pseudo<(outs DREGS:$reg),
1158-
(ins PTRDISPREGS:$ptrreg),
1158+
(ins PTRREGS:$ptrreg),
11591159
"ldw\t$reg, $ptrreg",
11601160
[(set i16:$reg, (load i16:$ptrreg))]>,
11611161
Requires<[HasSRAM]>;
@@ -1164,7 +1164,7 @@ isReMaterializable = 1 in
11641164
// Indirect loads (with postincrement or predecrement).
11651165
let mayLoad = 1,
11661166
hasSideEffects = 0,
1167-
Constraints = "$ptrreg = $base_wb,@earlyclobber $reg,@earlyclobber $base_wb" in
1167+
Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in
11681168
{
11691169
def LDRdPtrPi : FSTLD<0,
11701170
0b01,

‎test/CodeGen/AVR/atomics/load16.ll

+11-11
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33
; CHECK-LABEL: atomic_load16
44
; CHECK: in r0, 63
55
; CHECK-NEXT: cli
6+
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
67
; CHECK-NEXT: ld [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]
7-
; CHECK-NEXT: ldd [[RR:r[0-9]+]], [[RD:(X|Y|Z)]]+
88
; CHECK-NEXT: out 63, r0
99
define i16 @atomic_load16(i16* %foo) {
1010
%val = load atomic i16, i16* %foo unordered, align 2
@@ -29,8 +29,8 @@ define i16 @atomic_load_cmp_swap16(i16* %foo) {
2929
; CHECK-LABEL: atomic_load_add16
3030
; CHECK: in r0, 63
3131
; CHECK-NEXT: cli
32-
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
33-
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
32+
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
33+
; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
3434
; CHECK-NEXT: add [[RR1]], [[TMP:r[0-9]+]]
3535
; CHECK-NEXT: adc [[RR2]], [[TMP:r[0-9]+]]
3636
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -44,8 +44,8 @@ define i16 @atomic_load_add16(i16* %foo) {
4444
; CHECK-LABEL: atomic_load_sub16
4545
; CHECK: in r0, 63
4646
; CHECK-NEXT: cli
47-
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
48-
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
47+
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
48+
; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
4949
; CHECK-NEXT: sub [[RR1]], [[TMP:r[0-9]+]]
5050
; CHECK-NEXT: sbc [[RR2]], [[TMP:r[0-9]+]]
5151
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -59,8 +59,8 @@ define i16 @atomic_load_sub16(i16* %foo) {
5959
; CHECK-LABEL: atomic_load_and16
6060
; CHECK: in r0, 63
6161
; CHECK-NEXT: cli
62-
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
63-
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
62+
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
63+
; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
6464
; CHECK-NEXT: and [[RR1]], [[TMP:r[0-9]+]]
6565
; CHECK-NEXT: and [[RR2]], [[TMP:r[0-9]+]]
6666
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -74,8 +74,8 @@ define i16 @atomic_load_and16(i16* %foo) {
7474
; CHECK-LABEL: atomic_load_or16
7575
; CHECK: in r0, 63
7676
; CHECK-NEXT: cli
77-
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
78-
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
77+
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
78+
; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
7979
; CHECK-NEXT: or [[RR1]], [[TMP:r[0-9]+]]
8080
; CHECK-NEXT: or [[RR2]], [[TMP:r[0-9]+]]
8181
; CHECK-NEXT: st [[RD1]], [[RR1]]
@@ -89,8 +89,8 @@ define i16 @atomic_load_or16(i16* %foo) {
8989
; CHECK-LABEL: atomic_load_xor16
9090
; CHECK: in r0, 63
9191
; CHECK-NEXT: cli
92-
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]
93-
; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]+
92+
; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD1:(X|Y|Z)]]+
93+
; CHECK-NEXT: ld [[RR2:r[0-9]+]], [[RD2:(X|Y|Z)]]
9494
; CHECK-NEXT: eor [[RR1]], [[TMP:r[0-9]+]]
9595
; CHECK-NEXT: eor [[RR2]], [[TMP:r[0-9]+]]
9696
; CHECK-NEXT: st [[RD1]], [[RR1]]

‎test/CodeGen/AVR/load.ll

+7-7
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ define i8 @load8(i8* %x) {
99

1010
define i16 @load16(i16* %x) {
1111
; CHECK-LABEL: load16:
12-
; CHECK: ld r24, {{[YZ]}}
13-
; CHECK: ldd r25, {{[YZ]}}+1
12+
; CHECK: ld r24, {{[XYZ]}}+
13+
; CHECK: ld r25, {{[XYZ]}}
1414
%1 = load i16, i16* %x
1515
ret i16 %1
1616
}
@@ -45,11 +45,11 @@ define i16 @load16disp(i16* %x) {
4545

4646
define i16 @load16nodisp(i16* %x) {
4747
; CHECK-LABEL: load16nodisp:
48-
; CHECK: movw r30, r24
49-
; CHECK: subi r30, 192
50-
; CHECK: sbci r31, 255
51-
; CHECK: ld r24, {{[YZ]}}
52-
; CHECK: ldd r25, {{[YZ]}}+1
48+
; CHECK: movw r26, r24
49+
; CHECK: subi r26, 192
50+
; CHECK: sbci r27, 255
51+
; CHECK: ld r24, {{[XYZ]}}+
52+
; CHECK: ld r25, {{[XYZ]}}
5353
%1 = getelementptr inbounds i16, i16* %x, i64 32
5454
%2 = load i16, i16* %1
5555
ret i16 %2

‎test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -18,9 +18,9 @@ body: |
1818
1919
; CHECK-LABEL: test_ldwrdptr
2020
21-
; CHECK: ld [[SCRATCH:r[0-9]+]], Z
21+
; CHECK: ld [[SCRATCH:r[0-9]+]], Z+
2222
; CHECK-NEXT: push [[SCRATCH]]
23-
; CHECK-NEXT: ldd [[SCRATCH]], Z+1
23+
; CHECK-NEXT: ld [[SCRATCH]], Z
2424
; CHECK-NEXT: mov r31, [[SCRATCH]]
2525
; CHECK-NEXT: pop r30
2626

‎test/CodeGen/AVR/pseudo/LDWRdPtr.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ body: |
1717
1818
; CHECK-LABEL: test_ldwrdptr
1919
20-
; CHECK: %r0 = LDRdPtr %r31r30
21-
; CHECK-NEXT: early-clobber %r1 = LDDRdPtrQ %r31r30, 1
20+
; CHECK: %r0, %r31r30 = LDRdPtrPi %r31r30
21+
; CHECK-NEXT: %r1 = LDRdPtr %r31r30
2222
2323
%r1r0 = LDWRdPtr %r31r30
2424
...

‎test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ body: |
1717
1818
; CHECK-LABEL: test_ldwrdptrpd
1919
20-
; CHECK: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
21-
; CHECK-NEXT: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPd killed %r31r30
20+
; CHECK: early-clobber %r1, %r31r30 = LDRdPtrPd killed %r31r30
21+
; CHECK-NEXT: early-clobber %r0, %r31r30 = LDRdPtrPd killed %r31r30
2222
2323
%r1r0, %r31r30 = LDWRdPtrPd %r31r30
2424
...

‎test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ body: |
1717
1818
; CHECK-LABEL: test_ldwrdptrpi
1919
20-
; CHECK: early-clobber %r0, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
21-
; CHECK-NEXT: early-clobber %r1, early-clobber %r31r30 = LDRdPtrPi killed %r31r30
20+
; CHECK: early-clobber %r0, %r31r30 = LDRdPtrPi killed %r31r30
21+
; CHECK-NEXT: early-clobber %r1, %r31r30 = LDRdPtrPi killed %r31r30
2222
2323
%r1r0, %r31r30 = LDWRdPtrPi %r31r30
2424
...

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