Properly recognize workfree enable signals (#1936)

isWorkFreeClockOrResetOrEnable tried to detect constant enable signals,
but we forgot to update this when we changed the representation
of Enable in #1368.

This fixes the register duplication issue seen in #1935

(cherry picked from commit 0415bcf)

Author: leonschoorl

changelog/2021-09-28T18_46_48+02_00_fix_1935

@@ -0,0 +1 @@
+FIXED: Recognize enableGen as workfree and don't duplicate registers [#1935](https://github.com/clash-lang/clash-compiler/issues/1935)

clash-lib/src/Clash/Rewrite/WorkFree.hs

@@ -150,7 +150,7 @@ isWorkFreeClockOrResetOrEnable tcm e =
     case collectArgs e of
       (Prim p,_) -> Just (primName p == "Clash.Transformations.removedArg")
       (Var _, []) -> Just True
-      (Data _, []) -> Just True -- For Enable True/False
+      (Data _, [_dom, Left (stripTicks -> Data _)]) -> Just True -- For Enable True/False
       (Literal _,_) -> Just True
       _ -> Just False
   else

tests/Main.hs

@@ -137,6 +137,7 @@ runClashTest = defaultMain $ clashTestRoot
   [ clashTestGroup "netlist"
     [ clashLibTest ("tests" </> "shouldwork" </> "Netlist") allTargets [] "Identity" "main"
     , NEEDS_PRIMS(clashLibTest ("tests" </> "shouldwork" </> "Netlist") [VHDL] [] "NoDeDup" "main")
+    , clashLibTest ("tests" </> "shouldwork" </> "Netlist") allTargets [] "T1935" "main"
     ]
   , clashTestGroup "examples"
     [ runTest "ALU" def{hdlSim=False}

tests/shouldwork/Netlist/T1935.hs

@@ -0,0 +1,50 @@
+{-# LANGUAGE OverloadedStrings #-}
+module T1935 where
+
+import qualified Prelude as P
+
+import Clash.Prelude
+
+import Clash.Netlist.Types
+import Clash.Backend (Backend)
+
+import Test.Tasty.Clash
+import Test.Tasty.Clash.NetlistTest
+
+import Control.Monad (when)
+
+topEntity
+  :: Clock System
+  -> Reset System
+  -> Signal System (Unsigned 8)
+topEntity clk rst = withClockResetEnable clk rst enableGen x
+  where
+    x :: SystemClockResetEnable => Signal System (Unsigned 8)
+    x = register 4 (x+1)
+
+testPath :: FilePath
+testPath = "tests/shouldwork/Netlist/T1935.hs"
+
+countRegisters :: Component -> Int
+countRegisters (Component _nm _inps _outs ds) =
+  let regs = filter isRegister ds
+   in P.length regs
+ where
+  isRegister (BlackBoxD nm _ _ _ _ _)
+    | nm == "Clash.Signal.Internal.register#" = True
+  isRegister _ = False
+
+mainGeneric :: Backend (TargetToState target) => SBuildTarget target -> IO ()
+mainGeneric hdl = do
+  netlist <- runToNetlistStage hdl id testPath
+  let regs = sum $ fmap (countRegisters . snd) netlist
+  when (regs /= 1) $ error ("Expected 1 register, but found: " <> show regs)
+
+mainVHDL :: IO ()
+mainVHDL = mainGeneric SVHDL
+
+mainVerilog :: IO ()
+mainVerilog = mainGeneric SVerilog
+
+mainSystemVerilog :: IO ()
+mainSystemVerilog = mainGeneric SSystemVerilog

tests/src/Test/Tasty/Clash/NetlistTest.hs

@@ -16,6 +16,7 @@
 --
 module Test.Tasty.Clash.NetlistTest
   ( runToNetlistStage
+  , TargetToState
   ) where
 
 import qualified Prelude as P