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anderssonandersson
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Merge branch '[email protected]' into clk-for-6.13
Merge SAR2130P clock bindings through topic branch, to allow them being used in both clock and DeviceTree branches.
2 parents 04bad0c + 1114810 commit f93cea4

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‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml‎

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enum:
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- qcom,qdu1000-rpmh-clk
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- qcom,sa8775p-rpmh-clk
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- qcom,sar2130p-rpmh-clk
2223
- qcom,sc7180-rpmh-clk
2324
- qcom,sc7280-rpmh-clk
2425
- qcom,sc8180x-rpmh-clk

‎Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on sar2130p
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maintainers:
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- Dmitry Baryshkov <[email protected]>
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description: |
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Qualcomm global clock control module provides the clocks, resets and
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power domains on sar2130p.
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See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
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properties:
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compatible:
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const: qcom,sar2130p-gcc
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clocks:
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items:
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- description: XO reference clock
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- description: Sleep clock
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- description: PCIe 0 pipe clock
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- description: PCIe 1 pipe clock
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- description: Primary USB3 PHY wrapper pipe clock
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protected-clocks:
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maxItems: 240
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power-domains:
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maxItems: 1
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required:
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- compatible
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- clocks
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- '#power-domain-cells'
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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gcc: clock-controller@100000 {
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compatible = "qcom,sar2130p-gcc";
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reg = <0x100000 0x1f4200>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&pcie_0_pipe_clk>,
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<&pcie_1_pipe_clk>,
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<&usb_0_ssphy>;
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power-domains = <&rpmhpd RPMHPD_CX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...

‎Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml‎

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domains on Qualcomm SoCs.
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See also::
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include/dt-bindings/clock/qcom,sar2130p-gpucc.h
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include/dt-bindings/clock/qcom,sm4450-gpucc.h
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include/dt-bindings/clock/qcom,sm8450-gpucc.h
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include/dt-bindings/clock/qcom,sm8550-gpucc.h
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properties:
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compatible:
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enum:
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- qcom,sar2130p-gpucc
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- qcom,sm4450-gpucc
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- qcom,sm8450-gpucc
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- qcom,sm8475-gpucc

‎Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml‎

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properties:
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compatible:
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enum:
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- qcom,sar2130p-dispcc
2526
- qcom,sm8550-dispcc
2627
- qcom,sm8650-dispcc
2728
- qcom,x1e80100-dispcc

‎Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml‎

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compatible:
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items:
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- enum:
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- qcom,sar2130p-tcsr
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- qcom,sm8550-tcsr
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- qcom,sm8650-tcsr
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- qcom,x1e80100-tcsr

‎include/dt-bindings/clock/qcom,sar2130p-gcc.h‎

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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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/*
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* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SAR2130P_H
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/* GCC clocks */
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#define GCC_GPLL0 0
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#define GCC_GPLL0_OUT_EVEN 1
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#define GCC_GPLL1 2
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#define GCC_GPLL9 3
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#define GCC_GPLL9_OUT_EVEN 4
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#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 5
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 6
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#define GCC_BOOT_ROM_AHB_CLK 7
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#define GCC_CAMERA_AHB_CLK 8
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#define GCC_CAMERA_HF_AXI_CLK 9
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#define GCC_CAMERA_SF_AXI_CLK 10
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#define GCC_CAMERA_XO_CLK 11
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#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 12
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 13
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#define GCC_DDRSS_GPU_AXI_CLK 14
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#define GCC_DDRSS_PCIE_SF_CLK 15
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#define GCC_DISP_AHB_CLK 16
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#define GCC_DISP_HF_AXI_CLK 17
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#define GCC_GP1_CLK 18
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#define GCC_GP1_CLK_SRC 19
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#define GCC_GP2_CLK 20
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#define GCC_GP2_CLK_SRC 21
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#define GCC_GP3_CLK 22
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#define GCC_GP3_CLK_SRC 23
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#define GCC_GPU_CFG_AHB_CLK 24
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#define GCC_GPU_GPLL0_CLK_SRC 25
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 26
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#define GCC_GPU_MEMNOC_GFX_CLK 27
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#define GCC_GPU_SNOC_DVM_GFX_CLK 28
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#define GCC_IRIS_SS_HF_AXI1_CLK 29
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#define GCC_IRIS_SS_SPD_AXI1_CLK 30
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#define GCC_PCIE_0_AUX_CLK 31
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#define GCC_PCIE_0_AUX_CLK_SRC 32
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#define GCC_PCIE_0_CFG_AHB_CLK 33
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#define GCC_PCIE_0_MSTR_AXI_CLK 34
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#define GCC_PCIE_0_PHY_RCHNG_CLK 35
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 36
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#define GCC_PCIE_0_PIPE_CLK 37
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#define GCC_PCIE_0_PIPE_CLK_SRC 38
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#define GCC_PCIE_0_SLV_AXI_CLK 39
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 40
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#define GCC_PCIE_1_AUX_CLK 41
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#define GCC_PCIE_1_AUX_CLK_SRC 42
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#define GCC_PCIE_1_CFG_AHB_CLK 43
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#define GCC_PCIE_1_MSTR_AXI_CLK 44
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#define GCC_PCIE_1_PHY_RCHNG_CLK 45
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 46
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#define GCC_PCIE_1_PIPE_CLK 47
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#define GCC_PCIE_1_PIPE_CLK_SRC 48
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#define GCC_PCIE_1_SLV_AXI_CLK 49
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 50
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#define GCC_PDM2_CLK 51
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#define GCC_PDM2_CLK_SRC 52
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#define GCC_PDM_AHB_CLK 53
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#define GCC_PDM_XO4_CLK 54
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 55
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 56
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#define GCC_QMIP_GPU_AHB_CLK 57
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#define GCC_QMIP_PCIE_AHB_CLK 58
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#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 59
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 60
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#define GCC_QMIP_VIDEO_LSR_AHB_CLK 61
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#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 62
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 63
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 64
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#define GCC_QUPV3_WRAP0_CORE_CLK 65
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#define GCC_QUPV3_WRAP0_S0_CLK 66
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 67
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#define GCC_QUPV3_WRAP0_S1_CLK 68
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 69
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#define GCC_QUPV3_WRAP0_S2_CLK 70
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 71
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#define GCC_QUPV3_WRAP0_S3_CLK 72
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 73
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#define GCC_QUPV3_WRAP0_S4_CLK 74
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 75
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#define GCC_QUPV3_WRAP0_S5_CLK 76
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 77
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 78
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#define GCC_QUPV3_WRAP1_CORE_CLK 79
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#define GCC_QUPV3_WRAP1_S0_CLK 80
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 81
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#define GCC_QUPV3_WRAP1_S1_CLK 82
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 83
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#define GCC_QUPV3_WRAP1_S2_CLK 84
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 85
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#define GCC_QUPV3_WRAP1_S3_CLK 86
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 87
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#define GCC_QUPV3_WRAP1_S4_CLK 88
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 89
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#define GCC_QUPV3_WRAP1_S5_CLK 90
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 91
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 92
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 93
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 94
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 95
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#define GCC_SDCC1_AHB_CLK 96
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#define GCC_SDCC1_APPS_CLK 97
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#define GCC_SDCC1_APPS_CLK_SRC 98
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#define GCC_SDCC1_ICE_CORE_CLK 99
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 100
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#define GCC_USB30_PRIM_MASTER_CLK 101
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 102
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 103
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 104
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 105
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#define GCC_USB30_PRIM_SLEEP_CLK 106
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#define GCC_USB3_PRIM_PHY_AUX_CLK 107
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 108
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 109
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 110
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 111
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#define GCC_VIDEO_AHB_CLK 112
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#define GCC_VIDEO_AXI0_CLK 113
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#define GCC_VIDEO_AXI1_CLK 114
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#define GCC_VIDEO_XO_CLK 115
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#define GCC_GPLL4 116
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#define GCC_GPLL5 117
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#define GCC_GPLL7 118
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#define GCC_DDRSS_SPAD_CLK 119
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#define GCC_DDRSS_SPAD_CLK_SRC 120
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#define GCC_VIDEO_AXI0_SREG 121
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#define GCC_VIDEO_AXI1_SREG 122
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#define GCC_IRIS_SS_HF_AXI1_SREG 123
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#define GCC_IRIS_SS_SPD_AXI1_SREG 124
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/* GCC resets */
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#define GCC_CAMERA_BCR 0
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#define GCC_DISPLAY_BCR 1
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#define GCC_GPU_BCR 2
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#define GCC_PCIE_0_BCR 3
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#define GCC_PCIE_0_LINK_DOWN_BCR 4
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5
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#define GCC_PCIE_0_PHY_BCR 6
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7
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#define GCC_PCIE_1_BCR 8
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#define GCC_PCIE_1_LINK_DOWN_BCR 9
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#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10
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#define GCC_PCIE_1_PHY_BCR 11
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#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12
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#define GCC_PCIE_PHY_BCR 13
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#define GCC_PCIE_PHY_CFG_AHB_BCR 14
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#define GCC_PCIE_PHY_COM_BCR 15
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#define GCC_PDM_BCR 16
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#define GCC_QUPV3_WRAPPER_0_BCR 17
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#define GCC_QUPV3_WRAPPER_1_BCR 18
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#define GCC_QUSB2PHY_PRIM_BCR 19
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#define GCC_QUSB2PHY_SEC_BCR 20
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#define GCC_SDCC1_BCR 21
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#define GCC_USB30_PRIM_BCR 22
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#define GCC_USB3_DP_PHY_PRIM_BCR 23
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#define GCC_USB3_DP_PHY_SEC_BCR 24
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#define GCC_USB3_PHY_PRIM_BCR 25
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#define GCC_USB3_PHY_SEC_BCR 26
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#define GCC_USB3PHY_PHY_PRIM_BCR 27
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#define GCC_USB3PHY_PHY_SEC_BCR 28
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#define GCC_VIDEO_AXI0_CLK_ARES 29
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#define GCC_VIDEO_AXI1_CLK_ARES 30
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#define GCC_VIDEO_BCR 31
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#define GCC_IRIS_SS_HF_AXI_CLK_ARES 32
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#define GCC_IRIS_SS_SPD_AXI_CLK_ARES 33
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#define GCC_DDRSS_SPAD_CLK_ARES 34
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/* GCC power domains */
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#define PCIE_0_GDSC 0
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#define PCIE_0_PHY_GDSC 1
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#define PCIE_1_GDSC 2
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#define PCIE_1_PHY_GDSC 3
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#define USB30_PRIM_GDSC 4
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#define USB3_PHY_GDSC 5
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#define HLOS1_VOTE_MM_SNOC_MMU_TBU_HF0_GDSC 6
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#define HLOS1_VOTE_MM_SNOC_MMU_TBU_SF0_GDSC 7
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#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8
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#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9
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#endif

‎include/dt-bindings/clock/qcom,sar2130p-gpucc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
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* Copyright (c) 2024, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SAR2130P_H
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/* GPU_CC clocks */
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#define GPU_CC_AHB_CLK 0
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#define GPU_CC_CRC_AHB_CLK 1
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#define GPU_CC_CX_FF_CLK 2
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#define GPU_CC_CX_GMU_CLK 3
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#define GPU_CC_CXO_AON_CLK 4
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#define GPU_CC_CXO_CLK 5
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#define GPU_CC_FF_CLK_SRC 6
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#define GPU_CC_GMU_CLK_SRC 7
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#define GPU_CC_GX_GMU_CLK 8
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 9
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#define GPU_CC_HUB_AON_CLK 10
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#define GPU_CC_HUB_CLK_SRC 11
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#define GPU_CC_HUB_CX_INT_CLK 12
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#define GPU_CC_MEMNOC_GFX_CLK 13
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#define GPU_CC_PLL0 14
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#define GPU_CC_PLL1 15
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#define GPU_CC_SLEEP_CLK 16
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/* GDSCs */
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#define GPU_GX_GDSC 0
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#define GPU_CX_GDSC 1
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#endif

‎include/dt-bindings/reset/qcom,sar2130p-gpucc.h‎

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024, Linaro Limited
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*/
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#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H
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#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H
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#define GPUCC_GPU_CC_GX_BCR 0
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#define GPUCC_GPU_CC_ACD_BCR 1
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#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 2
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#endif

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