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SVA Monitors
This adds an alternative flow for checking SVA properties, by translating the property into a monitor, which is added to the transition system.
1 parent 8254d29 commit 53d123a

18 files changed

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-7
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CORE
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always1.sv
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--sva-monitor --smv-word-level
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^VAR initial : boolean;$
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^VAR always_activated : boolean;$
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^INIT sva-monitor::initial$
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^INIT !sva-monitor::always_activated$
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^TRANS !next\(sva-monitor::initial\)$
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^TRANS next\(sva-monitor::always_activated\) = sva-monitor::always_active$
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^LTLSPEC G \(sva-monitor::always_active -> FALSE\)$
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^EXIT=0$
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^SIGNAL=0$
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--
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module main(input clk);
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p0: assert property (0);
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endmodule
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CORE
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initial1.sv
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--sva-monitor --smv-word-level
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^EXIT=0$
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^SIGNAL=0$
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--
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module main(input clk);
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initial p0: assert property (0);
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endmodule
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CORE
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s_eventually1.sv
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--sva-monitor --smv-word-level
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^-- Verilog::main\.p0: not converted$
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^EXIT=0$
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^SIGNAL=0$
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--
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module main(input clk);
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p0: assert property (s_eventually 0);
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endmodule
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CORE
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s_nexttime1.sv
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--sva-monitor --smv-word-level
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^VAR initial : boolean;$
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^VAR nexttime_activated : boolean;$
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^INIT sva-monitor::initial$
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^INIT !sva-monitor::nexttime_activated$
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^TRANS !next\(sva-monitor::initial\)$
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^TRANS next\(sva-monitor::nexttime_activated\) = sva-monitor::initial$
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^LTLSPEC G \(sva-monitor::nexttime_activated -> FALSE\)$
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^EXIT=0$
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^SIGNAL=0$
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--
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module main(input clk);
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initial p0: assert property (s_nexttime 0);
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endmodule
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CORE
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sequence1.sv
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--sva-monitor --smv-word-level
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^EXIT=0$
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^SIGNAL=0$
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--
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module main(input clk);
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reg [31:0] x = 0;
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always_ff @(posedge clk)
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x++;
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initial p0: assert property (x==0 ##1 x==1 ##1 x==2);
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endmodule

src/ebmc/Makefile

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@@ -33,6 +33,7 @@ SRC = \
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show_formula_solver.cpp \
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show_properties.cpp \
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show_trans.cpp \
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sva_monitor.cpp \
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transition_system.cpp \
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waveform.cpp \
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#empty line

src/ebmc/ebmc_parse_options.cpp

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@@ -27,6 +27,7 @@ Author: Daniel Kroening, [email protected]
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#include "ranking_function.h"
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#include "show_properties.h"
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#include "show_trans.h"
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#include "sva_monitor.h"
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#include <iostream>
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@@ -216,6 +217,13 @@ int ebmc_parse_optionst::doit()
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auto properties = ebmc_propertiest::from_command_line(
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cmdline, transition_system, ui_message_handler);
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// possibly apply liveness-to-safety
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if(cmdline.isset("liveness-to-safety"))
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liveness_to_safety(transition_system, properties);
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if(cmdline.isset("sva-monitor"))
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sva_monitor(transition_system, properties);
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if(cmdline.isset("smv-word-level"))
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{
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auto filename = cmdline.value_opt("outfile").value_or("-");
@@ -237,10 +245,6 @@ int ebmc_parse_optionst::doit()
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return 0;
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}
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// possibly apply liveness-to-safety
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if(cmdline.isset("liveness-to-safety"))
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liveness_to_safety(transition_system, properties);
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if(cmdline.isset("show-varmap"))
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{
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auto netlist =
@@ -371,6 +375,7 @@ void ebmc_parse_optionst::help()
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" {y--show-properties} \t list the properties in the model\n"
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" {y--property} {uid} \t check the property with given ID\n"
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" {y--liveness-to-safety} \t translate liveness properties to safety properties\n"
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" {y--sva-monitor} \t translate SVA properties into a monitor circuit\n"
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"\n"
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"Methods:\n"
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" {y--k-induction} \t do k-induction with k=bound\n"

src/ebmc/ebmc_parse_options.h

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@@ -49,7 +49,7 @@ class ebmc_parse_optionst:public parse_options_baset
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"(random-traces)(trace-steps):(random-seed):(traces):"
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"(random-trace)(random-waveform)"
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"(bmc-with-assumptions)"
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"(liveness-to-safety)"
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"(liveness-to-safety)(sva-monitor)"
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"I:D:(preprocess)(systemverilog)(vl2smv-extensions)"
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"(warn-implicit-nets)",
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argc,

src/ebmc/output_smv_word_level.cpp

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@@ -119,7 +119,7 @@ smv_invar(const exprt &expr, const namespacet &ns, std::ostream &out)
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if(expr.id() == ID_and)
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{
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for(auto &conjunct : expr.operands())
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smv_initial_states(conjunct, ns, out);
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smv_invar(conjunct, ns, out);
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}
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else if(expr.is_true())
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{
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if(expr.id() == ID_and)
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{
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for(auto &conjunct : expr.operands())
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smv_initial_states(conjunct, ns, out);
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smv_transition_relation(conjunct, ns, out);
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}
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else if(expr.is_true())
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{

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