From 5e23916a636d091fa54f4c38fdc0d70d4c1e4f74 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 26 Jun 2024 07:30:59 -0700 Subject: [PATCH 1/3] Fix the SVE_ComputeAddress* --- src/coreclr/jit/hwintrinsiccodegenarm64.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index ed59e82e5823f2..7577ee2a50ffdc 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -2121,8 +2121,13 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) static_assert_no_msg(AreContiguous(NI_Sve_Compute16BitAddresses, NI_Sve_Compute32BitAddresses, NI_Sve_Compute64BitAddresses, NI_Sve_Compute8BitAddresses)); - GetEmitter()->emitInsSve_R_R_R_I(ins, EA_SCALABLE, targetReg, op1Reg, op2Reg, - (intrin.id - NI_Sve_Compute16BitAddresses), opt, + // imm intrinsic + // 1 NI_Sve_Compute16BitAddresses + // 2 NI_Sve_Compute32BitAddresses + // 3 NI_Sve_Compute64BitAddresses + // 0 NI_Sve_Compute8BitAddresses + size_t imm = ((intrin.id - NI_Sve_Compute16BitAddresses) + 1) % 4; + GetEmitter()->emitInsSve_R_R_R_I(ins, EA_SCALABLE, targetReg, op1Reg, op2Reg, imm, opt, INS_SCALABLE_OPTS_LSL_N); break; } From fe89f4c537dbe472b34dc49ab2a8436fc3d941ef Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 26 Jun 2024 09:23:53 -0700 Subject: [PATCH 2/3] review comments --- src/coreclr/jit/hwintrinsic.h | 4 +++- src/coreclr/jit/hwintrinsicarm64.cpp | 25 +++++++++++++++++++++ src/coreclr/jit/hwintrinsiccodegenarm64.cpp | 13 ++--------- 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/src/coreclr/jit/hwintrinsic.h b/src/coreclr/jit/hwintrinsic.h index 3c63cb79b3c651..1a959ec50e7972 100644 --- a/src/coreclr/jit/hwintrinsic.h +++ b/src/coreclr/jit/hwintrinsic.h @@ -555,8 +555,10 @@ struct HWIntrinsicInfo return static_cast(result); } -#ifdef TARGET_XARCH +#if defined(TARGET_XARCH) static int lookupIval(Compiler* comp, NamedIntrinsic id, var_types simdBaseType); +#elif defined(TARGET_ARM64) + static int lookupIval(NamedIntrinsic id); #endif static bool tryLookupSimdSize(NamedIntrinsic id, unsigned* pSimdSize) diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 765f433e614eee..5aebc897631522 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -152,6 +152,31 @@ CORINFO_InstructionSet HWIntrinsicInfo::lookupIsa(const char* className, const c return InstructionSet_ILLEGAL; } +//------------------------------------------------------------------------ +// lookupIval: Gets a the implicit immediate value for the given intrinsic +// +// Arguments: +// id - The intrinsic for which to get the ival +// +// Return Value: +// The immediate value for the given intrinsic or -1 if none exists +int HWIntrinsicInfo::lookupIval(NamedIntrinsic id) +{ + switch (id) + { + case NI_Sve_Compute16BitAddresses: + return 1; + case NI_Sve_Compute32BitAddresses: + return 2; + case NI_Sve_Compute64BitAddresses: + return 4; + case NI_Sve_Compute8BitAddresses: + return 0; + default: + unreached(); + } + return -1; +} //------------------------------------------------------------------------ // isFullyImplementedIsa: Gets a value that indicates whether the InstructionSet is fully implemented // diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index 7577ee2a50ffdc..3cbf803d3b0763 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -2118,17 +2118,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) case NI_Sve_Compute32BitAddresses: case NI_Sve_Compute64BitAddresses: { - static_assert_no_msg(AreContiguous(NI_Sve_Compute16BitAddresses, NI_Sve_Compute32BitAddresses, - NI_Sve_Compute64BitAddresses, NI_Sve_Compute8BitAddresses)); - - // imm intrinsic - // 1 NI_Sve_Compute16BitAddresses - // 2 NI_Sve_Compute32BitAddresses - // 3 NI_Sve_Compute64BitAddresses - // 0 NI_Sve_Compute8BitAddresses - size_t imm = ((intrin.id - NI_Sve_Compute16BitAddresses) + 1) % 4; - GetEmitter()->emitInsSve_R_R_R_I(ins, EA_SCALABLE, targetReg, op1Reg, op2Reg, imm, opt, - INS_SCALABLE_OPTS_LSL_N); + GetEmitter()->emitInsSve_R_R_R_I(ins, EA_SCALABLE, targetReg, op1Reg, op2Reg, + HWIntrinsicInfo::lookupIval(intrin.id), opt, INS_SCALABLE_OPTS_LSL_N); break; } From c4997abf7ca640dba0fd877ee9fccbf3cb8dab4e Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 26 Jun 2024 14:16:49 -0700 Subject: [PATCH 3/3] fix the typo --- src/coreclr/jit/hwintrinsicarm64.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 5aebc897631522..b63c872db29a9f 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -169,7 +169,7 @@ int HWIntrinsicInfo::lookupIval(NamedIntrinsic id) case NI_Sve_Compute32BitAddresses: return 2; case NI_Sve_Compute64BitAddresses: - return 4; + return 3; case NI_Sve_Compute8BitAddresses: return 0; default: