From 98baa883035af725b9435968707e831109e5b64c Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Mon, 22 Feb 2021 17:41:44 -0800 Subject: [PATCH 1/3] [Windows x86] Fix isByteReg() assert The change is similar to the one done in https://github.com/dotnet/runtime/pull/46567. If the type if `BYTE`, the use byte regs. Fixes the following failures: https://helixre8s23ayyeko0k025g8.blob.core.windows.net/dotnet-runtime-refs-pull-47307-head-c9ab37658a344842be/System.Linq.Queryable.Tests/console.2ce37104.log?sv=2019-07-07&se=2021-03-10T08%3A39%3A45Z&sr=c&sp=rl&sig=GdS1KlEkJHVcKz7lwpZeszudWYokZpr%2Bt7IGv4c61co%3D https://helixre8s23ayyeko0k025g8.blob.core.windows.net/dotnet-runtime-refs-pull-47307-head-c9ab37658a344842be/System.Linq.Tests/console.4bc4fd10.log?sv=2019-07-07&se=2021-03-10T08%3A39%3A45Z&sr=c&sp=rl&sig=GdS1KlEkJHVcKz7lwpZeszudWYokZpr%2Bt7IGv4c61co%3D --- src/coreclr/jit/lsrabuild.cpp | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/lsrabuild.cpp b/src/coreclr/jit/lsrabuild.cpp index 06b6799c182400..88430f70fe771a 100644 --- a/src/coreclr/jit/lsrabuild.cpp +++ b/src/coreclr/jit/lsrabuild.cpp @@ -3207,8 +3207,24 @@ void LinearScan::BuildStoreLocDef(GenTreeLclVarCommon* storeLoc, srcInterval->assignRelatedInterval(varDefInterval); } } - RefPosition* def = - newRefPosition(varDefInterval, currentLoc + 1, RefTypeDef, storeLoc, allRegs(varDsc->TypeGet()), index); + + regMaskTP defCandidates = RBM_NONE; + var_types type = varDsc->TypeGet(); + +#ifdef TARGET_X86 + if (varTypeIsByte(type)) + { + defCandidates = allByteRegs(); + } + else + { + defCandidates = allRegs(type); + } +#else + defCandidates = allRegs(type); +#endif // TARGET_X86 + + RefPosition* def = newRefPosition(varDefInterval, currentLoc + 1, RefTypeDef, storeLoc, defCandidates, index); if (varDefInterval->isWriteThru) { // We always make write-thru defs reg-optional, as we can store them if they don't From 91d9602556a06ee7e480e2730b3802ccde560ebe Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Tue, 2 Mar 2021 22:33:07 -0800 Subject: [PATCH 2/3] add an assert in allRegs() --- src/coreclr/jit/lsra.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index 996dcac0dd9f91..e9df712e03d76c 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -238,6 +238,8 @@ BasicBlock::weight_t LinearScan::getWeight(RefPosition* refPos) // in time (more of a 'bank' of registers). regMaskTP LinearScan::allRegs(RegisterType rt) { + assert(rt != TYP_BYTE); + if (rt == TYP_FLOAT) { return availableFloatRegs; From 956e75654b3012f56144b9535d6729e1aaade32c Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 3 Mar 2021 00:04:13 -0800 Subject: [PATCH 3/3] Revert "add an assert in allRegs()" This reverts commit 91d9602556a06ee7e480e2730b3802ccde560ebe. --- src/coreclr/jit/lsra.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index e9df712e03d76c..996dcac0dd9f91 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -238,8 +238,6 @@ BasicBlock::weight_t LinearScan::getWeight(RefPosition* refPos) // in time (more of a 'bank' of registers). regMaskTP LinearScan::allRegs(RegisterType rt) { - assert(rt != TYP_BYTE); - if (rt == TYP_FLOAT) { return availableFloatRegs;