Inverted I2S SCLK?!?

[Locutus74]

Version: 5.0.0
Board: genuine Pi Pico2 (without WiFi)
ADC/DAC-Board: Digilent Pmod I2S2 I²S Soundcard (Cirrus Logic chips)

I'm struggling with using a Digilent Pmod I²C module (for full duplex I/O) with a Pi Pico2. It seems like my SCLK is inverted?

I have no idea how this even can happen? Setup is like this:

void setup()
{
  // choose a very high clock rate were all required clk-sigs are obtainable by integer-division
  // we use 31.25 kHz which suits 256 MHz 
  set_sys_clock_khz( 256000000 / 1000 , true); // 256 MHz

  // setup pins: must be run before setFrequency() and i2s.begin()
  i2s.setDOUT(2);
  i2s.setDIN(3);
  i2s.setBCLK(0); // LRCLK = BCLK + 1
  i2s.setMCLK(15);
  i2s.setMCLKmult(256); 
  //i2s.setMCLKmult(384); // must use 240 MHz sysclk for 24 bit samples...

  //i2s.setLSBJFormat();
  
  i2s.setBitsPerSample(16);
  i2s.setFrequency( 31250 );
    
  i2s.setBuffers(4, bufferSizeSamples, 0); // 4 DMA buffers with 256 samples each

  i2s.onTransmit( onTransmitCallback );
  i2s.onReceive( onReceiveCallback );

  // prefill Buffer (maybe important?!?)
  while( i2s.availableForWrite() )
  {
    i2s.write( (uint32_t)0, false );
  }
  
  i2s.begin();
  ...
  ...

An audio recording looks like this:

Am I doing something obviously wrong here?

All the best and many thanks,
Stefan

[earlephilhower]

The I2S code here has a lot of different users and eyes on it, so I'm confident there's no inversion on the bit clock and the signals generated are good under normal conditions.

That DAC's been EOL for many years per Cirrus Logic's website. I'm surprised anyone is still shipping it, but good on them for leaving the datasheet up.

The Pico2 is spec'd for 150MHz operation and you're running it at 256MHz, a 1.7x overclock. So there's always the possibility that things like parts of the PIO or clock subsystem don't work stably at that range.

Since this is one very specific set of hardware and not something others can duplicate, I would recommend simplifying things and a logic analyzer. If you have one, grab the I2S out pins and have pulseview or Logic decode the I2S stream for sanity checking.

You should also grab the MCLK with the logic analyzer and see if there's anything special needed in this chip for it. Most DACs I've seen don't really care about the phase relationship of MCLK and BCLK/LRCLK/DIN, so MCLK generation here is free-running and not sync'd to any other I2S signals. If this specific DAC needs MCLK and BCLK all aligned then you're going to need to write some add'l code to synchronize the 2 PIOS generating them.

Your analog waveform looks like the DAC isn't lining up with the input digital bitstream and you're getting bits shifted from other samples into the current one (so you'll end up with sign-flipped data/etc.)

31.25khz is an odd output frequency, too. 32K is a common one and listed in the datasheet. I know some other DACs don't function properly at odd clocks (some hardcoded filters/etc.), maybe this one is like that. You could bump up to exactly 32K and see if there's any difference.

[Locutus74]

Here is the MCVE. Inside there is the .ino I used to capture the pulseview file (also contained in there).
I2SLoopback_Buffer_Test.zip

[earlephilhower]

Thanks, got it! Much easier to examine now.

Looking at the MCVE I see the difference: You're using a bidir I2S vs. the I2S output-only mode. That was added in #2775 and uses a completely different PIO program. It's possible that what worked for the user who contributed it isn't working for you due to setup/hold time differences in your config if the bidir PIO does output on the wrong edge.

I'll take a look on my end, but on your end unless you're our of pins then why not make 2 separate I2S instances, one input and one output, and see if that gets you going. You'll need to separate out both I2S BCLK and LRCLKs (the MCLK could be shared for input and output since it's free-running and not related to the data signals...so just have 1 I2S with MCLK).

[Locutus74]

Will try this.

[earlephilhower]

Moved to #3116. Simple code inspection does show DOUT coming on the 0->1 edge

    mov x, y         side 0b00 [1]
left1:
    out pins, 1      side 0b01
    in pins, 1       side 0b01
    jmp x--, left1   side 0b00 [1]

[earlephilhower]

@Locutus74 please try #3117 which I have running now with a loopback cable on a pico2. The write waveform now looks good edge-wise, and the loopback read seems to be inline, too.

[Locutus74]

I tried 86a840f and a60ba2b. I did so rather extensively with I²S-out and not so extensively with I²S-in. It seems to work perfectly, now. I will do some more tests this weekend as I wanted to implement some audio-fx with it. So maybe I'll find something more on the input side, who knows. But for now everything seems to work very fine!

Many thanks!
Stefan