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hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)
This patch realize the EIOINTC interrupt controller. Signed-off-by: Xiaojuan Yang <[email protected]> Signed-off-by: Song Gao <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
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‎hw/intc/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -99,3 +99,6 @@ config LOONGARCH_PCH_MSI
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select MSI_NONBROKEN
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bool
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select UNIMP
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config LOONGARCH_EXTIOI
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bool

‎hw/intc/loongarch_extioi.c

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@@ -0,0 +1,312 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Loongson 3A5000 ext interrupt controller emulation
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*
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* Copyright (C) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/loongarch/virt.h"
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#include "hw/qdev-properties.h"
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#include "exec/address-spaces.h"
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#include "hw/intc/loongarch_extioi.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static void extioi_update_irq(LoongArchExtIOI *s, int irq, int level)
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{
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int ipnum, cpu, found, irq_index, irq_mask;
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ipnum = s->sw_ipmap[irq / 32];
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cpu = s->sw_coremap[irq];
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irq_index = irq / 32;
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irq_mask = 1 << (irq & 0x1f);
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if (level) {
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/* if not enable return false */
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if (((s->enable[irq_index]) & irq_mask) == 0) {
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return;
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}
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s->coreisr[cpu][irq_index] |= irq_mask;
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found = find_first_bit(s->sw_isr[cpu][ipnum], EXTIOI_IRQS);
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set_bit(irq, s->sw_isr[cpu][ipnum]);
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if (found < EXTIOI_IRQS) {
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/* other irq is handling, need not update parent irq level */
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return;
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}
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} else {
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s->coreisr[cpu][irq_index] &= ~irq_mask;
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clear_bit(irq, s->sw_isr[cpu][ipnum]);
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found = find_first_bit(s->sw_isr[cpu][ipnum], EXTIOI_IRQS);
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if (found < EXTIOI_IRQS) {
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/* other irq is handling, need not update parent irq level */
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return;
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}
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}
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qemu_set_irq(s->parent_irq[cpu][ipnum], level);
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}
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static void extioi_setirq(void *opaque, int irq, int level)
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{
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LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
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trace_loongarch_extioi_setirq(irq, level);
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if (level) {
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/*
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* s->isr should be used in vmstate structure,
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* but it not support 'unsigned long',
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* so we have to switch it.
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*/
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set_bit(irq, (unsigned long *)s->isr);
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} else {
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clear_bit(irq, (unsigned long *)s->isr);
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}
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extioi_update_irq(s, irq, level);
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}
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static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
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{
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LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
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unsigned long offset = addr & 0xffff;
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uint32_t index, cpu, ret = 0;
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switch (offset) {
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case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
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index = (offset - EXTIOI_NODETYPE_START) >> 2;
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ret = s->nodetype[index];
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break;
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case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
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index = (offset - EXTIOI_IPMAP_START) >> 2;
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ret = s->ipmap[index];
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break;
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case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
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index = (offset - EXTIOI_ENABLE_START) >> 2;
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ret = s->enable[index];
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break;
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case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
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index = (offset - EXTIOI_BOUNCE_START) >> 2;
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ret = s->bounce[index];
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break;
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case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
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index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
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cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
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ret = s->coreisr[cpu][index];
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break;
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case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
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index = (offset - EXTIOI_COREMAP_START) >> 2;
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ret = s->coremap[index];
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break;
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default:
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break;
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}
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trace_loongarch_extioi_readw(addr, ret);
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return ret;
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}
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static inline void extioi_enable_irq(LoongArchExtIOI *s, int index,\
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uint32_t mask, int level)
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{
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uint32_t val;
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int irq;
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val = mask & s->isr[index];
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irq = ctz32(val);
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while (irq != 32) {
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/*
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* enable bit change from 0 to 1,
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* need to update irq by pending bits
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*/
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extioi_update_irq(s, irq + index * 32, level);
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val &= ~(1 << irq);
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irq = ctz32(val);
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}
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}
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static void extioi_writew(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
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int i, cpu, index, old_data, irq;
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uint32_t offset;
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trace_loongarch_extioi_writew(addr, val);
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offset = addr & 0xffff;
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switch (offset) {
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case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
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index = (offset - EXTIOI_NODETYPE_START) >> 2;
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s->nodetype[index] = val;
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break;
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case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of intr driver, need not update upper irq level
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*/
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index = (offset - EXTIOI_IPMAP_START) >> 2;
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s->ipmap[index] = val;
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/*
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* loongarch only support little endian,
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* so we paresd the value with little endian.
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*/
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val = cpu_to_le64(val);
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for (i = 0; i < 4; i++) {
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uint8_t ipnum;
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ipnum = val & 0xff;
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ipnum = ctz32(ipnum);
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ipnum = (ipnum >= 4) ? 0 : ipnum;
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s->sw_ipmap[index * 4 + i] = ipnum;
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val = val >> 8;
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}
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break;
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case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
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index = (offset - EXTIOI_ENABLE_START) >> 2;
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old_data = s->enable[index];
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s->enable[index] = val;
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/* unmask irq */
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val = s->enable[index] & ~old_data;
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extioi_enable_irq(s, index, val, 1);
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/* mask irq */
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val = ~s->enable[index] & old_data;
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extioi_enable_irq(s, index, val, 0);
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break;
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case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
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/* do not emulate hw bounced irq routing */
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index = (offset - EXTIOI_BOUNCE_START) >> 2;
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s->bounce[index] = val;
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break;
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case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
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index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
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cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
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old_data = s->coreisr[cpu][index];
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s->coreisr[cpu][index] = old_data & ~val;
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/* write 1 to clear interrrupt */
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old_data &= val;
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irq = ctz32(old_data);
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while (irq != 32) {
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extioi_update_irq(s, irq + index * 32, 0);
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old_data &= ~(1 << irq);
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irq = ctz32(old_data);
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}
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break;
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case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
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irq = offset - EXTIOI_COREMAP_START;
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index = irq / 4;
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s->coremap[index] = val;
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/*
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* loongarch only support little endian,
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* so we paresd the value with little endian.
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*/
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val = cpu_to_le64(val);
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for (i = 0; i < 4; i++) {
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cpu = val & 0xff;
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cpu = ctz32(cpu);
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cpu = (cpu >= 4) ? 0 : cpu;
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val = val >> 8;
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if (s->sw_coremap[irq + i] == cpu) {
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continue;
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}
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if (test_bit(irq, (unsigned long *)s->isr)) {
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/*
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* lower irq at old cpu and raise irq at new cpu
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*/
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extioi_update_irq(s, irq + i, 0);
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s->sw_coremap[irq + i] = cpu;
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extioi_update_irq(s, irq + i, 1);
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} else {
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s->sw_coremap[irq + i] = cpu;
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}
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}
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break;
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default:
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break;
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}
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}
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static const MemoryRegionOps extioi_ops = {
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.read = extioi_readw,
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.write = extioi_writew,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.valid.min_access_size = 4,
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.valid.max_access_size = 8,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static const VMStateDescription vmstate_loongarch_extioi = {
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.name = TYPE_LOONGARCH_EXTIOI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
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VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
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EXTIOI_IRQS_GROUP_COUNT),
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VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
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EXTIOI_IRQS_NODETYPE_COUNT / 2),
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VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, EXTIOI_IRQS / 32),
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VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOI, EXTIOI_IRQS / 32),
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VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE / 4),
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VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
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VMSTATE_UINT8_ARRAY(sw_ipmap, LoongArchExtIOI, EXTIOI_IRQS_IPMAP_SIZE),
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VMSTATE_UINT8_ARRAY(sw_coremap, LoongArchExtIOI, EXTIOI_IRQS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void loongarch_extioi_instance_init(Object *obj)
268+
{
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj);
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int i, cpu, pin;
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273+
for (i = 0; i < EXTIOI_IRQS; i++) {
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
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}
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qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
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for (cpu = 0; cpu < LOONGARCH_MAX_VCPUS; cpu++) {
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memory_region_init_io(&s->extioi_iocsr_mem[cpu], OBJECT(s), &extioi_ops,
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s, "extioi_iocsr", 0x900);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_iocsr_mem[cpu]);
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for (pin = 0; pin < LS3A_INTC_IP; pin++) {
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qdev_init_gpio_out(DEVICE(obj), &s->parent_irq[cpu][pin], 1);
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}
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}
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memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops,
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s, "extioi_system_mem", 0x900);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_system_mem);
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}
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static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
293+
{
294+
DeviceClass *dc = DEVICE_CLASS(klass);
295+
296+
dc->vmsd = &vmstate_loongarch_extioi;
297+
}
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static const TypeInfo loongarch_extioi_info = {
300+
.name = TYPE_LOONGARCH_EXTIOI,
301+
.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = loongarch_extioi_instance_init,
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.instance_size = sizeof(struct LoongArchExtIOI),
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.class_init = loongarch_extioi_class_init,
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};
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static void loongarch_extioi_register_types(void)
308+
{
309+
type_register_static(&loongarch_extioi_info);
310+
}
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312+
type_init(loongarch_extioi_register_types)

‎hw/intc/meson.build

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Original file line numberDiff line numberDiff line change
@@ -66,3 +66,4 @@ specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true: files('loongarch_ipi.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true: files('loongarch_pch_pic.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true: files('loongarch_pch_msi.c'))
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specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true: files('loongarch_extioi.c'))

‎hw/intc/trace-events

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Original file line numberDiff line numberDiff line change
@@ -303,3 +303,9 @@ loongarch_pch_pic_writeb(unsigned size, uint64_t addr, uint64_t val) "size: %u a
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# loongarch_pch_msi.c
305305
loongarch_msi_set_irq(int irq_num) "set msi irq %d"
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# loongarch_extioi.c
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loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
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loongarch_extioi_readw(uint64_t addr, uint32_t val) "addr: 0x%"PRIx64 "val: 0x%x"
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loongarch_extioi_writew(uint64_t addr, uint64_t val) "addr: 0x%"PRIx64 "val: 0x%" PRIx64
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‎hw/loongarch/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -5,3 +5,4 @@ config LOONGARCH_VIRT
55
select LOONGARCH_IPI
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select LOONGARCH_PCH_PIC
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select LOONGARCH_PCH_MSI
8+
select LOONGARCH_EXTIOI

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