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fhahnfhahn
committedMar 1, 2024
[SROA] Use !tbaa instead of !tbaa.struct if op matches field. (llvm#81289)
If a split memory access introduced by SROA accesses precisely a single field of the original operation's !tbaa.struct, use the !tbaa tag for the accessed field directly instead of the full !tbaa.struct. InstCombine already had a similar logic. Motivation for this and follow-on patches is to improve codegen for libc++, where using memcpy limits optimizations, like vectorization for code iteration over std::vector<std::complex<float>>: https://godbolt.org/z/f3vqYos3c Depends on llvm#81285. (cherry-picked from 53c0e80)
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‎llvm/include/llvm/IR/Metadata.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -740,6 +740,9 @@ struct AAMDNodes {
740740
/// If his AAMDNode has !tbaa.struct and \p AccessSize matches the size of the
741741
/// field at offset 0, get the TBAA tag describing the accessed field.
742742
AAMDNodes adjustForAccess(unsigned AccessSize);
743+
AAMDNodes adjustForAccess(size_t Offset, Type *AccessTy,
744+
const DataLayout &DL);
745+
AAMDNodes adjustForAccess(size_t Offset, unsigned AccessSize);
743746
};
744747

745748
// Specialize DenseMapInfo for AAMDNodes.

‎llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -834,3 +834,20 @@ AAMDNodes AAMDNodes::adjustForAccess(unsigned AccessSize) {
834834
}
835835
return New;
836836
}
837+
838+
AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, Type *AccessTy,
839+
const DataLayout &DL) {
840+
AAMDNodes New = shift(Offset);
841+
if (!DL.typeSizeEqualsStoreSize(AccessTy))
842+
return New;
843+
TypeSize Size = DL.getTypeStoreSize(AccessTy);
844+
if (Size.isScalable())
845+
return New;
846+
847+
return New.adjustForAccess(Size.getKnownMinValue());
848+
}
849+
850+
AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, unsigned AccessSize) {
851+
AAMDNodes New = shift(Offset);
852+
return New.adjustForAccess(AccessSize);
853+
}

‎llvm/lib/Transforms/Scalar/SROA.cpp

Lines changed: 33 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2715,7 +2715,8 @@ class llvm::sroa::AllocaSliceRewriter
27152715

27162716
// Do this after copyMetadataForLoad() to preserve the TBAA shift.
27172717
if (AATags)
2718-
NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2718+
NewLI->setAAMetadata(AATags.adjustForAccess(
2719+
NewBeginOffset - BeginOffset, NewLI->getType(), DL));
27192720

27202721
// Try to preserve nonnull metadata
27212722
V = NewLI;
@@ -2736,8 +2737,11 @@ class llvm::sroa::AllocaSliceRewriter
27362737
LoadInst *NewLI =
27372738
IRB.CreateAlignedLoad(TargetTy, getNewAllocaSlicePtr(IRB, LTy),
27382739
getSliceAlign(), LI.isVolatile(), LI.getName());
2740+
27392741
if (AATags)
2740-
NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2742+
NewLI->setAAMetadata(AATags.adjustForAccess(
2743+
NewBeginOffset - BeginOffset, NewLI->getType(), DL));
2744+
27412745
if (LI.isVolatile())
27422746
NewLI->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
27432747
NewLI->copyMetadata(LI, {LLVMContext::MD_mem_parallel_loop_access,
@@ -2807,7 +2811,8 @@ class llvm::sroa::AllocaSliceRewriter
28072811
Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
28082812
LLVMContext::MD_access_group});
28092813
if (AATags)
2810-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2814+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
2815+
V->getType(), DL));
28112816
Pass.DeadInsts.push_back(&SI);
28122817

28132818
// NOTE: Careful to use OrigV rather than V.
@@ -2834,7 +2839,8 @@ class llvm::sroa::AllocaSliceRewriter
28342839
Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
28352840
LLVMContext::MD_access_group});
28362841
if (AATags)
2837-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2842+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
2843+
V->getType(), DL));
28382844

28392845
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &SI,
28402846
Store, Store->getPointerOperand(),
@@ -2910,7 +2916,8 @@ class llvm::sroa::AllocaSliceRewriter
29102916
NewSI->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
29112917
LLVMContext::MD_access_group});
29122918
if (AATags)
2913-
NewSI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2919+
NewSI->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
2920+
V->getType(), DL));
29142921
if (SI.isVolatile())
29152922
NewSI->setAtomic(SI.getOrdering(), SI.getSyncScopeID());
29162923
if (NewSI->isAtomic())
@@ -3011,12 +3018,14 @@ class llvm::sroa::AllocaSliceRewriter
30113018
// a single value type, just emit a memset.
30123019
if (!CanContinue) {
30133020
Type *SizeTy = II.getLength()->getType();
3014-
Constant *Size = ConstantInt::get(SizeTy, NewEndOffset - NewBeginOffset);
3021+
unsigned Sz = NewEndOffset - NewBeginOffset;
3022+
Constant *Size = ConstantInt::get(SizeTy, Sz);
30153023
MemIntrinsic *New = cast<MemIntrinsic>(IRB.CreateMemSet(
30163024
getNewAllocaSlicePtr(IRB, OldPtr->getType()), II.getValue(), Size,
30173025
MaybeAlign(getSliceAlign()), II.isVolatile()));
30183026
if (AATags)
3019-
New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3027+
New->setAAMetadata(
3028+
AATags.adjustForAccess(NewBeginOffset - BeginOffset, Sz));
30203029

30213030
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &II,
30223031
New, New->getRawDest(), nullptr, DL);
@@ -3092,7 +3101,8 @@ class llvm::sroa::AllocaSliceRewriter
30923101
New->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
30933102
LLVMContext::MD_access_group});
30943103
if (AATags)
3095-
New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3104+
New->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3105+
V->getType(), DL));
30963106

30973107
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &II,
30983108
New, New->getPointerOperand(), V, DL);
@@ -3296,7 +3306,8 @@ class llvm::sroa::AllocaSliceRewriter
32963306
Load->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
32973307
LLVMContext::MD_access_group});
32983308
if (AATags)
3299-
Load->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3309+
Load->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3310+
Load->getType(), DL));
33003311
Src = Load;
33013312
}
33023313

@@ -3318,7 +3329,8 @@ class llvm::sroa::AllocaSliceRewriter
33183329
Store->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
33193330
LLVMContext::MD_access_group});
33203331
if (AATags)
3321-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3332+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3333+
Src->getType(), DL));
33223334

33233335
APInt Offset(DL.getIndexTypeSizeInBits(DstPtr->getType()), 0);
33243336
if (IsDest) {
@@ -3643,7 +3655,8 @@ class AggLoadStoreRewriter : public InstVisitor<AggLoadStoreRewriter, bool> {
36433655
DL.getIndexSizeInBits(Ptr->getType()->getPointerAddressSpace()), 0);
36443656
if (AATags &&
36453657
GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset))
3646-
Load->setAAMetadata(AATags.shift(Offset.getZExtValue()));
3658+
Load->setAAMetadata(
3659+
AATags.adjustForAccess(Offset.getZExtValue(), Load->getType(), DL));
36473660

36483661
Agg = IRB.CreateInsertValue(Agg, Load, Indices, Name + ".insert");
36493662
LLVM_DEBUG(dbgs() << " to: " << *Load << "\n");
@@ -3694,8 +3707,10 @@ class AggLoadStoreRewriter : public InstVisitor<AggLoadStoreRewriter, bool> {
36943707
APInt Offset(
36953708
DL.getIndexSizeInBits(Ptr->getType()->getPointerAddressSpace()), 0);
36963709
GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset);
3697-
if (AATags)
3698-
Store->setAAMetadata(AATags.shift(Offset.getZExtValue()));
3710+
if (AATags) {
3711+
Store->setAAMetadata(AATags.adjustForAccess(
3712+
Offset.getZExtValue(), ExtractValue->getType(), DL));
3713+
}
36993714

37003715
// migrateDebugInfo requires the base Alloca. Walk to it from this gep.
37013716
// If we cannot (because there's an intervening non-const or unbounded
@@ -4317,6 +4332,7 @@ bool SROAPass::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
43174332

43184333
Value *StoreBasePtr = SI->getPointerOperand();
43194334
IRB.SetInsertPoint(SI);
4335+
AAMDNodes AATags = SI->getAAMetadata();
43204336

43214337
LLVM_DEBUG(dbgs() << " Splitting store of load: " << *SI << "\n");
43224338

@@ -4337,6 +4353,10 @@ bool SROAPass::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
43374353
PStore->copyMetadata(*SI, {LLVMContext::MD_mem_parallel_loop_access,
43384354
LLVMContext::MD_access_group,
43394355
LLVMContext::MD_DIAssignID});
4356+
4357+
if (AATags)
4358+
PStore->setAAMetadata(
4359+
AATags.adjustForAccess(PartOffset, PLoad->getType(), DL));
43404360
LLVM_DEBUG(dbgs() << " +" << PartOffset << ":" << *PStore << "\n");
43414361
}
43424362

‎llvm/test/Transforms/SROA/tbaa-struct2.ll

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,9 @@ define double @bar(ptr %wishart) {
1313
; CHECK-NEXT: [[TMP_SROA_3:%.*]] = alloca [4 x i8], align 4
1414
; CHECK-NEXT: [[TMP_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[WISHART:%.*]], align 8, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
1515
; CHECK-NEXT: [[TMP_SROA_2_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 8
16-
; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
16+
; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa [[TBAA5:![0-9]+]]
1717
; CHECK-NEXT: [[TMP_SROA_3_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 12
18-
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT8:![0-9]+]]
18+
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
1919
; CHECK-NEXT: [[CALL:%.*]] = call double @subcall(double [[TMP_SROA_0_0_COPYLOAD]], i32 [[TMP_SROA_2_0_COPYLOAD]])
2020
; CHECK-NEXT: ret double [[CALL]]
2121
;
@@ -38,15 +38,14 @@ define double @bar(ptr %wishart) {
3838
;.
3939
; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
4040
;.
41-
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, !1, i64 8, i64 4, !5}
42-
; CHECK: [[META1:![0-9]+]] = !{!2, !2, i64 0}
43-
; CHECK: [[META2:![0-9]+]] = !{!"double", !3, i64 0}
44-
; CHECK: [[META3:![0-9]+]] = !{!"omnipotent char", !4, i64 0}
45-
; CHECK: [[META4:![0-9]+]] = !{!"Simple C++ TBAA"}
46-
; CHECK: [[META5:![0-9]+]] = !{!6, !6, i64 0}
47-
; CHECK: [[META6:![0-9]+]] = !{!"int", !3, i64 0}
48-
; CHECK: [[TBAA_STRUCT7]] = !{i64 0, i64 4, !5}
49-
; CHECK: [[TBAA_STRUCT8]] = !{}
41+
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, [[META1:![0-9]+]], i64 8, i64 4, [[TBAA5]]}
42+
; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
43+
; CHECK: [[META2]] = !{!"double", [[META3:![0-9]+]], i64 0}
44+
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
45+
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
46+
; CHECK: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
47+
; CHECK: [[META6]] = !{!"int", [[META3]], i64 0}
48+
; CHECK: [[TBAA_STRUCT7]] = !{}
5049
;.
5150
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
5251
; CHECK-MODIFY-CFG: {{.*}}

‎llvm/test/Transforms/SROA/tbaa-struct3.ll

Lines changed: 38 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,9 @@ define void @load_store_transfer_split_struct_tbaa_2_float(ptr dereferenceable(2
1313
; CHECK-NEXT: entry:
1414
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[A]] to i32
1515
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[B]] to i32
16-
; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4
16+
; CHECK-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
1717
; CHECK-NEXT: [[RES_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[RES]], i64 4
18-
; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4
18+
; CHECK-NEXT: store i32 [[TMP1]], ptr [[RES_SROA_IDX]], align 4, !tbaa [[TBAA1:![0-9]+]]
1919
; CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[RES]], align 8
2020
; CHECK-NEXT: ret void
2121
;
@@ -35,9 +35,9 @@ define void @memcpy_transfer(ptr dereferenceable(24) %res, float %a, float %b) {
3535
; CHECK-SAME: ptr dereferenceable(24) [[RES:%.*]], float [[A:%.*]], float [[B:%.*]]) {
3636
; CHECK-NEXT: entry:
3737
; CHECK-NEXT: [[L_PTR:%.*]] = load ptr, ptr [[RES]], align 8
38-
; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
38+
; CHECK-NEXT: store float [[A]], ptr [[L_PTR]], align 1, !tbaa.struct [[TBAA_STRUCT0]]
3939
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
40-
; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
40+
; CHECK-NEXT: store float [[B]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa [[TBAA1]]
4141
; CHECK-NEXT: ret void
4242
;
4343
entry:
@@ -59,7 +59,7 @@ define void @memcpy_transfer_tbaa_field_and_size_do_not_align(ptr dereferenceabl
5959
; CHECK-NEXT: [[TMP_SROA_2_0_L_PTR_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[L_PTR]], i64 4
6060
; CHECK-NEXT: [[TMP0:%.*]] = bitcast float [[B]] to i32
6161
; CHECK-NEXT: [[TMP_SROA_2_0_EXTRACT_TRUNC:%.*]] = trunc i32 [[TMP0]] to i16
62-
; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5]]
62+
; CHECK-NEXT: store i16 [[TMP_SROA_2_0_EXTRACT_TRUNC]], ptr [[TMP_SROA_2_0_L_PTR_SROA_IDX]], align 1, !tbaa.struct [[TBAA_STRUCT5:![0-9]+]]
6363
; CHECK-NEXT: ret void
6464
;
6565
entry:
@@ -103,7 +103,7 @@ define void @store_vector_part_first(ptr %y2, float %f) {
103103
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
104104
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT6:![0-9]+]]
105105
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 8
106-
; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT5]]
106+
; CHECK-NEXT: store float [[F]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 8, !tbaa [[TBAA1]]
107107
; CHECK-NEXT: ret void
108108
;
109109
%x7 = alloca { float, float, float, float }
@@ -121,7 +121,7 @@ define void @store_vector_part_second(ptr %y2, float %f) {
121121
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
122122
; CHECK-NEXT: store float [[F]], ptr [[Y2]], align 8, !tbaa.struct [[TBAA_STRUCT9:![0-9]+]]
123123
; CHECK-NEXT: [[X7_SROA_2_0_Y2_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[Y2]], i64 4
124-
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
124+
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[X7_SROA_2_0_Y2_SROA_IDX]], align 4, !tbaa [[TBAA7:![0-9]+]]
125125
; CHECK-NEXT: ret void
126126
;
127127
%x7 = alloca { float, float, float, float }
@@ -137,7 +137,7 @@ define void @store_vector_single(ptr %y2, float %f) {
137137
; CHECK-LABEL: define void @store_vector_single(
138138
; CHECK-SAME: ptr [[Y2:%.*]], float [[F:%.*]]) {
139139
; CHECK-NEXT: [[V_1:%.*]] = call <2 x float> @foo(ptr [[Y2]])
140-
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
140+
; CHECK-NEXT: store <2 x float> [[V_1]], ptr [[Y2]], align 4, !tbaa.struct [[TBAA_STRUCT10:![0-9]+]]
141141
; CHECK-NEXT: ret void
142142
;
143143
%x7 = alloca { float, float }
@@ -164,8 +164,8 @@ define void @memset(ptr %dst, ptr align 8 %src) {
164164
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_0_SRC_SROA_IDX]], i32 10, i1 false)
165165
; CHECK-NEXT: store i16 1, ptr [[A_SROA_3]], align 2
166166
; CHECK-NEXT: [[A_SROA_0_1_A_1_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 1
167-
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
168-
; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
167+
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_1_A_1_SROA_IDX2]], i8 42, i32 6, i1 false), !tbaa.struct [[TBAA_STRUCT11:![0-9]+]]
168+
; CHECK-NEXT: store i16 10794, ptr [[A_SROA_3]], align 2, !tbaa [[TBAA1]]
169169
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 7, i1 true)
170170
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 7
171171
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A_SROA_3]], align 2
@@ -202,8 +202,8 @@ define void @memset2(ptr %dst, ptr align 8 %src) {
202202
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 2 [[A_SROA_4_0_SRC_SROA_IDX]], i32 90, i1 false)
203203
; CHECK-NEXT: store i8 1, ptr [[A_SROA_3]], align 1
204204
; CHECK-NEXT: [[A_SROA_0_202_A_202_SROA_IDX2:%.*]] = getelementptr inbounds i8, ptr [[A_SROA_0]], i64 202
205-
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
206-
; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
205+
; CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 1 [[A_SROA_0_202_A_202_SROA_IDX2]], i8 42, i32 7, i1 false), !tbaa.struct [[TBAA_STRUCT12:![0-9]+]]
206+
; CHECK-NEXT: store i8 42, ptr [[A_SROA_3]], align 1, !tbaa [[TBAA7]]
207207
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 209, i1 true)
208208
; CHECK-NEXT: [[A_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 209
209209
; CHECK-NEXT: [[A_SROA_3_0_A_SROA_3_0_COPYLOAD1:%.*]] = load volatile i8, ptr [[A_SROA_3]], align 1
@@ -243,7 +243,7 @@ define void @slice_store_v2i8_1(ptr %dst, ptr %dst.2, ptr %src) {
243243
; CHECK-NEXT: [[A_SROA_2_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 6
244244
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_COPYLOAD:%.*]] = load <2 x i8>, ptr [[A_SROA_2_0_SRC_SROA_IDX]], align 2
245245
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_COPYLOAD]], ptr [[A_SROA_2_SROA_0]], align 4
246-
; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
246+
; CHECK-NEXT: store <2 x i8> bitcast (<1 x i16> <i16 123> to <2 x i8>), ptr [[A_SROA_2_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT13:![0-9]+]]
247247
; CHECK-NEXT: [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_2_SROA_0]], align 4
248248
; CHECK-NEXT: store <2 x i8> [[A_SROA_2_SROA_0_0_A_SROA_2_SROA_0_0_A_SROA_2_6_V_4]], ptr [[DST_2]], align 2
249249
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 1 [[A_SROA_0]], i32 6, i1 true)
@@ -282,8 +282,8 @@ define void @slice_store_v2i8_2(ptr %dst, ptr %dst.2, ptr %src) {
282282
; CHECK-NEXT: store i8 [[A_SROA_0_SROA_4_1_COPYLOAD]], ptr [[A_SROA_0_SROA_4]], align 1
283283
; CHECK-NEXT: [[A_SROA_4_1_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 3
284284
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[A_SROA_4]], ptr align 1 [[A_SROA_4_1_SRC_SROA_IDX]], i32 5, i1 false)
285-
; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
286-
; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa.struct [[TBAA_STRUCT18:![0-9]+]]
285+
; CHECK-NEXT: store <2 x i8> zeroinitializer, ptr [[A_SROA_0_SROA_1]], align 2, !tbaa.struct [[TBAA_STRUCT14:![0-9]+]]
286+
; CHECK-NEXT: store i8 0, ptr [[A_SROA_0_SROA_4]], align 1, !tbaa [[TBAA1]]
287287
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4:%.*]] = load <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
288288
; CHECK-NEXT: store <2 x i8> [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_A_SROA_0_1_V_4]], ptr [[DST_2]], align 2
289289
; CHECK-NEXT: [[A_SROA_0_SROA_1_0_A_SROA_0_SROA_1_1_COPYLOAD3:%.*]] = load volatile <2 x i8>, ptr [[A_SROA_0_SROA_1]], align 2
@@ -320,7 +320,7 @@ define double @tbaa_struct_load(ptr %src, ptr %dst) {
320320
; CHECK-NEXT: [[TMP_SROA_3_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 8
321321
; CHECK-NEXT: [[TMP_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[TMP_SROA_3_0_SRC_SROA_IDX]], align 8
322322
; CHECK-NEXT: store i64 [[TMP_SROA_3_0_COPYLOAD]], ptr [[TMP_SROA_3]], align 8
323-
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT10]]
323+
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_LG:%.*]] = load double, ptr [[TMP_SROA_0]], align 8, !tbaa [[TBAA7]]
324324
; CHECK-NEXT: [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1:%.*]] = load volatile double, ptr [[TMP_SROA_0]], align 8
325325
; CHECK-NEXT: store volatile double [[TMP_SROA_0_0_TMP_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 8
326326
; CHECK-NEXT: [[TMP_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 8
@@ -359,7 +359,7 @@ define i32 @shorten_integer_store_multiple_fields(ptr %dst, ptr %dst.2, ptr %src
359359
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
360360
; CHECK-NEXT: entry:
361361
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca i32, align 4
362-
; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa.struct [[TBAA_STRUCT19:![0-9]+]]
362+
; CHECK-NEXT: store i32 123, ptr [[A_SROA_0]], align 4, !tbaa [[TBAA7]]
363363
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load i32, ptr [[A_SROA_0]], align 4
364364
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_COPYLOAD:%.*]] = load volatile i32, ptr [[A_SROA_0]], align 4
365365
; CHECK-NEXT: store volatile i32 [[A_SROA_0_0_A_SROA_0_0_COPYLOAD]], ptr [[DST]], align 1
@@ -396,7 +396,7 @@ define <2 x i16> @shorten_vector_store_single_fields(ptr %dst, ptr %dst.2, ptr %
396396
; CHECK-SAME: ptr [[DST:%.*]], ptr [[DST_2:%.*]], ptr [[SRC:%.*]]) {
397397
; CHECK-NEXT: entry:
398398
; CHECK-NEXT: [[A_SROA_0:%.*]] = alloca <2 x i32>, align 8
399-
; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT19]]
399+
; CHECK-NEXT: store <2 x i32> <i32 1, i32 2>, ptr [[A_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT15:![0-9]+]]
400400
; CHECK-NEXT: [[A_SROA_0_0_A_SROA_0_0_L:%.*]] = load <2 x i16>, ptr [[A_SROA_0]], align 8
401401
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 1 [[DST]], ptr align 8 [[A_SROA_0]], i32 4, i1 true)
402402
; CHECK-NEXT: ret <2 x i16> [[A_SROA_0_0_A_SROA_0_0_L]]
@@ -432,11 +432,11 @@ define i32 @split_load_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
432432
; CHECK-NEXT: [[A3_SROA_5_0_SRC_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[SRC]], i64 9
433433
; CHECK-NEXT: [[A3_SROA_5_0_COPYLOAD:%.*]] = load i8, ptr [[A3_SROA_5_0_SRC_SROA_IDX]], align 1
434434
; CHECK-NEXT: store i8 [[A3_SROA_5_0_COPYLOAD]], ptr [[A3_SROA_5]], align 1
435-
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20:![0-9]+]]
435+
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD:%.*]] = load i16, ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16:![0-9]+]]
436436
; CHECK-NEXT: [[LOAD4_FCA_0_INSERT:%.*]] = insertvalue { i16, float, i8 } poison, i16 [[A3_SROA_0_0_A3_SROA_0_0_LOAD4_FCA_0_LOAD]], 0
437-
; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21:![0-9]+]]
437+
; CHECK-NEXT: [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD:%.*]] = load float, ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17:![0-9]+]]
438438
; CHECK-NEXT: [[LOAD4_FCA_1_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_0_INSERT]], float [[A3_SROA_33_0_A3_SROA_33_4_LOAD4_FCA_1_LOAD]], 1
439-
; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
439+
; CHECK-NEXT: [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD:%.*]] = load i8, ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
440440
; CHECK-NEXT: [[LOAD4_FCA_2_INSERT:%.*]] = insertvalue { i16, float, i8 } [[LOAD4_FCA_1_INSERT]], i8 [[A3_SROA_4_0_A3_SROA_4_8_LOAD4_FCA_2_LOAD]], 2
441441
; CHECK-NEXT: [[UNWRAP2:%.*]] = extractvalue { i16, float, i8 } [[LOAD4_FCA_2_INSERT]], 1
442442
; CHECK-NEXT: [[VALCAST2:%.*]] = bitcast float [[UNWRAP2]] to i32
@@ -495,11 +495,11 @@ define i32 @split_store_with_tbaa_struct(i32 %x, ptr %src, ptr %dst) {
495495
; CHECK-NEXT: [[I_2:%.*]] = insertvalue { i16, float, i8 } [[I_1]], float 3.000000e+00, 1
496496
; CHECK-NEXT: [[I_3:%.*]] = insertvalue { i16, float, i8 } [[I_2]], i8 99, 2
497497
; CHECK-NEXT: [[I_3_FCA_0_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 0
498-
; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT20]]
498+
; CHECK-NEXT: store i16 [[I_3_FCA_0_EXTRACT]], ptr [[A3_SROA_0]], align 8, !tbaa.struct [[TBAA_STRUCT16]]
499499
; CHECK-NEXT: [[I_3_FCA_1_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 1
500-
; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT21]]
500+
; CHECK-NEXT: store float [[I_3_FCA_1_EXTRACT]], ptr [[A3_SROA_33]], align 4, !tbaa.struct [[TBAA_STRUCT17]]
501501
; CHECK-NEXT: [[I_3_FCA_2_EXTRACT:%.*]] = extractvalue { i16, float, i8 } [[I_3]], 2
502-
; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa.struct [[TBAA_STRUCT15]]
502+
; CHECK-NEXT: store i8 [[I_3_FCA_2_EXTRACT]], ptr [[A3_SROA_4]], align 8, !tbaa [[TBAA7]]
503503
; CHECK-NEXT: [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1:%.*]] = load volatile i16, ptr [[A3_SROA_0]], align 8
504504
; CHECK-NEXT: store volatile i16 [[A3_SROA_0_0_A3_SROA_0_0_COPYLOAD1]], ptr [[DST]], align 1
505505
; CHECK-NEXT: [[A3_SROA_3_0_DST_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 2
@@ -551,26 +551,22 @@ declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias
551551
!15 = !{i64 0, i64 7, !6, i64 7, i64 1, !6}
552552
!16 = !{i64 0, i64 2, !6, i64 4, i64 4, !6, i64 8, i64 1, !6}
553553
;.
554-
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[META1:![0-9]+]], i64 4, i64 4, [[META1]]}
555-
; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
554+
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 4, [[TBAA1]]}
555+
; CHECK: [[TBAA1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
556556
; CHECK: [[META2]] = !{!"float", [[META3:![0-9]+]], i64 0}
557557
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
558558
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
559-
; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[META1]]}
560-
; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[META7:![0-9]+]], i64 8, i64 4, [[META1]]}
561-
; CHECK: [[META7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
559+
; CHECK: [[TBAA_STRUCT5]] = !{i64 0, i64 4, [[TBAA1]]}
560+
; CHECK: [[TBAA_STRUCT6]] = !{i64 0, i64 8, [[TBAA7]], i64 8, i64 4, [[TBAA1]]}
561+
; CHECK: [[TBAA7]] = !{[[META8:![0-9]+]], [[META8]], i64 0}
562562
; CHECK: [[META8]] = !{!"v2f32", [[META3]], i64 0}
563-
; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[META1]], i64 4, i64 8, [[META7]]}
564-
; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[META7]]}
565-
; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 8, [[META7]], i64 4, i64 8, [[META1]]}
566-
; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 2, [[META1]], i64 2, i64 6, [[META1]]}
567-
; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[META1]]}
568-
; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 7, [[META7]], i64 7, i64 1, [[META7]]}
569-
; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 1, [[META7]]}
570-
; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[META1]], i64 2, i64 2, [[META1]]}
571-
; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 3, [[META1]]}
572-
; CHECK: [[TBAA_STRUCT18]] = !{i64 0, i64 1, [[META1]]}
573-
; CHECK: [[TBAA_STRUCT19]] = !{i64 0, i64 4, [[META7]]}
574-
; CHECK: [[TBAA_STRUCT20]] = !{i64 0, i64 2, [[META7]], i64 4, i64 4, [[META7]], i64 8, i64 1, [[META7]]}
575-
; CHECK: [[TBAA_STRUCT21]] = !{i64 0, i64 4, [[META7]], i64 4, i64 1, [[META7]]}
563+
; CHECK: [[TBAA_STRUCT9]] = !{i64 0, i64 4, [[TBAA1]], i64 4, i64 8, [[TBAA7]]}
564+
; CHECK: [[TBAA_STRUCT10]] = !{i64 0, i64 8, [[TBAA7]], i64 4, i64 8, [[TBAA1]]}
565+
; CHECK: [[TBAA_STRUCT11]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 6, [[TBAA1]]}
566+
; CHECK: [[TBAA_STRUCT12]] = !{i64 0, i64 7, [[TBAA7]], i64 7, i64 1, [[TBAA7]]}
567+
; CHECK: [[TBAA_STRUCT13]] = !{i64 0, i64 2, [[TBAA1]], i64 2, i64 2, [[TBAA1]]}
568+
; CHECK: [[TBAA_STRUCT14]] = !{i64 0, i64 3, [[TBAA1]]}
569+
; CHECK: [[TBAA_STRUCT15]] = !{i64 0, i64 4, [[TBAA7]]}
570+
; CHECK: [[TBAA_STRUCT16]] = !{i64 0, i64 2, [[TBAA7]], i64 4, i64 4, [[TBAA7]], i64 8, i64 1, [[TBAA7]]}
571+
; CHECK: [[TBAA_STRUCT17]] = !{i64 0, i64 4, [[TBAA7]], i64 4, i64 1, [[TBAA7]]}
576572
;.

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