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arm: support SDIV/UDIV in the disassembler
Currently UDIV and SDIV can not be correctly decoded. This patch adds support for them and corresponding tests. fixes #20096 Change-Id: I8818c29bc03aa9f0aaf157bfa03cd39114e0925e Reviewed-on: https://go-review.googlesource.com/41891 Reviewed-by: Cherry Zhang <[email protected]> Run-TryBot: Cherry Zhang <[email protected]> TryBot-Result: Gobot Gobot <[email protected]>
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‎arm/arm.csv

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Original file line numberDiff line numberDiff line change
@@ -177,6 +177,7 @@
177177
"0x0fe00090","0x00c00010","SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs>","cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4",""
178178
"0x0fe00010","0x00c00000","SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>}","cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4","SEE SUBS PC, LR and related instructions"
179179
"0x0fe00070","0x07a00050","SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1>","cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4",""
180+
"0x0ff0f0f0","0x0710f010","SDIV<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|1|0|0|0|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4",""
180181
"0x0ff00ff0","0x06800fb0","SEL<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4",""
181182
"0xfffffdff","0xf1010000","SETEND <endian_specifier>","1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)",""
182183
"0x0fffffff","0x0320f004","SEV<c>","cond:4|0|0|1|1|0|0|1|0|0|0|0|0|(1)|(1)|(1)|(1)|(0)|(0)|(0)|(0)|0|0|0|0|0|1|0|0",""
@@ -252,6 +253,7 @@
252253
"0x0ff00ff0","0x06500f90","UADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
253254
"0x0ff00ff0","0x06500f30","UASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""
254255
"0x0fe00070","0x07e00050","UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1>","cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4",""
256+
"0x0ff0f0f0","0x0730f010","UDIV<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|1|0|0|1|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4",""
255257
"0x0ff00ff0","0x06700f10","UHADD16<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4",""
256258
"0x0ff00ff0","0x06700f90","UHADD8<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4",""
257259
"0x0ff00ff0","0x06700f30","UHASX<c> <Rd>,<Rn>,<Rm>","cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4",""

‎arm/armasm/tables.go

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Original file line numberDiff line numberDiff line change
@@ -1585,6 +1585,22 @@ const (
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SBFX_LE
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SBFX
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SBFX_ZZ
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SDIV_EQ
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SDIV_NE
1590+
SDIV_CS
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SDIV_CC
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SDIV_MI
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SDIV_PL
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SDIV_VS
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SDIV_VC
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SDIV_HI
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SDIV_LS
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SDIV_GE
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SDIV_LT
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SDIV_GT
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SDIV_LE
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SDIV
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SDIV_ZZ
15881604
SEL_EQ
15891605
SEL_NE
15901606
SEL_CS
@@ -2929,6 +2945,22 @@ const (
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UBFX_LE
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UBFX
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UBFX_ZZ
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UDIV_EQ
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UDIV_NE
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UDIV_CS
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UDIV_CC
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UDIV_MI
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UDIV_PL
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UDIV_VS
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UDIV_VC
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UDIV_HI
2957+
UDIV_LS
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UDIV_GE
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UDIV_LT
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UDIV_GT
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UDIV_LE
2962+
UDIV
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UDIV_ZZ
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UHADD16_EQ
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UHADD16_NE
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UHADD16_CS
@@ -6107,6 +6139,22 @@ var opstr = [...]string{
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SBFX_LE: "SBFX.LE",
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SBFX: "SBFX",
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SBFX_ZZ: "SBFX.ZZ",
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SDIV_EQ: "SDIV.EQ",
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SDIV_NE: "SDIV.NE",
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SDIV_CS: "SDIV.CS",
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SDIV_CC: "SDIV.CC",
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SDIV_MI: "SDIV.MI",
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SDIV_PL: "SDIV.PL",
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SDIV_VS: "SDIV.VS",
6149+
SDIV_VC: "SDIV.VC",
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SDIV_HI: "SDIV.HI",
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SDIV_LS: "SDIV.LS",
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SDIV_GE: "SDIV.GE",
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SDIV_LT: "SDIV.LT",
6154+
SDIV_GT: "SDIV.GT",
6155+
SDIV_LE: "SDIV.LE",
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SDIV: "SDIV",
6157+
SDIV_ZZ: "SDIV.ZZ",
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SEL_EQ: "SEL.EQ",
61116159
SEL_NE: "SEL.NE",
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SEL_CS: "SEL.CS",
@@ -7436,6 +7484,22 @@ var opstr = [...]string{
74367484
UBFX_LE: "UBFX.LE",
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UBFX: "UBFX",
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UBFX_ZZ: "UBFX.ZZ",
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UDIV_EQ: "UDIV.EQ",
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UDIV_NE: "UDIV.NE",
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UDIV_CS: "UDIV.CS",
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UDIV_CC: "UDIV.CC",
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UDIV_MI: "UDIV.MI",
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UDIV_PL: "UDIV.PL",
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UDIV_VS: "UDIV.VS",
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UDIV_VC: "UDIV.VC",
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UDIV_HI: "UDIV.HI",
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UDIV_LS: "UDIV.LS",
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UDIV_GE: "UDIV.GE",
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UDIV_LT: "UDIV.LT",
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UDIV_GT: "UDIV.GT",
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UDIV_LE: "UDIV.LE",
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UDIV: "UDIV",
7502+
UDIV_ZZ: "UDIV.ZZ",
74397503
UHADD16_EQ: "UHADD16.EQ",
74407504
UHADD16_NE: "UHADD16.NE",
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UHADD16_CS: "UHADD16.CS",
@@ -9267,6 +9331,8 @@ var instFormats = [...]instFormat{
92679331
{0x0fe00090, 0x00c00010, 4, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_R}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>,<type> <Rs> cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|Rs:4|0|type:2|1|Rm:4
92689332
{0x0fe00010, 0x00c00000, 2, SBC_EQ, 0x14011c04, instArgs{arg_R_12, arg_R_16, arg_R_shift_imm}}, // SBC{S}<c> <Rd>,<Rn>,<Rm>{,<shift>} cond:4|0|0|0|0|1|1|0|S|Rn:4|Rd:4|imm5:5|type:2|0|Rm:4
92699333
{0x0fe00070, 0x07a00050, 4, SBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // SBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|0|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4
9334+
{0x0ff0f0f0, 0x0710f010, 4, SDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SDIV<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4
9335+
{0x0ff000f0, 0x0710f010, 3, SDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // SDIV<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|0|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4
92709336
{0x0ff00ff0, 0x06800fb0, 4, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
92719337
{0x0ff000f0, 0x06800fb0, 3, SEL_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // SEL<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|1|0|0|0|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|1|1|Rm:4
92729338
{0xfffffdff, 0xf1010000, 4, SETEND, 0x0, instArgs{arg_endian}}, // SETEND <endian_specifier> 1|1|1|1|0|0|0|1|0|0|0|0|0|0|0|1|0|0|0|0|0|0|E|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)|(0)
@@ -9365,6 +9431,8 @@ var instFormats = [...]instFormat{
93659431
{0x0ff00ff0, 0x06500f30, 4, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
93669432
{0x0ff000f0, 0x06500f30, 3, UASX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UASX<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|0|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|1|1|Rm:4
93679433
{0x0fe00070, 0x07e00050, 4, UBFX_EQ, 0x1c04, instArgs{arg_R_12, arg_R_0, arg_imm5, arg_widthm1}}, // UBFX<c> <Rd>,<Rn>,#<lsb>,#<widthm1> cond:4|0|1|1|1|1|1|1|widthm1:5|Rd:4|lsb:5|1|0|1|Rn:4
9434+
{0x0ff0f0f0, 0x0730f010, 4, UDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // UDIV<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|1|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4
9435+
{0x0ff000f0, 0x0730f010, 3, UDIV_EQ, 0x1c04, instArgs{arg_R_16, arg_R_0, arg_R_8}}, // UDIV<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|1|0|0|1|1|Rd:4|(1)|(1)|(1)|(1)|Rm:4|0|0|0|1|Rn:4
93689436
{0x0ff00ff0, 0x06700f10, 4, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
93699437
{0x0ff000f0, 0x06700f10, 3, UHADD16_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD16<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|0|0|0|1|Rm:4
93709438
{0x0ff00ff0, 0x06700f90, 4, UHADD8_EQ, 0x1c04, instArgs{arg_R_12, arg_R_16, arg_R_0}}, // UHADD8<c> <Rd>,<Rn>,<Rm> cond:4|0|1|1|0|0|1|1|1|Rn:4|Rd:4|(1)|(1)|(1)|(1)|1|0|0|1|Rm:4

‎arm/armasm/testdata/decode.txt

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -304,6 +304,10 @@ ff818c71| 1 gnu strdvc r8, [ip, pc]
304304
|6b5721d3 1 gnu error: unknown instruction
305305
|76452001 1 gnu error: unknown instruction
306306
|97acd647 1 gnu error: unknown instruction
307+
11f71507| 1 plan9 SDIV.EQ R7, R1, R5
308+
15f715e7| 1 plan9 SDIV R7, R5, R5
309+
11f93517| 1 plan9 UDIV.NE R9, R1, R5
310+
12fb33e7| 1 plan9 UDIV R11, R2, R3
307311
ed003be9| 1 plan9 LDMDB [R0,R2-R3,R5-R7], R11!
308312
923124e0| 1 plan9 MLA R1, R2, R3, R4
309313
923134e0| 1 plan9 MLA.S R1, R2, R3, R4

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