Skip to content

Commit 67d85ad

Browse files
Archana Rlaboger
Archana R
authored and
laboger
committed
cmd/asm: add new classification for index memory operands on PPC64
When a base+displacement kind of operand is given in an index-mode instruction, the assembler does not flag it as an invalid instruction causing the user to get an incorrect encoding of that instruction leading to incorrect execution of the program. Enable assembler to recognize valid and invalid operands used in index mode instructions by classifying SOREG type into two further types XOREG (used uniquely in index addressing mode instructions) and SOREG for instructions working on base+displacement operands. Also cleaned up usage of obj.Addr.Scale on PPC64. Change-Id: Ib4d84343ae57477c6c074f44c4c2749496e11b91 Reviewed-on: https://go-review.googlesource.com/c/go/+/405542 Reviewed-by: Lynn Boger <[email protected]> TryBot-Result: Gopher Robot <[email protected]> Reviewed-by: Heschi Kreinick <[email protected]> Reviewed-by: Cherry Mui <[email protected]> Run-TryBot: Archana Ravindar <[email protected]>
1 parent 4381c61 commit 67d85ad

File tree

7 files changed

+268
-68
lines changed

7 files changed

+268
-68
lines changed

‎src/cmd/asm/internal/asm/operand_test.go

+1-1
Original file line numberDiff line numberDiff line change
@@ -473,7 +473,7 @@ var ppc64OperandTests = []operandTest{
473473
{"(R4)", "(R4)"},
474474
{"(R5)", "(R5)"},
475475
{"(R5)(R6*1)", "(R5)(R6*1)"},
476-
{"(R5+R6)", "(R5)(R6*1)"}, // Old syntax.
476+
{"(R5+R6)", "(R5)(R6)"},
477477
{"-1(R4)", "-1(R4)"},
478478
{"-1(R5)", "-1(R5)"},
479479
{"6(PC)", "6(PC)"},

‎src/cmd/asm/internal/asm/parse.go

+7-4
Original file line numberDiff line numberDiff line change
@@ -975,13 +975,13 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
975975
return
976976
}
977977
if p.arch.Family == sys.PPC64 {
978-
// Special form for PPC64: (R1+R2); alias for (R1)(R2*1).
978+
// Special form for PPC64: (R1+R2); alias for (R1)(R2).
979979
if prefix != 0 || scale != 0 {
980980
p.errorf("illegal address mode for register+register")
981981
return
982982
}
983983
a.Type = obj.TYPE_MEM
984-
a.Scale = 1
984+
a.Scale = 0
985985
a.Index = r2
986986
// Nothing may follow.
987987
return
@@ -1014,9 +1014,12 @@ func (p *Parser) registerIndirect(a *obj.Addr, prefix rune) {
10141014
p.errorf("unimplemented two-register form")
10151015
}
10161016
a.Index = r1
1017-
if scale != 0 && scale != 1 && p.arch.Family == sys.ARM64 {
1017+
if scale != 0 && scale != 1 && (p.arch.Family == sys.ARM64 ||
1018+
p.arch.Family == sys.PPC64) {
10181019
// Support (R1)(R2) (no scaling) and (R1)(R2*1).
1019-
p.errorf("arm64 doesn't support scaled register format")
1020+
if p.arch.Family != sys.PPC64 {
1021+
p.errorf("%s doesn't support scaled register format", p.arch.Name)
1022+
}
10201023
} else {
10211024
a.Scale = int16(scale)
10221025
}

‎src/cmd/asm/internal/asm/testdata/ppc64.s

+167-4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@
88

99
#include "../../../../../runtime/textflag.h"
1010

11+
// In case of index mode instructions, usage of
12+
// (Rx)(R0) is equivalent to (Rx+R0)
13+
// In case of base+displacement mode instructions if
14+
// the offset is 0, usage of (Rx) is equivalent to 0(Rx)
1115
TEXT asmtest(SB),DUPOK|NOSPLIT,$0
1216
// move constants
1317
MOVD $1, R3 // 38600001
@@ -26,58 +30,113 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
2630
MOVW $1234567, R5 // 6405001260a5d687
2731
MOVD 8(R3), R4 // e8830008
2832
MOVD (R3)(R4), R5 // 7ca4182a
33+
MOVD (R3)(R0), R5 // 7ca0182a
34+
MOVD (R3), R5 // e8a30000
2935
MOVW 4(R3), R4 // e8830006
3036
MOVW (R3)(R4), R5 // 7ca41aaa
37+
MOVW (R3)(R0), R5 // 7ca01aaa
38+
MOVW (R3), R5 // e8a30002
3139
MOVWZ 4(R3), R4 // 80830004
3240
MOVWZ (R3)(R4), R5 // 7ca4182e
41+
MOVWZ (R3)(R0), R5 // 7ca0182e
42+
MOVWZ (R3), R5 // 80a30000
3343
MOVH 4(R3), R4 // a8830004
3444
MOVH (R3)(R4), R5 // 7ca41aae
45+
MOVH (R3)(R0), R5 // 7ca01aae
46+
MOVH (R3), R5 // a8a30000
47+
3548
MOVHZ 2(R3), R4 // a0830002
3649
MOVHZ (R3)(R4), R5 // 7ca41a2e
50+
MOVHZ (R3)(R0), R5 // 7ca01a2e
51+
MOVHZ (R3), R5 // a0a30000
3752
MOVB 1(R3), R4 // 888300017c840774
3853
MOVB (R3)(R4), R5 // 7ca418ae7ca50774
54+
MOVB (R3)(R0), R5 // 7ca018ae7ca50774
55+
MOVB (R3), R5 // 88a300007ca50774
3956
MOVBZ 1(R3), R4 // 88830001
4057
MOVBZ (R3)(R4), R5 // 7ca418ae
58+
MOVBZ (R3)(R0), R5 // 7ca018ae
59+
MOVBZ (R3), R5 // 88a30000
4160
MOVDBR (R3)(R4), R5 // 7ca41c28
61+
MOVDBR (R3)(R0), R5 // 7ca01c28
62+
MOVDBR (R3), R5 // 7ca01c28
4263
MOVWBR (R3)(R4), R5 // 7ca41c2c
64+
MOVWBR (R3)(R0), R5 // 7ca01c2c
65+
MOVWBR (R3), R5 // 7ca01c2c
4366
MOVHBR (R3)(R4), R5 // 7ca41e2c
67+
MOVHBR (R3)(R0), R5 // 7ca01e2c
68+
MOVHBR (R3), R5 // 7ca01e2c
4469
MOVD $foo+4009806848(FP), R5 // 3ca1ef0138a5cc40
4570
MOVD $foo(SB), R5 // 3ca0000038a50000
4671

4772
MOVDU 8(R3), R4 // e8830009
4873
MOVDU (R3)(R4), R5 // 7ca4186a
74+
MOVDU (R3)(R0), R5 // 7ca0186a
75+
MOVDU (R3), R5 // e8a30001
4976
MOVWU (R3)(R4), R5 // 7ca41aea
77+
MOVWU (R3)(R0), R5 // 7ca01aea
5078
MOVWZU 4(R3), R4 // 84830004
5179
MOVWZU (R3)(R4), R5 // 7ca4186e
80+
MOVWZU (R3)(R0), R5 // 7ca0186e
81+
MOVWZU (R3), R5 // 84a30000
5282
MOVHU 2(R3), R4 // ac830002
5383
MOVHU (R3)(R4), R5 // 7ca41aee
84+
MOVHU (R3)(R0), R5 // 7ca01aee
85+
MOVHU (R3), R5 // aca30000
5486
MOVHZU 2(R3), R4 // a4830002
5587
MOVHZU (R3)(R4), R5 // 7ca41a6e
88+
MOVHZU (R3)(R0), R5 // 7ca01a6e
89+
MOVHZU (R3), R5 // a4a30000
5690
MOVBU 1(R3), R4 // 8c8300017c840774
5791
MOVBU (R3)(R4), R5 // 7ca418ee7ca50774
92+
MOVBU (R3)(R0), R5 // 7ca018ee7ca50774
93+
MOVBU (R3), R5 // 8ca300007ca50774
5894
MOVBZU 1(R3), R4 // 8c830001
5995
MOVBZU (R3)(R4), R5 // 7ca418ee
96+
MOVBZU (R3)(R0), R5 // 7ca018ee
97+
MOVBZU (R3), R5 // 8ca30000
6098

6199
MOVD R4, 8(R3) // f8830008
62100
MOVD R5, (R3)(R4) // 7ca4192a
101+
MOVD R5, (R3)(R0) // 7ca0192a
102+
MOVD R5, (R3) // f8a30000
63103
MOVW R4, 4(R3) // 90830004
64104
MOVW R5, (R3)(R4) // 7ca4192e
105+
MOVW R5, (R3)(R0) // 7ca0192e
106+
MOVW R5, (R3) // 90a30000
65107
MOVH R4, 2(R3) // b0830002
66108
MOVH R5, (R3)(R4) // 7ca41b2e
109+
MOVH R5, (R3)(R0) // 7ca01b2e
110+
MOVH R5, (R3) // b0a30000
67111
MOVB R4, 1(R3) // 98830001
68112
MOVB R5, (R3)(R4) // 7ca419ae
113+
MOVB R5, (R3)(R0) // 7ca019ae
114+
MOVB R5, (R3) // 98a30000
69115
MOVDBR R5, (R3)(R4) // 7ca41d28
116+
MOVDBR R5, (R3)(R0) // 7ca01d28
117+
MOVDBR R5, (R3) // 7ca01d28
70118
MOVWBR R5, (R3)(R4) // 7ca41d2c
119+
MOVWBR R5, (R3)(R0) // 7ca01d2c
120+
MOVWBR R5, (R3) // 7ca01d2c
71121
MOVHBR R5, (R3)(R4) // 7ca41f2c
122+
MOVHBR R5, (R3)(R0) // 7ca01f2c
123+
MOVHBR R5, (R3) // 7ca01f2c
72124

73125
MOVDU R4, 8(R3) // f8830009
74126
MOVDU R5, (R3)(R4) // 7ca4196a
127+
MOVDU R5, (R3)(R0) // 7ca0196a
128+
MOVDU R5, (R3) // f8a30001
75129
MOVWU R4, 4(R3) // 94830004
76130
MOVWU R5, (R3)(R4) // 7ca4196e
131+
MOVWU R5, (R3)(R0) // 7ca0196e
77132
MOVHU R4, 2(R3) // b4830002
78133
MOVHU R5, (R3)(R4) // 7ca41b6e
134+
MOVHU R5, (R3)(R0) // 7ca01b6e
135+
MOVHU R5, (R3) // b4a30000
79136
MOVBU R4, 1(R3) // 9c830001
80137
MOVBU R5, (R3)(R4) // 7ca419ee
138+
MOVBU R5, (R3)(R0) // 7ca019ee
139+
MOVBU R5, (R3) // 9ca30000
81140

82141
MOVB $0, R4 // 38800000
83142
MOVBZ $0, R4 // 38800000
@@ -372,23 +431,41 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
372431

373432
// load-and-reserve
374433
LBAR (R4)(R3*1),$1,R5 // 7ca32069
434+
LBAR (R4)(R0),$1,R5 // 7ca02069
375435
LBAR (R4),$0,R5 // 7ca02068
376436
LBAR (R3),R5 // 7ca01868
377437
LHAR (R4)(R3*1),$1,R5 // 7ca320e9
438+
LHAR (R4)(R0),$1,R5 // 7ca020e9
378439
LHAR (R4),$0,R5 // 7ca020e8
379440
LHAR (R3),R5 // 7ca018e8
380441
LWAR (R4)(R3*1),$1,R5 // 7ca32029
442+
LWAR (R4)(R0),$1,R5 // 7ca02029
381443
LWAR (R4),$0,R5 // 7ca02028
382444
LWAR (R3),R5 // 7ca01828
383445
LDAR (R4)(R3*1),$1,R5 // 7ca320a9
446+
LDAR (R4)(R0),$1,R5 // 7ca020a9
384447
LDAR (R4),$0,R5 // 7ca020a8
385448
LDAR (R3),R5 // 7ca018a8
386449

450+
LSW (R3)(R4), R5 // 7ca41c2a
451+
LSW (R3)(R0), R5 // 7ca01c2a
452+
LSW (R3), R5 // 7ca01c2a
453+
387454
STBCCC R3, (R4)(R5) // 7c65256d
455+
STBCCC R3, (R4)(R0) // 7c60256d
456+
STBCCC R3, (R4) // 7c60256d
388457
STWCCC R3, (R4)(R5) // 7c65212d
458+
STWCCC R3, (R4)(R0) // 7c60212d
459+
STWCCC R3, (R4) // 7c60212d
389460
STDCCC R3, (R4)(R5) // 7c6521ad
390-
STHCCC R3, (R4)(R5)
391-
STSW R3, (R4)(R5)
461+
STDCCC R3, (R4)(R0) // 7c6021ad
462+
STDCCC R3, (R4) // 7c6021ad
463+
STHCCC R3, (R4)(R5) // 7c6525ad
464+
STHCCC R3, (R4)(R0) // 7c6025ad
465+
STHCCC R3, (R4) // 7c6025ad
466+
STSW R3, (R4)(R5) // 7c65252a
467+
STSW R3, (R4)(R0) // 7c60252a
468+
STSW R3, (R4) // 7c60252a
392469

393470
SYNC // 7c0004ac
394471
ISYNC // 4c00012c
@@ -397,33 +474,68 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
397474
DARN $1, R5 // 7ca105e6
398475

399476
DCBF (R3)(R4) // 7c0418ac
400-
DCBI (R3)(R4) // 7c041bac
477+
DCBF (R3)(R0) // 7c0018ac
478+
DCBF (R3) // 7c0018ac
479+
401480
DCBST (R3)(R4) // 7c04186c
481+
DCBST (R3)(R0) // 7c00186c
482+
DCBST (R3) // 7c00186c
402483
DCBZ (R3)(R4) // 7c041fec
484+
DCBZ (R3)(R0) // 7c001fec
485+
DCBZ (R3) // 7c001fec
403486
DCBT (R3)(R4) // 7c041a2c
487+
DCBT (R3)(R0) // 7c001a2c
488+
DCBT (R3) // 7c001a2c
404489
ICBI (R3)(R4) // 7c041fac
490+
ICBI (R3)(R0) // 7c001fac
491+
ICBI (R3) // 7c001fac
405492

406493
// float constants
407494
FMOVD $(0.0), F1 // f0210cd0
408495
FMOVD $(-0.0), F1 // f0210cd0fc200850
409496

410497
FMOVD 8(R3), F1 // c8230008
411498
FMOVD (R3)(R4), F1 // 7c241cae
499+
FMOVD (R3)(R0), F1 // 7c201cae
500+
FMOVD (R3), F1 // c8230000
412501
FMOVDU 8(R3), F1 // cc230008
413502
FMOVDU (R3)(R4), F1 // 7c241cee
503+
FMOVDU (R3)(R0), F1 // 7c201cee
504+
FMOVDU (R3), F1 // cc230000
414505
FMOVS 4(R3), F1 // c0230004
415506
FMOVS (R3)(R4), F1 // 7c241c2e
507+
FMOVS (R3)(R0), F1 // 7c201c2e
508+
FMOVS (R3), F1 // c0230000
416509
FMOVSU 4(R3), F1 // c4230004
417510
FMOVSU (R3)(R4), F1 // 7c241c6e
511+
FMOVSU (R3)(R0), F1 // 7c201c6e
512+
FMOVSU (R3), F1 // c4230000
513+
FMOVSX (R3)(R4), F1 // 7c241eae
514+
FMOVSX (R3)(R0), F1 // 7c201eae
515+
FMOVSX (R3), F1 // 7c201eae
516+
FMOVSZ (R3)(R4), F1 // 7c241eee
517+
FMOVSZ (R3)(R0), F1 // 7c201eee
518+
FMOVSZ (R3), F1 // 7c201eee
418519

419520
FMOVD F1, 8(R3) // d8230008
420521
FMOVD F1, (R3)(R4) // 7c241dae
522+
FMOVD F1, (R3)(R0) // 7c201dae
523+
FMOVD F1, (R3) // d8230000
421524
FMOVDU F1, 8(R3) // dc230008
422525
FMOVDU F1, (R3)(R4) // 7c241dee
526+
FMOVDU F1, (R3)(R0) // 7c201dee
527+
FMOVDU F1, (R3) // dc230000
423528
FMOVS F1, 4(R3) // d0230004
424529
FMOVS F1, (R3)(R4) // 7c241d2e
530+
FMOVS F1, (R3)(R0) // 7c201d2e
531+
FMOVS F1, (R3) // d0230000
425532
FMOVSU F1, 4(R3) // d4230004
426533
FMOVSU F1, (R3)(R4) // 7c241d6e
534+
FMOVSU F1, (R3)(R0) // 7c201d6e
535+
FMOVSU F1, (R3) // d4230000
536+
FMOVSX F1, (R3)(R4) // 7c241fae
537+
FMOVSX F1, (R3)(R0) // 7c201fae
538+
FMOVSX F1, (R3) // 7c201fae
427539
FADD F1, F2 // fc42082a
428540
FADD F1, F2, F3 // fc62082a
429541
FADDCC F1, F2, F3 // fc62082b
@@ -507,17 +619,41 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
507619
FCMPO F1, F2 // fc011040
508620
FCMPU F1, F2 // fc011000
509621
LVX (R3)(R4), V1 // 7c2418ce
622+
LVX (R3)(R0), V1 // 7c2018ce
623+
LVX (R3), V1 // 7c2018ce
510624
LVXL (R3)(R4), V1 // 7c241ace
625+
LVXL (R3)(R0), V1 // 7c201ace
626+
LVXL (R3), V1 // 7c201ace
511627
LVSL (R3)(R4), V1 // 7c24180c
628+
LVSL (R3)(R0), V1 // 7c20180c
629+
LVSL (R3), V1 // 7c20180c
512630
LVSR (R3)(R4), V1 // 7c24184c
631+
LVSR (R3)(R0), V1 // 7c20184c
632+
LVSR (R3), V1 // 7c20184c
513633
LVEBX (R3)(R4), V1 // 7c24180e
634+
LVEBX (R3)(R0), V1 // 7c20180e
635+
LVEBX (R3), V1 // 7c20180e
514636
LVEHX (R3)(R4), V1 // 7c24184e
637+
LVEHX (R3)(R0), V1 // 7c20184e
638+
LVEHX (R3), V1 // 7c20184e
515639
LVEWX (R3)(R4), V1 // 7c24188e
640+
LVEWX (R3)(R0), V1 // 7c20188e
641+
LVEWX (R3), V1 // 7c20188e
516642
STVX V1, (R3)(R4) // 7c2419ce
643+
STVX V1, (R3)(R0) // 7c2019ce
644+
STVX V1, (R3) // 7c2019ce
517645
STVXL V1, (R3)(R4) // 7c241bce
646+
STVXL V1, (R3)(R0) // 7c201bce
647+
STVXL V1, (R3) // 7c201bce
518648
STVEBX V1, (R3)(R4) // 7c24190e
649+
STVEBX V1, (R3)(R0) // 7c20190e
650+
STVEBX V1, (R3) // 7c20190e
519651
STVEHX V1, (R3)(R4) // 7c24194e
652+
STVEHX V1, (R3)(R0) // 7c20194e
653+
STVEHX V1, (R3) // 7c20194e
520654
STVEWX V1, (R3)(R4) // 7c24198e
655+
STVEWX V1, (R3)(R0) // 7c20198e
656+
STVEWX V1, (R3) // 7c20198e
521657

522658
VAND V1, V2, V3 // 10611404
523659
VANDC V1, V2, V3 // 10611444
@@ -651,28 +787,55 @@ TEXT asmtest(SB),DUPOK|NOSPLIT,$0
651787
VSHASIGMAD $2, V1, $15, V2 // 104196c2
652788

653789
LXVD2X (R3)(R4), VS1 // 7c241e98
790+
LXVD2X (R3)(R0), VS1 // 7c201e98
791+
LXVD2X (R3), VS1 // 7c201e98
654792
LXVDSX (R3)(R4), VS1 // 7c241a98
793+
LXVDSX (R3)(R0), VS1 // 7c201a98
794+
LXVDSX (R3), VS1 // 7c201a98
655795
LXVH8X (R3)(R4), VS1 // 7c241e58
796+
LXVH8X (R3)(R0), VS1 // 7c201e58
797+
LXVH8X (R3), VS1 // 7c201e58
656798
LXVB16X (R3)(R4), VS1 // 7c241ed8
799+
LXVB16X (R3)(R0), VS1 // 7c201ed8
800+
LXVB16X (R3), VS1 // 7c201ed8
657801
LXVW4X (R3)(R4), VS1 // 7c241e18
802+
LXVW4X (R3)(R0), VS1 // 7c201e18
803+
LXVW4X (R3), VS1 // 7c201e18
658804
LXV 16(R3), VS1 // f4230011
805+
LXV (R3), VS1 // f4230001
659806
LXV 16(R3), VS33 // f4230019
807+
LXV (R3), VS33 // f4230009
660808
LXV 16(R3), V1 // f4230019
809+
LXV (R3), V1 // f4230009
661810
LXVL R3, R4, VS1 // 7c23221a
662811
LXVLL R3, R4, VS1 // 7c23225a
663812
LXVX R3, R4, VS1 // 7c232218
664813
LXSDX (R3)(R4), VS1 // 7c241c98
814+
LXSDX (R3)(R0), VS1 // 7c201c98
815+
LXSDX (R3), VS1 // 7c201c98
665816
STXVD2X VS1, (R3)(R4) // 7c241f98
817+
STXVD2X VS1, (R3)(R0) // 7c201f98
818+
STXVD2X VS1, (R3) // 7c201f98
666819
STXV VS1,16(R3) // f4230015
820+
STXV VS1,(R3) // f4230005
667821
STXVL VS1, R3, R4 // 7c23231a
668822
STXVLL VS1, R3, R4 // 7c23235a
669823
STXVX VS1, R3, R4 // 7c232318
670824
STXVB16X VS1, (R4)(R5) // 7c2527d8
825+
STXVB16X VS1, (R4)(R0) // 7c2027d8
826+
STXVB16X VS1, (R4) // 7c2027d8
671827
STXVH8X VS1, (R4)(R5) // 7c252758
672-
828+
STXVH8X VS1, (R4)(R0) // 7c202758
829+
STXVH8X VS1, (R4) // 7c202758
673830
STXSDX VS1, (R3)(R4) // 7c241d98
831+
STXSDX VS1, (R4)(R0) // 7c202598
832+
STXSDX VS1, (R4) // 7c202598
674833
LXSIWAX (R3)(R4), VS1 // 7c241898
834+
LXSIWAX (R3)(R0), VS1 // 7c201898
835+
LXSIWAX (R3), VS1 // 7c201898
675836
STXSIWX VS1, (R3)(R4) // 7c241918
837+
STXSIWX VS1, (R3)(R0) // 7c201918
838+
STXSIWX VS1, (R3) // 7c201918
676839
MFVSRD VS1, R3 // 7c230066
677840
MTFPRD R3, F0 // 7c030166
678841
MFVRD V0, R3 // 7c030067

‎src/cmd/internal/obj/ppc64/a.out.go

+2-1
Original file line numberDiff line numberDiff line change
@@ -419,9 +419,10 @@ const (
419419
C_SBRA /* A short offset argument to a branching instruction */
420420
C_LBRA /* A long offset argument to a branching instruction */
421421
C_LBRAPIC /* Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker. */
422-
C_ZOREG /* An reg+reg memory arg, or a $0+reg memory op */
422+
C_ZOREG /* An $0+reg memory op */
423423
C_SOREG /* An $n+reg memory arg where n is a 16 bit signed offset */
424424
C_LOREG /* An $n+reg memory arg where n is a 32 bit signed offset */
425+
C_XOREG /* An reg+reg memory arg */
425426
C_FPSCR /* The fpscr register */
426427
C_XER /* The xer, holds the carry bit */
427428
C_LR /* The link register */

‎src/cmd/internal/obj/ppc64/anames9.go

+1
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ var cnames9 = []string{
3939
"ZOREG",
4040
"SOREG",
4141
"LOREG",
42+
"XOREG",
4243
"FPSCR",
4344
"XER",
4445
"LR",

0 commit comments

Comments
 (0)