Merge pull request #325 from darayus/stm32f4-pin

Modernize STM32F4 GPIO implementation

Author: mcoffin

examples/app_blink_stm32f4.rs

@@ -6,19 +6,20 @@ extern crate core;
 extern crate zinc;
 
 use zinc::hal::timer::Timer;
+use zinc::hal::pin::Gpio;
 use zinc::hal::stm32f4::{pin, timer};
 
 #[zinc_main]
 pub fn main() {
   zinc::hal::mem_init::init_stack();
   zinc::hal::mem_init::init_data();
 
-  let led1 = pin::PinConf{
+  let led1 = pin::Pin {
     port: pin::Port::PortD,
     pin: 13u8,
     function: pin::Function::GPIOOut
   };
-  let led2 = pin::PinConf{
+  let led2 = pin::Pin {
     port: pin::Port::PortD,
     pin: 14u8,
     function: pin::Function::GPIOOut

src/hal/stm32f4/gpio.rs

@@ -16,7 +16,6 @@
 //! HAL for STM32F4.
 
 pub mod init;
-pub mod gpio;
 pub mod peripheral_clock;
 pub mod pin;
 pub mod timer;

src/hal/stm32f4/mod.rs

@@ -18,6 +18,7 @@
 //! Some pins that could be configured here may be missing from actual MCU
 //! depending on the package.
 
+use hal::pin::{Gpio, GpioDirection, GpioLevel};
 use super::peripheral_clock;
 use core::intrinsics::abort;
 
@@ -68,12 +69,9 @@ impl Port {
   }
 }
 
-/// Pin configuration.
-///
-/// This structure shouldn't be used directly, pinmap.rs, available via pin::map
-/// has all possible pin configurations.
+/// Pin configuration
 #[derive(Clone, Copy)]
-pub struct PinConf {
+pub struct Pin {
   /// Pin port, mcu-specific.
   pub port: Port,
   /// Pin number.
@@ -82,58 +80,33 @@ pub struct PinConf {
   pub function: Function,
 }
 
-impl PinConf {
+impl Pin {
   /// Setup the pin.
   #[inline(always)]
   pub fn setup(&self) {
     use self::Function::*;
+    use self::reg::GPIO_moder_mode as RegMode;
 
     self.port.clock().enable();  // TODO(farcaller): should be done once per port
 
-    let offset: u32 = self.pin as u32 * 2;
+    let offset = self.pin as usize;
     let gpreg = self.get_reg();
 
-    let bits: u32 = match self.function {
-      GPIOOut => 0b01 << offset as usize,
-      GPIOIn  => 0b00 << offset as usize,
+    let val = match self.function {
+      GPIOOut => RegMode::Output,
+      GPIOIn  => RegMode::Input,
       _       => unsafe { abort() },  // FIXME(farcaller): not implemented
     };
-    let mask: u32 = !(0b11 << offset as usize);
-    let val: u32 = gpreg.MODER();
 
-    gpreg.set_MODER(val & mask | bits);
-  }
-
-  /// Sets output GPIO value to high.
-  pub fn set_high(&self) {
-    let bit: u32 = 1 << self.pin as usize;
-    self.get_reg().set_BSRR(bit);
-  }
-
-  /// Sets output GPIO value to low.
-  pub fn set_low(&self) {
-    let bit: u32 = 1 << (self.pin as usize + 16);
-    self.get_reg().set_BSRR(bit);
+    gpreg.moder.set_mode(offset, val);
   }
 
   /// Toggles the GPIO value
   pub fn toggle(&self) {
-    let bit: u32 = 1 << self.pin as usize;
     let reg = self.get_reg();
-    let val: u32 = reg.ODR();
+    let offset = self.pin as usize;
 
-    reg.set_ODR(val ^ bit);
-  }
-
-  /// Returns input GPIO level.
-  pub fn level(&self) -> ::hal::pin::GpioLevel {
-    let bit: u32 = 1 << (self.pin as usize);
-    let reg = self.get_reg();
-
-    match reg.IDR() & bit {
-      0 => ::hal::pin::Low,
-      _ => ::hal::pin::High,
-    }
+    reg.odr.set_od(offset, !reg.odr.od(offset));
   }
 
   fn get_reg(&self) -> &reg::GPIO {
@@ -151,21 +124,103 @@ impl PinConf {
   }
 }
 
+impl Gpio for Pin {
+  /// Sets output GPIO value to high.
+  fn set_high(&self) {
+    let offset = self.pin as usize;
+    self.get_reg().bsrr.set_bs(offset, true);
+  }
+
+  /// Sets output GPIO value to low.
+  fn set_low(&self) {
+    let offset = self.pin as usize;
+    self.get_reg().bsrr.set_br(offset, true);
+  }
+
+  /// Returns input GPIO level.
+  fn level(&self) -> GpioLevel {
+    let offset = self.pin as usize;
+    let reg = self.get_reg();
+
+    match reg.idr.id(offset) {
+      false => GpioLevel::Low,
+      _ => GpioLevel::High,
+    }
+  }
+
+  /// Sets output GPIO direction.
+  fn set_direction(&self, new_mode: GpioDirection) {
+    // TODO(darayus): Verify that this works
+    // TODO(darayus): Change the Pin.function field to the new mode
+    use self::reg::GPIO_moder_mode as RegMode;
+    let offset = self.pin as usize;
+    let reg = self.get_reg();
+
+    let val = match new_mode {
+      GpioDirection::Out => RegMode::Output,
+      GpioDirection::In  => RegMode::Input,
+    };
+
+    reg.moder.set_mode(offset, val);
+  }
+}
+
 #[allow(dead_code)]
 mod reg {
+  use core::ops::Drop;
   use volatile_cell::VolatileCell;
 
-  ioreg_old!(GPIO: u32, MODER, OTYPER, OSPEEDER, PUPDR, IDR, ODR, BSRR, LCKR, AFRL, AFRH);
-  reg_rw!(GPIO, u32, MODER,    set_MODER,    MODER);
-  reg_rw!(GPIO, u32, OTYPER,   set_OTYPER,   OTYPER);
-  reg_rw!(GPIO, u32, OSPEEDER, set_OSPEEDER, OSPEEDER);
-  reg_rw!(GPIO, u32, PUPDR,    set_PUPDR,    PUPDR);
-  reg_rw!(GPIO, u32, IDR,      set_IDR,      IDR);
-  reg_rw!(GPIO, u32, ODR,      set_ODR,      ODR);
-  reg_rw!(GPIO, u32, BSRR,     set_BSRR,     BSRR);
-  reg_rw!(GPIO, u32, LCKR,     set_LCKR,     LCKR);
-  reg_rw!(GPIO, u32, AFRL,     set_AFRL,     AFRL);
-  reg_rw!(GPIO, u32, AFRH,     set_AFRH,     AFRH);
+  ioregs!(GPIO = {
+    0x0 => reg32 moder {
+      0..31 => mode[16] {
+        0 => Input,
+        1 => Output,
+        3 => Alternate,
+        4 => Analog
+      }
+    }
+    0x04 => reg32 otyper {
+      0..15 => ot[16] {
+        0 => PushPull,
+        1 => OpenDrain
+      }
+    }
+    0x08 => reg32 ospeedr {
+      0..31 => ospeed[16] {
+        0 => Low,
+        1 => Medium,
+        2 => Fast,
+        3 => High
+      }
+    }
+    0x0c => reg32 pupdr {
+      0..31 => pupd[16] {
+        0 => None,
+        1 => PullUp,
+        2 => PullDown
+      }
+    }
+    0x10 => reg32 idr {
+      0..15 => id[16]: ro
+    }
+    0x14 => reg32 odr {
+      0..15 => od[16]
+    }
+    0x18 => reg32 bsrr {
+      0..15 => bs[16]: wo,
+      16..31 => br[16]: wo
+    }
+    0x1c => reg32 lckr {
+      0..15 => lck[16],
+      16 => lckk
+    }
+    0x20 => reg32 afrl {
+      0..31 => afrl[8]
+    }
+    0x24 => reg32 afrh {
+      0..31 => afrh[8]
+    }
+  });
 
   extern {
     #[link_name="stm32f4_iomem_GPIOA"] pub static GPIO_A: GPIO;