From 640097d1f2a6e67986192fc97032ac2931984afa Mon Sep 17 00:00:00 2001 From: Isaac Foster Date: Sun, 29 Jun 2025 22:59:59 -0400 Subject: [PATCH] Update paging-development-notes.md typo Signed-off-by: Isaac Foster --- docs/paging-development-notes.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/paging-development-notes.md b/docs/paging-development-notes.md index ae63f1a18..e1f4d3c0b 100644 --- a/docs/paging-development-notes.md +++ b/docs/paging-development-notes.md @@ -1,6 +1,6 @@ # Paging in Hyperlight -Hyperlight uses paging, which means the all addresses inside a Hyperlight VM are treated as virtual addresses by the processor. Specifically, Hyperlight uses (ordinary) 4-level paging. 4-level paging is used because we set the following control registers on logical cores inside a VM: `CR0.PG = 1, CR4.PAE = 1, IA32_EFER.LME = 1, and CR4.LA57 = 0`. A Hyperlight VM is limited to 1GB of addressable memory, see below for more details. These control register settings have the following effects: +Hyperlight uses paging, which means that all addresses inside a Hyperlight VM are treated as virtual addresses by the processor. Specifically, Hyperlight uses (ordinary) 4-level paging. 4-level paging is used because we set the following control registers on logical cores inside a VM: `CR0.PG = 1, CR4.PAE = 1, IA32_EFER.LME = 1, and CR4.LA57 = 0`. A Hyperlight VM is limited to 1GB of addressable memory, see below for more details. These control register settings have the following effects: - `CR0.PG = 1`: Enables paging - `CR4.PAE = 1`: Enables Physical Address Extension (PAE) mode (this is required for 4-level paging)