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Merge tag 'arc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc
Pull ARC updates from Vineet Gupta: - fixes for -Wmissing-prototype warnings - missing compiler barrier in relaxed atomics - some uaccess simplification, declutter - removal of massive glocal struct cpuinfo_arc from bootlog code - __switch_to consolidation (removal of inline asm variant) - use GP to cache task pointer (vs. r25) - misc rework of entry code * tag 'arc-6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (24 commits) ARC: boot log: fix warning arc: Explicitly include correct DT includes ARC: pt_regs: create seperate type for ecr ARCv2: entry: rearrange pt_regs slightly ARC: entry: replace 8 byte ADD.ne with 4 byte ADD2.ne ARC: entry: replace 8 byte OR with 4 byte BSET ARC: entry: Add more common chores to EXCEPTION_PROLOGUE ARC: entry: EV_MachineCheck dont re-read ECR ARC: entry: ARcompact EV_ProtV to use r10 directly ARC: entry: rework (non-functional) ARC: __switch_to: move ksp to thread_info from thread_struct ARC: __switch_to: asm with dwarf ops (vs. inline asm) ARC: kernel stack: INIT_THREAD need not setup @init_stack in @ksp ARC: entry: use gp to cache task pointer (vs. r25) ARC: boot log: eliminate struct cpuinfo_arc #4: boot log per ISA ARC: boot log: eliminate struct cpuinfo_arc #3: don't export ARC: boot log: eliminate struct cpuinfo_arc #2: cache ARC: boot log: eliminate struct cpuinfo_arc #1: mm ARCv2: memset: don't prefetch for len == 0 which happens a alot ARC: uaccess: elide unaliged handling if hardware supports ...
2 parents ea4f9c3 + c40cad3 commit 3f86ed6

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lines changed

‎arch/arc/Kconfig

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@ config ARC
2727
select GENERIC_SCHED_CLOCK
2828
select GENERIC_SMP_IDLE_THREAD
2929
select GENERIC_IOREMAP
30+
select GENERIC_STRNCPY_FROM_USER if MMU
31+
select GENERIC_STRNLEN_USER if MMU
3032
select HAVE_ARCH_KGDB
3133
select HAVE_ARCH_TRACEHOOK
3234
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
@@ -491,11 +493,11 @@ config ARC_KVADDR_SIZE
491493
kernel-user gutter)
492494

493495
config ARC_CURR_IN_REG
494-
bool "Dedicate Register r25 for current_task pointer"
496+
bool "cache current task pointer in gp"
495497
default y
496498
help
497-
This reserved Register R25 to point to Current Task in
498-
kernel mode. This saves memory access for each such access
499+
This reserves gp register to point to Current Task in
500+
kernel mode eliding memory access for each access
499501

500502

501503
config ARC_EMUL_UNALIGNED

‎arch/arc/Makefile

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,14 @@ cflags-y += $(tune-mcpu-def-y)
2828
endif
2929
endif
3030

31-
3231
ifdef CONFIG_ARC_CURR_IN_REG
3332
# For a global register definition, make sure it gets passed to every file
3433
# We had a customer reported bug where some code built in kernel was NOT using
35-
# any kernel headers, and missing the r25 global register
34+
# any kernel headers, and missing the global register
3635
# Can't do unconditionally because of recursive include issues
3736
# due to <linux/thread_info.h>
3837
LINUXINCLUDE += -include $(srctree)/arch/arc/include/asm/current.h
38+
cflags-y += -ffixed-gp
3939
endif
4040

4141
cflags-y += -fsection-anchors
@@ -67,7 +67,7 @@ cflags-$(CONFIG_ARC_DW2_UNWIND) += -fasynchronous-unwind-tables $(cfi)
6767
# small data is default for elf32 tool-chain. If not usable, disable it
6868
# This also allows repurposing GP as scratch reg to gcc reg allocator
6969
disable_small_data := y
70-
cflags-$(disable_small_data) += -mno-sdata -fcall-used-gp
70+
cflags-$(disable_small_data) += -mno-sdata
7171

7272
cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mbig-endian
7373
ldflags-$(CONFIG_CPU_BIG_ENDIAN) += -EB

‎arch/arc/include/asm/arcregs.h

Lines changed: 55 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
2424
#define ARC_REG_XY_MEM_BCR 0x79
2525
#define ARC_REG_MAC_BCR 0x7a
26-
#define ARC_REG_MUL_BCR 0x7b
26+
#define ARC_REG_MPY_BCR 0x7b
2727
#define ARC_REG_SWAP_BCR 0x7c
2828
#define ARC_REG_NORM_BCR 0x7d
2929
#define ARC_REG_MIXMAX_BCR 0x7e
@@ -177,14 +177,67 @@ struct bcr_isa_arcv2 {
177177
#endif
178178
};
179179

180-
struct bcr_uarch_build_arcv2 {
180+
struct bcr_uarch_build {
181181
#ifdef CONFIG_CPU_BIG_ENDIAN
182182
unsigned int pad:8, prod:8, maj:8, min:8;
183183
#else
184184
unsigned int min:8, maj:8, prod:8, pad:8;
185185
#endif
186186
};
187187

188+
struct bcr_mmu_3 {
189+
#ifdef CONFIG_CPU_BIG_ENDIAN
190+
unsigned int ver:8, ways:4, sets:4, res:3, sasid:1, pg_sz:4,
191+
u_itlb:4, u_dtlb:4;
192+
#else
193+
unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, sasid:1, res:3, sets:4,
194+
ways:4, ver:8;
195+
#endif
196+
};
197+
198+
struct bcr_mmu_4 {
199+
#ifdef CONFIG_CPU_BIG_ENDIAN
200+
unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
201+
n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
202+
#else
203+
/* DTLB ITLB JES JE JA */
204+
unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
205+
pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
206+
#endif
207+
};
208+
209+
struct bcr_cache {
210+
#ifdef CONFIG_CPU_BIG_ENDIAN
211+
unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
212+
#else
213+
unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
214+
#endif
215+
};
216+
217+
struct bcr_slc_cfg {
218+
#ifdef CONFIG_CPU_BIG_ENDIAN
219+
unsigned int pad:24, way:2, lsz:2, sz:4;
220+
#else
221+
unsigned int sz:4, lsz:2, way:2, pad:24;
222+
#endif
223+
};
224+
225+
struct bcr_clust_cfg {
226+
#ifdef CONFIG_CPU_BIG_ENDIAN
227+
unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
228+
#else
229+
unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
230+
#endif
231+
};
232+
233+
struct bcr_volatile {
234+
#ifdef CONFIG_CPU_BIG_ENDIAN
235+
unsigned int start:4, limit:4, pad:22, order:1, disable:1;
236+
#else
237+
unsigned int disable:1, order:1, pad:22, limit:4, start:4;
238+
#endif
239+
};
240+
188241
struct bcr_mpy {
189242
#ifdef CONFIG_CPU_BIG_ENDIAN
190243
unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
@@ -302,48 +355,6 @@ struct bcr_generic {
302355
#endif
303356
};
304357

305-
/*
306-
*******************************************************************
307-
* Generic structures to hold build configuration used at runtime
308-
*/
309-
310-
struct cpuinfo_arc_mmu {
311-
unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
312-
unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
313-
};
314-
315-
struct cpuinfo_arc_cache {
316-
unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
317-
};
318-
319-
struct cpuinfo_arc_bpu {
320-
unsigned int ver, full, num_cache, num_pred, ret_stk;
321-
};
322-
323-
struct cpuinfo_arc_ccm {
324-
unsigned int base_addr, sz;
325-
};
326-
327-
struct cpuinfo_arc {
328-
struct cpuinfo_arc_cache icache, dcache, slc;
329-
struct cpuinfo_arc_mmu mmu;
330-
struct cpuinfo_arc_bpu bpu;
331-
struct bcr_identity core;
332-
struct bcr_isa_arcv2 isa;
333-
const char *release, *name;
334-
unsigned int vec_base;
335-
struct cpuinfo_arc_ccm iccm, dccm;
336-
struct {
337-
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
338-
fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
339-
ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
340-
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
341-
} extn;
342-
struct bcr_mpy extn_mpy;
343-
};
344-
345-
extern struct cpuinfo_arc cpuinfo_arc700[];
346-
347358
static inline int is_isa_arcv2(void)
348359
{
349360
return IS_ENABLED(CONFIG_ISA_ARCV2);

‎arch/arc/include/asm/atomic-llsc.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ static inline void arch_atomic_##op(int i, atomic_t *v) \
1818
: [val] "=&r" (val) /* Early clobber to prevent reg reuse */ \
1919
: [ctr] "r" (&v->counter), /* Not "m": llock only supports reg direct addr mode */ \
2020
[i] "ir" (i) \
21-
: "cc"); \
21+
: "cc", "memory"); \
2222
} \
2323

2424
#define ATOMIC_OP_RETURN(op, asm_op) \
@@ -34,7 +34,7 @@ static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
3434
: [val] "=&r" (val) \
3535
: [ctr] "r" (&v->counter), \
3636
[i] "ir" (i) \
37-
: "cc"); \
37+
: "cc", "memory"); \
3838
\
3939
return val; \
4040
}
@@ -56,7 +56,7 @@ static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
5656
[orig] "=&r" (orig) \
5757
: [ctr] "r" (&v->counter), \
5858
[i] "ir" (i) \
59-
: "cc"); \
59+
: "cc", "memory"); \
6060
\
6161
return orig; \
6262
}

‎arch/arc/include/asm/atomic64-arcv2.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ static inline void arch_atomic64_##op(s64 a, atomic64_t *v) \
6060
" bnz 1b \n" \
6161
: "=&r"(val) \
6262
: "r"(&v->counter), "ir"(a) \
63-
: "cc"); \
63+
: "cc", "memory"); \
6464
} \
6565

6666
#define ATOMIC64_OP_RETURN(op, op1, op2) \
@@ -77,7 +77,7 @@ static inline s64 arch_atomic64_##op##_return_relaxed(s64 a, atomic64_t *v) \
7777
" bnz 1b \n" \
7878
: [val] "=&r"(val) \
7979
: "r"(&v->counter), "ir"(a) \
80-
: "cc"); /* memory clobber comes from smp_mb() */ \
80+
: "cc", "memory"); \
8181
\
8282
return val; \
8383
}
@@ -99,7 +99,7 @@ static inline s64 arch_atomic64_fetch_##op##_relaxed(s64 a, atomic64_t *v) \
9999
" bnz 1b \n" \
100100
: "=&r"(orig), "=&r"(val) \
101101
: "r"(&v->counter), "ir"(a) \
102-
: "cc"); /* memory clobber comes from smp_mb() */ \
102+
: "cc", "memory"); \
103103
\
104104
return orig; \
105105
}

‎arch/arc/include/asm/current.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313

1414
#ifdef CONFIG_ARC_CURR_IN_REG
1515

16-
register struct task_struct *curr_arc asm("r25");
16+
register struct task_struct *curr_arc asm("gp");
1717
#define current (curr_arc)
1818

1919
#else

‎arch/arc/include/asm/dwarf.h

Lines changed: 20 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -10,23 +10,31 @@
1010

1111
#ifdef ARC_DW2_UNWIND_AS_CFI
1212

13-
#define CFI_STARTPROC .cfi_startproc
14-
#define CFI_ENDPROC .cfi_endproc
15-
#define CFI_DEF_CFA .cfi_def_cfa
16-
#define CFI_REGISTER .cfi_register
17-
#define CFI_REL_OFFSET .cfi_rel_offset
18-
#define CFI_UNDEFINED .cfi_undefined
13+
#define CFI_STARTPROC .cfi_startproc
14+
#define CFI_ENDPROC .cfi_endproc
15+
#define CFI_DEF_CFA .cfi_def_cfa
16+
#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
17+
#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
18+
#define CFI_OFFSET .cfi_offset
19+
#define CFI_REL_OFFSET .cfi_rel_offset
20+
#define CFI_REGISTER .cfi_register
21+
#define CFI_RESTORE .cfi_restore
22+
#define CFI_UNDEFINED .cfi_undefined
1923

2024
#else
2125

2226
#define CFI_IGNORE #
2327

24-
#define CFI_STARTPROC CFI_IGNORE
25-
#define CFI_ENDPROC CFI_IGNORE
26-
#define CFI_DEF_CFA CFI_IGNORE
27-
#define CFI_REGISTER CFI_IGNORE
28-
#define CFI_REL_OFFSET CFI_IGNORE
29-
#define CFI_UNDEFINED CFI_IGNORE
28+
#define CFI_STARTPROC CFI_IGNORE
29+
#define CFI_ENDPROC CFI_IGNORE
30+
#define CFI_DEF_CFA CFI_IGNORE
31+
#define CFI_DEF_CFA_OFFSET CFI_IGNORE
32+
#define CFI_DEF_CFA_REGISTER CFI_IGNORE
33+
#define CFI_OFFSET CFI_IGNORE
34+
#define CFI_REL_OFFSET CFI_IGNORE
35+
#define CFI_REGISTER CFI_IGNORE
36+
#define CFI_RESTORE CFI_IGNORE
37+
#define CFI_UNDEFINED CFI_IGNORE
3038

3139
#endif /* !ARC_DW2_UNWIND_AS_CFI */
3240

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