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dragoniteArmdragoniteArm
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GPIO port (ARMmbed#26)
* GPIO port * fixed hw_types * delete TODO * remove ARCM_BASE * fixed naming issue
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4 files changed

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-43
lines changed

4 files changed

+136
-43
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‎targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/PinNames.h

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -104,10 +104,11 @@ typedef enum {
104104
PIN_63 = P63,
105105
PIN_64 = P64,
106106

107-
// TODO: Use the right pin
108-
LED1 = P64,
107+
//LED 1 => RED, LED 2 => YELLOW, LED 3 = GREEN
108+
LED1 = PIN_64,
109+
LED2 = PIN_01,
110+
LED3 = PIN_02,
109111

110-
// TODO: Use the right pins
111112
// UART0
112113
USBTX = PIN_55,
113114
USBRX = PIN_57,

‎targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/device/CC3220SF.h

Lines changed: 0 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -181,26 +181,6 @@ typedef struct
181181
//__IO uint32_t CC; /*!< Address offset : 0xFC8 */
182182
} CC3220SF_UART_TypeDef;
183183

184-
/* =========================================================================================================================== */
185-
/* ================ GPIO ================ */
186-
/* =========================================================================================================================== */
187-
188-
/**
189-
* @brief GPIO
190-
*/
191-
typedef struct
192-
{
193-
// TODO ! These are just placeholders and are not accurate!
194-
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
195-
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
196-
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
197-
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
198-
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
199-
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
200-
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
201-
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
202-
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
203-
} CC3220SF_GPIO_TypeDef;
204184

205185

206186
/* =========================================================================================================================== */
@@ -272,19 +252,6 @@ typedef struct
272252
#define CC3220SF_UART0 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA0_BASE)
273253
#define CC3220SF_UART1 ((CC3220SF_UART_TypeDef *) CC3220SF_UARTA1_BASE)
274254

275-
276-
/******************************************************************************/
277-
/* */
278-
/* GPIO */
279-
/* */
280-
/******************************************************************************/
281-
282-
#define CC3220SF_GPIO0 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA0_BASE)
283-
#define CC3220SF_GPIO1 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA1_BASE)
284-
#define CC3220SF_GPIO2 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA2_BASE)
285-
#define CC3220SF_GPIO3 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA3_BASE)
286-
#define CC3220SF_GPIO4 ((CC3220SF_GPIO_TypeDef *) CC3220SF_GPIOA4_BASE)
287-
288255
/**
289256
* @}
290257
*/

‎targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/gpio_api.c

Lines changed: 131 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,87 @@
1515
*/
1616
#include "gpio_api.h"
1717
#include "pinmap.h"
18+
#include <ti/devices/cc32xx/inc/hw_types.h>
19+
#include <ti/devices/cc32xx/driverlib/pin.h>
20+
#include <ti/devices/cc32xx/driverlib/gpio.h>
21+
#include <ti/devices/cc32xx/inc/hw_ints.h>
22+
#include <ti/devices/cc32xx/driverlib/prcm.h>
23+
24+
#define PIN_RESERVED 0xFF
25+
26+
27+
28+
static const unsigned long g_ulPinToGPIOPinBit[64] =
29+
{
30+
GPIO_PIN_2,GPIO_PIN_3,GPIO_PIN_4,GPIO_PIN_5,GPIO_PIN_6,GPIO_PIN_7,GPIO_PIN_0,GPIO_PIN_1,255,255,GPIO_PIN_2,
31+
GPIO_PIN_3,GPIO_PIN_4,GPIO_PIN_5,GPIO_PIN_6,GPIO_PIN_7,GPIO_PIN_0,255,GPIO_PIN_4,GPIO_PIN_5,GPIO_PIN_1,255,
32+
255,255,255,255,255,255,255,255,255,255,255,
33+
255,255,255,255,255,255,255,255,255,255,255,
34+
GPIO_PIN_7,255,255,255,255,GPIO_PIN_0,255,255,GPIO_PIN_6,255,GPIO_PIN_1,
35+
255,GPIO_PIN_2,GPIO_PIN_3,GPIO_PIN_4,GPIO_PIN_5,GPIO_PIN_6,GPIO_PIN_7,GPIO_PIN_0,GPIO_PIN_1
36+
};
37+
38+
/* Table of GPIO input types */
39+
const uint16_t inPinTypes [] = {
40+
PIN_TYPE_STD, /* GPIO_CFG_IN_NOPULL */
41+
PIN_TYPE_STD_PD, /* GPIO_CFG_IN_PD */
42+
PIN_TYPE_STD_PU /* GPIO_CFG_IN_PU */
43+
44+
};
45+
46+
/* Table of GPIO output types */
47+
const uint16_t outPinTypes [] = {
48+
PIN_TYPE_STD, /* GPIO_CFG_OUT_STD */
49+
PIN_TYPE_OD_PD, /* GPIO_CFG_OUT_OD_PD */
50+
PIN_TYPE_OD_PU, /* GPIO_CFG_OUT_OD_PU */
51+
PIN_TYPE_OD /* GPIO_CFG_OUT_OD_NOPULL */
52+
};
53+
54+
/* Table of GPIO drive strengths */
55+
const uint16_t outPinStrengths [] = {
56+
PIN_STRENGTH_2MA, /* GPIO_CFG_OUT_STR_LOW */
57+
PIN_STRENGTH_4MA, /* GPIO_CFG_OUT_STR_MED */
58+
PIN_STRENGTH_6MA /* GPIO_CFG_OUT_STR_HIGH */
59+
};
60+
61+
static const PinMap PinMap_GPIO[] = {
62+
{PIN_50, CC3220SF_GPIOA0_BASE, 0}, //GPIO_00 (PM/Dig Mux)
63+
{PIN_55, CC3220SF_GPIOA0_BASE, 0}, //GPIO_01
64+
{PIN_57, CC3220SF_GPIOA0_BASE, 0}, //GPIO_02 (Dig/ADC Mux)
65+
{PIN_58, CC3220SF_GPIOA0_BASE, 0}, //GPIO_03 (Dig/ADC Mux)
66+
{PIN_59, CC3220SF_GPIOA0_BASE, 0}, //GPIO_04 (Dig/ADC Mux)
67+
{PIN_60, CC3220SF_GPIOA0_BASE, 0}, //GPIO_05 (Dig/ADC Mux)
68+
{PIN_61, CC3220SF_GPIOA0_BASE, 0}, //GPIO_06
69+
{PIN_62, CC3220SF_GPIOA0_BASE, 0}, //GPIO_07
70+
71+
{PIN_63, CC3220SF_GPIOA1_BASE, 0}, //GPIO_08
72+
{PIN_64, CC3220SF_GPIOA1_BASE, 0}, //GPIO_09
73+
{PIN_01, CC3220SF_GPIOA1_BASE, 0}, //GPIO_10
74+
{PIN_02, CC3220SF_GPIOA1_BASE, 0}, //GPIO_11
75+
{PIN_03, CC3220SF_GPIOA1_BASE, 0}, //GPIO_12
76+
{PIN_04, CC3220SF_GPIOA1_BASE, 0}, //GPIO_13
77+
{PIN_05, CC3220SF_GPIOA1_BASE, 0}, //GPIO_14
78+
{PIN_06, CC3220SF_GPIOA1_BASE, 0}, //GPIO_15
79+
80+
{PIN_07, CC3220SF_GPIOA2_BASE, 0}, //GPIO_16
81+
{PIN_08, CC3220SF_GPIOA2_BASE, 0}, //GPIO_17
82+
{PIN_RESERVED, CC3220SF_GPIOA2_BASE, 0}, //GPIO_18 (Reserved)
83+
{PIN_RESERVED, CC3220SF_GPIOA2_BASE, 0}, //GPIO_19 (Reserved)
84+
{PIN_RESERVED, CC3220SF_GPIOA2_BASE, 0}, //GPIO_20 (Reserved)
85+
{PIN_RESERVED, CC3220SF_GPIOA2_BASE, 0}, //GPIO_21 (Reserved)
86+
{PIN_15, CC3220SF_GPIOA2_BASE, 0}, //GPIO_22
87+
{PIN_16, CC3220SF_GPIOA2_BASE, 0}, //GPIO_23
88+
89+
{PIN_17, CC3220SF_GPIOA3_BASE, 0}, //GPIO_24
90+
{PIN_21, CC3220SF_GPIOA3_BASE, 0}, //GPIO_25
91+
{PIN_RESERVED, CC3220SF_GPIOA3_BASE, 0}, //GPIO_26 (Restricted Use; Antenna Selection 1 Only)
92+
{PIN_RESERVED, CC3220SF_GPIOA3_BASE, 0}, //GPIO_27 (Restricted Use; Antenna Selection 1 Only)
93+
{PIN_18, CC3220SF_GPIOA3_BASE, 0}, //GPIO_28
94+
{PIN_20, CC3220SF_GPIOA3_BASE, 0}, //GPIO_29
95+
{PIN_53, CC3220SF_GPIOA3_BASE, 0}, //GPIO_30 (PM/Dig Mux)
96+
{PIN_45, CC3220SF_GPIOA3_BASE, 0}, //GPIO_31 (PM/Dig Mux)
97+
{NC, NC, 0}
98+
};
1899

19100
// function to enable the GPIO pin
20101
uint32_t gpio_set(PinName pin)
@@ -27,17 +108,62 @@ uint32_t gpio_set(PinName pin)
27108
// with the object created for the pin
28109
void gpio_init(gpio_t *obj, PinName pin)
29110
{
30-
// TODO
111+
unsigned long gpio_base = (unsigned long)pinmap_peripheral(pin, PinMap_GPIO);
112+
obj->gpio_port_base_addr = gpio_base;
113+
obj->pin = pin;
114+
115+
116+
//figuring out PRCM GPIO CLOCK Index
117+
118+
unsigned short prcm_peripheral;
119+
switch (gpio_base)
120+
{
121+
case CC3220SF_GPIOA0_BASE:
122+
prcm_peripheral = PRCM_GPIOA0;
123+
break;
124+
125+
case CC3220SF_GPIOA1_BASE:
126+
prcm_peripheral = PRCM_GPIOA1;
127+
break;
128+
129+
case CC3220SF_GPIOA2_BASE:
130+
prcm_peripheral = PRCM_GPIOA2;
131+
break;
132+
133+
case CC3220SF_GPIOA3_BASE:
134+
prcm_peripheral = PRCM_GPIOA3;
135+
break;
136+
default:
137+
break;
138+
}
139+
140+
//initialize GPIO PORT clock
141+
PRCMPeripheralClkEnable(prcm_peripheral, PRCM_RUN_MODE_CLK || PRCM_SLP_MODE_CLK);
142+
143+
//wait until gpio clock settle
144+
while(!PRCMPeripheralStatusGet(prcm_peripheral)){}
145+
31146
}
32147

33148
void gpio_mode(gpio_t *obj, PinMode mode)
34149
{
35-
// TODO
150+
obj->mode = mode;
151+
152+
153+
if(obj->dir == PIN_INPUT){ //setting the correct input pin mode from STD, PULL_UP, or PULL_DOWN
154+
PinModeSet(obj->pin, inPinTypes[mode]);
155+
}
156+
else if(obj->dir == PIN_OUTPUT){ //setting the correct output pin mode from STD, open-drain PULL_UP, or open drain PULL_DOWN. It seem that Mbed does not have an option for open-drain no pull
157+
PinModeSet(obj->pin, outPinTypes[mode]);
158+
PinConfigSet(obj->pin,outPinStrengths[0],outPinTypes[mode]);
159+
}
160+
36161
}
37162

38163
void gpio_dir(gpio_t *obj, PinDirection direction)
39164
{
40-
// TODO
165+
obj->dir = direction;
166+
GPIODirModeSet(obj->gpio_port_base_addr, g_ulPinToGPIOPinBit[obj->pin],direction);
41167
}
42168

43169
int gpio_is_connected(const gpio_t *obj)
@@ -48,11 +174,10 @@ int gpio_is_connected(const gpio_t *obj)
48174

49175
void gpio_write(gpio_t *obj, int value)
50176
{
51-
//TODO
177+
GPIOPinWrite(obj->gpio_port_base_addr, g_ulPinToGPIOPinBit[obj->pin], value<<(g_ulPinToGPIOPinBit[obj->pin]>>1));
52178
}
53179

54180
int gpio_read(gpio_t *obj)
55181
{
56-
//TODO
57-
return 0;
182+
return (int)GPIOPinRead(obj->gpio_port_base_addr,g_ulPinToGPIOPinBit[obj->pin]);
58183
}

‎targets/TARGET_TI/TARGET_CC32XX/TARGET_CC3220SF/objects.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ extern "C" {
2727

2828
typedef struct {
2929
// TODO ! this is just a placeholder!
30-
CC3220SF_GPIO_TypeDef *gpio;
30+
unsigned long gpio_port_base_addr;
3131
PinName pin;
3232
PinMode mode;
3333
PinDirection dir;

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