diff --git a/Config.in b/Config.in index 21c103eb..2a383f07 100644 --- a/Config.in +++ b/Config.in @@ -11,6 +11,7 @@ source "$BR2_EXTERNAL_MCHP_PATH/package/wilcmchp_firmware/Config.in" source "$BR2_EXTERNAL_MCHP_PATH/package/9bit/Config.in" source "$BR2_EXTERNAL_MCHP_PATH/package/plplot/Config.in" source "$BR2_EXTERNAL_MCHP_PATH/package/mpfs_examples/Config.in" +source "$BR2_EXTERNAL_MCHP_PATH/package/hart-software-services/Config.in" source "$BR2_EXTERNAL_MCHP_PATH/package/hss-payload-generator/Config.in.host" source "$BR2_EXTERNAL_MCHP_PATH/package/mpfs_amp_examples/Config.in" diff --git a/board/microchip/polarberry/FLASH_CONFIG.CONF b/board/microchip/polarberry/FLASH_CONFIG.CONF new file mode 100644 index 00000000..4f2a163d --- /dev/null +++ b/board/microchip/polarberry/FLASH_CONFIG.CONF @@ -0,0 +1,5 @@ +BUILDROOT_DIRECTORY="/home/sundancedsp_polarberry/buildroot-2023.08.1" #set here path the buildroot you are used for building +UART_DEVICE="/dev/ttyUSB0" #set here POLARBERRY board UART device in linux +DEVICE_IP="192.168.1.72" #set here IP ADDRESS used for POLARBERRY board that you want to flash +PC_IP="192.168.1.177" #set here IP ADDRESS of you PC +IMAGE_NAME="fitimage_polarberry.itb" #set here file name of the linux image (it shall be placed in the TFTP directory) diff --git a/board/microchip/polarberry/README b/board/microchip/polarberry/README new file mode 100644 index 00000000..a6f0949b --- /dev/null +++ b/board/microchip/polarberry/README @@ -0,0 +1,100 @@ + +There are 4 scipts: +1) Program_HSS_to_eNVM.sh +2) Program_UBOOT_to_eMMC.sh +3) Program_LINUX_to_eNVM.sh +4) Program_ALL_to_Polarberry.sh + +and settings file: FLASH_CONFIG.CONF + +Script is used to burn images to the Polarberry board. + +The 1th is used to program ONLY HSS bootloader umage to the Polarberry board. +The 2th is used to program ONLY UBOOT image to the Polarberry board. +The 3th is used to program ONLY LINUX (Kernel and root filesystem, bith) image to the Polarberry board. +The 4th is used to program ALL (HSS, UBOOT, LINUX) images to the Polarberry oard. + + +The 1th script can be used with virgin Polarberry boards and requires ONLY JTAG connection with the board. +The 2th script can be used only after 1th was used (it means UBOOT programming requires HSS was installed before) + and requires JTAG and UART connection with the board. +The 3th script can be used only after 2th was used (it means Linux programming requires UBOOT (as HSS toot) + was installed before) and requires JTAG, UART and ETHERNET connection with the board. +The 4th script runs 1,2,3 one-by-one and do all thunigs that do 1,2,3 in automatic mode and requires JTAG + UART and ETHERNET connection with the board. Can be used with virgin Polarberry boards too. + +Before script can be used, you need to fix values in FLASH_CONFIG.CONF according to your PC. +The file contains strings with comments, so you can advice what you need: + +BUILDROOT_DIRECTORY - here you need to set PATH to the buildroot you are using +UART_DEVICE - here you need to set the name of the UART in your system. (/dev/ttyUSB1 for example) +DEVICE_IP - here you need to set IP ADDRESS that will be set on the board during flashing. + It shall be one of the free/unused IP addresses from you network. + +PC_IP - here you need to set IP ADDRESS of the PC you are using. (It can be obtained via "ifconfig" command) +IMAGE_NAME - here you need to set file name with LINUX image that is placed on the TFTP server + (default value is "fitimage_polarberry.itb", and this file is built by buildroot and placed in "output/images" directory) + + +To start building images via buildroot you need to run this command in buildrood sources: +1) "make sundancedsp_polarberry_defconfig BR2_EXTERNAL=../buildroot-external-microchip" + (where BR2_EXTERNAL shall point to the mbuildroot microsemi sources). + +2) "make" + Building will take time. Succesfull building will finish like this: + +FIT description: Linux fitImage for Polaberry +Created: Wed Nov 22 05:06:16 2023 + Image 0 (kernel-0) + Description: Linux Kernel + Created: Wed Nov 22 05:06:16 2023 + Type: Kernel Image + Compression: uncompressed + Data Size: 17612800 Bytes = 17200.00 KiB = 16.80 MiB + Architecture: RISC-V + OS: Linux + Load Address: 0x80200000 + Entry Point: 0x80200000 + Hash algo: sha256 + Hash value: 466f36e4c778103ce7ef2fa9dc3456cb1e25d291fe71ab96f3d88ac588004f11 + Image 1 (fdt-0) + Description: Flattened Device Tree blob + Created: Wed Nov 22 05:06:16 2023 + Type: Flat Device Tree + Compression: uncompressed + Data Size: 14949 Bytes = 14.60 KiB = 0.01 MiB + Architecture: RISC-V + Hash algo: sha256 + Hash value: 1ccea6c67588f89a9227a5018b98048390728ef3a21ba90cbd69d8ab750843a4 + Image 2 (ramdisk-0) + Description: ramdisk + Created: Wed Nov 22 05:06:16 2023 + Type: RAMDisk Image + Compression: uncompressed + Data Size: 4921601 Bytes = 4806.25 KiB = 4.69 MiB + Architecture: AArch64 + OS: Linux + Load Address: unavailable + Entry Point: unavailable + Hash algo: sha256 + Hash value: cae144f8a5c8eb441ba01aae3d3dc1c88ea0303afe710e7d7528d04b0e963997 + Default Configuration: 'conf-1' + Configuration 0 (conf-1) + Description: Boot Linux kernel with FDT blob + ramdisk + Kernel: kernel-0 + Init Ramdisk: ramdisk-0 + FDT: fdt-0 + Hash algo: sha256 + Hash value: unavailable + Configuration 1 (conf-2) + Description: Boot Linux kernel with FDT blob + Kernel: kernel-0 + FDT: fdt-0 + Hash algo: sha256 + Hash value: unavailable + + +To flash the images to the Polarberry board: +1) Fix FLASH_CONFIG.CONF file in the board/microchip/polarberry directory. +2) Power ON the Polarberry board +3) run "Program_ALL_to_Polarberry.sh", and wait until all finished. diff --git a/board/microchip/polarberry/fitimage_polarberry.its b/board/microchip/polarberry/fitimage_polarberry.its new file mode 100644 index 00000000..7f0b1b11 --- /dev/null +++ b/board/microchip/polarberry/fitimage_polarberry.its @@ -0,0 +1,66 @@ +/dts-v1/; + +/ { + description = "Linux fitImage for Polaberry"; + #address-cells = <1>; + + images { + kernel-0 { + description = "Linux Kernel"; + data = /incbin/("images/Image"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "none"; + load = <0x80200000>; + entry = <0x80200000>; + hash-1 { + algo = "sha256"; + }; + }; + + fdt-0 { + description = "Flattened Device Tree blob"; + data = /incbin/("images/linux_polarberry.dtb"); + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + + ramdisk-0 { + description = "ramdisk"; + data = /incbin/("images/rootfs.cpio.bz2"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Boot Linux kernel with FDT blob + ramdisk"; + kernel = "kernel-0"; + fdt = "fdt-0"; + ramdisk = "ramdisk-0"; + hash-1 { + algo = "sha256"; + }; + }; + conf-2 { + description = "Boot Linux kernel with FDT blob"; + kernel = "kernel-0"; + fdt = "fdt-0"; + hash-1 { + algo = "sha256"; + }; + }; + }; +}; diff --git a/board/microchip/polarberry/linux/linux_polarberry.dts b/board/microchip/polarberry/linux/linux_polarberry.dts new file mode 100644 index 00000000..d50bf064 --- /dev/null +++ b/board/microchip/polarberry/linux/linux_polarberry.dts @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "microchip/mpfs.dtsi" +#include "microchip/mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Microchip POLARBERRY"; + compatible = "microchip,mpfs"; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; +// spi0 = &spi0; +// qspi = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + }; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy4>; + status = "disabled"; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy5>; + status = "okay"; + + phy4: ethernet-phy@4 { // This PHY is connected to mac0, but the port itself is on the (optional) carrier board. + reg = <4>; + }; + + phy5: ethernet-phy@5 { // This PHY is connected to mac1, but the port itself is on the SOM (PolarBerry) board. + reg = <5>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + // 0x72 = SI538A-B-GM + + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "n25q00a"; + reg = <0x0>; + + spi-max-frequency = <10000000>; + + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x2000000>; //32Mb + }; + + partition@2000000 { + label = "qspi-linux"; + reg = <0x2000000 0x6000000>; //96Mb + }; + }; +}; + + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; diff --git a/board/microchip/polarberry/linux/linux_polarberry_defconfig b/board/microchip/polarberry/linux/linux_polarberry_defconfig new file mode 100644 index 00000000..bbee7dbb --- /dev/null +++ b/board/microchip/polarberry/linux/linux_polarberry_defconfig @@ -0,0 +1,131 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_BPF=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SMP=y +CONFIG_CMDLINE="earlycon debug uio_pdrv_genirq.of_id=generic-uio" +CONFIG_JUMP_LABEL=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_MPFS_DMA_PROXY=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_MACB=y +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_POLARFIRE_SOC=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=m +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_MICROCHIP_CORE=y +CONFIG_SPI_MICROCHIP_CORE_QSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_POLARFIRE_SOC=y +CONFIG_POWER_RESET=y +CONFIG_PMBUS=m +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=m +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_POLARFIRE_SOC=y +CONFIG_USB_INVENTRA_DMA=y +CONFIG_USB_SERIAL=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SPI=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_POLARFIRE_SOC=y +CONFIG_DMADEVICES=y +CONFIG_SF_PDMA=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +# CONFIG_VHOST_MENU is not set +CONFIG_POLARFIRE_SOC_MAILBOX=y +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_MIV_REMOTEPROC=y +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_MIV=y +CONFIG_RPMSG_MIV_TTY=m +CONFIG_RPMSG_VIRTIO=y +CONFIG_POLARFIRE_SOC_SYS_CTRL=y +CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V4=m +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_UTF8=m +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_SCHEDSTATS=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_STACKTRACE=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m diff --git a/board/microchip/polarberry/patches/glibc/0001_risv_abi_compilation_error.patch b/board/microchip/polarberry/patches/glibc/0001_risv_abi_compilation_error.patch new file mode 100644 index 00000000..7a6481b8 --- /dev/null +++ b/board/microchip/polarberry/patches/glibc/0001_risv_abi_compilation_error.patch @@ -0,0 +1,12 @@ +diff -ruN a/sysdeps/unix/sysv/linux/riscv/Makefile b/sysdeps/unix/sysv/linux/riscv/Makefile +--- a/sysdeps/unix/sysv/linux/riscv/Makefile 2023-02-02 17:43:23.000000000 -0800 ++++ b/sysdeps/unix/sysv/linux/riscv/Makefile 2023-06-30 02:18:04.531347540 -0700 +@@ -7,7 +7,7 @@ + gen-as-const-headers += ucontext_i.sym + endif + +-abi-variants := ilp32 ilp32d lp64 lp64d ++abi-variants := ilp32 ilp32d lp64d + + ifeq (,$(filter $(default-abi),$(abi-variants))) + $(error Unknown ABI $(default-abi), must be one of $(abi-variants)) diff --git a/board/microchip/polarberry/patches/uboot/tftp_memory_override.patch b/board/microchip/polarberry/patches/uboot/tftp_memory_override.patch new file mode 100644 index 00000000..2f676078 --- /dev/null +++ b/board/microchip/polarberry/patches/uboot/tftp_memory_override.patch @@ -0,0 +1,12 @@ +diff -ruN A/net/tftp.c B/net/tftp.c +--- A/net/tftp.c 2023-10-31 02:41:28.000000000 -0700 ++++ B/net/tftp.c 2023-11-21 12:55:45.687374117 -0800 +@@ -22,6 +22,8 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#undef CONFIG_LMB ++ + /* Well known TFTP port # */ + #define WELL_KNOWN_PORT 69 + /* Millisecs to timeout for lost pkt */ diff --git a/board/microchip/polarberry/payload-config.yaml b/board/microchip/polarberry/payload-config.yaml new file mode 100644 index 00000000..3ca873cc --- /dev/null +++ b/board/microchip/polarberry/payload-config.yaml @@ -0,0 +1,36 @@ +# +# HSS Payload Generator - buildroot configuration file +# + +# First, we can optionally set a name for our image, otherwise one will be created dynamically +set-name: 'Polarberry Fire-SoC-HSS::U-Boot' + +# +# Next, we'll define the entry point addresses for each hart, as follows: +# +hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200000'} + +# +# Finally, we'll define a payloads (source binary file) that will be placed at certain regions in memory +# The payload section is defined with the keyword payloads, and then a number of individual +# payload descriptors. +# +# Each payload has a name (path to its ELF/bin file), an owner-hart, and optionally 1-3 secondary-harts. +# +# Additionally, it has a privilege mode in which it will start execution. +# * Valid privilege modes are PRV_M, PRV_S and PRV_U. +# +# +# In this case, the only payload is the u-boot s-mode binary. +# +# Case only matters for the ELF path names, not the keywords. +# +payloads: + src.bin: { + exec-addr: '0x80200000', + owner-hart: u54_1, + secondary-hart: u54_2, + secondary-hart: u54_3, + secondary-hart: u54_4, + priv-mode: prv_s + } diff --git a/board/microchip/polarberry/post-image.sh b/board/microchip/polarberry/post-image.sh new file mode 100755 index 00000000..3ace83f0 --- /dev/null +++ b/board/microchip/polarberry/post-image.sh @@ -0,0 +1,13 @@ +#!/bin/sh + +#Create FAT linux Image (linux kernel + rootfs + DTS) +cp -R output/images ${BR2_EXTERNAL_MCHP_PATH}/board/microchip/polarberry +/usr/bin/mkimage -A riscv -O linux -T flat_dt -f ${BR2_EXTERNAL_MCHP_PATH}/board/microchip/polarberry/fitimage_polarberry.its output/images/fitimage_polarberry.itb + +#Copy UBOOT adopted image to the TFTP server directory +#sudo cp output/images/payload.bin /srv/tftp + +#Copy Linux FTD image to the TFTP server directory +#sudo cp output/images/fitimage_polarberry.itb /srv/tftp + +#clean up diff --git a/board/microchip/polarberry/program_all.sh b/board/microchip/polarberry/program_all.sh new file mode 100755 index 00000000..a6f5d7a0 --- /dev/null +++ b/board/microchip/polarberry/program_all.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +./program_hss.sh +./program_uboot.sh + +echo "reset" > $UART_DEVICE + +./program_linux.sh diff --git a/board/microchip/polarberry/program_hss.sh b/board/microchip/polarberry/program_hss.sh new file mode 100755 index 00000000..dfc9d12e --- /dev/null +++ b/board/microchip/polarberry/program_hss.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +DEV_BOARD=`cat $BUILDROOT_DIRECTORY/.config | grep BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD | sed 's/BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD=//g' | sed 's/"//g'` +DEV_DIE=`cat $BUILDROOT_DIRECTORY/.config | grep BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE | sed 's/BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE=//g' | sed 's/"//g'` +DEV_PACKAGE=`cat $BUILDROOT_DIRECTORY/.config | grep BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE | sed 's/BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE=//g' | sed 's/"//g'` + +echo +echo "BOARD is set to $DEV_BOARD" +echo "DIE is set to $DEV_DIE" +echo "PACKAGE is set to $DEV_PACKAGE" +echo + +make -C $BUILDROOT_DIRECTORY/output/build/hart-software-services-next program BOARD=$DEV_BOARD DIE=$DEV_DIE PACKAGE=$DEV_PACKAGE diff --git a/board/microchip/polarberry/program_linux.sh b/board/microchip/polarberry/program_linux.sh new file mode 100755 index 00000000..28e36c88 --- /dev/null +++ b/board/microchip/polarberry/program_linux.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +stty -F $UART_DEVICE 115200 cs8 -cstopb -parenb raw + +printf "\t\n ***** WAITING FOR UBOOT *****" + +( + while test "${key}" != "SundanceDSP" + do + read -r uart + key=`echo $uart | grep "Model: SundanceDSP Polarberry" | awk '{print $2}'` +# echo $uart + done +) < $UART_DEVICE + +printf "\t\n ***** GOT THE TIMEOUT STRING FROM UBOOT *****" +sleep 1 +echo ".\n" > $UART_DEVICE +printf "\t\n ***** Starting programming linux image to the POLARBERRY board *****" +echo "setenv ipaddr $DEVICE_IP" > $UART_DEVICE +echo "setenv serverip $PC_IP" > $UART_DEVICE +echo "setenv bootfile $IMAGE_NAME" > $UART_DEVICE +echo "run flash_linux" > $UART_DEVICE +sleep 1 + +( + while test "${key}" != "MMC" + do + read -r uart + key=`echo $uart | grep "MMC write" | awk '{print $1}'` +# echo $uart + done +) < $UART_DEVICE + +printf "\t\n ***** Programming LINUX to the eMMC of the POLARBERRY board is DONE!!! *****" diff --git a/board/microchip/polarberry/program_uboot.sh b/board/microchip/polarberry/program_uboot.sh new file mode 100755 index 00000000..0283153e --- /dev/null +++ b/board/microchip/polarberry/program_uboot.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +stty -F $UART_DEVICE 115200 cs8 -cstopb -parenb raw + +printf "\t\n ***** WAITING FOR HSS *****" + +( + while test "${key}" != "Timeout" + do + read -r uart + key=`echo $uart | grep Timeout | awk '{print $1}'` + done +) < $UART_DEVICE + +printf "\t\n ***** GOT THE TIMEOUT STRING *****" + +echo "" > $UART_DEVICE +printf "\t\n Starting \"ymodem\" command" +echo "ymodem" > $UART_DEVICE +sleep 1 +printf "\t\n Starting init eMMC command" +echo "2" > $UART_DEVICE +sleep 1 +printf "\t\n Starting ymodem receiving command\n" +echo "3" > $UART_DEVICE +sleep 1 + +sz -b --ymodem $BUILDROOT_DIRECTORY/output/images/payload.bin > $UART_DEVICE < $UART_DEVICE + +printf "\t\n Saving the UBOOT to the eMMC memory" +echo "5" > $UART_DEVICE +sleep 2 +echo "6" > $UART_DEVICE +sleep 1 +printf "\t\n ***** Programming U-BOOT to the eMMC of the POLARBERRY board is DONE!!! *****" diff --git a/board/microchip/polarberry/rootfs_overlay/etc/init.d/S02modules b/board/microchip/polarberry/rootfs_overlay/etc/init.d/S02modules new file mode 100755 index 00000000..e68d8512 --- /dev/null +++ b/board/microchip/polarberry/rootfs_overlay/etc/init.d/S02modules @@ -0,0 +1,68 @@ +#!/bin/sh +######################################################################## +# +# Description : Module auto-loading script +# +# Authors : Zack Winkles +# +# Version : 00.00 +# +# Notes : +# +######################################################################## + +. /etc/sysconfig/functions + +# Assure that the kernel has module support. +[ -e /proc/ksyms -o -e /proc/modules ] || exit 0 + +case "${1}" in + start) + + # Exit if there's no modules file or there are no + # valid entries + [ -r /etc/sysconfig/modules ] && + egrep -qv '^($|#)' /etc/sysconfig/modules || + exit 0 + + boot_mesg -n "Loading modules:" ${INFO} + + # Only try to load modules if the user has actually given us + # some modules to load. + while read module args; do + + # Ignore comments and blank lines. + case "$module" in + ""|"#"*) continue ;; + esac + + # Attempt to load the module, making + # sure to pass any arguments provided. + modprobe ${module} ${args} >/dev/null + + # Print the module name if successful, + # otherwise take note. + if [ $? -eq 0 ]; then + boot_mesg -n " ${module}" ${NORMAL} + else + failedmod="${failedmod} ${module}" + fi + done < /etc/sysconfig/modules + + boot_mesg "" ${NORMAL} + # Print a message about successfully loaded + # modules on the correct line. + echo_ok + + # Print a failure message with a list of any + # modules that may have failed to load. + if [ -n "${failedmod}" ]; then + boot_mesg "Failed to load modules:${failedmod}" ${FAILURE} + echo_failure + fi + ;; + *) + echo "Usage: ${0} {start}" + exit 1 + ;; +esac \ No newline at end of file diff --git a/board/microchip/polarberry/rootfs_overlay/etc/network/interfaces b/board/microchip/polarberry/rootfs_overlay/etc/network/interfaces new file mode 100644 index 00000000..0d2d25a9 --- /dev/null +++ b/board/microchip/polarberry/rootfs_overlay/etc/network/interfaces @@ -0,0 +1,8 @@ +auto lo +iface lo inet loopback + +auto eth0 +iface eth0 inet static + address 192.168.1.72 + netmask 255.255.255.0 + diff --git a/board/microchip/polarberry/rootfs_overlay/etc/sysconfig/functions b/board/microchip/polarberry/rootfs_overlay/etc/sysconfig/functions new file mode 100644 index 00000000..099eb110 --- /dev/null +++ b/board/microchip/polarberry/rootfs_overlay/etc/sysconfig/functions @@ -0,0 +1,145 @@ +#!/bin/sh +####################################################################### +# +# Description : Run Level Control Functions +# +# Authors : Gerard Beekmans - gerard@linuxfromscratch.org +# +# Version : 00.00 +# +# Notes : With code based on Matthias Benkmann's simpleinit-msb +# http://winterdrache.de/linux/newboot/index.html +# +######################################################################## + +## Environmental setup +# Setup default values for environment +umask 022 +export PATH="/bin:/usr/bin:/sbin:/usr/sbin" + +# Signal sent to running processes to refresh their configuration +RELOADSIG="HUP" + +# Number of seconds between STOPSIG and FALLBACK when stopping processes +KILLDELAY="3" + +## Screen Dimensions +# Find current screen size +if [ -z "${COLUMNS}" ]; then + COLUMNS=$(stty size) + COLUMNS=${COLUMNS##* } +fi + +# When using remote connections, such as a serial port, stty size returns 0 +if [ "${COLUMNS}" = "0" ]; then + COLUMNS=80 +fi + +## Measurements for positioning result messages +COL=$((${COLUMNS} - 8)) +WCOL=$((${COL} - 2)) + +## Provide an echo that supports -e and -n +# If formatting is needed, $ECHO should be used +case "`echo -e -n test`" in + -[en]*) + ECHO=/bin/echo + ;; + *) + ECHO=echo + ;; +esac + +## Set Cursor Position Commands, used via $ECHO +SET_COL="\\033[${COL}G" # at the $COL char +SET_WCOL="\\033[${WCOL}G" # at the $WCOL char +CURS_UP="\\033[1A\\033[0G" # Up one line, at the 0'th char + +## Set color commands, used via $ECHO +# Please consult `man console_codes for more information +# under the "ECMA-48 Set Graphics Rendition" section +# +# Warning: when switching from a 8bit to a 9bit font, +# the linux console will reinterpret the bold (1;) to +# the top 256 glyphs of the 9bit font. This does +# not affect framebuffer consoles +NORMAL="\\033[0;39m" # Standard console grey +SUCCESS="\\033[1;32m" # Success is green +WARNING="\\033[1;33m" # Warnings are yellow +FAILURE="\\033[1;31m" # Failures are red +INFO="\\033[1;36m" # Information is light cyan +BRACKET="\\033[1;34m" # Brackets are blue + +STRING_LENGTH="0" # the length of the current message + +#******************************************************************************* +# Function - boot_mesg() +# +# Purpose: Sending information from bootup scripts to the console +# +# Inputs: $1 is the message +# $2 is the colorcode for the console +# +# Outputs: Standard Output +# +# Dependencies: - sed for parsing strings. +# - grep for counting string length. +# +# Todo: +#******************************************************************************* +boot_mesg() +{ + local ECHOPARM="" + + while true + do + case "${1}" in + -n) + ECHOPARM=" -n " + shift 1 + ;; + -*) + echo "Unknown Option: ${1}" + return 1 + ;; + *) + break + ;; + esac + done + + ## Figure out the length of what is to be printed to be used + ## for warning messages. + STRING_LENGTH=$((${#1} + 1)) + + # Print the message to the screen + ${ECHO} ${ECHOPARM} -e "${2}${1}" + +} + +boot_mesg_flush() +{ + # Reset STRING_LENGTH for next message + STRING_LENGTH="0" +} + +echo_ok() +{ + ${ECHO} -n -e "${CURS_UP}${SET_COL}${BRACKET}[${SUCCESS} OK ${BRACKET}]" + ${ECHO} -e "${NORMAL}" + boot_mesg_flush +} + +echo_failure() +{ + ${ECHO} -n -e "${CURS_UP}${SET_COL}${BRACKET}[${FAILURE} FAIL ${BRACKET}]" + ${ECHO} -e "${NORMAL}" + boot_mesg_flush +} + +echo_warning() +{ + ${ECHO} -n -e "${CURS_UP}${SET_COL}${BRACKET}[${WARNING} WARN ${BRACKET}]" + ${ECHO} -e "${NORMAL}" + boot_mesg_flush +} diff --git a/board/microchip/polarberry/rootfs_overlay/etc/sysconfig/modules b/board/microchip/polarberry/rootfs_overlay/etc/sysconfig/modules new file mode 100644 index 00000000..e69de29b diff --git a/board/microchip/polarberry/rootfs_overlay/etc/sysctl.conf b/board/microchip/polarberry/rootfs_overlay/etc/sysctl.conf new file mode 100644 index 00000000..25ae4d5a --- /dev/null +++ b/board/microchip/polarberry/rootfs_overlay/etc/sysctl.conf @@ -0,0 +1 @@ +kernel.panic = 1 diff --git a/board/microchip/polarberry/uboot/uboot_env.txt b/board/microchip/polarberry/uboot/uboot_env.txt new file mode 100644 index 00000000..ec214933 --- /dev/null +++ b/board/microchip/polarberry/uboot/uboot_env.txt @@ -0,0 +1,19 @@ +arch=riscv +cpu=riscv +board=polarberry +board_name=polarberry +vendor=sundancedsp +baudrate=115200 +soc=polarfire +autoload=1 +bootdelay=5 +reset=1 +ipaddr=192.168.1.72 +memaddr=0x90000000 +netmask=255.255.255.0 +serverip=192.168.1.177 +bootcmd=run mmcboot +bootfile=fitimage_polarberry.itb +netboot=tftpboot $memaddr; bootm $memaddr +flash_linux=tftp $memaddr; mmc erase 0x800 0x10000; mmc write $memaddr 0x800 0x10000 +mmcboot=mmc read $memaddr 0x800 0x10000 && bootm $memaddr diff --git a/board/microchip/polarberry/uboot/uboot_polarberry.dts b/board/microchip/polarberry/uboot/uboot_polarberry.dts new file mode 100644 index 00000000..85fb577f --- /dev/null +++ b/board/microchip/polarberry/uboot/uboot_polarberry.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Microchip Technology Inc. + * Padmarao Begari + */ + +/dts-v1/; + +#include "microchip-mpfs.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model = "Microchip POLARBERRY"; + compatible = "microchip,mpfs"; + + aliases { + serial0 = &uart0; + ethernet0 = &mac1; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = ; + }; + + kernel: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x4000000>; + label = "kernel"; + }; + + ddr_cached_low: memory@8a000000 { + device_type = "memory"; + reg = <0x0 0x8a000000 0x0 0x8000000>; + label = "cached-low"; + }; + + ddr_non_cached_low: memory@c4000000 { + device_type = "memory"; + reg = <0x0 0xc4000000 0x0 0x6000000>; + label = "non-cached-low"; + }; + + ddr_cached_high: memory@1022000000 { + device_type = "memory"; + reg = <0x10 0x22000000 0x0 0x5e000000>; + label = "cached-high"; + }; + + ddr_non_cached_high: memory@1412000000 { + device_type = "memory"; + reg = <0x14 0x12000000 0x0 0x10000000>; + label = "non-cached-high"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer { + compatible = "shared-dma-pool"; + reg = <0x10 0x3fc00000 0x0 0x400000>; + no-map; + }; + + dma_non_cached_low: non-cached-low-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>; + dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>; + }; + + dma_non_cached_high: non-cached-high-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x14 0x12000000 0x0 0x10000000>; + dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>; + }; + + fabricbuf0ddrc: buffer@88000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x88000000 0x0 0x2000000>; + no-map; + }; + + fabricbuf1ddrnc: buffer@c8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xc8000000 0x0 0x2000000>; + no-map; + }; + + fabricbuf2ddrncwcb: buffer@d8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xd8000000 0x0 0x2000000>; + no-map; + }; + }; + + udmabuf0 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-c0"; + minor-number = <0>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf0ddrc>; + sync-mode = <3>; + }; + + udmabuf1 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-nc0"; + minor-number = <1>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf1ddrnc>; + sync-mode = <3>; + }; + + udmabuf2 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-nc-wcb0"; + minor-number = <2>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf2ddrncwcb>; + sync-mode = <3>; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&mmc { + uboot,dm-pre-reloc; + + status = "okay"; + + max-frequency = <200000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; +}; + +&i2c0 { + uboot,dm-pre-reloc; + + status = "okay"; + clock-frequency = <100000>; + + // 0x72 = SI538A-B-GM +}; + +&i2c1 { + uboot,dm-pre-reloc; + + status = "okay"; + clock-frequency = <100000>; +}; + +&mac1 { + status = "okay"; + + local-mac-address = [56 34 00 FC 00 03]; + phy-mode = "sgmii"; + phy-handle = <&phy5>; + + phy4: ethernet-phy@4 { + reg = <4>; + ti,fifo-depth = <0x01>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; +}; + +&usb { + uboot,dm-pre-reloc; + + status = "okay"; + xlnx,tz-nonsecure = <0x1>; + xlnx,usb-polarity = <0x0>; + xlnx,usb-reset-mode = <0x2>; + dr_mode = "host"; +}; + +&spi0 { + uboot,dm-pre-reloc; + compatible = "microchip,mpfs-qspi"; + status = "okay"; + num-cs = <1>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "n25q00a"; + reg = <0x0>; + + spi-max-frequency = <10000000>; + + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x2000000>; //32Mb + }; + + partition@2000000 { + label = "qspi-linux"; + reg = <0x2000000 0x6000000>; //96Mb + }; + }; +}; diff --git a/board/microchip/polarberry/uboot/uboot_polarberry_defconfig b/board/microchip/polarberry/uboot/uboot_polarberry_defconfig new file mode 100644 index 00000000..1fa59718 --- /dev/null +++ b/board/microchip/polarberry/uboot/uboot_polarberry_defconfig @@ -0,0 +1,35 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="mpfs-polarberry" +CONFIG_SYS_PROMPT="POLARBERRY: U-boot> " +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x90000000 +CONFIG_TARGET_SUNDANCEDSP_POLARBERRY=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_SPI_BOOT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 +# CONFIG_CMD_MTDPARTS is not set +CONFIG_CMD_UBI=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_DEFAULT_ENV_FILE="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/uboot/uboot_env.txt" +CONFIG_DDR_SPD=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_USB=y diff --git a/board/microchip/som1-soc/.gitignore b/board/microchip/som1-soc/.gitignore new file mode 100644 index 00000000..c291c091 --- /dev/null +++ b/board/microchip/som1-soc/.gitignore @@ -0,0 +1 @@ +images diff --git a/board/microchip/som1-soc/FLASH_CONFIG.CONF b/board/microchip/som1-soc/FLASH_CONFIG.CONF new file mode 100644 index 00000000..217cf8a9 --- /dev/null +++ b/board/microchip/som1-soc/FLASH_CONFIG.CONF @@ -0,0 +1,5 @@ +BUILDROOT_DIRECTORY="/home/sundancedsp_som1_soc/buildroot-2023.08.1" #set here path the buildroot you are used for building +UART_DEVICE="/dev/ttyUSB0" #set here SOM1_SOM board UART device in linux +DEVICE_IP="192.168.1.72" #set here IP ADDRESS used for SOM1_SOC board that you want to flash +PC_IP="192.168.1.177" #set here IP ADDRESS of you PC +IMAGE_NAME="fitimage_som1-soc.itb" #set here file name of the linux image (it shall be placed in the TFTP directory) diff --git a/board/microchip/som1-soc/README b/board/microchip/som1-soc/README new file mode 100644 index 00000000..cf308f46 --- /dev/null +++ b/board/microchip/som1-soc/README @@ -0,0 +1,109 @@ +There are 4 scipts: +1) program_hss.sh +2) Program_uboot.sh +3) Program_linux.sh +4) Program_all.sh + +and settings file: FLASH_CONFIG.CONF + +Script is used to burn images to the Polarberry board. + +The 1th is used to program ONLY HSS bootloader umage to the Polarberry board. +The 2th is used to program ONLY UBOOT image to the Polarberry board. +The 3th is used to program ONLY LINUX (Kernel and root filesystem, bith) image to the Polarberry board. +The 4th is used to program ALL (HSS, UBOOT, LINUX) images to the Polarberry oard. + + +The 1th script can be used with virgin Polarberry boards and requires ONLY JTAG connection with the board. +The 2th script can be used only after 1th was used (it means UBOOT programming requires HSS was installed before) + and requires JTAG and UART connection with the board. +The 3th script can be used only after 2th was used (it means Linux programming requires UBOOT (as HSS toot) + was installed before) and requires JTAG, UART and ETHERNET connection with the board. +The 4th script runs 1,2,3 one-by-one and do all thunigs that do 1,2,3 in automatic mode and requires JTAG + UART and ETHERNET connection with the board. Can be used with virgin Polarberry boards too. + +Before script can be used, you need to fix values in FLASH_CONFIG.CONF according to your PC. +The file contains strings with comments, so you can advice what you need: + +BUILDROOT_DIRECTORY - here you need to set PATH to the buildroot you are using +UART_DEVICE - here you need to set the name of the UART in your system. (/dev/ttyUSB1 for example) +DEVICE_IP - here you need to set IP ADDRESS that will be set on the board during flashing. + It shall be one of the free/unused IP addresses from you network. + +PC_IP - here you need to set IP ADDRESS of the PC you are using. (It can be obtained via "ifconfig" command) +IMAGE_NAME - here you need to set file name with LINUX image that is placed on the TFTP server + (default value is "fitimage_polarberry.itb", and this file is built by buildroot and placed in "output/images" directory) + + +To start building images via buildroot you need: + +1) Microchip Softconsole shall be installed (Microchip-SoftConsole-v2022.2-RISC-V-747-linux-x64-installer.run) +2) Microchip Program Debug tools shall be installed (Program_Debug_PolarFire_v2023.2_SP1.bin) + +3) run this command in buildrood sources: + +3.1) "make sundancedsp_polarberry_defconfig BR2_EXTERNAL=../buildroot-external-microchip" + (where BR2_EXTERNAL shall point to the buildroot microsemi sources). + +3.2) "make" + + + + + Building will take time. Succesfull building will finish like this: + +FIT description: Linux fitImage for Polaberry +Created: Wed Nov 22 05:06:16 2023 + Image 0 (kernel-0) + Description: Linux Kernel + Created: Wed Nov 22 05:06:16 2023 + Type: Kernel Image + Compression: uncompressed + Data Size: 17612800 Bytes = 17200.00 KiB = 16.80 MiB + Architecture: RISC-V + OS: Linux + Load Address: 0x80200000 + Entry Point: 0x80200000 + Hash algo: sha256 + Hash value: 466f36e4c778103ce7ef2fa9dc3456cb1e25d291fe71ab96f3d88ac588004f11 + Image 1 (fdt-0) + Description: Flattened Device Tree blob + Created: Wed Nov 22 05:06:16 2023 + Type: Flat Device Tree + Compression: uncompressed + Data Size: 14949 Bytes = 14.60 KiB = 0.01 MiB + Architecture: RISC-V + Hash algo: sha256 + Hash value: 1ccea6c67588f89a9227a5018b98048390728ef3a21ba90cbd69d8ab750843a4 + Image 2 (ramdisk-0) + Description: ramdisk + Created: Wed Nov 22 05:06:16 2023 + Type: RAMDisk Image + Compression: uncompressed + Data Size: 4921601 Bytes = 4806.25 KiB = 4.69 MiB + Architecture: AArch64 + OS: Linux + Load Address: unavailable + Entry Point: unavailable + Hash algo: sha256 + Hash value: cae144f8a5c8eb441ba01aae3d3dc1c88ea0303afe710e7d7528d04b0e963997 + Default Configuration: 'conf-1' + Configuration 0 (conf-1) + Description: Boot Linux kernel with FDT blob + ramdisk + Kernel: kernel-0 + Init Ramdisk: ramdisk-0 + FDT: fdt-0 + Hash algo: sha256 + Hash value: unavailable + Configuration 1 (conf-2) + Description: Boot Linux kernel with FDT blob + Kernel: kernel-0 + FDT: fdt-0 + Hash algo: sha256 + Hash value: unavailable + + +To flash the images to the Polarberry board: +1) Fix FLASH_CONFIG.CONF file in the board/microchip/polarberry directory. +2) Power ON the Polarberry board +3) run "Program_ALL_to_Polarberry.sh", and wait until all finished. diff --git a/board/microchip/som1-soc/fitimage_som1-soc.its b/board/microchip/som1-soc/fitimage_som1-soc.its new file mode 100644 index 00000000..cb71db4d --- /dev/null +++ b/board/microchip/som1-soc/fitimage_som1-soc.its @@ -0,0 +1,66 @@ +/dts-v1/; + +/ { + description = "Linux fitImage for Polaberry"; + #address-cells = <1>; + + images { + kernel-0 { + description = "Linux Kernel"; + data = /incbin/("images/Image"); + type = "kernel"; + arch = "riscv"; + os = "linux"; + compression = "none"; + load = <0x80200000>; + entry = <0x80200000>; + hash-1 { + algo = "sha256"; + }; + }; + + fdt-0 { + description = "Flattened Device Tree blob"; + data = /incbin/("images/linux_som1-soc.dtb"); + type = "flat_dt"; + arch = "riscv"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + + ramdisk-0 { + description = "ramdisk"; + data = /incbin/("images/rootfs.cpio.bz2"); + type = "ramdisk"; + arch = "arm64"; + os = "linux"; + compression = "none"; + hash-1 { + algo = "sha256"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Boot Linux kernel with FDT blob + ramdisk"; + kernel = "kernel-0"; + fdt = "fdt-0"; + ramdisk = "ramdisk-0"; + hash-1 { + algo = "sha256"; + }; + }; + conf-2 { + description = "Boot Linux kernel with FDT blob"; + kernel = "kernel-0"; + fdt = "fdt-0"; + hash-1 { + algo = "sha256"; + }; + }; + }; +}; diff --git a/board/microchip/som1-soc/linux/linux_som1-soc.dts b/board/microchip/som1-soc/linux/linux_som1-soc.dts new file mode 100644 index 00000000..9b91a6f4 --- /dev/null +++ b/board/microchip/som1-soc/linux/linux_som1-soc.dts @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "microchip/mpfs.dtsi" +#include "microchip/mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Microchip SOM1-SOC"; + compatible = "microchip,mpfs"; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; +// spi0 = &spi0; +// qspi = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + }; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy4>; + status = "disabled"; + + phy4: ethernet-phy@4 { // This PHY is connected to mac0 + reg = <4>; + }; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy5>; + status = "okay"; + + phy5: ethernet-phy@5 { // This PHY is connected to mac1 + reg = <5>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + // 0x77 = SI5341A-D-GM + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "n25q00a"; + reg = <0x0>; + + spi-max-frequency = <10000000>; + + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x2000000>; //32Mb + }; + + partition@2000000 { + label = "qspi-linux"; + reg = <0x2000000 0x6000000>; //96Mb + }; + }; +}; + + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; diff --git a/board/microchip/som1-soc/linux/linux_som1-soc_defconfig b/board/microchip/som1-soc/linux/linux_som1-soc_defconfig new file mode 100644 index 00000000..bbee7dbb --- /dev/null +++ b/board/microchip/som1-soc/linux/linux_som1-soc_defconfig @@ -0,0 +1,131 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_BPF=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SMP=y +CONFIG_CMDLINE="earlycon debug uio_pdrv_genirq.of_id=generic-uio" +CONFIG_JUMP_LABEL=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_BLK_DEV_ZONED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCIE_MICROCHIP_HOST=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_MPFS_DMA_PROXY=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_MACB=y +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_POLARFIRE_SOC=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=m +CONFIG_I2C_MICROCHIP_CORE=y +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_MICROCHIP_CORE=y +CONFIG_SPI_MICROCHIP_CORE_QSPI=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_POLARFIRE_SOC=y +CONFIG_POWER_RESET=y +CONFIG_PMBUS=m +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=m +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_POLARFIRE_SOC=y +CONFIG_USB_INVENTRA_DMA=y +CONFIG_USB_SERIAL=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SPI=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_POLARFIRE_SOC=y +CONFIG_DMADEVICES=y +CONFIG_SF_PDMA=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +CONFIG_UIO_DMEM_GENIRQ=y +# CONFIG_VHOST_MENU is not set +CONFIG_POLARFIRE_SOC_MAILBOX=y +CONFIG_REMOTEPROC=y +CONFIG_REMOTEPROC_CDEV=y +CONFIG_MIV_REMOTEPROC=y +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_MIV=y +CONFIG_RPMSG_MIV_TTY=m +CONFIG_RPMSG_VIRTIO=y +CONFIG_POLARFIRE_SOC_SYS_CTRL=y +CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_FANOTIFY=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +CONFIG_EXFAT_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V4=m +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_UTF8=m +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_WQ_WATCHDOG=y +CONFIG_SCHEDSTATS=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_STACKTRACE=y +CONFIG_SAMPLES=y +CONFIG_SAMPLE_RPMSG_CLIENT=m diff --git a/board/microchip/som1-soc/patches/glibc/0001_risv_abi_compilation_error.patch b/board/microchip/som1-soc/patches/glibc/0001_risv_abi_compilation_error.patch new file mode 100644 index 00000000..7a6481b8 --- /dev/null +++ b/board/microchip/som1-soc/patches/glibc/0001_risv_abi_compilation_error.patch @@ -0,0 +1,12 @@ +diff -ruN a/sysdeps/unix/sysv/linux/riscv/Makefile b/sysdeps/unix/sysv/linux/riscv/Makefile +--- a/sysdeps/unix/sysv/linux/riscv/Makefile 2023-02-02 17:43:23.000000000 -0800 ++++ b/sysdeps/unix/sysv/linux/riscv/Makefile 2023-06-30 02:18:04.531347540 -0700 +@@ -7,7 +7,7 @@ + gen-as-const-headers += ucontext_i.sym + endif + +-abi-variants := ilp32 ilp32d lp64 lp64d ++abi-variants := ilp32 ilp32d lp64d + + ifeq (,$(filter $(default-abi),$(abi-variants))) + $(error Unknown ABI $(default-abi), must be one of $(abi-variants)) diff --git a/board/microchip/som1-soc/patches/uboot/tftp_memory_override.patch b/board/microchip/som1-soc/patches/uboot/tftp_memory_override.patch new file mode 100644 index 00000000..2f676078 --- /dev/null +++ b/board/microchip/som1-soc/patches/uboot/tftp_memory_override.patch @@ -0,0 +1,12 @@ +diff -ruN A/net/tftp.c B/net/tftp.c +--- A/net/tftp.c 2023-10-31 02:41:28.000000000 -0700 ++++ B/net/tftp.c 2023-11-21 12:55:45.687374117 -0800 +@@ -22,6 +22,8 @@ + + DECLARE_GLOBAL_DATA_PTR; + ++#undef CONFIG_LMB ++ + /* Well known TFTP port # */ + #define WELL_KNOWN_PORT 69 + /* Millisecs to timeout for lost pkt */ diff --git a/board/microchip/som1-soc/patches/uboot/uboot_som1-soc.patch b/board/microchip/som1-soc/patches/uboot/uboot_som1-soc.patch new file mode 100644 index 00000000..fab3f33f --- /dev/null +++ b/board/microchip/som1-soc/patches/uboot/uboot_som1-soc.patch @@ -0,0 +1,870 @@ +diff -ruN A/arch/riscv/dts/mpfs-som1-soc.dts B/arch/riscv/dts/mpfs-som1-soc.dts +--- A/arch/riscv/dts/mpfs-som1-soc.dts 1969-12-31 16:00:00.000000000 -0800 ++++ B/arch/riscv/dts/mpfs-som1-soc.dts 2023-11-29 07:47:48.010869002 -0800 +@@ -0,0 +1,214 @@ ++/dts-v1/; ++ ++#include "microchip-mpfs.dtsi" ++ ++/* Clock frequency (in Hz) of the rtcclk */ ++#define RTCCLK_FREQ 1000000 ++ ++/ { ++ model = "SundanceDSP Polarberry"; ++ compatible = "sundance,polarberry", "microchip,mpfs"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &mac1; ++ spi0 = &spi0; ++ }; ++ ++ chosen { ++ stdout-path = "serial0"; ++ }; ++ ++ cpus { ++ timebase-frequency = ; ++ }; ++ ++ kernel: memory@80000000 { ++ device_type = "memory"; ++ reg = <0x0 0x80000000 0x0 0x4000000>; ++ label = "kernel"; ++ }; ++ ++ ddr_cached_low: memory@8a000000 { ++ device_type = "memory"; ++ reg = <0x0 0x8a000000 0x0 0x8000000>; ++ label = "cached-low"; ++ }; ++ ++ ddr_non_cached_low: memory@c4000000 { ++ device_type = "memory"; ++ reg = <0x0 0xc4000000 0x0 0x6000000>; ++ label = "non-cached-low"; ++ }; ++ ++ ddr_cached_high: memory@1022000000 { ++ device_type = "memory"; ++ reg = <0x10 0x22000000 0x0 0x5e000000>; ++ label = "cached-high"; ++ }; ++ ++ ddr_non_cached_high: memory@1412000000 { ++ device_type = "memory"; ++ reg = <0x14 0x12000000 0x0 0x10000000>; ++ label = "non-cached-high"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ hss: hss-buffer { ++ compatible = "shared-dma-pool"; ++ reg = <0x10 0x3fc00000 0x0 0x400000>; ++ no-map; ++ }; ++ ++ dma_non_cached_low: non-cached-low-buffer { ++ compatible = "shared-dma-pool"; ++ size = <0x0 0x4000000>; ++ no-map; ++ linux,dma-default; ++ alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>; ++ dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>; ++ }; ++ ++ dma_non_cached_high: non-cached-high-buffer { ++ compatible = "shared-dma-pool"; ++ size = <0x0 0x10000000>; ++ no-map; ++ linux,dma-default; ++ alloc-ranges = <0x14 0x12000000 0x0 0x10000000>; ++ dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>; ++ }; ++ ++ fabricbuf0ddrc: buffer@88000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x0 0x88000000 0x0 0x2000000>; ++ no-map; ++ }; ++ ++ fabricbuf1ddrnc: buffer@c8000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x0 0xc8000000 0x0 0x2000000>; ++ no-map; ++ }; ++ ++ fabricbuf2ddrncwcb: buffer@d8000000 { ++ compatible = "shared-dma-pool"; ++ reg = <0x0 0xd8000000 0x0 0x2000000>; ++ no-map; ++ }; ++ }; ++ ++ udmabuf0 { ++ compatible = "ikwzm,u-dma-buf"; ++ device-name = "udmabuf-ddr-c0"; ++ minor-number = <0>; ++ size = <0x0 0x2000000>; ++ memory-region = <&fabricbuf0ddrc>; ++ sync-mode = <3>; ++ }; ++ ++ udmabuf1 { ++ compatible = "ikwzm,u-dma-buf"; ++ device-name = "udmabuf-ddr-nc0"; ++ minor-number = <1>; ++ size = <0x0 0x2000000>; ++ memory-region = <&fabricbuf1ddrnc>; ++ sync-mode = <3>; ++ }; ++ ++ udmabuf2 { ++ compatible = "ikwzm,u-dma-buf"; ++ device-name = "udmabuf-ddr-nc-wcb0"; ++ minor-number = <2>; ++ size = <0x0 0x2000000>; ++ memory-region = <&fabricbuf2ddrncwcb>; ++ sync-mode = <3>; ++ }; ++}; ++ ++&refclk { ++ clock-frequency = <125000000>; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&mmc { ++ status = "okay"; ++ ++ max-frequency = <200000000>; ++ bus-width = <4>; ++ cap-mmc-highspeed; ++ cap-sd-highspeed; ++ no-1-8-v; ++ disable-wp; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ clock-frequency = <100000>; ++}; ++ ++&mac1 { ++ status = "okay"; ++ ++ phy-mode = "sgmii"; ++ phy-handle = <&phy5>; ++ ++ phy4: ethernet-phy@4 { ++ reg = <4>; ++ ti,fifo-depth = <0x01>; ++ }; ++ ++ phy5: ethernet-phy@5 { ++ reg = <5>; ++ ti,fifo-depth = <0x01>; ++ }; ++}; ++ ++&usb { ++ status = "okay"; ++ dr_mode = "host"; ++}; ++ ++&spi0 { ++ compatible = "microchip,mpfs-qspi"; ++ status = "okay"; ++ num-cs = <1>; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ compatible = "n25q00a"; ++ reg = <0x0>; ++ ++ spi-max-frequency = <10000000>; ++ ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <1>; ++ ++ partition@0 { ++ label = "bootloadr"; ++ reg = <0x0 0x2000000>; //32Mb ++ }; ++ ++ partition@2000000 { ++ label = "qspi-linux"; ++ reg = <0x2000000 0x6000000>; //96Mb ++ }; ++ }; ++}; +diff -ruN A/arch/riscv/Kconfig B/arch/riscv/Kconfig +--- A/arch/riscv/Kconfig 2023-10-31 02:41:28.000000000 -0700 ++++ B/arch/riscv/Kconfig 2023-11-29 07:46:53.258808056 -0800 +@@ -23,6 +23,9 @@ + config TARGET_SUNDANCEDSP_POLARBERRY + bool "Support SundanceDSP Polarberry Board (based on Microchip MPFS)" + ++config TARGET_SUNDANCEDSP_SOM1-SOC ++ bool "Support SundanceDSP SOM1-SOC Board (based on Microchip MPFS)" ++ + config TARGET_ALDEC_TYSOM_M_MPFS250T + bool "Support Aldec TySoM M MPFS250T Board" + +@@ -80,6 +83,7 @@ + source "board/microchip/mpfs_icicle/Kconfig" + source "board/microchip/mpfs_videokit/Kconfig" + source "board/sundancedsp/polarberry/Kconfig" ++source "board/sundancedsp/som1-soc/Kconfig" + source "board/sifive/unleashed/Kconfig" + source "board/sifive/unmatched/Kconfig" + source "board/openpiton/riscv64/Kconfig" +diff -ruN A/board/sundancedsp/som1-soc/Kconfig B/board/sundancedsp/som1-soc/Kconfig +--- A/board/sundancedsp/som1-soc/Kconfig 1969-12-31 16:00:00.000000000 -0800 ++++ B/board/sundancedsp/som1-soc/Kconfig 2023-11-29 07:44:31.294668345 -0800 +@@ -0,0 +1,44 @@ ++if TARGET_SUNDANCEDSP_SOM1-SOC ++ ++config SYS_BOARD ++ default "som1-soc" ++ ++config SYS_VENDOR ++ default "sundancedsp" ++ ++config SYS_CPU ++ default "mpfs" ++ ++config SYS_CONFIG_NAME ++ default "sundancedsp_som1-soc" ++ ++config TEXT_BASE ++ default 0x80000000 if !RISCV_SMODE ++ default 0x80200000 if RISCV_SMODE ++ ++config BOARD_SPECIFIC_OPTIONS # dummy ++ def_bool y ++ select MICROCHIP_MPFS ++ select BOARD_EARLY_INIT_F ++ select BOARD_LATE_INIT ++ imply SMP ++ imply CMD_DHCP ++ imply CMD_EXT2 ++ imply CMD_EXT4 ++ imply CMD_FAT ++ imply CMD_FS_GENERIC ++ imply CMD_NET ++ imply CMD_PING ++ imply CMD_MMC ++ imply DOS_PARTITION ++ imply EFI_PARTITION ++ imply IP_DYN ++ imply ISO_PARTITION ++ imply PHY_LIB ++ imply PHY_VITESSE ++ imply MTD_SPI_NAND ++ imply CMD_MTD ++ imply MTD_PARTITIONS ++ imply CMD_MTDPARTS ++ imply MPFS_PRIORITISE_QSPI_BOOT ++endif +diff -ruN A/board/sundancedsp/som1-soc/Makefile B/board/sundancedsp/som1-soc/Makefile +--- A/board/sundancedsp/som1-soc/Makefile 1969-12-31 16:00:00.000000000 -0800 ++++ B/board/sundancedsp/som1-soc/Makefile 2023-11-29 07:44:45.034680571 -0800 +@@ -0,0 +1 @@ ++obj-y += som1-soc.o +diff -ruN A/board/sundancedsp/som1-soc/som1-soc.c B/board/sundancedsp/som1-soc/som1-soc.c +--- A/board/sundancedsp/som1-soc/som1-soc.c 1969-12-31 16:00:00.000000000 -0800 ++++ B/board/sundancedsp/som1-soc/som1-soc.c 2023-10-31 02:41:28.000000000 -0700 +@@ -0,0 +1,380 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) ++#define MPFS_SYS_SERVICE_CR ((unsigned int *)0x37020050) ++#define MPFS_SYS_SERVICE_SR ((unsigned int *)0x37020054) ++#define MPFS_SYS_SERVICE_MAILBOX_U8 ((unsigned char *)0x37020800) ++#define MPFS_SYS_SERVICE_MAILBOX_U32 ((unsigned int *)0x37020800) ++ ++#define SERVICE_CR_REQ_MASK 0x1u ++#define SERVICE_SR_BUSY_MASK 0x2u ++#define SERVICE_SR_STATUS_SHIFT 16 ++#define SERVICE_CR_COMMAND_SHIFT 16 ++ ++#define SYS_SPI_CMD 0x50 ++#define SYS_SPI_MAILBOX_DATA_LEN 17 ++#define SYS_SPI_MAILBOX_SRC_OFFSET 8 ++#define SYS_SPI_MAILBOX_LENGTH_OFFSET 12 ++#define SYS_SPI_MAILBOX_FREQ_OFFSET 16 ++#define SYS_SPI_MAILBOX_FREQ 3 ++#define SPI_FLASH_ADDR 0x400 ++ ++#define PERIPH_RESET_VALUE 0x800001e8u ++ ++/* Descriptor table */ ++#define START_OFFSET 4 ++#define END_OFFSET 8 ++#define SIZE_OFFSET 12 ++#define DESC_NEXT 12 ++#define DESC_RESERVED_SIZE 0 ++#define DESC_SIZE 16 ++ ++#define BYTES_2 2 ++#define BYTES_4 4 ++#define BYTES_8 8 ++#define BYTES_16 16 ++#define BYTES_24 24 ++#define MASK_8BIT 0xff ++ ++#define DESIGN_MAGIC_0 0x4d /* 'M' */ ++#define DESIGN_MAGIC_1 0x43 /* 'C'*/ ++#define DESIGN_MAGIC_2 0x48 /* 'H'*/ ++#define DESIGN_MAGIC_3 0x50 /* 'P'*/ ++ ++static u8 no_of_dtbo; ++static u32 dtbos_size; ++ ++static void read_device_serial_number(u8 *response, u8 response_size) ++{ ++ u8 idx; ++ u8 *response_buf; ++ unsigned int val; ++ ++ response_buf = (u8 *)response; ++ ++ writel(SERVICE_CR_REQ_MASK, MPFS_SYS_SERVICE_CR); ++ /* ++ * REQ bit will remain set till the system controller starts ++ * processing. ++ */ ++ do { ++ val = readl(MPFS_SYS_SERVICE_CR); ++ } while (SERVICE_CR_REQ_MASK == (val & SERVICE_CR_REQ_MASK)); ++ ++ /* ++ * Once system controller starts processing the busy bit will ++ * go high and service is completed when busy bit is gone low ++ */ ++ do { ++ val = readl(MPFS_SYS_SERVICE_SR); ++ } while (SERVICE_SR_BUSY_MASK == (val & SERVICE_SR_BUSY_MASK)); ++ ++ for (idx = 0; idx < response_size; idx++) ++ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX_U8 + idx); ++} ++ ++static u16 execute_sys_service(u8 cmd_opcode, u8 *cmd_data, u16 cmd_data_size) ++{ ++ u32 *word_buf; ++ u32 mailbox_val; ++ u32 idx, value; ++ u16 status; ++ u8 *byte_buf; ++ u8 byte_offset; ++ u8 byte_idx; ++ ++ word_buf = (u32 *)cmd_data; ++ ++ for (idx = 0; idx < cmd_data_size / BYTES_4; idx++) ++ writel(word_buf[idx], MPFS_SYS_SERVICE_MAILBOX_U32 + idx); ++ ++ if (cmd_data_size % BYTES_4 > 0) { ++ byte_offset = (cmd_data_size / BYTES_4) * BYTES_4; ++ byte_buf = (u8 *)(cmd_data + byte_offset); ++ ++ mailbox_val = readl(MPFS_SYS_SERVICE_MAILBOX_U32 + idx); ++ ++ for (byte_idx = 0; byte_idx < cmd_data_size % 4; byte_idx++) { ++ mailbox_val &= ~(MASK_8BIT << (byte_idx * BYTES_8)); ++ value = byte_buf[byte_idx] << (byte_idx * BYTES_8); ++ mailbox_val |= value; ++ } ++ writel(mailbox_val, MPFS_SYS_SERVICE_MAILBOX_U32 + idx); ++ } ++ ++ writel((cmd_opcode << SERVICE_CR_COMMAND_SHIFT) | SERVICE_CR_REQ_MASK, ++ MPFS_SYS_SERVICE_CR); ++ ++ /* ++ * REQ bit will remain set till the system controller starts ++ * processing. ++ */ ++ do { ++ value = readl(MPFS_SYS_SERVICE_CR); ++ } while (SERVICE_CR_REQ_MASK == (value & SERVICE_CR_REQ_MASK)); ++ ++ /* ++ * Once system controller starts processing the busy bit will ++ * go high and service is completed when busy bit is gone low ++ */ ++ do { ++ value = readl(MPFS_SYS_SERVICE_SR); ++ } while (SERVICE_SR_BUSY_MASK == (value & SERVICE_SR_BUSY_MASK)); ++ ++ status = value >> SERVICE_SR_STATUS_SHIFT; ++ ++ return status; ++} ++ ++static u16 sys_service_spi_copy(void *dst_addr, u32 src_addr, u32 length) ++{ ++ u16 status; ++ u8 mailbox_format[SYS_SPI_MAILBOX_DATA_LEN]; ++ ++ *(u64 *)mailbox_format = (u64)dst_addr; ++ *(u32 *)(mailbox_format + SYS_SPI_MAILBOX_SRC_OFFSET) = src_addr; ++ *(u32 *)(mailbox_format + SYS_SPI_MAILBOX_LENGTH_OFFSET) = length; ++ mailbox_format[SYS_SPI_MAILBOX_FREQ_OFFSET] = SYS_SPI_MAILBOX_FREQ; ++ ++ status = execute_sys_service(SYS_SPI_CMD, mailbox_format, ++ SYS_SPI_MAILBOX_DATA_LEN); ++ return status; ++} ++ ++static u16 get_dtbo_desc_header(u8 *desc_data, u32 desc_addr) ++{ ++ u32 length, no_of_descs; ++ u16 status; ++ ++ /* Get first four bytes to calculate length */ ++ status = sys_service_spi_copy(desc_data, desc_addr, BYTES_4); ++ if (!status) { ++ /* Number of descriptors in dtbo descriptor */ ++ no_of_descs = *((u32 *)desc_data); ++ if (no_of_descs) { ++ length = DESC_SIZE + ((no_of_descs - 1) * DESC_SIZE); ++ status = sys_service_spi_copy(desc_data, desc_addr, ++ length); ++ } else { ++ status = -1; ++ } ++ } ++ ++ return status; ++} ++ ++static u8 *get_dtbo(u32 start_addr, u32 size) ++{ ++ u16 status; ++ u8 *dtbo; ++ ++ dtbo = (u8 *)malloc(size); ++ /* Get a dtbo from the spi flash */ ++ status = sys_service_spi_copy(dtbo, start_addr + SPI_FLASH_ADDR, ++ size); ++ if (status) { ++ free(dtbo); ++ dtbo = NULL; ++ } ++ ++ return dtbo; ++} ++ ++static void parse_desc_header(u8 *desc_header) ++{ ++ u32 dtbo_desc_start_addr; ++ u32 dtbo_desc_end_addr; ++ u32 dtbo_desc_size; ++ u32 no_of_descs; ++ u16 idx, rsvd = 0; ++ u8 dtbo_name[16]; ++ u8 dtbo_addr[20]; ++ u8 *desc; ++ u8 *dtbo; ++ ++ no_of_descs = *((u32 *)desc_header); ++ ++ for (idx = 0; idx < no_of_descs; idx++) { ++ desc = &desc_header[START_OFFSET + (DESC_NEXT * idx) + rsvd]; ++ dtbo_desc_start_addr = *((u32 *)desc); ++ ++ desc = &desc_header[END_OFFSET + (DESC_NEXT * idx) + rsvd]; ++ dtbo_desc_end_addr = *((u32 *)desc); ++ ++ desc = &desc_header[SIZE_OFFSET + (DESC_NEXT * idx) + rsvd]; ++ dtbo_desc_size = *((u32 *)desc); ++ ++ if (no_of_descs) ++ rsvd += DESC_RESERVED_SIZE; ++ ++ dtbo = get_dtbo(dtbo_desc_start_addr, dtbo_desc_size); ++ if (dtbo) { ++ sprintf(dtbo_name, "dtbo_image%d", no_of_dtbo); ++ sprintf(dtbo_addr, "0x%llx", (u64)dtbo); ++ env_set(dtbo_name, dtbo_addr); ++ ++no_of_dtbo; ++ dtbos_size += dtbo_desc_size; ++ } ++ } ++} ++ ++static void get_device_tree_overlays(void) ++{ ++ u32 desc_length; ++ u32 dtbo_desc_addr; ++ u32 dtbo_addr[5]; ++ u16 i, status, hart, no_of_harts; ++ u8 design_info_desc[256]; ++ u8 dtbo_desc_data[256]; ++ u8 no_of_dtbos[8]; ++ u8 dtbo_size[8]; ++ u8 *desc; ++ ++ no_of_dtbo = 0; ++ dtbos_size = 0; ++ ++ /* Read first 10 bytes to verify the descriptor is found or not */ ++ status = sys_service_spi_copy(design_info_desc, SPI_FLASH_ADDR, 10); ++ ++ if (!status && design_info_desc[0] == DESIGN_MAGIC_0 && ++ design_info_desc[1] == DESIGN_MAGIC_1 && ++ design_info_desc[2] == DESIGN_MAGIC_2 && ++ design_info_desc[3] == DESIGN_MAGIC_3) { ++ desc_length = *((u32 *)&design_info_desc[4]); ++ /* Read Design descriptor */ ++ status = sys_service_spi_copy(design_info_desc, ++ SPI_FLASH_ADDR, desc_length); ++ if (!status) { ++ no_of_harts = *((u16 *)&design_info_desc[10]); ++ ++ for (hart = 0; hart < no_of_harts; hart++) { ++ /* Start address of DTBO descriptor */ ++ desc = &design_info_desc[(0x4 * hart) + 0xc]; ++ ++ dtbo_desc_addr = *((u32 *)desc); ++ dtbo_addr[hart] = dtbo_desc_addr; ++ ++ if (!dtbo_addr[hart]) ++ continue; ++ ++ for (i = 0; i < hart; i++) { ++ if (dtbo_addr[hart] == dtbo_addr[i]) ++ continue; ++ } ++ ++ if (hart && hart == i) ++ continue; ++ ++ dtbo_desc_addr += SPI_FLASH_ADDR; ++ status = get_dtbo_desc_header(dtbo_desc_data, ++ dtbo_desc_addr); ++ if (status) ++ continue; ++ else ++ parse_desc_header(dtbo_desc_data); ++ } ++ } ++ } ++ sprintf(no_of_dtbos, "%d", no_of_dtbo); ++ env_set("no_of_overlays", no_of_dtbos); ++ sprintf(dtbo_size, "%d", dtbos_size); ++ env_set("dtbo_size", dtbo_size); ++} ++ ++int board_init(void) ++{ ++ /* For now nothing to do here. */ ++ ++ return 0; ++} ++ ++int board_early_init_f(void) ++{ ++ unsigned int val; ++ ++ /* Reset uart, mmc peripheral */ ++ val = readl(MPFS_SYSREG_SOFT_RESET); ++ val = (val & ~(PERIPH_RESET_VALUE)); ++ writel(val, MPFS_SYSREG_SOFT_RESET); ++ ++ return 0; ++} ++ ++int board_late_init(void) ++{ ++ u32 ret; ++ u32 node; ++ u8 idx; ++ u8 device_serial_number[16] = { 0 }; ++ unsigned char mac_addr[6]; ++ char icicle_mac_addr[20]; ++ void *blob = (void *)gd->fdt_blob; ++ ++ node = fdt_path_offset(blob, "ethernet0"); ++ if (node < 0) { ++ printf("No ethernet0 path offset\n"); ++ return -ENODEV; ++ } ++ ++ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6); ++ if (ret) { ++ printf("No local-mac-address property\n"); ++ return -EINVAL; ++ } ++ ++ read_device_serial_number(device_serial_number, 16); ++ ++ /* Update MAC address with device serial number */ ++ mac_addr[0] = 0x00; ++ mac_addr[1] = 0x04; ++ mac_addr[2] = 0xA3; ++ mac_addr[3] = device_serial_number[2]; ++ mac_addr[4] = device_serial_number[1]; ++ mac_addr[5] = device_serial_number[0]; ++ ++ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); ++ if (ret) { ++ printf("Error setting local-mac-address property\n"); ++ return -ENODEV; ++ } ++ ++ icicle_mac_addr[0] = '['; ++ ++ sprintf(&icicle_mac_addr[1], "%pM", mac_addr); ++ ++ icicle_mac_addr[18] = ']'; ++ icicle_mac_addr[19] = '\0'; ++ ++ for (idx = 0; idx < 20; idx++) { ++ if (icicle_mac_addr[idx] == ':') ++ icicle_mac_addr[idx] = ' '; ++ } ++ env_set("icicle_mac_addr0", icicle_mac_addr); ++ ++ mac_addr[5] = device_serial_number[0] + 1; ++ ++ icicle_mac_addr[0] = '['; ++ ++ sprintf(&icicle_mac_addr[1], "%pM", mac_addr); ++ ++ icicle_mac_addr[18] = ']'; ++ icicle_mac_addr[19] = '\0'; ++ ++ for (idx = 0; idx < 20; idx++) { ++ if (icicle_mac_addr[idx] == ':') ++ icicle_mac_addr[idx] = ' '; ++ } ++ env_set("icicle_mac_addr1", icicle_mac_addr); ++ ++ get_device_tree_overlays(); ++ ++ return 0; ++} +diff -ruN A/board/sundancedsp/som1-soc/uboot.env B/board/sundancedsp/som1-soc/uboot.env +--- A/board/sundancedsp/som1-soc/uboot.env 1969-12-31 16:00:00.000000000 -0800 ++++ B/board/sundancedsp/som1-soc/uboot.env 2023-11-29 07:45:27.406720143 -0800 +@@ -0,0 +1,19 @@ ++arch=riscv ++cpu=riscv ++board=som1-soc ++board_name=som1-soc ++vendor=sundancedsp ++baudrate=115200 ++soc=polarfire ++autoload=1 ++bootdelay=5 ++reset=1 ++ipaddr=192.168.1.72 ++netmask=255.255.255.0 ++serverip=192.168.1.177 ++fileaddr=0x90000000 ++bootcmd=run mmcboot ++bootfile=fitimage_som1-soc.itb ++netboot=tftpboot $fileaddr; bootm $fileaddr ++flash_linux=tftp $fileaddr; mmc erase 0x800 0x10000; mmc write $fileaddr 0x800 0x10000 ++mmcboot=mmc read $fileaddr 0x800 0x10000 && bootm $fileaddr +diff -ruN A/configs/sundancedsp_som1-soc_defconfig B/configs/sundancedsp_som1-soc_defconfig +--- A/configs/sundancedsp_som1-soc_defconfig 1969-12-31 16:00:00.000000000 -0800 ++++ B/configs/sundancedsp_som1-soc_defconfig 2023-11-29 07:49:32.950994829 -0800 +@@ -0,0 +1,37 @@ ++CONFIG_RISCV=y ++CONFIG_SYS_MALLOC_LEN=0x800000 ++CONFIG_SYS_MALLOC_F_LEN=0x2000 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 ++CONFIG_ENV_SIZE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="mpfs-som1-soc" ++CONFIG_TARGET_SUNDANCEDSP_SOM1-SOC=y ++CONFIG_ARCH_RV64I=y ++CONFIG_RISCV_SMODE=y ++CONFIG_DISTRO_DEFAULTS=y ++CONFIG_SYS_LOAD_ADDR=0x80200000 ++CONFIG_FIT=y ++CONFIG_QSPI_BOOT=y ++CONFIG_SD_BOOT=y ++CONFIG_SPI_BOOT=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DISPLAY_BOARDINFO=y ++CONFIG_SYS_CBSIZE=256 ++CONFIG_SYS_PBSIZE=282 ++CONFIG_SYS_BOOTM_LEN=0x4000000 ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYSRESET=y ++CONFIG_SYS_PROMPT="SOM1-SOC: U-boot> " ++# CONFIG_CMD_MTDPARTS is not set ++CONFIG_CMD_UBI=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="board/sundancedsp/som1-soc/uboot.env" ++CONFIG_DDR_SPD=y ++CONFIG_DM_MTD=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_USB=y ++CONFIG_OF_LIBFDT_OVERLAY=y +diff -ruN A/include/configs/sundancedsp_som1-soc.h B/include/configs/sundancedsp_som1-soc.h +--- A/include/configs/sundancedsp_som1-soc.h 1969-12-31 16:00:00.000000000 -0800 ++++ B/include/configs/sundancedsp_som1-soc.h 2023-11-29 07:52:22.679218494 -0800 +@@ -0,0 +1,126 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#include ++ ++#define CFG_SYS_SDRAM_BASE 0x80000000 ++ ++/* Environment options */ ++ ++#if defined(CONFIG_CMD_DHCP) ++#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) ++#else ++#define BOOT_TARGET_DEVICES_DHCP(func) ++#endif ++ ++#if defined(CONFIG_CMD_MTD) ++# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) ++#else ++# define BOOT_TARGET_DEVICES_QSPI(func) ++#endif ++ ++#if defined(CONFIG_CMD_MMC) ++#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) ++#else ++#define BOOT_TARGET_DEVICES_MMC(func) ++#endif ++ ++#if defined(CONFIG_MPFS_PRIORITISE_QSPI_BOOT) ++#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ ++ "bootcmd_qspi=echo Trying to boot from QSPI...; "\ ++ "setenv scriptname boot.scr.uimg; " \ ++ "if mtd list; then setenv mtd_present true; " \ ++ "mtd read env ${scriptaddr} 0; " \ ++ "source ${scriptaddr}; setenv mtd_present; " \ ++ "fi\0 " ++ ++#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ ++ "qspi " ++#else ++#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ ++ "" ++ ++#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ ++ "" ++#endif ++ ++#define BOOT_TARGET_DEVICES(func) \ ++ BOOT_TARGET_DEVICES_QSPI(func)\ ++ BOOT_TARGET_DEVICES_MMC(func)\ ++ BOOT_TARGET_DEVICES_DHCP(func) ++ ++#define BOOTENV_DESIGN_OVERLAYS \ ++ "design_overlays=" \ ++ "if test -n ${no_of_overlays}; then " \ ++ "setenv inc 1; " \ ++ "setenv idx 0; " \ ++ "fdt resize ${dtbo_size}; " \ ++ "while test $idx -ne ${no_of_overlays}; do " \ ++ "setenv dtbo_name dtbo_image${idx}; " \ ++ "setenv fdt_cmd \"fdt apply $\"$dtbo_name; " \ ++ "run fdt_cmd; " \ ++ "setexpr idx $inc + $idx; " \ ++ "done; " \ ++ "fi;\0 " \ ++ ++#if defined(CONFIG_FIT_SIGNATURE) ++#define BOOTENV\ ++ "fdt_high=0xffffffffffffffff;\0 initrd_high=0xffffffffffffffff;\0" \ ++ "bootcmd=if mtd list; then echo Trying to boot from QSPI...;" \ ++ "ubi part rootfs; ubifsmount ubi0:rootfs; ubifsload 0x80000000 boot/fitImage;" \ ++ "ubifsumount; ubi detach; " \ ++ "run setbootargs;" \ ++ "cp 0x80000000 ${scriptaddr} ${filesize};" \ ++ "bootm start ${scriptaddr}#conf-microchip_mpfs-icicle-kit.dtb#${dtbo_conf};" \ ++ "bootm loados; bootm prep; " \ ++ "fdt set /soc/ethernet@20112000 mac-address ${icicle_mac_addr0}; " \ ++ "fdt set /soc/ethernet@20110000 mac-address ${icicle_mac_addr1}; " \ ++ "bootm go; " \ ++ "reset; else " \ ++ "setenv devnum 0; setenv mmcbootpart 1;"\ ++ "if mmc rescan; then " \ ++ "load mmc 0:${mmcbootpart} ${scriptaddr} fitImage; " \ ++ "bootm start ${scriptaddr}; " \ ++ "bootm loados ${scriptaddr}; " \ ++ "bootm ramdisk; " \ ++ "bootm prep; " \ ++ "fdt set /soc/ethernet@20112000 mac-address ${icicle_mac_addr0}; " \ ++ "fdt set /soc/ethernet@20110000 mac-address ${icicle_mac_addr1}; " \ ++ "run design_overlays;" \ ++ "bootm go; " \ ++ "reset; " \ ++ "fi; fi\0 " ++ ++#undef CONFIG_BOOTCOMMAND ++#define CONFIG_BOOTCOMMAND\ ++ "run bootcmd;reset;" \ ++ ++#if defined(CONFIG_MTD_SPI_NAND) ++#define BOOTARGS\ ++ "qspibootargs=uio_pdrv_genirq.of_id=generic-uio ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rootwait rw\0 " \ ++ "setbootargs=setenv bootargs ${qspibootargs} mtdparts=spi2.0:2m(payload),128k(env),119m(rootfs)\0 " \ ++ "dtbo_conf=conf-mpfs_icicle_flash5_click.dtbo\0 " ++#else ++#define BOOTARGS\ ++ "qspibootargs=uio_pdrv_genirq.of_id=generic-uio ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rootwait rw\0 " \ ++ "setbootargs=setenv bootargs ${qspibootargs} mtdparts=spi2.0:2m(payload),128k(env),28m(rootfs)\0 " \ ++ "dtbo_conf=conf-mpfs_icicle_pmod_sf3.dtbo \0" ++#endif ++ ++#define CFG_EXTRA_ENV_SETTINGS \ ++ "bootm_size=0x10000000\0" \ ++ "scriptaddr=0x8e000000\0" \ ++ BOOTENV_DESIGN_OVERLAYS \ ++ BOOTARGS \ ++ BOOTENV ++#else ++#include ++ ++#define CFG_EXTRA_ENV_SETTINGS \ ++ "bootm_size=0x10000000\0" \ ++ "scriptaddr=0x8e000000\0" \ ++ BOOTENV_DESIGN_OVERLAYS \ ++ BOOTENV \ ++ ++#endif ++#endif /* __CONFIG_H */ diff --git a/board/microchip/som1-soc/payload-config.yaml b/board/microchip/som1-soc/payload-config.yaml new file mode 100644 index 00000000..3ca873cc --- /dev/null +++ b/board/microchip/som1-soc/payload-config.yaml @@ -0,0 +1,36 @@ +# +# HSS Payload Generator - buildroot configuration file +# + +# First, we can optionally set a name for our image, otherwise one will be created dynamically +set-name: 'Polarberry Fire-SoC-HSS::U-Boot' + +# +# Next, we'll define the entry point addresses for each hart, as follows: +# +hart-entry-points: {u54_1: '0x80200000', u54_2: '0x80200000', u54_3: '0x80200000', u54_4: '0x80200000'} + +# +# Finally, we'll define a payloads (source binary file) that will be placed at certain regions in memory +# The payload section is defined with the keyword payloads, and then a number of individual +# payload descriptors. +# +# Each payload has a name (path to its ELF/bin file), an owner-hart, and optionally 1-3 secondary-harts. +# +# Additionally, it has a privilege mode in which it will start execution. +# * Valid privilege modes are PRV_M, PRV_S and PRV_U. +# +# +# In this case, the only payload is the u-boot s-mode binary. +# +# Case only matters for the ELF path names, not the keywords. +# +payloads: + src.bin: { + exec-addr: '0x80200000', + owner-hart: u54_1, + secondary-hart: u54_2, + secondary-hart: u54_3, + secondary-hart: u54_4, + priv-mode: prv_s + } diff --git a/board/microchip/som1-soc/post-image.sh b/board/microchip/som1-soc/post-image.sh new file mode 100755 index 00000000..2da9c6b6 --- /dev/null +++ b/board/microchip/som1-soc/post-image.sh @@ -0,0 +1,13 @@ +#!/bin/sh + +#Create FAT linux Image (linux kernel + rootfs + DTS) +cp -R output/images ${BR2_EXTERNAL_MCHP_PATH}/board/microchip/som1-soc +/usr/bin/mkimage -A riscv -O linux -T flat_dt -f ${BR2_EXTERNAL_MCHP_PATH}/board/microchip/som1-soc/fitimage_som1-soc.its output/images/fitimage_som1-soc.itb + +#Copy UBOOT adopted image to the TFTP server directory +#sudo cp output/images/payload.bin /srv/tftp + +#Copy Linux FTD image to the TFTP server directory +#sudo cp output/images/fitimage_som1-soc.itb /srv/tftp + +#clean up diff --git a/board/microchip/som1-soc/program_all.sh b/board/microchip/som1-soc/program_all.sh new file mode 100755 index 00000000..4d7cbf16 --- /dev/null +++ b/board/microchip/som1-soc/program_all.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +./Program_HSS_to_eNVM.sh +./Program_UBOOT_to_eMMC.sh + +echo "reset" > $UART_DEVICE + +./Program_LINUX_to_eMMC.sh diff --git a/board/microchip/som1-soc/program_hss.sh b/board/microchip/som1-soc/program_hss.sh new file mode 100755 index 00000000..dfc9d12e --- /dev/null +++ b/board/microchip/som1-soc/program_hss.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +DEV_BOARD=`cat $BUILDROOT_DIRECTORY/.config | grep BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD | sed 's/BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD=//g' | sed 's/"//g'` +DEV_DIE=`cat $BUILDROOT_DIRECTORY/.config | grep BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE | sed 's/BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE=//g' | sed 's/"//g'` +DEV_PACKAGE=`cat $BUILDROOT_DIRECTORY/.config | grep BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE | sed 's/BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE=//g' | sed 's/"//g'` + +echo +echo "BOARD is set to $DEV_BOARD" +echo "DIE is set to $DEV_DIE" +echo "PACKAGE is set to $DEV_PACKAGE" +echo + +make -C $BUILDROOT_DIRECTORY/output/build/hart-software-services-next program BOARD=$DEV_BOARD DIE=$DEV_DIE PACKAGE=$DEV_PACKAGE diff --git a/board/microchip/som1-soc/program_linux.sh b/board/microchip/som1-soc/program_linux.sh new file mode 100755 index 00000000..28e36c88 --- /dev/null +++ b/board/microchip/som1-soc/program_linux.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +stty -F $UART_DEVICE 115200 cs8 -cstopb -parenb raw + +printf "\t\n ***** WAITING FOR UBOOT *****" + +( + while test "${key}" != "SundanceDSP" + do + read -r uart + key=`echo $uart | grep "Model: SundanceDSP Polarberry" | awk '{print $2}'` +# echo $uart + done +) < $UART_DEVICE + +printf "\t\n ***** GOT THE TIMEOUT STRING FROM UBOOT *****" +sleep 1 +echo ".\n" > $UART_DEVICE +printf "\t\n ***** Starting programming linux image to the POLARBERRY board *****" +echo "setenv ipaddr $DEVICE_IP" > $UART_DEVICE +echo "setenv serverip $PC_IP" > $UART_DEVICE +echo "setenv bootfile $IMAGE_NAME" > $UART_DEVICE +echo "run flash_linux" > $UART_DEVICE +sleep 1 + +( + while test "${key}" != "MMC" + do + read -r uart + key=`echo $uart | grep "MMC write" | awk '{print $1}'` +# echo $uart + done +) < $UART_DEVICE + +printf "\t\n ***** Programming LINUX to the eMMC of the POLARBERRY board is DONE!!! *****" diff --git a/board/microchip/som1-soc/program_uboot.sh b/board/microchip/som1-soc/program_uboot.sh new file mode 100755 index 00000000..0283153e --- /dev/null +++ b/board/microchip/som1-soc/program_uboot.sh @@ -0,0 +1,37 @@ +#!/bin/bash + +source ./FLASH_CONFIG.CONF + +stty -F $UART_DEVICE 115200 cs8 -cstopb -parenb raw + +printf "\t\n ***** WAITING FOR HSS *****" + +( + while test "${key}" != "Timeout" + do + read -r uart + key=`echo $uart | grep Timeout | awk '{print $1}'` + done +) < $UART_DEVICE + +printf "\t\n ***** GOT THE TIMEOUT STRING *****" + +echo "" > $UART_DEVICE +printf "\t\n Starting \"ymodem\" command" +echo "ymodem" > $UART_DEVICE +sleep 1 +printf "\t\n Starting init eMMC command" +echo "2" > $UART_DEVICE +sleep 1 +printf "\t\n Starting ymodem receiving command\n" +echo "3" > $UART_DEVICE +sleep 1 + +sz -b --ymodem $BUILDROOT_DIRECTORY/output/images/payload.bin > $UART_DEVICE < $UART_DEVICE + +printf "\t\n Saving the UBOOT to the eMMC memory" +echo "5" > $UART_DEVICE +sleep 2 +echo "6" > $UART_DEVICE +sleep 1 +printf "\t\n ***** Programming U-BOOT to the eMMC of the POLARBERRY board is DONE!!! *****" diff --git a/board/microchip/som1-soc/rootfs_overlay/etc/init.d/S02modules b/board/microchip/som1-soc/rootfs_overlay/etc/init.d/S02modules new file mode 100755 index 00000000..e68d8512 --- /dev/null +++ b/board/microchip/som1-soc/rootfs_overlay/etc/init.d/S02modules @@ -0,0 +1,68 @@ +#!/bin/sh +######################################################################## +# +# Description : Module auto-loading script +# +# Authors : Zack Winkles +# +# Version : 00.00 +# +# Notes : +# +######################################################################## + +. /etc/sysconfig/functions + +# Assure that the kernel has module support. +[ -e /proc/ksyms -o -e /proc/modules ] || exit 0 + +case "${1}" in + start) + + # Exit if there's no modules file or there are no + # valid entries + [ -r /etc/sysconfig/modules ] && + egrep -qv '^($|#)' /etc/sysconfig/modules || + exit 0 + + boot_mesg -n "Loading modules:" ${INFO} + + # Only try to load modules if the user has actually given us + # some modules to load. + while read module args; do + + # Ignore comments and blank lines. + case "$module" in + ""|"#"*) continue ;; + esac + + # Attempt to load the module, making + # sure to pass any arguments provided. + modprobe ${module} ${args} >/dev/null + + # Print the module name if successful, + # otherwise take note. + if [ $? -eq 0 ]; then + boot_mesg -n " ${module}" ${NORMAL} + else + failedmod="${failedmod} ${module}" + fi + done < /etc/sysconfig/modules + + boot_mesg "" ${NORMAL} + # Print a message about successfully loaded + # modules on the correct line. + echo_ok + + # Print a failure message with a list of any + # modules that may have failed to load. + if [ -n "${failedmod}" ]; then + boot_mesg "Failed to load modules:${failedmod}" ${FAILURE} + echo_failure + fi + ;; + *) + echo "Usage: ${0} {start}" + exit 1 + ;; +esac \ No newline at end of file diff --git a/board/microchip/som1-soc/rootfs_overlay/etc/network/interfaces b/board/microchip/som1-soc/rootfs_overlay/etc/network/interfaces new file mode 100644 index 00000000..0d2d25a9 --- /dev/null +++ b/board/microchip/som1-soc/rootfs_overlay/etc/network/interfaces @@ -0,0 +1,8 @@ +auto lo +iface lo inet loopback + +auto eth0 +iface eth0 inet static + address 192.168.1.72 + netmask 255.255.255.0 + diff --git a/board/microchip/som1-soc/rootfs_overlay/etc/sysconfig/functions b/board/microchip/som1-soc/rootfs_overlay/etc/sysconfig/functions new file mode 100644 index 00000000..099eb110 --- /dev/null +++ b/board/microchip/som1-soc/rootfs_overlay/etc/sysconfig/functions @@ -0,0 +1,145 @@ +#!/bin/sh +####################################################################### +# +# Description : Run Level Control Functions +# +# Authors : Gerard Beekmans - gerard@linuxfromscratch.org +# +# Version : 00.00 +# +# Notes : With code based on Matthias Benkmann's simpleinit-msb +# http://winterdrache.de/linux/newboot/index.html +# +######################################################################## + +## Environmental setup +# Setup default values for environment +umask 022 +export PATH="/bin:/usr/bin:/sbin:/usr/sbin" + +# Signal sent to running processes to refresh their configuration +RELOADSIG="HUP" + +# Number of seconds between STOPSIG and FALLBACK when stopping processes +KILLDELAY="3" + +## Screen Dimensions +# Find current screen size +if [ -z "${COLUMNS}" ]; then + COLUMNS=$(stty size) + COLUMNS=${COLUMNS##* } +fi + +# When using remote connections, such as a serial port, stty size returns 0 +if [ "${COLUMNS}" = "0" ]; then + COLUMNS=80 +fi + +## Measurements for positioning result messages +COL=$((${COLUMNS} - 8)) +WCOL=$((${COL} - 2)) + +## Provide an echo that supports -e and -n +# If formatting is needed, $ECHO should be used +case "`echo -e -n test`" in + -[en]*) + ECHO=/bin/echo + ;; + *) + ECHO=echo + ;; +esac + +## Set Cursor Position Commands, used via $ECHO +SET_COL="\\033[${COL}G" # at the $COL char +SET_WCOL="\\033[${WCOL}G" # at the $WCOL char +CURS_UP="\\033[1A\\033[0G" # Up one line, at the 0'th char + +## Set color commands, used via $ECHO +# Please consult `man console_codes for more information +# under the "ECMA-48 Set Graphics Rendition" section +# +# Warning: when switching from a 8bit to a 9bit font, +# the linux console will reinterpret the bold (1;) to +# the top 256 glyphs of the 9bit font. This does +# not affect framebuffer consoles +NORMAL="\\033[0;39m" # Standard console grey +SUCCESS="\\033[1;32m" # Success is green +WARNING="\\033[1;33m" # Warnings are yellow +FAILURE="\\033[1;31m" # Failures are red +INFO="\\033[1;36m" # Information is light cyan +BRACKET="\\033[1;34m" # Brackets are blue + +STRING_LENGTH="0" # the length of the current message + +#******************************************************************************* +# Function - boot_mesg() +# +# Purpose: Sending information from bootup scripts to the console +# +# Inputs: $1 is the message +# $2 is the colorcode for the console +# +# Outputs: Standard Output +# +# Dependencies: - sed for parsing strings. +# - grep for counting string length. +# +# Todo: +#******************************************************************************* +boot_mesg() +{ + local ECHOPARM="" + + while true + do + case "${1}" in + -n) + ECHOPARM=" -n " + shift 1 + ;; + -*) + echo "Unknown Option: ${1}" + return 1 + ;; + *) + break + ;; + esac + done + + ## Figure out the length of what is to be printed to be used + ## for warning messages. + STRING_LENGTH=$((${#1} + 1)) + + # Print the message to the screen + ${ECHO} ${ECHOPARM} -e "${2}${1}" + +} + +boot_mesg_flush() +{ + # Reset STRING_LENGTH for next message + STRING_LENGTH="0" +} + +echo_ok() +{ + ${ECHO} -n -e "${CURS_UP}${SET_COL}${BRACKET}[${SUCCESS} OK ${BRACKET}]" + ${ECHO} -e "${NORMAL}" + boot_mesg_flush +} + +echo_failure() +{ + ${ECHO} -n -e "${CURS_UP}${SET_COL}${BRACKET}[${FAILURE} FAIL ${BRACKET}]" + ${ECHO} -e "${NORMAL}" + boot_mesg_flush +} + +echo_warning() +{ + ${ECHO} -n -e "${CURS_UP}${SET_COL}${BRACKET}[${WARNING} WARN ${BRACKET}]" + ${ECHO} -e "${NORMAL}" + boot_mesg_flush +} diff --git a/board/microchip/som1-soc/rootfs_overlay/etc/sysconfig/modules b/board/microchip/som1-soc/rootfs_overlay/etc/sysconfig/modules new file mode 100644 index 00000000..e69de29b diff --git a/board/microchip/som1-soc/rootfs_overlay/etc/sysctl.conf b/board/microchip/som1-soc/rootfs_overlay/etc/sysctl.conf new file mode 100644 index 00000000..25ae4d5a --- /dev/null +++ b/board/microchip/som1-soc/rootfs_overlay/etc/sysctl.conf @@ -0,0 +1 @@ +kernel.panic = 1 diff --git a/board/microchip/som1-soc/uboot/uboot_env.txt b/board/microchip/som1-soc/uboot/uboot_env.txt new file mode 100644 index 00000000..c980b3a6 --- /dev/null +++ b/board/microchip/som1-soc/uboot/uboot_env.txt @@ -0,0 +1,19 @@ +arch=riscv +cpu=riscv +board=som1-soc +board_name=som1-soc +vendor=sundancedsp +baudrate=115200 +soc=polarfire +autoload=1 +bootdelay=5 +reset=1 +ipaddr=192.168.1.72 +memaddr=0x90000000 +netmask=255.255.255.0 +serverip=192.168.1.177 +bootcmd=run mmcboot +bootfile=fitimage_som1-soc.itb +netboot=tftpboot $memaddr; bootm $memaddr +flash_linux=tftp $memaddr; mmc erase 0x800 0x10000; mmc write $memaddr 0x800 0x10000 +mmcboot=mmc read $memaddr 0x800 0x10000 && bootm $memaddr diff --git a/board/microchip/som1-soc/uboot/uboot_som1-soc.dts b/board/microchip/som1-soc/uboot/uboot_som1-soc.dts new file mode 100644 index 00000000..37d9453f --- /dev/null +++ b/board/microchip/som1-soc/uboot/uboot_som1-soc.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Microchip Technology Inc. + * Padmarao Begari + */ + +/dts-v1/; + +#include "microchip-mpfs.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model = "Microchip SOM1-SOC"; + compatible = "microchip,mpfs"; + + aliases { + serial0 = &uart0; + ethernet0 = &mac1; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0"; + }; + + cpus { + timebase-frequency = ; + }; + + kernel: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x4000000>; + label = "kernel"; + }; + + ddr_cached_low: memory@8a000000 { + device_type = "memory"; + reg = <0x0 0x8a000000 0x0 0x8000000>; + label = "cached-low"; + }; + + ddr_non_cached_low: memory@c4000000 { + device_type = "memory"; + reg = <0x0 0xc4000000 0x0 0x6000000>; + label = "non-cached-low"; + }; + + ddr_cached_high: memory@1022000000 { + device_type = "memory"; + reg = <0x10 0x22000000 0x0 0x5e000000>; + label = "cached-high"; + }; + + ddr_non_cached_high: memory@1412000000 { + device_type = "memory"; + reg = <0x14 0x12000000 0x0 0x10000000>; + label = "non-cached-high"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer { + compatible = "shared-dma-pool"; + reg = <0x10 0x3fc00000 0x0 0x400000>; + no-map; + }; + + dma_non_cached_low: non-cached-low-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>; + dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>; + }; + + dma_non_cached_high: non-cached-high-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x14 0x12000000 0x0 0x10000000>; + dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>; + }; + + fabricbuf0ddrc: buffer@88000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x88000000 0x0 0x2000000>; + no-map; + }; + + fabricbuf1ddrnc: buffer@c8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xc8000000 0x0 0x2000000>; + no-map; + }; + + fabricbuf2ddrncwcb: buffer@d8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xd8000000 0x0 0x2000000>; + no-map; + }; + }; + + udmabuf0 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-c0"; + minor-number = <0>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf0ddrc>; + sync-mode = <3>; + }; + + udmabuf1 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-nc0"; + minor-number = <1>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf1ddrnc>; + sync-mode = <3>; + }; + + udmabuf2 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-nc-wcb0"; + minor-number = <2>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf2ddrncwcb>; + sync-mode = <3>; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&mmc { + uboot,dm-pre-reloc; + + status = "okay"; + + max-frequency = <200000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; +}; + +&i2c0 { + uboot,dm-pre-reloc; + + status = "okay"; + clock-frequency = <100000>; + + //0x77 - SI5341A-D-GM +}; + +&i2c1 { + uboot,dm-pre-reloc; + + status = "okay"; + clock-frequency = <100000>; +}; + +&mac1 { + status = "okay"; + + local-mac-address = [56 34 00 FC 00 03]; + phy-mode = "sgmii"; + phy-handle = <&phy5>; + + phy5: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; +}; + +&usb { + uboot,dm-pre-reloc; + + status = "okay"; + xlnx,tz-nonsecure = <0x1>; + xlnx,usb-polarity = <0x0>; + xlnx,usb-reset-mode = <0x2>; + dr_mode = "host"; +}; + +&spi0 { + uboot,dm-pre-reloc; + compatible = "microchip,mpfs-qspi"; + status = "okay"; + num-cs = <1>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "n25q00a"; + reg = <0x0>; + + spi-max-frequency = <10000000>; + + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x2000000>; //32Mb + }; + + partition@2000000 { + label = "qspi-linux"; + reg = <0x2000000 0x6000000>; //96Mb + }; + }; +}; diff --git a/board/microchip/som1-soc/uboot/uboot_som1-soc_defconfig b/board/microchip/som1-soc/uboot/uboot_som1-soc_defconfig new file mode 100644 index 00000000..1ee4ffdd --- /dev/null +++ b/board/microchip/som1-soc/uboot/uboot_som1-soc_defconfig @@ -0,0 +1,37 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="mpfs-som1-soc" +CONFIG_SYS_PROMPT="SOM1-SOC: U-boot> " +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0x90000000 +CONFIG_TARGET_SUNDANCEDSP_SOM1-SOC=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_QSPI_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_SPI_BOOT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_SYS_BOOTM_LEN=0x4000000 +# CONFIG_CMD_MTDPARTS is not set +CONFIG_CMD_UBI=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_DEFAULT_ENV_FILE="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/uboot/uboot_env.txt" +CONFIG_DDR_SPD=y +CONFIG_DM_MTD=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_USB=y +#CONFIG_CMD_GPIO=y +#CONFIG_CMD_GPIO_READ=y \ No newline at end of file diff --git a/configs/sundancedsp_polarberry_defconfig b/configs/sundancedsp_polarberry_defconfig new file mode 100644 index 00000000..ea53fb82 --- /dev/null +++ b/configs/sundancedsp_polarberry_defconfig @@ -0,0 +1,59 @@ +BR2_riscv=y +BR2_riscv_custom=y +BR2_RISCV_ISA_CUSTOM_RVM=y +BR2_RISCV_ISA_CUSTOM_RVA=y +BR2_RISCV_ISA_CUSTOM_RVF=y +BR2_RISCV_ISA_CUSTOM_RVD=y +BR2_RISCV_ISA_CUSTOM_RVC=y +BR2_KERNEL_HEADERS_5_15=y +BR2_BINUTILS_VERSION_2_39_X=y +BR2_GCC_VERSION_11_X=y +BR2_TOOLCHAIN_BUILDROOT_CXX=y +BR2_PACKAGE_HOST_GDB=y +BR2_SHARED_STATIC_LIBS=y +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/patches/" +BR2_TARGET_GENERIC_HOSTNAME="POLARBERRY" +BR2_TARGET_GENERIC_ISSUE="Welcome to POLARBERRY Linux" +BR2_TARGET_GENERIC_ROOT_PASSWD="root" +BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/rootfs_overlay" +BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/post-image.sh" +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_GIT=y +BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/linux4microchip/linux.git" +BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="linux-5.15-mchp" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/linux/linux_polarberry_defconfig" +BR2_LINUX_KERNEL_DTS_SUPPORT=y +BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/linux/linux_polarberry.dts" +BR2_PACKAGE_LINUX_TOOLS_GPIO=y +BR2_PACKAGE_SPIDEV_TEST=y +BR2_PACKAGE_SPI_TOOLS=y +BR2_PACKAGE_LIBSYSFS=y +# BR2_PACKAGE_JPEG_TURBO=y +# BR2_PACKAGE_LIBSVG_CAIRO=y +BR2_PACKAGE_DROPBEAR=y +# BR2_PACKAGE_DROPBEAR_CLIENT is not set +BR2_PACKAGE_UTIL_LINUX_MOUNT=y +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_CPIO_BZIP2=y +# BR2_TARGET_ROOTFS_TAR is not set +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_TARBALL=y +BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,polarfire-soc,u-boot)mpfs-uboot-2023.07-next.tar.gz" +BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y +BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/uboot/uboot_polarberry_defconfig" +BR2_TARGET_UBOOT_NEEDS_DTC=y +BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/uboot/uboot_polarberry.dts" +BR2_PACKAGE_HOST_DOSFSTOOLS=y +BR2_PACKAGE_HOST_E2FSPROGS=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_MTOOLS=y +BR2_PACKAGE_HART_SOFTWARE_SERVICES=y +BR2_PACKAGE_HART_SOFTWARE_SERVICES_CONFIG="boards/polarberry/def_config" +BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD="polarberry" +BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE="MPFS250T" +BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE="FCVG484" +BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR=y +BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR_CFG="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/payload-config.yaml" +BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR_SRC="output/images/u-boot.bin" diff --git a/configs/sundancedsp_som1-soc_defconfig b/configs/sundancedsp_som1-soc_defconfig new file mode 100644 index 00000000..cf76fd97 --- /dev/null +++ b/configs/sundancedsp_som1-soc_defconfig @@ -0,0 +1,60 @@ +BR2_riscv=y +BR2_riscv_custom=y +BR2_RISCV_ISA_CUSTOM_RVM=y +BR2_RISCV_ISA_CUSTOM_RVA=y +BR2_RISCV_ISA_CUSTOM_RVF=y +BR2_RISCV_ISA_CUSTOM_RVD=y +BR2_RISCV_ISA_CUSTOM_RVC=y +BR2_KERNEL_HEADERS_5_15=y +BR2_BINUTILS_VERSION_2_39_X=y +BR2_GCC_VERSION_11_X=y +BR2_TOOLCHAIN_BUILDROOT_CXX=y +BR2_PACKAGE_HOST_GDB=y +BR2_SHARED_STATIC_LIBS=y +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/patches/" +BR2_TARGET_GENERIC_HOSTNAME="SOM1-SOC" +BR2_TARGET_GENERIC_ISSUE="Welcome to SOM1-SOC Linux" +BR2_TARGET_GENERIC_ROOT_PASSWD="root" +BR2_ROOTFS_OVERLAY="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/rootfs_overlay" +BR2_ROOTFS_POST_IMAGE_SCRIPT="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/post-image.sh" +BR2_LINUX_KERNEL=y +BR2_LINUX_KERNEL_CUSTOM_GIT=y +BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/linux4microchip/linux.git" +BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="linux-5.15-mchp" +BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y +BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/linux/linux_som1-soc_defconfig" +BR2_LINUX_KERNEL_DTS_SUPPORT=y +BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/linux/linux_som1-soc.dts" +BR2_PACKAGE_LINUX_TOOLS_GPIO=y +BR2_PACKAGE_SPIDEV_TEST=y +BR2_PACKAGE_SPI_TOOLS=y +BR2_PACKAGE_LIBSYSFS=y +BR2_PACKAGE_JPEG_TURBO=y +BR2_PACKAGE_LIBSVG_CAIRO=y +BR2_PACKAGE_DROPBEAR=y +# BR2_PACKAGE_DROPBEAR_CLIENT is not set +BR2_PACKAGE_UTIL_LINUX_MOUNT=y +BR2_TARGET_ROOTFS_CPIO=y +BR2_TARGET_ROOTFS_CPIO_BZIP2=y +# BR2_TARGET_ROOTFS_TAR is not set +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_GIT=y +BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/polarfire-soc/u-boot.git" +BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="mpfs-uboot-2023.07-next" +BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y +BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/uboot/uboot_som1-soc_defconfig" +BR2_TARGET_UBOOT_NEEDS_DTC=y +BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/uboot/uboot_som1-soc.dts" +BR2_PACKAGE_HOST_DOSFSTOOLS=y +BR2_PACKAGE_HOST_E2FSPROGS=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_MTOOLS=y +BR2_PACKAGE_HART_SOFTWARE_SERVICES=y +BR2_PACKAGE_HART_SOFTWARE_SERVICES_CONFIG="boards/som1-soc/def_config" +BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD="som1-soc" +BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE="MPFS460T" +BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE="FCG1152" +BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR=y +BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR_CFG="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/som1-soc/payload-config.yaml" +BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR_SRC="output/images/u-boot.bin" diff --git a/package/hart-software-services/001-HSS_SOM1-SOC.patch b/package/hart-software-services/001-HSS_SOM1-SOC.patch new file mode 100644 index 00000000..9e0f9da6 --- /dev/null +++ b/package/hart-software-services/001-HSS_SOM1-SOC.patch @@ -0,0 +1,7456 @@ +diff -ruN A/boards/som1-soc/def_config B/boards/som1-soc/def_config +--- A/boards/som1-soc/def_config 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/def_config 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,229 @@ ++ ++# ++# Board/Design Configuration Options ++# ++ ++# ++# Custom Board Design Configuration Options ++# ++CONFIG_SOC_FPGA_DESIGN_XML="boards/som1-soc/soc_fpga_design/xml/som1-soc.xml" ++# end of Custom Board Design Configuration Options ++# end of Board/Design Configuration Options ++ ++# ++# Services ++# ++CONFIG_SERVICE_BEU=y ++CONFIG_SERVICE_BOOT=y ++ ++# ++# Boot Service ++# ++# CONFIG_SERVICE_BOOT_USE_PAYLOAD is not set ++# CONFIG_SERVICE_BOOT_CUSTOM_FLOW is not set ++CONFIG_SERVICE_BOOT_DDR_TARGET_ADDR=0x103FC00000 ++# CONFIG_SERVICE_BOOT_MMC_USE_GPT is not set ++# end of Boot Service ++ ++CONFIG_SERVICE_DDR=y ++CONFIG_SERVICE_GOTO=y ++# CONFIG_SERVICE_HEALTHMON is not set ++CONFIG_SERVICE_IPI_POLL=y ++CONFIG_SERVICE_MMC=y ++ ++# ++# MMC ++# ++ ++# ++# MMC Mode ++# ++CONFIG_SERVICE_MMC_MODE_EMMC=y ++# CONFIG_SERVICE_MMC_MODE_SDCARD is not set ++# end of MMC Mode ++ ++# ++# MMC Voltage ++# ++# CONFIG_SERVICE_MMC_BUS_VOLTAGE_1V8 is not set ++CONFIG_SERVICE_MMC_BUS_VOLTAGE_3V3=y ++# end of MMC Voltage ++ ++# ++# SDIO Control ++# ++# CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT is not set ++# end of SDIO Control ++ ++CONFIG_SERVICE_MMC_SPIN_TIMEOUT=y ++# CONFIG_SERVICE_MMC_SPIN_TIMEOUT_ASSERT is not set ++CONFIG_SERVICE_MMC_SPIN_TIMEOUT_MAX_SPINS=1000000 ++# end of MMC ++ ++CONFIG_SERVICE_OPENSBI=y ++ ++# ++# SBI Extension Support ++# ++CONFIG_SBI_ECALL_TIME=y ++CONFIG_SBI_ECALL_RFENCE=y ++CONFIG_SBI_ECALL_IPI=y ++CONFIG_SBI_ECALL_HSM=y ++CONFIG_SBI_ECALL_SRST=y ++CONFIG_SBI_ECALL_PMU=y ++CONFIG_SBI_ECALL_LEGACY=y ++CONFIG_SBI_ECALL_VENDOR=y ++# end of SBI Extension Support ++ ++CONFIG_FDT_IPI=y ++CONFIG_FDT_IPI_MSWI=y ++CONFIG_FDT_IPI_PLICSW=y ++CONFIG_FDT_IRQCHIP=y ++CONFIG_FDT_IRQCHIP_PLIC=y ++CONFIG_FDT_RESET=y ++CONFIG_FDT_SERIAL=y ++CONFIG_FDT_SERIAL_UART8250=y ++CONFIG_FDT_TIMER=y ++CONFIG_FDT_TIMER_MTIMER=y ++# CONFIG_SERVICE_POWERMODE is not set ++# CONFIG_SERVICE_QSPI is not set ++CONFIG_SERVICE_REBOOT=y ++# CONFIG_SERVICE_SCRUB is not set ++CONFIG_SERVICE_SGDMA=y ++# CONFIG_SERVICE_SPI is not set ++CONFIG_SERVICE_TINYCLI=y ++ ++# ++# Tiny Command Line Interface ++# ++CONFIG_SERVICE_TINYCLI_TIMEOUT=2 ++# CONFIG_SERVICE_TINYCLI_REGISTER is not set ++# CONFIG_SERVICE_TINYCLI_ENABLE_PREBOOT_TIMEOUT is not set ++# end of Tiny Command Line Interface ++ ++# CONFIG_SERVICE_UART is not set ++CONFIG_SERVICE_USBDMSC=y ++ ++# ++# USB Device Mass Storage Class ++# ++CONFIG_SERVICE_USBDMSC_REGISTER=y ++# CONFIG_SERVICE_USBDMSC_ENABLE_MAX_SESSION_TIMEOUT is not set ++# end of USB Device Mass Storage Class ++ ++CONFIG_SERVICE_WDOG=y ++ ++# ++# Watchdog Service ++# ++# CONFIG_SERVICE_WDOG_DEBUG is not set ++CONFIG_SERVICE_WDOG_DEBUG_TIMEOUT_SEC=240 ++CONFIG_SERVICE_WDOG_ENABLE_E51=y ++# end of Watchdog Service ++ ++CONFIG_SERVICE_YMODEM=y ++# end of Services ++ ++# ++# General Configuration Options ++# ++ ++# ++# Miscellaneous ++# ++# CONFIG_USE_PCIE is not set ++# CONFIG_UART_SURRENDER is not set ++CONFIG_OPENSBI=y ++# CONFIG_USE_IHC is not set ++ ++# ++# Serial Port ++# ++CONFIG_UART_POST_BOOT=0 ++# end of Serial Port ++ ++# ++# Tamper ++# ++# CONFIG_USE_TAMPER is not set ++# end of Tamper ++ ++CONFIG_ALLOW_COLDREBOOT=y ++ ++# ++# Cold Reboot ++# ++CONFIG_ALLOW_COLDREBOOT_ALWAYS=y ++# CONFIG_COLDREBOOT_TRY_AUTO_UPDATE is not set ++# CONFIG_ALLOW_COLDREBOOT_ON_OPENSBI_FAULT is not set ++# end of Cold Reboot ++# end of Miscellaneous ++ ++# ++# OpenSBI ++# ++# CONFIG_PROVIDE_DTB is not set ++# end of OpenSBI ++ ++# ++# Memory Options ++# ++# CONFIG_SKIP_DDR is not set ++ #CONFIG_MEMTEST is not set ++# CONFIG_USE_PDMA is not set ++# CONFIG_INITIALIZE_MEMORIES is not set ++# end of Memory Options ++# end of General Configuration Options ++ ++# ++# Build Options ++# ++# CONFIG_COLOR_OUTPUT is not set ++# CONFIG_USE_LOGO is not set ++ ++# ++# Logo ++# ++# end of Logo ++ ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++# CONFIG_CC_DUMP_STACKSIZE is not set ++# CONFIG_LD_RELAX is not set ++# CONFIG_CC_USE_MAKEDEP is not set ++# CONFIG_CC_USE_GNU_BUILD_ID is not set ++CONFIG_CC_HAS_INTTYPES=y ++CONFIG_DISPLAY_TOOL_VERSIONS=y ++# CONFIG_LOG_FUNCTION_NAMES is not set ++# end of Build Options ++ ++# ++# Compression ++# ++CONFIG_COMPRESSION=y ++CONFIG_COMPRESSION_MINIZ=y ++# end of Compression ++ ++# ++# Crypto ++# ++# CONFIG_CRYPTO_SIGNING is not set ++# end of Crypto ++ ++# ++# Debug Options ++# ++# CONFIG_DEBUG_LOG_STATE_TRANSITIONS is not set ++# CONFIG_DEBUG_LOOP_TIMES is not set ++# CONFIG_DEBUG_IPI_STATS is not set ++# CONFIG_DEBUG_CHUNK_DOWNLOADS is not set ++# CONFIG_DEBUG_MSCGEN_IPI is not set ++# CONFIG_DEBUG_PERF_CTRS is not set ++# CONFIG_DEBUG_RESET_REASON is not set ++# end of Debug Options ++ ++# ++# SSMB Options ++# ++CONFIG_IPI_MAX_NUM_QUEUE_MESSAGES=8 ++# CONFIG_IPI_FIXED_BASE is not set ++# end of SSMB Options +diff -ruN A/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_add_mapping.h B/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_add_mapping.h +--- A/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_add_mapping.h 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_add_mapping.h 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,174 @@ ++/******************************************************************************* ++ * Copyright 2021 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * MPFS HAL Embedded Software ++ * ++ */ ++ ++ /*========================================================================*//** ++ @mainpage Configuration for the MiV-IHC driver ++ ++ @section intro_sec Introduction ++ Used to configure the driver with base addresses from your Libero Projext. ++ These addresses will not change unless you change the Libero design ++ IHC subsytem design. ++ This file is used for reference only. ++ When usiing in a project copy to ++ src/boards/your-board/platform-config/drivers_config/fpga-ip/miv_ihc ++ and rename dropping the _reference. ++ @section ++ ++*//*==========================================================================*/ ++ ++ ++#ifndef MIV_IHC_ADD_MAPPING_H_ ++#define MIV_IHC_ADD_MAPPING_H_ ++ ++#ifndef COMMON_AHB_BASE_ADD ++#define COMMON_AHB_BASE_ADD 0x50000000UL ++#endif ++#ifndef IHC_HO_BASE_OFFSET ++#define IHC_HO_BASE_OFFSET 0x00000000UL ++#endif ++#ifndef IHC_H1_BASE_OFFSET ++#define IHC_H1_BASE_OFFSET 0x00000500UL ++#endif ++#ifndef IHC_H2_BASE_OFFSET ++#define IHC_H2_BASE_OFFSET 0x00000A00UL ++#endif ++#ifndef IHC_H3_BASE_OFFSET ++#define IHC_H3_BASE_OFFSET 0x00000F00UL ++#endif ++#ifndef IHC_H4_BASE_OFFSET ++#define IHC_H4_BASE_OFFSET 0x00001400UL ++#endif ++ ++/************** My Hart 0 ************/ ++ ++#ifndef IHC_LOCAL_H0_REMOTE_H1 ++#define IHC_LOCAL_H0_REMOTE_H1 0x50000000 ++#endif ++ ++#ifndef IHC_LOCAL_H0_REMOTE_H2 ++#define IHC_LOCAL_H0_REMOTE_H2 0x50000100 ++#endif ++ ++#ifndef IHC_LOCAL_H0_REMOTE_H3 ++#define IHC_LOCAL_H0_REMOTE_H3 0x50000200 ++#endif ++ ++#ifndef IHC_LOCAL_H0_REMOTE_H4 ++#define IHC_LOCAL_H0_REMOTE_H4 0x50000300 ++#endif ++ ++#ifndef IHCIA_LOCAL_H0 ++#define IHCIA_LOCAL_H0 0x50000400 ++#endif ++ ++/************** My Hart 1 ************/ ++ ++#ifndef IHC_LOCAL_H1_REMOTE_H0 ++#define IHC_LOCAL_H1_REMOTE_H0 0x50000500 ++#endif ++ ++#ifndef IHC_LOCAL_H1_REMOTE_H2 ++#define IHC_LOCAL_H1_REMOTE_H2 0x50000600 ++#endif ++ ++#ifndef IHC_LOCAL_H1_REMOTE_H3 ++#define IHC_LOCAL_H1_REMOTE_H3 0x50000700 ++#endif ++ ++#ifndef IHC_LOCAL_H1_REMOTE_H4 ++#define IHC_LOCAL_H1_REMOTE_H4 0x50000800 ++#endif ++ ++#ifndef IHCIA_LOCAL_H1 ++#define IHCIA_LOCAL_H1 0x50000900 ++#endif ++ ++/************** My Hart 2 ************/ ++ ++#ifndef IHC_LOCAL_H2_REMOTE_H0 ++#define IHC_LOCAL_H2_REMOTE_H0 0x50000A00 ++#endif ++ ++#ifndef IHC_LOCAL_H2_REMOTE_H1 ++#define IHC_LOCAL_H2_REMOTE_H1 0x50000B00 ++#endif ++ ++#ifndef IHC_LOCAL_H2_REMOTE_H3 ++#define IHC_LOCAL_H2_REMOTE_H3 0x50000C00 ++#endif ++ ++#ifndef IHC_LOCAL_H2_REMOTE_H4 ++#define IHC_LOCAL_H2_REMOTE_H4 0x50000D00 ++#endif ++ ++#ifndef IHCIA_LOCAL_H2 ++#define IHCIA_LOCAL_H2 0x50000E00 ++#endif ++ ++/************** My Hart 3 ************/ ++ ++#ifndef IHC_LOCAL_H3_REMOTE_H0 ++#define IHC_LOCAL_H3_REMOTE_H0 0x50000F00 ++#endif ++ ++#ifndef IHC_LOCAL_H3_REMOTE_H1 ++#define IHC_LOCAL_H3_REMOTE_H1 0x50001000 ++#endif ++ ++#ifndef IHC_LOCAL_H3_REMOTE_H2 ++#define IHC_LOCAL_H3_REMOTE_H2 0x50001100 ++#endif ++ ++#ifndef IHC_LOCAL_H3_REMOTE_H4 ++#define IHC_LOCAL_H3_REMOTE_H4 0x50001200 ++#endif ++ ++#ifndef IHCIA_LOCAL_H3 ++#define IHCIA_LOCAL_H3 0x50001300 ++#endif ++ ++/************** My Hart 4 ************/ ++ ++#ifndef IHC_LOCAL_H4_REMOTE_H0 ++#define IHC_LOCAL_H4_REMOTE_H0 0x50001400 ++#endif ++ ++#ifndef IHC_LOCAL_H4_REMOTE_H1 ++#define IHC_LOCAL_H4_REMOTE_H1 0x50001500 ++#endif ++ ++#ifndef IHC_LOCAL_H4_REMOTE_H2 ++#define IHC_LOCAL_H4_REMOTE_H2 0x50001600 ++#endif ++ ++#ifndef IHC_LOCAL_H4_REMOTE_H3 ++#define IHC_LOCAL_H4_REMOTE_H3 0x50001700 ++#endif ++ ++#ifndef IHCIA_LOCAL_H4 ++#define IHCIA_LOCAL_H4 0x50001800 ++#endif ++ ++/*------------------------------------------------------------------------------ ++ * choose the interrupt mapping used in our system ++ * Please see miv_ihc_regs.h for the defaults ++ */ ++#define IHCIA_hart0_IRQHandler fabric_f2h_63_plic_IRQHandler ++#define IHCIA_hart1_IRQHandler fabric_f2h_62_plic_IRQHandler ++#define IHCIA_hart2_IRQHandler fabric_f2h_61_plic_IRQHandler ++#define IHCIA_hart3_IRQHandler fabric_f2h_60_plic_IRQHandler ++#define IHCIA_hart4_IRQHandler fabric_f2h_59_plic_IRQHandler ++ ++#define IHCIA_hart0_INT FABRIC_F2H_63_PLIC ++#define IHCIA_hart1_INT FABRIC_F2H_62_PLIC ++#define IHCIA_hart2_INT FABRIC_F2H_61_PLIC ++#define IHCIA_hart3_INT FABRIC_F2H_60_PLIC ++#define IHCIA_hart4_INT FABRIC_F2H_59_PLIC ++ ++#endif /* MIV_IHC_ADD_MAPPING_H_ */ +diff -ruN A/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_config.h B/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_config.h +--- A/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_config.h 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/drivers_config/fpga_ip/miv_ihc/miv_ihc_config.h 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,59 @@ ++/******************************************************************************* ++ * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * MPFS HAL Embedded Software ++ * ++ */ ++ ++ /*========================================================================*//** ++ @mainpage Configuration for the MiV-IhC driver ++ ++ @section intro_sec Introduction ++ Used to configure the driver ++ ++ @section ++ ++*//*==========================================================================*/ ++ ++ ++#ifndef MIV_IHC_CONFIG_H_ ++#define MIV_IHC_CONFIG_H_ ++ ++#include "miv_ihc_add_mapping.h" ++ ++/*------------------------------------------------------------------------------ ++ * define the monitor hart (HSS hart) used in our system ++ */ ++#define HSS_HART_MASK HART0_MASK ++#define HSS_HART_ID HART0_ID ++ ++/*------------------------------------------------------------------------------ ++ * HSS_REMOTE_HARTS_MASK ++ * This is used to define the harts the HSS is communicating with ++ */ ++#define HSS_REMOTE_HARTS_MASK (HART1_MASK | HART2_MASK |HART3_MASK | HART4_MASK) ++ ++/*------------------------------------------------------------------------------ ++ * Define which harts are connected via comms channels to a particular hart ++ * user defined ++ */ ++#define IHCIA_H0_REMOTE_HARTS (HSS_REMOTE_HARTS_MASK) /* connected to all harts */ ++#define IHCIA_H1_REMOTE_HARTS (HSS_HART_MASK | HART4_MASK) /* HSS and Context B connected */ ++#define IHCIA_H2_REMOTE_HARTS (HSS_HART_MASK) ++#define IHCIA_H3_REMOTE_HARTS (HSS_HART_MASK) ++#define IHCIA_H4_REMOTE_HARTS (HSS_HART_MASK | HART1_MASK) /* HSS and Context A connected */ ++ ++/*------------------------------------------------------------------------------ ++ * interrupts enabled in this system design for a particular hart ++ * User defined ++ */ ++#define IHCIA_H0_REMOTE_HARTS_INTS HSS_HART_DEFAULT_INT_EN /* connected to all harts */ ++#define IHCIA_H1_REMOTE_HARTS_INTS (HSS_HART_MP_INT_EN | HSS_HART_ACK_INT_EN | HART4_MP_INT_EN | HART4_ACK_INT_EN) /* HSS and Context B connected */ ++#define IHCIA_H2_REMOTE_HARTS_INTS (HSS_HART_MP_INT_EN | HSS_HART_ACK_INT_EN) ++#define IHCIA_H3_REMOTE_HARTS_INTS (HSS_HART_MP_INT_EN | HSS_HART_ACK_INT_EN) ++#define IHCIA_H4_REMOTE_HARTS_INTS (HSS_HART_MP_INT_EN | HSS_HART_ACK_INT_EN | HART1_MP_INT_EN | HART1_ACK_INT_EN) /* HSS and Context A connected */ ++ ++#endif /* MIV_IHC_CONFIG_H_ */ ++ +diff -ruN A/boards/som1-soc/hss_board_init.c B/boards/som1-soc/hss_board_init.c +--- A/boards/som1-soc/hss_board_init.c 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/hss_board_init.c 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,154 @@ ++/******************************************************************************* ++ * Copyright 2017-2022 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * MPFS HSS Embedded Software ++ * ++ */ ++ ++/** ++ * \file HSS Board Initalization ++ * \brief Board Initialization ++ */ ++ ++#include "config.h" ++#include "hss_types.h" ++#include ++ ++#include "hss_debug.h" ++ ++#include "hss_init.h" ++#include "hss_state_machine.h" ++#include "ssmb_ipi.h" ++#include "hss_registry.h" ++ ++#ifndef __IO ++# define __IO volatile ++#endif ++#include "mss_io_config.h" ++#include "io/hw_mssio_mux.h" ++ ++/******************************************************************************************************/ ++/*! ++ * \brief Board Init Function Registration Table ++ * ++ * The following structure is used to connect in new board init functions. ++ */ ++ ++#include "hss_init.h" ++#include "hss_boot_pmp.h" ++#include "hss_sys_setup.h" ++#include "hss_board_init.h" ++ ++const struct InitFunction /*@null@*/ boardInitFunctions[] = { ++ // Name FunctionPointer Halt Restart ++ { "HSS_ZeroTIMs", HSS_ZeroTIMs, false, false }, ++ { "HSS_Setup_PLIC", HSS_Setup_PLIC, false, false }, ++ { "HSS_Setup_BusErrorUnit", HSS_Setup_BusErrorUnit, false, false }, ++ { "HSS_Setup_MPU", HSS_Setup_MPU, false, false }, ++ { "HSS_DDRInit", HSS_DDRInit, false, false }, ++ { "HSS_ZeroDDR", HSS_ZeroDDR, false, false }, ++#ifdef CONFIG_USE_PCIE ++ { "HSS_PCIeInit", HSS_PCIeInit, false, false }, ++#endif ++#ifdef CONFIG_USE_TAMPER ++ { "HSS_TamperInit", HSS_TamperInit, false, false }, ++#endif ++ //{ "HSS_USBInit", HSS_USBInit, false, false }, // if using 64-bit upper memory only, uncomment this ++}; ++ ++/******************************************************************************************************/ ++ ++/** ++ * \brief Board Initialization Function ++ * ++ * All other initialization routines to be chained off this... ++ */ ++ ++/****************************************************************************/ ++ ++ ++#include "mss_sysreg.h" ++bool HSS_BoardInit(void) ++{ ++ RunInitFunctions(ARRAY_SIZE(boardInitFunctions), boardInitFunctions); ++ ++ return true; ++} ++ ++bool HSS_BoardLateInit(void) ++{ ++ return true; ++} ++ ++ ++/** ++ * Is there a mux present, define is true by default ++ * @return true/false ++ */ ++__attribute__((weak)) uint8_t fabric_sd_emmc_demux_present(void) ++{ ++ return (uint8_t) false; // In the PolalBerry board SD/eMMC demuxer is alwqays disabled due to HW architecture ++//FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT; ++} ++ ++/* ++ * this function is used to switch external demux, and is board dependent ++ * For the MPFS-Video kit, we are changing I/O pullup and pull down states ++ * The setup for this is being automated in a future MSS Configurator release ++ * */ ++uint8_t switch_demux_using_fabric_ip(MSS_IO_OPTIONS option) ++{ ++ uint8_t result = false; ++ ++ if (!fabric_sd_emmc_demux_present()) ++ { ++ mHSS_PUTS("SD/eMMC internal demuxer is disabled!\n"); ++ result = true; ++ return result; ++ } ++ ++ switch(option) ++ { ++ case SD_MSSIO_CONFIGURATION: ++ mHSS_PUTS("SD_MSSIO_CONFIGURATION\n"); ++/* ++ SYSREG->IOMUX5_CR = LIBERO_SETTING_IOMUX5_CR; ++ SYSREG->IOMUX5_CR &= ~((0xF << 0) | (0xF << 16) | (0xF << 28)); ++ SYSREG->IOMUX5_CR |= ((0xE << 0) | (0xE << 16) | (0xD << 28)); ++ ++ //making usb pin pull down ++ SYSREG->IOMUX4_CR = LIBERO_SETTING_IOMUX4_CR; ++ SYSREG->IOMUX4_CR &= ~(0xF << 16); ++ SYSREG->IOMUX4_CR |= (0xD << 16); ++*/ ++ break; ++ ++ case EMMC_MSSIO_CONFIGURATION: ++ mHSS_PUTS("EMMC_MSSIO_CONFIGURATION\n"); ++ ++/* SYSREG->IOMUX5_CR = LIBERO_SETTING_IOMUX5_CR; ++ //masking pads need to make 30, 34, 37 and force pull down (0xD) ++ SYSREG->IOMUX5_CR &= ~((0xF << 0) | (0xF << 16) | (0xF << 28)); ++ SYSREG->IOMUX5_CR |= ((0xD << 0) | (0xD << 16) | (0xD << 28)); ++ ++ //making usb pin pull down ++ SYSREG->IOMUX4_CR = LIBERO_SETTING_IOMUX4_CR; ++ SYSREG->IOMUX4_CR &= ~(0xF << 16); ++ SYSREG->IOMUX4_CR |= (0xD << 16); ++*/ ++ break; ++ ++ case NO_SUPPORT_MSSIO_CONFIGURATION: ++ mHSS_PUTS("NO_SUPPORT_MSSIO_CONFIGURATION\n"); ++ break; ++ ++ case NOT_SETUP_MSSIO_CONFIGURATION: ++ mHSS_PUTS("NOT_SUPPORT_MSSIO_CONFIGURATION\n"); ++ break; ++ } ++ result = true; ++ ++ return result; ++} +\ No newline at end of file +diff -ruN A/boards/som1-soc/hss-l2scratch.ld B/boards/som1-soc/hss-l2scratch.ld +--- A/boards/som1-soc/hss-l2scratch.ld 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/hss-l2scratch.ld 2023-12-13 01:55:56.072295528 -0800 +@@ -0,0 +1,162 @@ ++OUTPUT_ARCH( "riscv" ) ++ENTRY(_start) ++MEMORY ++{ ++ envm (rx) : ORIGIN = 0x20220100, LENGTH = (128k-256) ++ dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k ++ switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k ++ e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k ++ u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k ++ u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k ++ u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k ++ u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k ++ l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 512k ++ l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k ++ ddr (rwx) : ORIGIN = 0x80000000, LENGTH = 32m ++ ddrhi (rwx) : ORIGIN = 0x1000000000, LENGTH = 1888m ++ ncddrhi (rwx) : ORIGIN = 0x1400000000, LENGTH = 2048m ++} ++PROVIDE(HEAP_SIZE = 0k); ++PROVIDE(STACK_SIZE_PER_HART = 16k); ++SECTIONS ++{ ++ PROVIDE(__envm_start = ORIGIN(envm)); ++ PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); ++ PROVIDE(__l2lim_start = ORIGIN(l2lim)); ++ PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); ++ PROVIDE(__l2_start = ORIGIN(l2zerodevice)); ++ PROVIDE(__l2_end = ORIGIN(l2zerodevice) + LENGTH(l2zerodevice)); ++ PROVIDE(__ddr_start = ORIGIN(ddr)); ++ PROVIDE(__ddr_end = ORIGIN(ddr) + LENGTH(ddr)); ++ PROVIDE(__ddrhi_start = ORIGIN(ddrhi)); ++ PROVIDE(__ddrhi_end = ORIGIN(ddrhi) + LENGTH(ddrhi)); ++ PROVIDE(__ddrhi_max_end = ORIGIN(ddrhi) + LENGTH(ncddrhi)); ++ PROVIDE(__ncddrhi_start = ORIGIN(ncddrhi)); ++ PROVIDE(__ncddrhi_end = ORIGIN(ncddrhi) + LENGTH(ncddrhi)); ++ PROVIDE(__dtim_start = ORIGIN(dtim)); ++ PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); ++ PROVIDE(__e51itim_start = ORIGIN(e51_itim)); ++ PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); ++ PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); ++ PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); ++ PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); ++ PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); ++ PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); ++ PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); ++ PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); ++ PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); ++ . = __l2_start; ++ PROVIDE(_hss_start = .); ++ PROVIDE(__l2_scratchpad_vma_start = .); ++ .text : ALIGN(0x10) ++ { ++ *(.entry) ++ . = ALIGN(0x10); ++ *(.text .text.* .gnu.linkonce.t.*) ++ *(.plt) ++ . = ALIGN(0x10); ++ KEEP (*crtbegin.o(.ctors)) ++ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) ++ KEEP (*(SORT(.ctors.*))) ++ KEEP (*crtend.o(.ctors)) ++ KEEP (*crtbegin.o(.dtors)) ++ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) ++ KEEP (*(SORT(.dtors.*))) ++ KEEP (*crtend.o(.dtors)) ++ *(.rodata .rodata.* .gnu.linkonce.r.*) ++ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) ++ *(.srodata*) ++ *(.sdata2*) ++ *(.gcc_except_table) ++ *(.eh_frame_hdr) ++ *(.eh_frame) ++ KEEP (*(.init)) ++ KEEP (*(.fini)) ++ PROVIDE_HIDDEN (__preinit_array_start = .); ++ KEEP (*(.preinit_array)) ++ PROVIDE_HIDDEN (__preinit_array_end = .); ++ PROVIDE_HIDDEN (__init_array_start = .); ++ KEEP (*(SORT(.init_array.*))) ++ KEEP (*(.init_array)) ++ PROVIDE_HIDDEN (__init_array_end = .); ++ PROVIDE_HIDDEN (__fini_array_start = .); ++ KEEP (*(.fini_array)) ++ KEEP (*(SORT(.fini_array.*))) ++ PROVIDE_HIDDEN (__fini_array_end = .); ++ . = ALIGN(0x10); ++ } >l2zerodevice ++ .gnu_build_id : ALIGN(8) { ++ PROVIDE(gnu_build_id = .); ++ *(.note.gnu.build-id) ++ } >l2zerodevice ++ PROVIDE(_hss_end = .); ++ .ram_code : ALIGN(0x10) ++ { ++ __sc_load = LOADADDR (.ram_code); ++ __sc_start = .; ++ *(.ram_codetext) ++ *(.ram_codetext*) ++ *(.ram_coderodata) ++ *(.ram_coderodata*) ++ . = ALIGN (0x10); ++ __sc_end = .; ++ } >switch_code ++ .sdata : ALIGN(0x40) ++ { ++ __sdata_load = LOADADDR(.sdata); ++ __sdata_start = .; ++ __global_pointer$ = . + 0x800; ++ *(.sdata .sdata.* .gnu.linkonce.s.*) ++ . = ALIGN(0x10); ++ __sdata_end = .; ++ } >l2zerodevice ++ .data : ALIGN(0x40) ++ { ++ __data_load = LOADADDR(.data); ++ __data_start = .; ++ *(.got.plt) *(.got) ++ *(.shdata) ++ *(.data .data.* .gnu.linkonce.d.*) ++ . = ALIGN(0x10); ++ __data_end = .; ++ } >l2zerodevice ++ .sbss : ALIGN(0x40) ++ { ++ __sbss_start = .; ++ *(.sbss .sbss.* .gnu.linkonce.sb.*) ++ *(.scommon) ++ . = ALIGN(0x10); ++ __sbss_end = .; ++ } >l2zerodevice ++ .bss : ALIGN(0x40) ++ { ++ __bss_start = .; ++ *(.shbss) ++ *(.bss .bss.* .gnu.linkonce.b.*) ++ *(COMMON) ++ . = ALIGN(0x10); ++ __bss_end = .; ++ } >l2zerodevice ++ .stack : ALIGN(0x40) ++ { ++ __stack_bottom = .; ++ __stack_bottom_h0$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h0$ = . - 8; ++ __stack_bottom_h1$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h1$ = . - 8; ++ __stack_bottom_h2$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h2$ = . - 8; ++ __stack_bottom_h3$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h3$ = . - 8; ++ __stack_bottom_h4$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h4$ = . - 8; ++ __stack_top = .; ++ } >l2zerodevice ++ _end = .; ++ PROVIDE(__l2_scratchpad_vma_end = .); ++} +diff -ruN A/boards/som1-soc/hss-l2scratch.lds B/boards/som1-soc/hss-l2scratch.lds +--- A/boards/som1-soc/hss-l2scratch.lds 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/hss-l2scratch.lds 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,365 @@ ++/******************************************************************************* ++ * Copyright 2019-2021 Microchip Corporation. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * GNU linker script for Hart Software Services (HSS) ++ * ++ */ ++ ++#include "config.h" ++ ++OUTPUT_ARCH( "riscv" ) ++ ++/* ++ ++ PolarFire SoC Memory map (ditaa diagram) ++ ---------------------------------------- ++ +-------------+ ++ +-----------+ | non-cache | ++ | non-cache | | WCB (SEG1) | ++ +---------------------+ | (SEG1) | 0x18_0000_0000 +-------------+ ++ | DDR cached | 0x14_0000_0000 +-----------+ | non-cache | ++ | (SEG0) | | non-cache | | WCB (SEG1) | ++0x10_0000_0000 +---------------------+ | (SEG1) | 0xD000_0000 +-------------+ ++ | DDR cached | 0xC000_0000 +-----------+ ++ | (SEG0) | ++ 0x8000_0000 +---------------------+ ++ | envm (128KiB) | ++ | | ++ 0x2022_0100 +---------------------+ ++ | Zero Device | ++ | | ++ 0x0A00_0000 +---------------------+ ++ | | ++ 0x0820_0000 +---------------------+ ++ | LIM (up to 1920KiB) | ++ | | ++ 0x0800_0000 +---------------------+ ++ | U54_4 ITIM (28KiB) | ++ | | ++ 0x0182_0000 +---------------------+ ++ | U54_3 ITIM (28KiB) | ++ | | ++ 0x0181_8000 +---------------------+ ++ | U54_2 ITIM (28KiB) | ++ | | ++ 0x0181_0000 +---------------------+ ++ | U54_1 ITIM (28KiB) | ++ | | ++ 0x0180_8000 +---------------------+ ++ | E51 ITIM (28KiB) | ++ | | ++ 0x0180_0000 +---------------------+ ++ | DTIM (8KiB) | ++ | | ++ 0x0100_0000 +---------------------+ ++ | Debug | ++ 0x0000_0000 +---------------------+ ++ ++ */ ++ ++/******************************************************************************* ++ * ++ * -- MSS hart Reset vector ++ * ++ * The MSS reset vector for each hart is configured by Libero and stored securely ++ * in the MPFS. ++ * ++ * The most common usage will be where the reset vector for each hart will be set ++ * to the start of the envm at address 0x2022_0100, giving (128KiB-256bytes) ++ * of contiguous non-volatile storage. Normally this is where the initial ++ * boot-loader will reside. ++ * ++ * Libero outputs the configured reset vector address to the xml file, see ++ * LIBERO_SETTING_RESET_VECTOR_HART0 etc in ++ * ++ * When debugging a bare metal program that is run out of reset from envm, a linker ++ * script will be used whereby the program will run from LIM instead of envm. ++ * In this case, set the reset vector in the linker script to 0x0800_0000. ++ * This means you are not continually programming the envm each time you load a ++ * program and there is no limitation with hardware break points whn debugging. ++ */ ++ENTRY(_start) ++ ++ ++/******************************************************************************* ++ * ++ * Memory Segments ++ * ++ * must be on 4k boundary (0x1000) - corresponds to page size, when using memory mem ++ */ ++MEMORY ++{ ++ envm (rx) : ORIGIN = 0x20220100, LENGTH = (128k-256) ++ ++ dtim (rwx) : ORIGIN = 0x01000000, LENGTH = 7k /* DTIM */ ++ switch_code (rx) : ORIGIN = 0x01001c00, LENGTH = 1k /* This 1K of DTIM is used to run code ++ * when switching the envm clock */ ++ e51_itim (rwx) : ORIGIN = 0x01800000, LENGTH = 28k ++ u54_1_itim (rwx) : ORIGIN = 0x01808000, LENGTH = 28k ++ u54_2_itim (rwx) : ORIGIN = 0x01810000, LENGTH = 28k ++ u54_3_itim (rwx) : ORIGIN = 0x01818000, LENGTH = 28k ++ u54_4_itim (rwx) : ORIGIN = 0x01820000, LENGTH = 28k ++ l2lim (rwx) : ORIGIN = 0x08000000, LENGTH = 512k ++ l2zerodevice (rwx) : ORIGIN = 0x0A000000, LENGTH = 512k ++ ddr (rwx) : ORIGIN = 0x80000000, LENGTH = 32m ++ ddrhi (rwx) : ORIGIN = 0x1000000000, LENGTH = 1888m ++ ncddrhi (rwx) : ORIGIN = 0x1400000000, LENGTH = 2048m ++} ++ ++PROVIDE(HEAP_SIZE = 0k); ++PROVIDE(STACK_SIZE_PER_HART = 16k); ++ ++/******************************************************************************* ++ * ++ * Memory Sections and Placement ++ */ ++SECTIONS ++{ ++ PROVIDE(__envm_start = ORIGIN(envm)); ++ PROVIDE(__envm_end = ORIGIN(envm) + LENGTH(envm)); ++ ++ PROVIDE(__l2lim_start = ORIGIN(l2lim)); ++ PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); ++ ++ PROVIDE(__l2_start = ORIGIN(l2zerodevice)); ++ PROVIDE(__l2_end = ORIGIN(l2zerodevice) + LENGTH(l2zerodevice)); ++ ++ PROVIDE(__ddr_start = ORIGIN(ddr)); ++ PROVIDE(__ddr_end = ORIGIN(ddr) + LENGTH(ddr)); ++ ++ PROVIDE(__ddrhi_start = ORIGIN(ddrhi)); ++ PROVIDE(__ddrhi_end = ORIGIN(ddrhi) + LENGTH(ddrhi)); ++ PROVIDE(__ddrhi_max_end = ORIGIN(ddrhi) + LENGTH(ncddrhi)); ++ ++ PROVIDE(__ncddrhi_start = ORIGIN(ncddrhi)); ++ PROVIDE(__ncddrhi_end = ORIGIN(ncddrhi) + LENGTH(ncddrhi)); ++ ++ PROVIDE(__dtim_start = ORIGIN(dtim)); ++ PROVIDE(__dtim_end = ORIGIN(dtim) + LENGTH(dtim)); ++ ++ PROVIDE(__e51itim_start = ORIGIN(e51_itim)); ++ PROVIDE(__e51itim_end = ORIGIN(e51_itim) + LENGTH(e51_itim)); ++ ++ PROVIDE(__u54_1_itim_start = ORIGIN(u54_1_itim)); ++ PROVIDE(__u54_1_itim_end = ORIGIN(u54_1_itim) + LENGTH(u54_1_itim)); ++ ++ PROVIDE(__u54_2_itim_start = ORIGIN(u54_2_itim)); ++ PROVIDE(__u54_2_itim_end = ORIGIN(u54_2_itim) + LENGTH(u54_2_itim)); ++ ++ PROVIDE(__u54_3_itim_start = ORIGIN(u54_3_itim)); ++ PROVIDE(__u54_3_itim_end = ORIGIN(u54_3_itim) + LENGTH(u54_3_itim)); ++ ++ PROVIDE(__u54_4_itim_start = ORIGIN(u54_4_itim)); ++ PROVIDE(__u54_4_itim_end = ORIGIN(u54_4_itim) + LENGTH(u54_4_itim)); ++ ++ /* ++ * Code and RO data lives in l2lim ++ */ ++ . = __l2_start; ++ ++ PROVIDE(_hss_start = .); ++ PROVIDE(__l2_scratchpad_vma_start = .); ++ ++ .text : ALIGN(0x10) ++ { ++ *(.entry) ++ . = ALIGN(0x10); ++ *(.text .text.* .gnu.linkonce.t.*) ++ *(.plt) ++ . = ALIGN(0x10); ++ ++ KEEP (*crtbegin.o(.ctors)) ++ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) ++ KEEP (*(SORT(.ctors.*))) ++ KEEP (*crtend.o(.ctors)) ++ KEEP (*crtbegin.o(.dtors)) ++ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) ++ KEEP (*(SORT(.dtors.*))) ++ KEEP (*crtend.o(.dtors)) ++ ++ *(.rodata .rodata.* .gnu.linkonce.r.*) ++ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) ++ *(.srodata*) ++ *(.sdata2*) ++ *(.gcc_except_table) ++ *(.eh_frame_hdr) ++ *(.eh_frame) ++ ++ KEEP (*(.init)) ++ KEEP (*(.fini)) ++ ++ PROVIDE_HIDDEN (__preinit_array_start = .); ++ KEEP (*(.preinit_array)) ++ PROVIDE_HIDDEN (__preinit_array_end = .); ++ PROVIDE_HIDDEN (__init_array_start = .); ++ KEEP (*(SORT(.init_array.*))) ++ KEEP (*(.init_array)) ++ PROVIDE_HIDDEN (__init_array_end = .); ++ PROVIDE_HIDDEN (__fini_array_start = .); ++ KEEP (*(.fini_array)) ++ KEEP (*(SORT(.fini_array.*))) ++ PROVIDE_HIDDEN (__fini_array_end = .); ++ . = ALIGN(0x10); ++ } >l2zerodevice ++ ++ .gnu_build_id : ALIGN(8) { ++ PROVIDE(gnu_build_id = .); ++ *(.note.gnu.build-id) ++ } >l2zerodevice ++ ++ PROVIDE(_hss_end = .); ++ ++ /******************************************************************************* ++ * ++ * The .ram_code section will contain the code That is run from RAM. ++ * We are using this code to switch the clocks including envm clock. ++ * This can not be done when running from envm ++ * This will need to be copied to ram, before any of this code is run. ++ * ++ */ ++ .ram_code : ALIGN(0x10) ++ { ++ __sc_load = LOADADDR (.ram_code); ++ __sc_start = .; ++ *(.ram_codetext) /* .ram_codetext sections (code) */ ++ *(.ram_codetext*) /* .ram_codetext* sections (code) */ ++ *(.ram_coderodata) /* read-only data (constants) */ ++ *(.ram_coderodata*) ++ . = ALIGN (0x10); ++ __sc_end = .; ++ } >switch_code ++ ++ /******************************************************************************* ++ * ++ * Short/global data section ++ * ++ */ ++ .sdata : ALIGN(0x40) /* short/global data section */ ++ { ++ __sdata_load = LOADADDR(.sdata); ++ __sdata_start = .; ++ ++ /* ++ * offset used with gp(gloabl pointer) are +/- 12 bits, so set ++ * point to middle of expected sdata range ++ * ++ * If sdata more than 4K, linker used direct addressing. ++ * Perhaps we should add check/warning to linker script if sdata is > 4k ++ */ ++ __global_pointer$ = . + 0x800; ++ *(.sdata .sdata.* .gnu.linkonce.s.*) ++ . = ALIGN(0x10); ++ __sdata_end = .; ++ } >l2zerodevice ++ ++ /******************************************************************************* ++ * ++ * (Explicitly) Initialized data section ++ * ++ */ ++#ifdef CONFIG_SERVICE_BOOT_USE_PAYLOAD ++ .data.payload : ALIGN(16) ++ { ++ _payload_start = .; ++ KEEP(boards/som1-soc/payload.o(.*)) ++ _payload_end = .; ++ } ++#endif ++ ++ .data : ALIGN(0x40) ++ { ++ __data_load = LOADADDR(.data); ++ __data_start = .; ++ *(.got.plt) *(.got) ++ *(.shdata) ++ *(.data .data.* .gnu.linkonce.d.*) ++ . = ALIGN(0x10); ++ __data_end = .; ++ } >l2zerodevice ++ ++ /******************************************************************************* ++ * ++ * Uninitialized (zero-initialized) section ++ */ ++ ++ /* ++ * Short zero-initialized section ++ * The name BSS is an anacronym for "Block Started by Symbol" from a mid 1950s ++ * assembly language for the IBM 704. ++ * ++ */ ++ .sbss : ALIGN(0x40) ++ { ++ __sbss_start = .; ++ *(.sbss .sbss.* .gnu.linkonce.sb.*) ++ *(.scommon) ++ . = ALIGN(0x10); ++ __sbss_end = .; ++ } >l2zerodevice ++ ++ /* ++ * General Zero-initialized section ++ * The name BSS is an anacronym for "Block Started by Symbol" from a mid 1950s ++ * assembly language for the IBM 704. ++ */ ++ .bss : ALIGN(0x40) ++ { ++ __bss_start = .; ++ *(.shbss) ++ *(.bss .bss.* .gnu.linkonce.b.*) ++ *(COMMON) ++ . = ALIGN(0x10); ++ __bss_end = .; ++ } >l2zerodevice ++ ++ /* ++ * Reserved space for Hart stacks ++ */ ++ .stack : ALIGN(0x40) ++ { ++ __stack_bottom = .; ++ ++ __stack_bottom_h0$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h0$ = . - 8; ++ ++ __stack_bottom_h1$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h1$ = . - 8; ++ ++ __stack_bottom_h2$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h2$ = . - 8; ++ ++ __stack_bottom_h3$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h3$ = . - 8; ++ ++ __stack_bottom_h4$ = .; ++ . += STACK_SIZE_PER_HART; ++ __stack_top_h4$ = . - 8; ++ ++ __stack_top = .; ++ } >l2zerodevice ++ ++ _end = .; ++ PROVIDE(__l2_scratchpad_vma_end = .); ++ ++ /* ++ * End of uninitialized data segment ++ * ++ *******************************************************************************/ ++ ++ /* ++ .heap : ALIGN(0x10) ++ { ++ __heap_start = .; ++ . += HEAP_SIZE; ++ __heap_end = .; ++ . = ALIGN(0x10); ++ _heap_end = __heap_end; ++ } >dtim ++ */ ++} +diff -ruN A/boards/som1-soc/hss_logo_init.c B/boards/som1-soc/hss_logo_init.c +--- A/boards/som1-soc/hss_logo_init.c 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/hss_logo_init.c 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,206 @@ ++/******************************************************************************* ++ * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * MPFS HSS Embedded Software ++ * ++ */ ++ ++/** ++ * \file HSS Software Initalization ++ * \brief Full System Initialization ++ */ ++ ++#include "config.h" ++#include "hss_types.h" ++ ++#include "hss_init.h" ++#include "hss_debug.h" ++ ++// ++// A variety of colored pixels are needed - red, white, black ++// define these as ASCII characters if color output is not enabled ++// ++#if IS_ENABLED(CONFIG_COLOR_OUTPUT) ++# if IS_ENABLED(CONFIG_LOGO_INVERT_COLORS) ++ const char B0_str[] ="\033[48;5;188m "; ++ const char W0_str[] ="\033[0m "; ++ const char r1_str[] ="\033[48;5;217m "; ++ const char r2_str[] ="\033[48;5;210m "; ++ const char r3_str[] ="\033[48;5;203m "; ++ const char r4_str[] ="\033[48;5;196m "; ++ const char b1_str[] ="\033[48;5;188m "; ++ const char b2_str[] ="\033[48;5;145m "; ++ const char b3_str[] ="\033[48;5;102m "; ++ const char b4_str[] ="\033[48;5;59m "; ++# else ++ const char B0_str[] = "\033[48;5;188m "; ++ const char W0_str[] = "\033[48;5;188m "; ++ const char r1_str[] ="\033[48;5;217m "; ++ const char r2_str[] ="\033[48;5;210m "; ++ const char r3_str[] ="\033[48;5;203m "; ++ const char r4_str[] ="\033[48;5;196m "; ++ const char b1_str[] ="\033[48;5;16m "; ++ const char b2_str[] ="\033[48;5;59m "; ++ const char b3_str[] ="\033[48;5;102m "; ++ const char b4_str[] ="\033[48;5;145m "; ++# endif ++ const char RST_str[] ="\033[0m"; ++#else ++ const char B0_str[] =" "; ++ const char W0_str[] =" "; ++ const char r1_str[] ="."; ++ const char r2_str[] ="-"; ++ const char r3_str[] ="x"; ++ const char r4_str[] ="X"; ++ const char b1_str[] =":"; ++ const char b2_str[] ="o"; ++ const char b3_str[] ="0"; ++ const char b4_str[] ="O"; ++ const char RST_str[] =""; ++#endif ++ ++enum Color { ++ B0 = 0, ++ W0, ++ r1, ++ r2, ++ r3, ++ r4, ++ b1, ++ b2, ++ b3, ++ b4, ++ RST, ++ CRLF_token, ++}; ++ ++const char* tokenStringTable[] = { ++ B0_str, ++ W0_str, ++ r1_str, ++ r2_str, ++ r3_str, ++ r4_str, ++ b1_str, ++ b2_str, ++ b3_str, ++ b4_str, ++ RST_str, ++ "\n", ++}; ++ ++ ++// RLE Microchip Logo, built up from our color pixel primitives above... ++// RLE shrinks the size of this ++const struct __attribute__((packed)) { ++ uint8_t const count; ++ enum Color const tokenIndex; ++} rleLogoElements[] = { ++ { 4, W0 }, { 1, r1 }, { 1, r3 }, { 7, r4 }, { 62, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 3, W0 }, { 1, r2 }, { 9, r4 }, { 1, r3 }, { 61, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 2, W0 }, { 1, r3 }, { 2, r4 }, { 1, r3 }, { 1, r2 }, { 5, r4 }, { 1, r2 }, ++ { 1, r4 }, { 1, r1 }, { 7, W0 }, { 1, b3 }, { 5, W0 }, { 1, b3 }, { 46, W0 }, ++ { 1, RST }, { 1, CRLF_token }, ++ ++ { 1, W0 }, { 1, r1 }, { 3, r4 }, { 2, B0 }, { 1, r2 }, { 3, r4 }, { 1, r1 }, ++ { 1, B0 }, { 1, r1 }, { 1, r4 }, { 6, W0 }, { 1, b4 }, { 1, b1 }, { 1, b2 }, ++ { 3, W0 }, { 1, b3 }, { 1, b1 }, { 1, b4 }, { 45, W0 }, { 1, RST }, ++ { 1, CRLF_token }, ++ ++ { 1, W0 }, { 3, r4 }, { 1, r1 }, { 3, B0 }, { 2, r4 }, { 1, r2 }, { 3, B0 }, ++ { 2, r3 }, { 5, W0 }, { 1, b4 }, { 2, b1 }, { 3, W0 }, { 2, b1 }, { 1, b4 }, ++ { 1, W0 }, { 1, b4 }, { 2, W0 }, { 1, b4 }, { 3, b3 }, { 1, b4 }, { 1, W0 }, ++ { 5, b4 }, { 2, W0 }, { 1, b4 }, { 3, b3 }, { 1, b4 }, { 2, W0 }, { 1, b4 }, ++ { 3, b3 }, { 1, b4 }, { 1, W0 }, { 1, b4 }, { 3, W0 }, { 1, b4 }, { 2, W0 }, ++ { 1, b4 }, { 1, W0 }, { 5, b4 }, { 1, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 1, r1 }, { 3, r4 }, { 4, B0 }, { 1, r1 }, { 1, r4 }, { 5, B0 }, { 1, r4 }, ++ { 1, r1 }, { 4, W0 }, { 1, b3 }, { 2, b1 }, { 1, b4 }, { 1, W0 }, { 1, b4 }, ++ { 2, b1 }, { 1, b3 }, { 1, W0 }, { 1, b1 }, { 1, b4 }, { 1, W0 }, { 5, b1 }, ++ { 1, W0 }, { 5, b1 }, { 1, b3 }, { 1, W0 }, { 5, b1 }, { 1, b4 }, { 1, W0 }, ++ { 5, b1 }, { 1, W0 }, { 1, b1 }, { 3, W0 }, { 1, b2 }, { 1, b4 }, { 1, W0 }, ++ { 1, b1 }, { 1, W0 }, { 5, b1 }, { 1, b3 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 1, r2 }, { 2, r4 }, { 1, r3 }, { 1, r2 }, { 4, B0 }, { 1, r3 }, { 1, r2 }, ++ { 4, B0 }, { 1, r2 }, { 1, r4 }, { 4, W0 }, { 1, b3 }, { 3, b2 }, { 1, W0 }, ++ { 2, b2 }, { 1, b3 }, { 1, b2 }, { 1, W0 }, { 1, b1 }, { 2, b4 }, { 1, b1 }, ++ { 5, W0 }, { 1, b1 }, { 1, b4 }, { 2, W0 }, { 1, b3 }, { 1, b2 }, { 1, b4 }, ++ { 1, b1 }, { 3, W0 }, { 1, b2 }, { 1, b3 }, { 1, b4 }, { 1, b1 }, { 5, W0 }, ++ { 1, b1 }, { 1, b4 }, { 2, W0 }, { 1, b2 }, { 1, b4 }, { 1, W0 }, { 1, b1 }, ++ { 1, W0 }, { 1, b1 }, { 1, b4 }, { 2, W0 }, { 1, b3 }, { 1, b2 }, { 1, RST }, ++ { 1, CRLF_token }, ++ ++ { 1, r3 }, { 1, r4 }, { 1, r1 }, { 1, B0 }, { 1, r4 }, { 5, B0 }, { 1, r4 }, ++ { 5, B0 }, { 1, r4 }, { 1, r2 }, { 3, W0 }, { 1, b2 }, { 1, b3 }, { 1, W0 }, ++ { 1, b1 }, { 1, b3 }, { 1, b1 }, { 1, b4 }, { 1, b3 }, { 1, b2 }, { 1, W0 }, ++ { 1, b1 }, { 2, b4 }, { 1, b2 }, { 5, W0 }, { 1, b1 }, { 1, b3 }, { 2, W0 }, ++ { 2, b3 }, { 1, b4 }, { 1, b1 }, { 3, W0 }, { 1, b2 }, { 1, b3 }, { 1, b4 }, ++ { 1, b2 }, { 5, W0 }, { 5, b1 }, { 1, b4 }, { 1, W0 }, { 1, b1 }, { 1, W0 }, ++ { 1, b1 }, { 1, b4 }, { 2, W0 }, { 1, b3 }, { 1, b2 }, { 1, RST }, ++ { 1, CRLF_token }, ++ ++ { 1, r3 }, { 1, r2 }, { 2, B0 }, { 1, r2 }, { 1, r3 }, { 4, B0 }, { 1, r1 }, ++ { 1, r3 }, { 4, B0 }, { 1, r1 }, { 1, r4 }, { 3, W0 }, { 1, b1 }, { 1, b3 }, ++ { 1, W0 }, { 3, b1 }, { 1, W0 }, { 1, b4 }, { 1, b1 }, { 1, W0 }, { 1, b1 }, ++ { 2, b4 }, { 1, b2 }, { 5, W0 }, { 5, b1 }, { 1, W0 }, { 1, b4 }, { 1, b1 }, ++ { 3, W0 }, { 1, b2 }, { 1, b3 }, { 1, b4 }, { 1, b2 }, { 5, W0 }, { 1, b1 }, ++ { 1, b3 }, { 2, b4 }, { 1, b2 }, { 1, b4 }, { 1, W0 }, { 1, b1 }, { 1, W0 }, ++ { 5, b1 }, { 1, b3 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 1, r1 }, { 4, B0 }, { 1, r4 }, { 1, r1 }, { 4, B0 }, { 1, r3 }, { 1, r2 }, ++ { 4, B0 }, { 1, r3 }, { 3, W0 }, { 1, b1 }, { 1, b4 }, { 1, W0 }, { 1, b3 }, ++ { 1, b1 }, { 1, b3 }, { 1, W0 }, { 1, b4 }, { 1, b1 }, { 1, W0 }, { 1, b1 }, ++ { 2, b4 }, { 1, b1 }, { 4, b4 }, { 1, W0 }, { 1, b1 }, { 1, b3 }, { 2, W0 }, ++ { 1, b2 }, { 1, b3 }, { 1, W0 }, { 1, b1 }, { 1, b3 }, { 2, b4 }, { 1, b1 }, ++ { 1, b3 }, { 1, b4 }, { 1, b1 }, { 4, b4 }, { 1, W0 }, { 1, b1 }, { 3, W0 }, ++ { 1, b2 }, { 1, b4 }, { 1, W0 }, { 1, b1 }, { 1, W0 }, { 1, b1 }, { 1, b3 }, ++ { 2, b4 }, { 2, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 5, B0 }, { 1, r3 }, { 1, r4 }, { 4, B0 }, { 1, r1 }, { 1, r4 }, { 5, B0 }, { 3, W0 }, ++ { 1, b1 }, { 1, b4 }, { 2, W0 }, { 1, b3 }, { 3, W0 }, { 1, b1 }, { 1, W0 }, ++ { 1, b1 }, { 1, b4 }, { 1, W0 }, { 5, b1 }, { 1, W0 }, { 1, b1 }, { 1, b4 }, ++ { 2, W0 }, { 2, b3 }, { 1, W0 }, { 1, b2 }, { 4, b1 }, { 2, W0 }, { 5, b1 }, ++ { 1, W0 }, { 1, b1 }, { 3, W0 }, { 1, b2 }, { 1, b4 }, { 1, W0 }, { 1, b1 }, ++ { 1, W0 }, { 1, b1 }, { 5, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 1, W0 }, { 3, B0 }, { 1, r2 }, { 2, r4 }, { 1, r2 }, { 3, B0 }, { 1, r3 }, { 1, r4 }, ++ { 1, r3 }, {2, B0 }, {1, B0}, { 58, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 1, W0 }, {1, r1}, { 2, B0 }, { 4, r4 }, { 2, B0 }, { 1, r1 }, { 3, r4 }, { 1, r1 }, ++ {1, B0 }, {1, r1}, { 58, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 2, W0 }, {1, r2}, { 5, r4 }, { 1, r3 }, { 1, r1 }, { 5, r4 }, {1, r3}, { 59, W0 }, ++ { 1, RST }, { 1, CRLF_token }, ++ ++ { 3, W0 }, { 1, r2 }, { 11, r4 }, { 60, W0 }, { 1, RST }, { 1, CRLF_token }, ++ ++ { 4, W0 }, { 1, r1 }, { 1, r3 }, { 7, r4 }, { 1, r3 }, { 61, W0 }, { 1, RST }, {1, CRLF_token} ++}; ++ ++bool HSS_LogoInit(void) ++{ ++ mHSS_PUTS("\n"); ++ int i; ++ ++ // decode and output our RLE Logo ++ for (i = 0; i < ARRAY_SIZE(rleLogoElements); i++) { ++ uint8_t j; ++ ++ for (j = 0u; j < rleLogoElements[i].count; j++) { ++ mHSS_PUTS(tokenStringTable[rleLogoElements[i].tokenIndex]); ++ } ++ } ++ ++ mHSS_PUTS("\n" ++ "-------------------------\n" ++ "-- Custom Board Design --\n" ++ "-- PolarFire SoC FPGA --\n" ++ "-------------------------\n" ++ "\n"); ++ ++ return true; ++} +diff -ruN A/boards/som1-soc/hss_uart_init.c B/boards/som1-soc/hss_uart_init.c +--- A/boards/som1-soc/hss_uart_init.c 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/hss_uart_init.c 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,48 @@ ++/******************************************************************************* ++ * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * MPFS HSS Embedded Software ++ * ++ */ ++ ++/** ++ * \file HSS Debug UART Initalization ++ * \brief Debug UART Initialization ++ */ ++ ++#include "config.h" ++#include "hss_types.h" ++#include "hss_init.h" ++ ++#include ++ ++#include "hss_debug.h" ++ ++#include "drivers/mss/mss_mmuart/mss_uart.h" ++#include "uart_helper.h" ++ ++bool HSS_UARTInit(void) ++{ ++ // initialise debug UART ++ ++ MSS_UART_init(HSS_UART_GetInstance(HSS_HART_E51), MSS_UART_115200_BAUD, ++ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); ++ ++ // default all UARTs to 115200 for now ++ // subsequent OS loads can change these if needed... ++ MSS_UART_init(HSS_UART_GetInstance(HSS_HART_U54_1), MSS_UART_115200_BAUD, ++ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); ++ ++ MSS_UART_init(HSS_UART_GetInstance(HSS_HART_U54_2), MSS_UART_115200_BAUD, ++ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); ++ ++ MSS_UART_init(HSS_UART_GetInstance(HSS_HART_U54_3), MSS_UART_115200_BAUD, ++ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); ++ ++ MSS_UART_init(HSS_UART_GetInstance(HSS_HART_U54_4), MSS_UART_115200_BAUD, ++ MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); ++ ++ return true; ++} +\ No newline at end of file +diff -ruN A/boards/som1-soc/Kconfig B/boards/som1-soc/Kconfig +--- A/boards/som1-soc/Kconfig 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/Kconfig 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,9 @@ ++menu "Custom Board Design Configuration Options" ++ ++config SOC_FPGA_DESIGN_XML ++ string "Enter path to Libero XML file" ++ default "boards/som1-soc/soc_fpga_design/xml/som1-soc.xml" ++ help ++ This option specifies the design XML file to use. ++endmenu ++ +diff -ruN A/boards/som1-soc/Makefile B/boards/som1-soc/Makefile +--- A/boards/som1-soc/Makefile 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/Makefile 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,136 @@ ++# ++# MPFS HSS Embedded Software ++# ++# Copyright 2019-2021 Microchip Corporation. ++# ++# SPDX-License-Identifier: MIT ++# ++# Permission is hereby granted, free of charge, to any person obtaining a copy ++# of this software and associated documentation files (the "Software"), to ++# deal in the Software without restriction, including without limitation the ++# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or ++# sell copies of the Software, and to permit persons to whom the Software is ++# furnished to do so, subject to the following conditions: ++# ++# The above copyright notice and this permission notice shall be included in ++# all copies or substantial portions of the Software. ++# ++# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++# IN THE SOFTWARE. ++# ++# ++# Defines target-specific build-rules variables, extra sources and include paths ++# ++ ++$(info ${BOARD} selected) ++ ++BINDIR=Default ++TARGET-l2scratch=hss-l2scratch.elf ++TARGET-envm-wrapper=hss-envm-wrapper.elf ++RISCV_TARGET=$(TARGET-l2scratch) $(TARGET-envm-wrapper) ++TARGET:=$(RISCV_TARGET) ++ ++LINKER_SCRIPT-l2scratch=boards/${BOARD}/hss-l2scratch.ld ++ ++BOARD_DIR=boards/${BOARD} ++ ++INCLUDES += \ ++ -I$(BOARD_DIR)/mpfs_hal_config/\ ++ -I$(BOARD_DIR)/fpga_design_config/\ ++ -I$(BOARD_DIR)/ \ ++ -Ibaremetal/polarfire-soc-bare-metal-library/src/platform \ ++ ++EXTRA_SRCS-y += \ ++ $(BOARD_DIR)/hss_uart_init.c \ ++ $(BOARD_DIR)/uart_device_list.c \ ++ $(BOARD_DIR)/hss_board_init.c \ ++ ++EXTRA_SRCS-$(CONFIG_USE_LOGO) += \ ++ $(BOARD_DIR)/hss_logo_init.c ++ ++$(BOARD_DIR)/hss_uart_init.o: CFLAGS=$(CFLAGS_GCCEXT) ++ ++EXTRA_OBJS-$(CONFIG_SERVICE_BOOT_USE_PAYLOAD) += $(BOARD_DIR)/payload.o ++$(BOARD_DIR)/payload.o: $(BOARD_DIR)/payload.bin ++ $(LD) -r -b binary $< -o $@ ++ ++################################################################################################ ++# ++# Extra hardware dependency rules for QSPI ++# ++ ++INCLUDES += \ ++ -Ibaremetal/ \ ++ -Ibaremetal/drivers/winbond_w25n01gv \ ++ ++baremetal/drivers/winbond_w25n01gv/winbond_w25n01gv.o: CFLAGS=$(CFLAGS_GCCEXT) ++ ++################################################################################################ ++# ++# Linker Scripts ++# ++ ++$(BOARD_DIR)/hss-l2scratch.ld: $(BOARD_DIR)/hss-l2scratch.lds config.h ++ ++################################################################################################ ++ ++# ++# Extra dependency rules for auto-generated configuration files (from Libero XML) ++# ++ ++SOC_CONFIG_FILES = \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_clk_ddr_pll.h \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_clk_mss_cfm.h \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_clk_mss_pll.h \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_clk_sgmii_cfm.h \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_clk_sgmii_pll.h \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_clk_sysreg.h \ ++ $(BOARD_DIR)/fpga_design_config/clocks/hw_mss_clks.h \ ++ $(BOARD_DIR)/fpga_design_config/ddr/hw_ddr_io_bank.h \ ++ $(BOARD_DIR)/fpga_design_config/ddr/hw_ddr_mode.h \ ++ $(BOARD_DIR)/fpga_design_config/ddr/hw_ddr_off_mode.h \ ++ $(BOARD_DIR)/fpga_design_config/ddr/hw_ddr_options.h \ ++ $(BOARD_DIR)/fpga_design_config/ddr/hw_ddr_segs.h \ ++ $(BOARD_DIR)/fpga_design_config/ddr/hw_ddrc.h \ ++ $(BOARD_DIR)/fpga_design_config/general/hw_gen_peripherals.h \ ++ $(BOARD_DIR)/fpga_design_config/fpga_design_config.h \ ++ $(BOARD_DIR)/fpga_design_config/io/hw_hsio_mux.h \ ++ $(BOARD_DIR)/fpga_design_config/io/hw_mssio_mux.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_apb_split.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_cache.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_memory.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_crypto.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_fic0.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_fic1.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_fic2.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_gem0.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_gem1.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_mmc.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_scb.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_trace.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_mpu_usb.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_pmp_hart0.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_pmp_hart1.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_pmp_hart2.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_pmp_hart3.h \ ++ $(BOARD_DIR)/fpga_design_config/memory_map/hw_pmp_hart4.h \ ++ $(BOARD_DIR)/fpga_design_config/sgmii/hw_sgmii_tip.h \ ++ ++$(info MSS config file is: $(CONFIG_SOC_FPGA_DESIGN_XML)) ++ ++SOC_FPGA_DESIGN_XML_FILE= $(subst $\",,$(CONFIG_SOC_FPGA_DESIGN_XML)) ++ifeq ("$(wildcard $(SOC_FPGA_DESIGN_XML_FILE))", "") ++$(error "XML file $(CONFIG_SOC_FPGA_DESIGN_XML) specified by CONFIG_SOC_FPGA_DESIGN_XML does not exist") ++endif ++ ++config.h: $(SOC_CONFIG_FILES) ++$(SOC_CONFIG_FILES): $(SOC_FPGA_DESIGN_XML_FILE) ++ @$(ECHO) " MPFSCFGGEN $<"; ++ $(PYTHON) tools/polarfire-soc-configuration-generator/mpfs_configuration_generator.py $< $(BOARD_DIR) ++ ++$(RISCV_TARGET): $(SOC_CONFIG_FILES) +diff -ruN A/boards/som1-soc/mpfs_hal_config/mss_sw_config.h B/boards/som1-soc/mpfs_hal_config/mss_sw_config.h +--- A/boards/som1-soc/mpfs_hal_config/mss_sw_config.h 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/mpfs_hal_config/mss_sw_config.h 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,246 @@ ++#ifndef MSS_SW_CONFIG_H_ ++#define MSS_SW_CONFIG_H_ ++ ++/******************************************************************************* ++ * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * MPFS HAL Embedded Software ++ * ++ */ ++ ++/******************************************************************************* ++ * ++ * Platform definitions ++ * Version based on requirements of MPFS MSS ++ * ++ */ ++ /*========================================================================*//** ++ @mainpage Sample file detailing how mss_sw_config.h should be constructed for ++ the MPFS MSS ++ ++ @section intro_sec Introduction ++ The mss_sw_config.h has the default software configuration settings for the ++ MPFS HAL and will be located at ++ /src/platform/platform_config_reference folder of the bare ++ metal SoftConsole project. The platform_config_reference is provided as a ++ default reference configuration. ++ When you want to configure the MPFS HAL with required configuration for ++ your project, the mss_sw_config.h must be edited and be placed in the ++ following project directory: ++ /src/boards//platform_config/mpfs_hal_config/ ++ ++ @section ++ ++*//*==========================================================================*/ ++ ++/* ++ * Include any driver setup/over-rides you may require. ++ */ ++#include "drivers/fpga_ip/miv_ihc/miv_ihc_defines.h" ++#include "drivers_config/fpga_ip/miv_ihc/miv_ihc_config.h" ++ ++/* ++ * MPFS_HAL_FIRST_HART and MPFS_HAL_LAST_HART defines are used to specify which ++ * harts to actually start. The value and the actual hart it represents are ++ * listed below: ++ * value hart ++ * 0 E51 ++ * 1 U54_1 ++ * 2 U54_2 ++ * 3 U54_3 ++ * 4 U54_4 ++ * Set MPFS_HAL_FIRST_HART to a value greater than 0 if you do not want your ++ * application to start and execute code on the harts represented by smaller ++ * value numbers. ++ * Set MPFS_HAL_LAST_HART to a value smaller than 4 if you do not wish to use ++ * all U54_x harts. ++ * Harts that are not started will remain in an infinite WFI loop unless used ++ * through some other method. ++ * The value of MPFS_HAL_FIRST_HART must always be less than MPFS_HAL_LAST_HART. ++ * The value of MPFS_HAL_LAST_HART must never be greater than 4. ++ * A typical use-case where you set MPFS_HAL_FIRST_HART = 1 and ++ * MPFS_HAL_LAST_HART = 1 is when ++ * your application is running on U54_1 and a bootloader running on E51 loads ++ * your application to the target memory and kicks-off U54_1 to run it. ++ */ ++#ifndef MPFS_HAL_FIRST_HART ++#define MPFS_HAL_FIRST_HART 1 // was 0 in OLD HSS ++#endif ++ ++#ifndef MPFS_HAL_LAST_HART ++#define MPFS_HAL_LAST_HART 4 ++#endif ++ ++/* ++ * IMAGE_LOADED_BY_BOOTLOADER ++ * We set IMAGE_LOADED_BY_BOOTLOADER = 0 if the application image runs from ++ * non-volatile memory after reset. (No previous stage bootloader is used.) ++ * Set IMAGE_LOADED_BY_BOOTLOADER = 1 if the application image is loaded by a ++ * previous stage bootloader. ++ * ++ * MPFS_HAL_HW_CONFIG is defined if we are a boot-loader. This is a ++ * conditional compile switch is used to determine if MPFS HAL will perform the ++ * hardware configurations or not. ++ * Defined => This program acts as a First stage bootloader and performs ++ * hardware configurations. ++ * Not defined => This program assumes that the hardware configurations are ++ * already performed (Typically by a previous boot stage) ++ * ++ * List of items initialised when MPFS_HAL_HW_CONFIG is enabled ++ * - load virtual rom (see load_virtual_rom(void) in system_startup.c) ++ * - l2 cache config ++ * - Bus error unit config ++ * - MPU config ++ * - pmp config ++ * - I/O, clock and clock mux's, DDR and SGMII ++ * - will start other harts, see text describing MPFS_HAL_FIRST_HART, ++ * MPFS_HAL_LAST_HART above ++ * ++ */ ++#define IMAGE_LOADED_BY_BOOTLOADER 0 ++#if (IMAGE_LOADED_BY_BOOTLOADER == 0) ++#define MPFS_HAL_HW_CONFIG ++#endif ++ ++/*------------------------------------------------------------------------------ ++ * Markers used to indicate startup status of hart ++ */ ++#define HLS_DATA_IN_WFI 0x12345678U ++#define HLS_DATA_PASSED_WFI 0x87654321U ++ ++/* ++ * If you are using common memory for sharing across harts, ++ * uncomment #define MPFS_HAL_SHARED_MEM_ENABLED ++ * make sure common memory is allocated in the linker script ++ * See app_hart_common mem section in the example platform ++ * linker scripts. ++ */ ++ ++//#define MPFS_HAL_SHARED_MEM_ENABLED ++ ++ ++/* define the required tick rate in Milliseconds */ ++/* if this program is running on one hart only, only that particular hart value ++ * will be used */ ++#define HART0_TICK_RATE_MS 5UL ++#define HART1_TICK_RATE_MS 5UL ++#define HART2_TICK_RATE_MS 5UL ++#define HART3_TICK_RATE_MS 5UL ++#define HART4_TICK_RATE_MS 5UL ++ ++/* ++ * Define the size of the Hart Local Storage (HLS). ++ * In the MPFS HAL, we are using HLS for debug data storage during the initial ++ * boot phase. ++ * This includes the flags which indicate the hart state regarding boot state. ++ * The HLS will take memory from top of each stack allocated at boot time. ++ * ++ */ ++#define HLS_DEBUG_AREA_SIZE 64 ++ ++/* ++ * Bus Error Unit (BEU) configurations ++ * BEU_ENABLE => Configures the events that the BEU can report. bit value ++ * 1= enabled, 0 = disabled. ++ * BEU_PLIC_INT => Configures which accrued events should generate an ++ * interrupt to the PLIC. ++ * BEU_LOCAL_INT => Configures which accrued events should generate a ++ * local interrupt to the hart on which the event accrued. ++ */ ++#define BEU_ENABLE 0x0ULL ++#define BEU_PLIC_INT 0x0ULL ++#define BEU_LOCAL_INT 0x0ULL ++ ++/* ++ * Clear memory on startup ++ * 0 => do not clear DTIM and L2 ++ * 1 => Clears memory ++ * Note: If you are the zero stage bootloader, set this to one. ++ */ ++#ifndef MPFS_HAL_CLEAR_MEMORY ++#define MPFS_HAL_CLEAR_MEMORY 0 ++#endif ++ ++/* ++ * Comment out the lines to disable the corresponding hardware support not required ++ * in your application. ++ * This is not necessary from an operational point of view as operation dictated ++ * by MSS configurator settings, and items are enabled/disabled by this method. ++ * The reason you may want to use below is to save code space. ++ */ ++#define SGMII_SUPPORT ++#define DDR_SUPPORT ++#define MSSIO_SUPPORT ++ ++/* ++ * Debugging IHC. This placed memory map in volatile memory and uses software ++ * state machine ++ */ ++#define LIBERO_SETTING_CONTEXT_A_HART_EN 0x0000000EUL /* harts 1 to 3 */ ++#define LIBERO_SETTING_CONTEXT_B_HART_EN 0x00000010UL /* hart 4 */ ++ ++/* ++ * DDR software options ++ */ ++ ++/* ++ * Debug DDR startup through a UART ++ * Comment out in normal operation. May be useful for debug purposes in bring-up ++ * of a new board design. ++ * See the weakly linked function setup_ddr_debug_port(mss_uart_instance_t * uart) ++ * If you need to edit this function, make another copy of the function in your ++ * application without the weak linking attribute. This copy will then get linked. ++ * */ ++#define DEBUG_DDR_INIT ++//#define DEBUG_DDR_RD_RW_FAIL ++//#define DEBUG_DDR_RD_RW_PASS ++//#define DEBUG_DDR_CFG_DDR_SGMII_PHY ++//#define DEBUG_DDR_DDRCFG ++ ++/* ++#define LIBERO_SETTING_TRAINING_SKIP_SETTING 0x00000002UL ++ ++// set to 6 for DDR3/DDR4 ++#define SW_TRAING_BCLK_SCLK_OFFSET 0x00000006UL ++#define TEST_64BIT_ACCESS 0 ++ ++#define LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE 0x00000000UL ++#define LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE 0x00000000UL ++#define LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE 0x00000018UL //75.6%, Range 0, 60.6% Range 1 ++//#define DEBUG_DDR_INIT ++//#define DEBUG_DDR_RD_RW_FAIL ++ ++ ++#define LIBERO_SETTING_CFG_READ_TO_WRITE 0x0000000FUL ++#define LIBERO_SETTING_CFG_READ_TO_WRITE_ODT 0x0000000FUL ++#define LIBERO_SETTING_CFG_CCD_L 0x00000006UL ++#define LIBERO_SETTING_CFG_LOOKAHEAD_PCH 0x00000001UL ++#define LIBERO_SETTING_CFG_LOOKAHEAD_ACT 0x00000001UL ++*/ ++ ++/* ++ * SDIO register address location in fabric ++ */ ++/* ++ * We want the Kconfig-generated config.h file to get the SDIO Register Address, ++ * but it defines CONFIG_OPENSBI... ++ * ++ * OpenSBI type definitions conflict with mpfs_hal ++ * so we need to undefine CONFIG_OPENSBI after including config.h ++ */ ++#include "config.h" ++#undef CONFIG_OPENSBI ++ ++#ifdef CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS ++# undef LIBERO_SETTING_FPGA_SWITCH_ADDRESS ++# define LIBERO_SETTING_FPGA_SWITCH_ADDRESS CONFIG_SERVICE_MMC_FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS ++#else ++# ifndef LIBERO_SETTING_FPGA_SWITCH_ADDRESS ++# define LIBERO_SETTING_FPGA_SWITCH_ADDRESS 0x4fffff00 ++# endif ++#endif ++ ++#endif /* USER_CONFIG_MSS_USER_CONFIG_H_ */ ++ +diff -ruN A/boards/som1-soc/mpfs_hal_config/readme.txt B/boards/som1-soc/mpfs_hal_config/readme.txt +--- A/boards/som1-soc/mpfs_hal_config/readme.txt 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/mpfs_hal_config/readme.txt 2023-12-13 01:55:54.632290589 -0800 +@@ -0,0 +1,2 @@ ++contains user configuration of the platform ++e.g. division of memory between harts etc. +\ No newline at end of file +diff -ruN A/boards/som1-soc/soc_fpga_design/xml/som1-soc.cfg B/boards/som1-soc/soc_fpga_design/xml/som1-soc.cfg +--- A/boards/som1-soc/soc_fpga_design/xml/som1-soc.cfg 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/soc_fpga_design/xml/som1-soc.cfg 2023-12-28 08:05:17.952458209 -0800 +@@ -0,0 +1,1215 @@ ++BANK2_VOLTAGE 1.8 ++BANK4_VOLTAGE 1.8 ++BANK5_VOLTAGE 2.5 ++CAN_0 UNUSED ++CAN_0_TX_EBL_N UNUSED ++CAN_1 UNUSED ++CAN_1_TX_EBL_N UNUSED ++CAN_CLK_FREQ 80 ++CAN_CLK_SOURCE MSS_PLL ++CORE_UP UNUSED ++CRYPTO UNUSED ++CRYPTO_DLL_JITTER_TOLERANCE MEDIUM_LOW ++CRYPTO_ENABLE_ALARM false ++CRYPTO_ENABLE_BUSERROR false ++CRYPTO_ENABLE_BUSY true ++CRYPTO_ENABLE_COMPLETE false ++CRYPTO_ENABLE_DLL_LOCK true ++CRYPTO_ENABLE_MESH false ++CRYPTO_ENABLE_STREAMING false ++CRYPTO_MSS_CLK_FREQ 200 ++CRYPTO_USE_EMBEDDED_DLL true ++DDR3_ADDRESS_MIRROR false ++DDR3_ADDRESS_ORDERING CHIP_ROW_BANK_COL ++DDR3_ADVANCED_CA_TRAINING false ++DDR3_BANK_ADDR_WIDTH 3 ++DDR3_BURST_LENGTH 0 ++DDR3_CAS_ADDITIVE_LATENCY 0 ++DDR3_CAS_LATENCY 5 ++DDR3_CAS_WRITE_LATENCY 5 ++DDR3_CLOCK_DDR 666 ++DDR3_COL_ADDR_WIDTH 11 ++DDR3_CONTROLLER_ADD_CMD_DRIVE 34 ++DDR3_CONTROLLER_CLK_DRIVE 34 ++DDR3_CONTROLLER_DQS_DRIVE 34 ++DDR3_CONTROLLER_DQS_ODT 60 ++DDR3_CONTROLLER_DQ_DRIVE 34 ++DDR3_CONTROLLER_DQ_ODT 120 ++DDR3_DEGREE0 0 ++DDR3_DEGREE45 1 ++DDR3_DEGREE90 2 ++DDR3_DM_MODE DM ++DDR3_DQDQS_TRAINING_OFFSET 1 ++DDR3_ENABLE_ECC false ++DDR3_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false ++DDR3_MEMORY_FORMAT COMPONENT ++DDR3_NB_CLKS 1 ++DDR3_NB_RANKS 1 ++DDR3_NUMBER_OF_OFFSETS 4 ++DDR3_ODT_ENABLE_RD_RNK0_ODT0 false ++DDR3_ODT_ENABLE_RD_RNK0_ODT1 false ++DDR3_ODT_ENABLE_RD_RNK1_ODT0 false ++DDR3_ODT_ENABLE_RD_RNK1_ODT1 false ++DDR3_ODT_ENABLE_WR_RNK0_ODT0 false ++DDR3_ODT_ENABLE_WR_RNK0_ODT1 false ++DDR3_ODT_ENABLE_WR_RNK1_ODT0 false ++DDR3_ODT_ENABLE_WR_RNK1_ODT1 false ++DDR3_OFFSET0 0 ++DDR3_OFFSET1 1 ++DDR3_OFFSET2 2 ++DDR3_OFFSET3 3 ++DDR3_OUTPUT_DRIVE_STRENGTH RZQ6 ++DDR3_PARTIAL_ARRAY_SELF_REFRESH FULL ++DDR3_READ_BURST_TYPE SEQUENTIAL ++DDR3_ROW_ADDR_WIDTH 13 ++DDR3_RTT_NOM DISABLED ++DDR3_RTT_WR OFF ++DDR3_SELF_REFRESH_TEMPERATURE NORMAL ++DDR3_TIMING_FAW 40 ++DDR3_TIMING_RAS 35 ++DDR3_TIMING_RC 47.5 ++DDR3_TIMING_RCD 12.5 ++DDR3_TIMING_REFI 7.8 ++DDR3_TIMING_RFC 110 ++DDR3_TIMING_RP 12.5 ++DDR3_TIMING_RRD 6.25 ++DDR3_TIMING_RTP 8 ++DDR3_TIMING_WR 18 ++DDR3_TIMING_WTR 4 ++DDR3_WIDTH 32 ++DDR3_ZQ_CALIB_PERIOD 200 ++DDR3_ZQ_CALIB_TYPE 0 ++DDR3_ZQ_CAL_INIT_TIME 512 ++DDR3_ZQ_CAL_L_TIME 256 ++DDR3_ZQ_CAL_S_TIME 64 ++DDR4_ADDRESS_MIRROR false ++DDR4_ADDRESS_ORDERING CHIP_ROW_BG_BANK_COL ++DDR4_ADVANCED_CA_TRAINING false ++DDR4_AUTO_SELF_REFRESH 3 ++DDR4_BANK_ADDR_WIDTH 2 ++DDR4_BANK_GROUP_ADDRESS_WIDTH 1 ++DDR4_BURST_LENGTH 0 ++DDR4_CAS_ADDITIVE_LATENCY 0 ++DDR4_CAS_LATENCY 12 ++DDR4_CAS_WRITE_LATENCY 11 ++DDR4_CA_PARITY_LATENCY_MODE 0 ++DDR4_CLOCK_DDR 800.0 ++DDR4_COL_ADDR_WIDTH 10 ++DDR4_CONTROLLER_ADD_CMD_DRIVE 34 ++DDR4_CONTROLLER_CLK_DRIVE 48 ++DDR4_CONTROLLER_DQS_DRIVE 48 ++DDR4_CONTROLLER_DQS_ODT 120 ++DDR4_CONTROLLER_DQ_DRIVE 48 ++DDR4_CONTROLLER_DQ_ODT 120 ++DDR4_DEGREE0 0 ++DDR4_DEGREE45 1 ++DDR4_DEGREE90 2 ++DDR4_DM_MODE DM ++DDR4_DQDQS_TRAINING_OFFSET 1 ++DDR4_ENABLE_ECC false ++DDR4_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false ++DDR4_ENABLE_PAR_ALERT false ++DDR4_GRANULARITY_MODE 0 ++DDR4_INTERNAL_VREF_MONITER 0 ++DDR4_MEMORY_FORMAT COMPONENT ++DDR4_NB_CLKS 1 ++DDR4_NB_RANKS 1 ++DDR4_NUMBER_OF_OFFSETS 4 ++DDR4_ODT_ENABLE_RD_RNK0_ODT0 false ++DDR4_ODT_ENABLE_RD_RNK0_ODT1 false ++DDR4_ODT_ENABLE_RD_RNK1_ODT0 false ++DDR4_ODT_ENABLE_RD_RNK1_ODT1 false ++DDR4_ODT_ENABLE_WR_RNK0_ODT0 false ++DDR4_ODT_ENABLE_WR_RNK0_ODT1 false ++DDR4_ODT_ENABLE_WR_RNK1_ODT0 false ++DDR4_ODT_ENABLE_WR_RNK1_ODT1 false ++DDR4_OFFSET0 0 ++DDR4_OFFSET1 1 ++DDR4_OFFSET2 2 ++DDR4_OFFSET3 3 ++DDR4_OUTPUT_DRIVE_STRENGTH RZQ7 ++DDR4_POWERDOWN_INPUT_BUFFER 1 ++DDR4_READ_BURST_TYPE SEQUENTIAL ++DDR4_READ_PREAMBLE 0 ++DDR4_ROW_ADDR_WIDTH 17 ++DDR4_RTT_NOM RZQ6 ++DDR4_RTT_PARK 0 ++DDR4_RTT_WR OFF ++DDR4_SELF_REFRESH_ABORT_MODE 0 ++DDR4_TEMPERATURE_REFRESH_MODE 0 ++DDR4_TEMPERATURE_REFRESH_RANGE NORMAL ++DDR4_TIMING_CCD_L 5 ++DDR4_TIMING_CCD_S 4 ++DDR4_TIMING_FAW 35 ++DDR4_TIMING_RAS 34 ++DDR4_TIMING_RC 45.92 ++DDR4_TIMING_RCD 13.92 ++DDR4_TIMING_REFI 7.8 ++DDR4_TIMING_RFC 350 ++DDR4_TIMING_RP 13.92 ++DDR4_TIMING_RRD_L 6 ++DDR4_TIMING_RRD_S 5 ++DDR4_TIMING_RTP 7.5 ++DDR4_TIMING_WR 15 ++DDR4_TIMING_WTR_L 6 ++DDR4_TIMING_WTR_S 2 ++DDR4_VREF_CA 45 ++DDR4_VREF_CALIB_ENABLE 1 ++DDR4_VREF_CALIB_RANGE 1 ++DDR4_VREF_CALIB_VALUE 64.5 ++DDR4_VREF_DATA 65 ++DDR4_WIDTH 32 ++DDR4_WRITE_PREAMBLE 0 ++DDR4_ZQ_CALIB_PERIOD 200 ++DDR4_ZQ_CALIB_TYPE 0 ++DDR4_ZQ_CAL_INIT_TIME 1024 ++DDR4_ZQ_CAL_L_TIME 512 ++DDR4_ZQ_CAL_S_TIME 128 ++DDR_CACHED_32BIT_MEM_SIZE 768 ++DDR_CACHED_32BIT_MEM_UNIT MB ++DDR_CACHED_32BIT_PHY_OFFSET 0x0000_0000 ++DDR_CACHED_64BIT_MEM_SIZE 3 ++DDR_CACHED_64BIT_MEM_UNIT GB ++DDR_CACHED_64BIT_PHY_OFFSET 0x3000_0000 ++DDR_NON_CACHED_32BIT_MEM_SIZE 256 ++DDR_NON_CACHED_32BIT_MEM_UNIT MB ++DDR_NON_CACHED_32BIT_PHY_OFFSET 0xF000_0000 ++DDR_NON_CACHED_64BIT_MEM_SIZE 0 ++DDR_NON_CACHED_64BIT_MEM_UNIT GB ++DDR_NON_CACHED_64BIT_PHY_OFFSET 0x0000_0000 ++DDR_REFCLK DEDICATED_IO ++DDR_SDRAM_TYPE DDR4 ++DIE MPFS460T ++EMMC MSSIO_B4 ++EMMC_DATA_7_4 MSSIO_B4 ++EMMC_SD_CLK_SOURCE MSS_PLL ++EMMC_SD_SDIO_FREQ 200 ++EMMC_SD_SWITCHING DISABLED ++EMMC_SPEED_MODE DEFAULT_SPEED ++ENABLE_FEEDBACK_PORTS false ++EXPOSE_BOOT_STATUS_PORTS false ++FF_IN_PROGRESS UNUSED ++FIC_0_AXI4_INITIATOR_USED true ++FIC_0_AXI4_TARGET_USED false ++FIC_0_EMBEDDED_DLL_JITTER_RANGE LOW ++FIC_0_EMBEDDED_DLL_USED false ++FIC_1_AXI4_INITIATOR_USED false ++FIC_1_AXI4_TARGET_USED false ++FIC_1_EMBEDDED_DLL_JITTER_RANGE LOW ++FIC_1_EMBEDDED_DLL_USED false ++FIC_2_AXI4_TARGET_USED false ++FIC_2_EMBEDDED_DLL_JITTER_RANGE LOW ++FIC_2_EMBEDDED_DLL_USED false ++FIC_3_APB_INITIATOR_USED false ++FIC_3_EMBEDDED_DLL_JITTER_RANGE LOW ++FIC_3_EMBEDDED_DLL_USED false ++FLASH_VALID UNUSED ++FREQOUT UNUSED ++G5C_IOOUT UNUSED ++GPIO_0_0 UNUSED ++GPIO_0_0_7_RESET_SOURCE MSS ++GPIO_0_0_DIR IN ++GPIO_0_1 UNUSED ++GPIO_0_10 UNUSED ++GPIO_0_10_DIR IN ++GPIO_0_11 UNUSED ++GPIO_0_11_DIR IN ++GPIO_0_12 MSSIO_B4 ++GPIO_0_12_DIR OUT ++GPIO_0_13 MSSIO_B4 ++GPIO_0_13_DIR OUT ++GPIO_0_1_DIR IN ++GPIO_0_2 UNUSED ++GPIO_0_2_DIR IN ++GPIO_0_3 UNUSED ++GPIO_0_3_DIR IN ++GPIO_0_4 UNUSED ++GPIO_0_4_DIR IN ++GPIO_0_5 UNUSED ++GPIO_0_5_DIR IN ++GPIO_0_6 UNUSED ++GPIO_0_6_DIR IN ++GPIO_0_7 UNUSED ++GPIO_0_7_DIR IN ++GPIO_0_8 UNUSED ++GPIO_0_8_13_RESET_SOURCE MSS ++GPIO_0_8_DIR IN ++GPIO_0_9 UNUSED ++GPIO_0_9_DIR IN ++GPIO_1_0 UNUSED ++GPIO_1_0_7_RESET_SOURCE MSS ++GPIO_1_0_DIR IN ++GPIO_1_1 UNUSED ++GPIO_1_10 UNUSED ++GPIO_1_10_DIR IN ++GPIO_1_11 UNUSED ++GPIO_1_11_DIR IN ++GPIO_1_12 MSSIO_B2 ++GPIO_1_12_DIR BI ++GPIO_1_13 MSSIO_B2 ++GPIO_1_13_DIR BI ++GPIO_1_14 UNUSED ++GPIO_1_14_DIR IN ++GPIO_1_15 UNUSED ++GPIO_1_15_DIR IN ++GPIO_1_16 MSSIO_B2 ++GPIO_1_16_23_RESET_SOURCE MSS ++GPIO_1_16_DIR BI ++GPIO_1_17 MSSIO_B2 ++GPIO_1_17_DIR BI ++GPIO_1_18 MSSIO_B2 ++GPIO_1_18_DIR BI ++GPIO_1_19 MSSIO_B2 ++GPIO_1_19_DIR BI ++GPIO_1_1_DIR IN ++GPIO_1_2 UNUSED ++GPIO_1_20 MSSIO_B2 ++GPIO_1_20_DIR BI ++GPIO_1_21 UNUSED ++GPIO_1_21_DIR IN ++GPIO_1_22 UNUSED ++GPIO_1_22_DIR IN ++GPIO_1_23 MSSIO_B2 ++GPIO_1_23_DIR BI ++GPIO_1_2_DIR IN ++GPIO_1_3 UNUSED ++GPIO_1_3_DIR IN ++GPIO_1_4 UNUSED ++GPIO_1_4_DIR IN ++GPIO_1_5 UNUSED ++GPIO_1_5_DIR IN ++GPIO_1_6 UNUSED ++GPIO_1_6_DIR IN ++GPIO_1_7 UNUSED ++GPIO_1_7_DIR IN ++GPIO_1_8 UNUSED ++GPIO_1_8_15_RESET_SOURCE MSS ++GPIO_1_8_DIR IN ++GPIO_1_9 UNUSED ++GPIO_1_9_DIR IN ++GPIO_2_0 UNUSED ++GPIO_2_0_7_RESET_SOURCE MSS ++GPIO_2_0_DIR IN ++GPIO_2_1 UNUSED ++GPIO_2_10 UNUSED ++GPIO_2_10_DIR IN ++GPIO_2_11 UNUSED ++GPIO_2_11_DIR IN ++GPIO_2_12 UNUSED ++GPIO_2_12_DIR IN ++GPIO_2_13 UNUSED ++GPIO_2_13_DIR IN ++GPIO_2_14 UNUSED ++GPIO_2_14_DIR IN ++GPIO_2_15 UNUSED ++GPIO_2_15_DIR IN ++GPIO_2_16 UNUSED ++GPIO_2_16_23_RESET_SOURCE MSS ++GPIO_2_16_DIR IN ++GPIO_2_17 UNUSED ++GPIO_2_17_DIR IN ++GPIO_2_18 UNUSED ++GPIO_2_18_DIR IN ++GPIO_2_19 UNUSED ++GPIO_2_19_DIR IN ++GPIO_2_1_DIR IN ++GPIO_2_2 UNUSED ++GPIO_2_20 UNUSED ++GPIO_2_20_DIR IN ++GPIO_2_21 UNUSED ++GPIO_2_21_DIR IN ++GPIO_2_22 UNUSED ++GPIO_2_22_DIR IN ++GPIO_2_23 UNUSED ++GPIO_2_23_DIR IN ++GPIO_2_24 UNUSED ++GPIO_2_24_31_RESET_SOURCE MSS ++GPIO_2_24_DIR IN ++GPIO_2_25 UNUSED ++GPIO_2_25_DIR IN ++GPIO_2_26 UNUSED ++GPIO_2_26_DIR IN ++GPIO_2_27 UNUSED ++GPIO_2_27_DIR IN ++GPIO_2_28 UNUSED ++GPIO_2_28_DIR IN ++GPIO_2_29 UNUSED ++GPIO_2_29_DIR IN ++GPIO_2_2_DIR IN ++GPIO_2_3 UNUSED ++GPIO_2_30 UNUSED ++GPIO_2_30_DIR IN ++GPIO_2_31 UNUSED ++GPIO_2_31_DIR IN ++GPIO_2_3_DIR IN ++GPIO_2_4 UNUSED ++GPIO_2_4_DIR IN ++GPIO_2_5 UNUSED ++GPIO_2_5_DIR IN ++GPIO_2_6 UNUSED ++GPIO_2_6_DIR IN ++GPIO_2_7 UNUSED ++GPIO_2_7_DIR IN ++GPIO_2_8 UNUSED ++GPIO_2_8_15_RESET_SOURCE MSS ++GPIO_2_8_DIR IN ++GPIO_2_9 UNUSED ++GPIO_2_9_DIR IN ++GPIO_INTERRUPT_FAB_CR_DATA 0x00000000 ++I2C_0 UNUSED ++I2C_0_BAUD_RATE_CLOCK UNUSED ++I2C_0_SMBUS UNUSED ++I2C_0_SPEED_MODE STANDARD ++I2C_1 UNUSED ++I2C_1_BAUD_RATE_CLOCK UNUSED ++I2C_1_SMBUS UNUSED ++I2C_1_SPEED_MODE STANDARD ++INTERNAL_DEBUG false ++INTERRUPT false ++IO_REFCLK_FREQ 125 ++JTAG_TRACE false ++JTAG_TRACE_CONTROL_VIA_FABRIC false ++L2CACHE_DMA_WAY0 true ++L2CACHE_DMA_WAY1 true ++L2CACHE_DMA_WAY10 false ++L2CACHE_DMA_WAY11 false ++L2CACHE_DMA_WAY12 false ++L2CACHE_DMA_WAY13 false ++L2CACHE_DMA_WAY14 false ++L2CACHE_DMA_WAY15 false ++L2CACHE_DMA_WAY2 true ++L2CACHE_DMA_WAY3 true ++L2CACHE_DMA_WAY4 true ++L2CACHE_DMA_WAY5 true ++L2CACHE_DMA_WAY6 true ++L2CACHE_DMA_WAY7 true ++L2CACHE_DMA_WAY8 false ++L2CACHE_DMA_WAY9 false ++L2CACHE_E51_D_WAY0 true ++L2CACHE_E51_D_WAY1 true ++L2CACHE_E51_D_WAY10 false ++L2CACHE_E51_D_WAY11 false ++L2CACHE_E51_D_WAY12 false ++L2CACHE_E51_D_WAY13 false ++L2CACHE_E51_D_WAY14 false ++L2CACHE_E51_D_WAY15 false ++L2CACHE_E51_D_WAY2 true ++L2CACHE_E51_D_WAY3 true ++L2CACHE_E51_D_WAY4 true ++L2CACHE_E51_D_WAY5 true ++L2CACHE_E51_D_WAY6 true ++L2CACHE_E51_D_WAY7 true ++L2CACHE_E51_D_WAY8 false ++L2CACHE_E51_D_WAY9 false ++L2CACHE_E51_I_WAY0 true ++L2CACHE_E51_I_WAY1 true ++L2CACHE_E51_I_WAY10 false ++L2CACHE_E51_I_WAY11 false ++L2CACHE_E51_I_WAY12 false ++L2CACHE_E51_I_WAY13 false ++L2CACHE_E51_I_WAY14 false ++L2CACHE_E51_I_WAY15 false ++L2CACHE_E51_I_WAY2 true ++L2CACHE_E51_I_WAY3 true ++L2CACHE_E51_I_WAY4 true ++L2CACHE_E51_I_WAY5 true ++L2CACHE_E51_I_WAY6 true ++L2CACHE_E51_I_WAY7 true ++L2CACHE_E51_I_WAY8 false ++L2CACHE_E51_I_WAY9 false ++L2CACHE_LIM_SIZE 4 ++L2CACHE_PORT_0_WAY0 true ++L2CACHE_PORT_0_WAY1 true ++L2CACHE_PORT_0_WAY10 false ++L2CACHE_PORT_0_WAY11 false ++L2CACHE_PORT_0_WAY12 false ++L2CACHE_PORT_0_WAY13 false ++L2CACHE_PORT_0_WAY14 false ++L2CACHE_PORT_0_WAY15 false ++L2CACHE_PORT_0_WAY2 true ++L2CACHE_PORT_0_WAY3 true ++L2CACHE_PORT_0_WAY4 true ++L2CACHE_PORT_0_WAY5 true ++L2CACHE_PORT_0_WAY6 true ++L2CACHE_PORT_0_WAY7 true ++L2CACHE_PORT_0_WAY8 false ++L2CACHE_PORT_0_WAY9 false ++L2CACHE_PORT_1_WAY0 true ++L2CACHE_PORT_1_WAY1 true ++L2CACHE_PORT_1_WAY10 false ++L2CACHE_PORT_1_WAY11 false ++L2CACHE_PORT_1_WAY12 false ++L2CACHE_PORT_1_WAY13 false ++L2CACHE_PORT_1_WAY14 false ++L2CACHE_PORT_1_WAY15 false ++L2CACHE_PORT_1_WAY2 true ++L2CACHE_PORT_1_WAY3 true ++L2CACHE_PORT_1_WAY4 true ++L2CACHE_PORT_1_WAY5 true ++L2CACHE_PORT_1_WAY6 true ++L2CACHE_PORT_1_WAY7 true ++L2CACHE_PORT_1_WAY8 false ++L2CACHE_PORT_1_WAY9 false ++L2CACHE_PORT_2_WAY0 true ++L2CACHE_PORT_2_WAY1 true ++L2CACHE_PORT_2_WAY10 false ++L2CACHE_PORT_2_WAY11 false ++L2CACHE_PORT_2_WAY12 false ++L2CACHE_PORT_2_WAY13 false ++L2CACHE_PORT_2_WAY14 false ++L2CACHE_PORT_2_WAY15 false ++L2CACHE_PORT_2_WAY2 true ++L2CACHE_PORT_2_WAY3 true ++L2CACHE_PORT_2_WAY4 true ++L2CACHE_PORT_2_WAY5 true ++L2CACHE_PORT_2_WAY6 true ++L2CACHE_PORT_2_WAY7 true ++L2CACHE_PORT_2_WAY8 false ++L2CACHE_PORT_2_WAY9 false ++L2CACHE_PORT_3_WAY0 true ++L2CACHE_PORT_3_WAY1 true ++L2CACHE_PORT_3_WAY10 false ++L2CACHE_PORT_3_WAY11 false ++L2CACHE_PORT_3_WAY12 false ++L2CACHE_PORT_3_WAY13 false ++L2CACHE_PORT_3_WAY14 false ++L2CACHE_PORT_3_WAY15 false ++L2CACHE_PORT_3_WAY2 true ++L2CACHE_PORT_3_WAY3 true ++L2CACHE_PORT_3_WAY4 true ++L2CACHE_PORT_3_WAY5 true ++L2CACHE_PORT_3_WAY6 true ++L2CACHE_PORT_3_WAY7 true ++L2CACHE_PORT_3_WAY8 false ++L2CACHE_PORT_3_WAY9 false ++L2CACHE_SCRATCH_SIZE 4 ++L2CACHE_U54_1_D_WAY0 true ++L2CACHE_U54_1_D_WAY1 true ++L2CACHE_U54_1_D_WAY10 false ++L2CACHE_U54_1_D_WAY11 false ++L2CACHE_U54_1_D_WAY12 false ++L2CACHE_U54_1_D_WAY13 false ++L2CACHE_U54_1_D_WAY14 false ++L2CACHE_U54_1_D_WAY15 false ++L2CACHE_U54_1_D_WAY2 true ++L2CACHE_U54_1_D_WAY3 true ++L2CACHE_U54_1_D_WAY4 true ++L2CACHE_U54_1_D_WAY5 true ++L2CACHE_U54_1_D_WAY6 true ++L2CACHE_U54_1_D_WAY7 true ++L2CACHE_U54_1_D_WAY8 false ++L2CACHE_U54_1_D_WAY9 false ++L2CACHE_U54_1_I_WAY0 true ++L2CACHE_U54_1_I_WAY1 true ++L2CACHE_U54_1_I_WAY10 false ++L2CACHE_U54_1_I_WAY11 false ++L2CACHE_U54_1_I_WAY12 false ++L2CACHE_U54_1_I_WAY13 false ++L2CACHE_U54_1_I_WAY14 false ++L2CACHE_U54_1_I_WAY15 false ++L2CACHE_U54_1_I_WAY2 true ++L2CACHE_U54_1_I_WAY3 true ++L2CACHE_U54_1_I_WAY4 true ++L2CACHE_U54_1_I_WAY5 true ++L2CACHE_U54_1_I_WAY6 true ++L2CACHE_U54_1_I_WAY7 true ++L2CACHE_U54_1_I_WAY8 false ++L2CACHE_U54_1_I_WAY9 false ++L2CACHE_U54_2_D_WAY0 true ++L2CACHE_U54_2_D_WAY1 true ++L2CACHE_U54_2_D_WAY10 false ++L2CACHE_U54_2_D_WAY11 false ++L2CACHE_U54_2_D_WAY12 false ++L2CACHE_U54_2_D_WAY13 false ++L2CACHE_U54_2_D_WAY14 false ++L2CACHE_U54_2_D_WAY15 false ++L2CACHE_U54_2_D_WAY2 true ++L2CACHE_U54_2_D_WAY3 true ++L2CACHE_U54_2_D_WAY4 true ++L2CACHE_U54_2_D_WAY5 true ++L2CACHE_U54_2_D_WAY6 true ++L2CACHE_U54_2_D_WAY7 true ++L2CACHE_U54_2_D_WAY8 false ++L2CACHE_U54_2_D_WAY9 false ++L2CACHE_U54_2_I_WAY0 true ++L2CACHE_U54_2_I_WAY1 true ++L2CACHE_U54_2_I_WAY10 false ++L2CACHE_U54_2_I_WAY11 false ++L2CACHE_U54_2_I_WAY12 false ++L2CACHE_U54_2_I_WAY13 false ++L2CACHE_U54_2_I_WAY14 false ++L2CACHE_U54_2_I_WAY15 false ++L2CACHE_U54_2_I_WAY2 true ++L2CACHE_U54_2_I_WAY3 true ++L2CACHE_U54_2_I_WAY4 true ++L2CACHE_U54_2_I_WAY5 true ++L2CACHE_U54_2_I_WAY6 true ++L2CACHE_U54_2_I_WAY7 true ++L2CACHE_U54_2_I_WAY8 false ++L2CACHE_U54_2_I_WAY9 false ++L2CACHE_U54_3_D_WAY0 true ++L2CACHE_U54_3_D_WAY1 true ++L2CACHE_U54_3_D_WAY10 false ++L2CACHE_U54_3_D_WAY11 false ++L2CACHE_U54_3_D_WAY12 false ++L2CACHE_U54_3_D_WAY13 false ++L2CACHE_U54_3_D_WAY14 false ++L2CACHE_U54_3_D_WAY15 false ++L2CACHE_U54_3_D_WAY2 true ++L2CACHE_U54_3_D_WAY3 true ++L2CACHE_U54_3_D_WAY4 true ++L2CACHE_U54_3_D_WAY5 true ++L2CACHE_U54_3_D_WAY6 true ++L2CACHE_U54_3_D_WAY7 true ++L2CACHE_U54_3_D_WAY8 false ++L2CACHE_U54_3_D_WAY9 false ++L2CACHE_U54_3_I_WAY0 true ++L2CACHE_U54_3_I_WAY1 true ++L2CACHE_U54_3_I_WAY10 false ++L2CACHE_U54_3_I_WAY11 false ++L2CACHE_U54_3_I_WAY12 false ++L2CACHE_U54_3_I_WAY13 false ++L2CACHE_U54_3_I_WAY14 false ++L2CACHE_U54_3_I_WAY15 false ++L2CACHE_U54_3_I_WAY2 true ++L2CACHE_U54_3_I_WAY3 true ++L2CACHE_U54_3_I_WAY4 true ++L2CACHE_U54_3_I_WAY5 true ++L2CACHE_U54_3_I_WAY6 true ++L2CACHE_U54_3_I_WAY7 true ++L2CACHE_U54_3_I_WAY8 false ++L2CACHE_U54_3_I_WAY9 false ++L2CACHE_U54_4_D_WAY0 true ++L2CACHE_U54_4_D_WAY1 true ++L2CACHE_U54_4_D_WAY10 false ++L2CACHE_U54_4_D_WAY11 false ++L2CACHE_U54_4_D_WAY12 false ++L2CACHE_U54_4_D_WAY13 false ++L2CACHE_U54_4_D_WAY14 false ++L2CACHE_U54_4_D_WAY15 false ++L2CACHE_U54_4_D_WAY2 true ++L2CACHE_U54_4_D_WAY3 true ++L2CACHE_U54_4_D_WAY4 true ++L2CACHE_U54_4_D_WAY5 true ++L2CACHE_U54_4_D_WAY6 true ++L2CACHE_U54_4_D_WAY7 true ++L2CACHE_U54_4_D_WAY8 false ++L2CACHE_U54_4_D_WAY9 false ++L2CACHE_U54_4_I_WAY0 true ++L2CACHE_U54_4_I_WAY1 true ++L2CACHE_U54_4_I_WAY10 false ++L2CACHE_U54_4_I_WAY11 false ++L2CACHE_U54_4_I_WAY12 false ++L2CACHE_U54_4_I_WAY13 false ++L2CACHE_U54_4_I_WAY14 false ++L2CACHE_U54_4_I_WAY15 false ++L2CACHE_U54_4_I_WAY2 true ++L2CACHE_U54_4_I_WAY3 true ++L2CACHE_U54_4_I_WAY4 true ++L2CACHE_U54_4_I_WAY5 true ++L2CACHE_U54_4_I_WAY6 true ++L2CACHE_U54_4_I_WAY7 true ++L2CACHE_U54_4_I_WAY8 false ++L2CACHE_U54_4_I_WAY9 false ++LOCK_DOWN_B2_IOS false ++LOCK_DOWN_B4_IOS false ++LOCK_DOWN_DDR_IOS false ++LOCK_DOWN_SGMII_IOS false ++LPDDR3_ADDRESS_ORDERING CHIP_ROW_BANK_COL ++LPDDR3_ADVANCED_CA_TRAINING false ++LPDDR3_BANK_ADDR_WIDTH 3 ++LPDDR3_CLK_DISABLE_IN_SELF_REFRESH false ++LPDDR3_CLOCK_DDR 666 ++LPDDR3_COL_ADDR_WIDTH 11 ++LPDDR3_CONTROLLER_ADD_CMD_DRIVE 40 ++LPDDR3_CONTROLLER_CLK_DRIVE 48 ++LPDDR3_CONTROLLER_DQS_DRIVE 48 ++LPDDR3_CONTROLLER_DQS_ODT 120 ++LPDDR3_CONTROLLER_DQ_DRIVE 48 ++LPDDR3_CONTROLLER_DQ_ODT 120 ++LPDDR3_DATA_LATENCY RL10WL6 ++LPDDR3_DEGREE0 0 ++LPDDR3_DEGREE45 1 ++LPDDR3_DEGREE90 2 ++LPDDR3_DM_MODE DM ++LPDDR3_DQDQS_TRAINING_OFFSET 1 ++LPDDR3_DQ_ODT DISABLE ++LPDDR3_ENABLE_DDR_SELF_REFRESH false ++LPDDR3_ENABLE_ECC false ++LPDDR3_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false ++LPDDR3_IDLE_TIME_TO_SELF_REFRESH 0 ++LPDDR3_MEMORY_FORMAT COMPONENT ++LPDDR3_NUMBER_OF_OFFSETS 4 ++LPDDR3_ODT_ENABLE_RD_RNK0_ODT0 false ++LPDDR3_ODT_ENABLE_WR_RNK0_ODT0 false ++LPDDR3_OFFSET0 0 ++LPDDR3_OFFSET1 1 ++LPDDR3_OFFSET2 2 ++LPDDR3_OFFSET3 3 ++LPDDR3_OUTPUT_DRIVE_STRENGTH PDPU34P3 ++LPDDR3_POWERDOWN_ODT 0 ++LPDDR3_ROW_ADDR_WIDTH 14 ++LPDDR3_TIMING_FAW 50 ++LPDDR3_TIMING_MRR 4 ++LPDDR3_TIMING_MRW 10 ++LPDDR3_TIMING_RAS 42 ++LPDDR3_TIMING_RC 57 ++LPDDR3_TIMING_RCD 15 ++LPDDR3_TIMING_REFI 3.9 ++LPDDR3_TIMING_RFC 130 ++LPDDR3_TIMING_RP 15 ++LPDDR3_TIMING_RRD 10 ++LPDDR3_TIMING_RTP 8 ++LPDDR3_TIMING_WR 18 ++LPDDR3_TIMING_WTR 4 ++LPDDR3_WIDTH 32 ++LPDDR3_ZQ_CALIB_PERIOD 200 ++LPDDR3_ZQ_CALIB_TYPE 0 ++LPDDR3_ZQ_CAL_INIT_TIME 1 ++LPDDR3_ZQ_CAL_L_TIME 360 ++LPDDR3_ZQ_CAL_R_TIME 50 ++LPDDR3_ZQ_CAL_S_TIME 90 ++LPDDR4_ADDRESS_ORDERING CHIP_ROW_BANK_COL ++LPDDR4_ADVANCED_CA_TRAINING false ++LPDDR4_BANK_ADDR_WIDTH 3 ++LPDDR4_CA_ODT RZQ4 ++LPDDR4_CLK_DISABLE_IN_SELF_REFRESH false ++LPDDR4_CLOCK_DDR 800 ++LPDDR4_COL_ADDR_WIDTH 10 ++LPDDR4_CONTROLLER_ADD_CMD_DRIVE 34 ++LPDDR4_CONTROLLER_CLK_DRIVE 34 ++LPDDR4_CONTROLLER_DQS_DRIVE 40 ++LPDDR4_CONTROLLER_DQS_ODT 40 ++LPDDR4_CONTROLLER_DQ_DRIVE 40 ++LPDDR4_CONTROLLER_DQ_ODT 40 ++LPDDR4_DEGREE0 0 ++LPDDR4_DEGREE45 1 ++LPDDR4_DEGREE90 2 ++LPDDR4_DM_MODE DM ++LPDDR4_DQDQS_TRAINING_OFFSET 1 ++LPDDR4_DQ_ODT RZQ2 ++LPDDR4_DRIVE_STRENGTH RZQ6 ++LPDDR4_ENABLE_DDR_SELF_REFRESH false ++LPDDR4_ENABLE_ECC false ++LPDDR4_ENABLE_LOOKAHEAD_PRECHARGE_ACTIVATE false ++LPDDR4_IDLE_TIME_TO_SELF_REFRESH 0 ++LPDDR4_MEMORY_FORMAT COMPONENT ++LPDDR4_NUMBER_OF_OFFSETS 4 ++LPDDR4_ODTE_CA 0 ++LPDDR4_ODTE_CK 0 ++LPDDR4_ODTE_CS 0 ++LPDDR4_OFFSET0 0 ++LPDDR4_OFFSET1 1 ++LPDDR4_OFFSET2 2 ++LPDDR4_OFFSET3 3 ++LPDDR4_PULLUP_CAL VDDQ3 ++LPDDR4_RD_POSTAMBLE CK0P5 ++LPDDR4_RD_PREAMBLE STATIC ++LPDDR4_READ_LATENCY RL14 ++LPDDR4_ROW_ADDR_WIDTH 16 ++LPDDR4_SELF_REFRESH_ABORT_MODE 0 ++LPDDR4_SOC_ODT RZQ6 ++LPDDR4_TIMING_FAW 40 ++LPDDR4_TIMING_MRR 8 ++LPDDR4_TIMING_MRW 10 ++LPDDR4_TIMING_RAS 42 ++LPDDR4_TIMING_RC 63 ++LPDDR4_TIMING_RCD 18 ++LPDDR4_TIMING_REFI 3.905 ++LPDDR4_TIMING_RFC 380 ++LPDDR4_TIMING_RP 21 ++LPDDR4_TIMING_RRD 10 ++LPDDR4_TIMING_RTP 10 ++LPDDR4_TIMING_WR 18 ++LPDDR4_TIMING_WTR 8 ++LPDDR4_VREF_CA 50 ++LPDDR4_VREF_CALIB_ENABLE 1 ++LPDDR4_VREF_CALIB_RANGE 1 ++LPDDR4_VREF_CALIB_VALUE 31.2 ++LPDDR4_VREF_DATA 15 ++LPDDR4_WIDTH 32 ++LPDDR4_WRITE_LATENCY WL8 ++LPDDR4_WR_POSTAMBLE CK0P5 ++LPDDR4_ZQ_CALIB_PERIOD 200 ++LPDDR4_ZQ_CAL_LATCH_TIME 30 ++LPDDR4_ZQ_CAL_R_TIME 50 ++LPDDR4_ZQ_CAL_TIME 1 ++LP_STATE UNUSED ++M2F_MONITOR UNUSED ++MAC_0 SGMII_IO_B5 ++MAC_0_MANAGEMENT FABRIC ++MAC_0_OTHER UNUSED ++MAC_0_TSU UNUSED ++MAC_1 SGMII_IO_B5 ++MAC_1_MANAGEMENT FABRIC ++MAC_1_OTHER UNUSED ++MAC_1_TSU UNUSED ++MAC_SGMII_REFCLK DEDICATED_IO ++MAC_TSU_REFCLK DEDICATED_IO ++MMUART_0 MSSIO_B2_B ++MMUART_0_MODE ASYNCHRONOUS ++MMUART_0_MODEM UNUSED ++MMUART_0_OTHER UNUSED ++MMUART_1 UNUSED ++MMUART_1_MODE ASYNCHRONOUS ++MMUART_1_MODEM UNUSED ++MMUART_1_OTHER UNUSED ++MMUART_2 UNUSED ++MMUART_3 UNUSED ++MMUART_4 UNUSED ++MODULE_NAME se301_som1_soc_mss ++MSSIO_0_ATP_EN false ++MSSIO_0_CLAMP_DIODE false ++MSSIO_0_LPMD_IBUF false ++MSSIO_0_LPMD_OBUF false ++MSSIO_0_LP_PERSIST false ++MSSIO_0_MD_IBUF true ++MSSIO_0_OUT_DRIVE 8 ++MSSIO_0_RES_PULL UP ++MSSIO_0_SCHMITT_TRIGGER false ++MSSIO_10_ATP_EN false ++MSSIO_10_CLAMP_DIODE false ++MSSIO_10_LPMD_IBUF false ++MSSIO_10_LPMD_OBUF false ++MSSIO_10_LP_PERSIST false ++MSSIO_10_MD_IBUF true ++MSSIO_10_OUT_DRIVE 8 ++MSSIO_10_RES_PULL UP ++MSSIO_10_SCHMITT_TRIGGER false ++MSSIO_11_ATP_EN false ++MSSIO_11_CLAMP_DIODE false ++MSSIO_11_LPMD_IBUF false ++MSSIO_11_LPMD_OBUF false ++MSSIO_11_LP_PERSIST false ++MSSIO_11_MD_IBUF true ++MSSIO_11_OUT_DRIVE 8 ++MSSIO_11_RES_PULL UP ++MSSIO_11_SCHMITT_TRIGGER false ++MSSIO_12_ATP_EN false ++MSSIO_12_CLAMP_DIODE false ++MSSIO_12_LPMD_IBUF false ++MSSIO_12_LPMD_OBUF false ++MSSIO_12_LP_PERSIST false ++MSSIO_12_MD_IBUF true ++MSSIO_12_OUT_DRIVE 8 ++MSSIO_12_RES_PULL UP ++MSSIO_12_SCHMITT_TRIGGER false ++MSSIO_13_ATP_EN false ++MSSIO_13_CLAMP_DIODE false ++MSSIO_13_LPMD_IBUF false ++MSSIO_13_LPMD_OBUF false ++MSSIO_13_LP_PERSIST false ++MSSIO_13_MD_IBUF true ++MSSIO_13_OUT_DRIVE 8 ++MSSIO_13_RES_PULL UP ++MSSIO_13_SCHMITT_TRIGGER false ++MSSIO_14_ATP_EN false ++MSSIO_14_CLAMP_DIODE false ++MSSIO_14_LPMD_IBUF false ++MSSIO_14_LPMD_OBUF false ++MSSIO_14_LP_PERSIST false ++MSSIO_14_MD_IBUF true ++MSSIO_14_OUT_DRIVE 8 ++MSSIO_14_RES_PULL UP ++MSSIO_14_SCHMITT_TRIGGER false ++MSSIO_15_ATP_EN false ++MSSIO_15_CLAMP_DIODE false ++MSSIO_15_LPMD_IBUF false ++MSSIO_15_LPMD_OBUF false ++MSSIO_15_LP_PERSIST false ++MSSIO_15_MD_IBUF true ++MSSIO_15_OUT_DRIVE 8 ++MSSIO_15_RES_PULL UP ++MSSIO_15_SCHMITT_TRIGGER false ++MSSIO_16_ATP_EN false ++MSSIO_16_CLAMP_DIODE false ++MSSIO_16_LPMD_IBUF false ++MSSIO_16_LPMD_OBUF false ++MSSIO_16_LP_PERSIST false ++MSSIO_16_MD_IBUF true ++MSSIO_16_OUT_DRIVE 8 ++MSSIO_16_RES_PULL UP ++MSSIO_16_SCHMITT_TRIGGER false ++MSSIO_17_ATP_EN false ++MSSIO_17_CLAMP_DIODE false ++MSSIO_17_LPMD_IBUF false ++MSSIO_17_LPMD_OBUF false ++MSSIO_17_LP_PERSIST false ++MSSIO_17_MD_IBUF true ++MSSIO_17_OUT_DRIVE 8 ++MSSIO_17_RES_PULL UP ++MSSIO_17_SCHMITT_TRIGGER false ++MSSIO_18_ATP_EN false ++MSSIO_18_CLAMP_DIODE false ++MSSIO_18_LPMD_IBUF false ++MSSIO_18_LPMD_OBUF false ++MSSIO_18_LP_PERSIST false ++MSSIO_18_MD_IBUF true ++MSSIO_18_OUT_DRIVE 8 ++MSSIO_18_RES_PULL UP ++MSSIO_18_SCHMITT_TRIGGER false ++MSSIO_19_ATP_EN false ++MSSIO_19_CLAMP_DIODE false ++MSSIO_19_LPMD_IBUF false ++MSSIO_19_LPMD_OBUF false ++MSSIO_19_LP_PERSIST false ++MSSIO_19_MD_IBUF true ++MSSIO_19_OUT_DRIVE 8 ++MSSIO_19_RES_PULL UP ++MSSIO_19_SCHMITT_TRIGGER false ++MSSIO_1_ATP_EN false ++MSSIO_1_CLAMP_DIODE false ++MSSIO_1_LPMD_IBUF false ++MSSIO_1_LPMD_OBUF false ++MSSIO_1_LP_PERSIST false ++MSSIO_1_MD_IBUF true ++MSSIO_1_OUT_DRIVE 8 ++MSSIO_1_RES_PULL UP ++MSSIO_1_SCHMITT_TRIGGER false ++MSSIO_20_ATP_EN false ++MSSIO_20_CLAMP_DIODE false ++MSSIO_20_LPMD_IBUF false ++MSSIO_20_LPMD_OBUF false ++MSSIO_20_LP_PERSIST false ++MSSIO_20_MD_IBUF true ++MSSIO_20_OUT_DRIVE 8 ++MSSIO_20_RES_PULL UP ++MSSIO_20_SCHMITT_TRIGGER false ++MSSIO_21_ATP_EN false ++MSSIO_21_CLAMP_DIODE false ++MSSIO_21_LPMD_IBUF false ++MSSIO_21_LPMD_OBUF false ++MSSIO_21_LP_PERSIST false ++MSSIO_21_MD_IBUF true ++MSSIO_21_OUT_DRIVE 8 ++MSSIO_21_RES_PULL UP ++MSSIO_21_SCHMITT_TRIGGER false ++MSSIO_22_ATP_EN false ++MSSIO_22_CLAMP_DIODE false ++MSSIO_22_LPMD_IBUF false ++MSSIO_22_LPMD_OBUF false ++MSSIO_22_LP_PERSIST false ++MSSIO_22_MD_IBUF true ++MSSIO_22_OUT_DRIVE 8 ++MSSIO_22_RES_PULL UP ++MSSIO_22_SCHMITT_TRIGGER false ++MSSIO_23_ATP_EN false ++MSSIO_23_CLAMP_DIODE false ++MSSIO_23_LPMD_IBUF false ++MSSIO_23_LPMD_OBUF false ++MSSIO_23_LP_PERSIST false ++MSSIO_23_MD_IBUF true ++MSSIO_23_OUT_DRIVE 8 ++MSSIO_23_RES_PULL UP ++MSSIO_23_SCHMITT_TRIGGER false ++MSSIO_24_ATP_EN false ++MSSIO_24_CLAMP_DIODE false ++MSSIO_24_LPMD_IBUF false ++MSSIO_24_LPMD_OBUF false ++MSSIO_24_LP_PERSIST false ++MSSIO_24_MD_IBUF true ++MSSIO_24_OUT_DRIVE 8 ++MSSIO_24_RES_PULL UP ++MSSIO_24_SCHMITT_TRIGGER false ++MSSIO_25_ATP_EN false ++MSSIO_25_CLAMP_DIODE false ++MSSIO_25_LPMD_IBUF false ++MSSIO_25_LPMD_OBUF false ++MSSIO_25_LP_PERSIST false ++MSSIO_25_MD_IBUF true ++MSSIO_25_OUT_DRIVE 8 ++MSSIO_25_RES_PULL UP ++MSSIO_25_SCHMITT_TRIGGER false ++MSSIO_26_ATP_EN false ++MSSIO_26_CLAMP_DIODE false ++MSSIO_26_LPMD_IBUF false ++MSSIO_26_LPMD_OBUF false ++MSSIO_26_LP_PERSIST false ++MSSIO_26_MD_IBUF true ++MSSIO_26_OUT_DRIVE 8 ++MSSIO_26_RES_PULL UP ++MSSIO_26_SCHMITT_TRIGGER false ++MSSIO_27_ATP_EN false ++MSSIO_27_CLAMP_DIODE false ++MSSIO_27_LPMD_IBUF false ++MSSIO_27_LPMD_OBUF false ++MSSIO_27_LP_PERSIST false ++MSSIO_27_MD_IBUF true ++MSSIO_27_OUT_DRIVE 8 ++MSSIO_27_RES_PULL UP ++MSSIO_27_SCHMITT_TRIGGER false ++MSSIO_28_ATP_EN false ++MSSIO_28_CLAMP_DIODE false ++MSSIO_28_LPMD_IBUF false ++MSSIO_28_LPMD_OBUF false ++MSSIO_28_LP_PERSIST false ++MSSIO_28_MD_IBUF true ++MSSIO_28_OUT_DRIVE 8 ++MSSIO_28_RES_PULL UP ++MSSIO_28_SCHMITT_TRIGGER false ++MSSIO_29_ATP_EN false ++MSSIO_29_CLAMP_DIODE false ++MSSIO_29_LPMD_IBUF false ++MSSIO_29_LPMD_OBUF false ++MSSIO_29_LP_PERSIST false ++MSSIO_29_MD_IBUF true ++MSSIO_29_OUT_DRIVE 8 ++MSSIO_29_RES_PULL UP ++MSSIO_29_SCHMITT_TRIGGER false ++MSSIO_2_ATP_EN false ++MSSIO_2_CLAMP_DIODE false ++MSSIO_2_LPMD_IBUF false ++MSSIO_2_LPMD_OBUF false ++MSSIO_2_LP_PERSIST false ++MSSIO_2_MD_IBUF true ++MSSIO_2_OUT_DRIVE 8 ++MSSIO_2_RES_PULL UP ++MSSIO_2_SCHMITT_TRIGGER false ++MSSIO_30_ATP_EN false ++MSSIO_30_CLAMP_DIODE false ++MSSIO_30_LPMD_IBUF false ++MSSIO_30_LPMD_OBUF false ++MSSIO_30_LP_PERSIST false ++MSSIO_30_MD_IBUF true ++MSSIO_30_OUT_DRIVE 8 ++MSSIO_30_RES_PULL UP ++MSSIO_30_SCHMITT_TRIGGER false ++MSSIO_31_ATP_EN false ++MSSIO_31_CLAMP_DIODE false ++MSSIO_31_LPMD_IBUF false ++MSSIO_31_LPMD_OBUF false ++MSSIO_31_LP_PERSIST false ++MSSIO_31_MD_IBUF true ++MSSIO_31_OUT_DRIVE 8 ++MSSIO_31_RES_PULL UP ++MSSIO_31_SCHMITT_TRIGGER false ++MSSIO_32_ATP_EN false ++MSSIO_32_CLAMP_DIODE false ++MSSIO_32_LPMD_IBUF false ++MSSIO_32_LPMD_OBUF false ++MSSIO_32_LP_PERSIST false ++MSSIO_32_MD_IBUF true ++MSSIO_32_OUT_DRIVE 8 ++MSSIO_32_RES_PULL UP ++MSSIO_32_SCHMITT_TRIGGER false ++MSSIO_33_ATP_EN false ++MSSIO_33_CLAMP_DIODE false ++MSSIO_33_LPMD_IBUF false ++MSSIO_33_LPMD_OBUF false ++MSSIO_33_LP_PERSIST false ++MSSIO_33_MD_IBUF true ++MSSIO_33_OUT_DRIVE 8 ++MSSIO_33_RES_PULL UP ++MSSIO_33_SCHMITT_TRIGGER false ++MSSIO_34_ATP_EN false ++MSSIO_34_CLAMP_DIODE false ++MSSIO_34_LPMD_IBUF false ++MSSIO_34_LPMD_OBUF false ++MSSIO_34_LP_PERSIST false ++MSSIO_34_MD_IBUF true ++MSSIO_34_OUT_DRIVE 8 ++MSSIO_34_RES_PULL UP ++MSSIO_34_SCHMITT_TRIGGER false ++MSSIO_35_ATP_EN false ++MSSIO_35_CLAMP_DIODE false ++MSSIO_35_LPMD_IBUF false ++MSSIO_35_LPMD_OBUF false ++MSSIO_35_LP_PERSIST false ++MSSIO_35_MD_IBUF true ++MSSIO_35_OUT_DRIVE 8 ++MSSIO_35_RES_PULL UP ++MSSIO_35_SCHMITT_TRIGGER false ++MSSIO_36_ATP_EN false ++MSSIO_36_CLAMP_DIODE false ++MSSIO_36_LPMD_IBUF false ++MSSIO_36_LPMD_OBUF false ++MSSIO_36_LP_PERSIST false ++MSSIO_36_MD_IBUF true ++MSSIO_36_OUT_DRIVE 8 ++MSSIO_36_RES_PULL UP ++MSSIO_36_SCHMITT_TRIGGER false ++MSSIO_37_ATP_EN false ++MSSIO_37_CLAMP_DIODE false ++MSSIO_37_LPMD_IBUF false ++MSSIO_37_LPMD_OBUF false ++MSSIO_37_LP_PERSIST false ++MSSIO_37_MD_IBUF true ++MSSIO_37_OUT_DRIVE 8 ++MSSIO_37_RES_PULL UP ++MSSIO_37_SCHMITT_TRIGGER false ++MSSIO_3_ATP_EN false ++MSSIO_3_CLAMP_DIODE false ++MSSIO_3_LPMD_IBUF false ++MSSIO_3_LPMD_OBUF false ++MSSIO_3_LP_PERSIST false ++MSSIO_3_MD_IBUF true ++MSSIO_3_OUT_DRIVE 8 ++MSSIO_3_RES_PULL UP ++MSSIO_3_SCHMITT_TRIGGER false ++MSSIO_4_ATP_EN false ++MSSIO_4_CLAMP_DIODE false ++MSSIO_4_LPMD_IBUF false ++MSSIO_4_LPMD_OBUF false ++MSSIO_4_LP_PERSIST false ++MSSIO_4_MD_IBUF true ++MSSIO_4_OUT_DRIVE 8 ++MSSIO_4_RES_PULL UP ++MSSIO_4_SCHMITT_TRIGGER false ++MSSIO_5_ATP_EN false ++MSSIO_5_CLAMP_DIODE false ++MSSIO_5_LPMD_IBUF false ++MSSIO_5_LPMD_OBUF false ++MSSIO_5_LP_PERSIST false ++MSSIO_5_MD_IBUF true ++MSSIO_5_OUT_DRIVE 8 ++MSSIO_5_RES_PULL UP ++MSSIO_5_SCHMITT_TRIGGER false ++MSSIO_6_ATP_EN false ++MSSIO_6_CLAMP_DIODE false ++MSSIO_6_LPMD_IBUF false ++MSSIO_6_LPMD_OBUF false ++MSSIO_6_LP_PERSIST false ++MSSIO_6_MD_IBUF true ++MSSIO_6_OUT_DRIVE 8 ++MSSIO_6_RES_PULL UP ++MSSIO_6_SCHMITT_TRIGGER false ++MSSIO_7_ATP_EN false ++MSSIO_7_CLAMP_DIODE false ++MSSIO_7_LPMD_IBUF false ++MSSIO_7_LPMD_OBUF false ++MSSIO_7_LP_PERSIST false ++MSSIO_7_MD_IBUF true ++MSSIO_7_OUT_DRIVE 8 ++MSSIO_7_RES_PULL UP ++MSSIO_7_SCHMITT_TRIGGER false ++MSSIO_8_ATP_EN false ++MSSIO_8_CLAMP_DIODE false ++MSSIO_8_LPMD_IBUF false ++MSSIO_8_LPMD_OBUF false ++MSSIO_8_LP_PERSIST false ++MSSIO_8_MD_IBUF true ++MSSIO_8_OUT_DRIVE 8 ++MSSIO_8_RES_PULL UP ++MSSIO_8_SCHMITT_TRIGGER false ++MSSIO_9_ATP_EN false ++MSSIO_9_CLAMP_DIODE false ++MSSIO_9_LPMD_IBUF false ++MSSIO_9_LPMD_OBUF false ++MSSIO_9_LP_PERSIST false ++MSSIO_9_MD_IBUF true ++MSSIO_9_OUT_DRIVE 8 ++MSSIO_9_RES_PULL UP ++MSSIO_9_SCHMITT_TRIGGER false ++MSSIO_REFCLK_IOSTD LVDS25 ++MSSIO_REFCLK_ODT 100 ++MSSIO_REFCLK_PULL_UP false ++MSSIO_REFCLK_SCHMITT_TRIGGER false ++MSSIO_REFCLK_THEVENIN OFF ++MSS_AHB_APB_CLK_DIV 4 ++MSS_AXI_CLK_DIV 2 ++MSS_CLK_DIV 1 ++MSS_MANUAL_DDR_PHY_OFFSET_ENABLE false ++MSS_PLLOUT_FREQ 600.000 ++MSS_PMP_ENABLE false ++MSS_REFCLK DEDICATED_IO ++PACKAGE FCG1152_Eval ++PFSOC_MSS_VERSION 2023.2 ++PLL_NW_REFCLK0_FREQ 100 ++PLL_NW_REFCLK1_FREQ 125 ++PMP_CAN0_CONTEXT_A_EN true ++PMP_CAN0_CONTEXT_B_EN false ++PMP_CAN1_CONTEXT_A_EN false ++PMP_CAN1_CONTEXT_B_EN true ++PMP_CRYPTO_CFG_CONTEXT_A_EN true ++PMP_CRYPTO_CFG_CONTEXT_B_EN false ++PMP_CRYPTO_MEM_CONTEXT_A_EN true ++PMP_CRYPTO_MEM_CONTEXT_B_EN false ++PMP_EMMC_CONTEXT_A_EN true ++PMP_EMMC_CONTEXT_B_EN false ++PMP_GEM0_CONTEXT_A_EN true ++PMP_GEM0_CONTEXT_B_EN false ++PMP_GEM1_CONTEXT_A_EN false ++PMP_GEM1_CONTEXT_B_EN true ++PMP_GPIO0_CONTEXT_A_EN true ++PMP_GPIO0_CONTEXT_B_EN false ++PMP_GPIO1_CONTEXT_A_EN false ++PMP_GPIO1_CONTEXT_B_EN true ++PMP_GPIO2_CONTEXT_A_EN true ++PMP_GPIO2_CONTEXT_B_EN false ++PMP_I2C0_CONTEXT_A_EN true ++PMP_I2C0_CONTEXT_B_EN false ++PMP_I2C1_CONTEXT_A_EN false ++PMP_I2C1_CONTEXT_B_EN true ++PMP_INITIATOR_U54_1_CONTEXT_A_EN true ++PMP_INITIATOR_U54_1_CONTEXT_B_EN false ++PMP_INITIATOR_U54_2_CONTEXT_A_EN true ++PMP_INITIATOR_U54_2_CONTEXT_B_EN false ++PMP_INITIATOR_U54_3_CONTEXT_A_EN false ++PMP_INITIATOR_U54_3_CONTEXT_B_EN true ++PMP_INITIATOR_U54_4_CONTEXT_A_EN false ++PMP_INITIATOR_U54_4_CONTEXT_B_EN true ++PMP_MMUART1_CONTEXT_A_EN true ++PMP_MMUART1_CONTEXT_B_EN false ++PMP_MMUART2_CONTEXT_A_EN true ++PMP_MMUART2_CONTEXT_B_EN false ++PMP_MMUART3_CONTEXT_A_EN false ++PMP_MMUART3_CONTEXT_B_EN true ++PMP_MMUART4_CONTEXT_A_EN false ++PMP_MMUART4_CONTEXT_B_EN true ++PMP_QSPI_CONTEXT_A_EN true ++PMP_QSPI_CONTEXT_B_EN false ++PMP_RTC_CONTEXT_A_EN true ++PMP_RTC_CONTEXT_B_EN false ++PMP_SPI0_CONTEXT_A_EN true ++PMP_SPI0_CONTEXT_B_EN false ++PMP_SPI1_CONTEXT_A_EN false ++PMP_SPI1_CONTEXT_B_EN true ++PMP_USB_CONTEXT_A_EN true ++PMP_USB_CONTEXT_B_EN false ++QSPI UNUSED ++QSPI_CLK UNUSED ++QSPI_DATA_3_2 UNUSED ++SD UNUSED ++SD_CLE UNUSED ++SD_LED UNUSED ++SD_LED_IS_INVERTED false ++SD_PORTS_DISABLE false ++SD_SDIO_SPEED_MODE DEFAULT_SPEED ++SD_VOLT_0 UNUSED ++SD_VOLT_0_IS_INVERTED false ++SD_VOLT_1 UNUSED ++SD_VOLT_1_IS_INVERTED false ++SD_VOLT_2 UNUSED ++SD_VOLT_2_IS_INVERTED false ++SD_VOLT_CMD_DIR_IS_INVERTED false ++SD_VOLT_DIR_0_IS_INVERTED false ++SD_VOLT_DIR_1_3_IS_INVERTED false ++SD_VOLT_EN_IS_INVERTED false ++SD_VOLT_PORTS UNUSED ++SD_VOLT_SEL_IS_INVERTED false ++SGMII_RX0_IOSTD LVDS25 ++SGMII_RX0_ODT 100 ++SGMII_RX0_PULLMODE NONE ++SGMII_RX0_VCM_RANGE MID ++SGMII_RX1_IOSTD LVDS25 ++SGMII_RX1_ODT 100 ++SGMII_RX1_PULLMODE NONE ++SGMII_RX1_VCM_RANGE MID ++SGMII_TX0_IOSTD LVDS25 ++SGMII_TX0_OUT_DRIVE 6 ++SGMII_TX0_PULLMODE NONE ++SGMII_TX0_SOURCE_TERM 100 ++SGMII_TX1_IOSTD LVDS25 ++SGMII_TX1_OUT_DRIVE 6 ++SGMII_TX1_PULLMODE NONE ++SGMII_TX1_SOURCE_TERM 100 ++SPEED -1 ++SPI_0 UNUSED ++SPI_0_SPEED_MODE MASTER ++SPI_0_SS1 UNUSED ++SPI_1 UNUSED ++SPI_1_SPEED_MODE MASTER ++SPI_1_SS1 UNUSED ++USB MSSIO_B2 ++USOC_DEBUG_TRACE false ++WD_RESETN UNUSED +diff -ruN A/boards/som1-soc/soc_fpga_design/xml/som1-soc.xml B/boards/som1-soc/soc_fpga_design/xml/som1-soc.xml +--- A/boards/som1-soc/soc_fpga_design/xml/som1-soc.xml 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/soc_fpga_design/xml/som1-soc.xml 2023-12-28 08:05:17.952458209 -0800 +@@ -0,0 +1,4327 @@ ++ ++ ++ 2023.2 ++ se301_som1_soc_mss ++ MPFS460T ++ FCG1152_Eval ++ 11-29-2023_12:37:38 ++ 0.6.8 ++ ++ ++ ++ ++ 0x20220000 ++ 0x20220000 ++ 0x20220000 ++ 0x20220000 ++ 0x20220000 ++ 0x80000000 ++ 0xC0000000 ++ 0x1000000000 ++ 0x1400000000 ++ 0xD0000000 ++ 0x1800000000 ++ 0x00000000 ++ 0x00000000 ++ ++ ++ ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0xB ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x4 ++ ++ ++ ++ ++ ++ ++ 0x00 ++ 0x0 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ ++ ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ ++ ++ ++ ++ 0x9F ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0xFFFFFFFFFFFFFFFF ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x9F ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0xFFFFFFFFFFFFFFFF ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x9F ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0xFFFFFFFFFFFFFFFF ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x9F ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0xFFFFFFFFFFFFFFFF ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ 0xFFFFFFFFF ++ 0x0 ++ 0x1F ++ ++ ++ ++ ++ ++ ++ 0 ++ ++ ++ 220 ++ ++ ++ 0 ++ ++ ++ 511 ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0xB ++ 0xB ++ ++ ++ 0x4 ++ 0x4 ++ 0x4 ++ 0x4 ++ 0x4 ++ 0x4 ++ 0x4 ++ 0x4 ++ ++ ++ 0x4 ++ 0x4 ++ 0x4 ++ 0x4 ++ 0xB ++ 0xB ++ 0x5 ++ 0x5 ++ ++ ++ 0xB ++ 0xB ++ 0xB ++ 0xB ++ 0xB ++ 0xF ++ 0xF ++ 0xB ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0xD ++ 0x00 ++ 0xA ++ 0x0 ++ 0x4 ++ 0x0 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0xD ++ 0x00 ++ 0xA ++ 0x0 ++ 0x4 ++ 0x0 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0xD ++ 0x00 ++ 0xA ++ 0x0 ++ 0x4 ++ 0x0 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0xD ++ 0x00 ++ 0xA ++ 0x0 ++ 0x4 ++ 0x0 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0928 ++ 0x0928 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x2 ++ 0xC ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0x7 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ ++ ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x14 ++ 0x0 ++ 0x2 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x7 ++ 0x7 ++ 0x7 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x4 ++ 0x7 ++ 0x7 ++ 0x3 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x7 ++ 0x7 ++ 0x7 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x4 ++ 0x7 ++ 0x7 ++ 0x3 ++ 0x0 ++ ++ ++ 0x8 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x2 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x3 ++ 0x0 ++ 0x3 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0xf000 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x0 ++ ++ ++ 0xFF000000 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x1 ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x3 ++ 0x0 ++ 0x0 ++ 0x7F ++ 0x1F ++ ++ ++ 0x02 ++ ++ ++ 3 ++ ++ ++ 3 ++ ++ ++ 4 ++ ++ ++ 3 ++ ++ ++ 1 ++ ++ ++ 1 ++ ++ ++ 1 ++ ++ ++ 4 ++ ++ ++ 2 ++ ++ ++ 3 ++ ++ ++ 0 ++ ++ ++ 1 ++ ++ ++ 7 ++ ++ ++ 0 ++ ++ ++ 0 ++ ++ ++ 1 ++ ++ ++ 0 ++ ++ ++ 0 ++ ++ ++ 7 ++ ++ ++ 6 ++ ++ ++ 5 ++ ++ ++ 0 ++ ++ ++ 7 ++ ++ ++ 0 ++ ++ ++ 1 ++ ++ ++ 2 ++ ++ ++ 3 ++ ++ ++ 4 ++ ++ ++ 2 ++ ++ ++ 5 ++ ++ ++ 1 ++ ++ ++ 2 ++ ++ ++ 3 ++ ++ ++ 2 ++ ++ ++ 1 ++ ++ ++ 2 ++ ++ ++ 3 ++ ++ ++ 2 ++ ++ ++ 0 ++ ++ ++ 1 ++ ++ ++ 6 ++ ++ ++ 7 ++ ++ ++ 0 ++ ++ ++ 1 ++ ++ ++ 6 ++ ++ ++ 0 ++ ++ ++ 2 ++ ++ ++ 1 ++ ++ ++ 3 ++ ++ ++ 0 ++ ++ ++ 0 ++ ++ ++ 0 ++ ++ ++ 0x0 ++ ++ ++ 0 ++ ++ ++ 0 ++ ++ ++ 1 ++ ++ ++ 1 ++ ++ ++ 0x1 ++ ++ ++ 1 ++ ++ ++ 1 ++ ++ ++ 2 ++ ++ ++ 2 ++ ++ ++ 0x2 ++ ++ ++ 2 ++ ++ ++ 2 ++ ++ ++ ++ ++ ++ ++ 0x3 ++ 0x16 ++ 0x1 ++ 0x0 ++ 0xE ++ 0x1 ++ 0x0 ++ 0x0 ++ ++ ++ 0x2 ++ ++ ++ 0x2 ++ ++ ++ 0x2 ++ ++ ++ 0x2 ++ ++ ++ 0x6 ++ ++ ++ 0x6 ++ ++ ++ 0x7 ++ ++ ++ 0x7 ++ ++ ++ 0x7 ++ ++ ++ 0x3 ++ ++ ++ 0x4 ++ ++ ++ 0x3 ++ ++ ++ 0x4 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ ++ ++ 0x1 ++ ++ ++ ++ ++ ++ ++ 0x2 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x4 ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x7F80 ++ 0x0 ++ 0x1 ++ ++ ++ 0x7030 ++ 0x0 ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x30 ++ 0x0 ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ 0x1 ++ ++ ++ 0x20 ++ 0x0 ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ 0x1 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000004 ++ ++ ++ 0x0000000A ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000140 ++ ++ ++ 0x000000A0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000001 ++ ++ ++ 0xC ++ ++ ++ 0xC ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x1 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x4 ++ ++ ++ 0x5 ++ ++ ++ 0x1 ++ ++ ++ 0x1 ++ ++ ++ 0x1E ++ ++ ++ 0x5 ++ ++ ++ 0x6 ++ ++ ++ 0x2 ++ ++ ++ 0x6 ++ ++ ++ 0x7 ++ ++ ++ 0xB ++ ++ ++ 0x11 ++ ++ ++ 0x118 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x81881881 ++ ++ ++ 0x00008818 ++ ++ ++ 0xa92a92a9 ++ ++ ++ 0x00002a92 ++ ++ ++ 0xc28c28c2 ++ ++ ++ 0x00008c28 ++ ++ ++ 0xea2ea2ea ++ ++ ++ 0x00002ea2 ++ ++ ++ 0x03903903 ++ ++ ++ 0x00009039 ++ ++ ++ 0x2b32b32b ++ ++ ++ 0x000032b3 ++ ++ ++ 0x44944944 ++ ++ ++ 0x00009449 ++ ++ ++ 0x6c36c36c ++ ++ ++ 0x000036c3 ++ ++ ++ 0x85985985 ++ ++ ++ 0x00009859 ++ ++ ++ 0xad3ad3ad ++ ++ ++ 0x00003ad3 ++ ++ ++ 0xc69c69c6 ++ ++ ++ 0x00009c69 ++ ++ ++ 0xee3ee3ee ++ ++ ++ 0x00003ee3 ++ ++ ++ 0x07a07a07 ++ ++ ++ 0x0000a07a ++ ++ ++ 0x2f42f42f ++ ++ ++ 0x000042f4 ++ ++ ++ 0x48a48a48 ++ ++ ++ 0x0000a48a ++ ++ ++ 0x70470470 ++ ++ ++ 0x00004704 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x1 ++ ++ ++ 0x1C ++ ++ ++ 0xC ++ ++ ++ 0x00000007 ++ ++ ++ 0xC ++ ++ ++ 0x25 ++ ++ ++ 0x1C ++ ++ ++ 0x00000076 ++ ++ ++ 0x6 ++ ++ ++ 0xC ++ ++ ++ 0x00000008 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000003 ++ ++ ++ 0x00000024 ++ ++ ++ 0xC ++ ++ ++ 0xF ++ ++ ++ 0x2 ++ ++ ++ 0x2 ++ ++ ++ 0x1 ++ ++ ++ 0xF ++ ++ ++ 0x2 ++ ++ ++ 0x2 ++ ++ ++ 0x1 ++ ++ ++ 0x7 ++ ++ ++ 0x00000010 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x3 ++ ++ ++ 0x0 ++ ++ ++ 0x1860 ++ ++ ++ 0x27100 ++ ++ ++ 0xA ++ ++ ++ 0x11 ++ ++ ++ 0x3 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00 ++ ++ ++ 0x00 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ ++ ++ 0x18 ++ ++ ++ 0x120 ++ ++ ++ 0x00000200 ++ ++ ++ 0x120 ++ ++ ++ 0x0 ++ ++ ++ 0xB ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x3 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x27100 ++ ++ ++ 0x0 ++ ++ ++ 0x80 ++ ++ ++ 0x0 ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x000029B0 ++ ++ ++ 0x400 ++ ++ ++ 0x200 ++ ++ ++ 0x80 ++ ++ ++ 0x0000000b ++ ++ ++ 0x00000002 ++ ++ ++ 0x00000010 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000009 ++ ++ ++ 0x0000000C ++ ++ ++ 0x0 ++ ++ ++ 0x1 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000001 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000030 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000640 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000008 ++ ++ ++ 0x0000000b ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x1 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000001 ++ ++ ++ 0x00000001 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000001 ++ ++ ++ 0x000000FF ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x1 ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x14 ++ ++ ++ 0x6 ++ ++ ++ 0x1 ++ ++ ++ 0x00000001 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0xFFFFFFFF ++ ++ ++ 0x0 ++ ++ ++ 0xFFFFFFFF ++ ++ ++ 0x0 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x8001 ++ ++ ++ 0x1 ++ ++ ++ 0x1 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x2F ++ ++ ++ 0x3F ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ 0x18 ++ ++ ++ 0x00000000 ++ ++ ++ 0x1 ++ ++ ++ 0x00000000 ++ ++ ++ 0x00000000 ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x1 ++ ++ ++ 125000000 ++ ++ ++ 600000000 ++ ++ ++ 600000000 ++ ++ ++ 1000000 ++ ++ ++ 300000000 ++ ++ ++ 150000000 ++ ++ ++ 1600000000 ++ ++ ++ ++ ++ ++ ++ 0x1 ++ ++ ++ 0x0 ++ 0x1 ++ 0x2 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x7D ++ ++ ++ 0x5 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x40 ++ ++ ++ ++ ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x5 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x3 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x8 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x6 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0xd ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x8 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x60 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x8 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x6 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0xd ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x2 ++ 0x4 ++ 0x6 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x14 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ DDR3 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x5 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x2 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x8 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x6 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0xd ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x2 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x80 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x8 ++ 0x10 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ ++ ++ 0x3 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ 0x1 ++ 0x1 ++ 0x0 ++ ++ ++ 0x5 ++ ++ ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x3 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x3 ++ 0x0 ++ 0x1 ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ ++ ++ ++ ++ ++ ++ 0x3 ++ 0x0 ++ 0x7 ++ 0x0 ++ 0xF ++ 0x0 ++ ++ ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ ++ ++ 0x1 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x0 ++ 0x1 ++ 0x1 ++ 0x0 ++ ++ ++ ++ ++ +diff -ruN A/boards/som1-soc/uart_device_list.c B/boards/som1-soc/uart_device_list.c +--- A/boards/som1-soc/uart_device_list.c 1969-12-31 16:00:00.000000000 -0800 ++++ B/boards/som1-soc/uart_device_list.c 2023-12-13 01:55:54.636290603 -0800 +@@ -0,0 +1,61 @@ ++/******************************************************************************* ++ * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions. ++ * ++ * SPDX-License-Identifier: MIT ++ * ++ * Allow overrides (per board) of default UART ports ++ */ ++ ++#include "config.h" ++#include "hss_types.h" ++ ++#include ++ ++#include "hss_debug.h" ++ ++#include "drivers/mss/mss_mmuart/mss_uart.h" ++#include ++#include ++ ++#include "hss_boot_init.h" ++#include "uart_helper.h" ++ ++extern mss_uart_instance_t * const pUartDeviceList[]; ++ ++void *HSS_UART_GetInstance(int hartid) ++{ ++ mss_uart_instance_t *pUart; ++ const bool postBoot = HSS_BootInit_IsPostInit(); ++ ++ switch (hartid) { ++ default: ++ pUart = pUartDeviceList[0]; ++ break; ++ ++ case HSS_HART_E51: ++ if (postBoot) { ++ pUart = pUartDeviceList[CONFIG_UART_POST_BOOT]; ++ } else { ++ pUart = pUartDeviceList[0]; ++ } ++ break; ++ ++ case HSS_HART_U54_1: ++ pUart = pUartDeviceList[1]; ++ break; ++ ++ case HSS_HART_U54_2: ++ pUart = pUartDeviceList[2]; ++ break; ++ ++ case HSS_HART_U54_3: ++ pUart = pUartDeviceList[3]; ++ break; ++ ++ case HSS_HART_U54_4: ++ pUart = pUartDeviceList[4]; ++ break; ++ } ++ ++ return pUart; ++} diff --git a/package/hart-software-services/002-ETHERNET-PHY-RESET.patch b/package/hart-software-services/002-ETHERNET-PHY-RESET.patch new file mode 100644 index 00000000..299619b7 --- /dev/null +++ b/package/hart-software-services/002-ETHERNET-PHY-RESET.patch @@ -0,0 +1,25 @@ +diff -ruN a/boards/som1-soc/hss_board_init.c b/boards/som1-soc/hss_board_init.c +--- a/boards/som1-soc/hss_board_init.c 2024-01-10 04:21:31.283722794 -0800 ++++ b/boards/som1-soc/hss_board_init.c 2024-01-10 04:08:02.513198414 -0800 +@@ -23,6 +23,8 @@ + #include "ssmb_ipi.h" + #include "hss_registry.h" + ++#include "mss_gpio.h" ++ + #ifndef __IO + # define __IO volatile + #endif +@@ -79,6 +81,12 @@ + + bool HSS_BoardLateInit(void) + { ++ mHSS_PUTS("Clear (set to HIGH\1) Ethernet PHY RESET: GPIO0_LO, PIN13\n"); ++ ++ MSS_GPIO_init(GPIO0_LO); ++ MSS_GPIO_config(GPIO0_LO, MSS_GPIO_13, MSS_GPIO_OUTPUT_MODE); ++ MSS_GPIO_set_outputs(GPIO0_LO, MSS_GPIO_13_MASK); ++ + return true; + } + diff --git a/package/hart-software-services/Config.in b/package/hart-software-services/Config.in new file mode 100644 index 00000000..fcd849fc --- /dev/null +++ b/package/hart-software-services/Config.in @@ -0,0 +1,27 @@ +config BR2_PACKAGE_HART_SOFTWARE_SERVICES + bool "HSS (Hart-Software-Services) Microsemi First Stage Bootloader" + help + Microchip Hart Software Services package for PolarFire SOC. + +if BR2_PACKAGE_HART_SOFTWARE_SERVICES + +config BR2_PACKAGE_HART_SOFTWARE_SERVICES_CONFIG + string "Path to the HSS config file" + help + Set here the PATH to the HSS config file + +config BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD + string "Name of the board" + help + Set here name of the board you have + +config BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE + string "DIE Setting" + help + Set here the CHIP setting + +config BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE + string "PACKAGE Setting" + help + Set here PACKAGE setting +endif diff --git a/package/hart-software-services/hart-software-services.mk b/package/hart-software-services/hart-software-services.mk new file mode 100644 index 00000000..895fa91f --- /dev/null +++ b/package/hart-software-services/hart-software-services.mk @@ -0,0 +1,16 @@ +################################################################################ +# +# hart-software-services +# +################################################################################ +HART_SOFTWARE_SERVICES_VERSION = next +HART_SOFTWARE_SERVICES_SITE = $(call github,polarfire-soc,hart-software-services,$(HART_SOFTWARE_SERVICES_VERSION)) +HART_SOFTWARE_SERVICES_LICENSE = MIT +HART_SOFTWARE_SERVICES_LICENSE_FILES = LICENSE.md + +define HART_SOFTWARE_SERVICES_BUILD_CMDS + cp $(@D)/$(subst ",,$(BR2_PACKAGE_HART_SOFTWARE_SERVICES_CONFIG)) $(@D)/.config + $(MAKE) -C $(@D) BOARD=$(subst ",,$(BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD)) CROSS_COMPILE=$(TARGET_CROSS) V=3 DIE=$(subst ",,$(BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE)) PACKAGE=$(subst ",,$(BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE)) +endef + +$(eval $(generic-package))