Skip to content

Commit 00ca4b1

Browse files
committed
Avoid more multple inheritance
1 parent 56bc80d commit 00ca4b1

File tree

1 file changed

+5
-4
lines changed

1 file changed

+5
-4
lines changed

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -908,9 +908,10 @@ def memri34_pcrel : Operand<iPTR> { // memri, imm is a 34-bit value.
908908
def PPCRegGxRCOperand : AsmOperandClass {
909909
let Name = "RegGxRC"; let PredicateMethod = "isRegNumber";
910910
}
911-
def ptr_rc_idx : Operand<iPTR>,
912-
RegClassByHwMode<[PPC32, PPC64],
913-
[GPRC, G8RC]> {
911+
def ptr_rc_idx : RegClassByHwMode<[PPC32, PPC64],
912+
[GPRC, G8RC]>;
913+
914+
def PtrRCIdxOp : RegisterOperand<ptr_rc_idx> {
914915
let ParserMatchClass = PPCRegGxRCOperand;
915916
}
916917

@@ -985,7 +986,7 @@ def memri : Operand<iPTR> {
985986
}
986987
def memrr : Operand<iPTR> {
987988
let PrintMethod = "printMemRegReg";
988-
let MIOperandInfo = (ops PtrOpNoR0:$ptrreg, ptr_rc_idx:$offreg);
989+
let MIOperandInfo = (ops PtrOpNoR0:$ptrreg, PtrRCIdxOp:$offreg);
989990
let OperandType = "OPERAND_MEMORY";
990991
}
991992
def memrix : Operand<iPTR> { // memri where the imm is 4-aligned.

0 commit comments

Comments
 (0)