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1 parent 7fb2b4d commit 019d67fCopy full SHA for 019d67f
llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -169,7 +169,7 @@ class RISCVSImmOp<int bitsNum> : RISCVOp {
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let OperandType = "OPERAND_SIMM" # bitsNum;
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}
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-class RISCVSImmLeafOp<int bitsNum > :
+class RISCVSImmLeafOp<int bitsNum> :
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RISCVSImmOp<bitsNum>, ImmLeaf<XLenVT, "return isInt<" # bitsNum # ">(Imm);">;
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def FenceArg : AsmOperandClass {
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