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[AMDGPU][AsmParser] Simplify the implementation of SWZ operands.
Those are implicit helper operands and therefore don't need any parsers or printers. Part of <#62629>. Reviewed By: piotr, foad Differential Revision: https://reviews.llvm.org/D154432
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6 files changed

+11
-22
lines changed

6 files changed

+11
-22
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,8 @@ def FMA : Predicate<"Subtarget->hasFMA()">;
123123

124124
def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
125125

126+
def i1imm_0 : OperandWithDefaultOps<i1, (ops (i1 0))>;
127+
126128
class CustomOperandClass<string name, bit optional, string parserMethod,
127129
string defaultMethod>
128130
: AsmOperandClass {

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
121121
ImmTyOffset1,
122122
ImmTySMEMOffsetMod,
123123
ImmTyCPol,
124-
ImmTySWZ,
125124
ImmTyTFE,
126125
ImmTyD16,
127126
ImmTyClampSI,
@@ -378,7 +377,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
378377
bool isGDS() const { return isImmTy(ImmTyGDS); }
379378
bool isLDS() const { return isImmTy(ImmTyLDS); }
380379
bool isCPol() const { return isImmTy(ImmTyCPol); }
381-
bool isSWZ() const { return isImmTy(ImmTySWZ); }
382380
bool isTFE() const { return isImmTy(ImmTyTFE); }
383381
bool isD16() const { return isImmTy(ImmTyD16); }
384382
bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }
@@ -1009,7 +1007,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
10091007
case ImmTyOffset1: OS << "Offset1"; break;
10101008
case ImmTySMEMOffsetMod: OS << "SMEMOffsetMod"; break;
10111009
case ImmTyCPol: OS << "CPol"; break;
1012-
case ImmTySWZ: OS << "SWZ"; break;
10131010
case ImmTyTFE: OS << "TFE"; break;
10141011
case ImmTyD16: OS << "D16"; break;
10151012
case ImmTyFORMAT: OS << "FORMAT"; break;
@@ -7650,7 +7647,6 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
76507647

76517648
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
76527649
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
7653-
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySWZ);
76547650
}
76557651

76567652
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/BUFInstructions.td

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -157,7 +157,7 @@ class getMTBUFInsDA<list<RegisterClass> vdataList,
157157
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
158158
RegisterOperand vdata_op = getLdStRegisterOperand<vdataClass>.ret;
159159

160-
dag NonVaddrInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol, SWZ:$swz);
160+
dag NonVaddrInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol, i1imm:$swz);
161161
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
162162
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
163163
}
@@ -185,7 +185,7 @@ class getMTBUFAsmOps<int addrKind> {
185185
!if(!eq(addrKind, BUFAddrKind.Addr64),
186186
"$vaddr, $srsrc,$format $soffset addr64",
187187
"")))));
188-
string ret = " $vdata, " # Pfx # "$offset$cpol$swz";
188+
string ret = " $vdata, " # Pfx # "$offset$cpol";
189189
}
190190

191191
class MTBUF_SetupAddr<int addrKind> {
@@ -386,7 +386,7 @@ class getMUBUFInsDA<list<RegisterClass> vdataList,
386386
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
387387
RegisterOperand vdata_op = getLdStVDataRegisterOperand<vdataClass, isTFE>.ret;
388388

389-
dag NonVaddrInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol, SWZ_0:$swz);
389+
dag NonVaddrInputs = (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol_0:$cpol, i1imm_0:$swz);
390390
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddrClass:$vaddr), NonVaddrInputs));
391391
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
392392
}
@@ -420,7 +420,7 @@ class getMUBUFIns<int addrKind, list<RegisterClass> vdataList, bit isTFE> {
420420
(ins))))));
421421
}
422422

423-
class getMUBUFAsmOps<int addrKind, bit noVdata = 0, bit isLds = 0, bit isTFE = 0, bit isSwz = 0> {
423+
class getMUBUFAsmOps<int addrKind, bit noVdata = 0, bit isLds = 0, bit isTFE = 0> {
424424
string Vdata = !if(noVdata, " ", " $vdata, ");
425425
string Lds = !if(isLds, " lds", "");
426426
string TFE = !if(isTFE, " tfe", "");
@@ -433,9 +433,8 @@ class getMUBUFAsmOps<int addrKind, bit noVdata = 0, bit isLds = 0, bit isTFE = 0
433433
"")))));
434434
string Offset = "$offset";
435435
string OtherArgs = "$cpol";
436-
string Swz = !if(isSwz, "$swz", "");
437436

438-
string ret = Vdata # MainArgs # Offset # OtherArgs # Lds # TFE # Swz;
437+
string ret = Vdata # MainArgs # Offset # OtherArgs # Lds # TFE;
439438
}
440439

441440
class MUBUF_SetupAddr<int addrKind> {
@@ -466,7 +465,7 @@ class MUBUF_Load_Pseudo <string opName,
466465
!if(!or(isLds, isLdsOpc), (outs), (outs vdata_op:$vdata)),
467466
!con(getMUBUFIns<addrKindCopy, [], isTFE>.ret,
468467
!if(HasTiedDest, (ins vdata_op:$vdata_in), (ins))),
469-
getMUBUFAsmOps<addrKindCopy, !or(isLds, isLdsOpc), isLds, isTFE, 1>.ret,
468+
getMUBUFAsmOps<addrKindCopy, !or(isLds, isLdsOpc), isLds, isTFE>.ret,
470469
pattern>,
471470
MUBUF_SetupAddr<addrKindCopy> {
472471
let PseudoInstr = opName # !if(isLds, "_lds", "") # !if(isTFE, "_tfe", "") #
@@ -561,7 +560,7 @@ class MUBUF_Store_Pseudo <string opName,
561560
: MUBUF_Pseudo<opName,
562561
(outs),
563562
getMUBUFIns<addrKindCopy, [getVregSrcForVT<store_vt>.ret], isTFE>.ret,
564-
getMUBUFAsmOps<addrKindCopy, 0, 0, isTFE, 1>.ret,
563+
getMUBUFAsmOps<addrKindCopy, 0, 0, isTFE>.ret,
565564
pattern>,
566565
MUBUF_SetupAddr<addrKindCopy> {
567566
let PseudoInstr = opName # "_" # !if(isTFE, "_tfe", "") #
@@ -608,8 +607,8 @@ multiclass MUBUF_Pseudo_Stores<string opName, ValueType store_vt = i32,
608607
class MUBUF_Pseudo_Store_Lds<string opName>
609608
: MUBUF_Pseudo<opName,
610609
(outs),
611-
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, SWZ:$swz),
612-
" $srsrc, $soffset$offset lds$cpol$swz"> {
610+
(ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, i1imm:$swz),
611+
" $srsrc, $soffset$offset lds$cpol"> {
613612
let LGKM_CNT = 1;
614613
let mayLoad = 1;
615614
let mayStore = 1;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -208,10 +208,6 @@ void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
208208
O << " /* unexpected cache policy bit */";
209209
}
210210

211-
void AMDGPUInstPrinter::printSWZ(const MCInst *MI, unsigned OpNo,
212-
const MCSubtargetInfo &STI, raw_ostream &O) {
213-
}
214-
215211
void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
216212
const MCSubtargetInfo &STI, raw_ostream &O) {
217213
printNamedBit(MI, OpNo, O, "tfe");

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -71,8 +71,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
7171
raw_ostream &O);
7272
void printCPol(const MCInst *MI, unsigned OpNo,
7373
const MCSubtargetInfo &STI, raw_ostream &O);
74-
void printSWZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
75-
raw_ostream &O);
7674
void printTFE(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
7775
raw_ostream &O);
7876
void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1094,8 +1094,6 @@ def CPol_0 : DefaultOperand<CPol, 0>;
10941094
def CPol_GLC1 : DefaultOperand<CPol, 1>;
10951095

10961096
def TFE : NamedBitOperand<"tfe">;
1097-
def SWZ : NamedBitOperand<"swz">;
1098-
def SWZ_0 : DefaultOperand<SWZ, 0>;
10991097
def UNorm : NamedBitOperand<"unorm">;
11001098
def DA : NamedBitOperand<"da">;
11011099
def R128A16 : CustomOperand<i1, 1>;

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