@@ -1374,27 +1374,6 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
1374
1374
MachineInstr &NewMI = *std::prev (MII);
1375
1375
NewMI.setDebugLoc (DL);
1376
1376
1377
- // In a situation like the following:
1378
- //
1379
- // undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
1380
- // ; DefSubIdx = subreg
1381
- // %3:reg = COPY %2 ; SrcIdx = DstIdx = 0
1382
- // .... = SOMEINSTR %3:reg
1383
- //
1384
- // there are no subranges for %3 so after rematerialization we need
1385
- // to explicitly create them. Undefined subranges are removed later on.
1386
- if (DstReg.isVirtual () && DefSubIdx && !CP.getSrcIdx () && !CP.getDstIdx () &&
1387
- MRI->shouldTrackSubRegLiveness (DstReg)) {
1388
- LiveInterval &DstInt = LIS->getInterval (DstReg);
1389
- if (!DstInt.hasSubRanges ()) {
1390
- LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg (DstReg);
1391
- LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask (DefSubIdx);
1392
- LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1393
- DstInt.createSubRangeFrom (LIS->getVNInfoAllocator (), UsedLanes, DstInt);
1394
- DstInt.createSubRangeFrom (LIS->getVNInfoAllocator (), UnusedLanes, DstInt);
1395
- }
1396
- }
1397
-
1398
1377
// In a situation like the following:
1399
1378
// %0:subreg = instr ; DefMI, subreg = DstIdx
1400
1379
// %1 = copy %0:subreg ; CopyMI, SrcIdx = 0
@@ -1507,7 +1486,6 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
1507
1486
NewRC = TRI->getCommonSubClass (NewRC, DefRC);
1508
1487
assert (NewRC && " subreg chosen for remat incompatible with instruction" );
1509
1488
}
1510
-
1511
1489
// Remap subranges to new lanemask and change register class.
1512
1490
LiveInterval &DstInt = LIS->getInterval (DstReg);
1513
1491
for (LiveInterval::SubRange &SR : DstInt.subranges ()) {
0 commit comments