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[CodeGen] change prototype of regalloc filter function
change the prototype of the filter function so that we can filter not just by RegClass. We need to implement more complicated filter based upon some other info associated with each register. Patch provided by: Gang Chen ([email protected])
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13 files changed

+54
-48
lines changed

13 files changed

+54
-48
lines changed

‎llvm/include/llvm/CodeGen/Passes.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -205,20 +205,20 @@ namespace llvm {
205205
/// possible. It is best suited for debug code where live ranges are short.
206206
///
207207
FunctionPass *createFastRegisterAllocator();
208-
FunctionPass *createFastRegisterAllocator(RegClassFilterFunc F,
208+
FunctionPass *createFastRegisterAllocator(RegAllocFilterFunc F,
209209
bool ClearVirtRegs);
210210

211211
/// BasicRegisterAllocation Pass - This pass implements a degenerate global
212212
/// register allocator using the basic regalloc framework.
213213
///
214214
FunctionPass *createBasicRegisterAllocator();
215-
FunctionPass *createBasicRegisterAllocator(RegClassFilterFunc F);
215+
FunctionPass *createBasicRegisterAllocator(RegAllocFilterFunc F);
216216

217217
/// Greedy register allocation pass - This pass implements a global register
218218
/// allocator for optimized builds.
219219
///
220220
FunctionPass *createGreedyRegisterAllocator();
221-
FunctionPass *createGreedyRegisterAllocator(RegClassFilterFunc F);
221+
FunctionPass *createGreedyRegisterAllocator(RegAllocFilterFunc F);
222222

223223
/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
224224
/// Quadratic Prograaming (PBQP) based register allocator.

‎llvm/include/llvm/CodeGen/RegAllocCommon.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,18 +9,20 @@
99
#ifndef LLVM_CODEGEN_REGALLOCCOMMON_H
1010
#define LLVM_CODEGEN_REGALLOCCOMMON_H
1111

12+
#include "llvm/CodeGen/Register.h"
1213
#include <functional>
1314

1415
namespace llvm {
1516

1617
class TargetRegisterClass;
1718
class TargetRegisterInfo;
19+
class MachineRegisterInfo;
1820

1921
/// Filter function for register classes during regalloc. Default register class
2022
/// filter is nullptr, where all registers should be allocated.
2123
typedef std::function<bool(const TargetRegisterInfo &TRI,
22-
const TargetRegisterClass &RC)>
23-
RegClassFilterFunc;
24+
const MachineRegisterInfo &MRI, const Register Reg)>
25+
RegAllocFilterFunc;
2426
}
2527

2628
#endif // LLVM_CODEGEN_REGALLOCCOMMON_H

‎llvm/include/llvm/CodeGen/RegAllocFast.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
namespace llvm {
1616

1717
struct RegAllocFastPassOptions {
18-
RegClassFilterFunc Filter = nullptr;
18+
RegAllocFilterFunc Filter = nullptr;
1919
StringRef FilterName = "all";
2020
bool ClearVRegs = true;
2121
};

‎llvm/include/llvm/Passes/PassBuilder.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -390,9 +390,9 @@ class PassBuilder {
390390
/// returns false.
391391
Error parseAAPipeline(AAManager &AA, StringRef PipelineText);
392392

393-
/// Parse RegClassFilterName to get RegClassFilterFunc.
394-
std::optional<RegClassFilterFunc>
395-
parseRegAllocFilter(StringRef RegClassFilterName);
393+
/// Parse RegAllocFilterName to get RegAllocFilterFunc.
394+
std::optional<RegAllocFilterFunc>
395+
parseRegAllocFilter(StringRef RegAllocFilterName);
396396

397397
/// Print pass names.
398398
void printPassNames(raw_ostream &OS);
@@ -586,7 +586,7 @@ class PassBuilder {
586586
/// needs it. E.g. AMDGPU requires regalloc passes can handle sgpr and vgpr
587587
/// separately.
588588
void registerRegClassFilterParsingCallback(
589-
const std::function<RegClassFilterFunc(StringRef)> &C) {
589+
const std::function<RegAllocFilterFunc(StringRef)> &C) {
590590
RegClassFilterParsingCallbacks.push_back(C);
591591
}
592592

@@ -807,7 +807,7 @@ class PassBuilder {
807807
2>
808808
MachineFunctionPipelineParsingCallbacks;
809809
// Callbacks to parse `filter` parameter in register allocation passes
810-
SmallVector<std::function<RegClassFilterFunc(StringRef)>, 2>
810+
SmallVector<std::function<RegAllocFilterFunc(StringRef)>, 2>
811811
RegClassFilterParsingCallbacks;
812812
};
813813

‎llvm/lib/CodeGen/RegAllocBase.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ class RegAllocBase {
7272

7373
private:
7474
/// Private, callees should go through shouldAllocateRegister
75-
const RegClassFilterFunc ShouldAllocateClass;
75+
const RegAllocFilterFunc shouldAllocateRegisterImpl;
7676

7777
protected:
7878
/// Inst which is a def of an original reg and whose defs are already all
@@ -81,7 +81,8 @@ class RegAllocBase {
8181
/// always available for the remat of all the siblings of the original reg.
8282
SmallPtrSet<MachineInstr *, 32> DeadRemats;
8383

84-
RegAllocBase(const RegClassFilterFunc F = nullptr) : ShouldAllocateClass(F) {}
84+
RegAllocBase(const RegAllocFilterFunc F = nullptr)
85+
: shouldAllocateRegisterImpl(F) {}
8586

8687
virtual ~RegAllocBase() = default;
8788

@@ -90,9 +91,9 @@ class RegAllocBase {
9091

9192
/// Get whether a given register should be allocated
9293
bool shouldAllocateRegister(Register Reg) {
93-
if (!ShouldAllocateClass)
94+
if (!shouldAllocateRegisterImpl)
9495
return true;
95-
return ShouldAllocateClass(*TRI, *MRI->getRegClass(Reg));
96+
return shouldAllocateRegisterImpl(*TRI, *MRI, Reg);
9697
}
9798

9899
// The top-level driver. The output is a VirtRegMap that us updated with

‎llvm/lib/CodeGen/RegAllocBasic.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ class RABasic : public MachineFunctionPass,
7474
void LRE_WillShrinkVirtReg(Register) override;
7575

7676
public:
77-
RABasic(const RegClassFilterFunc F = nullptr);
77+
RABasic(const RegAllocFilterFunc F = nullptr);
7878

7979
/// Return the pass name.
8080
StringRef getPassName() const override { return "Basic Register Allocator"; }
@@ -168,10 +168,8 @@ void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) {
168168
enqueue(&LI);
169169
}
170170

171-
RABasic::RABasic(RegClassFilterFunc F):
172-
MachineFunctionPass(ID),
173-
RegAllocBase(F) {
174-
}
171+
RABasic::RABasic(RegAllocFilterFunc F)
172+
: MachineFunctionPass(ID), RegAllocBase(F) {}
175173

176174
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
177175
AU.setPreservesCFG();
@@ -333,6 +331,6 @@ FunctionPass* llvm::createBasicRegisterAllocator() {
333331
return new RABasic();
334332
}
335333

336-
FunctionPass* llvm::createBasicRegisterAllocator(RegClassFilterFunc F) {
334+
FunctionPass *llvm::createBasicRegisterAllocator(RegAllocFilterFunc F) {
337335
return new RABasic(F);
338336
}

‎llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -177,9 +177,9 @@ class InstrPosIndexes {
177177

178178
class RegAllocFastImpl {
179179
public:
180-
RegAllocFastImpl(const RegClassFilterFunc F = nullptr,
180+
RegAllocFastImpl(const RegAllocFilterFunc F = nullptr,
181181
bool ClearVirtRegs_ = true)
182-
: ShouldAllocateClass(F), StackSlotForVirtReg(-1),
182+
: ShouldAllocateRegisterImpl(F), StackSlotForVirtReg(-1),
183183
ClearVirtRegs(ClearVirtRegs_) {}
184184

185185
private:
@@ -188,7 +188,7 @@ class RegAllocFastImpl {
188188
const TargetRegisterInfo *TRI = nullptr;
189189
const TargetInstrInfo *TII = nullptr;
190190
RegisterClassInfo RegClassInfo;
191-
const RegClassFilterFunc ShouldAllocateClass;
191+
const RegAllocFilterFunc ShouldAllocateRegisterImpl;
192192

193193
/// Basic block currently being allocated.
194194
MachineBasicBlock *MBB = nullptr;
@@ -397,7 +397,7 @@ class RegAllocFast : public MachineFunctionPass {
397397
public:
398398
static char ID;
399399

400-
RegAllocFast(const RegClassFilterFunc F = nullptr, bool ClearVirtRegs_ = true)
400+
RegAllocFast(const RegAllocFilterFunc F = nullptr, bool ClearVirtRegs_ = true)
401401
: MachineFunctionPass(ID), Impl(F, ClearVirtRegs_) {}
402402

403403
bool runOnMachineFunction(MachineFunction &MF) override {
@@ -440,10 +440,10 @@ INITIALIZE_PASS(RegAllocFast, "regallocfast", "Fast Register Allocator", false,
440440

441441
bool RegAllocFastImpl::shouldAllocateRegister(const Register Reg) const {
442442
assert(Reg.isVirtual());
443-
if (!ShouldAllocateClass)
443+
if (!ShouldAllocateRegisterImpl)
444444
return true;
445-
const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
446-
return ShouldAllocateClass(*TRI, RC);
445+
446+
return ShouldAllocateRegisterImpl(*TRI, *MRI, Reg);
447447
}
448448

449449
void RegAllocFastImpl::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
@@ -1841,7 +1841,7 @@ void RegAllocFastPass::printPipeline(
18411841

18421842
FunctionPass *llvm::createFastRegisterAllocator() { return new RegAllocFast(); }
18431843

1844-
FunctionPass *llvm::createFastRegisterAllocator(RegClassFilterFunc Ftor,
1844+
FunctionPass *llvm::createFastRegisterAllocator(RegAllocFilterFunc Ftor,
18451845
bool ClearVirtRegs) {
18461846
return new RegAllocFast(Ftor, ClearVirtRegs);
18471847
}

‎llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -192,14 +192,12 @@ FunctionPass* llvm::createGreedyRegisterAllocator() {
192192
return new RAGreedy();
193193
}
194194

195-
FunctionPass *llvm::createGreedyRegisterAllocator(RegClassFilterFunc Ftor) {
195+
FunctionPass *llvm::createGreedyRegisterAllocator(RegAllocFilterFunc Ftor) {
196196
return new RAGreedy(Ftor);
197197
}
198198

199-
RAGreedy::RAGreedy(RegClassFilterFunc F):
200-
MachineFunctionPass(ID),
201-
RegAllocBase(F) {
202-
}
199+
RAGreedy::RAGreedy(RegAllocFilterFunc F)
200+
: MachineFunctionPass(ID), RegAllocBase(F) {}
203201

204202
void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
205203
AU.setPreservesCFG();
@@ -2306,7 +2304,7 @@ void RAGreedy::tryHintRecoloring(const LiveInterval &VirtReg) {
23062304
if (Reg.isPhysical())
23072305
continue;
23082306

2309-
// This may be a skipped class
2307+
// This may be a skipped register.
23102308
if (!VRM->hasPhys(Reg)) {
23112309
assert(!shouldAllocateRegister(Reg) &&
23122310
"We have an unallocated variable which should have been handled");

‎llvm/lib/CodeGen/RegAllocGreedy.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
281281
bool ReverseLocalAssignment = false;
282282

283283
public:
284-
RAGreedy(const RegClassFilterFunc F = nullptr);
284+
RAGreedy(const RegAllocFilterFunc F = nullptr);
285285

286286
/// Return the pass name.
287287
StringRef getPassName() const override { return "Greedy Register Allocator"; }

‎llvm/lib/Passes/PassBuilder.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1180,7 +1180,7 @@ parseRegAllocFastPassOptions(PassBuilder &PB, StringRef Params) {
11801180
std::tie(ParamName, Params) = Params.split(';');
11811181

11821182
if (ParamName.consume_front("filter=")) {
1183-
std::optional<RegClassFilterFunc> Filter =
1183+
std::optional<RegAllocFilterFunc> Filter =
11841184
PB.parseRegAllocFilter(ParamName);
11851185
if (!Filter) {
11861186
return make_error<StringError>(
@@ -2190,7 +2190,7 @@ Error PassBuilder::parseAAPipeline(AAManager &AA, StringRef PipelineText) {
21902190
return Error::success();
21912191
}
21922192

2193-
std::optional<RegClassFilterFunc>
2193+
std::optional<RegAllocFilterFunc>
21942194
PassBuilder::parseRegAllocFilter(StringRef FilterName) {
21952195
if (FilterName == "all")
21962196
return nullptr;

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -85,16 +85,19 @@ class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
8585
};
8686

8787
static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
88-
const TargetRegisterClass &RC) {
89-
return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
88+
const MachineRegisterInfo &MRI,
89+
const Register Reg) {
90+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
91+
return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC);
9092
}
9193

9294
static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
93-
const TargetRegisterClass &RC) {
94-
return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
95+
const MachineRegisterInfo &MRI,
96+
const Register Reg) {
97+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
98+
return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC);
9599
}
96100

97-
98101
/// -{sgpr|vgpr}-regalloc=... command line option.
99102
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
100103

@@ -749,7 +752,7 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
749752
});
750753

751754
PB.registerRegClassFilterParsingCallback(
752-
[](StringRef FilterName) -> RegClassFilterFunc {
755+
[](StringRef FilterName) -> RegAllocFilterFunc {
753756
if (FilterName == "sgpr")
754757
return onlyAllocateSGPRs;
755758
if (FilterName == "vgpr")

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -279,8 +279,10 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
279279
};
280280

281281
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
282-
const TargetRegisterClass &RC) {
283-
return RISCVRegisterInfo::isRVVRegClass(&RC);
282+
const MachineRegisterInfo &MRI,
283+
const Register Reg) {
284+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
285+
return RISCVRegisterInfo::isRVVRegClass(RC);
284286
}
285287

286288
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }

‎llvm/lib/Target/X86/X86TargetMachine.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -676,8 +676,10 @@ std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
676676
}
677677

678678
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI,
679-
const TargetRegisterClass &RC) {
680-
return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
679+
const MachineRegisterInfo &MRI,
680+
const Register Reg) {
681+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
682+
return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(RC);
681683
}
682684

683685
bool X86PassConfig::addRegAssignAndRewriteOptimized() {

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