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jwanggit86jwanggit86
authoredOct 24, 2024··
[AMDGPU][MC] Fix disassembler problem for image_atomic with TFE (#112622)
For image_atomic instructions with TFE, in some cases (e.g., when dmask=3) the disassembler produces dst register with wrong size (e.g., image_atomic_smin v5, v1, s[8:15] dmask:0x3 tfe, instead of v[5:7]). This patch fixes the VDataDwords values for image atomic instructions.
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‎llvm/lib/Target/AMDGPU/MIMGInstructions.td

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1119,14 +1119,22 @@ multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0,
11191119
// _V* variants have different dst size, but the size is encoded implicitly,
11201120
// using dmask and tfe. Only 32-bit variant is registered with disassembler.
11211121
// Other variants are reconstructed by disassembler using dmask and tfe.
1122-
let VDataDwords = !if(isCmpSwap, 2, 1) in
1123-
defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP, renamed>;
1124-
let VDataDwords = !if(isCmpSwap, 4, 2) in
1125-
defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP, renamed>;
1126-
let VDataDwords = !if(isCmpSwap, 2, 2) in
1122+
if !not(isCmpSwap) then {
1123+
let VDataDwords = 1 in
1124+
defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, VGPR_32, 1, isFP, renamed>;
1125+
}
1126+
1127+
let VDataDwords = 2 in
1128+
defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, VReg_64, isCmpSwap, isFP, renamed>;
1129+
let VDataDwords = 3 in
11271130
defm _V3 : MIMG_Atomic_Addr_Helper_m <op, asm, VReg_96, 0, isFP, renamed>;
1128-
let VDataDwords = !if(isCmpSwap, 4, 4) in
1129-
defm _V4 : MIMG_Atomic_Addr_Helper_m <op, asm, VReg_160, 0, isFP, renamed>;
1131+
1132+
if isCmpSwap then {
1133+
let VDataDwords = 4 in
1134+
defm _V4 : MIMG_Atomic_Addr_Helper_m <op, asm, VReg_128, 0, isFP, renamed>;
1135+
let VDataDwords = 5 in
1136+
defm _V5 : MIMG_Atomic_Addr_Helper_m <op, asm, VReg_160, 0, isFP, renamed>;
1137+
}
11301138
}
11311139
} // End IsAtomicRet = 1
11321140
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.mir

Lines changed: 30 additions & 30 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/release-vgprs.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -548,9 +548,9 @@ machineFunctionInfo:
548548
body: |
549549
bb.0:
550550
; CHECK-LABEL: name: image_atomic
551-
; CHECK: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx11 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr4, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, 0, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 7)
551+
; CHECK: renamable $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx11 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr4, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, 0, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 7)
552552
; CHECK-NEXT: S_ENDPGM 0, implicit $vgpr97
553-
renamable $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_ATOMIC_CMPSWAP_V2_V1_gfx11 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr4, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, 0, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 7)
553+
renamable $vgpr0_vgpr1_vgpr2_vgpr3 = IMAGE_ATOMIC_CMPSWAP_V4_V1_gfx11 killed renamable $vgpr0_vgpr1_vgpr2_vgpr3, killed renamable $vgpr4, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, 15, 0, 1, 1, 0, 0, 0, 0, implicit $exec :: (volatile dereferenceable load store (s64), addrspace 7)
554554
S_ENDPGM 0, implicit $vgpr97
555555
...
556556

‎llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg_features.txt

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
1+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX1010
2+
3+
#===------------------------------------------------------------------------===#
4+
# Image atomics
5+
#===------------------------------------------------------------------------===#
6+
7+
# GFX1010: image_atomic_add v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
8+
0x00,0x01,0x45,0xf0,0x01,0x05,0x02,0x00
9+
10+
# GFX1010: image_atomic_add v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
11+
0x00,0x03,0x45,0xf0,0x01,0x05,0x02,0x00
12+
13+
# GFX1010: image_atomic_and v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
14+
0x00,0x01,0x61,0xf0,0x01,0x05,0x02,0x00
15+
16+
# GFX1010: image_atomic_and v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
17+
0x00,0x03,0x61,0xf0,0x01,0x05,0x02,0x00
18+
19+
# GFX1010: image_atomic_cmpswap v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
20+
0x00,0x03,0x41,0xf0,0x01,0x05,0x02,0x00
21+
22+
# GFX1010: image_atomic_cmpswap v[5:9], v1, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
23+
0x00,0x0f,0x41,0xf0,0x01,0x05,0x02,0x00
24+
25+
# GFX1010: image_atomic_dec v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
26+
0x00,0x01,0x71,0xf0,0x01,0x05,0x02,0x00
27+
28+
# GFX1010: image_atomic_dec v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
29+
0x00,0x03,0x71,0xf0,0x01,0x05,0x02,0x00
30+
31+
# GFX1010: image_atomic_inc v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
32+
0x00,0x01,0x6d,0xf0,0x01,0x05,0x02,0x00
33+
34+
# GFX1010: image_atomic_inc v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
35+
0x00,0x03,0x6d,0xf0,0x01,0x05,0x02,0x00
36+
37+
# GFX1010: image_atomic_or v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
38+
0x00,0x01,0x65,0xf0,0x01,0x05,0x02,0x00
39+
40+
# GFX1010: image_atomic_or v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
41+
0x00,0x03,0x65,0xf0,0x01,0x05,0x02,0x00
42+
43+
# GFX1010: image_atomic_smax v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
44+
0x00,0x01,0x59,0xf0,0x01,0x05,0x02,0x00
45+
46+
# GFX1010: image_atomic_smax v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
47+
0x00,0x03,0x59,0xf0,0x01,0x05,0x02,0x00
48+
49+
# GFX1010: image_atomic_smin v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
50+
0x00,0x01,0x51,0xf0,0x01,0x05,0x02,0x00
51+
52+
# GFX1010: image_atomic_smin v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
53+
0x00,0x03,0x51,0xf0,0x01,0x05,0x02,0x00
54+
55+
# GFX1010: image_atomic_sub v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
56+
0x00,0x01,0x49,0xf0,0x01,0x05,0x02,0x00
57+
58+
# GFX1010: image_atomic_sub v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
59+
0x00,0x03,0x49,0xf0,0x01,0x05,0x02,0x00
60+
61+
# GFX1010: image_atomic_swap v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
62+
0x00,0x01,0x3d,0xf0,0x01,0x05,0x02,0x00
63+
64+
# GFX1010: image_atomic_swap v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
65+
0x00,0x03,0x3d,0xf0,0x01,0x05,0x02,0x00
66+
67+
# GFX1010: image_atomic_umax v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
68+
0x00,0x01,0x5d,0xf0,0x01,0x05,0x02,0x00
69+
70+
# GFX1010: image_atomic_umax v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
71+
0x00,0x03,0x5d,0xf0,0x01,0x05,0x02,0x00
72+
73+
# GFX1010: image_atomic_umin v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
74+
0x00,0x01,0x55,0xf0,0x01,0x05,0x02,0x00
75+
76+
# GFX1010: image_atomic_umin v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
77+
0x00,0x03,0x55,0xf0,0x01,0x05,0x02,0x00
78+
79+
# GFX1010: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
80+
0x00,0x01,0x69,0xf0,0x01,0x05,0x02,0x00
81+
82+
# GFX1010: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
83+
0x00,0x03,0x69,0xf0,0x01,0x05,0x02,0x00
84+

‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_mimg_features.txt

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,89 @@
135135
# GFX11: image_atomic_dec v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x41,0x58,0xf0,0x20,0x04,0x18,0x00]
136136
0x00,0x41,0x58,0xf0,0x20,0x04,0x18,0x00
137137

138+
#===------------------------------------------------------------------------===#
139+
# TFE in image_atomic
140+
#===------------------------------------------------------------------------===#
141+
142+
# GFX11: image_atomic_add v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
143+
0x00,0x01,0x30,0xf0,0x01,0x05,0x22,0x00
144+
145+
# GFX11: image_atomic_add v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
146+
0x00,0x03,0x30,0xf0,0x01,0x05,0x22,0x00
147+
148+
# GFX11: image_atomic_and v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
149+
0x00,0x01,0x48,0xf0,0x01,0x05,0x22,0x00
150+
151+
# GFX11: image_atomic_and v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
152+
0x00,0x03,0x48,0xf0,0x01,0x05,0x22,0x00
153+
154+
# GFX11: image_atomic_cmpswap v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
155+
0x00,0x03,0x2c,0xf0,0x01,0x05,0x22,0x00
156+
157+
# GFX11: image_atomic_cmpswap v[5:9], v1, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
158+
0x00,0x0f,0x2c,0xf0,0x01,0x05,0x22,0x00
159+
160+
# GFX11: image_atomic_dec v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
161+
0x00,0x01,0x58,0xf0,0x01,0x05,0x22,0x00
162+
163+
# GFX11: image_atomic_dec v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
164+
0x00,0x03,0x58,0xf0,0x01,0x05,0x22,0x00
165+
166+
# GFX11: image_atomic_inc v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
167+
0x00,0x01,0x54,0xf0,0x01,0x05,0x22,0x00
168+
169+
# GFX11: image_atomic_inc v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
170+
0x00,0x03,0x54,0xf0,0x01,0x05,0x22,0x00
171+
172+
# GFX11: image_atomic_or v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
173+
0x00,0x01,0x4c,0xf0,0x01,0x05,0x22,0x00
174+
175+
# GFX11: image_atomic_or v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
176+
0x00,0x03,0x4c,0xf0,0x01,0x05,0x22,0x00
177+
178+
# GFX11: image_atomic_smax v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
179+
0x00,0x01,0x40,0xf0,0x01,0x05,0x22,0x00
180+
181+
# GFX11: image_atomic_smax v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
182+
0x00,0x03,0x40,0xf0,0x01,0x05,0x22,0x00
183+
184+
# GFX11: image_atomic_smin v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
185+
0x00,0x01,0x38,0xf0,0x01,0x05,0x22,0x00
186+
187+
# GFX11: image_atomic_smin v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
188+
0x00,0x03,0x38,0xf0,0x01,0x05,0x22,0x00
189+
190+
# GFX11: image_atomic_sub v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
191+
0x00,0x01,0x34,0xf0,0x01,0x05,0x22,0x00
192+
193+
# GFX11: image_atomic_sub v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
194+
0x00,0x03,0x34,0xf0,0x01,0x05,0x22,0x00
195+
196+
# GFX11: image_atomic_swap v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
197+
0x00,0x01,0x28,0xf0,0x01,0x05,0x22,0x00
198+
199+
# GFX11: image_atomic_swap v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
200+
0x00,0x03,0x28,0xf0,0x01,0x05,0x22,0x00
201+
202+
# GFX11: image_atomic_umax v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
203+
0x00,0x01,0x44,0xf0,0x01,0x05,0x22,0x00
204+
205+
# GFX11: image_atomic_umax v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
206+
0x00,0x03,0x44,0xf0,0x01,0x05,0x22,0x00
207+
208+
# GFX11: image_atomic_umin v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
209+
0x00,0x01,0x3c,0xf0,0x01,0x05,0x22,0x00
210+
211+
# GFX11: image_atomic_umin v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
212+
0x00,0x03,0x3c,0xf0,0x01,0x05,0x22,0x00
213+
214+
# GFX11: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
215+
0x00,0x01,0x50,0xf0,0x01,0x05,0x22,0x00
216+
217+
# GFX11: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
218+
0x00,0x03,0x50,0xf0,0x01,0x05,0x22,0x00
219+
220+
138221
# GFX11: image_sample v[64:66], v32, s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_1D ; encoding: [0x00,0x07,0x6c,0xf0,0x20,0x40,0x01,0x64]
139222
0x00,0x07,0x6c,0xf0,0x20,0x40,0x01,0x64
140223

‎llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage_features.txt

Lines changed: 101 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,101 @@
1+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s
2+
3+
#===------------------------------------------------------------------------===#
4+
# TFE in image_atomic
5+
#===------------------------------------------------------------------------===#
6+
7+
# GFX12: image_atomic_add_flt v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
8+
0x00,0xc0,0x60,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
9+
10+
# GFX12: image_atomic_add_flt v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
11+
0x00,0xc0,0xe0,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
12+
13+
# GFX12: image_atomic_add_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
14+
0x00,0x00,0x43,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
15+
16+
# GFX12: image_atomic_add_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
17+
0x00,0x00,0xc3,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
18+
19+
# GFX12: image_atomic_and v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
20+
0x00,0x80,0x44,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
21+
22+
# GFX12: image_atomic_and v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
23+
0x00,0x80,0xc4,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
24+
25+
# GFX12: image_atomic_cmpswap v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
26+
0x00,0xc0,0xc2,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
27+
28+
# GFX12: image_atomic_cmpswap v[5:9], v1, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D tfe
29+
0x00,0xc0,0xc2,0xd3,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
30+
31+
# GFX12: image_atomic_dec_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
32+
0x00,0x80,0x45,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
33+
34+
# GFX12: image_atomic_dec_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
35+
0x00,0x80,0xc5,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
36+
37+
# GFX12: image_atomic_inc_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
38+
0x00,0x40,0x45,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
39+
40+
# GFX12: image_atomic_inc_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
41+
0x00,0x40,0xc5,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
42+
43+
# GFX12: image_atomic_max_int v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
44+
0x00,0x00,0x44,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
45+
46+
# GFX12: image_atomic_max_int v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
47+
0x00,0x00,0xc4,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
48+
49+
# GFX12: image_atomic_max_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
50+
0x00,0x40,0x44,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
51+
52+
# GFX12: image_atomic_max_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
53+
0x00,0x40,0xc4,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
54+
55+
# GFX12: image_atomic_min_int v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
56+
0x00,0x80,0x43,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
57+
58+
# GFX12: image_atomic_min_int v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
59+
0x00,0x80,0xc3,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
60+
61+
# GFX12: image_atomic_min_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
62+
0x00,0xc0,0x43,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
63+
64+
# GFX12: image_atomic_min_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
65+
0x00,0xc0,0xc3,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
66+
67+
# GFX12: image_atomic_or v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
68+
0x00,0xc0,0x44,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
69+
70+
# GFX12: image_atomic_or v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
71+
0x00,0xc0,0xc4,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
72+
73+
# GFX12: image_atomic_sub_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
74+
0x00,0x40,0x43,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
75+
76+
# GFX12: image_atomic_sub_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
77+
0x00,0x40,0xc3,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
78+
79+
# GFX12: image_atomic_swap v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
80+
0x00,0x80,0x42,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
81+
82+
# GFX12: image_atomic_swap v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
83+
0x00,0x80,0xc2,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
84+
85+
# GFX12: image_atomic_max_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
86+
0x00,0x40,0x44,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
87+
88+
# GFX12: image_atomic_max_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
89+
0x00,0x40,0xc4,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
90+
91+
# GFX12: image_atomic_min_uint v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
92+
0x00,0xc0,0x43,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
93+
94+
# GFX12: image_atomic_min_uint v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
95+
0x00,0xc0,0xc3,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
96+
97+
# GFX12: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe
98+
0x00,0x00,0x45,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00
99+
100+
# GFX12: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe
101+
0x00,0x00,0xc5,0xd0,0x05,0x10,0x80,0x00,0x01,0x00,0x00,0x00

‎llvm/test/MC/Disassembler/AMDGPU/gfx8_mimg_features.txt

Lines changed: 82 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -184,6 +184,85 @@
184184
# VI: image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
185185
0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00
186186

187+
# VI: image_atomic_add v[5:6], v1, s[8:15] dmask:0x1 tfe
188+
0x00,0x01,0x49,0xf0,0x01,0x05,0x02,0x00
189+
190+
# VI: image_atomic_add v[5:7], v1, s[8:15] dmask:0x3 tfe
191+
0x00,0x03,0x49,0xf0,0x01,0x05,0x02,0x00
192+
193+
# VI: image_atomic_and v[5:6], v1, s[8:15] dmask:0x1 tfe
194+
0x00,0x01,0x61,0xf0,0x01,0x05,0x02,0x00
195+
196+
# VI: image_atomic_and v[5:7], v1, s[8:15] dmask:0x3 tfe
197+
0x00,0x03,0x61,0xf0,0x01,0x05,0x02,0x00
198+
199+
# VI: image_atomic_cmpswap v[5:7], v1, s[8:15] dmask:0x3 tfe
200+
0x00,0x03,0x45,0xf0,0x01,0x05,0x02,0x00
201+
202+
# VI: image_atomic_cmpswap v[5:9], v1, s[8:15] dmask:0xf tfe
203+
0x00,0x0f,0x45,0xf0,0x01,0x05,0x02,0x00
204+
205+
# VI: image_atomic_dec v[5:6], v1, s[8:15] dmask:0x1 tfe
206+
0x00,0x01,0x71,0xf0,0x01,0x05,0x02,0x00
207+
208+
# VI: image_atomic_dec v[5:7], v1, s[8:15] dmask:0x3 tfe
209+
0x00,0x03,0x71,0xf0,0x01,0x05,0x02,0x00
210+
211+
# VI: image_atomic_inc v[5:6], v1, s[8:15] dmask:0x1 tfe
212+
0x00,0x01,0x6d,0xf0,0x01,0x05,0x02,0x00
213+
214+
# VI: image_atomic_inc v[5:7], v1, s[8:15] dmask:0x3 tfe
215+
0x00,0x03,0x6d,0xf0,0x01,0x05,0x02,0x00
216+
217+
# VI: image_atomic_or v[5:6], v1, s[8:15] dmask:0x1 tfe
218+
0x00,0x01,0x65,0xf0,0x01,0x05,0x02,0x00
219+
220+
# VI: image_atomic_or v[5:7], v1, s[8:15] dmask:0x3 tfe
221+
0x00,0x03,0x65,0xf0,0x01,0x05,0x02,0x00
222+
223+
# VI: image_atomic_smax v[5:6], v1, s[8:15] dmask:0x1 tfe
224+
0x00,0x01,0x59,0xf0,0x01,0x05,0x02,0x00
225+
226+
# VI: image_atomic_smax v[5:7], v1, s[8:15] dmask:0x3 tfe
227+
0x00,0x03,0x59,0xf0,0x01,0x05,0x02,0x00
228+
229+
# VI: image_atomic_smin v[5:6], v1, s[8:15] dmask:0x1 tfe
230+
0x00,0x01,0x51,0xf0,0x01,0x05,0x02,0x00
231+
232+
# VI: image_atomic_smin v[5:7], v1, s[8:15] dmask:0x3 tfe
233+
0x00,0x03,0x51,0xf0,0x01,0x05,0x02,0x00
234+
235+
# VI: image_atomic_sub v[5:6], v1, s[8:15] dmask:0x1 tfe
236+
0x00,0x01,0x4d,0xf0,0x01,0x05,0x02,0x00
237+
238+
# VI: image_atomic_sub v[5:7], v1, s[8:15] dmask:0x3 tfe
239+
0x00,0x03,0x4d,0xf0,0x01,0x05,0x02,0x00
240+
241+
# VI: image_atomic_swap v[5:6], v1, s[8:15] dmask:0x1 tfe
242+
0x00,0x01,0x41,0xf0,0x01,0x05,0x02,0x00
243+
244+
# VI: image_atomic_swap v[5:7], v1, s[8:15] dmask:0x3 tfe
245+
0x00,0x03,0x41,0xf0,0x01,0x05,0x02,0x00
246+
247+
# VI: image_atomic_umax v[5:6], v1, s[8:15] dmask:0x1 tfe
248+
0x00,0x01,0x5d,0xf0,0x01,0x05,0x02,0x00
249+
250+
# VI: image_atomic_umax v[5:7], v1, s[8:15] dmask:0x3 tfe
251+
0x00,0x03,0x5d,0xf0,0x01,0x05,0x02,0x00
252+
253+
# VI: image_atomic_umin v[5:6], v1, s[8:15] dmask:0x1 tfe
254+
0x00,0x01,0x55,0xf0,0x01,0x05,0x02,0x00
255+
256+
# VI: image_atomic_umin v[5:7], v1, s[8:15] dmask:0x3 tfe
257+
0x00,0x03,0x55,0xf0,0x01,0x05,0x02,0x00
258+
259+
# VI: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x1 tfe
260+
0x00,0x01,0x69,0xf0,0x01,0x05,0x02,0x00
261+
262+
# VI: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 tfe
263+
0x00,0x03,0x69,0xf0,0x01,0x05,0x02,0x00
264+
265+
187266
#===------------------------------------------------------------------------===#
188267
# Invalid image atomics (incorrect dmask value).
189268
# Disassembler may produce a partially incorrect instruction but should not fail.
@@ -192,10 +271,10 @@
192271
# VI: image_atomic_add v5, v1, s[8:15] dmask:0x2 unorm ; encoding: [0x00,0x12,0x48,0xf0,0x01,0x05,0x02,0x00]
193272
0x00,0x12,0x48,0xf0,0x01,0x05,0x02,0x00
194273

195-
# VI: image_atomic_add v5, v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
274+
# VI: image_atomic_add v[5:7], v1, s[8:15] dmask:0x7 unorm ; encoding: [0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00]
196275
0x00,0x17,0x48,0xf0,0x01,0x05,0x02,0x00
197276

198-
# VI: image_atomic_add v[5:9], v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x48,0xf0,0x01,0x05,0x02,0x00]
277+
# VI: image_atomic_add v5, v1, s[8:15] dmask:0xf unorm ; encoding: [0x00,0x1f,0x48,0xf0,0x01,0x05,0x02,0x00]
199278
0x00,0x1f,0x48,0xf0,0x01,0x05,0x02,0x00
200279

201280
# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] unorm ; encoding: [0x00,0x10,0x44,0xf0,0x01,0x05,0x02,0x00]
@@ -204,7 +283,7 @@
204283
# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x1 unorm ; encoding: [0x00,0x11,0x44,0xf0,0x01,0x05,0x02,0x00]
205284
0x00,0x11,0x44,0xf0,0x01,0x05,0x02,0x00
206285

207-
# VI: image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0xe unorm ; encoding: [0x00,0x1e,0x44,0xf0,0x01,0x05,0x02,0x00]
286+
# VI: image_atomic_cmpswap v[5:7], v1, s[8:15] dmask:0xe unorm ; encoding: [0x00,0x1e,0x44,0xf0,0x01,0x05,0x02,0x00]
208287
0x00,0x1e,0x44,0xf0,0x01,0x05,0x02,0x00
209288

210289
#===------------------------------------------------------------------------===#

‎llvm/test/MC/Disassembler/AMDGPU/gfx9_mimg_features.txt

Lines changed: 83 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,83 @@
1+
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX900
2+
3+
#===------------------------------------------------------------------------===#
4+
# Image atomics
5+
#===------------------------------------------------------------------------===#
6+
# GFX900: image_atomic_add v[5:6], v1, s[8:15] dmask:0x1 tfe
7+
0x00,0x01,0x49,0xf0,0x01,0x05,0x02,0x00
8+
9+
# GFX900: image_atomic_add v[5:7], v1, s[8:15] dmask:0x3 tfe
10+
0x00,0x03,0x49,0xf0,0x01,0x05,0x02,0x00
11+
12+
# GFX900: image_atomic_and v[5:6], v1, s[8:15] dmask:0x1 tfe
13+
0x00,0x01,0x61,0xf0,0x01,0x05,0x02,0x00
14+
15+
# GFX900: image_atomic_and v[5:7], v1, s[8:15] dmask:0x3 tfe
16+
0x00,0x03,0x61,0xf0,0x01,0x05,0x02,0x00
17+
18+
# GFX900: image_atomic_cmpswap v[5:7], v1, s[8:15] dmask:0x3 tfe
19+
0x00,0x03,0x45,0xf0,0x01,0x05,0x02,0x00
20+
21+
# GFX900: image_atomic_cmpswap v[5:9], v1, s[8:15] dmask:0xf tfe
22+
0x00,0x0f,0x45,0xf0,0x01,0x05,0x02,0x00
23+
24+
# GFX900: image_atomic_dec v[5:6], v1, s[8:15] dmask:0x1 tfe
25+
0x00,0x01,0x71,0xf0,0x01,0x05,0x02,0x00
26+
27+
# GFX900: image_atomic_dec v[5:7], v1, s[8:15] dmask:0x3 tfe
28+
0x00,0x03,0x71,0xf0,0x01,0x05,0x02,0x00
29+
30+
# GFX900: image_atomic_inc v[5:6], v1, s[8:15] dmask:0x1 tfe
31+
0x00,0x01,0x6d,0xf0,0x01,0x05,0x02,0x00
32+
33+
# GFX900: image_atomic_inc v[5:7], v1, s[8:15] dmask:0x3 tfe
34+
0x00,0x03,0x6d,0xf0,0x01,0x05,0x02,0x00
35+
36+
# GFX900: image_atomic_or v[5:6], v1, s[8:15] dmask:0x1 tfe
37+
0x00,0x01,0x65,0xf0,0x01,0x05,0x02,0x00
38+
39+
# GFX900: image_atomic_or v[5:7], v1, s[8:15] dmask:0x3 tfe
40+
0x00,0x03,0x65,0xf0,0x01,0x05,0x02,0x00
41+
42+
# GFX900: image_atomic_smax v[5:6], v1, s[8:15] dmask:0x1 tfe
43+
0x00,0x01,0x59,0xf0,0x01,0x05,0x02,0x00
44+
45+
# GFX900: image_atomic_smax v[5:7], v1, s[8:15] dmask:0x3 tfe
46+
0x00,0x03,0x59,0xf0,0x01,0x05,0x02,0x00
47+
48+
# GFX900: image_atomic_smin v[5:6], v1, s[8:15] dmask:0x1 tfe
49+
0x00,0x01,0x51,0xf0,0x01,0x05,0x02,0x00
50+
51+
# GFX900: image_atomic_smin v[5:7], v1, s[8:15] dmask:0x3 tfe
52+
0x00,0x03,0x51,0xf0,0x01,0x05,0x02,0x00
53+
54+
# GFX900: image_atomic_sub v[5:6], v1, s[8:15] dmask:0x1 tfe
55+
0x00,0x01,0x4d,0xf0,0x01,0x05,0x02,0x00
56+
57+
# GFX900: image_atomic_sub v[5:7], v1, s[8:15] dmask:0x3 tfe
58+
0x00,0x03,0x4d,0xf0,0x01,0x05,0x02,0x00
59+
60+
# GFX900: image_atomic_swap v[5:6], v1, s[8:15] dmask:0x1 tfe
61+
0x00,0x01,0x41,0xf0,0x01,0x05,0x02,0x00
62+
63+
# GFX900: image_atomic_swap v[5:7], v1, s[8:15] dmask:0x3 tfe
64+
0x00,0x03,0x41,0xf0,0x01,0x05,0x02,0x00
65+
66+
# GFX900: image_atomic_umax v[5:6], v1, s[8:15] dmask:0x1 tfe
67+
0x00,0x01,0x5d,0xf0,0x01,0x05,0x02,0x00
68+
69+
# GFX900: image_atomic_umax v[5:7], v1, s[8:15] dmask:0x3 tfe
70+
0x00,0x03,0x5d,0xf0,0x01,0x05,0x02,0x00
71+
72+
# GFX900: image_atomic_umin v[5:6], v1, s[8:15] dmask:0x1 tfe
73+
0x00,0x01,0x55,0xf0,0x01,0x05,0x02,0x00
74+
75+
# GFX900: image_atomic_umin v[5:7], v1, s[8:15] dmask:0x3 tfe
76+
0x00,0x03,0x55,0xf0,0x01,0x05,0x02,0x00
77+
78+
# GFX900: image_atomic_xor v[5:6], v1, s[8:15] dmask:0x1 tfe
79+
0x00,0x01,0x69,0xf0,0x01,0x05,0x02,0x00
80+
81+
# GFX900: image_atomic_xor v[5:7], v1, s[8:15] dmask:0x3 tfe
82+
0x00,0x03,0x69,0xf0,0x01,0x05,0x02,0x00
83+

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