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michaelmaitlandmichaelmaitland
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[RISCV] Add VL optimization related tests
These tests are good candidate for VL optimization. This is a pre-commit for PR #108640, but can could probably also be improved by the peephole VL optimizations.
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‎llvm/test/CodeGen/RISCV/rvv/vl-opt-no-prop.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, iXLen)
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declare <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.iXLen(
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<vscale x 4 x i32>,
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<vscale x 4 x i32>,
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<vscale x 4 x i32>,
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iXLen)
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declare <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
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<vscale x 4 x i32>,
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<vscale x 4 x i32>,
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iXLen,
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iXLen,
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iXLen);
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declare <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
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<vscale x 4 x i32>,
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<vscale x 4 x i32>,
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i32,
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iXLen);
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define <vscale x 4 x i32> @vrgather(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
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; CHECK-LABEL: vrgather:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v12, v10, v12
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vrgather.vv v8, v12, v10
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; CHECK-NEXT: ret
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%v = add <vscale x 4 x i32> %a, %b
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%w = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.iXLen(
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<vscale x 4 x i32> poison,
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<vscale x 4 x i32> %v,
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<vscale x 4 x i32> %a,
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iXLen %vl1)
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ret <vscale x 4 x i32> %w
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}
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define <vscale x 4 x i32> @vslidedown(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) nounwind {
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; CHECK-LABEL: vslidedown:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v10, v12, v14
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vslidedown.vx v8, v10, a0
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; CHECK-NEXT: ret
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entry:
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%v = add <vscale x 4 x i32> %a, %b
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%w = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(
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<vscale x 4 x i32> %0,
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<vscale x 4 x i32> %v,
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iXLen %2,
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iXLen %2,
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iXLen 1)
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ret <vscale x 4 x i32> %w
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}
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define <vscale x 4 x i32> @vslide1down(<vscale x 4 x i32> %0, i32 %1, iXLen %2, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) nounwind {
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; CHECK-LABEL: vslide1down:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a2, zero, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v12
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vslide1down.vx v8, v8, a0
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; CHECK-NEXT: ret
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entry:
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%v = add <vscale x 4 x i32> %a, %b
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%w = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
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<vscale x 4 x i32> poison,
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<vscale x 4 x i32> %v,
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i32 %1,
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iXLen %2)
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ret <vscale x 4 x i32> %w
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}

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvl512b -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvl512b -verify-machineinstrs | FileCheck %s
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define <2 x i32> @vdot_lane_s32(<2 x i32> noundef %var_1, <8 x i8> noundef %var_3, <8 x i8> noundef %var_5, <8 x i16> %x) {
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; CHECK-LABEL: vdot_lane_s32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e16, mf4, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v11, 0
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; CHECK-NEXT: vnsrl.wi v9, v11, 16
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; CHECK-NEXT: vwadd.vv v10, v8, v9
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v10, 0
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; CHECK-NEXT: li a0, 32
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; CHECK-NEXT: vnsrl.wx v9, v10, a0
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: ret
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entry:
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%a = shufflevector <8 x i16> %x, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <8 x i16> %x, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%c = sext <4 x i16> %a to <4 x i32>
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%d = sext <4 x i16> %b to <4 x i32>
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%e = add nsw <4 x i32> %c, %d
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%z10 = shufflevector <4 x i32> %e, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
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%z11 = shufflevector <4 x i32> %e, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
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%y12 = add <2 x i32> %z10, %z11
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ret <2 x i32> %y12
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}
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declare <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(
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<vscale x 2 x i16>,
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<vscale x 2 x i32>,
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<vscale x 2 x i16>,
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iXLen);
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define <vscale x 2 x i16> @intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %2, <vscale x 2 x i32> %3, <vscale x 2 x i32> %4, <vscale x 2 x i16> %z) nounwind {
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; CHECK-LABEL: intrinsic_vnsrl_wv_nxv2i16_nxv2i32_nxv2i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vwadd.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; CHECK-NEXT: vnsrl.wv v8, v10, v12
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; CHECK-NEXT: ret
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entry:
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%c = sext <vscale x 2 x i16> %a to <vscale x 2 x i32>
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%d = sext <vscale x 2 x i16> %b to <vscale x 2 x i32>
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%v1 = add <vscale x 2 x i32> %c, %d
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%x = call <vscale x 2 x i16> @llvm.riscv.vnsrl.nxv2i16.nxv2i32.nxv2i16(
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<vscale x 2 x i16> undef,
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<vscale x 2 x i32> %v1,
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<vscale x 2 x i16> %z,
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iXLen %2)
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ret <vscale x 2 x i16> %x
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}
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declare <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
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<vscale x 2 x i16>,
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<vscale x 2 x i32>,
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<vscale x 2 x i16>,
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iXLen, iXLen);
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define <vscale x 2 x i16> @vnclip(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b, iXLen %2, <vscale x 2 x i32> %3, <vscale x 2 x i32> %4, <vscale x 2 x i16> %z) nounwind {
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; CHECK-LABEL: vnclip:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vwadd.vv v10, v8, v9
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; CHECK-NEXT: csrwi vxrm, 0
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; CHECK-NEXT: vnclip.wv v8, v10, v12
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; CHECK-NEXT: ret
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entry:
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%c = sext <vscale x 2 x i16> %a to <vscale x 2 x i32>
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%d = sext <vscale x 2 x i16> %b to <vscale x 2 x i32>
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%v1 = add <vscale x 2 x i32> %c, %d
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%x = call <vscale x 2 x i16> @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16(
77+
<vscale x 2 x i16> undef,
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<vscale x 2 x i32> %v1,
79+
<vscale x 2 x i16> %z,
80+
iXLen 0, iXLen %2)
81+
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ret <vscale x 2 x i16> %x
83+
}

‎llvm/test/CodeGen/RISCV/rvv/vl-opt.ll

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@@ -0,0 +1,106 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
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5+
declare <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, iXLen)
6+
7+
define <vscale x 4 x i32> @different_imm_vl_with_ta(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
8+
; CHECK-LABEL: different_imm_vl_with_ta:
9+
; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v12
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; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v10
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; CHECK-NEXT: ret
15+
%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 5)
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%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 4)
17+
ret <vscale x 4 x i32> %w
18+
}
19+
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; No benificial to propagate VL since VL is larger in the use side.
21+
define <vscale x 4 x i32> @different_imm_vl_with_ta_larger_vl(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
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; CHECK-LABEL: different_imm_vl_with_ta_larger_vl:
23+
; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v12
26+
; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)
30+
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen 5)
31+
ret <vscale x 4 x i32> %w
32+
}
33+
34+
define <vscale x 4 x i32> @different_imm_reg_vl_with_ta(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
35+
; CHECK-LABEL: different_imm_reg_vl_with_ta:
36+
; CHECK: # %bb.0:
37+
; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v12
39+
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 4)
43+
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen %vl1)
44+
ret <vscale x 4 x i32> %w
45+
}
46+
47+
48+
; No benificial to propagate VL since VL is already one.
49+
define <vscale x 4 x i32> @different_imm_vl_with_ta_1(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
50+
; CHECK-LABEL: different_imm_vl_with_ta_1:
51+
; CHECK: # %bb.0:
52+
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
53+
; CHECK-NEXT: vadd.vv v8, v10, v12
54+
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
55+
; CHECK-NEXT: vadd.vv v8, v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 1)
58+
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a, iXLen %vl1)
59+
ret <vscale x 4 x i32> %w
60+
}
61+
62+
; Propgate %vl2 to last instruction since it is may smaller than %vl1,
63+
; it's still safe even %vl2 is larger than %vl1, becuase rest of the vector are
64+
; undefined value.
65+
define <vscale x 4 x i32> @different_vl_with_ta(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
66+
; CHECK-LABEL: different_vl_with_ta:
67+
; CHECK: # %bb.0:
68+
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
69+
; CHECK-NEXT: vadd.vv v10, v8, v10
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; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v10, v8
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1)
74+
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a,iXLen %vl2)
75+
ret <vscale x 4 x i32> %w
76+
}
77+
78+
; Test case to make sure VL won't propgate if using tail-undisturbed policy.
79+
define <vscale x 4 x i32> @different_vl_with_tu(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
80+
; CHECK-LABEL: different_vl_with_tu:
81+
; CHECK: # %bb.0:
82+
; CHECK-NEXT: vmv2r.v v14, v10
83+
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
84+
; CHECK-NEXT: vadd.vv v14, v10, v12
85+
; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma
86+
; CHECK-NEXT: vadd.vv v8, v14, v10
87+
; CHECK-NEXT: ret
88+
%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1)
89+
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a,iXLen %vl2)
90+
ret <vscale x 4 x i32> %w
91+
}
92+
93+
; Test case to make sure VL won't propgate if using tail-undisturbed policy.
94+
define <vscale x 4 x i32> @different_imm_vl_with_tu(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen %vl1, iXLen %vl2) {
95+
; CHECK-LABEL: different_imm_vl_with_tu:
96+
; CHECK: # %bb.0:
97+
; CHECK-NEXT: vmv2r.v v14, v10
98+
; CHECK-NEXT: vsetivli zero, 5, e32, m2, tu, ma
99+
; CHECK-NEXT: vadd.vv v14, v10, v12
100+
; CHECK-NEXT: vsetivli zero, 4, e32, m2, tu, ma
101+
; CHECK-NEXT: vadd.vv v8, v14, v10
102+
; CHECK-NEXT: ret
103+
%v = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, iXLen 5)
104+
%w = call <vscale x 4 x i32> @llvm.riscv.vadd.nxv4i32.nxv4i32(<vscale x 4 x i32> %passthru, <vscale x 4 x i32> %v, <vscale x 4 x i32> %a,iXLen 4)
105+
ret <vscale x 4 x i32> %w
106+
}

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