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remove constant zero tests
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‎llvm/test/CodeGen/AArch64/xor-smin-smax.ll‎

Lines changed: 22 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -7,64 +7,47 @@ define i64 @test_smin_neg_one(i64 %a) {
77
; CHECK-LABEL: test_smin_neg_one:
88
; CHECK: // %bb.0:
99
; CHECK-NEXT: cmn x0, #1
10-
; CHECK-NEXT: csinv x0, xzr, x0, ge
10+
; CHECK-NEXT: csinv x8, x0, xzr, lt
11+
; CHECK-NEXT: mvn x0, x8
1112
; CHECK-NEXT: ret
1213
%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 -1)
1314
%retval.0 = xor i64 %1, -1
1415
ret i64 %retval.0
1516
}
1617

17-
define i64 @test_smin_zero(i64 %a) {
18-
; CHECK-LABEL: test_smin_zero:
19-
; CHECK: // %bb.0:
20-
; CHECK-NEXT: and x0, x0, x0, asr #63
21-
; CHECK-NEXT: ret
22-
%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 0)
23-
%retval.0 = xor i64 %1, 0
24-
ret i64 %retval.0
25-
}
26-
2718
define i64 @test_smin_constant(i64 %a) {
2819
; CHECK-LABEL: test_smin_constant:
2920
; CHECK: // %bb.0:
30-
; CHECK-NEXT: eor x8, x0, #0x8
21+
; CHECK-NEXT: mov w8, #8
3122
; CHECK-NEXT: cmp x0, #8
32-
; CHECK-NEXT: csel x0, x8, xzr, lt
23+
; CHECK-NEXT: csel x8, x0, x8, lt
24+
; CHECK-NEXT: eor x0, x8, #0x8
3325
; CHECK-NEXT: ret
3426
%1 = tail call i64 @llvm.smin.i64(i64 %a, i64 8)
3527
%retval.0 = xor i64 %1, 8
3628
ret i64 %retval.0
3729
}
3830

3931
; Test for DAGCombiner optimization: fold (xor (smax(x, C), C)) -> select (x > C), xor (x, C), 0
40-
4132
define i64 @test_smax_neg_one(i64 %a) {
4233
; CHECK-LABEL: test_smax_neg_one:
4334
; CHECK: // %bb.0:
44-
; CHECK-NEXT: mvn x8, x0
45-
; CHECK-NEXT: bic x0, x8, x0, asr #63
35+
; CHECK-NEXT: cmp x0, #0
36+
; CHECK-NEXT: csinv x8, x0, xzr, ge
37+
; CHECK-NEXT: mvn x0, x8
4638
; CHECK-NEXT: ret
4739
%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 -1)
4840
%retval.0 = xor i64 %1, -1
4941
ret i64 %retval.0
5042
}
5143

52-
define i64 @test_smax_zero(i64 %a) {
53-
; CHECK-LABEL: test_smax_zero:
54-
; CHECK: // %bb.0:
55-
; CHECK-NEXT: bic x0, x0, x0, asr #63
56-
; CHECK-NEXT: ret
57-
%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 0)
58-
%retval.0 = xor i64 %1, 0
59-
ret i64 %retval.0
60-
}
61-
6244
define i64 @test_smax_constant(i64 %a) {
6345
; CHECK-LABEL: test_smax_constant:
6446
; CHECK: // %bb.0:
65-
; CHECK-NEXT: eor x8, x0, #0x8
47+
; CHECK-NEXT: mov w8, #8
6648
; CHECK-NEXT: cmp x0, #8
67-
; CHECK-NEXT: csel x0, x8, xzr, gt
49+
; CHECK-NEXT: csel x8, x0, x8, gt
50+
; CHECK-NEXT: eor x0, x8, #0x8
6851
; CHECK-NEXT: ret
6952
%1 = tail call i64 @llvm.smax.i64(i64 %a, i64 8)
7053
%retval.0 = xor i64 %1, 8
@@ -81,22 +64,13 @@ define i64 @test_umin_neg_one(i64 %a) {
8164
ret i64 %retval.0
8265
}
8366

84-
define i64 @test_umin_zero(i64 %a) {
85-
; CHECK-LABEL: test_umin_zero:
86-
; CHECK: // %bb.0:
87-
; CHECK-NEXT: mov x0, xzr
88-
; CHECK-NEXT: ret
89-
%1 = tail call i64 @llvm.umin.i64(i64 %a, i64 0)
90-
%retval.0 = xor i64 %1, 0
91-
ret i64 %retval.0
92-
}
93-
9467
define i64 @test_umin_constant(i64 %a) {
9568
; CHECK-LABEL: test_umin_constant:
9669
; CHECK: // %bb.0:
97-
; CHECK-NEXT: eor x8, x0, #0x8
70+
; CHECK-NEXT: mov w8, #8
9871
; CHECK-NEXT: cmp x0, #8
99-
; CHECK-NEXT: csel x0, x8, xzr, lo
72+
; CHECK-NEXT: csel x8, x0, x8, lo
73+
; CHECK-NEXT: eor x0, x8, #0x8
10074
; CHECK-NEXT: ret
10175
%1 = tail call i64 @llvm.umin.i64(i64 %a, i64 8)
10276
%retval.0 = xor i64 %1, 8
@@ -113,52 +87,32 @@ define i64 @test_umax_neg_one(i64 %a) {
11387
ret i64 %retval.0
11488
}
11589

116-
define i64 @test_umax_zero(i64 %a) {
117-
; CHECK-LABEL: test_umax_zero:
118-
; CHECK: // %bb.0:
119-
; CHECK-NEXT: ret
120-
%1 = tail call i64 @llvm.umax.i64(i64 %a, i64 0)
121-
%retval.0 = xor i64 %1, 0
122-
ret i64 %retval.0
123-
}
124-
12590
define i64 @test_umax_constant(i64 %a) {
12691
; CHECK-LABEL: test_umax_constant:
12792
; CHECK: // %bb.0:
128-
; CHECK-NEXT: eor x8, x0, #0x8
93+
; CHECK-NEXT: mov w8, #8
12994
; CHECK-NEXT: cmp x0, #8
130-
; CHECK-NEXT: csel x0, x8, xzr, hi
95+
; CHECK-NEXT: csel x8, x0, x8, hi
96+
; CHECK-NEXT: eor x0, x8, #0x8
13197
; CHECK-NEXT: ret
13298
%1 = tail call i64 @llvm.umax.i64(i64 %a, i64 8)
13399
%retval.0 = xor i64 %1, 8
134100
ret i64 %retval.0
135101
}
136102

137103
; Test vector cases
138-
139104
define <4 x i32> @test_smin_vector_neg_one(<4 x i32> %a) {
140105
; CHECK-LABEL: test_smin_vector_neg_one:
141106
; CHECK: // %bb.0:
142107
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
143-
; CHECK-NEXT: cmgt v1.4s, v1.4s, v0.4s
144-
; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
108+
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
109+
; CHECK-NEXT: mvn v0.16b, v0.16b
145110
; CHECK-NEXT: ret
146111
%1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
147112
%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
148113
ret <4 x i32> %retval.0
149114
}
150115

151-
define <4 x i32> @test_smin_vector_zero(<4 x i32> %a) {
152-
; CHECK-LABEL: test_smin_vector_zero:
153-
; CHECK: // %bb.0:
154-
; CHECK-NEXT: movi v1.2d, #0000000000000000
155-
; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
156-
; CHECK-NEXT: ret
157-
%1 = tail call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
158-
%retval.0 = xor <4 x i32> %1, <i32 0, i32 0, i32 0, i32 0>
159-
ret <4 x i32> %retval.0
160-
}
161-
162116
define <4 x i32> @test_smin_vector_constant(<4 x i32> %a) {
163117
; CHECK-LABEL: test_smin_vector_constant:
164118
; CHECK: // %bb.0:
@@ -174,25 +128,15 @@ define <4 x i32> @test_smin_vector_constant(<4 x i32> %a) {
174128
define <4 x i32> @test_smax_vector_neg_one(<4 x i32> %a) {
175129
; CHECK-LABEL: test_smax_vector_neg_one:
176130
; CHECK: // %bb.0:
177-
; CHECK-NEXT: cmge v1.4s, v0.4s, #0
178-
; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
131+
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
132+
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
133+
; CHECK-NEXT: mvn v0.16b, v0.16b
179134
; CHECK-NEXT: ret
180135
%1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
181136
%retval.0 = xor <4 x i32> %1, <i32 -1, i32 -1, i32 -1, i32 -1>
182137
ret <4 x i32> %retval.0
183138
}
184139

185-
define <4 x i32> @test_smax_vector_zero(<4 x i32> %a) {
186-
; CHECK-LABEL: test_smax_vector_zero:
187-
; CHECK: // %bb.0:
188-
; CHECK-NEXT: movi v1.2d, #0000000000000000
189-
; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
190-
; CHECK-NEXT: ret
191-
%1 = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
192-
%retval.0 = xor <4 x i32> %1, <i32 0, i32 0, i32 0, i32 0>
193-
ret <4 x i32> %retval.0
194-
}
195-
196140
define <4 x i32> @test_smax_vector_constant(<4 x i32> %a) {
197141
; CHECK-LABEL: test_smax_vector_constant:
198142
; CHECK: // %bb.0:
@@ -215,16 +159,6 @@ define <4 x i32> @test_umin_vector_neg_one(<4 x i32> %a) {
215159
ret <4 x i32> %retval.0
216160
}
217161

218-
define <4 x i32> @test_umin_vector_zero(<4 x i32> %a) {
219-
; CHECK-LABEL: test_umin_vector_zero:
220-
; CHECK: // %bb.0:
221-
; CHECK-NEXT: movi v0.2d, #0000000000000000
222-
; CHECK-NEXT: ret
223-
%1 = tail call <4 x i32> @llvm.umin.v4i32(<4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
224-
%retval.0 = xor <4 x i32> %1, <i32 0, i32 0, i32 0, i32 0>
225-
ret <4 x i32> %retval.0
226-
}
227-
228162
define <4 x i32> @test_umin_vector_constant(<4 x i32> %a) {
229163
; CHECK-LABEL: test_umin_vector_constant:
230164
; CHECK: // %bb.0:
@@ -247,15 +181,6 @@ define <4 x i32> @test_umax_vector_neg_one(<4 x i32> %a) {
247181
ret <4 x i32> %retval.0
248182
}
249183

250-
define <4 x i32> @test_umax_vector_zero(<4 x i32> %a) {
251-
; CHECK-LABEL: test_umax_vector_zero:
252-
; CHECK: // %bb.0:
253-
; CHECK-NEXT: ret
254-
%1 = tail call <4 x i32> @llvm.umax.v4i32(<4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 0, i32 0>)
255-
%retval.0 = xor <4 x i32> %1, <i32 0, i32 0, i32 0, i32 0>
256-
ret <4 x i32> %retval.0
257-
}
258-
259184
define <4 x i32> @test_umax_vector_constant(<4 x i32> %a) {
260185
; CHECK-LABEL: test_umax_vector_constant:
261186
; CHECK: // %bb.0:

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