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[TwoAddressInstruction] Handle physical registers with LiveIntervals (#66784)
Teach the LiveIntervals path in isPlainlyKilled to handle physical registers, to get equivalent functionality with the LiveVariables path. Test this by adding -early-live-intervals RUN lines to a handful of tests that would fail without this.
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7 files changed

+51
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‎llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

Lines changed: 27 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ class TwoAddressInstructionPass : public MachineFunctionPass {
125125
bool isCopyToReg(MachineInstr &MI, Register &SrcReg, Register &DstReg,
126126
bool &IsSrcPhys, bool &IsDstPhys) const;
127127

128+
bool isPlainlyKilled(const MachineInstr *MI, LiveRange &LR) const;
128129
bool isPlainlyKilled(const MachineInstr *MI, Register Reg) const;
129130
bool isPlainlyKilled(const MachineOperand &MO) const;
130131

@@ -305,27 +306,37 @@ bool TwoAddressInstructionPass::isCopyToReg(MachineInstr &MI, Register &SrcReg,
305306
return true;
306307
}
307308

309+
bool TwoAddressInstructionPass::isPlainlyKilled(const MachineInstr *MI,
310+
LiveRange &LR) const {
311+
// This is to match the kill flag version where undefs don't have kill flags.
312+
if (!LR.hasAtLeastOneValue())
313+
return false;
314+
315+
SlotIndex useIdx = LIS->getInstructionIndex(*MI);
316+
LiveInterval::const_iterator I = LR.find(useIdx);
317+
assert(I != LR.end() && "Reg must be live-in to use.");
318+
return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
319+
}
320+
308321
/// Test if the given register value, which is used by the
309322
/// given instruction, is killed by the given instruction.
310323
bool TwoAddressInstructionPass::isPlainlyKilled(const MachineInstr *MI,
311324
Register Reg) const {
312-
if (LIS && Reg.isVirtual() && !LIS->isNotInMIMap(*MI)) {
313-
// FIXME: Sometimes tryInstructionTransform() will add instructions and
314-
// test whether they can be folded before keeping them. In this case it
315-
// sets a kill before recursively calling tryInstructionTransform() again.
316-
// If there is no interval available, we assume that this instruction is
317-
// one of those. A kill flag is manually inserted on the operand so the
318-
// check below will handle it.
319-
LiveInterval &LI = LIS->getInterval(Reg);
320-
// This is to match the kill flag version where undefs don't have kill
321-
// flags.
322-
if (!LI.hasAtLeastOneValue())
325+
// FIXME: Sometimes tryInstructionTransform() will add instructions and
326+
// test whether they can be folded before keeping them. In this case it
327+
// sets a kill before recursively calling tryInstructionTransform() again.
328+
// If there is no interval available, we assume that this instruction is
329+
// one of those. A kill flag is manually inserted on the operand so the
330+
// check below will handle it.
331+
if (LIS && !LIS->isNotInMIMap(*MI)) {
332+
if (Reg.isVirtual())
333+
return isPlainlyKilled(MI, LIS->getInterval(Reg));
334+
// Reserved registers are considered always live.
335+
if (MRI->isReserved(Reg))
323336
return false;
324-
325-
SlotIndex useIdx = LIS->getInstructionIndex(*MI);
326-
LiveInterval::const_iterator I = LI.find(useIdx);
327-
assert(I != LI.end() && "Reg must be live-in to use.");
328-
return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
337+
return all_of(TRI->regunits(Reg), [&](MCRegUnit U) {
338+
return isPlainlyKilled(MI, LIS->getRegUnit(U));
339+
});
329340
}
330341

331342
return MI->killsRegister(Reg);

‎llvm/test/CodeGen/RISCV/rvv/fmaximum-sdnode.ll

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,20 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
5+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
46
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
57
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
8+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
9+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
610
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d \
711
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
12+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d \
13+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
814
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d \
915
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
16+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d \
17+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
1018

1119
declare <vscale x 1 x half> @llvm.maximum.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>)
1220

‎llvm/test/CodeGen/RISCV/rvv/fminimum-sdnode.ll

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,20 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
5+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
46
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
57
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
8+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
9+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
610
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d \
711
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
12+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=ilp32d \
13+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
814
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d \
915
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
16+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfhmin,+v,+m -target-abi=lp64d \
17+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
1018

1119
declare <vscale x 1 x half> @llvm.minimum.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>)
1220

‎llvm/test/CodeGen/RISCV/rvv/vfmsub-sdnode.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,12 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
33
; RUN: -verify-machineinstrs < %s | FileCheck %s
4+
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
5+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s
46
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
57
; RUN: -verify-machineinstrs < %s | FileCheck %s
8+
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
9+
; RUN: -verify-machineinstrs -early-live-intervals < %s | FileCheck %s
610

711
; This tests a mix of vfmsac and vfmsub by using different operand orders to
812
; trigger commuting in TwoAddressInstructionPass.

‎llvm/test/CodeGen/X86/combine-or.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -249,9 +249,8 @@ define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) {
249249
; CHECK-LIS-LABEL: test18:
250250
; CHECK-LIS: # %bb.0:
251251
; CHECK-LIS-NEXT: pxor %xmm2, %xmm2
252-
; CHECK-LIS-NEXT: pxor %xmm3, %xmm3
253-
; CHECK-LIS-NEXT: pblendw {{.*#+}} xmm3 = xmm0[0,1],xmm3[2,3,4,5,6,7]
254-
; CHECK-LIS-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,1,1]
252+
; CHECK-LIS-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
253+
; CHECK-LIS-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
255254
; CHECK-LIS-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7]
256255
; CHECK-LIS-NEXT: por %xmm0, %xmm2
257256
; CHECK-LIS-NEXT: movdqa %xmm2, %xmm0

‎llvm/test/CodeGen/X86/machine-cse.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
3+
; RUN: llc -mtriple=x86_64-unknown-unknown -early-live-intervals < %s | FileCheck %s
34
; rdar://7610418
45

56
%ptr = type { ptr }

‎llvm/test/CodeGen/X86/ternlog.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | llc -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s
3+
; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | llc -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl -early-live-intervals | FileCheck %s
34

45
;; This is just a simple test to make sure there are no regressions
56
;; cause by splitting/recombining ternlog intrinsics.

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